From 6457809037fd37915d175a3af61abddd4dfd56ed Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Tue, 15 Aug 2023 05:05:47 -0400 Subject: [PATCH] All compiling --- CPLD/LCMXO2-1200HC/.run_manager.ini | 9 + CPLD/LCMXO2-1200HC/.setting.ini | 4 + CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf | 17 + CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.lpf | 68 + .../RAM2GS_LCMXO2_1200HC_tcl.html | 70 + .../pn230815050136.tcr | 5 + CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_640HC1.sty | 205 + CPLD/LCMXO2-1200HC/impl1/.build_status | 62 + .../.vdbs/RAM2GS_LCMXO2_1200HC_impl1_map.vdb | Bin 0 -> 70832 bytes CPLD/LCMXO2-1200HC/impl1/.vdbs/RAM2GS_rtl.vdb | Bin 0 -> 74348 bytes .../LCMXO2-1200HC/impl1/.vdbs/RAM2GS_tech.vdb | Bin 0 -> 67455 bytes CPLD/LCMXO2-1200HC/impl1/.vdbs/dbStat.txt | 1 + .../impl1/RAM2GS_LCMXO2_1200HC_impl1.alt | 75 + .../impl1/RAM2GS_LCMXO2_1200HC_impl1.arearep | 21 + .../impl1/RAM2GS_LCMXO2_1200HC_impl1.bgn | 86 + .../RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd | Bin 0 -> 197895 bytes .../RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.pad | 309 + .../RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.par | 301 + .../5_1_par.asd | 38 + .../RAM2GS_LCMXO2_1200HC_impl1.par | 28 + .../impl1/RAM2GS_LCMXO2_1200HC_impl1.drc | 1 + .../impl1/RAM2GS_LCMXO2_1200HC_impl1.jed | 2779 ++ .../impl1/RAM2GS_LCMXO2_1200HC_impl1.log | 4 + .../impl1/RAM2GS_LCMXO2_1200HC_impl1.lpf | 4 + .../impl1/RAM2GS_LCMXO2_1200HC_impl1.lsedata | 6331 ++++ .../impl1/RAM2GS_LCMXO2_1200HC_impl1.mrp | 402 + .../impl1/RAM2GS_LCMXO2_1200HC_impl1.mt | 9 + .../impl1/RAM2GS_LCMXO2_1200HC_impl1.ncd | Bin 0 -> 197895 bytes .../impl1/RAM2GS_LCMXO2_1200HC_impl1.ngd | Bin 0 -> 156243 bytes .../impl1/RAM2GS_LCMXO2_1200HC_impl1.p2t | 9 + .../impl1/RAM2GS_LCMXO2_1200HC_impl1.p3t | 5 + .../impl1/RAM2GS_LCMXO2_1200HC_impl1.pad | 309 + .../impl1/RAM2GS_LCMXO2_1200HC_impl1.par | 329 + .../impl1/RAM2GS_LCMXO2_1200HC_impl1.prf | 80 + .../impl1/RAM2GS_LCMXO2_1200HC_impl1.pt | 10 + .../impl1/RAM2GS_LCMXO2_1200HC_impl1.t2b | 5 + .../impl1/RAM2GS_LCMXO2_1200HC_impl1.tw1 | 349 + .../impl1/RAM2GS_LCMXO2_1200HC_impl1.twr | 2163 ++ .../impl1/RAM2GS_LCMXO2_1200HC_impl1_bgn.html | 152 + .../RAM2GS_LCMXO2_1200HC_impl1_iotiming.html | 204 + ...RAM2GS_LCMXO2_1200HC_impl1_lattice.synproj | 41 + .../impl1/RAM2GS_LCMXO2_1200HC_impl1_map.asd | 15 + .../impl1/RAM2GS_LCMXO2_1200HC_impl1_map.cam | 88 + .../impl1/RAM2GS_LCMXO2_1200HC_impl1_map.hrr | 10 + .../impl1/RAM2GS_LCMXO2_1200HC_impl1_map.ncd | Bin 0 -> 140118 bytes .../RAM2GS_LCMXO2_1200HC_impl1_mapvho.sdf | 3176 ++ .../RAM2GS_LCMXO2_1200HC_impl1_mapvho.vho | 26387 ++++++++++++++++ .../RAM2GS_LCMXO2_1200HC_impl1_mapvo.sdf | 3176 ++ .../impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo | 3692 +++ .../impl1/RAM2GS_LCMXO2_1200HC_impl1_mrp.html | 425 + .../impl1/RAM2GS_LCMXO2_1200HC_impl1_pad.html | 374 + .../impl1/RAM2GS_LCMXO2_1200HC_impl1_par.html | 397 + .../RAM2GS_LCMXO2_1200HC_impl1_summary.html | 83 + .../impl1/RAM2GS_LCMXO2_1200HC_impl1_tw1.html | 430 + .../impl1/RAM2GS_LCMXO2_1200HC_impl1_twr.html | 2244 ++ CPLD/LCMXO2-1200HC/impl1/RAM2GS_drc.log | 16 + CPLD/LCMXO2-1200HC/impl1/RAM2GS_lse.twr | 297 + .../impl1/RAM2GS_lse_lsetwr.html | 362 + CPLD/LCMXO2-1200HC/impl1/RAM2GS_prim.v | 802 + CPLD/LCMXO2-1200HC/impl1/automake.log | 1111 + .../impl1/hdla_gen_hierarchy.html | 9 + CPLD/LCMXO2-1200HC/impl1/impl1.xcf | 55 + .../impl1/ram2gs_lcmxo2_1200hc_impl1.ior | 139 + .../impl1/ram2gs_lcmxo2_1200hc_impl1_trce.asd | 13 + CPLD/LCMXO2-1200HC/impl1/synthesis.log | 239 + CPLD/LCMXO2-1200HC/impl1/synthesis_lse.html | 304 + CPLD/LCMXO2-1200HC/impl1/xxx_lse_cp_file_list | 250 + CPLD/LCMXO2-1200HC/impl1/xxx_lse_sign_file | 250 + CPLD/LCMXO2-640HC/.run_manager.ini | 9 + CPLD/LCMXO2-640HC/.setting.ini | 4 + CPLD/LCMXO2-640HC/.spread_sheet.ini | 3 + CPLD/LCMXO2-640HC/.spreadsheet_view.ini | 76 + CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ccl | 1 + CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf | 17 + CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf | 68 + CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC1.sty | 205 + .../LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcl.html | 82 + .../pn230815045824.tcr | 9 + .../pn230815050055.tcr | 4 + CPLD/LCMXO2-640HC/hdlparser.log | 3 + CPLD/LCMXO2-640HC/impl1/.build_status | 48 + .../.vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb | Bin 0 -> 67964 bytes CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_rtl.vdb | Bin 0 -> 74346 bytes CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_tech.vdb | Bin 0 -> 67453 bytes CPLD/LCMXO2-640HC/impl1/.vdbs/dbStat.txt | 1 + .../impl1/RAM2GS_LCMXO2_640HC_impl1.alt | 75 + .../impl1/RAM2GS_LCMXO2_640HC_impl1.arearep | 21 + .../impl1/RAM2GS_LCMXO2_640HC_impl1.bgn | 86 + .../RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd | Bin 0 -> 194841 bytes .../RAM2GS_LCMXO2_640HC_impl1.dir/5_1.pad | 281 + .../RAM2GS_LCMXO2_640HC_impl1.dir/5_1.par | 231 + .../RAM2GS_LCMXO2_640HC_impl1.dir/5_1_par.asd | 38 + .../RAM2GS_LCMXO2_640HC_impl1.par | 28 + .../impl1/RAM2GS_LCMXO2_640HC_impl1.drc | 1 + .../impl1/RAM2GS_LCMXO2_640HC_impl1.jed | 1435 + .../impl1/RAM2GS_LCMXO2_640HC_impl1.log | 4 + .../impl1/RAM2GS_LCMXO2_640HC_impl1.lpf | 4 + .../impl1/RAM2GS_LCMXO2_640HC_impl1.lsedata | 6331 ++++ .../impl1/RAM2GS_LCMXO2_640HC_impl1.mrp | 336 + .../impl1/RAM2GS_LCMXO2_640HC_impl1.mt | 9 + .../impl1/RAM2GS_LCMXO2_640HC_impl1.ncd | Bin 0 -> 194841 bytes .../impl1/RAM2GS_LCMXO2_640HC_impl1.ngd | Bin 0 -> 156242 bytes .../impl1/RAM2GS_LCMXO2_640HC_impl1.p2t | 9 + .../impl1/RAM2GS_LCMXO2_640HC_impl1.p3t | 5 + .../impl1/RAM2GS_LCMXO2_640HC_impl1.pad | 281 + .../impl1/RAM2GS_LCMXO2_640HC_impl1.par | 259 + .../impl1/RAM2GS_LCMXO2_640HC_impl1.prf | 80 + .../impl1/RAM2GS_LCMXO2_640HC_impl1.pt | 10 + .../impl1/RAM2GS_LCMXO2_640HC_impl1.t2b | 5 + .../impl1/RAM2GS_LCMXO2_640HC_impl1.tw1 | 349 + .../impl1/RAM2GS_LCMXO2_640HC_impl1.twr | 2164 ++ .../impl1/RAM2GS_LCMXO2_640HC_impl1_bgn.html | 152 + .../RAM2GS_LCMXO2_640HC_impl1_iotiming.html | 204 + .../RAM2GS_LCMXO2_640HC_impl1_lattice.synproj | 41 + .../impl1/RAM2GS_LCMXO2_640HC_impl1_map.asd | 15 + .../impl1/RAM2GS_LCMXO2_640HC_impl1_map.cam | 88 + .../impl1/RAM2GS_LCMXO2_640HC_impl1_map.hrr | 10 + .../impl1/RAM2GS_LCMXO2_640HC_impl1_map.ncd | Bin 0 -> 137575 bytes .../RAM2GS_LCMXO2_640HC_impl1_mapvho.sdf | 3176 ++ .../RAM2GS_LCMXO2_640HC_impl1_mapvho.vho | 26387 ++++++++++++++++ .../impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.sdf | 3176 ++ .../impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.vo | 3692 +++ .../impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html | 368 + .../impl1/RAM2GS_LCMXO2_640HC_impl1_pad.html | 346 + .../impl1/RAM2GS_LCMXO2_640HC_impl1_par.html | 327 + .../RAM2GS_LCMXO2_640HC_impl1_summary.html | 83 + .../impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html | 430 + .../impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html | 2245 ++ CPLD/LCMXO2-640HC/impl1/RAM2GS_drc.log | 15 + CPLD/LCMXO2-640HC/impl1/RAM2GS_lse.twr | 297 + .../LCMXO2-640HC/impl1/RAM2GS_lse_lsetwr.html | 362 + CPLD/LCMXO2-640HC/impl1/RAM2GS_prim.v | 802 + CPLD/LCMXO2-640HC/impl1/automake.log | 1033 + .../impl1/hdla_gen_hierarchy.html | 9 + CPLD/LCMXO2-640HC/impl1/impl1.xcf | 56 + .../impl1/ram2gs_lcmxo2_640hc_impl1.ior | 139 + .../impl1/ram2gs_lcmxo2_640hc_impl1_trce.asd | 13 + CPLD/LCMXO2-640HC/impl1/synthesis.log | 237 + CPLD/LCMXO2-640HC/impl1/synthesis_lse.html | 302 + CPLD/LCMXO2-640HC/impl1/xxx_lse_cp_file_list | 250 + CPLD/LCMXO2-640HC/impl1/xxx_lse_sign_file | 250 + CPLD/LCMXO256C/.run_manager.ini | 9 + CPLD/LCMXO256C/.setting.ini | 5 + CPLD/LCMXO256C/.spread_sheet.ini | 3 + CPLD/LCMXO256C/.spreadsheet_view.ini | 65 + CPLD/LCMXO256C/RAM2GS_LCMXO256C.ccl | 1 + CPLD/LCMXO256C/RAM2GS_LCMXO256C.ldf | 17 + CPLD/LCMXO256C/RAM2GS_LCMXO256C.lpf | 137 + CPLD/LCMXO256C/RAM2GS_LCMXO256C1.sty | 205 + CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcl.html | 94 + .../pn230815043617.tcr | 9 + .../pn230815044855.tcr | 8 + .../pn230815050150.tcr | 4 + CPLD/LCMXO256C/hdlparser.log | 3 + CPLD/LCMXO256C/impl1/.build_status | 49 + .../.vdbs/RAM2GS_LCMXO256C_impl1_map.vdb | Bin 0 -> 62815 bytes CPLD/LCMXO256C/impl1/.vdbs/RAM2GS_rtl.vdb | Bin 0 -> 74340 bytes CPLD/LCMXO256C/impl1/.vdbs/RAM2GS_tech.vdb | Bin 0 -> 72003 bytes CPLD/LCMXO256C/impl1/.vdbs/dbStat.txt | 1 + .../impl1/RAM2GS_LCMXO256C_impl1.alt | 75 + .../impl1/RAM2GS_LCMXO256C_impl1.arearep | 23 + .../impl1/RAM2GS_LCMXO256C_impl1.bgn | 45 + .../impl1/RAM2GS_LCMXO256C_impl1.bit | Bin 0 -> 9225 bytes .../impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.ncd | Bin 0 -> 162296 bytes .../impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.pad | 271 + .../impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.par | 235 + .../RAM2GS_LCMXO256C_impl1.dir/5_1_par.asd | 30 + .../RAM2GS_LCMXO256C_impl1.par | 28 + .../impl1/RAM2GS_LCMXO256C_impl1.drc | 1 + .../impl1/RAM2GS_LCMXO256C_impl1.jed | 977 + .../impl1/RAM2GS_LCMXO256C_impl1.log | 4 + .../impl1/RAM2GS_LCMXO256C_impl1.lpf | 4 + .../impl1/RAM2GS_LCMXO256C_impl1.lsedata | 6331 ++++ .../impl1/RAM2GS_LCMXO256C_impl1.mrp | 336 + .../LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mt | 9 + .../impl1/RAM2GS_LCMXO256C_impl1.n2e | 596 + .../impl1/RAM2GS_LCMXO256C_impl1.ncd | Bin 0 -> 162296 bytes .../impl1/RAM2GS_LCMXO256C_impl1.ngd | Bin 0 -> 160693 bytes .../impl1/RAM2GS_LCMXO256C_impl1.p2t | 9 + .../impl1/RAM2GS_LCMXO256C_impl1.p3t | 5 + .../impl1/RAM2GS_LCMXO256C_impl1.pad | 271 + .../impl1/RAM2GS_LCMXO256C_impl1.par | 263 + .../impl1/RAM2GS_LCMXO256C_impl1.prf | 81 + .../LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pt | 10 + .../impl1/RAM2GS_LCMXO256C_impl1.t2b | 2 + .../impl1/RAM2GS_LCMXO256C_impl1.tw1 | 353 + .../impl1/RAM2GS_LCMXO256C_impl1.twr | 2170 ++ .../impl1/RAM2GS_LCMXO256C_impl1_bgn.html | 111 + .../RAM2GS_LCMXO256C_impl1_iotiming.html | 203 + .../RAM2GS_LCMXO256C_impl1_lattice.synproj | 41 + .../impl1/RAM2GS_LCMXO256C_impl1_map.asd | 13 + .../impl1/RAM2GS_LCMXO256C_impl1_map.cam | 99 + .../impl1/RAM2GS_LCMXO256C_impl1_map.hrr | 10 + .../impl1/RAM2GS_LCMXO256C_impl1_map.ncd | Bin 0 -> 107268 bytes .../impl1/RAM2GS_LCMXO256C_impl1_mapvho.sdf | 3036 ++ .../impl1/RAM2GS_LCMXO256C_impl1_mapvho.vho | 26269 +++++++++++++++ .../impl1/RAM2GS_LCMXO256C_impl1_mapvo.sdf | 3036 ++ .../impl1/RAM2GS_LCMXO256C_impl1_mapvo.vo | 3678 +++ .../impl1/RAM2GS_LCMXO256C_impl1_mrp.html | 368 + .../impl1/RAM2GS_LCMXO256C_impl1_pad.html | 336 + .../impl1/RAM2GS_LCMXO256C_impl1_par.html | 331 + .../impl1/RAM2GS_LCMXO256C_impl1_summary.html | 83 + .../impl1/RAM2GS_LCMXO256C_impl1_tw1.html | 434 + .../impl1/RAM2GS_LCMXO256C_impl1_twr.html | 2251 ++ CPLD/LCMXO256C/impl1/RAM2GS_drc.log | 15 + CPLD/LCMXO256C/impl1/RAM2GS_lse.twr | 291 + CPLD/LCMXO256C/impl1/RAM2GS_lse_lsetwr.html | 356 + CPLD/LCMXO256C/impl1/RAM2GS_prim.v | 819 + CPLD/LCMXO256C/impl1/automake.log | 1026 + CPLD/LCMXO256C/impl1/hdla_gen_hierarchy.html | 9 + CPLD/LCMXO256C/impl1/impl1.xcf | 50 + .../impl1/ram2gs_lcmxo256c_impl1.ior | 138 + .../impl1/ram2gs_lcmxo256c_impl1_trce.asd | 13 + CPLD/LCMXO256C/impl1/synthesis.log | 238 + CPLD/LCMXO256C/impl1/synthesis_lse.html | 303 + CPLD/LCMXO256C/impl1/xxx_lse_cp_file_list | 250 + CPLD/LCMXO256C/impl1/xxx_lse_sign_file | 250 + CPLD/LCMXO640C/.run_manager.ini | 9 + CPLD/LCMXO640C/.setting.ini | 4 + CPLD/LCMXO640C/RAM2GS_LCMXO256C1.sty | 205 + CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf | 17 + CPLD/LCMXO640C/RAM2GS_LCMXO640C.lpf | 137 + CPLD/LCMXO640C/impl1/.build_status | 60 + .../.vdbs/RAM2GS_LCMXO640C_impl1_map.vdb | Bin 0 -> 62815 bytes CPLD/LCMXO640C/impl1/.vdbs/RAM2GS_rtl.vdb | Bin 0 -> 74340 bytes CPLD/LCMXO640C/impl1/.vdbs/RAM2GS_tech.vdb | Bin 0 -> 72003 bytes CPLD/LCMXO640C/impl1/.vdbs/dbStat.txt | 1 + .../impl1/RAM2GS_LCMXO640C_impl1.alt | 75 + .../impl1/RAM2GS_LCMXO640C_impl1.arearep | 23 + .../impl1/RAM2GS_LCMXO640C_impl1.bgn | 45 + .../impl1/RAM2GS_LCMXO640C_impl1.bit | Bin 0 -> 20212 bytes .../impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.ncd | Bin 0 -> 163428 bytes .../impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.pad | 353 + .../impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.par | 225 + .../RAM2GS_LCMXO640C_impl1.dir/5_1_par.asd | 42 + .../RAM2GS_LCMXO640C_impl1.par | 28 + .../impl1/RAM2GS_LCMXO640C_impl1.drc | 1 + .../impl1/RAM2GS_LCMXO640C_impl1.jed | 1745 + .../impl1/RAM2GS_LCMXO640C_impl1.log | 4 + .../impl1/RAM2GS_LCMXO640C_impl1.lpf | 4 + .../impl1/RAM2GS_LCMXO640C_impl1.lsedata | 6331 ++++ .../impl1/RAM2GS_LCMXO640C_impl1.mrp | 336 + .../LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mt | 9 + .../impl1/RAM2GS_LCMXO640C_impl1.n2e | 596 + .../impl1/RAM2GS_LCMXO640C_impl1.ncd | Bin 0 -> 163428 bytes .../impl1/RAM2GS_LCMXO640C_impl1.ngd | Bin 0 -> 160693 bytes .../impl1/RAM2GS_LCMXO640C_impl1.p2t | 9 + .../impl1/RAM2GS_LCMXO640C_impl1.p3t | 5 + .../impl1/RAM2GS_LCMXO640C_impl1.pad | 353 + .../impl1/RAM2GS_LCMXO640C_impl1.par | 253 + .../impl1/RAM2GS_LCMXO640C_impl1.prf | 81 + .../LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pt | 10 + .../impl1/RAM2GS_LCMXO640C_impl1.t2b | 2 + .../impl1/RAM2GS_LCMXO640C_impl1.tw1 | 353 + .../impl1/RAM2GS_LCMXO640C_impl1.twr | 2161 ++ .../impl1/RAM2GS_LCMXO640C_impl1_bgn.html | 111 + .../RAM2GS_LCMXO640C_impl1_iotiming.html | 203 + .../RAM2GS_LCMXO640C_impl1_lattice.synproj | 41 + .../impl1/RAM2GS_LCMXO640C_impl1_map.asd | 13 + .../impl1/RAM2GS_LCMXO640C_impl1_map.cam | 99 + .../impl1/RAM2GS_LCMXO640C_impl1_map.hrr | 10 + .../impl1/RAM2GS_LCMXO640C_impl1_map.ncd | Bin 0 -> 107278 bytes .../impl1/RAM2GS_LCMXO640C_impl1_mapvho.sdf | 3036 ++ .../impl1/RAM2GS_LCMXO640C_impl1_mapvho.vho | 26269 +++++++++++++++ .../impl1/RAM2GS_LCMXO640C_impl1_mapvo.sdf | 3036 ++ .../impl1/RAM2GS_LCMXO640C_impl1_mapvo.vo | 3678 +++ .../impl1/RAM2GS_LCMXO640C_impl1_mrp.html | 368 + .../impl1/RAM2GS_LCMXO640C_impl1_pad.html | 418 + .../impl1/RAM2GS_LCMXO640C_impl1_par.html | 321 + .../impl1/RAM2GS_LCMXO640C_impl1_summary.html | 83 + .../impl1/RAM2GS_LCMXO640C_impl1_tw1.html | 434 + .../impl1/RAM2GS_LCMXO640C_impl1_twr.html | 2242 ++ CPLD/LCMXO640C/impl1/RAM2GS_drc.log | 15 + CPLD/LCMXO640C/impl1/RAM2GS_lse.twr | 291 + CPLD/LCMXO640C/impl1/RAM2GS_lse_lsetwr.html | 356 + CPLD/LCMXO640C/impl1/RAM2GS_prim.v | 819 + CPLD/LCMXO640C/impl1/automake.log | 1016 + CPLD/LCMXO640C/impl1/hdla_gen_hierarchy.html | 9 + CPLD/LCMXO640C/impl1/impl1.xcf | 50 + .../impl1/ram2gs_lcmxo640c_impl1.ior | 138 + .../impl1/ram2gs_lcmxo640c_impl1_trce.asd | 13 + CPLD/LCMXO640C/impl1/synthesis.log | 238 + CPLD/LCMXO640C/impl1/synthesis_lse.html | 303 + CPLD/LCMXO640C/impl1/xxx_lse_cp_file_list | 250 + CPLD/LCMXO640C/impl1/xxx_lse_sign_file | 250 + CPLD/MAXII/RAM2GS.qws | Bin 619 -> 619 bytes CPLD/MAXII/db/RAM2GS.(0).cnf.cdb | Bin 20872 -> 21188 bytes CPLD/MAXII/db/RAM2GS.(0).cnf.hdb | Bin 3747 -> 3743 bytes CPLD/MAXII/db/RAM2GS.asm.qmsg | 14 +- CPLD/MAXII/db/RAM2GS.asm.rdb | Bin 806 -> 807 bytes CPLD/MAXII/db/RAM2GS.asm_labs.ddb | Bin 2747 -> 2679 bytes CPLD/MAXII/db/RAM2GS.cmp.cdb | Bin 44340 -> 43889 bytes CPLD/MAXII/db/RAM2GS.cmp.hdb | Bin 18612 -> 18634 bytes CPLD/MAXII/db/RAM2GS.cmp.idb | Bin 2737 -> 2726 bytes CPLD/MAXII/db/RAM2GS.cmp.rdb | Bin 14333 -> 14361 bytes CPLD/MAXII/db/RAM2GS.cmp0.ddb | Bin 78630 -> 77067 bytes CPLD/MAXII/db/RAM2GS.db_info | 2 +- CPLD/MAXII/db/RAM2GS.fit.qmsg | 90 +- CPLD/MAXII/db/RAM2GS.hier_info | 72 +- CPLD/MAXII/db/RAM2GS.hif | Bin 596 -> 596 bytes CPLD/MAXII/db/RAM2GS.map.cdb | Bin 17971 -> 17914 bytes CPLD/MAXII/db/RAM2GS.map.hdb | Bin 17714 -> 17679 bytes CPLD/MAXII/db/RAM2GS.map.qmsg | 54 +- CPLD/MAXII/db/RAM2GS.map.rdb | Bin 1264 -> 1261 bytes CPLD/MAXII/db/RAM2GS.pre_map.hdb | Bin 16802 -> 16376 bytes CPLD/MAXII/db/RAM2GS.routing.rdb | Bin 1591 -> 1512 bytes CPLD/MAXII/db/RAM2GS.rtlv.hdb | Bin 16470 -> 16298 bytes CPLD/MAXII/db/RAM2GS.rtlv_sg.cdb | Bin 19171 -> 19172 bytes CPLD/MAXII/db/RAM2GS.rtlv_sg_swap.cdb | Bin 840 -> 840 bytes CPLD/MAXII/db/RAM2GS.sta.qmsg | 50 +- CPLD/MAXII/db/RAM2GS.sta.rdb | Bin 13037 -> 13070 bytes CPLD/MAXII/db/RAM2GS.sta_cmp.5_slow.tdb | Bin 46370 -> 46242 bytes CPLD/MAXII/db/RAM2GS.tmw_info | 8 +- CPLD/MAXII/db/RAM2GS.vpr.ammdb | Bin 647 -> 650 bytes CPLD/MAXII/db/prev_cmp_RAM2GS-MAXII.qmsg | 227 +- .../RAM2GS.root_partition.map.kpt | Bin 2669 -> 2659 bytes CPLD/MAXII/output_files/RAM2GS.asm.rpt | 14 +- CPLD/MAXII/output_files/RAM2GS.done | 2 +- CPLD/MAXII/output_files/RAM2GS.fit.rpt | 213 +- CPLD/MAXII/output_files/RAM2GS.fit.summary | 2 +- CPLD/MAXII/output_files/RAM2GS.flow.rpt | 18 +- CPLD/MAXII/output_files/RAM2GS.map.rpt | 20 +- CPLD/MAXII/output_files/RAM2GS.map.summary | 2 +- CPLD/MAXII/output_files/RAM2GS.pof | Bin 7861 -> 7861 bytes CPLD/MAXII/output_files/RAM2GS.sta.rpt | 938 +- CPLD/MAXII/output_files/RAM2GS.sta.summary | 38 +- CPLD/MAXV/RAM2GS.qws | Bin 1321 -> 0 bytes CPLD/MAXV/db/RAM2GS.(0).cnf.cdb | Bin 20872 -> 21188 bytes CPLD/MAXV/db/RAM2GS.(0).cnf.hdb | Bin 3751 -> 3726 bytes CPLD/MAXV/db/RAM2GS.ace_cmp.cdb | Bin 0 -> 44062 bytes CPLD/MAXV/db/RAM2GS.ace_cmp.hdb | Bin 0 -> 18555 bytes CPLD/MAXV/db/RAM2GS.acvq.rdb | Bin 0 -> 402 bytes CPLD/MAXV/db/RAM2GS.asm.qmsg | 14 +- CPLD/MAXV/db/RAM2GS.asm.rdb | Bin 809 -> 809 bytes CPLD/MAXV/db/RAM2GS.asm_labs.ddb | Bin 2738 -> 2742 bytes CPLD/MAXV/db/RAM2GS.cmp.cdb | Bin 43929 -> 44062 bytes CPLD/MAXV/db/RAM2GS.cmp.hdb | Bin 18442 -> 18555 bytes CPLD/MAXV/db/RAM2GS.cmp.idb | Bin 2746 -> 2719 bytes CPLD/MAXV/db/RAM2GS.cmp.rdb | Bin 14278 -> 14283 bytes CPLD/MAXV/db/RAM2GS.cmp0.ddb | Bin 79262 -> 79147 bytes CPLD/MAXV/db/RAM2GS.db_info | 2 +- CPLD/MAXV/db/RAM2GS.fit.qmsg | 90 +- CPLD/MAXV/db/RAM2GS.hier_info | 12 +- CPLD/MAXV/db/RAM2GS.hif | Bin 595 -> 595 bytes CPLD/MAXV/db/RAM2GS.map.cdb | Bin 17966 -> 17914 bytes CPLD/MAXV/db/RAM2GS.map.hdb | Bin 17606 -> 17643 bytes CPLD/MAXV/db/RAM2GS.map.qmsg | 54 +- CPLD/MAXV/db/RAM2GS.map.rdb | Bin 1260 -> 1262 bytes CPLD/MAXV/db/RAM2GS.pre_map.hdb | Bin 16315 -> 16328 bytes CPLD/MAXV/db/RAM2GS.routing.rdb | Bin 1545 -> 1525 bytes CPLD/MAXV/db/RAM2GS.rtlv.hdb | Bin 16241 -> 16245 bytes CPLD/MAXV/db/RAM2GS.rtlv_sg.cdb | Bin 19071 -> 19172 bytes CPLD/MAXV/db/RAM2GS.rtlv_sg_swap.cdb | Bin 841 -> 841 bytes CPLD/MAXV/db/RAM2GS.sta.qmsg | 50 +- CPLD/MAXV/db/RAM2GS.sta.rdb | Bin 13207 -> 13288 bytes CPLD/MAXV/db/RAM2GS.sta_cmp.4_slow.tdb | Bin 46379 -> 46425 bytes CPLD/MAXV/db/RAM2GS.tmw_info | 8 +- CPLD/MAXV/db/RAM2GS.vpr.ammdb | Bin 647 -> 650 bytes CPLD/MAXV/db/prev_cmp_RAM2GS-MAXV.qmsg | 224 +- .../RAM2GS.root_partition.map.kpt | Bin 2647 -> 2645 bytes CPLD/MAXV/output_files/RAM2GS.asm.rpt | 18 +- CPLD/MAXV/output_files/RAM2GS.done | 2 +- CPLD/MAXV/output_files/RAM2GS.fit.rpt | 220 +- CPLD/MAXV/output_files/RAM2GS.fit.summary | 2 +- CPLD/MAXV/output_files/RAM2GS.flow.rpt | 16 +- CPLD/MAXV/output_files/RAM2GS.map.rpt | 18 +- CPLD/MAXV/output_files/RAM2GS.map.summary | 2 +- CPLD/MAXV/output_files/RAM2GS.pof | Bin 7861 -> 7861 bytes CPLD/MAXV/output_files/RAM2GS.sta.rpt | 914 +- CPLD/MAXV/output_files/RAM2GS.sta.summary | 34 +- CPLD/RAM2GS-MAX.v | 4 +- CPLD/RAM2GS-SPI.v | 411 + 372 files changed, 232424 insertions(+), 1724 deletions(-) create mode 100644 CPLD/LCMXO2-1200HC/.run_manager.ini create mode 100644 CPLD/LCMXO2-1200HC/.setting.ini create mode 100644 CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf create mode 100644 CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.lpf create mode 100644 CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC_tcl.html create mode 100644 CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC_tcr.dir/pn230815050136.tcr create mode 100644 CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_640HC1.sty create mode 100644 CPLD/LCMXO2-1200HC/impl1/.build_status create mode 100644 CPLD/LCMXO2-1200HC/impl1/.vdbs/RAM2GS_LCMXO2_1200HC_impl1_map.vdb create mode 100644 CPLD/LCMXO2-1200HC/impl1/.vdbs/RAM2GS_rtl.vdb create mode 100644 CPLD/LCMXO2-1200HC/impl1/.vdbs/RAM2GS_tech.vdb create mode 100644 CPLD/LCMXO2-1200HC/impl1/.vdbs/dbStat.txt create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.alt create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.arearep create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.bgn create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.pad create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.par create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1_par.asd create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/RAM2GS_LCMXO2_1200HC_impl1.par create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.drc create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.jed create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.log create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.lpf create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.lsedata create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mrp create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mt create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.ncd create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.ngd create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.p2t create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.p3t create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pad create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.par create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.prf create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pt create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.t2b create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.tw1 create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.twr create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_bgn.html create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_iotiming.html create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_lattice.synproj create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.asd create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.cam create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.hrr create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.ncd create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvho.sdf create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvho.vho create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.sdf create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mrp.html create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_pad.html create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_par.html create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_summary.html create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_tw1.html create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_twr.html create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_drc.log create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_lse.twr create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_lse_lsetwr.html create mode 100644 CPLD/LCMXO2-1200HC/impl1/RAM2GS_prim.v create mode 100644 CPLD/LCMXO2-1200HC/impl1/automake.log create mode 100644 CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html create mode 100644 CPLD/LCMXO2-1200HC/impl1/impl1.xcf create mode 100644 CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1.ior create mode 100644 CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1_trce.asd create mode 100644 CPLD/LCMXO2-1200HC/impl1/synthesis.log create mode 100644 CPLD/LCMXO2-1200HC/impl1/synthesis_lse.html create mode 100644 CPLD/LCMXO2-1200HC/impl1/xxx_lse_cp_file_list create mode 100644 CPLD/LCMXO2-1200HC/impl1/xxx_lse_sign_file create mode 100644 CPLD/LCMXO2-640HC/.run_manager.ini create mode 100644 CPLD/LCMXO2-640HC/.setting.ini create mode 100644 CPLD/LCMXO2-640HC/.spread_sheet.ini create mode 100644 CPLD/LCMXO2-640HC/.spreadsheet_view.ini create mode 100644 CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ccl create mode 100644 CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf create mode 100644 CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf create mode 100644 CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC1.sty create mode 100644 CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcl.html create mode 100644 CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn230815045824.tcr create mode 100644 CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn230815050055.tcr create mode 100644 CPLD/LCMXO2-640HC/hdlparser.log create mode 100644 CPLD/LCMXO2-640HC/impl1/.build_status create mode 100644 CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb create mode 100644 CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_rtl.vdb create mode 100644 CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_tech.vdb create mode 100644 CPLD/LCMXO2-640HC/impl1/.vdbs/dbStat.txt create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.alt create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.arearep create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bgn create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.pad create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.par create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1_par.asd create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/RAM2GS_LCMXO2_640HC_impl1.par create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.drc create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.jed create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.log create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lpf create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lsedata create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mt create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ncd create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ngd create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.p2t create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.p3t create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.pad create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.par create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.prf create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.pt create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.t2b create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.tw1 create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.twr create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_bgn.html create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_iotiming.html create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_lattice.synproj create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.asd create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.cam create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.hrr create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.ncd create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvho.sdf create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvho.vho create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.sdf create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.vo create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_pad.html create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_par.html create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_drc.log create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_lse.twr create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_lse_lsetwr.html create mode 100644 CPLD/LCMXO2-640HC/impl1/RAM2GS_prim.v create mode 100644 CPLD/LCMXO2-640HC/impl1/automake.log create mode 100644 CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html create mode 100644 CPLD/LCMXO2-640HC/impl1/impl1.xcf create mode 100644 CPLD/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1.ior create mode 100644 CPLD/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1_trce.asd create mode 100644 CPLD/LCMXO2-640HC/impl1/synthesis.log create mode 100644 CPLD/LCMXO2-640HC/impl1/synthesis_lse.html create mode 100644 CPLD/LCMXO2-640HC/impl1/xxx_lse_cp_file_list create mode 100644 CPLD/LCMXO2-640HC/impl1/xxx_lse_sign_file create mode 100644 CPLD/LCMXO256C/.run_manager.ini create mode 100644 CPLD/LCMXO256C/.setting.ini create mode 100644 CPLD/LCMXO256C/.spread_sheet.ini create mode 100644 CPLD/LCMXO256C/.spreadsheet_view.ini create mode 100644 CPLD/LCMXO256C/RAM2GS_LCMXO256C.ccl create mode 100644 CPLD/LCMXO256C/RAM2GS_LCMXO256C.ldf create mode 100644 CPLD/LCMXO256C/RAM2GS_LCMXO256C.lpf create mode 100644 CPLD/LCMXO256C/RAM2GS_LCMXO256C1.sty create mode 100644 CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcl.html create mode 100644 CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230815043617.tcr create mode 100644 CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230815044855.tcr create mode 100644 CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230815050150.tcr create mode 100644 CPLD/LCMXO256C/hdlparser.log create mode 100644 CPLD/LCMXO256C/impl1/.build_status create mode 100644 CPLD/LCMXO256C/impl1/.vdbs/RAM2GS_LCMXO256C_impl1_map.vdb create mode 100644 CPLD/LCMXO256C/impl1/.vdbs/RAM2GS_rtl.vdb create mode 100644 CPLD/LCMXO256C/impl1/.vdbs/RAM2GS_tech.vdb create mode 100644 CPLD/LCMXO256C/impl1/.vdbs/dbStat.txt create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.alt create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.arearep create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bgn create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bit create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.ncd create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.pad create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.par create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1_par.asd create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/RAM2GS_LCMXO256C_impl1.par create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.drc create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.jed create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.log create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.lpf create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.lsedata create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mrp create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mt create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.n2e create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.ncd create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.ngd create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p2t create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p3t create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pad create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.par create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.prf create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pt create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.t2b create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.tw1 create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.twr create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_bgn.html create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_iotiming.html create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_lattice.synproj create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.asd create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.cam create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.hrr create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.ncd create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvho.sdf create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvho.vho create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.sdf create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.vo create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mrp.html create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_pad.html create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_par.html create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_summary.html create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_tw1.html create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_twr.html create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_drc.log create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_lse.twr create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_lse_lsetwr.html create mode 100644 CPLD/LCMXO256C/impl1/RAM2GS_prim.v create mode 100644 CPLD/LCMXO256C/impl1/automake.log create mode 100644 CPLD/LCMXO256C/impl1/hdla_gen_hierarchy.html create mode 100644 CPLD/LCMXO256C/impl1/impl1.xcf create mode 100644 CPLD/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1.ior create mode 100644 CPLD/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1_trce.asd create mode 100644 CPLD/LCMXO256C/impl1/synthesis.log create mode 100644 CPLD/LCMXO256C/impl1/synthesis_lse.html create mode 100644 CPLD/LCMXO256C/impl1/xxx_lse_cp_file_list create mode 100644 CPLD/LCMXO256C/impl1/xxx_lse_sign_file create mode 100644 CPLD/LCMXO640C/.run_manager.ini create mode 100644 CPLD/LCMXO640C/.setting.ini create mode 100644 CPLD/LCMXO640C/RAM2GS_LCMXO256C1.sty create mode 100644 CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf create mode 100644 CPLD/LCMXO640C/RAM2GS_LCMXO640C.lpf create mode 100644 CPLD/LCMXO640C/impl1/.build_status create mode 100644 CPLD/LCMXO640C/impl1/.vdbs/RAM2GS_LCMXO640C_impl1_map.vdb create mode 100644 CPLD/LCMXO640C/impl1/.vdbs/RAM2GS_rtl.vdb create mode 100644 CPLD/LCMXO640C/impl1/.vdbs/RAM2GS_tech.vdb create mode 100644 CPLD/LCMXO640C/impl1/.vdbs/dbStat.txt create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.alt create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.arearep create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.bgn create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.bit create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.ncd create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.pad create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.par create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1_par.asd create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/RAM2GS_LCMXO640C_impl1.par create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.drc create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.jed create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.log create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lpf create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lsedata create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mrp create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mt create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.n2e create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.ncd create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.ngd create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.p2t create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.p3t create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pad create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.par create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.prf create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pt create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.t2b create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.tw1 create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.twr create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_bgn.html create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_iotiming.html create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_lattice.synproj create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.asd create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.cam create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.hrr create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.ncd create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvho.sdf create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvho.vho create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvo.sdf create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvo.vo create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mrp.html create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_pad.html create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_par.html create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_summary.html create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_tw1.html create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_twr.html create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_drc.log create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_lse.twr create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_lse_lsetwr.html create mode 100644 CPLD/LCMXO640C/impl1/RAM2GS_prim.v create mode 100644 CPLD/LCMXO640C/impl1/automake.log create mode 100644 CPLD/LCMXO640C/impl1/hdla_gen_hierarchy.html create mode 100644 CPLD/LCMXO640C/impl1/impl1.xcf create mode 100644 CPLD/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1.ior create mode 100644 CPLD/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1_trce.asd create mode 100644 CPLD/LCMXO640C/impl1/synthesis.log create mode 100644 CPLD/LCMXO640C/impl1/synthesis_lse.html create mode 100644 CPLD/LCMXO640C/impl1/xxx_lse_cp_file_list create mode 100644 CPLD/LCMXO640C/impl1/xxx_lse_sign_file delete mode 100644 CPLD/MAXV/RAM2GS.qws create mode 100644 CPLD/MAXV/db/RAM2GS.ace_cmp.cdb create mode 100644 CPLD/MAXV/db/RAM2GS.ace_cmp.hdb create mode 100644 CPLD/MAXV/db/RAM2GS.acvq.rdb create mode 100644 CPLD/RAM2GS-SPI.v diff --git a/CPLD/LCMXO2-1200HC/.run_manager.ini b/CPLD/LCMXO2-1200HC/.run_manager.ini new file mode 100644 index 0000000..8c0aa7b --- /dev/null +++ b/CPLD/LCMXO2-1200HC/.run_manager.ini @@ -0,0 +1,9 @@ +[Runmanager] +Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0) +windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) +headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0) + +[impl1%3CStrategy1%3E] +isChecked=false +isHidden=false +isExpanded=false diff --git a/CPLD/LCMXO2-1200HC/.setting.ini b/CPLD/LCMXO2-1200HC/.setting.ini new file mode 100644 index 0000000..39eb32a --- /dev/null +++ b/CPLD/LCMXO2-1200HC/.setting.ini @@ -0,0 +1,4 @@ +[General] +PAR.auto_tasks=PARTrace, IOTiming +Map.auto_tasks=MapTrace, MapVerilogSimFile, MapVHDLSimFile +Export.auto_tasks=Jedecgen diff --git a/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf b/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf new file mode 100644 index 0000000..c6d7112 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.lpf b/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.lpf new file mode 100644 index 0000000..63de512 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.lpf @@ -0,0 +1,68 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +LOCATE COMP "CROW[0]" SITE "10" ; +LOCATE COMP "CROW[1]" SITE "16" ; +LOCATE COMP "PHI2" SITE "8" ; +LOCATE COMP "RCLK" SITE "62" ; +LOCATE COMP "nCCAS" SITE "9" ; +LOCATE COMP "nCRAS" SITE "17" ; +LOCATE COMP "Din[0]" SITE "3" ; +LOCATE COMP "Din[6]" SITE "2" ; +LOCATE COMP "Din[7]" SITE "1" ; +LOCATE COMP "Din[4]" SITE "99" ; +LOCATE COMP "Din[5]" SITE "98" ; +LOCATE COMP "Din[3]" SITE "97" ; +LOCATE COMP "Din[1]" SITE "96" ; +LOCATE COMP "Din[2]" SITE "88" ; +LOCATE COMP "MAin[0]" SITE "14" ; +LOCATE COMP "MAin[1]" SITE "12" ; +LOCATE COMP "MAin[2]" SITE "13" ; +LOCATE COMP "MAin[3]" SITE "21" ; +LOCATE COMP "MAin[4]" SITE "20" ; +LOCATE COMP "MAin[5]" SITE "19" ; +LOCATE COMP "MAin[6]" SITE "24" ; +LOCATE COMP "MAin[7]" SITE "18" ; +LOCATE COMP "MAin[8]" SITE "25" ; +LOCATE COMP "MAin[9]" SITE "32" ; +LOCATE COMP "UFMSDO" SITE "27" ; +LOCATE COMP "nFWE" SITE "28" ; +LOCATE COMP "Dout[0]" SITE "76" ; +LOCATE COMP "Dout[1]" SITE "86" ; +LOCATE COMP "Dout[2]" SITE "87" ; +LOCATE COMP "Dout[3]" SITE "85" ; +LOCATE COMP "Dout[4]" SITE "83" ; +LOCATE COMP "Dout[5]" SITE "84" ; +LOCATE COMP "Dout[6]" SITE "78" ; +LOCATE COMP "Dout[7]" SITE "82" ; +LOCATE COMP "LED" SITE "34" ; +LOCATE COMP "RA[0]" SITE "66" ; +LOCATE COMP "RA[1]" SITE "67" ; +LOCATE COMP "RA[2]" SITE "69" ; +LOCATE COMP "RA[3]" SITE "71" ; +LOCATE COMP "RA[4]" SITE "74" ; +LOCATE COMP "RA[5]" SITE "70" ; +LOCATE COMP "RA[6]" SITE "68" ; +LOCATE COMP "RA[7]" SITE "75" ; +LOCATE COMP "RA[8]" SITE "65" ; +LOCATE COMP "RA[9]" SITE "63" ; +LOCATE COMP "RA[10]" SITE "64" ; +LOCATE COMP "RA[11]" SITE "59" ; +LOCATE COMP "RBA[0]" SITE "58" ; +LOCATE COMP "RBA[1]" SITE "60" ; +LOCATE COMP "RCKE" SITE "53" ; +LOCATE COMP "RDQMH" SITE "51" ; +LOCATE COMP "RDQML" SITE "48" ; +LOCATE COMP "UFMCLK" SITE "29" ; +LOCATE COMP "UFMSDI" SITE "30" ; +LOCATE COMP "nRCAS" SITE "52" ; +LOCATE COMP "nRCS" SITE "57" ; +LOCATE COMP "nRRAS" SITE "54" ; +LOCATE COMP "nRWE" SITE "49" ; +LOCATE COMP "RD[0]" SITE "36" ; +LOCATE COMP "RD[1]" SITE "37" ; +LOCATE COMP "RD[2]" SITE "38" ; +LOCATE COMP "RD[3]" SITE "39" ; +LOCATE COMP "RD[4]" SITE "40" ; +LOCATE COMP "RD[5]" SITE "41" ; +LOCATE COMP "RD[6]" SITE "42" ; +LOCATE COMP "RD[7]" SITE "43" ; diff --git a/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC_tcl.html b/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC_tcl.html new file mode 100644 index 0000000..b85aee7 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC_tcl.html @@ -0,0 +1,70 @@ + +Lattice TCL Log + + +
pn230815050136
+#Start recording tcl command: 8/15/2023 05:01:06
+#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC; Project name: RAM2GS_LCMXO2_1200HC
+prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf"
+prj_run Export -impl impl1 -forceAll
+#Stop recording: 8/15/2023 05:01:36
+
+
+
+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+
+ + diff --git a/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC_tcr.dir/pn230815050136.tcr b/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC_tcr.dir/pn230815050136.tcr new file mode 100644 index 0000000..857aaf4 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC_tcr.dir/pn230815050136.tcr @@ -0,0 +1,5 @@ +#Start recording tcl command: 8/15/2023 05:01:06 +#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC; Project name: RAM2GS_LCMXO2_1200HC +prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf" +prj_run Export -impl impl1 -forceAll +#Stop recording: 8/15/2023 05:01:36 diff --git a/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_640HC1.sty b/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_640HC1.sty new file mode 100644 index 0000000..7292d5f --- /dev/null +++ b/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_640HC1.sty @@ -0,0 +1,205 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO2-1200HC/impl1/.build_status b/CPLD/LCMXO2-1200HC/impl1/.build_status new file mode 100644 index 0000000..94e5b25 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/.build_status @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO2-1200HC/impl1/.vdbs/RAM2GS_LCMXO2_1200HC_impl1_map.vdb b/CPLD/LCMXO2-1200HC/impl1/.vdbs/RAM2GS_LCMXO2_1200HC_impl1_map.vdb new file mode 100644 index 0000000000000000000000000000000000000000..f28b48bf9a2e079ad9c17d968c531e2c78bb6968 GIT binary patch literal 70832 zcmeIbd3a>kl^^y1R22&7t}38`W}{ndbS+@33W#S2G1*v{nl zyX(2P3jAh(YCC_V{-}G;x#!(;@44rmbMAfb-FNk?SEjN_^6dn_#^3qTD^sao_w-+T zX=37$E3>K3z4*dQ#3zmUWRPTz-fF+Sd1w+~=UVdjjeZljiJAK4#Vd35N9XIj5Qrqi zOyqao-n`eiyR&=n_T9TX+o^-C`9;aivom z>lcr!b24G6s%9dYI)7oF*@@J%U;KfW(?9mg8?U{B2I$|!*~a$PTL*U!wj|>rWXybe ze(~bv3zrvyL)fTP)%;_TI^dp_YQ3S=-|H1 zPaZum*vXx3lS5B0*zCxjPI?CSEh}{aM3QZ6A05b^2Z*@WQ}gSWkL&SNl78ac!nJkN zlh+UCYt699_%OO%)dx%q3F=mz`|B?dq|)sdFE{WGUx-c4^}&i#E2f`&R2qQnfbP>w(ZAfp3>*~Wvz%?FXk2vBjw>1!Kv*N*iVh%ml&cUx6pM#m0E zwsG{G-B9lZBIYu+{`kUiDsVQLg0xNbDX>!>F?0i|EmUqu&J-^!twTo^=9cVLX9`28 z)b8ev7CJ^5ahAV+=ECJGxO`(ld#=eO)7m?<#R_`YLo*AD7v?@TcWurRXCLgqZ6CgO zTeZf|inEOeM>`Mh?QBb#3?XB=OkZ1Hy0*MDf1GU2B-vK;-WIDiy`NrLUgSj%2o^)I5P+&Rn4~lHxs7v6p;}8!-2c?(;q9H{I^XyztIg~+TAK|U zaAfuas1rbg0O|!$KY+Rc)DEC#0JQ>Wuh9(JBB4%DHVB|z0QCc?8$j&;gKo}1JVLSwc@emNkLqHf00bx7@ zgz@kYWl#)dAVJ7Lf{=j(Ap;3Q1`>n}BnTM@5He``RzN2u1U(RC&;tQM4+I1~5D@f0 zK+ppLK@S83J@C*pM(3$>UJnW(h<1mi5=-I(7Z8+QKu~%CLFokqr56yCUO-TK z4=JVhO`{Bo0;JLlkV-E=D!l-y^a7;P3y@0hK`Om(1(jYvP-I(7Z8+QKu~%C zLFokqr56yC-b0K^8n=(!h`5y-<|KlL# ze;lOzkAsx|agg#q4pRQdLCXI)2t%;haFFsp4pRQdLCXI)NckTJDgWaj<$oNc{Evf_ z|FMwqKj%XK<3R0y9H{+|1GWEgp!Pow)c(hT+W%Nk`ybm1j>oQ)frOO*ag@scI7s;) z2PyyKAmx7?r2LPAl>f1i@jtd{YAP<&9jN_}1GWEgp!Pow)c(hT+W$CE`yUHx|6^Oh zsTjyWLdyR*O67kXr2LPAl>c#%@;?qz{>MSe|5(WQAKSEP?SC8y69WI^z(N2j|D(!A z_@7aD`X5`D@;??3{>P!b|FJ0gAKh;4e{5d)A5CQZj|GhXaUg@P$4wL9j`5y~e|6^hAf2!+GM9X@K8S+29qn|oDcK!3i+=QR0mbmQTG7Ia7%dr5I6;5yco$h!HF0h|5}xsKtoY7*UN8l^9Wq5#<GE> z1b3Q;yStmdeS-+@MQ}fYyAj-u;ARB3LU?)wdoXiOucy~Suoi-=Ay^H;N(h!hupENL z5G({BmMzq;jr!uox`}PzT!v8PVN_`tRT)NAhf%A;sM;`UZ5XvOggV=5HaNu~erW z5F}>`!>E<=5Y^f+sy2*T9Y$4$QI%m-X&6-=Miqxqg<;f6ak%xvD8#t2BoODuD8zX& z3b9^<$~U{p95oK#6|&B^Mq>BcqiFX>Vml+TgOS+YNNj&3wmTBr9*J#^#I{Ca_q553 zw>v7n7E=e?ssV* zTxauEs~xlvB^$blVF~NfUOvRnnEhYJlnC5KU34bbAh19(9cLR|z>wa6NNn_wK0iO_ zfaxbTt}S_oWf{5h^l}|r(WcHRY!R5OjY&+4aI0CboUF)zFfoazFfoZon3%*POibbt zCMNL+6O(v^iAg-d#3UYJViJ!qF^NZ*n8YJYOyUtHCh-UplX!%QNj$>DBpzX65|1!3 ziAR{2#3M{h;t?h$@dy)>c!Y^bJi^2z4q;*vqs)_L<#gy_9g}!i$0Q!sF^PwDOyXf3 zlXzIiBp%i=iHCJe;$XWbH!A2f>nV>gYjTe;YjTe;YjTe;YjTe;YjTe;YjTe;YjTe; zYjTe;YjTe;YjTe;YjTe;YjTe;YjTe;YjTe;YjTg!nkD36*5sbTtjRsXtjRsXtjRsX ztjRsXtjRsXtjRsXtjQh1tjSHZYc=a#59>9#hxMA=!+K5bVZA2zuwIjUSg*-Ftk>io z)@yPP>ovBA^%~p5dX4R2y~g&iUSm60ud!YC^%~oQYK`qdwZ`_KT4Q@qt+73**4Q3Y zYitjyHMR%U8ry*`EW|q1#_^Mh3kyT64GTl84GTl84GTl84GTl84GTl84GTl84GTl8 z4GTl84GTl84GTl84GTl84GTl84GTl84GTl84GTl84GTl84GTl84GTl84GTl84GROT z4GXc8Vpm<0i46-wqzMZ{qzMZ{qzMZ{qzMZ{qzMZ{qzMZ{qzMZ{qzMZHjhiM^E(xb_HKcLc6K0@oXX8;rnpM&R~G;P!@bIqa)neDd59?o`=W3?qZR z_hBUV=ZBHl!yiUs?Kh0X8gUqjwd61oYtCWh+9)K}u)~yC>kcEaCLTs&?L3Uc8hZ$t zy}h;Fz-{JlnvqtqvfUGe$5)%sZj%ttjY0eEo*N)6cs(@RYH+7jVwyvk_7J8!gy|1q zdPA5&jA1bCLMt6iJCISg1N1_~S?OuD5OE+EA|AlX!vSacyy$lhw;G2#NADSNWj6hW z45Xz(cwq>p=a#MsFpKS*R-?Up-&{?&+vqrWX8l@ytzIoI=(hqUlUWeJ^fkMV#4p-{ zNej&|Yq=2Z7HuKgE!qM!_Jq-ZD+{8<*b^Q?m4{KFxo~aSEwU2aGvw;eTSV1i^?2*Y z78kf26Yq?isfW1u?osAvw|4m;#4(SBrjyhbipe2ds)^?<(;o*5yGp?tKNyXvzw zpI!6W6_-uHRqYyfDL6Bihr4rmI7F9+%XE1-RhNhExjY=R%fofMJe<4B!~MHF0tA;w z2;uSwGF%>Eh|42Tae0I?E{|Zx%iJ2%X7J-m!1DOyN;FTVAL?ZnH(7E&FWAXDdEi_1RUQ zt@-Sl&#t&E=h=4*JI*tg$2@a+%rlqAJac)>GndCab9u}&m&ZJFdCW7H$2@a+%rlqA zJac)>GndCab9u}&m&ZJFdCW7H$2@a+%rlqAJac)>GndCab9u}&m&ZJFdCW7HZ#A~x za&i;-w#auyzAy4UkspYBN96ZKe$VHr;`0{`<1|7+2Pm9+visuPwMV3PnyE`nZ241f zZ9e#e$C>^DT+QW$YmcbP@gyl;o^rs{`T1)GKehg-%PuasEQn1@Q|+DYKWOt!pHK5` z4P84N?h>!YA0|cQX6o^IGt`dWh#ks<*zmskSCEf> z&eSndc>5w`9O8x;LoM+B#&L|#CNqU=tn=LByx}%ej1lD+QHl|j7*UN8g>x~N7*UQ9 zr5I6(5!DD`M+i|NUhD|pRQ8BiL{oTZ_c-}9zMplb_BXd&@X`_afynnnzAy4!k#CE9 zQ{-DdpT@T0g7x<>h62ELqAN-5ZSHQG5kvEQz9aGjk?)CoU*x+Y-xm3%$hSm(fAc_# z0uM2EM1COhJ(2H=d{^Y#BHtAGmd{VkE!h`Sk+u4n+T7Vbusz4?W`{06a=DReZyu>t z2;!MkQ{-DdKY2%s5^w3c=w))p<7}9dYTXufiF{k+Z;x)qZPC)(z6Vq1T*r{L-322r z<)+BDMZPQYeUa~p{6OS8BEK*4t=nFEnj+s8`L4+KMZPEU1Cj5D{JzNV`8>S-Ij7E0 zbODqF08#k4*A)4-$ah7)FY-N+ABcQMG@T*|x zU;5l7EV7Nh&hSmbrS-Xw*s}&^_#UA|WDmFShW_R^tsj`VvIHY4u9&{Kw6QRE`GTo2 zc*Fn9{PGj)OXugFLhDSqSb1mOez0@oUs2o+pj`<~U%8AnFE5!orq=^7+devgzTeX` z1Wy@uLpXy%h|XM`!5k0}ri6#mOQNOO&K4dc^M%<#1otAiAHm%SZbxu4f?E;X=Z=}+ z-;LmQ1gmEY1$`?l$K7#P8*clw4n*$&HzT+m!QBY%M{qBK2NB!}VGhb2Gx&&5&(B}R zE|EP81Ci%}eqS3w$@byVH}6|>pS^wO!9BaDgT17T9&0tWfV3tUD6Q1Q0!oDppb|C5 z-rkO0;T4FXIrixMv9Iu^a7co&xyr`-{1hgX;)hpfuy#fLQ6uy#vfOJG!NL$SZj5?w z76H?-LBr?BX40KgAx^evYo{`iOm+T_ZPUNWuFLgZuIF+C zm+QD(%eqBz8b{mVx-Qpuxt_}nT&`ntQw8tIiauNR*^e4FgLT;Jt-E;n$wj?4KYJp92OZM(@a*>$JG zI5_Vg9QvgI+S85Tb_6#gxD~>ggPnJ+)S<$cu~%$mP7rG?52m&cwjU_Hf|4Obcl)%d z?JZLPYrzA4JVXYR81h+zXW_f9G{qm!>fe`z_*3p4%(3XU8!r}7L<@Lqjf`g;2-~tJ&9)D~5 z$oCMU_X5F4EP5~$WcC0L8??9E_N>0ydpif4yGH_(jo~d>K9TSW95fVM5y4vm9>Kmj z#9m+&dkK@hgB^Q^p>V-Y!enpZh`l;E&;}onlZ;K|7Cd$?LeD7>L!NVC>DWV{W|Q!& zLJalNg>!SuOSs0GTy;bg>NoHV9xIvOxFiTLCw_Xz5JdgKNshY*58m4}(+mfKaSqyR zVeKzstABaXBc_*@aq5|2j&<+hp{*HfV)MgML>I5jpOZ0Gh>0bTdh7o7?c?GrO#a2? zrHghOCw zG2`@w3v=rq5}s$aRE>tMl_?_Er3D14QmQd7=ETFd5WF5I*)SLkPwJAPp>0C0&RsR= zM{vs2Fg9*RcKhB>9YG0?J#7ldb1t%4G71&c$MD!cq-rV}p=$H>_4%cX3yT});&zQL ziQ9JeXnW_a-K|6JTOZrLpZ6XMDpSJp>XEl6xE|e>Dl!5cw`|6o;<|qBxba((XA@$Y z{6f!hZ9zR$b9rw-qR3uQ9 zz^Vjl0vHaQShH{TLJWVWM=37d+80jEx0p&Csz= zH9YbkSdM)m)1Jr=M7|^P|Iy{XK7VP6%T5_euo)6!b z&BF9S*t>zZzPx6`PQ~= zXKLqNhflB1ZEU=0hycuc;3JPd?uYn-05aH>y7Qi`nK!Zlnkq6|yGI^MwYS`Z6Vs5# zo44ld=^N8G)IYCafZ74n44{^PH~{l{G_cUb&^Q2Nc1KGbVFe_v#}aLVWwG*}NE+%| z9Kff}|7V{v`95E4*s>G-=^Lfu)s^e3`0wX$eWQ7{`4i=z{8}sb>TBP4C1>(q@BWwV zTR)L&w%>gHC%dn_@oMh%{;k%lufO?5?&_f#8%TlT>zIZb}T`hp6(AC-fn~g@R zIcOZ+!RyCkgd3A zG~XRBr&7eJ=Q!occnfTNB5n5rk#2N-ljuL5Ah%~2dk}>CvXJBw|RIgW8ehx81aph#5DzD9^HR>}JOvF+P4mMXB>x|^P zbACq7w!BQsctdfFYTA>0^372)T@^CT?~m7StVMpK;QdB^Z@jElLRPbTUZw@S)Hyzx zw)Uk=3wY~kgomnmp{DZ9@%FSB_Vi563pH25ORMASYIiT_D&CrcKrURI@u zRaLNR^Tp-yiM5Q=7=&00I2vMDS@BsM{c$`-=b0RiQuMP$ZBoF4)Ji3~khQh)34I7( zy!OVuP%EGvueaN`e)8+x^@X|I8eTjXQ?ydPTD!hdD4mem{y;Lzzx?GdK%MyCZFFzu zig>eqe7u^SfLFiqy@(<;$L38PM`rOBuKFk(1w5HskzR9b0^SR}XJJ(exHxYbf=TNd zlHu7UUJzr76?iCsALncvVfKqho7+4RW$e6o=z!-nQ$k!)W?Yir<17De7JcG_Zu6b} z_nXakzVeNmU;NS=U;1?W^Uu8a?dQJm#m|1*{o8S_}sJ4zwqsMo-3^2BvG{8+NN~1QYhat0>%5%PN0)HO=yEJ?(dCb>gdkc@GDov z$iDvC*T44W(yKpd#}%(?i)O4ye>Xk_3;f<(vxx=MvoF7V^Yfqj^3ijj-!=k4V_i!! z`4-P}a0Ah3Kq4PByYFb4ghoRkltzJ_9<$Cc}ZZ()>pC;qZ z`@L@W>rjUGo9z=a&kurGcAiWtb;K7q$YAN>(xYo{VoY*t4@Lg_f&B9=$p7BXTRU&> zKkuavE9<16%4tDG>R2cjY00aF6Yg8(^^jV1%K0o)?`4W zjdZX14sOVF2kny?>HK~W6)nmLjQMt>eKWTfu0WwNYuBM@CsWb9W>;8+?-Q<2 z1-e}oeB$dXH*=M6E2>z%S}tE-Iq5D?KiG;YXcJJW!u8>`eyheff5i(p-_lXPokz<3 zclz%Pnvin;Wb!Q(^!mh3r1Jo+`>%NSkKum^6No20d1o}+#00vx!~21`YQRs08-w@z z`|YoP&_-vwC!Iz-Hp(-c(K26g>WpYaNV}_JZzJueZ`6uc%f;)}6IzQxNiPqqpwH-7 zr&7RusvI^whQ(W{C{J5Fv3=qpU%t259+or|?pf)|#$@&bmpAtdTddZf3&Bq2 zs-yh*sjYD@^yd()4l7I(Fx~vv=Bjck+t8+P+K{3bOzGJHLP~uPI#-mo`4b<&9Sq*@ z?w@SR=9__OR*Hljauvzv=^IeiQt|rg+6jF?f0$9FUZ|}U?Q#tr_Cn1!^#amN zm{ax=d!B(YHuGg=4cj}|0hBs?+PkcXAp`y8ipbl*%B@^M?xu`QTUx=c%4`SPqMuQ) z5opf~cQRKTHEB-0jnoV#&6zb!8ZNswE`Qw4+@KNVQH?nDv}s3;P?5M={h3DWiAH2{ z_|D0&u{^c;*i#y1!Ag4B8Tq;OFK zxF|jwly3#gpT@WXfC8QpVK=M{&Qb8)#y*@wi?Ro6)A_dSJnjQXdo#Y~R71mK;(9iP zH(2kf2IcU1o`)cLto4QDXKG5{@x+zse_!@LhXZUMLKAoZs2Kb`#wU0H?5w(BmIV3ao5nvVBG$20l8AO^Ii|Fp)Yure|hESDGy;%MlHAZr{rDP*0;dZF=! zXOF({!uCrq96q0`1uNFb$o2M4Xyo#pVAVRSSE_^kj@`${!<^p2C8VvgH zwEFLN`zO`0)o|C~5iHWb`0R^n+W?=cg>`A;j?G~XQH_|_~ zmezodMX_=!0=Cw3b{`A8u3X@?I)0cDD+FD&Ti2&uUBP6D-p=;Wd;Pp`t`x-QCRo^O z_0?`cuYb~;6Wt&{Hw%z8EX&RE=Pd43D&_umt9vuSZxVMAMDGq&cymZcF?Qo`EDDE*1mtLE?JlS3 zc~|s2F}S|KrE~bGqKgAHV7`r8xz z&E)q(ccSdeDR-Ryjqv+?#3Vxa8EyrZO!Vq#<;2<7`Ib=dc~;J;Nh@ajo7UjcJ073pL$2796Dun zW4BbtHmALbz-YwiF``5lBG|c%`yCF4M`(hmMcMa#>;~h;LcjU`K7zIr1&6qWAWe+2 z@8x=_%pklb_tD0p-T6+qnWo+ucy#?zeSI-k2)0$mF?I8;a8E@&wy(JvsqYC1_Z|X2+=7?R@{D>8H0U#)s&ra4neUHR6|KzW5{J!0C!+ms^qgb6TUF$5KfI*!iw|^iJLVEXzHDQ}b#E zTLUV*>o*2Au&lD{QzEm?rIiPJ5$w zHL_3mHn_DRv_%HeLm*b*4ex~U%oH8ZQVQoU7P z{K%EFDj=}Y>sWZ~8uKn1c9(`C4WxpN!2 z%BUUd({jUoM>)h?k11x=z|9#SbJ|VfJf?`$C%ppJ|L#d>Jf-7goXYP9uPay?<84(w z=Y+@PPj(v^k5&aT&fp!w-NSeBeBdb8dTMSf5jVWZ2W~cM4f@*}>D*7<0z8r-bt;1w z{Mg^-!{LVKI|6RlH1_>P81Ke6i-`51NE|y_K?|^th!*7ZD$~$gDn=@Rk+LVdYr`#D5=Wo`PNfBtyn0BYd`fst$loL4Nl@# zzWs3K4i;6x+(FDpTY*5cKVap5kLI{poLQSDjS{dkG=V|bGg;XWK^%N;OV^T$$VUX5SR@0 zYy=<0zE#JvSv?t1U#atuklddB84s#EA*XUHGG=uy{d`NKs;Y;-}A!r#U-g_W8;jap5UxPb#B5*ZL8JXszHbXcN3#c;Zq(UvKDO$v_Z|-OYRJ4$3kJguMJJTQLs%b|qV+M4 zt}yH4{zG6_iP-S~3C+&TL%cBL<{>tg9zqjVq9z~^Gfl{087G#CW7#6cJzO#K)cF9q zzqz%sn%4cmv@Ypz2yf1JaJ~g^k2m%j&)?j9J6DyK_30a{m8*EgX6>W~9nbNI-kHt) zRRr5sf%n94!mN(9%X_1`j6+`HF4uyMe`7sP{ZJ>Srsz6OB&yUG7x)nZ_k!aL9}E$P z2DO4{%-Z(THl#ot+upLr8+N%u6n~%2f4748+b9_}$!#lldBD3OHN47a?WMQ1+k*$R0 zqjEZZ!t;+}4jFxdJ&w3)*D%B7hZx+wha&EkNZh#Rz$h`_dMIHxUMC0!7q=W#*j*ay z;C4q1F7{g@G3Ux-9b7!zJ3P2pOGRAG;PS;CF}Tf#BJN@&ZYHG^A`gPX$6QD7*?70=@x(_k{e zF01E;_8$(rwTK-Iv)_oB;eB$a&*<`aS5dWS6@_O$?9xSTyOren_0;!V@En*JY;zm2 zXYRJl@M&1l)80b}*{e~=&copBO}vM|ZZ%@Zvx?**#UFn=nZpe}IjvTUS1ZNqh1C;o zkn9J~WWE_3m2&FwFNUY26jsQ;IKwJ(=%DEm$e?2#MMW4+JQb!WPVS8qYoRMLgyH!mghD@(64^Ts2%&QUe-Vk$tyf+Nbc$u$8%yCLkBzAw8IIPZinb#ub-67`w=yI5x@iJeF zn74C5O`R*fbl1A zI>I}9@3&8QJVK!u@|~u2!HGC}ev9MgVci10Pv0n)dH1DOIazQ~D2I$^v|+__9G0~^ z+a6|ZysS$RYi&~nYj==7j9SEct$1~{c)fhWEy_YAVvX325})(Ewx{;Pq>Yz#HDZlG zS+e$@2!K5sFXz>eb9PVZ_U56DAnoS}V9UnKxE3+qj~LreAHa@{m+@M}SUXPNWBZu} z*s$?3UWpiMr|B8nPddPU>7zoN{W_&$BRZ1yE2|x*XKX(o0sA#x#>I%Sc9x#8{Zs`E z*mxP2BgWcMddBv%7%*SsWn79FYbWU$+fQ)7c#W5FC1R`{q-ShD_W{#2UdGjkv38D@ zvHP?L3|GV#=lAe1l#}`>JTV$5HN!9-7@!T8`-}ot;h<)plE z{GpV$;;q>k-u`PrFkmBjS5L~jI)b-mr+K??6TyT9oa;C62=ChU6Q1UTvjKuWXDM%< z(WSY{uOPvO1&p7*fq(#;ht(6FwTa`Y1J<)T=;K{~%iMo+35IOE%-163I`EUs{TH5K z%*M-nC1S3FKgryGPl~UP%g2dME%t&wOT@lgI;#Uf$=rXv3MOs5%!?6o9Ry0|{##kF zYU5>Ij+pB}P%`&l=7M1xFY{8wTnB@ax&ICrEZcaQS0d&*Ae7AgSI1!5#>>1KG1oz% zWbVIl2J1Fn=Bp8N9T-aH{)=j`a3h(Y^fX}{85deO-Sc-34!5m^^WSfSg&QyPwTQXy zxo0lE76$_t@kUq-)4qDrZQ+%W_l&+L^yV#dOGtd04(3gNc*})rr(|8wUj?(~ZARY? z60F^K@L=4=%eok`)^~ygYxmJTn6~k{Y5o>+_N3eFE6NFhC zFY8LgTHpE+tlhT@VbsRUx*D<8TV;Z^`%ofG+IU&7My&Pbq+{*B$_RTFa6auf8fp<^ zy#~W4Ahk8~Ux0)y3mBjJr1G_qobkO$&Dni!5{4{btoFY5-yfXtu%E(8$X7+j{IsQE zYrkv>BNjX_Vc0fLeEf3wxP)R$UYf1=h$c)}#25=d^mlN=gb-slNr9?v9673nOnSzoXHA+jY2KuBCT08Bj&mkmFzKR6A2I0#lP;O`qDe2A z^dlyH)TEb9x@^)bCM}xuF_TtJS~KaINx#dalq1{sag*LK>8Ft<8GU*(a{Q(EWoY)N zh?M=K{K=Ov>q}<&c9T9X5)gk=*YHQ4C8X@*GE(+2N%Na7`t!f2ja5^GB%=r`NG&T~ zRs_t;csWJ$-AE~l$BJSu!eNa)!^ogmtCaKxz!@qI4)`UQ|TNizo%98EN%t4M6-YP^g>` z6b3KjXci1i#Uh^7Fr|>0Qn*Z6E#<&b<#j72y=v0`1S#82VYA$(*8%f7+cyfGa$-ul zPa;ju@cGBEkCW73Hs+%yP104|47c)9;$)l1Q^^UZ(s2^FZ%7-FQwb;@O~c1RLK?DR z8QCbBj6T^8Ab(R7H5HL>(VqRv^LYB|vpBK$aQk^6`BROi#;`V~Ns5R6u?W8@ z%AZ)y2BvH~XIqly2O#aFoFq$57LKkep5Yw9*}Uef%Vv7hB$5wP)<}(2{I-$urwq0& zWvVB?RdZ!mh^DsC4i}Mfa+B}J6uJ5?B_RG(>q$mwvbbo{WR^EZ@2T%H0L7n@12v27 zV@g-yzPSz5OF;cb;AsL=CQX}k+N4>N&X|<-kp4VUHkl$K{EJOmH|Zx#`m{+KCVd8J zlKO1JjfavCYyA=meg#X@c=>$&5;FXyI9&8&944mh_;-Vh@TU|x9<+4i84erCs3A;? zNUws7=_*p19?lZNtR_jXVXxaM^k;yfw_Hcc%aim&O@O2QdLJl`m4l@})fs_V>DH~=} z4m)8EJ1hP)(j;A|FKj%841bC*$vM8CQ^h4=a+Q*D(okw<@*w2nmH1^i`oyv=i~`se zYxJ3tCyhVxYPQVslg2PE_Jj6j8gK@agPO^h2BJJo9>lY*C6m(FkS7fn8~y`GlUaV- zH}LSP^}L34Gfi+zz50;Z>yRy8Ke6T{&GBCc!FM601!GFX%9Ix}rIqI#=MZN<@tpmn*;q5){))@bYA;;tc`CPb9^!3roI`T0-PiTR7vs$^{I6bL{dNR9-~N!G4TLq@0~h zDKW;`OczZ#MN$Mz1*0e^8j64^uV*+xJp0J&*hi*xvFszmhN4LkR^jmfW&K?b;P_Mi znbVNOtc;q+;ZCyp0INZueWWNF%A~-vgO~l+|A6OD%`7@0%86;RP_$}Vz+f%cd7us{ z@l$aKZ6Z}v5zn}<2`U0Kk#b`Z`$h9wL`rj-WSgNOKJyZgKY|iUgzk`?;+2#XudE`q zhMCigbgYRf4KiD0(~ko#0&XBpvTb!Dg%<{gyI`(l%}E;f#KLHlXbvq?Hl2)?EEu>y|gHKY_TQ;w@m)p(^V*mkn*P@?51 zEAdQODN|O;l$8}tN?27&Z-_k>fc&W_;Kx8mrmUB#l^#>}jrCI*SwBLuO8&jAQyi&)&8s9wt$e$85Z56dxImPK$LIO@^7SJpHAZtnEjTRqr zFbJf=vG^v7Q~iDC0F~s};vY1nOh04b?=|UXP5P`!pEK$AnN$TbkQ^Vq#^wA?zJxz= zBiGL(O;oGRa}p$AtLgJe@Ffx`(TBdCj+W)Wf#vB{+@BAmLW@tSFilbj@D7pkrz$6w z7yn9@p5@ob@0pKzkpw>_S$YZ9!8FO}kA1NaKUE9y)D9IZO;uN11E_Lbdt5as8*pSp zHRS_X%8|7T8Eyt7D$?bR5ajt&g8EUE&`U5TN>n6@$30n!pK1jQ*q2|f2r9u;S0?)R zp@7PtLP{l^LCUF5gUU9XH+X7U5inD7WJ)?4!g8v!yGm)NO93M_8-BmJz-m7$<^_+L z^rJ{QD{RF~tAOb>nX0&D!NrBc-iyYS7kw8}_9B_7#FmAkDWQmb)woTYZ?gjCPq{a` zc@nS=N`#VtODUF|g-US2DEbC@R6woWet=Q zh0l}$I@6j-8HEsL=)#nom@*n+syNK@*t8&!SBn7Bu(g~<)F4_I3d#X#gu(}3Re|PnxysxHO&&KST|ErF+?M*W=gsmhmqW=Wf)0vn1i^OXci}^C7D|D zfh1Lmg&Zw)?NrSdQVEE>Y74Oj_Bx_QI*kf>EmPs!T|l7pjfK=Rrkqh6?c^+T;4LqQlSsBp7p{cEN#s>qIK4VNGk*`NW(#O7*&&p$yweQzGuFR2$(-5RmzFYWD0X5hlwh<3N#~s7Bl5&Czy~h z(wLFR^QT%&3Qowck|MJgY(!CStUhp$Ai?_w!B$xMB_MwoC3F#_WW!0xL9(eb#;Ca| zVj#AW<>dTdAWf!g!A!`q;@@p5;!G$4=1gEp;gTUW{xPIaASFYl#H$%FT^z3P6%Z6b zU@Nqv#S4kI71)$59OY8Z7< zCQOq|H|QIsdL4L5^%<694=9kT>f3Ke38hHNB2sDw`=+iyjd9zlr4SKz)a}_7)KV7s`W{#)7}qa8B&oQ)1-h8 zGmp4?s@RZ#-Lfg!QgCIHvU&=e`>gPba`%Upowk6*(?~gFI>O>Z2=~l)N`d50S?@(q zu~kfImi_b7q@d2Rgi`z=Qe@h}xUrn0L8<6*Ylq{e%<}Ir6r2sDRiG*2=jy!78?^1Y{j46A@#SLx*#ETdeN-+o^4IMpG6%=GzLjtwt z=|$FsoeK9}1wbXC8z`WzeAy7V*B>l_^|UXOAYGD;riiR9x4KKe%6n3ud;Xc*$nmFi zlGRXDls9g%#Lm|ZEvk#@ zG7jYo=FX>4Okt|xsj{0H>RK*siYQdGE{!+1-E9@MTAn~LTfmf~PBOx3qGb9*+R;Ec zTgv{^ZbX}m3WW$uLgd36Mtc_$Pld^{-XR63yFC}-{%V!Mz zimI-LC-wqCQKgF@GsSqU&J}ZpP)XT0Rg4Hi*3QR>wU;-ixkvk8X#<@`t_5#_c#eGrDjuWfLVVsCHBYJX_`1T zOBZ?*uGE(j;qd4}@8eaWZLTUz<4Xr#n$+#QshDY!+7oT$NF~5h&zKgGuo4PSS=^~r zznW$nNkm7=6dmw|d~aX4^=Y zqz3Jd8#VTXHi?mwvQ6o7JnXa{tejQ_S`kNg)M(bNcu)FUQS3I2A@$A1Jf1JLk>-h> zUhz%sN3CKhTg5cV41zwf)$9}H&k<(C80$J`5}U2cQ+uLz^0rZisy)XqGA`S1q@$ES zWqZz}5{?_wWTEuo+d!N))M-V07H7e`T~8qSQ&m#qS*6naG)~j>O7|I{X)w6xr#Zt0 zTrHU2MDkiyn6BaDR6+4sQ_M6uQy#jjs+7KrLbmc8i5Aw5?UHg56+=v8$cvN$&A4+% zf#FZ-AW0~16)VmTZ})P{WZmy643%-Q(mmy82R=nC$Ce-PxCdDqK zw|=w{ETm2|O{R+BMiw0auVk7`m3<+vB$8LE!W6zS@9rG2Q^azRn9`SMBacG~{arnh zF^FWtKZ6v3i!5fpu9@QRRmC_?IK0{xe^wRaG-qGTtG~xw{j4g+yF|X2ylwGwsu(YX z`(j@Ggt_|rRB;t=n7Y|csZxhH;Zzu$F2{izLoOKI4CY>k6He_ zDsK;!v&$_1PgOZTg%RGkWS?37pQ&=5I3Jd?(=7jfRo)vaXRlfQpR4l0Q2FOf`7dF4 z`V}5&gA9Ml%;ik+FJ-a5Z|a`2oPG(oS5ZLy$ROqOhLjUi4k=SgpD724`twPox+1)` zfGmIN34vRN(1ya~%nO*Zf)$f;B}bS6DpO7wrW`1yiUAhc`gwgI_?u)?Ujqe$m`9K% zlimzc3m9&Yo3c09Zu;Kmo@s;>v=^k%dV;q{LpAy+ii;>#W+jb?(iN+P5-kRcsco!< zPAW+pSjX4|VXpMHftPQl3FMCnZxu*BnJhBTqV}hORw|?wp}xnw)R9-uOoS zm0N${R_pbC{f&10M(z57xyd{6Gif-+9|G0Q(WLeiLr@)AQZ?&`YqbXsg7iI0sw}`T zsXZGIqz^2qvIfJX_832q{;VZcmSLFGp123n_bsWi62qkSa6FKHU`dt57$&vn*n#v9 zSyE1;n%+CSJWRi2rL#tPIO=&HhL?)cl7nv9dD5#Qq325dRTN ztW3@@u|F~m#DCNhEBiA{?2kAD@qc59zkhTG{gGrK{%gv`){l8uyxjNzheq8#G~@9nEbT92bBAf&xmswz zpR}~Ud^D{)2n)1-%F_Od(X=glausO*w59!(q#f3^mFxD&_lZAaN!1;cVN!cI6l(pm zmh@MRuGJpr1k(S`lK$$^r1k(NkpB0U^w*3gwMQm_^v_w+Upt!A9&!ZIKW|CZ?)Y%G z?6E{3{R@`#h0(RzgM>i(7cJ?pA5ChH{sHO#U`f9?n$#ZF1JeJ|lD8FYR$&!9)B&pbb zocL>&^vfej#YW`B|7=NLCh5@Jl1~au{B=wFm65daCg#N7u(V$tNh^2OC;k^p`$ME1 z8ZH0E#l-(g%CCaxHJC^vjj3)M{SAh8MTH@b2n%JK<0ph=BiGSN@Vt+aWi2uGN{_UfQ{b>#$ z{s)%$cZ??Xr!Ro`A6nuc8BOd@O91gdvc$i0G_gP30L1^;5_3H^Vz~Wj1R(w=miR|W zJfz7Vbl!jdrg_wG;-6aD-#wakAZY)YrTsmlY2EwzXv06Zw7+*Wt$U#!wEx1={=U() z?hSa*{!2^y`$yBdSJpxMuPp7?M$@`?%t8CVS=v`d)4G?!LHoa3+OLy#$o`8LyC(h* zOUgyZC{nkinD{>}DVG()bKgH$JMphA<&TY|^v}6X{2NR8eW5nVMlG7nmS_o_~&jr>~YU};h z9e4aOhiy7)+Yv{caO}2sZ+YaFi>9WgC(oI_;=`A2xoq3k%RabeTgcJ2!%w{Eq)qSG zcEU-=9eK=&M;yO(+mX-P^z5xi9(TpIcW*sp^4Mn`vuWGk7P$Sqv!~BF^V~DCEcep? z^?v=S@TZ?Q*)w_O@YyF%^`3Udd8hRH_fzNII(_0V(%ktAfWg$N$ zemTd!wAg2sb)BF(KWWo3o1Xo_?v)$%-#D;x&B_g{56&A$O5s5y(~)k{}GuLeL z1X{0MOuo-2-xreabIJGV6P?J>XLrRfFzF<+1{~2PAsvDWLL>5$!f`Nk~NZ!tYtD(Pn%p> z)-qjj%~f0r71w;lwODb@R9v&ED>X@$QNIArz(k{Gxm7Z`-V?@~K$b6;qoduu zK>~tA4GubzJ=_!kq==wbLNt1oW1?JRX-KH`+SoL*90MBTnTri5%Q3GpUZB{_vK-?Z zGpH}B?AREyoTg!nS6pneSx&<-#w$BE>@25Q8RG_u%|FX&bjDbDR41L2Q|C;dJhl0} zJ=-QWo<235H;$3Y1NGs&?Sa^2AZbYklGyAOxBk-cRiJ@$k4`&DasQWTAndQc_Kr5G{(x)GD#f#wO}Uv9xeH2i6-L; zM@)wl++2kteZu`uN!GGZ;m9@N0ykgbC@bNPmt-xA6^XpDzjhr#KtpDp4+y0`?4&&B#8Cf072 zQ%YmD1SZyXmQ!|P-Wix!^I1-f7;{lzq8+l_>WPu;!oWnUgav!vkZ+NL!%exg2gnO4{>DWWA;Vv<* zI`&Xj;tX6l_AnHX4&g49q+<^p`h*MVm17SaesCdNb?m{94ttp-8GG`#%V{0fh%9R> zm#gigp~L0}JWxl?dmo5R7OSnzmz1ZFA@%FH2r_4N0sH6!_gJ#-Tbr%T_Q{s1Yae^$ z2_C^RHQm%TU2#oTTvLgw~JK*H$lTY*N zZ9in9>Kv;&$E(iKs&l039I85ptIolyvz|I*b8D%cv3b(7*4p+_efyZ?YS)L*HxYMp=z!w&c@@gTRMhiIqfh1h(7KQTsfj; zIqk9q?w1nquM&kX$GI%0-L}I0NCN)C@jl1D2oVH!`XD4&vJTo{-KghNBu0n9+t4ApqSG+Aj=sEEUdHXjF9Dw5f+wQ zDr`DGWI3aUg>^QaEwcRP7?zSMY&v&jIU|mRbvB(zvYfHV(xtW(Hl0_poKeccI-AZi zS^mfs$O(h;)C+?eIe2Nu%FWTwn=CJIZGuB4F3yqV=+k0G5* zX3;EXYO#=XMukk~)GTMtu{51bX4ovhGlrx)D`Ya?W;wHzg>*8ReY2eD%hF^(P{?F1 z&T{583u$DsFuz&^e)LL4C(U-p0s3o!BPIG|;L3$L9DamjBup3PaFh*>kuGZ~7v^x( z7;y%!T$sb*2N&WjHwEDEBTh!=tfgF-!(l%-M%1jOT$sbrDu~m#bW;ElPXaQGXSHNg z0Ft%{$@pB^6o90W6Kx=qO#w(eAw#surT`?KkXDddvMB(GCu!RJlx_+@(kUUCD6(3y zDG+Q$ZztM7PQ)F9K;lWr`y^RyU6o{vf&8tJ_2F|t{aF)W@FLnk4pvD#Aw#soRT594 zwQ00AR3#ZtA(`W{+DMiBz5IwakfT)+PeR&ETN|&EOb?JYW!A>3B(oCH26CcG;t3g| zT~{UXgbYQg4^?UiPe?PFFMG56JMzgfntAKFZ?Jsu>pF3Iu5sdg&6)qxo$^}ird+$@k|#)xkQAFSwbmo$JWBFJ$Sn5X?{;nSp)4$pAJbV$LK z!!sP|6YlB4ba;j%*MtjPIXrKaAL$V885XV_p5f3ZT;RTkY#g@0$^;_#dwBd2YD zn7?dN_JZ~i-~MPkMd2Q3lOtdGKy0!F(w60?DJ~_M)!ux@DgHH|j9;eWmu>c?#Xc*0 zA-(H2tXZ>S$!aDfDN?xy)yhid`NxseVP-}g?oNti4QSv5EjHdDGik66vCLd1SXm*%PE>MZw^c}UY1i}V@`)j zO_}ACJ%7GFEF~TgqnWduIx)`D;z6+Fs4L?vH6G|njyg2X(yKOsET=m27wE%MtTu=& zr=pFuH1$xHG?y&L1jbsbT0B=+GY&CZx=GW?^4H0?^?6Q#L;#Wu=oK9sPnKiO{Du0k z$arD!Oe`u-jBSipbZm%OPE#<(jT4(|meWv-v2-d!N6$jzgl9kTi8^p})TZa;jboL> zgBT&`#=TkFAwvh$<0#RlC3fN%Oda*qF?7IS8YXcJrcAwbwCX(A5uxIaEatyl1n8mlO=bV+?PwXNhT$6(=DsDPRltX*)Ext zl-=yAkdX(yuT`nCEGIwqF!5e}QEe6#nB`>CsP_b_sLm`W_eL!Ss;Jy7r%*;M1gfa& zET??-R8yqo6`$o4+o&R~f}%EzD$*(_t0Wd{mR4z^ET2*!+u4Enh%^Wc5Sn3#09iypZBy|j>j^WfXm^$jIW1Svk%N(SR zvD7i1I!05+Na`3$9mA<(Fm=>RN9(oQud!-U<+NTqn|z;1zW?W+dNHe5x@QhpbXMWR=n(tCS8|rF6(Dr9)OJ9kNR4kX1^DtWr8AQirTkGO|kPkX1^DtWr8; zmC_-rlnz;?bjT{vfmIIo%E2n-_jp7DYyEee6 ziEHiPx8(e`n0ek-|8@;k}zC4Z3oQSv8Aqk&E0itTTG%JXplpU*pmaK$SUcg9yF?u@TU z+!qgCg4)j3vmPE?)is?PdoHCI*VaMd|fb&gb>qgCg4 z)j3vmPE?)is?Pd&HCI*VaMd|fb&j|*Y?d@mrqYwuK$bJK+3v?)Ek+e<1HEI4)SiJV zRtkF26RAA{RjeEImM2oX2dY>_=oL?-)�pQ)D@#sbyogKou(tz1)e^>Od9ijVx#E zwNR@9RjfYrS|?Jw2C7(#WH}?Xh1w-h#mXeh8NiKN8K`2NlI4u+My&``v1-w)oJcJX zlx9n-Xa!&vuuubmDpoXE&g5WJf1rx>jo#oysvf9fwWHTJk?IRnvG&PwW*CdGH&De& zD9f36jOqzgu`bGT<|CuJ168b&^vWhuU4bgrOnP4vsZOYJ1*La2k?9CbTuEyp1Y*Riv2HjVgOpq?qcB zDtlF=SOFMS_Nqv+Ffgj@Rgq%7U{u+wBE>SosIpf@iq(ZtWv_}9iw>j8UKJ_UB1V{XFsonutlt0Kkn$EdPbMT%9CQDv`+6pJOJ%3c*I z)=);3y(&^Ht&A#rRis#P8CCYGNU;zzs_0dR)12hV^30f`S4Ds7Ps>rZJG^XfPkzwIzOwp?%!*bG?qE|(RMW!*e4G}JI z^-8!A3l}%Tvlck4LAbz`?<(Q2A>sBRT>7pO64MhfkjcABNLmabA7UYs1I&=L zG(rY4c~=QZ3nk>3g-qU6LejDc8OY>aB_ut9kmD9IIlv4_PalXsPn^gu%HYax?& zm5}sYLIyHOl97UtflS_2LNdY-a=nF2-c>>}G7&P6$-7EOMl?ch zu#m~SN=QaRLIyHOl988?flS_2LNa0#@{txYc~=R^NKeQ>ChsaC znIQ;ypoL7{RYEee5HgU1<%>*6W+Xx$WFd#EBr_Qy136TZy!@fh5pu{vj#NoH79j&U zS|#x$tJ7Dv2j#h<06-#FJx zswBM&az7*2RY^J!(FU?UTB#vC3Hb;MIanp>K#=_BSag>p(=?dWQca8O5#bh zhgh_uRgw+_`6wgDt0aAdXahM`CGjNWqb=k_m86eA9&F^gDoHmW+CbLFD>Z~CWQcaK zO5zC_iZWa!@q`Q}8>*6c@{08_LYBh*Rp4qIm$DP7{WdP&??Gl|>kCUINsByOvp#QlHp zPTe}jHmk6f&@oDfDywv;qDqG1$|`k~}*$&VyImi$C=kL0J4pGkf$`Gw?{l6xh;lKfio?~>n0ek;ji z{SPevot(dy{6X?Z$)6;Dmi$HXSIPa7tfnB67D-LgDru7}le9}ZB+H8(^Aj~z^XRe( z$lUb+XB=Amp9);lcg)@8=c3%@|5V^E|EGfBDt64>8F$Rx8F$Rx8F$Rx8F$Rx8F$Rx z8F$Rx8F$Rx8F$QsbBB3FdxEM#J7=+%swtgiv?my;Jp)zDIocD9)Eo!%A- znrXvmYYm;=8VZ^j#b|2})%8o3GuIevEuy-b$?~5^*4jizXcN9R$#Ui=3u~=H|Dlnr zgtDBO%UEj{9id$mVVTp6wU(j((5QrEwlmh+#?nJ(%!9^S>sWfoj2Y5cYadGwnK5@7 zYb|8yAv2p*U!Y;Y+DPS)*?kJQ{CQ4+L;#WuNM=B?3{o(V;)7HYNL7MVIEYz5tOsIb zkhTEQWI$RLNCO0|o${FQObuuH%bCCJ7@B21J=DhRZj29#<)Jp_eq($fjq9&0XJufF z5594gmgTG)jPU_GuI042h>Q>NamAPAtT`-$K zRx=ixHCmk$ic8TfXR%|HwRXKhEGgDPM)~|$EN!!#rIJxTs}@V(EN3NUl+VS*QaQ_6 zXc^@*c(J6;a@Ju+`Mj?uwrysmEN7W!l#L|G5-m=y zm-_7eAd();8VzD;Jd4jH3&|_p|98Mk#@0eojrU|~NsjXMB;Vr;NxsKdkbI9X9r+$# zGx9yYSmb+rmB{z_@{sTGbs^v53qmrXV|TGl*s;6P@&68ZVU@!R3;p*U@G`5!4r*2@ z9kNR4(4mIXp<@iCLkAa1hmIChpA(xGDor9%e^N{2S9 zN{0r%(xCyebZ8(g9U5>;hX&@-p#i*fsINo^Ryp3R680R*@9_pU{Np`se2=%e@jc%8 z#`k!%mGA%IiRW~rtQ7<5+QAoVvU-W+rIMFPUM_is!k{QW%$*knvk~zt|WI?hhd5`41 zlJ`m8FDcG;uN}NX&JRdFD7jK{mE=Q`4@*8Gxmxm3$;Tugms}&cR`LnSb&~5PH%M-j z+$6bK@=3`pl3OL8lH4ZwwB$3A&q_Wg`Ml%{lEGp-;{>_N?F@JMc80tBUpCz3+Zpci z?F@JMc80rrJHuVRoe^Bcc7{9Sc7{9Sc7{9Sc7{9Sc7{9Sc7{9Sc7{9Sc7{9Sc7{9S z0YG=g1Ay*~2LRm}4*R0d7zR5Vhj;R{VY()0Wn4nqkbBw64(2C5Rfr%?O z-JunkZv-Z;<8+5sWbOz|T-E6gt;l>mFma8i!8bBr3rt+`=?<;Pd^Ip}{g>r7fzWks zhe=k0SDZ{US4E0h+NiQuMT*JWsIpf@iaFh=vR6fFDpF;yiqv$Z%3c+znMjqrDpK1c zRrIRE)w1-L&qk)`RgrmjWQtxDnYqXmy(%*EktuprWELV*^s2}#MyBXhk$F#Kie43& z_eQ4ZRgrmLWQtxDnfFJ=dR6fdtbYK7I8h%)@E~@))s6PGVV)nEcP6Q2d8H z?UTn)#w6EX5(+;;dB)=cSNrZUlrhPrmxRKPP+k#niL8D67|NLBb_+t`M<}n@xX9Lf zff&k|^t>3s@FbX9Dz4M@q9Fz|rj{HQBN(0pbJNGAzTRBKV8+yvlVSwJlVIMK;?sg& zg~VXSq*q!H3{Qf2M23}#F%IUq(bJPBsq$My)q zbB|sC#c)Q|lH*~7!;^5{Ba4S8y;F+ej7l%EARL~A^G;qof$23>3};k&jRoQGB%F^M z#bcb_e8q4^)sll@gu|0?J`@$tf_j-2!x>dej)f5pPr~`=Ryjawd6n;;qWA!59`JAvHn>hhBK;` z90wyDo`mz6qIk&8@@rx^qiV@vFv8(UIG=oqCv{x}7Q-1;OOApO4o|}UM8d=$pYV0b zn0#y~GOCsw1S1@tg!3t~*fY?@Wigylwd5EW;qWA!&$`9NgZ`s5hBK;`90DU8o`my> zyx6_a9ceL~QMKd<7~$|F+|MN{U$F(Ef4h~BmCvYJasZ5QcoNQ+8^u0~{{J_IGpd#x z{~{cog!2_lu^E%)SH*Bf)sn+sgu|0?z9=eobh7-)7|y6#a`cOEcoNRnS;e+cmVYpY zGpd#x{30Blg!84F{+T9@FCU2EjH)Haz6ggW;e0iyZNnJuiWttQaz9zGWMK$wj2_Ad zlXG9)bHhU$k<(5)`9c5VF#jLlrnP!p+g5io@ju)q)Zib#$9;+Na`n9Bm95&Ikrdk} zdCRNie2t|1KlJb~Xz?h7yL|7!FMjd8gYe%=9ZA-*oFwf3GTx{!V#;N=CCvY2ydf|# z+qx)$Fby$9m{15^k`NgSv*gq{ejEgR6Y(Xhhr>K34(tW4Jax`dQv5itcd~_xr_S@& z%4x^-%wI85Bjto*Ef&Z<5hXuEuJ;NO!0I9-{W}#zQ+>;e2-@a_#RIQ z@I9Uj;Cnm?!1ws>pR;TK_nc&_zJbkkOWgm(C&+jnex_Q6jIRof@8hF3_|A~;@y#ON-9xO zi9J(W5RthqFtML%3nDU~2u$p?+JcD8wSkF!SX&U0xh62NM{5frG9M32?BCjfh|I?V z6MMThAR_b8z{I|v<+KSa&((p6BSDtaQjGZsOgb)PIgQ3nh*&LDPsh-hjI(;Eo{piB z8D}+7Jsm^iGtTOwdOC(iX`IzY^>hr4)i|q<>ggC7v2j)-)zdLFZsV*@s;6UU^u}4O zR8Pmy8H}@fsg6;)-UOC&5mqzR5lc6mMAqtN=_!$Ik+s@cdP;;|W-(j+EIlPc|1;KV zXz3{tdZw{fM@vtM&}WUcT3UKagx+kd)zi{bBJ^`(t)`Zq60s40+OWE+oD!K+z%EW_ zK!HR6k_<>@K(Y){Fp%PdR1!#4g5Dv^Qyz>Zc1FMwFUQX;XQVO4GF^_cSUMZ#xP^7a?5c&%NgN}F{6~Df0i@;8DqvQ=ZGw4bTq~qK{=CTIb)|W z)_BVKCd(OFjj=jVy_U<5-uhsA8sfp;tJI=dtewZ4^una#f**SiUS5l&r|!~GUceI; z8OQthUvA#CBzGa@Ek9M>eIB47K&ZA0}vz)l? z8lwC3MWrbUpwnED`fZ?!E1z_f3yKScico{6Ss`?eD^eD!EUM0MiLsleVYpk!0+)r( za&m9C0fn%d&X4z4DVs4CM)8#9Ya0&t1pPG^+pU^Z@)jN|*#wOx6287sZ=vNG0I z=@nzR(@Vu<@ahe8|G`=$Z@FJ((vwHJ*2r6Od9+9>YYClrl2@xF-)0q}U+8LCCTF{( zGa0%&< zYAY^RXfknu!uPl&;d@+!@I5X&_#PJ;eBW8qD-X%i^vYwgxXOdDxXPoixc;_(f~iie zH0SilCGP*me=aG9cb4)0g^vL39jnzmc9X1;>@L|uvZrJ($y!OW^l$GNl*f={STZ76 zC)r!FkK`eeN;hrq7?szUWLz>Kd8p)Jl6@r)mlWN%y<@$c8zlQn9w9kE@<_>}BnL{$ zOJ$pN>z4n5CH|0VJ~r_zr3a9%Q!1tb-1O?8E56I zcHu0i`Pp!5C9HPnET>@_Yh|oIE##m*ht6>HMW6TKUK$ztW6~>tH%HcB0 z8Ayz=@~BSArBTmpWx6|BUE)EUx9!)D-v0md*DwE7Rds^oM9E2#=SiL~d4c4Gl49ew zz2il4zF6`S$x9_Kle}E=3dt)a{ly~tfi`rV^9@~h`C%}3`C%}3&1|yejk{(muI<6) zmxuj#{rcsg#{Tk13N>i^&!^~%nDR&p^=iz?fhmuqP}|15DKO=c6l@T7vjbBeNx?G4 zydf~ zF-3VILqjp8B>%eGBh<~it<=KTLk4Pq@=8T->+MTHwev;R08^ErzlZ?#&jidRq)NM7Y3JZ;PQ`3HKHY zSG_F;YY;AQNyyC>GC2SMNfsf`FfzF<29kUb zZ6K2~0FZb>hG>)9Vj%J4ZOEAxZE;&n{wlfcb%+s_QM=uL(egpx@XYIwwR(16m+nMN zq>i!FF`ha`Q^!c^_*?FaURQ2%wCM-gd{cnEkg?P;o;pTT$4KfZu0$q+;gl)1B4Bp9 zv$EZ{4|t@AM=barPicfljpJnvm$(t$4&Si53KM#9(mz=+@9cjJa&`r+;ny= z%F6GNyjSu*$@?W&NIoF>pyW!)Rg!XNr?cxra(`Iz5y{n(k4io!`MBg7$+ePCNQ#}G z&aUg_yg_oKPSsRFvx;;=u>(;Jgq`nfUqOEJI zGE!d-RMGOazZt171*+%=+7yk{7Xy`C0**B;^Ir&5u`8&T?veU@ppq>%Y;U1H7pS8D z$QOz&wxTwQEjC(*QAKSO6phBHqBaVOwq#UM8wEuZGpeYKf}-UaRn$g7(IAZ~YNMcN zr$!aEQBX8rql(%nC~MUe*=i%*I=oJSy4W&=0SOEeKS&lpatTrpkg|eQ2S|;9R;gvL z)iEy-w!s+EF8X$s(|L@s43{H-{t-ShR?2dm(0Q!LSk;uHiB4Qa#_F>ib9AOEGG+vp zR>v!&`pfCkmIJd~IezI}RAkKD$@2%9$OHa{>xP5Y77@1mXGFMS zuiavVS^m$5e)Bo^H@K29YrLz4Pg{YtPG5M@2mgBi{r7kDbad2Ic7A>B+|&E_z^`xl z$Vl*;Fu#16RgbO+s5-~1&e5uKr0N{1I)|&y!K$-fbq*eI(4HFxLe_?dL)Pl%*AueF zF3EA5wwlJknl)&!IU=umRG6>07Amf}ifg*!nyk2{5*PI`J$KFuQmwDpeRnk_RpYq% zttMHVqgCff)j3pk4p*JJ#X!*)QPopt+xq^2fpbZ^qqn=80?TJZ@Tsp1KCKsDb;)t2 z(z9+IDzz1>SK;pL*>zWP%cjlw7hH+gid`T6@ZdFt*I3BE6r^Da{mUQm2v@-Cp+SKa zTmOc_F_AjPQpb4e7)>1`sbeU045yC4)KO0zV+X9*KoR=-4>_c!YS)cd@;QhM;uuXG zBdKF3bquGD!PHSN9j#YyxzcL1cVORrsg2fmUAD!lr=w?Vj4E!u_+7!Hci>?UGmVR{ z3PB#WJ_Nx|8_aU6_9%P?g3s_n+-LVa_6vpT-{rsqiKcB;^y%yiKFhA&a_J=>4Y^ry z=%HpCJ7L&dibqb}TfbxASKHTW>s=FGxL^i`SeP3;CqGl#`cardGt#LB+Df$Br7Gm zNOqNQUT$k_`5mj|vzug%WOvCPl07ARN!Chg{mVCai_Kd`^a&xG6$lk6*b zxMV-cddUXK{*p&X4v;)j@+e8m)+@dJw09gR_ra1!OAe82lsraqsHA~RFu2C|m4DXM zB-ivNAp4`aI_n!(ZY+A|z^YZNYT2WVZ-?2i+=jN@*Ovah_^;czR}#wD`z*eW$;rlr zjjb17hN1h%2o?y7&ii=X{6jK*Q_?^7$g7V%e#>)?53O;%)l;4IR42Ds#tyQGJhq?` z%m3zcPhO5reQo1Oq{v51G3rD^4sX~|$J#?RNA-%DC$~<=3e-LiTCs<<(E7n?RG#aZ znYqUFv*U82v#s$z$kG3@9EI0DU9(b|GnMnzU;OT@j_vY&_SNTKnfP_qCx$i-PpPY< zo`donTH@I;J!_%2q>4ixdLZ>2@zAMf$Gk#MPKJq1S$-B-er}RwtHixl@3wl62^*;g zM;p&ZhmY7wyD)2GvEl2EUB^ccHKYK2>YYf)MHLMc4<6^RQQO! zr1j|I4!dA0)war-FGC%sSFTS)_tmERSG^S1g}~O^1~D*&F^@(a< zem7BvZr*yn28Zpq&otGJ?bNaQq4@<{w%6AUF<>QLHO;l2qt}tz8!WYu+kCw zOvr1;%xuH%w?v_5MdMTy_^4&Cu+*2$&NhxZ>M-cu{>Ew0eAKcR)&$wI?X#@&p*sdr zIux^G2IEXNu66~BK7b!=Vcmivou_Rrbu5R>Yg=?^HAWUmW8eM&WT|)#MQeDSlj7dmuh%ZrR`YPBaYF1 zQ;lR2nOoE-HXW0C$fHuV5K+(eg-|Uq!`&67ke`l4l_;*IRH6&W@Sd7SYq7{S1^7~` zucL7V3Rhc+LT)<8hLqv;zHXAnT&WSNvxg|u$~5X;u;t6tX7CS#-~6NqvY0U4W7N`K ztEs2NyJtSO2X9XUyEHyVYJAkPk2C#eJqtT3-GmY!QOSBcJ<6J1U*l#J_=sbQ&HIBx zn)s(yAGF4_c1g8D757uJ$vH}J`NgrCRRy0Rx-Tcu_0P=*Tf}N0#`>DZ?I`jQC(oX_ z9drLxl=z6bw+Wkp*d~L4RgJHq!AH!#Y0!vFqqCyn&1^h1TjySB9Ii21(b&6*#z?B6 za(|nA{2<9k-=Zq0y58AkxbZ{O_=vrtZ+-{0m19lR7IsiuQBeyma$tNUbo7e-2KH*) zO}c!_xrpW~>IkwjC!AUt;NT<4?#NWADgPt>vp4ze0xt~c71NBfA&l+OB+hSPyY-HPIEd9ujP!_&lK z4pPtYn1jT#eVuZk-?=oeixsgR=WR97#JamQ`bnOTIQQ6iv@u#^^B3WP|VJCbgZ~y(AszfIoZQ<;uSGfRK&)lBF1Ayq@JU(A`;K` z!MYvfHLp++y<^_oENh8w&#ZTjErAlEXWplL z+Fa^C_!_0c!b4XUz@xiuxRZu`HE_cEc;7oi1?Ax<3OdNc~)xV8{S6&q! z>Dwy`KDNp z{Sr&C}DTpMC1w`oV#nQY-oss&AnZAESbjwG5`o_Rpbq)R8BhwCR|`PrQ2T z`OhyC?w_u3lUovQV00%1vno$hSW$P)qzErA6In5`lwQ%F&^GoJ`z!6M8wXHve8kbQ zZ*I{oKNs8Cnz6=#sPPe>mIrLW)iAl&Mm8-r?D=RLC@Y%DK)Kgy-zD7rp^bxyi;tLO z&oqmZcU*kw?3Gu1m}u5il*0ViH{}~!+THRUkp7BVNUd)=X1{2-18WHx5UIj~LT(p0XAv z*|xKtb~RfnW1ynyrCey1=o5&MkCWb%K2psF#!$tW-O`HbUB`pLdN2GXWv%pW->#Ys zuSitFgsG2Ivy@N+>n4_DDIx1aO|xXJEzQ!v#L`G6%WU;dr1?#VzS&BC6Q({?&2K{4 z9$+#AsD`W?rP-+uSF`=@GBX2XOLLl#y<=%k6QXaXlGB8#4_9-VP(A8em0?C%wSl3M z)xm03-}1iW60$z7wNBBc1_z!_hQb1;K9*7|`V*>q zLX?*_@$MZ@m$QuAzQNcxrH6>J)Jc&3Nik`O6Ru}kTpYg=|K6d&k&Q)3Q({C!QObnq znvXHr3sG$;K8?|Ls~IPhwr~3m`?b65-FP}`e8e@>uCuPTFr$(GUyeHL$SY6UblioE zHtiL4AFUU6h;^@h8~;G8d=#)Zpyny80Z!;{v!jq7b^ zv9-H#JQ1E^5ngG=?3-?u?y0Ep5!3CmH&vHk9A821Ypkn;v@{C)>$sR+$F7Yth=`9` zc7~-Fax~&OS~I$%M$Z(Zgtsh=&{0teiP^fKe2aa+A!$5ey;2|d2d3n$PV2^0&sW-0 z{#;gW{>z?ck#Rn1*&{9Ewm8_ag~*nPYLdA!whiG8d!iO%?Agv{N>b4N9TY=+10y~d z6;EwcOaGe2xnz=$xPq~2Dc{ZYuWGy<6+WU$&+O7v2UDexVvja4s#$w@6D5`{u`iRO zzEzEjNRE$~Tz$~)N-zLqVXALHYK<=i4W?ziOtYQACqUg{f8HzdB@qs0VpZt6YG zf+Y+ssrMjrNf=lX@1Dh^;E8|tNEtarRS~T6(;{?_mMQ(UEJJs_Oeyj1(ff$9iWBvr z9a6HEQ%Py0OsUqP<{4UY_d2{onG)}wg(RiKzjvrGjh+n>qI-CUEZBfh$-+>Xh0Y`k z6J-_>?;h=F6opOvJHuSBC!5xyffvuAKaG88PNq($MKJnJ9QzoDIcVZcPGDq-JQvdV zB&{S&ZCx|+4e=+w-4mKDJ?_N2bDepsmJ?6wTH0LLdgWDi@TD^h&*OT_HZ{C*_qE9z z^~QTt_$;~Lt-%#wf6?3NBTuXKEs z*~*Ezo4@ePh|bbOQJ$&RNup6Ym-;YmA5PN{w1H>L6_5iU5h&@2;0b&mjdw|#j z#2z5_0I>&%JwWUMVh<2|fY<}X9w7Dru?L7fKuR4Cs@#~IvIDW(NTaMp${Ep+lIeypidyaQGe&6v2jz4s~+wn(^KX&|y z<2{Z)b^Mv*&mDi^_)Euo9e?HcYsY_g{Eg#p9q)7eo#XEv|KRvXN9=ru+Zn{pAa(|^ zGl-o*>F6#Lggg2C*}Uok8pjVrLLLgV-6w z&LDOMu``IBLF^1-XAnDs*crsmAa(|^Gl-o*>F6#Lggg2C*}Uok8pjVrLLLgV-6w&LDOM|Ky0B?~F6#Lggg2C*}U zok8pjVrLLLgV-6w&LDOMu``IBLF^1-XAnDs*crsmAa(|^Gl-o*>F6#Lggg2C*}Uok8pjVrLLLgV-6w&LDOMu``IBLF^1-XAnDs z*crsmAa(|^Gl-o*>F6#Lggg2C*}Uok8pjVrLLLgV-6w&LDOMu``IBLF^1-XAnDs z*crsmAa(|^Gl-o*>F6#Lggg2C*}Uok8pj zVrLLLgV-6w&LDOM8Mi_DHHf|U6k=}>dxO{;#NHtG2C+AYy+P~^Vs8+8gV-Cy-XQh{ zu{VglLF^4;ZxDNf*c-&&Aod2aH;BDK>=u`7sOLF@`* zR}i~`*cHUCAa(_@D~Me|>=u`7sOLF@@)PmuX{Zz0dq4;At}4e~q<@;nXlJPq9-*L7Np;T z^jnaA3({{v`YlMm1?jgS{T8I(g7jOEehboXLHaF7zXj>HApI7k--7g8kbVo&Z$bJk zNWTT?w;=r%q~C({TabPW(r-cfEl9rw>9-*L7Np;T^jnaA3({{v`YlMm1?jgS`^iTM zpD*{(j_jA)#7s>i9B8_Q~;Q zpB#L#@PE1tdR0j4~b*70+WpLhI%;};#j$C=J^0_@ z_zlN99lz=LEl2*h27T)1b|LixQa>Q|15!UA^#h)xaCZp#^&s#(NB(UM_xTBbr}H2@ z2oFA4c$biN_D9D*IsU~_7mXU<;@IZc;n?Tc?>OMNtK%vm?RAag?v8sn?&-KzNPmyW z`z+kN&jNX$1@b-%P5&-e>W?hxb^#{{eX)1oD0e%^#Rq9J!w!o}1{wX-96C$IU(R z;H)Ee!{a8uyssj^Ao&H!FGzkt@(Yq*ko5-GJb-LpCIEWNIM2;#~|$(q#b9qsd@S$e~mNr@h4UAGgZM%gfDe`xsVS3 zdLbPiq{D-Bc#sYc(&0e{QjmcWB>bsD!h?hd2@et;Bs@rXkZ_xYgaZi&5)LFBh(1Vq zAmMn?OgNBmAmKp5fusi#4&=(NIpO;qnK-YI`!$a5*FujMq`Wx0O2~^d5Px3aknS}? z(gjHuBwdhnLDB`uH%R&*1KTHr)c;r9eY?BAD&)bR7cV?muz?HS<^CYy|Ll0bV@(YK z|2D^Ej_r<}j@^zuj=he3j&;Xfh2(<=RUTl6+zpb>LmWpP#~mkx)DsJ3%D1oMeva!M zHwcNB1sM-gAms!}7bKm7g~W4+<6|5Tb!-T+M_fpO)H6uM+4y1+C9h$(hpjlY=ShKrzoy$dlyHl$nJ)i-trg$eh z5g~6;K{`1|CkN@|B)_{SPn^Wf>LF{hi!aFPiq#?R7IbeDM?Or4tlGaOEbHp;FY1Ry z2hp(T2wAj$bm|!hI<3D`G4zZE;dShMTxSNnV3$vh(KRtv3=LPZM$h9YFLulFU5H~ZkK+X%2S^;GPvatvw+qqp zILhnbvV2#{v{oGXc%hJdfW(2l-yoz+rwNJc0wMYqSG-JawE}B|TO~M9lCO|!F9y%b z&2m}GZXypxVP&b1+%=cAtP%NW6m}^UlH2F9mfb}jg2Jw)LUJEn*0P64F1yNCl?urX zby*8naB&k>zPeOM?ySpNxSxw_vhv+Zh2$2ytcAY z)_Cj7+8Q^lKy0!Jm2hC zG8442(tV-6&<0;Dqz%4Y_#yev2^C{<-y=WIqndq>2l{ZSl-vTDyfk6U;1io76*-LJi)B#2UvudYI*q6W{fk6UuEvyGl z?xW1|W#Zbd5J_NcPhgP1Ac46!)&nQESL#|kacv(ENnqLqfk6U;1mhd* z2fRN!<~}3$I4*ZwEo6q~c{OWK{?}?*?>_sGN^3*JYrsj4}B=(WR02X zlgbR$lPfZ+g+w#EmGbdovip61${w-Vq|u+y z$~A+VUy_NplV(6*Qk9e$;uY$y&LWz+&#&umSpE^0jK>u^Tn)tU**aqUtsiG<*8@-=93RFvQa9 z_zAyxB4emU>oqbd3Jk9(@auoBpzBi;1%^-*_~AfT(3Pr*0>dN8~N zO9frMnkX>bq42&^LD#V+3Jhr|@FR(y2VK#cC@^fH!0#)%g05{%6d0ON;HMc~L07pZ z3JgCe@T-odkX$gE<@<`U%b!uv)vm>LvswOds2e=AsN(Y3EZ-06#*!+oqSX)2K;2YQ z#l^JxwHm0KORBi0Hp};i;udVrMsaCvmOldOmXa#2u+8!Vpl&Ux;zC>f0uR)uN~*Zt zHp?Fcbz4E%Et^l0pL~ylx?108#aWwO8GCG?j){~tY@TWKj~&(`>yLi4wMdpyEL6J` z)Yg|gq)6#)-XK{?!FQMZe9E(sg6}E$g_LI<1>alpb1Ba<3cj!8r&FF)6nwqpCsUq9 z6nuZlPo+F-DENVb5C2Z~6!~e0d$Pd#?tMNYF!pB4!hhC04W0e+r$(LMxenuUwk-Ug z%`<||)1%JsU57C{TNeHo@$b>e^1l<4Byqhk>ni_=*b?Y( z94TM>C=y_OK>`;#ZgreF@wZI$InsbKLIu9>*(%r1LR%$F|14 zf7X%y&*ied2K##UQ6$52FUefw_%6q3#|6g^2ubE@A(Q5>g;d)O!mKr3nA_f+-iE8v z{7xo3UMlR{JV*Ekxlg9$D~R8F)16*r>p}ies%)vnAa5Z^TX`2sPkPs^!q6>flq5%^ zB$;yw(>aq~tf|KRRC(G5HPA(g*k337AqodR#*uwv+zsKBN_v>PA1fr>kwR+X9-*~R z%cG@dM(u7qjnI6MR-L#erNhs}@)*W%KCqZ3u7f>J;zsXq$4!opcYK255su^m{iB5B z@rgq6@>C&J{t2P|kc(Y)+SA*3y4?0bmfG1&xk6buSEK$1g?B3G*BtL~yvuPnMa5F< zeRA9H!Cd_jMl;32HVUzv=dpa#V*!Z;Bo>fZSd>{TntCR$33sUW)*H_tYkXMSh)5+#!!ViMMJ%#R8t=97RjEz#@~sx4;zv0(D1dV zbiuWbLqZDjP~lej@9+MPbT@OxW%6fSe!cK1LfKLUT=_XwjYiMTZ^)ZyL81kTmVy)Q zC2|uj{zQwLXfGEM?Hhz1ttzC5mZ6+zL81kTmWm?Ucgan(_!BK|qTMDW+BXV4T2)*T zEn_&*fY8zYxFPiFI6~=D&pyp0$G7i$#-1d*15gc1!yamenDqHe!0EzLTlf3VD-u zks~j#crVH$iHf7V^7{rJav33CEryDTAs5`u8V7&YN1!dOx-Ey{hY&mxs}lk*S7i1? z*R?nse{W?g4;%lngfPW5fKSFVSM!=E-s+0ymx}rgy(WsEa>cioiuy&pCW^PY;ssH$bzxzWlN$WB zyjH%f%6Z(lN|?3I%#`fsHD0sg=Z1^G&L->^oaNpNV|%piI>qh&4c&5Y>wa%Qu*C6U zQs~hJ><(JAAGC5)_OsO~DOz+dK_t{c!p_$%iT<>$G-dr=i&$`~{OTFo4dY^N> zFO+(d&GhJHG{Y~JdQ;8x=x^wKsnA=j+%I=!GP&`P!XrQ17FpkXQ#~dVcxHg>(d$~6 zv#ZASlNOK1tuC@rA2;bcvj(q)G%4+%!{i3XR?KIDPVo~TJ_@ulE8Xhx+$Lnap^q|Y zK7#dG*L>4>(PfJw#5=u%4*7$l3^xd~`jQLbUluB*^UqRXTY*X$a9rWI(s38ZT^(0B zt`<@O9IsMF=VK*3mISpELE(54#vTnvw7}cpy5>xmi?^dLm5vUxJoy00hkkiSW0Nfh z{q>h>A7xgvD3QsmYuc6s#S1XkAu)6)K-M#5wG`g%o#btTn7-;-6f3Li7ckO`^Sz!r zsHd+t=MmrG5x01Nnq#YDo8vM^4x5sJ4q?X67la=* z@w{52x>HeN8y5dGz~4CjLYVcWzi{GJQKPw{eV`P+Bc$S}nyhEqtQ9IQ+6&u8EwYU^ z+0A;kPty*n)lA&q^*Allb^SO*lWMl+c$X9@-5(wQ?8wVb{Qv66yFuKU*G4X+$kuPV z>!UOq`%M+kvptXeK!NC7cMG$w*#+{Nv_o6!!x7PsO=qU54jel7n9gET9XM+9XQng1 zRLATDN8M3akivl!HVZ5C@>d+(z&83|NDOtL(K)<_k z6j6Ier-`6M$I&y3E9p}FqZ1{n6eVk>U6V~m45}X;dR*4ExSi&~%js7o;|1*w9eQI{ z*ALD#tI(^(QIROpT{HdE(T@EBEeem8^^2~#rjLK;cnhSjxI5 znpXmaM~N{j>zZm>2^1b3#xsrUO)G)Iqr+II$z|u2K;cnjFyyD4npXmaN6UuFuIZ+g zK;hA0dQkbAR|17cDa;*X%`1VzqZH>m4@;d7-nvFw@T=k)>piZ(}lNAC5Ri9mgFfgrra0nXWory7*`%Fq?M--rMmZ zLM%sQS(hFamozBC42fe%95J2p*K54d*=h-ncw&6SuO7HVe2g1#=#p_QfSTGS#zUbp zU9GybFgC)HX-Z5jY7}mo7>S@m4QE}GO%sbXNA2rK&*EJ1G|iI%`4fDefUs<>26irCzu+u8q`}&=ORa5X#G2%v*OXcJQ1gnQ0#M=|rdoT`il73} zIn;EfnpOlAfKCIQ)~T7YBBni?RK#J%PA2S(vs6T2rxSL&vs6T2=Mr|-St`QV?or#` zo8b-ahkW*;@31;z;c_6!caQI=L|bL^nN?Cy8re~am>}r{2U|=-J1WsiA*qYUqSRIX z;7(jeqJvRr$&6`W7`BF+8wul}6o#$orbfaz=!9WwyG?RSXK{>!jtyJAhYTH{i-)xl z!jC1{%LT10uoiW>Rro}q_V|XIs9`qLE-BRpo2X$w)ZSI9)tjhcNYvQ-w?w;#o7XHg z$^y{dQgVX7 z+KWpy?fdQ!8&*W^C8e77eRoj9im1Ibs&xVqFf`q$89yI3Ya zLmb=G9906ZalF>?I>+lBZ*aWP@g~Qo2{YYsPIV?nr7rc+;Z^F>e=ij}{y&=P&`wla z>HetD{a@tx633Skv_51@!s2k$WU_w#Cn+!_5HK4U-botvLgjx-h3p(}s)IXGwd|lm zcAn?>0>>8;v_8D^>^w^fWQTy+Kv>1?SUas4>p33h363W^oG-hyqRK-e77&&D5w8Xu1ZO%X){KsC68pihYx4 z$}lTrX%Wjb=l=7K3yzD9?-AM!7Q+u<=w$<@nj+Z)K=6JbKsZCmH_A^(WXWK+MLo79WCR%+n zrWKD7#ERX5&+37@=a-eJVs2}#iYR$_-Inc!ZS>N1F%R@QPqkU-S zW9Q|e94OL&Gz0CtJd^`PT3EJx`#gEvS$QZ2y4DK&=O3UvlmpGs?x%NJ9?F3py-J%H zJ1-CAK#^{z*>30Mp&Te$zg#~1faRea=+d{d{)Go959L6UQ6*bG^MJ7u8@h}<8ew)? zcFK$%Ba@ok&dW}jQDo@S1itgKQ)U!xZ0j9tGGtn(V5mgRM%Mnh2PihhMU#mkTfX>! z#iqFEGI?mI+i9^WE_zHZYMDDPHpNAe*+&ZpQ*7ELDK3g(daCcN*c6wsm^n7tu9#iqC@hPA*t zJ7?hkT<1#*OPJ!a0=bs>^jl;*AA~3_n%AMZeBl9$O>xn^9^Jm#ofezoqQ_%_+V0Ma zO>t4Y(G-fJlu{2a)1-;cI3Y@arX+dp2a!ZLGnK@+H&}gh%YM^8Wo|~ zOl+2$+dVg5v)oKC)v?^bky?wV%CS=1+~EZ-b8HuCA#07-&v5+>bp`o2jwxfhO_q5?jyw6wm+RUwUGitl7RJmMSoWEF*a_RAV`x3 z>0)|W!g07^yX_^`AJzObSNa7?J&QXQ#hxi(iRxa{n%_~&3JgoZe&cwbg&zO?o3*qA>w{5>N!?P$1xn3xvdnS+bjD_r+ulVnk5{ z55VJ}Kmiqr$l=ZBTiv@XWM&^eJyrFso^KyhzuBo@*Wm`fY9N^y!G3F~^7XK6wVt8_K+F3(bhWu};jtnXc(rBXar-b{V( z@+_62HUALjk$3n&7|y9YOQl#&Y*hx-9kEqsL7t@vah@SnL1EZ4rN!q}p7pKc6nCp8 z8tZ$PXQ}Sd`;m-N-@80Z6`m=r^fd4;&r)fX0DjP}>s_9u(Fy|N+@7stnl-4Urt}aM z>BAtYf_O6UQ-GTa>@*Nf2gbkfeEXr0X-=m{s7W6M$qW!b2K-Fm9tU<7h@Jq(&uW{z zFD%hQr`gn`b3if|#Pfik58MJ^p9IlDVEhN~4;-w>US#YdRWApNDp53JWKcKR~gYy&851nDav zc@@N)fPW3R&A@H}(d)q2j)4c{sL7Pypqy<5rEMVH4w4-peiQh&fZGY|E)eYo#*KM! z(%X8$x!KD$?EuL;Al?W3yTEkk=EH_Mt?-P zztz?m ze~zvD4%qKO^nE@JjuL(El*BV zUT8J;clExi-dS^zOFuCD2g=D)$nf53=;LFGTt^gk$bKbkB8B@0pq5)a}S_yo8V*b;~`U_3*7{?qc1ndOt`Q09LWp10A1ZhLD#8wus|o@-_?IxcBEDm WByY@O^8-rD-1Y9;UFWd7HV!zhci%ea$oqfQ-6!08XGY09Tl(G8r>m-~ zyQ`|JtNZjhbJVNm7aF5zd!&Em@4S6}q4=^hp135JJ9vI`@i`Z-z65wwZjUCS`rUVp z+_&kG;@w-eJ{sjt9-ldT{-V}Jhjt&{ws=OzA@kd3`1|Wd4;xu`=!~I}4L9F5x^{iX zjGM>T4R_qU;fNVWbwq8$>36!R;eM8%MXV zShf1xC4(!rFI#rmdE4K;S^|tNHUpaX3w&klH+Wzis&l)=KqH_ng?_1%9jkk@gzh%Qs$3;2c{XagX zf9m|YjYF+Nw{+jOW_ZT+H*H)y!{1*w`p%Jcx5S;l-a3E%%^TLwIO_VwnYmn{&~)=H zYesL`u;!+x8g5yC)4JiC$D5a*yJS`Qyz`bXyUtfKYsKC@(+n@)fJkEw8%t zvRr4Bi%j+fDP-Tdq*a;Am9G=C=JDZ`OV2KkKl;J@mCI^7mz&Wvr@d|N;yEYIn_Z2K zqL<2Ao&r&f^21AvA{XU{!d-5y2j$k=P2R4m^D?REiotUSFMhb?^ivNXXrDcI_To9G z&NYa3mBFLjOr^OdT@C_}9|`bMfSWw?qXABva;>^p3-aRuPRsHQxiLa% ze3YLd7-hgYo)a;y*~2LB+OZ?>rRzEH2G13*7+f{j$ml$K-NaB@K`Hxi2D67c+DkdB zCD9bEC}N-9U{|gj9+}i&oA$7I(rYb)ozza7A9<*}W%Iq8AKChtH>Ucid2fxWeiCEy zrsa)k0kVkl;~BFXOB-5#BAshancYIfh}kVR9hiOvoDE%D&V17~lXb+>DYtydSY$-=Qn6$&~jB%JO zFmP61q13rS_xhJRh6@CSn8KQx6BEK+y^_+IX)fn=3_KSV7N0twJKef}DgOm-Pk7WF za!A{v6Rmg+E)JV3UoCjxaIS5^ICIMc%2C$fQ`%T8`FNroADT=RxrRMd``-GkmX3LC6|-Pn)U>zy zuA4;P&zB&iIj`>)m-CLR-sQaGa+FOe?Y~%f)8+*bCfYwAI44ylxle+S;+Fmb^nZX-%Q>iv!h!`GGKC3ohsLj=zs14Ns1Lx`r zYRkPrAe$fzK9y<`O?cIeEgM@lt!nlLz|(Z!SgT1w&j zZqyG|+@zmIYZx)tkz*v?pdVs(_@EjWTY|$6!XvGoqdg2UyLz+gffwp_xS$@3+f4-q zpGpOZ#A6i+0d>iADp9$`+#8@ zRxXL(oL2=1Qxiy`GX!_8MtVm{hwKi>+-AYdsthr;RRtsRR<(5H(&+-ELR7!ERyEnO zu~vY@svr!>2|9v4AJ#8r4-W!Ie-9Zv9>VVdj-20b@Su0618Cvpa7kEnw1-j7)f0wp z?tKE~z#DujK_+tZf?T;`<%*}zLuQAk7pwP>E|>O@kJ2r~_YwV4VtouaBKnxYW3fIC z9QuzMJS$dsQ0C)?OT@}>`KW$~)$t2rb!HC?oGTZGQtrb7naB-3mB<(6%;)t>`zve{ddfLm5OVG_0+}EUK9wL7 zx#h~lHG3F)YujnIs8vgpJHl@AcFk;PIimmIpq>=ml=(dfk_qdZ0sdWs$4dSdaFpfXiIPzyFmR4n7)iPB2xN*h_*9Ba zq~XOg&JNZjo0)&=eH-tRyc6;>e`fg;_H7(4y>Igay3E-5seUQ3{t!5G^Dhk^i}gpq zq5qk|gIIGv4)C8FJc!iI2k?g1uM8K)jl;nQ+%F6loRh=Bix|M+l6jsO02nyezGR*U z2MnCmm(26Ip9p3vBtuN4-$b2Wzr*9xZfES*CU4gK>(x+c!^eOwm!4J%Idz06tywoI ztrY{j$>6cp>VO|9(nf>FTB}#KaFmBPD5V^6j^mqXkwHUQaE^DPMbnjA93BjS!wi>*oLL<{;9R*xG}Yw)ZR;fWF{n_i_eHh`gg z*PcX)D4#Y^Zk3e_N_0+-dN3Z>j%4;`o&iQ%tz0sDyM;JFti~!#R_VFrg4;}Eh^b5? zu>@}#yOynd8n<_{rs1dk%nn=Ln}#jp(aNB$K?mo*@GVF=Jx8W1oHi1tMJ z#DFjac%o~EOALsB0~qC8{}Kbj@MtUbSz9U%2p|o%jwc4>d=fxvG_HkYo99Bo&AJRR zm31Y?6y}0m(=H4S;9QWkE}xrpE_e&wLQ>c2CS@gW4e)muJhqOv1^6`vkFDYDz_F66 z4W89LFf7BBN#+3D2QYB1o<#fLfPr&u3);_JC9ur_2A@h5!?EOZU#{IH9+dX$Tu4arq zviZb_yj87OIqkaj0JPfT@4j4FBE@(gZpujos2A@h5iR8U1mi`&5;!(PV zm_DwXlqwzrj*32F@K_a(2l|g1JXXbrfFm{s&#D3*)bTMZlT`)ulykVODu97=ZHra$ zVS!B*2A@h5iR8U1bV6df&CCP1n^S94q_-13Nk$a_~g>*eft_j#pOrz`(isgYa{og&$=NK9ztId3pg4FIzHQOub*n*!=W0GN{(Y zi?7U9LfF0W!uK(Cz0rs5P?t+@hklhVGa-FXHz`$oO<6kw@=e`<|E}R7RVVtkbZy9L6c{+iGiWsTOMz|B8hk3HB{~X9TRH86)cqQ?UQIOzt;hMLN_NotoL>mL zTzb&f>uH#&u!YBB$)lkL;E1+l@K}Y7fxgw?u?m|4e1^fZDug$@+6m5!TZsE4-K4~QEO7kaB7?``J}%HN zHh3)V#%$Fx)1pQV>vf-q6^+4L{* zl4l0^IR=jnU}=CaGk9zOX934EEjM`90N{-$Txqz(05A^tgIi&^!~noi2RO$w7=ZJH zz^Koa%X&#*;HR8|6-KrA);^uTUk4p(dCBxahZoRv2GL7( zlhV@*1NRYn&S;5Lz7Wc>vAV{mQ5N}N7E)(1q0fv~$R1(YZBWdI>^i0gvbQvYzsGF2= zTmu|st~GdU9PbG5>kJ+n!?gi^y}`4}hX-}sV7RQOgb%oNhD(%>g5iZ>Ib5QA3Q683aR|T|^sdcWy;Be6TzeC}Qw|v8+RCN$ez)K@t_?Aj-V-%@y$?-4t`Fc8kX_to z*NNFFz|X8TADB8^dI}gt0BGwyx=C5VSb)FR;Ia0{1N?mkkF`D#;13x*t8I8=DUTQ~ zJIdh??qS1aM>%zXd%xilZQ}u`2kUaUMB9vVVBm~rqHPxp00e1`NxAq31veL9h^b5= z(Y!Z>9r`!zl5($4g-&*eJ!=Zi1*Ai#kJ1rT`U%~nRQj<1|3`xdmAY9NS_b<+87`>R z;h<+=Ib2X}?jHoU=+fX*2`rJ17uZt$n?_)Hz0|&!=TMSkv|dCbgKBjYIT7))PdG;V zX_`)Vzi8c!kNw=qp4KbB|6Lot1YKEBZ^yZ&z|JP3g zHA4f3OYi^wm`fFK>)uJC4@ zLjolDwDuHw0y5VqxCNhvn94|(E)6yrdzO*uUbOf#@hshR5-s-YCS_ecz_F^M4IW$7 zf&gD=@YtG;1dcWJ8a!)7@Su)9!)2`qKHyxrtY-lRPggFnA}kCTIM?oAMY*E{HqT=4 zsg$MwT8NgDRZaL(7>*ZGk6e6?kr_( zd3=s;@G=e`3ucgV2orqet8>8c1g=bCr#ycKMmg7xV5hmW;fJ6NK9!&oxdtaOGWnN! z{DYXM@lA%mrXvi*7wINtea{7sRldOBv7ny^oB{Ykg9iaStArL_4wpCs1}-qlxq5<- zbI*q#c!N(RNR8Y0G0Jr+(5xq1(|OwicznzU0X27f9WMPu>q5GPC@$AcN~{+J_+r4Ce6Z=EmD7dP`?c$mbskeiXWp^YjLy6YC*62|BLcv=yhArBrM)S@uQGV7v^Ohj z8}Dz`4a$3)Pp>w*Scz9chZBJg!N1+7*BD)*R2&L4I51aNqEr+Pe-uvn%FqiKPRx}H zN_G3^z~Jfn6(&tLW@#%ttu5)$i$MtxrdBYuEAtk?Ek-iLl%^6}hBuX!F+hBy%BP?9 zMY=lGxtE&^?6kO<#T$p8XR@Z^&B(95JT7zkDm{kZNhdLfyL6K>hueUo?%NF>o5Ol# zEi&Jv8}N4;KA3?MH)WXD?l4@Udelof%*5dm)ngXGP@!u}GM*_%J!r|{g6eY{1vVua zd@3a+I`K-HST-@;5xE06NBJ@9U8~Eb-?qD-j-ZI0x=AVG0cGulksZ20I1V2xWIK2i zF`^p;1YPoRB&QH?ly$g7Ax!?jDChVFh2(|>Ho+QvD#0dl^n%r~|LNweKa&;0d*~#N z;qP>l68d`s{BI2&3;TV*5%$9d4_2RhD8L^vcp_jd7h3B0fZ>9GonoNJSvp)|@%SZR z;9MJm#k<)J7&zDN;Ouhm7uaSugHNTjL`Pm}dh^0Z9%5VDWgWnMQ8!Da_eDQO(-G4@ z=_aL$j{`^K|7h@_3MW2bh{2VK)$s|+AVPyrC5EKe!FJ=v?J8bd3B8 zEkyJs6GgmU_;i4O(cnQuxz7N{4}Zbnv3NcU9FczB;8|-0hJSWt5^Kdj14G=do~*S3 z1LxWntTp#JflU<#pGp>ZcKxKXwwU{#Zcyrf89r9tH^Bq{u5M7)e;Phk;%29th&O*_^m@izLgEHNiqa7HPt1q}7x7`Gc`m8UNaTY)(8e^J@v%W33%`}FX z%0v>2@Fuck`cv*jb!0E&tmNBl-YE7U&T@)RukL?Ew@|!3J}d#pqxILynqq&i8wB}B z!^evM4S0kI9tHow@Imp;|ARw8j(1k+(4$z#H#>rXp#xVgjNshw1U3~Id@2&BgQCcnZ#-bN`NjE8>Hz{jEpQ#%J=kT%6n<>X=n_=aGuyZZIQHFyj zf@TB(0|(E_(FF`ayLw_lx5AI8%ivQ9I+1Ixe5DHP;epCxl1}CD|EAfcRJZnaIP;O-L2HHg_^AgF-ROfscC_g*9;8PBCwMdXRC-F<>^q?? zoWGFhx1Ua8^e1IIe++Pha)QC*L2_)MUu^JrkQ^827a2SmBnS{5)N!KW5^n?!dIpf= z7Y2#*aKOO1a>*3Lzyk)(wL45fx#I=4Si|5`DJ{`aJduQt1Bz|!uy4QK{mpu@?1J6r zYCbOYxXhau*+Z3+zx#Uz;$Q+=shgB9EGuii@GRYcUt#!I%}bQESE;~b27^kOsFoXD ztoAdNwFu;FPq)nQiTY6$Jn*-!4O#WW7t=V$$|dT@G~kJf9WJYWVDNP94(fN&32k8V zv$m!qkfS{ir)&k22*m9l0R(9+EyNGma!Um_mu-lttZK=!U_^W6vK5`gF8kr#YJuvD z^4qqAyV#BIx$~agHQ$`K-$I`Dt3n5GNt2zSeJ*3$>FuWr5H2=$iEdIhx*9mP@p6O5 zws~QIUuy8!7B2#hy*PMcgV++h;q?kDlh`2k2|eXpJ&6s10|w5O3pSX$SYUHA2A|3x zv=1`w<}>eRcIn@=6I@~6Cpaf=PH%^VqNLP+4E+{f5)V*Gm~v94RoH^KIhdfZTp>JJB_o?me`z-p{k`oWUH-6g%-R8H)rvEI`0o?ys;N7O(Zwe6ICL)*9y-k6qdxt6qf1N$ zwL*hhU0q4AfH}Y)6Qq3QmKiX#>dJ*+!G)H<;OY96m`4l5m> z^Jfel&l##eggl=^IGEAbb(1oq&ns(B(*8p?n9G+9ADhz`lr?kucio__K=&1+i_Pha z%G$c;-*f|?Ck&sM5o!g8$-yh_aWFApXchixGr~Clqi)ys#Ejrcdoh)-S-Gqk(ME7z z1(!A>3erIA-XT+m3$ZbPAdPFX?r|Hs0BNcR@AQW22-IH9Tv<$s5+S9S&^ftezeR>o?f1r4A$M&1UOFa6bbSZ4mO2hQO!2$K*k`a3)skJ9&GuxoUD<4R zHrtuameSd}MQ!cv8>qT*MoSAF7G$x5lx90faq9=}U1cP#3l>09&}J<8rq+WGrnU7S z8hU)wosR(OIQaPE9cUO(r)$3mL}3JNvran669DRQ1a&f-w#9L#Kb`4KXZq5ah3QOB zI@6WTbf+_&=}ak|={>n)Ff z((WMLM|;R&ho9g&)ppRSr^2T0kN|0#=^*vHx7>H{2VHAA&N#z#qt*z9FlKa=%j&*e z47GXN?gX_26cF$Q)$e!u{a(L6==Vqc zp3+a#dX&?z_<@HW+2TiLE}sXYUtz<#4nGer`VzkbK)cdUNL>6hR3h_|1H#^aS=q~BuwPSo!t{Z7{J8Ty@~UztxOD-ame zRo~4=4pCiSPpNy|FS-A*0h)L07%h)n9K3E*UHN?B%KZ7TLi9f(v8N^KU`^})q__oTXp%$vS|Bm(7!D=uD$NgwYS}{MZaw~-gw=e zH(s|%w>Kzr-4>UWlV=Is+&=bY%3V zft~@bT?5?vv35F5%GD$uwiiJ)Rx21Z&_O>7zi9+`#nQB4U zf=5+vPpS@}sCkzZH)@J|v8qh#s&S`K7w_KmNF}1F)Gwh8Yn)eMI)&+~g=rkwWz4oz z73uQK+N&@>*9aZJpHhMeP;tzCq&UXJxd_a?ShTG%NSUw{3Yfl_DRz@oV}Gt4O8 z3^A8NarSU|=+P}(?|EQz`P?NJFS+Q7%g!rbmw)Ji*+aGAZNral&d@e4S+Zm$fBCg- zXfn(OH7M+_1Zuy(60*tuit0`_SCokwO6vyN#@3tvS4S_W?QgB@X#MbDdD|l&u>RGR zuY!gcD>LvKcOrjHn6IkPazklB*TCXg?UnGxv7Mvk;OtfPdf46$+g$5;OI}%KJe8MU zc3!TO8s3c)Dir1r6=IL7d<3JYqEP28iJn>*h1~;ca_=0!1@NhR4h2E#H0K>MfV7eq_~~==0l?8cSVS%eX@LzW`%s#7&HpM+O-w zS?6FtEJ@Jr4e`M`#wTmnT0x#7^YK(;V% z&Y^P-@896Z_Kb$|62|tbYK!QiW*5o0I&~ialZ+5MOr{FIp0pu=BJa@q7A`no4&C&7 z-|lj!Qdy45K;Wfe1bD%M=FVoAy}{sP>5sW0sSJKJkH z!1SmX8yeS~8`es4;m<=f+e|dssXFa6yrH|WKI_8U2)ei3NOU<#L}{l@rTtGP+7F

BMAF5_5tNnre1! zn76jnwKpVP3!tcZLO#lE-rQLo%cR3OTbOrg#kOvsx7#ht2Nn#3o!gFQoN`Kqh7ZWB z>7C(djW|wH%-<1)v4a|3Zy`8OiS?HnK6xfY?xC%8E4IuIiU$J1Qj#M4#Z z%%MMpbJiN`Ud*Fxy%@9vhQ{rh ztd)0GxuCFC_Ce=l{!S}nthXx>mVK#1ps<6wV#U((aCw<|y6Wj||Ep=dRIP?)DW83lT3b%` zeL->kNWwLMT*w`KN3CUQO268q*oU1)8>8dp9Yb;0Jz5@62npv00_obh)_+g|_*Uci@r1^VM)Or*)-^J$aTH3x40jUCV zJ&BrRo5((Vs`hM3+7m!o;f@YgyJQKMu-C5!R71^$tcD66`KqJ_`^v6BEHA?Zzy>M1 za@n|ZpSG+`UY!FAIy*bpF#%;+?#s@m-_B*`m>3@_KVXk9sttgxZLKPa6qgSy{ais0GF@6?Xh*Rt<^Qx$vR1`o_rbkc#km!ZU$RZqu&k0~=0?UOo0no@ayu-;*Fcfy>%PdBHLv~RJ9jK4lJssuEuFN- zgHOYo$*WrTnnqS2o4TYA0TlW$cA#bBpS5(?+K}46xp4MGm2_&kVJ{cIS6y2!{OKmi z3!N9QFO{FGQDB#f8MgY7 z6b?OpCN=pZDf=5$>ckUCzXB-I_G$37I$JTh*4@-m^I@uN2dVvQ!rlHT8d7V60^J$2UH4yA19g9c!xqH~dnopPJ@w>y_2MH=ul2+;HRf9SJA1;z z?ONL~Dbmt{r`dZdw5-}l4d=WjeXXwQ*jLj6>!FS_Pt(7q9!YJ-^=ock%($sIBa%L` zGowo!^%ueppL?p#156{}89gGN-LYtoh-VIKPwauMcWu3I*QyogZkdL4+mNVNEWhH4 z!E={hzI%H5))CR$)9vYLTeK+LGh=IarzG6??PuSj+VoQoetf)Ha}BHomnraQC|S*$W<~G)II~SPcw`?$#&r?OLHce z!{#4yNQGJIxw##$PNHL-1Yu*a#=h6^xV}51PApD35kPJwI#TnX;67<8#C-h<(5l1A zqm#{&^wxS0yaC+p7{bL+@1yn{xK1ggNuQISOh6WUmS^Q1+?-17@!Z zFmU#&00U^R3NVoNssICOuL>}*_NG9+#H!aAUZXLTene6);nf05M76*YL@ltoTMMjC z)dH*OHNXuE+{+ktW;k^Mv!Oo)PdzGc=$!=KHwk=U3ZCZQlY*!DcTED9r{blN%CpU! zd9DdpJ8M0hN*#LB%Uy#~OGON4dk?nkpX}+|xIW>d(4Z$B8aPn)NSzBr+UJ)~7o}Y) z0uo=<6c2KT+*8|Gsj56EI(RI3&N5Wy6{`{6Ya;epcwBj-`em1jD)(tx@2;HIdvtvB z8G6k=8~q;Po>1@#nVwXHz(hGc(5rFcdwAS!&*oE|^B|7qry_}3Tk||9O=_CtLHM{| zxc-l%;rGo0C~AeEpHlRh04 zV0->9msWv#hoZ06I}``?q;<%msrHeE{eNtxm*Uijg|!-?ty-aaYNC2Ub=5@mgX*q@ zI!LFOLyX%MF9lDk8Vqh1ODo*kPbTzn7P*jbBzC!+ze6KXq}?6W-C3({t?7j-)k3wT z-eV~-*?d($?GUC^lL05f%77C=Wx$D$GT=l&8F13}3^-|b3f#cUH`)@Km$bQAFSxH* za#15K%{gedGqtR+=Iough_ z0kn792P=T~diyyEu-UbTw>FknK;1d%l@(BT>g?PEYOUvmYkLj*%ie~a-Z(F9ueArT z(_9tU>8=Xwv{wao`l|vv4OW4j4y(XUi&bE!$11SXWEI#^^U;g~0tvlz)D_@neLDkT zhmU1A;%0q5qZV|mCUm?ebhIXPq$bo2vdT8NahipCYtz>+<|KU!CfL4VZUS`nt8ZW& zUIF8y4W}nCvo-e-gjET&)cZ7VjfWX?|7KBpa-kPMlGA^+H^*AtQ&&5$RqKiC3Y$Xy zMb_h^ofSGJV6%#^L19%mD^R~-WZy;?~H*QP6Qp!7+;+AkvSmrDFO3YJVeM#Jg2>Q`6)RG;Z6 z>5y+?5nb!550bIA@rS*pSR48iy|oVc`o{^SuE`(b)(lIh`1*jI2?(3I?g@xaan!N^ z&UA(sZ{7DqVsn$V)mjLy9JY@hygIRjVGkl2j)jHCsvbW3^uR!obj((7RMcQ=4-0g> zg_C^lLoK{FTKi#vHU#W&_1`2N2%vC|xR(RU)uUyfo)?t#(p6$WwT>t6_u{yuhv-Qa zwH!<8NuvABTifuV5c|Tr^tn1;+RTf0MFIP2c3wRISXR2FBIg7|$ zx$wo#C3vc+*$zS9fB&Z4e90<`&akUL8vQ}{_d^B@cF@8~BVaraS8a;$){I=v=y1s0xg9tkFhW=96Bz&NiL@ zSTcCUswG!krf&$Xy7aPKCx6}~Zm}!m-j4|fD|Iw~b2w!}W!VvPn8g68V`!0`PpiF| zIzGH|DSnovkgqd<^c5)?T+}df^M-+rd57W;>)Xp`3uG6)jO4yJccyN3No98z^(Rur z=PsXa@+t7Q2)Fvtjt`xd6RQ?X1Ql32Yq?9Lxo^sHWLKpb{Q29HRCxt%L zGp;;*0zGibhZH>Zl9ttvcl-K6xqyeB`a?TH9{fgMo_a(3=ojrH1s?kOgol#?C#5~~ zgLXhidr7GeJaAIrq`(6`DdpFx-PA`4UsB-6gL2SO4*kH76gVkx=z)_0Ck0M<;H2;m z@(u8N1a}tF-hSFfGBW+2i|_@ye|A2K{*_d~Q8A3_mzBdFO}_Ct%T}MatbEyEu5;$Q z9(m{kk8ai5CY#ESZr$yv^nJh|h|z;$aG%mwDE*<*MPl@XcwM2C{Ih*J;L~UM^mLz| z=F?~T^yA|56P0_R(x_oA-??*}3%OK_)CuaiR%M{wsdSCf%}QMveSCAS7*v#*5c($3 zPAg zxZZuO4$cQ1<_Z-SdSVJg{MUiF7@qUgH|yw?s0xr=D3X_Ip#NGa{4Y`()!7&Ae#5Q) zz*Ir#Q&io@ROt7DQ4BK3FIM_BDf%&`-O8UVx(htJ&nthv;BQg>S4x+N?!T43K^DIps&suho)Jx;Lr$jO2X-NDsiHx z{IM?yXDa`qQe^xd6~gxTYr9T%^XB+3z}B}MbWkBWAu7B>v_BHV2LpYUmwUtItljFM6tN2#;|{+NBhGe~VImtv7l^{IIwkN@uIhCklSG z+WZOSzbU%2mDe-048x}TRp4F`z>tCZq$ecbtvnUHRp~oCqYlsbVwD?FISg})(x_o! zhH*0t@Bm2dcF*W-N|y+JjS4g>y+!G_QWf?Hf1w!Oqx48sv{)&B=khMApeIv73l-pM z4)QG`zd(6f{C1_+`WBSDgA}g z_j-mu5Z$SwdxPMS(x{;`!`Q3@?+n9hl=i3~)`9cFI+iL$6xVnW(SV~xM@2soJZdOq z7&d|UsSq%HhX|kN8By@nf|KIjU$2xF9qB84k5WYN4W-CjUuy0>nMbJ%xYoA$^97Ic z^VE#53Cn=Pxb5@KP<@e%2w?l4o&Y1Y4?d>}D2cJ*4nODW>9KkO2M910s`|7e=*kcv z%TNW%Ru$bD0yvq-x;vyEb=FxRxKYA=A%kKqLjZ>NsI~aSE}S3@m^@WcV$Z!pxost zU*+rQHOd`X$|98S7Uki-tMGocFVSZuCTf%z^}Ju>Df^Ye0hvUNW7!gQFB0aTg`uu7 zU-Gpou~hJXQJ#JrV|9&ZOIqtDe2Lfjx{g(PL|oTsjS>&}60i3qj`JnVS{g^PCF+<* zL+k!dC7EAo6_R*^=Wx7Ir{nnZ&T<-$3wWb2P`**=1?tCDD#=Ig@9-s0Py^^~ z|1JD40Ze+6R<6TS?W_Obu@mhf73(J7M0!onT$BRQhwzks2Nc z?`v#K)j-RBBslJdAd*j=+hZOz1paFUhc6Cxf%kL7B6Z3ir}P~vj~gR?dyVMn;ir_| z0DWkAga1OH&B8N|RF5=cZWoq`iJ9{UN}p8Txe)($hNC{}D5&!fq^SQ#)U-7`e#%!z zxu7yZ=NSaFglwe5WuydJq!;^?$c8-83Mr8Y>FbqVqjZB$x2ki%=PSKU=^H)#N~Pql z_vt#Nhbn)A$KR-wayR+3Q{`Wx{C4F@|JK7dD}~RsN~!mk9v%YrhkbsY%7g#0@+j*% zpC=HZ{2iX|2*IiMaGxIL)44u9)TeWNdWcUC_US=Bo$b>OpU(1WyHDGc(w><KC#XQLWU!Q)@r{DGI*OlHU{0@~TeZTVb*9HIXOP*#; zt;ZZAJBsozlO+?BV|ysYEI&M;KOw4nhNy_1nG;YxVcUgb{zk!xrWp}L)0B%J_AiR^ z>jlRcpkFQe$W}r6O#KpwJpo#U;NqAdJlyvLm=6S(Kwx9i9~1C+%nJNP#(>Zue79X) zdq7QKYJuRdjex1Xf`FL?g6BfeoP5C8gw%Gz2?%Khf8v;lg}9vw2Vr61A5)%*2mCId z;$Fz($VhRSq&Qtt+%+kVo|LJAlu0HkE-Sl3a`nxN776G&@d}}6*|({rv{Il4>N9gn((wVwXw+L=J(? zN)0-#R7rqtAYk$l2mS4biYibd1g}&Y)$c41N#;G=OHTalX#|P5pAUojT~&DG2>u0z z-%*7}jNo5r_=ze!QUw1Z!;e+r5hC~(8(wdfRJ0EnfDR1>iOEle0JyAc&U>@eh9VK#-i^5y9vEFoW%Xho<$h=GaY`s63-e7 z{8EP>t;Dkg0)Ljnk5uAW>3|<}_@PQX3lZ?=IQ(!Wp7jR!W#Aieu<_|7?*N(C5YsC> zMd~DzLWP&AEHf$;mwAfRsU}asTnokJo+5Q_MRH^|yy#t-VcpE~meIaRb)-smw7nNrYQP;zZqq$Yy&9sX%;(YdU59f7v`f6Z@HWw1 zD0(8c9}0Unyjs(*IGXpKRbEC>E^*PHs|YK)Art!)@k&m@=EBr#PmNAJ<;Y@l}1hRo1LEiInZ;7>3=G^uW2qW(xArh`lXT2 zET0QGmzbP2a=qB^Humx3#4nLOA!=*zC|XX4HdA0)-mjD{GvUy(ulpLG(1?3X`EjKm zQ_6aNt5W8KTa~gZeXG(>i++R3zg6k4ls{AS?6tj6>Gzew?~6*KI%|?Ozoq;<0qjEa zXT05)C9?R2Xh)U*iqgka$4ixtD7`=_ZKQ5u>@O(g&z)^l-IV*b^7M^x54w8==ez5t zD1BV%mjzG%Rk8Zd3ixjVVodK6(Wvj}x0Jt6d3I3Vsgy08M=7ko|1|XY?t8z*{RvTV zqbmEM?pfG=N-5rj81IvwFWx6j&trmh!bAUAPfu+4nS_2UO%H$QS+oawVoC%~yTyMz zMPCp9%LQk_@qp+CMMA%57cuEKm8W0uqrECWnksMoq5P*jf65WlvPh+V(T}9)>k0Fy z=d4sc#KN@WEuv?^Nx3J5r(TuU+1FTpO=qXd5ldrGcPgddl%G&}43B*u3=g?tXtam+ zvz6)fGMwVuz|Jag+VO-^c3~(_e~8`RAv}7ezJC-P`NKEj&rB_v8`S#}LGBWmVub!Q z3wDU{7DwKnB8QBX0-H*3r}o=Lj+6?Hyf;M-H_#Mgp@Gn!RQ`Nls~XdnB8QB130&_H z*|&Tn*tbDuB41cR&T@uYAb+XniU_Gi`?#i1E)Dp1AH#^e;je~ z1c`Zx?ynXxa|9{ApA@IAKlId9>fW%CTk-y|1cWnV3y2s$s$1CC+quDzLa!6}%>oZ8 z#b-u!T?_gov^o|Wj#T`RC-QR5ycDYJECCaPB z_)1FT$K#T377RQ5hG=ZMs_X6T?vC5kDTeHGF{gZvqRk_th%7$#EoK+0D63Ay`g&+e z3(@FJH!r$reY;}u4Zo&EnztAWn?>*irROXCs+c~e^c70~k5V2?FezZ{w<=|__$R^N zsr+}8zD?<`l(Ln^M8#Gc6V)k_2$Ro*@Ly5-X5}AHs>Ygr`J)+UkXK_*6OJYD%YB_u zsi$UR>sc}EP$TXX;oqwO=KAkS`Ey=5-?-l@Pvy*D_QH9MUK^wLi+~NzEh@O#GsJPw zOZ?0qgeRqfh>w^|#^_-Y&=LyNi2-xuxbHUO5QgmQ{~kuo$rt&aNnYda=c@dE(OjYw zk>BAP6BQOFhRFQNfW{*_FQOAMiA|g>{_hd`eM;-aOJdgX0{7*=P|w|-@0FrK6`xa^ zQMn!y_H`w!J}k(MV)0|8ry8rFN>=%|coqa;ga%PdpU%;m$M7!?NUdM;{2y0J+`%8_ zGCNJF{xaX^VbNS*ZPEG2xGjZ+>h)srKTc!}>SL6C(pc>@laDt<)Cs~BcFoQb4VK8} zI+n}`o2jyoiWeh2YFSv-Rx1nUtKYY>3k9g+5d1HMF~>PX}z~xwCYO8w3z{I?Emyf#eq- zDsA$Iy0Knp*fERhbb>Om;^PH=hrmrrZ&CUw_0AqcwhoP8Om5fkM{0@wS<`P76%xJ? zX8QAK9I;C|gQY^Dp^KD$6q35m-ed$91|>~Kzz(5l)(4f+g{XPh>f`hV(`EIv-h7Qn z+4ClSn^LCv7b<0Id6UwYD81U_S+POKl8^KkKK+SLnRTP~KAjMpm;U2d@Ads;qGl|= z$g_+}{YDxuPmgpam%ms9^brl?(=P4nz*?{=icp9qW3I^Xl;kG0*VJj0CUM;%?0 zMh?xh%hJW9<^KrgSPRB z5z}w@l2EVj(zj&+?-T`HLX6Rjl0Kd>FMKS@$1?f%iwtiLnQxH{D+B@s1VcT?t7Uk{ zW0l9wqPo7yVNZ0-uzvz{qx+8S#HtsQ^Fx$DT=XMLUvV9(Ihc#bh@AE9i^XfZN|64o z(swGo18#Ml3sV03QgvWNU>;-Nqhe)|nQN)*Pj}=fp&t?1g+ilgo-#om6;iz=?D@2i zEQ$X`DNEviRvNVq?M#IH-xO1qX6f>v?h)M&jB0!YU8MGJ{8%Gy!v^V&c#T4p+QSjm zlV0Oc(b=fb7b~F&*Y!C8KPmVPs_rr1n zpfqaTxzo+q@fMV-)*pJdEeJe|lkdWXie7h8KxjgT+r{*U%Gg}p(LK3+BV}qrXN=*f zZb7A)uwunb)`@3S*V~_n-`x0r3Qd4Wf1~2W$c|MZjAmN+uAqpU=|RD61@?O$3sqFy zRe}A#9t%}e+*yJBrN=@Q6^BQ&^)lB|FH})+qypQZu7LfcVMi;lJPra2Ra6|Wz&3d- zR8euP0^97dP)QmU*cOk4O46vnwt6g7l12rVh=W!^B{dM}1uw*A8~YHq%ZylgM0NUG zbx8#920_>wWI1CFudXW{PkllrutlZL5SnqwsvrB&s;ANvSm|O4c#f!}b8@rVEc|Wa zf!j3qT&KVG6}PBJR6z)Rsj4EnJx2|HO6izV76$4-NwLq}+{&T}j96dXuar<<==4+y zH=Yl3h>M2*Koqt+S=Zas6A#L|Zhh#}yd7Xl)xGDK&wUlv=UtqdpWb9fMx=Vll;A?sqY%6PQMNs;d z!_0Dpo{kN4?uKII`0llw6~-|y2t zpZ0qELZt))BT5zC5N_;L75bNdzNEH8_iPn8W72Xp7Ha;N-r@1+-&EDqQyI_PCK48t zEGKS-tDZ#i*Q8JIHFT=t>vYd1`f?gj=vbCuZfFTYV{c%N{$db89-nOYz>o-gMAEcCyM zmKncaESTYWO@bMoMJf@%Prc#SD~|{07F(O?bv}u}aYtO?I+a|n5}TCbN~5Me8zPBg zFB1KHN=#U9v6|W_=J@}jnC@1pzzaeA7q{vHZDbqfF_C@Q(0XkwaZ1Ex1XycDOT`+| zDKXB(34cMQaKbne(pUHtM?)URGFK^%fjo|a6vsh|BLRPT@vEoJLaH=q4cxFknVW~=j!fDH}OH0`j|?cFXqJ9 zq!y8DKQ`$}o~12O^=rkFI7dqzDtQ(4sS>8s?E)`TB?K8nM->|&ZxI+p;=UF3qVqw_19rJA>*g$+yqx&fRcsy{|2=gDpuv6uz+M)-a}`7w9AAi4QMF-J!A!&P%< zSuB}5S147{zNF})P!y7=eyFM_PwpwY(iL5p6kQyO+Qa?g_^#N2Hlc>iDlkteSW?iLLvHV&X14SEiEp1j0jI59K`k|@7xRR~bf(kFyu7tv;g zdj4`(mMzVI?YWL^SHkwBz!s9Ip0~HMMQJ%j&vQk)lcFbwqL9d`bfz5ocLX_G;BUz> zy;F2&DSeMpwp}eusvoPW3E5E7DpylyQqwa+O^`(O6IDeKCq@64D_Tm5o)U_h#5t41 zU&Ag5Dyy0a^6R>@u#59ZDP&tfnq4*Mp;-#q9*|}^oI^?>X9c8bkuyjsWJf@nE;u`# zLe36IlXip79;J{61*8dxb4MxU!2xL^D1@&LMY$sa;;&40`u&L>F8KM z9UV|FbSNDf3#f$w^&*E_n4o$C%FZ}3lHyW*0d>ABr6Xd2VShlq#G$$q)G-0|Qisy9 zuu$sQfU@&UJcEo;#|6{{lqx1W`ngjBX0>6G$6L8)1klktIQvvw~hwMxvBgBIc z-sq5}G%^>EZwe*(Y?28m%H;#{&7oupSq#W4LF#16}5&c zy+Z=(T948@ksftuK&=5)#AlxVDK&R%UE^ z6V?;!{77k3*OiI@3!f3>1~K4obKR!&0+D?bvZns9X3E1~5x^;mrdU7RqLl3gt#b6` zk9cv*{b9P)9j;692we*Ebji=xCD*A-R3xskXF4&&BlTH1HSJz)hE|e&mnTDyDx>+VqqzjcRVxkkh3;uS;D)mts+uLY*%8dR=l2 zxJQPSZjLU+Lv<<4)g^zJF1f>XiSpYXv8W!vB98a9&M5O?8M_oBDLU^DeYHok zP7+o7$-1;XLzmJiy39OPml@C0rS&vjT29xc`B}O&4d~MNY+V}8(51etOWhJ(if8Il zSgK3@EM0Pgx~P)PR{6~G3#gn+LH}ix3&S>RlR&+GOF>2II%AA-%@cZxQr4;FJDq1x zyIb{4NwA$|G$MXzgflTi&Z~%`sK=8o17>{GXT+|kQxgs|U&XX~nl~`eIk3pMs9;kc zr!&%!;@GZ)Z%eB77JZ>EsE$?QV8zHD` zWAq~pD(WwQxbngmhjxv*3=JRN=`-|iG-T-C#PCEyHa6rlknIW?nl>@+F|Z!qks=!p z8OX+Wrpbo=-V$ZTLI&33da`02DMhX8)xMb#u~cSaM=CR; zUFhm^o~{%XFH^D7g}OAY)+Kj=F4{bd@!Biwb+nR6p)Ymc8{f~GP@(n*b!mH#E~WSC zGV^`9%y>wb*7xhu@~|$=kLc3$0bLsZR+omq)204@>r%H{m*NL?DLkr6{xMy0kL#iu c7bLa!CilgOVCAT4EEu*j{3{>zs`-Wg2N8|}mjD0& literal 0 HcmV?d00001 diff --git a/CPLD/LCMXO2-1200HC/impl1/.vdbs/dbStat.txt b/CPLD/LCMXO2-1200HC/impl1/.vdbs/dbStat.txt new file mode 100644 index 0000000..0a575a4 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/.vdbs/dbStat.txt @@ -0,0 +1 @@ +RAM2GS_rtl.vdb diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.alt b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.alt new file mode 100644 index 0000000..9569a06 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.alt @@ -0,0 +1,75 @@ +NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * +NOTE All Rights Reserved * +NOTE DATE CREATED: Tue Aug 15 05:03:45 2023 * +NOTE DESIGN NAME: RAM2GS * +NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100 * +NOTE PIN ASSIGNMENTS * +NOTE PINS RD[7] : 43 : inout * +NOTE PINS RD[6] : 42 : inout * +NOTE PINS RD[5] : 41 : inout * +NOTE PINS RD[4] : 40 : inout * +NOTE PINS RD[3] : 39 : inout * +NOTE PINS RD[2] : 38 : inout * +NOTE PINS RD[1] : 37 : inout * +NOTE PINS RD[0] : 36 : inout * +NOTE PINS Dout[7] : 82 : out * +NOTE PINS Dout[6] : 78 : out * +NOTE PINS Dout[5] : 84 : out * +NOTE PINS Dout[4] : 83 : out * +NOTE PINS Dout[3] : 85 : out * +NOTE PINS Dout[2] : 87 : out * +NOTE PINS Dout[1] : 86 : out * +NOTE PINS Dout[0] : 76 : out * +NOTE PINS LED : 34 : out * +NOTE PINS RBA[1] : 60 : out * +NOTE PINS RBA[0] : 58 : out * +NOTE PINS RA[11] : 59 : out * +NOTE PINS RA[10] : 64 : out * +NOTE PINS RA[9] : 63 : out * +NOTE PINS RA[8] : 65 : out * +NOTE PINS RA[7] : 75 : out * +NOTE PINS RA[6] : 68 : out * +NOTE PINS RA[5] : 70 : out * +NOTE PINS RA[4] : 74 : out * +NOTE PINS RA[3] : 71 : out * +NOTE PINS RA[2] : 69 : out * +NOTE PINS RA[1] : 67 : out * +NOTE PINS RA[0] : 66 : out * +NOTE PINS nRCS : 57 : out * +NOTE PINS RCKE : 53 : out * +NOTE PINS nRWE : 49 : out * +NOTE PINS nRRAS : 54 : out * +NOTE PINS nRCAS : 52 : out * +NOTE PINS RDQMH : 51 : out * +NOTE PINS RDQML : 48 : out * +NOTE PINS nUFMCS : 47 : out * +NOTE PINS UFMCLK : 29 : out * +NOTE PINS UFMSDI : 30 : out * +NOTE PINS PHI2 : 8 : in * +NOTE PINS MAin[9] : 32 : in * +NOTE PINS MAin[8] : 25 : in * +NOTE PINS MAin[7] : 18 : in * +NOTE PINS MAin[6] : 24 : in * +NOTE PINS MAin[5] : 19 : in * +NOTE PINS MAin[4] : 20 : in * +NOTE PINS MAin[3] : 21 : in * +NOTE PINS MAin[2] : 13 : in * +NOTE PINS MAin[1] : 12 : in * +NOTE PINS MAin[0] : 14 : in * +NOTE PINS CROW[1] : 16 : in * +NOTE PINS CROW[0] : 10 : in * +NOTE PINS Din[7] : 1 : in * +NOTE PINS Din[6] : 2 : in * +NOTE PINS Din[5] : 98 : in * +NOTE PINS Din[4] : 99 : in * +NOTE PINS Din[3] : 97 : in * +NOTE PINS Din[2] : 88 : in * +NOTE PINS Din[1] : 96 : in * +NOTE PINS Din[0] : 3 : in * +NOTE PINS nCCAS : 9 : in * +NOTE PINS nCRAS : 17 : in * +NOTE PINS nFWE : 28 : in * +NOTE PINS RCLK : 62 : in * +NOTE PINS UFMSDO : 27 : in * +NOTE CONFIGURATION MODE: NONE * +NOTE COMPRESSION: on * diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.arearep b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.arearep new file mode 100644 index 0000000..b2ad5bc --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.arearep @@ -0,0 +1,21 @@ +---------------------------------------------------------------------- +Report for cell RAM2GS.TECH +Register bits: 102 of 1520 (6.711%) +I/O cells: 67 + Cell usage: + cell count Res Usage(%) + BB 8 100.0 + CCU2D 10 100.0 + FD1P3AX 29 100.0 + FD1P3AY 5 100.0 + FD1P3IX 3 100.0 + FD1S3AX 47 100.0 + FD1S3IX 14 100.0 + FD1S3JX 4 100.0 + GSR 1 100.0 + IB 26 100.0 + INV 3 100.0 + LUT4 122 100.0 + OB 33 100.0 + PFUMX 1 100.0 + TOTAL 306 diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.bgn b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.bgn new file mode 100644 index 0000000..38d8e8b --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.bgn @@ -0,0 +1,86 @@ +BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:42 2023 + + +Command: bitgen -g RamCfg:Reset -path D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC -w -jedec -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf + +Loading design for application Bitgen from file RAM2GS_LCMXO2_1200HC_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 4 +Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. + +Running DRC. +DRC detected 0 errors and 0 warnings. +Reading Preference File from RAM2GS_LCMXO2_1200HC_impl1.prf. + +Preference Summary: ++---------------------------------+---------------------------------+ +| Preference | Current Setting | ++---------------------------------+---------------------------------+ +| RamCfg | Reset** | ++---------------------------------+---------------------------------+ +| MCCLK_FREQ | 2.08** | ++---------------------------------+---------------------------------+ +| CONFIG_SECURE | OFF** | ++---------------------------------+---------------------------------+ +| INBUF | ON** | ++---------------------------------+---------------------------------+ +| JTAG_PORT | ENABLE** | ++---------------------------------+---------------------------------+ +| SDM_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| SLAVE_SPI_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| MASTER_SPI_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| I2C_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| MUX_CONFIGURATION_PORTS | DISABLE** | ++---------------------------------+---------------------------------+ +| CONFIGURATION | CFG** | ++---------------------------------+---------------------------------+ +| COMPRESS_CONFIG | ON** | ++---------------------------------+---------------------------------+ +| MY_ASSP | OFF** | ++---------------------------------+---------------------------------+ +| ONE_TIME_PROGRAM | OFF** | ++---------------------------------+---------------------------------+ +| ENABLE_TRANSFR | DISABLE** | ++---------------------------------+---------------------------------+ +| SHAREDEBRINIT | DISABLE** | ++---------------------------------+---------------------------------+ +| BACKGROUND_RECONFIG | OFF** | ++---------------------------------+---------------------------------+ + * Default setting. + ** The specified setting matches the default setting. + + +Creating bit map... + +Bitstream Status: Final Version 1.95. + +Saving bit stream in "RAM2GS_LCMXO2_1200HC_impl1.jed". + +=========== +UFM Summary. +=========== +UFM Size: 511 Pages (128*511 Bits). +UFM Utilization: General Purpose Flash Memory. + +Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510). +Initialized UFM Pages: 0 Page. + +Total CPU Time: 2 secs +Total REAL Time: 3 secs +Peak Memory Usage: 253 MB diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd new file mode 100644 index 0000000000000000000000000000000000000000..c492e5d51d9f51a342f152faa3d9b82acc561858 GIT binary patch literal 197895 zcmeEv3w&Kgwf;%p4@!BolsAO}Z7E1jo=vernxrK*ZA#Ko5HS|07=e_hhzJ%H5fKr& ziueLWMMQjDRIU%MA{P-+k&Co=0TmPEUlB>F_`>%5zi+KsduI082aulHRL=SRCRuy! zHLo?Z)~uOXGke;!!NIDUNB=uFGB>iTc}dNp?%XMl9QnGcT-96F)SO&ho$F{>a$IN4 zVfmWs>Z4n7%a2*OEDvm54!_;_=SBaXMi#l;g!aw_E4tfTkDHgT!sB>BPV~rXVsmM% z&{n0fHJP-v#EwnV))6}7IJ1#|9 zlUd;!sc^ayHIhQQ5;aocbR}w}!s$xXNQKjtsF4b%D^VjAPBXnmDy$9UtCq?0TEV6h zsFi}HTewyVHZjGVS}E9sG*$|h?m4wmurzyXr6rV+zPOp4p-x&N&D}a_i8OcXq$Sea zt&<9;xmzc>rMX)t6;3m!PAZ&cPMuUZ-5ctp!bRnk3Tt_Ng){qky;L||iF&DUx)SwL z;dCYHGh4VmXklN3K&U)2kSUK0M9L$bM2$|QZ)x+AHm5_DH23z+YMNI)8={=c?I6lT zUrP3Rj?(Crkb|&Yw44vU#loaMGLy5D&f+xpP#9!mP^MLrjG4u&Ft-}r%S#S zmPT&_j%r6P$x+qdQRJY`s>w^f6@Hd{E9@-!R$4lG8x&flD=u{KT7|3RYn82%uZ3MH zjlNSycUw=(vhJQG&C7Zgws*AA`r7#|Z+T14>F2EOIj8s3zMePqp1xW}hh00*Tz&Sc zb9?(vo!+vh@08wid)M@ld_qg-k|k|jE$z)6LN|U{`%+PbI!G=%y1gdG%h0g{%XtEZ zo)c#^>F6`T;^ie`K;VWaPoODq@HqjJeB!KpIt6K=9Xvr%3erduq2o`$@N?p<#&iPG zO#XdC`n_~7|Gqx`URu(>uS>s|ru6S?)9SgzK9rh+B@6(mg8Nv=-h_2F-W`mA=0YOm;+Fg?r(h{pPh>6Mjba&Iagn#dtm2_8; zwt$)G&ZOg?k6-j&SnA)W`aSG=FuP zGNG$ATiA3QOkNk&UOH*=+EqSbuBfVjxoPI;P?$td^G3(QUL`dXCIvNfjheg{UIp)6t0wP-Wx;#btbD)x_+@SLgfS!9 zmnOLiR+wT~)?2X=u}7Dn7XB3{BFrmB3*(B>!n9(vFsv9Y+$u&3lZw&88$%}?$u71I z!$zFcT}R)Mohz0nEh?sy^)v8N{|vk^AOkNP$iNE=GVs|v$ZjJYD2sTY zqhv8!$H*eq=*+OVC^|M~;7hPThr$f{5-iY>FN0oKkl>Skkli75d`qa4j-V5}415VL zxMj2=?&$cHkxmIN=y;VuucENPYZ~d7IzEjkLTfj0=!6B?!l$E9Q5rh>6r)w1(mCpA zQ%tQ~FQP6{dmUVgx}FX##Z1wWB?Dig3uJ2<9ZZT-(V-**U!n^%l+Xn_hGe8uf(Z># zF_XrNbYX&xRAGXRw7|sf_C+!)T(+W%v&ONf{i~sbc!w&~y3x8E_K>{O} zcP=a7$F!=>VJ5;XgxLs(ARLD9 z3IsBu8X=ERgHVgW4WoL5xd=@N^AL_ecqPJogjXRPiEtD`Gr|Id7KB!WHiU%;ix7@R zXh(Q8!eWG_2%QMa5RO6ULg+?Vj<5pZScH`b#~~b#@EU{@5MGOLBEstsdJtZZunOTM zgp(0YL0FCO282@)-iXkP@Fs-Q5Kc!p1ECLL4FcQgEQGTW&OtaA;XH&lBb<-GhP?pc zLWH*=T!e5j!rKwnB3y#-4up3iybIw{gm)uchVUMQ%Msp-a0SBq5UxacKf+ZAA3(So z;e!a*Ap8fyhY&uDa4o_|5UxY`D8k1OK92ASgij(|k8lIRrw~4ka3jKJ5I&3WIfR=K zK96uS!WR&3LHHuVtq5O2_%gy*5Wb4=p9r@hd=2622;V@s9pS$azKQTHgl{8!2jLEc z|3>&O!uJsFMEE|!T?qe!a5usa5bik!r>JdE%Qg#SZ$1mRJH#}Iyr@GFF0BRr1q8-#v@0fZ+Iev9xV!v90qfbctn zrx1RR@HE075S~F8L>NNYi10^*KOsDe@Mna-Ap8~KZwP-!cn;wo2%8W#BNSA;tE%vS z1j0y!Q3#_E#vqJE7>6((VFJQLgdGqjA?%1S8DS@coe_3H*cD+4!c>Ia5T+sQj<5&9 zo(Ov(?2WJw!oCRmAxuZuAK?Im83+d=9E5N%!c2r&2(u9mL70PZD8gX~uRu5)p&B8N zP=ip5P=`>D(16g0Fc+Z-VIIN}2(Lt#kMJslBN2{5Xhv9o(1Os4(1x%OVG+X72<-^3 zMp%r{fv^N&DMBa0GK6Cgx)8b%mLse{I2K_g!f^=4BfJLT1ccWjoQUu`gdT*~BdkI= z3E^afQxH}oyaC}TZ$>yj2fe(o zyQd*v-P6;X2YXcB`9FLCo&_%^yBMoZIi;trCl6)@FN5U3_3RgDir_^mxwsG$lG35A zf=C{Z_6zVkMrA|02Jd{FxX2!lJ`vEzX_d-9uBA^au4J56T*vX4+@4+AQ#&_ivrh_L zxMZ?3wQ?cT_e7WOldVE~Zm^E?J1SKf>B5t%)(c*IN*qcX> zJ^j3MdsdzDrk+$WdeH>(PADRlPi}7QKJTP6de1#~HM)FtoanUPd>-;sBXLWmup6Yy zk(|By%$|IMmLtxkB_HMz*K2fdO?6$&gK_LP=r(arlipMVbj>73 za>glbeXCA7eKqPFXFa~Jrmn8>wbj+qVOR^X1EGI&qZX`KNG$X*ei%7&(8vjP&RRUk zZzrT4R5u@Yy{UNHH+M=9C zXE1IF&sgBKQfmAehgD^=J?`~mTNZTn)HcO=By1A2BtV9+WsOb3S78%-m0=s!;z53s z+WUIX?OMI+lnao0T*xtJNcl;&R%r2OJeIb>vbua+I_W)e?48k}&~3F(WYiLCb*N=y zoX&V+!J4^oJ*R+|VN+yCP}2R#?b^7@V($_qse|Vherx%MzsbPn(fIXsT1ev7@(+KM zoR)gI7UEo zrIO(`9huh{>yM<92va0+b`sbTNq2xaymkYAIgY`wN0^BL1Wj| zW;OPN-p08N8OiL}*R|&SmNln$uRb09ATF{b)|3%xa-uRgQq;u55BQ zHTbkvQ20ZItliOf%6!Zova+}|UbKUVaeGclxWE{}-aMUduoHCF-cIq30x-KcG#`R`deq8=ZCUCLT7AM=7AqnJVW7ee6r3_CSn2vEz-9a+#AHL-IFF2zx`nq!V~&@9#pUMOW5FP3`a06btR;P2Df(K{$6P0UZ7KR1(#NI^>1#^S=Sd$o5$W@#=&`xfn6kP_Umep= zNcb5SeXP1jmm-e&qQoiA`;=p*D{+eLo;Yq%B~J0&6UTi|iBk;s#3^Bv3Z}U2iDQkf zDW_QNiQ{2GiBo(YizQ-q^Qbe6OLW+~$J4x|FvQu95f|vVEfUf=b0JOT4I@|+O{Yr7 z>2#`&G@U9)Q>kLXS5i%P$>tN9;xvsg-PfB>n43))_r%fgzD_9tOEK<+Buw=|BaC|> z2~+*g2;<&I!c^Zg!no&=FxBsjFz$6EO!YY0-nQoRUOO9Lu5-r=)QLPiu*$Or@-+xMCIPiBl;HaVq8UIOZh@#|=0}PJhMe zCZuum32CbJ64JQwgf!K532EGPLYiv1gfwnAAx*VgLK-)lkfvHKA&prpq^UMbNMptd zX_~KcEUHL2-D#;%ipR?_s4PnCB}8&Oj>n>k2=%a3m?CsCCTM95q6b1kI^E^#ETXhy z5h3mSv5UD6OB4Qn^rP;M_LjDu>YO;1%0sTJu_a&MDwvTV{@Rkx*0y;qEh}oKceO3b z&zsS?lt8rr$K>Z7GyRxq{8^Zvw{ZHxYW!K$-8HYZy}NkU!Q4(-l6Xx_X9 zKpxt{Kdt<;0B;U$;h$FgnNG*jQA|xMHezw!09VyftP5E&B1cgALsf3XF-CWcqZghXsN7wfjTBsqdFHJ=TaQK@VEp$Mwy}!NaHda zXZ&%=F7f$|UQ(SzAM1FhRO6dFR@C$?S<$gvpGSg~E@d*5wH}!pwX(I-cmdGLw6Zxt zk0u=AYg{3SuXPC`szWnDhaI!B)t3zqzR-B6NlJ}}+T>v@QuUGe#WcxGzS!8>6 zm2Ibb1KDnVxybf7FWX~ZKC(T&BHRC3+13M`C1l%Ob|Cg+dfe8tlUcHTvzKL&?a%vX zk?q4&ww*2IWxMWWW0OzxvOVGDBilPvWcyz%+ahkIWLu7!W{=zMn!gO2{1z|EBHLf^ z&yrb<%66U36av{^@NyZqcl5G7>E$EalPj|QFP81+v&n0p$0pZX2C~NOFMC-Q+5VD$ z7TK;>*{&~=ZEus`S!yk99#*+pv2K-GPkX6LX|gmlZ^;X-sV%IouGTfR>iYWndGnfO zC9O;gYdd>E-|6Ke=(|(|eX9$4v^4PLfC84clX7fd$5%Cz^Dx#xv}y1Ho3tC`zfFKy#XwzQOc*hARu zm6)aqwcLKVg90jmQnY|D%?$J;coB~=YMl2l)b%h z@AdK#?tLo4{jU{nx8GdC2_?1Q9SV0%txmHuM(R&_VV05l2LH@BRXeM2;{<=`VwSIN z$=8`tJsbCH=qF@G!*ynCZWL}W9FLm|C*sz^Nw~3aGHxr}88;Q~idzb&!dRV#+X?r; z&4hd5R>FO7BjJ9z>9~vV0Ng`(AnqVM821m(%6&u3^p4I&?Jd(6=jY8kIzNBb#m$Gz zy0{gg<&XulXV0F#7$)`6)$?Zo9bmber@n13%B>A6cX0fgKcju=vChM-rHx)~a0i-) zf9CB5u&49bwyqw1t3Gc^7COFV_^rV{-!C^}v3RKMD|*6t^d#o{^p}as&`C?hZ_PQo z(Nk?}__l=0Wcrx`KjMe)8uVgRxK^h3z8ggou+JtQYBD8%y?+*p40Yxzf3S-X2&=hl8ysm)$Xr2RY0iCe`cxVyP7xU)f zUw7N``3Nu4AGTO=IVHL zhU$$-2jFti-@9mfLAyjP_({Y-JuFlv*6+d6m6Ie zZfnll1>WaU^%l|A9`7p#cx}GlqjIVq6j9^0}>tVyqvl${zmn zBEEd520%1lsMG7w(-r`(1&*a(zw9YK?IQgp86=EWU_DIWSUD|ivdVzOrkvuu=~ znK{bOuBeBKdMJl_C?4hgp_a6zzak~)`}k*(^F3A0aWz4>DgZfe^iHmC4y97ZWEm{O z+4=Jfz-1J&a11^)Q^*dh2w6qQ${}PUiYC)d!A^HFc*=D8QYS>QHz|e4&z5N_bGFP? zH4c|sZYp0NilrMYF&D-l8BUWiI9|K}Q)L+;WenAc^0pcz54S<`6`Ar|U6J34{FXz0 zGq%(kMOb+RIlWG%-{aysS^7;=;`@>wSr73esTkl7`ezwg-{q7-@fun%fgT}R0XM@U zh0fnEHwZ0qgnv_ib9 zHn$~T>+S8+LJ|Jw?QOsN_0ndtp^@E~IY`f~NMU7=F2^9PMs~DdReHhtASXISPN9jF zjW53qAJJ*b6rFh$(W!_|IYehYx8zv{skJIe_(DOr=)*zCZ|#(S zarYCUY}$MkJG-sng!SUq7vAi7A$rEJ*nRVfn|Uy6*h1HMj~Jc|iC&Ob|$#yjm%bmvJ* zdyK$*t$bTUw`XV%+4#Y}k4Ju!3={na-a0p5ChxZ=CWET(WT;{CmEpj9~ z%Jj;SnN~t`MXyx!N;&k3u7ZU-$)xcNzo&cMAeO~j{j=zf1D&pj z?@*y5S>jWU57&whNflIJxtvbFlA$cu8Dm^Z20W>*bb2vrIzeQYTZ8Vt>;HuNFj2eBVEdn%L2)iFmCX z*PkYn`kh_ef~kclfMMl}dbHCDFr!{Aplp=2SF}P! zD{LLDkgs+t6UEbneBdI(o%C@1AyF9VImG2&4Ty1&UVj+rjDvXHAKo>|KKig)_g|7Z zN-wR*V?`dzA&(h;X~CuC$$%;Y_a!Phb+KO>*7=ibRA^T76jzlDrW{nad_c{bd~-0x zsZUI`9WbX^JhqdSJG^WGZow89*nYLnT)4MriEf#h-JO{NeN085D*{~(fi7O6s|y4= z?T(MXM z2H~q3y+0;vk*+~(1D(3Z_QEw@HOK^gntv8m(V?oMKK2{nYJT#WBEOnnzOBE^Q(@Ez z^mWI7IRFmW?*qyO6Sh0}Piu-|&(Y?~lSd-WaS%Ur{ zFW5rU=AT8-FLHt&Pq{g9u$!Q`mdB|BckT27h%L7XJ`=9QIR_!EySa@!Io}zq$II>= zPPIVpWm3UwBB&9z#4>nk4zpmx@h0TQWeWLgDnecn@~tG~$+}wVfJ#-p7itmmW&T;> zT9eTB)=m0 z<&*r-0oQ*eRh@If34rt3P02kZHQ59Zx!=t{i`>s}av$#x(*4Fxtm|4JC7(+KTn*fE zx&LU!1b}iK%e`AK;FKOP9X-elEbhf%58uPiN=@amY;+ zf>;GF%_ktd@44J3{Z2Ez@TN??aC${ARP;hQ^n$Jg#Cjn*CLEdx^~qu2v^8+0mv%~j z)q(z5q`%!sf4nou9-*>$169IJd^${5)r zOP_~u>@2_gIP<^gfNs{;o3pQeKGR0|HJOrsRz>nFlD~B%zoxF_SbjlDzCY-nIhI$s zFFZ8F4gg%$_wufvc;WGYa$QjQkqmiFUQ@K$yi^?q36Zl0CbK?_SsIdq5RGh zP|n$%TaoOFWS2v-xpWrq*5&IcDXilQioqA1?-*Ij+D4MOX`AvvoX+y0$i_^Ax4_Vmx93=Z$D ztv=i-fY|kiD}CNRp!oA<4(|8SLfG<^|JDrq0H=PqzK_cRZNDE*K7!H(|LL6zkK@!o zG1xP#^l*Ou)?yLW*T=ZJjyT3?y%7ryv(RBiF6!>mdlSblu3ntS=Oy)N48A^@JdAE> zOW-kjFj1*Sp`3BG-{}L8kgBP#FbA}>YLGGw-{WVL>~)He z=vc1LBNw)GDx@C;ma2}be7hoUiWKh1^KZ_hTIvI>TZ@Av( zWzeqbEZ>J1=Vr(tKeMEVcEeGaUvQniFu9R4L++p;-eyDNg%!E0$lZ#6rQFpgyIkr0 zubL7g;~riDMI!&lNnr66cJ*Ea&H1f-8{o|uA}A-?=`sP(t=`{3ZC^(z-$v4g45@~&_~yoC#=XOF~dP5R&Nq#vX6I|P)~tV=4B)XF5a9Fx@IGb{Pjr54fdRlSVGoWTZ* zP@*={UnySgM`y8*ck<7Y#&?}siM`c$L_N4lQm3rtT-46G<Rlk}PlQH8@Iig>qI5tmj}L`6lELq%jPcvmM|S;b#6&gVtm{VG?eKx*s*ZfW&V z>(v8|`KrDBvn2On|19d`{Z4%pIkz=>Ti=$v%J(J5-)C4QSn}q@)Pdfhvnx-zMCJ(e zh+FAaTLjNM@3P$)Chsw=bD7sV@AX>e@`~1}Xq~O3b^LW(8Cs_<*-lf3`bg{4i4Nf% zJMrRr>U%p?v;2FB@n8N~w9f5L>%>lVG+OGskG&Z!R68`UwtS^MYl#6y3+Fvt*2A2~ zR@>Fj9+z;*Oz4G{``%}=e1(%`U2vvq(q-t%HyrUj!%oKxk!#x$Al@zY3f?U`aiPMY z2|DbUm92gY01v@l#LCv1WOD#-YLf@bkdMSCA4}vbqV(~Y*8*EDU|!)vP54loJV;*A zlaD2NMelsP(XGq6nwMx-8MCs*@2ZSh+2yxYR336Uzr^rLFIFHRu){I~&Zo69ld(htfX@PqPIl|i{O zD3?Q!bt({UTiYilim#ZSo4B(Uf5y23U+3TU~Xq5*cfW#a;_Y0w?-s(GpkqXVDUusg{`QEIE0~b-}=>_lIHZ zvo+;2+mFatE#Rjq5)I)l+vaKk@4$HBJ;4u~q<+XrYQzlH`I$KXw8cY z>M%9uKVo8jtsjs->IdZODg$z5KrY9CTx`xaI4_(Gb6y5kKT?O2fVsiiTRc!7m(mWw zGQXsEzJD(R^;u4P#9nk9sAF?pKZHSpq8y&Azs(w`Dx8Lr7ilz#S}9)Xe~ni(GGkcf zpC!h3{Ie*cZ#zYl;Y{e=o~VVmxWF~Z@~re{`qb-Pnpo7=NrEj(a-ov`P|#4ERJ_n) z{|zSR*E>0{%pEFoha4q)>n`@c!Aq7*5Zpbrb7Ox(4Dk(qF3v3jF7}siF8;lYA)X6# zEp*Y1Cgj1#uXw*Tq-z-a0Dano`cr=J{)`{IZ>$X7mBD)}4c__G`hK`tkk2O$LRq`< z?zn96zCdG%tMA^J(jkZXXBoXe?w@7!{+JuRW9LE~h->iE2u@Tue3x%m;HV58!vn9g zS$lS%V@Kf1Kq9D!C=qvpZon{1C)1^&)b(Ro4b!++A`e^ zht8{>{t_I0KW_@)CO^o3!4L8`R|fgYAYYC_Uiat1d3L=l`ujO}czs1McaPWnPD`nP zss338>sJ3PgY^WbB4VdHo}3K_YrVjtd?#lg%NndPQgerZBeS0qEa1ppmfibpeW>V* zrbuq_isVaPk=$BQBo#$c4n>l2V!(gxqS)%!FJO8t6KbHjC1wQYc_kutM*1@Bnf|>f znNK<;6T28f$&~nbZh4mT9>`EK&g7t%Ar=?-bsX{G_4>wn_F}mYx8rX`&GUj+ZoT-^ zieE9s@@21B{?jX#uT~UGMX{7av8aU-tu)joD-9WY2(^iklAfpB?e&A`kKO&V7%5-% z&!RuR;`B$6pJ8y`h-MJY6s{rmQCl%*=B_c}Z)&5zO%+CH< z?3HggB~#>v85~sf=OSpWl*5tgi3}Yh9|7dGpwW^F9T(`pAbRKDVsYg=riQ-l)zE)? zHFQTs4OP@oIn+?b9H?GYg7?jgCP?+7A9QskHe62jIz#3_yZUE|^WXkibjlr0rxZD7 z2Cm)o+Mr(1OUTRdh2eX$bc)P!;1MM&BxbhoVkqvna^0kC=QXp|Y|A*^`JQQw?|QBA zeXlj{tZ0pj)+mS8$S_{2MaXS)H_{n;UqT6mQYXrw#By!om>H{@3%x24UG*OSET#Cm zf0oq0=2T7Weu?GU20um8O=GGW-4)vMQzT!`QZ=n}E)GwE6+zp2f|lj{ z?1sFo6AaEPDYZ&pH9IAPbDRvuu8neEpr6OuDZ=s{M97@Sw&3`nxEv*-D0h*Ra~j*y zR!+C)pPK0Z#ECwZ6@Mn6T!DUnWgc6Z$ChIro3Wst7t#0g*l2MqpKSUCJNFP)Pd&%HhrygRbL>`6o#ILPb9SoVfy)ZBOK0C5qHZ~Mdb88!zmR)y6O+mxCoKD~c z+Vhs={l`aNP&xdrhgXA@ecniro_8VlN5On2KTghZ=Z5)!T)E5Ch=y2txh}J|K5^E(xtBB-hY8BBD#agAsYYovVOZ~IN_@RH6wC^#kQtU41 z7g9NqqRSxHJ!q|Lx!+HwR>88V+!~kcvN-DndZwIPEoIdzPncF2@LJ_buT_3q(JB?K zvX!(-g9vzuot6fX_H0k%dYS2DY86ScSgS1ZT0`*_XqG;ujfHpas0))n-3>Zi-jOl|`czFQWWwKXtvqw9o(Z+UF^+eSTNbJ{9d# z4(*e%&#UJ!OK2b6u2Jn1t-@CA;xz>|N!9-TSv1MF{Ih71Z<;14@`?;rWvNKGGgH3f z42>CzgrBHN6p3!qU`h7Hcw#+mV)}b0rol#ufR&F$@}rQIZ_jMuw`Vduv2;_FBYN5` zxiOhrL=u`i#Y><_=zb=Fu{We#y5R3~r})t|xqSDz-<%muGSM8Pn2)i zRxNAq%q?4xpKBT+m;3m#=GNBsdGdGq@~(F7Ao5}P^!85ZIhfANR&;bw$mh3qu3UO( zYghZRZS&_I+TGE%va5M{+x+g1&XtF@bTltnHotS}^w#F(&6Y&x^kci)7S8L0XTq{Y zM7A$Qiqkt=32Ro<+n099qYzB*IJUK$FI_6rbGb>m(NZ+`30{q*52K}kuqbjHb0a}S z=#ROvF0RsyVhJ3%WZ_^bLxT7EoW=1^ERKJ2Mb%hiT~YOkYL$&NamGO?$U)26m$tXk z);YXLo!7|Xv@3eluDSiuP7SGcvMud@k9PV~(oW9~uXZYSfX+9FaAr2tPtZ{HaYH3* z`~Myd_2;Ca{xZB8Dr37x&sJtO)ct6vx>Q5`dr8z^lZN`+@M@?U(R}d=y7>HLHq_71 zP_=PG<^R2gsJ|x-_1y4ksM?H%Dm_L$fQG6`HPpYCMExUas7=GGq3SXkN;a%ACF+0C zQ2A6t*-p{F#~8IaX{f^RYN-0+hH8}M_{@g-IU1@u)lhbP@!z7MU`J zL&*#(v!NbpU31>K@kDC5-zLfBE)6G7oHlV1HNX0wnnoRceE0IUuD0&>?)gibOU18BCf>r{uG(Z=(kA1F zSDWmf(I&EopD8E5kT!{CJ&1n|Kp>yV6}dCT%i#c(uu18EsN}cKN8ZNi=O)o^SN? z%k8R7c1qf0=i${Rdl$FKT=7E998VtWXwwF8n>| z*MjDF1*U86cB-_dBrP&^c(us>87)$J0{<(vNTjp6wpSU!x4@i?OdDP;azI9ll%Br- zx(gx_jqF`>x6?rcUsrN1vd8dhkr^2+QhM_KI9nu^k?nPwxM$KLdkwD^IWVI|N>AN? zgBEED*N3|j*X-?Vj<|QyAo~oj2019BK}yft`_UkC;|AGIEvd7NW;96Y8T%7xkZ4W5t8P18LOCF5kQu|PL1tw%Na^YN zZ_yypf_zu)cG@5ZCJl1X@M@6R#SPL_danK?8YEhc@7i7$84pexWajW{kV7&Wr1Wh4 z|Di#mrTDJe?Q{&mw;J6c2yS#8dU;yW-o~JOoz?Ite*!cs0mj84Xf;s{RxjB%Y}!A0XJy8srs8gB(7*8srrj z4N`ih{`3`_!S{b&-f|}~>v_a~U2B{xj4KgpIK}yflpXuxBYK}G5cDh5=kTgi+ z@M@4FG8&}xJbe%&NZcSezAGAxC&jj_P4&4+i!=?d7I|e+i`3{vl$o3ALtU-MEIB$H zMDp9K(wdjF$PvSmSMz%;t&>|Q{wo@5-Wzr(^hgXZdDx*b8Pu2g}w_@Rv z$nwPj`6@M12%0h4BK>G|;Agt?I`K}X=Txovp+ z>V&t8hZk=%KHOPddTRT3;cescczcLWyr zw&5+VGrZ&wa4-i|Le!u005EZ$b-gtyVgc1Pgxylr@UT*BMq zhZk=rWbn4+%&e-arK@vg?8VVBcU$+{*Cf0>VR-R&Vg_$Z&djPt2yf$l8@Ro0n|}M+ zgtsRSFW&Bu!P}A(v#OD;SWt-PWx)a9ZNu8vC9LfkUaZB9ndv#Ne$F*h-Hsw_<7ruN z2f?;s?ducPt{Psf-LaUpH6>?dRinw;Xi~O(n;W+$C9FMpc(HbJ25U=B%BseYwb7hx z`8J=E;X-aV-(5YtSi4gOYfH|_s>YJF(Ufd?zIt2R2yaMud+PAw?ampzEx9dMHIBTE zrewIuVq5d}jR|jihZk>m$>43t4YsQBbA8)=u0@eW_WRSpA62Ho{;U( z*Aja-b_BQHZ<{`QX2RLCh8Jh|&ERb5>DZ*cg|Q=VaPVN;F!t<(vF8jg#_pHF*pi!M zRXcXYPCH%o+u9}J+=Q{`4KK#dEoN+O>8aRc@xJK{y>EikOWUT;zBys-`NNB~3o=++ zdMdWlkA6f)nzOOykXx9;#j^YcX)f20%T0b)p)h#HG1Yv--!z~W6beI=m*f?Z!#7Ih zr<8bo4q_~HxL1(WqBxv;KXy%_u>SXoGk9!wq42Xa9L~XG+6#qeo>QE`lU=&G9EGjt zWWHUb<(>`jeYxDbZ^-3#{jGQa@umCi^Rq%>^Rtvs_rtx$f;&IJq2|PGx-h`Ob(__W z;*L_>roRPrShXQt6c_xF^g_C^x!j?z16_z4=kf^4GTzaJW!VAz_-QKc&M4b!!RtqY zvh0$}&HFv@VS2kN-QceRx+#i_%Cei{qWZd~kK*pGW$C{=NN*1*EKwf&DK1KHy2g!g`@8h+4AMKm)h*=948=wH9;jvRUlhbWNa+T{ zG9T>t9QLa@O1J)|ATIhW+b!bD;o3I_!t&*nF3Pt~c@@=-(uuwnm8Ds6>kbR@UEtz| zedEpP%%R&fTa{G{mq3v@i%fZsk2R+&;^Yp}EAL#s2CIz5=}DPfT!U3^W4c4ZJImK#mF1Xj z@*$ot21`B8kLe^0S3ZL!J;48EFbH^@@e}TtaR4qS`V}( z+SKwenEbP{kT1V{yYiy{ZY>{q)PJ|~MR8ibr>=txpxrDzgUM&ZCHbP=1~(`VCOeq< z4xJeC#ih4OagrWjNl$RvZc@H)piK9>@(HZv8))(Ak&b+^dMK=XiR%GetCi1SrPK0h zzHGN=keAlOV9htAGyVBGAc&D%CIavC$!!f-FR)YpyA9!JXjs1%KUiEj_ZmK7he;%gZFrG&JRO*X#kY4{HO)su5`p`maHxIL4 zrTd@Agz&}53Sf~BhtvA%yLE?oJ`*OL;jG`Y53AnLzD-#26kqYoP98TUT?v{NR*WM9_y1k2ZzK(*s z*x}qe;w;}I-8uy-C;C}>{9fQDoEN>4Ai(;Uvd6C8CJ>D)Wwa!=#=Nd)&U z!43L%GN!aa<~TbbJ>P)`&myg6^wG`s&f#W4f9gBZ<#H3=4XgZjiko?e;ud}(mz#Qz zy;Ix;D8ue=z+A+=Blevi%jNc5k;~aT;@*7~(p&G}3GN13{{9_iGNXZ?ysWvar=_E_ zWpQ`=qNU9pRlrr{<%54?&pi3`(|USOAu1>Hpc+C)>x2SkzRY^w1+o0gG0CjQS;&P| ztqIDE!>j$=$n3VeS`w;BOdI8q^za|-7`&VqRZW9et2hl_O`N?i6#j0MloCIcuutu3X)+U40&fLCknc0z)jf_*aXOKt|Xd9|;~G_)R#j>B4t zcyQx_q%Ro{=J@WlpXNUl^tb~QwfUls?k?7dKb!De+nS_r-S_4NMW{P{mNPZ6O;7r= z&QetWZ61a3oSYfjzd1?ErYnJTyi%zKzw9e%sC#^kL{A_KVOpV37!?Q%#;ncbHT%sM zY0YF@gz(5%i2v-Q8V7W3g~HQ+QJliSq16WO%)s585%-CJ?g@=MB%Rsk!QS!*jIqpD zVeKu0&~ZgL*K@3VfBgu0C>TXLg&}B{!fv5X22Nr8KMmveKOD}%6UHH~8>Z9^^qk=6s~HvOK%8Q257?;uO~UZhEpf?!dJ%-Cq&+@Ao=7fe}~Qia6+cS5}s9 z$ni?!Xdatalgjh&w~rJGzxku$6jq)N+^9I^2ga3NPp7b^H!w%(SkKL?5g?(O2l|OC zgNmEd(LNivQG2K5A=2&U^JG0?Y>{P2pqos^e0E8qJWQV~ z_9~`P(|_VHk22-)b+6P6^%GC^D&@z+~qen{ggjMAg^H#Wz(Km52*`2CL+ zr?8_tycjq5lMI|IpVkwSbP0Of5lW}9miY-MtzjNRiaD6|FJLLMykhMAJhVIbx ztZ#^XiPKQ>`^AncX&&{P!D-!0jr7jLjO%(GaRL;&END9 z4fTMJ2s?@5r)9(cH=~Rz98O>zM1Jn7$^rT3sQ$AjW1x6k=@dp~$o{q%_q#u!Tev|+ zVGQnI;jjKv=@dpufg5m&-O}U#O;de(o2DWUbo0L#6sNG}yUD472=|cES-#Ap-y`e_rqD{=6RL`vJNzCP3ti!dkw~-^{>0pg66&HK^jWPTC4qH&Ju0iza0T-!?s@ zaW}a#Ygsj}m6^EB-&CBHMQ{%|oRmdw&*8M7LF}L<+66h^MCW2N53E?23_I4}uJ#7x zNG-flBF6i{wCf#CU}VO|x;m)j)mi|>_0`liN(M_cYbJE{Qs5hgBe^X{1z{JX!Nl z7+s{^=bHg@K61{=Mn!&n9D{Hb}w7z}QKBO6@*QrNZ1?Mi33-+mR=v{MiYLrB-56`W8i ztjb`s8+Vhqw?kP;nbGnBBM@EgI_Zi~F=LDzA1zpgg0<#y8|6k0r)HSeXq#WB!wC>faK zg~@EiTYN<81Yh-r+boS3jvJURa{0CYzMvF`>K5ImO9C9`<)j;WJis+-a!-u+<#4Eh zdjc}F4`&Mz4l05?9Q?NLp|4WZ#u+{}LmlDAxudll>kkhyXw-(K&gqAC9DEc0uOSW` z#x!bOt#Mj$+^*`s&+4r>E`e{l#Om$ohA`@By@^A8p}hz0as0nW>1ap|0M<&nxc`lO zzinmJxLPjM5*_H*>lLRka8wnS#&jEg?x(j3E8Rxd;UnCPIPTxTgGZeJDXe9GV!YCY zI2&=o^oG7#OgAt|aYjeOPp8mo1a5dl^BB4%ru*&V;BAxQ6b3z(?f<;N7X?26BId}%9^$-1mbXcr$@WICy3J+eWID@S}uq~}Up11&uSFUabPdXRd zWpg#I!Lw?R@2QG2*!mK&Mwh38kTPR&&cW8dNM~`Ue9Y4s%=FmjSUzi`O$P>swZO_N z_Bl_7J0B((orkS&k}}EnQ{dG>#9-UO!TY%W8uDes{{{U|VC{c{=+~s9ENotc09|Bl zL|maoan_dFw-J}apzGrzN0XG!`W10Qw#t?kJKe57(n%&K;j;vFcl z8}^vn0D7EoLq-mJ51hPX+`fEcgO~$dKJV!ugo+zl<1IR%gfrLs!GR0#XdI=)|Mw$& z)8Pb$nfn1$)S1u>5`ndG87( zIN9gGIFie)(9Bt-gU|;*iIgtz_L&XfC-^CySzduL#wjA&NF(DvvLAGolEPR8c_S3$ zGNn@(bm-)T6I@&uXTqTn())?SY~R5%F_@{9h0O{Fi-qQ_EKLXLL2xxa9VmzJUN#(r zPJD@bPVVXH?Rzs*Kh|@db6HmW3D0$+klfJJVy-JG-fu({*X%695NCK2hsoP}{Fisc zaYKOrS9+dX)=zoc%CZie?562x94@GjWkN`t<$enP|C%byWZ+ns$&OCm1BWT-(?bp? zFmNnjM3>8ryc2SDGU+@lYo+@u&R|(L6&x!kJ?c2mSg!hWrz_}DR+X9FED{knO8kd5 z(eC5n@$*q^(bKt{!BT{oL2&>}aRet$`CR2B!SSBq*u0`H*;Mdt4HQLl^Wi~TgM_$s zkNDj@XKH9{q;d*Uxsj=>U~P8mDw_}YxOFfgG#SNd9HWnMoUJ`~zTy7^Vp4Ei4fcoAQdS}H+p%It5bn|^NoivSW z5`{qn0ov@QWA=UmEUrI4z_?Ik4&D*@>)H$~8V6gMM3^NVqy@pX^t23CO{PW$O0Ryc z@73fM1Z~r0zCDdKcl#-np#lbuVTu+R|Ia}puNRbqQQ|t(mc>`xUUPx_vd2%46G7cLl{=W}Vc4tz6Ukw=g zOQxhwkJ)>Br`!GNKisOBQwyT8n%{@@f&Y#ChbL&aiF_u})!3ER&kp=3VR#c4`Kw}c zg}z9UpC@t>TQ#B|ZG-Z%P&N`*bep4{02Ek;XB9{&xMVx>-0pLCd zdiRdFD#We2(!UejS@?^A&)x|RZ7VqUPH-nWoO?%H?q`ViT?F?|aQ7(A-ccWReggC4 zwRmgqfLn-uz2^bJJK)*}p-^tLcT7#+*IjP!6xaN5&^>PN98Q!Gl#;w7PUT|o3Y7)^ z=Z|efURGZVgJ7oO4Bq22FrhC|oWVPevS|}WBL`E)B)xyiZK|rPS+!_Su?lbUBhu^O zmWBSk;Z`cvPAyC>CzA*Cq8p$Qu&Qz>OrCYS=u4qSZ_-$bdnZ;I=rmyOh_yJZ?a#%? zP%aQY@l=>gAJw=9zY{Ad_rJrX=is+qgk@GI-3D7;a7F9x$;+7gdaa>YM!DR+STQeD z`5GcgN=>2B&tL0RKnm^NLTOj3!5cl*crA>khjc#=1Hg@L2Jeo%%oWRE5!D-ATo;G9 zLSu}Z`47asRdEJWd8@eb(*k)Nmr$(M|g(fcH2jI$@CB9pu|$2`cG zPQN~CtFn*y#Zas_kZR~&zg=IWsEzeLqH#1x3xg?tnk)W)EnuI6xia+3@k(bft37nD z;w+A^!gWr=9e|aX=Ppt@gM~egE=lj3n58_Wbo)4%>1{-j`LnnU`+D2ZU|CTUa~(Bi z6C!P8nZ~vE9IZA5bS%FzP3bH@;w)b)t2CvQxi8<;Bx@fhdx@<=LJxv*zg^hk>Ln=( zZsWoh*HxecT}DFd;y@L1k*BE%5}eDO;uFOa6DXV#Bsv}c=t34_-P1lI zx)Z4ef{mRc6!pYpAF)|c>n0nI9*gW=RKv63hWI!pgES|a}E z;L5>rDwxLsde2pgQ@Bt#8iV1+DT-6LP`Kb-g~I|H;!C zyfZrZU6+#%2GD)*`v#nan}&C`fNwC%zHUt%mudXw4v!;D`d@!YaRytxiM4zuyca-*lgR5t4K=jx8Ok)H0_$oQrLp?MgOR3a2-byAV=IM#_ctDBS+bt2B{ zX5|;0tA~|K#e(U z@k>C4TIm(md{rO)XL(eMCO>e7N1>&e{Q8}JS_iOlR$^5mwU})X$2FdHD_x0J5~rh2 z|5=uq;@BAm&am8wvvizQf1Bc{jOuQK;yD|(s#`2q7>*ea11Eyx;X@L-T+ZNwFe*+) z`|@XS{onm=qQOnDfy`abV3{Rf8^@jTPSkOK#TmT&=b=!Xz#6>wPYZ?r{fN>T%zCeX zPH{@7t3?{uV8=%h;uP*0#!cab&oOTO&YFjnZ~DzpK$xlVHv=~O524hua5I)bsXAdY z_)zTjsT&2_(8283Y*R_k#o1#nW-YKb_%nD4R=0k0i{cEnwkOv3tNmQ*j7L-y$}8iC z>sO91($}tWIL8;_)?-alyDZaN+10A@|0Xa06oyZt5rbJ*SE2COX@$Zav!YoSYzyht zLX1dPBGN93d+hb3wpfaLe0HI5?>)fDI~P~tsH^(@BNX@7kD#}VfM?q0pl&ZyoWkHV zxOg{?H8Ed>p<*Om;^=r)OW-tLo1HKjMOgP$Z>`}`7Stb4TWdy&|ED0z3MK{GZvn=9 zTH`2A-`hLla2E=sE0;T6v*sMevcBC_pmQ!Sz_2uiz*LRnaPGam<1G~^z{z~urq3?00td z-N3_?PGOV_9Ys&IxE;d7Aof3kqP&-M25TefDG#6C*u9|4ey`~nJO(o!yZu99bjll0 z&TBP2g*D%SgEX$iX@br3ODvP|XYiTFA}$75{tSM{7tDD#mowPv%`&r21CHmKht(7R z(edmQ4?Ecq>Z=XG9PBt-t@y33@tur~3MJcrpVwioo%^3F)?rGDC>zZr(*pEArv>Pj z5!T+@I~G8%Lg`uEx9X(RSNBLM&h)*l5u_-^z=MAFXjNIO zpB81P*Q4CXp;@3EF%0RdvzD+>rBMo1EU9*hflkXzab!Kc-NB&!kU-GH9BsQs+W^)oj!W1I*h12WU!Sf&Vze-k3%F_7KNc>v5IR4vJ?jHa_H)R zD4oLSx(gu+_bX0eE#FYD;;ejsJqdKuTo_3O#%J1OvaY`>)o~9QAuG7K_QVwRrzA|4y34#W@7Z)1=PeRcpcSuWMX`-+m}? zmnzO+OP7-4d~q5{akf^8Gn6@~H2UoN@A_rLDL_&G7Xoj|>DrINMZ?3L`TdkP_IbVu zt*8m2haQC%lVU1oHvy$7lMd0p17U&Eq@~9HjH_|fmBmImy0SdFH(Kd2-zyXb?k?Xe z6h;rc7_IF_YlXGv=_;h9jkqu))aTA%E2oyl(w^{Z*jY|~4W4onrnSOMEDJc;>ce`7 z^5RI$QACt=UsGP_&++{U#tu!dfqT5#a`w-_Uy9Y1k|N3t=q;|(Gn;|GXf^|X(PHa+ zErQ}=wN+2DbF~yB0lrF0G4!}E#dKHjK>Jw1e&Q9<1eYJGF!Z>VYjA_&r20@QQhg_k zQr4fivi`)yMO_9rKtcS#{KE~_@|z&DPNbu&rJej#7&jj5VdI>^Sgk-`({avVjFlXZ zU3XMi^B9n__)~i<*?G#INdT>pe&UT(oBDpt8>xm04(Kk>IqSxK{PLZlf-{}nA zdjwPyRwVf|xZ!(X@~Mh5SY~@rZ~R5L+hW{|*=P_Hg+GJogR2Moayf&U-o|}mI>9w7 z&hpp;noJEF%qSg98STF+rej=n){o1lht7RmE_11stxJJ~nVuP5_FiyKUszd~hg#k~ zk2w%CTQM+L==Rd`8BeF6GwW!Gd>uTc-}D}E4(1NYZ;sTs28&L*R&h+5!wh>8|MMp} zw1ePWdk{zd5@&oC9QZ3Z$7f4h^ta1{IP#Y`<1^!uzl>{q7TlK|4*&TRz8$7}N9RJzx777dEV)UFEGR>u15iO52W^d7EH@@43l=whJ}?olq1mqka;t@}$?b7=vm5Z$92@KARxV z_qL9q0{ys$3SsD)y(bnr79jcH?gP`?fy>8!nqxR`F;yNMmorr0fImwkhBlaq>%D%b z#Kbi?N@1S+0qT{IF-!vn193G}c54j4@AVqbEu|aVPqhVg-tz?Bkk14uMY>bZ6 zXmw6<_j_=ngPDTefuZjmPNc!|!$hbFM#RaQufm##4(3MZR-;ZNorh&L?z6-goldut zGYOb_|9P3Fr-O>Ucewc)ms513+k8B6K94=1VeFiO!R(BB4h6=VdrvKpg`;N;e-YjO z#8_Fl^#k}x;ym1nC4P0#&E*UhjdZWlg*ZDO5#d@$r}f+nqgDmM;|lW?S8zOFyB1bB z90no&q)sR+HJjc^0wKUsCC?|TFnBuFQwB$=ujV^+ucoK{MYm6Q;7SHeDWAig;BfeF zW$uT|7|U!%oz-2mvEzZYgJ@$o$?<3HAY~Su^*fUaQd$3WxI2jxrGho(nkHGfd7G-1 zk$8i(eolt_d;IWf^7rX#HHtHse6oCHneIc5-;zgPL(i&H-lXR& zF7i5_wT8Y3ukkWQe9BMd$TIdkp~V09B8FHj2ID_^TmPpVoxs4cwFTF5#wl&O-#d?gCXxp?u_Nbw)Wn(c?P4|CB~<0xP3y}fgOnHkwajatlIm;6LGGLd3dC#1=4;Vb z+U7l^^YDa|P@WqVXE4*#bGV*P`qCvzXXy|}p7Ce-%~=pHulqcnK%E5V>SpC9&gx-hWqMj> zH>}8D@D8s>r(zhq0r8IXQwI~(^Sqtz^r%uI#s?8&2Q87ooFYE>N5vT|wUS=#S`Dz& zP;h-UHPzzk{7$b!kvHd1;Xx%UP9VolbAN;W(@?#?yU-64Ysyys0uF!VN?oi;LbN*iz`+Giaz| zZN;qzGx@VPW3W;D(AA1Fm~NWvQ~Vh$RdwklIF~NzEIrZ<+)NB`4%Xrm6ZAPgUgq1_ zdRyRrV-*j4f&+6&+7kmt(%Br$Z-(eqUl@QKECq1`hQU%O!S&VTb;062S{$0FwiS7+ zUn()1A-I5+RIkORPL&_7gOl;=(X$Hdd0%H;4aTgt79~7JaRzfM@6ij0gJteuDQTV< zA9vGo>xGzs3#|6?!&RhnEJqxvor_C*`r#@oDydN8CV6?eukm4s1aV)VQRCp2M^d3P zK0L{LHo4cnYV7Fjy%v>J>Z@8$@V#1Rbhz9*;rI4-Ozs|t>_uzn;FjIVItLA9a3`G}uAkN_ zoMg(@9maYa&-fLfFhFyj+8@jg4Hfu{8R~p*doEP%9e#`FKxS)|!2kE7GT$Rk=g$4- zyS(t9KMo8$_b-Dk{!3hm10Q!(d+8&JQy8nQzscoZ-KRK%cl$A}_}V}m3`Ym=hB<0A z8A_akcl#a`!QUOu!4qDEUjAjp87%ELC#K^C)#g)RFz5KDSTrs+*RclmC>oIUP*`uw zdgu(r@%F5T&Ok$9y=ncl7{?p9zJHA36ozCT3HlQhr?8W*u^}DSe{k``U8{*hKRyV3 zyEz*t{ZQg!)4|n=_0YL`3U@10^JSQTwlW_IgLxN*;S6p9PTgYQ3FTnP!?n4!$CSsQ zF=jFk7_Sbt{y?0ygUFF<592xetMcA>X`P=jjYm$yxcXY%MFt(t>aP8taa}(}-32E+ zfZ0_qX4e&dcmRXN7zxgYPXdbLV&FU%4iB|>eI`_qv#|^w&t`BomcdeWnP)jR0M?{g zz`lIFtapf*zt0zm`Ex?N-W#S?q_KXNJt$KDdc+t&j5SQw!!+~FDcN8tQozXpz)~c^ z!F9F)3L=-gQj0?se7G}x0*9~JD(UMk^TX32iW=C%PgW6;`XD^B1Kx@4_&2|RW%JjO zzG{XFHtLVoi0e=DR8v?^D;xfQ2@JU3;T+6v_{8KG#{-YnP6mrz`!}VFaF-S1*1Nfp zbPU?qVQ-$O zU2gqVeyq116`b6%9<{6QE7qd|ziI1HfAmu}>plUMp@KV}tw#lmH$ji0NbP&J7b$~< ztF9$NobAvXZucF6UgltFr9Uc%?Y-cxi*Xb7^yefDCimB071J@Uu5|daO7DQS;Ll)b zxv3er!xU#}vt=z0E0^>NS3ctC)=M1!^G6)(PMq;T;-a1s*VWg`Aic+xMQ|vC;9OZ4 zmvv%Xts6ftsxHr0`A&5O)|oDYS#nflUs=C8%lCzybUaxXbPtCLmm#gI1?tthTA-G! z#{|h6>OJ8D>;7h4jQPT-slg6yF82Wy4<=|jH}Dh( z|HTjry!i|jc=Nduio(7RS_KXaW>gr=6)ydtNlqLh2seBQ+U^V%!oy;cxt6o{g1b%W z?7fyMz~Q~%gs!g(mx1xfMZJtGS8E;V#(-HK_j-nc`|XH==nZAuZ>OY%LIKim_uG+| zL)TawmcZTvC+~>U5}Zu%gT=Y``h9=Yp9da(`5&d6r0IWNfVH6cJ8H$BJGKh%J=MP>*5ZtTajMfPXebAB zyIQACx^+#Mjx&Zc*wRJoG^sPnhqN-|kpXlv`|tWAy!mXEc?Fwhxt1-L>%g+nDik`# zF2NG%*Nd=AaRwZ7z7%a|q3{T1X({Y7c<9b7!X5)t4;>&y+vN_&#bwxEi>TE=bv^*0 zzf^I;=2tj2<3E4R$1+{3jpC+#L2+6a#ZCR9;<2t=_5BMS-BTI32Z?K4bKbdXjD6T^50kFg80&@z&&I0JhDaT{ ztrJl#N1KY zp0e#)&$fNkMPs1T4Bf|SWiFz$Uc;Ba3bViE*8xiG3<^vd31uys1I1VT8?HzHr z0!s|Kj}~PeUb5N47KRS|e_4Hn<>Wn^yvtQHchrwrEM`P=19zIBFH1^zCxvuzcskQO zUkz^B7d~TXLjDXs@dDhs`6a~}eC8)H{d`z)23uaJAWpHiEu~dglPAr`d_`gENZEs1 zb%+9wi*MC2QoO?;lzdVaJTAbV&^S!q-UBD^h|?kv`gl?1;Wb>-bb2~e>zB1gGnVGf z(};9Ow7eC@ETRdsfQyvQU~aycJCwnkSq#;ZPG=c}Im=L7UsF9_e8LwHS=02|bfq_K zh(e4_w-(lq@BQx_#rK69`%q!I|X2x{I(MM*+boG%j9DQVn`wI-9!cj`6F!~b)=Kk4=QyBTS zVR3i8;uHo>%0yh(0^FmgYUBoAZ`Kf+VIVl=bs~iy^MwybYDDINMy!3@)>ei33X8?O z+^prD4u^LlbC3(hq3W>tqQO)hcBabUGf^O6xNbAY|d&ZK!O# z%{D=M!1~dCb$YVSDF=d&>`YZJ$Z!oCqdw=_4`=MD1*g<(+8lgh%22^AG4sGZ^o(^^ z`Yk)#W*hHaH8I~2s$h9)2J2|`!hgt0*Y}7+6&?ml&vMga{O6C01ViYiEI9v5T#17r zZxVLio>ZK|7)p=GI?QUp=xkCrb;yR@>m@ZNGUrrosO$YCYiYDF* z4yK&0hjw5d7I)_9hGWi{Ub5x-HyN1bIND!8{`|8PKz!tsyn&Wvf$z*Cxq)a z_?;d%nun;voQyx?mwHVIFZU4*6}Sn%Qga*(z8dE4weoGsb>?CD!qZ!n}Tic6{ZZue%7QoS^#)RE)=rC}OtJTMPeRj) zl;bKf2OB*mLvEv5hTqTlB4LqBCPWu@E<8@`MJBqNvLw8vRtjab_uT(ZYA zA&ZRvSU0uLv>GfoAfK#s2G^jc=;uvyIfI39=xO{}+=D-g-YHFr6W$J<(F2M3y3!de zD*F<}Svu?`cB!Gg7nLq_efe6wHurPN1u`2|W)BFD2pAWFFC6aWMuEV|3|d?Icwjm? z#%Ov-_lv0T^;$rKrJzm~8ZM7<(3W=%p7}edq}3YNU>SF-igD4nhO~tVE)R<%W0;F8 zA_|*Bi_i3MSi$uXdZ9K*=e@~yUgJ^VIB7g8`d*P^XFL9*b6NGJ+84N@;Xi-&-rm`8 zC^GnY&7B;5H@3{4DH;x4i>wbuH5=%H%M7_%kCA^MXi6K^f@}Pnm1{ekP3 zjeWtK2fCV47MjoduxeIf{NJ1!4zXG!!=ae|$mBa<5>|@X7W~hjsMx3QAGU~1moy#3 z#e~#`NQ3tpFb^>-**JK&CvDh-nsG4gI~@wt)+5a0)wX(Nu=EdboIk@&_yYRlS&B1w z$D;y!*1MSL>_k%1Dn~wJlbw9C_kWTBXiq&MzcqB69cx82$AZ!eu zsp-(ivJ$6dwzRD~kt)8UrKXX%o4r(^8}rE9;5mMM!)(9XygxR$BE9V?k2+jC+dyz{ zOJ1q^yFC?DfE>^ZE_^X5Y4TJH9MzK^Cspj9%CeJ}AVh5ISrhl1~$p@&Ns2u^Ri{`Iqc^P5sb}m4 z?1@R|zA>hI_DKJoT7@;e%}YpUuresb4Y|&$`C8h>HO9qN6rwk7(dMANGeWm~!*3P= zMY-A(TwHRbip$2seG3^XxVQwXNBnW`b<<_|k0stsuNPDTQ@7hGX@kd{iZ;U7!=J(I znEGvWpAI{hUD085JofPPmo=`z688wjSsbm9;w)_{0L#PT2u|XHSFjdxxi1#;Dp<%h zUIh!e*c)RiLwES)s{<9)AGnLqlEF`Sbq)THMcuIWBsd4}ilxiv7Ael)G1xaBoTNB| zS@wQW3O*gF_d~^WLwEfD!oCGg>#AD&ebq3$Ap$CiNr4QANW=Z&g%J?Q3ku?;R8+iV z%Al#4W?6drb*N)y9kYJlIbQPE$1n^2qtfaChUe(($Yo5j@BqrPOXyN?M6XPoF2Jeozq4$ z$>oRE@j2HdK^t0^_Rh7u!hHuUnJ+1aEU?z44wGof-EJ6h^?JFTv-~OuH!?TGcvF2L}?Y#vXXTKF+qg1$|x>f z;Ft0Q5r!P_Wk=_DVhQzg%BS(}*aM(Bze>e;cWe+@`=b0A_gj)JA!DacpN@|fjNXox z6-7L`CDV*UzQJGiH{u%Ptx@S3JKv~QQiWx7U(-ts$`#Wquy^L}z8CnV2)uf9=Hpqo z^S+}6euWYPv2*5S#FX4fb(lt&ty)~g9T^GFJrHKxwF+xI3sXuye`)M^`#KyNE!IzR z-eB{^G}@VYFai~cd5B_|K`q2jKJgunl7e#a7jpp5I*4d?k4d)wC7QAQL)y5(JmxDN z%X`Llb!L6E_jq8ZblE=GcRn%ub;dkail{*2j? zc0gzObKD`9l!oIG_wwg3?3fjn)=cQ{|H=A`T}(8Y>fVH+WJv4dO(^-bI}>W29X~><*kwwemJ!QbvPwNA@*bUQl7aI{J#c=5hI|Gs^6Na|i=NPV zi!`=Kuaq~m)G{7_rfP)R$cqp;&gd?liUx_TSoh+*b;QPFaako7nP>?Xt@kJ~UtV{5 zxJX^=@^k}M0T_LGS@IxBPmF+}&tSllBw)<;wR>^$m)r-hM;nhE@@GtczRA{M`9Rf< z_3~#t{V&jnKZ#~c?dwV!X@8{k+=`mgquZ7=_%ddxxNk8pd{k@8YNcV!`=qvGXwIK8 zOUhSTI-e>5`LjE<#r~Y0%0T|iYgpb(GL3m6&3UtoR1EaTBd;-Fd{mmTD`+S>8g%78 zI~Q zZ;W2!=ef^vri!uueiBaiO?j%juxB~+=K`^Z{!Fp^CI?B}CilqI3!)j@f7q1Ko&7@G zFb({R4!L+Xo+K1=_sqP3W2kCcXK}H&ZORdO=SN{vc4Kyyw}`n88TbEuVN)hd-P%4v zJlh{>-81WHyv=FHOQIQ%xD-0Sw`j)HOW)q?c$6Xevpe;+^hX}(PrRU|LNigR{4%Sf zWmPm(mQ~SESun*->`5I%&;yYODt?b(66R}rZb*znFb9iihlvcOM#wlaSJ2q_L`EVk zjljssV_64TIxzUU$|)^og|t4VwB*TZjt^S}^) z?6bIz!)JwkF^e&m6@HhpZA|_5&3netlYf@6am*WL_S($Op^)9}sA$D{AjWs>={r~F zUNzXUPkhlubFXG^v7@0s&bOR!Ja;Zkh>_GYnFBV8cOs9Q^Gtx- z$ss$>1lTLSe?^e62Z7mArGn*`KfBv4N@PlOBEMGJ%oB!SEcWu$WlFnab8+32jizM< zt$!qwf+HGK8lUlCnjM?L!#VoWC-0W(ctdL3xh#cEVYqnhSM-dzXzs-?W5>bJPLFrA zZ@EwL8IQ$i+Lnp2dFm;O;NjWc#ZWxE^{HCz8|U?!`$Aj9UzFKaeE*J&MM1##Y4q(- z^i`{UXBj2{G02b`X*tZusi<D>_Q0)K=`Wq%DnK7(L&@cLds^Qxh#=ZkKweNi^dTx8%uBV@^DJ z^3!-k69!9HE37dKr>#(CVk(bl=@QS#%{t`<9Z%)zTJ76+L*Di0)NIAwmzQ6i$70jB zNyVn`W0hq2p7KWH+w=6=7 z5yp-&O7x?6_x=f`Ys~#J?@wA{Jo#}9c>YR%m=aEy8`ip_Rnq1)V)IFV4!b{0*3Em7 z!hJWw+{69iy`mXMseHW;+P~M+con8@5XQoO!VJ58viv!oDA5#O&=611QhW|Wn!@7f zRO8Yp_uphKX4%~d-6(cWp3AceI8^#t-KmHEDf#e>K&V*WJQ=<*E3Z)U#{*3VVFRMw zNOhP|pF}GYjVJc|C4AbXe16;b`g0M->59+zMugkX%9J#H}X`HLs7V{0*2$Arv*stw_!Tr$a^I&jaH0DQl3+J%hq~-XG zC+rF92qnRvF)L&Hzt+!#j{TbuD z(Ir?qd0sSOnJC`aRYyx{m}m0jjd8|f(arVjxlY(+%2X^P8q1cI^Uem-GH^br2g0M~zkvQGxRZHUoe+{j?mGNOkG2tlHf%P=<$% z4|7p}M%WAK&p4IpiauyxuBUau7}er8y0XA2Y?6!lABo!9!*jwTugu1VG2eaGNjr2+ z2~+F5jny>1OTA?yc|m>?=5|c)1vhpX(4XZITAt)$d2l{Ta&g{M`6d~JMnhdgqeBK9 zFU5k$hTPLp+ir)-7nj+knf%`m%F9Z-ks15M_bUi-V4?-qcu5zv8p9td)$a!-e}O?m z1rsgo$CyX^UFOI3@wU}IfBX}j>Ad|J=E7aPdXdQg@M&rS*P%pxsWQuic_ z58v4ogK?}<(B-@h9p8~rRqs8LUMVPd-mxk6~3sDS_ zI$yxb%SWL^i=*T%iI%J)hZ(sE7S$>8XMEZW*m_?T&G-h)P5Fqr@eN0V z_FMTgc3NqO6h>BS&fOX?gP{azd~9SotUj$1FPQ)e?(oPaf{SRF)e7=P=Txx3nz$vaAE_|~g4ORZ-* zNb&~_--?kIwYp=pXu{H5FSk*1w|>7?yZzN{ZV7|-L^er;@i$B%y%3x69#_HCNam4o zh$$6y9qn%MqIh89fX9tpq8aaTIBGA9dj5=uJ(bS`7&8s#n?I))#gftu8qy0|q#Ly( z3hMc+I*>o-Qre3XDCbM3o2Iht7AggdMp@wS#G;+7Tn3KjbVzpJJA<*!MO^ zaw#VesI~aXC%){2TssmT{AjjjjVWeN0vJ=|b&~+W(F?hDd`7CgenMUCFjK|V$tD%s zU6Grp9gB09kT#96!mXd6+OfV#*&$1c<>v@cJy&r4oo;ia;yCH&>q5K?t0O9n-FpMd!RnPVc)b_g#l8+&JTS$ z?htoM!|?h0(dd21mwzsE=S|bq^pPSQm6H4RY#tYWH$mO?W4Aje9NK4IyG@L zG}LavW(u=EHGGNu88?iqRE|K2@@IVZ#kc|})gt4YP$$R7coj7(;ps>ZEMt+ z-FA7BkeFS#XsJI5F8?SlnfA4+F%Wxu(2i3T|&sXW`@92OnX z{^Z-KsFG~CiZm%2k1r?|QtY0(7>tWZi!Npu45rmMW;IJR;acsJJJ{8TCXC5Yn95qm zHpU3`qU_I@OJd%sVH~fgJjVDS1K8IafWx+rijdOnj z#L}Fuag<(kF*yzH_|)6*+Q~^gcneDY0P$xWmHipfjF~Q9RN>G3$JiwDA=%Sig(`pM zA+#oViAo+i^K#Z~7V@3-UE2k!niGcARdQ5V{^S{kA6teyL}NvsFwmhyV}+Xh;Y5QQ ze-6VbHFs^s*PolaHe*hy9rk7ftr&Ak?TGzEGj>|3@=l`bD>;jDypks@j%=h@!3{P zW}Efmo}*%Dv*{$&x=m?R9U6#ovoVK7FLHby0%ZDXrfCnR@Y`4yEbAz z9p_19V_u5k$zo$_@V3not+9C`)nQ5FB^LaZ{(R?>-IEn9LxpQ>9zD>E_6*N>4 z4%54fr=_u(l(PWk%VGyfdgYu$>dX}wk$fLx{0&Sc6d{MA54FU35#y1qj;u|83shXaaH!Z}TRNU@VUHh|p6ifJvrZo!X&slXS z*gFyG$-KYeA~lGU4z6ojOXJ~5%^F#I*tAYUYZc#vnH@E)lhF{_jWo_0G0bT*EZU5( zhoP`f8Vwk8rsxPXrTiIlrs#-%iI#8}57Fo~H%|HpBC1rjD2L4V2(&P_BZtMvpCmM+ z?d9DQBc(3ovOq-X(6zYETJ{oX^BLUHh#i(DmjI}B{IXPe1$NsV_FvL;kjRg1@=y^m zPpSH`P2*k1Ve#u4rNPCer_lHHMdM@kSI+H zskk5YLuz(57tc6+SQ+kqChrF_sVz@=gT**eU##d)Rlv;+`4Ng#eWPfw0fTpSTe!mM zk=$e%#Ur_Ut99HwE(tQipdt8`NK0BB_Ke*8l+-569`XS+7ojkJ2*iQaHq)*W+E*eT}X zp}f1)b*{KbWwg>QFR-+t6vNu1C75y_ccDAoH%WJ#A?i*K^ADvAB^t|8$D^fN@65x= z1+2wsZ>h1$QhU1{H}vTg(35c_ECFduXLsn|>FD9^Qo6$Or|UJdzi2>ik-sPeSlLks ziD$WsrWt6*Bbwu*zs;zsp(ioEH2)SG)8HGJ(U<*qZWqxAQ+diKIZ@Z5%PjWRp{kKo znwQZNI5587KqS#h8zYx1pwVG(WXwrk-~M169pE5xs7YYD^HNex7H3R~6On7M9Vqqj&PfJV)y1}ey(v7#m=*_px7c5y_VyPifNE^EHC&d%HusiTNnS7rl! zyzI=)#nV@|MvE(&oSULa+K;I_6`GbvZ53%qgW9=OY5D3UxzqH-1<+U0moZLMp?~lz z&B7YBKYoM!aWwz<4O)irTQpo&A?A|HFQFOy8T0)ay|04WlQ4N|U0LsMFw(U@W15kh z50XEJjT1??ie~IQlIpNLpW@{q<0!FclOz}NpfXT=PLF1*({-3A

*QYn1VuS?gFR zcS6#|J82io*lgIf&TQRXNy#%z&?B?r(KH?PwnNDuP05B1(dfpX!*GGqCaN(PILALK zf5z7#j!}OV&Dim#N)%1fUvqX2(=fH|r96PcoCoF7Yd~qA_+kv-^I%NEd~n!X;fyI} z4JZ+1!it(ahIoUYzh!=qc+8=6<^lF6B$N@=I`O7afjlD+w6&aY`S1>hk~k=a(J3an z@#ioHyolxUlSMP;s@dD$7R{KeW}~kV&6q1>!@ET@c3SBD8Yjlve^cmThjPgV2}(uA zJGbRr4pr0Dd3-i!M`>3qlZIaVQN4i33Gpeu546;$#__m9G~6eaMJ>%VZM|l(wcRF-&3j>@N%`Z1J!;tLC~ZFrD+Fdz5mI7BpKKJ)3j9gL^{vEV%6;PxnmH4e^$ z)~r*I|0AZ!%49WL`CDYogg7uhMh{HKwlm2)q4}R{MB;*by^fj($!wsVP45DzTBqtzM90rSkXOP(aktP^`!e zh0Ey4ENU0XJz4!QjYm$m&&$PDHWVum?>E47GAoUFb(60QGiJuOqu1ll{-VK10yGX` zJX!B=7-rpk;=(wDagY2tOb9TAwR;FF`7;m762tO5XH?R6BrH~TN(NnXd5*}!x;IM( zQ~XS>JX)0Mssh9Ln}}oa#yosq5(@ zJNAr*1gw{fhr|EoP)tDcf1|%38r}GFm_zr<3x&p~K_SL(kw4?>z79j`H=-Fwul@zn z7R@>3#QA#Yr#t88Sg~04>8NFVM`7Kyb@?f@t#g}hLtN4#v#dcu6 z8qM+|u)Wi`sHiy85@}U#A(N)D#cdsrNHG5G*`bs$?L)sSY`n*I&|-9j(NMx{vD#OO z>pB|jJpRHRm@S&$?RA)-Mc8A{YrZs|_o!BT7uMpu-4-SZo6B-OD_KNQtcxLa%<^fy zHe>E+_8xv?w!WI-k;zW1sL8e4s!23xA@3fM&w@Vgiz;8t2SNa`E;YR=Yl$&R|i`i+< zRxT*cR5qwF?OL0c7%j?TE8A50Di_{j-g>lVaHRV*7qOS(7;8FkA(@!bU>Mu|mX zn3rJbm6WuwM5tYh#)-w14BH&Myf5>DszH5ec_iC@B%#4*spVymRL|uT&h2ns!uT?d z-Al=|HD+7WQcM04R@9``-!U;EIO~@=^YFFU@I6qH?JTZSexG6w`}I|{rr(34&}W5d zLKERN2TA^td)S@hL=%S6oI!~ytT4hx9He2i6ASg#_lre}1T~8VSx(cqvJJ?!$Zb?{ z@x;+8lX8UJUkNKd#QQ@O_qs$2tm1S{kUQFx?}9#0{)FXEBXPS+Rkp2>zqqV6^Vqw=fTU}#mba{I6rrb`CSDRl> zqhgwaKNe;?)QbZF8)3$Sv5>HFx%?UPK4HHFU`*9(y-EHYcG!22x4T6%W>=&IH>h$7 zLlt#cyR&QuiMo$3e|D!}<&UpVhhX>0f}JUGmFxFzo{C4&i{_~vh9GZUQ{Bm! zm;c$MGLEdk=;hBiSPUAMG4yQ@D`8_6j|b$& zikkj-1r`U!)d6CMi9nxd2bS+jl5`G8#VtJMuqjV0pv>v3HapjpFxVU)zJEuzn<}pH z;q$QCIgrf2JzP65;{szv-NO&f z%Vp05rPkH*2ny`mWhKS851MZMoID^q_& z4rMBDVJ8V{Qr^OD%_-(+7f6U5YqIfDC=+jC=OCr)Trp!DN-!@o&1Lk#FG1LQi)Kvb zJJ!^PrGohucE`ubo4-fzjUj%*p`0(b$Dh*(0c}h)3JW-dRnThGSvDLgtkVl&MY>V*qS+jrH62Au)hZvZJS^3`L-XQk zvMc2ib0Jf5mtxFGU606(hyBt66U-DQOupI=RbGrk`-6sFZ)!B9Lo$nV)Hsv_1hd$f zClYp5lx*4C&P0ga@QndN#*rMWI)28HbkLA=+^t^SKPNp>9d3D~#z~Lu)eg{-X*&@i zF2|R0#?Sb`Z$mo25Y0GP7%Q4_uoJW>Eof<_dO+sK?c`f|9mM<`l5NRUTG7e9h3tO@ z+PG5b81ptkpT01T(+e*peqdO>0vvoDQt${IJO&NDuuAK|%;H3qR?F(V#}FijX)TWZ z7p2v*8X+#SQIIi{u6rhKprau>97%?v49!WSSD}WMv$rInQgjy6^hK-PxkB@lo|EUC zCGpq~c&avI*1^tuBne|h9qdesMaSUi1DPYVP1K6gC^1L(H z_oKbsAeu34%kK5{w0>h@@!TbvG5vMiUGI;tEbd4$FdhMm%VCXag=x1pxK21q>=?yo z9+XMZ>>j09_#+R>CjH^jK>WXYa4t-ErTEIz;1*2LnH6frqu?ADcoN)rA7t1kW{g7! zspB#ZW`c(0b~5w9%*;qJQ#RLTrZ7VaX4qU0_;hZrjr(J^!M2=nFtCPFKp2(|a4-`z z><9+EdPru*6|lJH&de0+Q>itI3V5ZM>6pbNGLFRVO*AG990>=Fqa$`A)!{j5h?irY z^1eZm&ceT@yfhYauupuup{=2D#`t2=;hoTGV|*c-?y#|q@r|g-BFv)c_*6e6ZkR?t zHOu9A1SB@g<#@!hDHb}ZTc}~%iy=yXrs4STg&pqkh%p;)k26f8J??C@q#guA^j++Er5* zVeI2d%kr z+VrTRBXinpNYPPt6gz%MVn;bHcT1^O$R`^23PP+@GRDzhjT6mS(U6ulbDVHIaP`of z{2cI!{FJluPQD@63`m1N`NX%15ZDUD7bwQ`(pG`7$A5#f|HkR*MRmMzf8sMkk(q* ze`#Sy7;fP|xPkE%1Bua@ouidVxfbi$-{Krkn5OoL?+@{Bi;@<`9PJ%mOf^Q*4}zWO zu#Lse=Fm}Ne32E=V9m#7h3c5hBI*N`x!l)ey(?DCit?-Nj`BMaH7`{K;}PSL)R|-( zhba;c9hxqhap+Ufnxpg%%e-*q2)#o&mFLBzVuxxfJ^2LZXwf_kE{xXTRFAQY5i@!R z?Xfh*7dj^zbSX6Z@XQV3rG|7A;|lB275PdANP{{epZKEBR)e4dXuCoM&~`=g7w*ud z-?`m4#v))>u}BygH0;glStJY$1=xlhk5PQWPKz|;B-TmB_0CB#lZ4F0oc(}&^-57I zI<_JgpRCVG=Ku#uISF^rpoTgfYm6^yMdtwei#8+5`H0Mq+l=C@%}8}gecaPQ?c_t! z;|@fw-DV^_bQ;=>uQDCXDksby&i8Z}v$qp1_=%=}eCB6fYMF}DgXX7LA`bc3C-`BU z>y)Cz7mH>bJVdL3ERr|i;3sG(E!KtVM>03)FWJ7AXBk~u{j=T`Jwf~P2=QZc zlcbM1wkTlRCCQz81#CYWb66IF?RS>8#DU{iT&35 z^B@W&w%V;P^}a8dIc>ckLB59`Y7OI-h0w}zc7zel?(7BV*4L9tQLGa(C-|Gum+Kzp zq!F@i6DcIU(ZuVUcO*#2qS#B<>g(DX2YCuXj^JFIwF$%D*Z zFDpsgI4RGYK0W?rOWJW8Xs}KA<*GRn z`L#QfY1T^h%1i70r0wX)Tvs_^kExFr`*_kvcTIeY` z?ftYTx7_Uk(u~&;U$4_&_KGjr-Jo>1OOmI)6h<_=+YNhqxT9ylsi!Ypuz2b0g(odO zb?M>-^QzTF7oK;)wLD-G7tdFxX2wP%R&-?La1Sk3*c9t`nnj!&bJStXjV{gZa``~?$OFDHCt>4nYboqySd@g!$;nwVpsjh-Wv{g}L-KU+H9 zzA!U4N2KyW@@pC&6%K<9U;Z41+l>9#uCe2wzmleh ziDftAL=#-A)3d0-I&;%r^d;U-wSSNeD^T~aQF>m&EUt-L|rf;N*Z_J$wp2IL^ zyRI#UYU7F7#*3Dph9~bcGVcSVlqK(O3W_O;Fc0k$Uz`Xq@5ZrjZ4d>g&CFa~;oXti z#FBBe4y)wPI9idQfzQQPpTGQ)tFF560{E%U%sPV&JlxY>&WP_1jfMGCE8ZFNG+yzH z>mEu>ff32$V18YqCA`LBFM?r3j6=6mgo?VtWQZyh$`(V3lD(B6IF zX=QGuJap=x$HR#o`9z4XxoJ0swG8`I^N_~)8}{kuu#AlHeaV|7+$hfUl+KrM?s z*>3fUIdr!6_{k?GH+O+l9umzsTCV#q{jrx3)Xo;uJ<|vE&mW zc0-6+O2c@MqoJ~EMKj)Kk32(e96YTq_yZ39f(A972)F97nM2NPK{73K^L&KWczw2> z6NmDN5Z59^^bsn6R&>3g`Rh~4;f`kK4D4dLl{8}%9D4SiJAnf`4*CO!A;a0dIh>yN z&87*tmg3&#P^FX?j1ahGvIWKsf0Rkf+4!P|;Wuc>J>G`o=|a}gip=euy9cwZnPF7hmKXYL)LPJ5bieJ~ z0i$ZRyx<^A*Y5aY4tm2Qi5A%YNdq@i@u?n{xnci!Cu;50S=Q!eW0rNYRpe81WvaC) z_Ko;50~?u&-7y>fP3*zHfD~h$wU-Qybv|D&2^u?Ih6UF#doZsz*Tr#dcl0;!B*T=y zOEg+{TN52AN-a9lRC*lE(|zplT<4ALACskv7M{Lz+0sTZR-K z=?8tGT*`ZNlG@5Mk0~S2HT114w|6>-XmaP#WH5J}Xu>*@?1vh8BzfzzI+Ep@h~9xe2-_q^zxv$M;UT zc!ka>_wfRKq>RRsgK0lQ7qO$W32vj)$?kST${OaMkW=>RZDGH7_4a}Hcv)+ux@eD0 z*|2rP-eoh-FMsT|>25cs9ERM9y;CmEKse<-M#by`yFZ5*cPM7260zT(QpPuE$=z1v3e=577N1Sh!1=%yc{) z{Plzh2GO$cXB;9dXbdA3=cT8UG=gNN9GYRrK@%oV`aX#y&*I#pv!>H@ z5=o($Ql%14f@8p9H`16}hMA5w(N{_uFTOmFN{wf&zy{}A7_w3^cD%|>bn++X+@L~o z1XdmuJ`p!Ita-28$TI?sK%n7~Q00LCt=uS-Xq@<3dof~4ZlpR)15AERQ((xIF!z1= zW)ow^@vGZ%e8i4dxd{X6l-{{17I{v>jq4BoKXbDfoE?nZq}8$^KU8iMDyO~{Wn;I< zO$sv^;`8QU#430%{X#{c$J%|GmCO=j)V$hpwn?}HVPKjYA+nx zcW&$%-}m9)48{uIAE0lC67AJ7EE~ItrZC6}67@L-Vc4)|LOKV?pD<{M<0(jvX$WKI zX2eSx>rFI1i+ks0c{aFCuGOB$SZSwvgLZ+jM%I_3W~1kFm;3xM6Jr|Cum)x)9?NkzKQlSx;~bdLW!fu;me?fn`jCHI}LHHi%!@W9s87gQ;l%q{AGs4 z?C<1g1(syaJ;E<8jbt;2rntSh9=Tw<6;-o_{Ayx8Eer;m$Tne$NnGjh(|XVm9>38rg1d*wXpcj{wi;S1B)IUkIBN|t7@xl}0mi zQ5yy;tT1;Kxb_%xuEw>;IOQBAmvWAlqf$L9=iGf^ea_E>WEz6j&{ zU9^rVKH-$}pU_{FIm)I|Jv-+dZTm}?A_w(3M{S!13%Rd;!T#|*%Q=VdtLWRIm>QNR zH?me_H*%^lDd&HnuZ;KpgziTp)p+9LmPVyw-1wSvjzjSYH=+hA=b$C*^y8ZDxV52r zPR{rsSw!W|xsTUsKiv~~8eKP4k!(KBYjkkxr5oRs;{2!Jo)(cpiT3#3uwc>F$W1hb zL94h4W%)JHglo0`_yTH0^!diM+QUa>t5z5^#A~Zo7}AQg7+>@3*-eX;$EC{S?x3#J zWp|?bJm`ofcru?qx#K1O_w|*p=FdoEchtUeazNkxnflU}{z8~n% zD6FvL;;qh(m0ELY_A8o6-F9)ET4Oj$#b~*&&_h;o z=xb;3WP?e?RdHxVW4Zr{BIMyx$F9#7G}v79*ZD$0!<)isCUVoRw({i6gM)9=V=Nyq%sSLy@{g0RfqL|vA5Y1Tpi*_PP3cNC+hKQ69aufvf8o5B{*d=0=q8%6=PEwJ|26WPHH-#3R-nS+-tP^mCG)>bm=7*kfdvd7plKJ zFWUq+*J{_G&)mrvLeIr{^z!I!e@0@@_+DpA$hcPf>^$_>$-)t?)$V~rd>gDVu7|ua z(~O5hyB~`N5F=k`_fx=q(df465%MB`#GKymIm(-`*r%`NsrX;@{G8=uAT&%Fmz%vY z;9zy_d@#>+7xNUnb&GQoJqL~w-Ur&!bKof9D0Nt4{2421Qktj6NxR8_)n%EZCUI0= zaBcIXcznCyh}*h&(#YGojQgL2t}mG##^l0JEf`1Jgu23soC(?)dO>DqoY*NJEg^>x zPhC1t=glZN~dx*U4|c!(>n`6DA9Fmr300sOgJaI*|2B^+K`3#R`;Ytb7-T zGRLYKln*bX=0r<+Kt5Gln6WKr^t!hr0d^%{|*BKU9 zb|pOQJMfoO);Rj}1L(`~;EV29@u}l!g}Yd#zt}H%7Pf$nKXwVW(7-$^?pYg%&@jTw zvvDLL!tDch-lJ=;hyWt?!31VzdrufKCU^J`H_+Z|TgL87hH_Rh|{*(<&mz: -5.186ns/-468.418ns; real time: 7 secs +Level 2, iteration 1 +11(0.01%) conflicts; 474(70.33%) untouched conns; 377050 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-377.051ns; real time: 8 secs +Level 3, iteration 1 +20(0.02%) conflicts; 254(37.69%) untouched conns; 373495 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-373.496ns; real time: 8 secs +Level 4, iteration 1 +11(0.01%) conflicts; 0(0.00%) untouched conn; 386254 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-386.255ns; real time: 8 secs + +Info: Initial congestion level at 75% usage is 0 +Info: Initial congestion area at 75% usage is 0 (0.00%) + +Start NBR section for normal routing at 05:03:39 08/15/23 +Level 1, iteration 1 +7(0.01%) conflicts; 4(0.59%) untouched conns; 379537 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-379.537ns; real time: 8 secs +Level 4, iteration 1 +9(0.01%) conflicts; 0(0.00%) untouched conn; 380799 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-380.800ns; real time: 8 secs +Level 4, iteration 2 +6(0.01%) conflicts; 0(0.00%) untouched conn; 390586 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-390.587ns; real time: 8 secs +Level 4, iteration 3 +6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-384.719ns; real time: 8 secs +Level 4, iteration 4 +6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-384.719ns; real time: 8 secs +Level 4, iteration 5 +4(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.014ns; real time: 8 secs +Level 4, iteration 6 +3(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.014ns; real time: 8 secs +Level 4, iteration 7 +3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.875ns; real time: 8 secs +Level 4, iteration 8 +3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.875ns; real time: 8 secs +Level 4, iteration 9 +2(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-409.289ns; real time: 8 secs +Level 4, iteration 10 +3(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-409.289ns; real time: 8 secs +Level 4, iteration 11 +3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.036ns; real time: 8 secs +Level 4, iteration 12 +3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.036ns; real time: 8 secs +Level 4, iteration 13 +2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score; +Estimated worst slack/total negative slack: -4.574ns/-404.327ns; real time: 8 secs +Level 4, iteration 14 +2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score; +Estimated worst slack/total negative slack: -4.574ns/-404.327ns; real time: 8 secs +Level 4, iteration 15 +2(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 16 +3(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 17 +2(0.00%) conflicts; 0(0.00%) untouched conn; 404668 (nbr) score; +Estimated worst slack/total negative slack: -4.574ns/-404.669ns; real time: 8 secs +Level 4, iteration 18 +1(0.00%) conflict; 0(0.00%) untouched conn; 404668 (nbr) score; +Estimated worst slack/total negative slack: -4.574ns/-404.669ns; real time: 8 secs +Level 4, iteration 19 +1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 20 +1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 21 +1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 22 +1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 23 +1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.277ns; real time: 8 secs +Level 4, iteration 24 +1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.277ns; real time: 8 secs +Level 4, iteration 25 +0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 8 secs + +Start NBR section for performance tuning (iteration 1) at 05:03:39 08/15/23 +Level 4, iteration 1 +1(0.00%) conflict; 0(0.00%) untouched conn; 405829 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-405.830ns; real time: 8 secs +Level 4, iteration 2 +0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 8 secs + +Start NBR section for re-routing at 05:03:39 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 8 secs + +Start NBR section for post-routing at 05:03:39 08/15/23 + +End NBR router with 0 unrouted connection + +NBR Summary +----------- + Number of unrouted connections : 0 (0.00%) + Number of connections with timing violations : 254 (37.69%) + Estimated worst slack : -4.650ns + Timing score : 391939 +----------- +Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. + + + +WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. + Signal=nCCAS_c loads=6 clock_loads=4 + +Total CPU time 7 secs +Total REAL time: 8 secs +Completely routed. +End of route. 674 routed (100.00%); 0 unrouted. + +Hold time timing score: 0, hold timing errors: 0 + +Timing score: 391939 + +Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd. + + +All signals are completely routed. + + +PAR_SUMMARY::Run status = Completed +PAR_SUMMARY::Number of unrouted conns = 0 +PAR_SUMMARY::Worst slack> = -4.650 +PAR_SUMMARY::Timing score> = 391.939 +PAR_SUMMARY::Worst slack> = 0.304 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Number of errors = 0 + +Total CPU time to completion: 8 secs +Total REAL time to completion: 8 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1_par.asd b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1_par.asd new file mode 100644 index 0000000..38b1fbf --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1_par.asd @@ -0,0 +1,38 @@ +[ActiveSupport PAR] +; Global primary clocks +GLOBAL_PRIMARY_USED = 2; +; Global primary clock #0 +GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c; +GLOBAL_PRIMARY_0_DRIVERTYPE = PIO; +GLOBAL_PRIMARY_0_LOADNUM = 40; +; Global primary clock #1 +GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c; +GLOBAL_PRIMARY_1_DRIVERTYPE = PIO; +GLOBAL_PRIMARY_1_LOADNUM = 13; +; # of global secondary clocks +GLOBAL_SECONDARY_USED = 1; +; Global secondary clock #0 +GLOBAL_SECONDARY_0_SIGNALNAME = nCRAS_c; +GLOBAL_SECONDARY_0_DRIVERTYPE = PIO; +GLOBAL_SECONDARY_0_LOADNUM = 9; +GLOBAL_SECONDARY_0_SIGTYPE = CLK; +; I/O Bank 0 Usage +BANK_0_USED = 13; +BANK_0_AVAIL = 19; +BANK_0_VCCIO = 2.5V; +BANK_0_VREF1 = NA; +; I/O Bank 1 Usage +BANK_1_USED = 20; +BANK_1_AVAIL = 21; +BANK_1_VCCIO = 2.5V; +BANK_1_VREF1 = NA; +; I/O Bank 2 Usage +BANK_2_USED = 17; +BANK_2_AVAIL = 20; +BANK_2_VCCIO = 2.5V; +BANK_2_VREF1 = NA; +; I/O Bank 3 Usage +BANK_3_USED = 17; +BANK_3_AVAIL = 20; +BANK_3_VCCIO = 2.5V; +BANK_3_VREF1 = NA; diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/RAM2GS_LCMXO2_1200HC_impl1.par b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/RAM2GS_LCMXO2_1200HC_impl1.par new file mode 100644 index 0000000..9d23cf4 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/RAM2GS_LCMXO2_1200HC_impl1.par @@ -0,0 +1,28 @@ +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:31 2023 + +C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_1200HC_impl1.p2t +RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir +RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset +D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml + + +Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf. + +Level/ Number Worst Timing Worst Timing Run NCD +Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status +---------- -------- ----- ------ ----------- ----------- ---- ------ +5_1 * 0 -4.650 391939 0.304 0 08 Completed + +* : Design saved. + +Total (real) run time for 1-seed: 8 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.drc b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.drc new file mode 100644 index 0000000..ec074a2 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.drc @@ -0,0 +1 @@ +DRC detected 0 errors and 0 warnings. diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.jed b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.jed new file mode 100644 index 0000000..8ec6c65 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.jed @@ -0,0 +1,2779 @@ +* +NOTE Diamond (64-bit) 3.12.1.454 JEDEC Compatible Fuse File.* +NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.* +NOTE All Rights Reserved.* +NOTE DATE CREATED: Tue Aug 15 05:03:43 2023* +NOTE DESIGN NAME: RAM2GS_LCMXO2_1200HC_impl1.ncd* +NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100* +NOTE JEDEC FILE STATUS: Final Version 1.95* +NOTE PIN ASSIGNMENTS* +NOTE PINS RD[7] : 43 : inout* +NOTE PINS RD[6] : 42 : inout* +NOTE PINS RD[5] : 41 : inout* +NOTE PINS RD[4] : 40 : inout* +NOTE PINS RD[3] : 39 : inout* +NOTE PINS RD[2] : 38 : inout* +NOTE PINS RD[1] : 37 : inout* +NOTE PINS RD[0] : 36 : inout* +NOTE PINS Dout[7] : 82 : out* +NOTE PINS Dout[6] : 78 : out* +NOTE PINS Dout[5] : 84 : out* +NOTE PINS Dout[4] : 83 : out* +NOTE PINS Dout[3] : 85 : out* +NOTE PINS Dout[2] : 87 : out* +NOTE PINS Dout[1] : 86 : out* +NOTE PINS Dout[0] : 76 : out* +NOTE PINS LED : 34 : out* +NOTE PINS RBA[1] : 60 : out* +NOTE PINS RBA[0] : 58 : out* +NOTE PINS RA[11] : 59 : out* +NOTE PINS RA[10] : 64 : out* +NOTE PINS RA[9] : 63 : out* +NOTE PINS RA[8] : 65 : out* +NOTE PINS RA[7] : 75 : out* +NOTE PINS RA[6] : 68 : out* +NOTE PINS RA[5] : 70 : out* +NOTE PINS RA[4] : 74 : out* +NOTE PINS RA[3] : 71 : out* +NOTE PINS RA[2] : 69 : out* +NOTE PINS RA[1] : 67 : out* +NOTE PINS RA[0] : 66 : out* +NOTE PINS nRCS : 57 : out* +NOTE PINS RCKE : 53 : out* +NOTE PINS nRWE : 49 : out* +NOTE PINS nRRAS : 54 : out* +NOTE PINS nRCAS : 52 : out* +NOTE PINS RDQMH : 51 : out* +NOTE PINS RDQML : 48 : out* +NOTE PINS nUFMCS : 47 : out* +NOTE PINS UFMCLK : 29 : out* +NOTE PINS UFMSDI : 30 : out* +NOTE PINS PHI2 : 8 : in* +NOTE PINS MAin[9] : 32 : in* +NOTE PINS MAin[8] : 25 : in* +NOTE PINS MAin[7] : 18 : in* +NOTE PINS MAin[6] : 24 : in* +NOTE PINS MAin[5] : 19 : in* +NOTE PINS MAin[4] : 20 : in* +NOTE PINS MAin[3] : 21 : in* +NOTE PINS MAin[2] : 13 : in* +NOTE PINS MAin[1] : 12 : in* +NOTE PINS MAin[0] : 14 : in* +NOTE PINS CROW[1] : 16 : in* +NOTE PINS CROW[0] : 10 : in* +NOTE PINS Din[7] : 1 : in* +NOTE PINS Din[6] : 2 : in* +NOTE PINS Din[5] : 98 : in* +NOTE PINS Din[4] : 99 : in* +NOTE PINS Din[3] : 97 : in* +NOTE PINS Din[2] : 88 : in* +NOTE PINS Din[1] : 96 : in* +NOTE PINS Din[0] : 3 : in* +NOTE PINS nCCAS : 9 : in* +NOTE PINS nCRAS : 17 : in* +NOTE PINS nFWE : 28 : in* +NOTE PINS RCLK : 62 : in* +NOTE PINS UFMSDO : 27 : in* +QP100* +QF343936* +G0* +F0* +L000000 +11111111111111111011110110110011111111111111111100111011000000000000000000000000000000100000000000000000000000001100000000001010 +00000011001010000000010101010000010010001111111101000110000000000000000000000000101110001110000000000001010011010000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000100011000001000100100110000000000000000001000110000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010010000000000000000000011 +00111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +01101001100111001000000000000000000000100111000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000001100010100000001001010000000100100000000000000000100011000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000010000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000010000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000010010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000010011100000010000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000 +00000000010010000000000000100110000001001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000100010000000001000010000000001001100000000000010001100000100011000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000010000000000100001100111000000001001110000000000000000000100001000001000010000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000100000000000000000000000000000000 +00001000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000100010000000000000000000000000000000000000000000000000000000000000000000000010001010011100000000000000000000000000000000000 +00000000000000000000000000000100000000000000000000000000000000000000000100011000000000000000000000000000000000000000000000100110 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00100110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010010100000000 +00000000000000000000000000100100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000001000110000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000110000110000000001000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00100001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00001100001100000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000110000110000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100110000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +01000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100 +00110000000000010101000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000001001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000100111000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000010101000000010001100001000011001110000000000000000010001100000000000000000000000000000000001000110000000000000000 +00000000000000000000000000100110000000000000000000000000000000000001001100000000000000000000000000000000000000000000000000000000 +00010010100000000000000000000000000000000000010011000000000000000000000000000000000000000000000000000000000000000000001001010000 +00000000000000000000000000000000000000000000000000000000000000000001001000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000100011100011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110000100100000 +00000000000000000000000000000000000000000001001011001010000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000001001000000100001100111000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001010000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000110000100100000000000000000000000000000000000000000000000000 +00100100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000001001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000100110000000000001001000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000100100000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000010011000000000100001000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000001100001001000000000100011000000000000000000000000000000000000000000001000100000 +00000000000001000100000000000000000000000000000000000000000000000000000000000000100011000000000000001000010001001010000000000000 +00000000000000000000000000010000000000000000000000100000000000000000000000000000000000000000000000000000000000000000010000100000 +00000000000010000000010010000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000011000010010000000110001010000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000100110100111000000000000000000000000010011000000000100010 +00000000000000000000100110000000000000000000000000000000000000000000000000000000000000000000000000000000000000010101000000000000 +00000000000000010010000000000100000000000000000000000001001000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000001000010000000000000000000000000000000000000000000000000000000100010 +00000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000 +00000000000001000000000000000000000000000000000000000001000110000000000000000000000000000000000100001000001001100010001000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000010010100000000000000000000000000000000000100 +01100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000100110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000101101000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000100100000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101101000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010001100000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000001001010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000001001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000101101000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000010001100000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001010000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101101000000000001001010101001000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000110010010001000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000100010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000010010000001001110000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000010001010011100 +00000000000001001100000000000000000000000000000000000000000000000000000000000000000010000110011100000000000000000100011000000000 +00000000000000000000000010000100000000000010011000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000010010100000000000000000000000000000000000100110000000000000000100011000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000010010000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010001000000000000000000 +00000000000000000000000010010100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000 +11100000000000000000000000000000000000000000000000010010000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000001000010000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000010010000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000010001000000000000000000000000000000000000000000000000000000000000000000 +01001110000010010100000000000000000000000000000000000000000000000000000000000011000001110000000000000000000000000000000000000000 +00000000010000000000000000000000100001000000100100000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000010010100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000101010000000000000010001000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000110000010000100000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000001001000000000010000110011100100111000000000010 +11000000010010100000100000000000000000000000000000000000000000000000000000000000000000000000000001000101001110000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110000011100000 +00010010100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000100001100111001000110000000010011100000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000001000100100111000010010100000001000100000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000011000001110000000000111001100000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010010000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000100010010011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100010000000000000 +00000011100000101001110000000000000000010001100010001000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000001000000000000000000000010000100000000000000000000000100000000000000000000000000000000000100011000000000000 +00000000000000010010000000000000000000000000000000000000000000000000000000000000000000000000000000001001010000000000000000000000 +00000000000010010100000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010001100 +00010011100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000001001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000010001000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000010110100000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000001000010000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100110000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +01001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000101111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000001010111001110000000000000000100010000001010111001110 +00000000000000000000010101110011100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000100101001011000000100010000000000000100010001010110010011100000010001000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000001001011000110001000011101000101010011110011101000011001100000 +10000110011001001110010000110011010011000010000110011000100111000000000010011100000010011100000000000100011000010001100000000000 +00000000000000000001001010000000000000000000000000000000000000000110011000010011101001110000100110100001100001000100110000100011 +01001100000001000110101100000000000000000100001000000100001000000000000000001001010000000000000000000000000000010001100000000000 +00000000000000000000000001100010100100000000001000001000010000100000000010011010000000001100110000010001100000000000000000000000 +00000000000000010010100000000000000000000000000000000001001011000110000000000000000000000000000000000000001000100001001010000000 +00000000000010010001000100010011100010101100000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000011010000101001100010010000010011010011100100001100110010001000100001100110010000001000101000011101001001010011 +10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010001000000000000000000000010011000 +00000000010011001000001011000010011001011000001001100000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000001000000000000000000000000011000101010000000110001010000010000000000100000001000100011100001010001000100000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010001100000000011000100101010110100000 +11010010101001111100001110100000001000110001011000101010000111010100011000100101001111011100100100010000100000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000001101000011000000001000011001110000100111010000 +10000010110111000010010010011100010011000100001000100100000000000100000000010110100000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000001100010010111010000001000111000010100000000010011100100101000000100110010010 +01101011000010110011000010011000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000001000011001110000000001101000100000001000100010001001000110110100101011010000011001100100000110100000100000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000110100100000001001010100010 +10011101010100001001110101010000100111001100011010110001001011011000001001010100110010011010010110011100000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000011100010000100011000001110000100000000000100001 +00000010101110011111100001000100100100110100011001001100000000000000000000000000000000000000000000000000000000000000010011000000 +00000000000000000000000000000000011100000100110001010000000000001000101001110100001000001000011010010011000100011101000010000100 +00100111010001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001010 +00000100010110001010000000000010000100000010001010001100010010010000010000100000000000000000000000000000000000000000000000000000 +00000000000100011000000000000000000000000000000000000000000000010001110100111000110000100000001010101000100111000010100110101010 +01110000100011100001011000010010001011000011101010110111000100010010001000111001100000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000110011100000100001100101010011101000010110010100101001100100011011000 +01001010011001000110111010000000010001100000100101000001000011001110000000000000000000000000000000000000000000000000000000000000 +00000000000000001010100000000000000000000000001001100010110100100011010011010100101000101110001000010011001001000001001100110001 +00101100100100100000111000001010010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000100010000100010100010100010000100101010010001001010001001000100101000100110100000000100000001001110000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111001000111001001011000000100100010 +00011110000001010010010101010001001001111001111001001010101000100111000010110011000011100001101101010101000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100101010000111001001001001110100101010 +01101000111000110100110010011001000110001001100000010000100100000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000010000000100000010011100100101100011100100110100001001001001110000100100011011010 +00010101001010011110001100100100100100010010011100001000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000100000100100000010000010010100100000100100010010100010010001001011000000011000010011 +00000111000100001001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +01000001010000011100100000100001010010010100011111111001101001001110011111111111111001110010010110011111111111111001101001001110 +01111111111111100111001001011001111111011011010011110101010110011000001110111111110000011000111100110010000110100000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010100000010010100100100101000011000011 +01001110110000001100001101001110110000010100010001111101000101100110000011101111111100001111100011001001001010000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111000101101001010111111011110110000100 +10000110000110100111011000000110000110100111011000001111111100110000110011000111010110011010001010000010100010010011011001100000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010001010101000000 +10000111001111111111111100110100000111001111111111111100111000001011001111111111111100110100000111001111111111111100111000001011 +00111111111111110010101011000111011111110000010000111110010000011111110111000011101100110000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000001011011001001000111011110011000010010010001011011010001000001111 +01001110010010001111110001001101101000100000111101001110010010001111110001001101101000100000111101001110010010000010011000000111 +00001010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000110 +01110010000010000001100000110000100101000010000111001000011000000100110001000101001010001001000101011000000000000000000000000000 +01000100000000000000000000000000000000000001010010000000000000000000000000000000000000000000000100111101110110100001010000100100 +11110000100001001101000011101000010110001001010111001001001000011101000100010011110011110101011001000101101000010000000010011100 +00000000000000010001110001100010000010001100000000000000000000000000000100011000000000000100110000000000010001000000000000000000 +00000000100000010001110011010011100001001111000111010010101100011010001000100101000100110100111100001000010011100000000000000000 +00000000000001001010000000000000000000000000000000000010011010011000000000000000000010000000000000000000000000000000100001110001 +00011000001000110010011100000100011100000100001000010000010000110001110001101100110000101011100000100011000001000100000000000000 +00000100110100101000000000000000000000000000000000010011000000100100100100000000000000000000000000000000000000000000000100101100 +10001011001101011000101001100000001011000000100000010000001001111000100001000000000100000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000001000110000000000001001001100000110110100010110001101000101001111000010 +00101101010000110000110010110000100110100001010011010010101000010000100001000001001110000000000000000000000000000000000000000000 +00000000000000000000000000000001000100000000000000000001001010000000000001011001100100100110100001011100001001011111100101010111 +00001000100101000100001110010010011011000010000101001101001001101000100001010010000000000000000000000000000000000000000000000000 +00000000000000000000110000111100000000010000000000000000000000000000000000000100000100001000000000011100000011000111001010100010 +01000001000011001010110001000101100101001100001000000100010000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000101111100010001001010111100100010010011000100101000101110010010010111101000101001011001000 +01101000010110100010000110000110110110010000111000100101111101001010001110011101000110000000001001000101001000000000001000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000011011001010100111100000100101111010000011100100 +10010001110110110001000100001110110000010001110010010100110001001001100100100100110011100001001001101000110000010000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000100100111110000100110011110111 +00100110100000101100001001000101101111000010010011110010010011011000010011010111001110100010111010000010011011101000101000111001 +10111000100000000000000000000000000000100001000000000000000000000000000000000000000011000011110000000000000000000000000000000000 +00000010001100010111011011000000110001001010001010000010011011100001000100000010000110111010011101000001000111001100010010001100 +00100110000110000010001010011001001100000000001001100000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000001001100101001100010110000011010010101000111101010101100000100011100110001101000010100111111000100011010001 +00001001001000001001001010100111010000011000010010100001010011100000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000010001100001001000100100010011101001100110110010010011100100100111000100011000010010110 +00110001001111001001001010100001101011100101001100011001010001100000000000000000000000000000000000000000000000000000000000000100 +00100000000000000000000000000000000000000000001001001001100110010010010010110011100010000100100101111010100010000111111001001000 +00100110010011010100101101110001111000000110101010011010010110110011110010001000010000000000000000000000000000000010000110011100 +00000000000000000000000000000000000000000000000000000000000000000010011000001101100000010000101001000111010000010001011100010001 +11000000111011100001001001001010100001100110000010000101100001100100100100101100010100001010011000000000000000000000000000000000 +00000000000000000000000000000001001110000000000000100111000000000000000000000000000000000000010011110011010111010010110100110010 +11000101000111100000110011101000011001110101001011010101001001110100100100000100101111000010010000110010110100101000011110001000 +00000010010001000000000000000000000000000000000000000000000000000000000100000000001100001111000000000000000000000000000000000000 +00000001000110101011010011101100001001010111100100011100101011110000101001100010110011100000100011000100010100001000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000110010001001101101000 +00110100110000110011010110100100101101010100100001110010000100100011000100101100100001010010100110100010010011001001010100011000 +00001000010000000000000000000000000000000000000000000000000000100010000000000000000000000000000000000000000000000000000001100000 +11010101000100101011010001101001101101000100001000101100000110100000100111100000111000100010110010000101110010000010011010001111 +00101001100100111001000010011000000100110000000000000000000000000000000000000000000000000000000000000110000111100100110001001101 +10001010000000000000000000000000000010011000001001010100010100011100111011010000101001010100110100110011110000011001101000001000 +00110001001001000011000000100000100110101011100100010010001100100110110111000000000000000000000000000000000000000000000000000000 +00000000000000000000000000001000110001001110000000000000000000000000000010010010010001000011001011110010000010011110101011000101 +00110000100111100100101000111000010010010111100110010100100100110101100001101010010100101010101100000000000000000000000000000000 +00000000000000000000000000000000000000000000010011000000000000000000000000000000000001000001101001001010100101100010001100011001 +11000100011001100001000100110001000111000100010010001000000010010111010001101100100100100110000000000000000000000000000000000000 +00000000000000000000000000000000010011110010000100011010001000000000000000000000000001001110000100001001001000010001110010010011 +01100000110000010001010001010011111100001001000011001011000111000011001010100110001001101000000000000000000000000000000000000000 +00000000000000000000000000000000000000000101111000000000000000000000000000000000000011110011001010000111001100110100001010001011 +11100001111101110110100001111111101101000100001101000111000100010011010100010000010000101110001000100110110010001011111100001000 +01111001000011111111011001100000000000000000000000000000000000000000000000000000000000000000000001001100000000000000000000000000 +00000000000110000011001110111011110110000011111100111110111111101110110111111110111110010011000100011111110000100011111111100111 +01111111100100101000010001110100001001001011011110001000100011110010001001001001110010011101000101100000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000011000001101100001111111010101011011100001110011001 +11110011001100001110110011001110100010010011000011001111111101001110101000110011000011000011011101111111110000110001000001001001 +11111000011011001101000110111010110010010000100011000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000001100110011111111110010000111001100111110001110100110101000110111111110000111001111111010000100000 +11111111011000011100011101101000101010011110011011000011111110000110110011010011010000111000011001000011111001100100001101010000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010110110010010001110111100 +11000100101110100000011100001110010000000110100010100110001101110010010001111110001010011000110010100011111100011100110001100000 +00000000000000000000000000000000000000000000000000000000000000000000000001011110000000000000000000000000000000110011100000001000 +10100100000010000001101000100010011110000010000010000100111000100001011010100011000010010100000000000000000000000000000000000000 +00000000000000000000000000000000000000000100111000000000000000000000000000000000010001100111011000001001110010001011010010101000 +01111000001001000010011001000101100001100100111000110010001010011010101001001110110100101011010011011000111001110000000000000000 +00000000000000100011000000000000000000000000000000000000000000000010011000000000000000000000000000000010011010000111000110001001 +11001011110000100001111001000010010111001000010100010111000011001000111011110100011010011100010011000101100100110100111000000000 +00000000000000000000010001110010100000000000000000000000000000000000100110000000000000000000000000000000000000000001000010010000 +10100000000010011010000010001100011101100001101000001100000010010110001000001100010100011001110001000001000011000100000000000000 +00000000000000000100101000000000000000000000000000000000000100100000000000000000000000000000000000000000001100100100100000010010 +10100011001100100010100001100001100111100010000001001111010111001011000100010011110000010010010001000000000000100100000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000001000110000000100001100111010010001001101000011 +11000001010010100100011110100001011110010011000011001110110011000010000111001000100100000001000011000100010011101101001010110100 +00100000000000000000000000000010001100000000000000000000000000000000000000000000000000100010100010000001000100000000000000000000 +00111000010001011000100110011100000011001011111001000111100101001001010001010011000111000011001011110100000101100100110100001011 +01100100100111100011000100110010011010011000001001010000000000000000000000000000000000000000000000000000010110000000001011010000 +00000010000010000000000100000000000000000100101000000011000101010000100100100000010010100101111101011000011010000100100000100011 +01001001000011110000001010011110011000110010010110000001001001001000000000000000000000000010010100000000000000000000000000000000 +00000000000000000000000000000000000000000000000000100001100111100111111000100010100110000001000010010110010010010001110000010000 +10101111010010010001010010001110101000110001001011010000100100101110100101010010010000110000001001001000011001000000000000000000 +00000000000000000000000000000000000000000000000000000000001001000000000000000000000000000000001000010100001000000110100101011000 +00111100000110100001011001000111010011100011000100110110001001110010110010111100000101000011001101000110100011110110010111000010 +01010011010010110011101100110010100110000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000010000110011100000000010001100100111101001000100000100001000101001100011100001110001101001000111000011100010001110101000110 +00011001101000011010111000110100101100100000100000111010000000100001000000000000000000000000000000000000000000000000000000000000 +00001011010000000000000000000000000000000000000000010000000010001000101001010011111100010101011011001101001011001101010101001011 +00111101001100110100101010011110000000100111101111110001001110001010000101001011011110100000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000010001000111000100001000111000111000010110110010011110110001000 +10110011000001001011000111010010000100001011101000000100011110000011001001010011000100011101100000110100001000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000001000110100110100001111001000010011000111001 +00001001011101000001110010010111011000000111001000010101111100000011110000110111010000010001101010111100110000100100110010010110 +01001000011001101010010100011000000000000000000000000000000000000000000000000000000000000000000000000000000111001000000000000000 +01000011001110000000000000000000100110011001001001100100011100000001001110010011101101000100001000011100011000110100000110011110 +01011010011000011110000110100101010110010001100010101010100100000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000010000110011111100000101001100010001110011110001010011010000110010110000011000011001011101010110 +11101100000010000110010011001000010100101100111010000011010001001001110110000110110111001000000000000000000000000000000000000000 +00000000000000000000000000000000000000000010011100000000000000001000101110001000000000000001001110100100100000000010000111100010 +10100111010110010001110010011000101101100100010010110001010101001101101100110110110001101001110100011110000100100010001110010110 +01101001000000000000000000000000000000000000000000000000000000000000000000000101101000000000000000010011100000000100110000000000 +01000010111010000010011100100111010010101110100000100101001100100011010011101001101001110010111010001000100101111000010000010000 +00010000110011011100100000010010000000000000000000000000000000000000000000000000000000000000000000000000000000000010000100000100 +00110011100000000000000101100010010101001010100000001000100001100010100100101110100000111001011001000010100100100110100111100000 +10111010110010001010000011101000001000000011000101010100000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000100011010000010011111010110000010000111001000100101010101101010000110001010000010001110 +00001001001110010100110010011001001111110000010100110100010010010000010011010001001001110010011000000000000000000000000000000000 +00000000000000000000000000000000101101000000010001101100100010000000000000000000000100111010000000100111111000000110011010010100 +10000110011111010001000110010100110010110111010001111010000101110000001100110100011010010110001001000010100001100011100011010110 +10000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011100000000100011000000000001000100010 +00010100011100010001001110010011111100000011000001001011000001000111001011000001101000100100010000100010100001001110100000100110 +11001000011000001001110100101100110100000100100000000000000000000000000000000000000000000000000000000000000010000000000000000000 +00000100101011010010010000000000000000000000000010101000110010010010000100100001010011000111000000111000110011000001100001011110 +10110000100010100111101011111010000010100110001010000001100001001010011010101110001110000111011000011000110000000000000000000000 +00000000000000000000000000000000000000010010000000000000001001000010110000000000001001100000000000000000001000011001011001101111 +01000010101011001011000100101001010011110101000100110100100101001010001001101000100000110010001010001110000011011000001001011001 +00100110000100111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010001 +11000100000111111101110011011000011111111001010001100000110100110101000101000100001010100010011001100101110011111011111011110100 +00010100001100001111111001100101011011111110000010100011100010001001100000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000001010000001111111001110010111011010101011111001010110110000001100000110110000111 +01101011111111111111010001010011111111111011100101110101110111110111011011101001100100011101111110000011001010001001001111101110 +11100010011000111011011100010001100100101000111000100010001100000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000100010010001010010101111110001110000111010110110111011011000000110000100111000011101010001111001 +01011011101001010001101000100110000111010001110100011011100001111111011111111000011001011101100100010111111001111001100001100101 +01111110111011000101010001111001100100100010001110001100000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000001110111111001111110011101010111111001111111110100011111110011010101111110111111100101010000111 +11011111111101110110101001110111111100001101000101000101010110010001011111100110110010101111110111010110010001111101000001000010 +11010011001010100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010110111 +00110000110000110010111100110001101110010010001110111100110001101110010011000011001111000011001100011010111010000011000011001111 +00010000100001111010000010000011010001000010110110010010001111110001000011000110000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000100000000000111010000000100101100011101011001000101001100100001 +10010110011100001000000000000000000000000100100000000000000000000000000000000000000000000000100010100111000000000000000000000000 +00000000000000000000000100010010011100000101110100101000111010001010001010011000111001000011010000101001100000100001010000100000 +00000000000000000000000000100011000000000000000000000000000000000000000000000000000000000000000000000000000000000100010000000101 +00100110100110011010001001011111001000011100010000110001001010111000001001010000000000000000000000000000000000000000000000000000 +00000000000000010011000000000000000000000000000000000000000000001110000001000000100000000100011100000100001101010010000110010110 +10110000000000000000000000000001001010000000000010010100000000000000000000000000000000001001000000000000000000000000000000000000 +00000000000001011100101011010001000001001110100001100111001001100010011100000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000010001000010011011001001101001010010011110001001110000100100101000110100 +00101001101000110100001000100111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000001011000000000010011110011100000000000010010100000100011000000000000000000000000000000000000000000000000000000000000 +00000000110000110000000000000000000000000000000000000000000000000100000000101010100000100010100111000110100000110111010010101000 +10100111100010010010100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000010010100001000011001101001000010010111010011001001101000101100100010111000010110000110011001000011000000110001001000001101 +00010001000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +01000101101010010110011010000001001101010111100000110011100000111110010011011101000001111000100100010100110010111111000110101001 +10110110000000000000000010000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000100110001100110000010100110001111010001001001011000101001001000101000011101000100001001001000111000111011000111001000010 +11000000000000000000000000000000000000000000000000000000000000000000000000001100001100000000000000000000000000000000000000000000 +10001110000101110000001100011010011111000100011100010001101010100111010010010000110101111100110010100000100010100000100110101101 +00101011001000000000000010110100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00100010000000000010010110001011100001101011100100011101101111000100010000011010110100100110100111010001100000010000100000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000001001100000010011010 +01101000110100110101010011100001000101001100100100100000100010100011001001110000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000001000100010010000001011111001001000011101100000101011101100100101100 +00100110101010010011110011000001001100100010000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000010011100000010010001010011000000011000100101001101100110101110010000100100101010011000100111000100 +01000000000000000000000000000000000000000000000000000000000000000000000000100111000000000000000001001000000000000000100010000100 +11001001010001000011011101000101010110010111101010011011100100111001001111000110001001110010101100000000000000000000000000000000 +00000000000000000000000000000000000011000011000000000000000000000000000000000000000000000001000100010011110010111000010011000010 +01110000100111011000010000011000011000100011000000010011101000100010001100000000000100011000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000010010000001000000010100110010011001100011110001100100111010000010000011110 +10010110100000100011001100001010110011000101011000010110000011000010010100000000000100101000000000000000000000000000000000000000 +00000000000000000000000000000000000010011000000000000000100111000010010000001100110000011100010101001110100011100100100001100011 +10010010001110000010011001000110000000010011100000000000000000000000000000000000000000000000000000000000000000011000011000000000 +00000000000000000000000000000000000000010010101000011001101001100001000101110010000100011100110001100001001101011100000100001001 +00100111000000111100100000000010000100000000000000000000000000000000000000000000000000000000000000000000000001000110000000000000 +00000000000000000001000010000100100010000101100100010100000100110000010001010001001011001011011100001001100010100010000000000000 +00000000000000000000000000000000000000000000000000000000000000000000100100100010000000000000000000000000000000001000011001000100 +00000000110100001010010110001100011001100001101000010100001010010000110000100110011010011100000000000000000000000000000000000000 +00000000000000000000000000000000000000000010010001001011100110000000000000000000000000000000000000000100101001001000100010101110 +10011110001110010010011110001000111011000011100010011001110010001100000100000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000001010000110001010111101000000111111110110100001101111111001111 +11110111000111011001101010000100001101000111111111010011000100001110111111100000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000110111011100111010000011011100001010001111011111100011101000100010100 +01010100011000111011100001110111110111101001001100110011101000101100001100010100110111111100000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000011101011001100101100101000111010000011011000001000111 +11101111101010001000111001001111011111101111110000111010100001001001100010001101000100011001001001101100110000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001110101100100110111101111100010100001 +10111111110100010000110100010111110101011010101010100001110001000111111111001010100010000111011001100000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101101110011000010101110011000100000 +01000101001100011000110111001000110000011100110001100000101011000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000010001010011100000000000000000100100000000000000000000000010001010011100000000000000000000 +00000001000101001110000000000000000000000000000000000000000000000000000000000000000000000000000000010010100000000000000000000000 +00000000000010001100000100011000000000001000110000010001100000000000000000000000000000000000000000000000000000000000000000000000 +10011100010001000000000000010001010010100000000000000000000010001010011010011100000000000000000000001001010000000000000000010011 +00000000000000000000000000000000000000000000000000000001000010000100000000000100011000000100111000000000000000000000011100100100 +00001001010000010011000000000000000000100110000000000001001000000000000000000011001100001100110000000000000000000000000000000000 +00000000000000000000000000000000000000000000100100000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000010010100000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000010001100000000000100101000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000100011000000000000010010010111000100111000001000000000001 +00110010011000000010001001001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +00111100111000000000001001111001111000000010010110001100001000010010001000000100011000000100101010010000100010000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000001000110000010001000000100001001001010010101010010 +10000000100000000100100000000001000110100110000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000011010001000000001001110000000000000000000000011001100000000000010010101001000001001110000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000010011000000100110000001010010000000000000000000000000001 +00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011000001000110000000 +00100011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +10001100100010001101000100000100111010001100000101110100111000010000110011100000000000000000000000000001000011001110000000000000 +00010001010011100000000000000000000000000000000000000000000000000000000000000000100101000100111011000010010010000100100101000100 +10101001010000000000101001000000000010010100000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000001010010000000001001100000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000100111000000010001000100110000100111000000000000000000000000000000010001000010011000000 +00000000000000000000000000000000000000000000000000000000000000000000000010110000000000000000001000000000010000100100011000100100 +00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000100 +00000000011000101010000010010100000101011000000000000000000000000000100011000000000000000000000000000000000000000000000000000000 +00000000000000000000000111000100000000000000000000100110000001000101001110000000000000010010001001100000000000000000000000000000 +01001010000000000000000000000000000000000000000000000000011011010000000000000010001001001010000000000000000000010011010011101000 +10000000000000100011001100011000010001100000000000100011000000000000000001001100000000000000000000000000000000000000000000000000 +01000100000000000010010100000000000000010001010001100100010001100010010000000000100011000001001010000100111000000000000000000000 +00000000100110000000000000000000000000000000000000000000000000000000000000000001001100000000000000011101000000011010110001001110 +00010000000000010010100000000100010010010100000000000100111000000000000000001001000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000010000100000000000000000000000100001000000000000000000000001000010000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000001100110000000000000000000000000001100110000000000000000000000000001 +10011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100101100001000000 +00000000001001011000010000000000000000000000100101100001000000000001000010000000000000000100101100001000000000000000000000000000 +00000000000000000000000010011000000000000100110000000000000000000000000000000000000000001001100000000000000000000000000000000000 +00000000000000000000000000000000000000000000000010011100000000000000000000000000000000000000000000000000000100111000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001011100000000000000000010111000000000 +00000000000000011000111100000000000000000000000000000000000000000011000101000100000100000000000000000000000000000000000000000000 +00000000000101110000000000000000001011100000000000000000000000011000111100000000010000100000000000000000000110001010001000001000 +00000000001100010100010000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00010000110001101001111001110100001100011010011110011100000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000010000110001101001111001110000000100001100011010011110011101000011000110100111100111000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001110000001000110000010001101 +00111100011000000000000010011110001101001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000100101000000000000000111000101000000000000000000 +00000000000000000000010011100000000000000000100111000000000000000001001110000000000000000000000010011100000000000000000100111000 +00000000000000100111000000000000000001001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000100011101111110111111111111111111111111111111111111111111111111 +11111111111111111100001010000000000000000000000000000000000000000000000000000000001010101010011100100010000000000000000000000000 +01000000000000000000000000000000111111111111111111111111111111111111111111111111111111111111111101011110000000000000000000000000 +11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 +* +NOTE END CONFIG DATA* +L62976 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +* +C680B* +NOTE FEATURE_ROW* +E0000000000000000000000000000000000000000000000000000000000000000 +0000010001100000* +NOTE User Electronic Signature Data* +UH00000000* +8380 diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.log b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.log new file mode 100644 index 0000000..d0353b8 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.log @@ -0,0 +1,4 @@ +---- MParTrce Tool Log File ---- + +==== Par Standard Out ==== +==== End of Par Standard Out ==== diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.lpf b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.lpf new file mode 100644 index 0000000..2743d95 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.lpf @@ -0,0 +1,4 @@ +#BLOCK ASYNCPATHS; +#BLOCK RESETPATHS; + +#FREQUENCY 200.000000 MHz; diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.lsedata b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.lsedata new file mode 100644 index 0000000..558a037 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.lsedata @@ -0,0 +1,6331 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mrp b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mrp new file mode 100644 index 0000000..8e79120 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mrp @@ -0,0 +1,402 @@ + + Lattice Mapping Report File for Design Module 'RAM2GS' + + +Design Information +------------------ + +Command line: map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial + RAM2GS_LCMXO2_1200HC_impl1.ngd -o RAM2GS_LCMXO2_1200HC_impl1_map.ncd -pr + RAM2GS_LCMXO2_1200HC_impl1.prf -mp RAM2GS_LCMXO2_1200HC_impl1.mrp -lpf D:/O + neDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200 + HC_impl1.lpf -lpf D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/RA + M2GS_LCMXO2_1200HC.lpf -c 0 -gui -msgset + D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml +Target Vendor: LATTICE +Target Device: LCMXO2-1200HCTQFP100 +Target Performance: 4 +Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454 +Mapped on: 08/15/23 05:03:26 + +Design Summary +-------------- + + Number of registers: 102 out of 1520 (7%) + PFU registers: 102 out of 1280 (8%) + PIO registers: 0 out of 240 (0%) + Number of SLICEs: 75 out of 640 (12%) + SLICEs as Logic/ROM: 75 out of 640 (12%) + SLICEs as RAM: 0 out of 480 (0%) + SLICEs as Carry: 10 out of 640 (2%) + Number of LUT4s: 143 out of 1280 (11%) + Number used as logic LUTs: 123 + Number used as distributed RAM: 0 + Number used as ripple logic: 20 + Number used as shift registers: 0 + Number of PIO sites used: 67 + 4(JTAG) out of 80 (89%) + Number of block RAMs: 0 out of 7 (0%) + Number of GSRs: 0 out of 1 (0%) + EFB used : No + JTAG used : No + Readback used : No + Oscillator used : No + Startup used : No + POR : On + Bandgap : On + Number of Power Controller: 0 out of 1 (0%) + Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) + Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%) + Number of DCCA: 0 out of 8 (0%) + Number of DCMA: 0 out of 2 (0%) + Number of PLLs: 0 out of 1 (0%) + Number of DQSDLLs: 0 out of 2 (0%) + Number of CLKDIVC: 0 out of 4 (0%) + Number of ECLKSYNCA: 0 out of 4 (0%) + Number of ECLKBRIDGECS: 0 out of 2 (0%) + Notes:- + 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of + distributed RAMs) + 2*(Number of ripple logic) + 2. Number of logic LUT4s does not include count of distributed RAM and + ripple logic. + Number of clocks: 4 + Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK ) + + Page 1 + + + + +Design: RAM2GS Date: 08/15/23 05:03:26 + +Design Summary (cont) +--------------------- + Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 ) + Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) + Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS ) + Number of Clock Enables: 14 + Net RCLK_c_enable_6: 4 loads, 4 LSLICEs + Net RCLK_c_enable_5: 2 loads, 2 LSLICEs + Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_2: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_6: 1 loads, 1 LSLICEs + Net RCLK_c_enable_27: 8 loads, 8 LSLICEs + Net RCLK_c_enable_10: 3 loads, 3 LSLICEs + Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs + Net RCLK_c_enable_16: 1 loads, 1 LSLICEs + Net RCLK_c_enable_28: 1 loads, 1 LSLICEs + Net RCLK_c_enable_15: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_3: 1 loads, 1 LSLICEs + Net Ready_N_292: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_8: 2 loads, 2 LSLICEs + Number of LSRs: 7 + Net RASr2: 1 loads, 1 LSLICEs + Net nRowColSel_N_35: 1 loads, 1 LSLICEs + Net Ready: 7 loads, 7 LSLICEs + Net nRWE_N_177: 1 loads, 1 LSLICEs + Net C1Submitted_N_237: 2 loads, 2 LSLICEs + Net n2366: 2 loads, 2 LSLICEs + Net nRowColSel_N_34: 1 loads, 1 LSLICEs + Number of nets driven by tri-state buffers: 0 + Top 10 highest fanout non-clock nets: + Net Ready: 18 loads + Net InitReady: 15 loads + Net RASr2: 15 loads + Net nRowColSel_N_35: 13 loads + Net nRowColSel: 12 loads + Net Din_c_4: 10 loads + Net MAin_c_1: 10 loads + Net Din_c_5: 9 loads + Net MAin_c_0: 9 loads + Net Din_c_0: 8 loads + + + + + Number of warnings: 0 + Number of errors: 0 + + +Design Errors/Warnings +---------------------- + + No errors or warnings present. + +IO (PIO) Attributes +------------------- + ++---------------------+-----------+-----------+------------+ +| IO Name | Direction | Levelmode | IO | + + Page 2 + + + + +Design: RAM2GS Date: 08/15/23 05:03:26 + +IO (PIO) Attributes (cont) +-------------------------- +| | | IO_TYPE | Register | ++---------------------+-----------+-----------+------------+ +| RD[7] | BIDIR | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RD[6] | BIDIR | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RD[5] | BIDIR | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RD[4] | BIDIR | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RD[3] | BIDIR | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RD[2] | BIDIR | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RD[1] | BIDIR | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RD[0] | BIDIR | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Dout[7] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Dout[6] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Dout[5] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Dout[4] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Dout[3] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Dout[2] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Dout[1] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Dout[0] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| LED | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RBA[1] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RBA[0] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[11] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[10] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[9] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[8] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[7] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[6] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[5] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[4] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ + + Page 3 + + + + +Design: RAM2GS Date: 08/15/23 05:03:26 + +IO (PIO) Attributes (cont) +-------------------------- +| RA[3] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[2] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[1] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[0] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| nRCS | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RCKE | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| nRWE | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| nRRAS | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| nRCAS | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RDQMH | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RDQML | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| nUFMCS | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| UFMCLK | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| UFMSDI | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| PHI2 | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[9] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[8] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[7] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[6] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[5] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[4] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[3] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[2] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[1] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[0] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| CROW[1] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| CROW[0] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Din[7] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ + + Page 4 + + + + +Design: RAM2GS Date: 08/15/23 05:03:26 + +IO (PIO) Attributes (cont) +-------------------------- +| Din[6] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Din[5] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Din[4] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Din[3] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Din[2] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Din[1] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Din[0] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| nCCAS | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| nCRAS | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| nFWE | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RCLK | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| UFMSDO | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ + +Removed logic +------------- + +Block i2 undriven or does not drive anything - clipped. +Block GSR_INST undriven or does not drive anything - clipped. +Signal PHI2_N_120 was merged into signal PHI2_c +Signal n1407 was merged into signal nRowColSel_N_34 +Signal n2380 was merged into signal Ready +Signal n1408 was merged into signal nRowColSel_N_35 +Signal nRWE_N_176 was merged into signal nRWE_N_177 +Signal GND_net undriven or does not drive anything - clipped. +Signal VCC_net undriven or does not drive anything - clipped. +Signal FS_610_add_4_19/S1 undriven or does not drive anything - clipped. +Signal FS_610_add_4_19/CO undriven or does not drive anything - clipped. +Signal FS_610_add_4_1/S0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_1/CI undriven or does not drive anything - clipped. +Block i2046 was optimized away. +Block i1118_1_lut was optimized away. +Block i637_1_lut_rep_31 was optimized away. +Block i1119_1_lut was optimized away. +Block nRWE_I_50_1_lut was optimized away. +Block i1 was optimized away. + + + +Run Time and Memory Usage +------------------------- + + Total CPU Time: 0 secs + Total REAL Time: 0 secs + Peak Memory Usage: 41 MB + + Page 5 + + + + +Design: RAM2GS Date: 08/15/23 05:03:26 + +Run Time and Memory Usage (cont) +-------------------------------- + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Page 6 + + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. + Copyright (c) 1995 AT&T Corp. All rights reserved. + Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. + Copyright (c) 2001 Agere Systems All rights reserved. + Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights + reserved. diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mt b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mt new file mode 100644 index 0000000..2d70ad1 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mt @@ -0,0 +1,9 @@ +-v +1 + + +-gt + + +-mapchkpnt 0 +-sethld diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.ncd b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.ncd new file mode 100644 index 0000000000000000000000000000000000000000..c492e5d51d9f51a342f152faa3d9b82acc561858 GIT binary patch literal 197895 zcmeEv3w&Kgwf;%p4@!BolsAO}Z7E1jo=vernxrK*ZA#Ko5HS|07=e_hhzJ%H5fKr& ziueLWMMQjDRIU%MA{P-+k&Co=0TmPEUlB>F_`>%5zi+KsduI082aulHRL=SRCRuy! zHLo?Z)~uOXGke;!!NIDUNB=uFGB>iTc}dNp?%XMl9QnGcT-96F)SO&ho$F{>a$IN4 zVfmWs>Z4n7%a2*OEDvm54!_;_=SBaXMi#l;g!aw_E4tfTkDHgT!sB>BPV~rXVsmM% z&{n0fHJP-v#EwnV))6}7IJ1#|9 zlUd;!sc^ayHIhQQ5;aocbR}w}!s$xXNQKjtsF4b%D^VjAPBXnmDy$9UtCq?0TEV6h zsFi}HTewyVHZjGVS}E9sG*$|h?m4wmurzyXr6rV+zPOp4p-x&N&D}a_i8OcXq$Sea zt&<9;xmzc>rMX)t6;3m!PAZ&cPMuUZ-5ctp!bRnk3Tt_Ng){qky;L||iF&DUx)SwL z;dCYHGh4VmXklN3K&U)2kSUK0M9L$bM2$|QZ)x+AHm5_DH23z+YMNI)8={=c?I6lT zUrP3Rj?(Crkb|&Yw44vU#loaMGLy5D&f+xpP#9!mP^MLrjG4u&Ft-}r%S#S zmPT&_j%r6P$x+qdQRJY`s>w^f6@Hd{E9@-!R$4lG8x&flD=u{KT7|3RYn82%uZ3MH zjlNSycUw=(vhJQG&C7Zgws*AA`r7#|Z+T14>F2EOIj8s3zMePqp1xW}hh00*Tz&Sc zb9?(vo!+vh@08wid)M@ld_qg-k|k|jE$z)6LN|U{`%+PbI!G=%y1gdG%h0g{%XtEZ zo)c#^>F6`T;^ie`K;VWaPoODq@HqjJeB!KpIt6K=9Xvr%3erduq2o`$@N?p<#&iPG zO#XdC`n_~7|Gqx`URu(>uS>s|ru6S?)9SgzK9rh+B@6(mg8Nv=-h_2F-W`mA=0YOm;+Fg?r(h{pPh>6Mjba&Iagn#dtm2_8; zwt$)G&ZOg?k6-j&SnA)W`aSG=FuP zGNG$ATiA3QOkNk&UOH*=+EqSbuBfVjxoPI;P?$td^G3(QUL`dXCIvNfjheg{UIp)6t0wP-Wx;#btbD)x_+@SLgfS!9 zmnOLiR+wT~)?2X=u}7Dn7XB3{BFrmB3*(B>!n9(vFsv9Y+$u&3lZw&88$%}?$u71I z!$zFcT}R)Mohz0nEh?sy^)v8N{|vk^AOkNP$iNE=GVs|v$ZjJYD2sTY zqhv8!$H*eq=*+OVC^|M~;7hPThr$f{5-iY>FN0oKkl>Skkli75d`qa4j-V5}415VL zxMj2=?&$cHkxmIN=y;VuucENPYZ~d7IzEjkLTfj0=!6B?!l$E9Q5rh>6r)w1(mCpA zQ%tQ~FQP6{dmUVgx}FX##Z1wWB?Dig3uJ2<9ZZT-(V-**U!n^%l+Xn_hGe8uf(Z># zF_XrNbYX&xRAGXRw7|sf_C+!)T(+W%v&ONf{i~sbc!w&~y3x8E_K>{O} zcP=a7$F!=>VJ5;XgxLs(ARLD9 z3IsBu8X=ERgHVgW4WoL5xd=@N^AL_ecqPJogjXRPiEtD`Gr|Id7KB!WHiU%;ix7@R zXh(Q8!eWG_2%QMa5RO6ULg+?Vj<5pZScH`b#~~b#@EU{@5MGOLBEstsdJtZZunOTM zgp(0YL0FCO282@)-iXkP@Fs-Q5Kc!p1ECLL4FcQgEQGTW&OtaA;XH&lBb<-GhP?pc zLWH*=T!e5j!rKwnB3y#-4up3iybIw{gm)uchVUMQ%Msp-a0SBq5UxacKf+ZAA3(So z;e!a*Ap8fyhY&uDa4o_|5UxY`D8k1OK92ASgij(|k8lIRrw~4ka3jKJ5I&3WIfR=K zK96uS!WR&3LHHuVtq5O2_%gy*5Wb4=p9r@hd=2622;V@s9pS$azKQTHgl{8!2jLEc z|3>&O!uJsFMEE|!T?qe!a5usa5bik!r>JdE%Qg#SZ$1mRJH#}Iyr@GFF0BRr1q8-#v@0fZ+Iev9xV!v90qfbctn zrx1RR@HE075S~F8L>NNYi10^*KOsDe@Mna-Ap8~KZwP-!cn;wo2%8W#BNSA;tE%vS z1j0y!Q3#_E#vqJE7>6((VFJQLgdGqjA?%1S8DS@coe_3H*cD+4!c>Ia5T+sQj<5&9 zo(Ov(?2WJw!oCRmAxuZuAK?Im83+d=9E5N%!c2r&2(u9mL70PZD8gX~uRu5)p&B8N zP=ip5P=`>D(16g0Fc+Z-VIIN}2(Lt#kMJslBN2{5Xhv9o(1Os4(1x%OVG+X72<-^3 zMp%r{fv^N&DMBa0GK6Cgx)8b%mLse{I2K_g!f^=4BfJLT1ccWjoQUu`gdT*~BdkI= z3E^afQxH}oyaC}TZ$>yj2fe(o zyQd*v-P6;X2YXcB`9FLCo&_%^yBMoZIi;trCl6)@FN5U3_3RgDir_^mxwsG$lG35A zf=C{Z_6zVkMrA|02Jd{FxX2!lJ`vEzX_d-9uBA^au4J56T*vX4+@4+AQ#&_ivrh_L zxMZ?3wQ?cT_e7WOldVE~Zm^E?J1SKf>B5t%)(c*IN*qcX> zJ^j3MdsdzDrk+$WdeH>(PADRlPi}7QKJTP6de1#~HM)FtoanUPd>-;sBXLWmup6Yy zk(|By%$|IMmLtxkB_HMz*K2fdO?6$&gK_LP=r(arlipMVbj>73 za>glbeXCA7eKqPFXFa~Jrmn8>wbj+qVOR^X1EGI&qZX`KNG$X*ei%7&(8vjP&RRUk zZzrT4R5u@Yy{UNHH+M=9C zXE1IF&sgBKQfmAehgD^=J?`~mTNZTn)HcO=By1A2BtV9+WsOb3S78%-m0=s!;z53s z+WUIX?OMI+lnao0T*xtJNcl;&R%r2OJeIb>vbua+I_W)e?48k}&~3F(WYiLCb*N=y zoX&V+!J4^oJ*R+|VN+yCP}2R#?b^7@V($_qse|Vherx%MzsbPn(fIXsT1ev7@(+KM zoR)gI7UEo zrIO(`9huh{>yM<92va0+b`sbTNq2xaymkYAIgY`wN0^BL1Wj| zW;OPN-p08N8OiL}*R|&SmNln$uRb09ATF{b)|3%xa-uRgQq;u55BQ zHTbkvQ20ZItliOf%6!Zova+}|UbKUVaeGclxWE{}-aMUduoHCF-cIq30x-KcG#`R`deq8=ZCUCLT7AM=7AqnJVW7ee6r3_CSn2vEz-9a+#AHL-IFF2zx`nq!V~&@9#pUMOW5FP3`a06btR;P2Df(K{$6P0UZ7KR1(#NI^>1#^S=Sd$o5$W@#=&`xfn6kP_Umep= zNcb5SeXP1jmm-e&qQoiA`;=p*D{+eLo;Yq%B~J0&6UTi|iBk;s#3^Bv3Z}U2iDQkf zDW_QNiQ{2GiBo(YizQ-q^Qbe6OLW+~$J4x|FvQu95f|vVEfUf=b0JOT4I@|+O{Yr7 z>2#`&G@U9)Q>kLXS5i%P$>tN9;xvsg-PfB>n43))_r%fgzD_9tOEK<+Buw=|BaC|> z2~+*g2;<&I!c^Zg!no&=FxBsjFz$6EO!YY0-nQoRUOO9Lu5-r=)QLPiu*$Or@-+xMCIPiBl;HaVq8UIOZh@#|=0}PJhMe zCZuum32CbJ64JQwgf!K532EGPLYiv1gfwnAAx*VgLK-)lkfvHKA&prpq^UMbNMptd zX_~KcEUHL2-D#;%ipR?_s4PnCB}8&Oj>n>k2=%a3m?CsCCTM95q6b1kI^E^#ETXhy z5h3mSv5UD6OB4Qn^rP;M_LjDu>YO;1%0sTJu_a&MDwvTV{@Rkx*0y;qEh}oKceO3b z&zsS?lt8rr$K>Z7GyRxq{8^Zvw{ZHxYW!K$-8HYZy}NkU!Q4(-l6Xx_X9 zKpxt{Kdt<;0B;U$;h$FgnNG*jQA|xMHezw!09VyftP5E&B1cgALsf3XF-CWcqZghXsN7wfjTBsqdFHJ=TaQK@VEp$Mwy}!NaHda zXZ&%=F7f$|UQ(SzAM1FhRO6dFR@C$?S<$gvpGSg~E@d*5wH}!pwX(I-cmdGLw6Zxt zk0u=AYg{3SuXPC`szWnDhaI!B)t3zqzR-B6NlJ}}+T>v@QuUGe#WcxGzS!8>6 zm2Ibb1KDnVxybf7FWX~ZKC(T&BHRC3+13M`C1l%Ob|Cg+dfe8tlUcHTvzKL&?a%vX zk?q4&ww*2IWxMWWW0OzxvOVGDBilPvWcyz%+ahkIWLu7!W{=zMn!gO2{1z|EBHLf^ z&yrb<%66U36av{^@NyZqcl5G7>E$EalPj|QFP81+v&n0p$0pZX2C~NOFMC-Q+5VD$ z7TK;>*{&~=ZEus`S!yk99#*+pv2K-GPkX6LX|gmlZ^;X-sV%IouGTfR>iYWndGnfO zC9O;gYdd>E-|6Ke=(|(|eX9$4v^4PLfC84clX7fd$5%Cz^Dx#xv}y1Ho3tC`zfFKy#XwzQOc*hARu zm6)aqwcLKVg90jmQnY|D%?$J;coB~=YMl2l)b%h z@AdK#?tLo4{jU{nx8GdC2_?1Q9SV0%txmHuM(R&_VV05l2LH@BRXeM2;{<=`VwSIN z$=8`tJsbCH=qF@G!*ynCZWL}W9FLm|C*sz^Nw~3aGHxr}88;Q~idzb&!dRV#+X?r; z&4hd5R>FO7BjJ9z>9~vV0Ng`(AnqVM821m(%6&u3^p4I&?Jd(6=jY8kIzNBb#m$Gz zy0{gg<&XulXV0F#7$)`6)$?Zo9bmber@n13%B>A6cX0fgKcju=vChM-rHx)~a0i-) zf9CB5u&49bwyqw1t3Gc^7COFV_^rV{-!C^}v3RKMD|*6t^d#o{^p}as&`C?hZ_PQo z(Nk?}__l=0Wcrx`KjMe)8uVgRxK^h3z8ggou+JtQYBD8%y?+*p40Yxzf3S-X2&=hl8ysm)$Xr2RY0iCe`cxVyP7xU)f zUw7N``3Nu4AGTO=IVHL zhU$$-2jFti-@9mfLAyjP_({Y-JuFlv*6+d6m6Ie zZfnll1>WaU^%l|A9`7p#cx}GlqjIVq6j9^0}>tVyqvl${zmn zBEEd520%1lsMG7w(-r`(1&*a(zw9YK?IQgp86=EWU_DIWSUD|ivdVzOrkvuu=~ znK{bOuBeBKdMJl_C?4hgp_a6zzak~)`}k*(^F3A0aWz4>DgZfe^iHmC4y97ZWEm{O z+4=Jfz-1J&a11^)Q^*dh2w6qQ${}PUiYC)d!A^HFc*=D8QYS>QHz|e4&z5N_bGFP? zH4c|sZYp0NilrMYF&D-l8BUWiI9|K}Q)L+;WenAc^0pcz54S<`6`Ar|U6J34{FXz0 zGq%(kMOb+RIlWG%-{aysS^7;=;`@>wSr73esTkl7`ezwg-{q7-@fun%fgT}R0XM@U zh0fnEHwZ0qgnv_ib9 zHn$~T>+S8+LJ|Jw?QOsN_0ndtp^@E~IY`f~NMU7=F2^9PMs~DdReHhtASXISPN9jF zjW53qAJJ*b6rFh$(W!_|IYehYx8zv{skJIe_(DOr=)*zCZ|#(S zarYCUY}$MkJG-sng!SUq7vAi7A$rEJ*nRVfn|Uy6*h1HMj~Jc|iC&Ob|$#yjm%bmvJ* zdyK$*t$bTUw`XV%+4#Y}k4Ju!3={na-a0p5ChxZ=CWET(WT;{CmEpj9~ z%Jj;SnN~t`MXyx!N;&k3u7ZU-$)xcNzo&cMAeO~j{j=zf1D&pj z?@*y5S>jWU57&whNflIJxtvbFlA$cu8Dm^Z20W>*bb2vrIzeQYTZ8Vt>;HuNFj2eBVEdn%L2)iFmCX z*PkYn`kh_ef~kclfMMl}dbHCDFr!{Aplp=2SF}P! zD{LLDkgs+t6UEbneBdI(o%C@1AyF9VImG2&4Ty1&UVj+rjDvXHAKo>|KKig)_g|7Z zN-wR*V?`dzA&(h;X~CuC$$%;Y_a!Phb+KO>*7=ibRA^T76jzlDrW{nad_c{bd~-0x zsZUI`9WbX^JhqdSJG^WGZow89*nYLnT)4MriEf#h-JO{NeN085D*{~(fi7O6s|y4= z?T(MXM z2H~q3y+0;vk*+~(1D(3Z_QEw@HOK^gntv8m(V?oMKK2{nYJT#WBEOnnzOBE^Q(@Ez z^mWI7IRFmW?*qyO6Sh0}Piu-|&(Y?~lSd-WaS%Ur{ zFW5rU=AT8-FLHt&Pq{g9u$!Q`mdB|BckT27h%L7XJ`=9QIR_!EySa@!Io}zq$II>= zPPIVpWm3UwBB&9z#4>nk4zpmx@h0TQWeWLgDnecn@~tG~$+}wVfJ#-p7itmmW&T;> zT9eTB)=m0 z<&*r-0oQ*eRh@If34rt3P02kZHQ59Zx!=t{i`>s}av$#x(*4Fxtm|4JC7(+KTn*fE zx&LU!1b}iK%e`AK;FKOP9X-elEbhf%58uPiN=@amY;+ zf>;GF%_ktd@44J3{Z2Ez@TN??aC${ARP;hQ^n$Jg#Cjn*CLEdx^~qu2v^8+0mv%~j z)q(z5q`%!sf4nou9-*>$169IJd^${5)r zOP_~u>@2_gIP<^gfNs{;o3pQeKGR0|HJOrsRz>nFlD~B%zoxF_SbjlDzCY-nIhI$s zFFZ8F4gg%$_wufvc;WGYa$QjQkqmiFUQ@K$yi^?q36Zl0CbK?_SsIdq5RGh zP|n$%TaoOFWS2v-xpWrq*5&IcDXilQioqA1?-*Ij+D4MOX`AvvoX+y0$i_^Ax4_Vmx93=Z$D ztv=i-fY|kiD}CNRp!oA<4(|8SLfG<^|JDrq0H=PqzK_cRZNDE*K7!H(|LL6zkK@!o zG1xP#^l*Ou)?yLW*T=ZJjyT3?y%7ryv(RBiF6!>mdlSblu3ntS=Oy)N48A^@JdAE> zOW-kjFj1*Sp`3BG-{}L8kgBP#FbA}>YLGGw-{WVL>~)He z=vc1LBNw)GDx@C;ma2}be7hoUiWKh1^KZ_hTIvI>TZ@Av( zWzeqbEZ>J1=Vr(tKeMEVcEeGaUvQniFu9R4L++p;-eyDNg%!E0$lZ#6rQFpgyIkr0 zubL7g;~riDMI!&lNnr66cJ*Ea&H1f-8{o|uA}A-?=`sP(t=`{3ZC^(z-$v4g45@~&_~yoC#=XOF~dP5R&Nq#vX6I|P)~tV=4B)XF5a9Fx@IGb{Pjr54fdRlSVGoWTZ* zP@*={UnySgM`y8*ck<7Y#&?}siM`c$L_N4lQm3rtT-46G<Rlk}PlQH8@Iig>qI5tmj}L`6lELq%jPcvmM|S;b#6&gVtm{VG?eKx*s*ZfW&V z>(v8|`KrDBvn2On|19d`{Z4%pIkz=>Ti=$v%J(J5-)C4QSn}q@)Pdfhvnx-zMCJ(e zh+FAaTLjNM@3P$)Chsw=bD7sV@AX>e@`~1}Xq~O3b^LW(8Cs_<*-lf3`bg{4i4Nf% zJMrRr>U%p?v;2FB@n8N~w9f5L>%>lVG+OGskG&Z!R68`UwtS^MYl#6y3+Fvt*2A2~ zR@>Fj9+z;*Oz4G{``%}=e1(%`U2vvq(q-t%HyrUj!%oKxk!#x$Al@zY3f?U`aiPMY z2|DbUm92gY01v@l#LCv1WOD#-YLf@bkdMSCA4}vbqV(~Y*8*EDU|!)vP54loJV;*A zlaD2NMelsP(XGq6nwMx-8MCs*@2ZSh+2yxYR336Uzr^rLFIFHRu){I~&Zo69ld(htfX@PqPIl|i{O zD3?Q!bt({UTiYilim#ZSo4B(Uf5y23U+3TU~Xq5*cfW#a;_Y0w?-s(GpkqXVDUusg{`QEIE0~b-}=>_lIHZ zvo+;2+mFatE#Rjq5)I)l+vaKk@4$HBJ;4u~q<+XrYQzlH`I$KXw8cY z>M%9uKVo8jtsjs->IdZODg$z5KrY9CTx`xaI4_(Gb6y5kKT?O2fVsiiTRc!7m(mWw zGQXsEzJD(R^;u4P#9nk9sAF?pKZHSpq8y&Azs(w`Dx8Lr7ilz#S}9)Xe~ni(GGkcf zpC!h3{Ie*cZ#zYl;Y{e=o~VVmxWF~Z@~re{`qb-Pnpo7=NrEj(a-ov`P|#4ERJ_n) z{|zSR*E>0{%pEFoha4q)>n`@c!Aq7*5Zpbrb7Ox(4Dk(qF3v3jF7}siF8;lYA)X6# zEp*Y1Cgj1#uXw*Tq-z-a0Dano`cr=J{)`{IZ>$X7mBD)}4c__G`hK`tkk2O$LRq`< z?zn96zCdG%tMA^J(jkZXXBoXe?w@7!{+JuRW9LE~h->iE2u@Tue3x%m;HV58!vn9g zS$lS%V@Kf1Kq9D!C=qvpZon{1C)1^&)b(Ro4b!++A`e^ zht8{>{t_I0KW_@)CO^o3!4L8`R|fgYAYYC_Uiat1d3L=l`ujO}czs1McaPWnPD`nP zss338>sJ3PgY^WbB4VdHo}3K_YrVjtd?#lg%NndPQgerZBeS0qEa1ppmfibpeW>V* zrbuq_isVaPk=$BQBo#$c4n>l2V!(gxqS)%!FJO8t6KbHjC1wQYc_kutM*1@Bnf|>f znNK<;6T28f$&~nbZh4mT9>`EK&g7t%Ar=?-bsX{G_4>wn_F}mYx8rX`&GUj+ZoT-^ zieE9s@@21B{?jX#uT~UGMX{7av8aU-tu)joD-9WY2(^iklAfpB?e&A`kKO&V7%5-% z&!RuR;`B$6pJ8y`h-MJY6s{rmQCl%*=B_c}Z)&5zO%+CH< z?3HggB~#>v85~sf=OSpWl*5tgi3}Yh9|7dGpwW^F9T(`pAbRKDVsYg=riQ-l)zE)? zHFQTs4OP@oIn+?b9H?GYg7?jgCP?+7A9QskHe62jIz#3_yZUE|^WXkibjlr0rxZD7 z2Cm)o+Mr(1OUTRdh2eX$bc)P!;1MM&BxbhoVkqvna^0kC=QXp|Y|A*^`JQQw?|QBA zeXlj{tZ0pj)+mS8$S_{2MaXS)H_{n;UqT6mQYXrw#By!om>H{@3%x24UG*OSET#Cm zf0oq0=2T7Weu?GU20um8O=GGW-4)vMQzT!`QZ=n}E)GwE6+zp2f|lj{ z?1sFo6AaEPDYZ&pH9IAPbDRvuu8neEpr6OuDZ=s{M97@Sw&3`nxEv*-D0h*Ra~j*y zR!+C)pPK0Z#ECwZ6@Mn6T!DUnWgc6Z$ChIro3Wst7t#0g*l2MqpKSUCJNFP)Pd&%HhrygRbL>`6o#ILPb9SoVfy)ZBOK0C5qHZ~Mdb88!zmR)y6O+mxCoKD~c z+Vhs={l`aNP&xdrhgXA@ecniro_8VlN5On2KTghZ=Z5)!T)E5Ch=y2txh}J|K5^E(xtBB-hY8BBD#agAsYYovVOZ~IN_@RH6wC^#kQtU41 z7g9NqqRSxHJ!q|Lx!+HwR>88V+!~kcvN-DndZwIPEoIdzPncF2@LJ_buT_3q(JB?K zvX!(-g9vzuot6fX_H0k%dYS2DY86ScSgS1ZT0`*_XqG;ujfHpas0))n-3>Zi-jOl|`czFQWWwKXtvqw9o(Z+UF^+eSTNbJ{9d# z4(*e%&#UJ!OK2b6u2Jn1t-@CA;xz>|N!9-TSv1MF{Ih71Z<;14@`?;rWvNKGGgH3f z42>CzgrBHN6p3!qU`h7Hcw#+mV)}b0rol#ufR&F$@}rQIZ_jMuw`Vduv2;_FBYN5` zxiOhrL=u`i#Y><_=zb=Fu{We#y5R3~r})t|xqSDz-<%muGSM8Pn2)i zRxNAq%q?4xpKBT+m;3m#=GNBsdGdGq@~(F7Ao5}P^!85ZIhfANR&;bw$mh3qu3UO( zYghZRZS&_I+TGE%va5M{+x+g1&XtF@bTltnHotS}^w#F(&6Y&x^kci)7S8L0XTq{Y zM7A$Qiqkt=32Ro<+n099qYzB*IJUK$FI_6rbGb>m(NZ+`30{q*52K}kuqbjHb0a}S z=#ROvF0RsyVhJ3%WZ_^bLxT7EoW=1^ERKJ2Mb%hiT~YOkYL$&NamGO?$U)26m$tXk z);YXLo!7|Xv@3eluDSiuP7SGcvMud@k9PV~(oW9~uXZYSfX+9FaAr2tPtZ{HaYH3* z`~Myd_2;Ca{xZB8Dr37x&sJtO)ct6vx>Q5`dr8z^lZN`+@M@?U(R}d=y7>HLHq_71 zP_=PG<^R2gsJ|x-_1y4ksM?H%Dm_L$fQG6`HPpYCMExUas7=GGq3SXkN;a%ACF+0C zQ2A6t*-p{F#~8IaX{f^RYN-0+hH8}M_{@g-IU1@u)lhbP@!z7MU`J zL&*#(v!NbpU31>K@kDC5-zLfBE)6G7oHlV1HNX0wnnoRceE0IUuD0&>?)gibOU18BCf>r{uG(Z=(kA1F zSDWmf(I&EopD8E5kT!{CJ&1n|Kp>yV6}dCT%i#c(uu18EsN}cKN8ZNi=O)o^SN? z%k8R7c1qf0=i${Rdl$FKT=7E998VtWXwwF8n>| z*MjDF1*U86cB-_dBrP&^c(us>87)$J0{<(vNTjp6wpSU!x4@i?OdDP;azI9ll%Br- zx(gx_jqF`>x6?rcUsrN1vd8dhkr^2+QhM_KI9nu^k?nPwxM$KLdkwD^IWVI|N>AN? zgBEED*N3|j*X-?Vj<|QyAo~oj2019BK}yft`_UkC;|AGIEvd7NW;96Y8T%7xkZ4W5t8P18LOCF5kQu|PL1tw%Na^YN zZ_yypf_zu)cG@5ZCJl1X@M@6R#SPL_danK?8YEhc@7i7$84pexWajW{kV7&Wr1Wh4 z|Di#mrTDJe?Q{&mw;J6c2yS#8dU;yW-o~JOoz?Ite*!cs0mj84Xf;s{RxjB%Y}!A0XJy8srs8gB(7*8srrj z4N`ih{`3`_!S{b&-f|}~>v_a~U2B{xj4KgpIK}yflpXuxBYK}G5cDh5=kTgi+ z@M@4FG8&}xJbe%&NZcSezAGAxC&jj_P4&4+i!=?d7I|e+i`3{vl$o3ALtU-MEIB$H zMDp9K(wdjF$PvSmSMz%;t&>|Q{wo@5-Wzr(^hgXZdDx*b8Pu2g}w_@Rv z$nwPj`6@M12%0h4BK>G|;Agt?I`K}X=Txovp+ z>V&t8hZk=%KHOPddTRT3;cescczcLWyr zw&5+VGrZ&wa4-i|Le!u005EZ$b-gtyVgc1Pgxylr@UT*BMq zhZk=rWbn4+%&e-arK@vg?8VVBcU$+{*Cf0>VR-R&Vg_$Z&djPt2yf$l8@Ro0n|}M+ zgtsRSFW&Bu!P}A(v#OD;SWt-PWx)a9ZNu8vC9LfkUaZB9ndv#Ne$F*h-Hsw_<7ruN z2f?;s?ducPt{Psf-LaUpH6>?dRinw;Xi~O(n;W+$C9FMpc(HbJ25U=B%BseYwb7hx z`8J=E;X-aV-(5YtSi4gOYfH|_s>YJF(Ufd?zIt2R2yaMud+PAw?ampzEx9dMHIBTE zrewIuVq5d}jR|jihZk>m$>43t4YsQBbA8)=u0@eW_WRSpA62Ho{;U( z*Aja-b_BQHZ<{`QX2RLCh8Jh|&ERb5>DZ*cg|Q=VaPVN;F!t<(vF8jg#_pHF*pi!M zRXcXYPCH%o+u9}J+=Q{`4KK#dEoN+O>8aRc@xJK{y>EikOWUT;zBys-`NNB~3o=++ zdMdWlkA6f)nzOOykXx9;#j^YcX)f20%T0b)p)h#HG1Yv--!z~W6beI=m*f?Z!#7Ih zr<8bo4q_~HxL1(WqBxv;KXy%_u>SXoGk9!wq42Xa9L~XG+6#qeo>QE`lU=&G9EGjt zWWHUb<(>`jeYxDbZ^-3#{jGQa@umCi^Rq%>^Rtvs_rtx$f;&IJq2|PGx-h`Ob(__W z;*L_>roRPrShXQt6c_xF^g_C^x!j?z16_z4=kf^4GTzaJW!VAz_-QKc&M4b!!RtqY zvh0$}&HFv@VS2kN-QceRx+#i_%Cei{qWZd~kK*pGW$C{=NN*1*EKwf&DK1KHy2g!g`@8h+4AMKm)h*=948=wH9;jvRUlhbWNa+T{ zG9T>t9QLa@O1J)|ATIhW+b!bD;o3I_!t&*nF3Pt~c@@=-(uuwnm8Ds6>kbR@UEtz| zedEpP%%R&fTa{G{mq3v@i%fZsk2R+&;^Yp}EAL#s2CIz5=}DPfT!U3^W4c4ZJImK#mF1Xj z@*$ot21`B8kLe^0S3ZL!J;48EFbH^@@e}TtaR4qS`V}( z+SKwenEbP{kT1V{yYiy{ZY>{q)PJ|~MR8ibr>=txpxrDzgUM&ZCHbP=1~(`VCOeq< z4xJeC#ih4OagrWjNl$RvZc@H)piK9>@(HZv8))(Ak&b+^dMK=XiR%GetCi1SrPK0h zzHGN=keAlOV9htAGyVBGAc&D%CIavC$!!f-FR)YpyA9!JXjs1%KUiEj_ZmK7he;%gZFrG&JRO*X#kY4{HO)su5`p`maHxIL4 zrTd@Agz&}53Sf~BhtvA%yLE?oJ`*OL;jG`Y53AnLzD-#26kqYoP98TUT?v{NR*WM9_y1k2ZzK(*s z*x}qe;w;}I-8uy-C;C}>{9fQDoEN>4Ai(;Uvd6C8CJ>D)Wwa!=#=Nd)&U z!43L%GN!aa<~TbbJ>P)`&myg6^wG`s&f#W4f9gBZ<#H3=4XgZjiko?e;ud}(mz#Qz zy;Ix;D8ue=z+A+=Blevi%jNc5k;~aT;@*7~(p&G}3GN13{{9_iGNXZ?ysWvar=_E_ zWpQ`=qNU9pRlrr{<%54?&pi3`(|USOAu1>Hpc+C)>x2SkzRY^w1+o0gG0CjQS;&P| ztqIDE!>j$=$n3VeS`w;BOdI8q^za|-7`&VqRZW9et2hl_O`N?i6#j0MloCIcuutu3X)+U40&fLCknc0z)jf_*aXOKt|Xd9|;~G_)R#j>B4t zcyQx_q%Ro{=J@WlpXNUl^tb~QwfUls?k?7dKb!De+nS_r-S_4NMW{P{mNPZ6O;7r= z&QetWZ61a3oSYfjzd1?ErYnJTyi%zKzw9e%sC#^kL{A_KVOpV37!?Q%#;ncbHT%sM zY0YF@gz(5%i2v-Q8V7W3g~HQ+QJliSq16WO%)s585%-CJ?g@=MB%Rsk!QS!*jIqpD zVeKu0&~ZgL*K@3VfBgu0C>TXLg&}B{!fv5X22Nr8KMmveKOD}%6UHH~8>Z9^^qk=6s~HvOK%8Q257?;uO~UZhEpf?!dJ%-Cq&+@Ao=7fe}~Qia6+cS5}s9 z$ni?!Xdatalgjh&w~rJGzxku$6jq)N+^9I^2ga3NPp7b^H!w%(SkKL?5g?(O2l|OC zgNmEd(LNivQG2K5A=2&U^JG0?Y>{P2pqos^e0E8qJWQV~ z_9~`P(|_VHk22-)b+6P6^%GC^D&@z+~qen{ggjMAg^H#Wz(Km52*`2CL+ zr?8_tycjq5lMI|IpVkwSbP0Of5lW}9miY-MtzjNRiaD6|FJLLMykhMAJhVIbx ztZ#^XiPKQ>`^AncX&&{P!D-!0jr7jLjO%(GaRL;&END9 z4fTMJ2s?@5r)9(cH=~Rz98O>zM1Jn7$^rT3sQ$AjW1x6k=@dp~$o{q%_q#u!Tev|+ zVGQnI;jjKv=@dpufg5m&-O}U#O;de(o2DWUbo0L#6sNG}yUD472=|cES-#Ap-y`e_rqD{=6RL`vJNzCP3ti!dkw~-^{>0pg66&HK^jWPTC4qH&Ju0iza0T-!?s@ zaW}a#Ygsj}m6^EB-&CBHMQ{%|oRmdw&*8M7LF}L<+66h^MCW2N53E?23_I4}uJ#7x zNG-flBF6i{wCf#CU}VO|x;m)j)mi|>_0`liN(M_cYbJE{Qs5hgBe^X{1z{JX!Nl z7+s{^=bHg@K61{=Mn!&n9D{Hb}w7z}QKBO6@*QrNZ1?Mi33-+mR=v{MiYLrB-56`W8i ztjb`s8+Vhqw?kP;nbGnBBM@EgI_Zi~F=LDzA1zpgg0<#y8|6k0r)HSeXq#WB!wC>faK zg~@EiTYN<81Yh-r+boS3jvJURa{0CYzMvF`>K5ImO9C9`<)j;WJis+-a!-u+<#4Eh zdjc}F4`&Mz4l05?9Q?NLp|4WZ#u+{}LmlDAxudll>kkhyXw-(K&gqAC9DEc0uOSW` z#x!bOt#Mj$+^*`s&+4r>E`e{l#Om$ohA`@By@^A8p}hz0as0nW>1ap|0M<&nxc`lO zzinmJxLPjM5*_H*>lLRka8wnS#&jEg?x(j3E8Rxd;UnCPIPTxTgGZeJDXe9GV!YCY zI2&=o^oG7#OgAt|aYjeOPp8mo1a5dl^BB4%ru*&V;BAxQ6b3z(?f<;N7X?26BId}%9^$-1mbXcr$@WICy3J+eWID@S}uq~}Up11&uSFUabPdXRd zWpg#I!Lw?R@2QG2*!mK&Mwh38kTPR&&cW8dNM~`Ue9Y4s%=FmjSUzi`O$P>swZO_N z_Bl_7J0B((orkS&k}}EnQ{dG>#9-UO!TY%W8uDes{{{U|VC{c{=+~s9ENotc09|Bl zL|maoan_dFw-J}apzGrzN0XG!`W10Qw#t?kJKe57(n%&K;j;vFcl z8}^vn0D7EoLq-mJ51hPX+`fEcgO~$dKJV!ugo+zl<1IR%gfrLs!GR0#XdI=)|Mw$& z)8Pb$nfn1$)S1u>5`ndG87( zIN9gGIFie)(9Bt-gU|;*iIgtz_L&XfC-^CySzduL#wjA&NF(DvvLAGolEPR8c_S3$ zGNn@(bm-)T6I@&uXTqTn())?SY~R5%F_@{9h0O{Fi-qQ_EKLXLL2xxa9VmzJUN#(r zPJD@bPVVXH?Rzs*Kh|@db6HmW3D0$+klfJJVy-JG-fu({*X%695NCK2hsoP}{Fisc zaYKOrS9+dX)=zoc%CZie?562x94@GjWkN`t<$enP|C%byWZ+ns$&OCm1BWT-(?bp? zFmNnjM3>8ryc2SDGU+@lYo+@u&R|(L6&x!kJ?c2mSg!hWrz_}DR+X9FED{knO8kd5 z(eC5n@$*q^(bKt{!BT{oL2&>}aRet$`CR2B!SSBq*u0`H*;Mdt4HQLl^Wi~TgM_$s zkNDj@XKH9{q;d*Uxsj=>U~P8mDw_}YxOFfgG#SNd9HWnMoUJ`~zTy7^Vp4Ei4fcoAQdS}H+p%It5bn|^NoivSW z5`{qn0ov@QWA=UmEUrI4z_?Ik4&D*@>)H$~8V6gMM3^NVqy@pX^t23CO{PW$O0Ryc z@73fM1Z~r0zCDdKcl#-np#lbuVTu+R|Ia}puNRbqQQ|t(mc>`xUUPx_vd2%46G7cLl{=W}Vc4tz6Ukw=g zOQxhwkJ)>Br`!GNKisOBQwyT8n%{@@f&Y#ChbL&aiF_u})!3ER&kp=3VR#c4`Kw}c zg}z9UpC@t>TQ#B|ZG-Z%P&N`*bep4{02Ek;XB9{&xMVx>-0pLCd zdiRdFD#We2(!UejS@?^A&)x|RZ7VqUPH-nWoO?%H?q`ViT?F?|aQ7(A-ccWReggC4 zwRmgqfLn-uz2^bJJK)*}p-^tLcT7#+*IjP!6xaN5&^>PN98Q!Gl#;w7PUT|o3Y7)^ z=Z|efURGZVgJ7oO4Bq22FrhC|oWVPevS|}WBL`E)B)xyiZK|rPS+!_Su?lbUBhu^O zmWBSk;Z`cvPAyC>CzA*Cq8p$Qu&Qz>OrCYS=u4qSZ_-$bdnZ;I=rmyOh_yJZ?a#%? zP%aQY@l=>gAJw=9zY{Ad_rJrX=is+qgk@GI-3D7;a7F9x$;+7gdaa>YM!DR+STQeD z`5GcgN=>2B&tL0RKnm^NLTOj3!5cl*crA>khjc#=1Hg@L2Jeo%%oWRE5!D-ATo;G9 zLSu}Z`47asRdEJWd8@eb(*k)Nmr$(M|g(fcH2jI$@CB9pu|$2`cG zPQN~CtFn*y#Zas_kZR~&zg=IWsEzeLqH#1x3xg?tnk)W)EnuI6xia+3@k(bft37nD z;w+A^!gWr=9e|aX=Ppt@gM~egE=lj3n58_Wbo)4%>1{-j`LnnU`+D2ZU|CTUa~(Bi z6C!P8nZ~vE9IZA5bS%FzP3bH@;w)b)t2CvQxi8<;Bx@fhdx@<=LJxv*zg^hk>Ln=( zZsWoh*HxecT}DFd;y@L1k*BE%5}eDO;uFOa6DXV#Bsv}c=t34_-P1lI zx)Z4ef{mRc6!pYpAF)|c>n0nI9*gW=RKv63hWI!pgES|a}E z;L5>rDwxLsde2pgQ@Bt#8iV1+DT-6LP`Kb-g~I|H;!C zyfZrZU6+#%2GD)*`v#nan}&C`fNwC%zHUt%mudXw4v!;D`d@!YaRytxiM4zuyca-*lgR5t4K=jx8Ok)H0_$oQrLp?MgOR3a2-byAV=IM#_ctDBS+bt2B{ zX5|;0tA~|K#e(U z@k>C4TIm(md{rO)XL(eMCO>e7N1>&e{Q8}JS_iOlR$^5mwU})X$2FdHD_x0J5~rh2 z|5=uq;@BAm&am8wvvizQf1Bc{jOuQK;yD|(s#`2q7>*ea11Eyx;X@L-T+ZNwFe*+) z`|@XS{onm=qQOnDfy`abV3{Rf8^@jTPSkOK#TmT&=b=!Xz#6>wPYZ?r{fN>T%zCeX zPH{@7t3?{uV8=%h;uP*0#!cab&oOTO&YFjnZ~DzpK$xlVHv=~O524hua5I)bsXAdY z_)zTjsT&2_(8283Y*R_k#o1#nW-YKb_%nD4R=0k0i{cEnwkOv3tNmQ*j7L-y$}8iC z>sO91($}tWIL8;_)?-alyDZaN+10A@|0Xa06oyZt5rbJ*SE2COX@$Zav!YoSYzyht zLX1dPBGN93d+hb3wpfaLe0HI5?>)fDI~P~tsH^(@BNX@7kD#}VfM?q0pl&ZyoWkHV zxOg{?H8Ed>p<*Om;^=r)OW-tLo1HKjMOgP$Z>`}`7Stb4TWdy&|ED0z3MK{GZvn=9 zTH`2A-`hLla2E=sE0;T6v*sMevcBC_pmQ!Sz_2uiz*LRnaPGam<1G~^z{z~urq3?00td z-N3_?PGOV_9Ys&IxE;d7Aof3kqP&-M25TefDG#6C*u9|4ey`~nJO(o!yZu99bjll0 z&TBP2g*D%SgEX$iX@br3ODvP|XYiTFA}$75{tSM{7tDD#mowPv%`&r21CHmKht(7R z(edmQ4?Ecq>Z=XG9PBt-t@y33@tur~3MJcrpVwioo%^3F)?rGDC>zZr(*pEArv>Pj z5!T+@I~G8%Lg`uEx9X(RSNBLM&h)*l5u_-^z=MAFXjNIO zpB81P*Q4CXp;@3EF%0RdvzD+>rBMo1EU9*hflkXzab!Kc-NB&!kU-GH9BsQs+W^)oj!W1I*h12WU!Sf&Vze-k3%F_7KNc>v5IR4vJ?jHa_H)R zD4oLSx(gu+_bX0eE#FYD;;ejsJqdKuTo_3O#%J1OvaY`>)o~9QAuG7K_QVwRrzA|4y34#W@7Z)1=PeRcpcSuWMX`-+m}? zmnzO+OP7-4d~q5{akf^8Gn6@~H2UoN@A_rLDL_&G7Xoj|>DrINMZ?3L`TdkP_IbVu zt*8m2haQC%lVU1oHvy$7lMd0p17U&Eq@~9HjH_|fmBmImy0SdFH(Kd2-zyXb?k?Xe z6h;rc7_IF_YlXGv=_;h9jkqu))aTA%E2oyl(w^{Z*jY|~4W4onrnSOMEDJc;>ce`7 z^5RI$QACt=UsGP_&++{U#tu!dfqT5#a`w-_Uy9Y1k|N3t=q;|(Gn;|GXf^|X(PHa+ zErQ}=wN+2DbF~yB0lrF0G4!}E#dKHjK>Jw1e&Q9<1eYJGF!Z>VYjA_&r20@QQhg_k zQr4fivi`)yMO_9rKtcS#{KE~_@|z&DPNbu&rJej#7&jj5VdI>^Sgk-`({avVjFlXZ zU3XMi^B9n__)~i<*?G#INdT>pe&UT(oBDpt8>xm04(Kk>IqSxK{PLZlf-{}nA zdjwPyRwVf|xZ!(X@~Mh5SY~@rZ~R5L+hW{|*=P_Hg+GJogR2Moayf&U-o|}mI>9w7 z&hpp;noJEF%qSg98STF+rej=n){o1lht7RmE_11stxJJ~nVuP5_FiyKUszd~hg#k~ zk2w%CTQM+L==Rd`8BeF6GwW!Gd>uTc-}D}E4(1NYZ;sTs28&L*R&h+5!wh>8|MMp} zw1ePWdk{zd5@&oC9QZ3Z$7f4h^ta1{IP#Y`<1^!uzl>{q7TlK|4*&TRz8$7}N9RJzx777dEV)UFEGR>u15iO52W^d7EH@@43l=whJ}?olq1mqka;t@}$?b7=vm5Z$92@KARxV z_qL9q0{ys$3SsD)y(bnr79jcH?gP`?fy>8!nqxR`F;yNMmorr0fImwkhBlaq>%D%b z#Kbi?N@1S+0qT{IF-!vn193G}c54j4@AVqbEu|aVPqhVg-tz?Bkk14uMY>bZ6 zXmw6<_j_=ngPDTefuZjmPNc!|!$hbFM#RaQufm##4(3MZR-;ZNorh&L?z6-goldut zGYOb_|9P3Fr-O>Ucewc)ms513+k8B6K94=1VeFiO!R(BB4h6=VdrvKpg`;N;e-YjO z#8_Fl^#k}x;ym1nC4P0#&E*UhjdZWlg*ZDO5#d@$r}f+nqgDmM;|lW?S8zOFyB1bB z90no&q)sR+HJjc^0wKUsCC?|TFnBuFQwB$=ujV^+ucoK{MYm6Q;7SHeDWAig;BfeF zW$uT|7|U!%oz-2mvEzZYgJ@$o$?<3HAY~Su^*fUaQd$3WxI2jxrGho(nkHGfd7G-1 zk$8i(eolt_d;IWf^7rX#HHtHse6oCHneIc5-;zgPL(i&H-lXR& zF7i5_wT8Y3ukkWQe9BMd$TIdkp~V09B8FHj2ID_^TmPpVoxs4cwFTF5#wl&O-#d?gCXxp?u_Nbw)Wn(c?P4|CB~<0xP3y}fgOnHkwajatlIm;6LGGLd3dC#1=4;Vb z+U7l^^YDa|P@WqVXE4*#bGV*P`qCvzXXy|}p7Ce-%~=pHulqcnK%E5V>SpC9&gx-hWqMj> zH>}8D@D8s>r(zhq0r8IXQwI~(^Sqtz^r%uI#s?8&2Q87ooFYE>N5vT|wUS=#S`Dz& zP;h-UHPzzk{7$b!kvHd1;Xx%UP9VolbAN;W(@?#?yU-64Ysyys0uF!VN?oi;LbN*iz`+Giaz| zZN;qzGx@VPW3W;D(AA1Fm~NWvQ~Vh$RdwklIF~NzEIrZ<+)NB`4%Xrm6ZAPgUgq1_ zdRyRrV-*j4f&+6&+7kmt(%Br$Z-(eqUl@QKECq1`hQU%O!S&VTb;062S{$0FwiS7+ zUn()1A-I5+RIkORPL&_7gOl;=(X$Hdd0%H;4aTgt79~7JaRzfM@6ij0gJteuDQTV< zA9vGo>xGzs3#|6?!&RhnEJqxvor_C*`r#@oDydN8CV6?eukm4s1aV)VQRCp2M^d3P zK0L{LHo4cnYV7Fjy%v>J>Z@8$@V#1Rbhz9*;rI4-Ozs|t>_uzn;FjIVItLA9a3`G}uAkN_ zoMg(@9maYa&-fLfFhFyj+8@jg4Hfu{8R~p*doEP%9e#`FKxS)|!2kE7GT$Rk=g$4- zyS(t9KMo8$_b-Dk{!3hm10Q!(d+8&JQy8nQzscoZ-KRK%cl$A}_}V}m3`Ym=hB<0A z8A_akcl#a`!QUOu!4qDEUjAjp87%ELC#K^C)#g)RFz5KDSTrs+*RclmC>oIUP*`uw zdgu(r@%F5T&Ok$9y=ncl7{?p9zJHA36ozCT3HlQhr?8W*u^}DSe{k``U8{*hKRyV3 zyEz*t{ZQg!)4|n=_0YL`3U@10^JSQTwlW_IgLxN*;S6p9PTgYQ3FTnP!?n4!$CSsQ zF=jFk7_Sbt{y?0ygUFF<592xetMcA>X`P=jjYm$yxcXY%MFt(t>aP8taa}(}-32E+ zfZ0_qX4e&dcmRXN7zxgYPXdbLV&FU%4iB|>eI`_qv#|^w&t`BomcdeWnP)jR0M?{g zz`lIFtapf*zt0zm`Ex?N-W#S?q_KXNJt$KDdc+t&j5SQw!!+~FDcN8tQozXpz)~c^ z!F9F)3L=-gQj0?se7G}x0*9~JD(UMk^TX32iW=C%PgW6;`XD^B1Kx@4_&2|RW%JjO zzG{XFHtLVoi0e=DR8v?^D;xfQ2@JU3;T+6v_{8KG#{-YnP6mrz`!}VFaF-S1*1Nfp zbPU?qVQ-$O zU2gqVeyq116`b6%9<{6QE7qd|ziI1HfAmu}>plUMp@KV}tw#lmH$ji0NbP&J7b$~< ztF9$NobAvXZucF6UgltFr9Uc%?Y-cxi*Xb7^yefDCimB071J@Uu5|daO7DQS;Ll)b zxv3er!xU#}vt=z0E0^>NS3ctC)=M1!^G6)(PMq;T;-a1s*VWg`Aic+xMQ|vC;9OZ4 zmvv%Xts6ftsxHr0`A&5O)|oDYS#nflUs=C8%lCzybUaxXbPtCLmm#gI1?tthTA-G! z#{|h6>OJ8D>;7h4jQPT-slg6yF82Wy4<=|jH}Dh( z|HTjry!i|jc=Nduio(7RS_KXaW>gr=6)ydtNlqLh2seBQ+U^V%!oy;cxt6o{g1b%W z?7fyMz~Q~%gs!g(mx1xfMZJtGS8E;V#(-HK_j-nc`|XH==nZAuZ>OY%LIKim_uG+| zL)TawmcZTvC+~>U5}Zu%gT=Y``h9=Yp9da(`5&d6r0IWNfVH6cJ8H$BJGKh%J=MP>*5ZtTajMfPXebAB zyIQACx^+#Mjx&Zc*wRJoG^sPnhqN-|kpXlv`|tWAy!mXEc?Fwhxt1-L>%g+nDik`# zF2NG%*Nd=AaRwZ7z7%a|q3{T1X({Y7c<9b7!X5)t4;>&y+vN_&#bwxEi>TE=bv^*0 zzf^I;=2tj2<3E4R$1+{3jpC+#L2+6a#ZCR9;<2t=_5BMS-BTI32Z?K4bKbdXjD6T^50kFg80&@z&&I0JhDaT{ ztrJl#N1KY zp0e#)&$fNkMPs1T4Bf|SWiFz$Uc;Ba3bViE*8xiG3<^vd31uys1I1VT8?HzHr z0!s|Kj}~PeUb5N47KRS|e_4Hn<>Wn^yvtQHchrwrEM`P=19zIBFH1^zCxvuzcskQO zUkz^B7d~TXLjDXs@dDhs`6a~}eC8)H{d`z)23uaJAWpHiEu~dglPAr`d_`gENZEs1 zb%+9wi*MC2QoO?;lzdVaJTAbV&^S!q-UBD^h|?kv`gl?1;Wb>-bb2~e>zB1gGnVGf z(};9Ow7eC@ETRdsfQyvQU~aycJCwnkSq#;ZPG=c}Im=L7UsF9_e8LwHS=02|bfq_K zh(e4_w-(lq@BQx_#rK69`%q!I|X2x{I(MM*+boG%j9DQVn`wI-9!cj`6F!~b)=Kk4=QyBTS zVR3i8;uHo>%0yh(0^FmgYUBoAZ`Kf+VIVl=bs~iy^MwybYDDINMy!3@)>ei33X8?O z+^prD4u^LlbC3(hq3W>tqQO)hcBabUGf^O6xNbAY|d&ZK!O# z%{D=M!1~dCb$YVSDF=d&>`YZJ$Z!oCqdw=_4`=MD1*g<(+8lgh%22^AG4sGZ^o(^^ z`Yk)#W*hHaH8I~2s$h9)2J2|`!hgt0*Y}7+6&?ml&vMga{O6C01ViYiEI9v5T#17r zZxVLio>ZK|7)p=GI?QUp=xkCrb;yR@>m@ZNGUrrosO$YCYiYDF* z4yK&0hjw5d7I)_9hGWi{Ub5x-HyN1bIND!8{`|8PKz!tsyn&Wvf$z*Cxq)a z_?;d%nun;voQyx?mwHVIFZU4*6}Sn%Qga*(z8dE4weoGsb>?CD!qZ!n}Tic6{ZZue%7QoS^#)RE)=rC}OtJTMPeRj) zl;bKf2OB*mLvEv5hTqTlB4LqBCPWu@E<8@`MJBqNvLw8vRtjab_uT(ZYA zA&ZRvSU0uLv>GfoAfK#s2G^jc=;uvyIfI39=xO{}+=D-g-YHFr6W$J<(F2M3y3!de zD*F<}Svu?`cB!Gg7nLq_efe6wHurPN1u`2|W)BFD2pAWFFC6aWMuEV|3|d?Icwjm? z#%Ov-_lv0T^;$rKrJzm~8ZM7<(3W=%p7}edq}3YNU>SF-igD4nhO~tVE)R<%W0;F8 zA_|*Bi_i3MSi$uXdZ9K*=e@~yUgJ^VIB7g8`d*P^XFL9*b6NGJ+84N@;Xi-&-rm`8 zC^GnY&7B;5H@3{4DH;x4i>wbuH5=%H%M7_%kCA^MXi6K^f@}Pnm1{ekP3 zjeWtK2fCV47MjoduxeIf{NJ1!4zXG!!=ae|$mBa<5>|@X7W~hjsMx3QAGU~1moy#3 z#e~#`NQ3tpFb^>-**JK&CvDh-nsG4gI~@wt)+5a0)wX(Nu=EdboIk@&_yYRlS&B1w z$D;y!*1MSL>_k%1Dn~wJlbw9C_kWTBXiq&MzcqB69cx82$AZ!eu zsp-(ivJ$6dwzRD~kt)8UrKXX%o4r(^8}rE9;5mMM!)(9XygxR$BE9V?k2+jC+dyz{ zOJ1q^yFC?DfE>^ZE_^X5Y4TJH9MzK^Cspj9%CeJ}AVh5ISrhl1~$p@&Ns2u^Ri{`Iqc^P5sb}m4 z?1@R|zA>hI_DKJoT7@;e%}YpUuresb4Y|&$`C8h>HO9qN6rwk7(dMANGeWm~!*3P= zMY-A(TwHRbip$2seG3^XxVQwXNBnW`b<<_|k0stsuNPDTQ@7hGX@kd{iZ;U7!=J(I znEGvWpAI{hUD085JofPPmo=`z688wjSsbm9;w)_{0L#PT2u|XHSFjdxxi1#;Dp<%h zUIh!e*c)RiLwES)s{<9)AGnLqlEF`Sbq)THMcuIWBsd4}ilxiv7Ael)G1xaBoTNB| zS@wQW3O*gF_d~^WLwEfD!oCGg>#AD&ebq3$Ap$CiNr4QANW=Z&g%J?Q3ku?;R8+iV z%Al#4W?6drb*N)y9kYJlIbQPE$1n^2qtfaChUe(($Yo5j@BqrPOXyN?M6XPoF2Jeozq4$ z$>oRE@j2HdK^t0^_Rh7u!hHuUnJ+1aEU?z44wGof-EJ6h^?JFTv-~OuH!?TGcvF2L}?Y#vXXTKF+qg1$|x>f z;Ft0Q5r!P_Wk=_DVhQzg%BS(}*aM(Bze>e;cWe+@`=b0A_gj)JA!DacpN@|fjNXox z6-7L`CDV*UzQJGiH{u%Ptx@S3JKv~QQiWx7U(-ts$`#Wquy^L}z8CnV2)uf9=Hpqo z^S+}6euWYPv2*5S#FX4fb(lt&ty)~g9T^GFJrHKxwF+xI3sXuye`)M^`#KyNE!IzR z-eB{^G}@VYFai~cd5B_|K`q2jKJgunl7e#a7jpp5I*4d?k4d)wC7QAQL)y5(JmxDN z%X`Llb!L6E_jq8ZblE=GcRn%ub;dkail{*2j? zc0gzObKD`9l!oIG_wwg3?3fjn)=cQ{|H=A`T}(8Y>fVH+WJv4dO(^-bI}>W29X~><*kwwemJ!QbvPwNA@*bUQl7aI{J#c=5hI|Gs^6Na|i=NPV zi!`=Kuaq~m)G{7_rfP)R$cqp;&gd?liUx_TSoh+*b;QPFaako7nP>?Xt@kJ~UtV{5 zxJX^=@^k}M0T_LGS@IxBPmF+}&tSllBw)<;wR>^$m)r-hM;nhE@@GtczRA{M`9Rf< z_3~#t{V&jnKZ#~c?dwV!X@8{k+=`mgquZ7=_%ddxxNk8pd{k@8YNcV!`=qvGXwIK8 zOUhSTI-e>5`LjE<#r~Y0%0T|iYgpb(GL3m6&3UtoR1EaTBd;-Fd{mmTD`+S>8g%78 zI~Q zZ;W2!=ef^vri!uueiBaiO?j%juxB~+=K`^Z{!Fp^CI?B}CilqI3!)j@f7q1Ko&7@G zFb({R4!L+Xo+K1=_sqP3W2kCcXK}H&ZORdO=SN{vc4Kyyw}`n88TbEuVN)hd-P%4v zJlh{>-81WHyv=FHOQIQ%xD-0Sw`j)HOW)q?c$6Xevpe;+^hX}(PrRU|LNigR{4%Sf zWmPm(mQ~SESun*->`5I%&;yYODt?b(66R}rZb*znFb9iihlvcOM#wlaSJ2q_L`EVk zjljssV_64TIxzUU$|)^og|t4VwB*TZjt^S}^) z?6bIz!)JwkF^e&m6@HhpZA|_5&3netlYf@6am*WL_S($Op^)9}sA$D{AjWs>={r~F zUNzXUPkhlubFXG^v7@0s&bOR!Ja;Zkh>_GYnFBV8cOs9Q^Gtx- z$ss$>1lTLSe?^e62Z7mArGn*`KfBv4N@PlOBEMGJ%oB!SEcWu$WlFnab8+32jizM< zt$!qwf+HGK8lUlCnjM?L!#VoWC-0W(ctdL3xh#cEVYqnhSM-dzXzs-?W5>bJPLFrA zZ@EwL8IQ$i+Lnp2dFm;O;NjWc#ZWxE^{HCz8|U?!`$Aj9UzFKaeE*J&MM1##Y4q(- z^i`{UXBj2{G02b`X*tZusi<D>_Q0)K=`Wq%DnK7(L&@cLds^Qxh#=ZkKweNi^dTx8%uBV@^DJ z^3!-k69!9HE37dKr>#(CVk(bl=@QS#%{t`<9Z%)zTJ76+L*Di0)NIAwmzQ6i$70jB zNyVn`W0hq2p7KWH+w=6=7 z5yp-&O7x?6_x=f`Ys~#J?@wA{Jo#}9c>YR%m=aEy8`ip_Rnq1)V)IFV4!b{0*3Em7 z!hJWw+{69iy`mXMseHW;+P~M+con8@5XQoO!VJ58viv!oDA5#O&=611QhW|Wn!@7f zRO8Yp_uphKX4%~d-6(cWp3AceI8^#t-KmHEDf#e>K&V*WJQ=<*E3Z)U#{*3VVFRMw zNOhP|pF}GYjVJc|C4AbXe16;b`g0M->59+zMugkX%9J#H}X`HLs7V{0*2$Arv*stw_!Tr$a^I&jaH0DQl3+J%hq~-XG zC+rF92qnRvF)L&Hzt+!#j{TbuD z(Ir?qd0sSOnJC`aRYyx{m}m0jjd8|f(arVjxlY(+%2X^P8q1cI^Uem-GH^br2g0M~zkvQGxRZHUoe+{j?mGNOkG2tlHf%P=<$% z4|7p}M%WAK&p4IpiauyxuBUau7}er8y0XA2Y?6!lABo!9!*jwTugu1VG2eaGNjr2+ z2~+F5jny>1OTA?yc|m>?=5|c)1vhpX(4XZITAt)$d2l{Ta&g{M`6d~JMnhdgqeBK9 zFU5k$hTPLp+ir)-7nj+knf%`m%F9Z-ks15M_bUi-V4?-qcu5zv8p9td)$a!-e}O?m z1rsgo$CyX^UFOI3@wU}IfBX}j>Ad|J=E7aPdXdQg@M&rS*P%pxsWQuic_ z58v4ogK?}<(B-@h9p8~rRqs8LUMVPd-mxk6~3sDS_ zI$yxb%SWL^i=*T%iI%J)hZ(sE7S$>8XMEZW*m_?T&G-h)P5Fqr@eN0V z_FMTgc3NqO6h>BS&fOX?gP{azd~9SotUj$1FPQ)e?(oPaf{SRF)e7=P=Txx3nz$vaAE_|~g4ORZ-* zNb&~_--?kIwYp=pXu{H5FSk*1w|>7?yZzN{ZV7|-L^er;@i$B%y%3x69#_HCNam4o zh$$6y9qn%MqIh89fX9tpq8aaTIBGA9dj5=uJ(bS`7&8s#n?I))#gftu8qy0|q#Ly( z3hMc+I*>o-Qre3XDCbM3o2Iht7AggdMp@wS#G;+7Tn3KjbVzpJJA<*!MO^ zaw#VesI~aXC%){2TssmT{AjjjjVWeN0vJ=|b&~+W(F?hDd`7CgenMUCFjK|V$tD%s zU6Grp9gB09kT#96!mXd6+OfV#*&$1c<>v@cJy&r4oo;ia;yCH&>q5K?t0O9n-FpMd!RnPVc)b_g#l8+&JTS$ z?htoM!|?h0(dd21mwzsE=S|bq^pPSQm6H4RY#tYWH$mO?W4Aje9NK4IyG@L zG}LavW(u=EHGGNu88?iqRE|K2@@IVZ#kc|})gt4YP$$R7coj7(;ps>ZEMt+ z-FA7BkeFS#XsJI5F8?SlnfA4+F%Wxu(2i3T|&sXW`@92OnX z{^Z-KsFG~CiZm%2k1r?|QtY0(7>tWZi!Npu45rmMW;IJR;acsJJJ{8TCXC5Yn95qm zHpU3`qU_I@OJd%sVH~fgJjVDS1K8IafWx+rijdOnj z#L}Fuag<(kF*yzH_|)6*+Q~^gcneDY0P$xWmHipfjF~Q9RN>G3$JiwDA=%Sig(`pM zA+#oViAo+i^K#Z~7V@3-UE2k!niGcARdQ5V{^S{kA6teyL}NvsFwmhyV}+Xh;Y5QQ ze-6VbHFs^s*PolaHe*hy9rk7ftr&Ak?TGzEGj>|3@=l`bD>;jDypks@j%=h@!3{P zW}Efmo}*%Dv*{$&x=m?R9U6#ovoVK7FLHby0%ZDXrfCnR@Y`4yEbAz z9p_19V_u5k$zo$_@V3not+9C`)nQ5FB^LaZ{(R?>-IEn9LxpQ>9zD>E_6*N>4 z4%54fr=_u(l(PWk%VGyfdgYu$>dX}wk$fLx{0&Sc6d{MA54FU35#y1qj;u|83shXaaH!Z}TRNU@VUHh|p6ifJvrZo!X&slXS z*gFyG$-KYeA~lGU4z6ojOXJ~5%^F#I*tAYUYZc#vnH@E)lhF{_jWo_0G0bT*EZU5( zhoP`f8Vwk8rsxPXrTiIlrs#-%iI#8}57Fo~H%|HpBC1rjD2L4V2(&P_BZtMvpCmM+ z?d9DQBc(3ovOq-X(6zYETJ{oX^BLUHh#i(DmjI}B{IXPe1$NsV_FvL;kjRg1@=y^m zPpSH`P2*k1Ve#u4rNPCer_lHHMdM@kSI+H zskk5YLuz(57tc6+SQ+kqChrF_sVz@=gT**eU##d)Rlv;+`4Ng#eWPfw0fTpSTe!mM zk=$e%#Ur_Ut99HwE(tQipdt8`NK0BB_Ke*8l+-569`XS+7ojkJ2*iQaHq)*W+E*eT}X zp}f1)b*{KbWwg>QFR-+t6vNu1C75y_ccDAoH%WJ#A?i*K^ADvAB^t|8$D^fN@65x= z1+2wsZ>h1$QhU1{H}vTg(35c_ECFduXLsn|>FD9^Qo6$Or|UJdzi2>ik-sPeSlLks ziD$WsrWt6*Bbwu*zs;zsp(ioEH2)SG)8HGJ(U<*qZWqxAQ+diKIZ@Z5%PjWRp{kKo znwQZNI5587KqS#h8zYx1pwVG(WXwrk-~M169pE5xs7YYD^HNex7H3R~6On7M9Vqqj&PfJV)y1}ey(v7#m=*_px7c5y_VyPifNE^EHC&d%HusiTNnS7rl! zyzI=)#nV@|MvE(&oSULa+K;I_6`GbvZ53%qgW9=OY5D3UxzqH-1<+U0moZLMp?~lz z&B7YBKYoM!aWwz<4O)irTQpo&A?A|HFQFOy8T0)ay|04WlQ4N|U0LsMFw(U@W15kh z50XEJjT1??ie~IQlIpNLpW@{q<0!FclOz}NpfXT=PLF1*({-3A

*QYn1VuS?gFR zcS6#|J82io*lgIf&TQRXNy#%z&?B?r(KH?PwnNDuP05B1(dfpX!*GGqCaN(PILALK zf5z7#j!}OV&Dim#N)%1fUvqX2(=fH|r96PcoCoF7Yd~qA_+kv-^I%NEd~n!X;fyI} z4JZ+1!it(ahIoUYzh!=qc+8=6<^lF6B$N@=I`O7afjlD+w6&aY`S1>hk~k=a(J3an z@#ioHyolxUlSMP;s@dD$7R{KeW}~kV&6q1>!@ET@c3SBD8Yjlve^cmThjPgV2}(uA zJGbRr4pr0Dd3-i!M`>3qlZIaVQN4i33Gpeu546;$#__m9G~6eaMJ>%VZM|l(wcRF-&3j>@N%`Z1J!;tLC~ZFrD+Fdz5mI7BpKKJ)3j9gL^{vEV%6;PxnmH4e^$ z)~r*I|0AZ!%49WL`CDYogg7uhMh{HKwlm2)q4}R{MB;*by^fj($!wsVP45DzTBqtzM90rSkXOP(aktP^`!e zh0Ey4ENU0XJz4!QjYm$m&&$PDHWVum?>E47GAoUFb(60QGiJuOqu1ll{-VK10yGX` zJX!B=7-rpk;=(wDagY2tOb9TAwR;FF`7;m762tO5XH?R6BrH~TN(NnXd5*}!x;IM( zQ~XS>JX)0Mssh9Ln}}oa#yosq5(@ zJNAr*1gw{fhr|EoP)tDcf1|%38r}GFm_zr<3x&p~K_SL(kw4?>z79j`H=-Fwul@zn z7R@>3#QA#Yr#t88Sg~04>8NFVM`7Kyb@?f@t#g}hLtN4#v#dcu6 z8qM+|u)Wi`sHiy85@}U#A(N)D#cdsrNHG5G*`bs$?L)sSY`n*I&|-9j(NMx{vD#OO z>pB|jJpRHRm@S&$?RA)-Mc8A{YrZs|_o!BT7uMpu-4-SZo6B-OD_KNQtcxLa%<^fy zHe>E+_8xv?w!WI-k;zW1sL8e4s!23xA@3fM&w@Vgiz;8t2SNa`E;YR=Yl$&R|i`i+< zRxT*cR5qwF?OL0c7%j?TE8A50Di_{j-g>lVaHRV*7qOS(7;8FkA(@!bU>Mu|mX zn3rJbm6WuwM5tYh#)-w14BH&Myf5>DszH5ec_iC@B%#4*spVymRL|uT&h2ns!uT?d z-Al=|HD+7WQcM04R@9``-!U;EIO~@=^YFFU@I6qH?JTZSexG6w`}I|{rr(34&}W5d zLKERN2TA^td)S@hL=%S6oI!~ytT4hx9He2i6ASg#_lre}1T~8VSx(cqvJJ?!$Zb?{ z@x;+8lX8UJUkNKd#QQ@O_qs$2tm1S{kUQFx?}9#0{)FXEBXPS+Rkp2>zqqV6^Vqw=fTU}#mba{I6rrb`CSDRl> zqhgwaKNe;?)QbZF8)3$Sv5>HFx%?UPK4HHFU`*9(y-EHYcG!22x4T6%W>=&IH>h$7 zLlt#cyR&QuiMo$3e|D!}<&UpVhhX>0f}JUGmFxFzo{C4&i{_~vh9GZUQ{Bm! zm;c$MGLEdk=;hBiSPUAMG4yQ@D`8_6j|b$& zikkj-1r`U!)d6CMi9nxd2bS+jl5`G8#VtJMuqjV0pv>v3HapjpFxVU)zJEuzn<}pH z;q$QCIgrf2JzP65;{szv-NO&f z%Vp05rPkH*2ny`mWhKS851MZMoID^q_& z4rMBDVJ8V{Qr^OD%_-(+7f6U5YqIfDC=+jC=OCr)Trp!DN-!@o&1Lk#FG1LQi)Kvb zJJ!^PrGohucE`ubo4-fzjUj%*p`0(b$Dh*(0c}h)3JW-dRnThGSvDLgtkVl&MY>V*qS+jrH62Au)hZvZJS^3`L-XQk zvMc2ib0Jf5mtxFGU606(hyBt66U-DQOupI=RbGrk`-6sFZ)!B9Lo$nV)Hsv_1hd$f zClYp5lx*4C&P0ga@QndN#*rMWI)28HbkLA=+^t^SKPNp>9d3D~#z~Lu)eg{-X*&@i zF2|R0#?Sb`Z$mo25Y0GP7%Q4_uoJW>Eof<_dO+sK?c`f|9mM<`l5NRUTG7e9h3tO@ z+PG5b81ptkpT01T(+e*peqdO>0vvoDQt${IJO&NDuuAK|%;H3qR?F(V#}FijX)TWZ z7p2v*8X+#SQIIi{u6rhKprau>97%?v49!WSSD}WMv$rInQgjy6^hK-PxkB@lo|EUC zCGpq~c&avI*1^tuBne|h9qdesMaSUi1DPYVP1K6gC^1L(H z_oKbsAeu34%kK5{w0>h@@!TbvG5vMiUGI;tEbd4$FdhMm%VCXag=x1pxK21q>=?yo z9+XMZ>>j09_#+R>CjH^jK>WXYa4t-ErTEIz;1*2LnH6frqu?ADcoN)rA7t1kW{g7! zspB#ZW`c(0b~5w9%*;qJQ#RLTrZ7VaX4qU0_;hZrjr(J^!M2=nFtCPFKp2(|a4-`z z><9+EdPru*6|lJH&de0+Q>itI3V5ZM>6pbNGLFRVO*AG990>=Fqa$`A)!{j5h?irY z^1eZm&ceT@yfhYauupuup{=2D#`t2=;hoTGV|*c-?y#|q@r|g-BFv)c_*6e6ZkR?t zHOu9A1SB@g<#@!hDHb}ZTc}~%iy=yXrs4STg&pqkh%p;)k26f8J??C@q#guA^j++Er5* zVeI2d%kr z+VrTRBXinpNYPPt6gz%MVn;bHcT1^O$R`^23PP+@GRDzhjT6mS(U6ulbDVHIaP`of z{2cI!{FJluPQD@63`m1N`NX%15ZDUD7bwQ`(pG`7$A5#f|HkR*MRmMzf8sMkk(q* ze`#Sy7;fP|xPkE%1Bua@ouidVxfbi$-{Krkn5OoL?+@{Bi;@<`9PJ%mOf^Q*4}zWO zu#Lse=Fm}Ne32E=V9m#7h3c5hBI*N`x!l)ey(?DCit?-Nj`BMaH7`{K;}PSL)R|-( zhba;c9hxqhap+Ufnxpg%%e-*q2)#o&mFLBzVuxxfJ^2LZXwf_kE{xXTRFAQY5i@!R z?Xfh*7dj^zbSX6Z@XQV3rG|7A;|lB275PdANP{{epZKEBR)e4dXuCoM&~`=g7w*ud z-?`m4#v))>u}BygH0;glStJY$1=xlhk5PQWPKz|;B-TmB_0CB#lZ4F0oc(}&^-57I zI<_JgpRCVG=Ku#uISF^rpoTgfYm6^yMdtwei#8+5`H0Mq+l=C@%}8}gecaPQ?c_t! z;|@fw-DV^_bQ;=>uQDCXDksby&i8Z}v$qp1_=%=}eCB6fYMF}DgXX7LA`bc3C-`BU z>y)Cz7mH>bJVdL3ERr|i;3sG(E!KtVM>03)FWJ7AXBk~u{j=T`Jwf~P2=QZc zlcbM1wkTlRCCQz81#CYWb66IF?RS>8#DU{iT&35 z^B@W&w%V;P^}a8dIc>ckLB59`Y7OI-h0w}zc7zel?(7BV*4L9tQLGa(C-|Gum+Kzp zq!F@i6DcIU(ZuVUcO*#2qS#B<>g(DX2YCuXj^JFIwF$%D*Z zFDpsgI4RGYK0W?rOWJW8Xs}KA<*GRn z`L#QfY1T^h%1i70r0wX)Tvs_^kExFr`*_kvcTIeY` z?ftYTx7_Uk(u~&;U$4_&_KGjr-Jo>1OOmI)6h<_=+YNhqxT9ylsi!Ypuz2b0g(odO zb?M>-^QzTF7oK;)wLD-G7tdFxX2wP%R&-?La1Sk3*c9t`nnj!&bJStXjV{gZa``~?$OFDHCt>4nYboqySd@g!$;nwVpsjh-Wv{g}L-KU+H9 zzA!U4N2KyW@@pC&6%K<9U;Z41+l>9#uCe2wzmleh ziDftAL=#-A)3d0-I&;%r^d;U-wSSNeD^T~aQF>m&EUt-L|rf;N*Z_J$wp2IL^ zyRI#UYU7F7#*3Dph9~bcGVcSVlqK(O3W_O;Fc0k$Uz`Xq@5ZrjZ4d>g&CFa~;oXti z#FBBe4y)wPI9idQfzQQPpTGQ)tFF560{E%U%sPV&JlxY>&WP_1jfMGCE8ZFNG+yzH z>mEu>ff32$V18YqCA`LBFM?r3j6=6mgo?VtWQZyh$`(V3lD(B6IF zX=QGuJap=x$HR#o`9z4XxoJ0swG8`I^N_~)8}{kuu#AlHeaV|7+$hfUl+KrM?s z*>3fUIdr!6_{k?GH+O+l9umzsTCV#q{jrx3)Xo;uJ<|vE&mW zc0-6+O2c@MqoJ~EMKj)Kk32(e96YTq_yZ39f(A972)F97nM2NPK{73K^L&KWczw2> z6NmDN5Z59^^bsn6R&>3g`Rh~4;f`kK4D4dLl{8}%9D4SiJAnf`4*CO!A;a0dIh>yN z&87*tmg3&#P^FX?j1ahGvIWKsf0Rkf+4!P|;Wuc>J>G`o=|a}gip=euy9cwZnPF7hmKXYL)LPJ5bieJ~ z0i$ZRyx<^A*Y5aY4tm2Qi5A%YNdq@i@u?n{xnci!Cu;50S=Q!eW0rNYRpe81WvaC) z_Ko;50~?u&-7y>fP3*zHfD~h$wU-Qybv|D&2^u?Ih6UF#doZsz*Tr#dcl0;!B*T=y zOEg+{TN52AN-a9lRC*lE(|zplT<4ALACskv7M{Lz+0sTZR-K z=?8tGT*`ZNlG@5Mk0~S2HT114w|6>-XmaP#WH5J}Xu>*@?1vh8BzfzzI+Ep@h~9xe2-_q^zxv$M;UT zc!ka>_wfRKq>RRsgK0lQ7qO$W32vj)$?kST${OaMkW=>RZDGH7_4a}Hcv)+ux@eD0 z*|2rP-eoh-FMsT|>25cs9ERM9y;CmEKse<-M#by`yFZ5*cPM7260zT(QpPuE$=z1v3e=577N1Sh!1=%yc{) z{Plzh2GO$cXB;9dXbdA3=cT8UG=gNN9GYRrK@%oV`aX#y&*I#pv!>H@ z5=o($Ql%14f@8p9H`16}hMA5w(N{_uFTOmFN{wf&zy{}A7_w3^cD%|>bn++X+@L~o z1XdmuJ`p!Ita-28$TI?sK%n7~Q00LCt=uS-Xq@<3dof~4ZlpR)15AERQ((xIF!z1= zW)ow^@vGZ%e8i4dxd{X6l-{{17I{v>jq4BoKXbDfoE?nZq}8$^KU8iMDyO~{Wn;I< zO$sv^;`8QU#430%{X#{c$J%|GmCO=j)V$hpwn?}HVPKjYA+nx zcW&$%-}m9)48{uIAE0lC67AJ7EE~ItrZC6}67@L-Vc4)|LOKV?pD<{M<0(jvX$WKI zX2eSx>rFI1i+ks0c{aFCuGOB$SZSwvgLZ+jM%I_3W~1kFm;3xM6Jr|Cum)x)9?NkzKQlSx;~bdLW!fu;me?fn`jCHI}LHHi%!@W9s87gQ;l%q{AGs4 z?C<1g1(syaJ;E<8jbt;2rntSh9=Tw<6;-o_{Ayx8Eer;m$Tne$NnGjh(|XVm9>38rg1d*wXpcj{wi;S1B)IUkIBN|t7@xl}0mi zQ5yy;tT1;Kxb_%xuEw>;IOQBAmvWAlqf$L9=iGf^ea_E>WEz6j&{ zU9^rVKH-$}pU_{FIm)I|Jv-+dZTm}?A_w(3M{S!13%Rd;!T#|*%Q=VdtLWRIm>QNR zH?me_H*%^lDd&HnuZ;KpgziTp)p+9LmPVyw-1wSvjzjSYH=+hA=b$C*^y8ZDxV52r zPR{rsSw!W|xsTUsKiv~~8eKP4k!(KBYjkkxr5oRs;{2!Jo)(cpiT3#3uwc>F$W1hb zL94h4W%)JHglo0`_yTH0^!diM+QUa>t5z5^#A~Zo7}AQg7+>@3*-eX;$EC{S?x3#J zWp|?bJm`ofcru?qx#K1O_w|*p=FdoEchtUeazNkxnflU}{z8~n% zD6FvL;;qh(m0ELY_A8o6-F9)ET4Oj$#b~*&&_h;o z=xb;3WP?e?RdHxVW4Zr{BIMyx$F9#7G}v79*ZD$0!<)isCUVoRw({i6gM)9=V=Nyq%sSLy@{g0RfqL|vA5Y1Tpi*_PP3cNC+hKQ69aufvf8o5B{*d=0=q8%6=PEwJ|26WPHH-#3R-nS+-tP^mCG)>bm=7*kfdvd7plKJ zFWUq+*J{_G&)mrvLeIr{^z!I!e@0@@_+DpA$hcPf>^$_>$-)t?)$V~rd>gDVu7|ua z(~O5hyB~`N5F=k`_fx=q(df465%MB`#GKymIm(-`*r%`NsrX;@{G8=uAT&%Fmz%vY z;9zy_d@#>+7xNUnb&GQoJqL~w-Ur&!bKof9D0Nt4{2421Qktj6NxR8_)n%EZCUI0= zaBcIXcznCyh}*h&(#YGojQgL2t}mG##^l0JEf`1Jgu23soC(?)dO>DqoY*NJEg^>x zPhC1t=glZN~dx*U4|c!(>n`6DA9Fmr300sOgJaI*|2B^+K`3#R`;Ytb7-T zGRLYKln*bX=0r<+Kt5Gln6WKr^t!hr0d^%{|*BKU9 zb|pOQJMfoO);Rj}1L(`~;EV29@u}l!g}Yd#zt}H%7Pf$nKXwVW(7-$^?pYg%&@jTw zvvDLL!tDch-lJ=;hyWt?!31VzdrufKCU^J`H_+Z|TgL87hH_Rh|{*(<&mz~Zo%uViB*q}$)9aS>P8D!Rnum*#Bgomdcdlqmo7ee#qmp1hH=WW6Hi*PdX>?< zV$sUgtCkw0>+23&ykgD%M(w!jnsL?R>c-c_I(shhSZwX;nk9(@v|R6itXjKvZTs;j zEo(n%#nG$Um#;W}89637vksp=drHf!)>-XyTc$V9mkp=f+GwpFhJpRTV~E`oiUx#4$vxJdg9DO zT4qn2*)#==%ZzeHQ(LogYG@U!U;5gFqXtqfBaDmdO=la*PK(r|9_yYtabb1!k*KoDB)Ouxy{7&6lh?G@%Kz*5e@rCb zv&dXk-B3Rsq7S;D2CQmonuv%eUjzYa<~#%}`K1M-YSqlur#7uVe%7+%AwArX(45I_ zO|#mkw^t{VFqG|HHQsOc&a?hhpv>wM#~+O}= zZbV`UDt_6LKu|Gis->+X0K*_vdmWNjBwug=4Ny=_c%L|-#JJo1?Ml23HT7C$cwGW&lJ9y7p4Y;7G*kn6+bDq=p>*>QT7sAy<^>WmBB`_)0MOD% z#h*J-sG$MS4_*mW59miXfLhzfC)%t1Mt;SL;EDFS@#EY5_D^jF4g&&5dhMA*hZI3Zn| zgm>P@UV!*^Xv0u7qc-1C0w9&n!$C((t8ZVtbZOvb&Mal3&d=>AREzkfb}&jHgd=sJ z8-?nsQS(WqQVs2`?TD!gb!v(gm9K4p{4bmUl9F|est;1T8DZ5{m-Wq0!-BO**yn|S zACnhYo^2!h>+7W0I4btCM{n(g7{fLy=j(WOyt)9Y3;4;b+y{% z{;d`jF8HjhlyasWA=9TtaLzCNeW3OythNz zH?zl75-P^ED6=?%u*|!5Afd{nu2o1wEk=~&ci^ImMvNk+I zpv>m3y5^9#m8Gs_;k`UX(1u-o28XiY{xyf&5w4O!`=#OvZ)|Hhq=i%0?>xyuGY-bq$BQ|1%W9_-(L!283og>Kfi`=fm`RM^C~HoQ~ES>biZ=(qr3Mq2nq* z&LMxce1c|Oi)*w@LoNOIlj{>S{#wT;IP|}QYlzj<%HjPRTT=B>Kf`~jBY}n*YPkg0 zQYDu_SK2;7v9ov`h{@`dH>`H!VYYL5;8ewUQcAjQx3brJFv=vp|$majSr)sds6sb9$;?>qu z%O0+#Xv+XwQ?w=F_*4UfHC9s`?NXCHpI1*i=Yf#k%JFltp{N?pxv3?NPc?F2Z*&z^ zThEwfe5$6NHJs)tUJZ37zj1sjL944=pQ@2*VQPvxe{N`sJ}h!H#aK7FK9y*M+hXkj#eVfj3{w%=J%;8DxYV8IelZ0D~XO)-8WElts%Jxon8e)~F_Vq4}xP)lQy z)XpZU6*YR!NiDM^P#*y83TO;~$qpq}$>8i{t7|#;q*@$B)g@@s09R4tWv^g@@96Ut zLYL-RN~R8hM_Sv8q6!1cbtS(p2=fY00`;{GYPH$U0<{d|a#M2jQWHa$0{pTn+)VjX zJYP`mOaPqVNT5WJ0UT#aT(3Mjdw%9d0jaTuvAjazb=vIIF-Cjg`F&)v2};XN#U?%IgvtbnxWA z0kaDv>KKY^d@4F+tB6wHQJ#{m;Iim>W(iZa7rpMN#N`~;YE;Nq>u%QBGZ9SLGb5fV zLwFP5e6t^J4HJ8|Tge5yx(`_ATk`)Lzl_|>qKa{r4=4jv4vEw;W>hX32-L8nUnZ$= zAlLdxB#CKa@<(4yIMB@Xkwn7pBCz3DzjUHH;n$?h=xD?r8@<4N-0jw*+$es22`YSS;vhwgSNL0w+e z+u2iR`Gq8)nvvttT(1JBJN0e}94W+nx=0raE#Q(SHMFD@fXkr;-bP0ptdu)@eq&bP zau;=3*QG`Ymy1Ho5S=}%oDy7yt2W4vJ?%5v1j6HQb6FU zX-xC}`|poCh&wxw9k3vCCWSSlLLNFGoa%6?7-@+~OfQ=j08&`e$2xm{>B}KQY+JMa zrt$}6-}?G%yTDiVk3BOm0F~9>+zZYSST->x-uj?GHPTEeChe(zha$4@B$$jsZ=Dq{ zl^fkOwi)hEqPx)feaIfu!=OS?1no2SOxo?Yi6UeLa7Rkd>j(m+gRGsFp#CCgLF@N zF^R>%tG^|#t7l9Cjj~v8P)x>Hm1t-stm0Uip2~QZK0OyLt&H_#>HPRWhD!hXoLnNist^a{vcvLHMUK$8(KPIA{er z{oh{AVD{+Li*%ocKeBG$Fsab5%X`Ds3{{j4(vUICE;PJDTL#mXF)~@N3*{jut5V{A zQlQMR9Z*D7rdr;QLZ3O?Z~|>d8>mrCMy3Ayz*;I$`qfxS8{S%-kLWM!3haQ&aa|p~ zC?rr~Yrm4nxGJk_SQf1gJ)T33@{Qe}fq)M0QY%vHm~d#861va&vYma(`rWktmaeEK zRYgRB4y%m+^HJOUc|aR?W*GDO4Y^94GMU!)Rx(&w#7*TR68#KTCKE60vNC*Kr8;zg zWX@mK0cOyE72%J1({N7QS5z^IoXe`2pzNH1ZH)UmFT#;wC#sgiN?wBvr_fHCQqlM8 zZzapuFKtvEy|ZU;hm3hMo7-1#pLmWza{i2&yhF@qIr3J@-T(s>QnneP+j)bevu78N zm{i35{hn?>a$m5o5s+MY?&$?2_Y`XRF3WP~G1%2yY8n;Fa_RZ8t(hyhL;ehus+KGI zeN0VpS-roZDb_hUp!j%d6j-Vp4Nz-+8o*~g`?#8i`wGeD98g^A&T5{)wXR9#+$pUP z{G}(ar%BwF*G*0BtCp>S+~?#SJ!krySuM>FJyx=n7Wotck2W9>tMVZ}MEKYU0sqOv zbA(jot%%IzP@)yBQ-gahojpfF#Mjg6Kj3KbA`n!kvTg*ZF9S=Vs^{Sw$|wrr$OR+3vpOF`|uo}<7Ytx;=HM_nF(O{Y!v(z zue2uK78>D30EFu-hn;Xo96e})4IerncAv#edf$_mjOczYE|sAxn1bpKn>2g{bA3Os zHJ{HL5_U*4WC<&znQR9*A ztsU=|_1@P=o!0h};mg#r#0Jf;)%@pepI;;SMnI{MdG9+uQmsq8XaN~8v-z+#bj0LK zq!{-E%YSMIlq}!bGtWmL?T;4IT_r<=!`vsKgx^d#LrYANkNIbsA+4TQKW77xHcWwr zUJ$h5u(m0_hR4a@d}i}#WCNm{+QyR-9I}?QFI%-}@$t*raU%+YE(NRDIh1wDFRTCv zB$55e&jI^_0nUt_=TzeImg#V}k|Af$z3e_1RCT=52ZMFL3|!aEAbXnhy?w-$z$6^@ zVJ6G$d)5JlUVkXh?QF8700k@=Eb3zEleq?CUH+HDvPnw99;2fQ^qyT7CE0M#DD8d1Fds`z*QMfY%$G;x+yIVH6@0V&hZ_DPiV-gXrM zll(@0N+TRCQ;!=yzk$?aAfyA0GD9@4(J$+5)cgjm?HR`}ftd(7Wd)R~&D)?6JsPK; z(Fn)h)Ki{cf+M;2f#&Iv+IvUy_1K(x+Vo4PnE-^eSdP^1x&h_a|BmG&dZhL?Y8jjX z^h0u^N1?WfD^@K`a;!*lbi9djHM!R5?UUxrYHgm6_P^MoTyD}d z%%rYt)`{)4IAekSK^^M6p&Wxa2&G)9MIJ&VC@0TH%@V;z$~|h7VA80^yb_Evdg>{= z1mnz``j=UP$vOK;w**sDdnv~GIOTd;j$U*vTzrd^$abK0kE|PD$x&S&u@?Bd~ zIBSK+^(YbWLA>e(Z20zw4Qi{I7{1i_mHgOIY}}j2Xf96^?QI4Sjt&NoFOu4F-o|fa zpWQ|a;%+#e{&$`wZ-^~FY&xnf8VF6zVay>L>INW(P~sMr&?z>3VjItL{oVt%=ZrZ_ zuXP5lt8$a)w9N;#ohzv+tu=C{N$4pXqe;>Wcnk~A45dsAjpPki%!SHgUg@ zeANg$yb9>lAFAQBb6b2L1!A0D0f&h5J#$H^PX8$g{Hd0ud|pg$%Iu>fqI=cLO)Wt<_|N(Cp!b}In%Onn59h*r*+ zM|mX>*LjD#B@n04Bb^e6)8^q`3B-xhvP&RNoy&nlYUHeSuoXZ{)ZWRC0CExp?H5{t zB?qR#D8P9!Yepmx@6`AxzyaYqJ0ih$HLVE11Zg%SK%(UI>$p%h*{+VO;z%+?HTrDA&Ki-Q@gjSs@`MSjPn+mPXSXGMD&0ZiVw{zDU z0nKGd>Q<1dYBf8{$?Q6>6qGaJ%|zbvoS3`ZQc%v2x0FfB>Gck~ zR8r2HcX_3toB-Fm0jO6|shjKoZ}*ieo^qp{rKlz%4?wE*HeDs{UX&~k_TX2{p;Fz*dBkg3rNsoO$K z?lE3-0-0d3br&GNF1Z4D&5O{|>dv$7NdQ}?M$A`DTsN!Hw)%MkMANjnO>Hw~;o&_d zRu=#z+b7SN-ZWdid-9qMaK~x0FvljpGSqbo)@-e_+vmy~WlISLZ_FSM8#qp!VwItC zT0h4uLwTPj^((g=<#=|XSB`Q}yP!gr!}vu`xh%)KUl`>myT~uSa+C{>bDeUOyMdqE zWoRR7BUs{bk|Xrby>gTbs(0OT6r!hEWgrfE!UTXNY8&bB8BRIM;GA48E0-y!l%w(} z?P+$o2D)~JS&lL|C%NS)8YuamQI1m7EC(5d6U#;A+I@vpCM!?%u5imyhT#~y9Hql6 zjB=FbE-}kdx@MNk)^jSGX_v{$GqZ1%%hH5-<)S=9Wqg(?WZUtD94f61Dt5uFN42PKID7#gCIXa&9X6!OqygY+61z1`eL?^lB zAQhNi89JU0PqNEVIy}KCM;YFO&2p4Z)K|!|U)Fi$vUDw3ABK z2f5`a>`lIDm7x?J4XjiFofzkoqYT4=b~(znG`w<@=I#lwR4>CY(kMsi#Liwh$}kMC zK+!v$I={ zGD&ta%2C!9cgj(=#Spg~WlC;gmZOZ$Rz^9>sBi6-qx5)-a+GHPldqPeR1mYu6yRoT zXU}=%qBVGJ4eu$M<-&CcMDlyP9G1>i2y?ITt4dkk)x5|kS5e3P%P%XWk?uHl>sCl} z)AB2$0%n!Juq$BRvaFa-YwEax`I%KNjTh4JHiB0UQ^$Em1^u1z6s=@0wI1g=CNYlw1Uqky8P)ffv~oFm*3ADquRf#HoPk&CzZJOy7^T zD`2{_#H)bW!pB(Ua5cNwf6Q{2s+RyP3oE@@W>vsUhh>%0jP@5sg*1d0+7&3RUQj8_ zh_pkv%n&-Wz^j01wq;hpjJD;J!wH79y%MIAmRliBCy%l!V7B`LrvhejS1fjF@aP2T zU{pxc`HIyF&i@0R=T=D5%h{DMr=3ksg*1e7UKv`Am1<|tbgLZ3{s2!EjB*$o1iXdo zR={*}j#B|s_bjslW~Ao06)?j+s}iQ~bDaul8aUssfEmCxuN=lk0nbs~au_=WSYlSd zn1hm^R!T#7hF2~u-wK=VRKWE8P_qJNq^4EEOovvtLYm&>j0%_`IkXbSG@JYq!X;fq zzQxjJRiJde)hUPN`;(I^q_IKh>}fJ8q}gPX-3pjawptZ1lc&Y2fa%R4l`wsuQVBCs zO?IrzNxb3L*|P`GQs3p!y{}ac%f-Nf6);|U>+Crg!lg>^re9~z1fv3`m!?wzv*9P3 z6)-cfVzpn5T~B9E(yfqYOtM}DOaqgZFhf;ul}nFjm9<7WT+dK7*cC97{$sZSW{p-k zI-X`X04e$;V7na{E80A*LbaHRI9F{A%eSwxbS&#&w+C8k9#)cg z5#6nTse3!G0%o9g0a~VnDZi6Z0n^Ft%?gDH=t z6)+9F(y4&C`~AIL0n^J%%?g;I`i)xw)4)qArRmNkMujwE^1Diy!_+%=g*1dOu0+}H zuU5d2{Tmd-HgCpVZ*~4D`MC+83SY%I5k+1mv5xnMA$pBP4nDcWvzF~R&WPJL5}MZ1 zEI$#^YEuA|Jc`u`Ue#^Wg6}L%_cRyJ<7lO(aY(3+TZq(y4kQMkJP$pXxTY@uA<2JT z(ygmjteGiKBw_<ZEu=3qX}=BrLHujsJ5JSomvW2Gxm;E zBF4nH)+>RS6xX;V5S#cUy9DCLg;LjeB^VoVJdj8L*}eW!3ek#FoDwO#)7{xqG=Vj> z&S;;_W2_jy>{1yN`>j(7F~`mU6sb^l=u5m(jG6I@18fk2rUSMU=tx11|2>4xZ=Eq| z&SaGMw+m_rVvOsLJzNiMoj$dtX?8UZU17d471BDJ)JGsfKI*Gk?EqQMw8Ce!X7kwD z$G%MKY}R#z0dhp^BwW6$E^%C-TIMg%Hh6Y~4T-8lW(9{%20H+rY-M#euBr~1-s~Tz ze%S+k3`9|J-o^ERLsXrgS|DVm^Sg)#sDY~0e0do#b z0}ZTH(#*HLDy2D*9A{TZ%WuY<1-ML$+Qu7|IJ0tfAM%`fhC2~?#Ecg1Zk1r{A!@DW zht>}xB=;pL~FJD1#X99j#I^bf;8cEc0LsyF`Hek&cEySe{SFrW$Gb6b(OK6CAAe zb$t$psU?$qHj>|3pof5;tCjpO4bUk`%b0)W zf*z{q!*Lqvg&gR0Er-qFkkHxlrU&xAmgd&U?bBK&qQcYz0Pr0^G^RRMo;5Ws8@HB? zD|@9=f{!Q8q)B-tcs+3@&P2Bar;15t3B)v<~U?U5? zw*wMvweU#Y<7$!ceSy>i5kVeTlt&%zHA^Msp@{qJQc#}LxW_03<(Y~{fccq*rPz_9 zj)Ho88C#aZA#~7NHV-S4*yDJf9vOLakuN~0xgvmW2Ee}p? za09+Rrs}D_E_*|8aNCk4bEFBDAmP zeIvkvqm%bjZgbkCmaw>=?E$I6npSmDL}Qr~MVK~=OAuzxA~!0- zk(f;Id)*Q_ncsI?C74X_Hv_pKyB~10m`vTjS(=oYduzaziTehaGI$GvynV~iP>{BF zSQ?U9>)9dcC)=y8hJu{^hp8c%qHkFtspD#ENS@>IypU89Njb+<;e&uUfhxbAww*

bDKH&euFEiwne?f zQYUx17icti<&ODxf#b`{cM9>jM)@VF^Iad+hSkYE^aW-qjPi$gK18jv0G#iHz^rC0 z%TpJdA%c%^*2&Gt#fA^gI(hNR6>HWkI9 zkNA#$y0amXnKS00Pq5>zumV8NhJY5kB@jDvS0EL>FyncF99|mn+kL1Rl;z7RB6YW+ z0r_T0>TiL7eE%tRn-}u+aPJj?@iW6S=0V8Udpex9HU<3`^3ie?oCZ|YLFq-8$D1vG;yc&v4P8>O|9HqePH8yc~i@@ zX;>8%;vfb#wal2=+RWXVoC@}8VuF3;fK}BrX(smDaI<=&33@1%gZZ*%!v7mwFsd3; ztzada5g@eT+`fkNUY z-}3?ry@`F{JzFC+F!`98(KY^EnGmG(wt5*JkN$-@8DoCN_sn&7MmmPX!}3 zfal1OTr%)OL7>RDW_c0$LB8aVRv8Z2Ph4QTPh?FSJbB6b->^{U3HY>1>N*=Baua<; zCTFmAfRG2)fW+F`MavhVOfMz3Osrjo9~3;!1zD9?yL|c5p z_?$@ZP2J!qj$e8Bo>=NegB*4l@KWI`iGP(Ps%x~p;j0;`6=V&fLCaxZQjQ-xF_SJe zz>tmLwhA+XG3f>X)#;uO*k{c&Tcd0TN{w z(+r$}0wuYLB@EpfGay;-G!G<&@dNJf48>i%T)ymF4~k_cC-7DcK0HTqNMh}H{GjYY z6C}zuCit>XY9zT321yrY_+$fqK(?EpkwcA2)%Olal*Q{hEPJ^P5@pAaN9*HRoT*5> za!qcVr^wpnFcP7&NsgXqjGkoRV-chIJ&-*o8GGV-PZFTW1Az~SU@MdS(NX0S3HhzB z{e7}}c{KyHj{z=Bslg9O0g9&7Cgexh*P1@LD8bOnv6jMAg;$Ck#jQ!mST6@9RVlCb zw-kx^P=Nj|6=Yxv}Hkexm2KuNB8&%Dh7iQKAIs+tXus2A0;Yy&6?<2$Hq ziQm{hDO)1>wFz=d`5_znpPJ)nwmjC+XoIA#glyzJ$W%cR z=66ZL_uU!T0lqa*YOvHwEy@2_pa+cJvpn$Rz3hS~dzWvQwjdxG1Km>iQfeSCV-tF( zY|}kc27)cS3)Dw?uZklX3%p7OOY6#{9lDD{{%9&fQ~$&;zy_0{8)QRXI!2v+Sf?HJ z<@d0n@_t)^r^KKVABFWwM0}QNIJ&f@8|6pyOjr1D6>qB#=ec@&Gf*l(mcP9s|YMKz#4#$1ceEw&1xVkD5b`CYP-@4 zaMeYFNx@G$96zCmN_l=ijkp{QX#VM71!|cue$oc^;`D_Zi1>qmnp$2nfJ?Q}W>D>A zL_FZ^gc3A%wyjm6h=TUBLMX^go!GL6ly)Pk8DyZ$5JpgH-N%clV7!z)ex03G$gLbW z{Dh^}(;%lp;g?qx>%3EXDIbZ=MRrLU4uci5u^cRs5>|<5m_@2KD5juvXm^S-vVJ1N zy5x_BU%Wh*Y5GJnD8LVcDOF5#GH2OfG8g5DuVyCA8|{PzWix3;J8<8G&}GdWFXM9r7$2i*3;Z4cDt{c~Nz&B;>pAoAa;pSiIzg z&0T_jafAHBJwR^I$aS`6IsV08^~H@w{g{JiQEgan)pGTMuE@+YMCOo!dcRO)=2#+g zn1|X7NN47Ch|Ez2D3;AEa73mpjyLyhQVZiEGu?s(QgS|!8K!#KP-I#XDA%Fha|4BP zQ^31ZYPqZzRF_EIW>U-Vxy-2M7g`A&Rpyk#yjk69w~2&lVV$%8F-qTItKsmD!``4@CPD0z3fpltAL^131U_k#MX zBqH;)1zs;C9rEr1?@>rT9+O(Sz^9}v_lyZ1bUx~l_ef4;o;B152t?+AxX3)yr9P@5 zGWSptIvX}SOCu}bfKI@%IgKsQ-3B(WHy5LybYd1-iL^a@g$7j?6B6SY*DpMdo7&zHPJEe{&-9Ed<|lNPX#uOs}bKB!Wsn zx)=9C$;%GxMFptt6Dj!>sDU;pljXjHj={7)C8J3v{K+zeX2wqOgX z%x8wkd}FAC0B8db6ePcKDY^!f$?s&jVZ9=|a{{)+$lE+8vfEkU z*^+WacKa?^CaJ9rk=+84-#Fy$0BWb4x@U>{I$&o^eS1S>cLi@xQ{7?~+1*^!*^9N1 z#d1agl6g>4=T6{l1bqbf+hB-n)=*#n0uPd7bKtp@9B+wi4a#j1Befr>LTK{_sRiX4^Xl)ki0pyAB71OL{dp@`oDKpEn}>g}WsD6fJ=YcKg&pe8^@(&YA<_#_!&u2X!~@j@%Aw@c zxJWNSx&2L2)4K2vk_T9%=H&4&roKHR((RCJLw)3v9P(Nn)ZUA7lFETP+`{=&S?=%xq`|9`Jj;TAG4KqQo8pS}5u{8~hk`dhjvA!o z5qZQ7^)=e$O|>EEsZY^}^kH%M2VPQ^J1POhR;PnSdXXv8Rsrv;yHY1=pO?T5dMUZs z0KZFpPE@29cc5G^9w}IqoN1vJP!l9I8AfPo61*0N)NwhHUgzM2c2`oa zNT1rF{v;eE<05^A1ue2%9yP2gs6UN`D@&wLN~mw+iu5U6kOZ&Aqn0(cNFNWKO$Mp8 zo=BhOq6Ul9Y7=^G^#MAOJ`2d2UiBSQkv`cH=@TK@=1}tZgh>C)1Z9#sHZRi0bg4hG zCenEWJWz*tW`qo>O4F))e}9DUYdi>JSdZr%b;bctNxlPa1Z{W zTu#=v+y>uKe@joKm-oWkocgpS{Db7t7M>7E$zx1V1^h)5gF27JzZD%Kb+|)Hpxn7# zC>JC3J6EJHfX;TwyR=KBFEZ61GZX1643WMV<(7Gryrdw~mx8y%C3Qaj{U)J~G>Y_Z zJ(2!JPCeIzb`v_mYnPH2LFcc*TVk=?6&)h|s~BqVNL?65IafUZ1!ar04avm@d6z-* zEDt<~)Y*`{GOwPxLdq5C%VEn(lf2(sDBBCll2k#Yf1Xf(LQkZB3EtVZ`f8_0pJ#~l zIhHzYDbk$@Xz4;Zo8^9$M-4GhE~&G7VS%CkY8d0?`BS{JeT_j5r&hpmU9^LBt^)SASj) zEoOtV)gP)8>Dy4>m5^K~?YtQ}yJG4umWlKoplncbT9H>cO-~-)V{T?T|b>MxF!S&2dN?q^^Z6SLHX(vtw*kGjNL^r%cSjt&xH`B3|G?`) zxeH{uzoFb;9g(_NO8(6i>1#k;5@WerP51#@uCz&A1>Rp=k@|x}>Y9W|-vsJPlho~w zNdF-rQolDy-Q9sYZSZ2G{+`Fbn2>+^Q>6c7LDB)`kauk_kb?S4lp=jy0skzK`jboE zjVO1$iFacxQa2c&V9T{J$s^LyDNnw@jvS;t^?g*4e#{f;Zd3i~OObva<(@3y{JYfh zZ&Rcn?p1#b6ub_RzQJsS}a9ehy$r_%sMfw5MFxnvXAZ)q6OMN>XSJ3iz z)Hh1na$iBD|7EDJtV7bnKWN#Q5(%bio2; zt5ciM*CEpXNT}1IBK?qye>rvFQ>0x7|G;ausPk$3d(u*8L*au7|Dbb>MEmj*$wRLZ~BJnB&dqw&Ys9fnpcI5kiJnnwf=HXvneWYEa zpLIm~J_w#HEqT;Hv4Z+DqiBUZ{>9XvW)$hibBIMk{Ygjoi3%QfWB93xH3{`uJ`f@^ z&rl#RFE#*o4R1mF-xR|i3BSn&XNz$?qb{X{$jq_$yDBD9HyeFOZa#L>ZtUsQ*`Xz` z>r3Zm2R~tbt0WgVTJi?F51m7H*k;9CCAl!JC2x)OAvt)#?=vSU$@%;x?Yzb5Lvqme zWAf}Ju(KthCA-`{BnRdb)4P00M@!z(mz@KSzoK@SlDw=}OWxjB?Nx{0yWg*s9-5IppwbrnW1|KjyXMt#%)hgGbL@^?{Q7gP|qw zbo-DTwEXMszf_V}1is(VSM3A$X?gDS404hvdMa2drGA zB<~L-ALvVRz^>l5XDP|YEdHj>2fRLXR#{(@g49ydu^ewE9Dagn&J5@rrT}I=rIXU17~`Q1hd#>_akU6b5{(B%d+0GiXq`{lebhc^-SKDsM@c@xUo!Gfx_w9vJmB$` zuaxB9EiL&>Uy=i6Jvib;C3&x>C7(6=&{>uJa57h3$Pm@>{|Y4^588dRX(LVpgOdM{Q5poD|Fi;~q2!P`&4>77(gVFLLCI(O(m8nOO^x3w zoloYp_t;TMKGdZp zUvm49tQz_2d25v9!~8{$lF!v&^*FjI(*EH@>vjcXr|PXd9|0Chz-ym-zMSz3_wN6 z*Khzyxr7fn!?dCc%)rH~xOmmX#mgpq^8$|&&CAY&fo$x1TMd7?PMCMF$!vk%8#cH!^qPQ>xoV}awD;<#NTnf1x0XY0625 zl;bbK$#h<0%5ge5)zg@Ae4`~$5r3rPuUM5W?%8nsO)KKK=LC*#y=4#ouyJwwH3!anCL7z3;|;s`nl@V#+-zy_x9V)h+M6X*A@!hVH!+;7_FY z!t>Xzxmm*kFN6UL4&qufT{)OWxmkp>nCk z(M;vik8o*noLIjuy=#}c^xjXp)Np^|pU}94=pLCXcWIiV9vUl`s_m#tH5SJwl#IGW z3#T~>jJP!K@u3TpOVze!DwjAU)mX&(b?I%V)TMXbpK7JOcG`tqZm8%U*ir6MbzBXr z%B5N}>QW;d{G7H#U8056GU&`L6jRg2wDr5)u3V}$RS7@w_-wt{XcOz#CCqarGvPb- zPq{Sk(J9+N_E9R%Za*lSe}OvXiUT< zT6lC$ff1LMkF0xIxirhsOy$y-jwl|MC)U49Wv%3yKjqStx)ug|Yw^hUg>sh;^Juni zCCiPvG&|0d6w1J0c#sx)3XHfk(ONh}xn#MT>AQqXogF9EuS@TQeQ6^nt@j;~lo$Pu zc*oy9$Ardh#3SDszDwG|;%r+T`B?9A#5){qMtvJ3HP=)JK%{BKrCm74k$@hw8I~w= z(&32_s8C?U!MVR3b%{LS1C5#~b!NUofw`u}l+)kA>7`x7`gMAv7xNDmCO@ImAJ{mF z!i$e%@ZKU~`WIYKerS^A@j@<1gPHue*GJ!gdbSnao9Tqz3YuIxe+)*-L6(p&YKh`J z1LsI`;2DyaP}C-q)B+?kc^f=Z?VdXC@`03`fiRKxVT`=#mZCN)o+&B$5~3&`)q#LI z>Lo@|%z^r^i*gRjEsv>_G4Fe%7RPZGrWXnkdTnmz^E^#fpl@{MBaen_OqwpSV-gyZ z4oGZ)qp=MhD#?83&=rkIXQbQ=*)kkBrArc7{D&>zfqba`(ZStu_Gs2Y5Y_dghp{>A3%Ga#f$;H+SPS4C~W|;Cvni^9n z{~uEn<=?69Kjl9z8;vroJ^OGM z2bXAHbTs}7p3Lr5V8qR;$4|?nZ5e}rsa*Q31LKFw0{!-4#Ij`0{KESwmzvg1;i7*# zjK*g9XuKeS-UKIo~c^S%4w!@>4z>% zFogPd>8o%wmW}ge?5AAX?x`iaK;!nJdqBS2rM7r<8L$WrzKNkkxs)@wVWcq;m)H<( zaRo+P+WCn^^OQ@A0)LfD+!y8y7U;K?Hd(RFqI>+W48ClIO!^eT{@)om$Zj|Zs&^3G zTO`VTo7)B7;LUnhb~|*IaJz6cs80*DD&pIZFm-O10wcbSKl{Y3)#N!7npi@w+Hjz+ zc(la&_3cw9@a;1fF44DQ3>TXmk(5Zkv*@y~m;MIT?I<3>h^5ZL2Sdv8JQfCBh>$_w zjLFMTpC+cY%j_kxd=z-mO7R`JM!s(jf*6WhToIpWc6zkr^d;A(H!jOq@@97~;keBGm~ zvyh_P=&L>L!Z`QBG$Gv6W^r7yILA_;-qXHNU{Q?~9odMVdplfp+zABr51SUl7k_>3 zHP=npUNiWcsH~PpZHo(KwQ`r+8;&wx8gT9l1LrY$(Qng^K49sA(73bc-nOD?kL*(C zJ5|#zw$=I0^)9`iQ;0V0ybh81#(*B>y&QLWJhXUZmjZRuZiePwY--!alv4|&rKXaUtBGP80?Or*S|Hh7lJXZwClqjm z)YA*3vrs#hOa21sOk2n!vU0spJUh=LvN8Nb7D(TE0wyakx7K7QguI}NdBJ9JYEs-9+6>|J+59(x4WwGpDhA6JJG#2#m$-mru96|k4 z(!*0@+SEeO=LS7II|4PFY7>_3euFzw{tP8Mb}&PI{BKj=ANd_?gJl z;c>s07SBzn1JmnW=I}W=^+tm1kj2vxqU|i`fya6j&+cKPoq83hyZW$R0Yw^vD%I8J z752Ljw+2z*oSbG#%{-V5?Zo=+>fgGRqxgR;e-!^dyla`xmX z9L_U$>ARMvq1$bO<7g(hdb~mB(ZE1EPXrP(3l(_vlwMig~nth*&TqLW)hRF{jC|a_P2C1Xl*Qhk`n26U_WDiGoLAr z6y2NaG}p~lJQ*R_F{WGlL^!smsdv6-#)Uk}zTRa(^6_Zf+mPHbPwT31N7&y7@6{oo zP=UJbcZC}#ni`XPf$VNBawM*?^*SHUn7j4>l@IxVsq(=nh@vf(^qUVqnictw8f2?{ zz(*E>K7Zu>@n=x;Zdjb@)DQ9@Z;R|!aQ}6W4*%RhM?i2@KAhpI^ZByDia+m==kxs; ze;p)8qD)CX>;xzCwgP>XS;L}Qjj4Rt4!)h?YE0$B$UNjaG^X-lYXoX8Q!nk~h$Taq-39)hlF*p)mwCO))tK@(?ug=9md2F7yC)Er95I>y zKlHO^O$|YV{qHsFh~gGoL(LwddrQ672-d78cFC6_{59*^LUhf#IuTvitai{FLZ_AC zTfp!WyR_kQbtKoUYYQ4%ue1A*?83X%!e(_sGm8eAGCR~3#nle6{%OhidBTc;fK^KzzY=b^}(pUH^GydE4pmP*A;I2g0=&qVhv znu34ikk3|w&OCJLRu@9+o}xQ$2lH5Ju*2?q4ib1v6yD4vwXOqHL3izZuX;~$E1SHN zA-Rng!w>ges(5xAsX~FilI%8lD)KRv;(X)7^u%>KQu=F9Fd6N3dOqs?&m56W0x$9YEeD3nW@CP;j>{d%>6DW> z8+u=8oTj`#J+GO{``QFj*CE!g_uH8IW>0D>59z$MizLBC|J$&=tWn=V<36H$JGb2F zV=+GMgRm(#PeB5_jSL@R(dko>0J|W=rD?^Ld6BK}qG@51XZMBE#}*VQm8j-Db$Y{_ z%E40{pQ&_a**8y(>jKK@1K{+^Jh6VA9^z@IlU$jmwlIHcL7I6q_82toE4sJ$%AG#R z5ZSDuTl)BpXr8Y`yCVd?(C&Lh_ZaEBPJp|ryP7Q@i|N9}! zh~~jNLF0a+yGFaDEi4{q;te@ek8sCC@p4SAysal!ghk;+?>PS&l3CxEpdH5-utqka zytH?YU6uP#-Q>GGp_x*re8?g^jVY(ces84^iba2Z8e~;?igA zTFXy6rM6{;Z;ujz&pWz-&kG;jW^)uCgRZK54jTIxUFxBN^7*PRksW90#uoW#WB(CU zbzVo{Dx}4MaoQ9%c7_iee$k~s9f4#{6t4;}nMJa(MPAFP#-4zX2dBAx$Hx^=)})+t zJYJdH$-eG=TCeQ1Ey|1)-TUhC7(GC>@x^hqPgef^!4TP0Li_Z4m-`}C7x9U^;ER1n zwND2F`-7nbWw2BWuG%Yo7eW0)G-%$LPc&Ys8T=hK@5sC;{@x`fy~GftpRmaJXD8#Q z=AX&8pK=3AA0WC9OoTZt!&%^*e42D}6Ye+QIz)yZ5=> z(+dtlJqL>JM9dFGaPRZiNbZ`PzW3SLq3&9KVz9G2SdH)=<|dQWB?t_u4IZhB5_qk- zOW*tagI`YF`@Ar(BsWSezfnB@-sfe#g0D);FWh2qLvqz3^zw;m(VV9$R5=kFIFB4-8;Z?hk>! z@ZRTzc`YX$lXAZa?p`N35`jI`EGdecc#LS zJR^eJLuz^Xm7yM2rFQ`R{FL%`K zA(^4YE8=_~o%Td>f0QkXf>>#u$8J6S4RxdEH-^vj7o5B^bh+bWNtOF`XvHhy#QM$s z5&i8khI>D?!}b!w7>QbM(#DAQ zb!fIfxeC-hfBz25X3`lsw7Condj1*roVh{u{PS#GKzTpL!{FIVtY7bUuDlhL+9l?% zSVqQzNo>EFsVkrd16;b-cQu&AE`h6DqrC31p)W+Uk9GAVc7?6hC~7#o0@jfH!S8bS0|Ua3e*EWS0@(|lBu93F|JOour(&tXSv$BLi)=9so6UX>;i*w za(Ex%2E)5tX^%91YNb8>m93sd>1xrPb$ri*mG*_6`~-sEtQVIw>u)U{R%XTF6Ip&U zp?IOEK$#7y3D*oc`drn77u%XCn=tc%iB*k7tluWw%_(_smD<_+{~Npyn4Hg|o*E3^ zI-7&R`^tj+xnz1ICx)XYb+eRughsH9K5e{HKqpdNxh=#pm^w2$$fyTYd-L#|S#`kx$L9N1m!mOsQue{myJKtxR5&$HB9}ji(eX{DUk>qf(ZOwwgPRIf#c_i ziZ^vBL4W+qw%P*9HKv9s?o@7wYfSk&#X(EUveMtZ%KEh7{r~mp3cmTsrvN2 zc}e+w`WD2v88>2alo?uX=#}4L@%!|Rmi!Kj->2_}Wm5|={6zZnp@`bmwgRJly35j7 z*r)FfqAMMc{rq}I%Wd#rKz6D{S2Py(=|5W<3;VQsr;IHf_UU``T2A%pi3w4>C8x2E zJk~KOPDhD_eY&+*6mPUNruy`urYPQRD-3;lZ?kfXxd-}mYEM`YY%%xtg3g^iYTo-O zT`#(mdg#Wj6V?q?SG^ykdiZU~=yy!L^!O{n(B?OwUdQlLXT|#yw1`%!KF!l!_qiIA zs^l9)x5YIUxH@mpzGoBEKcTB_o+$p+ATC`UTe;@yb0dA+O$T#AZp4t?RX$|j5#xC; z?do65sB_mRM0#NdtBbTFk9OTbEaKcN2~qrusWCW5lRx*WF8J9G1oaQmz{_oO`&W$T zvO&{xU5pemeA3GUE4@tZrzfVd;l#Anc1=@IQ&M#AsfQ@tBE_3ayu86yUiu9R>iJ%2 zSqyG;sn^D&DaAYSDTD}C+xi};Nr~=Sozn<`thsn&L4Hjt`KbXrig#nwa#p$VWD%Tj)BL%S2 z*vBw$Qp?oaJ2X=+Q~6!1;+-zBewV3ZW0ixNyjO_TeK@E^?iC)Duh{^F2aE3AD+aZD zOp%_0xT+P)&7MfN8G6fc4^rV9P%0Jv+JSFS*|aQ7h4h@fDBfc#&{vXfhtD^A8dIt8 znE|;jjRk#Rc5dOG1oaO)h{}o91bVuRjm(L0ee{7*t{&8^VEkTPmp&58(s=#ID_^$U z;^L-JLc4lzOfAk-AGqI9W4lU~TNCQ$nsWRaOw+?{nix8sJ=n%1%ONgzk zCI-2{yWi26R4v|ZW8qa93KqoFyNxa#cC@r}FR2#p!hJx)6w zjOMo+@|$OV8(-Zk(lZOXjk^l!zNvEc+C0C2rYzHAN4l*;6mK^asM~ltI?dI+8dGh| zyQWf`JM1ocnY#?#S>uFVryZQRHGV42tBoQThnygs5U!Ek5cbIxzT3oxS1L)*MjRfqXl~HF8Rqq) zw#EXVbN4T6BdC8upJ(Jm@fnl2^4YCyXX*1nZr?s1G-%rPC_F)QPe_#e{0w}af-z0` z{1RGy2DGRIf5nOV{5X7`?>Ar2&U4Tl&venW(C2nr6kjql7WU;=9E}A&@9_P~&k5?E z(C1bM!8D0WpKHy2e6Bb9_IcW<{qII$Q*`f^FZcOLSELWOw9hVlZtvATug827wln7F z^b#5o>Bi|COncH*pl;{G3!>;68Vh}1Pe{fl@OgS-ZCaxKf1%HoC5o>k2uq(6{rOyH z^zHMI;^}oLJP|ib;^jWCM=w1hrhR_eLR-eQ&rf0K3VmMh@k@cUB9hxvTv1$~SD^O! zP?-C)rLoZGr=$yXEAV+t>ckf*sDDDAkH|x@M_l?`9V@+^Qs;$RuT*^ugEtlk_$w{A z_y`sB`=Zpb2P_x^os&d&z3Yb}*m~X8>u;|NPUHVD6!nRuUa)+gN#4sjMQ!j%J%H&S zH)s5<*Q0U8llzq7(*;GTt=Gezr2MUyi!tDz!M*T*W7fb%%-?!F5EsQq(EZ+*H9S_} zv*Q?k!mXFwKHb)oc>VPIq|mDq~uU`6N z-E)Xm*a!X<7wN-n=!y1$sWw$8Q1^ku(0&g}bLm*v2cDytj84!8=A;(&vu-&GLHd^; z2Q2kcPU&6JgUz41OM1jN`*x$cW(@E;+tEQ#GXrd^cOuujq+WKT%hYELqzDSqQp|#~ zKnDFEg%l`Px9|+h&%uA(-#=pUva6Xz13KkbEuO^{+qmuoH>>Z56!4)} z^qrI2=7&s;!8z3t&%86eA3^;?6kaN3P2#}in!(>h<(es*|BESC-iwXeU?#`J~w$mFO^4ZCOAKJ#AfjU`|bv{ zQ$+Uxk?C2b?7w>Pc~`i(-eoWCPN-hGK~gUiM0y>x%idNj%d3Yw%ISxZ=Bs>j_2xW%dK?Yn(Ox#vdY8X2P#rya z+!W>Xi(Q&211X>XJeSv)aypN6d6-cDPB+IY=b(uuI`bqulHJW=XFht&ga@E-s_3pZ z%15z>x}y84mpY=OST~ji9N|=S{@D@TWj%>zKPf>w!;UU@Sq}wHzV0D+(j3KJ>QI7y zw~?b=x1%wsUY=J`Ulj{ee3gZjZH{s>#hd#WwdpwDw@XF*U3T`m8k9K{{&to7`-T@i zss3gzdQ$y;_#01Xe_yrLI~{6Qxe3&sCQS+b%??MJzu_s+@7vj3VDp>OX8NHkyf`kUR{6~$L=jmb)~yBeanNn+C9tlQ5`q)BL$|9unbfWo>rpnIC=-XjtM)sT<& zBFzi>Vf6F8(VIwbThW_H*cnC+MQ%d5;~izOep4fTN*6Ydy$X!pMA8pCbqAk{&hfUT z<<{%YacW}n1l2h{Gc;3mgf%u|Ar<%A`&;^$)#S$0G$I`#ve{mK&9=9rmNrC1cZ6WG z{b@m@PeWW~))sp(6r67R?N|K7i4OB`x+1;CcUi9n(rZ0Y)UVw7O46%M0Y!mZ4i_f~ zDb#5U4Z+#C7*sD3tKXT^|DE(^$!mc| zentX@%MdO#pJq2tc>OFSy#BCVu#qzlu?cl!fvs+@saF=EjKP|nH6ru%;07>BML z`}t1^%z8E_fQ=aP?czMSe{G6X(jrcp1*T_2V>zcl_Id^$R*#zt5&%7qz41>8E+>a! zYG;g`jW%N{0nm*eUz>zU;r)%~mqGfue!?4M1$yH%_iaF(w8;0cqk8`iP4i(V71w1G zqM@K$>1 zB57lRG1*CSN*p#Q6DIWzbeiiOWczvth7($<%OIK~hlu<^@u=Rfb9Cz*>)q@rAF7!C z4l7sWJAXp^Ijyf;|L$P?rxiUO)$(q+uX76Yo0NXr>@lVy9Gd`*-(?t+dgTiDXTL#S zr(Rfq{TwPM^$u{F2ewRL{Vgr9wFK7f#S?x;<)PRG=fDmU*cS#pU4w;xlhA*IxEaF3 zb?VO;_OpCdEVb^Rknn{;)F^DFYvm^IHwnhV!Ms_QsuI|Cm!C!(9Kk0X%nK5t@n@F~ zsF>bD0vmvst{q@#ng@o1d8cv497=VdtXGaFI7mKcoYdpJOP}6%D1bnA25mg39xK^6X1__2Tm~aUfpGm!z_o zV=Pd)>)u1uwH-QwPld{ZHXKcPH28!n7iC4`CW{V8mBZa;1Go2518k>xucxm`YocP@`w7G_4ZzPq4)~l8P4Bl$e`{UZ^)oiP?)YCiTkXMGM2g(U<|~ zP8H8)OeJPouKkoHOzJ%&a--Z(L?hiX*ZWhr;ma*Or}U7nQ!Ya7Q6k^d3*%Yo`4*Y# zzXf>HrIX8VvuZ=A(V%b0q=?WcpTw2&%HxTi}tG0v0h-*O^3+2PnNxpcbBvHKm&&+`U1mYkfxvMNpFgV;^ZhL8T_Fs5R6iVcxD z#-wTGIdjQnO!`t@u2#Eh(w9T5=E8>|Bh?N!HQ__TAfDXe0Ah2d$RC`D3jYtJj%DG+ z?cltjaIEB4`~!w?U&9w(#5s^WnN&giJ4#;QYYc=B%8JJSI80uqEjoQfvy7=A#!f04 zXG{vGQ%ZEfmtpL=V+^sVi*@DVh47X0k`a`~6O z#a%qLa`L^0ke*sly|ee|=2R3@pcJV1PHLLDErI+YG*CMFhf`1E1N4^;21=(LxXbY9 zL8bIu6OPT%F{$*-Eo9>{o}Z1!7{Lf0&~0{a)Hz$^$D5HrF4kDu2rjlO3wpnh3gpKB z8MLX%Bly3TZi?S*dO|Hx34Ki?7!4{g@HGOtUEqHi$a35Ae+HM6fh_Ow{cliL>aE*= zIQh+{a#HVTqxtMJ5+hjdgPdgsdiPjllu&0Zu03!L=G9_xS67|j%28I_7V58rLP@K* zgQu>>$`Y|JG`=Zi#kw1+GD>VYD7_*;x_*>ufkvC-M z>>cszNLL<`M`_+fSCnSt9NHr`bS)pHziluH*N*g&){uZYPiYQL(%j8Wt zQQSVOKsNvFhG_gpfiV?#Nd3ijamJ)~lQ$MHZ3J~yxE+|q$dcux`6oA@B5KDY+-fHo zn(*=A5F0jNz|rVsg2+}lBke-Tzcca$YRb`#zd_-0xLr~y))Z(&DtfFp zIUb9fUu*@kqjA}!NC-tKkFzT=75qD*_qrUMDzyc9h29Z|j;OBGJ7Eh`#$?miYuQ0y z?{w1+)a5xMe`YiP;*1%I(I?mV&z#B~DuuSgw1E9IU++IGeJdF|E*JttCCn?7_Zt6c zD$s9IZYBRS$C&aj_MwaIY{sO2<%!KdEXI_7X;A!2b|UpoF}E&elSIBRMs?+C7dr_l%ozTN#!5c5ZK*4bAIMWJKd{epgTNj& z|B|_=GezWwrlbD-PeKdqV$9P6yG>dP?BX_YEwGE**!0#yq7v$rf&HI^0=2+Kvy6p- z-6pU>5ZLH~%PIffiX^a&O_Z3|PCT;*cRH3)2dm3!Qg($P~z{`8nHJXqy!Q`Uc2 z{=Y0eN`QI_<b+B9G6t1w)s%8_~#YKY(jH!^m z7Vg|B!I*OKRR%DJFew}=nw`kZM6Rwq*Vcqja{}Qfe$zpq@-&ejVMK)=2{~7%S@@y0 z%4CvXu}em;gq}D z2S!uEv5QkYAWr3^@bjAsmp=`tod#N*w0oDs*(%j_)IwCAF7hX{aEyF;!dmQX3c2wh zSr!jB)E0&8w|J08r#p%tCuZ78KqUpTSFsI&s*D8zzW431>H)s%R~Ot$HTXkeujEdT z33N@k3h*tYF4~xoYY=Te;*gJa9g8~WVa?@4-Fpb)^R^tj_W)bI0M(D{&T#L|2FLZ0 zD0!pB?(Kwcm)k@|b8me@6c2F}$QHOB?mfU}OvVkpS+&?X;@%a|c4Saj>7`ijBrz4& zX7jk7V<4_CgoW6>wX@A2u1{OH@E-I$13BA^3f}`+`WP<|UY753^@Z<-#Rx9v_yhV- zB)M-AEPVGIF8{h{RTEB^J&JpH3S{9cNO+ksDO@JQ-E78WT-SYEK>P>gr0^8HQruk{ zND80jHWxk%j;_4`-U)Nt*}i4%Is_D_F!U^ zXG{u^*kM84jUKwBZ8k{Za#D;e*D1l6lq503VoVB?*q$z9C4<^a7y=R*`_3b5KS=AE zA*?NV$pMzU7GZy2ma%UCu)dVhMu-L(%-wY88EwyFKFlSkTJi>1P-NP)#WT49_ zdw-WP1iD(Zw09?TA&@^|PCwNX=#g+4@foZ6a&$}Qm9;5r3F<)Rm_&4h9|Tj54@P)< zNFAHz5pE#bmmuEc5G?L)(!~Q#ZF`{JVvne3!q0@Ccumg2hr}@zTdE*W*~<)seStCA zJY7{l7mP{kCb4uc?m>{!JI4-gNRtnYnd7$hz?l8lpZXGN&ldS{IbS(n_b48ekuS~e z{iA_!Dt0kNs@8#4m%eq4Y4_$7J7h&_SKz)@#aBSrK^X<|y*YIzHN+U2g6ps)w9D7$ zJtptNLA!jg(Lg^b_xTtLue4w`*+yA zmJiThI;easY*E}ZO_+@7OO56+P3uv)PSKX39dGZn0CnbI{T++OG-lXTKXf4J7Wcxp z?m6e zOG+7waHZK_1gQm@SNY8GNq-qzMl!!W-cyB%46Hk|W(O!mrOO0iXLEn&V zZr$C~ksX)Jx)F8+_M*4xsss#Wouj;s*8kqD%H#ACh zrGR-(W%9kmX)XDVI;kT~1{aC^DV&IcZSSJFF*G#v^Zbn2O5Dh{XusEhS{TNLCrYF=XBBC3c6@4v|t{kB@lhL zEs7@u8bZ;>=Tt#Cc`4B|Z$07}CAwRI4=T}Qxl_}GRTaIYc?y=7aw!GtS8%&doY;VN zE{4=*1F{ze-J=Cg!C1m3pMuwc|K_>J9mpoLZ! zVAHl7dRCqPCoq$K4eNa2QONc*)DjVl@$J}zK1_SNbn=LHz?a3--E74~R)Kyaa&g$x zU`#e8XWnBIj0Kuc?a;rS*5Yvmb^5H_-_4>|ixQ`Z1^N*t-6+i{EpVd4SZIN|9AmP1 zc|v_$fic-h9qtP$cC!eR!mo%`j$<1>Zh0J^c;5k}{1Pa)LT@WQN9ROxO`OMZpSV7b zPm1f~_yigTl7`eOt0x_V`q6=ga2#{?*2Z!7p$8nQ#_>sU5<}6f#<5HW9${6-u^l{Y zPHFwc@EtdC)tc`a7iapcmFQ^W@28qsa-xO)u#q#MX`^pP*we9;X@*% zrvvp@n60Tlq5Elfpua^TKf#WwKg|)zdtpeG!;=>6*s}WLF(HQ&*U1(=@dfSZ>hA^d z(;Nk|`l}34Oj?Wu>dkL!@LsHsEm1t)Gl;wdm8l~kJ{-Cg<3-wf$d#zHQ`n<2drGkwbb4nZ+l5Xt*I|97Ru z6VOsBiw0qOrYrZ8PfI9J-wZj*W=ySxXfvc2K@^2bfZV*O4eD<6KviO9n#)Ns5<7+< zSyxJu*eNDs;bus8m$8z8_L6ICQS4D>>^o03fv0-?cEPU%f>eh7wgoA*EAn&!aZ_Ln zyCTGQvp0D2nGX|)#RC0N32>Pg{Mw~*G+b@8HX2SJ-t!YQgOM<(5FHIELnQBp6Vzxp zsZ5XW;?aQ39c?u9h||wBiI0{G?nfY}3gX7wi*boD*6bbdk{ zBkGR|lu8pO*BTIGtAesArGAgMcd1wEPcHC5sa~GQ^vn`gRsGUf74_G{S1r$ionGv7 zE1JGsL zbcgCk#Vgb!E^;1m41G^O$Sa=Zn?zUNKduUDzMuTSk$Wliqk@A<{o@FhaW++`s(y)E z#rM~=8u@keIvs(guN3*Qv8Z~S-={Fw`{RBT=6R&!-Wy!XI^!)}{g49AWE`}ksZZf# zr+9i!fjsUH12)QL3{9!X@3Fq~Af+C6(clBrUjaRl7R4b2!m6rYYE@CcwAIL8IHk{K zG<_9r0c+;_i7|cLkIB-rRayO5M^}$^N^+$`97EqHDeFxnOp1{Kl*0T~9Ft`%P=E42 zW{g$p$2xpa`Thx46bH%*Rn;#utEgXQw-)*P%Y<#hb@{s*eq~Sqju6f1trwpniPU2_uyHvt2%@)K5d?TP9&u)vt)`SKQF5 z%X{oC?>)F$iSp}cXS(V;4@S4gE1xivjjEHm~1|UJAlvyV^VnC|FWVux<|fPcnH)KgvzgVTJ;w97@QWy)o%i zx)aDBnWi0?;IJY+`>1hzfd0}!2vjxCY&U;&^q^Eqk1Z%p$kH*X^hU4p9DcdoS{7T> zrSoFcz7AJ^jOc(Kn^14p^5^feKA^|N^#MIHK|`NtggHFb79Jd%P@q1b`zmBby|o92SAP!s;@BK|S%x)>>uU~n z$w#F10X+uJo>}17#kMk@Nul@!u}d*IBF&_~@Gt<98N}ZhgE7Rea--F0|0M+Sr^3g5 zH)S^R0s2b^m5&#ek<&7SsbSnan$=A?D>S+KO*ykykFQ7N>oHMzQMp!5zbR*YL6@oTDaY^pNgvQ}7dwFr<@rLj7=0 zfqF;}3a||>NkK^O`)&Fp719$kTtSAk92fm{=K zga&UA`B^dF#~h)>Nf^feKoCo36$ik_S+oK-#jwVLJ*H)4s=>E&(jxgVtRv&Dct%2` z_*QprtnT+5QgDLElgE_*g)Pu5W3pj+)5=7TF`259D-+ZOW3rRFf1jAYLZFFGGzJH}q^49KXgbGL z1*Ne_?q+YVbsZZBcPUwy~8sic~^qnJHl12m-a8>QmZy~rQ>wjj5vkEyY4Sp zoO5{!WcNPlAm}rUN%zVy7~wLe+&kMt7+8!c;ZK!CF&!sN3cuZL?%scxbgjt5zH6wr z|MEpH>f9vqlbWThw5{I2qV%RQD;l6L`o9aSGj=TnqP}?}O}KIzyft zVA8$vvckm)RoQPo`D{iM7g~%d_s+|S;v#~S@Kshb_tw%vOS)J4q2D~~4EpWR3Xz{} z`g()))zqAN299#*g(h}4UFslIk%~K_I5nq0se(MQ+55wuqdO4DA3_7q?pi+Y3_d`A zD?Hm}=Ty(=LD_%Z@1`hTXwot1*_F-HQ|*=>{C~vD!>&P{TSPvSi#l`>rkOB3ElvxW zo}}H2Q%!m_8#{Cnrl%e@JM=t9;FsLvjw^aeX|oZO`{#9Rppm^EbNGw3e+dxDFw#R6#RsfkoSnE_$-9i#|6?<{@g* z!AkV1vM5fDD^M40`vs-_l;~~NjQ_V1J=x|8N;FyS+$>>LMXz)to;F$&-L1>EqtN25 zB7YfA!GY+D5vvcto9fJAT1*$cAg+s^mLc;fx|ooa=m!w37dr~nMNcD$TuecuM4$L( z+rKK&3j!-C(PX)48LCiKv=a?)vo+CEzU}`sTD(o<7bT*eo}U)U2hoBOJ-Mulo@eNy z=fTqtSVT?p^g|g@oS#;pE_!mAu?;NxkYA5hFJLatGx(qqO_rONC9JCGm67ni*KJMo z?4_Olg%)oY`Sa6J(U;^PI>(}?A!CJOdS*@+J;x^V5H(HoYC{w+$th45J`GZcy6kU&*DX%NUqMZ=uCxZ z%-~ugn@%y|(+$G=A!N9VJmO2CEW;&LXNqDbzyi_RKY4h2CHkTaS5TtKa?{g^ltfD#y(?uos1Um6#2=SsOSY{b=$rQ?}ZiF`=XdGdWuEnQFK|fye)r0S%JFf zg$2eoaClFjJMacyG#!&x@;wd9O|b~8BD%h5Z(H|teN%g*HPJO+pHGYHyF`Av9Tk0H zPTiKFM9(z!@V+#wi^h2fe$_zK!tj>2U0j$`pe}l*$ygw|$HN!k62`|CR+3phC`C)l z&5~GE(R;ap=uNbW#(l`W@sAen!AkBp=W=v&x5&?EmdK{NBKeTVGxLnN_Ilgm3|o7> zZE=<%l6hYXdph}W8j0Ef{Ei65hq)f#aosGnFwM%3)Ngo+lCm0IUBwf;O`<<1f3?0+P<27+noSi1Ds-(Tm zN-wo{Ta(mzP3mK`c(2G`?MA&cAEEhbnI&D2(7iOLOuwF^k0$9u6SJzTKuuC??%Y?D zqze*!PuD70HbZ& zf+EO^tGdmIquH(kHAy=@(B~#4=@OFMM-&&>gjJQan_Ves?^Xlv54SJ)16sUa zf3Y zUP>JVhBulD)Fh?79>{`}=CAZ?2zAawzd0|~+f<>dqz;j>)WK~{(%936oQ4)xAhDN0TMpWayHXr0LNSL?-l7Y6njguQe5@N$OU+-|tG&O$HxSUivpGEJ+hqRni`j zv9yofnxvW8;oZ^V10p{)7adF2=I9q*fussAEph4hWr`qsN&Z6W+MEJ4Nxfzq@R2Xc zHv)UTFa7-o8d_lIFBO{hw&@L6M)Aj!L>JrhdYF9&c zQ}4}28+=enIy4UN#|f({sZ&JKK2B?1I&yR0)6wF?B7duN@QdQCcc4gohtp;9)T?S4-i;rN9 zSB^@$!B+2T-Qbd!uJUwAH)5sVkGN=KDb)`QZ?F}pNjkLaf&WsHuJZVxlGGnwx-mys zRY@J4N=f^+>ZLs!4s1Y+Yeaso(@auaB%gC7H%PjzBIDhR)Nz|66DINGM_EV;905zf zAJ{S5^RrXeD@nIyDV!ys3_pV# zB;B0Ry|f}Nk}vrLIq;Hi=dc(^5W|X$7hh5Hnv!&Lh7U?FB|or5aYdT2s$SYRB5B`N zC5?G*KE=;t7)!aRmu^YWD@0k+osKSPDbjU0wsueqeNZ#vjilJ0bfemIr} zSfaQzPFPh*hFR&Q{bA#lllW2HE}n-LAIHXz7nO9or{0me!6h%<9@8aVR;FLhp{72T z`j=76Q=m4M+TDKagG$ovbWD?UI^23$nXsyo_VFqu9n`9q4r@4?f*BrK5|2u{HHTmJ zy6mMDF78ypHyJX;%L^h^V-cCqOUXePOSk3}s7czR>4<$r-ES0RE+16sVHcR{@&aL1 zB^~5cN;;%fFYU7W)JbUZ36a0Rib}c$wEG$?>2{2zP|{_#NWSQ^=dnbu+ACfo8CHy? zf!!w`tt8!^sgRU>IRh`*gjJPvh*2r&P*}C)!0VTr`vO{g5|WxF@ntdf*7gl91>T(r zUDC}SE`fQdsd*{Yz95Rr2$QjeYAWL$(Q)jLO46MPJ}AAEe9=VO@d&FbsdF^&tkxve z4Qxk0dV5Ob7Zjpiy4>>LbK#PtD=@@EFI|D4e8)gdUD8oD;>c2<7I=p_M|M_{t}ywa zlJo*>a7B)=s*<|cm0mieRY^NPJr4V-v8P3TjvbYhg`^%f2i_fNUD8qn-pj;Am(&Z& zvz7uiNgcL5;B6)8jx--sl3w5`Tq@bc2WVS11k;+AF5TxHeBuYual?{*q>1y3!Ex{&Xej`U)>Cr)k({&*>pK7|O3Sh+#!~m^pv;<4V%?X+EeV zJ%@aqZY+LW7@*#cKk zqDN!|S|_Zk=mQNFO&hfk4L`QLV|&8-<7S}6=Mb8XKiUG(&%lqvOcuR5rtjD~hAtXc zaPdk{qNa%+o)yJs3_WVHCa$S+PuML*#P`EJe)F8TIxPZ#|-#%k#4N8%!Rn)HVzdb}-)PdI42 zGL(;dbLuK3`f-mBhN2(OFy?#O6U9g3gjE%tuqr)$WUHbVKHPmBT3iRwUR3njn0gk8 z61}RRi+(tvi@p!xeWpd!G|^`kL~$))m7)(Gw_t)2y{f7*nFtjws%jCakLH zBOMm4#`MufYh!v^uj6(?i!b2D0iGX&@Lpy456N}O(`zh!Ot1BH(NEg+R!{n9qEEL( zah0V&ExdPFfAmF4^cp^>jp?->S5Tr)b4BqETrmj|N>#bhhy7xyn@bXo*FFLr2@CedVc!qgTPJ8i0@zESTNlFpq%qPzYI+17a7g^rXx*=thef$ZuEBkZD0xQ zyozzEC8sYf^4C)si}8ei$64_~q@&I`j30-N<Dy>Wg{-VD@8El?pg_KD zjZV`ZG#Haj$y?NNX~s6#(x02XU3NZFf^>jBGdVwL7+U3D(~g-0r%My4WHD$UP1+RG)1 zIh5QfK`i7jRhsF{`dL?jzGms(r%lF`W;(Zf&S5Oje85-jClJV=Ky&I325jyUE;V;= zrdiNUnDtG)VI{u%RR6WhzAujd9+mUB-kR_=2X|xMWvibXiyFoKpOl6*h>6MSw)5QTDbV3 zG+|PBk1dSgMsTk%n$P_Ep=(g*HIcvEi0XX+3TuNA`~af)%{c453-j&|_$CPz zSC(-MwoozfNLi!~C=-=122yF6LfRFZ6XjNq2Sfe#bC!AaRGg^F8aHk-s?`mGq9M?}@!& z>XP1%)8n5M`ylXoLHRqL0yRl}4mJGQ{{@o|DoIaUqWFHCu&R=h5lMYwtw}ofhrX1_ z-xm1?3sFgKTxF3BF3pMWBQt*EV6YqX?F~q>rF}IoQKoPuLz(k=EM-m_^bh5w_igk= zBg|ioUxNy7v@GdFqtZ*gz1AdM(r|1Ry}Tpx%k5^8Y<*AcZ9|vzPK@3gp$M{<{BdzeBdTuzFSPTTrphH4 zD;a1nby8du-^wxeohPxfD6S_6p7y26tCb&Ej7h=rqHKe#E9bjfj~6zzF%zqolqb|b z8clJ`N0CP(E*`hjMzr>x$gkpzgJ&CV=a3=agjrw2qY-y7>Dzk=T*E5x66g82sC(PN zwv0{3UV=rQ_Z4wo|zkokO^ux(LJHkf=TOO4V; zN0B0DJog|-%!`ubJq~4@c>B19?7F;-CN9z<+{6OR%aedM3gW~gLx}?P}d<&vO z7rvMkbuU}&!k5z``AS-`;_C8R*7Icr>MnfC^fBLsZ>2@?#Vlc=3tw?D=gS7Aq!VJ5 zlIrXhB+YrO`)+6qK3tKDN_xYlOIj@H)q*Z*9TLb>kgK9{J-q5B6w^QwUCVmIR-i8F z)q;=tlAdvpt1QAoNiMMU9$`{a%B+-RIxR@*-(&A#sQ97C*IQ9ZFB)`7izU5YG08bKqf$~o zvjs^t+h6<~di_Y`Z*ZcLo`;w6LGH+BbuYc?Ou=G;nz=TM?8dvNCNpHZ?&)W*r zCFQd|=6mUt93;7fg_7RJJCz1X=~B{(HcR5Sfz>zlk0CFfY-{IveJN9_^SnuOI~|P% zKNk5rV}UGnp4T|p(9Yr;M$Ail9Bg$z!CliW1!|JekdOJ1`D#WqWH3jb-*lpf@H^G> z|FNZsda60)98}yO^1}8dwe=G~YH z9ySS+bWY-+@mch3iB69lJA0`3smR}DMCsf?p^#uJVv4D|H;%Fz9h%=8@30iebnb<9 zUY3}m<5XIwpVfkOW+eI_j@CXC`RlDHoez;6wp~mo#@t~d1h~0foz>TFtvLo z>6{vI*2zW-bavm==g(-ZQRMH9N32scU7AstP6lK81y}VPScm2a(+8Q(i=dOqP(exO zG>?llXybCd~_ zbOuG}^mkgY&K{c=kq5pI`CFS==LY1z=N+c=cudqiou*#Gk(ETAD&8Qw4(Ys@z$IlW zr|1lb#LghA1v-Ofo`8EAVqc2<{a(~rFJ&kr`E(lT4DlV`5P@~p*;qMesOyl<>lofZHx<|4`0Jb_}=wPu|h z9>Z=BCh4TDN;>`B7U=X^J#sHpgrgp^Bi1RN6%(lxJFEC$7S@SVFJbJYx@Pde48k-z z?;*S&%n~N)474lhq+7DispIx&K*c|c{56>j78PThYHw(Bzr zWM?&`1qu@;=?sWCYp~UVb#~~q`=_Y*wa70kMCn}biq!Erzn9Y0IZ^jsPW8;rN*xJ0 z*SiX2Ixocq3KJ&joZ(hl=XA3LI)`nZ@*XPwMdY(?gih%i4>t*LD3>r5)vYh9o|#Uv ze?p*`0-4Tpra)oB6dk9M&KX_{bQXNu_aCU(ggL7mrE>>H*5C|V=LUrGYX#~hbXM|= zv?$%-gG}fBtSH@JP(ev&P{cZeofhaEc=kSXQ1P##VUZc7bEgUGl$lO8ChDG(KG5j& zcSPwV4M?UIx8$u_l7~eXml(K z*0B`G)_DWgSs^iLoq|YvlJX-skXt*jCrQpW4q%^^(E85N10VJ*c@P2$)UsQ8^|c-V;2xh5u(m-3udy4A&Ym`%NCbY{R= z*ANDf>Ad9%6edhrCqieW(}HzIZrg@#Tr7!(`Odm;Sgk4EzL`!sfwV!hfD*hlER>h-qu7y2*EHIsG;jDs7y=Zh|u*9{} z5}~s^8<;F8=?w8AbXs!OqzkqY=;24v@K`fCcNrqp+hsaf+Slb0WnJ`5sVx8eFIcwO0?Ojy-Ni^J6h|;+^j%OwZv2$Gl&&@^A3TO4qiqg$-1^T?} zK6FIsIvG!r&d`W;hT1JyXI!_TH=?!8h@ECx`F2|*7a44wB?a6skgKGVoP(}!w=3!V zxgbhQ3WP~IqwGp&jcUm{W8$NhqvFq^;qG+QI(K8vIzMpM3eaitsFyI5lZ#-TyE6)8 z>v&~Mp&^~2P9>cQMhn*2fAmBO<-d!D8*))Px0kURG}$^=n|SuEt$Ge(r>h6+lq>0M zf_1Jo36s_tZ&cD5XSP76<6}L)M#W!5!y{&t&Js%`2L^PO#qmBB>O{BBz#JT7DUhx6 zt${f!PMD-KHdaZ;a$2C%dzV=cpyEG7!=3RcoqJr7oZ+x_u5(1)=du^gS#xb?i zu5nT?A)UHWu*A}=0@*saF`%@}CQQ;f+pMHBz9l*%(%qM!;=ho0Vo~ed06IfFw$3#O z>_G5TI#>5Q{lpmRpL_k6VWE7D-IP`=(0b%TO|eq);M zdRIO3$f_ITfR3d=rZe6ar5n?PDeJ^4=~!k9bdFsxZ8IwV2P3O_>=>eMu*KH78A)+` zS@j&yISY4>MB9Ks}>@m8gE#&|8z>HGG;Pf+o{pp%Wp&hi{$C(Cr|4P0K3 zKG5j&O(0Hk)O9e>lS5#!dV?@!ok;AQWw$_Q#z<=%D*i4SZnUCwZZ3a4zqotu4-tuqwXQQP5?&R8d69is(03y1ekfzJQ18uX%cZZSb8$JP-skz8n_tnMr@ zF5O}(km<}aMM)5(tYg`gbk1ric6tsz{9tM6hGos@)Fba)=>&AJ`q|z0OAyL1S*bo- zL5J==E(tH7GbL6@XL3t)_Bg5bSI}uA8rC#(mdJ=YQ1aKx&m`z3Jk@hR=PJaB$W+jw zo9aqxM@%|vnpH{XoR;XM-d^wx=(H6Ln7`HKcJ8ZmYg*J{YVhf-L?}NbMQfpq)P!Oc zbm;LaYEnP9hIog-c!jgi%6JJIk!B1&hqE$Xmu;nR5%=M{Yo>P2%F7L29U zwgTBYxSUyf(jZJ)XL5wjIbI8Nc4)s~Fgn;Cq1-HXR+mNHqv?Q7maeN(FB%=3`;=Cf z707hj!&y&e36pdtL}F*E+X9`PJ9g-b4t5X?Su<*#$BB;1baEEmTBv&FXs^RAOX=|l zouh0~%2`xU(wXX2I%{f6&f4aq{an!5Q8e7sEOyq#aD6Yqba0;nekzMjbnD=}xwMWj zfNY&!2=8Yc!X%w@tV%kQj25hO);|^|(bi6)A(xI?=K)Nij|Fs|Ezm7})Qje<$6<*F zTm>?nKER$W5T@wZm2}Q=TA(w+o3%4KXeS!(%|+?Fgiyx0mLJNGWa)N1)pOu1__Oqq ztw6sZ-G*0sBukj06N#NkEz!wrn${U~YD5F(q(~aX25}uC#;3C?Lr?EjJqL8|G)3t- zQ-OX#dNOZmRfaH0XL7_k6I!CPhdK3sptCcU?#)8^1>~J~0_&`Vbs8+yb3o^5SCsey zDO+b9EVeSV&Xfq9OiQsdeZS-G2c18Nh6lZ&!4JV`sYALhOurVE@xVXBW}1BGHUa4Av<#od*;2D;3pqV4Zg@&>>74 zS#d{{9+U+Yorra2x-HN-tb?%>ZS9K9I4er$K1N%kE$DAnL=YxJh zdOTQZtxW|bo#_!e=UXk%sVQ{31a#t}VWl0Vvkt-gc@R5mFlW8s_Z-mqG>yFDdyt*= zKCH8b*eE*Z*|8nft$e+|r?b%WaTgB$A$pf^Gs`9m|M;8f|KmF#-Gwt~CQ8_K58s<@g2w7~Vj+)OMzTL@xK8M}4fZG2z7tYfJ4pgndZmT*jo} zH5^oc^g<-*lcEc=x2eCt&xaO?xa>Tt5zR$MlyLx+y)6^}zmo zBWG!CS-X+5^az$N@q~X@ROxYBBG-R6k-cw!xN$ z+w5Ji{gk^1qYBN-bCz z(;i_e#aNtx!&~gmi$URZPrJqLJR{J2@Y+eFxr1o9iPKEr-uvY&;L|O==+Ij&aXY_5 zuD{<@Z>x|7FFjPC+Yg9Es5$wrhhjMe`i&$fm;wzkCYz#nRiHV>0?mu#y?-K*KcVIi za~M?x!lmYUUUT>2wn7!j+TDcKqSSLBxCa&o*{FNhWYj(MUw9<$VF<@15MSz38G1+> zyEg}^H(J!WCiMdwUdSkrrCtSD4+rv~|0ph!^8?`@7wF9$#3>Y>To0mrjmK}2o>o}mn*;oYQ>Ugy>5Z(a>^Gmh z2z5V-Gp173S{Uf#0%2149JhH)&vX5lo@)k*Mt6Kh}#IEs>o$!f}6FYOjQ%$5E4fEh9>A5*9i-WfTOOWlTl*{;nwT%{8o- z(($Vvms5`3tt?7;hcK!4Vxzg<*_@*1hyLvyAM*|{a8=~MpNQTZ2l%Ou}O zu-*?UQuMp<=xfxs=25x*@`4f&|GM&2p zNl7)MQnx&YCwH7s2Z9|%!$YyCYq7AzV_i9vHy}ZsgaP5Zwk*Pz$&|24mVqs;Ui!$! zHSQcy3`4o@-w4}}Ed_EY_qRo9LtqRgeCHfoTjp|dq{#4oH>j&ZIb$HaZ7Qci*=RO~ zdlwBv@Ek;3@H^%&y&$F!8hYs-Ah<7tbDrifEa6_>ur_hlyKJ&sZI`Y3WX;xEFdlekt%tOgm>QwM9PNgm%Jr4{gP9qaGChl+p0l-;G}kP zM9DP>lfoAV%YB}UMQuM9G8e*EEWCD*6$syMUb_=Pa6i%Tff@Dq%LR2yy9(}?Es=cP zW#J93NbL+`s^s++0)L#tgZV>;eh{p9vK8s3_R`A*1#+mrSq5e?raZnUjM3mSCYw(V z_C)EeG-Jx+FBwRN4q-}ov*aauZ|Ut&ef#aQ2zvL2US4k@!>OeuW+=IQRC?cs`;LHK z<;>5Z>2;U73!Nz!i5~@ylhsnR@AJN)3QA*<|2BKE+yIR>lxpXK2p>ca0f zNf!Fdp<_~|ZAZs(eUokYDcTOh`P6TA{S%t$BpTK?3ul}(YASJAF1Zw*Q{nu&DN z>{U0buQA`pw=O18iCEx|IR&y;Z-EClc#J8p_K1tp>n3Ar98*$rvy4eIrw%3SNlfa6 z$+nC9@~ij14FvC{Rv6B`|6>N>95;py2f+hG!wa0i0{3DsK}%q`XE+tEu--7}{a1<$ zhpbFe`2-VG?xoe#YZhY=r#!g#Zxe{BRtz3NzC_iPAxXo=-m*b z$JcVCzk*{81>zL?IXNFhKQR>OH<>yVKK-M~m~1#n3((hdj440&M>)0B429ED<`r2^ z3HPFLz2(un-{pzf;MG|)U_V6Z4cz-4@kUrEy@j-XD)_lgzw=PE*uBYhWl?%B;Hun9 zr+tMq^AFr>{ju|I1oEfCz0-#te;6O2zk$lsE*Vk!+$Kz_T<9-)#k& zIZ!kp2SvS_Rasc6d=Fl256#M}pSn2v4<@5GJ^Bd}d$oXLjxRQ_0A-g?vc!)#D+}zH zhE+_)lvi)HMCntPG3C`0VpyDcjH#S_AM_SvIjQ&3<~h0cP_>{GwTD|l6nETq+MS?q zkZAZg5!L%yLZ5@)az$!yoAth#(X-Xt36Y$WV7+fUv=meHSg)LeKJ!7=Ye3suk~7&r z>P=C$dNae?q~7FAlzTgcGG6i((In4&UNMP7;KRDVJMdSUu^@`OF6j0z0{KG~AddcQ z_KtmW@>hI-{t~KGK8e;oFB2wJUbW?yzSlP`bz6H|&a`={57F`=qTw0KcQpSJzI0zf zd+B@Wow!I&wLs6Mb0g@%<|n*k&^H(ai%sGq6O?k#{cy#71qJ$V%Slf6u&(k8%BG+R z&)yi;b|Kosau)4!1=(_nR-0v$u&R$hxY}tpBh~Ka!nI3`AVrJX4o=|gBPX4{222kX z4R3PF3N}0bgdh!9mYXb*9Ak2D|Lm%jrSw7RZ#e`)PO;^1mTSpBISTZ{Ihjs~(k6>B z8P0Mo`LoMd;PGwUAx{&?pTOgF|IP^XNVxR)QX{IlzUfK|=c_`^^-b5r0?jq^4V+N7 zIZQM>-)vgKZAqzpvz(@XvFRlxtQjk5IYUdAmVQCFhiAlJ7$SLxN1VcGDYYxS{%ux) zev@_oaYX4Cn=xepI^EbNrF zEO7SFU-$nXf&2-ao$7Ck(l-ghrRF7ORI`5uadqfyp`SsF*?zbC!1Qp@@RAwL-ai@I z`(;aCdU(!jnVpR-IQeQ}cuA<>Np0{ZnlzW|5Meem#Zzy*qTKi5Ol5(?K23fIXV9!(Xp9^YA z-ssYlj4j#ZR7&Fpee;mG=lc2}T2@akguw3|;w&BL(jQF5J*RX-OEek(xxfcyo5^!c zYL_wDa&oputrJ#tf?mdpu==KDHY9#vNS%RS7p~v-WpFq~G`w8)B~p8!(?-^a;bD@l zL?npH*ICh#0*q{Sy&Z%Osyaazsn~RZ2D^)fSKVkv+yu2@==^{{3Pa~>Sdl_U*}EyG z_SDoU`T-N=!D-^9jUo!9O@Z0MK;m1!{Fs!1^tGuf`_0R>P7^`WAF`9w;aO4o!6r<` z&kbg?_3Re+RQCI3%n@kjSkZthLy@zxri}Ii`I3h$PkBOVYD6NO>`-@_Cd%GT83l4? zz*K>%j0Kq?Gw+}}0{J5Y%a(dJdjmRNG@cL8UpgqeO-`{zN&S#Ss=V25uCg&kqr|Ll zy2%KOJCZU-gI7?x#wqYe-W@z!Mx>3WNy4&mxTYB+hQ4(;II@s;_2`i%q18pZQ zIC$si!5{++ef|8Sq6d{WS_Xe9ttYkJ;zhO9H{E9X+HMK8?J(nDT9_Y)JAAxo#3EYd z-mVO<(q>O2XG0r^#xQ-x=r#b3*uSPl@)3t^@|7!+_Zmbq^sbD$Vorg+cau}%Xvkws zHk^Flp~e}L10wkZwEZ>Bn9_SMB0~+=ws_h>?+=~WHva7eg~%NPgTFoQQPgcyztPN9 zjQgEp>_%C*=P z`4*~E3lc)n9b%&U1h@;0e_$vL_>SoNt09j0%-TkDp9RyFo&Nty&P6lFi<hOQ{q2OyY2s=d@lTZql#m^-mwtn%)X|da0j=$@+8!@QI zgO}P<8vVdHf5`zyqxYVo<_=`feQc_%K0LcM_RlgzJ;|tPJeeWMNV>T3c$YycCtcjw zGofSB#f>M}j73@QZ&zVyoiqa*PHlRLnp?9XzrDo`V1?&jxpnb2WqIcUSk{V~J8hBQH|Qt^S$@1FJ#JOn2t`EW2|-Vir6J=DN7QGl zd*5ZniTj}UK8SWtH2gcm4QRce9Drf(eH|_s_TDef*jD%6=Iw4jqW7ez!J;_7Uz!`x zdLLNP(*~Dx9%FOCu=nm3V_V&O_w7yE7ON9A*TqGCn=Ch=^?ppCDb#+f$pypSd)bU_ zb?;Mt&CEpaDN(c15)Hp{ef$mleoUEBt@oUcH5z1(!3D;)y7#^-E@_Y6PY^YCIilfr zn;X!2pPFVc?0uM{W2*Nd8OFA{_fhi>y&JuoqUP>|X!tFluk}8}<5t7oEmy}>@5AGa zaqrtz$?(X)PCQ8Sea4&&o3}Yp)GW`4hW{Ac3MM2TcEfE3Lkef6L#)23h!Uc4q#0tI z`X}WWBU-oxuVUgk=G&M*@oX~NVD_N~+8#C3xDJd?f>B(N-@)bvV!^F!jpsTH5~Cjs z>U|XcuRer*k8h&!+=Py)No$OwV;emxHy;02AFBH|gRnCK=7fEV!w4`-l>$9r@>aIS zGfWLrcj`5c%j(#l9jcoSu(s5m#HMgDBy-XG8;{COj5GNEbL8NDM-Ka*3okDhz(YV_V$)Hn$2-%M^m>wQdu!O$L7TF3m6%@EDGTQ{5S zRG9S}dhaJ{E=Nvnn+aM7v)Z6IgJJIzDj2EW(*~E@>fXW9R(dem;6XP1Ib0toC1v8`UClN`^t|{YQiRes)kWWHiCi z%PB^K%8Y@LzM4FKMW)IMsLRYgMKJ0wYHo;uQP6<4P8(6t`xhQD8kXRmh*6`%-_&2p z(r%8ab=p~RKC+c|D?57(9r_?x4uIW|_;$6p0nKh>a}0)dn`rCU2A7zRDCn57+o&vK z#AvHh@yyky?+!+%i<;MSBL4@28_-hmITbyrR6IH;M=Vt;9-U#3FqMkOGbGdLMvs_J zEHg;uR4Sfi>X=H!gKQmBso2hGn4gMg>->&Usd#aKg{gQ^&|a8|FVAp$(MWUBRU&PC zuj8|@*g#R!;EIO-IoyC2X_tEpl0p?}^DQ0w|3%tGHrL(iNZW4G;j}k3NYvo&mVC_R z2DC_9RA!J^su6l+LdQ0snrOTttz#T_e2=kO*GChbWEM2oL5m!jnIotF2{D;zWR!(5U*S|osyWf9r&IhYF>jKmY1X%W8b&3nrV#fwPV{gU^x^cJ0bEl z8E!xuGZ*9-B$mqK^9wq*!6om`O6ZvK?ktC~sNL3-tJrOBr?UKZKFp^bcXmZkGnkiDgq078H`4{HNSdQu|2XSY4d~7J3*iYI2y& z;&#{`KYh3H3YS52P`iUkrdg2HFh4nF0%hBx+|D+YyU^uwTkXIj-%X-Un-QXBwI}ks z#km2^fmb>Vl4Rw;X+c408kc&X>*?i`1E<-HZ8f7_k9EY3UYn6fdPpL>IoyE8Xj-5> zWVA3S7cyFyVURGz=+dA;X0$b@gpIMomd;xXTBBg7w8*!2xn+&k^a6t+g?T}DVQ#yq z!gz|-`2kg?)ymi_J9XQq7lYAgfPglp_}G5v&YuBsqAdmW5y&<7$a)(i0AGa zh2YHnyZ{W{bXy{%z*CU$LX4wlc~BQdsaR$gs!cb$4(NO@7@Y;9I3j;&pi4_g*#IO) zU!Y&ncy-W|G>Svmwdt7uk<4wvuEP=aAxtHt>kEuEW0|OuHjnHwYa>{mjSZ)=$R8dw zps`#LfFaAP%G^`Pa!EzG>S=R{#dV`BKPpsVdD2%S-v`UFqUKSs>=SgPvAjCRt%fY` ztiaTyC^C9EVksK$uE3Nn?=-nwlx5Wut3}<~Tnv`uM2%~U{2?AUps`#QXE0=Wm!V_- zzbWWem+OM%)}4$`yt4N$U^yNm1qtn_1UI0ikEK}#iKWW?cQYhY#Riw`c2Al?83l&4 zrNIb)7Y2R` zMiWKN(>akpEXxgOjP7w6Bt|Nv%r zYPulu$)EvkNZ#mjtJJ$n!q+eqtO`Zr?KXpwCB6X*8YE05j->{d+e*8YoyCp)eh14* zqUIG#=PeT{pA zKEmPmgvsT?eGPU0D&f(n`np^ts?MG_;3rsY3j9?T`C5Y;)uKxMMwAYabyQS6<8VR3 z{(p&nmB)3XEPu&WVcD(Axc{R2siJ0mM&!F%+O)1}x{QYT(f4Rt$5iyKE;ANJ-$Ry;spP-b4zbFd z_FJ{Z&~D=nI|LS+CTbpnUwa2)G`~LPaI3^zMc+z8$JAozSxd*rulk4TD!)GEF&>S+ z-{MuGZ;$;h7z~!vMGbzLn(rEzLu2`3f?Ew)zToPZV)=Mn$Eve@#NcvKmQ|N*+pj!u zAXuIUmRXGC950eki#yj? zt_iS^%-|!BQ?P{~!B-=kGWEBk(<6)T}W@{@5}% zCHbmx`A~sD>Qk)))&>Q`mB}hDrY$?4%rYo-8KmK9m$8Udk1r&uMCjzEx$VGmCgwd) zM<$E~>LzbTyI;L2D=IB^;mam&!ZmU_& z9y9t+U^z$BynwjeKX8V|@-3HJ4OzN|jwzNK7*b>04!+8NP+b+5p9QAaYLv~ z&^uX7WyP0+o(NNZ{UE4ISarX?qcPvgt(L@#7e4@&7m1qZkQGmGgPy|s9$vB;l)a;f zX#5oaS0BmJAnbkoUwtAr>Y2z@$;ktkUs6Qx^Ko4>hgCzF8_;a@ewIP%N!jQfTgQ}* z8eAPC8;Qn`0(($hH9|k|xLlOw-kB;a_uX^uEU>&7*ABDTxGiu48p~HR42CRUF?Ebs z>K`gs-IH$yMI$V$&m5<2UicVTF2ITgdE^K?Xd%37wBRxrvivA0NSLzaA5Fbn3oHZG zU@2E%TeB@xcDj8r?ha60hznt^$R8PaN!x^Zr(8k7C3lAVZsFqV$7JDV9G37`yoYvG(uukId!Z zyI9n`Y>NB=m3-BFw7#tOsn-4BUY_Go~_ZHCxWFd zY9360WzeW*RrRYq>MgWtlSkj_6I%6qM*==peLR2Va=EQ$+5Mw#{n6EBuqCq2u@*O= zvHWY$YRK}3I2R0A{uopy?Efme@_?zvELaNA~@CCxkGT@5MXOwH98C^|O7x?>x^l=XstP-EXG*$2;f#=A85U zJ?B~OHZyOqO7SHi7GI&Vet6Ki|Ezv9jz^W}VJ&gN!H4j2lk=#UB}}Q@xEYljV!EFg zp&QdWCPwI|Her=2M+D9GCDBpuqRR6j@?aWrebbactL4vS>|!1jC6lVvVu$EmZ9$#gTuQv%*D!+{Bm{9rSKU9(rdsVgk$s@c% zW&Na}9v?k-(l40eB8WT`h1`KrN}#LE5U5msC>8D@TgSw>{3u0Oh06MAK|OwCe3%l_~>2 z8Fy5)&Hboy8AQGcVJ$sMpi~yN^9dxCw9j6t$15>bOMPR0rCMeQuTWWkdNH8K@hj!U9+!TVD$mLXs7yM&`lHHgAo4~EazkYTrLyT4 z2}+fPa7m{4ihI#!xJ z1ZiitzxxDMstmkRm@%V^jVb{mpW}KtB1H+5%0k#BP^tU_nL z)bbCH94l3x9}Sp2eLA(?8&zHhk+zf@3%SE79$)EtrqH5DD5<1<_R27(Qr}2rB_?Y5-wfdu zD(kPw1k`du>!VOa-3<`=mk+tYGJ&SDWuCHIwoe%-ky#LmF-;}6Dqr#grUmXo&=h6cA0}JU5LDzhFnsTYfl0< z_(qq9m}w3cIBU zWQzE``@){Kjx~C`#|aY0Mw4MXWeBXSTj0~dWa|@lMMZZ&yNJ!$j|P zDC&NqcRM;dCVID*PgsS@4ZVZTAEy1-g#DJUlW>L7K`gK4n!ZcS-6PQ>kyvFSy6| z_sJJkLLa=-*+T#BYswQp%h6|sz3pA?KSgn?u!MP>#vaAhu?g~#!v=XLTY=Qk`^z#g zA)y3r&0u0}=oLF7a1wULrY8&ds!ok>j316&>3vLV$cNM(KCt)*FOMzBXe z_d{e|5-&T8M6RifWe8+75-RIW9TQ{gfS8U25Bvch`C;$swX6@kwbbr|Nu5#U0}%Pd zgxu)Osl?O&(xy}na&=6ojAwOBEFuTybxh2PeI3GT9)m4c4)2XBAH<6g9D}1}0)1AL zv5PTyP?VU|7#v)Ni7|MvPkuEkG8TqSRP+$uRKR&U!KMV7qM;svj9n-ioYt{M^nk)X zn^AO-^s8CX;e$_0qM|HB-bq7lx=f%c8s>&dn^I&sIwlnLvvo|==n#i6rl_XxfwlQ9 z(Fzqk43Uq0JVh^30(J6R7#1UtDH12Y`=oX3Ta(oYZ`qYL?q@S>U|H-&pJ8^gVh5i9c(eb_fju{DpX?x%D<1r4E8Xa*(a^HhwZ$r%FGI6B(ZF`;Or^s8A>^6Oy_prR-7_>8O5@FXSG6peKV zR5coD>R6-4dTlEH6&v#tiX5A;niY-nPaBSkp2CaD4CH1+DS@VFf=i%MG*wDhHByVM zQZ$M}D<9i#I4Hi#`Va9+&Gy)JBOL%5XzX=`>Y>-KN-?ePe#XbsLo;-%6E%Up$*KtK0ji@&!EC zL6yUON}%7tTT$VsmN&D=TVOv(qQ*DZ`sAa#vFRmXyuj3e`dIfLkJCI9BL0T=(PEl4;359c# zIwop)oMdNyqLyd-x}T`!i7sKNvbLM$eUj}bpvtxQQJ@gy&bKLnwl*FvLB=lD#$)s3 z$Q5~P)j0?Mij867$d`^0R7b(5 z!Ppj8=CfmzKvQ&jl0cEJDLSo;U5xBh8735|g^(#1 zicUywv7-95gWf_51e&77MFLfg&dlprqsMyfG=juhW-{zphrpU^WcO%0 z6&1Y&Mw=MqPDoP%P0^`Y0+ph9wvGu!OENkpYNSpXNKtKH{xVjD-a}b=hX4C>DxDjxoL$_*UdKxBUx2{t*+zf33xxD?rn(t+l8Duj;T*O7fzHi zHAO{YVwfn(Ne*E(vv-~`=MiLo2kYTM?s%C%W1nMER>htoNE;+4Ckd>Xz5lxYY}mdF zk)LhIUF=Z;js0{9D)v*#>QS1;vK}?FPg_3mBV>OMm%0$-PFLje+oy$-H^Y9GO`fXq zi_?VF%sy$-sL{y&FEF+?_iQ)yzJt)!2E+{ys$h!nV)F)U?rmaVT776QtUHwW(u* z{h}mcHM5Vj$K8(XA0T@ca_W3eYx`wc%Brz%rtKGb~6k#>9@1K}E8QGh_z>C)0$$3hkv0v*FsM>zHsbiw@*GsHs z_9J_DdKlRYV6;f#jLT3`js0>7Dt2(lQMG+Vl(3rF2Y=kJJ+iOI%H!I9hDixDcE}T` z*w2+riv2p9{Ay<3^@#o_Ap1vP7})kRi6mEy@+4t3w|!E}v411Gk0(bC_Is8RXl=iCGwdr}a#U@?3<_dor?rjz`!mvKJ|V#=cZy zihX5_K*fHIPgu?Dt)5-ffb3sj<$cI4md(`I&vPiNVprG6iv9d7`PIzc;lapyWd9N( zzhl2INK*ohJ>w9l*l$egnCSOQ(uCE_KKb6xtB`#oM80z&w$W6eTOz9|bn?g< z15nnt5cxHY_thkuChJazQmbm+uVFN{9`|)WQLWW!!nQeEJ*icOWIbr=enQsGvYlHdYs%w?{D88)$HQ+Cau+z1S(9~(O`wvsTIyGw zc)ygu{DiE>Qxv;pvW^L#z8GZ{!Pwr$>o1S8XtEy65U6B5U@MHOwK}RWl68l~woKMy ztJ{w#>j#MZ7spmwHcpe}ZbsIvqyVP@$$G>gP*v-uf5@tOdt{$w!%ss+KjM-Vh1`W{ zN~$g9_eoF{>Xs}yD)t8?hD9lR68=>_;0aKV)uS&%_Mh-_DTbq`NJ+Ij?T_RMWK8RQ zwqV|E>X^9Go=xf)yVI_3EH>}3*jrPCSE~Fe8K82jc4PNKl|SQYRtE1PQ#`)P=TuL4 zgesMf+BzmwKI!UMu*$4QeibT%pREk|wZ-?S@)um?eZ1KdqXe4Do6-c5O4?_y4BN72 zE4O(RU!iitAH{%Lwp%)`9a8;@cbiSfT_QV8Q+d0TPAZ}BXqK2rB@`Ym^JBGy!X5Zm zY|Kye_&t)OQsv)4PbPa_U|fJI|BZ_+_V{@wCDl~kRi;Rc%e!oHR4Q*O>R3r-875TT zCoxo6+Y_LzCx`JfGIhVncY}_D*D#_f%m^X$lc&m0*(D1nN_jBR#p$e zzAj0@HM0-AYbKj(e}d7}|-13mS zJ5LETc28zi>~E&YQL(=w{c2`E^qzJy;6p4^cnVaUibUT zWY`O?j(v?gPc3#LPDAd_4CP{{8Uwd-8R=SwKrEE_mrsQ^bit*=?Nd?m!`lqvUp^I{ zBdGG>e|_NZEi8(*-=6)f7cLkswTuO!PYTx7<~@k5gQ+1Y3BEO zO2@>ax;9T(wQ?;cEI3A$Olgaay^aDiWy5^{TC5CBe^T2vg;HK1o1sGABX)7Fx(}X;0 z5~zf{9MiCpke6iZm5`i_ttRBKH{0Ms5pIdU(@})nl`iGigglidPzlLpG>n9Jgh?Sy zBc)&_+z{umW)1(9!YZmp!8_(~^)O|wlxQITM8n&j&k zAIVMA%KQRP2%C6qPW{E&mF5?rXgsdlcpHfPWJ2yHlj1aj8yx}_ z!SfQUMi6W2xGyGag9KT~T_NK%g12M;ASi4lOIeLz=+k4r#bgmMy2K#orYV;qD0GmZ zY(Zg2%>*OQ9yAb>8DR9vL+;k-W(aJLKt+&B5mv1QvzxnKhXmVV3p~iJawtw~!2-#u z2rem-V>N<4p%YHTWZQw!E(5viWG;>1N|{U%JVg2VfimcyG_qm3=iGz3VY2PPXpf`l zc3%d{VOn@DMW7^T>XRp|S_{Ts-Qxlzh=O4v!CfZBsTMR%mB|!=8gA7Hri6BEfys6N zqq~Cy+076<79&s+6b_Y2su2vc>uy7WwqWd%gxo!8%B5ORm?AMnaCe5lY6SH&=4`}d zJA$#F54lTI6sHlak)R}K`c}588bP1O7qL#>30r^!OY@r{xWXe)5;R|&C9E33_~qmA zu?1M7jLfB4(0r*+$rQn@X~L=z%;`S=2~5@whiMkqq9Vm<1UJfNDS|6aa;!$M zXkq`sn5;b*eN1RL+om{;V5I~VK}PyjBiMb>abIDw4meDU(2!2cKsnKxH?v$fFL%hX z8o|`eSvw*@M=u|;4;aoT5y?1j@4Rl#IL*WhXlKVv1bMv9^4#(I$2T#>g=Ez!IG<^eUP9#UZWJD zVOfTRX(hVZCr~3O5>}0%SFid#FxhTkbi)!|pQkvD;2PO1MR0kH9IFwG?%Vx)Ox6Pl zutayd6sHl~kS0(OTqKoLBj|kC;I5c#ckE;&xH(C=G=iH`1S*2%H50VBfA0q{Sx-Ex z$U?)FS<0mm+)yM?5nOB&R;>l0Ci6f{wg(;$kl;QUrx9G_P%=fZG)h=Cg0{U{u}vj4-F5+C{81|B2S=d!7`h$ zY6LsKclhg=tTz(iVt2ia(+M0(rU}0%=jox|m~0;~cEuLlC&g+6mzb1H5nPid ztQx_@WoNUqihaS@4LjMTFnpDLaFs`>BDmTmtQx_7=S^k9bU$nXmPkD()CiVkDVZWz zVG>r2;E?5!{V`b#jE)X8T;))lMsQ7$Kt-S~*sBrj*>v2ym~4L}DB=;#r(7DrwKjo@ z00^pbMElGf{A^?)ChG%6+bA?F^<|*ygB2M9H3I2atp(vO<5(XY0LG3nXt>{@Tv`ht zMW7;3S3Ok;R-amj$@+rP8C#$hPK{tQ_bQt2Fp0DpfjMsmKEVth2*y50@Q_Dw8o{b4 zfvN?MORO3}@2>~Hg30VFz08;HZygN9pD6sHk9Eiu)C$6Nxd5e)3L{fn6FAe?B}$?Dm= zMsSx$$rQm8dBUm@47$$fg~=?O2S{*hmf|#m=h6f!g8MRrRU?=+^~AF=SsaYM4m7AG zMk9FAreuoX&J?@ODkKj9EW3jkQBKDwLf_UsElVQ(z8YZ4gHb0uwu}@s)_fV8D z`CPL3QBTLd^qJptnqS#N6#pDI;FBP`tmwfmOom{^JY2?QQuPp}`Kb&svDU2TOph0J zj6XzazR%RL#x(7TR~DOhcx&W4Y~W~*di=$HfXbtvoVx~99*QH##ics0Qq!ZJ=4WFB zDwPj-Iwn*;?dw>u%KN2XrONZt0V=1jnKBYp9tOtlIQp(m6OmTS+p`2JmCw35CRE;T z>sYYLdt@mpR0cmbn=`TvJ3}6dDzV2QLqwX&`%?remG_n@7b+hq^9xp)%~QS#mGyx? zra9xwt>&Q0VYqJl(4emFHI?egkW%?vk(d}JR6cC$7*h$&50|w@j7vO}mbOZjfj`Y` z-VxdrRSpMZ4_y4OaVdeOvh0aaY4*G%>!DP>lA&OR36<|ebxf#ySH@PT^sjb;#^u^U zC!op^cmpT|4cD2JR8zTDVyc#}rwLRl*OVy|Dqr+}~lMUcuvzg+C0%EQ6v zk3D{aLkTpMZ>0!SDjSkICVKoWU&n&S<+`9+29L`zzqR}gRgMH>0QUGj#DlMLC3@E( zRH-Wm5u8<@0$0RV~#6 zTZRdh4W8~NRKA+jF`@Epm#_+z!M{8*&^ml5svHA`jjQ@wQjn(dowB-#TE1x#6RD(q z_R6r}aruEuz7;C{yS#uNw?>?T>sL4l#`p|0tjSOUP33!80#z*=eH|0EeA(79QAnNN}{0wh$gtZ;290x|f zC^V=^q1Q4)S(VB+Y#kG|eBaYCQOmWyj)_|4rC){0`WBgh9v`!|%@3$@JQxE*(C}`I zl4>eHkf2ies$`;CLi5@b1ye1d`L(iGq4G7C{3=xj{wu>F=6-CwoPa8Ej=yA50!`%$ zHi1gz`$-+!vf1-tkz!G0ZJ&ppdG9GWvBML=7-B-hV-6)?A2=HDoz2d^Zp#zMRDN$V z?DeRQHF^yD+10TolVL@hu!_0`|D(!@&oB536-@%;5bWKxX-c5gZG%gos@o<<$HW-? z$wcn^Kc)z)P#L^}_n5pl z8<$hTNTi|RN!d(I<l&HZxQs3meKF*`6#NK2FCChG^|U>4C-k3OO!yR@_R?e zM2~+`h6UHsm-)h>@QTkb_wXaDFz{{%2E5JwS3t&N27WyJV;}ccI4eHC${#d2fw$V~ z@bOoD401b3m31h+^sfV~b-t2>3!XUHitA)`s2~3gK&X~)=@#A4zFm&Q^v8e^cc9@7 zN{+8`J^t1ul=q9r*4a<;3M+lvt@$fkVK|FT=I0j)<5jrSFR#Mo=0B^DxGVJmRskQO z)q6ozcv_~#+Q=&Wl~!bRby)Pvyif~XbTs|)T2GkM39o_b@HyJZOc_fX{C{bss(#~Z z`6_Nky`2tNs282riCqFZU>t@8ebJ*7+JxAo6_0M2eHSH1R%9{MKDBjBEH0lDq@5mq zmnN`cLIf`^vA$idN0rmTn1Iuktx>eeQ|-@F1TjVHecqjE9ow>L+az0Eq0(;*1=RAi zVN`LSTK_5K&A}yVOuGv zV6&a@ad?*R1_e!anGf4aLB7p)!gFvQ6@!ANM41oUNIzFCl$1T1L1{W z3=XWG`kZEo$xpK^;ZyNCA``@vUMt9NUf z`LL}Nw9(@`XW|)JU?J3FrBcwB4i7pDk7C)NLgZZL!?se;CWr4V0b@imDCk+2`LL}N zgwI6S&e=HK1DRfOxD)deh1ldWAbbvxMZ+qH7^3-W|Dd@8_4>}jy zMt1XBimBm_b46sZ%NF zQ=bQ23C7W>pr9vsV(wR3jXb`S0ps+*pr?K2!!}}a_|8?>reqM)s~+=V8wI(1=V~xc zaDsx=GpbV1XEqPI28^k})yps+wzU*(`rKtZ;pJdVF9tEGXPu>>FIY?{d@UIBg4>kj zPWY!3^d;X9uK;6iG>GXjw<2hx2m&z92n7YHM>i#=jV6l|H_QE%SF*~pj>iHK1xjg7bFct?gt(W~&>fG;r9<&mSaB7Hi4elpK#CIOwxfy4!8^p9B#(daTlGp6>om;?|;sph5j4~g#m4dzz zJ1z#rf`Z<5xswViilAG;Sl|Q&eUh&T`Zmpg@NKw81eV+vnVFv`#J4UFx*b>8Oc0a0 z{w@W5&0<2~J8(V)%KO^nPRvg*6*&;T6Q_GIh)La&Ed@1;pu51B6WFHrlf=XhpP{AwJsC;8s0H{1@S^AU?*{U}xF^KOx)-b7wU8oV6{^LwIY557WKJelV9!!qy09 zHSe~+PCpglZ6JPutHGiCME2mk4a8UIxfdF7ycZCPKzwOh^B(fxcEb=hAihke?DzZ` z7bCna#37}5Px9yQf$(+^U#Tk@)p}B2gtv$I14+$$L29pG5RM}3Y49m?TCv9O0CD{8 zkm{Yi8mI4sa9fB!sKXOSp7bihJ3{;hU3Z6eE!lv*?FX=zZMz|})pU7+Q zi8HnufN(eTE-E;j=+$l>!Y0JmXi36#MvNW1c7-^8B12M!`=++}H^SY~TT>FAdR?+5 z!n;BIO;ht8@>k0b5bgnSeC(-`w7AXcj_~f7L{~Da|FL%?+!Nw2>6Ff|le!|j2gIM$ zlN`Ka)_Vx=3Gr8S%E^tpT#oQw5Pv+XQSLr>w-~~`ApTZJgF8AMCnCHz#PJ!S64oDUPf9|ZA#nHoI*f~jvHY(f0D=NS|NNe#NSD4@G)(>J&&*r@sIS}JN>+ki|`KiE9_u|)A$++9Rl$$#Gzpb#J_Yob|^BZxOEuBzu`t`D8xT;xH$~spPAemj_(S; z5!eKqV~3->BDY3Dydbbqs7?5dM$6~#jzP8@bI0<1urVTN5Duv51%mi8_yClOSHY<9QUsn*}x*;=l7ZLsKALw7EGI;(rynbu`9` zEYl#-BF(X5AYOW$xl6KDHyvu@oe>64uGc z>vQZBi2su2)&fYh%5ZBT=5x4pD#U*?xwQx_@$PAm=q#+$A+fX1-#r5ooosF`hQvt;ns5@!b@+E`fw0-n|sr(j2=CBeLAO9C=-CErmoEpIcWz zVi&=&3=+F>D0C$xqA_k}P<@nJS3#ny%dM-CS76sbqGO(8%OMeQxOFXB0$Txz?R<^_ zB>D^MI!FxgICecGdI;+VNc78c>_$i=Om3}&#NJ76-2{m~9=C3WL@dLtTOhGNH}EHu z5($CbiV?!^Hc0eM^S5tD-W0d)fW$#jZrurqeI0Jyg;~VAcSB+y@$M=}42uutsc_9P?@6WCLbI3&-_ry(&W#;s={F(JL9=Be^SYb6lVibo$IpnpuxdswL#k(&-Vwhli84@G% z{M}a|G1BDLT8tGOuYxrt!?D-Enrw6Hb+oeFS_jrl;r9kuBgMOKf;FDM8F~w>Q6@L@ zU`us=(_PF&9SV!c!^)6V`TyDJw))Ufs{qz90$Y#zI28H_tf|8K7$c(G+yK@DkeU5#C`ULhVSYy*1`wT26 z&#liJxq~!J6%IY%5fn47auc>w+w| z+JJS5%dH4lm)qPjz*;K&wgu~Ifo%uYl`;PA_F!F{}81-1iN%LLXItSi`?p}HN> z&*RokV5P;oJA-wO&#`u3-I(H5d$6vzxzz!zON-p<2-dkVZgm3dyfn8ugLS^ctu7dm z<<>5kg&Co`u3%kba;qCyS2^4=QH#&5UBMDRhEUfXv*bCp8*;eZ>VfJ#ZtV`%MJaCe zM9b&a9$;mn+}abZG`IFbUY}dNz~WLub$f&LAUErJgLPkwzq=1u4>;V~7p*+E_5*9R zcsB;t{ZWqX57x>gxB7tPX1R3$Sht$o>WdsHZXF2LZ9cd9fpv3{TlHYwndVl1#G>39 zfDt~o2BH?1TL*!4hp;TL9upjKux|JGy9u!F71qIE-4x@P4b~%RZVdwK31)=q2IIRf zw+;d8mOQtHfOVI{twX`O+ve6`XbFy?V6Dn zg7u`wtx;gT%ZyOnXt16WS;m0%Y?fn5RONGPELg9b+&Tg*c2bKGMm_D{>SlrUN{m~x!Ft(aR*RFM=@pY(^P#CB$*fk} OLgAnyx3-5uBJ)3J((4ug literal 0 HcmV?d00001 diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.p2t b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.p2t new file mode 100644 index 0000000..16daf53 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.p2t @@ -0,0 +1,9 @@ +-w +-l 5 +-i 6 +-n 1 +-t 1 +-s 1 +-c 0 +-e 0 +-exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.p3t b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.p3t new file mode 100644 index 0000000..1635283 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.p3t @@ -0,0 +1,5 @@ +-rem +-distrce +-log "RAM2GS_LCMXO2_1200HC_impl1.log" +-o "RAM2GS_LCMXO2_1200HC_impl1.csv" +-pr "RAM2GS_LCMXO2_1200HC_impl1.prf" diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pad b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pad new file mode 100644 index 0000000..dd18c97 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pad @@ -0,0 +1,309 @@ +PAD Specification File +*************************** + +PART TYPE: LCMXO2-1200HC +Performance Grade: 4 +PACKAGE: TQFP100 +Package Status: Final Version 1.44 + +Tue Aug 15 05:03:35 2023 + +Pinout by Port Name: ++-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+ +| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties | ++-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+ +| CROW[0] | 10/3 | LVCMOS25_IN | PL4B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| CROW[1] | 16/3 | LVCMOS25_IN | PL8A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[0] | 3/3 | LVCMOS25_IN | PL3A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[1] | 96/0 | LVCMOS25_IN | PT10B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[2] | 88/0 | LVCMOS25_IN | PT12A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[3] | 97/0 | LVCMOS25_IN | PT10A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[4] | 99/0 | LVCMOS25_IN | PT9A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[5] | 98/0 | LVCMOS25_IN | PT9B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[6] | 2/3 | LVCMOS25_IN | PL2D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[7] | 1/3 | LVCMOS25_IN | PL2C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Dout[0] | 76/0 | LVCMOS25_OUT | PT17D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[1] | 86/0 | LVCMOS25_OUT | PT12C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[2] | 87/0 | LVCMOS25_OUT | PT12B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[3] | 85/0 | LVCMOS25_OUT | PT12D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[4] | 83/0 | LVCMOS25_OUT | PT15B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[5] | 84/0 | LVCMOS25_OUT | PT15A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[6] | 78/0 | LVCMOS25_OUT | PT16C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[7] | 82/0 | LVCMOS25_OUT | PT15C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| LED | 34/2 | LVCMOS25_OUT | PB9A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| MAin[0] | 14/3 | LVCMOS25_IN | PL5C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[1] | 12/3 | LVCMOS25_IN | PL5A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[2] | 13/3 | LVCMOS25_IN | PL5B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[3] | 21/3 | LVCMOS25_IN | PL9B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[4] | 20/3 | LVCMOS25_IN | PL9A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[5] | 19/3 | LVCMOS25_IN | PL8D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[6] | 24/3 | LVCMOS25_IN | PL10C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[7] | 18/3 | LVCMOS25_IN | PL8C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[8] | 25/3 | LVCMOS25_IN | PL10D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[9] | 32/2 | LVCMOS25_IN | PB6D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| PHI2 | 8/3 | LVCMOS25_IN | PL3D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| RA[0] | 66/1 | LVCMOS25_OUT | PR4D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[10] | 64/1 | LVCMOS25_OUT | PR5B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[11] | 59/1 | LVCMOS25_OUT | PR8D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[1] | 67/1 | LVCMOS25_OUT | PR4C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[2] | 69/1 | LVCMOS25_OUT | PR4A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[3] | 71/1 | LVCMOS25_OUT | PR3A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[4] | 74/1 | LVCMOS25_OUT | PR2B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[5] | 70/1 | LVCMOS25_OUT | PR3B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[6] | 68/1 | LVCMOS25_OUT | PR4B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[7] | 75/1 | LVCMOS25_OUT | PR2A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[8] | 65/1 | LVCMOS25_OUT | PR5A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[9] | 63/1 | LVCMOS25_OUT | PR5C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RBA[0] | 58/1 | LVCMOS25_OUT | PR9A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RBA[1] | 60/1 | LVCMOS25_OUT | PR8C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RCKE | 53/1 | LVCMOS25_OUT | PR9D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RCLK | 62/1 | LVCMOS25_IN | PR5D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| RDQMH | 51/1 | LVCMOS25_OUT | PR10D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RDQML | 48/2 | LVCMOS25_OUT | PB20C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RD[0] | 36/2 | LVCMOS25_BIDI | PB11C | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[1] | 37/2 | LVCMOS25_BIDI | PB11D | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[2] | 38/2 | LVCMOS25_BIDI | PB11A | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[3] | 39/2 | LVCMOS25_BIDI | PB11B | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[4] | 40/2 | LVCMOS25_BIDI | PB15A | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[5] | 41/2 | LVCMOS25_BIDI | PB15B | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[6] | 42/2 | LVCMOS25_BIDI | PB18A | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[7] | 43/2 | LVCMOS25_BIDI | PB18B | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| UFMCLK | 29/2 | LVCMOS25_OUT | PB6A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| UFMSDI | 30/2 | LVCMOS25_OUT | PB6B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| UFMSDO | 27/2 | LVCMOS25_IN | PB4C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| nCCAS | 9/3 | LVCMOS25_IN | PL4A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| nCRAS | 17/3 | LVCMOS25_IN | PL8B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| nFWE | 28/2 | LVCMOS25_IN | PB4D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| nRCAS | 52/1 | LVCMOS25_OUT | PR10C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| nRCS | 57/1 | LVCMOS25_OUT | PR9B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| nRRAS | 54/1 | LVCMOS25_OUT | PR9C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| nRWE | 49/2 | LVCMOS25_OUT | PB20D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| nUFMCS | 47/2 | LVCMOS25_OUT | PB18D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | ++-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+ + +Vccio by Bank: ++------+-------+ +| Bank | Vccio | ++------+-------+ +| 0 | 2.5V | +| 1 | 2.5V | +| 2 | 2.5V | +| 3 | 2.5V | ++------+-------+ + +Vref by Bank: ++------+-----+-----------------+---------+ +| Vref | Pin | Bank # / Vref # | Load(s) | ++------+-----+-----------------+---------+ ++------+-----+-----------------+---------+ + +Pinout by Pin Number: ++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ +| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable | ++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ +| 1/3 | Din[7] | LOCATED | LVCMOS25_IN | PL2C | L_GPLLT_IN | | | +| 2/3 | Din[6] | LOCATED | LVCMOS25_IN | PL2D | L_GPLLC_IN | | | +| 3/3 | Din[0] | LOCATED | LVCMOS25_IN | PL3A | PCLKT3_2 | | | +| 4/3 | unused, PULL:DOWN | | | PL3B | PCLKC3_2 | | | +| 7/3 | unused, PULL:DOWN | | | PL3C | | | | +| 8/3 | PHI2 | LOCATED | LVCMOS25_IN | PL3D | | | | +| 9/3 | nCCAS | LOCATED | LVCMOS25_IN | PL4A | | | | +| 10/3 | CROW[0] | LOCATED | LVCMOS25_IN | PL4B | | | | +| 12/3 | MAin[1] | LOCATED | LVCMOS25_IN | PL5A | PCLKT3_1 | | | +| 13/3 | MAin[2] | LOCATED | LVCMOS25_IN | PL5B | PCLKC3_1 | | | +| 14/3 | MAin[0] | LOCATED | LVCMOS25_IN | PL5C | | | | +| 15/3 | unused, PULL:DOWN | | | PL5D | | | | +| 16/3 | CROW[1] | LOCATED | LVCMOS25_IN | PL8A | | | | +| 17/3 | nCRAS | LOCATED | LVCMOS25_IN | PL8B | | | | +| 18/3 | MAin[7] | LOCATED | LVCMOS25_IN | PL8C | | | | +| 19/3 | MAin[5] | LOCATED | LVCMOS25_IN | PL8D | | | | +| 20/3 | MAin[4] | LOCATED | LVCMOS25_IN | PL9A | PCLKT3_0 | | | +| 21/3 | MAin[3] | LOCATED | LVCMOS25_IN | PL9B | PCLKC3_0 | | | +| 24/3 | MAin[6] | LOCATED | LVCMOS25_IN | PL10C | | | | +| 25/3 | MAin[8] | LOCATED | LVCMOS25_IN | PL10D | | | | +| 27/2 | UFMSDO | LOCATED | LVCMOS25_IN | PB4C | CSSPIN | | | +| 28/2 | nFWE | LOCATED | LVCMOS25_IN | PB4D | | | | +| 29/2 | UFMCLK | LOCATED | LVCMOS25_OUT | PB6A | | | | +| 30/2 | UFMSDI | LOCATED | LVCMOS25_OUT | PB6B | | | | +| 31/2 | unused, PULL:DOWN | | | PB6C | MCLK/CCLK | | | +| 32/2 | MAin[9] | LOCATED | LVCMOS25_IN | PB6D | SO/SPISO | | | +| 34/2 | LED | LOCATED | LVCMOS25_OUT | PB9A | PCLKT2_0 | | | +| 35/2 | unused, PULL:DOWN | | | PB9B | PCLKC2_0 | | | +| 36/2 | RD[0] | LOCATED | LVCMOS25_BIDI | PB11C | | | | +| 37/2 | RD[1] | LOCATED | LVCMOS25_BIDI | PB11D | | | | +| 38/2 | RD[2] | LOCATED | LVCMOS25_BIDI | PB11A | PCLKT2_1 | | | +| 39/2 | RD[3] | LOCATED | LVCMOS25_BIDI | PB11B | PCLKC2_1 | | | +| 40/2 | RD[4] | LOCATED | LVCMOS25_BIDI | PB15A | | | | +| 41/2 | RD[5] | LOCATED | LVCMOS25_BIDI | PB15B | | | | +| 42/2 | RD[6] | LOCATED | LVCMOS25_BIDI | PB18A | | | | +| 43/2 | RD[7] | LOCATED | LVCMOS25_BIDI | PB18B | | | | +| 45/2 | unused, PULL:DOWN | | | PB18C | | | | +| 47/2 | nUFMCS | | LVCMOS25_OUT | PB18D | | | | +| 48/2 | RDQML | LOCATED | LVCMOS25_OUT | PB20C | SN | | | +| 49/2 | nRWE | LOCATED | LVCMOS25_OUT | PB20D | SI/SISPI | | | +| 51/1 | RDQMH | LOCATED | LVCMOS25_OUT | PR10D | DQ1 | | | +| 52/1 | nRCAS | LOCATED | LVCMOS25_OUT | PR10C | DQ1 | | | +| 53/1 | RCKE | LOCATED | LVCMOS25_OUT | PR9D | DQ1 | | | +| 54/1 | nRRAS | LOCATED | LVCMOS25_OUT | PR9C | DQ1 | | | +| 57/1 | nRCS | LOCATED | LVCMOS25_OUT | PR9B | DQ1 | | | +| 58/1 | RBA[0] | LOCATED | LVCMOS25_OUT | PR9A | DQ1 | | | +| 59/1 | RA[11] | LOCATED | LVCMOS25_OUT | PR8D | DQ1 | | | +| 60/1 | RBA[1] | LOCATED | LVCMOS25_OUT | PR8C | DQ1 | | | +| 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | | +| 62/1 | RCLK | LOCATED | LVCMOS25_IN | PR5D | PCLKC1_0/DQ0 | | | +| 63/1 | RA[9] | LOCATED | LVCMOS25_OUT | PR5C | PCLKT1_0/DQ0 | | | +| 64/1 | RA[10] | LOCATED | LVCMOS25_OUT | PR5B | DQS0N | | | +| 65/1 | RA[8] | LOCATED | LVCMOS25_OUT | PR5A | DQS0 | | | +| 66/1 | RA[0] | LOCATED | LVCMOS25_OUT | PR4D | DQ0 | | | +| 67/1 | RA[1] | LOCATED | LVCMOS25_OUT | PR4C | DQ0 | | | +| 68/1 | RA[6] | LOCATED | LVCMOS25_OUT | PR4B | DQ0 | | | +| 69/1 | RA[2] | LOCATED | LVCMOS25_OUT | PR4A | DQ0 | | | +| 70/1 | RA[5] | LOCATED | LVCMOS25_OUT | PR3B | DQ0 | | | +| 71/1 | RA[3] | LOCATED | LVCMOS25_OUT | PR3A | DQ0 | | | +| 74/1 | RA[4] | LOCATED | LVCMOS25_OUT | PR2B | DQ0 | | | +| 75/1 | RA[7] | LOCATED | LVCMOS25_OUT | PR2A | DQ0 | | | +| 76/0 | Dout[0] | LOCATED | LVCMOS25_OUT | PT17D | DONE | | | +| 77/0 | unused, PULL:DOWN | | | PT17C | INITN | | | +| 78/0 | Dout[6] | LOCATED | LVCMOS25_OUT | PT16C | | | | +| 81/0 | unused, PULL:DOWN | | | PT15D | PROGRAMN | | | +| 82/0 | Dout[7] | LOCATED | LVCMOS25_OUT | PT15C | JTAGENB | | | +| 83/0 | Dout[4] | LOCATED | LVCMOS25_OUT | PT15B | | | | +| 84/0 | Dout[5] | LOCATED | LVCMOS25_OUT | PT15A | | | | +| 85/0 | Dout[3] | LOCATED | LVCMOS25_OUT | PT12D | SDA/PCLKC0_0 | | | +| 86/0 | Dout[1] | LOCATED | LVCMOS25_OUT | PT12C | SCL/PCLKT0_0 | | | +| 87/0 | Dout[2] | LOCATED | LVCMOS25_OUT | PT12B | PCLKC0_1 | | | +| 88/0 | Din[2] | LOCATED | LVCMOS25_IN | PT12A | PCLKT0_1 | | | +| 90/0 | Reserved: sysCONFIG | | | PT11D | TMS | | | +| 91/0 | Reserved: sysCONFIG | | | PT11C | TCK | | | +| 94/0 | Reserved: sysCONFIG | | | PT10D | TDI | | | +| 95/0 | Reserved: sysCONFIG | | | PT10C | TDO | | | +| 96/0 | Din[1] | LOCATED | LVCMOS25_IN | PT10B | | | | +| 97/0 | Din[3] | LOCATED | LVCMOS25_IN | PT10A | | | | +| 98/0 | Din[5] | LOCATED | LVCMOS25_IN | PT9B | | | | +| 99/0 | Din[4] | LOCATED | LVCMOS25_IN | PT9A | | | | +| PB4A/2 | unused, PULL:DOWN | | | PB4A | | | | +| PB4B/2 | unused, PULL:DOWN | | | PB4B | | | | +| PB9C/2 | unused, PULL:DOWN | | | PB9C | | | | +| PB9D/2 | unused, PULL:DOWN | | | PB9D | | | | +| PB15C/2 | unused, PULL:DOWN | | | PB15C | | | | +| PB15D/2 | unused, PULL:DOWN | | | PB15D | | | | +| PB20A/2 | unused, PULL:DOWN | | | PB20A | | | | +| PB20B/2 | unused, PULL:DOWN | | | PB20B | | | | +| PL2A/3 | unused, PULL:DOWN | | | PL2A | L_GPLLT_FB | | | +| PL2B/3 | unused, PULL:DOWN | | | PL2B | L_GPLLC_FB | | | +| PL4C/3 | unused, PULL:DOWN | | | PL4C | | | | +| PL4D/3 | unused, PULL:DOWN | | | PL4D | | | | +| PL10A/3 | unused, PULL:DOWN | | | PL10A | | | | +| PL10B/3 | unused, PULL:DOWN | | | PL10B | | | | +| PR2C/1 | unused, PULL:DOWN | | | PR2C | DQ0 | | | +| PR2D/1 | unused, PULL:DOWN | | | PR2D | DQ0 | | | +| PR8B/1 | unused, PULL:DOWN | | | PR8B | DQS1N | | | +| PR10A/1 | unused, PULL:DOWN | | | PR10A | DQ1 | | | +| PR10B/1 | unused, PULL:DOWN | | | PR10B | DQ1 | | | +| PT9C/0 | unused, PULL:DOWN | | | PT9C | | | | +| PT9D/0 | unused, PULL:DOWN | | | PT9D | | | | +| PT11A/0 | unused, PULL:DOWN | | | PT11A | | | | +| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | | +| PT16A/0 | unused, PULL:DOWN | | | PT16A | | | | +| PT16B/0 | unused, PULL:DOWN | | | PT16B | | | | +| PT16D/0 | unused, PULL:DOWN | | | PT16D | | | | +| PT17A/0 | unused, PULL:DOWN | | | PT17A | | | | +| PT17B/0 | unused, PULL:DOWN | | | PT17B | | | | ++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ + +sysCONFIG Pins: ++----------+--------------------+--------------------+----------+-------------+-------------------+ +| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode | ++----------+--------------------+--------------------+----------+-------------+-------------------+ +| PT11D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP | +| PT11C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down | +| PT10D | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP | +| PT10C | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP | ++----------+--------------------+--------------------+----------+-------------+-------------------+ + +Dedicated sysCONFIG Pins: + + +List of All Pins' Locate Preferences Based on Final Placement After PAR +to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): + +LOCATE COMP "CROW[0]" SITE "10"; +LOCATE COMP "CROW[1]" SITE "16"; +LOCATE COMP "Din[0]" SITE "3"; +LOCATE COMP "Din[1]" SITE "96"; +LOCATE COMP "Din[2]" SITE "88"; +LOCATE COMP "Din[3]" SITE "97"; +LOCATE COMP "Din[4]" SITE "99"; +LOCATE COMP "Din[5]" SITE "98"; +LOCATE COMP "Din[6]" SITE "2"; +LOCATE COMP "Din[7]" SITE "1"; +LOCATE COMP "Dout[0]" SITE "76"; +LOCATE COMP "Dout[1]" SITE "86"; +LOCATE COMP "Dout[2]" SITE "87"; +LOCATE COMP "Dout[3]" SITE "85"; +LOCATE COMP "Dout[4]" SITE "83"; +LOCATE COMP "Dout[5]" SITE "84"; +LOCATE COMP "Dout[6]" SITE "78"; +LOCATE COMP "Dout[7]" SITE "82"; +LOCATE COMP "LED" SITE "34"; +LOCATE COMP "MAin[0]" SITE "14"; +LOCATE COMP "MAin[1]" SITE "12"; +LOCATE COMP "MAin[2]" SITE "13"; +LOCATE COMP "MAin[3]" SITE "21"; +LOCATE COMP "MAin[4]" SITE "20"; +LOCATE COMP "MAin[5]" SITE "19"; +LOCATE COMP "MAin[6]" SITE "24"; +LOCATE COMP "MAin[7]" SITE "18"; +LOCATE COMP "MAin[8]" SITE "25"; +LOCATE COMP "MAin[9]" SITE "32"; +LOCATE COMP "PHI2" SITE "8"; +LOCATE COMP "RA[0]" SITE "66"; +LOCATE COMP "RA[10]" SITE "64"; +LOCATE COMP "RA[11]" SITE "59"; +LOCATE COMP "RA[1]" SITE "67"; +LOCATE COMP "RA[2]" SITE "69"; +LOCATE COMP "RA[3]" SITE "71"; +LOCATE COMP "RA[4]" SITE "74"; +LOCATE COMP "RA[5]" SITE "70"; +LOCATE COMP "RA[6]" SITE "68"; +LOCATE COMP "RA[7]" SITE "75"; +LOCATE COMP "RA[8]" SITE "65"; +LOCATE COMP "RA[9]" SITE "63"; +LOCATE COMP "RBA[0]" SITE "58"; +LOCATE COMP "RBA[1]" SITE "60"; +LOCATE COMP "RCKE" SITE "53"; +LOCATE COMP "RCLK" SITE "62"; +LOCATE COMP "RDQMH" SITE "51"; +LOCATE COMP "RDQML" SITE "48"; +LOCATE COMP "RD[0]" SITE "36"; +LOCATE COMP "RD[1]" SITE "37"; +LOCATE COMP "RD[2]" SITE "38"; +LOCATE COMP "RD[3]" SITE "39"; +LOCATE COMP "RD[4]" SITE "40"; +LOCATE COMP "RD[5]" SITE "41"; +LOCATE COMP "RD[6]" SITE "42"; +LOCATE COMP "RD[7]" SITE "43"; +LOCATE COMP "UFMCLK" SITE "29"; +LOCATE COMP "UFMSDI" SITE "30"; +LOCATE COMP "UFMSDO" SITE "27"; +LOCATE COMP "nCCAS" SITE "9"; +LOCATE COMP "nCRAS" SITE "17"; +LOCATE COMP "nFWE" SITE "28"; +LOCATE COMP "nRCAS" SITE "52"; +LOCATE COMP "nRCS" SITE "57"; +LOCATE COMP "nRRAS" SITE "54"; +LOCATE COMP "nRWE" SITE "49"; +LOCATE COMP "nUFMCS" SITE "47"; + + + + + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:38 2023 + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.par b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.par new file mode 100644 index 0000000..89d3d6a --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.par @@ -0,0 +1,329 @@ +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:31 2023 + +C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_1200HC_impl1.p2t +RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir +RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset +D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml + + +Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf. + +Level/ Number Worst Timing Worst Timing Run NCD +Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status +---------- -------- ----- ------ ----------- ----------- ---- ------ +5_1 * 0 -4.650 391939 0.304 0 08 Completed + +* : Design saved. + +Total (real) run time for 1-seed: 8 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Lattice Place and Route Report for Design "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" +Tue Aug 15 05:03:31 2023 + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf +Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf. +Placement level-cost: 5-1. +Routing Iterations: 6 + +Loading design for application par from file RAM2GS_LCMXO2_1200HC_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 4 +Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +License checked out. + + +Ignore Preference Error(s): True +Device utilization summary: + + PIO (prelim) 67+4(JTAG)/108 66% used + 67+4(JTAG)/80 89% bonded + + SLICE 75/640 11% used + + + +Number of Signals: 285 +Number of Connections: 674 +WARNING - par: Placement timing preferences are hard to meet. However, placement will continue. Use static timing analysis to identify errors. + +Pin Constraint Summary: + 66 out of 67 pins locked (98% locked). + +The following 2 signals are selected to use the primary clock routing resources: + RCLK_c (driver: RCLK, clk load #: 40) + PHI2_c (driver: PHI2, clk load #: 13) + +WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. +WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. + +The following 1 signal is selected to use the secondary clock routing resources: + nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0) + +WARNING - par: Signal "nCRAS_c" is selected to use Secondary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. +No signal is selected as Global Set/Reset. +. +Starting Placer Phase 0. +.......... +Finished Placer Phase 0. REAL time: 0 secs + +Starting Placer Phase 1. +................... +Placer score = 143529. +Finished Placer Phase 1. REAL time: 4 secs + +Starting Placer Phase 2. +. +Placer score = 143450 +Finished Placer Phase 2. REAL time: 4 secs + + +------------------ Clock Report ------------------ + +Global Clock Resources: + CLK_PIN : 0 out of 8 (0%) + General PIO: 3 out of 108 (2%) + PLL : 0 out of 1 (0%) + DCM : 0 out of 2 (0%) + DCC : 0 out of 8 (0%) + +Global Clocks: + PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 40 + PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3D)", clk load = 13 + SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL8B)", clk load = 7, ce load = 0, sr load = 0 + + PRIMARY : 2 out of 8 (25%) + SECONDARY: 1 out of 8 (12%) + +Edge Clocks: + No edge clock selected. + +--------------- End of Clock Report --------------- + + +I/O Usage Summary (final): + 67 + 4(JTAG) out of 108 (65.7%) PIO sites used. + 67 + 4(JTAG) out of 80 (88.8%) bonded PIO sites used. + Number of PIO comps: 67; differential: 0. + Number of Vref pins used: 0. + +I/O Bank Usage Summary: ++----------+----------------+------------+-----------+ +| I/O Bank | Usage | Bank Vccio | Bank Vref | ++----------+----------------+------------+-----------+ +| 0 | 13 / 19 ( 68%) | 2.5V | - | +| 1 | 20 / 21 ( 95%) | 2.5V | - | +| 2 | 17 / 20 ( 85%) | 2.5V | - | +| 3 | 17 / 20 ( 85%) | 2.5V | - | ++----------+----------------+------------+-----------+ + +Total placer CPU time: 4 secs + +Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd. + +0 connections routed; 674 unrouted. +Starting router resource preassignment +WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. +WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. + +WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. + Signal=nCCAS_c loads=6 clock_loads=4 + +Completed router resource preassignment. Real time: 7 secs + +Start NBR router at 05:03:38 08/15/23 + +***************************************************************** +Info: NBR allows conflicts(one node used by more than one signal) + in the earlier iterations. In each iteration, it tries to + solve the conflicts while keeping the critical connections + routed as short as possible. The routing process is said to + be completed when no conflicts exist and all connections + are routed. +Note: NBR uses a different method to calculate timing slacks. The + worst slack and total negative slack may not be the same as + that in TRCE report. You should always run TRCE to verify + your design. +***************************************************************** + +Start NBR special constraint process at 05:03:38 08/15/23 + +Start NBR section for initial routing at 05:03:38 08/15/23 +Level 1, iteration 1 +2(0.00%) conflicts; 537(79.67%) untouched conns; 468417 (nbr) score; +Estimated worst slack/total negative slack: -5.186ns/-468.418ns; real time: 7 secs +Level 2, iteration 1 +11(0.01%) conflicts; 474(70.33%) untouched conns; 377050 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-377.051ns; real time: 8 secs +Level 3, iteration 1 +20(0.02%) conflicts; 254(37.69%) untouched conns; 373495 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-373.496ns; real time: 8 secs +Level 4, iteration 1 +11(0.01%) conflicts; 0(0.00%) untouched conn; 386254 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-386.255ns; real time: 8 secs + +Info: Initial congestion level at 75% usage is 0 +Info: Initial congestion area at 75% usage is 0 (0.00%) + +Start NBR section for normal routing at 05:03:39 08/15/23 +Level 1, iteration 1 +7(0.01%) conflicts; 4(0.59%) untouched conns; 379537 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-379.537ns; real time: 8 secs +Level 4, iteration 1 +9(0.01%) conflicts; 0(0.00%) untouched conn; 380799 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-380.800ns; real time: 8 secs +Level 4, iteration 2 +6(0.01%) conflicts; 0(0.00%) untouched conn; 390586 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-390.587ns; real time: 8 secs +Level 4, iteration 3 +6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-384.719ns; real time: 8 secs +Level 4, iteration 4 +6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-384.719ns; real time: 8 secs +Level 4, iteration 5 +4(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.014ns; real time: 8 secs +Level 4, iteration 6 +3(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.014ns; real time: 8 secs +Level 4, iteration 7 +3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.875ns; real time: 8 secs +Level 4, iteration 8 +3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.875ns; real time: 8 secs +Level 4, iteration 9 +2(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-409.289ns; real time: 8 secs +Level 4, iteration 10 +3(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-409.289ns; real time: 8 secs +Level 4, iteration 11 +3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.036ns; real time: 8 secs +Level 4, iteration 12 +3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.036ns; real time: 8 secs +Level 4, iteration 13 +2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score; +Estimated worst slack/total negative slack: -4.574ns/-404.327ns; real time: 8 secs +Level 4, iteration 14 +2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score; +Estimated worst slack/total negative slack: -4.574ns/-404.327ns; real time: 8 secs +Level 4, iteration 15 +2(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 16 +3(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 17 +2(0.00%) conflicts; 0(0.00%) untouched conn; 404668 (nbr) score; +Estimated worst slack/total negative slack: -4.574ns/-404.669ns; real time: 8 secs +Level 4, iteration 18 +1(0.00%) conflict; 0(0.00%) untouched conn; 404668 (nbr) score; +Estimated worst slack/total negative slack: -4.574ns/-404.669ns; real time: 8 secs +Level 4, iteration 19 +1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 20 +1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 21 +1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 22 +1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 23 +1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.277ns; real time: 8 secs +Level 4, iteration 24 +1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.277ns; real time: 8 secs +Level 4, iteration 25 +0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 8 secs + +Start NBR section for performance tuning (iteration 1) at 05:03:39 08/15/23 +Level 4, iteration 1 +1(0.00%) conflict; 0(0.00%) untouched conn; 405829 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-405.830ns; real time: 8 secs +Level 4, iteration 2 +0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 8 secs + +Start NBR section for re-routing at 05:03:39 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 8 secs + +Start NBR section for post-routing at 05:03:39 08/15/23 + +End NBR router with 0 unrouted connection + +NBR Summary +----------- + Number of unrouted connections : 0 (0.00%) + Number of connections with timing violations : 254 (37.69%) + Estimated worst slack : -4.650ns + Timing score : 391939 +----------- +Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. + + + +WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. + Signal=nCCAS_c loads=6 clock_loads=4 + +Total CPU time 7 secs +Total REAL time: 8 secs +Completely routed. +End of route. 674 routed (100.00%); 0 unrouted. + +Hold time timing score: 0, hold timing errors: 0 + +Timing score: 391939 + +Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd. + + +All signals are completely routed. + + +PAR_SUMMARY::Run status = Completed +PAR_SUMMARY::Number of unrouted conns = 0 +PAR_SUMMARY::Worst slack> = -4.650 +PAR_SUMMARY::Timing score> = 391.939 +PAR_SUMMARY::Worst slack> = 0.304 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Number of errors = 0 + +Total CPU time to completion: 8 secs +Total REAL time to completion: 8 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.prf b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.prf new file mode 100644 index 0000000..0fcb3d2 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.prf @@ -0,0 +1,80 @@ +SCHEMATIC START ; +# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:03:27 2023 + +SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ; +LOCATE COMP "RD[7]" SITE "43" ; +LOCATE COMP "RD[6]" SITE "42" ; +LOCATE COMP "RD[5]" SITE "41" ; +LOCATE COMP "RD[4]" SITE "40" ; +LOCATE COMP "RD[3]" SITE "39" ; +LOCATE COMP "RD[2]" SITE "38" ; +LOCATE COMP "RD[1]" SITE "37" ; +LOCATE COMP "RD[0]" SITE "36" ; +LOCATE COMP "Dout[7]" SITE "82" ; +LOCATE COMP "Dout[6]" SITE "78" ; +LOCATE COMP "Dout[5]" SITE "84" ; +LOCATE COMP "Dout[4]" SITE "83" ; +LOCATE COMP "Dout[3]" SITE "85" ; +LOCATE COMP "Dout[2]" SITE "87" ; +LOCATE COMP "Dout[1]" SITE "86" ; +LOCATE COMP "Dout[0]" SITE "76" ; +LOCATE COMP "LED" SITE "34" ; +LOCATE COMP "RBA[1]" SITE "60" ; +LOCATE COMP "RBA[0]" SITE "58" ; +LOCATE COMP "RA[11]" SITE "59" ; +LOCATE COMP "RA[10]" SITE "64" ; +LOCATE COMP "RA[9]" SITE "63" ; +LOCATE COMP "RA[8]" SITE "65" ; +LOCATE COMP "RA[7]" SITE "75" ; +LOCATE COMP "RA[6]" SITE "68" ; +LOCATE COMP "RA[5]" SITE "70" ; +LOCATE COMP "RA[4]" SITE "74" ; +LOCATE COMP "RA[3]" SITE "71" ; +LOCATE COMP "RA[2]" SITE "69" ; +LOCATE COMP "RA[1]" SITE "67" ; +LOCATE COMP "RA[0]" SITE "66" ; +LOCATE COMP "nRCS" SITE "57" ; +LOCATE COMP "RCKE" SITE "53" ; +LOCATE COMP "nRWE" SITE "49" ; +LOCATE COMP "nRRAS" SITE "54" ; +LOCATE COMP "nRCAS" SITE "52" ; +LOCATE COMP "RDQMH" SITE "51" ; +LOCATE COMP "RDQML" SITE "48" ; +LOCATE COMP "UFMCLK" SITE "29" ; +LOCATE COMP "UFMSDI" SITE "30" ; +LOCATE COMP "PHI2" SITE "8" ; +LOCATE COMP "MAin[9]" SITE "32" ; +LOCATE COMP "MAin[8]" SITE "25" ; +LOCATE COMP "MAin[7]" SITE "18" ; +LOCATE COMP "MAin[6]" SITE "24" ; +LOCATE COMP "MAin[5]" SITE "19" ; +LOCATE COMP "MAin[4]" SITE "20" ; +LOCATE COMP "MAin[3]" SITE "21" ; +LOCATE COMP "MAin[2]" SITE "13" ; +LOCATE COMP "MAin[1]" SITE "12" ; +LOCATE COMP "MAin[0]" SITE "14" ; +LOCATE COMP "CROW[1]" SITE "16" ; +LOCATE COMP "CROW[0]" SITE "10" ; +LOCATE COMP "Din[7]" SITE "1" ; +LOCATE COMP "Din[6]" SITE "2" ; +LOCATE COMP "Din[5]" SITE "98" ; +LOCATE COMP "Din[4]" SITE "99" ; +LOCATE COMP "Din[3]" SITE "97" ; +LOCATE COMP "Din[2]" SITE "88" ; +LOCATE COMP "Din[1]" SITE "96" ; +LOCATE COMP "Din[0]" SITE "3" ; +LOCATE COMP "nCCAS" SITE "9" ; +LOCATE COMP "nCRAS" SITE "17" ; +LOCATE COMP "nFWE" SITE "28" ; +LOCATE COMP "RCLK" SITE "62" ; +LOCATE COMP "UFMSDO" SITE "27" ; +SCHEMATIC END ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +COMMERCIAL ; + +// No timing preferences found. TRCE invokes auto-generation of timing preferences +// Section Autogen +FREQUENCY NET "RCLK_c" 299.401 MHz ; +FREQUENCY NET "PHI2_c" 99.079 MHz ; +// End Section Autogen diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pt b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pt new file mode 100644 index 0000000..e5e32de --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pt @@ -0,0 +1,10 @@ +-v +10 + + + + +-gt +-sethld +-sp 4 +-sphld m diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.t2b b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.t2b new file mode 100644 index 0000000..f5d2846 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.t2b @@ -0,0 +1,5 @@ + + +-g RamCfg:Reset + +-path "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC" diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.tw1 b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.tw1 new file mode 100644 index 0000000..278d419 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.tw1 @@ -0,0 +1,349 @@ + +Loading design for application trce from file ram2gs_lcmxo2_1200hc_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 4 +Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:28 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_1200HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.prf +Design file: ram2gs_lcmxo2_1200hc_impl1_map.ncd +Preference file: ram2gs_lcmxo2_1200hc_impl1.prf +Device,speed: LCMXO2-1200HC,4 +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +Report Type: based on TRACE automatically generated preferences +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ; + 459 items scored, 245 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path exceeds requirements by 3.815ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i13 (from RCLK_c +) + Destination: FF Data in n8MEGEN_418 (to RCLK_c +) + + Delay: 6.873ns (28.2% logic, 71.8% route), 4 logic levels. + + Constraint Details: + + 6.873ns physical path delay SLICE_0 to SLICE_57 exceeds + 3.340ns delay constraint less + 0.282ns CE_SET requirement (totaling 3.058ns) by 3.815ns + + Physical Path Details: + + Data path SLICE_0 to SLICE_57: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 SLICE_0.CLK to SLICE_0.Q0 SLICE_0 (from RCLK_c) +ROUTE 3 e 1.234 SLICE_0.Q0 to SLICE_85.B0 FS_13 +CTOF_DEL --- 0.495 SLICE_85.B0 to SLICE_85.F0 SLICE_85 +ROUTE 5 e 1.234 SLICE_85.F0 to SLICE_57.A1 n10 +CTOF_DEL --- 0.495 SLICE_57.A1 to SLICE_57.F1 SLICE_57 +ROUTE 2 e 1.234 SLICE_57.F1 to SLICE_84.A0 n2367 +CTOF_DEL --- 0.495 SLICE_84.A0 to SLICE_84.F0 SLICE_84 +ROUTE 1 e 1.234 SLICE_84.F0 to SLICE_57.CE RCLK_c_enable_15 (to RCLK_c) + -------- + 6.873 (28.2% logic, 71.8% route), 4 logic levels. + +Warning: 139.762MHz is the maximum frequency for this preference. + + +================================================================================ +Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ; + 113 items scored, 104 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path exceeds requirements by 4.837ns (weighted slack = -9.674ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 9.577ns (30.6% logic, 69.4% route), 6 logic levels. + + Constraint Details: + + 9.577ns physical path delay SLICE_101 to SLICE_19 exceeds + 5.047ns delay constraint less + 0.307ns CE_SET requirement (totaling 4.740ns) by 4.837ns + + Physical Path Details: + + Data path SLICE_101 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 SLICE_101.CLK to SLICE_101.Q1 SLICE_101 (from PHI2_c) +ROUTE 1 e 1.234 SLICE_101.Q1 to SLICE_100.C1 Bank_7 +CTOF_DEL --- 0.495 SLICE_100.C1 to SLICE_100.F1 SLICE_100 +ROUTE 1 e 1.234 SLICE_100.F1 to SLICE_74.B1 n2277 +CTOF_DEL --- 0.495 SLICE_74.B1 to SLICE_74.F1 SLICE_74 +ROUTE 8 e 1.234 SLICE_74.F1 to SLICE_91.B1 n26 +CTOF_DEL --- 0.495 SLICE_91.B1 to SLICE_91.F1 SLICE_91 +ROUTE 1 e 1.234 SLICE_91.F1 to SLICE_88.D0 n2362 +CTOF_DEL --- 0.495 SLICE_88.D0 to SLICE_88.F0 SLICE_88 +ROUTE 3 e 0.480 SLICE_88.F0 to SLICE_88.C1 C1Submitted_N_237 +CTOF_DEL --- 0.495 SLICE_88.C1 to SLICE_88.F1 SLICE_88 +ROUTE 1 e 1.234 SLICE_88.F1 to SLICE_19.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 9.577 (30.6% logic, 69.4% route), 6 logic levels. + +Warning: 50.592MHz is the maximum frequency for this preference. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY NET "RCLK_c" 299.401000 MHz ; | 299.401 MHz| 139.762 MHz| 4 * + | | | +FREQUENCY NET "PHI2_c" 99.079000 MHz ; | 99.079 MHz| 50.592 MHz| 6 * + | | | +---------------------------------------------------------------------------- + + +2 preferences(marked by "*" above) not met. + +---------------------------------------------------------------------------- +Critical Nets | Loads| Errors| % of total +---------------------------------------------------------------------------- +n26 | 8| 78| 22.35% + | | | +---------------------------------------------------------------------------- + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 + Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Setup): +--------------- + +Timing errors: 349 Score: 848079 +Cumulative negative slack: 584487 + +Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:28 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_1200HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.prf +Design file: ram2gs_lcmxo2_1200hc_impl1_map.ncd +Preference file: ram2gs_lcmxo2_1200hc_impl1.prf +Device,speed: LCMXO2-1200HC,M +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ; + 459 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.351ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i4 (from RCLK_c +) + Destination: FF Data in IS_FSM__i5 (to RCLK_c +) + + Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels. + + Constraint Details: + + 0.332ns physical path delay SLICE_106 to SLICE_106 meets + -0.019ns M_HLD and + 0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns + + Physical Path Details: + + Data path SLICE_106 to SLICE_106: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 SLICE_106.CLK to SLICE_106.Q0 SLICE_106 (from RCLK_c) +ROUTE 1 e 0.199 SLICE_106.Q0 to SLICE_106.M1 n736 (to RCLK_c) + -------- + 0.332 (40.1% logic, 59.9% route), 1 logic levels. + + +================================================================================ +Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ; + 113 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.447ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted_406 (from PHI2_c -) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels. + + Constraint Details: + + 0.434ns physical path delay SLICE_15 to SLICE_15 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns + + Physical Path Details: + + Data path SLICE_15 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 SLICE_15.CLK to SLICE_15.Q0 SLICE_15 (from PHI2_c) +ROUTE 2 e 0.199 SLICE_15.Q0 to SLICE_15.C0 C1Submitted +CTOF_DEL --- 0.101 SLICE_15.C0 to SLICE_15.F0 SLICE_15 +ROUTE 1 e 0.001 SLICE_15.F0 to SLICE_15.DI0 n1398 (to PHI2_c) + -------- + 0.434 (53.9% logic, 46.1% route), 2 logic levels. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference(MIN Delays) | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY NET "RCLK_c" 299.401000 MHz ; | 0.000 ns| 0.351 ns| 1 + | | | +FREQUENCY NET "PHI2_c" 99.079000 MHz ; | 0.000 ns| 0.447 ns| 2 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 + Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 349 (setup), 0 (hold) +Score: 848079 (setup), 0 (hold) +Cumulative negative slack: 584487 (584487+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.twr b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.twr new file mode 100644 index 0000000..7c6f2bd --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.twr @@ -0,0 +1,2163 @@ + +Loading design for application trce from file ram2gs_lcmxo2_1200hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 4 +Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:40 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_1200HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf +Design file: ram2gs_lcmxo2_1200hc_impl1.ncd +Preference file: ram2gs_lcmxo2_1200hc_impl1.prf +Device,speed: LCMXO2-1200HC,4 +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +Report Type: based on TRACE automatically generated preferences +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ; + 459 items scored, 247 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path exceeds requirements by 2.400ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i12 (from RCLK_c +) + Destination: FF Data in UFMCLK_416 (to RCLK_c +) + + Delay: 5.574ns (43.6% logic, 56.4% route), 5 logic levels. + + Constraint Details: + + 5.574ns physical path delay SLICE_1 to SLICE_44 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.400ns + + Physical Path Details: + + Data path SLICE_1 to SLICE_44: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R7C15C.CLK to R7C15C.Q1 SLICE_1 (from RCLK_c) +ROUTE 5 1.440 R7C15C.Q1 to R8C15A.B0 FS_12 +CTOF_DEL --- 0.495 R8C15A.B0 to R8C15A.F0 SLICE_105 +ROUTE 1 0.626 R8C15A.F0 to R8C15D.D1 n12 +CTOF_DEL --- 0.495 R8C15D.D1 to R8C15D.F1 SLICE_82 +ROUTE 3 0.640 R8C15D.F1 to R8C16B.D1 n13_adj_6 +CTOF_DEL --- 0.495 R8C16B.D1 to R8C16B.F1 SLICE_44 +ROUTE 1 0.436 R8C16B.F1 to R8C16B.C0 n1893 +CTOF_DEL --- 0.495 R8C16B.C0 to R8C16B.F0 SLICE_44 +ROUTE 1 0.000 R8C16B.F0 to R8C16B.DI0 UFMCLK_N_224 (to RCLK_c) + -------- + 5.574 (43.6% logic, 56.4% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R7C15C.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_44: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R8C16B.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.383ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i12 (from RCLK_c +) + Destination: FF Data in InitReady_394 (to RCLK_c +) + + Delay: 5.441ns (35.6% logic, 64.4% route), 4 logic levels. + + Constraint Details: + + 5.441ns physical path delay SLICE_1 to SLICE_26 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.282ns CE_SET requirement (totaling 3.058ns) by 2.383ns + + Physical Path Details: + + Data path SLICE_1 to SLICE_26: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R7C15C.CLK to R7C15C.Q1 SLICE_1 (from RCLK_c) +ROUTE 5 1.440 R7C15C.Q1 to R8C15A.B0 FS_12 +CTOF_DEL --- 0.495 R8C15A.B0 to R8C15A.F0 SLICE_105 +ROUTE 1 0.626 R8C15A.F0 to R8C15D.D1 n12 +CTOF_DEL --- 0.495 R8C15D.D1 to R8C15D.F1 SLICE_82 +ROUTE 3 0.453 R8C15D.F1 to R8C15D.C0 n13_adj_6 +CTOF_DEL --- 0.495 R8C15D.C0 to R8C15D.F0 SLICE_82 +ROUTE 1 0.985 R8C15D.F0 to R8C13D.CE RCLK_c_enable_28 (to RCLK_c) + -------- + 5.441 (35.6% logic, 64.4% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R7C15C.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_26: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R8C13D.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.217ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i16 (from RCLK_c +) + Destination: FF Data in nUFMCS_415 (to RCLK_c +) + + Delay: 5.391ns (45.1% logic, 54.9% route), 5 logic levels. + + Constraint Details: + + 5.391ns physical path delay SLICE_9 to SLICE_70 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.217ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_70: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R7C16A.CLK to R7C16A.Q1 SLICE_9 (from RCLK_c) +ROUTE 3 1.017 R7C16A.Q1 to R7C16D.B0 FS_16 +CTOF_DEL --- 0.495 R7C16D.B0 to R7C16D.F0 SLICE_85 +ROUTE 5 0.340 R7C16D.F0 to R7C17A.D1 n10 +CTOF_DEL --- 0.495 R7C17A.D1 to R7C17A.F1 SLICE_76 +ROUTE 2 0.635 R7C17A.F1 to R7C17D.D1 n2368 +CTOF_DEL --- 0.495 R7C17D.D1 to R7C17D.F1 SLICE_70 +ROUTE 1 0.967 R7C17D.F1 to R7C17D.A0 n64 +CTOF_DEL --- 0.495 R7C17D.A0 to R7C17D.F0 SLICE_70 +ROUTE 1 0.000 R7C17D.F0 to R7C17D.DI0 nUFMCS_N_199 (to RCLK_c) + -------- + 5.391 (45.1% logic, 54.9% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R7C16A.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_70: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R7C17D.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.180ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i15 (from RCLK_c +) + Destination: FF Data in nUFMCS_415 (to RCLK_c +) + + Delay: 5.354ns (45.4% logic, 54.6% route), 5 logic levels. + + Constraint Details: + + 5.354ns physical path delay SLICE_9 to SLICE_70 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.180ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_70: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R7C16A.CLK to R7C16A.Q0 SLICE_9 (from RCLK_c) +ROUTE 3 0.980 R7C16A.Q0 to R7C16D.A0 FS_15 +CTOF_DEL --- 0.495 R7C16D.A0 to R7C16D.F0 SLICE_85 +ROUTE 5 0.340 R7C16D.F0 to R7C17A.D1 n10 +CTOF_DEL --- 0.495 R7C17A.D1 to R7C17A.F1 SLICE_76 +ROUTE 2 0.635 R7C17A.F1 to R7C17D.D1 n2368 +CTOF_DEL --- 0.495 R7C17D.D1 to R7C17D.F1 SLICE_70 +ROUTE 1 0.967 R7C17D.F1 to R7C17D.A0 n64 +CTOF_DEL --- 0.495 R7C17D.A0 to R7C17D.F0 SLICE_70 +ROUTE 1 0.000 R7C17D.F0 to R7C17D.DI0 nUFMCS_N_199 (to RCLK_c) + -------- + 5.354 (45.4% logic, 54.6% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R7C16A.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_70: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R7C17D.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.166ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i16 (from RCLK_c +) + Destination: FF Data in UFMCLK_416 (to RCLK_c +) + + Delay: 5.340ns (45.5% logic, 54.5% route), 5 logic levels. + + Constraint Details: + + 5.340ns physical path delay SLICE_9 to SLICE_44 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.166ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_44: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R7C16A.CLK to R7C16A.Q1 SLICE_9 (from RCLK_c) +ROUTE 3 1.206 R7C16A.Q1 to R8C15A.C0 FS_16 +CTOF_DEL --- 0.495 R8C15A.C0 to R8C15A.F0 SLICE_105 +ROUTE 1 0.626 R8C15A.F0 to R8C15D.D1 n12 +CTOF_DEL --- 0.495 R8C15D.D1 to R8C15D.F1 SLICE_82 +ROUTE 3 0.640 R8C15D.F1 to R8C16B.D1 n13_adj_6 +CTOF_DEL --- 0.495 R8C16B.D1 to R8C16B.F1 SLICE_44 +ROUTE 1 0.436 R8C16B.F1 to R8C16B.C0 n1893 +CTOF_DEL --- 0.495 R8C16B.C0 to R8C16B.F0 SLICE_44 +ROUTE 1 0.000 R8C16B.F0 to R8C16B.DI0 UFMCLK_N_224 (to RCLK_c) + -------- + 5.340 (45.5% logic, 54.5% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R7C16A.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_44: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R8C16B.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.158ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i16 (from RCLK_c +) + Destination: FF Data in UFMCLK_416 (to RCLK_c +) + + Delay: 5.332ns (45.6% logic, 54.4% route), 5 logic levels. + + Constraint Details: + + 5.332ns physical path delay SLICE_9 to SLICE_44 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.158ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_44: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R7C16A.CLK to R7C16A.Q1 SLICE_9 (from RCLK_c) +ROUTE 3 1.017 R7C16A.Q1 to R7C16D.B0 FS_16 +CTOF_DEL --- 0.495 R7C16D.B0 to R7C16D.F0 SLICE_85 +ROUTE 5 0.461 R7C16D.F0 to R7C16D.C1 n10 +CTOF_DEL --- 0.495 R7C16D.C1 to R7C16D.F1 SLICE_85 +ROUTE 1 0.986 R7C16D.F1 to R8C16B.A1 n2267 +CTOF_DEL --- 0.495 R8C16B.A1 to R8C16B.F1 SLICE_44 +ROUTE 1 0.436 R8C16B.F1 to R8C16B.C0 n1893 +CTOF_DEL --- 0.495 R8C16B.C0 to R8C16B.F0 SLICE_44 +ROUTE 1 0.000 R8C16B.F0 to R8C16B.DI0 UFMCLK_N_224 (to RCLK_c) + -------- + 5.332 (45.6% logic, 54.4% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R7C16A.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_44: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R8C16B.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.149ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i16 (from RCLK_c +) + Destination: FF Data in InitReady_394 (to RCLK_c +) + + Delay: 5.207ns (37.2% logic, 62.8% route), 4 logic levels. + + Constraint Details: + + 5.207ns physical path delay SLICE_9 to SLICE_26 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.282ns CE_SET requirement (totaling 3.058ns) by 2.149ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_26: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R7C16A.CLK to R7C16A.Q1 SLICE_9 (from RCLK_c) +ROUTE 3 1.206 R7C16A.Q1 to R8C15A.C0 FS_16 +CTOF_DEL --- 0.495 R8C15A.C0 to R8C15A.F0 SLICE_105 +ROUTE 1 0.626 R8C15A.F0 to R8C15D.D1 n12 +CTOF_DEL --- 0.495 R8C15D.D1 to R8C15D.F1 SLICE_82 +ROUTE 3 0.453 R8C15D.F1 to R8C15D.C0 n13_adj_6 +CTOF_DEL --- 0.495 R8C15D.C0 to R8C15D.F0 SLICE_82 +ROUTE 1 0.985 R8C15D.F0 to R8C13D.CE RCLK_c_enable_28 (to RCLK_c) + -------- + 5.207 (37.2% logic, 62.8% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R7C16A.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_26: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R8C13D.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.131ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i7 (from RCLK_c +) + Destination: FF Data in n8MEGEN_418 (to RCLK_c +) + + Delay: 5.189ns (37.3% logic, 62.7% route), 4 logic levels. + + Constraint Details: + + 5.189ns physical path delay SLICE_2 to SLICE_57 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.282ns CE_SET requirement (totaling 3.058ns) by 2.131ns + + Physical Path Details: + + Data path SLICE_2 to SLICE_57: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R7C15A.CLK to R7C15A.Q0 SLICE_2 (from RCLK_c) +ROUTE 3 1.086 R7C15A.Q0 to R8C14D.D0 FS_7 +CTOF_DEL --- 0.495 R8C14D.D0 to R8C14D.F0 SLICE_95 +ROUTE 1 0.747 R8C14D.F0 to R8C14A.C0 n15 +CTOF_DEL --- 0.495 R8C14A.C0 to R8C14A.F0 SLICE_86 +ROUTE 1 0.766 R8C14A.F0 to R8C16C.C0 n4_adj_7 +CTOF_DEL --- 0.495 R8C16C.C0 to R8C16C.F0 SLICE_84 +ROUTE 1 0.653 R8C16C.F0 to R8C16A.CE RCLK_c_enable_15 (to RCLK_c) + -------- + 5.189 (37.3% logic, 62.7% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_2: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R7C15A.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_57: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R8C16A.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.121ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i15 (from RCLK_c +) + Destination: FF Data in UFMCLK_416 (to RCLK_c +) + + Delay: 5.295ns (45.9% logic, 54.1% route), 5 logic levels. + + Constraint Details: + + 5.295ns physical path delay SLICE_9 to SLICE_44 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.121ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_44: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R7C16A.CLK to R7C16A.Q0 SLICE_9 (from RCLK_c) +ROUTE 3 0.980 R7C16A.Q0 to R7C16D.A0 FS_15 +CTOF_DEL --- 0.495 R7C16D.A0 to R7C16D.F0 SLICE_85 +ROUTE 5 0.461 R7C16D.F0 to R7C16D.C1 n10 +CTOF_DEL --- 0.495 R7C16D.C1 to R7C16D.F1 SLICE_85 +ROUTE 1 0.986 R7C16D.F1 to R8C16B.A1 n2267 +CTOF_DEL --- 0.495 R8C16B.A1 to R8C16B.F1 SLICE_44 +ROUTE 1 0.436 R8C16B.F1 to R8C16B.C0 n1893 +CTOF_DEL --- 0.495 R8C16B.C0 to R8C16B.F0 SLICE_44 +ROUTE 1 0.000 R8C16B.F0 to R8C16B.DI0 UFMCLK_N_224 (to RCLK_c) + -------- + 5.295 (45.9% logic, 54.1% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R7C16A.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_44: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R8C16B.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.087ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i12 (from RCLK_c +) + Destination: FF Data in UFMSDI_417 (to RCLK_c +) + + Delay: 5.261ns (46.2% logic, 53.8% route), 5 logic levels. + + Constraint Details: + + 5.261ns physical path delay SLICE_1 to SLICE_45 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.087ns + + Physical Path Details: + + Data path SLICE_1 to SLICE_45: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R7C15C.CLK to R7C15C.Q1 SLICE_1 (from RCLK_c) +ROUTE 5 0.786 R7C15C.Q1 to R8C15C.C1 FS_12 +CTOF_DEL --- 0.495 R8C15C.C1 to R8C15C.F1 SLICE_80 +ROUTE 3 0.640 R8C15C.F1 to R8C14D.D1 n2375 +CTOF_DEL --- 0.495 R8C14D.D1 to R8C14D.F1 SLICE_95 +ROUTE 1 0.967 R8C14D.F1 to R8C14C.A1 n7 +CTOF_DEL --- 0.495 R8C14C.A1 to R8C14C.F1 SLICE_45 +ROUTE 1 0.436 R8C14C.F1 to R8C14C.C0 n2174 +CTOF_DEL --- 0.495 R8C14C.C0 to R8C14C.F0 SLICE_45 +ROUTE 1 0.000 R8C14C.F0 to R8C14C.DI0 UFMSDI_N_231 (to RCLK_c) + -------- + 5.261 (46.2% logic, 53.8% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R7C15C.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_45: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R8C14C.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + +Warning: 174.216MHz is the maximum frequency for this preference. + + +================================================================================ +Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ; + 113 items scored, 88 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path exceeds requirements by 2.325ns (weighted slack = -4.650ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i6 (from PHI2_c +) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 7.065ns (41.4% logic, 58.6% route), 6 logic levels. + + Constraint Details: + + 7.065ns physical path delay SLICE_101 to SLICE_19 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.307ns CE_SET requirement (totaling 4.740ns) by 2.325ns + + Physical Path Details: + + Data path SLICE_101 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R9C16C.CLK to R9C16C.Q0 SLICE_101 (from PHI2_c) +ROUTE 1 0.986 R9C16C.Q0 to R9C14A.A0 Bank_6 +CTOF_DEL --- 0.495 R9C14A.A0 to R9C14A.F0 SLICE_68 +ROUTE 1 0.766 R9C14A.F0 to R9C15B.C1 n2287 +CTOF_DEL --- 0.495 R9C15B.C1 to R9C15B.F1 SLICE_74 +ROUTE 8 0.662 R9C15B.F1 to R9C14D.D1 n26 +CTOF_DEL --- 0.495 R9C14D.D1 to R9C14D.F1 SLICE_91 +ROUTE 1 0.626 R9C14D.F1 to R9C14C.D0 n2362 +CTOF_DEL --- 0.495 R9C14C.D0 to R9C14C.F0 SLICE_88 +ROUTE 3 0.445 R9C14C.F0 to R9C14C.C1 C1Submitted_N_237 +CTOF_DEL --- 0.495 R9C14C.C1 to R9C14C.F1 SLICE_88 +ROUTE 1 0.653 R9C14C.F1 to R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 7.065 (41.4% logic, 58.6% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_101: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R9C16C.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R9C14B.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.287ns (weighted slack = -4.574ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i1 (from PHI2_c +) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 7.027ns (41.7% logic, 58.3% route), 6 logic levels. + + Constraint Details: + + 7.027ns physical path delay SLICE_93 to SLICE_19 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.307ns CE_SET requirement (totaling 4.740ns) by 2.287ns + + Physical Path Details: + + Data path SLICE_93 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R9C16A.CLK to R9C16A.Q1 SLICE_93 (from PHI2_c) +ROUTE 1 0.744 R9C16A.Q1 to R9C15C.C1 Bank_1 +CTOF_DEL --- 0.495 R9C15C.C1 to R9C15C.F1 SLICE_99 +ROUTE 2 0.635 R9C15C.F1 to R9C15D.D1 n22 +CTOF_DEL --- 0.495 R9C15D.D1 to R9C15D.F1 SLICE_79 +ROUTE 7 0.997 R9C15D.F1 to R9C14D.A1 n2369 +CTOF_DEL --- 0.495 R9C14D.A1 to R9C14D.F1 SLICE_91 +ROUTE 1 0.626 R9C14D.F1 to R9C14C.D0 n2362 +CTOF_DEL --- 0.495 R9C14C.D0 to R9C14C.F0 SLICE_88 +ROUTE 3 0.445 R9C14C.F0 to R9C14C.C1 C1Submitted_N_237 +CTOF_DEL --- 0.495 R9C14C.C1 to R9C14C.F1 SLICE_88 +ROUTE 1 0.653 R9C14C.F1 to R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 7.027 (41.7% logic, 58.3% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R9C16A.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R9C14B.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.166ns (weighted slack = -4.332ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i4 (from PHI2_c +) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 6.906ns (42.4% logic, 57.6% route), 6 logic levels. + + Constraint Details: + + 6.906ns physical path delay SLICE_102 to SLICE_19 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.307ns CE_SET requirement (totaling 4.740ns) by 2.166ns + + Physical Path Details: + + Data path SLICE_102 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R8C15B.CLK to R8C15B.Q0 SLICE_102 (from PHI2_c) +ROUTE 1 0.623 R8C15B.Q0 to R9C15C.D1 Bank_4 +CTOF_DEL --- 0.495 R9C15C.D1 to R9C15C.F1 SLICE_99 +ROUTE 2 0.635 R9C15C.F1 to R9C15D.D1 n22 +CTOF_DEL --- 0.495 R9C15D.D1 to R9C15D.F1 SLICE_79 +ROUTE 7 0.997 R9C15D.F1 to R9C14D.A1 n2369 +CTOF_DEL --- 0.495 R9C14D.A1 to R9C14D.F1 SLICE_91 +ROUTE 1 0.626 R9C14D.F1 to R9C14C.D0 n2362 +CTOF_DEL --- 0.495 R9C14C.D0 to R9C14C.F0 SLICE_88 +ROUTE 3 0.445 R9C14C.F0 to R9C14C.C1 C1Submitted_N_237 +CTOF_DEL --- 0.495 R9C14C.C1 to R9C14C.F1 SLICE_88 +ROUTE 1 0.653 R9C14C.F1 to R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 6.906 (42.4% logic, 57.6% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_102: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R8C15B.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R9C14B.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 1.984ns (weighted slack = -3.968ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i3 (from PHI2_c +) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 6.724ns (43.5% logic, 56.5% route), 6 logic levels. + + Constraint Details: + + 6.724ns physical path delay SLICE_103 to SLICE_19 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.307ns CE_SET requirement (totaling 4.740ns) by 1.984ns + + Physical Path Details: + + Data path SLICE_103 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R9C16D.CLK to R9C16D.Q1 SLICE_103 (from PHI2_c) +ROUTE 1 0.645 R9C16D.Q1 to R9C14A.D0 Bank_3 +CTOF_DEL --- 0.495 R9C14A.D0 to R9C14A.F0 SLICE_68 +ROUTE 1 0.766 R9C14A.F0 to R9C15B.C1 n2287 +CTOF_DEL --- 0.495 R9C15B.C1 to R9C15B.F1 SLICE_74 +ROUTE 8 0.662 R9C15B.F1 to R9C14D.D1 n26 +CTOF_DEL --- 0.495 R9C14D.D1 to R9C14D.F1 SLICE_91 +ROUTE 1 0.626 R9C14D.F1 to R9C14C.D0 n2362 +CTOF_DEL --- 0.495 R9C14C.D0 to R9C14C.F0 SLICE_88 +ROUTE 3 0.445 R9C14C.F0 to R9C14C.C1 C1Submitted_N_237 +CTOF_DEL --- 0.495 R9C14C.C1 to R9C14C.F1 SLICE_88 +ROUTE 1 0.653 R9C14C.F1 to R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 6.724 (43.5% logic, 56.5% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_103: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R9C16D.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R9C14B.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 1.874ns (weighted slack = -3.748ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 6.614ns (44.3% logic, 55.7% route), 6 logic levels. + + Constraint Details: + + 6.614ns physical path delay SLICE_101 to SLICE_19 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.307ns CE_SET requirement (totaling 4.740ns) by 1.874ns + + Physical Path Details: + + Data path SLICE_101 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R9C16C.CLK to R9C16C.Q1 SLICE_101 (from PHI2_c) +ROUTE 1 0.986 R9C16C.Q1 to R9C15A.A1 Bank_7 +CTOF_DEL --- 0.495 R9C15A.A1 to R9C15A.F1 SLICE_100 +ROUTE 1 0.315 R9C15A.F1 to R9C15B.D1 n2277 +CTOF_DEL --- 0.495 R9C15B.D1 to R9C15B.F1 SLICE_74 +ROUTE 8 0.662 R9C15B.F1 to R9C14D.D1 n26 +CTOF_DEL --- 0.495 R9C14D.D1 to R9C14D.F1 SLICE_91 +ROUTE 1 0.626 R9C14D.F1 to R9C14C.D0 n2362 +CTOF_DEL --- 0.495 R9C14C.D0 to R9C14C.F0 SLICE_88 +ROUTE 3 0.445 R9C14C.F0 to R9C14C.C1 C1Submitted_N_237 +CTOF_DEL --- 0.495 R9C14C.C1 to R9C14C.F1 SLICE_88 +ROUTE 1 0.653 R9C14C.F1 to R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 6.614 (44.3% logic, 55.7% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_101: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R9C16C.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R9C14B.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 1.803ns (weighted slack = -3.606ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i6 (from PHI2_c +) + Destination: FF Data in ADSubmitted_407 (to PHI2_c -) + + Delay: 6.565ns (37.0% logic, 63.0% route), 5 logic levels. + + Constraint Details: + + 6.565ns physical path delay SLICE_101 to SLICE_10 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.285ns LSR_SET requirement (totaling 4.762ns) by 1.803ns + + Physical Path Details: + + Data path SLICE_101 to SLICE_10: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R9C16C.CLK to R9C16C.Q0 SLICE_101 (from PHI2_c) +ROUTE 1 0.986 R9C16C.Q0 to R9C14A.A0 Bank_6 +CTOF_DEL --- 0.495 R9C14A.A0 to R9C14A.F0 SLICE_68 +ROUTE 1 0.766 R9C14A.F0 to R9C15B.C1 n2287 +CTOF_DEL --- 0.495 R9C15B.C1 to R9C15B.F1 SLICE_74 +ROUTE 8 0.662 R9C15B.F1 to R9C14D.D1 n26 +CTOF_DEL --- 0.495 R9C14D.D1 to R9C14D.F1 SLICE_91 +ROUTE 1 0.626 R9C14D.F1 to R9C14C.D0 n2362 +CTOF_DEL --- 0.495 R9C14C.D0 to R9C14C.F0 SLICE_88 +ROUTE 3 1.093 R9C14C.F0 to R10C14B.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 6.565 (37.0% logic, 63.0% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_101: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R9C16C.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_10: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R10C14B.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 1.803ns (weighted slack = -3.606ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i6 (from PHI2_c +) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 6.565ns (37.0% logic, 63.0% route), 5 logic levels. + + Constraint Details: + + 6.565ns physical path delay SLICE_101 to SLICE_15 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.285ns LSR_SET requirement (totaling 4.762ns) by 1.803ns + + Physical Path Details: + + Data path SLICE_101 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R9C16C.CLK to R9C16C.Q0 SLICE_101 (from PHI2_c) +ROUTE 1 0.986 R9C16C.Q0 to R9C14A.A0 Bank_6 +CTOF_DEL --- 0.495 R9C14A.A0 to R9C14A.F0 SLICE_68 +ROUTE 1 0.766 R9C14A.F0 to R9C15B.C1 n2287 +CTOF_DEL --- 0.495 R9C15B.C1 to R9C15B.F1 SLICE_74 +ROUTE 8 0.662 R9C15B.F1 to R9C14D.D1 n26 +CTOF_DEL --- 0.495 R9C14D.D1 to R9C14D.F1 SLICE_91 +ROUTE 1 0.626 R9C14D.F1 to R9C14C.D0 n2362 +CTOF_DEL --- 0.495 R9C14C.D0 to R9C14C.F0 SLICE_88 +ROUTE 3 1.093 R9C14C.F0 to R10C14C.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 6.565 (37.0% logic, 63.0% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_101: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R9C16C.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R10C14C.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 1.765ns (weighted slack = -3.530ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i1 (from PHI2_c +) + Destination: FF Data in ADSubmitted_407 (to PHI2_c -) + + Delay: 6.527ns (37.3% logic, 62.7% route), 5 logic levels. + + Constraint Details: + + 6.527ns physical path delay SLICE_93 to SLICE_10 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.285ns LSR_SET requirement (totaling 4.762ns) by 1.765ns + + Physical Path Details: + + Data path SLICE_93 to SLICE_10: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R9C16A.CLK to R9C16A.Q1 SLICE_93 (from PHI2_c) +ROUTE 1 0.744 R9C16A.Q1 to R9C15C.C1 Bank_1 +CTOF_DEL --- 0.495 R9C15C.C1 to R9C15C.F1 SLICE_99 +ROUTE 2 0.635 R9C15C.F1 to R9C15D.D1 n22 +CTOF_DEL --- 0.495 R9C15D.D1 to R9C15D.F1 SLICE_79 +ROUTE 7 0.997 R9C15D.F1 to R9C14D.A1 n2369 +CTOF_DEL --- 0.495 R9C14D.A1 to R9C14D.F1 SLICE_91 +ROUTE 1 0.626 R9C14D.F1 to R9C14C.D0 n2362 +CTOF_DEL --- 0.495 R9C14C.D0 to R9C14C.F0 SLICE_88 +ROUTE 3 1.093 R9C14C.F0 to R10C14B.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 6.527 (37.3% logic, 62.7% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R9C16A.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_10: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R10C14B.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 1.765ns (weighted slack = -3.530ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i1 (from PHI2_c +) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 6.527ns (37.3% logic, 62.7% route), 5 logic levels. + + Constraint Details: + + 6.527ns physical path delay SLICE_93 to SLICE_15 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.285ns LSR_SET requirement (totaling 4.762ns) by 1.765ns + + Physical Path Details: + + Data path SLICE_93 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R9C16A.CLK to R9C16A.Q1 SLICE_93 (from PHI2_c) +ROUTE 1 0.744 R9C16A.Q1 to R9C15C.C1 Bank_1 +CTOF_DEL --- 0.495 R9C15C.C1 to R9C15C.F1 SLICE_99 +ROUTE 2 0.635 R9C15C.F1 to R9C15D.D1 n22 +CTOF_DEL --- 0.495 R9C15D.D1 to R9C15D.F1 SLICE_79 +ROUTE 7 0.997 R9C15D.F1 to R9C14D.A1 n2369 +CTOF_DEL --- 0.495 R9C14D.A1 to R9C14D.F1 SLICE_91 +ROUTE 1 0.626 R9C14D.F1 to R9C14C.D0 n2362 +CTOF_DEL --- 0.495 R9C14C.D0 to R9C14C.F0 SLICE_88 +ROUTE 3 1.093 R9C14C.F0 to R10C14C.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 6.527 (37.3% logic, 62.7% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R9C16A.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R10C14C.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 1.750ns (weighted slack = -3.500ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i6 (from PHI2_c +) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 6.490ns (37.5% logic, 62.5% route), 5 logic levels. + + Constraint Details: + + 6.490ns physical path delay SLICE_101 to SLICE_19 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.307ns CE_SET requirement (totaling 4.740ns) by 1.750ns + + Physical Path Details: + + Data path SLICE_101 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R9C16C.CLK to R9C16C.Q0 SLICE_101 (from PHI2_c) +ROUTE 1 0.986 R9C16C.Q0 to R9C14A.A0 Bank_6 +CTOF_DEL --- 0.495 R9C14A.A0 to R9C14A.F0 SLICE_68 +ROUTE 1 0.766 R9C14A.F0 to R9C15B.C1 n2287 +CTOF_DEL --- 0.495 R9C15B.C1 to R9C15B.F1 SLICE_74 +ROUTE 8 0.688 R9C15B.F1 to R10C15C.D0 n26 +CTOF_DEL --- 0.495 R10C15C.D0 to R10C15C.F0 SLICE_104 +ROUTE 2 0.965 R10C15C.F0 to R9C14C.D1 n2363 +CTOF_DEL --- 0.495 R9C14C.D1 to R9C14C.F1 SLICE_88 +ROUTE 1 0.653 R9C14C.F1 to R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 6.490 (37.5% logic, 62.5% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_101: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R9C16C.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R9C14B.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + +Warning: 67.833MHz is the maximum frequency for this preference. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY NET "RCLK_c" 299.401000 MHz ; | 299.401 MHz| 174.216 MHz| 5 * + | | | +FREQUENCY NET "PHI2_c" 99.079000 MHz ; | 99.079 MHz| 67.833 MHz| 6 * + | | | +---------------------------------------------------------------------------- + + +2 preferences(marked by "*" above) not met. + +---------------------------------------------------------------------------- +Critical Nets | Loads| Errors| % of total +---------------------------------------------------------------------------- +n26 | 8| 64| 19.10% + | | | +n1996 | 1| 49| 14.63% + | | | +n1997 | 1| 46| 13.73% + | | | +n1995 | 1| 45| 13.43% + | | | +n1998 | 1| 38| 11.34% + | | | +n1994 | 1| 37| 11.04% + | | | +---------------------------------------------------------------------------- + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 + Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Setup): +--------------- + +Timing errors: 335 Score: 391939 +Cumulative negative slack: 304509 + +Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:40 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_1200HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf +Design file: ram2gs_lcmxo2_1200hc_impl1.ncd +Preference file: ram2gs_lcmxo2_1200hc_impl1.prf +Device,speed: LCMXO2-1200HC,m +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ; + 459 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.304ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i4 (from RCLK_c +) + Destination: FF Data in IS_FSM__i5 (to RCLK_c +) + + Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. + + Constraint Details: + + 0.285ns physical path delay SLICE_106 to SLICE_106 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.304ns + + Physical Path Details: + + Data path SLICE_106 to SLICE_106: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R10C13B.CLK to R10C13B.Q0 SLICE_106 (from RCLK_c) +ROUTE 1 0.152 R10C13B.Q0 to R10C13B.M1 n736 (to RCLK_c) + -------- + 0.285 (46.7% logic, 53.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_106: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R10C13B.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_106: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R10C13B.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.304ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CASr_382 (from RCLK_c +) + Destination: FF Data in CASr2_383 (to RCLK_c +) + + Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. + + Constraint Details: + + 0.285ns physical path delay SLICE_16 to SLICE_16 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.304ns + + Physical Path Details: + + Data path SLICE_16 to SLICE_16: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R7C12B.CLK to R7C12B.Q0 SLICE_16 (from RCLK_c) +ROUTE 1 0.152 R7C12B.Q0 to R7C12B.M1 CASr (to RCLK_c) + -------- + 0.285 (46.7% logic, 53.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_16: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R7C12B.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_16: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R7C12B.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.304ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i8 (from RCLK_c +) + Destination: FF Data in IS_FSM__i9 (to RCLK_c +) + + Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. + + Constraint Details: + + 0.285ns physical path delay SLICE_75 to SLICE_75 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.304ns + + Physical Path Details: + + Data path SLICE_75 to SLICE_75: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R10C13D.CLK to R10C13D.Q0 SLICE_75 (from RCLK_c) +ROUTE 1 0.152 R10C13D.Q0 to R10C13D.M1 n732 (to RCLK_c) + -------- + 0.285 (46.7% logic, 53.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_75: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R10C13D.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_75: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R10C13D.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.304ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i12 (from RCLK_c +) + Destination: FF Data in IS_FSM__i13 (to RCLK_c +) + + Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. + + Constraint Details: + + 0.285ns physical path delay SLICE_78 to SLICE_78 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.304ns + + Physical Path Details: + + Data path SLICE_78 to SLICE_78: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R8C12B.CLK to R8C12B.Q0 SLICE_78 (from RCLK_c) +ROUTE 1 0.152 R8C12B.Q0 to R8C12B.M1 n728 (to RCLK_c) + -------- + 0.285 (46.7% logic, 53.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_78: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R8C12B.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_78: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R8C12B.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.304ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i14 (from RCLK_c +) + Destination: FF Data in IS_FSM__i15 (to RCLK_c +) + + Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. + + Constraint Details: + + 0.285ns physical path delay SLICE_81 to SLICE_81 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.304ns + + Physical Path Details: + + Data path SLICE_81 to SLICE_81: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R9C12A.CLK to R9C12A.Q0 SLICE_81 (from RCLK_c) +ROUTE 1 0.152 R9C12A.Q0 to R9C12A.M1 n726 (to RCLK_c) + -------- + 0.285 (46.7% logic, 53.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_81: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R9C12A.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_81: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R9C12A.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.304ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i2 (from RCLK_c +) + Destination: FF Data in IS_FSM__i3 (to RCLK_c +) + + Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. + + Constraint Details: + + 0.285ns physical path delay SLICE_84 to SLICE_84 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.304ns + + Physical Path Details: + + Data path SLICE_84 to SLICE_84: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R8C16C.CLK to R8C16C.Q0 SLICE_84 (from RCLK_c) +ROUTE 1 0.152 R8C16C.Q0 to R8C16C.M1 n738 (to RCLK_c) + -------- + 0.285 (46.7% logic, 53.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_84: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R8C16C.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_84: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R8C16C.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.304ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i6 (from RCLK_c +) + Destination: FF Data in IS_FSM__i7 (to RCLK_c +) + + Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. + + Constraint Details: + + 0.285ns physical path delay SLICE_97 to SLICE_97 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.304ns + + Physical Path Details: + + Data path SLICE_97 to SLICE_97: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R10C14A.CLK to R10C14A.Q0 SLICE_97 (from RCLK_c) +ROUTE 1 0.152 R10C14A.Q0 to R10C14A.M1 n734 (to RCLK_c) + -------- + 0.285 (46.7% logic, 53.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_97: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R10C14A.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_97: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R10C14A.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.306ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RASr_379 (from RCLK_c +) + Destination: FF Data in RASr2_380 (to RCLK_c +) + + Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. + + Constraint Details: + + 0.287ns physical path delay SLICE_30 to SLICE_30 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.306ns + + Physical Path Details: + + Data path SLICE_30 to SLICE_30: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R8C13B.CLK to R8C13B.Q0 SLICE_30 (from RCLK_c) +ROUTE 2 0.154 R8C13B.Q0 to R8C13B.M1 RASr (to RCLK_c) + -------- + 0.287 (46.3% logic, 53.7% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_30: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R8C13B.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_30: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R8C13B.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.306ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i1 (from RCLK_c +) + Destination: FF Data in IS_FSM__i2 (to RCLK_c +) + + Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. + + Constraint Details: + + 0.287ns physical path delay SLICE_98 to SLICE_84 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.306ns + + Physical Path Details: + + Data path SLICE_98 to SLICE_84: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R8C16D.CLK to R8C16D.Q1 SLICE_98 (from RCLK_c) +ROUTE 4 0.154 R8C16D.Q1 to R8C16C.M0 nRCAS_N_165 (to RCLK_c) + -------- + 0.287 (46.3% logic, 53.7% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_98: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R8C16D.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_84: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R8C16C.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.306ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i0 (from RCLK_c +) + Destination: FF Data in IS_FSM__i1 (to RCLK_c +) + + Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. + + Constraint Details: + + 0.287ns physical path delay SLICE_98 to SLICE_98 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.306ns + + Physical Path Details: + + Data path SLICE_98 to SLICE_98: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R8C16D.CLK to R8C16D.Q0 SLICE_98 (from RCLK_c) +ROUTE 4 0.154 R8C16D.Q0 to R8C16D.M1 nRCS_N_139 (to RCLK_c) + -------- + 0.287 (46.3% logic, 53.7% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_98: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R8C16D.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_98: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R8C16D.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + +================================================================================ +Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ; + 113 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted_406 (from PHI2_c -) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_15 to SLICE_15 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_15 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R10C14C.CLK to R10C14C.Q0 SLICE_15 (from PHI2_c) +ROUTE 2 0.132 R10C14C.Q0 to R10C14C.A0 C1Submitted +CTOF_DEL --- 0.101 R10C14C.A0 to R10C14C.F0 SLICE_15 +ROUTE 1 0.000 R10C14C.F0 to R10C14C.DI0 n1398 (to PHI2_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R10C14C.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R10C14C.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.629ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q ADSubmitted_407 (from PHI2_c -) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 0.601ns (38.9% logic, 61.1% route), 2 logic levels. + + Constraint Details: + + 0.601ns physical path delay SLICE_10 to SLICE_19 meets + -0.028ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.028ns) by 0.629ns + + Physical Path Details: + + Data path SLICE_10 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R10C14B.CLK to R10C14B.Q0 SLICE_10 (from PHI2_c) +ROUTE 1 0.224 R10C14B.Q0 to R9C14C.B1 ADSubmitted +CTOF_DEL --- 0.101 R9C14C.B1 to R9C14C.F1 SLICE_88 +ROUTE 1 0.143 R9C14C.F1 to R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 0.601 (38.9% logic, 61.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_10: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R10C14B.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R9C14B.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.715ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in XOR8MEG_408 (to PHI2_c -) + + Delay: 0.687ns (34.1% logic, 65.9% route), 2 logic levels. + + Constraint Details: + + 0.687ns physical path delay SLICE_19 to SLICE_50 meets + -0.028ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.028ns) by 0.715ns + + Physical Path Details: + + Data path SLICE_19 to SLICE_50: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R9C14B.CLK to R9C14B.Q0 SLICE_19 (from PHI2_c) +ROUTE 2 0.310 R9C14B.Q0 to R10C15B.B1 CmdEnable +CTOF_DEL --- 0.101 R10C15B.B1 to R10C15B.F1 SLICE_83 +ROUTE 1 0.143 R10C15B.F1 to R10C15D.CE PHI2_N_120_enable_3 (to PHI2_c) + -------- + 0.687 (34.1% logic, 65.9% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R9C14B.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_50: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R10C15D.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.873ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in CmdUFMCS_412 (to PHI2_c -) + FF CmdUFMCLK_413 + + Delay: 0.845ns (39.6% logic, 60.4% route), 3 logic levels. + + Constraint Details: + + 0.845ns physical path delay SLICE_19 to SLICE_100 meets + -0.028ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.028ns) by 0.873ns + + Physical Path Details: + + Data path SLICE_19 to SLICE_100: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R9C14B.CLK to R9C14B.Q0 SLICE_19 (from PHI2_c) +ROUTE 2 0.224 R9C14B.Q0 to R10C15A.C0 CmdEnable +CTOF_DEL --- 0.101 R10C15A.C0 to R10C15A.F0 SLICE_73 +ROUTE 2 0.138 R10C15A.F0 to R10C15A.C1 n2204 +CTOF_DEL --- 0.101 R10C15A.C1 to R10C15A.F1 SLICE_73 +ROUTE 2 0.148 R10C15A.F1 to R9C15A.CE PHI2_N_120_enable_8 (to PHI2_c) + -------- + 0.845 (39.6% logic, 60.4% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R9C14B.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_100: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R9C15A.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.873ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in CmdUFMSDI_414 (to PHI2_c -) + + Delay: 0.845ns (39.6% logic, 60.4% route), 3 logic levels. + + Constraint Details: + + 0.845ns physical path delay SLICE_19 to SLICE_99 meets + -0.028ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.028ns) by 0.873ns + + Physical Path Details: + + Data path SLICE_19 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R9C14B.CLK to R9C14B.Q0 SLICE_19 (from PHI2_c) +ROUTE 2 0.224 R9C14B.Q0 to R10C15A.C0 CmdEnable +CTOF_DEL --- 0.101 R10C15A.C0 to R10C15A.F0 SLICE_73 +ROUTE 2 0.138 R10C15A.F0 to R10C15A.C1 n2204 +CTOF_DEL --- 0.101 R10C15A.C1 to R10C15A.F1 SLICE_73 +ROUTE 2 0.148 R10C15A.F1 to R9C15C.CE PHI2_N_120_enable_8 (to PHI2_c) + -------- + 0.845 (39.6% logic, 60.4% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R9C14B.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R9C15C.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.252ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted_406 (from PHI2_c -) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 1.224ns (35.6% logic, 64.4% route), 4 logic levels. + + Constraint Details: + + 1.224ns physical path delay SLICE_15 to SLICE_19 meets + -0.028ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.028ns) by 1.252ns + + Physical Path Details: + + Data path SLICE_15 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R10C14C.CLK to R10C14C.Q0 SLICE_15 (from PHI2_c) +ROUTE 2 0.212 R10C14C.Q0 to R10C14D.A1 C1Submitted +CTOF_DEL --- 0.101 R10C14D.A1 to R10C14D.F1 SLICE_77 +ROUTE 1 0.222 R10C14D.F1 to R10C14A.B1 n2210 +CTOF_DEL --- 0.101 R10C14A.B1 to R10C14A.F1 SLICE_97 +ROUTE 1 0.211 R10C14A.F1 to R9C14C.A1 n7_adj_5 +CTOF_DEL --- 0.101 R9C14C.A1 to R9C14C.F1 SLICE_88 +ROUTE 1 0.143 R9C14C.F1 to R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 1.224 (35.6% logic, 64.4% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R10C14C.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R9C14B.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.277ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in CmdSubmitted_411 (to PHI2_c -) + + Delay: 1.249ns (34.9% logic, 65.1% route), 4 logic levels. + + Constraint Details: + + 1.249ns physical path delay SLICE_19 to SLICE_20 meets + -0.028ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.028ns) by 1.277ns + + Physical Path Details: + + Data path SLICE_19 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R9C14B.CLK to R9C14B.Q0 SLICE_19 (from PHI2_c) +ROUTE 2 0.224 R9C14B.Q0 to R10C15A.C0 CmdEnable +CTOF_DEL --- 0.101 R10C15A.C0 to R10C15A.F0 SLICE_73 +ROUTE 2 0.225 R10C15A.F0 to R9C15B.B0 n2204 +CTOF_DEL --- 0.101 R9C15B.B0 to R9C15B.F0 SLICE_74 +ROUTE 2 0.221 R9C15B.F0 to R9C17A.D1 n2220 +CTOF_DEL --- 0.101 R9C17A.D1 to R9C17A.F1 SLICE_89 +ROUTE 1 0.143 R9C17A.F1 to R9C17D.CE PHI2_N_120_enable_7 (to PHI2_c) + -------- + 1.249 (34.9% logic, 65.1% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R9C14B.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R9C17D.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.277ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in Cmdn8MEGEN_410 (to PHI2_c -) + + Delay: 1.249ns (34.9% logic, 65.1% route), 4 logic levels. + + Constraint Details: + + 1.249ns physical path delay SLICE_19 to SLICE_24 meets + -0.028ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.028ns) by 1.277ns + + Physical Path Details: + + Data path SLICE_19 to SLICE_24: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R9C14B.CLK to R9C14B.Q0 SLICE_19 (from PHI2_c) +ROUTE 2 0.224 R9C14B.Q0 to R10C15A.C0 CmdEnable +CTOF_DEL --- 0.101 R10C15A.C0 to R10C15A.F0 SLICE_73 +ROUTE 2 0.225 R10C15A.F0 to R9C15B.B0 n2204 +CTOF_DEL --- 0.101 R9C15B.B0 to R9C15B.F0 SLICE_74 +ROUTE 2 0.221 R9C15B.F0 to R9C17A.D0 n2220 +CTOF_DEL --- 0.101 R9C17A.D0 to R9C17A.F0 SLICE_89 +ROUTE 1 0.143 R9C17A.F0 to R9C17C.CE PHI2_N_120_enable_6 (to PHI2_c) + -------- + 1.249 (34.9% logic, 65.1% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R9C14B.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_24: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R9C17C.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 5.431ns (weighted slack = 10.862ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q XOR8MEG_408 (from PHI2_c -) + Destination: FF Data in RA11_385 (to PHI2_c +) + + Delay: 0.371ns (63.1% logic, 36.9% route), 2 logic levels. + + Constraint Details: + + 0.371ns physical path delay SLICE_50 to SLICE_33 meets + -0.013ns DIN_HLD and + -5.047ns delay constraint less + 0.000ns skew requirement (totaling -5.060ns) by 5.431ns + + Physical Path Details: + + Data path SLICE_50 to SLICE_33: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R10C15D.CLK to R10C15D.Q0 SLICE_50 (from PHI2_c) +ROUTE 1 0.137 R10C15D.Q0 to R10C16A.C0 XOR8MEG +CTOF_DEL --- 0.101 R10C16A.C0 to R10C16A.F0 SLICE_33 +ROUTE 1 0.000 R10C16A.F0 to R10C16A.DI0 RA11_N_184 (to PHI2_c) + -------- + 0.371 (63.1% logic, 36.9% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_50: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R10C15D.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_33: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R10C16A.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 5.992ns (weighted slack = 11.984ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i0 (from PHI2_c +) + Destination: FF Data in CmdUFMCS_412 (to PHI2_c -) + FF CmdUFMCLK_413 + + Delay: 0.917ns (47.5% logic, 52.5% route), 4 logic levels. + + Constraint Details: + + 0.917ns physical path delay SLICE_93 to SLICE_100 meets + -0.028ns CE_HLD and + -5.047ns delay constraint less + 0.000ns skew requirement (totaling -5.075ns) by 5.992ns + + Physical Path Details: + + Data path SLICE_93 to SLICE_100: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R9C16A.CLK to R9C16A.Q0 SLICE_93 (from PHI2_c) +ROUTE 1 0.138 R9C16A.Q0 to R9C15A.C1 Bank_0 +CTOF_DEL --- 0.101 R9C15A.C1 to R9C15A.F1 SLICE_100 +ROUTE 1 0.053 R9C15A.F1 to R9C15B.D1 n2277 +CTOF_DEL --- 0.101 R9C15B.D1 to R9C15B.F1 SLICE_74 +ROUTE 8 0.142 R9C15B.F1 to R10C15A.D1 n26 +CTOF_DEL --- 0.101 R10C15A.D1 to R10C15A.F1 SLICE_73 +ROUTE 2 0.148 R10C15A.F1 to R9C15A.CE PHI2_N_120_enable_8 (to PHI2_c) + -------- + 0.917 (47.5% logic, 52.5% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R9C16A.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_100: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R9C15A.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference(MIN Delays) | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY NET "RCLK_c" 299.401000 MHz ; | 0.000 ns| 0.304 ns| 1 + | | | +FREQUENCY NET "PHI2_c" 99.079000 MHz ; | 0.000 ns| 0.379 ns| 2 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 + Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 335 (setup), 0 (hold) +Score: 391939 (setup), 0 (hold) +Cumulative negative slack: 304509 (304509+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_bgn.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_bgn.html new file mode 100644 index 0000000..e5f11b0 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_bgn.html @@ -0,0 +1,152 @@ + +Bitgen Report + + +

BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 15 05:01:23 2023
+
+
+Command: bitgen -g RamCfg:Reset -path D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC -w -jedec -gui RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf 
+
+Loading design for application Bitgen from file RAM2GS_LCMXO2_1200HC_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 4
+Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.44.
+Performance Hardware Data Status:   Final          Version 34.4.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from RAM2GS_LCMXO2_1200HC_impl1.prf.
+
+
+Preference Summary:
+
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                         RamCfg  |                        Reset**  |
++---------------------------------+---------------------------------+
+|                     MCCLK_FREQ  |                         2.08**  |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                      JTAG_PORT  |                       ENABLE**  |
++---------------------------------+---------------------------------+
+|                       SDM_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                 SLAVE_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                MASTER_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                       I2C_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|        MUX_CONFIGURATION_PORTS  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  CONFIGURATION  |                          CFG**  |
++---------------------------------+---------------------------------+
+|                COMPRESS_CONFIG  |                           ON**  |
++---------------------------------+---------------------------------+
+|                        MY_ASSP  |                          OFF**  |
++---------------------------------+---------------------------------+
+|               ONE_TIME_PROGRAM  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                 ENABLE_TRANSFR  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  SHAREDEBRINIT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|            BACKGROUND_RECONFIG  |                          OFF**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+ 
+Bitstream Status: Final           Version 1.95.
+ 
+Saving bit stream in "RAM2GS_LCMXO2_1200HC_impl1.jed".
+ 
+===========
+UFM Summary.
+===========
+UFM Size:        511 Pages (128*511 Bits).
+UFM Utilization: General Purpose Flash Memory.
+ 
+Available General Purpose Flash Memory:  511 Pages (Page 0 to Page 510).
+Initialized UFM Pages:                     0 Page.
+ 
+Total CPU Time: 1 secs 
+Total REAL Time: 2 secs 
+Peak Memory Usage: 253 MB
+
+
+
+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+
+ + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_iotiming.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_iotiming.html new file mode 100644 index 0000000..1fddacf --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_iotiming.html @@ -0,0 +1,204 @@ + +I/O Timing Report + + +
I/O Timing Report
+Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 5
+Package Status:                     Final          Version 1.44.
+Performance Hardware Data Status:   Final          Version 34.4.
+Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 6
+Package Status:                     Final          Version 1.44.
+Performance Hardware Data Status:   Final          Version 34.4.
+Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: M
+Package Status:                     Final          Version 1.44.
+Performance Hardware Data Status:   Final          Version 34.4.
+// Design: RAM2GS
+// Package: TQFP100
+// ncd File: ram2gs_lcmxo2_1200hc_impl1.ncd
+// Version: Diamond (64-bit) 3.12.1.454
+// Written on Tue Aug 15 05:03:41 2023
+// M: Minimum Performance Grade
+// iotiming RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
+
+I/O Timing Report (All units are in ns)
+
+Worst Case Results across Performance Grades (M, 6, 5, 4):
+
+// Input Setup and Hold Times
+
+Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
+----------------------------------------------------------------------
+CROW[0] nCRAS F     0.891      4       0.676     4
+CROW[1] nCRAS F     0.281      4       1.216     4
+Din[0]  PHI2  F     7.907      4       0.089     6
+Din[0]  nCCAS F     1.465      4       0.158     4
+Din[1]  PHI2  F     7.300      4       1.026     4
+Din[1]  nCCAS F     1.035      4       0.527     4
+Din[2]  PHI2  F     6.237      4       1.467     4
+Din[2]  nCCAS F     1.719      4      -0.108     M
+Din[3]  PHI2  F     6.623      4       0.176     6
+Din[3]  nCCAS F     0.339      4       0.916     4
+Din[4]  PHI2  F     6.902      4       1.033     4
+Din[4]  nCCAS F     0.687      4       0.951     4
+Din[5]  PHI2  F     6.837      4       1.369     4
+Din[5]  nCCAS F     2.810      4      -0.220     M
+Din[6]  PHI2  F     7.648      4      -0.050     M
+Din[6]  nCCAS F     1.281      4       0.266     4
+Din[7]  PHI2  F     7.823      4      -0.159     M
+Din[7]  nCCAS F     1.810      4      -0.096     M
+MAin[0] PHI2  F     6.751      4      -0.273     M
+MAin[0] nCRAS F     1.765      4      -0.033     4
+MAin[1] PHI2  F     5.718      4       0.117     M
+MAin[1] nCRAS F     1.814      4      -0.051     M
+MAin[2] PHI2  F     5.759      4      -0.021     M
+MAin[2] nCRAS F     1.323      4       0.309     4
+MAin[3] PHI2  F     6.165      4      -0.235     M
+MAin[3] nCRAS F     0.694      4       0.836     4
+MAin[4] PHI2  F     5.236      4      -0.147     M
+MAin[4] nCRAS F     0.730      4       0.835     4
+MAin[5] PHI2  F     6.024      4       0.135     M
+MAin[5] nCRAS F     0.734      4       0.868     4
+MAin[6] PHI2  F     5.689      4      -0.277     M
+MAin[6] nCRAS F     0.288      4       1.210     4
+MAin[7] PHI2  F     6.398      4      -0.307     M
+MAin[7] nCRAS F     1.215      4       0.401     4
+MAin[8] nCRAS F     0.817      4       0.727     4
+MAin[9] nCRAS F     0.941      4       0.601     4
+PHI2    RCLK  R     0.771      4       1.143     4
+UFMSDO  RCLK  R    -0.238      M       2.305     4
+nCCAS   RCLK  R     1.651      4       0.388     4
+nCCAS   nCRAS F     5.028      4      -0.828     M
+nCRAS   RCLK  R     0.593      4       1.309     4
+nFWE    PHI2  F     5.741      4       0.781     4
+nFWE    nCRAS F     0.578      4       0.996     4
+
+
+// Clock to Output Delay
+
+Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
+------------------------------------------------------------------------
+LED    RCLK  R    14.758         4        4.129          M
+LED    nCRAS F    12.396         4        3.434          M
+RA[0]  RCLK  R    13.780         4        3.894          M
+RA[0]  nCRAS F    11.795         4        3.277          M
+RA[10] RCLK  R    12.425         4        3.587          M
+RA[11] PHI2  R    10.432         4        3.084          M
+RA[1]  RCLK  R    15.081         4        4.198          M
+RA[1]  nCRAS F    12.364         4        3.447          M
+RA[2]  RCLK  R    14.518         4        4.082          M
+RA[2]  nCRAS F    11.696         4        3.275          M
+RA[3]  RCLK  R    13.789         4        3.897          M
+RA[3]  nCRAS F    12.223         4        3.392          M
+RA[4]  RCLK  R    15.175         4        4.228          M
+RA[4]  nCRAS F    12.424         4        3.464          M
+RA[5]  RCLK  R    13.789         4        3.897          M
+RA[5]  nCRAS F    12.359         4        3.437          M
+RA[6]  RCLK  R    15.420         4        4.299          M
+RA[6]  nCRAS F    12.865         4        3.560          M
+RA[7]  RCLK  R    14.672         4        4.127          M
+RA[7]  nCRAS F    12.253         4        3.386          M
+RA[8]  RCLK  R    14.952         4        4.191          M
+RA[8]  nCRAS F    12.244         4        3.383          M
+RA[9]  RCLK  R    14.092         4        3.978          M
+RA[9]  nCRAS F    13.164         4        3.653          M
+RBA[0] nCRAS F    10.278         4        2.970          M
+RBA[1] nCRAS F    10.474         4        3.030          M
+RCKE   RCLK  R    12.407         4        3.610          M
+RDQMH  RCLK  R    13.754         4        3.857          M
+RDQML  RCLK  R    13.482         4        3.833          M
+RD[0]  nCCAS F    10.515         4        3.076          M
+RD[1]  nCCAS F    10.118         4        2.965          M
+RD[2]  nCCAS F     9.759         4        2.886          M
+RD[3]  nCCAS F     9.798         4        2.878          M
+RD[4]  nCCAS F    10.979         4        3.178          M
+RD[5]  nCCAS F    11.063         4        3.207          M
+RD[6]  nCCAS F    10.317         4        3.018          M
+RD[7]  nCCAS F    10.232         4        2.986          M
+UFMCLK RCLK  R    12.402         4        3.606          M
+UFMSDI RCLK  R    11.975         4        3.501          M
+nRCAS  RCLK  R    12.350         4        3.564          M
+nRCS   RCLK  R    11.923         4        3.459          M
+nRRAS  RCLK  R    11.995         4        3.494          M
+nRWE   RCLK  R    11.975         4        3.501          M
+nUFMCS RCLK  R    11.818         4        3.434          M
+WARNING: you must also run trce with hold speed: 4
+WARNING: you must also run trce with hold speed: 6
+WARNING: you must also run trce with setup speed: M
+
+
+
+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+
+ + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_lattice.synproj b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_lattice.synproj new file mode 100644 index 0000000..7edeb6a --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_lattice.synproj @@ -0,0 +1,41 @@ +-a "MachXO2" +-d LCMXO2-1200HC +-t TQFP100 +-s 4 +-frequency 200 +-optimization_goal Balanced +-bram_utilization 100 +-ramstyle Auto +-romstyle auto +-dsp_utilization 100 +-use_dsp 1 +-use_carry_chain 1 +-carry_chain_length 0 +-force_gsr Auto +-resource_sharing 1 +-propagate_constants 1 +-remove_duplicate_regs 1 +-mux_style Auto +-max_fanout 1000 +-fsm_encoding_style Auto +-twr_paths 3 +-fix_gated_clocks 1 +-loop_limit 1950 + + + +-use_io_insertion 1 +-resolve_mixed_drivers 0 +-use_io_reg auto + + +-lpf 1 +-p "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC" +-ver "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v" +-top RAM2GS + + +-p "C:/lscc/diamond/3.12/ispfpga/xo2c00/data" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC" + +-ngd "RAM2GS_LCMXO2_1200HC_impl1.ngd" + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.asd b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.asd new file mode 100644 index 0000000..4f5aca5 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.asd @@ -0,0 +1,15 @@ +[ActiveSupport MAP] +Device = LCMXO2-1200HC; +Package = TQFP100; +Performance = 4; +LUTS_avail = 1280; +LUTS_used = 143; +FF_avail = 1360; +FF_used = 102; +INPUT_LVCMOS25 = 26; +OUTPUT_LVCMOS25 = 33; +BIDI_LVCMOS25 = 8; +IO_avail = 80; +IO_used = 67; +EBR_avail = 7; +EBR_used = 0; diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.cam b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.cam new file mode 100644 index 0000000..0e2396b --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.cam @@ -0,0 +1,88 @@ +[ START MERGED ] +n2380 Ready +PHI2_N_120 PHI2_c +nRWE_N_176 nRWE_N_177 +n1407 nRowColSel_N_34 +n1408 nRowColSel_N_35 +[ END MERGED ] +[ START CLIPPED ] +GND_net +VCC_net +FS_610_add_4_19/S1 +FS_610_add_4_19/CO +FS_610_add_4_1/S0 +FS_610_add_4_1/CI +[ END CLIPPED ] +[ START DESIGN PREFS ] +SCHEMATIC START ; +# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:03:27 2023 + +SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ; +LOCATE COMP "RD[7]" SITE "43" ; +LOCATE COMP "RD[6]" SITE "42" ; +LOCATE COMP "RD[5]" SITE "41" ; +LOCATE COMP "RD[4]" SITE "40" ; +LOCATE COMP "RD[3]" SITE "39" ; +LOCATE COMP "RD[2]" SITE "38" ; +LOCATE COMP "RD[1]" SITE "37" ; +LOCATE COMP "RD[0]" SITE "36" ; +LOCATE COMP "Dout[7]" SITE "82" ; +LOCATE COMP "Dout[6]" SITE "78" ; +LOCATE COMP "Dout[5]" SITE "84" ; +LOCATE COMP "Dout[4]" SITE "83" ; +LOCATE COMP "Dout[3]" SITE "85" ; +LOCATE COMP "Dout[2]" SITE "87" ; +LOCATE COMP "Dout[1]" SITE "86" ; +LOCATE COMP "Dout[0]" SITE "76" ; +LOCATE COMP "LED" SITE "34" ; +LOCATE COMP "RBA[1]" SITE "60" ; +LOCATE COMP "RBA[0]" SITE "58" ; +LOCATE COMP "RA[11]" SITE "59" ; +LOCATE COMP "RA[10]" SITE "64" ; +LOCATE COMP "RA[9]" SITE "63" ; +LOCATE COMP "RA[8]" SITE "65" ; +LOCATE COMP "RA[7]" SITE "75" ; +LOCATE COMP "RA[6]" SITE "68" ; +LOCATE COMP "RA[5]" SITE "70" ; +LOCATE COMP "RA[4]" SITE "74" ; +LOCATE COMP "RA[3]" SITE "71" ; +LOCATE COMP "RA[2]" SITE "69" ; +LOCATE COMP "RA[1]" SITE "67" ; +LOCATE COMP "RA[0]" SITE "66" ; +LOCATE COMP "nRCS" SITE "57" ; +LOCATE COMP "RCKE" SITE "53" ; +LOCATE COMP "nRWE" SITE "49" ; +LOCATE COMP "nRRAS" SITE "54" ; +LOCATE COMP "nRCAS" SITE "52" ; +LOCATE COMP "RDQMH" SITE "51" ; +LOCATE COMP "RDQML" SITE "48" ; +LOCATE COMP "UFMCLK" SITE "29" ; +LOCATE COMP "UFMSDI" SITE "30" ; +LOCATE COMP "PHI2" SITE "8" ; +LOCATE COMP "MAin[9]" SITE "32" ; +LOCATE COMP "MAin[8]" SITE "25" ; +LOCATE COMP "MAin[7]" SITE "18" ; +LOCATE COMP "MAin[6]" SITE "24" ; +LOCATE COMP "MAin[5]" SITE "19" ; +LOCATE COMP "MAin[4]" SITE "20" ; +LOCATE COMP "MAin[3]" SITE "21" ; +LOCATE COMP "MAin[2]" SITE "13" ; +LOCATE COMP "MAin[1]" SITE "12" ; +LOCATE COMP "MAin[0]" SITE "14" ; +LOCATE COMP "CROW[1]" SITE "16" ; +LOCATE COMP "CROW[0]" SITE "10" ; +LOCATE COMP "Din[7]" SITE "1" ; +LOCATE COMP "Din[6]" SITE "2" ; +LOCATE COMP "Din[5]" SITE "98" ; +LOCATE COMP "Din[4]" SITE "99" ; +LOCATE COMP "Din[3]" SITE "97" ; +LOCATE COMP "Din[2]" SITE "88" ; +LOCATE COMP "Din[1]" SITE "96" ; +LOCATE COMP "Din[0]" SITE "3" ; +LOCATE COMP "nCCAS" SITE "9" ; +LOCATE COMP "nCRAS" SITE "17" ; +LOCATE COMP "nFWE" SITE "28" ; +LOCATE COMP "RCLK" SITE "62" ; +LOCATE COMP "UFMSDO" SITE "27" ; +SCHEMATIC END ; +[ END DESIGN PREFS ] diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.hrr b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.hrr new file mode 100644 index 0000000..a9cd083 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.hrr @@ -0,0 +1,10 @@ +--------------------------------------------------- +Report for cell RAM2GS + Instance path: RAM2GS + Cell usage: + cell count Res Usage(%) + SLIC 75.00 100.0 + LUT4 123.00 100.0 + IOBUF 67 100.0 + PFUREG 102 100.0 + RIPPLE 10 100.0 diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.ncd b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.ncd new file mode 100644 index 0000000000000000000000000000000000000000..331614c53e06d54bef656752479767b37bc115ae GIT binary patch literal 140118 zcmeHQ2Y4Jsvfg!+Y-5v5<`B_|ut{1;#u!CgShDPu6Hyp!KwxAJOuE47a?UyDoO90U z9T&NrbK>1`IftiLT{T_*bWe}%Gty~=N1sd9)O6Q$SJhwD-P1F3^wGcjUB2|)59Ma& zX4X0eN^6F4JHE5}vV1Oo+wRhpg+i{sYhc@8>8xU@P*~fQ+qAKFLy@?Z9Q_<+e(m?q zJ#>j&ZeHJD=jNfl?rrVGJRLSNb3T{_!_E0zE}QqcrC`~z;m-BTRt$HJ&uuo`**>?$ zaA*14s^OBB=y$BWt%f_p=e8NHv=<%b<~DdmOTiA8xWj%YN-V+eM2S1>ccR1{_B&DH z4*Q)bafkg*l(@sb(o5W7F%Y^I)One?zJM|}%(rlv8#dolPMI4v&*yT(e9tL!!+iCY z*%G2iG&krB6}E)0-3nX6*KUO^;cK_T9rm?b;j8)Dt#F5Z<4bU5he&D>$X6V2RVzZ1>eVZRg2K?^s>EQ}_^Km}$DQ((p*1!jb(*^0jP9Rod4 z3>oMc8C}}eURXv@&gB+xFp<;T!^ZUU+}Fmg+Thlu#ZZ0j^!&!)?NB(fkSH3Sf6ffiE6Ak>36E$Bxt#{V``V^)!4oJ<~>2ZNF3YCc~S^(s)YIZMsi(zjoYS#>i&;|pEde&QX%cDEPqR;^pB5-OO^dmt1mX1BdsnK2<@DOD z)Va0pptnn$PCd&ibI8hLP?Sv*7lWL zKBtZarkxj4>bZ1jn`EDPwqB7d#tKB~2?a!gNj?`7k}q9a^d+!`7N9^v0vl;Q#rTUU z{am`V>I+~q;e3mKp4|)QoBi`_Nu00v=h>7vU-r+lEpfi&pJ!v@e53$Xz4RX{ZuRO* z8bWRV2ggSOH&0GUARE@RcNk?^pp}OEM0R74ZE; zhUBpV2|ci$XODJubqu*q%nlUuQQw2g?8H>F7S&YmEwlH|8tvWM!y<8ltv0j2r`zL; zvr^Uzd%L8)`Fh^(gv<~Y)Tp|k#aDx5zF2{T1aViD;3HOM5cBoC?`|@e!1+j7>aL8o zm@<85lKhAIiSw*docDcACLK8MyP8ZtaNhSc$$>cUJDN;MaNbw2WI>$w^()hqdA05^ z*d!0?=|u0@N%eHpc~vfls+e+pj>b`Cy7wTzWH8Q=?)4pb8o};II#mIz5Py2dl z=C;oot#t|d6e`UeUuV_2`q#NwX=YEQ6YD&1HFHEIQ9kOLBZ${5P*rh!jhNzm&9p=i zui4T@+s{ZD=F5q$f$arbrm}wSyj)o%3|juvzqgpF5J-5&Wf4Qw_dNxTvm$Zntlt{ zDGYW>Y1Us-2rDniX2m7hth6MX6_#YPwvudCQj*QOv24{yxY?41ZDH-ZWZ#*Cn>VRN zSyhsB1AOj%fY03z@VWm1J}V%=XAK1StbzbPtb?$PBvB@GAXzfWmK>Q-jm!*_O_AIf z;HRiSQemKciV7t21>RL(E_4Fh!zqpB07}lFrveWjvzXcXfctwcXKq+F+|4_9Y=IL(FsH+65WsJ zB%&swlZj3tI+f@&qSJ}aAX-ASlxP{za-y?{&L%R7C=eBiN{m{2T>iLA$lv( z+lbyy^bVqT61|J)-9+ypdN0xYh~7{10iq8QeTeA8L?0pgDAC7=K2G!rqE8Ziis;is z|3mZ{qC1H`OY}LS&l7!t=!-;OBD#y{%S2xx`YO@ah`vtr4We%neT(SZMBgF$F46ah zzEAW6q8}3di0H>eKOy=l(a(r}PV@_+UlQF-^uI*EBKkGaJw(4D`YqA#h<;D>2cka` z{fX$$M1LXrE79MG{!a7{qJI+oi|F4(|3@?~@XqJy{~1IxiDnVaCYnPum#BfLk!T*# ze4+(JhY&3!T10dx(P2b~6CFWxB++7`qlk_sI)><2qT`5;Cpv-XM56ls*(z2Ee6nARztCwL*)?_!b=)R{Pd*VV z@5)NMzS~R4ay#kDa{JgwliM51!{t_2%@9Q{oZ76k%e!5VS;ZCRDc_YAtL66ItL0t` z?RL8fzS~b%HLhu5El54#8qI5(+wO%UMe^8PH}4tVzT?_quNfm`0zStj9F;HX=pMTH zit9)A?Ab{!UvPyUJyI+Zeo9<7O~O%xuBgb3J8u{+wn#hNt8^9PS8@9_d!$sTxH@Ps zenW2KdK!CEiP*087mg4wrF)GdrBHhg>AHSL&*=6mcI~7-yO(YpEmbPjO9};c7}E4!2$jv}&hSB%jC{~SuvW8E#fuD6)Zj?CcxHpCK<4tqnA>zlc~v)lsFSc#Sh#T#8b_!*(71wr z43|b0%IzPc1O90g2cg!O!!hR3FKS>*A&P2-H)ejBA3D)iC5;>RH^*bng1As zi(=$4f$F$4hvC*hk@;3orRZMaSXw0S7$T1(%{7x9Q=;jiwpb+;wHoDYxy_Y*xLJS~ z(UsPan?~o$nd=15#_Z_C$(k z4yllkQLPFwgkj19IfrXwQKjTp`E+P58NiR zu(m*@MH(_prYO1Tv0-SqcW7XE#08LB#Y-TziYv%CE+K_ulj-r8`DK0@2q^(>bX~U( zM@g79o)$|{Za6udl-6d0AO}@9eA?!@d37EKA&LoA*Z+*x$nla90f9DoZl2spA$+?{ zn>kW;6W#-;|FhO~Y@&Hn?)EYI#Xk);YnY=kX3;Mbki{M0ltouPMwQ9d0NSyNu04-b z7f1t9<47^&h;zx`I)+DF4M$8@!438jraxomm-$)bV9bjv^ZLXIhDThRfbYTuDT`xR z2!LLZP~wYP?_M%uy4P#4jW<0RGr!D_+oh6gA>&S^XuxXdhCP?xx>vSjNvN@EMbX<(f~b*nnqzI*NQQ*sV7_$A44OjLUT-Fu^MnkqaPWe z@I~FI%=!t}ibJ~O8Y0$I*RNwITqFX$Cg!n*ajt^`6RyL7?{?BnZf+K%iCbGs6sqGrF@8E`ewiP4%IG$x zVI=YbQ*g}uGCz$RVkyG9%HW|h1>ROy4X{u$Ie3FBSKeIOjA9mT%q7RnFY^;IUEP>0 z1~Yi8JdGpeP%xddwbng6;$BgBt`1GOONL?-*^^wU?|PQ-T*q>QS1H1->E4+6Wqyvc zQ8sQj8G@SAW9FCn5%Dgrh3D!mUEbcBMpJrrRCA><^UM51SaD4dFrY zbQS3bg=CwL9;sHH7#B(t3vFy-o4QfZiz=>hLxTWsZjV77#~0V1DJr!!hlZRqFbG*2 zamU39_^$k85|#+%W|JOhi6|KnAlB_R_^vsUmkUiU8b(4RKePO!6F3*ONwL)c5{xdZ zp-E#TnReRH(9!kO1#(fE3st=IpS)&E;F`%&q3{v;vum=5xi5Q#LVoh9Q3^BQ88g4k zPjmrSl@ZeoGf8=&HIQVfkcUPWaDzm|ban5>BRh#UEgv(#%nv(eXkr%yI8UQ8YIZeh zl4de00F=Cp=OW%XQaM^-HLVykzswJ687P+Hm2S(#FRtZVOnLVrrhH3U`DRnzy|^jgoL0VK%DbvH}^9)f;u2@&&j2Jk_V$^trM{I<2s)7b)y%9+F+9OJPs# zDC}BP3VS+7Vb}Mhu%~bo_Q1#;^t6q_ZbTQ!o~lvUO$$=k)AL+fA~tUBI5TgFj(c~b z8D1JNxR;;9TcBNAXi@j#T-3WZ4T43eFV$?E_N7KeeW_H`lS&J|EY)|(j*Ht|nYN(s z>m3)jh6}o$IGc7~dqKcTbiL3N^nB13bUn}%^!(2jbiL0M^nA}2bUn`$^!&~ibiK|L z^nA`1bd6&QdbY6zUDKF?zGZmz(RVi4Z5;PDSuszP<2}YsIbJ_Zl;bVO@p93+rC)G1 zFK1Fgq>yMmHc--RId)3&UgHFED3X~i$cd8u;gV)qA6K_4X#VBx9%ZL&v^Jk8D|}aO zG;j-*HM^MOavRKiHPP5vhU=7@$3s_=IPBtVuHpMgLtz(dQrJTq3cGld!XDyK*u|U_ z_E3kyF7BkThddN^u_uK+^r5heKPl`X5QSZpN?{L$DD2`;3VTRIVHb;1*hAwy^RyO6 zN>8#p#pQ-T6!s)@VNY@+J?6!NT?5YHr@vgeTGTZk7xk>CMP1`@QO|Z-)HNL!^(?1F zUBhuv&u&`OH5(W8tfoa>)pAkKW?Ix$EEo0l%8x}Qz!^O)6-RL+KL!;lN%s;Q95A$9~9`jeRX{g2$JBBV?-__JVR2y7x_yr@BPxO+UuEBPq zCUe#H_MyV6!fjV=-@g6Kp4jpGfQgt~Yz2pw;I_x|33k9sQe2!vmZ9 zH_7o#Qe`CBDAe?NW^UHj?m?>y`qQ>)YlpIDo4@1yQq%~;FGm8YYQ#1IBkr87-Dn#f zpwV;3d#ScpHgR&m*wVWf=;%hnQP;Ykk z26_vQy;PU+YFeg_iC#`tjE?z1qL<;AH_k5-R7Vy(xKKSCsGfE3pn6V*Y6rQKk7|B`L~=*`WQiV6m$lXgsE)=@2N$a61J&~m9#k*LQ2k#g6ifVsy~{xTGmeMSlzTT<*k?<=wcZ!{Fh8-{Lq63;)iDtpLB>j3t*bJ3%slrKPRt5K~9gKlead70DcGn%>X|G$9%0$ z0eDLg;P>(6@FRigBMu%+FU~MM>6mtx!})b80IqwI->MQGjJNXAcL>$528tQgufj2- zdQ?zd4Wjx*PTG#{ZSifb3A&>dypu)AxsbS%)nRU89oX$GzELH5qdNmf9X$9wI>YZI z;&)cyb{0b{4AC~3O9$r5F9syJ{zC+ktwBiM#}nPyX$FgP1n%2>1cWq(SQewxr=2n_)Cfl!lWVDb*JFQlo+P8j7w56=8$7~~` z{WtCOpWR+Ye-00B>8TCNS=nSJ#o{~70vp9>=zLOc#yZ{-c0Y!5w1q}T)=dWqvSmJz zZ4`@kmzk|$ld+{FzG@|31VBoTpKFnKkkVd8|HgBb0c(6#w}kOL`End{i3@SeVc>)a z(&4r2j|Cu2cwRwxUU3HjdPO%NO;GPzA-L{X(P_ZWux@Xs|Au-tts>gbeWFQx7bhCt zr&xHO9EA6&8N7M#XB6nOeW2qx-gBxcet-9Y%EUPiVfjjgz}tZ;y>3&F8LF4zn4x-h z1l91W^rPZXl`MNlhk+nv;^@W`(k%9D-EZX#ob{GC9wlpXI*U(7_mUzf5MJ>td1eq^ zXJzop;58BOnvs}2w#DwZYI@`O<0B*Zgm*B$I1ZmEoh>!9zZG3bV9^>-C*?QFVU*xH zr#OwBW7F8#L7WvboMkwh2%H6O##9+p=3!KS0Y|>cWEODzGi|z4!q0unk?VLU`xP8> z?t4T8-tgkiYXab7^X-J2sK@P?Or zu8V{BKOeZ_zR7`22IHgEYA}noX86mp=tN{u8Lc{NGwExnr$?X(@A0c6(6j|X)1HAQ z1IlkLB!y&p9REL$@=&1+h22c;n0XskGrG zeQ?h~F@5Auk9m06fMae_V}$bXYb4$sKsnD1=_Z7o8ZKRGwgE8i%{~CWyLbS1`xWQd z!9x>9I*<)M(fIUUZRR=O;(v88>vm-L&+tDH_?HEr`0dBNy(^*`ZRSa?__Ri6{3+xv zV3;%Y18~e3KP|#^_$3l=31gbJ=9ycIifXf6uk(BZ>jPM*{V#yI%YwNx2v-v)!NOrglO4Z zAUS&fcMsg#RU%r3?X_s_38HmPhSm(N6Ngr3eBGRWuZ8gy-V`KH#3a$W4CpjyrH@&= zcFOkct&Px2h`xaT z(mUdtT_<3uie)6b(e+-f z9c{1!*ufz1HfF%ffHx7qORgPNV!-qF1hsM!vunrk6{l9d&tn#xU9j%PG1uLLV@{gw z5tzfXO?ef={yp1iKyJ6PE1v)3Eq|DMPB5T{ETC&aKyS(bodJ5{03Dx^7Uh8xi`w|9 zlDwtC-Y1F!x`lJCOjcb;KOGR}De2KTW=Qu7q?^Mxa?>6~p`6U=+3w?wtqe=jrX7M) z|0v29i{i~e6mQK?oS}FkP@H@erH#{P2#?PM{+j_??sW4> zo*)l@>4L5T(ePy~&Cg^X2riLm4{R$S&A>0TVB8i2<3$-5GcZmP76T5~>vB{@dgL3AqmFNbm2iAP-ZQ2ahHV>?e zBd~_I9)=!EGaDPC*ADRzH$D&!rQ|8hw^vxKZVzJh$_%R+RwoXt4j!>}!Cx*e={GWb ztR4?+GFCU@m=o(s5mv+Zc;uzo?y|5M{$ewsjEV0sH+tmdCfMLW+aUh)cY{s9Y;~ta z=#C&lugVabA#~yp8ehuAXXRv9Lww*HZ6EaTNgtAR2fjz)nDKdPgwOD8o96`vz9D?d z`#I%iteLq+cV)5hXusaeIRV(b#$xm8AT~!bY-ZS;2y6yk%}~%6ekHP}OgRl25(DHa zKdY0x-TGwUlxts$W5(^#5pKiV1z#4xEkA3ciIq`&VEBx`Omm{2w7JgW_u3$ScV+m^ z@H-Lsm6>XM^jj=MNK9h1Ss$A7v+EOqN`un;X*gz-_C+WS-?4GF;M+~T=H{rs&wej& z5Q}o=q+v4tqK4~(m>kV8nPGAwFd6trOo8W}cEdw_DBK)-##KkSyq@#~V30HC+6aT; zZ^XPQkSU!JF7Rl#)9>G#Gw(exLmy}izgP1Hn>BX_5qkd&p&3Fa2ce}(YHqyU!{O6# zY;t2hdL4C3_y+28_JPYfdqc!c7J)ZL2&A>{oB2Si*!NP-{<>rz?7@E;+TiDvGRNqcCMt?YIu`iXdN<-j)G61N1}yI(f@f?uv#VE^X0=+T1bkAVA9V(Bp8-pgm`#TsS8JYIuu7 zcOc)&zQGlD(C3(<*(u$G;dk)T_m^nbL(^dIHZwKVfofoM8lOKtAPFToy)kOjjEzwg znbB)Gy%A?7edb)=CpC9nVO^0v)g(uA=u1v|FuSWq|DGe;{-x9`YH1{KcJDTnksXUD z6J4x<>hkBFbf6uvzuHwNkBJ+hys^Wd;@?P8~(6?pkXfGQ5wDZ=S(P!sIUo)pRGr@|jWiY(`FX-(A{CQY-D2`diha>ohH_wEg zdDi6TJ&k{<;mKQcpdhUAGra$tG0pf?zjAK5Dw8J1Wp ziQ~Lvzlh?aybKicV#x_OW^vELF{AuR5z50`ZGIg{^7g?kT{nrpsta%Dq6idy*f#c_ zu4$O(A7i7#qY)h*hv@LwEIMS-VUnT)-fAFqZt*MvsEoC?hj z8`>w14?ZlVCp_e{eswwmev$>;6OrSdf*kkcEXQRzZXy6DBVcEzn?Bj$?<;TBJ#fj- z0k-jkHuRQ}UKhf-OK{8y?m;-_1b17M;KKWK_Ul6rQEsFAi4(WDH7WDlr&*Lg6)1lO zQ2z7`U^(^S;@GM#%exilIq}^;LV0*g&(8yi&u&R@-WU?U zQFC8ezkPuX3eQJScoBla3$vh*1%-(S3dzqK7AyLWufY1Pe1HXacjAGeCG~0RD#Jgy zuzL{#0*{op>?rRb4!GN6*)ISU(fToD5%p zV@`(8kCI_{r_=d?Sinh7bDq7+={)r6PXWL(yy?~l(v2^=%dkHIk~{kP(nasHMF=izNn z-%Y`}xjiH=!1ed{nkXPIPl&G)^J}fA2jt&jA^&zj{#}6lJ2S{#}q5*VAZL8>$lhyJ~|#A+|pAU zrcX%eI-k@ykj1_a*l_WFgo_U$TzoJK7g@NNh;R`Y`ZqIlu~W>sL)OeVmdU?64!9E7 z=Ar))IOaMZ!ZBn2gAw+_Tg5&d!afZIl8^M+Pfp1P;wBOP6F9N|h(-5@f$on1-5<@+ zouPXo&>a{I6c~*5o|}Vhd000E_!S0i%Br7k6LUkt0|9xCDUZQ1x8j{RX6f&ULPB^m z*qcKkp>u_KMWUS&L?3*e;Ab2s^e)~fEc8DP=zj{(|6~UJ4EhrR{lKEWyw?=?jxXHH zQ~aTC0JOwr2rj%=0=^9IO*m$FZ^bdg`?C?e!&}|jLhv?2dPVnAd48E5{@9-lp8sQk z_UQ;{*#^&SgXbh{@RWTmaV%9e9r`osR>nbc*Yx#33M1*p2r1!>U>Aju5?}A;#c_H2 z1!YHC{WdRx^ma?f@15^!i`bnON}tJ~lx-24ye(pZ#|z~?R1z^axroU(MTiM+1PkRB zC$-4TQc%RH>Ch_DjgX%(Di(Wge` z!(FVD5hD?8cR{{ z#l-HD@>^t9cqom%1Dt15&%t@Vz_TM1hqp)tQQWy=($`Ap?#BeKlYZHv_%5LMt3dHr zG8AVho(L2N)=7)H$0>Q!w5-n%B|l>-pK1#(q=eIR?mPgSCx1gYX5h!38e-tTFamyf z&(x~|lf&SB6KAcIzC06cpV+_eE+#ii><#$lJ$>y11@pmGZe8lT%)f5&{(`sZo@m4SN&jv2TQ7oZjk;jK;|Js_k`#zv>TVb{D> zvwfh5&rj_W#NVdA|M_Zm*ZK)z%J!x zeQF^&FqdsjA^f+byuz*n=w|fSaLnlc6pk7FAF=2UZ)v*Ep#Mh}{XYcye**OXI75Gi z{>ehWH!FA6)><_C2hh(54Wgg1oV>%-1#~m|*W;LL{11*<_NOiS!@HO6GwA=BMgLEM z{$Bw7KhMygp?{Ll-@-slSy^vkRE9SwrhmO%L?+R{2I%IC4&a!tb0>}&{hzVu4{vVz zR$%1s+LbwLA zXE85-H~?(`pFbJL4EXoqm;wJ@3;6IJt!e=9{8n2#%Xik~_qE^T9t)>mM{tU*i}Rl| zvJVkuA0q1L#`lX1xc>7G5e4>}$h|I;ApOmZRUJ}0NXqR1QW!}mS)_#bX1#V_NU8Ik zCcm}V{0&mw?~&?$m!-Na)lE{W!v}Z+Yhm#xdmVu0PjmsAdkT&@)jbc#4DsjIx-YI? z%AYUEZ|ED$ZRjkvcIwwmUa+B~ySuNQe>ZKa^_lxc=3rA(-ynT%g6{?wbrqzXVp;u;MOy{`a1?TtQuV3)ZMYE!-^Pe+EVN3Z6Boj z#T(WbX5V^}*fiK}{+3HM^{ub*As1-s-_ku~PDWCia=Altv$<*9-rO9iB?q&)fplLv z_lMj}DrElpV{UF#SIW#XEr^QqC8EE%4a&!7HB57GWSWDcsHswGZq!sc%8|;Ak>;Oz zIyL0<4SnnTy3NZJ&Phbw5-)K^O?T{?JDKd%;@PQ#<(qQ%1v~vo?eypRvQu(5X0e60 zdjt*jc`{V9YpCY?7NGv3hWcxL87dGca`datyoAF$x#8D@SdBXO}@c4 zapp&a6ATij6;9@;P3G2@O^y!OBz?yEO}2?M6(XBpggvcn(x5hJtS_4!6R-*IO%3AY zTWk|&*0ZTt!WeB@*<_yDWPW|w zpTPgXSj350wdslx`u<9Uk)!L&BBul_l0JR^VT~Z-WcFI?G)*G(rHsfT$JUocP7PQj zee(VzV-Xi4({-A7oLc1g`m)Gr0gI$h-G59LX^XE9*QV>5;|Xez6YI+$rw0s@K5zdC z8Kl)U$TS^k-A@g2QhgcZjDSJXC+$BagE;$}YNcsvkR~{t^&)9!P265Kp zYn5rbgmQ`+Y`CxbW(^0o3bHOOgdkkjkSAj^^lX-l80|AGwStj5=- z>muVBYLF%MWsv0ogQU;ae@O;$mf~yWX_`amdtT8*WLbR~WJSOr>67)l$so=;e62D~ z4YFJfvZB5Wa%R9F>2vk}C4;zA^~y9|&Y~BxMF=^oz6^3!z#!>U^tsr`ENu$FavW z#Yai)QLZn0v<2*uK2QJ6Xl-lU9-XDaG&M*?4bog+25Ao%Bz>O#+tFIB!;M(eG^Mww zL8|p-kd*<0q|eiTM;XL5NU<k*@l(NJqdT=`;1eY*^bTFZq<2dVd)ck@e(q`aXp4D-iT$2f^1HxNkJr zzc(1C@-Gv2LB62mSHE z=+rpwT2*deeJOWFK)LBt;lHzTom~X|vF(~uquUEqx9jRlw}B7+71C$5|6tuZ8v@92 zF=n3{<@T#`2kJ|?ftPp{)9)nzla=e--0zR=p`04s(z|w}f!knx=~g}*5`Qa2shB?1 z{1@xixli98+c7*fy4|3<-B@3`O}@*qR7{^V{+o5{+;Z=a-7lFM-PTmML-nQGh|LL((U|!Zc}Gw`5CNR*KcDxUZ=)yFHzlIT3@FgUWvbfY`cf^uER$B<-QjKOyevPr1tZ0;)}&l;!6b)jD&sO;bK6qgQ4}W80nerP@OSs!g4f<>wmJ zI#aSu#llpN5w23*UR__hJuINx)Z23T2BTYNN=7fSm}=c#qq-fbFWnv<&~54swtS<} zturMfzr`K4smWy5s&22VFWnvy&~56iviv-wTX$$1dop5bRJ%)6dwqSW_Q-&0)2C$f zN4wnJUj3D+4hW;F+1>S}*%JerO`ni080~U5HulF}ct15hdxL8B{`IBV`vo+cJ{>z` zwAbCk8++zpY7~2;D)y%OQtU|q#imcj7S`NNJGJJizHPoo6?=1iDYiAK*mC+*Y!UCi z8I13~i9NV9H9mWbs`l3UQf+5Iwdqr_L+`xPY^1r7)*N!ZIeMpTE@!CaA@ofvLmLaZ z)$|{+jy8ve28xzN++5B${qU9MuQgJC8U6W$T<%dX$>omtIq$^L@>Ybw$!ZcsCG!E^ zi~w(DfHy0^n;qcI3Gn6ycntwwV}Q3Hz&k9!J3PQUBEUN`z&k3yQxnAWcTAw%u>sz3 z0p1A#-iZO;{Q|s`0=%XG@8kgQlmPG40PnN_@ALrgi~w&%fOmF)cTRv;4Dc!eo}wgX zkB&gO&H(R%0FU61%P|~F=C8Gar&;u;TAn^Kw|bm`qYl!kEY%Gls?A0zBRXfEa~obi zT&(bw`s7MxzpwVaSCOwS(VR%lyU)2?0LH-goly-HgWuf`%TAeChy#v-bS1W2Muv9#2ai8huX^UI(0S8FH>Y7il%aAvfL99efDyf@vSOWD8K|lz zM@tkX@I2~EsHcM^?J`Rn z!&eRukBr`87+cUXjZtWsviz2rWNWH#MZ2^t@S-fFA!!lyzT(6C&23s@YV!)tj1c0C~-Jo1sL}-n)1G9eEjY=8odtMVJ8dd9U3mOdt5FO zj1T7Q)gVDxfMv5S1&`^oER@oVu(Mnt7n$Q+1m309m35|N!O;szmZmL?p3pj##Z4J4 zwzYBCz7iVKd46vflw+^b+tueN%m`>RqIN)lY9}T@C+7(Pt&I7dq3TFe_VPY%Mq4>y zTotN~o}xB*rp;yt90m7+`TJ@SF^~SdLvXkF#SZS4St&5Ejw9gyXW3GSJ7vqln4~qy zTA5_&1Qq@Rmi9zJ1D`Pc$;tD6xK&`44rBf2Sn&C!j< z5VZ7o+aIvnEencJ7KTL1f>Jf6fTbY?tP8AouOnM)-J*wUp$EMP^iUfg|K4@u;~!j_ zj0&SPe&?ug9VBQDM08h{@1?Yg&v|i|R5y6nvS`4`+J5zWoz6gG%7VFdhJ%i4vO-1U z6SM@lj>l?c2Ho}Oj*b-29cB65VIfx9ovl#=*7?hWhFac7D9)2j&8qV*Un*xAW54BMXGSHq-nbNVh(Q>v4_x~ zS^>(`Fal603ux-J?LjGJp_IlSl){Kc@vE^FrNB}IV2Gm?!O~I~^k^xtv=l4FjAA%1 z-Xi)ifje)z1$`(B$UDK7!q7pNY~d#uhG$0{l|#?iJU$2dIPyB*b0R5hq9 zA3me4oO>P+s;xSU)m9!izHfA7kFM7|P-K|3-otDM;13!l;N}|m;3CRG%Eny`?agsk zJUm~03$ipk;)?2Sa3p2HYjjZuvefLTsAfkabfOQIF3Z5|V7baM3QJT+|3N}GF5;+Ql)v}S({}VIR%xOHa+&G&e&Av#_$WhIxM4ChePRD8S509AR$ZJ2-ZsL`vDeQxWkqLtJku;{*H=! za5#Jz?6BAthaI#VxHP-RXsJ}-81!)1K+D1@lm%?77GM^Z*wH<7^A*>R?Afz(hXF)| z0r3blZk{$yV}i2w?Q-1JM?#t^9&J@=zRMMzhLt&TKT1TI;Sszy*|6B~NZlsJ)2c9; zuM2bhXtY}!2|rgMzL85s3G|PV>L#k_P!8Qz-$mZiQeLx0OT{+E$YUY#tfW~~A{wNn zz~YX|oRCLwj}w_@zWi{SH9dsp7I!(gQ?Y2(B71SLbRL8&X?M^=Z4X#&Ru%xOEO@W7 zfMEq0Sll;)NHas^@i3oaG@yT6M5-5?Ifk>sp8yf627pvq36PdscrE3LQr+AfgX3!^ zQjkI!%ah8`iqMaSDzH{2D}tq0T$?Nvsf^x(!$>RJoMSyWsRW}^f3OL&| zVN-7PIB(wQ&*eI{lUSEKKnou4OmNrda*N-c;0}(Df9LcBcfLs^M-uo$Dw7X$>LCAww?IGRed-oh#Ng{VCHA>@sQ;I7K*?$c1i zwQ2UxT6mFEH=#hw0xrq|?sek`;tdNl58T?N;1{D!V=~-6?R`d%dRIVK&%7xPeGbsd zcnM@^X(;7Vaj_piD`_4XesGe0smL(H{zr_DzrQCj{FrAohP1QDvJhf*2#pcR@wOBc zqcIW{l?7cX3q99mW{Ah|Lx-Ol)IB$l?(*dSWzt;}xgI$_{+X{Nx~r)OSJI9k@95A9 zSJI&sSlSU(R2IbR92w&%U5^5b9Vj`au^YSsB9>UY4fbwR z)ha~MJ8scv>p;(%9*Wnw+$%+dfr+kAz#Fv{5CEUi%ZSWkxyX%rl}I#`4XqB`Dht|G zOF_Fj(t-Q(MQB1DwcX6RTKIaeh7weGK#zWu68GYn)@ww9aj!>>kN^C)3HQ<#LJjIT z82o5f1`A%I%F;nKWa-i=90$In6@e2s;K{ybyIN7=vBGQ7BW(g~pg6$XQEx+lb&mBY zuymOREUYN0pK1?Lsxv7|yMt2VNA?y6&jns59dWmIsY)~zLgP9XL;O+=z~!_(&^TY5 zk_YSW^>SI`!!vBtfeK~eva4+=SQRYSUUUs!pn5~-8d?6GjN@0n;2WO)vF}dY)Jq|sW(ADtgzl0p97(q1EmG6+{rhGs;m7}q7Tl|RyM<1 zLbX*NvD(UudS8~?`fo*joxdP7D9gWk7uHaWytj!I6C$+=oIzR0jv5;f(4<}b?qV~( zl1&3|NAu25J*sk)Ks?-P!;36Nb4KJx zrM8J)vush|P+91#1~jNd)2-K9x&{yOK8EhAKp00^Fpdhuuz|a8?uW9(kE72zos5A_ zMJ7N;0(e^U2?&T4*4!FHvX@&0^q&k>SL3V11Zw5tp9^-iifFFAhV1rR`A`+N0_Q ztJ{kAvY*)<$b*Qlz*;I1*3ztth%MGO`!qQ}eHHc9r{M1J7F8|Rk9?ISd`%=69NuDV zJwE=$qGM~7i$17as7TsnypW}S9qrP>=+}1f!eax=$_ztx!f!x?uDk<=T~@PU7_x+K ziUgA(ZMEyeDg^yd7Cc+84!feae4%flsahYsy+V51QB7iwd&}YQ+Yq7GgCW(A z!o6h)-$8G0liuD{a(b&m&|77Ndh7ZOM;N})chOX>kKR%gHcREF&q(Pl&mq1C5jq5e zZ58X`-m--6iv$y5ZI}rkILZEY2uPuMXSl)uASso3H%?v|bBC0Xswir4v#V zz}fSM5TQ+gxqJ8S+$`ZoBEdNK14IEomUkuOR*&;tD3uG`s<{yD^irYT@`ZkkrfOmI zcBk}qbxX3h{XN~XT>2A{U_#8{wrA+<5tfBU9dB7)+@t&LEgUv~iZ*Fk3}KYzjcU#3 z4b4J=JU;L<$k2s6^h;ToJc$>W(8~kSpQHXt+g|vvu0@7@m?iu|Bp4GuP)zv40mp|` zF1%CY3$&$|3Ym~E^h-2V3!|%7i3uwwCQUe6tP~jYcZ&pL!c%Q$AwgNO(cWpc7~GE) z=sx<)&HI%IH`_H;68z(2D+n>_6lH0Q0!y*23$K`q=)EIoPa4%KOTfQ|qEsNdsjOHx z1AXFo&OPXpRzshZ1(Rvd!CGp&2_MuBfTf$EeQ&4R`<#n^1KVMYp;|gbFQU5CnY{-; zeo;%GnF5q~!1Y^b>o_X~+ESLUtw;;0+wDK9R z#Js)Id+dyd4s3=$LBw)ZfZA7MHX6zb;3jbWKcl`DMiZ`)CY+j2Hes|_=KV_?A^sv# zOfb{T11UNmgd)zcZAFCCiogK3byRLz{S^(>%D9BGyvlU@%S;f5jHJIog62ZRY?a_6 zsmMv^?^4->sb<^ukh`nuby*6k*TFRKtFvF|LB)FjG}8tif&2r?*6PrNUKh&NQc#XA z)u45vY?`6-sP><75fk%OV(20oH}tj^dLk0--6nmgoxT#Ir ztn*blYIhwg!IL!iqNOCqJj4`#@rfB<=4Xm*11lXfpnaPC;mevSW9vXmY^#v#wFz)} z&7NSHM&%5yOsdS!g08eW45%zWK5*UHsH+PNsH-fmuDdQ=Vo7r#Nh2bh;4s@&Z(Vq_ zSm42NzCo&+NUYjJLzIPvsQsX09aJPVWwKVjQ7&OZLzit1E}`iX@-$t7MRi&8{2qz? zJoH(sha{@gMb(R~CIaN=qd|uz8>GsIH|l;;1mZ{{?ddfV7ob5aRia*9B_{M!=GjI5 z5LCZFt7|yX>Tp-NdXd$;5S8^V792o*!qcU>F<>HWevwo+4lvhV8;DXCl%Wz41T+Pq z6t|G$3gh-rG_p5&6?F?wzg*u8JMxF2z6ML=Vy%xR@%2q7**=G(la0yCD+|rn9>MWd zxnSu}mjz)d>fht7ndv+WxMy)>v)pY|CF0U-_@+M+)=Z{5o z9e$wm%JN}a;ejhlI1Uo@E;1UR5HMd0aCrfRk**Ug0@TDy1Oxpv@sJ?thY~?_43L2>L zpjl=4Q{mB8hR~^@+N#=EZRJr{D0voJ`L<;KG}Kq8fO?dL4s!KqVnlE2Bpsa&5gJ6G zBNgFkn4>wP=nT}?AvnBOMf%#SmRNmDP+JFCxVo~i48|QWL4X73QdHN03;M4k9x6;ir zZjncRMTj}xf*S@0U#T!2T2TM+q)L_L*T<9249Y5`=t3q`d5jh8 zsWNF7o)Wc+Ff-v;W@|#24i+H{5y#yHCqd7A?VW;N8=9yh5O#C{({o_#r#3R$A!Ctk z8DzlLs(*H4lA({B8YwH$zlBLDM_Cp^kPa}wV!@-;GP}^ZXco|=ZBUjM8>lwhZWU^; zu-8VXl;zi^c+7$2JXFVWfd&SR$BArDBU+=3)u^ruS{t% zSC$vnMtPjlfx0?w57hNrUM+L<=tS)f+e(Bqs7>u)O~%*m3f0!4D$rMYmERvrAE?*& zdtZ>eHfpOtdu_H@PpGyQRe{NCv%z{%Tm2IKMr{>nug%zA6RNF6RiJn6=m{g9O0Iblv(@Y`$5LY?ja(>&}6sqqs=ETa!Hv^4r~iLC$q>P^Y@zfs5wq3jmE}Kq zH7e^D>q50v2eI196BSCn=|^pyC%|i!mAE!<$;%IfYU_1kwUx)$rqMM!{d%cxLbH}d ztWXx?oPT*x!jU>(@w9zRw9zu$`#?#qRcV(srr*+MrCSL{U!yTwJ2Vtv4svUPm?9vYpb_K4l{Vo0%m z;7Zv>FRNU(7b$GqOCZJif-B|1@$p|R*^3m0>!pxVi(ZK5O1X&Mph0&sLp`EBB7Ey4 ze;I@vk#v-c$HzY~Kjqem`9_n-7#10GDVjW1?&F^EekTnqu#yps)PrNME!B__<0*V% zJcV_Pw^lEqv7dt*fAC0}dAT&xyawZOlCAE!+G(b)V8`UDQqXj;^isOo7ORO{j`%Kz zF8IdEY1WJJR@&agc-q4lkGshC^#`So+hNWpj*s6;=J0mF>cH4vFX92k6{xNYF9;hL z!fD4v$5md{W7obC5_IeX32JpO1<{f~k>kz|RM*`QsIC&RJ|qn&(V{B-mES4VO-|I& z4<>*bNKw6P6`g1h&B-pIY2i7Yo9X)F^n;e^ogj!-mOnWgEs3CFNRUoBAV^thf=VGl P$JlN_kg|M1ci#E`(tLfn literal 0 HcmV?d00001 diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvho.sdf b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvho.sdf new file mode 100644 index 0000000..f178e30 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvho.sdf @@ -0,0 +1,3176 @@ +(DELAYFILE + (SDFVERSION "3.0") + (DESIGN "RAM2GS") + (DATE "Tue Aug 15 05:03:31 2023") + (VENDOR "Lattice") + (PROGRAM "ldbanno") + (VERSION "Diamond (64-bit) 3.12.1.454") + (DIVIDER /) + (VOLTAGE 1.26:1.20:1.14) + (PROCESS "default") + (TEMPERATURE -40:25:85) + (TIMESCALE 1ps) + (CELL + (CELLTYPE "SLICE_0") + (INSTANCE SLICE_0I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_1") + (INSTANCE SLICE_1I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_2") + (INSTANCE SLICE_2I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_3") + (INSTANCE SLICE_3I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_4") + (INSTANCE SLICE_4I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_5") + (INSTANCE SLICE_5I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_6") + (INSTANCE SLICE_6I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_7") + (INSTANCE SLICE_7I) + (DELAY + (ABSOLUTE + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_8") + (INSTANCE SLICE_8I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_9") + (INSTANCE SLICE_9I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_10") + (INSTANCE SLICE_10I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_15") + (INSTANCE SLICE_15I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_16") + (INSTANCE SLICE_16I) + (DELAY + (ABSOLUTE + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_19") + (INSTANCE SLICE_19I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_20") + (INSTANCE SLICE_20I) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_24") + (INSTANCE SLICE_24I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_25") + (INSTANCE SLICE_25I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_26") + (INSTANCE SLICE_26I) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_27") + (INSTANCE SLICE_27I) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_30") + (INSTANCE SLICE_30I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_32") + (INSTANCE SLICE_32I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_33") + (INSTANCE SLICE_33I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_35") + (INSTANCE SLICE_35I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_36") + (INSTANCE SLICE_36I) + (DELAY + (ABSOLUTE + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_37") + (INSTANCE SLICE_37I) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_44") + (INSTANCE SLICE_44I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_45") + (INSTANCE SLICE_45I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_50") + (INSTANCE SLICE_50I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_57") + (INSTANCE SLICE_57I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_59") + (INSTANCE SLICE_59I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_61") + (INSTANCE SLICE_61I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_62") + (INSTANCE SLICE_62I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_64") + (INSTANCE SLICE_64I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_65") + (INSTANCE SLICE_65I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_66") + (INSTANCE SLICE_66I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_67") + (INSTANCE SLICE_67I) + (DELAY + (ABSOLUTE + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_68") + (INSTANCE SLICE_68I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_69") + (INSTANCE SLICE_69I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_70") + (INSTANCE SLICE_70I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "i30_SLICE_71") + (INSTANCE i30_SLICE_71I) + (DELAY + (ABSOLUTE + (IOPATH C1 OFX0 (457:589:721)(457:589:721)) + (IOPATH B1 OFX0 (457:589:721)(457:589:721)) + (IOPATH A1 OFX0 (457:589:721)(457:589:721)) + (IOPATH D0 OFX0 (457:589:721)(457:589:721)) + (IOPATH C0 OFX0 (457:589:721)(457:589:721)) + (IOPATH B0 OFX0 (457:589:721)(457:589:721)) + (IOPATH A0 OFX0 (457:589:721)(457:589:721)) + (IOPATH M0 OFX0 (322:349:376)(322:349:376)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_72") + (INSTANCE SLICE_72I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_73") + (INSTANCE SLICE_73I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_74") + (INSTANCE SLICE_74I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_75") + (INSTANCE SLICE_75I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_76") + (INSTANCE SLICE_76I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_77") + (INSTANCE SLICE_77I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_78") + (INSTANCE SLICE_78I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_79") + (INSTANCE SLICE_79I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_80") + (INSTANCE SLICE_80I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_81") + (INSTANCE SLICE_81I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_82") + (INSTANCE SLICE_82I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_83") + (INSTANCE SLICE_83I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_84") + (INSTANCE SLICE_84I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_85") + (INSTANCE SLICE_85I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_86") + (INSTANCE SLICE_86I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_87") + (INSTANCE SLICE_87I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_88") + (INSTANCE SLICE_88I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_89") + (INSTANCE SLICE_89I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_90") + (INSTANCE SLICE_90I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_91") + (INSTANCE SLICE_91I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_92") + (INSTANCE SLICE_92I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_93") + (INSTANCE SLICE_93I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_94") + (INSTANCE SLICE_94I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_95") + (INSTANCE SLICE_95I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_96") + (INSTANCE SLICE_96I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_97") + (INSTANCE SLICE_97I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_98") + (INSTANCE SLICE_98I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_99") + (INSTANCE SLICE_99I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_100") + (INSTANCE SLICE_100I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_101") + (INSTANCE SLICE_101I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_102") + (INSTANCE SLICE_102I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_103") + (INSTANCE SLICE_103I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_104") + (INSTANCE SLICE_104I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_105") + (INSTANCE SLICE_105I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_106") + (INSTANCE SLICE_106I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_7_B") + (INSTANCE RD_7_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD7 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD7 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD7 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD7) (3330:3330:3330)) + (WIDTH (negedge RD7) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_6_B") + (INSTANCE RD_6_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD6 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD6 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD6 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD6) (3330:3330:3330)) + (WIDTH (negedge RD6) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_5_B") + (INSTANCE RD_5_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD5 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD5 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD5 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD5) (3330:3330:3330)) + (WIDTH (negedge RD5) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_4_B") + (INSTANCE RD_4_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD4 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD4 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD4 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD4) (3330:3330:3330)) + (WIDTH (negedge RD4) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_3_B") + (INSTANCE RD_3_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD3 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD3 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD3 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD3) (3330:3330:3330)) + (WIDTH (negedge RD3) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_2_B") + (INSTANCE RD_2_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD2 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD2 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD2 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD2) (3330:3330:3330)) + (WIDTH (negedge RD2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_1_B") + (INSTANCE RD_1_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD1 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD1 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD1 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD1) (3330:3330:3330)) + (WIDTH (negedge RD1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_0_B") + (INSTANCE RD_0_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD0 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD0 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD0 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD0) (3330:3330:3330)) + (WIDTH (negedge RD0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Dout_7_B") + (INSTANCE Dout_7_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout7 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_6_B") + (INSTANCE Dout_6_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout6 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_5_B") + (INSTANCE Dout_5_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout5 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_4_B") + (INSTANCE Dout_4_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout4 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_3_B") + (INSTANCE Dout_3_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout3 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_2_B") + (INSTANCE Dout_2_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout2 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_1_B") + (INSTANCE Dout_1_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout1 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_0_B") + (INSTANCE Dout_0_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout0 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "LEDB") + (INSTANCE LEDI) + (DELAY + (ABSOLUTE + (IOPATH PADDO LEDS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_1_B") + (INSTANCE RBA_1_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RBA1 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_0_B") + (INSTANCE RBA_0_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RBA0 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_11_B") + (INSTANCE RA_11_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA11 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_10_B") + (INSTANCE RA_10_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA10 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_9_B") + (INSTANCE RA_9_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA9 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_8_B") + (INSTANCE RA_8_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA8 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_7_B") + (INSTANCE RA_7_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA7 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_6_B") + (INSTANCE RA_6_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA6 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_5_B") + (INSTANCE RA_5_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA5 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_4_B") + (INSTANCE RA_4_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA4 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_3_B") + (INSTANCE RA_3_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA3 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_2_B") + (INSTANCE RA_2_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA2 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_1_B") + (INSTANCE RA_1_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA1 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_0_B") + (INSTANCE RA_0_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA0 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nRCSB") + (INSTANCE nRCSI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRCSS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RCKEB") + (INSTANCE RCKEI) + (DELAY + (ABSOLUTE + (IOPATH PADDO RCKES (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nRWEB") + (INSTANCE nRWEI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRWES (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nRRASB") + (INSTANCE nRRASI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRRASS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nRCASB") + (INSTANCE nRCASI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRCASS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RDQMHB") + (INSTANCE RDQMHI) + (DELAY + (ABSOLUTE + (IOPATH PADDO RDQMHS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RDQMLB") + (INSTANCE RDQMLI) + (DELAY + (ABSOLUTE + (IOPATH PADDO RDQMLS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nUFMCSB") + (INSTANCE nUFMCSI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nUFMCSS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "UFMCLKB") + (INSTANCE UFMCLKI) + (DELAY + (ABSOLUTE + (IOPATH PADDO UFMCLKS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "UFMSDIB") + (INSTANCE UFMSDII) + (DELAY + (ABSOLUTE + (IOPATH PADDO UFMSDIS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "PHI2B") + (INSTANCE PHI2I) + (DELAY + (ABSOLUTE + (IOPATH PHI2S PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge PHI2S) (3330:3330:3330)) + (WIDTH (negedge PHI2S) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_9_B") + (INSTANCE MAin_9_I) + (DELAY + (ABSOLUTE + (IOPATH MAin9 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin9) (3330:3330:3330)) + (WIDTH (negedge MAin9) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_8_B") + (INSTANCE MAin_8_I) + (DELAY + (ABSOLUTE + (IOPATH MAin8 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin8) (3330:3330:3330)) + (WIDTH (negedge MAin8) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_7_B") + (INSTANCE MAin_7_I) + (DELAY + (ABSOLUTE + (IOPATH MAin7 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin7) (3330:3330:3330)) + (WIDTH (negedge MAin7) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_6_B") + (INSTANCE MAin_6_I) + (DELAY + (ABSOLUTE + (IOPATH MAin6 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin6) (3330:3330:3330)) + (WIDTH (negedge MAin6) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_5_B") + (INSTANCE MAin_5_I) + (DELAY + (ABSOLUTE + (IOPATH MAin5 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin5) (3330:3330:3330)) + (WIDTH (negedge MAin5) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_4_B") + (INSTANCE MAin_4_I) + (DELAY + (ABSOLUTE + (IOPATH MAin4 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin4) (3330:3330:3330)) + (WIDTH (negedge MAin4) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_3_B") + (INSTANCE MAin_3_I) + (DELAY + (ABSOLUTE + (IOPATH MAin3 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin3) (3330:3330:3330)) + (WIDTH (negedge MAin3) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_2_B") + (INSTANCE MAin_2_I) + (DELAY + (ABSOLUTE + (IOPATH MAin2 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin2) (3330:3330:3330)) + (WIDTH (negedge MAin2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_1_B") + (INSTANCE MAin_1_I) + (DELAY + (ABSOLUTE + (IOPATH MAin1 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin1) (3330:3330:3330)) + (WIDTH (negedge MAin1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_0_B") + (INSTANCE MAin_0_I) + (DELAY + (ABSOLUTE + (IOPATH MAin0 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin0) (3330:3330:3330)) + (WIDTH (negedge MAin0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "CROW_1_B") + (INSTANCE CROW_1_I) + (DELAY + (ABSOLUTE + (IOPATH CROW1 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW1) (3330:3330:3330)) + (WIDTH (negedge CROW1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "CROW_0_B") + (INSTANCE CROW_0_I) + (DELAY + (ABSOLUTE + (IOPATH CROW0 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW0) (3330:3330:3330)) + (WIDTH (negedge CROW0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_7_B") + (INSTANCE Din_7_I) + (DELAY + (ABSOLUTE + (IOPATH Din7 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din7) (3330:3330:3330)) + (WIDTH (negedge Din7) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_6_B") + (INSTANCE Din_6_I) + (DELAY + (ABSOLUTE + (IOPATH Din6 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din6) (3330:3330:3330)) + (WIDTH (negedge Din6) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_5_B") + (INSTANCE Din_5_I) + (DELAY + (ABSOLUTE + (IOPATH Din5 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din5) (3330:3330:3330)) + (WIDTH (negedge Din5) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_4_B") + (INSTANCE Din_4_I) + (DELAY + (ABSOLUTE + (IOPATH Din4 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din4) (3330:3330:3330)) + (WIDTH (negedge Din4) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_3_B") + (INSTANCE Din_3_I) + (DELAY + (ABSOLUTE + (IOPATH Din3 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din3) (3330:3330:3330)) + (WIDTH (negedge Din3) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_2_B") + (INSTANCE Din_2_I) + (DELAY + (ABSOLUTE + (IOPATH Din2 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din2) (3330:3330:3330)) + (WIDTH (negedge Din2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_1_B") + (INSTANCE Din_1_I) + (DELAY + (ABSOLUTE + (IOPATH Din1 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din1) (3330:3330:3330)) + (WIDTH (negedge Din1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_0_B") + (INSTANCE Din_0_I) + (DELAY + (ABSOLUTE + (IOPATH Din0 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din0) (3330:3330:3330)) + (WIDTH (negedge Din0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nCCASB") + (INSTANCE nCCASI) + (DELAY + (ABSOLUTE + (IOPATH nCCASS PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nCCASS) (3330:3330:3330)) + (WIDTH (negedge nCCASS) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nCRASB") + (INSTANCE nCRASI) + (DELAY + (ABSOLUTE + (IOPATH nCRASS PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nCRASS) (3330:3330:3330)) + (WIDTH (negedge nCRASS) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nFWEB") + (INSTANCE nFWEI) + (DELAY + (ABSOLUTE + (IOPATH nFWES PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nFWES) (3330:3330:3330)) + (WIDTH (negedge nFWES) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RCLKB") + (INSTANCE RCLKI) + (DELAY + (ABSOLUTE + (IOPATH RCLKS PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RCLKS) (3330:3330:3330)) + (WIDTH (negedge RCLKS) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "UFMSDOB") + (INSTANCE UFMSDOI) + (DELAY + (ABSOLUTE + (IOPATH UFMSDOS PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge UFMSDOS) (3330:3330:3330)) + (WIDTH (negedge UFMSDOS) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RAM2GS") + (INSTANCE ) + (DELAY + (ABSOLUTE + (INTERCONNECT SLICE_0I/Q1 SLICE_0I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q1 SLICE_76I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q1 SLICE_80I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q1 SLICE_82I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q1 SLICE_85I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q0 SLICE_0I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q0 SLICE_85I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q0 SLICE_105I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/F1 SLICE_0I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/F0 SLICE_0I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_0I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_1I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_2I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_3I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_4I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_5I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_6I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_7I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_8I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_9I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_16I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_26I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_27I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_30I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_32I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_35I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_36I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_37I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_44I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_45I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_57I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_59I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_61I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_62I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_64I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_65I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_66I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_67I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_68I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_69I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_70I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_75I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_78I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_79I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_81I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_84I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_86I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_97I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_98I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_106I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/FCO SLICE_0I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/FCO SLICE_9I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q1 SLICE_1I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q1 SLICE_76I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q1 SLICE_80I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q1 SLICE_85I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q1 SLICE_105I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_1I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_57I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_70I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_76I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_80I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_82I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_85I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_105I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/F1 SLICE_1I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/F0 SLICE_1I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/FCO SLICE_1I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q1 SLICE_2I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q1 SLICE_45I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q1 SLICE_68I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q0 SLICE_2I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q0 SLICE_95I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q0 SLICE_95I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/F1 SLICE_2I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/F0 SLICE_2I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/FCO SLICE_2I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/FCO SLICE_6I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q1 SLICE_3I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q1 SLICE_86I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q1 SLICE_105I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q0 SLICE_3I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q0 SLICE_95I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q0 SLICE_95I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/F1 SLICE_3I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/F0 SLICE_3I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/FCO SLICE_3I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q1 SLICE_4I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q1 SLICE_95I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q0 SLICE_4I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q0 SLICE_44I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q0 SLICE_95I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/F1 SLICE_4I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/F0 SLICE_4I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/FCO SLICE_4I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/FCO SLICE_8I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_5I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_68I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/F1 SLICE_5I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16I/Q1 SLICE_5I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16I/Q1 SLICE_66I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16I/Q1 SLICE_96I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q0 SLICE_96I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q0 SLICE_96I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q1 SLICE_6I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q1 SLICE_45I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q1 SLICE_57I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q1 SLICE_70I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q1 SLICE_76I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q1 SLICE_82I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q0 SLICE_6I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q0 SLICE_86I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q0 SLICE_95I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/F1 SLICE_6I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/F0 SLICE_6I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q0 SLICE_7I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q0 SLICE_82I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q0 SLICE_85I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/F0 SLICE_7I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/FCO SLICE_7I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q1 SLICE_8I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q1 SLICE_44I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q1 SLICE_86I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q0 SLICE_8I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q0 SLICE_86I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/F1 SLICE_8I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/F0 SLICE_8I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/Q1 SLICE_9I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/Q1 SLICE_85I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/Q1 SLICE_105I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/Q0 SLICE_9I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/Q0 SLICE_85I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/Q0 SLICE_105I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/F1 SLICE_9I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/F0 SLICE_9I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_10I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_24I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_33I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_50I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_89I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_89I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_89I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_90I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_102I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_106I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_10I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_24I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_33I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_33I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_75I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_77I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_88I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_101I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_10I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_50I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_90I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_90I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_90I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_93I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_100I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_10I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_24I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_33I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_88I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_90I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_90I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_101I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106I/F1 SLICE_10I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_10I/F1 SLICE_10I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/F0 SLICE_10I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_10I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_73I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_10I/F0 SLICE_10I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F0 SLICE_10I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/F0 SLICE_10I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/F0 SLICE_15I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/F0 SLICE_88I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_10I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_15I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_19I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_20I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_24I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_33I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_50I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_86I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_93I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_99I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_100I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_101I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_102I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_103I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_10I/Q0 SLICE_88I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F1 SLICE_15I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F1 SLICE_73I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F1 SLICE_74I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F1 SLICE_79I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F1 SLICE_83I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F1 SLICE_91I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F1 SLICE_91I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F1 SLICE_104I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_5_I/PADDI SLICE_15I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_5_I/PADDI SLICE_79I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_5_I/PADDI SLICE_82I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_5_I/PADDI SLICE_101I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99I/F1 SLICE_15I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99I/F1 SLICE_79I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_2_I/PADDI SLICE_15I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_2_I/PADDI SLICE_79I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_2_I/PADDI SLICE_91I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_2_I/PADDI SLICE_103I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_15I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_19I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_73I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_74I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_79I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_83I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_91I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_91I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_97I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_102I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_15I/Q0 SLICE_15I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_15I/Q0 SLICE_77I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_15I/F1 SLICE_15I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_15I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_25I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_25I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_74I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_79I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_104I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_104I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_106I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_15I/F0 SLICE_15I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_16I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_88I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_89I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_90I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_92I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_104I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16I/F0 SLICE_16I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16I/F0 SLICE_25I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16I/Q0 SLICE_16I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97I/F0 SLICE_19I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_19I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_24I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_25I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_75I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_77I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_89I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_89I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_89I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_102I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77I/F0 SLICE_19I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77I/F0 SLICE_77I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/F0 SLICE_19I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/F0 SLICE_75I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19I/F1 SLICE_19I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90I/F1 SLICE_19I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90I/F1 SLICE_77I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F0 SLICE_19I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F0 SLICE_88I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19I/F0 SLICE_19I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/F1 SLICE_19I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19I/Q0 SLICE_73I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19I/Q0 SLICE_83I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_20I/F0 SLICE_20I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89I/F1 SLICE_20I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_20I/Q0 SLICE_35I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_20I/Q0 SLICE_84I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24I/F1 SLICE_24I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24I/F1 SLICE_50I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24I/F1 SLICE_83I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57I/Q0 SLICE_24I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57I/Q0 SLICE_33I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_24I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_50I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_90I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_90I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_90I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_93I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_99I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_106I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24I/F0 SLICE_24I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89I/F0 SLICE_24I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24I/Q0 SLICE_57I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_25I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_50I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_75I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_77I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_89I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_89I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_92I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_103I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F0 SLICE_25I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_25I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_30I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_30I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_74I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_76I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_82I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_87I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_91I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_104I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_65I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 i30_SLICE_71I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 i30_SLICE_71I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_81I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_96I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q1 SLICE_30I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q1 SLICE_59I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q1 i30_SLICE_71I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q1 i30_SLICE_71I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q1 SLICE_81I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q1 SLICE_96I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q1 SLICE_96I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/F0 SLICE_26I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/F0 SLICE_26I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_32I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_35I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_35I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_44I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_45I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_57I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_62I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_70I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_70I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_72I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_76I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_80I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_84I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_92I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_92I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_27I/F0 SLICE_27I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/F0 SLICE_27I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_27I/Q0 SLICE_30I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_27I/Q0 SLICE_50I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/F0 SLICE_30I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q0 SLICE_30I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q0 SLICE_36I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/F1 LEDI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_32I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_36I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_59I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_61I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_62I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_66I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_67I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_69I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_69I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 i30_SLICE_71I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_72I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_78I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_86I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_92I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_92I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_32I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_59I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_61I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_62I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_62I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_68I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 i30_SLICE_71I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_78I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_87I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_92I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_92I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_94I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_94I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q1 SLICE_32I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q1 SLICE_59I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q1 SLICE_64I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q1 SLICE_84I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_32I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_33I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_35I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_59I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_61I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_62I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_64I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_72I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_74I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_76I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_82I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_87I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_87I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_91I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_92I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_94I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_94I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_104I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32I/F1 SLICE_32I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 SLICE_32I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 SLICE_62I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 SLICE_92I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 SLICE_98I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32I/F0 SLICE_32I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/Q1 SLICE_32I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/Q1 SLICE_64I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/Q1 SLICE_79I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32I/Q0 RA_10_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_50I/Q0 SLICE_33I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_33I/F0 SLICE_33I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_33I/Q0 RA_11_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_33I/F1 SLICE_73I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q1 SLICE_35I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q1 SLICE_69I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q1 SLICE_84I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q1 SLICE_35I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q1 SLICE_84I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT i30_SLICE_71I/OFX0 SLICE_35I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/F0 SLICE_35I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/F1 SLICE_35I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/F1 SLICE_59I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/F1 SLICE_61I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/F1 SLICE_62I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/Q0 SLICE_36I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/F1 SLICE_44I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/F1 SLICE_45I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/F1 SLICE_70I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/Q1 SLICE_36I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/F0 SLICE_36I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/Q0 SLICE_36I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_61I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_69I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_78I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 RCKEI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/F0 SLICE_37I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_72I/F1 SLICE_37I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/F1 SLICE_44I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/F1 SLICE_44I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/F1 SLICE_70I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/F1 SLICE_82I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100I/Q0 SLICE_44I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44I/F1 SLICE_44I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44I/F0 SLICE_44I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/F0 SLICE_44I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/F0 SLICE_45I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44I/Q0 UFMCLKI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/F0 SLICE_45I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/F0 SLICE_57I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/F0 SLICE_76I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/F0 SLICE_80I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/F0 SLICE_85I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95I/F1 SLICE_45I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 SLICE_45I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99I/Q0 SLICE_45I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_45I/F1 SLICE_45I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_45I/F0 SLICE_45I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_45I/Q0 UFMSDII/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_50I/F1 SLICE_50I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_50I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_77I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_88I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_92I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_97I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_100I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_103I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_106I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_50I/F0 SLICE_50I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83I/F1 SLICE_50I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/F1 SLICE_57I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/F1 SLICE_80I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/F1 SLICE_95I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT UFMSDOI/PADDI SLICE_57I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57I/F1 SLICE_57I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57I/F1 SLICE_84I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57I/F0 SLICE_57I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84I/F0 SLICE_57I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/F0 SLICE_59I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/F0 SLICE_61I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_59I/F1 SLICE_59I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F0 SLICE_59I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F0 SLICE_64I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_59I/F0 SLICE_59I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_59I/Q0 nRCASI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61I/F1 SLICE_61I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62I/F1 SLICE_61I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62I/F1 SLICE_62I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61I/F0 SLICE_61I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61I/Q0 nRCSI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/F1 SLICE_62I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62I/F0 SLICE_62I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62I/Q0 nRRASI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/F1 SLICE_64I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/F1 SLICE_64I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/F0 SLICE_64I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94I/F0 SLICE_64I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94I/F0 SLICE_65I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 nRWEI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_65I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_67I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 i30_SLICE_71I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_81I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_87I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_65I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_66I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_66I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_81I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_87I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96I/F1 SLICE_65I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/F1 SLICE_65I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/F1 SLICE_78I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/F1 SLICE_94I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94I/F1 SLICE_65I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/F0 SLICE_65I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_93I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_93I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_98I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_98I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_99I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_100I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_101I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_101I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_102I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_102I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_103I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_103I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_66I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_67I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_72I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_87I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_94I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/F0 SLICE_66I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/F1 i30_SLICE_71I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/F0 SLICE_67I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/F0 SLICE_68I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103I/Q1 SLICE_68I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101I/Q0 SLICE_68I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/F0 SLICE_74I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/F1 SLICE_86I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/F0 SLICE_69I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/F1 SLICE_70I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/F1 SLICE_76I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100I/Q1 SLICE_70I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_70I/F1 SLICE_70I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_70I/F0 SLICE_70I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_70I/Q0 nUFMCSI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_72I/F0 SLICE_72I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/Q1 SLICE_72I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/Q1 SLICE_98I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73I/F0 SLICE_73I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73I/F0 SLICE_74I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F1 SLICE_73I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F1 SLICE_74I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F1 SLICE_79I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F1 SLICE_83I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F1 SLICE_91I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F1 SLICE_91I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F1 SLICE_104I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_73I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_74I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_77I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_83I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_88I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_91I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_97I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_97I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_101I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73I/F1 SLICE_99I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73I/F1 SLICE_100I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102I/Q1 SLICE_74I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100I/F1 SLICE_74I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103I/Q0 SLICE_74I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F0 SLICE_89I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F0 SLICE_89I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_101I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q1 SLICE_102I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90I/F0 SLICE_75I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106I/F0 SLICE_75I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106I/F0 SLICE_83I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/Q0 SLICE_75I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97I/Q1 SLICE_75I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F1 SLICE_75I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F1 SLICE_78I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F1 SLICE_79I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F1 SLICE_81I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F1 SLICE_84I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F1 SLICE_97I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F1 SLICE_98I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F1 SLICE_106I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/F1 SLICE_88I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_9_I/PADDI SLICE_76I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_9_I/PADDI SLICE_93I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_9_I/PADDI SLICE_93I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_9_I/PADDI SLICE_98I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_8_I/PADDI SLICE_76I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_8_I/PADDI SLICE_98I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/Q0 SLICE_98I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/Q1 SLICE_93I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77I/F1 SLICE_97I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/F0 SLICE_78I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96I/F0 SLICE_78I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96I/F0 SLICE_81I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/Q0 SLICE_78I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/Q1 SLICE_78I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/Q1 SLICE_81I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/Q0 SLICE_79I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/F1 SLICE_81I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/Q0 SLICE_81I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F0 SLICE_82I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_4_I/PADDI SLICE_82I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_4_I/PADDI SLICE_100I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_4_I/PADDI SLICE_102I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/Q0 SLICE_102I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/Q1 SLICE_101I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83I/F0 SLICE_83I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/F0 SLICE_84I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84I/F1 SLICE_84I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84I/Q0 SLICE_84I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84I/Q1 SLICE_106I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/F1 SLICE_86I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95I/F0 SLICE_86I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/F0 SLICE_87I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT CROW_1_I/PADDI SLICE_87I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT CROW_0_I/PADDI SLICE_87I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q0 RBA_0_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q1 RBA_1_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97I/F1 SLICE_88I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/F1 SLICE_88I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/Q0 RD_6_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/Q1 RD_7_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89I/Q0 RD_4_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89I/Q1 RD_5_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90I/Q0 RD_0_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90I/Q1 RD_1_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT MAin_3_I/PADDI SLICE_91I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_3_I/PADDI SLICE_99I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_3_I/PADDI SLICE_103I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/Q0 SLICE_103I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/Q1 SLICE_103I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/Q0 RD_2_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/Q1 RD_3_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93I/F0 RA_9_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93I/Q0 SLICE_100I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93I/F1 RDQMLI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93I/Q1 SLICE_99I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97I/Q0 SLICE_97I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106I/Q1 SLICE_97I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/F0 RA_8_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/F1 RDQMHI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102I/Q0 SLICE_99I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_7_I/PADDI SLICE_99I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_7_I/PADDI SLICE_99I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_7_I/PADDI SLICE_104I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/Q1 SLICE_99I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99I/F0 RA_7_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101I/Q1 SLICE_100I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_6_I/PADDI SLICE_100I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_6_I/PADDI SLICE_100I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_6_I/PADDI SLICE_104I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/Q0 SLICE_100I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100I/F0 RA_6_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101I/F0 RA_5_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101I/F1 RA_0_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102I/F0 RA_4_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102I/F1 RA_1_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103I/F0 RA_3_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103I/F1 RA_2_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F1 RD_7_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F1 RD_6_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F1 RD_5_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F1 RD_4_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F1 RD_3_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F1 RD_2_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F1 RD_1_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F1 RD_0_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106I/Q0 SLICE_106I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT RD_7_I/PADDI Dout_7_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_6_I/PADDI Dout_6_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_5_I/PADDI Dout_5_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_4_I/PADDI Dout_4_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_3_I/PADDI Dout_3_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_2_I/PADDI Dout_2_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_1_I/PADDI Dout_1_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_0_I/PADDI Dout_0_I/PADDO (0:0:0)(0:0:0)) + ) + ) + ) +) diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvho.vho b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvho.vho new file mode 100644 index 0000000..61a9bb6 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvho.vho @@ -0,0 +1,26387 @@ + +-- VHDL netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 + +-- ldbanno -n VHDL -o RAM2GS_LCMXO2_1200HC_impl1_mapvho.vho -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd +-- Netlist created on Tue Aug 15 05:03:26 2023 +-- Netlist written on Tue Aug 15 05:03:31 2023 +-- Design is for device LCMXO2-1200HC +-- Design is for package TQFP100 +-- Design is for performance grade 4 + +-- entity vmuxregsre + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity vmuxregsre is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre : ENTITY IS TRUE; + + end vmuxregsre; + + architecture Structure of vmuxregsre is + begin + INST01: FL1P3DX + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q); + end Structure; + +-- entity vcc + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity vcc is + port (PWR1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vcc : ENTITY IS TRUE; + + end vcc; + + architecture Structure of vcc is + begin + INST1: VHI + port map (Z=>PWR1); + end Structure; + +-- entity gnd + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity gnd is + port (PWR0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF gnd : ENTITY IS TRUE; + + end gnd; + + architecture Structure of gnd is + begin + INST1: VLO + port map (Z=>PWR0); + end Structure; + +-- entity ccu2B0 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity ccu2B0 is + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF ccu2B0 : ENTITY IS TRUE; + + end ccu2B0; + + architecture Structure of ccu2B0 is + begin + inst1: CCU2D + generic map (INIT0 => X"faaa", INIT1 => X"faaa", INJECT1_0 => "NO", + INJECT1_1 => "NO") + port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, + C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); + end Structure; + +-- entity SLICE_0 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_0 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_0"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_0 : ENTITY IS TRUE; + + end SLICE_0; + + architecture Structure of SLICE_0 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i14: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i13: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_15: ccu2B0 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_1 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_1 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_1"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_1 : ENTITY IS TRUE; + + end SLICE_1; + + architecture Structure of SLICE_1 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i12: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i11: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_13: ccu2B0 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_2 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_2 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_2"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_2 : ENTITY IS TRUE; + + end SLICE_2; + + architecture Structure of SLICE_2 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i8: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i7: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_9: ccu2B0 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_3 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_3 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_3"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_3 : ENTITY IS TRUE; + + end SLICE_3; + + architecture Structure of SLICE_3 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i6: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i5: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_7: ccu2B0 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_4 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_4 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_4"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_4 : ENTITY IS TRUE; + + end SLICE_4; + + architecture Structure of SLICE_4 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i2: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i1: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_3: ccu2B0 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity ccu20001 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity ccu20001 is + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF ccu20001 : ENTITY IS TRUE; + + end ccu20001; + + architecture Structure of ccu20001 is + begin + inst1: CCU2D + generic map (INIT0 => X"F000", INIT1 => X"0555", INJECT1_0 => "NO", + INJECT1_1 => "NO") + port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, + C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); + end Structure; + +-- entity SLICE_5 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_5 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_5"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; DI1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_5 : ENTITY IS TRUE; + + end SLICE_5; + + architecture Structure of SLICE_5 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu20001 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i0: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CASr3_384: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_1: ccu20001 + port map (A0=>GNDI, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>GNDI, S0=>open, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, DI1_dly, M0_dly, CLK_dly, Q0_out, F1_out, + Q1_out, FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_6 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_6 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_6"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_6 : ENTITY IS TRUE; + + end SLICE_6; + + architecture Structure of SLICE_6 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i10: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i9: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_11: ccu2B0 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity ccu20002 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity ccu20002 is + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF ccu20002 : ENTITY IS TRUE; + + end ccu20002; + + architecture Structure of ccu20002 is + begin + inst1: CCU2D + generic map (INIT0 => X"faaa", INIT1 => X"0000", INJECT1_0 => "NO", + INJECT1_1 => "NO") + port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, + C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); + end Structure; + +-- entity SLICE_7 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_7 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_7"; + + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_7 : ENTITY IS TRUE; + + end SLICE_7; + + architecture Structure of SLICE_7 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu20002 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i17: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_add_4_19: ccu20002 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>GNDI, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>open, + CO1=>open); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A0_ipd, DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_8 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_8 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_8"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_8 : ENTITY IS TRUE; + + end SLICE_8; + + architecture Structure of SLICE_8 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i4: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i3: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_5: ccu2B0 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_9 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_9 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_9"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_9 : ENTITY IS TRUE; + + end SLICE_9; + + architecture Structure of SLICE_9 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i16: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i15: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_17: ccu2B0 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut4 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut4 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut4 : ENTITY IS TRUE; + + end lut4; + + architecture Structure of lut4 is + begin + INST10: ROM16X1A + generic map (initval => X"0002") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40003 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40003 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40003 : ENTITY IS TRUE; + + end lut40003; + + architecture Structure of lut40003 is + begin + INST10: ROM16X1A + generic map (initval => X"2000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity vmuxregsre0004 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity vmuxregsre0004 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre0004 : ENTITY IS TRUE; + + end vmuxregsre0004; + + architecture Structure of vmuxregsre0004 is + begin + INST01: FL1P3IY + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q); + end Structure; + +-- entity inverter + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity inverter is + port (I: in Std_logic; Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF inverter : ENTITY IS TRUE; + + end inverter; + + architecture Structure of inverter is + begin + INST1: INV + port map (A=>I, Z=>Z); + end Structure; + +-- entity SLICE_10 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_10 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_10"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_10 : ENTITY IS TRUE; + + end SLICE_10; + + architecture Structure of SLICE_10 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40003 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + begin + i3_3_lut_4_lut: lut4 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_4_lut_adj_4: lut40003 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + ADSubmitted_407: vmuxregsre0004 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, + F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40005 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40005 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40005 : ENTITY IS TRUE; + + end lut40005; + + architecture Structure of lut40005 is + begin + INST10: ROM16X1A + generic map (initval => X"FF7F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40006 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40006 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40006 : ENTITY IS TRUE; + + end lut40006; + + architecture Structure of lut40006 is + begin + INST10: ROM16X1A + generic map (initval => X"E0F0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity vmuxregsre0007 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity vmuxregsre0007 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre0007 : ENTITY IS TRUE; + + end vmuxregsre0007; + + architecture Structure of vmuxregsre0007 is + begin + INST01: FL1P3JY + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q); + end Structure; + +-- entity SLICE_15 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_15 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_15"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_15 : ENTITY IS TRUE; + + end SLICE_15; + + architecture Structure of SLICE_15 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40005 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40006 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0007 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + begin + i13_2_lut_rep_16_4_lut: lut40005 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1110_2_lut_3_lut_4_lut: lut40006 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + C1Submitted_406: vmuxregsre0007 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40008 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40008 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40008 : ENTITY IS TRUE; + + end lut40008; + + architecture Structure of lut40008 is + begin + INST10: ROM16X1A + generic map (initval => X"5555") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_16 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_16 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_16"; + + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_16 : ENTITY IS TRUE; + + end SLICE_16; + + architecture Structure of SLICE_16 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40008 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2045: lut40008 + port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CASr2_383: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CASr_382: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, + Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40009 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40009 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40009 : ENTITY IS TRUE; + + end lut40009; + + architecture Structure of lut40009 is + begin + INST10: ROM16X1A + generic map (initval => X"C0CA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40010 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40010 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40010 : ENTITY IS TRUE; + + end lut40010; + + architecture Structure of lut40010 is + begin + INST10: ROM16X1A + generic map (initval => X"4000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_19 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_19 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_19"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_19 : ENTITY IS TRUE; + + end SLICE_19; + + architecture Structure of SLICE_19 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40009 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40010 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i26_4_lut: lut40009 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i2_3_lut_4_lut: lut40010 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CmdEnable_405: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40011 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40011 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40011 : ENTITY IS TRUE; + + end lut40011; + + architecture Structure of lut40011 is + begin + INST10: ROM16X1A + generic map (initval => X"FFFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_20 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_20 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_20"; + + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_20 : ENTITY IS TRUE; + + end SLICE_20; + + architecture Structure of SLICE_20 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40011 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + n2447_001_BUF1_BUF1: lut40011 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CmdSubmitted_411: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0 <= F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40012 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40012 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40012 : ENTITY IS TRUE; + + end lut40012; + + architecture Structure of lut40012 is + begin + INST10: ROM16X1A + generic map (initval => X"FEFE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40013 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40013 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40013 : ENTITY IS TRUE; + + end lut40013; + + architecture Structure of lut40013 is + begin + INST10: ROM16X1A + generic map (initval => X"CC5C") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_24 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_24 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_24"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_24 : ENTITY IS TRUE; + + end SLICE_24; + + architecture Structure of SLICE_24 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40012 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40013 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_3_lut_adj_15: lut40012 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + Cmdn8MEGEN_I_93_4_lut: lut40013 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + Cmdn8MEGEN_410: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40014 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40014 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40014 : ENTITY IS TRUE; + + end lut40014; + + architecture Structure of lut40014 is + begin + INST10: ROM16X1A + generic map (initval => X"4040") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_25 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_25 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_25"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_25 : ENTITY IS TRUE; + + end SLICE_25; + + architecture Structure of SLICE_25 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40008 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40014 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_3_lut: lut40014 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_1_lut_rep_24: lut40008 + port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + CBR_390: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + FWEr_389: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, A0_ipd, DI0_dly, M1_dly, + CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_26 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_26 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_26"; + + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_26 : ENTITY IS TRUE; + + end SLICE_26; + + architecture Structure of SLICE_26 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40011 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + n2447_000_BUF1_BUF1: lut40011 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + InitReady_394: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0 <= F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_27 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_27 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_27"; + + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_27 : ENTITY IS TRUE; + + end SLICE_27; + + architecture Structure of SLICE_27 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40011 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + m1_lut: lut40011 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + LEDEN_419: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0 <= F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40015 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40015 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40015 : ENTITY IS TRUE; + + end lut40015; + + architecture Structure of lut40015 is + begin + INST10: ROM16X1A + generic map (initval => X"FBFB") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_30 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_30 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_30"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_30 : ENTITY IS TRUE; + + end SLICE_30; + + architecture Structure of SLICE_30 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40008 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40015 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2010_3_lut_3_lut: lut40015 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2044: lut40008 + port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + RASr2_380: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + RASr_379: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, A0_ipd, DI0_dly, M1_dly, + CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40016 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40016 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40016 : ENTITY IS TRUE; + + end lut40016; + + architecture Structure of lut40016 is + begin + INST10: ROM16X1A + generic map (initval => X"8080") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40017 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40017 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40017 : ENTITY IS TRUE; + + end lut40017; + + architecture Structure of lut40017 is + begin + INST10: ROM16X1A + generic map (initval => X"FFFB") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_32 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_32 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_32"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_32 : ENTITY IS TRUE; + + end SLICE_32; + + architecture Structure of SLICE_32 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component vmuxregsre0007 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40016 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40017 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_rep_32: lut40016 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_2_lut_3_lut_4_lut: lut40017 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RA10_400: vmuxregsre0007 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40018 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40018 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40018 : ENTITY IS TRUE; + + end lut40018; + + architecture Structure of lut40018 is + begin + INST10: ROM16X1A + generic map (initval => X"1010") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40019 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40019 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40019 : ENTITY IS TRUE; + + end lut40019; + + architecture Structure of lut40019 is + begin + INST10: ROM16X1A + generic map (initval => X"C6C6") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_33 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_33 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_33"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_33 : ENTITY IS TRUE; + + end SLICE_33; + + architecture Structure of SLICE_33 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40019 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_3_lut: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RA11_I_54_3_lut: lut40019 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + RA11_385: vmuxregsre0004 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40020 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40020 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40020 : ENTITY IS TRUE; + + end lut40020; + + architecture Structure of lut40020 is + begin + INST10: ROM16X1A + generic map (initval => X"20FF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40021 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40021 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40021 : ENTITY IS TRUE; + + end lut40021; + + architecture Structure of lut40021 is + begin + INST10: ROM16X1A + generic map (initval => X"CACA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_35 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_35 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_35"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_35 : ENTITY IS TRUE; + + end SLICE_35; + + architecture Structure of SLICE_35 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40020 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_4_lut_adj_25: lut40020 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i29_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RCKEEN_401: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40022 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40022 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40022 : ENTITY IS TRUE; + + end lut40022; + + architecture Structure of lut40022 is + begin + INST10: ROM16X1A + generic map (initval => X"CFC8") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_36 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_36 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_36"; + + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_36 : ENTITY IS TRUE; + + end SLICE_36; + + architecture Structure of SLICE_36 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40022 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1404_4_lut: lut40022 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + PHI2r2_377: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RCKE_395: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, M1_dly, + CLK_dly, F0_out, Q0_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_37 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_37 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_37"; + + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_37 : ENTITY IS TRUE; + + end SLICE_37; + + architecture Structure of SLICE_37 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40011 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + n2447_002_BUF1_BUF1: lut40011 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + Ready_404: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0 <= F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40023 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40023 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40023 : ENTITY IS TRUE; + + end lut40023; + + architecture Structure of lut40023 is + begin + INST10: ROM16X1A + generic map (initval => X"3A0A") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_44 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_44 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_44"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_44 : ENTITY IS TRUE; + + end SLICE_44; + + architecture Structure of SLICE_44 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40023 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1970_4_lut: lut40023 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1603_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + UFMCLK_416: vmuxregsre0004 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40024 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40024 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40024 : ENTITY IS TRUE; + + end lut40024; + + architecture Structure of lut40024 is + begin + INST10: ROM16X1A + generic map (initval => X"CAC0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_45 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_45 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_45"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_45 : ENTITY IS TRUE; + + end SLICE_45; + + architecture Structure of SLICE_45 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40024 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i4_4_lut_adj_17: lut4 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1589_4_lut: lut40024 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + UFMSDI_417: vmuxregsre0004 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, + F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40025 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40025 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40025 : ENTITY IS TRUE; + + end lut40025; + + architecture Structure of lut40025 is + begin + INST10: ROM16X1A + generic map (initval => X"FEFA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40026 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40026 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40026 : ENTITY IS TRUE; + + end lut40026; + + architecture Structure of lut40026 is + begin + INST10: ROM16X1A + generic map (initval => X"0008") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_50 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_50 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_50"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_50 : ENTITY IS TRUE; + + end SLICE_50; + + architecture Structure of SLICE_50 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40025 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40026 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1962_4_lut: lut40025 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i2_3_lut_4_lut_adj_11: lut40026 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + XOR8MEG_408: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40027 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40027 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40027 : ENTITY IS TRUE; + + end lut40027; + + architecture Structure of lut40027 is + begin + INST10: ROM16X1A + generic map (initval => X"1000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40028 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40028 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40028 : ENTITY IS TRUE; + + end lut40028; + + architecture Structure of lut40028 is + begin + INST10: ROM16X1A + generic map (initval => X"BF04") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_57 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_57 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_57"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_57 : ENTITY IS TRUE; + + end SLICE_57; + + architecture Structure of SLICE_57 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40027 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40028 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_rep_18_4_lut: lut40027 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + n8MEGEN_I_14_3_lut_4_lut: lut40028 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + n8MEGEN_418: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40029 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40029 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40029 : ENTITY IS TRUE; + + end lut40029; + + architecture Structure of lut40029 is + begin + INST10: ROM16X1A + generic map (initval => X"3AFA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40030 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40030 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40030 : ENTITY IS TRUE; + + end lut40030; + + architecture Structure of lut40030 is + begin + INST10: ROM16X1A + generic map (initval => X"FE0E") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity vmuxregsre0031 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity vmuxregsre0031 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre0031 : ENTITY IS TRUE; + + end vmuxregsre0031; + + architecture Structure of vmuxregsre0031 is + begin + INST01: FL1P3BX + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q); + end Structure; + +-- entity SLICE_59 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_59 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_59"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_59 : ENTITY IS TRUE; + + end SLICE_59; + + architecture Structure of SLICE_59 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40029 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40030 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0031 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + begin + nRCAS_I_43_4_lut: lut40029 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + nRCAS_I_0_452_3_lut_4_lut: lut40030 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nRCAS_398: vmuxregsre0031 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40032 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40032 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40032 : ENTITY IS TRUE; + + end lut40032; + + architecture Structure of lut40032 is + begin + INST10: ROM16X1A + generic map (initval => X"1F10") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_61 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_61 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_61"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_61 : ENTITY IS TRUE; + + end SLICE_61; + + architecture Structure of SLICE_61 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0031 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40032 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRCS_I_31_3_lut_4_lut: lut40032 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + nRCS_I_0_448_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + nRCS_396: vmuxregsre0031 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40033 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40033 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40033 : ENTITY IS TRUE; + + end lut40033; + + architecture Structure of lut40033 is + begin + INST10: ROM16X1A + generic map (initval => X"BFFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_62 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_62 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_62"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_62 : ENTITY IS TRUE; + + end SLICE_62; + + architecture Structure of SLICE_62 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40029 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0031 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40033 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i3_4_lut_adj_2: lut40033 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + nRCS_N_137_I_0_4_lut: lut40029 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nRRAS_397: vmuxregsre0031 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40034 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40034 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40034 : ENTITY IS TRUE; + + end lut40034; + + architecture Structure of lut40034 is + begin + INST10: ROM16X1A + generic map (initval => X"EEEE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40035 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40035 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40035 : ENTITY IS TRUE; + + end lut40035; + + architecture Structure of lut40035 is + begin + INST10: ROM16X1A + generic map (initval => X"CFC5") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_64 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_64 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_64"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_64 : ENTITY IS TRUE; + + end SLICE_64; + + architecture Structure of SLICE_64 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0031 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40035 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1477_2_lut: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + nRWE_I_0_455_4_lut: lut40035 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nRWE_399: vmuxregsre0031 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40036 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40036 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40036 : ENTITY IS TRUE; + + end lut40036; + + architecture Structure of lut40036 is + begin + INST10: ROM16X1A + generic map (initval => X"3032") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_65 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_65 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_65"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_65 : ENTITY IS TRUE; + + end SLICE_65; + + architecture Structure of SLICE_65 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40036 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i786_2_lut: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1432_4_lut: lut40036 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nRowColSel_402: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40037 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40037 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40037 : ENTITY IS TRUE; + + end lut40037; + + architecture Structure of lut40037 is + begin + INST10: ROM16X1A + generic map (initval => X"BBBB") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_66 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_66 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_66"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_66 : ENTITY IS TRUE; + + end SLICE_66; + + architecture Structure of SLICE_66 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40037 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_adj_23: lut40037 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1439_2_lut: lut40034 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + S_FSM_i4: vmuxregsre0004 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI0_dly, LSR_dly, + CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40038 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40038 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40038 : ENTITY IS TRUE; + + end lut40038; + + architecture Structure of lut40038 is + begin + INST10: ROM16X1A + generic map (initval => X"2222") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_67 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_67 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_67"; + + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_67 : ENTITY IS TRUE; + + end SLICE_67; + + architecture Structure of SLICE_67 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40038 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_adj_10: lut40038 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + S_FSM_i3: vmuxregsre0004 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, + Q0_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40039 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40039 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40039 : ENTITY IS TRUE; + + end lut40039; + + architecture Structure of lut40039 is + begin + INST10: ROM16X1A + generic map (initval => X"8888") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_68 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_68 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_68"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_68 : ENTITY IS TRUE; + + end SLICE_68; + + architecture Structure of SLICE_68 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i4_2_lut: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1989_2_lut: lut40039 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + S_FSM_i2: vmuxregsre0004 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, M0_dly, LSR_dly, + CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_69 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_69 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_69"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_69 : ENTITY IS TRUE; + + end SLICE_69; + + architecture Structure of SLICE_69 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40008 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1491_2_lut_rep_30: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RASr2_I_0_1_lut_rep_25: lut40008 + port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + PHI2r3_378: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + S_FSM_i1: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, + F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40040 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40040 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40040 : ENTITY IS TRUE; + + end lut40040; + + architecture Structure of lut40040 is + begin + INST10: ROM16X1A + generic map (initval => X"FFFE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40041 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40041 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40041 : ENTITY IS TRUE; + + end lut40041; + + architecture Structure of lut40041 is + begin + INST10: ROM16X1A + generic map (initval => X"3FBB") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_70 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_70 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_70"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_70 : ENTITY IS TRUE; + + end SLICE_70; + + architecture Structure of SLICE_70 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0031 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40040 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40041 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_4_lut: lut40040 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1448_4_lut: lut40041 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nUFMCS_415: vmuxregsre0031 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40042 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40042 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40042 : ENTITY IS TRUE; + + end lut40042; + + architecture Structure of lut40042 is + begin + INST10: ROM16X1A + generic map (initval => X"1F1F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40043 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40043 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40043 : ENTITY IS TRUE; + + end lut40043; + + architecture Structure of lut40043 is + begin + INST10: ROM16X1A + generic map (initval => X"5540") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity selmux2 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity selmux2 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF selmux2 : ENTITY IS TRUE; + + end selmux2; + + architecture Structure of selmux2 is + begin + INST1: MUX21 + port map (D0=>D0, D1=>D1, SD=>SD, Z=>Z); + end Structure; + +-- entity i30_SLICE_71 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity i30_SLICE_71 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "i30_SLICE_71"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF i30_SLICE_71 : ENTITY IS TRUE; + + end i30_SLICE_71; + + architecture Structure of i30_SLICE_71 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal i30_SLICE_71_i30_SLICE_71_K1_H1: Std_logic; + signal i30_SLICE_71_i30_GATE_H0: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40042 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40043 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + begin + i30_SLICE_71_K1: lut40042 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, + Z=>i30_SLICE_71_i30_SLICE_71_K1_H1); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i30_GATE: lut40043 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, + Z=>i30_SLICE_71_i30_GATE_H0); + i30_SLICE_71_K0K1MUX: selmux2 + port map (D0=>i30_SLICE_71_i30_GATE_H0, + D1=>i30_SLICE_71_i30_SLICE_71_K1_H1, SD=>M0_ipd, Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M0_ipd, OFX0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + OFX0_zd := OFX0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 7 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40044 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40044 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40044 : ENTITY IS TRUE; + + end lut40044; + + architecture Structure of lut40044 is + begin + INST10: ROM16X1A + generic map (initval => X"FF40") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_72 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_72 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_72"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_72 : ENTITY IS TRUE; + + end SLICE_72; + + architecture Structure of SLICE_72 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40044 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_4_lut_4_lut_adj_12: lut40044 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i2_2_lut: lut40039 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_73 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_73 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_73"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_73 : ENTITY IS TRUE; + + end SLICE_73; + + architecture Structure of SLICE_73 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40003 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40010 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_4_lut_adj_14: lut40003 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i4_4_lut: lut40010 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40045 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40045 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40045 : ENTITY IS TRUE; + + end lut40045; + + architecture Structure of lut40045 is + begin + INST10: ROM16X1A + generic map (initval => X"0020") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_74 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_74 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_74"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_74 : ENTITY IS TRUE; + + end SLICE_74; + + architecture Structure of SLICE_74 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40033 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40045 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i12_4_lut: lut40033 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut_3_lut_4_lut: lut40045 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RowA_i1: vmuxregsre0004 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i0: vmuxregsre0004 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, + Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_75 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_75 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_75"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_75 : ENTITY IS TRUE; + + end SLICE_75; + + architecture Structure of SLICE_75 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40027 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40038 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i3_4_lut_adj_18: lut40027 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut: lut40038 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_FSM_i9: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i8: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_76 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_76 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_76"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_76 : ENTITY IS TRUE; + + end SLICE_76; + + architecture Structure of SLICE_76 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component vmuxregsre0007 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40012 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40026 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_19_3_lut: lut40012 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1_2_lut_rep_15_4_lut: lut40026 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RowA_i9: vmuxregsre0007 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i8: vmuxregsre0004 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40046 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40046 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40046 : ENTITY IS TRUE; + + end lut40046; + + architecture Structure of lut40046 is + begin + INST10: ROM16X1A + generic map (initval => X"0800") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_77 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_77 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_77"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_77 : ENTITY IS TRUE; + + end SLICE_77; + + architecture Structure of SLICE_77 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40046 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i3_4_lut_adj_22: lut40046 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i3_4_lut: lut40046 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40047 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40047 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40047 : ENTITY IS TRUE; + + end lut40047; + + architecture Structure of lut40047 is + begin + INST10: ROM16X1A + generic map (initval => X"F0DD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40048 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40048 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40048 : ENTITY IS TRUE; + + end lut40048; + + architecture Structure of lut40048 is + begin + INST10: ROM16X1A + generic map (initval => X"DDDD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_78 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_78 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_78"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_78 : ENTITY IS TRUE; + + end SLICE_78; + + architecture Structure of SLICE_78 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40047 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40048 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRCS_N_146_bdd_4_lut: lut40047 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1423_2_lut: lut40048 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_FSM_i13: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i12: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40049 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40049 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40049 : ENTITY IS TRUE; + + end lut40049; + + architecture Structure of lut40049 is + begin + INST10: ROM16X1A + generic map (initval => X"0200") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_79 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_79 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_79"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_79 : ENTITY IS TRUE; + + end SLICE_79; + + architecture Structure of SLICE_79 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40016 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40049 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i11_3_lut_rep_20: lut40016 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_c_0_bdd_4_lut: lut40049 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + IS_FSM_i11: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i10: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40050 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40050 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40050 : ENTITY IS TRUE; + + end lut40050; + + architecture Structure of lut40050 is + begin + INST10: ROM16X1A + generic map (initval => X"0001") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_80 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_80 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_80"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_80 : ENTITY IS TRUE; + + end SLICE_80; + + architecture Structure of SLICE_80 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40050 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i3_2_lut_rep_26: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2005_3_lut_rep_17_4_lut: lut40050 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40051 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40051 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40051 : ENTITY IS TRUE; + + end lut40051; + + architecture Structure of lut40051 is + begin + INST10: ROM16X1A + generic map (initval => X"FCDD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_81 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_81 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_81"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_81 : ENTITY IS TRUE; + + end SLICE_81; + + architecture Structure of SLICE_81 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40051 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_29: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1427_4_lut: lut40051 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + IS_FSM_i15: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i14: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40052 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40052 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40052 : ENTITY IS TRUE; + + end lut40052; + + architecture Structure of lut40052 is + begin + INST10: ROM16X1A + generic map (initval => X"8000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_82 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_82 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_82"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_82 : ENTITY IS TRUE; + + end SLICE_82; + + architecture Structure of SLICE_82 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component vmuxregsre0007 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40052 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i6_4_lut: lut40052 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut_adj_3: lut40039 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RowA_i5: vmuxregsre0007 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i4: vmuxregsre0004 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40053 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40053 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40053 : ENTITY IS TRUE; + + end lut40053; + + architecture Structure of lut40053 is + begin + INST10: ROM16X1A + generic map (initval => X"0004") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40054 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40054 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40054 : ENTITY IS TRUE; + + end lut40054; + + architecture Structure of lut40054 is + begin + INST10: ROM16X1A + generic map (initval => X"FFDF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_83 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_83 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_83"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_83 : ENTITY IS TRUE; + + end SLICE_83; + + architecture Structure of SLICE_83 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40053 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40054 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_4_lut_adj_21: lut40053 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i2_3_lut_4_lut_adj_6: lut40054 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40055 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40055 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40055 : ENTITY IS TRUE; + + end lut40055; + + architecture Structure of lut40055 is + begin + INST10: ROM16X1A + generic map (initval => X"2020") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_84 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_84 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_84"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_84 : ENTITY IS TRUE; + + end SLICE_84; + + architecture Structure of SLICE_84 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40024 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40055 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_rep_28: lut40055 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1573_4_lut: lut40024 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + IS_FSM_i3: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i2: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40056 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40056 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40056 : ENTITY IS TRUE; + + end lut40056; + + architecture Structure of lut40056 is + begin + INST10: ROM16X1A + generic map (initval => X"FFEF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_85 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_85 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_85"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_85 : ENTITY IS TRUE; + + end SLICE_85; + + architecture Structure of SLICE_85 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40040 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40056 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1969_2_lut_3_lut_4_lut: lut40056 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i3_4_lut_adj_7: lut40040 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_86 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_86 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_86"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_86 : ENTITY IS TRUE; + + end SLICE_86; + + architecture Structure of SLICE_86 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40012 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i5_3_lut: lut40012 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1_4_lut_adj_8: lut4 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RASr3_381: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + PHI2r_376: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_87 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_87 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_87"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_87 : ENTITY IS TRUE; + + end SLICE_87; + + architecture Structure of SLICE_87 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40040 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40048 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i4_4_lut_adj_16: lut40040 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut_2_lut: lut40048 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RBA_i2: vmuxregsre0004 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RBA_i1: vmuxregsre0004 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40057 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40057 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40057 : ENTITY IS TRUE; + + end lut40057; + + architecture Structure of lut40057 is + begin + INST10: ROM16X1A + generic map (initval => X"C0C5") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_88 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_88 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_88"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_88 : ENTITY IS TRUE; + + end SLICE_88; + + architecture Structure of SLICE_88 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40053 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40057 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i34_4_lut: lut40057 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_4_lut_adj_13: lut40053 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + WRD_i7: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + WRD_i6: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40058 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40058 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40058 : ENTITY IS TRUE; + + end lut40058; + + architecture Structure of lut40058 is + begin + INST10: ROM16X1A + generic map (initval => X"8088") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40059 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40059 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40059 : ENTITY IS TRUE; + + end lut40059; + + architecture Structure of lut40059 is + begin + INST10: ROM16X1A + generic map (initval => X"C444") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_89 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_89 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_89"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_89 : ENTITY IS TRUE; + + end SLICE_89; + + architecture Structure of SLICE_89 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40058 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40059 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_4_lut: lut40058 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_4_lut: lut40059 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + WRD_i5: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + WRD_i4: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_90 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_90 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_90"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_90 : ENTITY IS TRUE; + + end SLICE_90; + + architecture Structure of SLICE_90 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40049 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40055 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_3_lut_4_lut_adj_1: lut40049 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut_rep_21_3_lut: lut40055 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + WRD_i1: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + WRD_i0: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40060 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40060 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40060 : ENTITY IS TRUE; + + end lut40060; + + architecture Structure of lut40060 is + begin + INST10: ROM16X1A + generic map (initval => X"DFDF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40061 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40061 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40061 : ENTITY IS TRUE; + + end lut40061; + + architecture Structure of lut40061 is + begin + INST10: ROM16X1A + generic map (initval => X"DFFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_91 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_91 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_91"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_91 : ENTITY IS TRUE; + + end SLICE_91; + + architecture Structure of SLICE_91 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40060 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40061 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_13_3_lut: lut40060 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1_2_lut_3_lut_4_lut_adj_5: lut40061 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RowA_i3: vmuxregsre0004 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i2: vmuxregsre0004 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40062 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40062 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40062 : ENTITY IS TRUE; + + end lut40062; + + architecture Structure of lut40062 is + begin + INST10: ROM16X1A + generic map (initval => X"0080") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_92 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_92 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_92"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_92 : ENTITY IS TRUE; + + end SLICE_92; + + architecture Structure of SLICE_92 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40005 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40062 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2008_2_lut_4_lut: lut40062 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut_rep_22_4_lut: lut40005 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + WRD_i3: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + WRD_i2: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40063 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40063 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40063 : ENTITY IS TRUE; + + end lut40063; + + architecture Structure of lut40063 is + begin + INST10: ROM16X1A + generic map (initval => X"7777") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_93 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_93 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_93"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_93 : ENTITY IS TRUE; + + end SLICE_93; + + architecture Structure of SLICE_93 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40063 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2001_2_lut: lut40063 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_9_I_0_427_i10_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + Bank_i1: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + Bank_i0: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, + M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40064 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40064 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40064 : ENTITY IS TRUE; + + end lut40064; + + architecture Structure of lut40064 is + begin + INST10: ROM16X1A + generic map (initval => X"FFFD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_94 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_94 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_94"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_94 : ENTITY IS TRUE; + + end SLICE_94; + + architecture Structure of SLICE_94 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40048 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40064 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i771_2_lut_rep_23_2_lut: lut40048 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_3_lut_4_lut_4_lut: lut40064 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40065 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40065 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40065 : ENTITY IS TRUE; + + end lut40065; + + architecture Structure of lut40065 is + begin + INST10: ROM16X1A + generic map (initval => X"1404") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_95 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_95 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_95"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_95 : ENTITY IS TRUE; + + end SLICE_95; + + architecture Structure of SLICE_95 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40040 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40065 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_4_lut_adj_20: lut40065 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i6_4_lut_adj_9: lut40040 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_96 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_96 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_96"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_96 : ENTITY IS TRUE; + + end SLICE_96; + + architecture Structure of SLICE_96 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40027 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_27: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_3_lut_4_lut_adj_24: lut40027 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40066 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40066 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40066 : ENTITY IS TRUE; + + end lut40066; + + architecture Structure of lut40066 is + begin + INST10: ROM16X1A + generic map (initval => X"C5C5") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_97 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_97 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_97"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_97 : ENTITY IS TRUE; + + end SLICE_97; + + architecture Structure of SLICE_97 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40066 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i13_3_lut: lut40066 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1956_2_lut: lut40034 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + IS_FSM_i7: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i6: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, M1_dly, + M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_98 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_98 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_98"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_98 : ENTITY IS TRUE; + + end SLICE_98; + + architecture Structure of SLICE_98 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40037 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1416_2_lut: lut40037 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_9_I_0_427_i9_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + IS_FSM_i1: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i0: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, + M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_99 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_99 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_99"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_99 : ENTITY IS TRUE; + + end SLICE_99; + + architecture Structure of SLICE_99 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40052 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i8_4_lut: lut40052 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + MAin_9_I_0_427_i8_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CmdUFMSDI_414: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_100 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_100 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_100"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_100 : ENTITY IS TRUE; + + end SLICE_100; + + architecture Structure of SLICE_100 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40052 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1979_4_lut: lut40052 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + MAin_9_I_0_427_i7_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CmdUFMCS_412: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + CmdUFMCLK_413: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_101 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_101 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_101"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_101 : ENTITY IS TRUE; + + end SLICE_101; + + architecture Structure of SLICE_101 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i1_3_lut: lut40021 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_9_I_0_427_i6_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + Bank_i7: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + Bank_i6: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_102 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_102 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_102"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_102 : ENTITY IS TRUE; + + end SLICE_102; + + architecture Structure of SLICE_102 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i2_3_lut: lut40021 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_9_I_0_427_i5_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + Bank_i5: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + Bank_i4: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_103 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_103 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_103"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_103 : ENTITY IS TRUE; + + end SLICE_103; + + architecture Structure of SLICE_103 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i3_3_lut: lut40021 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_9_I_0_427_i4_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + Bank_i3: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + Bank_i2: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40067 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40067 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40067 : ENTITY IS TRUE; + + end lut40067; + + architecture Structure of lut40067 is + begin + INST10: ROM16X1A + generic map (initval => X"FDFD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_104 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_104 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_104"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_104 : ENTITY IS TRUE; + + end SLICE_104; + + architecture Structure of SLICE_104 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40067 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1417_2_lut: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1_2_lut_rep_14_3_lut: lut40067 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + RowA_i7: vmuxregsre0004 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i6: vmuxregsre0004 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, + M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_105 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_105 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_105"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_105 : ENTITY IS TRUE; + + end SLICE_105; + + architecture Structure of SLICE_105 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40052 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_adj_19: lut40039 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i5_4_lut: lut40052 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_106 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_106 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_106"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_106 : ENTITY IS TRUE; + + end SLICE_106; + + architecture Structure of SLICE_106 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_33: lut40039 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1930_2_lut: lut40034 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + IS_FSM_i5: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i4: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, + CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity xo2iobuf + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity xo2iobuf is + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + + ATTRIBUTE Vital_Level0 OF xo2iobuf : ENTITY IS TRUE; + + end xo2iobuf; + + architecture Structure of xo2iobuf is + begin + INST1: IBPD + port map (I=>PADI, O=>Z); + INST2: OBZPD + port map (I=>I, T=>T, O=>PAD); + end Structure; + +-- entity RD_7_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_7_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD7 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD7_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD7 : VitalDelayType := 0 ns; + tpw_RD7_posedge : VitalDelayType := 0 ns; + tpw_RD7_negedge : VitalDelayType := 0 ns; + tpd_RD7_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD7: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_7_B : ENTITY IS TRUE; + + end RD_7_B; + + architecture Structure of RD_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD7_ipd : std_logic := 'X'; + signal RD7_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_7_713: xo2iobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD7_out, + PADI=>RD7_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD7_ipd, RD7, tipd_RD7); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD7_ipd, RD7_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD7_zd : std_logic := 'X'; + VARIABLE RD7_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD7_RD7 : x01 := '0'; + VARIABLE periodcheckinfo_RD7 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD7_ipd, + TestSignalName => "RD7", + Period => tperiod_RD7, + PulseWidthHigh => tpw_RD7_posedge, + PulseWidthLow => tpw_RD7_negedge, + PeriodData => periodcheckinfo_RD7, + Violation => tviol_RD7_RD7, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD7_zd := RD7_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD7_ipd'last_event, + PathDelay => tpd_RD7_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD7, OutSignalName => "RD7", OutTemp => RD7_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD7, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD7, + PathCondition => TRUE)), + GlitchData => RD7_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_6_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_6_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD6 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD6_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD6 : VitalDelayType := 0 ns; + tpw_RD6_posedge : VitalDelayType := 0 ns; + tpw_RD6_negedge : VitalDelayType := 0 ns; + tpd_RD6_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD6: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_6_B : ENTITY IS TRUE; + + end RD_6_B; + + architecture Structure of RD_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD6_ipd : std_logic := 'X'; + signal RD6_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_6_714: xo2iobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD6_out, + PADI=>RD6_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD6_ipd, RD6, tipd_RD6); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD6_ipd, RD6_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD6_zd : std_logic := 'X'; + VARIABLE RD6_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD6_RD6 : x01 := '0'; + VARIABLE periodcheckinfo_RD6 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD6_ipd, + TestSignalName => "RD6", + Period => tperiod_RD6, + PulseWidthHigh => tpw_RD6_posedge, + PulseWidthLow => tpw_RD6_negedge, + PeriodData => periodcheckinfo_RD6, + Violation => tviol_RD6_RD6, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD6_zd := RD6_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD6_ipd'last_event, + PathDelay => tpd_RD6_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD6, OutSignalName => "RD6", OutTemp => RD6_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD6, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD6, + PathCondition => TRUE)), + GlitchData => RD6_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_5_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_5_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD5 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD5_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD5 : VitalDelayType := 0 ns; + tpw_RD5_posedge : VitalDelayType := 0 ns; + tpw_RD5_negedge : VitalDelayType := 0 ns; + tpd_RD5_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD5: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_5_B : ENTITY IS TRUE; + + end RD_5_B; + + architecture Structure of RD_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD5_ipd : std_logic := 'X'; + signal RD5_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_5_715: xo2iobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD5_out, + PADI=>RD5_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD5_ipd, RD5, tipd_RD5); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD5_ipd, RD5_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD5_zd : std_logic := 'X'; + VARIABLE RD5_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD5_RD5 : x01 := '0'; + VARIABLE periodcheckinfo_RD5 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD5_ipd, + TestSignalName => "RD5", + Period => tperiod_RD5, + PulseWidthHigh => tpw_RD5_posedge, + PulseWidthLow => tpw_RD5_negedge, + PeriodData => periodcheckinfo_RD5, + Violation => tviol_RD5_RD5, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD5_zd := RD5_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD5_ipd'last_event, + PathDelay => tpd_RD5_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD5, OutSignalName => "RD5", OutTemp => RD5_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD5, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD5, + PathCondition => TRUE)), + GlitchData => RD5_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_4_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_4_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD4 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD4_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD4 : VitalDelayType := 0 ns; + tpw_RD4_posedge : VitalDelayType := 0 ns; + tpw_RD4_negedge : VitalDelayType := 0 ns; + tpd_RD4_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD4: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_4_B : ENTITY IS TRUE; + + end RD_4_B; + + architecture Structure of RD_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD4_ipd : std_logic := 'X'; + signal RD4_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_4_716: xo2iobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD4_out, + PADI=>RD4_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD4_ipd, RD4, tipd_RD4); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD4_ipd, RD4_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD4_zd : std_logic := 'X'; + VARIABLE RD4_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD4_RD4 : x01 := '0'; + VARIABLE periodcheckinfo_RD4 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD4_ipd, + TestSignalName => "RD4", + Period => tperiod_RD4, + PulseWidthHigh => tpw_RD4_posedge, + PulseWidthLow => tpw_RD4_negedge, + PeriodData => periodcheckinfo_RD4, + Violation => tviol_RD4_RD4, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD4_zd := RD4_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD4_ipd'last_event, + PathDelay => tpd_RD4_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD4, OutSignalName => "RD4", OutTemp => RD4_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD4, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD4, + PathCondition => TRUE)), + GlitchData => RD4_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_3_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_3_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD3 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD3_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD3 : VitalDelayType := 0 ns; + tpw_RD3_posedge : VitalDelayType := 0 ns; + tpw_RD3_negedge : VitalDelayType := 0 ns; + tpd_RD3_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD3: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_3_B : ENTITY IS TRUE; + + end RD_3_B; + + architecture Structure of RD_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD3_ipd : std_logic := 'X'; + signal RD3_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_3_717: xo2iobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD3_out, + PADI=>RD3_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD3_ipd, RD3, tipd_RD3); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD3_ipd, RD3_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD3_zd : std_logic := 'X'; + VARIABLE RD3_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD3_RD3 : x01 := '0'; + VARIABLE periodcheckinfo_RD3 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD3_ipd, + TestSignalName => "RD3", + Period => tperiod_RD3, + PulseWidthHigh => tpw_RD3_posedge, + PulseWidthLow => tpw_RD3_negedge, + PeriodData => periodcheckinfo_RD3, + Violation => tviol_RD3_RD3, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD3_zd := RD3_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD3_ipd'last_event, + PathDelay => tpd_RD3_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD3, OutSignalName => "RD3", OutTemp => RD3_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD3, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD3, + PathCondition => TRUE)), + GlitchData => RD3_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_2_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_2_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD2 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD2_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD2 : VitalDelayType := 0 ns; + tpw_RD2_posedge : VitalDelayType := 0 ns; + tpw_RD2_negedge : VitalDelayType := 0 ns; + tpd_RD2_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD2: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_2_B : ENTITY IS TRUE; + + end RD_2_B; + + architecture Structure of RD_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD2_ipd : std_logic := 'X'; + signal RD2_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_2_718: xo2iobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD2_out, + PADI=>RD2_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD2_ipd, RD2, tipd_RD2); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD2_ipd, RD2_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD2_zd : std_logic := 'X'; + VARIABLE RD2_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD2_RD2 : x01 := '0'; + VARIABLE periodcheckinfo_RD2 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD2_ipd, + TestSignalName => "RD2", + Period => tperiod_RD2, + PulseWidthHigh => tpw_RD2_posedge, + PulseWidthLow => tpw_RD2_negedge, + PeriodData => periodcheckinfo_RD2, + Violation => tviol_RD2_RD2, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD2_zd := RD2_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD2_ipd'last_event, + PathDelay => tpd_RD2_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD2, OutSignalName => "RD2", OutTemp => RD2_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD2, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD2, + PathCondition => TRUE)), + GlitchData => RD2_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_1_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD1 : VitalDelayType := 0 ns; + tpw_RD1_posedge : VitalDelayType := 0 ns; + tpw_RD1_negedge : VitalDelayType := 0 ns; + tpd_RD1_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD1: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_1_B : ENTITY IS TRUE; + + end RD_1_B; + + architecture Structure of RD_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD1_ipd : std_logic := 'X'; + signal RD1_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_1_719: xo2iobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD1_out, + PADI=>RD1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD1_ipd, RD1, tipd_RD1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD1_ipd, RD1_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD1_zd : std_logic := 'X'; + VARIABLE RD1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD1_RD1 : x01 := '0'; + VARIABLE periodcheckinfo_RD1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD1_ipd, + TestSignalName => "RD1", + Period => tperiod_RD1, + PulseWidthHigh => tpw_RD1_posedge, + PulseWidthLow => tpw_RD1_negedge, + PeriodData => periodcheckinfo_RD1, + Violation => tviol_RD1_RD1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD1_zd := RD1_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD1_ipd'last_event, + PathDelay => tpd_RD1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD1, OutSignalName => "RD1", OutTemp => RD1_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD1, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD1, + PathCondition => TRUE)), + GlitchData => RD1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_0_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD0 : VitalDelayType := 0 ns; + tpw_RD0_posedge : VitalDelayType := 0 ns; + tpw_RD0_negedge : VitalDelayType := 0 ns; + tpd_RD0_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD0: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_0_B : ENTITY IS TRUE; + + end RD_0_B; + + architecture Structure of RD_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD0_ipd : std_logic := 'X'; + signal RD0_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_0_720: xo2iobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD0_out, + PADI=>RD0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD0_ipd, RD0, tipd_RD0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD0_ipd, RD0_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD0_zd : std_logic := 'X'; + VARIABLE RD0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD0_RD0 : x01 := '0'; + VARIABLE periodcheckinfo_RD0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD0_ipd, + TestSignalName => "RD0", + Period => tperiod_RD0, + PulseWidthHigh => tpw_RD0_posedge, + PulseWidthLow => tpw_RD0_negedge, + PeriodData => periodcheckinfo_RD0, + Violation => tviol_RD0_RD0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD0_zd := RD0_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD0_ipd'last_event, + PathDelay => tpd_RD0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD0, OutSignalName => "RD0", OutTemp => RD0_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD0, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD0, + PathCondition => TRUE)), + GlitchData => RD0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity xo2iobuf0068 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity xo2iobuf0068 is + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + + ATTRIBUTE Vital_Level0 OF xo2iobuf0068 : ENTITY IS TRUE; + + end xo2iobuf0068; + + architecture Structure of xo2iobuf0068 is + begin + INST5: OBZPD + port map (I=>I, T=>T, O=>PAD); + end Structure; + +-- entity Dout_7_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_7_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout7 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout7: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_7_B : ENTITY IS TRUE; + + end Dout_7_B; + + architecture Structure of Dout_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout7_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_7: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout7_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout7_out) + VARIABLE Dout7_zd : std_logic := 'X'; + VARIABLE Dout7_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout7_zd := Dout7_out; + + VitalPathDelay01 ( + OutSignal => Dout7, OutSignalName => "Dout7", OutTemp => Dout7_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout7, + PathCondition => TRUE)), + GlitchData => Dout7_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_6_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_6_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout6 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout6: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_6_B : ENTITY IS TRUE; + + end Dout_6_B; + + architecture Structure of Dout_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout6_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_6: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout6_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout6_out) + VARIABLE Dout6_zd : std_logic := 'X'; + VARIABLE Dout6_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout6_zd := Dout6_out; + + VitalPathDelay01 ( + OutSignal => Dout6, OutSignalName => "Dout6", OutTemp => Dout6_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout6, + PathCondition => TRUE)), + GlitchData => Dout6_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_5_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_5_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout5 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout5: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_5_B : ENTITY IS TRUE; + + end Dout_5_B; + + architecture Structure of Dout_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout5_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_5: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout5_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout5_out) + VARIABLE Dout5_zd : std_logic := 'X'; + VARIABLE Dout5_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout5_zd := Dout5_out; + + VitalPathDelay01 ( + OutSignal => Dout5, OutSignalName => "Dout5", OutTemp => Dout5_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout5, + PathCondition => TRUE)), + GlitchData => Dout5_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_4_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_4_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout4 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout4: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_4_B : ENTITY IS TRUE; + + end Dout_4_B; + + architecture Structure of Dout_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout4_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_4: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout4_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout4_out) + VARIABLE Dout4_zd : std_logic := 'X'; + VARIABLE Dout4_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout4_zd := Dout4_out; + + VitalPathDelay01 ( + OutSignal => Dout4, OutSignalName => "Dout4", OutTemp => Dout4_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout4, + PathCondition => TRUE)), + GlitchData => Dout4_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_3_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_3_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout3 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout3: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_3_B : ENTITY IS TRUE; + + end Dout_3_B; + + architecture Structure of Dout_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout3_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_3: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout3_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout3_out) + VARIABLE Dout3_zd : std_logic := 'X'; + VARIABLE Dout3_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout3_zd := Dout3_out; + + VitalPathDelay01 ( + OutSignal => Dout3, OutSignalName => "Dout3", OutTemp => Dout3_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout3, + PathCondition => TRUE)), + GlitchData => Dout3_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_2_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_2_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout2 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout2: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_2_B : ENTITY IS TRUE; + + end Dout_2_B; + + architecture Structure of Dout_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout2_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_2: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout2_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout2_out) + VARIABLE Dout2_zd : std_logic := 'X'; + VARIABLE Dout2_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout2_zd := Dout2_out; + + VitalPathDelay01 ( + OutSignal => Dout2, OutSignalName => "Dout2", OutTemp => Dout2_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout2, + PathCondition => TRUE)), + GlitchData => Dout2_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_1_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout1 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_1_B : ENTITY IS TRUE; + + end Dout_1_B; + + architecture Structure of Dout_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_1: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout1_out) + VARIABLE Dout1_zd : std_logic := 'X'; + VARIABLE Dout1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout1_zd := Dout1_out; + + VitalPathDelay01 ( + OutSignal => Dout1, OutSignalName => "Dout1", OutTemp => Dout1_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout1, + PathCondition => TRUE)), + GlitchData => Dout1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_0_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_0_B : ENTITY IS TRUE; + + end Dout_0_B; + + architecture Structure of Dout_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_0: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout0_out) + VARIABLE Dout0_zd : std_logic := 'X'; + VARIABLE Dout0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout0_zd := Dout0_out; + + VitalPathDelay01 ( + OutSignal => Dout0, OutSignalName => "Dout0", OutTemp => Dout0_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout0, + PathCondition => TRUE)), + GlitchData => Dout0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity LEDB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity LEDB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "LEDB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_LEDS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; LEDS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF LEDB : ENTITY IS TRUE; + + end LEDB; + + architecture Structure of LEDB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal LEDS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + LED_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>LEDS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, LEDS_out) + VARIABLE LEDS_zd : std_logic := 'X'; + VARIABLE LEDS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + LEDS_zd := LEDS_out; + + VitalPathDelay01 ( + OutSignal => LEDS, OutSignalName => "LEDS", OutTemp => LEDS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_LEDS, + PathCondition => TRUE)), + GlitchData => LEDS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RBA_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RBA_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RBA_1_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RBA1 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RBA1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RBA_1_B : ENTITY IS TRUE; + + end RBA_1_B; + + architecture Structure of RBA_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RBA1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RBA_pad_1: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RBA1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RBA1_out) + VARIABLE RBA1_zd : std_logic := 'X'; + VARIABLE RBA1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RBA1_zd := RBA1_out; + + VitalPathDelay01 ( + OutSignal => RBA1, OutSignalName => "RBA1", OutTemp => RBA1_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RBA1, + PathCondition => TRUE)), + GlitchData => RBA1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RBA_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RBA_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RBA_0_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RBA0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RBA0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RBA_0_B : ENTITY IS TRUE; + + end RBA_0_B; + + architecture Structure of RBA_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RBA0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RBA_pad_0: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RBA0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RBA0_out) + VARIABLE RBA0_zd : std_logic := 'X'; + VARIABLE RBA0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RBA0_zd := RBA0_out; + + VitalPathDelay01 ( + OutSignal => RBA0, OutSignalName => "RBA0", OutTemp => RBA0_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RBA0, + PathCondition => TRUE)), + GlitchData => RBA0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_11_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_11_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_11_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA11 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA11: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_11_B : ENTITY IS TRUE; + + end RA_11_B; + + architecture Structure of RA_11_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA11_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_11: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA11_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA11_out) + VARIABLE RA11_zd : std_logic := 'X'; + VARIABLE RA11_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA11_zd := RA11_out; + + VitalPathDelay01 ( + OutSignal => RA11, OutSignalName => "RA11", OutTemp => RA11_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA11, + PathCondition => TRUE)), + GlitchData => RA11_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_10_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_10_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_10_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA10 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA10: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_10_B : ENTITY IS TRUE; + + end RA_10_B; + + architecture Structure of RA_10_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA10_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_10: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA10_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA10_out) + VARIABLE RA10_zd : std_logic := 'X'; + VARIABLE RA10_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA10_zd := RA10_out; + + VitalPathDelay01 ( + OutSignal => RA10, OutSignalName => "RA10", OutTemp => RA10_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA10, + PathCondition => TRUE)), + GlitchData => RA10_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_9_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_9_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_9_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA9 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA9: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_9_B : ENTITY IS TRUE; + + end RA_9_B; + + architecture Structure of RA_9_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA9_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_9: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA9_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA9_out) + VARIABLE RA9_zd : std_logic := 'X'; + VARIABLE RA9_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA9_zd := RA9_out; + + VitalPathDelay01 ( + OutSignal => RA9, OutSignalName => "RA9", OutTemp => RA9_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA9, + PathCondition => TRUE)), + GlitchData => RA9_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_8_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_8_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_8_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA8 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA8: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_8_B : ENTITY IS TRUE; + + end RA_8_B; + + architecture Structure of RA_8_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA8_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_8: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA8_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA8_out) + VARIABLE RA8_zd : std_logic := 'X'; + VARIABLE RA8_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA8_zd := RA8_out; + + VitalPathDelay01 ( + OutSignal => RA8, OutSignalName => "RA8", OutTemp => RA8_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA8, + PathCondition => TRUE)), + GlitchData => RA8_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_7_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_7_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA7 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA7: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_7_B : ENTITY IS TRUE; + + end RA_7_B; + + architecture Structure of RA_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA7_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_7: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA7_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA7_out) + VARIABLE RA7_zd : std_logic := 'X'; + VARIABLE RA7_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA7_zd := RA7_out; + + VitalPathDelay01 ( + OutSignal => RA7, OutSignalName => "RA7", OutTemp => RA7_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA7, + PathCondition => TRUE)), + GlitchData => RA7_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_6_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_6_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA6 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA6: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_6_B : ENTITY IS TRUE; + + end RA_6_B; + + architecture Structure of RA_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA6_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_6: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA6_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA6_out) + VARIABLE RA6_zd : std_logic := 'X'; + VARIABLE RA6_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA6_zd := RA6_out; + + VitalPathDelay01 ( + OutSignal => RA6, OutSignalName => "RA6", OutTemp => RA6_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA6, + PathCondition => TRUE)), + GlitchData => RA6_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_5_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_5_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA5 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA5: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_5_B : ENTITY IS TRUE; + + end RA_5_B; + + architecture Structure of RA_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA5_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_5: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA5_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA5_out) + VARIABLE RA5_zd : std_logic := 'X'; + VARIABLE RA5_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA5_zd := RA5_out; + + VitalPathDelay01 ( + OutSignal => RA5, OutSignalName => "RA5", OutTemp => RA5_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA5, + PathCondition => TRUE)), + GlitchData => RA5_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_4_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_4_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA4 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA4: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_4_B : ENTITY IS TRUE; + + end RA_4_B; + + architecture Structure of RA_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA4_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_4: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA4_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA4_out) + VARIABLE RA4_zd : std_logic := 'X'; + VARIABLE RA4_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA4_zd := RA4_out; + + VitalPathDelay01 ( + OutSignal => RA4, OutSignalName => "RA4", OutTemp => RA4_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA4, + PathCondition => TRUE)), + GlitchData => RA4_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_3_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_3_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA3 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA3: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_3_B : ENTITY IS TRUE; + + end RA_3_B; + + architecture Structure of RA_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA3_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_3: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA3_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA3_out) + VARIABLE RA3_zd : std_logic := 'X'; + VARIABLE RA3_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA3_zd := RA3_out; + + VitalPathDelay01 ( + OutSignal => RA3, OutSignalName => "RA3", OutTemp => RA3_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA3, + PathCondition => TRUE)), + GlitchData => RA3_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_2_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_2_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA2 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA2: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_2_B : ENTITY IS TRUE; + + end RA_2_B; + + architecture Structure of RA_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA2_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_2: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA2_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA2_out) + VARIABLE RA2_zd : std_logic := 'X'; + VARIABLE RA2_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA2_zd := RA2_out; + + VitalPathDelay01 ( + OutSignal => RA2, OutSignalName => "RA2", OutTemp => RA2_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA2, + PathCondition => TRUE)), + GlitchData => RA2_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_1_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA1 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_1_B : ENTITY IS TRUE; + + end RA_1_B; + + architecture Structure of RA_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_1: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA1_out) + VARIABLE RA1_zd : std_logic := 'X'; + VARIABLE RA1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA1_zd := RA1_out; + + VitalPathDelay01 ( + OutSignal => RA1, OutSignalName => "RA1", OutTemp => RA1_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA1, + PathCondition => TRUE)), + GlitchData => RA1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_0_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_0_B : ENTITY IS TRUE; + + end RA_0_B; + + architecture Structure of RA_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_0: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA0_out) + VARIABLE RA0_zd : std_logic := 'X'; + VARIABLE RA0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA0_zd := RA0_out; + + VitalPathDelay01 ( + OutSignal => RA0, OutSignalName => "RA0", OutTemp => RA0_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA0, + PathCondition => TRUE)), + GlitchData => RA0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRCSB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRCSB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRCSB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nRCSS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; nRCSS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRCSB : ENTITY IS TRUE; + + end nRCSB; + + architecture Structure of nRCSB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nRCSS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nRCS_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRCSS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nRCSS_out) + VARIABLE nRCSS_zd : std_logic := 'X'; + VARIABLE nRCSS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRCSS_zd := nRCSS_out; + + VitalPathDelay01 ( + OutSignal => nRCSS, OutSignalName => "nRCSS", OutTemp => nRCSS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nRCSS, + PathCondition => TRUE)), + GlitchData => nRCSS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RCKEB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RCKEB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RCKEB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RCKES : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RCKES: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RCKEB : ENTITY IS TRUE; + + end RCKEB; + + architecture Structure of RCKEB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RCKES_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RCKE_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RCKES_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RCKES_out) + VARIABLE RCKES_zd : std_logic := 'X'; + VARIABLE RCKES_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RCKES_zd := RCKES_out; + + VitalPathDelay01 ( + OutSignal => RCKES, OutSignalName => "RCKES", OutTemp => RCKES_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RCKES, + PathCondition => TRUE)), + GlitchData => RCKES_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRWEB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRWEB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRWEB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nRWES : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; nRWES: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRWEB : ENTITY IS TRUE; + + end nRWEB; + + architecture Structure of nRWEB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nRWES_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nRWE_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRWES_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nRWES_out) + VARIABLE nRWES_zd : std_logic := 'X'; + VARIABLE nRWES_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRWES_zd := nRWES_out; + + VitalPathDelay01 ( + OutSignal => nRWES, OutSignalName => "nRWES", OutTemp => nRWES_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nRWES, + PathCondition => TRUE)), + GlitchData => nRWES_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRRASB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRRASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRRASB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nRRASS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; nRRASS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRRASB : ENTITY IS TRUE; + + end nRRASB; + + architecture Structure of nRRASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nRRASS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nRRAS_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRRASS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nRRASS_out) + VARIABLE nRRASS_zd : std_logic := 'X'; + VARIABLE nRRASS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRRASS_zd := nRRASS_out; + + VitalPathDelay01 ( + OutSignal => nRRASS, OutSignalName => "nRRASS", OutTemp => nRRASS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nRRASS, + PathCondition => TRUE)), + GlitchData => nRRASS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRCASB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRCASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRCASB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nRCASS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; nRCASS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRCASB : ENTITY IS TRUE; + + end nRCASB; + + architecture Structure of nRCASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nRCASS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nRCAS_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRCASS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nRCASS_out) + VARIABLE nRCASS_zd : std_logic := 'X'; + VARIABLE nRCASS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRCASS_zd := nRCASS_out; + + VitalPathDelay01 ( + OutSignal => nRCASS, OutSignalName => "nRCASS", OutTemp => nRCASS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nRCASS, + PathCondition => TRUE)), + GlitchData => nRCASS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RDQMHB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RDQMHB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RDQMHB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RDQMHS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RDQMHS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RDQMHB : ENTITY IS TRUE; + + end RDQMHB; + + architecture Structure of RDQMHB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RDQMHS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RDQMH_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RDQMHS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RDQMHS_out) + VARIABLE RDQMHS_zd : std_logic := 'X'; + VARIABLE RDQMHS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RDQMHS_zd := RDQMHS_out; + + VitalPathDelay01 ( + OutSignal => RDQMHS, OutSignalName => "RDQMHS", OutTemp => RDQMHS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RDQMHS, + PathCondition => TRUE)), + GlitchData => RDQMHS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RDQMLB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RDQMLB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RDQMLB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RDQMLS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RDQMLS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RDQMLB : ENTITY IS TRUE; + + end RDQMLB; + + architecture Structure of RDQMLB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RDQMLS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RDQML_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RDQMLS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RDQMLS_out) + VARIABLE RDQMLS_zd : std_logic := 'X'; + VARIABLE RDQMLS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RDQMLS_zd := RDQMLS_out; + + VitalPathDelay01 ( + OutSignal => RDQMLS, OutSignalName => "RDQMLS", OutTemp => RDQMLS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RDQMLS, + PathCondition => TRUE)), + GlitchData => RDQMLS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nUFMCSB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nUFMCSB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nUFMCSB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nUFMCSS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; nUFMCSS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nUFMCSB : ENTITY IS TRUE; + + end nUFMCSB; + + architecture Structure of nUFMCSB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nUFMCSS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nUFMCS_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nUFMCSS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nUFMCSS_out) + VARIABLE nUFMCSS_zd : std_logic := 'X'; + VARIABLE nUFMCSS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nUFMCSS_zd := nUFMCSS_out; + + VitalPathDelay01 ( + OutSignal => nUFMCSS, OutSignalName => "nUFMCSS", OutTemp => nUFMCSS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nUFMCSS, + PathCondition => TRUE)), + GlitchData => nUFMCSS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity UFMCLKB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity UFMCLKB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "UFMCLKB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_UFMCLKS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; UFMCLKS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF UFMCLKB : ENTITY IS TRUE; + + end UFMCLKB; + + architecture Structure of UFMCLKB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal UFMCLKS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + UFMCLK_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>UFMCLKS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, UFMCLKS_out) + VARIABLE UFMCLKS_zd : std_logic := 'X'; + VARIABLE UFMCLKS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + UFMCLKS_zd := UFMCLKS_out; + + VitalPathDelay01 ( + OutSignal => UFMCLKS, OutSignalName => "UFMCLKS", OutTemp => UFMCLKS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_UFMCLKS, + PathCondition => TRUE)), + GlitchData => UFMCLKS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity UFMSDIB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity UFMSDIB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "UFMSDIB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_UFMSDIS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; UFMSDIS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF UFMSDIB : ENTITY IS TRUE; + + end UFMSDIB; + + architecture Structure of UFMSDIB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal UFMSDIS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + UFMSDI_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>UFMSDIS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, UFMSDIS_out) + VARIABLE UFMSDIS_zd : std_logic := 'X'; + VARIABLE UFMSDIS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + UFMSDIS_zd := UFMSDIS_out; + + VitalPathDelay01 ( + OutSignal => UFMSDIS, OutSignalName => "UFMSDIS", OutTemp => UFMSDIS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_UFMSDIS, + PathCondition => TRUE)), + GlitchData => UFMSDIS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity xo2iobuf0069 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity xo2iobuf0069 is + port (Z: out Std_logic; PAD: in Std_logic); + + ATTRIBUTE Vital_Level0 OF xo2iobuf0069 : ENTITY IS TRUE; + + end xo2iobuf0069; + + architecture Structure of xo2iobuf0069 is + begin + INST1: IBPD + port map (I=>PAD, O=>Z); + end Structure; + +-- entity PHI2B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity PHI2B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "PHI2B"; + + tipd_PHI2S : VitalDelayType01 := (0 ns, 0 ns); + tpd_PHI2S_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_PHI2S : VitalDelayType := 0 ns; + tpw_PHI2S_posedge : VitalDelayType := 0 ns; + tpw_PHI2S_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; PHI2S: in Std_logic); + + ATTRIBUTE Vital_Level0 OF PHI2B : ENTITY IS TRUE; + + end PHI2B; + + architecture Structure of PHI2B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PHI2S_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + PHI2_pad: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>PHI2S_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PHI2S_ipd, PHI2S, tipd_PHI2S); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PHI2S_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_PHI2S_PHI2S : x01 := '0'; + VARIABLE periodcheckinfo_PHI2S : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => PHI2S_ipd, + TestSignalName => "PHI2S", + Period => tperiod_PHI2S, + PulseWidthHigh => tpw_PHI2S_posedge, + PulseWidthLow => tpw_PHI2S_negedge, + PeriodData => periodcheckinfo_PHI2S, + Violation => tviol_PHI2S_PHI2S, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => PHI2S_ipd'last_event, + PathDelay => tpd_PHI2S_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_9_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_9_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_9_B"; + + tipd_MAin9 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin9_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin9 : VitalDelayType := 0 ns; + tpw_MAin9_posedge : VitalDelayType := 0 ns; + tpw_MAin9_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin9: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_9_B : ENTITY IS TRUE; + + end MAin_9_B; + + architecture Structure of MAin_9_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin9_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_9: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin9_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin9_ipd, MAin9, tipd_MAin9); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin9_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin9_MAin9 : x01 := '0'; + VARIABLE periodcheckinfo_MAin9 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin9_ipd, + TestSignalName => "MAin9", + Period => tperiod_MAin9, + PulseWidthHigh => tpw_MAin9_posedge, + PulseWidthLow => tpw_MAin9_negedge, + PeriodData => periodcheckinfo_MAin9, + Violation => tviol_MAin9_MAin9, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin9_ipd'last_event, + PathDelay => tpd_MAin9_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_8_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_8_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_8_B"; + + tipd_MAin8 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin8_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin8 : VitalDelayType := 0 ns; + tpw_MAin8_posedge : VitalDelayType := 0 ns; + tpw_MAin8_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin8: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_8_B : ENTITY IS TRUE; + + end MAin_8_B; + + architecture Structure of MAin_8_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin8_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_8: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin8_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin8_ipd, MAin8, tipd_MAin8); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin8_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin8_MAin8 : x01 := '0'; + VARIABLE periodcheckinfo_MAin8 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin8_ipd, + TestSignalName => "MAin8", + Period => tperiod_MAin8, + PulseWidthHigh => tpw_MAin8_posedge, + PulseWidthLow => tpw_MAin8_negedge, + PeriodData => periodcheckinfo_MAin8, + Violation => tviol_MAin8_MAin8, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin8_ipd'last_event, + PathDelay => tpd_MAin8_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_7_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_7_B"; + + tipd_MAin7 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin7_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin7 : VitalDelayType := 0 ns; + tpw_MAin7_posedge : VitalDelayType := 0 ns; + tpw_MAin7_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin7: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_7_B : ENTITY IS TRUE; + + end MAin_7_B; + + architecture Structure of MAin_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin7_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_7: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin7_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin7_ipd, MAin7, tipd_MAin7); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin7_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin7_MAin7 : x01 := '0'; + VARIABLE periodcheckinfo_MAin7 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin7_ipd, + TestSignalName => "MAin7", + Period => tperiod_MAin7, + PulseWidthHigh => tpw_MAin7_posedge, + PulseWidthLow => tpw_MAin7_negedge, + PeriodData => periodcheckinfo_MAin7, + Violation => tviol_MAin7_MAin7, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin7_ipd'last_event, + PathDelay => tpd_MAin7_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_6_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_6_B"; + + tipd_MAin6 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin6_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin6 : VitalDelayType := 0 ns; + tpw_MAin6_posedge : VitalDelayType := 0 ns; + tpw_MAin6_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin6: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_6_B : ENTITY IS TRUE; + + end MAin_6_B; + + architecture Structure of MAin_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin6_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_6: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin6_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin6_ipd, MAin6, tipd_MAin6); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin6_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin6_MAin6 : x01 := '0'; + VARIABLE periodcheckinfo_MAin6 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin6_ipd, + TestSignalName => "MAin6", + Period => tperiod_MAin6, + PulseWidthHigh => tpw_MAin6_posedge, + PulseWidthLow => tpw_MAin6_negedge, + PeriodData => periodcheckinfo_MAin6, + Violation => tviol_MAin6_MAin6, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin6_ipd'last_event, + PathDelay => tpd_MAin6_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_5_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_5_B"; + + tipd_MAin5 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin5_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin5 : VitalDelayType := 0 ns; + tpw_MAin5_posedge : VitalDelayType := 0 ns; + tpw_MAin5_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin5: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_5_B : ENTITY IS TRUE; + + end MAin_5_B; + + architecture Structure of MAin_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin5_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_5: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin5_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin5_ipd, MAin5, tipd_MAin5); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin5_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin5_MAin5 : x01 := '0'; + VARIABLE periodcheckinfo_MAin5 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin5_ipd, + TestSignalName => "MAin5", + Period => tperiod_MAin5, + PulseWidthHigh => tpw_MAin5_posedge, + PulseWidthLow => tpw_MAin5_negedge, + PeriodData => periodcheckinfo_MAin5, + Violation => tviol_MAin5_MAin5, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin5_ipd'last_event, + PathDelay => tpd_MAin5_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_4_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_4_B"; + + tipd_MAin4 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin4_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin4 : VitalDelayType := 0 ns; + tpw_MAin4_posedge : VitalDelayType := 0 ns; + tpw_MAin4_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin4: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_4_B : ENTITY IS TRUE; + + end MAin_4_B; + + architecture Structure of MAin_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin4_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_4: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin4_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin4_ipd, MAin4, tipd_MAin4); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin4_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin4_MAin4 : x01 := '0'; + VARIABLE periodcheckinfo_MAin4 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin4_ipd, + TestSignalName => "MAin4", + Period => tperiod_MAin4, + PulseWidthHigh => tpw_MAin4_posedge, + PulseWidthLow => tpw_MAin4_negedge, + PeriodData => periodcheckinfo_MAin4, + Violation => tviol_MAin4_MAin4, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin4_ipd'last_event, + PathDelay => tpd_MAin4_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_3_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_3_B"; + + tipd_MAin3 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin3_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin3 : VitalDelayType := 0 ns; + tpw_MAin3_posedge : VitalDelayType := 0 ns; + tpw_MAin3_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin3: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_3_B : ENTITY IS TRUE; + + end MAin_3_B; + + architecture Structure of MAin_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin3_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_3: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin3_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin3_ipd, MAin3, tipd_MAin3); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin3_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin3_MAin3 : x01 := '0'; + VARIABLE periodcheckinfo_MAin3 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin3_ipd, + TestSignalName => "MAin3", + Period => tperiod_MAin3, + PulseWidthHigh => tpw_MAin3_posedge, + PulseWidthLow => tpw_MAin3_negedge, + PeriodData => periodcheckinfo_MAin3, + Violation => tviol_MAin3_MAin3, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin3_ipd'last_event, + PathDelay => tpd_MAin3_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_2_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_2_B"; + + tipd_MAin2 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin2_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin2 : VitalDelayType := 0 ns; + tpw_MAin2_posedge : VitalDelayType := 0 ns; + tpw_MAin2_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin2: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_2_B : ENTITY IS TRUE; + + end MAin_2_B; + + architecture Structure of MAin_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin2_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_2: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin2_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin2_ipd, MAin2, tipd_MAin2); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin2_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin2_MAin2 : x01 := '0'; + VARIABLE periodcheckinfo_MAin2 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin2_ipd, + TestSignalName => "MAin2", + Period => tperiod_MAin2, + PulseWidthHigh => tpw_MAin2_posedge, + PulseWidthLow => tpw_MAin2_negedge, + PeriodData => periodcheckinfo_MAin2, + Violation => tviol_MAin2_MAin2, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin2_ipd'last_event, + PathDelay => tpd_MAin2_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_1_B"; + + tipd_MAin1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin1 : VitalDelayType := 0 ns; + tpw_MAin1_posedge : VitalDelayType := 0 ns; + tpw_MAin1_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin1: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_1_B : ENTITY IS TRUE; + + end MAin_1_B; + + architecture Structure of MAin_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin1_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_1: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin1_ipd, MAin1, tipd_MAin1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin1_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin1_MAin1 : x01 := '0'; + VARIABLE periodcheckinfo_MAin1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin1_ipd, + TestSignalName => "MAin1", + Period => tperiod_MAin1, + PulseWidthHigh => tpw_MAin1_posedge, + PulseWidthLow => tpw_MAin1_negedge, + PeriodData => periodcheckinfo_MAin1, + Violation => tviol_MAin1_MAin1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin1_ipd'last_event, + PathDelay => tpd_MAin1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_0_B"; + + tipd_MAin0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin0 : VitalDelayType := 0 ns; + tpw_MAin0_posedge : VitalDelayType := 0 ns; + tpw_MAin0_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin0: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_0_B : ENTITY IS TRUE; + + end MAin_0_B; + + architecture Structure of MAin_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin0_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_0: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin0_ipd, MAin0, tipd_MAin0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin0_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin0_MAin0 : x01 := '0'; + VARIABLE periodcheckinfo_MAin0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin0_ipd, + TestSignalName => "MAin0", + Period => tperiod_MAin0, + PulseWidthHigh => tpw_MAin0_posedge, + PulseWidthLow => tpw_MAin0_negedge, + PeriodData => periodcheckinfo_MAin0, + Violation => tviol_MAin0_MAin0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin0_ipd'last_event, + PathDelay => tpd_MAin0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity CROW_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity CROW_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "CROW_1_B"; + + tipd_CROW1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CROW1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CROW1 : VitalDelayType := 0 ns; + tpw_CROW1_posedge : VitalDelayType := 0 ns; + tpw_CROW1_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; CROW1: in Std_logic); + + ATTRIBUTE Vital_Level0 OF CROW_1_B : ENTITY IS TRUE; + + end CROW_1_B; + + architecture Structure of CROW_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal CROW1_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + CROW_pad_1: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>CROW1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(CROW1_ipd, CROW1, tipd_CROW1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, CROW1_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_CROW1_CROW1 : x01 := '0'; + VARIABLE periodcheckinfo_CROW1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => CROW1_ipd, + TestSignalName => "CROW1", + Period => tperiod_CROW1, + PulseWidthHigh => tpw_CROW1_posedge, + PulseWidthLow => tpw_CROW1_negedge, + PeriodData => periodcheckinfo_CROW1, + Violation => tviol_CROW1_CROW1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => CROW1_ipd'last_event, + PathDelay => tpd_CROW1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity CROW_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity CROW_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "CROW_0_B"; + + tipd_CROW0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CROW0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CROW0 : VitalDelayType := 0 ns; + tpw_CROW0_posedge : VitalDelayType := 0 ns; + tpw_CROW0_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; CROW0: in Std_logic); + + ATTRIBUTE Vital_Level0 OF CROW_0_B : ENTITY IS TRUE; + + end CROW_0_B; + + architecture Structure of CROW_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal CROW0_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + CROW_pad_0: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>CROW0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(CROW0_ipd, CROW0, tipd_CROW0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, CROW0_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_CROW0_CROW0 : x01 := '0'; + VARIABLE periodcheckinfo_CROW0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => CROW0_ipd, + TestSignalName => "CROW0", + Period => tperiod_CROW0, + PulseWidthHigh => tpw_CROW0_posedge, + PulseWidthLow => tpw_CROW0_negedge, + PeriodData => periodcheckinfo_CROW0, + Violation => tviol_CROW0_CROW0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => CROW0_ipd'last_event, + PathDelay => tpd_CROW0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_7_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_7_B"; + + tipd_Din7 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din7_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din7 : VitalDelayType := 0 ns; + tpw_Din7_posedge : VitalDelayType := 0 ns; + tpw_Din7_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din7: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_7_B : ENTITY IS TRUE; + + end Din_7_B; + + architecture Structure of Din_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din7_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_7: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>Din7_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din7_ipd, Din7, tipd_Din7); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din7_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din7_Din7 : x01 := '0'; + VARIABLE periodcheckinfo_Din7 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din7_ipd, + TestSignalName => "Din7", + Period => tperiod_Din7, + PulseWidthHigh => tpw_Din7_posedge, + PulseWidthLow => tpw_Din7_negedge, + PeriodData => periodcheckinfo_Din7, + Violation => tviol_Din7_Din7, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din7_ipd'last_event, + PathDelay => tpd_Din7_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_6_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_6_B"; + + tipd_Din6 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din6_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din6 : VitalDelayType := 0 ns; + tpw_Din6_posedge : VitalDelayType := 0 ns; + tpw_Din6_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din6: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_6_B : ENTITY IS TRUE; + + end Din_6_B; + + architecture Structure of Din_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din6_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_6: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>Din6_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din6_ipd, Din6, tipd_Din6); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din6_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din6_Din6 : x01 := '0'; + VARIABLE periodcheckinfo_Din6 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din6_ipd, + TestSignalName => "Din6", + Period => tperiod_Din6, + PulseWidthHigh => tpw_Din6_posedge, + PulseWidthLow => tpw_Din6_negedge, + PeriodData => periodcheckinfo_Din6, + Violation => tviol_Din6_Din6, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din6_ipd'last_event, + PathDelay => tpd_Din6_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_5_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_5_B"; + + tipd_Din5 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din5_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din5 : VitalDelayType := 0 ns; + tpw_Din5_posedge : VitalDelayType := 0 ns; + tpw_Din5_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din5: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_5_B : ENTITY IS TRUE; + + end Din_5_B; + + architecture Structure of Din_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din5_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_5: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>Din5_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din5_ipd, Din5, tipd_Din5); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din5_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din5_Din5 : x01 := '0'; + VARIABLE periodcheckinfo_Din5 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din5_ipd, + TestSignalName => "Din5", + Period => tperiod_Din5, + PulseWidthHigh => tpw_Din5_posedge, + PulseWidthLow => tpw_Din5_negedge, + PeriodData => periodcheckinfo_Din5, + Violation => tviol_Din5_Din5, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din5_ipd'last_event, + PathDelay => tpd_Din5_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_4_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_4_B"; + + tipd_Din4 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din4_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din4 : VitalDelayType := 0 ns; + tpw_Din4_posedge : VitalDelayType := 0 ns; + tpw_Din4_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din4: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_4_B : ENTITY IS TRUE; + + end Din_4_B; + + architecture Structure of Din_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din4_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_4: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>Din4_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din4_ipd, Din4, tipd_Din4); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din4_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din4_Din4 : x01 := '0'; + VARIABLE periodcheckinfo_Din4 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din4_ipd, + TestSignalName => "Din4", + Period => tperiod_Din4, + PulseWidthHigh => tpw_Din4_posedge, + PulseWidthLow => tpw_Din4_negedge, + PeriodData => periodcheckinfo_Din4, + Violation => tviol_Din4_Din4, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din4_ipd'last_event, + PathDelay => tpd_Din4_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_3_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_3_B"; + + tipd_Din3 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din3_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din3 : VitalDelayType := 0 ns; + tpw_Din3_posedge : VitalDelayType := 0 ns; + tpw_Din3_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din3: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_3_B : ENTITY IS TRUE; + + end Din_3_B; + + architecture Structure of Din_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din3_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_3: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>Din3_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din3_ipd, Din3, tipd_Din3); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din3_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din3_Din3 : x01 := '0'; + VARIABLE periodcheckinfo_Din3 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din3_ipd, + TestSignalName => "Din3", + Period => tperiod_Din3, + PulseWidthHigh => tpw_Din3_posedge, + PulseWidthLow => tpw_Din3_negedge, + PeriodData => periodcheckinfo_Din3, + Violation => tviol_Din3_Din3, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din3_ipd'last_event, + PathDelay => tpd_Din3_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_2_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_2_B"; + + tipd_Din2 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din2_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din2 : VitalDelayType := 0 ns; + tpw_Din2_posedge : VitalDelayType := 0 ns; + tpw_Din2_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din2: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_2_B : ENTITY IS TRUE; + + end Din_2_B; + + architecture Structure of Din_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din2_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_2: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>Din2_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din2_ipd, Din2, tipd_Din2); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din2_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din2_Din2 : x01 := '0'; + VARIABLE periodcheckinfo_Din2 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din2_ipd, + TestSignalName => "Din2", + Period => tperiod_Din2, + PulseWidthHigh => tpw_Din2_posedge, + PulseWidthLow => tpw_Din2_negedge, + PeriodData => periodcheckinfo_Din2, + Violation => tviol_Din2_Din2, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din2_ipd'last_event, + PathDelay => tpd_Din2_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_1_B"; + + tipd_Din1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din1 : VitalDelayType := 0 ns; + tpw_Din1_posedge : VitalDelayType := 0 ns; + tpw_Din1_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din1: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_1_B : ENTITY IS TRUE; + + end Din_1_B; + + architecture Structure of Din_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din1_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_1: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>Din1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din1_ipd, Din1, tipd_Din1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din1_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din1_Din1 : x01 := '0'; + VARIABLE periodcheckinfo_Din1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din1_ipd, + TestSignalName => "Din1", + Period => tperiod_Din1, + PulseWidthHigh => tpw_Din1_posedge, + PulseWidthLow => tpw_Din1_negedge, + PeriodData => periodcheckinfo_Din1, + Violation => tviol_Din1_Din1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din1_ipd'last_event, + PathDelay => tpd_Din1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_0_B"; + + tipd_Din0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din0 : VitalDelayType := 0 ns; + tpw_Din0_posedge : VitalDelayType := 0 ns; + tpw_Din0_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din0: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_0_B : ENTITY IS TRUE; + + end Din_0_B; + + architecture Structure of Din_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din0_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_0: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>Din0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din0_ipd, Din0, tipd_Din0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din0_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din0_Din0 : x01 := '0'; + VARIABLE periodcheckinfo_Din0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din0_ipd, + TestSignalName => "Din0", + Period => tperiod_Din0, + PulseWidthHigh => tpw_Din0_posedge, + PulseWidthLow => tpw_Din0_negedge, + PeriodData => periodcheckinfo_Din0, + Violation => tviol_Din0_Din0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din0_ipd'last_event, + PathDelay => tpd_Din0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nCCASB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nCCASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nCCASB"; + + tipd_nCCASS : VitalDelayType01 := (0 ns, 0 ns); + tpd_nCCASS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nCCASS : VitalDelayType := 0 ns; + tpw_nCCASS_posedge : VitalDelayType := 0 ns; + tpw_nCCASS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; nCCASS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nCCASB : ENTITY IS TRUE; + + end nCCASB; + + architecture Structure of nCCASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal nCCASS_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + nCCAS_pad: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>nCCASS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(nCCASS_ipd, nCCASS, tipd_nCCASS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, nCCASS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_nCCASS_nCCASS : x01 := '0'; + VARIABLE periodcheckinfo_nCCASS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => nCCASS_ipd, + TestSignalName => "nCCASS", + Period => tperiod_nCCASS, + PulseWidthHigh => tpw_nCCASS_posedge, + PulseWidthLow => tpw_nCCASS_negedge, + PeriodData => periodcheckinfo_nCCASS, + Violation => tviol_nCCASS_nCCASS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => nCCASS_ipd'last_event, + PathDelay => tpd_nCCASS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nCRASB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nCRASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nCRASB"; + + tipd_nCRASS : VitalDelayType01 := (0 ns, 0 ns); + tpd_nCRASS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nCRASS : VitalDelayType := 0 ns; + tpw_nCRASS_posedge : VitalDelayType := 0 ns; + tpw_nCRASS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; nCRASS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nCRASB : ENTITY IS TRUE; + + end nCRASB; + + architecture Structure of nCRASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal nCRASS_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + nCRAS_pad: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>nCRASS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(nCRASS_ipd, nCRASS, tipd_nCRASS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, nCRASS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_nCRASS_nCRASS : x01 := '0'; + VARIABLE periodcheckinfo_nCRASS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => nCRASS_ipd, + TestSignalName => "nCRASS", + Period => tperiod_nCRASS, + PulseWidthHigh => tpw_nCRASS_posedge, + PulseWidthLow => tpw_nCRASS_negedge, + PeriodData => periodcheckinfo_nCRASS, + Violation => tviol_nCRASS_nCRASS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => nCRASS_ipd'last_event, + PathDelay => tpd_nCRASS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nFWEB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nFWEB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nFWEB"; + + tipd_nFWES : VitalDelayType01 := (0 ns, 0 ns); + tpd_nFWES_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nFWES : VitalDelayType := 0 ns; + tpw_nFWES_posedge : VitalDelayType := 0 ns; + tpw_nFWES_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; nFWES: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nFWEB : ENTITY IS TRUE; + + end nFWEB; + + architecture Structure of nFWEB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal nFWES_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + nFWE_pad: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>nFWES_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(nFWES_ipd, nFWES, tipd_nFWES); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, nFWES_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_nFWES_nFWES : x01 := '0'; + VARIABLE periodcheckinfo_nFWES : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => nFWES_ipd, + TestSignalName => "nFWES", + Period => tperiod_nFWES, + PulseWidthHigh => tpw_nFWES_posedge, + PulseWidthLow => tpw_nFWES_negedge, + PeriodData => periodcheckinfo_nFWES, + Violation => tviol_nFWES_nFWES, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => nFWES_ipd'last_event, + PathDelay => tpd_nFWES_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RCLKB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RCLKB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RCLKB"; + + tipd_RCLKS : VitalDelayType01 := (0 ns, 0 ns); + tpd_RCLKS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RCLKS : VitalDelayType := 0 ns; + tpw_RCLKS_posedge : VitalDelayType := 0 ns; + tpw_RCLKS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; RCLKS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RCLKB : ENTITY IS TRUE; + + end RCLKB; + + architecture Structure of RCLKB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal RCLKS_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + RCLK_pad: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>RCLKS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(RCLKS_ipd, RCLKS, tipd_RCLKS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, RCLKS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RCLKS_RCLKS : x01 := '0'; + VARIABLE periodcheckinfo_RCLKS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RCLKS_ipd, + TestSignalName => "RCLKS", + Period => tperiod_RCLKS, + PulseWidthHigh => tpw_RCLKS_posedge, + PulseWidthLow => tpw_RCLKS_negedge, + PeriodData => periodcheckinfo_RCLKS, + Violation => tviol_RCLKS_RCLKS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RCLKS_ipd'last_event, + PathDelay => tpd_RCLKS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity UFMSDOB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity UFMSDOB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "UFMSDOB"; + + tipd_UFMSDOS : VitalDelayType01 := (0 ns, 0 ns); + tpd_UFMSDOS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_UFMSDOS : VitalDelayType := 0 ns; + tpw_UFMSDOS_posedge : VitalDelayType := 0 ns; + tpw_UFMSDOS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; UFMSDOS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF UFMSDOB : ENTITY IS TRUE; + + end UFMSDOB; + + architecture Structure of UFMSDOB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal UFMSDOS_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + UFMSDO_pad: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>UFMSDOS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(UFMSDOS_ipd, UFMSDOS, tipd_UFMSDOS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, UFMSDOS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_UFMSDOS_UFMSDOS : x01 := '0'; + VARIABLE periodcheckinfo_UFMSDOS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => UFMSDOS_ipd, + TestSignalName => "UFMSDOS", + Period => tperiod_UFMSDOS, + PulseWidthHigh => tpw_UFMSDOS_posedge, + PulseWidthLow => tpw_UFMSDOS_negedge, + PeriodData => periodcheckinfo_UFMSDOS, + Violation => tviol_UFMSDOS_UFMSDOS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => UFMSDOS_ipd'last_event, + PathDelay => tpd_UFMSDOS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RAM2GS + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RAM2GS is + port (PHI2: in Std_logic; MAin: in Std_logic_vector (9 downto 0); + CROW: in Std_logic_vector (1 downto 0); + Din: in Std_logic_vector (7 downto 0); + Dout: out Std_logic_vector (7 downto 0); nCCAS: in Std_logic; + nCRAS: in Std_logic; nFWE: in Std_logic; LED: out Std_logic; + RBA: out Std_logic_vector (1 downto 0); + RA: out Std_logic_vector (11 downto 0); + RD: inout Std_logic_vector (7 downto 0); nRCS: out Std_logic; + RCLK: in Std_logic; RCKE: out Std_logic; nRWE: out Std_logic; + nRRAS: out Std_logic; nRCAS: out Std_logic; RDQMH: out Std_logic; + RDQML: out Std_logic; nUFMCS: out Std_logic; UFMCLK: out Std_logic; + UFMSDI: out Std_logic; UFMSDO: in Std_logic); + + + + end RAM2GS; + + architecture Structure of RAM2GS is + signal FS_14: Std_logic; + signal FS_13: Std_logic; + signal n81: Std_logic; + signal n82: Std_logic; + signal RCLK_c: Std_logic; + signal n1998: Std_logic; + signal n1999: Std_logic; + signal FS_12: Std_logic; + signal FS_11: Std_logic; + signal n83: Std_logic; + signal n84: Std_logic; + signal n1997: Std_logic; + signal FS_8: Std_logic; + signal FS_7: Std_logic; + signal n87: Std_logic; + signal n88: Std_logic; + signal n1995: Std_logic; + signal n1996: Std_logic; + signal FS_6: Std_logic; + signal FS_5: Std_logic; + signal n89: Std_logic; + signal n90: Std_logic; + signal n1994: Std_logic; + signal FS_2: Std_logic; + signal FS_1: Std_logic; + signal n93: Std_logic; + signal n94: Std_logic; + signal n1992: Std_logic; + signal n1993: Std_logic; + signal FS_0: Std_logic; + signal n95: Std_logic; + signal CASr2: Std_logic; + signal CASr3: Std_logic; + signal FS_10: Std_logic; + signal FS_9: Std_logic; + signal n85: Std_logic; + signal n86: Std_logic; + signal FS_17: Std_logic; + signal n78: Std_logic; + signal n2000: Std_logic; + signal FS_4: Std_logic; + signal FS_3: Std_logic; + signal n91: Std_logic; + signal n92: Std_logic; + signal FS_16: Std_logic; + signal FS_15: Std_logic; + signal n79: Std_logic; + signal n80: Std_logic; + signal Din_c_4: Std_logic; + signal Din_c_6: Std_logic; + signal Din_c_1: Std_logic; + signal Din_c_7: Std_logic; + signal n2382: Std_logic; + signal n8: Std_logic; + signal n2225: Std_logic; + signal n2180: Std_logic; + signal ADSubmitted_N_246: Std_logic; + signal PHI2_N_120_enable_2: Std_logic; + signal C1Submitted_N_237: Std_logic; + signal PHI2_c: Std_logic; + signal ADSubmitted: Std_logic; + signal n26: Std_logic; + signal MAin_c_5: Std_logic; + signal n22: Std_logic; + signal MAin_c_2: Std_logic; + signal MAin_c_1: Std_logic; + signal C1Submitted: Std_logic; + signal n2365: Std_logic; + signal nFWE_c: Std_logic; + signal n1398: Std_logic; + signal nCCAS_c: Std_logic; + signal nCCAS_N_3: Std_logic; + signal CASr: Std_logic; + signal n2254: Std_logic; + signal Din_c_5: Std_logic; + signal n2191: Std_logic; + signal n2183: Std_logic; + signal n15_adj_1: Std_logic; + signal n2208: Std_logic; + signal n2363: Std_logic; + signal CmdEnable_N_248: Std_logic; + signal PHI2_N_120_enable_1: Std_logic; + signal CmdEnable: Std_logic; + signal n2447_001_BUF1: Std_logic; + signal PHI2_N_120_enable_7: Std_logic; + signal CmdSubmitted: Std_logic; + signal n1314: Std_logic; + signal n8MEGEN: Std_logic; + signal Din_c_0: Std_logic; + signal Cmdn8MEGEN_N_264: Std_logic; + signal PHI2_N_120_enable_6: Std_logic; + signal Cmdn8MEGEN: Std_logic; + signal Din_c_3: Std_logic; + signal n2373: Std_logic; + signal nCRAS_c: Std_logic; + signal FWEr: Std_logic; + signal CBR: Std_logic; + signal n2447_000_BUF1: Std_logic; + signal RCLK_c_enable_28: Std_logic; + signal InitReady: Std_logic; + signal n2447: Std_logic; + signal RCLK_c_enable_16: Std_logic; + signal LEDEN: Std_logic; + signal nCRAS_c_inv: Std_logic; + signal RASr: Std_logic; + signal LED_c: Std_logic; + signal RASr2: Std_logic; + signal nRowColSel_N_35: Std_logic; + signal nRCAS_N_165: Std_logic; + signal Ready: Std_logic; + signal n2381: Std_logic; + signal nRCS_N_139: Std_logic; + signal n2036: Std_logic; + signal nRWE_N_177: Std_logic; + signal RA_0S: Std_logic; + signal XOR8MEG: Std_logic; + signal RA11_N_184: Std_logic; + signal RA_c: Std_logic; + signal n6_adj_2: Std_logic; + signal PHI2r2: Std_logic; + signal PHI2r3: Std_logic; + signal n15_adj_4: Std_logic; + signal RCKEEN_N_121: Std_logic; + signal RCLK_c_enable_6: Std_logic; + signal RCKEEN: Std_logic; + signal RCLK_c_enable_10: Std_logic; + signal RASr3: Std_logic; + signal RCKE_N_132: Std_logic; + signal PHI2r: Std_logic; + signal RCKE_c: Std_logic; + signal n2447_002_BUF1: Std_logic; + signal Ready_N_292: Std_logic; + signal n2267: Std_logic; + signal n13_adj_6: Std_logic; + signal CmdUFMCLK: Std_logic; + signal n1893: Std_logic; + signal UFMCLK_N_224: Std_logic; + signal n2366: Std_logic; + signal UFMCLK_c: Std_logic; + signal n10: Std_logic; + signal n7: Std_logic; + signal n4: Std_logic; + signal CmdUFMSDI: Std_logic; + signal n2174: Std_logic; + signal UFMSDI_N_231: Std_logic; + signal UFMSDI_c: Std_logic; + signal n2260: Std_logic; + signal Din_c_2: Std_logic; + signal XOR8MEG_N_110: Std_logic; + signal PHI2_N_120_enable_3: Std_logic; + signal n2375: Std_logic; + signal UFMSDO_c: Std_logic; + signal n2367: Std_logic; + signal n8MEGEN_N_91: Std_logic; + signal RCLK_c_enable_15: Std_logic; + signal nRCS_N_142: Std_logic; + signal nRCAS_N_166: Std_logic; + signal n2371: Std_logic; + signal nRCAS_N_161: Std_logic; + signal nRCAS_c: Std_logic; + signal nRCS_N_141: Std_logic; + signal nRCS_N_137: Std_logic; + signal nRCS_N_136: Std_logic; + signal nRCS_c: Std_logic; + signal n2379: Std_logic; + signal nRRAS_N_156: Std_logic; + signal nRRAS_c: Std_logic; + signal nRWE_N_178: Std_logic; + signal n1765: Std_logic; + signal nRWE_N_171: Std_logic; + signal RCLK_c_enable_5: Std_logic; + signal nRWE_c: Std_logic; + signal nRowColSel_N_34: Std_logic; + signal nRowColSel_N_33: Std_logic; + signal n2376: Std_logic; + signal n1060: Std_logic; + signal n2372: Std_logic; + signal n917: Std_logic; + signal nRowColSel: Std_logic; + signal nRowColSel_N_32: Std_logic; + signal n827: Std_logic; + signal n2227: Std_logic; + signal n1406: Std_logic; + signal Bank_3: Std_logic; + signal Bank_6: Std_logic; + signal n2287: Std_logic; + signal n13: Std_logic; + signal n2374: Std_logic; + signal n2368: Std_logic; + signal CmdUFMCS: Std_logic; + signal n64: Std_logic; + signal nUFMCS_N_199: Std_logic; + signal nUFMCS_c: Std_logic; + signal n6_adj_3: Std_logic; + signal Ready_N_296: Std_logic; + signal n2204: Std_logic; + signal n2369: Std_logic; + signal MAin_c_0: Std_logic; + signal PHI2_N_120_enable_8: Std_logic; + signal Bank_5: Std_logic; + signal n2277: Std_logic; + signal Bank_2: Std_logic; + signal n2220: Std_logic; + signal RowA_0: Std_logic; + signal RowA_1: Std_logic; + signal n2370: Std_logic; + signal n2228: Std_logic; + signal n732: Std_logic; + signal n733: Std_logic; + signal RCLK_c_enable_27: Std_logic; + signal n2055: Std_logic; + signal MAin_c_9: Std_logic; + signal MAin_c_8: Std_logic; + signal RowA_8: Std_logic; + signal RowA_9: Std_logic; + signal n2210: Std_logic; + signal nRWE_N_182: Std_logic; + signal nRCS_N_146: Std_logic; + signal n728: Std_logic; + signal n729: Std_logic; + signal n727: Std_logic; + signal n730: Std_logic; + signal n2378: Std_logic; + signal n726: Std_logic; + signal n12: Std_logic; + signal MAin_c_4: Std_logic; + signal RowA_4: Std_logic; + signal RowA_5: Std_logic; + signal n1277: Std_logic; + signal n4_adj_7: Std_logic; + signal n2377: Std_logic; + signal n738: Std_logic; + signal n737: Std_logic; + signal n14: Std_logic; + signal n15: Std_logic; + signal n6: Std_logic; + signal CROW_c_1: Std_logic; + signal CROW_c_0: Std_logic; + signal RBA_c_0: Std_logic; + signal RBA_c_1: Std_logic; + signal n7_adj_5: Std_logic; + signal n2362: Std_logic; + signal WRD_6: Std_logic; + signal WRD_7: Std_logic; + signal WRD_4: Std_logic; + signal WRD_5: Std_logic; + signal WRD_0: Std_logic; + signal WRD_1: Std_logic; + signal MAin_c_3: Std_logic; + signal RowA_2: Std_logic; + signal RowA_3: Std_logic; + signal WRD_2: Std_logic; + signal WRD_3: Std_logic; + signal RA_1_9: Std_logic; + signal Bank_0: Std_logic; + signal RDQML_c: Std_logic; + signal Bank_1: Std_logic; + signal n734: Std_logic; + signal n735: Std_logic; + signal RA_1_8: Std_logic; + signal RDQMH_c: Std_logic; + signal Bank_4: Std_logic; + signal MAin_c_7: Std_logic; + signal RowA_7: Std_logic; + signal RA_1_7: Std_logic; + signal Bank_7: Std_logic; + signal MAin_c_6: Std_logic; + signal RowA_6: Std_logic; + signal RA_1_6: Std_logic; + signal RA_1_5: Std_logic; + signal RA_1_0: Std_logic; + signal RA_1_4: Std_logic; + signal RA_1_1: Std_logic; + signal RA_1_3: Std_logic; + signal RA_1_2: Std_logic; + signal n984: Std_logic; + signal n736: Std_logic; + signal Dout_c: Std_logic; + signal Dout_0S: Std_logic; + signal Dout_1S: Std_logic; + signal Dout_2S: Std_logic; + signal Dout_3S: Std_logic; + signal Dout_4S: Std_logic; + signal Dout_5S: Std_logic; + signal Dout_6S: Std_logic; + signal VCCI: Std_logic; + component SLICE_0 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_1 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_2 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_3 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_4 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_5 + port (A1: in Std_logic; DI1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_6 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_7 + port (A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_8 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_9 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_10 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_15 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_16 + port (A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_19 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_20 + port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_24 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_25 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_26 + port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_27 + port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_30 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_32 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_33 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_35 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_36 + port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_37 + port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_44 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_45 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_50 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_57 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_59 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_61 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_62 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_64 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_65 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_66 + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_67 + port (B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic); + end component; + component SLICE_68 + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_69 + port (B1: in Std_logic; A1: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_70 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component i30_SLICE_71 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); + end component; + component SLICE_72 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_73 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_74 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_75 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_76 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_77 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_78 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_79 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_80 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_81 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_82 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_83 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_84 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_85 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_86 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_87 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_88 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_89 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_90 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_91 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_92 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_93 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_94 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_95 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_96 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_97 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_98 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_99 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_100 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_101 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_102 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_103 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_104 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_105 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_106 + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component RD_7_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD7: inout Std_logic); + end component; + component RD_6_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD6: inout Std_logic); + end component; + component RD_5_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD5: inout Std_logic); + end component; + component RD_4_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD4: inout Std_logic); + end component; + component RD_3_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD3: inout Std_logic); + end component; + component RD_2_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD2: inout Std_logic); + end component; + component RD_1_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD1: inout Std_logic); + end component; + component RD_0_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD0: inout Std_logic); + end component; + component Dout_7_B + port (PADDO: in Std_logic; Dout7: out Std_logic); + end component; + component Dout_6_B + port (PADDO: in Std_logic; Dout6: out Std_logic); + end component; + component Dout_5_B + port (PADDO: in Std_logic; Dout5: out Std_logic); + end component; + component Dout_4_B + port (PADDO: in Std_logic; Dout4: out Std_logic); + end component; + component Dout_3_B + port (PADDO: in Std_logic; Dout3: out Std_logic); + end component; + component Dout_2_B + port (PADDO: in Std_logic; Dout2: out Std_logic); + end component; + component Dout_1_B + port (PADDO: in Std_logic; Dout1: out Std_logic); + end component; + component Dout_0_B + port (PADDO: in Std_logic; Dout0: out Std_logic); + end component; + component LEDB + port (PADDO: in Std_logic; LEDS: out Std_logic); + end component; + component RBA_1_B + port (PADDO: in Std_logic; RBA1: out Std_logic); + end component; + component RBA_0_B + port (PADDO: in Std_logic; RBA0: out Std_logic); + end component; + component RA_11_B + port (PADDO: in Std_logic; RA11: out Std_logic); + end component; + component RA_10_B + port (PADDO: in Std_logic; RA10: out Std_logic); + end component; + component RA_9_B + port (PADDO: in Std_logic; RA9: out Std_logic); + end component; + component RA_8_B + port (PADDO: in Std_logic; RA8: out Std_logic); + end component; + component RA_7_B + port (PADDO: in Std_logic; RA7: out Std_logic); + end component; + component RA_6_B + port (PADDO: in Std_logic; RA6: out Std_logic); + end component; + component RA_5_B + port (PADDO: in Std_logic; RA5: out Std_logic); + end component; + component RA_4_B + port (PADDO: in Std_logic; RA4: out Std_logic); + end component; + component RA_3_B + port (PADDO: in Std_logic; RA3: out Std_logic); + end component; + component RA_2_B + port (PADDO: in Std_logic; RA2: out Std_logic); + end component; + component RA_1_B + port (PADDO: in Std_logic; RA1: out Std_logic); + end component; + component RA_0_B + port (PADDO: in Std_logic; RA0: out Std_logic); + end component; + component nRCSB + port (PADDO: in Std_logic; nRCSS: out Std_logic); + end component; + component RCKEB + port (PADDO: in Std_logic; RCKES: out Std_logic); + end component; + component nRWEB + port (PADDO: in Std_logic; nRWES: out Std_logic); + end component; + component nRRASB + port (PADDO: in Std_logic; nRRASS: out Std_logic); + end component; + component nRCASB + port (PADDO: in Std_logic; nRCASS: out Std_logic); + end component; + component RDQMHB + port (PADDO: in Std_logic; RDQMHS: out Std_logic); + end component; + component RDQMLB + port (PADDO: in Std_logic; RDQMLS: out Std_logic); + end component; + component nUFMCSB + port (PADDO: in Std_logic; nUFMCSS: out Std_logic); + end component; + component UFMCLKB + port (PADDO: in Std_logic; UFMCLKS: out Std_logic); + end component; + component UFMSDIB + port (PADDO: in Std_logic; UFMSDIS: out Std_logic); + end component; + component PHI2B + port (PADDI: out Std_logic; PHI2S: in Std_logic); + end component; + component MAin_9_B + port (PADDI: out Std_logic; MAin9: in Std_logic); + end component; + component MAin_8_B + port (PADDI: out Std_logic; MAin8: in Std_logic); + end component; + component MAin_7_B + port (PADDI: out Std_logic; MAin7: in Std_logic); + end component; + component MAin_6_B + port (PADDI: out Std_logic; MAin6: in Std_logic); + end component; + component MAin_5_B + port (PADDI: out Std_logic; MAin5: in Std_logic); + end component; + component MAin_4_B + port (PADDI: out Std_logic; MAin4: in Std_logic); + end component; + component MAin_3_B + port (PADDI: out Std_logic; MAin3: in Std_logic); + end component; + component MAin_2_B + port (PADDI: out Std_logic; MAin2: in Std_logic); + end component; + component MAin_1_B + port (PADDI: out Std_logic; MAin1: in Std_logic); + end component; + component MAin_0_B + port (PADDI: out Std_logic; MAin0: in Std_logic); + end component; + component CROW_1_B + port (PADDI: out Std_logic; CROW1: in Std_logic); + end component; + component CROW_0_B + port (PADDI: out Std_logic; CROW0: in Std_logic); + end component; + component Din_7_B + port (PADDI: out Std_logic; Din7: in Std_logic); + end component; + component Din_6_B + port (PADDI: out Std_logic; Din6: in Std_logic); + end component; + component Din_5_B + port (PADDI: out Std_logic; Din5: in Std_logic); + end component; + component Din_4_B + port (PADDI: out Std_logic; Din4: in Std_logic); + end component; + component Din_3_B + port (PADDI: out Std_logic; Din3: in Std_logic); + end component; + component Din_2_B + port (PADDI: out Std_logic; Din2: in Std_logic); + end component; + component Din_1_B + port (PADDI: out Std_logic; Din1: in Std_logic); + end component; + component Din_0_B + port (PADDI: out Std_logic; Din0: in Std_logic); + end component; + component nCCASB + port (PADDI: out Std_logic; nCCASS: in Std_logic); + end component; + component nCRASB + port (PADDI: out Std_logic; nCRASS: in Std_logic); + end component; + component nFWEB + port (PADDI: out Std_logic; nFWES: in Std_logic); + end component; + component RCLKB + port (PADDI: out Std_logic; RCLKS: in Std_logic); + end component; + component UFMSDOB + port (PADDI: out Std_logic; UFMSDOS: in Std_logic); + end component; + begin + SLICE_0I: SLICE_0 + port map (A1=>FS_14, A0=>FS_13, DI1=>n81, DI0=>n82, CLK=>RCLK_c, + FCI=>n1998, F0=>n82, Q0=>FS_13, F1=>n81, Q1=>FS_14, FCO=>n1999); + SLICE_1I: SLICE_1 + port map (A1=>FS_12, A0=>FS_11, DI1=>n83, DI0=>n84, CLK=>RCLK_c, + FCI=>n1997, F0=>n84, Q0=>FS_11, F1=>n83, Q1=>FS_12, FCO=>n1998); + SLICE_2I: SLICE_2 + port map (A1=>FS_8, A0=>FS_7, DI1=>n87, DI0=>n88, CLK=>RCLK_c, + FCI=>n1995, F0=>n88, Q0=>FS_7, F1=>n87, Q1=>FS_8, FCO=>n1996); + SLICE_3I: SLICE_3 + port map (A1=>FS_6, A0=>FS_5, DI1=>n89, DI0=>n90, CLK=>RCLK_c, + FCI=>n1994, F0=>n90, Q0=>FS_5, F1=>n89, Q1=>FS_6, FCO=>n1995); + SLICE_4I: SLICE_4 + port map (A1=>FS_2, A0=>FS_1, DI1=>n93, DI0=>n94, CLK=>RCLK_c, + FCI=>n1992, F0=>n94, Q0=>FS_1, F1=>n93, Q1=>FS_2, FCO=>n1993); + SLICE_5I: SLICE_5 + port map (A1=>FS_0, DI1=>n95, M0=>CASr2, CLK=>RCLK_c, Q0=>CASr3, F1=>n95, + Q1=>FS_0, FCO=>n1992); + SLICE_6I: SLICE_6 + port map (A1=>FS_10, A0=>FS_9, DI1=>n85, DI0=>n86, CLK=>RCLK_c, + FCI=>n1996, F0=>n86, Q0=>FS_9, F1=>n85, Q1=>FS_10, FCO=>n1997); + SLICE_7I: SLICE_7 + port map (A0=>FS_17, DI0=>n78, CLK=>RCLK_c, FCI=>n2000, F0=>n78, + Q0=>FS_17); + SLICE_8I: SLICE_8 + port map (A1=>FS_4, A0=>FS_3, DI1=>n91, DI0=>n92, CLK=>RCLK_c, + FCI=>n1993, F0=>n92, Q0=>FS_3, F1=>n91, Q1=>FS_4, FCO=>n1994); + SLICE_9I: SLICE_9 + port map (A1=>FS_16, A0=>FS_15, DI1=>n79, DI0=>n80, CLK=>RCLK_c, + FCI=>n1999, F0=>n80, Q0=>FS_15, F1=>n79, Q1=>FS_16, FCO=>n2000); + SLICE_10I: SLICE_10 + port map (D1=>Din_c_4, C1=>Din_c_6, B1=>Din_c_1, A1=>Din_c_7, D0=>n2382, + C0=>n8, B0=>n2225, A0=>n2180, DI0=>ADSubmitted_N_246, + CE=>PHI2_N_120_enable_2, LSR=>C1Submitted_N_237, CLK=>PHI2_c, + F0=>ADSubmitted_N_246, Q0=>ADSubmitted, F1=>n8); + SLICE_15I: SLICE_15 + port map (D1=>n26, C1=>MAin_c_5, B1=>n22, A1=>MAin_c_2, D0=>MAin_c_1, + C0=>C1Submitted, B0=>n2365, A0=>nFWE_c, DI0=>n1398, + LSR=>C1Submitted_N_237, CLK=>PHI2_c, F0=>n1398, + Q0=>C1Submitted, F1=>n2365); + SLICE_16I: SLICE_16 + port map (A0=>nCCAS_c, DI0=>nCCAS_N_3, M1=>CASr, CLK=>RCLK_c, + F0=>nCCAS_N_3, Q0=>CASr, Q1=>CASr2); + SLICE_19I: SLICE_19 + port map (D1=>n2254, C1=>Din_c_5, B1=>n2191, A1=>n2183, D0=>n15_adj_1, + C0=>n2208, B0=>MAin_c_1, A0=>n2363, DI0=>CmdEnable_N_248, + CE=>PHI2_N_120_enable_1, CLK=>PHI2_c, F0=>CmdEnable_N_248, + Q0=>CmdEnable, F1=>n15_adj_1); + SLICE_20I: SLICE_20 + port map (DI0=>n2447_001_BUF1, CE=>PHI2_N_120_enable_7, CLK=>PHI2_c, + F0=>n2447_001_BUF1, Q0=>CmdSubmitted); + SLICE_24I: SLICE_24 + port map (C1=>Din_c_5, B1=>Din_c_7, A1=>Din_c_6, D0=>n1314, C0=>Din_c_4, + B0=>n8MEGEN, A0=>Din_c_0, DI0=>Cmdn8MEGEN_N_264, + CE=>PHI2_N_120_enable_6, CLK=>PHI2_c, F0=>Cmdn8MEGEN_N_264, + Q0=>Cmdn8MEGEN, F1=>n1314); + SLICE_25I: SLICE_25 + port map (C1=>Din_c_3, B1=>Din_c_5, A1=>nFWE_c, A0=>nFWE_c, DI0=>n2373, + M1=>nCCAS_N_3, CLK=>nCRAS_c, F0=>n2373, Q0=>FWEr, F1=>n2180, + Q1=>CBR); + SLICE_26I: SLICE_26 + port map (DI0=>n2447_000_BUF1, CE=>RCLK_c_enable_28, CLK=>RCLK_c, + F0=>n2447_000_BUF1, Q0=>InitReady); + SLICE_27I: SLICE_27 + port map (DI0=>n2447, CE=>RCLK_c_enable_16, CLK=>RCLK_c, F0=>n2447, + Q0=>LEDEN); + SLICE_30I: SLICE_30 + port map (C1=>CBR, B1=>LEDEN, A1=>nCRAS_c, A0=>nCRAS_c, DI0=>nCRAS_c_inv, + M1=>RASr, CLK=>RCLK_c, F0=>nCRAS_c_inv, Q0=>RASr, F1=>LED_c, + Q1=>RASr2); + SLICE_32I: SLICE_32 + port map (C1=>nRowColSel_N_35, B1=>InitReady, A1=>RASr2, D0=>nRCAS_N_165, + C0=>Ready, B0=>n2381, A0=>nRCS_N_139, DI0=>n2036, + LSR=>nRWE_N_177, CLK=>RCLK_c, F0=>n2036, Q0=>RA_0S, F1=>n2381); + SLICE_33I: SLICE_33 + port map (C1=>Din_c_4, B1=>Din_c_7, A1=>Din_c_6, C0=>n8MEGEN, + B0=>XOR8MEG, A0=>Din_c_6, DI0=>RA11_N_184, LSR=>Ready, + CLK=>PHI2_c, F0=>RA11_N_184, Q0=>RA_c, F1=>n6_adj_2); + SLICE_35I: SLICE_35 + port map (D1=>InitReady, C1=>CmdSubmitted, B1=>PHI2r2, A1=>PHI2r3, + C0=>Ready, B0=>n15_adj_4, A0=>InitReady, DI0=>RCKEEN_N_121, + CE=>RCLK_c_enable_6, CLK=>RCLK_c, F0=>RCKEEN_N_121, Q0=>RCKEEN, + F1=>RCLK_c_enable_10); + SLICE_36I: SLICE_36 + port map (D0=>RASr3, C0=>RASr2, B0=>RCKEEN, A0=>RASr, DI0=>RCKE_N_132, + M1=>PHI2r, CLK=>RCLK_c, F0=>RCKE_N_132, Q0=>RCKE_c, Q1=>PHI2r2); + SLICE_37I: SLICE_37 + port map (DI0=>n2447_002_BUF1, CE=>Ready_N_292, CLK=>RCLK_c, + F0=>n2447_002_BUF1, Q0=>Ready); + SLICE_44I: SLICE_44 + port map (D1=>FS_1, C1=>n2267, B1=>n13_adj_6, A1=>FS_4, C0=>InitReady, + B0=>CmdUFMCLK, A0=>n1893, DI0=>UFMCLK_N_224, + CE=>RCLK_c_enable_10, LSR=>n2366, CLK=>RCLK_c, + F0=>UFMCLK_N_224, Q0=>UFMCLK_c, F1=>n1893); + SLICE_45I: SLICE_45 + port map (D1=>n10, C1=>FS_10, B1=>FS_8, A1=>n7, D0=>n4, C0=>InitReady, + B0=>CmdUFMSDI, A0=>n2174, DI0=>UFMSDI_N_231, + CE=>RCLK_c_enable_10, LSR=>n2366, CLK=>RCLK_c, + F0=>UFMSDI_N_231, Q0=>UFMSDI_c, F1=>n2174); + SLICE_50I: SLICE_50 + port map (D1=>LEDEN, C1=>n1314, B1=>Din_c_1, A1=>Din_c_4, D0=>Din_c_3, + C0=>n2260, B0=>Din_c_2, A0=>Din_c_0, DI0=>XOR8MEG_N_110, + CE=>PHI2_N_120_enable_3, CLK=>PHI2_c, F0=>XOR8MEG_N_110, + Q0=>XOR8MEG, F1=>n2260); + SLICE_57I: SLICE_57 + port map (D1=>FS_10, C1=>FS_11, B1=>n2375, A1=>n10, D0=>Cmdn8MEGEN, + C0=>UFMSDO_c, B0=>n2367, A0=>InitReady, DI0=>n8MEGEN_N_91, + CE=>RCLK_c_enable_15, CLK=>RCLK_c, F0=>n8MEGEN_N_91, + Q0=>n8MEGEN, F1=>n2367); + SLICE_59I: SLICE_59 + port map (D1=>CBR, C1=>nRowColSel_N_35, B1=>RASr2, A1=>nRCS_N_142, + D0=>nRCAS_N_166, C0=>Ready, B0=>nRCAS_N_165, A0=>n2371, + DI0=>nRCAS_N_161, CE=>RCLK_c_enable_6, CLK=>RCLK_c, + F0=>nRCAS_N_161, Q0=>nRCAS_c, F1=>nRCAS_N_166); + SLICE_61I: SLICE_61 + port map (D1=>nRCS_N_142, C1=>nRowColSel_N_35, B1=>RASr2, A1=>RCKE_c, + C0=>Ready, B0=>nRCS_N_141, A0=>nRCS_N_137, DI0=>nRCS_N_136, + CE=>RCLK_c_enable_6, CLK=>RCLK_c, F0=>nRCS_N_136, Q0=>nRCS_c, + F1=>nRCS_N_141); + SLICE_62I: SLICE_62 + port map (D1=>RASr2, C1=>nRowColSel_N_35, B1=>InitReady, A1=>nRCS_N_139, + D0=>nRowColSel_N_35, C0=>Ready, B0=>n2379, A0=>nRCS_N_137, + DI0=>nRRAS_N_156, CE=>RCLK_c_enable_6, CLK=>RCLK_c, + F0=>nRRAS_N_156, Q0=>nRRAS_c, F1=>nRCS_N_137); + SLICE_64I: SLICE_64 + port map (B1=>nRCAS_N_165, A1=>nRWE_N_177, D0=>n2371, C0=>Ready, + B0=>nRWE_N_178, A0=>n1765, DI0=>nRWE_N_171, + CE=>RCLK_c_enable_5, CLK=>RCLK_c, F0=>nRWE_N_171, Q0=>nRWE_c, + F1=>n1765); + SLICE_65I: SLICE_65 + port map (B1=>nRowColSel_N_34, A1=>nRowColSel_N_33, D0=>n2376, C0=>n1060, + B0=>n2372, A0=>FWEr, DI0=>n917, CE=>RCLK_c_enable_5, + CLK=>RCLK_c, F0=>n917, Q0=>nRowColSel, F1=>n1060); + SLICE_66I: SLICE_66 + port map (B1=>CASr2, A1=>nRowColSel_N_33, B0=>nRowColSel_N_32, + A0=>nRowColSel_N_33, DI0=>n827, LSR=>RASr2, CLK=>RCLK_c, + F0=>n827, Q0=>nRowColSel_N_32, F1=>n2227); + SLICE_67I: SLICE_67 + port map (B0=>nRowColSel_N_32, A0=>RASr2, DI0=>n1406, + LSR=>nRowColSel_N_34, CLK=>RCLK_c, F0=>n1406, + Q0=>nRowColSel_N_33); + SLICE_68I: SLICE_68 + port map (B1=>FS_0, A1=>FS_8, B0=>Bank_3, A0=>Bank_6, M0=>n1406, + LSR=>nRowColSel_N_35, CLK=>RCLK_c, F0=>n2287, + Q0=>nRowColSel_N_34, F1=>n13); + SLICE_69I: SLICE_69 + port map (B1=>RASr2, A1=>RCKE_c, A0=>RASr2, DI0=>n2374, M1=>PHI2r2, + CLK=>RCLK_c, F0=>n2374, Q0=>nRowColSel_N_35, F1=>n2379, + Q1=>PHI2r3); + SLICE_70I: SLICE_70 + port map (D1=>FS_10, C1=>InitReady, B1=>n2368, A1=>FS_11, D0=>InitReady, + C0=>CmdUFMCS, B0=>n64, A0=>n13_adj_6, DI0=>nUFMCS_N_199, + CE=>RCLK_c_enable_10, CLK=>RCLK_c, F0=>nUFMCS_N_199, + Q0=>nUFMCS_c, F1=>n64); + i30_SLICE_71I: i30_SLICE_71 + port map (C1=>RASr2, B1=>FWEr, A1=>CBR, D0=>nRowColSel_N_34, C0=>FWEr, + B0=>n2227, A0=>CBR, M0=>nRowColSel_N_35, OFX0=>n15_adj_4); + SLICE_72I: SLICE_72 + port map (D1=>Ready, C1=>nRowColSel_N_32, B1=>n6_adj_3, A1=>RASr2, + B0=>Ready_N_296, A0=>InitReady, F0=>n6_adj_3, F1=>Ready_N_292); + SLICE_73I: SLICE_73 + port map (D1=>n2204, C1=>n2180, B1=>n26, A1=>n2369, D0=>n6_adj_2, + C0=>CmdEnable, B0=>MAin_c_0, A0=>MAin_c_1, F0=>n2204, + F1=>PHI2_N_120_enable_8); + SLICE_74I: SLICE_74 + port map (D1=>Bank_5, C1=>n2287, B1=>n2277, A1=>Bank_2, D0=>nFWE_c, + C0=>n2204, B0=>n26, A0=>n2369, M1=>MAin_c_1, M0=>MAin_c_0, + LSR=>Ready, CLK=>nCRAS_c, F0=>n2220, Q0=>RowA_0, F1=>n26, + Q1=>RowA_1); + SLICE_75I: SLICE_75 + port map (D1=>n2370, C1=>n2183, B1=>n2228, A1=>Din_c_5, B0=>Din_c_3, + A0=>Din_c_6, M1=>n732, M0=>n733, CE=>RCLK_c_enable_27, + CLK=>RCLK_c, F0=>n2183, Q0=>n732, F1=>n2055, Q1=>nRWE_N_177); + SLICE_76I: SLICE_76 + port map (C1=>n10, B1=>FS_14, A1=>FS_12, D0=>InitReady, C0=>n2368, + B0=>FS_11, A0=>FS_10, M1=>MAin_c_9, M0=>MAin_c_8, LSR=>Ready, + CLK=>nCRAS_c, F0=>RCLK_c_enable_16, Q0=>RowA_8, F1=>n2368, + Q1=>RowA_9); + SLICE_77I: SLICE_77 + port map (D1=>n2208, C1=>C1Submitted, B1=>n2191, A1=>Din_c_5, + D0=>MAin_c_0, C0=>Din_c_6, B0=>Din_c_3, A0=>Din_c_2, F0=>n2191, + F1=>n2210); + SLICE_78I: SLICE_78 + port map (D1=>nRowColSel_N_35, C1=>nRWE_N_182, B1=>n1060, A1=>nRCS_N_146, + B0=>RASr2, A0=>RCKE_c, M1=>n728, M0=>n729, + CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>nRWE_N_182, Q0=>n728, + F1=>nRWE_N_178, Q1=>n727); + SLICE_79I: SLICE_79 + port map (C1=>MAin_c_5, B1=>n22, A1=>MAin_c_2, D0=>MAin_c_1, C0=>nFWE_c, + B0=>n26, A0=>n2369, M1=>n730, M0=>nRWE_N_177, + CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>PHI2_N_120_enable_2, + Q0=>n730, F1=>n2369, Q1=>n729); + SLICE_80I: SLICE_80 + port map (B1=>FS_14, A1=>FS_12, D0=>FS_11, C0=>InitReady, B0=>n2375, + A0=>n10, F0=>n2366, F1=>n2375); + SLICE_81I: SLICE_81 + port map (B1=>CBR, A1=>FWEr, D0=>nRowColSel_N_33, C0=>n2378, + B0=>nRowColSel_N_34, A0=>nRCS_N_146, M1=>n726, M0=>n727, + CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>nRCS_N_142, Q0=>n726, + F1=>n2378, Q1=>Ready_N_296); + SLICE_82I: SLICE_82 + port map (D1=>FS_17, C1=>FS_14, B1=>n12, A1=>FS_11, B0=>n13_adj_6, + A0=>FS_10, M1=>MAin_c_5, M0=>MAin_c_4, LSR=>Ready, + CLK=>nCRAS_c, F0=>RCLK_c_enable_28, Q0=>RowA_4, F1=>n13_adj_6, + Q1=>RowA_5); + SLICE_83I: SLICE_83 + port map (D1=>n1314, C1=>n1277, B1=>CmdEnable, A1=>n2228, D0=>MAin_c_1, + C0=>MAin_c_0, B0=>n26, A0=>n2369, F0=>n1277, + F1=>PHI2_N_120_enable_3); + SLICE_84I: SLICE_84 + port map (C1=>CmdSubmitted, B1=>PHI2r2, A1=>PHI2r3, D0=>n4_adj_7, + C0=>InitReady, B0=>n2377, A0=>n2367, M1=>n738, M0=>nRCAS_N_165, + CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>RCLK_c_enable_15, + Q0=>n738, F1=>n2377, Q1=>n737); + SLICE_85I: SLICE_85 + port map (D1=>n10, C1=>FS_11, B1=>FS_14, A1=>FS_12, D0=>FS_16, C0=>FS_15, + B0=>FS_13, A0=>FS_17, F0=>n10, F1=>n2267); + SLICE_86I: SLICE_86 + port map (C1=>FS_6, B1=>FS_9, A1=>FS_3, D0=>n14, C0=>n13, B0=>n15, + A0=>FS_4, M1=>RASr2, M0=>PHI2_c, CLK=>RCLK_c, F0=>n4_adj_7, + Q0=>PHI2r, F1=>n14, Q1=>RASr3); + SLICE_87I: SLICE_87 + port map (D1=>n6, C1=>nRowColSel_N_32, B1=>nRowColSel_N_33, + A1=>nRowColSel_N_35, B0=>nRowColSel_N_34, A0=>Ready, + M1=>CROW_c_1, M0=>CROW_c_0, LSR=>Ready, CLK=>nCRAS_c, F0=>n6, + Q0=>RBA_c_0, F1=>RCLK_c_enable_6, Q1=>RBA_c_1); + SLICE_88I: SLICE_88 + port map (D1=>n2363, C1=>C1Submitted_N_237, B1=>ADSubmitted, + A1=>n7_adj_5, D0=>n2362, C0=>MAin_c_0, B0=>n2055, A0=>Din_c_2, + M1=>Din_c_7, M0=>Din_c_6, CLK=>nCCAS_c, F0=>C1Submitted_N_237, + Q0=>WRD_6, F1=>PHI2_N_120_enable_1, Q1=>WRD_7); + SLICE_89I: SLICE_89 + port map (D1=>Din_c_5, C1=>Din_c_3, B1=>Din_c_4, A1=>n2220, D0=>Din_c_3, + C0=>Din_c_4, B0=>n2220, A0=>Din_c_5, M1=>Din_c_5, M0=>Din_c_4, + CLK=>nCCAS_c, F0=>PHI2_N_120_enable_6, Q0=>WRD_4, + F1=>PHI2_N_120_enable_7, Q1=>WRD_5); + SLICE_90I: SLICE_90 + port map (D1=>Din_c_0, C1=>Din_c_4, B1=>Din_c_1, A1=>Din_c_7, + C0=>Din_c_0, B0=>Din_c_1, A0=>Din_c_7, M1=>Din_c_1, + M0=>Din_c_0, CLK=>nCCAS_c, F0=>n2370, Q0=>WRD_0, F1=>n2208, + Q1=>WRD_1); + SLICE_91I: SLICE_91 + port map (C1=>MAin_c_1, B1=>n26, A1=>n2369, D0=>MAin_c_1, C0=>MAin_c_0, + B0=>n26, A0=>n2369, M1=>MAin_c_3, M0=>MAin_c_2, LSR=>Ready, + CLK=>nCRAS_c, F0=>n2225, Q0=>RowA_2, F1=>n2362, Q1=>RowA_3); + SLICE_92I: SLICE_92 + port map (D1=>Ready, C1=>nRowColSel_N_35, B1=>InitReady, A1=>RASr2, + D0=>nRCS_N_139, C0=>nRowColSel_N_35, B0=>InitReady, A0=>RASr2, + M1=>Din_c_3, M0=>Din_c_2, CLK=>nCCAS_c, F0=>n2371, Q0=>WRD_2, + F1=>RCLK_c_enable_27, Q1=>WRD_3); + SLICE_93I: SLICE_93 + port map (B1=>nRowColSel, A1=>MAin_c_9, C0=>nRowColSel, B0=>MAin_c_9, + A0=>RowA_9, M1=>Din_c_1, M0=>Din_c_0, CLK=>PHI2_c, F0=>RA_1_9, + Q0=>Bank_0, F1=>RDQML_c, Q1=>Bank_1); + SLICE_94I: SLICE_94 + port map (B1=>nRowColSel_N_35, A1=>Ready, D0=>nRowColSel_N_35, + C0=>nRowColSel_N_32, B0=>n1060, A0=>Ready, F0=>RCLK_c_enable_5, + F1=>n2372); + SLICE_95I: SLICE_95 + port map (D1=>FS_5, C1=>FS_9, B1=>FS_7, A1=>n2375, D0=>FS_2, C0=>FS_1, + B0=>FS_7, A0=>FS_5, F0=>n15, F1=>n7); + SLICE_96I: SLICE_96 + port map (B1=>CASr3, A1=>CBR, D0=>CASr2, C0=>FWEr, B0=>CASr3, A0=>CBR, + F0=>nRCS_N_146, F1=>n2376); + SLICE_97I: SLICE_97 + port map (C1=>MAin_c_1, B1=>n2210, A1=>MAin_c_0, B0=>Din_c_2, + A0=>MAin_c_0, M1=>n734, M0=>n735, CE=>RCLK_c_enable_27, + CLK=>RCLK_c, F0=>n2254, Q0=>n734, F1=>n7_adj_5, Q1=>n733); + SLICE_98I: SLICE_98 + port map (B1=>nRowColSel, A1=>MAin_c_9, C0=>nRowColSel, B0=>MAin_c_8, + A0=>RowA_8, M1=>nRCS_N_139, M0=>Ready_N_296, + CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>RA_1_8, Q0=>nRCS_N_139, + F1=>RDQMH_c, Q1=>nRCAS_N_165); + SLICE_99I: SLICE_99 + port map (D1=>Bank_1, C1=>Bank_4, B1=>MAin_c_3, A1=>MAin_c_7, + C0=>nRowColSel, B0=>MAin_c_7, A0=>RowA_7, M0=>Din_c_0, + CE=>PHI2_N_120_enable_8, CLK=>PHI2_c, F0=>RA_1_7, + Q0=>CmdUFMSDI, F1=>n22); + SLICE_100I: SLICE_100 + port map (D1=>Bank_0, C1=>Bank_7, B1=>MAin_c_4, A1=>MAin_c_6, + C0=>nRowColSel, B0=>MAin_c_6, A0=>RowA_6, M1=>Din_c_2, + M0=>Din_c_1, CE=>PHI2_N_120_enable_8, CLK=>PHI2_c, F0=>RA_1_6, + Q0=>CmdUFMCLK, F1=>n2277, Q1=>CmdUFMCS); + SLICE_101I: SLICE_101 + port map (C1=>nRowColSel, B1=>MAin_c_0, A1=>RowA_0, C0=>nRowColSel, + B0=>MAin_c_5, A0=>RowA_5, M1=>Din_c_7, M0=>Din_c_6, + CLK=>PHI2_c, F0=>RA_1_5, Q0=>Bank_6, F1=>RA_1_0, Q1=>Bank_7); + SLICE_102I: SLICE_102 + port map (C1=>nRowColSel, B1=>MAin_c_1, A1=>RowA_1, C0=>nRowColSel, + B0=>MAin_c_4, A0=>RowA_4, M1=>Din_c_5, M0=>Din_c_4, + CLK=>PHI2_c, F0=>RA_1_4, Q0=>Bank_4, F1=>RA_1_1, Q1=>Bank_5); + SLICE_103I: SLICE_103 + port map (C1=>nRowColSel, B1=>MAin_c_2, A1=>RowA_2, C0=>nRowColSel, + B0=>MAin_c_3, A0=>RowA_3, M1=>Din_c_3, M0=>Din_c_2, + CLK=>PHI2_c, F0=>RA_1_3, Q0=>Bank_2, F1=>RA_1_2, Q1=>Bank_3); + SLICE_104I: SLICE_104 + port map (B1=>nFWE_c, A1=>nCCAS_c, C0=>nFWE_c, B0=>n26, A0=>n2369, + M1=>MAin_c_7, M0=>MAin_c_6, LSR=>Ready, CLK=>nCRAS_c, + F0=>n2363, Q0=>RowA_6, F1=>n984, Q1=>RowA_7); + SLICE_105I: SLICE_105 + port map (B1=>FS_6, A1=>FS_11, D0=>FS_16, C0=>FS_15, B0=>FS_12, + A0=>FS_13, F0=>n12, F1=>n4); + SLICE_106I: SLICE_106 + port map (B1=>Din_c_2, A1=>Din_c_0, B0=>Din_c_4, A0=>nFWE_c, M1=>n736, + M0=>n737, CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>n2228, + Q0=>n736, F1=>n2382, Q1=>n735); + RD_7_I: RD_7_B + port map (PADDI=>Dout_c, PADDT=>n984, PADDO=>WRD_7, RD7=>RD(7)); + RD_6_I: RD_6_B + port map (PADDI=>Dout_0S, PADDT=>n984, PADDO=>WRD_6, RD6=>RD(6)); + RD_5_I: RD_5_B + port map (PADDI=>Dout_1S, PADDT=>n984, PADDO=>WRD_5, RD5=>RD(5)); + RD_4_I: RD_4_B + port map (PADDI=>Dout_2S, PADDT=>n984, PADDO=>WRD_4, RD4=>RD(4)); + RD_3_I: RD_3_B + port map (PADDI=>Dout_3S, PADDT=>n984, PADDO=>WRD_3, RD3=>RD(3)); + RD_2_I: RD_2_B + port map (PADDI=>Dout_4S, PADDT=>n984, PADDO=>WRD_2, RD2=>RD(2)); + RD_1_I: RD_1_B + port map (PADDI=>Dout_5S, PADDT=>n984, PADDO=>WRD_1, RD1=>RD(1)); + RD_0_I: RD_0_B + port map (PADDI=>Dout_6S, PADDT=>n984, PADDO=>WRD_0, RD0=>RD(0)); + Dout_7_I: Dout_7_B + port map (PADDO=>Dout_c, Dout7=>Dout(7)); + Dout_6_I: Dout_6_B + port map (PADDO=>Dout_0S, Dout6=>Dout(6)); + Dout_5_I: Dout_5_B + port map (PADDO=>Dout_1S, Dout5=>Dout(5)); + Dout_4_I: Dout_4_B + port map (PADDO=>Dout_2S, Dout4=>Dout(4)); + Dout_3_I: Dout_3_B + port map (PADDO=>Dout_3S, Dout3=>Dout(3)); + Dout_2_I: Dout_2_B + port map (PADDO=>Dout_4S, Dout2=>Dout(2)); + Dout_1_I: Dout_1_B + port map (PADDO=>Dout_5S, Dout1=>Dout(1)); + Dout_0_I: Dout_0_B + port map (PADDO=>Dout_6S, Dout0=>Dout(0)); + LEDI: LEDB + port map (PADDO=>LED_c, LEDS=>LED); + RBA_1_I: RBA_1_B + port map (PADDO=>RBA_c_1, RBA1=>RBA(1)); + RBA_0_I: RBA_0_B + port map (PADDO=>RBA_c_0, RBA0=>RBA(0)); + RA_11_I: RA_11_B + port map (PADDO=>RA_c, RA11=>RA(11)); + RA_10_I: RA_10_B + port map (PADDO=>RA_0S, RA10=>RA(10)); + RA_9_I: RA_9_B + port map (PADDO=>RA_1_9, RA9=>RA(9)); + RA_8_I: RA_8_B + port map (PADDO=>RA_1_8, RA8=>RA(8)); + RA_7_I: RA_7_B + port map (PADDO=>RA_1_7, RA7=>RA(7)); + RA_6_I: RA_6_B + port map (PADDO=>RA_1_6, RA6=>RA(6)); + RA_5_I: RA_5_B + port map (PADDO=>RA_1_5, RA5=>RA(5)); + RA_4_I: RA_4_B + port map (PADDO=>RA_1_4, RA4=>RA(4)); + RA_3_I: RA_3_B + port map (PADDO=>RA_1_3, RA3=>RA(3)); + RA_2_I: RA_2_B + port map (PADDO=>RA_1_2, RA2=>RA(2)); + RA_1_I: RA_1_B + port map (PADDO=>RA_1_1, RA1=>RA(1)); + RA_0_I: RA_0_B + port map (PADDO=>RA_1_0, RA0=>RA(0)); + nRCSI: nRCSB + port map (PADDO=>nRCS_c, nRCSS=>nRCS); + RCKEI: RCKEB + port map (PADDO=>RCKE_c, RCKES=>RCKE); + nRWEI: nRWEB + port map (PADDO=>nRWE_c, nRWES=>nRWE); + nRRASI: nRRASB + port map (PADDO=>nRRAS_c, nRRASS=>nRRAS); + nRCASI: nRCASB + port map (PADDO=>nRCAS_c, nRCASS=>nRCAS); + RDQMHI: RDQMHB + port map (PADDO=>RDQMH_c, RDQMHS=>RDQMH); + RDQMLI: RDQMLB + port map (PADDO=>RDQML_c, RDQMLS=>RDQML); + nUFMCSI: nUFMCSB + port map (PADDO=>nUFMCS_c, nUFMCSS=>nUFMCS); + UFMCLKI: UFMCLKB + port map (PADDO=>UFMCLK_c, UFMCLKS=>UFMCLK); + UFMSDII: UFMSDIB + port map (PADDO=>UFMSDI_c, UFMSDIS=>UFMSDI); + PHI2I: PHI2B + port map (PADDI=>PHI2_c, PHI2S=>PHI2); + MAin_9_I: MAin_9_B + port map (PADDI=>MAin_c_9, MAin9=>MAin(9)); + MAin_8_I: MAin_8_B + port map (PADDI=>MAin_c_8, MAin8=>MAin(8)); + MAin_7_I: MAin_7_B + port map (PADDI=>MAin_c_7, MAin7=>MAin(7)); + MAin_6_I: MAin_6_B + port map (PADDI=>MAin_c_6, MAin6=>MAin(6)); + MAin_5_I: MAin_5_B + port map (PADDI=>MAin_c_5, MAin5=>MAin(5)); + MAin_4_I: MAin_4_B + port map (PADDI=>MAin_c_4, MAin4=>MAin(4)); + MAin_3_I: MAin_3_B + port map (PADDI=>MAin_c_3, MAin3=>MAin(3)); + MAin_2_I: MAin_2_B + port map (PADDI=>MAin_c_2, MAin2=>MAin(2)); + MAin_1_I: MAin_1_B + port map (PADDI=>MAin_c_1, MAin1=>MAin(1)); + MAin_0_I: MAin_0_B + port map (PADDI=>MAin_c_0, MAin0=>MAin(0)); + CROW_1_I: CROW_1_B + port map (PADDI=>CROW_c_1, CROW1=>CROW(1)); + CROW_0_I: CROW_0_B + port map (PADDI=>CROW_c_0, CROW0=>CROW(0)); + Din_7_I: Din_7_B + port map (PADDI=>Din_c_7, Din7=>Din(7)); + Din_6_I: Din_6_B + port map (PADDI=>Din_c_6, Din6=>Din(6)); + Din_5_I: Din_5_B + port map (PADDI=>Din_c_5, Din5=>Din(5)); + Din_4_I: Din_4_B + port map (PADDI=>Din_c_4, Din4=>Din(4)); + Din_3_I: Din_3_B + port map (PADDI=>Din_c_3, Din3=>Din(3)); + Din_2_I: Din_2_B + port map (PADDI=>Din_c_2, Din2=>Din(2)); + Din_1_I: Din_1_B + port map (PADDI=>Din_c_1, Din1=>Din(1)); + Din_0_I: Din_0_B + port map (PADDI=>Din_c_0, Din0=>Din(0)); + nCCASI: nCCASB + port map (PADDI=>nCCAS_c, nCCASS=>nCCAS); + nCRASI: nCRASB + port map (PADDI=>nCRAS_c, nCRASS=>nCRAS); + nFWEI: nFWEB + port map (PADDI=>nFWE_c, nFWES=>nFWE); + RCLKI: RCLKB + port map (PADDI=>RCLK_c, RCLKS=>RCLK); + UFMSDOI: UFMSDOB + port map (PADDI=>UFMSDO_c, UFMSDOS=>UFMSDO); + VHI_INST: VHI + port map (Z=>VCCI); + PUR_INST: PUR + port map (PUR=>VCCI); + GSR_INST: GSR + port map (GSR=>VCCI); + end Structure; + + + + library IEEE, vital2000, MACHXO2; + configuration Structure_CON of RAM2GS is + for Structure + end for; + end Structure_CON; + + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.sdf b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.sdf new file mode 100644 index 0000000..357899e --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.sdf @@ -0,0 +1,3176 @@ +(DELAYFILE + (SDFVERSION "3.0") + (DESIGN "RAM2GS") + (DATE "Tue Aug 15 05:03:30 2023") + (VENDOR "Lattice") + (PROGRAM "ldbanno") + (VERSION "Diamond (64-bit) 3.12.1.454") + (DIVIDER /) + (VOLTAGE 1.26:1.20:1.14) + (PROCESS "default") + (TEMPERATURE -40:25:85) + (TIMESCALE 1ps) + (CELL + (CELLTYPE "SLICE_0") + (INSTANCE SLICE_0) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_1") + (INSTANCE SLICE_1) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_2") + (INSTANCE SLICE_2) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_3") + (INSTANCE SLICE_3) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_4") + (INSTANCE SLICE_4) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_5") + (INSTANCE SLICE_5) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_6") + (INSTANCE SLICE_6) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_7") + (INSTANCE SLICE_7) + (DELAY + (ABSOLUTE + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_8") + (INSTANCE SLICE_8) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_9") + (INSTANCE SLICE_9) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_10") + (INSTANCE SLICE_10) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_15") + (INSTANCE SLICE_15) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_16") + (INSTANCE SLICE_16) + (DELAY + (ABSOLUTE + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_19") + (INSTANCE SLICE_19) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_20") + (INSTANCE SLICE_20) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_24") + (INSTANCE SLICE_24) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_25") + (INSTANCE SLICE_25) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_26") + (INSTANCE SLICE_26) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_27") + (INSTANCE SLICE_27) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_30") + (INSTANCE SLICE_30) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_32") + (INSTANCE SLICE_32) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_33") + (INSTANCE SLICE_33) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_35") + (INSTANCE SLICE_35) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_36") + (INSTANCE SLICE_36) + (DELAY + (ABSOLUTE + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_37") + (INSTANCE SLICE_37) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_44") + (INSTANCE SLICE_44) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_45") + (INSTANCE SLICE_45) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_50") + (INSTANCE SLICE_50) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_57") + (INSTANCE SLICE_57) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_59") + (INSTANCE SLICE_59) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_61") + (INSTANCE SLICE_61) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_62") + (INSTANCE SLICE_62) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_64") + (INSTANCE SLICE_64) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_65") + (INSTANCE SLICE_65) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_66") + (INSTANCE SLICE_66) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_67") + (INSTANCE SLICE_67) + (DELAY + (ABSOLUTE + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_68") + (INSTANCE SLICE_68) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_69") + (INSTANCE SLICE_69) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_70") + (INSTANCE SLICE_70) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "i30_SLICE_71") + (INSTANCE i30\/SLICE_71) + (DELAY + (ABSOLUTE + (IOPATH C1 OFX0 (457:589:721)(457:589:721)) + (IOPATH B1 OFX0 (457:589:721)(457:589:721)) + (IOPATH A1 OFX0 (457:589:721)(457:589:721)) + (IOPATH D0 OFX0 (457:589:721)(457:589:721)) + (IOPATH C0 OFX0 (457:589:721)(457:589:721)) + (IOPATH B0 OFX0 (457:589:721)(457:589:721)) + (IOPATH A0 OFX0 (457:589:721)(457:589:721)) + (IOPATH M0 OFX0 (322:349:376)(322:349:376)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_72") + (INSTANCE SLICE_72) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_73") + (INSTANCE SLICE_73) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_74") + (INSTANCE SLICE_74) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_75") + (INSTANCE SLICE_75) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_76") + (INSTANCE SLICE_76) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_77") + (INSTANCE SLICE_77) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_78") + (INSTANCE SLICE_78) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_79") + (INSTANCE SLICE_79) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_80") + (INSTANCE SLICE_80) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_81") + (INSTANCE SLICE_81) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_82") + (INSTANCE SLICE_82) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_83") + (INSTANCE SLICE_83) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_84") + (INSTANCE SLICE_84) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_85") + (INSTANCE SLICE_85) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_86") + (INSTANCE SLICE_86) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_87") + (INSTANCE SLICE_87) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_88") + (INSTANCE SLICE_88) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_89") + (INSTANCE SLICE_89) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_90") + (INSTANCE SLICE_90) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_91") + (INSTANCE SLICE_91) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_92") + (INSTANCE SLICE_92) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_93") + (INSTANCE SLICE_93) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_94") + (INSTANCE SLICE_94) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_95") + (INSTANCE SLICE_95) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_96") + (INSTANCE SLICE_96) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_97") + (INSTANCE SLICE_97) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_98") + (INSTANCE SLICE_98) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_99") + (INSTANCE SLICE_99) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_100") + (INSTANCE SLICE_100) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_101") + (INSTANCE SLICE_101) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_102") + (INSTANCE SLICE_102) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_103") + (INSTANCE SLICE_103) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_104") + (INSTANCE SLICE_104) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_105") + (INSTANCE SLICE_105) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_106") + (INSTANCE SLICE_106) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_7_") + (INSTANCE RD\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD7 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD7 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD7 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD7) (3330:3330:3330)) + (WIDTH (negedge RD7) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_6_") + (INSTANCE RD\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD6 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD6 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD6 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD6) (3330:3330:3330)) + (WIDTH (negedge RD6) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_5_") + (INSTANCE RD\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD5 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD5 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD5 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD5) (3330:3330:3330)) + (WIDTH (negedge RD5) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_4_") + (INSTANCE RD\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD4 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD4 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD4 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD4) (3330:3330:3330)) + (WIDTH (negedge RD4) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_3_") + (INSTANCE RD\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD3 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD3 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD3 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD3) (3330:3330:3330)) + (WIDTH (negedge RD3) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_2_") + (INSTANCE RD\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD2 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD2 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD2 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD2) (3330:3330:3330)) + (WIDTH (negedge RD2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_1_") + (INSTANCE RD\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD1 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD1 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD1 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD1) (3330:3330:3330)) + (WIDTH (negedge RD1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_0_") + (INSTANCE RD\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD0 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD0 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD0 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD0) (3330:3330:3330)) + (WIDTH (negedge RD0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Dout_7_") + (INSTANCE Dout\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout7 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_6_") + (INSTANCE Dout\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout6 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_5_") + (INSTANCE Dout\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout5 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_4_") + (INSTANCE Dout\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout4 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_3_") + (INSTANCE Dout\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout3 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_2_") + (INSTANCE Dout\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout2 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_1_") + (INSTANCE Dout\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout1 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_0_") + (INSTANCE Dout\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout0 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "LED") + (INSTANCE LED_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO LED (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_1_") + (INSTANCE RBA\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RBA1 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_0_") + (INSTANCE RBA\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RBA0 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_11_") + (INSTANCE RA\[11\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA11 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_10_") + (INSTANCE RA\[10\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA10 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_9_") + (INSTANCE RA\[9\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA9 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_8_") + (INSTANCE RA\[8\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA8 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_7_") + (INSTANCE RA\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA7 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_6_") + (INSTANCE RA\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA6 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_5_") + (INSTANCE RA\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA5 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_4_") + (INSTANCE RA\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA4 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_3_") + (INSTANCE RA\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA3 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_2_") + (INSTANCE RA\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA2 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_1_") + (INSTANCE RA\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA1 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_0_") + (INSTANCE RA\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA0 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nRCS") + (INSTANCE nRCS_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRCS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RCKE") + (INSTANCE RCKE_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RCKE (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nRWE") + (INSTANCE nRWE_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRWE (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nRRAS") + (INSTANCE nRRAS_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRRAS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nRCAS") + (INSTANCE nRCAS_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRCAS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RDQMH") + (INSTANCE RDQMH_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RDQMH (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RDQML") + (INSTANCE RDQML_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RDQML (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nUFMCS") + (INSTANCE nUFMCS_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nUFMCS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "UFMCLK") + (INSTANCE UFMCLK_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO UFMCLK (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "UFMSDI") + (INSTANCE UFMSDI_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO UFMSDI (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "PHI2") + (INSTANCE PHI2_I) + (DELAY + (ABSOLUTE + (IOPATH PHI2 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge PHI2) (3330:3330:3330)) + (WIDTH (negedge PHI2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_9_") + (INSTANCE MAin\[9\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin9 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin9) (3330:3330:3330)) + (WIDTH (negedge MAin9) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_8_") + (INSTANCE MAin\[8\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin8 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin8) (3330:3330:3330)) + (WIDTH (negedge MAin8) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_7_") + (INSTANCE MAin\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin7 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin7) (3330:3330:3330)) + (WIDTH (negedge MAin7) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_6_") + (INSTANCE MAin\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin6 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin6) (3330:3330:3330)) + (WIDTH (negedge MAin6) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_5_") + (INSTANCE MAin\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin5 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin5) (3330:3330:3330)) + (WIDTH (negedge MAin5) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_4_") + (INSTANCE MAin\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin4 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin4) (3330:3330:3330)) + (WIDTH (negedge MAin4) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_3_") + (INSTANCE MAin\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin3 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin3) (3330:3330:3330)) + (WIDTH (negedge MAin3) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_2_") + (INSTANCE MAin\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin2 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin2) (3330:3330:3330)) + (WIDTH (negedge MAin2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_1_") + (INSTANCE MAin\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin1 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin1) (3330:3330:3330)) + (WIDTH (negedge MAin1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_0_") + (INSTANCE MAin\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin0 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin0) (3330:3330:3330)) + (WIDTH (negedge MAin0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "CROW_1_") + (INSTANCE CROW\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH CROW1 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW1) (3330:3330:3330)) + (WIDTH (negedge CROW1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "CROW_0_") + (INSTANCE CROW\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH CROW0 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW0) (3330:3330:3330)) + (WIDTH (negedge CROW0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_7_") + (INSTANCE Din\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din7 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din7) (3330:3330:3330)) + (WIDTH (negedge Din7) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_6_") + (INSTANCE Din\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din6 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din6) (3330:3330:3330)) + (WIDTH (negedge Din6) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_5_") + (INSTANCE Din\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din5 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din5) (3330:3330:3330)) + (WIDTH (negedge Din5) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_4_") + (INSTANCE Din\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din4 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din4) (3330:3330:3330)) + (WIDTH (negedge Din4) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_3_") + (INSTANCE Din\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din3 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din3) (3330:3330:3330)) + (WIDTH (negedge Din3) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_2_") + (INSTANCE Din\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din2 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din2) (3330:3330:3330)) + (WIDTH (negedge Din2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_1_") + (INSTANCE Din\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din1 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din1) (3330:3330:3330)) + (WIDTH (negedge Din1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_0_") + (INSTANCE Din\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din0 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din0) (3330:3330:3330)) + (WIDTH (negedge Din0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nCCAS") + (INSTANCE nCCAS_I) + (DELAY + (ABSOLUTE + (IOPATH nCCAS PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nCCAS) (3330:3330:3330)) + (WIDTH (negedge nCCAS) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nCRAS") + (INSTANCE nCRAS_I) + (DELAY + (ABSOLUTE + (IOPATH nCRAS PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nCRAS) (3330:3330:3330)) + (WIDTH (negedge nCRAS) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nFWE") + (INSTANCE nFWE_I) + (DELAY + (ABSOLUTE + (IOPATH nFWE PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nFWE) (3330:3330:3330)) + (WIDTH (negedge nFWE) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RCLK") + (INSTANCE RCLK_I) + (DELAY + (ABSOLUTE + (IOPATH RCLK PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RCLK) (3330:3330:3330)) + (WIDTH (negedge RCLK) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "UFMSDO") + (INSTANCE UFMSDO_I) + (DELAY + (ABSOLUTE + (IOPATH UFMSDO PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge UFMSDO) (3330:3330:3330)) + (WIDTH (negedge UFMSDO) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RAM2GS") + (INSTANCE ) + (DELAY + (ABSOLUTE + (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_76/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_80/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_82/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_85/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q0 SLICE_0/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q0 SLICE_85/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q0 SLICE_105/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/F1 SLICE_0/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/F0 SLICE_0/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_0/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_1/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_2/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_3/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_4/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_5/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_6/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_7/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_8/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_9/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_16/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_26/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_27/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_30/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_32/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_35/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_36/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_37/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_44/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_45/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_57/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_59/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_61/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_62/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_64/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_65/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_66/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_67/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_68/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_69/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_70/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_75/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_78/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_79/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_81/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_84/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_86/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_97/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_98/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_106/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/FCO SLICE_0/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/FCO SLICE_9/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_1/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_76/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_80/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_85/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_105/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_57/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_70/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_76/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_80/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_82/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_85/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_105/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/F1 SLICE_1/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/F0 SLICE_1/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/FCO SLICE_1/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_45/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_68/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_95/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_95/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/F1 SLICE_2/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/F0 SLICE_2/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/FCO SLICE_2/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/FCO SLICE_6/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_86/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_105/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_95/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_95/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/F1 SLICE_3/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/F0 SLICE_3/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/FCO SLICE_3/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_95/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q0 SLICE_44/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q0 SLICE_95/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/F1 SLICE_4/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/F0 SLICE_4/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/FCO SLICE_4/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/FCO SLICE_8/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_68/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/F1 SLICE_5/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/Q1 SLICE_5/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/Q1 SLICE_66/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/Q1 SLICE_96/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_96/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_96/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_6/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_45/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_57/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_70/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_76/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_82/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q0 SLICE_6/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q0 SLICE_86/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q0 SLICE_95/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/F1 SLICE_6/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/F0 SLICE_6/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q0 SLICE_7/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q0 SLICE_82/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q0 SLICE_85/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/F0 SLICE_7/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/FCO SLICE_7/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q1 SLICE_8/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q1 SLICE_44/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q1 SLICE_86/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q0 SLICE_8/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q0 SLICE_86/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/F1 SLICE_8/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/F0 SLICE_8/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q1 SLICE_9/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q1 SLICE_85/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q1 SLICE_105/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q0 SLICE_9/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q0 SLICE_85/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q0 SLICE_105/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/F1 SLICE_9/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/F0 SLICE_9/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_10/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_24/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_33/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_50/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_89/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_89/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_89/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_90/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_102/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_106/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_10/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_24/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_33/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_33/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_75/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_77/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_88/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_101/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_10/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_50/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_90/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_90/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_90/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_93/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_100/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_10/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_24/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_33/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_88/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_90/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_90/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_101/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106/F1 SLICE_10/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_10/F1 SLICE_10/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/F0 SLICE_10/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_10/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_73/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_10/F0 SLICE_10/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F0 SLICE_10/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F0 SLICE_10/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F0 SLICE_15/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F0 SLICE_88/C1 (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_10/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_15/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_19/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_20/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_24/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_33/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_50/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_86/M0 (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_93/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_99/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_100/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_101/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_102/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_103/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_10/Q0 SLICE_88/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_15/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_73/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_74/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_79/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_83/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_91/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_91/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_104/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_15/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_79/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_82/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_101/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/F1 SLICE_15/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/F1 SLICE_79/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_15/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_79/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_91/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_103/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_15/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_19/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_73/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_74/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_79/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_83/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_91/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_91/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_97/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_102/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_15/Q0 SLICE_15/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_15/Q0 SLICE_77/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_15/F1 SLICE_15/B0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_15/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_25/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_25/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_74/D0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_79/C0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_104/B1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_104/C0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_106/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_15/F0 SLICE_15/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_16/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_88/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_89/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_90/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_92/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_104/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/F0 SLICE_16/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/F0 SLICE_25/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/Q0 SLICE_16/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/F0 SLICE_19/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_19/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_24/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_25/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_75/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_77/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_89/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_89/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_89/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_102/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/F0 SLICE_19/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/F0 SLICE_77/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/F0 SLICE_19/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/F0 SLICE_75/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/F1 SLICE_19/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/F1 SLICE_19/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/F1 SLICE_77/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F0 SLICE_19/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F0 SLICE_88/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/F0 SLICE_19/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F1 SLICE_19/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/Q0 SLICE_73/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/Q0 SLICE_83/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_20/F0 SLICE_20/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/F1 SLICE_20/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_20/Q0 SLICE_35/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_20/Q0 SLICE_84/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24/F1 SLICE_24/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24/F1 SLICE_50/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24/F1 SLICE_83/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57/Q0 SLICE_24/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57/Q0 SLICE_33/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_24/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_50/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_90/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_90/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_90/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_93/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_99/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_106/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24/F0 SLICE_24/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/F0 SLICE_24/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24/Q0 SLICE_57/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_25/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_50/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_75/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_77/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_89/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_89/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_92/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_103/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F0 SLICE_25/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_25/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_30/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_30/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_74/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_76/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_82/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_87/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_91/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_104/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_65/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 i30\/SLICE_71/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 i30\/SLICE_71/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_81/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_96/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q1 SLICE_30/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q1 SLICE_59/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q1 i30\/SLICE_71/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q1 i30\/SLICE_71/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q1 SLICE_81/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q1 SLICE_96/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q1 SLICE_96/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/F0 SLICE_26/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F0 SLICE_26/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_32/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_35/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_35/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_44/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_45/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_57/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_62/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_70/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_70/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_72/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_76/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_80/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_84/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_92/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_92/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_27/F0 SLICE_27/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/F0 SLICE_27/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_27/Q0 SLICE_30/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_27/Q0 SLICE_50/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/F0 SLICE_30/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q0 SLICE_30/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q0 SLICE_36/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/F1 LED_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_32/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_36/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_59/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_61/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_62/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_66/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_67/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_69/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_69/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 i30\/SLICE_71/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_72/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_78/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_86/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_92/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_92/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_32/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_59/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_61/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_62/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_62/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_68/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 i30\/SLICE_71/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_78/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_87/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_92/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_92/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_94/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_94/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 SLICE_32/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 SLICE_59/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 SLICE_64/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 SLICE_84/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_32/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_33/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_35/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_59/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_61/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_62/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_64/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_72/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_74/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_76/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_82/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_87/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_87/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_91/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_92/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_94/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_94/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_104/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32/F1 SLICE_32/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_32/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_62/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_92/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_98/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32/F0 SLICE_32/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/Q1 SLICE_32/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/Q1 SLICE_64/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/Q1 SLICE_79/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32/Q0 RA\[10\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_50/Q0 SLICE_33/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_33/F0 SLICE_33/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_33/Q0 RA\[11\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_33/F1 SLICE_73/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q1 SLICE_35/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q1 SLICE_69/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q1 SLICE_84/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q1 SLICE_35/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q1 SLICE_84/A1 (0:0:0)(0:0:0)) + (INTERCONNECT i30\/SLICE_71/OFX0 SLICE_35/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/F0 SLICE_35/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/F1 SLICE_35/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/F1 SLICE_59/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/F1 SLICE_61/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/F1 SLICE_62/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/Q0 SLICE_36/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/F1 SLICE_44/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/F1 SLICE_45/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/F1 SLICE_70/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/Q1 SLICE_36/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/F0 SLICE_36/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/Q0 SLICE_36/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_61/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_69/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_78/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 RCKE_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/F0 SLICE_37/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_72/F1 SLICE_37/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F1 SLICE_44/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F1 SLICE_44/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F1 SLICE_70/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F1 SLICE_82/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/Q0 SLICE_44/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/F1 SLICE_44/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/F0 SLICE_44/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F0 SLICE_44/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F0 SLICE_45/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/Q0 UFMCLK_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F0 SLICE_45/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F0 SLICE_57/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F0 SLICE_76/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F0 SLICE_80/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F0 SLICE_85/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95/F1 SLICE_45/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 SLICE_45/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/Q0 SLICE_45/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_45/F1 SLICE_45/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_45/F0 SLICE_45/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_45/Q0 UFMSDI_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_50/F1 SLICE_50/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_50/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_77/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_88/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_92/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_97/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_100/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_103/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_106/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_50/F0 SLICE_50/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/F1 SLICE_50/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F1 SLICE_57/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F1 SLICE_80/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F1 SLICE_95/A1 (0:0:0)(0:0:0)) + (INTERCONNECT UFMSDO_I/PADDI SLICE_57/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57/F1 SLICE_57/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57/F1 SLICE_84/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57/F0 SLICE_57/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/F0 SLICE_57/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F0 SLICE_59/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F0 SLICE_61/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_59/F1 SLICE_59/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F0 SLICE_59/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F0 SLICE_64/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_59/F0 SLICE_59/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_59/Q0 nRCAS_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61/F1 SLICE_61/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62/F1 SLICE_61/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62/F1 SLICE_62/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61/F0 SLICE_61/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61/Q0 nRCS_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/F1 SLICE_62/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62/F0 SLICE_62/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62/Q0 nRRAS_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/F1 SLICE_64/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/F1 SLICE_64/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/F0 SLICE_64/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94/F0 SLICE_64/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94/F0 SLICE_65/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 nRWE_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_65/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_67/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 i30\/SLICE_71/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_81/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_87/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_65/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_66/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_66/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_81/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_87/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/F1 SLICE_65/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/F1 SLICE_65/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/F1 SLICE_78/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/F1 SLICE_94/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94/F1 SLICE_65/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/F0 SLICE_65/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_93/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_93/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_98/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_98/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_99/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_100/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_101/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_101/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_102/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_102/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_103/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_103/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_66/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_67/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_72/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_87/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_94/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/F0 SLICE_66/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/F1 i30\/SLICE_71/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/F0 SLICE_67/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/F0 SLICE_68/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/Q1 SLICE_68/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/Q0 SLICE_68/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/F0 SLICE_74/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/F1 SLICE_86/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/F0 SLICE_69/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/F1 SLICE_70/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/F1 SLICE_76/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/Q1 SLICE_70/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_70/F1 SLICE_70/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_70/F0 SLICE_70/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_70/Q0 nUFMCS_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_72/F0 SLICE_72/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/Q1 SLICE_72/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/Q1 SLICE_98/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73/F0 SLICE_73/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73/F0 SLICE_74/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_73/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_74/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_79/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_83/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_91/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_91/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_104/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_73/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_74/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_77/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_83/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_88/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_91/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_97/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_97/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_101/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73/F1 SLICE_99/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73/F1 SLICE_100/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/Q1 SLICE_74/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F1 SLICE_74/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/Q0 SLICE_74/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F0 SLICE_89/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F0 SLICE_89/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_101/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q1 SLICE_102/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/F0 SLICE_75/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106/F0 SLICE_75/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106/F0 SLICE_83/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/Q0 SLICE_75/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/Q1 SLICE_75/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_75/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_78/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_79/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_81/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_84/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_97/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_98/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_106/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/F1 SLICE_88/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_76/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_93/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_93/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_98/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[8\]_I/PADDI SLICE_76/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[8\]_I/PADDI SLICE_98/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/Q0 SLICE_98/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/Q1 SLICE_93/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/F1 SLICE_97/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/F0 SLICE_78/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/F0 SLICE_78/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/F0 SLICE_81/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/Q0 SLICE_78/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/Q1 SLICE_78/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/Q1 SLICE_81/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/Q0 SLICE_79/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F1 SLICE_81/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/Q0 SLICE_81/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F0 SLICE_82/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_82/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_100/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_102/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/Q0 SLICE_102/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/Q1 SLICE_101/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/F0 SLICE_83/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/F0 SLICE_84/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/F1 SLICE_84/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/Q0 SLICE_84/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/Q1 SLICE_106/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/F1 SLICE_86/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95/F0 SLICE_86/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/F0 SLICE_87/D1 (0:0:0)(0:0:0)) + (INTERCONNECT CROW\[1\]_I/PADDI SLICE_87/M1 (0:0:0)(0:0:0)) + (INTERCONNECT CROW\[0\]_I/PADDI SLICE_87/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q0 RBA\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q1 RBA\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/F1 SLICE_88/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/F1 SLICE_88/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/Q0 RD\[6\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/Q1 RD\[7\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/Q0 RD\[4\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/Q1 RD\[5\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/Q0 RD\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/Q1 RD\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_91/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_99/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_103/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/Q0 SLICE_103/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/Q1 SLICE_103/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/Q0 RD\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/Q1 RD\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/F0 RA\[9\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/Q0 SLICE_100/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/F1 RDQML_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/Q1 SLICE_99/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/Q0 SLICE_97/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106/Q1 SLICE_97/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/F0 RA\[8\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/F1 RDQMH_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/Q0 SLICE_99/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_99/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_99/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_104/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/Q1 SLICE_99/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/F0 RA\[7\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/Q1 SLICE_100/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_100/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_100/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_104/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/Q0 SLICE_100/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F0 RA\[6\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/F0 RA\[5\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/F1 RA\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/F0 RA\[4\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/F1 RA\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/F0 RA\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/F1 RA\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 RD\[7\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 RD\[6\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 RD\[5\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 RD\[4\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 RD\[3\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 RD\[2\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 RD\[1\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 RD\[0\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106/Q0 SLICE_106/M1 (0:0:0)(0:0:0)) + (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (0:0:0)(0:0:0)) + ) + ) + ) +) diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo new file mode 100644 index 0000000..ec046df --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo @@ -0,0 +1,3692 @@ + +// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 + +// ldbanno -n Verilog -o RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd +// Netlist created on Tue Aug 15 05:03:26 2023 +// Netlist written on Tue Aug 15 05:03:29 2023 +// Design is for device LCMXO2-1200HC +// Design is for package TQFP100 +// Design is for performance grade 4 + +`timescale 1 ns / 1 ps + +module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, + RD, nRCS, RCLK, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, + UFMCLK, UFMSDI, UFMSDO ); + input PHI2; + input [9:0] MAin; + input [1:0] CROW; + input [7:0] Din; + input nCCAS, nCRAS, nFWE, RCLK, UFMSDO; + output [7:0] Dout; + output LED; + output [1:0] RBA; + output [11:0] RA; + output nRCS, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI; + inout [7:0] RD; + wire FS_14, FS_13, n81, n82, RCLK_c, n1998, n1999, FS_12, FS_11, n83, n84, + n1997, FS_8, FS_7, n87, n88, n1995, n1996, FS_6, FS_5, n89, n90, + n1994, FS_2, FS_1, n93, n94, n1992, n1993, FS_0, n95, CASr2, CASr3, + FS_10, FS_9, n85, n86, FS_17, n78, n2000, FS_4, FS_3, n91, n92, FS_16, + FS_15, n79, n80, Din_c_4, Din_c_6, Din_c_1, Din_c_7, n2382, n8, n2225, + n2180, ADSubmitted_N_246, PHI2_N_120_enable_2, C1Submitted_N_237, + PHI2_c, ADSubmitted, n26, MAin_c_5, n22, MAin_c_2, MAin_c_1, + C1Submitted, n2365, nFWE_c, n1398, nCCAS_c, nCCAS_N_3, CASr, n2254, + Din_c_5, n2191, n2183, n15_adj_1, n2208, n2363, CmdEnable_N_248, + PHI2_N_120_enable_1, CmdEnable, \n2447\001/BUF1 , PHI2_N_120_enable_7, + CmdSubmitted, n1314, n8MEGEN, Din_c_0, Cmdn8MEGEN_N_264, + PHI2_N_120_enable_6, Cmdn8MEGEN, Din_c_3, n2373, nCRAS_c, FWEr, CBR, + \n2447\000/BUF1 , RCLK_c_enable_28, InitReady, n2447, + RCLK_c_enable_16, LEDEN, nCRAS_c__inv, RASr, LED_c, RASr2, + nRowColSel_N_35, nRCAS_N_165, Ready, n2381, nRCS_N_139, n2036, + nRWE_N_177, RA_0, XOR8MEG, RA11_N_184, RA_c, n6_adj_2, PHI2r2, PHI2r3, + n15_adj_4, RCKEEN_N_121, RCLK_c_enable_6, RCKEEN, RCLK_c_enable_10, + RASr3, RCKE_N_132, PHI2r, RCKE_c, \n2447\002/BUF1 , Ready_N_292, + n2267, n13_adj_6, CmdUFMCLK, n1893, UFMCLK_N_224, n2366, UFMCLK_c, + n10, n7, n4, CmdUFMSDI, n2174, UFMSDI_N_231, UFMSDI_c, n2260, Din_c_2, + XOR8MEG_N_110, PHI2_N_120_enable_3, n2375, UFMSDO_c, n2367, + n8MEGEN_N_91, RCLK_c_enable_15, nRCS_N_142, nRCAS_N_166, n2371, + nRCAS_N_161, nRCAS_c, nRCS_N_141, nRCS_N_137, nRCS_N_136, nRCS_c, + n2379, nRRAS_N_156, nRRAS_c, nRWE_N_178, n1765, nRWE_N_171, + RCLK_c_enable_5, nRWE_c, nRowColSel_N_34, nRowColSel_N_33, n2376, + n1060, n2372, n917, nRowColSel, nRowColSel_N_32, n827, n2227, n1406, + Bank_3, Bank_6, n2287, n13, n2374, n2368, CmdUFMCS, n64, nUFMCS_N_199, + nUFMCS_c, n6_adj_3, Ready_N_296, n2204, n2369, MAin_c_0, + PHI2_N_120_enable_8, Bank_5, n2277, Bank_2, n2220, RowA_0, RowA_1, + n2370, n2228, n732, n733, RCLK_c_enable_27, n2055, MAin_c_9, MAin_c_8, + RowA_8, RowA_9, n2210, nRWE_N_182, nRCS_N_146, n728, n729, n727, n730, + n2378, n726, n12, MAin_c_4, RowA_4, RowA_5, n1277, n4_adj_7, n2377, + n738, n737, n14, n15, n6, CROW_c_1, CROW_c_0, RBA_c_0, RBA_c_1, + n7_adj_5, n2362, WRD_6, WRD_7, WRD_4, WRD_5, WRD_0, WRD_1, MAin_c_3, + RowA_2, RowA_3, WRD_2, WRD_3, RA_1_9, Bank_0, RDQML_c, Bank_1, n734, + n735, RA_1_8, RDQMH_c, Bank_4, MAin_c_7, RowA_7, RA_1_7, Bank_7, + MAin_c_6, RowA_6, RA_1_6, RA_1_5, RA_1_0, RA_1_4, RA_1_1, RA_1_3, + RA_1_2, n984, n736, Dout_c, Dout_0, Dout_1, Dout_2, Dout_3, Dout_4, + Dout_5, Dout_6, VCCI; + + SLICE_0 SLICE_0( .A1(FS_14), .A0(FS_13), .DI1(n81), .DI0(n82), .CLK(RCLK_c), + .FCI(n1998), .F0(n82), .Q0(FS_13), .F1(n81), .Q1(FS_14), .FCO(n1999)); + SLICE_1 SLICE_1( .A1(FS_12), .A0(FS_11), .DI1(n83), .DI0(n84), .CLK(RCLK_c), + .FCI(n1997), .F0(n84), .Q0(FS_11), .F1(n83), .Q1(FS_12), .FCO(n1998)); + SLICE_2 SLICE_2( .A1(FS_8), .A0(FS_7), .DI1(n87), .DI0(n88), .CLK(RCLK_c), + .FCI(n1995), .F0(n88), .Q0(FS_7), .F1(n87), .Q1(FS_8), .FCO(n1996)); + SLICE_3 SLICE_3( .A1(FS_6), .A0(FS_5), .DI1(n89), .DI0(n90), .CLK(RCLK_c), + .FCI(n1994), .F0(n90), .Q0(FS_5), .F1(n89), .Q1(FS_6), .FCO(n1995)); + SLICE_4 SLICE_4( .A1(FS_2), .A0(FS_1), .DI1(n93), .DI0(n94), .CLK(RCLK_c), + .FCI(n1992), .F0(n94), .Q0(FS_1), .F1(n93), .Q1(FS_2), .FCO(n1993)); + SLICE_5 SLICE_5( .A1(FS_0), .DI1(n95), .M0(CASr2), .CLK(RCLK_c), .Q0(CASr3), + .F1(n95), .Q1(FS_0), .FCO(n1992)); + SLICE_6 SLICE_6( .A1(FS_10), .A0(FS_9), .DI1(n85), .DI0(n86), .CLK(RCLK_c), + .FCI(n1996), .F0(n86), .Q0(FS_9), .F1(n85), .Q1(FS_10), .FCO(n1997)); + SLICE_7 SLICE_7( .A0(FS_17), .DI0(n78), .CLK(RCLK_c), .FCI(n2000), .F0(n78), + .Q0(FS_17)); + SLICE_8 SLICE_8( .A1(FS_4), .A0(FS_3), .DI1(n91), .DI0(n92), .CLK(RCLK_c), + .FCI(n1993), .F0(n92), .Q0(FS_3), .F1(n91), .Q1(FS_4), .FCO(n1994)); + SLICE_9 SLICE_9( .A1(FS_16), .A0(FS_15), .DI1(n79), .DI0(n80), .CLK(RCLK_c), + .FCI(n1999), .F0(n80), .Q0(FS_15), .F1(n79), .Q1(FS_16), .FCO(n2000)); + SLICE_10 SLICE_10( .D1(Din_c_4), .C1(Din_c_6), .B1(Din_c_1), .A1(Din_c_7), + .D0(n2382), .C0(n8), .B0(n2225), .A0(n2180), .DI0(ADSubmitted_N_246), + .CE(PHI2_N_120_enable_2), .LSR(C1Submitted_N_237), .CLK(PHI2_c), + .F0(ADSubmitted_N_246), .Q0(ADSubmitted), .F1(n8)); + SLICE_15 SLICE_15( .D1(n26), .C1(MAin_c_5), .B1(n22), .A1(MAin_c_2), + .D0(MAin_c_1), .C0(C1Submitted), .B0(n2365), .A0(nFWE_c), .DI0(n1398), + .LSR(C1Submitted_N_237), .CLK(PHI2_c), .F0(n1398), .Q0(C1Submitted), + .F1(n2365)); + SLICE_16 SLICE_16( .A0(nCCAS_c), .DI0(nCCAS_N_3), .M1(CASr), .CLK(RCLK_c), + .F0(nCCAS_N_3), .Q0(CASr), .Q1(CASr2)); + SLICE_19 SLICE_19( .D1(n2254), .C1(Din_c_5), .B1(n2191), .A1(n2183), + .D0(n15_adj_1), .C0(n2208), .B0(MAin_c_1), .A0(n2363), + .DI0(CmdEnable_N_248), .CE(PHI2_N_120_enable_1), .CLK(PHI2_c), + .F0(CmdEnable_N_248), .Q0(CmdEnable), .F1(n15_adj_1)); + SLICE_20 SLICE_20( .DI0(\n2447\001/BUF1 ), .CE(PHI2_N_120_enable_7), + .CLK(PHI2_c), .F0(\n2447\001/BUF1 ), .Q0(CmdSubmitted)); + SLICE_24 SLICE_24( .C1(Din_c_5), .B1(Din_c_7), .A1(Din_c_6), .D0(n1314), + .C0(Din_c_4), .B0(n8MEGEN), .A0(Din_c_0), .DI0(Cmdn8MEGEN_N_264), + .CE(PHI2_N_120_enable_6), .CLK(PHI2_c), .F0(Cmdn8MEGEN_N_264), + .Q0(Cmdn8MEGEN), .F1(n1314)); + SLICE_25 SLICE_25( .C1(Din_c_3), .B1(Din_c_5), .A1(nFWE_c), .A0(nFWE_c), + .DI0(n2373), .M1(nCCAS_N_3), .CLK(nCRAS_c), .F0(n2373), .Q0(FWEr), + .F1(n2180), .Q1(CBR)); + SLICE_26 SLICE_26( .DI0(\n2447\000/BUF1 ), .CE(RCLK_c_enable_28), + .CLK(RCLK_c), .F0(\n2447\000/BUF1 ), .Q0(InitReady)); + SLICE_27 SLICE_27( .DI0(n2447), .CE(RCLK_c_enable_16), .CLK(RCLK_c), + .F0(n2447), .Q0(LEDEN)); + SLICE_30 SLICE_30( .C1(CBR), .B1(LEDEN), .A1(nCRAS_c), .A0(nCRAS_c), + .DI0(nCRAS_c__inv), .M1(RASr), .CLK(RCLK_c), .F0(nCRAS_c__inv), .Q0(RASr), + .F1(LED_c), .Q1(RASr2)); + SLICE_32 SLICE_32( .C1(nRowColSel_N_35), .B1(InitReady), .A1(RASr2), + .D0(nRCAS_N_165), .C0(Ready), .B0(n2381), .A0(nRCS_N_139), .DI0(n2036), + .LSR(nRWE_N_177), .CLK(RCLK_c), .F0(n2036), .Q0(RA_0), .F1(n2381)); + SLICE_33 SLICE_33( .C1(Din_c_4), .B1(Din_c_7), .A1(Din_c_6), .C0(n8MEGEN), + .B0(XOR8MEG), .A0(Din_c_6), .DI0(RA11_N_184), .LSR(Ready), .CLK(PHI2_c), + .F0(RA11_N_184), .Q0(RA_c), .F1(n6_adj_2)); + SLICE_35 SLICE_35( .D1(InitReady), .C1(CmdSubmitted), .B1(PHI2r2), + .A1(PHI2r3), .C0(Ready), .B0(n15_adj_4), .A0(InitReady), + .DI0(RCKEEN_N_121), .CE(RCLK_c_enable_6), .CLK(RCLK_c), .F0(RCKEEN_N_121), + .Q0(RCKEEN), .F1(RCLK_c_enable_10)); + SLICE_36 SLICE_36( .D0(RASr3), .C0(RASr2), .B0(RCKEEN), .A0(RASr), + .DI0(RCKE_N_132), .M1(PHI2r), .CLK(RCLK_c), .F0(RCKE_N_132), .Q0(RCKE_c), + .Q1(PHI2r2)); + SLICE_37 SLICE_37( .DI0(\n2447\002/BUF1 ), .CE(Ready_N_292), .CLK(RCLK_c), + .F0(\n2447\002/BUF1 ), .Q0(Ready)); + SLICE_44 SLICE_44( .D1(FS_1), .C1(n2267), .B1(n13_adj_6), .A1(FS_4), + .C0(InitReady), .B0(CmdUFMCLK), .A0(n1893), .DI0(UFMCLK_N_224), + .CE(RCLK_c_enable_10), .LSR(n2366), .CLK(RCLK_c), .F0(UFMCLK_N_224), + .Q0(UFMCLK_c), .F1(n1893)); + SLICE_45 SLICE_45( .D1(n10), .C1(FS_10), .B1(FS_8), .A1(n7), .D0(n4), + .C0(InitReady), .B0(CmdUFMSDI), .A0(n2174), .DI0(UFMSDI_N_231), + .CE(RCLK_c_enable_10), .LSR(n2366), .CLK(RCLK_c), .F0(UFMSDI_N_231), + .Q0(UFMSDI_c), .F1(n2174)); + SLICE_50 SLICE_50( .D1(LEDEN), .C1(n1314), .B1(Din_c_1), .A1(Din_c_4), + .D0(Din_c_3), .C0(n2260), .B0(Din_c_2), .A0(Din_c_0), .DI0(XOR8MEG_N_110), + .CE(PHI2_N_120_enable_3), .CLK(PHI2_c), .F0(XOR8MEG_N_110), .Q0(XOR8MEG), + .F1(n2260)); + SLICE_57 SLICE_57( .D1(FS_10), .C1(FS_11), .B1(n2375), .A1(n10), + .D0(Cmdn8MEGEN), .C0(UFMSDO_c), .B0(n2367), .A0(InitReady), + .DI0(n8MEGEN_N_91), .CE(RCLK_c_enable_15), .CLK(RCLK_c), .F0(n8MEGEN_N_91), + .Q0(n8MEGEN), .F1(n2367)); + SLICE_59 SLICE_59( .D1(CBR), .C1(nRowColSel_N_35), .B1(RASr2), + .A1(nRCS_N_142), .D0(nRCAS_N_166), .C0(Ready), .B0(nRCAS_N_165), + .A0(n2371), .DI0(nRCAS_N_161), .CE(RCLK_c_enable_6), .CLK(RCLK_c), + .F0(nRCAS_N_161), .Q0(nRCAS_c), .F1(nRCAS_N_166)); + SLICE_61 SLICE_61( .D1(nRCS_N_142), .C1(nRowColSel_N_35), .B1(RASr2), + .A1(RCKE_c), .C0(Ready), .B0(nRCS_N_141), .A0(nRCS_N_137), + .DI0(nRCS_N_136), .CE(RCLK_c_enable_6), .CLK(RCLK_c), .F0(nRCS_N_136), + .Q0(nRCS_c), .F1(nRCS_N_141)); + SLICE_62 SLICE_62( .D1(RASr2), .C1(nRowColSel_N_35), .B1(InitReady), + .A1(nRCS_N_139), .D0(nRowColSel_N_35), .C0(Ready), .B0(n2379), + .A0(nRCS_N_137), .DI0(nRRAS_N_156), .CE(RCLK_c_enable_6), .CLK(RCLK_c), + .F0(nRRAS_N_156), .Q0(nRRAS_c), .F1(nRCS_N_137)); + SLICE_64 SLICE_64( .B1(nRCAS_N_165), .A1(nRWE_N_177), .D0(n2371), .C0(Ready), + .B0(nRWE_N_178), .A0(n1765), .DI0(nRWE_N_171), .CE(RCLK_c_enable_5), + .CLK(RCLK_c), .F0(nRWE_N_171), .Q0(nRWE_c), .F1(n1765)); + SLICE_65 SLICE_65( .B1(nRowColSel_N_34), .A1(nRowColSel_N_33), .D0(n2376), + .C0(n1060), .B0(n2372), .A0(FWEr), .DI0(n917), .CE(RCLK_c_enable_5), + .CLK(RCLK_c), .F0(n917), .Q0(nRowColSel), .F1(n1060)); + SLICE_66 SLICE_66( .B1(CASr2), .A1(nRowColSel_N_33), .B0(nRowColSel_N_32), + .A0(nRowColSel_N_33), .DI0(n827), .LSR(RASr2), .CLK(RCLK_c), .F0(n827), + .Q0(nRowColSel_N_32), .F1(n2227)); + SLICE_67 SLICE_67( .B0(nRowColSel_N_32), .A0(RASr2), .DI0(n1406), + .LSR(nRowColSel_N_34), .CLK(RCLK_c), .F0(n1406), .Q0(nRowColSel_N_33)); + SLICE_68 SLICE_68( .B1(FS_0), .A1(FS_8), .B0(Bank_3), .A0(Bank_6), + .M0(n1406), .LSR(nRowColSel_N_35), .CLK(RCLK_c), .F0(n2287), + .Q0(nRowColSel_N_34), .F1(n13)); + SLICE_69 SLICE_69( .B1(RASr2), .A1(RCKE_c), .A0(RASr2), .DI0(n2374), + .M1(PHI2r2), .CLK(RCLK_c), .F0(n2374), .Q0(nRowColSel_N_35), .F1(n2379), + .Q1(PHI2r3)); + SLICE_70 SLICE_70( .D1(FS_10), .C1(InitReady), .B1(n2368), .A1(FS_11), + .D0(InitReady), .C0(CmdUFMCS), .B0(n64), .A0(n13_adj_6), + .DI0(nUFMCS_N_199), .CE(RCLK_c_enable_10), .CLK(RCLK_c), .F0(nUFMCS_N_199), + .Q0(nUFMCS_c), .F1(n64)); + i30_SLICE_71 \i30/SLICE_71 ( .C1(RASr2), .B1(FWEr), .A1(CBR), + .D0(nRowColSel_N_34), .C0(FWEr), .B0(n2227), .A0(CBR), + .M0(nRowColSel_N_35), .OFX0(n15_adj_4)); + SLICE_72 SLICE_72( .D1(Ready), .C1(nRowColSel_N_32), .B1(n6_adj_3), + .A1(RASr2), .B0(Ready_N_296), .A0(InitReady), .F0(n6_adj_3), + .F1(Ready_N_292)); + SLICE_73 SLICE_73( .D1(n2204), .C1(n2180), .B1(n26), .A1(n2369), + .D0(n6_adj_2), .C0(CmdEnable), .B0(MAin_c_0), .A0(MAin_c_1), .F0(n2204), + .F1(PHI2_N_120_enable_8)); + SLICE_74 SLICE_74( .D1(Bank_5), .C1(n2287), .B1(n2277), .A1(Bank_2), + .D0(nFWE_c), .C0(n2204), .B0(n26), .A0(n2369), .M1(MAin_c_1), + .M0(MAin_c_0), .LSR(Ready), .CLK(nCRAS_c), .F0(n2220), .Q0(RowA_0), + .F1(n26), .Q1(RowA_1)); + SLICE_75 SLICE_75( .D1(n2370), .C1(n2183), .B1(n2228), .A1(Din_c_5), + .B0(Din_c_3), .A0(Din_c_6), .M1(n732), .M0(n733), .CE(RCLK_c_enable_27), + .CLK(RCLK_c), .F0(n2183), .Q0(n732), .F1(n2055), .Q1(nRWE_N_177)); + SLICE_76 SLICE_76( .C1(n10), .B1(FS_14), .A1(FS_12), .D0(InitReady), + .C0(n2368), .B0(FS_11), .A0(FS_10), .M1(MAin_c_9), .M0(MAin_c_8), + .LSR(Ready), .CLK(nCRAS_c), .F0(RCLK_c_enable_16), .Q0(RowA_8), .F1(n2368), + .Q1(RowA_9)); + SLICE_77 SLICE_77( .D1(n2208), .C1(C1Submitted), .B1(n2191), .A1(Din_c_5), + .D0(MAin_c_0), .C0(Din_c_6), .B0(Din_c_3), .A0(Din_c_2), .F0(n2191), + .F1(n2210)); + SLICE_78 SLICE_78( .D1(nRowColSel_N_35), .C1(nRWE_N_182), .B1(n1060), + .A1(nRCS_N_146), .B0(RASr2), .A0(RCKE_c), .M1(n728), .M0(n729), + .CE(RCLK_c_enable_27), .CLK(RCLK_c), .F0(nRWE_N_182), .Q0(n728), + .F1(nRWE_N_178), .Q1(n727)); + SLICE_79 SLICE_79( .C1(MAin_c_5), .B1(n22), .A1(MAin_c_2), .D0(MAin_c_1), + .C0(nFWE_c), .B0(n26), .A0(n2369), .M1(n730), .M0(nRWE_N_177), + .CE(RCLK_c_enable_27), .CLK(RCLK_c), .F0(PHI2_N_120_enable_2), .Q0(n730), + .F1(n2369), .Q1(n729)); + SLICE_80 SLICE_80( .B1(FS_14), .A1(FS_12), .D0(FS_11), .C0(InitReady), + .B0(n2375), .A0(n10), .F0(n2366), .F1(n2375)); + SLICE_81 SLICE_81( .B1(CBR), .A1(FWEr), .D0(nRowColSel_N_33), .C0(n2378), + .B0(nRowColSel_N_34), .A0(nRCS_N_146), .M1(n726), .M0(n727), + .CE(RCLK_c_enable_27), .CLK(RCLK_c), .F0(nRCS_N_142), .Q0(n726), + .F1(n2378), .Q1(Ready_N_296)); + SLICE_82 SLICE_82( .D1(FS_17), .C1(FS_14), .B1(n12), .A1(FS_11), + .B0(n13_adj_6), .A0(FS_10), .M1(MAin_c_5), .M0(MAin_c_4), .LSR(Ready), + .CLK(nCRAS_c), .F0(RCLK_c_enable_28), .Q0(RowA_4), .F1(n13_adj_6), + .Q1(RowA_5)); + SLICE_83 SLICE_83( .D1(n1314), .C1(n1277), .B1(CmdEnable), .A1(n2228), + .D0(MAin_c_1), .C0(MAin_c_0), .B0(n26), .A0(n2369), .F0(n1277), + .F1(PHI2_N_120_enable_3)); + SLICE_84 SLICE_84( .C1(CmdSubmitted), .B1(PHI2r2), .A1(PHI2r3), + .D0(n4_adj_7), .C0(InitReady), .B0(n2377), .A0(n2367), .M1(n738), + .M0(nRCAS_N_165), .CE(RCLK_c_enable_27), .CLK(RCLK_c), + .F0(RCLK_c_enable_15), .Q0(n738), .F1(n2377), .Q1(n737)); + SLICE_85 SLICE_85( .D1(n10), .C1(FS_11), .B1(FS_14), .A1(FS_12), .D0(FS_16), + .C0(FS_15), .B0(FS_13), .A0(FS_17), .F0(n10), .F1(n2267)); + SLICE_86 SLICE_86( .C1(FS_6), .B1(FS_9), .A1(FS_3), .D0(n14), .C0(n13), + .B0(n15), .A0(FS_4), .M1(RASr2), .M0(PHI2_c), .CLK(RCLK_c), .F0(n4_adj_7), + .Q0(PHI2r), .F1(n14), .Q1(RASr3)); + SLICE_87 SLICE_87( .D1(n6), .C1(nRowColSel_N_32), .B1(nRowColSel_N_33), + .A1(nRowColSel_N_35), .B0(nRowColSel_N_34), .A0(Ready), .M1(CROW_c_1), + .M0(CROW_c_0), .LSR(Ready), .CLK(nCRAS_c), .F0(n6), .Q0(RBA_c_0), + .F1(RCLK_c_enable_6), .Q1(RBA_c_1)); + SLICE_88 SLICE_88( .D1(n2363), .C1(C1Submitted_N_237), .B1(ADSubmitted), + .A1(n7_adj_5), .D0(n2362), .C0(MAin_c_0), .B0(n2055), .A0(Din_c_2), + .M1(Din_c_7), .M0(Din_c_6), .CLK(nCCAS_c), .F0(C1Submitted_N_237), + .Q0(WRD_6), .F1(PHI2_N_120_enable_1), .Q1(WRD_7)); + SLICE_89 SLICE_89( .D1(Din_c_5), .C1(Din_c_3), .B1(Din_c_4), .A1(n2220), + .D0(Din_c_3), .C0(Din_c_4), .B0(n2220), .A0(Din_c_5), .M1(Din_c_5), + .M0(Din_c_4), .CLK(nCCAS_c), .F0(PHI2_N_120_enable_6), .Q0(WRD_4), + .F1(PHI2_N_120_enable_7), .Q1(WRD_5)); + SLICE_90 SLICE_90( .D1(Din_c_0), .C1(Din_c_4), .B1(Din_c_1), .A1(Din_c_7), + .C0(Din_c_0), .B0(Din_c_1), .A0(Din_c_7), .M1(Din_c_1), .M0(Din_c_0), + .CLK(nCCAS_c), .F0(n2370), .Q0(WRD_0), .F1(n2208), .Q1(WRD_1)); + SLICE_91 SLICE_91( .C1(MAin_c_1), .B1(n26), .A1(n2369), .D0(MAin_c_1), + .C0(MAin_c_0), .B0(n26), .A0(n2369), .M1(MAin_c_3), .M0(MAin_c_2), + .LSR(Ready), .CLK(nCRAS_c), .F0(n2225), .Q0(RowA_2), .F1(n2362), + .Q1(RowA_3)); + SLICE_92 SLICE_92( .D1(Ready), .C1(nRowColSel_N_35), .B1(InitReady), + .A1(RASr2), .D0(nRCS_N_139), .C0(nRowColSel_N_35), .B0(InitReady), + .A0(RASr2), .M1(Din_c_3), .M0(Din_c_2), .CLK(nCCAS_c), .F0(n2371), + .Q0(WRD_2), .F1(RCLK_c_enable_27), .Q1(WRD_3)); + SLICE_93 SLICE_93( .B1(nRowColSel), .A1(MAin_c_9), .C0(nRowColSel), + .B0(MAin_c_9), .A0(RowA_9), .M1(Din_c_1), .M0(Din_c_0), .CLK(PHI2_c), + .F0(RA_1_9), .Q0(Bank_0), .F1(RDQML_c), .Q1(Bank_1)); + SLICE_94 SLICE_94( .B1(nRowColSel_N_35), .A1(Ready), .D0(nRowColSel_N_35), + .C0(nRowColSel_N_32), .B0(n1060), .A0(Ready), .F0(RCLK_c_enable_5), + .F1(n2372)); + SLICE_95 SLICE_95( .D1(FS_5), .C1(FS_9), .B1(FS_7), .A1(n2375), .D0(FS_2), + .C0(FS_1), .B0(FS_7), .A0(FS_5), .F0(n15), .F1(n7)); + SLICE_96 SLICE_96( .B1(CASr3), .A1(CBR), .D0(CASr2), .C0(FWEr), .B0(CASr3), + .A0(CBR), .F0(nRCS_N_146), .F1(n2376)); + SLICE_97 SLICE_97( .C1(MAin_c_1), .B1(n2210), .A1(MAin_c_0), .B0(Din_c_2), + .A0(MAin_c_0), .M1(n734), .M0(n735), .CE(RCLK_c_enable_27), .CLK(RCLK_c), + .F0(n2254), .Q0(n734), .F1(n7_adj_5), .Q1(n733)); + SLICE_98 SLICE_98( .B1(nRowColSel), .A1(MAin_c_9), .C0(nRowColSel), + .B0(MAin_c_8), .A0(RowA_8), .M1(nRCS_N_139), .M0(Ready_N_296), + .CE(RCLK_c_enable_27), .CLK(RCLK_c), .F0(RA_1_8), .Q0(nRCS_N_139), + .F1(RDQMH_c), .Q1(nRCAS_N_165)); + SLICE_99 SLICE_99( .D1(Bank_1), .C1(Bank_4), .B1(MAin_c_3), .A1(MAin_c_7), + .C0(nRowColSel), .B0(MAin_c_7), .A0(RowA_7), .M0(Din_c_0), + .CE(PHI2_N_120_enable_8), .CLK(PHI2_c), .F0(RA_1_7), .Q0(CmdUFMSDI), + .F1(n22)); + SLICE_100 SLICE_100( .D1(Bank_0), .C1(Bank_7), .B1(MAin_c_4), .A1(MAin_c_6), + .C0(nRowColSel), .B0(MAin_c_6), .A0(RowA_6), .M1(Din_c_2), .M0(Din_c_1), + .CE(PHI2_N_120_enable_8), .CLK(PHI2_c), .F0(RA_1_6), .Q0(CmdUFMCLK), + .F1(n2277), .Q1(CmdUFMCS)); + SLICE_101 SLICE_101( .C1(nRowColSel), .B1(MAin_c_0), .A1(RowA_0), + .C0(nRowColSel), .B0(MAin_c_5), .A0(RowA_5), .M1(Din_c_7), .M0(Din_c_6), + .CLK(PHI2_c), .F0(RA_1_5), .Q0(Bank_6), .F1(RA_1_0), .Q1(Bank_7)); + SLICE_102 SLICE_102( .C1(nRowColSel), .B1(MAin_c_1), .A1(RowA_1), + .C0(nRowColSel), .B0(MAin_c_4), .A0(RowA_4), .M1(Din_c_5), .M0(Din_c_4), + .CLK(PHI2_c), .F0(RA_1_4), .Q0(Bank_4), .F1(RA_1_1), .Q1(Bank_5)); + SLICE_103 SLICE_103( .C1(nRowColSel), .B1(MAin_c_2), .A1(RowA_2), + .C0(nRowColSel), .B0(MAin_c_3), .A0(RowA_3), .M1(Din_c_3), .M0(Din_c_2), + .CLK(PHI2_c), .F0(RA_1_3), .Q0(Bank_2), .F1(RA_1_2), .Q1(Bank_3)); + SLICE_104 SLICE_104( .B1(nFWE_c), .A1(nCCAS_c), .C0(nFWE_c), .B0(n26), + .A0(n2369), .M1(MAin_c_7), .M0(MAin_c_6), .LSR(Ready), .CLK(nCRAS_c), + .F0(n2363), .Q0(RowA_6), .F1(n984), .Q1(RowA_7)); + SLICE_105 SLICE_105( .B1(FS_6), .A1(FS_11), .D0(FS_16), .C0(FS_15), + .B0(FS_12), .A0(FS_13), .F0(n12), .F1(n4)); + SLICE_106 SLICE_106( .B1(Din_c_2), .A1(Din_c_0), .B0(Din_c_4), .A0(nFWE_c), + .M1(n736), .M0(n737), .CE(RCLK_c_enable_27), .CLK(RCLK_c), .F0(n2228), + .Q0(n736), .F1(n2382), .Q1(n735)); + RD_7_ \RD[7]_I ( .PADDI(Dout_c), .PADDT(n984), .PADDO(WRD_7), .RD7(RD[7])); + RD_6_ \RD[6]_I ( .PADDI(Dout_0), .PADDT(n984), .PADDO(WRD_6), .RD6(RD[6])); + RD_5_ \RD[5]_I ( .PADDI(Dout_1), .PADDT(n984), .PADDO(WRD_5), .RD5(RD[5])); + RD_4_ \RD[4]_I ( .PADDI(Dout_2), .PADDT(n984), .PADDO(WRD_4), .RD4(RD[4])); + RD_3_ \RD[3]_I ( .PADDI(Dout_3), .PADDT(n984), .PADDO(WRD_3), .RD3(RD[3])); + RD_2_ \RD[2]_I ( .PADDI(Dout_4), .PADDT(n984), .PADDO(WRD_2), .RD2(RD[2])); + RD_1_ \RD[1]_I ( .PADDI(Dout_5), .PADDT(n984), .PADDO(WRD_1), .RD1(RD[1])); + RD_0_ \RD[0]_I ( .PADDI(Dout_6), .PADDT(n984), .PADDO(WRD_0), .RD0(RD[0])); + Dout_7_ \Dout[7]_I ( .PADDO(Dout_c), .Dout7(Dout[7])); + Dout_6_ \Dout[6]_I ( .PADDO(Dout_0), .Dout6(Dout[6])); + Dout_5_ \Dout[5]_I ( .PADDO(Dout_1), .Dout5(Dout[5])); + Dout_4_ \Dout[4]_I ( .PADDO(Dout_2), .Dout4(Dout[4])); + Dout_3_ \Dout[3]_I ( .PADDO(Dout_3), .Dout3(Dout[3])); + Dout_2_ \Dout[2]_I ( .PADDO(Dout_4), .Dout2(Dout[2])); + Dout_1_ \Dout[1]_I ( .PADDO(Dout_5), .Dout1(Dout[1])); + Dout_0_ \Dout[0]_I ( .PADDO(Dout_6), .Dout0(Dout[0])); + LED LED_I( .PADDO(LED_c), .LED(LED)); + RBA_1_ \RBA[1]_I ( .PADDO(RBA_c_1), .RBA1(RBA[1])); + RBA_0_ \RBA[0]_I ( .PADDO(RBA_c_0), .RBA0(RBA[0])); + RA_11_ \RA[11]_I ( .PADDO(RA_c), .RA11(RA[11])); + RA_10_ \RA[10]_I ( .PADDO(RA_0), .RA10(RA[10])); + RA_9_ \RA[9]_I ( .PADDO(RA_1_9), .RA9(RA[9])); + RA_8_ \RA[8]_I ( .PADDO(RA_1_8), .RA8(RA[8])); + RA_7_ \RA[7]_I ( .PADDO(RA_1_7), .RA7(RA[7])); + RA_6_ \RA[6]_I ( .PADDO(RA_1_6), .RA6(RA[6])); + RA_5_ \RA[5]_I ( .PADDO(RA_1_5), .RA5(RA[5])); + RA_4_ \RA[4]_I ( .PADDO(RA_1_4), .RA4(RA[4])); + RA_3_ \RA[3]_I ( .PADDO(RA_1_3), .RA3(RA[3])); + RA_2_ \RA[2]_I ( .PADDO(RA_1_2), .RA2(RA[2])); + RA_1_ \RA[1]_I ( .PADDO(RA_1_1), .RA1(RA[1])); + RA_0_ \RA[0]_I ( .PADDO(RA_1_0), .RA0(RA[0])); + nRCS nRCS_I( .PADDO(nRCS_c), .nRCS(nRCS)); + RCKE RCKE_I( .PADDO(RCKE_c), .RCKE(RCKE)); + nRWE nRWE_I( .PADDO(nRWE_c), .nRWE(nRWE)); + nRRAS nRRAS_I( .PADDO(nRRAS_c), .nRRAS(nRRAS)); + nRCAS nRCAS_I( .PADDO(nRCAS_c), .nRCAS(nRCAS)); + RDQMH RDQMH_I( .PADDO(RDQMH_c), .RDQMH(RDQMH)); + RDQML RDQML_I( .PADDO(RDQML_c), .RDQML(RDQML)); + nUFMCS nUFMCS_I( .PADDO(nUFMCS_c), .nUFMCS(nUFMCS)); + UFMCLK UFMCLK_I( .PADDO(UFMCLK_c), .UFMCLK(UFMCLK)); + UFMSDI UFMSDI_I( .PADDO(UFMSDI_c), .UFMSDI(UFMSDI)); + PHI2 PHI2_I( .PADDI(PHI2_c), .PHI2(PHI2)); + MAin_9_ \MAin[9]_I ( .PADDI(MAin_c_9), .MAin9(MAin[9])); + MAin_8_ \MAin[8]_I ( .PADDI(MAin_c_8), .MAin8(MAin[8])); + MAin_7_ \MAin[7]_I ( .PADDI(MAin_c_7), .MAin7(MAin[7])); + MAin_6_ \MAin[6]_I ( .PADDI(MAin_c_6), .MAin6(MAin[6])); + MAin_5_ \MAin[5]_I ( .PADDI(MAin_c_5), .MAin5(MAin[5])); + MAin_4_ \MAin[4]_I ( .PADDI(MAin_c_4), .MAin4(MAin[4])); + MAin_3_ \MAin[3]_I ( .PADDI(MAin_c_3), .MAin3(MAin[3])); + MAin_2_ \MAin[2]_I ( .PADDI(MAin_c_2), .MAin2(MAin[2])); + MAin_1_ \MAin[1]_I ( .PADDI(MAin_c_1), .MAin1(MAin[1])); + MAin_0_ \MAin[0]_I ( .PADDI(MAin_c_0), .MAin0(MAin[0])); + CROW_1_ \CROW[1]_I ( .PADDI(CROW_c_1), .CROW1(CROW[1])); + CROW_0_ \CROW[0]_I ( .PADDI(CROW_c_0), .CROW0(CROW[0])); + Din_7_ \Din[7]_I ( .PADDI(Din_c_7), .Din7(Din[7])); + Din_6_ \Din[6]_I ( .PADDI(Din_c_6), .Din6(Din[6])); + Din_5_ \Din[5]_I ( .PADDI(Din_c_5), .Din5(Din[5])); + Din_4_ \Din[4]_I ( .PADDI(Din_c_4), .Din4(Din[4])); + Din_3_ \Din[3]_I ( .PADDI(Din_c_3), .Din3(Din[3])); + Din_2_ \Din[2]_I ( .PADDI(Din_c_2), .Din2(Din[2])); + Din_1_ \Din[1]_I ( .PADDI(Din_c_1), .Din1(Din[1])); + Din_0_ \Din[0]_I ( .PADDI(Din_c_0), .Din0(Din[0])); + nCCAS nCCAS_I( .PADDI(nCCAS_c), .nCCAS(nCCAS)); + nCRAS nCRAS_I( .PADDI(nCRAS_c), .nCRAS(nCRAS)); + nFWE nFWE_I( .PADDI(nFWE_c), .nFWE(nFWE)); + RCLK RCLK_I( .PADDI(RCLK_c), .RCLK(RCLK)); + UFMSDO UFMSDO_I( .PADDI(UFMSDO_c), .UFMSDO(UFMSDO)); + VHI VHI_INST( .Z(VCCI)); + PUR PUR_INST( .PUR(VCCI)); + GSR GSR_INST( .GSR(VCCI)); +endmodule + +module SLICE_0 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre FS_610__i14( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i13( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_15( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module vcc ( output PWR1 ); + + VHI INST1( .Z(PWR1)); +endmodule + +module gnd ( output PWR0 ); + + VLO INST1( .Z(PWR0)); +endmodule + +module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'hfaaa; + defparam inst1.INIT1 = 16'hfaaa; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_1 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre FS_610__i12( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i11( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_13( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_2 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre FS_610__i8( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i7( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_9( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_3 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre FS_610__i6( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i5( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_7( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_4 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre FS_610__i2( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i1( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_3( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_5 ( input A1, DI1, M0, CLK, output Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, M0_dly; + + vmuxregsre FS_610__i0( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CASr3_384( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20001 FS_610_add_4_1( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'hF000; + defparam inst1.INIT1 = 16'h0555; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_6 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre FS_610__i10( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i9( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_11( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_7 ( input A0, DI0, CLK, FCI, output F0, Q0 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; + + vmuxregsre FS_610__i17( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + ccu20002 FS_610_add_4_19( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(GNDI), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), + .CO1()); + + specify + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module ccu20002 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'hfaaa; + defparam inst1.INIT1 = 16'h0000; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_8 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre FS_610__i4( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i3( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_5( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_9 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre FS_610__i16( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i15( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_17( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_10 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut4 i3_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40003 i1_4_lut_adj_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0004 ADSubmitted_407( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut4 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40003 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0004 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module inverter ( input I, output Z ); + + INV INST1( .A(I), .Z(Z)); +endmodule + +module SLICE_15 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output + F0, Q0, F1 ); + wire VCCI, CLK_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40005 i13_2_lut_rep_16_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40006 i1110_2_lut_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0007 C1Submitted_406( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40005 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40006 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hE0F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0007 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3JY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module SLICE_16 ( input A0, DI0, M1, CLK, output F0, Q0, Q1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; + + lut40008 i2045( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CASr2_383( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre CASr_382( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40008 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_19 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40009 i26_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40010 i2_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdEnable_405( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40009 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC0CA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40010 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_20 ( input DI0, CE, CLK, output F0, Q0 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; + + lut40011 \n2447\001/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CmdSubmitted_411( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40011 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_24 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; + + lut40012 i1_2_lut_3_lut_adj_15( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40013 Cmdn8MEGEN_I_93_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre Cmdn8MEGEN_410( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40012 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40013 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCC5C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_25 ( input C1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, M1_dly; + + lut40014 i2_3_lut_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40008 i2_1_lut_rep_24( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre CBR_390( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre FWEr_389( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + endspecify + +endmodule + +module lut40014 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_26 ( input DI0, CE, CLK, output F0, Q0 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40011 \n2447\000/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre InitReady_394( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_27 ( input DI0, CE, CLK, output F0, Q0 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40011 m1_lut( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre LEDEN_419( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_30 ( input C1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; + + lut40015 i2010_3_lut_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40008 i2044( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre RASr2_380( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre RASr_379( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40015 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFBFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_32 ( input C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40016 i2_3_lut_rep_32( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40017 i2_2_lut_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0007 RA10_400( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40016 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40017 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_33 ( input C1, B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40018 i1_2_lut_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40019 RA11_I_54_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0004 RA11_385( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40018 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40019 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC6C6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_35 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40020 i1_2_lut_4_lut_adj_25( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40021 i29_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre RCKEEN_401( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40020 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h20FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40021 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_36 ( input D0, C0, B0, A0, DI0, M1, CLK, output F0, Q0, Q1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, M1_dly; + + lut40022 i1404_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre PHI2r2_377( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre RCKE_395( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40022 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCFC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_37 ( input DI0, CE, CLK, output F0, Q0 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40011 \n2447\002/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre Ready_404( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_44 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, CLK, output + F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40023 i1970_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40021 i1603_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 UFMCLK_416( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40023 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3A0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_45 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut4 i4_4_lut_adj_17( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40024 i1589_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0004 UFMSDI_417( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40024 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_50 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40025 i1962_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40026 i2_3_lut_4_lut_adj_11( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre XOR8MEG_408( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40025 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40026 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40027 i2_3_lut_rep_18_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40028 n8MEGEN_I_14_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre n8MEGEN_418( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40027 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40028 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBF04) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40029 nRCAS_I_43_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40030 nRCAS_I_0_452_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0031 nRCAS_398( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40029 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3AFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40030 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFE0E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0031 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module SLICE_61 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40032 nRCS_I_31_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40021 nRCS_I_0_448_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0031 nRCS_396( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40032 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1F10) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40033 i3_4_lut_adj_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40029 nRCS_N_137_I_0_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0031 nRRAS_397( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40033 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_64 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40034 i1477_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40035 nRWE_I_0_455_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0031 nRWE_399( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40034 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40035 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCFC5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_65 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40034 i786_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40036 i1432_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre nRowColSel_402( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40036 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3032) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_66 ( input B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40037 i1_2_lut_adj_23( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40034 i1439_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0004 S_FSM_i4( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40037 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_67 ( input B0, A0, DI0, LSR, CLK, output F0, Q0 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40038 i1_2_lut_adj_10( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 S_FSM_i3( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40038 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_68 ( input B1, A1, B0, A0, M0, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, LSR_dly; + + lut40034 i4_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40039 i1989_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0004 S_FSM_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40039 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_69 ( input B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; + + lut40034 i1491_2_lut_rep_30( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40008 RASr2_I_0_1_lut_rep_25( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), + .Z(F0)); + vmuxregsre PHI2r3_378( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre S_FSM_i1( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_70 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40040 i1_2_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40041 i1448_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0031 nUFMCS_415( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40040 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40041 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3FBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module i30_SLICE_71 ( input C1, B1, A1, D0, C0, B0, A0, M0, output OFX0 ); + wire GNDI, \i30/SLICE_71/i30/SLICE_71_K1_H1 , \i30/SLICE_71/i30/GATE_H0 ; + + lut40042 \i30/SLICE_71_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(\i30/SLICE_71/i30/SLICE_71_K1_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40043 \i30/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\i30/SLICE_71/i30/GATE_H0 )); + selmux2 \i30/SLICE_71_K0K1MUX ( .D0(\i30/SLICE_71/i30/GATE_H0 ), + .D1(\i30/SLICE_71/i30/SLICE_71_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40042 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1F1F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40043 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5540) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module selmux2 ( input D0, D1, SD, output Z ); + + MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); +endmodule + +module SLICE_72 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); + wire GNDI; + + lut40044 i1_4_lut_4_lut_adj_12( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40039 i2_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40044 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40003 i2_3_lut_4_lut_adj_14( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40010 i4_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_74 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40033 i12_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40045 i1_2_lut_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0004 RowA_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 RowA_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40045 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_75 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40027 i3_4_lut_adj_18( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40038 i1_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre IS_FSM__i9( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i8( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_76 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40012 i1_2_lut_rep_19_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40026 i1_2_lut_rep_15_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0007 RowA_i9( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 RowA_i8( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_77 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40046 i3_4_lut_adj_22( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40046 i3_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40046 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_78 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40047 nRCS_N_146_bdd_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40048 i1423_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre IS_FSM__i13( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i12( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40047 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF0DD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40048 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_79 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40016 i11_3_lut_rep_20( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40049 MAin_c_0_bdd_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre IS_FSM__i11( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i10( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40049 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_80 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40034 i3_2_lut_rep_26( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40050 i2005_3_lut_rep_17_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40050 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_81 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40034 i1_2_lut_rep_29( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40051 i1427_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre IS_FSM__i15( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i14( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40051 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFCDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_82 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40052 i6_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40039 i1_2_lut_adj_3( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0007 RowA_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 RowA_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40052 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_83 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40053 i2_4_lut_adj_21( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40054 i2_3_lut_4_lut_adj_6( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40053 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40054 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_84 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40055 i2_3_lut_rep_28( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40024 i1573_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre IS_FSM__i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40055 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40056 i1969_2_lut_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40040 i3_4_lut_adj_7( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40056 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_86 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40012 i5_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut4 i1_4_lut_adj_8( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre RASr3_381( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre PHI2r_376( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_87 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40040 i4_4_lut_adj_16( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40048 i1_2_lut_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 RBA__i2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 RBA__i1( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_88 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40057 i34_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40053 i1_4_lut_adj_13( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre WRD_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre WRD_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module lut40057 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC0C5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_89 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40058 i2_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40059 i1_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre WRD_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre WRD_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module lut40058 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8088) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40059 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_90 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40049 i1_2_lut_3_lut_4_lut_adj_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40055 i1_2_lut_rep_21_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre WRD_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre WRD_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module SLICE_91 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40060 i1_2_lut_rep_13_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40061 i1_2_lut_3_lut_4_lut_adj_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0004 RowA_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 RowA_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40060 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40061 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_92 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40062 i2008_2_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40005 i1_2_lut_rep_22_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre WRD_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre WRD_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module lut40062 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_93 ( input B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40063 i2001_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40021 MAin_9__I_0_427_i10_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre Bank_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre Bank_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40063 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_94 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40048 i771_2_lut_rep_23_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40064 i2_3_lut_4_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40064 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_95 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40065 i2_4_lut_adj_20( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40040 i6_4_lut_adj_9( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40065 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_96 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40034 i1_2_lut_rep_27( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40027 i2_3_lut_4_lut_adj_24( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_97 ( input C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40066 i13_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40034 i1956_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre IS_FSM__i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40066 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC5C5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_98 ( input B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40037 i1416_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40021 MAin_9__I_0_427_i9_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre IS_FSM__i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_99 ( input D1, C1, B1, A1, C0, B0, A0, M0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; + + lut40052 i8_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40021 MAin_9__I_0_427_i8_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CmdUFMSDI_414( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_100 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40052 i1979_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40021 MAin_9__I_0_427_i7_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CmdUFMCS_412( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre CmdUFMCLK_413( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_101 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40021 MAin_9__I_0_427_i1_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40021 MAin_9__I_0_427_i6_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre Bank_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre Bank_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_102 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40021 MAin_9__I_0_427_i2_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40021 MAin_9__I_0_427_i5_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre Bank_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre Bank_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_103 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40021 MAin_9__I_0_427_i3_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40021 MAin_9__I_0_427_i4_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre Bank_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre Bank_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_104 ( input B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40034 i1417_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40067 i1_2_lut_rep_14_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0004 RowA_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 RowA_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40067 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_105 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40039 i1_2_lut_adj_19( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40052 i5_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_106 ( input B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40039 i1_2_lut_rep_33( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40034 i1930_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre IS_FSM__i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 ); + + xo2iobuf Dout_pad_7__713( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), + .PADI(RD7)); + + specify + (PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD7) = (0:0:0,0:0:0); + (RD7 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD7, 0:0:0); + $width (negedge RD7, 0:0:0); + endspecify + +endmodule + +module xo2iobuf ( input I, T, output Z, PAD, input PADI ); + + IBPD INST1( .I(PADI), .O(Z)); + OBZPD INST2( .I(I), .T(T), .O(PAD)); +endmodule + +module RD_6_ ( output PADDI, input PADDT, PADDO, inout RD6 ); + + xo2iobuf Dout_pad_6__714( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD6), + .PADI(RD6)); + + specify + (PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD6) = (0:0:0,0:0:0); + (RD6 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD6, 0:0:0); + $width (negedge RD6, 0:0:0); + endspecify + +endmodule + +module RD_5_ ( output PADDI, input PADDT, PADDO, inout RD5 ); + + xo2iobuf Dout_pad_5__715( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD5), + .PADI(RD5)); + + specify + (PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD5) = (0:0:0,0:0:0); + (RD5 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD5, 0:0:0); + $width (negedge RD5, 0:0:0); + endspecify + +endmodule + +module RD_4_ ( output PADDI, input PADDT, PADDO, inout RD4 ); + + xo2iobuf Dout_pad_4__716( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD4), + .PADI(RD4)); + + specify + (PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD4) = (0:0:0,0:0:0); + (RD4 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD4, 0:0:0); + $width (negedge RD4, 0:0:0); + endspecify + +endmodule + +module RD_3_ ( output PADDI, input PADDT, PADDO, inout RD3 ); + + xo2iobuf Dout_pad_3__717( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD3), + .PADI(RD3)); + + specify + (PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD3) = (0:0:0,0:0:0); + (RD3 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD3, 0:0:0); + $width (negedge RD3, 0:0:0); + endspecify + +endmodule + +module RD_2_ ( output PADDI, input PADDT, PADDO, inout RD2 ); + + xo2iobuf Dout_pad_2__718( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD2), + .PADI(RD2)); + + specify + (PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD2) = (0:0:0,0:0:0); + (RD2 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD2, 0:0:0); + $width (negedge RD2, 0:0:0); + endspecify + +endmodule + +module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 ); + + xo2iobuf Dout_pad_1__719( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD1), + .PADI(RD1)); + + specify + (PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD1) = (0:0:0,0:0:0); + (RD1 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD1, 0:0:0); + $width (negedge RD1, 0:0:0); + endspecify + +endmodule + +module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 ); + + xo2iobuf Dout_pad_0__720( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), + .PADI(RD0)); + + specify + (PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD0) = (0:0:0,0:0:0); + (RD0 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD0, 0:0:0); + $width (negedge RD0, 0:0:0); + endspecify + +endmodule + +module Dout_7_ ( input PADDO, output Dout7 ); + wire GNDI; + + xo2iobuf0068 Dout_pad_7( .I(PADDO), .T(GNDI), .PAD(Dout7)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module xo2iobuf0068 ( input I, T, output PAD ); + + OBZPD INST5( .I(I), .T(T), .O(PAD)); +endmodule + +module Dout_6_ ( input PADDO, output Dout6 ); + wire GNDI; + + xo2iobuf0068 Dout_pad_6( .I(PADDO), .T(GNDI), .PAD(Dout6)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_5_ ( input PADDO, output Dout5 ); + wire GNDI; + + xo2iobuf0068 Dout_pad_5( .I(PADDO), .T(GNDI), .PAD(Dout5)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_4_ ( input PADDO, output Dout4 ); + wire GNDI; + + xo2iobuf0068 Dout_pad_4( .I(PADDO), .T(GNDI), .PAD(Dout4)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_3_ ( input PADDO, output Dout3 ); + wire GNDI; + + xo2iobuf0068 Dout_pad_3( .I(PADDO), .T(GNDI), .PAD(Dout3)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_2_ ( input PADDO, output Dout2 ); + wire GNDI; + + xo2iobuf0068 Dout_pad_2( .I(PADDO), .T(GNDI), .PAD(Dout2)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_1_ ( input PADDO, output Dout1 ); + wire GNDI; + + xo2iobuf0068 Dout_pad_1( .I(PADDO), .T(GNDI), .PAD(Dout1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_0_ ( input PADDO, output Dout0 ); + wire GNDI; + + xo2iobuf0068 Dout_pad_0( .I(PADDO), .T(GNDI), .PAD(Dout0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module LED ( input PADDO, output LED ); + wire GNDI; + + xo2iobuf0068 LED_pad( .I(PADDO), .T(GNDI), .PAD(LED)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => LED) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RBA_1_ ( input PADDO, output RBA1 ); + wire GNDI; + + xo2iobuf0068 RBA_pad_1( .I(PADDO), .T(GNDI), .PAD(RBA1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RBA1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RBA_0_ ( input PADDO, output RBA0 ); + wire GNDI; + + xo2iobuf0068 RBA_pad_0( .I(PADDO), .T(GNDI), .PAD(RBA0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RBA0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_11_ ( input PADDO, output RA11 ); + wire GNDI; + + xo2iobuf0068 RA_pad_11( .I(PADDO), .T(GNDI), .PAD(RA11)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA11) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_10_ ( input PADDO, output RA10 ); + wire GNDI; + + xo2iobuf0068 RA_pad_10( .I(PADDO), .T(GNDI), .PAD(RA10)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA10) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_9_ ( input PADDO, output RA9 ); + wire GNDI; + + xo2iobuf0068 RA_pad_9( .I(PADDO), .T(GNDI), .PAD(RA9)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA9) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_8_ ( input PADDO, output RA8 ); + wire GNDI; + + xo2iobuf0068 RA_pad_8( .I(PADDO), .T(GNDI), .PAD(RA8)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA8) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_7_ ( input PADDO, output RA7 ); + wire GNDI; + + xo2iobuf0068 RA_pad_7( .I(PADDO), .T(GNDI), .PAD(RA7)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_6_ ( input PADDO, output RA6 ); + wire GNDI; + + xo2iobuf0068 RA_pad_6( .I(PADDO), .T(GNDI), .PAD(RA6)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_5_ ( input PADDO, output RA5 ); + wire GNDI; + + xo2iobuf0068 RA_pad_5( .I(PADDO), .T(GNDI), .PAD(RA5)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_4_ ( input PADDO, output RA4 ); + wire GNDI; + + xo2iobuf0068 RA_pad_4( .I(PADDO), .T(GNDI), .PAD(RA4)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_3_ ( input PADDO, output RA3 ); + wire GNDI; + + xo2iobuf0068 RA_pad_3( .I(PADDO), .T(GNDI), .PAD(RA3)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_2_ ( input PADDO, output RA2 ); + wire GNDI; + + xo2iobuf0068 RA_pad_2( .I(PADDO), .T(GNDI), .PAD(RA2)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_1_ ( input PADDO, output RA1 ); + wire GNDI; + + xo2iobuf0068 RA_pad_1( .I(PADDO), .T(GNDI), .PAD(RA1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_0_ ( input PADDO, output RA0 ); + wire GNDI; + + xo2iobuf0068 RA_pad_0( .I(PADDO), .T(GNDI), .PAD(RA0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRCS ( input PADDO, output nRCS ); + wire GNDI; + + xo2iobuf0068 nRCS_pad( .I(PADDO), .T(GNDI), .PAD(nRCS)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nRCS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RCKE ( input PADDO, output RCKE ); + wire GNDI; + + xo2iobuf0068 RCKE_pad( .I(PADDO), .T(GNDI), .PAD(RCKE)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RCKE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRWE ( input PADDO, output nRWE ); + wire GNDI; + + xo2iobuf0068 nRWE_pad( .I(PADDO), .T(GNDI), .PAD(nRWE)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nRWE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRRAS ( input PADDO, output nRRAS ); + wire GNDI; + + xo2iobuf0068 nRRAS_pad( .I(PADDO), .T(GNDI), .PAD(nRRAS)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nRRAS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRCAS ( input PADDO, output nRCAS ); + wire GNDI; + + xo2iobuf0068 nRCAS_pad( .I(PADDO), .T(GNDI), .PAD(nRCAS)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nRCAS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RDQMH ( input PADDO, output RDQMH ); + wire GNDI; + + xo2iobuf0068 RDQMH_pad( .I(PADDO), .T(GNDI), .PAD(RDQMH)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RDQMH) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RDQML ( input PADDO, output RDQML ); + wire GNDI; + + xo2iobuf0068 RDQML_pad( .I(PADDO), .T(GNDI), .PAD(RDQML)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RDQML) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nUFMCS ( input PADDO, output nUFMCS ); + wire GNDI; + + xo2iobuf0068 nUFMCS_pad( .I(PADDO), .T(GNDI), .PAD(nUFMCS)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nUFMCS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module UFMCLK ( input PADDO, output UFMCLK ); + wire GNDI; + + xo2iobuf0068 UFMCLK_pad( .I(PADDO), .T(GNDI), .PAD(UFMCLK)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => UFMCLK) = (0:0:0,0:0:0); + endspecify + +endmodule + +module UFMSDI ( input PADDO, output UFMSDI ); + wire GNDI; + + xo2iobuf0068 UFMSDI_pad( .I(PADDO), .T(GNDI), .PAD(UFMSDI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => UFMSDI) = (0:0:0,0:0:0); + endspecify + +endmodule + +module PHI2 ( output PADDI, input PHI2 ); + + xo2iobuf0069 PHI2_pad( .Z(PADDI), .PAD(PHI2)); + + specify + (PHI2 => PADDI) = (0:0:0,0:0:0); + $width (posedge PHI2, 0:0:0); + $width (negedge PHI2, 0:0:0); + endspecify + +endmodule + +module xo2iobuf0069 ( output Z, input PAD ); + + IBPD INST1( .I(PAD), .O(Z)); +endmodule + +module MAin_9_ ( output PADDI, input MAin9 ); + + xo2iobuf0069 MAin_pad_9( .Z(PADDI), .PAD(MAin9)); + + specify + (MAin9 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin9, 0:0:0); + $width (negedge MAin9, 0:0:0); + endspecify + +endmodule + +module MAin_8_ ( output PADDI, input MAin8 ); + + xo2iobuf0069 MAin_pad_8( .Z(PADDI), .PAD(MAin8)); + + specify + (MAin8 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin8, 0:0:0); + $width (negedge MAin8, 0:0:0); + endspecify + +endmodule + +module MAin_7_ ( output PADDI, input MAin7 ); + + xo2iobuf0069 MAin_pad_7( .Z(PADDI), .PAD(MAin7)); + + specify + (MAin7 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin7, 0:0:0); + $width (negedge MAin7, 0:0:0); + endspecify + +endmodule + +module MAin_6_ ( output PADDI, input MAin6 ); + + xo2iobuf0069 MAin_pad_6( .Z(PADDI), .PAD(MAin6)); + + specify + (MAin6 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin6, 0:0:0); + $width (negedge MAin6, 0:0:0); + endspecify + +endmodule + +module MAin_5_ ( output PADDI, input MAin5 ); + + xo2iobuf0069 MAin_pad_5( .Z(PADDI), .PAD(MAin5)); + + specify + (MAin5 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin5, 0:0:0); + $width (negedge MAin5, 0:0:0); + endspecify + +endmodule + +module MAin_4_ ( output PADDI, input MAin4 ); + + xo2iobuf0069 MAin_pad_4( .Z(PADDI), .PAD(MAin4)); + + specify + (MAin4 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin4, 0:0:0); + $width (negedge MAin4, 0:0:0); + endspecify + +endmodule + +module MAin_3_ ( output PADDI, input MAin3 ); + + xo2iobuf0069 MAin_pad_3( .Z(PADDI), .PAD(MAin3)); + + specify + (MAin3 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin3, 0:0:0); + $width (negedge MAin3, 0:0:0); + endspecify + +endmodule + +module MAin_2_ ( output PADDI, input MAin2 ); + + xo2iobuf0069 MAin_pad_2( .Z(PADDI), .PAD(MAin2)); + + specify + (MAin2 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin2, 0:0:0); + $width (negedge MAin2, 0:0:0); + endspecify + +endmodule + +module MAin_1_ ( output PADDI, input MAin1 ); + + xo2iobuf0069 MAin_pad_1( .Z(PADDI), .PAD(MAin1)); + + specify + (MAin1 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin1, 0:0:0); + $width (negedge MAin1, 0:0:0); + endspecify + +endmodule + +module MAin_0_ ( output PADDI, input MAin0 ); + + xo2iobuf0069 MAin_pad_0( .Z(PADDI), .PAD(MAin0)); + + specify + (MAin0 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin0, 0:0:0); + $width (negedge MAin0, 0:0:0); + endspecify + +endmodule + +module CROW_1_ ( output PADDI, input CROW1 ); + + xo2iobuf0069 CROW_pad_1( .Z(PADDI), .PAD(CROW1)); + + specify + (CROW1 => PADDI) = (0:0:0,0:0:0); + $width (posedge CROW1, 0:0:0); + $width (negedge CROW1, 0:0:0); + endspecify + +endmodule + +module CROW_0_ ( output PADDI, input CROW0 ); + + xo2iobuf0069 CROW_pad_0( .Z(PADDI), .PAD(CROW0)); + + specify + (CROW0 => PADDI) = (0:0:0,0:0:0); + $width (posedge CROW0, 0:0:0); + $width (negedge CROW0, 0:0:0); + endspecify + +endmodule + +module Din_7_ ( output PADDI, input Din7 ); + + xo2iobuf0069 Din_pad_7( .Z(PADDI), .PAD(Din7)); + + specify + (Din7 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din7, 0:0:0); + $width (negedge Din7, 0:0:0); + endspecify + +endmodule + +module Din_6_ ( output PADDI, input Din6 ); + + xo2iobuf0069 Din_pad_6( .Z(PADDI), .PAD(Din6)); + + specify + (Din6 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din6, 0:0:0); + $width (negedge Din6, 0:0:0); + endspecify + +endmodule + +module Din_5_ ( output PADDI, input Din5 ); + + xo2iobuf0069 Din_pad_5( .Z(PADDI), .PAD(Din5)); + + specify + (Din5 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din5, 0:0:0); + $width (negedge Din5, 0:0:0); + endspecify + +endmodule + +module Din_4_ ( output PADDI, input Din4 ); + + xo2iobuf0069 Din_pad_4( .Z(PADDI), .PAD(Din4)); + + specify + (Din4 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din4, 0:0:0); + $width (negedge Din4, 0:0:0); + endspecify + +endmodule + +module Din_3_ ( output PADDI, input Din3 ); + + xo2iobuf0069 Din_pad_3( .Z(PADDI), .PAD(Din3)); + + specify + (Din3 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din3, 0:0:0); + $width (negedge Din3, 0:0:0); + endspecify + +endmodule + +module Din_2_ ( output PADDI, input Din2 ); + + xo2iobuf0069 Din_pad_2( .Z(PADDI), .PAD(Din2)); + + specify + (Din2 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din2, 0:0:0); + $width (negedge Din2, 0:0:0); + endspecify + +endmodule + +module Din_1_ ( output PADDI, input Din1 ); + + xo2iobuf0069 Din_pad_1( .Z(PADDI), .PAD(Din1)); + + specify + (Din1 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din1, 0:0:0); + $width (negedge Din1, 0:0:0); + endspecify + +endmodule + +module Din_0_ ( output PADDI, input Din0 ); + + xo2iobuf0069 Din_pad_0( .Z(PADDI), .PAD(Din0)); + + specify + (Din0 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din0, 0:0:0); + $width (negedge Din0, 0:0:0); + endspecify + +endmodule + +module nCCAS ( output PADDI, input nCCAS ); + + xo2iobuf0069 nCCAS_pad( .Z(PADDI), .PAD(nCCAS)); + + specify + (nCCAS => PADDI) = (0:0:0,0:0:0); + $width (posedge nCCAS, 0:0:0); + $width (negedge nCCAS, 0:0:0); + endspecify + +endmodule + +module nCRAS ( output PADDI, input nCRAS ); + + xo2iobuf0069 nCRAS_pad( .Z(PADDI), .PAD(nCRAS)); + + specify + (nCRAS => PADDI) = (0:0:0,0:0:0); + $width (posedge nCRAS, 0:0:0); + $width (negedge nCRAS, 0:0:0); + endspecify + +endmodule + +module nFWE ( output PADDI, input nFWE ); + + xo2iobuf0069 nFWE_pad( .Z(PADDI), .PAD(nFWE)); + + specify + (nFWE => PADDI) = (0:0:0,0:0:0); + $width (posedge nFWE, 0:0:0); + $width (negedge nFWE, 0:0:0); + endspecify + +endmodule + +module RCLK ( output PADDI, input RCLK ); + + xo2iobuf0069 RCLK_pad( .Z(PADDI), .PAD(RCLK)); + + specify + (RCLK => PADDI) = (0:0:0,0:0:0); + $width (posedge RCLK, 0:0:0); + $width (negedge RCLK, 0:0:0); + endspecify + +endmodule + +module UFMSDO ( output PADDI, input UFMSDO ); + + xo2iobuf0069 UFMSDO_pad( .Z(PADDI), .PAD(UFMSDO)); + + specify + (UFMSDO => PADDI) = (0:0:0,0:0:0); + $width (posedge UFMSDO, 0:0:0); + $width (negedge UFMSDO, 0:0:0); + endspecify + +endmodule diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mrp.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mrp.html new file mode 100644 index 0000000..bf146ce --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mrp.html @@ -0,0 +1,425 @@ + +Project Summary + + +

+            Lattice Mapping Report File for Design Module 'RAM2GS'
+
+
+
+Design Information
+
+Command line:   map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
+     RAM2GS_LCMXO2_1200HC_impl1.ngd -o RAM2GS_LCMXO2_1200HC_impl1_map.ncd -pr
+     RAM2GS_LCMXO2_1200HC_impl1.prf -mp RAM2GS_LCMXO2_1200HC_impl1.mrp -lpf D:/O
+     neDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200
+     HC_impl1.lpf -lpf D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/RA
+     M2GS_LCMXO2_1200HC.lpf -c 0 -gui -msgset
+     D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml 
+Target Vendor:  LATTICE
+Target Device:  LCMXO2-1200HCTQFP100
+Target Performance:   4
+Mapper:  xo2c00,  version:  Diamond (64-bit) 3.12.1.454
+Mapped on:  08/15/23  05:03:26
+
+
+Design Summary
+   Number of registers:    102 out of  1520 (7%)
+      PFU registers:          102 out of  1280 (8%)
+      PIO registers:            0 out of   240 (0%)
+   Number of SLICEs:        75 out of   640 (12%)
+      SLICEs as Logic/ROM:     75 out of   640 (12%)
+      SLICEs as RAM:            0 out of   480 (0%)
+      SLICEs as Carry:         10 out of   640 (2%)
+   Number of LUT4s:        143 out of  1280 (11%)
+      Number used as logic LUTs:        123
+      Number used as distributed RAM:     0
+      Number used as ripple logic:       20
+      Number used as shift registers:     0
+   Number of PIO sites used: 67 + 4(JTAG) out of 80 (89%)
+   Number of block RAMs:  0 out of 7 (0%)
+   Number of GSRs:        0 out of 1 (0%)
+   EFB used :        No
+   JTAG used :       No
+   Readback used :   No
+   Oscillator used : No
+   Startup used :    No
+   POR :             On
+   Bandgap :         On
+   Number of Power Controller:  0 out of 1 (0%)
+   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
+   Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)
+   Number of DCCA:  0 out of 8 (0%)
+   Number of DCMA:  0 out of 2 (0%)
+   Number of PLLs:  0 out of 1 (0%)
+   Number of DQSDLLs:  0 out of 2 (0%)
+   Number of CLKDIVC:  0 out of 4 (0%)
+   Number of ECLKSYNCA:  0 out of 4 (0%)
+   Number of ECLKBRIDGECS:  0 out of 2 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
+     distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and
+     ripple logic.
+   Number of clocks:  4
+     Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK )
+
+     Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
+     Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
+     Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
+   Number of Clock Enables:  14
+     Net RCLK_c_enable_6: 4 loads, 4 LSLICEs
+     Net RCLK_c_enable_5: 2 loads, 2 LSLICEs
+     Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs
+     Net PHI2_N_120_enable_2: 1 loads, 1 LSLICEs
+     Net PHI2_N_120_enable_6: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_27: 8 loads, 8 LSLICEs
+     Net RCLK_c_enable_10: 3 loads, 3 LSLICEs
+     Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_16: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_28: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_15: 1 loads, 1 LSLICEs
+     Net PHI2_N_120_enable_3: 1 loads, 1 LSLICEs
+     Net Ready_N_292: 1 loads, 1 LSLICEs
+     Net PHI2_N_120_enable_8: 2 loads, 2 LSLICEs
+   Number of LSRs:  7
+     Net RASr2: 1 loads, 1 LSLICEs
+     Net nRowColSel_N_35: 1 loads, 1 LSLICEs
+     Net Ready: 7 loads, 7 LSLICEs
+     Net nRWE_N_177: 1 loads, 1 LSLICEs
+     Net C1Submitted_N_237: 2 loads, 2 LSLICEs
+     Net n2366: 2 loads, 2 LSLICEs
+     Net nRowColSel_N_34: 1 loads, 1 LSLICEs
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+     Net Ready: 18 loads
+     Net InitReady: 15 loads
+     Net RASr2: 15 loads
+     Net nRowColSel_N_35: 13 loads
+     Net nRowColSel: 12 loads
+     Net Din_c_4: 10 loads
+     Net MAin_c_1: 10 loads
+     Net Din_c_5: 9 loads
+     Net MAin_c_0: 9 loads
+     Net Din_c_0: 8 loads
+
+
+
+
+   Number of warnings:  0
+   Number of errors:    0
+     
+
+
+
+
+Design Errors/Warnings
+
+   No errors or warnings present.
+
+
+
+IO (PIO) Attributes
+
++---------------------+-----------+-----------+------------+
+| IO Name             | Direction | Levelmode | IO         |
+
+|                     |           |  IO_TYPE  | Register   |
++---------------------+-----------+-----------+------------+
+| RD[7]               | BIDIR     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RD[6]               | BIDIR     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RD[5]               | BIDIR     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RD[4]               | BIDIR     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RD[3]               | BIDIR     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RD[2]               | BIDIR     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RD[1]               | BIDIR     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RD[0]               | BIDIR     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Dout[7]             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Dout[6]             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Dout[5]             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Dout[4]             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Dout[3]             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Dout[2]             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Dout[1]             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Dout[0]             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| LED                 | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RBA[1]              | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RBA[0]              | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[11]              | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[10]              | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[9]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[8]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[7]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[6]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[5]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[4]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+
+| RA[3]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[2]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[1]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[0]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| nRCS                | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RCKE                | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| nRWE                | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| nRRAS               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| nRCAS               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RDQMH               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RDQML               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| nUFMCS              | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| UFMCLK              | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| UFMSDI              | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| PHI2                | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[9]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[8]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[7]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[6]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[5]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[4]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[3]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[2]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[1]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[0]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| CROW[1]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| CROW[0]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Din[7]              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+
+| Din[6]              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Din[5]              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Din[4]              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Din[3]              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Din[2]              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Din[1]              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Din[0]              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| nCCAS               | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| nCRAS               | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| nFWE                | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RCLK                | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| UFMSDO              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+
+
+
+Removed logic
+
+Block i2 undriven or does not drive anything - clipped.
+Block GSR_INST undriven or does not drive anything - clipped.
+Signal PHI2_N_120 was merged into signal PHI2_c
+Signal n1407 was merged into signal nRowColSel_N_34
+Signal n2380 was merged into signal Ready
+Signal n1408 was merged into signal nRowColSel_N_35
+Signal nRWE_N_176 was merged into signal nRWE_N_177
+Signal GND_net undriven or does not drive anything - clipped.
+Signal VCC_net undriven or does not drive anything - clipped.
+Signal FS_610_add_4_19/S1 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_19/CO undriven or does not drive anything - clipped.
+Signal FS_610_add_4_1/S0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_1/CI undriven or does not drive anything - clipped.
+Block i2046 was optimized away.
+Block i1118_1_lut was optimized away.
+Block i637_1_lut_rep_31 was optimized away.
+Block i1119_1_lut was optimized away.
+Block nRWE_I_50_1_lut was optimized away.
+Block i1 was optimized away.
+
+     
+
+
+
+Run Time and Memory Usage
+-------------------------
+
+   Total CPU Time: 0 secs  
+   Total REAL Time: 0 secs  
+   Peak Memory Usage: 41 MB
+
+        
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+     Copyright (c) 1995 AT&T Corp.   All rights reserved.
+     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+     Copyright (c) 2001 Agere Systems   All rights reserved.
+     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
+     reserved.
+
+
+
+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+
+ + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_pad.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_pad.html new file mode 100644 index 0000000..b2d8069 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_pad.html @@ -0,0 +1,374 @@ + +PAD Specification File + + +
PAD Specification File
+***************************
+
+PART TYPE:        LCMXO2-1200HC
+Performance Grade:      4
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.44
+
+Tue Aug 15 05:03:35 2023
+
+Pinout by Port Name:
++-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+
+| Port Name | Pin/Bank | Buffer Type   | Site  | PG Enable | BC Enable | Properties                                               |
++-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+
+| CROW[0]   | 10/3     | LVCMOS25_IN   | PL4B  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| CROW[1]   | 16/3     | LVCMOS25_IN   | PL8A  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Din[0]    | 3/3      | LVCMOS25_IN   | PL3A  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Din[1]    | 96/0     | LVCMOS25_IN   | PT10B |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Din[2]    | 88/0     | LVCMOS25_IN   | PT12A |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Din[3]    | 97/0     | LVCMOS25_IN   | PT10A |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Din[4]    | 99/0     | LVCMOS25_IN   | PT9A  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Din[5]    | 98/0     | LVCMOS25_IN   | PT9B  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Din[6]    | 2/3      | LVCMOS25_IN   | PL2D  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Din[7]    | 1/3      | LVCMOS25_IN   | PL2C  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Dout[0]   | 76/0     | LVCMOS25_OUT  | PT17D |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| Dout[1]   | 86/0     | LVCMOS25_OUT  | PT12C |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| Dout[2]   | 87/0     | LVCMOS25_OUT  | PT12B |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| Dout[3]   | 85/0     | LVCMOS25_OUT  | PT12D |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| Dout[4]   | 83/0     | LVCMOS25_OUT  | PT15B |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| Dout[5]   | 84/0     | LVCMOS25_OUT  | PT15A |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| Dout[6]   | 78/0     | LVCMOS25_OUT  | PT16C |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| Dout[7]   | 82/0     | LVCMOS25_OUT  | PT15C |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| LED       | 34/2     | LVCMOS25_OUT  | PB9A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| MAin[0]   | 14/3     | LVCMOS25_IN   | PL5C  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[1]   | 12/3     | LVCMOS25_IN   | PL5A  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[2]   | 13/3     | LVCMOS25_IN   | PL5B  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[3]   | 21/3     | LVCMOS25_IN   | PL9B  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[4]   | 20/3     | LVCMOS25_IN   | PL9A  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[5]   | 19/3     | LVCMOS25_IN   | PL8D  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[6]   | 24/3     | LVCMOS25_IN   | PL10C |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[7]   | 18/3     | LVCMOS25_IN   | PL8C  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[8]   | 25/3     | LVCMOS25_IN   | PL10D |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[9]   | 32/2     | LVCMOS25_IN   | PB6D  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| PHI2      | 8/3      | LVCMOS25_IN   | PL3D  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| RA[0]     | 66/1     | LVCMOS25_OUT  | PR4D  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[10]    | 64/1     | LVCMOS25_OUT  | PR5B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[11]    | 59/1     | LVCMOS25_OUT  | PR8D  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[1]     | 67/1     | LVCMOS25_OUT  | PR4C  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[2]     | 69/1     | LVCMOS25_OUT  | PR4A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[3]     | 71/1     | LVCMOS25_OUT  | PR3A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[4]     | 74/1     | LVCMOS25_OUT  | PR2B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[5]     | 70/1     | LVCMOS25_OUT  | PR3B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[6]     | 68/1     | LVCMOS25_OUT  | PR4B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[7]     | 75/1     | LVCMOS25_OUT  | PR2A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[8]     | 65/1     | LVCMOS25_OUT  | PR5A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[9]     | 63/1     | LVCMOS25_OUT  | PR5C  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RBA[0]    | 58/1     | LVCMOS25_OUT  | PR9A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RBA[1]    | 60/1     | LVCMOS25_OUT  | PR8C  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RCKE      | 53/1     | LVCMOS25_OUT  | PR9D  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RCLK      | 62/1     | LVCMOS25_IN   | PR5D  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| RDQMH     | 51/1     | LVCMOS25_OUT  | PR10D |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RDQML     | 48/2     | LVCMOS25_OUT  | PB20C |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RD[0]     | 36/2     | LVCMOS25_BIDI | PB11C |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[1]     | 37/2     | LVCMOS25_BIDI | PB11D |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[2]     | 38/2     | LVCMOS25_BIDI | PB11A |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[3]     | 39/2     | LVCMOS25_BIDI | PB11B |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[4]     | 40/2     | LVCMOS25_BIDI | PB15A |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[5]     | 41/2     | LVCMOS25_BIDI | PB15B |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[6]     | 42/2     | LVCMOS25_BIDI | PB18A |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[7]     | 43/2     | LVCMOS25_BIDI | PB18B |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| UFMCLK    | 29/2     | LVCMOS25_OUT  | PB6A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| UFMSDI    | 30/2     | LVCMOS25_OUT  | PB6B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| UFMSDO    | 27/2     | LVCMOS25_IN   | PB4C  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| nCCAS     | 9/3      | LVCMOS25_IN   | PL4A  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| nCRAS     | 17/3     | LVCMOS25_IN   | PL8B  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| nFWE      | 28/2     | LVCMOS25_IN   | PB4D  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| nRCAS     | 52/1     | LVCMOS25_OUT  | PR10C |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| nRCS      | 57/1     | LVCMOS25_OUT  | PR9B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| nRRAS     | 54/1     | LVCMOS25_OUT  | PR9C  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| nRWE      | 49/2     | LVCMOS25_OUT  | PB20D |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| nUFMCS    | 47/2     | LVCMOS25_OUT  | PB18D |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
++-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 2.5V  |
+| 1    | 2.5V  |
+| 2    | 2.5V  |
+| 3    | 2.5V  |
++------+-------+
+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+| Pin/Bank | Pin Info              | Preference | Buffer Type   | Site  | Dual Function | PG Enable | BC Enable |
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+| 1/3      | Din[7]                | LOCATED    | LVCMOS25_IN   | PL2C  | L_GPLLT_IN    |           |           |
+| 2/3      | Din[6]                | LOCATED    | LVCMOS25_IN   | PL2D  | L_GPLLC_IN    |           |           |
+| 3/3      | Din[0]                | LOCATED    | LVCMOS25_IN   | PL3A  | PCLKT3_2      |           |           |
+| 4/3      |     unused, PULL:DOWN |            |               | PL3B  | PCLKC3_2      |           |           |
+| 7/3      |     unused, PULL:DOWN |            |               | PL3C  |               |           |           |
+| 8/3      | PHI2                  | LOCATED    | LVCMOS25_IN   | PL3D  |               |           |           |
+| 9/3      | nCCAS                 | LOCATED    | LVCMOS25_IN   | PL4A  |               |           |           |
+| 10/3     | CROW[0]               | LOCATED    | LVCMOS25_IN   | PL4B  |               |           |           |
+| 12/3     | MAin[1]               | LOCATED    | LVCMOS25_IN   | PL5A  | PCLKT3_1      |           |           |
+| 13/3     | MAin[2]               | LOCATED    | LVCMOS25_IN   | PL5B  | PCLKC3_1      |           |           |
+| 14/3     | MAin[0]               | LOCATED    | LVCMOS25_IN   | PL5C  |               |           |           |
+| 15/3     |     unused, PULL:DOWN |            |               | PL5D  |               |           |           |
+| 16/3     | CROW[1]               | LOCATED    | LVCMOS25_IN   | PL8A  |               |           |           |
+| 17/3     | nCRAS                 | LOCATED    | LVCMOS25_IN   | PL8B  |               |           |           |
+| 18/3     | MAin[7]               | LOCATED    | LVCMOS25_IN   | PL8C  |               |           |           |
+| 19/3     | MAin[5]               | LOCATED    | LVCMOS25_IN   | PL8D  |               |           |           |
+| 20/3     | MAin[4]               | LOCATED    | LVCMOS25_IN   | PL9A  | PCLKT3_0      |           |           |
+| 21/3     | MAin[3]               | LOCATED    | LVCMOS25_IN   | PL9B  | PCLKC3_0      |           |           |
+| 24/3     | MAin[6]               | LOCATED    | LVCMOS25_IN   | PL10C |               |           |           |
+| 25/3     | MAin[8]               | LOCATED    | LVCMOS25_IN   | PL10D |               |           |           |
+| 27/2     | UFMSDO                | LOCATED    | LVCMOS25_IN   | PB4C  | CSSPIN        |           |           |
+| 28/2     | nFWE                  | LOCATED    | LVCMOS25_IN   | PB4D  |               |           |           |
+| 29/2     | UFMCLK                | LOCATED    | LVCMOS25_OUT  | PB6A  |               |           |           |
+| 30/2     | UFMSDI                | LOCATED    | LVCMOS25_OUT  | PB6B  |               |           |           |
+| 31/2     |     unused, PULL:DOWN |            |               | PB6C  | MCLK/CCLK     |           |           |
+| 32/2     | MAin[9]               | LOCATED    | LVCMOS25_IN   | PB6D  | SO/SPISO      |           |           |
+| 34/2     | LED                   | LOCATED    | LVCMOS25_OUT  | PB9A  | PCLKT2_0      |           |           |
+| 35/2     |     unused, PULL:DOWN |            |               | PB9B  | PCLKC2_0      |           |           |
+| 36/2     | RD[0]                 | LOCATED    | LVCMOS25_BIDI | PB11C |               |           |           |
+| 37/2     | RD[1]                 | LOCATED    | LVCMOS25_BIDI | PB11D |               |           |           |
+| 38/2     | RD[2]                 | LOCATED    | LVCMOS25_BIDI | PB11A | PCLKT2_1      |           |           |
+| 39/2     | RD[3]                 | LOCATED    | LVCMOS25_BIDI | PB11B | PCLKC2_1      |           |           |
+| 40/2     | RD[4]                 | LOCATED    | LVCMOS25_BIDI | PB15A |               |           |           |
+| 41/2     | RD[5]                 | LOCATED    | LVCMOS25_BIDI | PB15B |               |           |           |
+| 42/2     | RD[6]                 | LOCATED    | LVCMOS25_BIDI | PB18A |               |           |           |
+| 43/2     | RD[7]                 | LOCATED    | LVCMOS25_BIDI | PB18B |               |           |           |
+| 45/2     |     unused, PULL:DOWN |            |               | PB18C |               |           |           |
+| 47/2     | nUFMCS                |            | LVCMOS25_OUT  | PB18D |               |           |           |
+| 48/2     | RDQML                 | LOCATED    | LVCMOS25_OUT  | PB20C | SN            |           |           |
+| 49/2     | nRWE                  | LOCATED    | LVCMOS25_OUT  | PB20D | SI/SISPI      |           |           |
+| 51/1     | RDQMH                 | LOCATED    | LVCMOS25_OUT  | PR10D | DQ1           |           |           |
+| 52/1     | nRCAS                 | LOCATED    | LVCMOS25_OUT  | PR10C | DQ1           |           |           |
+| 53/1     | RCKE                  | LOCATED    | LVCMOS25_OUT  | PR9D  | DQ1           |           |           |
+| 54/1     | nRRAS                 | LOCATED    | LVCMOS25_OUT  | PR9C  | DQ1           |           |           |
+| 57/1     | nRCS                  | LOCATED    | LVCMOS25_OUT  | PR9B  | DQ1           |           |           |
+| 58/1     | RBA[0]                | LOCATED    | LVCMOS25_OUT  | PR9A  | DQ1           |           |           |
+| 59/1     | RA[11]                | LOCATED    | LVCMOS25_OUT  | PR8D  | DQ1           |           |           |
+| 60/1     | RBA[1]                | LOCATED    | LVCMOS25_OUT  | PR8C  | DQ1           |           |           |
+| 61/1     |     unused, PULL:DOWN |            |               | PR8A  | DQS1          |           |           |
+| 62/1     | RCLK                  | LOCATED    | LVCMOS25_IN   | PR5D  | PCLKC1_0/DQ0  |           |           |
+| 63/1     | RA[9]                 | LOCATED    | LVCMOS25_OUT  | PR5C  | PCLKT1_0/DQ0  |           |           |
+| 64/1     | RA[10]                | LOCATED    | LVCMOS25_OUT  | PR5B  | DQS0N         |           |           |
+| 65/1     | RA[8]                 | LOCATED    | LVCMOS25_OUT  | PR5A  | DQS0          |           |           |
+| 66/1     | RA[0]                 | LOCATED    | LVCMOS25_OUT  | PR4D  | DQ0           |           |           |
+| 67/1     | RA[1]                 | LOCATED    | LVCMOS25_OUT  | PR4C  | DQ0           |           |           |
+| 68/1     | RA[6]                 | LOCATED    | LVCMOS25_OUT  | PR4B  | DQ0           |           |           |
+| 69/1     | RA[2]                 | LOCATED    | LVCMOS25_OUT  | PR4A  | DQ0           |           |           |
+| 70/1     | RA[5]                 | LOCATED    | LVCMOS25_OUT  | PR3B  | DQ0           |           |           |
+| 71/1     | RA[3]                 | LOCATED    | LVCMOS25_OUT  | PR3A  | DQ0           |           |           |
+| 74/1     | RA[4]                 | LOCATED    | LVCMOS25_OUT  | PR2B  | DQ0           |           |           |
+| 75/1     | RA[7]                 | LOCATED    | LVCMOS25_OUT  | PR2A  | DQ0           |           |           |
+| 76/0     | Dout[0]               | LOCATED    | LVCMOS25_OUT  | PT17D | DONE          |           |           |
+| 77/0     |     unused, PULL:DOWN |            |               | PT17C | INITN         |           |           |
+| 78/0     | Dout[6]               | LOCATED    | LVCMOS25_OUT  | PT16C |               |           |           |
+| 81/0     |     unused, PULL:DOWN |            |               | PT15D | PROGRAMN      |           |           |
+| 82/0     | Dout[7]               | LOCATED    | LVCMOS25_OUT  | PT15C | JTAGENB       |           |           |
+| 83/0     | Dout[4]               | LOCATED    | LVCMOS25_OUT  | PT15B |               |           |           |
+| 84/0     | Dout[5]               | LOCATED    | LVCMOS25_OUT  | PT15A |               |           |           |
+| 85/0     | Dout[3]               | LOCATED    | LVCMOS25_OUT  | PT12D | SDA/PCLKC0_0  |           |           |
+| 86/0     | Dout[1]               | LOCATED    | LVCMOS25_OUT  | PT12C | SCL/PCLKT0_0  |           |           |
+| 87/0     | Dout[2]               | LOCATED    | LVCMOS25_OUT  | PT12B | PCLKC0_1      |           |           |
+| 88/0     | Din[2]                | LOCATED    | LVCMOS25_IN   | PT12A | PCLKT0_1      |           |           |
+| 90/0     | Reserved: sysCONFIG   |            |               | PT11D | TMS           |           |           |
+| 91/0     | Reserved: sysCONFIG   |            |               | PT11C | TCK           |           |           |
+| 94/0     | Reserved: sysCONFIG   |            |               | PT10D | TDI           |           |           |
+| 95/0     | Reserved: sysCONFIG   |            |               | PT10C | TDO           |           |           |
+| 96/0     | Din[1]                | LOCATED    | LVCMOS25_IN   | PT10B |               |           |           |
+| 97/0     | Din[3]                | LOCATED    | LVCMOS25_IN   | PT10A |               |           |           |
+| 98/0     | Din[5]                | LOCATED    | LVCMOS25_IN   | PT9B  |               |           |           |
+| 99/0     | Din[4]                | LOCATED    | LVCMOS25_IN   | PT9A  |               |           |           |
+| PB4A/2   |     unused, PULL:DOWN |            |               | PB4A  |               |           |           |
+| PB4B/2   |     unused, PULL:DOWN |            |               | PB4B  |               |           |           |
+| PB9C/2   |     unused, PULL:DOWN |            |               | PB9C  |               |           |           |
+| PB9D/2   |     unused, PULL:DOWN |            |               | PB9D  |               |           |           |
+| PB15C/2  |     unused, PULL:DOWN |            |               | PB15C |               |           |           |
+| PB15D/2  |     unused, PULL:DOWN |            |               | PB15D |               |           |           |
+| PB20A/2  |     unused, PULL:DOWN |            |               | PB20A |               |           |           |
+| PB20B/2  |     unused, PULL:DOWN |            |               | PB20B |               |           |           |
+| PL2A/3   |     unused, PULL:DOWN |            |               | PL2A  | L_GPLLT_FB    |           |           |
+| PL2B/3   |     unused, PULL:DOWN |            |               | PL2B  | L_GPLLC_FB    |           |           |
+| PL4C/3   |     unused, PULL:DOWN |            |               | PL4C  |               |           |           |
+| PL4D/3   |     unused, PULL:DOWN |            |               | PL4D  |               |           |           |
+| PL10A/3  |     unused, PULL:DOWN |            |               | PL10A |               |           |           |
+| PL10B/3  |     unused, PULL:DOWN |            |               | PL10B |               |           |           |
+| PR2C/1   |     unused, PULL:DOWN |            |               | PR2C  | DQ0           |           |           |
+| PR2D/1   |     unused, PULL:DOWN |            |               | PR2D  | DQ0           |           |           |
+| PR8B/1   |     unused, PULL:DOWN |            |               | PR8B  | DQS1N         |           |           |
+| PR10A/1  |     unused, PULL:DOWN |            |               | PR10A | DQ1           |           |           |
+| PR10B/1  |     unused, PULL:DOWN |            |               | PR10B | DQ1           |           |           |
+| PT9C/0   |     unused, PULL:DOWN |            |               | PT9C  |               |           |           |
+| PT9D/0   |     unused, PULL:DOWN |            |               | PT9D  |               |           |           |
+| PT11A/0  |     unused, PULL:DOWN |            |               | PT11A |               |           |           |
+| PT11B/0  |     unused, PULL:DOWN |            |               | PT11B |               |           |           |
+| PT16A/0  |     unused, PULL:DOWN |            |               | PT16A |               |           |           |
+| PT16B/0  |     unused, PULL:DOWN |            |               | PT16B |               |           |           |
+| PT16D/0  |     unused, PULL:DOWN |            |               | PT16D |               |           |           |
+| PT17A/0  |     unused, PULL:DOWN |            |               | PT17A |               |           |           |
+| PT17B/0  |     unused, PULL:DOWN |            |               | PT17B |               |           |           |
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+
+sysCONFIG Pins:
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode  |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| PT11D    | TMS                | JTAG_PORT=ENABLE   | 90/0     |             | PULLUP            |
+| PT11C    | TCK/TEST_CLK       | JTAG_PORT=ENABLE   | 91/0     |             | NO pull up/down   |
+| PT10D    | TDI/MD7            | JTAG_PORT=ENABLE   | 94/0     |             | PULLUP            |
+| PT10C    | TDO                | JTAG_PORT=ENABLE   | 95/0     |             | PULLUP            |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+
+Dedicated sysCONFIG Pins:
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "CROW[0]"  SITE  "10";
+LOCATE  COMP  "CROW[1]"  SITE  "16";
+LOCATE  COMP  "Din[0]"  SITE  "3";
+LOCATE  COMP  "Din[1]"  SITE  "96";
+LOCATE  COMP  "Din[2]"  SITE  "88";
+LOCATE  COMP  "Din[3]"  SITE  "97";
+LOCATE  COMP  "Din[4]"  SITE  "99";
+LOCATE  COMP  "Din[5]"  SITE  "98";
+LOCATE  COMP  "Din[6]"  SITE  "2";
+LOCATE  COMP  "Din[7]"  SITE  "1";
+LOCATE  COMP  "Dout[0]"  SITE  "76";
+LOCATE  COMP  "Dout[1]"  SITE  "86";
+LOCATE  COMP  "Dout[2]"  SITE  "87";
+LOCATE  COMP  "Dout[3]"  SITE  "85";
+LOCATE  COMP  "Dout[4]"  SITE  "83";
+LOCATE  COMP  "Dout[5]"  SITE  "84";
+LOCATE  COMP  "Dout[6]"  SITE  "78";
+LOCATE  COMP  "Dout[7]"  SITE  "82";
+LOCATE  COMP  "LED"  SITE  "34";
+LOCATE  COMP  "MAin[0]"  SITE  "14";
+LOCATE  COMP  "MAin[1]"  SITE  "12";
+LOCATE  COMP  "MAin[2]"  SITE  "13";
+LOCATE  COMP  "MAin[3]"  SITE  "21";
+LOCATE  COMP  "MAin[4]"  SITE  "20";
+LOCATE  COMP  "MAin[5]"  SITE  "19";
+LOCATE  COMP  "MAin[6]"  SITE  "24";
+LOCATE  COMP  "MAin[7]"  SITE  "18";
+LOCATE  COMP  "MAin[8]"  SITE  "25";
+LOCATE  COMP  "MAin[9]"  SITE  "32";
+LOCATE  COMP  "PHI2"  SITE  "8";
+LOCATE  COMP  "RA[0]"  SITE  "66";
+LOCATE  COMP  "RA[10]"  SITE  "64";
+LOCATE  COMP  "RA[11]"  SITE  "59";
+LOCATE  COMP  "RA[1]"  SITE  "67";
+LOCATE  COMP  "RA[2]"  SITE  "69";
+LOCATE  COMP  "RA[3]"  SITE  "71";
+LOCATE  COMP  "RA[4]"  SITE  "74";
+LOCATE  COMP  "RA[5]"  SITE  "70";
+LOCATE  COMP  "RA[6]"  SITE  "68";
+LOCATE  COMP  "RA[7]"  SITE  "75";
+LOCATE  COMP  "RA[8]"  SITE  "65";
+LOCATE  COMP  "RA[9]"  SITE  "63";
+LOCATE  COMP  "RBA[0]"  SITE  "58";
+LOCATE  COMP  "RBA[1]"  SITE  "60";
+LOCATE  COMP  "RCKE"  SITE  "53";
+LOCATE  COMP  "RCLK"  SITE  "62";
+LOCATE  COMP  "RDQMH"  SITE  "51";
+LOCATE  COMP  "RDQML"  SITE  "48";
+LOCATE  COMP  "RD[0]"  SITE  "36";
+LOCATE  COMP  "RD[1]"  SITE  "37";
+LOCATE  COMP  "RD[2]"  SITE  "38";
+LOCATE  COMP  "RD[3]"  SITE  "39";
+LOCATE  COMP  "RD[4]"  SITE  "40";
+LOCATE  COMP  "RD[5]"  SITE  "41";
+LOCATE  COMP  "RD[6]"  SITE  "42";
+LOCATE  COMP  "RD[7]"  SITE  "43";
+LOCATE  COMP  "UFMCLK"  SITE  "29";
+LOCATE  COMP  "UFMSDI"  SITE  "30";
+LOCATE  COMP  "UFMSDO"  SITE  "27";
+LOCATE  COMP  "nCCAS"  SITE  "9";
+LOCATE  COMP  "nCRAS"  SITE  "17";
+LOCATE  COMP  "nFWE"  SITE  "28";
+LOCATE  COMP  "nRCAS"  SITE  "52";
+LOCATE  COMP  "nRCS"  SITE  "57";
+LOCATE  COMP  "nRRAS"  SITE  "54";
+LOCATE  COMP  "nRWE"  SITE  "49";
+LOCATE  COMP  "nUFMCS"  SITE  "47";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 15 05:03:38 2023
+
+
+
+
+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+
+ + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_par.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_par.html new file mode 100644 index 0000000..2db9546 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_par.html @@ -0,0 +1,397 @@ + +Place & Route Report + + +
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 15 05:03:31 2023
+
+C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_1200HC_impl1.p2t
+RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir
+RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset
+D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
+
+
+Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf.
+
+Cost Table Summary
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            -4.650       391939       0.304        0            08           Completed
+* : Design saved.
+
+Total (real) run time for 1-seed: 8 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Lattice Place and Route Report for Design "RAM2GS_LCMXO2_1200HC_impl1_map.ncd"
+Tue Aug 15 05:03:31 2023
+
+
+Best Par Run
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
+Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file RAM2GS_LCMXO2_1200HC_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 4
+Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.44.
+Performance Hardware Data Status:   Final          Version 34.4.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+
+Device utilization summary:
+
+   PIO (prelim)   67+4(JTAG)/108     66% used
+                  67+4(JTAG)/80      89% bonded
+
+   SLICE             75/640          11% used
+
+
+
+Number of Signals: 285
+Number of Connections: 674
+WARNING - par: Placement timing preferences are hard to meet. However, placement will continue. Use static timing analysis to identify errors.
+
+Pin Constraint Summary:
+   66 out of 67 pins locked (98% locked).
+
+The following 2 signals are selected to use the primary clock routing resources:
+    RCLK_c (driver: RCLK, clk load #: 40)
+    PHI2_c (driver: PHI2, clk load #: 13)
+
+WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+
+The following 1 signal is selected to use the secondary clock routing resources:
+    nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0)
+
+WARNING - par: Signal "nCRAS_c" is selected to use Secondary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+No signal is selected as Global Set/Reset.
+.
+Starting Placer Phase 0.
+..........
+Finished Placer Phase 0.  REAL time: 0 secs 
+
+Starting Placer Phase 1.
+...................
+Placer score = 143529.
+Finished Placer Phase 1.  REAL time: 4 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  143450
+Finished Placer Phase 2.  REAL time: 4 secs 
+
+
+
+Clock Report
+
+Global Clock Resources:
+  CLK_PIN    : 0 out of 8 (0%)
+  General PIO: 3 out of 108 (2%)
+  PLL        : 0 out of 1 (0%)
+  DCM        : 0 out of 2 (0%)
+  DCC        : 0 out of 8 (0%)
+
+Global Clocks:
+  PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 40
+  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3D)", clk load = 13
+  SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL8B)", clk load = 7, ce load = 0, sr load = 0
+
+  PRIMARY  : 2 out of 8 (25%)
+  SECONDARY: 1 out of 8 (12%)
+
+Edge Clocks:
+  No edge clock selected.
+
+
+
+
+I/O Usage Summary (final):
+   67 + 4(JTAG) out of 108 (65.7%) PIO sites used.
+   67 + 4(JTAG) out of 80 (88.8%) bonded PIO sites used.
+   Number of PIO comps: 67; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+-----------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref |
++----------+----------------+------------+-----------+
+| 0        | 13 / 19 ( 68%) | 2.5V       | -         |
+| 1        | 20 / 21 ( 95%) | 2.5V       | -         |
+| 2        | 17 / 20 ( 85%) | 2.5V       | -         |
+| 3        | 17 / 20 ( 85%) | 2.5V       | -         |
++----------+----------------+------------+-----------+
+
+Total placer CPU time: 4 secs 
+
+Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd.
+
+0 connections routed; 674 unrouted.
+Starting router resource preassignment
+WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
+WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=nCCAS_c loads=6 clock_loads=4
+
+Completed router resource preassignment. Real time: 7 secs 
+
+Start NBR router at 05:03:38 08/15/23
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 05:03:38 08/15/23
+
+Start NBR section for initial routing at 05:03:38 08/15/23
+Level 1, iteration 1
+2(0.00%) conflicts; 537(79.67%) untouched conns; 468417 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -5.186ns/-468.418ns; real time: 7 secs 
+Level 2, iteration 1
+11(0.01%) conflicts; 474(70.33%) untouched conns; 377050 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-377.051ns; real time: 8 secs 
+Level 3, iteration 1
+20(0.02%) conflicts; 254(37.69%) untouched conns; 373495 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-373.496ns; real time: 8 secs 
+Level 4, iteration 1
+11(0.01%) conflicts; 0(0.00%) untouched conn; 386254 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-386.255ns; real time: 8 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 05:03:39 08/15/23
+Level 1, iteration 1
+7(0.01%) conflicts; 4(0.59%) untouched conns; 379537 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-379.537ns; real time: 8 secs 
+Level 4, iteration 1
+9(0.01%) conflicts; 0(0.00%) untouched conn; 380799 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-380.800ns; real time: 8 secs 
+Level 4, iteration 2
+6(0.01%) conflicts; 0(0.00%) untouched conn; 390586 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-390.587ns; real time: 8 secs 
+Level 4, iteration 3
+6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-384.719ns; real time: 8 secs 
+Level 4, iteration 4
+6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-384.719ns; real time: 8 secs 
+Level 4, iteration 5
+4(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-393.014ns; real time: 8 secs 
+Level 4, iteration 6
+3(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-393.014ns; real time: 8 secs 
+Level 4, iteration 7
+3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-393.875ns; real time: 8 secs 
+Level 4, iteration 8
+3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-393.875ns; real time: 8 secs 
+Level 4, iteration 9
+2(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-409.289ns; real time: 8 secs 
+Level 4, iteration 10
+3(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-409.289ns; real time: 8 secs 
+Level 4, iteration 11
+3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-393.036ns; real time: 8 secs 
+Level 4, iteration 12
+3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-393.036ns; real time: 8 secs 
+Level 4, iteration 13
+2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.574ns/-404.327ns; real time: 8 secs 
+Level 4, iteration 14
+2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.574ns/-404.327ns; real time: 8 secs 
+Level 4, iteration 15
+2(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs 
+Level 4, iteration 16
+3(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs 
+Level 4, iteration 17
+2(0.00%) conflicts; 0(0.00%) untouched conn; 404668 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.574ns/-404.669ns; real time: 8 secs 
+Level 4, iteration 18
+1(0.00%) conflict; 0(0.00%) untouched conn; 404668 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.574ns/-404.669ns; real time: 8 secs 
+Level 4, iteration 19
+1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs 
+Level 4, iteration 20
+1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs 
+Level 4, iteration 21
+1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs 
+Level 4, iteration 22
+1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs 
+Level 4, iteration 23
+1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.277ns; real time: 8 secs 
+Level 4, iteration 24
+1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.277ns; real time: 8 secs 
+Level 4, iteration 25
+0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.953ns; real time: 8 secs 
+
+Start NBR section for performance tuning (iteration 1) at 05:03:39 08/15/23
+Level 4, iteration 1
+1(0.00%) conflict; 0(0.00%) untouched conn; 405829 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-405.830ns; real time: 8 secs 
+Level 4, iteration 2
+0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.953ns; real time: 8 secs 
+
+Start NBR section for re-routing at 05:03:39 08/15/23
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.953ns; real time: 8 secs 
+
+Start NBR section for post-routing at 05:03:39 08/15/23
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 254 (37.69%)
+  Estimated worst slack<setup> : -4.650ns
+  Timing score<setup> : 391939
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=nCCAS_c loads=6 clock_loads=4
+
+Total CPU time 7 secs 
+Total REAL time: 8 secs 
+Completely routed.
+End of route.  674 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 391939 
+
+Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack<setup/<ns>> = -4.650
+PAR_SUMMARY::Timing score<setup/<ns>> = 391.939
+PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.304
+PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 8 secs 
+Total REAL time to completion: 8 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+
+
+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+
+ + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_summary.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_summary.html new file mode 100644 index 0000000..affe710 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_summary.html @@ -0,0 +1,83 @@ + +Project Summary + + +

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
RAM2GS_LCMXO2_1200HC project summary
Module Name:RAM2GS_LCMXO2_1200HCSynthesis:Lattice LSE
Implementation Name:impl1Strategy Name:Strategy1
Last Process:JEDEC FileState:Passed
Target Device:LCMXO2-1200HC-4TG100CDevice Family:MachXO2
Device Type:LCMXO2-1200HCPackage Type:TQFP100
Performance grade:4Operating conditions:COM
Logic preference file:RAM2GS_LCMXO2_1200HC.lpf
Physical Preference file:impl1/RAM2GS_LCMXO2_1200HC_impl1.prf
Product Version:3.12.1.454Patch Version:
Updated:2023/08/15 05:03:45
Implementation Location:D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1
Project File:D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf

+

+

+

+

+

+
+ + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_tw1.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_tw1.html new file mode 100644 index 0000000..2254cfa --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_tw1.html @@ -0,0 +1,430 @@ + +Lattice Map TRACE Report + + +
Map TRACE Report
+
+Loading design for application trce from file ram2gs_lcmxo2_1200hc_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 4
+Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.44.
+Performance Hardware Data Status:   Final          Version 34.4.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
+Tue Aug 15 05:03:28 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_1200HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_1200hc_impl1_map.ncd
+Preference file: ram2gs_lcmxo2_1200hc_impl1.prf
+Device,speed:    LCMXO2-1200HC,4
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "RCLK_c" 299.401000 MHz (245 errors)
    • 
+                459 items scored, 245 timing errors detected.
+Warning: 139.762MHz is the maximum frequency for this preference.
+
+
  • FREQUENCY NET "PHI2_c" 99.079000 MHz (104 errors)
    • 
+                113 items scored, 104 timing errors detected.
+Warning:  50.592MHz is the maximum frequency for this preference.
+
+Report Type:     based on TRACE automatically generated preferences
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
+            459 items scored, 245 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 3.815ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i13  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_418  (to RCLK_c +)
+
+   Delay:               6.873ns  (28.2% logic, 71.8% route), 4 logic levels.
+
+ Constraint Details:
+
+      6.873ns physical path delay SLICE_0 to SLICE_57 exceeds
+      3.340ns delay constraint less
+      0.282ns CE_SET requirement (totaling 3.058ns) by 3.815ns
+
+ Physical Path Details:
+
+      Data path SLICE_0 to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452    SLICE_0.CLK to     SLICE_0.Q0 SLICE_0 (from RCLK_c)
+ROUTE         3   e 1.234     SLICE_0.Q0 to    SLICE_85.B0 FS_13
+CTOF_DEL    ---     0.495    SLICE_85.B0 to    SLICE_85.F0 SLICE_85
+ROUTE         5   e 1.234    SLICE_85.F0 to    SLICE_57.A1 n10
+CTOF_DEL    ---     0.495    SLICE_57.A1 to    SLICE_57.F1 SLICE_57
+ROUTE         2   e 1.234    SLICE_57.F1 to    SLICE_84.A0 n2367
+CTOF_DEL    ---     0.495    SLICE_84.A0 to    SLICE_84.F0 SLICE_84
+ROUTE         1   e 1.234    SLICE_84.F0 to    SLICE_57.CE RCLK_c_enable_15 (to RCLK_c)
+                  --------
+                    6.873   (28.2% logic, 71.8% route), 4 logic levels.
+
+Warning: 139.762MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
+            113 items scored, 104 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 4.837ns (weighted slack = -9.674ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               9.577ns  (30.6% logic, 69.4% route), 6 logic levels.
+
+ Constraint Details:
+
+      9.577ns physical path delay SLICE_101 to SLICE_19 exceeds
+      5.047ns delay constraint less
+      0.307ns CE_SET requirement (totaling 4.740ns) by 4.837ns
+
+ Physical Path Details:
+
+      Data path SLICE_101 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452  SLICE_101.CLK to   SLICE_101.Q1 SLICE_101 (from PHI2_c)
+ROUTE         1   e 1.234   SLICE_101.Q1 to   SLICE_100.C1 Bank_7
+CTOF_DEL    ---     0.495   SLICE_100.C1 to   SLICE_100.F1 SLICE_100
+ROUTE         1   e 1.234   SLICE_100.F1 to    SLICE_74.B1 n2277
+CTOF_DEL    ---     0.495    SLICE_74.B1 to    SLICE_74.F1 SLICE_74
+ROUTE         8   e 1.234    SLICE_74.F1 to    SLICE_91.B1 n26
+CTOF_DEL    ---     0.495    SLICE_91.B1 to    SLICE_91.F1 SLICE_91
+ROUTE         1   e 1.234    SLICE_91.F1 to    SLICE_88.D0 n2362
+CTOF_DEL    ---     0.495    SLICE_88.D0 to    SLICE_88.F0 SLICE_88
+ROUTE         3   e 0.480    SLICE_88.F0 to    SLICE_88.C1 C1Submitted_N_237
+CTOF_DEL    ---     0.495    SLICE_88.C1 to    SLICE_88.F1 SLICE_88
+ROUTE         1   e 1.234    SLICE_88.F1 to    SLICE_19.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    9.577   (30.6% logic, 69.4% route), 6 logic levels.
+
+Warning:  50.592MHz is the maximum frequency for this preference.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "RCLK_c" 299.401000 MHz ; |  299.401 MHz|  139.762 MHz|   4 *
+                                        |             |             |
+FREQUENCY NET "PHI2_c" 99.079000 MHz ;  |   99.079 MHz|   50.592 MHz|   6 *
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+2 preferences(marked by "*" above) not met.
+
+----------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+----------------------------------------------------------------------------
+n26                                     |       8|      78|     22.35%
+                                        |        |        |
+----------------------------------------------------------------------------
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
+   Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 349  Score: 848079
+Cumulative negative slack: 584487
+
+Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
+Tue Aug 15 05:03:28 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_1200HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_1200hc_impl1_map.ncd
+Preference file: ram2gs_lcmxo2_1200hc_impl1.prf
+Device,speed:    LCMXO2-1200HC,M
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "RCLK_c" 299.401000 MHz (0 errors)
    •             459 items scored, 0 timing errors detected.
+
+
  • FREQUENCY NET "PHI2_c" 99.079000 MHz (0 errors)
    •             113 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
+            459 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.351ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i4  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i5  (to RCLK_c +)
+
+   Delay:               0.332ns  (40.1% logic, 59.9% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.332ns physical path delay SLICE_106 to SLICE_106 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
+
+ Physical Path Details:
+
+      Data path SLICE_106 to SLICE_106:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133  SLICE_106.CLK to   SLICE_106.Q0 SLICE_106 (from RCLK_c)
+ROUTE         1   e 0.199   SLICE_106.Q0 to   SLICE_106.M1 n736 (to RCLK_c)
+                  --------
+                    0.332   (40.1% logic, 59.9% route), 1 logic levels.
+
+
+================================================================================
+Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
+            113 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.447ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_406  (from PHI2_c -)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               0.434ns  (53.9% logic, 46.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.434ns physical path delay SLICE_15 to SLICE_15 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
+
+ Physical Path Details:
+
+      Data path SLICE_15 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_15.CLK to    SLICE_15.Q0 SLICE_15 (from PHI2_c)
+ROUTE         2   e 0.199    SLICE_15.Q0 to    SLICE_15.C0 C1Submitted
+CTOF_DEL    ---     0.101    SLICE_15.C0 to    SLICE_15.F0 SLICE_15
+ROUTE         1   e 0.001    SLICE_15.F0 to   SLICE_15.DI0 n1398 (to PHI2_c)
+                  --------
+                    0.434   (53.9% logic, 46.1% route), 2 logic levels.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "RCLK_c" 299.401000 MHz ; |     0.000 ns|     0.351 ns|   1  
+                                        |             |             |
+FREQUENCY NET "PHI2_c" 99.079000 MHz ;  |     0.000 ns|     0.447 ns|   2  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
+   Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 349 (setup), 0 (hold)
+Score: 848079 (setup), 0 (hold)
+Cumulative negative slack: 584487 (584487+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_twr.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_twr.html new file mode 100644 index 0000000..eab0fb8 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_twr.html @@ -0,0 +1,2244 @@ + +Lattice TRACE Report + + +
    Place & Route TRACE Report
+
+Loading design for application trce from file ram2gs_lcmxo2_1200hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 4
+Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.44.
+Performance Hardware Data Status:   Final          Version 34.4.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
+Tue Aug 15 05:03:40 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_1200HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_1200hc_impl1.ncd
+Preference file: ram2gs_lcmxo2_1200hc_impl1.prf
+Device,speed:    LCMXO2-1200HC,4
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "RCLK_c" 299.401000 MHz (247 errors)
    • 
+                459 items scored, 247 timing errors detected.
+Warning: 174.216MHz is the maximum frequency for this preference.
+
+
  • FREQUENCY NET "PHI2_c" 99.079000 MHz (88 errors)
    • 
+                113 items scored, 88 timing errors detected.
+Warning:  67.833MHz is the maximum frequency for this preference.
+
+Report Type:     based on TRACE automatically generated preferences
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
+            459 items scored, 247 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 2.400ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i12  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
+
+   Delay:               5.574ns  (43.6% logic, 56.4% route), 5 logic levels.
+
+ Constraint Details:
+
+      5.574ns physical path delay SLICE_1 to SLICE_44 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.400ns
+
+ Physical Path Details:
+
+      Data path SLICE_1 to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R7C15C.CLK to      R7C15C.Q1 SLICE_1 (from RCLK_c)
+ROUTE         5     1.440      R7C15C.Q1 to      R8C15A.B0 FS_12
+CTOF_DEL    ---     0.495      R8C15A.B0 to      R8C15A.F0 SLICE_105
+ROUTE         1     0.626      R8C15A.F0 to      R8C15D.D1 n12
+CTOF_DEL    ---     0.495      R8C15D.D1 to      R8C15D.F1 SLICE_82
+ROUTE         3     0.640      R8C15D.F1 to      R8C16B.D1 n13_adj_6
+CTOF_DEL    ---     0.495      R8C16B.D1 to      R8C16B.F1 SLICE_44
+ROUTE         1     0.436      R8C16B.F1 to      R8C16B.C0 n1893
+CTOF_DEL    ---     0.495      R8C16B.C0 to      R8C16B.F0 SLICE_44
+ROUTE         1     0.000      R8C16B.F0 to     R8C16B.DI0 UFMCLK_N_224 (to RCLK_c)
+                  --------
+                    5.574   (43.6% logic, 56.4% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R7C15C.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R8C16B.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.383ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i12  (from RCLK_c +)
+   Destination:    FF         Data in        InitReady_394  (to RCLK_c +)
+
+   Delay:               5.441ns  (35.6% logic, 64.4% route), 4 logic levels.
+
+ Constraint Details:
+
+      5.441ns physical path delay SLICE_1 to SLICE_26 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.282ns CE_SET requirement (totaling 3.058ns) by 2.383ns
+
+ Physical Path Details:
+
+      Data path SLICE_1 to SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R7C15C.CLK to      R7C15C.Q1 SLICE_1 (from RCLK_c)
+ROUTE         5     1.440      R7C15C.Q1 to      R8C15A.B0 FS_12
+CTOF_DEL    ---     0.495      R8C15A.B0 to      R8C15A.F0 SLICE_105
+ROUTE         1     0.626      R8C15A.F0 to      R8C15D.D1 n12
+CTOF_DEL    ---     0.495      R8C15D.D1 to      R8C15D.F1 SLICE_82
+ROUTE         3     0.453      R8C15D.F1 to      R8C15D.C0 n13_adj_6
+CTOF_DEL    ---     0.495      R8C15D.C0 to      R8C15D.F0 SLICE_82
+ROUTE         1     0.985      R8C15D.F0 to      R8C13D.CE RCLK_c_enable_28 (to RCLK_c)
+                  --------
+                    5.441   (35.6% logic, 64.4% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R7C15C.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R8C13D.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.217ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i16  (from RCLK_c +)
+   Destination:    FF         Data in        nUFMCS_415  (to RCLK_c +)
+
+   Delay:               5.391ns  (45.1% logic, 54.9% route), 5 logic levels.
+
+ Constraint Details:
+
+      5.391ns physical path delay SLICE_9 to SLICE_70 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.217ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R7C16A.CLK to      R7C16A.Q1 SLICE_9 (from RCLK_c)
+ROUTE         3     1.017      R7C16A.Q1 to      R7C16D.B0 FS_16
+CTOF_DEL    ---     0.495      R7C16D.B0 to      R7C16D.F0 SLICE_85
+ROUTE         5     0.340      R7C16D.F0 to      R7C17A.D1 n10
+CTOF_DEL    ---     0.495      R7C17A.D1 to      R7C17A.F1 SLICE_76
+ROUTE         2     0.635      R7C17A.F1 to      R7C17D.D1 n2368
+CTOF_DEL    ---     0.495      R7C17D.D1 to      R7C17D.F1 SLICE_70
+ROUTE         1     0.967      R7C17D.F1 to      R7C17D.A0 n64
+CTOF_DEL    ---     0.495      R7C17D.A0 to      R7C17D.F0 SLICE_70
+ROUTE         1     0.000      R7C17D.F0 to     R7C17D.DI0 nUFMCS_N_199 (to RCLK_c)
+                  --------
+                    5.391   (45.1% logic, 54.9% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R7C16A.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R7C17D.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.180ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i15  (from RCLK_c +)
+   Destination:    FF         Data in        nUFMCS_415  (to RCLK_c +)
+
+   Delay:               5.354ns  (45.4% logic, 54.6% route), 5 logic levels.
+
+ Constraint Details:
+
+      5.354ns physical path delay SLICE_9 to SLICE_70 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.180ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R7C16A.CLK to      R7C16A.Q0 SLICE_9 (from RCLK_c)
+ROUTE         3     0.980      R7C16A.Q0 to      R7C16D.A0 FS_15
+CTOF_DEL    ---     0.495      R7C16D.A0 to      R7C16D.F0 SLICE_85
+ROUTE         5     0.340      R7C16D.F0 to      R7C17A.D1 n10
+CTOF_DEL    ---     0.495      R7C17A.D1 to      R7C17A.F1 SLICE_76
+ROUTE         2     0.635      R7C17A.F1 to      R7C17D.D1 n2368
+CTOF_DEL    ---     0.495      R7C17D.D1 to      R7C17D.F1 SLICE_70
+ROUTE         1     0.967      R7C17D.F1 to      R7C17D.A0 n64
+CTOF_DEL    ---     0.495      R7C17D.A0 to      R7C17D.F0 SLICE_70
+ROUTE         1     0.000      R7C17D.F0 to     R7C17D.DI0 nUFMCS_N_199 (to RCLK_c)
+                  --------
+                    5.354   (45.4% logic, 54.6% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R7C16A.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R7C17D.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i16  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
+
+   Delay:               5.340ns  (45.5% logic, 54.5% route), 5 logic levels.
+
+ Constraint Details:
+
+      5.340ns physical path delay SLICE_9 to SLICE_44 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.166ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R7C16A.CLK to      R7C16A.Q1 SLICE_9 (from RCLK_c)
+ROUTE         3     1.206      R7C16A.Q1 to      R8C15A.C0 FS_16
+CTOF_DEL    ---     0.495      R8C15A.C0 to      R8C15A.F0 SLICE_105
+ROUTE         1     0.626      R8C15A.F0 to      R8C15D.D1 n12
+CTOF_DEL    ---     0.495      R8C15D.D1 to      R8C15D.F1 SLICE_82
+ROUTE         3     0.640      R8C15D.F1 to      R8C16B.D1 n13_adj_6
+CTOF_DEL    ---     0.495      R8C16B.D1 to      R8C16B.F1 SLICE_44
+ROUTE         1     0.436      R8C16B.F1 to      R8C16B.C0 n1893
+CTOF_DEL    ---     0.495      R8C16B.C0 to      R8C16B.F0 SLICE_44
+ROUTE         1     0.000      R8C16B.F0 to     R8C16B.DI0 UFMCLK_N_224 (to RCLK_c)
+                  --------
+                    5.340   (45.5% logic, 54.5% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R7C16A.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R8C16B.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.158ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i16  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
+
+   Delay:               5.332ns  (45.6% logic, 54.4% route), 5 logic levels.
+
+ Constraint Details:
+
+      5.332ns physical path delay SLICE_9 to SLICE_44 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.158ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R7C16A.CLK to      R7C16A.Q1 SLICE_9 (from RCLK_c)
+ROUTE         3     1.017      R7C16A.Q1 to      R7C16D.B0 FS_16
+CTOF_DEL    ---     0.495      R7C16D.B0 to      R7C16D.F0 SLICE_85
+ROUTE         5     0.461      R7C16D.F0 to      R7C16D.C1 n10
+CTOF_DEL    ---     0.495      R7C16D.C1 to      R7C16D.F1 SLICE_85
+ROUTE         1     0.986      R7C16D.F1 to      R8C16B.A1 n2267
+CTOF_DEL    ---     0.495      R8C16B.A1 to      R8C16B.F1 SLICE_44
+ROUTE         1     0.436      R8C16B.F1 to      R8C16B.C0 n1893
+CTOF_DEL    ---     0.495      R8C16B.C0 to      R8C16B.F0 SLICE_44
+ROUTE         1     0.000      R8C16B.F0 to     R8C16B.DI0 UFMCLK_N_224 (to RCLK_c)
+                  --------
+                    5.332   (45.6% logic, 54.4% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R7C16A.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R8C16B.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.149ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i16  (from RCLK_c +)
+   Destination:    FF         Data in        InitReady_394  (to RCLK_c +)
+
+   Delay:               5.207ns  (37.2% logic, 62.8% route), 4 logic levels.
+
+ Constraint Details:
+
+      5.207ns physical path delay SLICE_9 to SLICE_26 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.282ns CE_SET requirement (totaling 3.058ns) by 2.149ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R7C16A.CLK to      R7C16A.Q1 SLICE_9 (from RCLK_c)
+ROUTE         3     1.206      R7C16A.Q1 to      R8C15A.C0 FS_16
+CTOF_DEL    ---     0.495      R8C15A.C0 to      R8C15A.F0 SLICE_105
+ROUTE         1     0.626      R8C15A.F0 to      R8C15D.D1 n12
+CTOF_DEL    ---     0.495      R8C15D.D1 to      R8C15D.F1 SLICE_82
+ROUTE         3     0.453      R8C15D.F1 to      R8C15D.C0 n13_adj_6
+CTOF_DEL    ---     0.495      R8C15D.C0 to      R8C15D.F0 SLICE_82
+ROUTE         1     0.985      R8C15D.F0 to      R8C13D.CE RCLK_c_enable_28 (to RCLK_c)
+                  --------
+                    5.207   (37.2% logic, 62.8% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R7C16A.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R8C13D.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.131ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i7  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_418  (to RCLK_c +)
+
+   Delay:               5.189ns  (37.3% logic, 62.7% route), 4 logic levels.
+
+ Constraint Details:
+
+      5.189ns physical path delay SLICE_2 to SLICE_57 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.282ns CE_SET requirement (totaling 3.058ns) by 2.131ns
+
+ Physical Path Details:
+
+      Data path SLICE_2 to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R7C15A.CLK to      R7C15A.Q0 SLICE_2 (from RCLK_c)
+ROUTE         3     1.086      R7C15A.Q0 to      R8C14D.D0 FS_7
+CTOF_DEL    ---     0.495      R8C14D.D0 to      R8C14D.F0 SLICE_95
+ROUTE         1     0.747      R8C14D.F0 to      R8C14A.C0 n15
+CTOF_DEL    ---     0.495      R8C14A.C0 to      R8C14A.F0 SLICE_86
+ROUTE         1     0.766      R8C14A.F0 to      R8C16C.C0 n4_adj_7
+CTOF_DEL    ---     0.495      R8C16C.C0 to      R8C16C.F0 SLICE_84
+ROUTE         1     0.653      R8C16C.F0 to      R8C16A.CE RCLK_c_enable_15 (to RCLK_c)
+                  --------
+                    5.189   (37.3% logic, 62.7% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_2:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R7C15A.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R8C16A.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.121ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i15  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
+
+   Delay:               5.295ns  (45.9% logic, 54.1% route), 5 logic levels.
+
+ Constraint Details:
+
+      5.295ns physical path delay SLICE_9 to SLICE_44 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.121ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R7C16A.CLK to      R7C16A.Q0 SLICE_9 (from RCLK_c)
+ROUTE         3     0.980      R7C16A.Q0 to      R7C16D.A0 FS_15
+CTOF_DEL    ---     0.495      R7C16D.A0 to      R7C16D.F0 SLICE_85
+ROUTE         5     0.461      R7C16D.F0 to      R7C16D.C1 n10
+CTOF_DEL    ---     0.495      R7C16D.C1 to      R7C16D.F1 SLICE_85
+ROUTE         1     0.986      R7C16D.F1 to      R8C16B.A1 n2267
+CTOF_DEL    ---     0.495      R8C16B.A1 to      R8C16B.F1 SLICE_44
+ROUTE         1     0.436      R8C16B.F1 to      R8C16B.C0 n1893
+CTOF_DEL    ---     0.495      R8C16B.C0 to      R8C16B.F0 SLICE_44
+ROUTE         1     0.000      R8C16B.F0 to     R8C16B.DI0 UFMCLK_N_224 (to RCLK_c)
+                  --------
+                    5.295   (45.9% logic, 54.1% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R7C16A.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R8C16B.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.087ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i12  (from RCLK_c +)
+   Destination:    FF         Data in        UFMSDI_417  (to RCLK_c +)
+
+   Delay:               5.261ns  (46.2% logic, 53.8% route), 5 logic levels.
+
+ Constraint Details:
+
+      5.261ns physical path delay SLICE_1 to SLICE_45 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.087ns
+
+ Physical Path Details:
+
+      Data path SLICE_1 to SLICE_45:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R7C15C.CLK to      R7C15C.Q1 SLICE_1 (from RCLK_c)
+ROUTE         5     0.786      R7C15C.Q1 to      R8C15C.C1 FS_12
+CTOF_DEL    ---     0.495      R8C15C.C1 to      R8C15C.F1 SLICE_80
+ROUTE         3     0.640      R8C15C.F1 to      R8C14D.D1 n2375
+CTOF_DEL    ---     0.495      R8C14D.D1 to      R8C14D.F1 SLICE_95
+ROUTE         1     0.967      R8C14D.F1 to      R8C14C.A1 n7
+CTOF_DEL    ---     0.495      R8C14C.A1 to      R8C14C.F1 SLICE_45
+ROUTE         1     0.436      R8C14C.F1 to      R8C14C.C0 n2174
+CTOF_DEL    ---     0.495      R8C14C.C0 to      R8C14C.F0 SLICE_45
+ROUTE         1     0.000      R8C14C.F0 to     R8C14C.DI0 UFMSDI_N_231 (to RCLK_c)
+                  --------
+                    5.261   (46.2% logic, 53.8% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R7C15C.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_45:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R8C14C.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+Warning: 174.216MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
+            113 items scored, 88 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 2.325ns (weighted slack = -4.650ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               7.065ns  (41.4% logic, 58.6% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.065ns physical path delay SLICE_101 to SLICE_19 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 4.740ns) by 2.325ns
+
+ Physical Path Details:
+
+      Data path SLICE_101 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R9C16C.CLK to      R9C16C.Q0 SLICE_101 (from PHI2_c)
+ROUTE         1     0.986      R9C16C.Q0 to      R9C14A.A0 Bank_6
+CTOF_DEL    ---     0.495      R9C14A.A0 to      R9C14A.F0 SLICE_68
+ROUTE         1     0.766      R9C14A.F0 to      R9C15B.C1 n2287
+CTOF_DEL    ---     0.495      R9C15B.C1 to      R9C15B.F1 SLICE_74
+ROUTE         8     0.662      R9C15B.F1 to      R9C14D.D1 n26
+CTOF_DEL    ---     0.495      R9C14D.D1 to      R9C14D.F1 SLICE_91
+ROUTE         1     0.626      R9C14D.F1 to      R9C14C.D0 n2362
+CTOF_DEL    ---     0.495      R9C14C.D0 to      R9C14C.F0 SLICE_88
+ROUTE         3     0.445      R9C14C.F0 to      R9C14C.C1 C1Submitted_N_237
+CTOF_DEL    ---     0.495      R9C14C.C1 to      R9C14C.F1 SLICE_88
+ROUTE         1     0.653      R9C14C.F1 to      R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    7.065   (41.4% logic, 58.6% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_101:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to     R9C16C.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to     R9C14B.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.287ns (weighted slack = -4.574ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i1  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               7.027ns  (41.7% logic, 58.3% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.027ns physical path delay SLICE_93 to SLICE_19 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 4.740ns) by 2.287ns
+
+ Physical Path Details:
+
+      Data path SLICE_93 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R9C16A.CLK to      R9C16A.Q1 SLICE_93 (from PHI2_c)
+ROUTE         1     0.744      R9C16A.Q1 to      R9C15C.C1 Bank_1
+CTOF_DEL    ---     0.495      R9C15C.C1 to      R9C15C.F1 SLICE_99
+ROUTE         2     0.635      R9C15C.F1 to      R9C15D.D1 n22
+CTOF_DEL    ---     0.495      R9C15D.D1 to      R9C15D.F1 SLICE_79
+ROUTE         7     0.997      R9C15D.F1 to      R9C14D.A1 n2369
+CTOF_DEL    ---     0.495      R9C14D.A1 to      R9C14D.F1 SLICE_91
+ROUTE         1     0.626      R9C14D.F1 to      R9C14C.D0 n2362
+CTOF_DEL    ---     0.495      R9C14C.D0 to      R9C14C.F0 SLICE_88
+ROUTE         3     0.445      R9C14C.F0 to      R9C14C.C1 C1Submitted_N_237
+CTOF_DEL    ---     0.495      R9C14C.C1 to      R9C14C.F1 SLICE_88
+ROUTE         1     0.653      R9C14C.F1 to      R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    7.027   (41.7% logic, 58.3% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to     R9C16A.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to     R9C14B.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.166ns (weighted slack = -4.332ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i4  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               6.906ns  (42.4% logic, 57.6% route), 6 logic levels.
+
+ Constraint Details:
+
+      6.906ns physical path delay SLICE_102 to SLICE_19 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 4.740ns) by 2.166ns
+
+ Physical Path Details:
+
+      Data path SLICE_102 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R8C15B.CLK to      R8C15B.Q0 SLICE_102 (from PHI2_c)
+ROUTE         1     0.623      R8C15B.Q0 to      R9C15C.D1 Bank_4
+CTOF_DEL    ---     0.495      R9C15C.D1 to      R9C15C.F1 SLICE_99
+ROUTE         2     0.635      R9C15C.F1 to      R9C15D.D1 n22
+CTOF_DEL    ---     0.495      R9C15D.D1 to      R9C15D.F1 SLICE_79
+ROUTE         7     0.997      R9C15D.F1 to      R9C14D.A1 n2369
+CTOF_DEL    ---     0.495      R9C14D.A1 to      R9C14D.F1 SLICE_91
+ROUTE         1     0.626      R9C14D.F1 to      R9C14C.D0 n2362
+CTOF_DEL    ---     0.495      R9C14C.D0 to      R9C14C.F0 SLICE_88
+ROUTE         3     0.445      R9C14C.F0 to      R9C14C.C1 C1Submitted_N_237
+CTOF_DEL    ---     0.495      R9C14C.C1 to      R9C14C.F1 SLICE_88
+ROUTE         1     0.653      R9C14C.F1 to      R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    6.906   (42.4% logic, 57.6% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_102:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to     R8C15B.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to     R9C14B.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.984ns (weighted slack = -3.968ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i3  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               6.724ns  (43.5% logic, 56.5% route), 6 logic levels.
+
+ Constraint Details:
+
+      6.724ns physical path delay SLICE_103 to SLICE_19 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 4.740ns) by 1.984ns
+
+ Physical Path Details:
+
+      Data path SLICE_103 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R9C16D.CLK to      R9C16D.Q1 SLICE_103 (from PHI2_c)
+ROUTE         1     0.645      R9C16D.Q1 to      R9C14A.D0 Bank_3
+CTOF_DEL    ---     0.495      R9C14A.D0 to      R9C14A.F0 SLICE_68
+ROUTE         1     0.766      R9C14A.F0 to      R9C15B.C1 n2287
+CTOF_DEL    ---     0.495      R9C15B.C1 to      R9C15B.F1 SLICE_74
+ROUTE         8     0.662      R9C15B.F1 to      R9C14D.D1 n26
+CTOF_DEL    ---     0.495      R9C14D.D1 to      R9C14D.F1 SLICE_91
+ROUTE         1     0.626      R9C14D.F1 to      R9C14C.D0 n2362
+CTOF_DEL    ---     0.495      R9C14C.D0 to      R9C14C.F0 SLICE_88
+ROUTE         3     0.445      R9C14C.F0 to      R9C14C.C1 C1Submitted_N_237
+CTOF_DEL    ---     0.495      R9C14C.C1 to      R9C14C.F1 SLICE_88
+ROUTE         1     0.653      R9C14C.F1 to      R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    6.724   (43.5% logic, 56.5% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_103:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to     R9C16D.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to     R9C14B.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.874ns (weighted slack = -3.748ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               6.614ns  (44.3% logic, 55.7% route), 6 logic levels.
+
+ Constraint Details:
+
+      6.614ns physical path delay SLICE_101 to SLICE_19 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 4.740ns) by 1.874ns
+
+ Physical Path Details:
+
+      Data path SLICE_101 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R9C16C.CLK to      R9C16C.Q1 SLICE_101 (from PHI2_c)
+ROUTE         1     0.986      R9C16C.Q1 to      R9C15A.A1 Bank_7
+CTOF_DEL    ---     0.495      R9C15A.A1 to      R9C15A.F1 SLICE_100
+ROUTE         1     0.315      R9C15A.F1 to      R9C15B.D1 n2277
+CTOF_DEL    ---     0.495      R9C15B.D1 to      R9C15B.F1 SLICE_74
+ROUTE         8     0.662      R9C15B.F1 to      R9C14D.D1 n26
+CTOF_DEL    ---     0.495      R9C14D.D1 to      R9C14D.F1 SLICE_91
+ROUTE         1     0.626      R9C14D.F1 to      R9C14C.D0 n2362
+CTOF_DEL    ---     0.495      R9C14C.D0 to      R9C14C.F0 SLICE_88
+ROUTE         3     0.445      R9C14C.F0 to      R9C14C.C1 C1Submitted_N_237
+CTOF_DEL    ---     0.495      R9C14C.C1 to      R9C14C.F1 SLICE_88
+ROUTE         1     0.653      R9C14C.F1 to      R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    6.614   (44.3% logic, 55.7% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_101:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to     R9C16C.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to     R9C14B.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.803ns (weighted slack = -3.606ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        ADSubmitted_407  (to PHI2_c -)
+
+   Delay:               6.565ns  (37.0% logic, 63.0% route), 5 logic levels.
+
+ Constraint Details:
+
+      6.565ns physical path delay SLICE_101 to SLICE_10 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.285ns LSR_SET requirement (totaling 4.762ns) by 1.803ns
+
+ Physical Path Details:
+
+      Data path SLICE_101 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R9C16C.CLK to      R9C16C.Q0 SLICE_101 (from PHI2_c)
+ROUTE         1     0.986      R9C16C.Q0 to      R9C14A.A0 Bank_6
+CTOF_DEL    ---     0.495      R9C14A.A0 to      R9C14A.F0 SLICE_68
+ROUTE         1     0.766      R9C14A.F0 to      R9C15B.C1 n2287
+CTOF_DEL    ---     0.495      R9C15B.C1 to      R9C15B.F1 SLICE_74
+ROUTE         8     0.662      R9C15B.F1 to      R9C14D.D1 n26
+CTOF_DEL    ---     0.495      R9C14D.D1 to      R9C14D.F1 SLICE_91
+ROUTE         1     0.626      R9C14D.F1 to      R9C14C.D0 n2362
+CTOF_DEL    ---     0.495      R9C14C.D0 to      R9C14C.F0 SLICE_88
+ROUTE         3     1.093      R9C14C.F0 to    R10C14B.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    6.565   (37.0% logic, 63.0% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_101:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to     R9C16C.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to    R10C14B.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.803ns (weighted slack = -3.606ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               6.565ns  (37.0% logic, 63.0% route), 5 logic levels.
+
+ Constraint Details:
+
+      6.565ns physical path delay SLICE_101 to SLICE_15 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.285ns LSR_SET requirement (totaling 4.762ns) by 1.803ns
+
+ Physical Path Details:
+
+      Data path SLICE_101 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R9C16C.CLK to      R9C16C.Q0 SLICE_101 (from PHI2_c)
+ROUTE         1     0.986      R9C16C.Q0 to      R9C14A.A0 Bank_6
+CTOF_DEL    ---     0.495      R9C14A.A0 to      R9C14A.F0 SLICE_68
+ROUTE         1     0.766      R9C14A.F0 to      R9C15B.C1 n2287
+CTOF_DEL    ---     0.495      R9C15B.C1 to      R9C15B.F1 SLICE_74
+ROUTE         8     0.662      R9C15B.F1 to      R9C14D.D1 n26
+CTOF_DEL    ---     0.495      R9C14D.D1 to      R9C14D.F1 SLICE_91
+ROUTE         1     0.626      R9C14D.F1 to      R9C14C.D0 n2362
+CTOF_DEL    ---     0.495      R9C14C.D0 to      R9C14C.F0 SLICE_88
+ROUTE         3     1.093      R9C14C.F0 to    R10C14C.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    6.565   (37.0% logic, 63.0% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_101:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to     R9C16C.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to    R10C14C.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.765ns (weighted slack = -3.530ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i1  (from PHI2_c +)
+   Destination:    FF         Data in        ADSubmitted_407  (to PHI2_c -)
+
+   Delay:               6.527ns  (37.3% logic, 62.7% route), 5 logic levels.
+
+ Constraint Details:
+
+      6.527ns physical path delay SLICE_93 to SLICE_10 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.285ns LSR_SET requirement (totaling 4.762ns) by 1.765ns
+
+ Physical Path Details:
+
+      Data path SLICE_93 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R9C16A.CLK to      R9C16A.Q1 SLICE_93 (from PHI2_c)
+ROUTE         1     0.744      R9C16A.Q1 to      R9C15C.C1 Bank_1
+CTOF_DEL    ---     0.495      R9C15C.C1 to      R9C15C.F1 SLICE_99
+ROUTE         2     0.635      R9C15C.F1 to      R9C15D.D1 n22
+CTOF_DEL    ---     0.495      R9C15D.D1 to      R9C15D.F1 SLICE_79
+ROUTE         7     0.997      R9C15D.F1 to      R9C14D.A1 n2369
+CTOF_DEL    ---     0.495      R9C14D.A1 to      R9C14D.F1 SLICE_91
+ROUTE         1     0.626      R9C14D.F1 to      R9C14C.D0 n2362
+CTOF_DEL    ---     0.495      R9C14C.D0 to      R9C14C.F0 SLICE_88
+ROUTE         3     1.093      R9C14C.F0 to    R10C14B.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    6.527   (37.3% logic, 62.7% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to     R9C16A.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to    R10C14B.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.765ns (weighted slack = -3.530ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i1  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               6.527ns  (37.3% logic, 62.7% route), 5 logic levels.
+
+ Constraint Details:
+
+      6.527ns physical path delay SLICE_93 to SLICE_15 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.285ns LSR_SET requirement (totaling 4.762ns) by 1.765ns
+
+ Physical Path Details:
+
+      Data path SLICE_93 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R9C16A.CLK to      R9C16A.Q1 SLICE_93 (from PHI2_c)
+ROUTE         1     0.744      R9C16A.Q1 to      R9C15C.C1 Bank_1
+CTOF_DEL    ---     0.495      R9C15C.C1 to      R9C15C.F1 SLICE_99
+ROUTE         2     0.635      R9C15C.F1 to      R9C15D.D1 n22
+CTOF_DEL    ---     0.495      R9C15D.D1 to      R9C15D.F1 SLICE_79
+ROUTE         7     0.997      R9C15D.F1 to      R9C14D.A1 n2369
+CTOF_DEL    ---     0.495      R9C14D.A1 to      R9C14D.F1 SLICE_91
+ROUTE         1     0.626      R9C14D.F1 to      R9C14C.D0 n2362
+CTOF_DEL    ---     0.495      R9C14C.D0 to      R9C14C.F0 SLICE_88
+ROUTE         3     1.093      R9C14C.F0 to    R10C14C.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    6.527   (37.3% logic, 62.7% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to     R9C16A.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to    R10C14C.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.750ns (weighted slack = -3.500ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               6.490ns  (37.5% logic, 62.5% route), 5 logic levels.
+
+ Constraint Details:
+
+      6.490ns physical path delay SLICE_101 to SLICE_19 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 4.740ns) by 1.750ns
+
+ Physical Path Details:
+
+      Data path SLICE_101 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R9C16C.CLK to      R9C16C.Q0 SLICE_101 (from PHI2_c)
+ROUTE         1     0.986      R9C16C.Q0 to      R9C14A.A0 Bank_6
+CTOF_DEL    ---     0.495      R9C14A.A0 to      R9C14A.F0 SLICE_68
+ROUTE         1     0.766      R9C14A.F0 to      R9C15B.C1 n2287
+CTOF_DEL    ---     0.495      R9C15B.C1 to      R9C15B.F1 SLICE_74
+ROUTE         8     0.688      R9C15B.F1 to     R10C15C.D0 n26
+CTOF_DEL    ---     0.495     R10C15C.D0 to     R10C15C.F0 SLICE_104
+ROUTE         2     0.965     R10C15C.F0 to      R9C14C.D1 n2363
+CTOF_DEL    ---     0.495      R9C14C.D1 to      R9C14C.F1 SLICE_88
+ROUTE         1     0.653      R9C14C.F1 to      R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    6.490   (37.5% logic, 62.5% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_101:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to     R9C16C.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to     R9C14B.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+Warning:  67.833MHz is the maximum frequency for this preference.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "RCLK_c" 299.401000 MHz ; |  299.401 MHz|  174.216 MHz|   5 *
+                                        |             |             |
+FREQUENCY NET "PHI2_c" 99.079000 MHz ;  |   99.079 MHz|   67.833 MHz|   6 *
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+2 preferences(marked by "*" above) not met.
+
+----------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+----------------------------------------------------------------------------
+n26                                     |       8|      64|     19.10%
+                                        |        |        |
+n1996                                   |       1|      49|     14.63%
+                                        |        |        |
+n1997                                   |       1|      46|     13.73%
+                                        |        |        |
+n1995                                   |       1|      45|     13.43%
+                                        |        |        |
+n1998                                   |       1|      38|     11.34%
+                                        |        |        |
+n1994                                   |       1|      37|     11.04%
+                                        |        |        |
+----------------------------------------------------------------------------
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
+   Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 335  Score: 391939
+Cumulative negative slack: 304509
+
+Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
+Tue Aug 15 05:03:40 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_1200HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_1200hc_impl1.ncd
+Preference file: ram2gs_lcmxo2_1200hc_impl1.prf
+Device,speed:    LCMXO2-1200HC,m
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "RCLK_c" 299.401000 MHz (0 errors)
    •             459 items scored, 0 timing errors detected.
+
+
  • FREQUENCY NET "PHI2_c" 99.079000 MHz (0 errors)
    •             113 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
+            459 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i4  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i5  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_106 to SLICE_106 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_106 to SLICE_106:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    R10C13B.CLK to     R10C13B.Q0 SLICE_106 (from RCLK_c)
+ROUTE         1     0.152     R10C13B.Q0 to     R10C13B.M1 n736 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_106:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to    R10C13B.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_106:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to    R10C13B.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CASr_382  (from RCLK_c +)
+   Destination:    FF         Data in        CASr2_383  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_16 to SLICE_16 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_16 to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R7C12B.CLK to      R7C12B.Q0 SLICE_16 (from RCLK_c)
+ROUTE         1     0.152      R7C12B.Q0 to      R7C12B.M1 CASr (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to     R7C12B.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to     R7C12B.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i8  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i9  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_75 to SLICE_75 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_75 to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    R10C13D.CLK to     R10C13D.Q0 SLICE_75 (from RCLK_c)
+ROUTE         1     0.152     R10C13D.Q0 to     R10C13D.M1 n732 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to    R10C13D.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to    R10C13D.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i12  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i13  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_78 to SLICE_78 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_78 to SLICE_78:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R8C12B.CLK to      R8C12B.Q0 SLICE_78 (from RCLK_c)
+ROUTE         1     0.152      R8C12B.Q0 to      R8C12B.M1 n728 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_78:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to     R8C12B.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_78:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to     R8C12B.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i14  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i15  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_81 to SLICE_81 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_81 to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R9C12A.CLK to      R9C12A.Q0 SLICE_81 (from RCLK_c)
+ROUTE         1     0.152      R9C12A.Q0 to      R9C12A.M1 n726 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to     R9C12A.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to     R9C12A.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i2  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i3  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_84 to SLICE_84 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_84 to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R8C16C.CLK to      R8C16C.Q0 SLICE_84 (from RCLK_c)
+ROUTE         1     0.152      R8C16C.Q0 to      R8C16C.M1 n738 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to     R8C16C.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to     R8C16C.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i6  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i7  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_97 to SLICE_97 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_97 to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    R10C14A.CLK to     R10C14A.Q0 SLICE_97 (from RCLK_c)
+ROUTE         1     0.152     R10C14A.Q0 to     R10C14A.M1 n734 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to    R10C14A.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to    R10C14A.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.306ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RASr_379  (from RCLK_c +)
+   Destination:    FF         Data in        RASr2_380  (to RCLK_c +)
+
+   Delay:               0.287ns  (46.3% logic, 53.7% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.287ns physical path delay SLICE_30 to SLICE_30 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.306ns
+
+ Physical Path Details:
+
+      Data path SLICE_30 to SLICE_30:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R8C13B.CLK to      R8C13B.Q0 SLICE_30 (from RCLK_c)
+ROUTE         2     0.154      R8C13B.Q0 to      R8C13B.M1 RASr (to RCLK_c)
+                  --------
+                    0.287   (46.3% logic, 53.7% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_30:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to     R8C13B.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_30:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to     R8C13B.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.306ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i1  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i2  (to RCLK_c +)
+
+   Delay:               0.287ns  (46.3% logic, 53.7% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.287ns physical path delay SLICE_98 to SLICE_84 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.306ns
+
+ Physical Path Details:
+
+      Data path SLICE_98 to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R8C16D.CLK to      R8C16D.Q1 SLICE_98 (from RCLK_c)
+ROUTE         4     0.154      R8C16D.Q1 to      R8C16C.M0 nRCAS_N_165 (to RCLK_c)
+                  --------
+                    0.287   (46.3% logic, 53.7% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to     R8C16D.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to     R8C16C.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.306ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i0  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i1  (to RCLK_c +)
+
+   Delay:               0.287ns  (46.3% logic, 53.7% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.287ns physical path delay SLICE_98 to SLICE_98 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.306ns
+
+ Physical Path Details:
+
+      Data path SLICE_98 to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R8C16D.CLK to      R8C16D.Q0 SLICE_98 (from RCLK_c)
+ROUTE         4     0.154      R8C16D.Q0 to      R8C16D.M1 nRCS_N_139 (to RCLK_c)
+                  --------
+                    0.287   (46.3% logic, 53.7% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to     R8C16D.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to     R8C16D.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
+            113 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_406  (from PHI2_c -)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_15 to SLICE_15 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_15 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    R10C14C.CLK to     R10C14C.Q0 SLICE_15 (from PHI2_c)
+ROUTE         2     0.132     R10C14C.Q0 to     R10C14C.A0 C1Submitted
+CTOF_DEL    ---     0.101     R10C14C.A0 to     R10C14C.F0 SLICE_15
+ROUTE         1     0.000     R10C14C.F0 to    R10C14C.DI0 n1398 (to PHI2_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to    R10C14C.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to    R10C14C.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.629ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_407  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               0.601ns  (38.9% logic, 61.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.601ns physical path delay SLICE_10 to SLICE_19 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 0.629ns
+
+ Physical Path Details:
+
+      Data path SLICE_10 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    R10C14B.CLK to     R10C14B.Q0 SLICE_10 (from PHI2_c)
+ROUTE         1     0.224     R10C14B.Q0 to      R9C14C.B1 ADSubmitted
+CTOF_DEL    ---     0.101      R9C14C.B1 to      R9C14C.F1 SLICE_88
+ROUTE         1     0.143      R9C14C.F1 to      R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    0.601   (38.9% logic, 61.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to    R10C14B.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to     R9C14B.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.715ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        XOR8MEG_408  (to PHI2_c -)
+
+   Delay:               0.687ns  (34.1% logic, 65.9% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.687ns physical path delay SLICE_19 to SLICE_50 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 0.715ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_50:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R9C14B.CLK to      R9C14B.Q0 SLICE_19 (from PHI2_c)
+ROUTE         2     0.310      R9C14B.Q0 to     R10C15B.B1 CmdEnable
+CTOF_DEL    ---     0.101     R10C15B.B1 to     R10C15B.F1 SLICE_83
+ROUTE         1     0.143     R10C15B.F1 to     R10C15D.CE PHI2_N_120_enable_3 (to PHI2_c)
+                  --------
+                    0.687   (34.1% logic, 65.9% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to     R9C14B.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_50:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to    R10C15D.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.873ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMCS_412  (to PHI2_c -)
+                   FF                        CmdUFMCLK_413
+
+   Delay:               0.845ns  (39.6% logic, 60.4% route), 3 logic levels.
+
+ Constraint Details:
+
+      0.845ns physical path delay SLICE_19 to SLICE_100 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 0.873ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_100:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R9C14B.CLK to      R9C14B.Q0 SLICE_19 (from PHI2_c)
+ROUTE         2     0.224      R9C14B.Q0 to     R10C15A.C0 CmdEnable
+CTOF_DEL    ---     0.101     R10C15A.C0 to     R10C15A.F0 SLICE_73
+ROUTE         2     0.138     R10C15A.F0 to     R10C15A.C1 n2204
+CTOF_DEL    ---     0.101     R10C15A.C1 to     R10C15A.F1 SLICE_73
+ROUTE         2     0.148     R10C15A.F1 to      R9C15A.CE PHI2_N_120_enable_8 (to PHI2_c)
+                  --------
+                    0.845   (39.6% logic, 60.4% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to     R9C14B.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_100:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to     R9C15A.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.873ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMSDI_414  (to PHI2_c -)
+
+   Delay:               0.845ns  (39.6% logic, 60.4% route), 3 logic levels.
+
+ Constraint Details:
+
+      0.845ns physical path delay SLICE_19 to SLICE_99 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 0.873ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R9C14B.CLK to      R9C14B.Q0 SLICE_19 (from PHI2_c)
+ROUTE         2     0.224      R9C14B.Q0 to     R10C15A.C0 CmdEnable
+CTOF_DEL    ---     0.101     R10C15A.C0 to     R10C15A.F0 SLICE_73
+ROUTE         2     0.138     R10C15A.F0 to     R10C15A.C1 n2204
+CTOF_DEL    ---     0.101     R10C15A.C1 to     R10C15A.F1 SLICE_73
+ROUTE         2     0.148     R10C15A.F1 to      R9C15C.CE PHI2_N_120_enable_8 (to PHI2_c)
+                  --------
+                    0.845   (39.6% logic, 60.4% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to     R9C14B.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to     R9C15C.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.252ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_406  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               1.224ns  (35.6% logic, 64.4% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.224ns physical path delay SLICE_15 to SLICE_19 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 1.252ns
+
+ Physical Path Details:
+
+      Data path SLICE_15 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    R10C14C.CLK to     R10C14C.Q0 SLICE_15 (from PHI2_c)
+ROUTE         2     0.212     R10C14C.Q0 to     R10C14D.A1 C1Submitted
+CTOF_DEL    ---     0.101     R10C14D.A1 to     R10C14D.F1 SLICE_77
+ROUTE         1     0.222     R10C14D.F1 to     R10C14A.B1 n2210
+CTOF_DEL    ---     0.101     R10C14A.B1 to     R10C14A.F1 SLICE_97
+ROUTE         1     0.211     R10C14A.F1 to      R9C14C.A1 n7_adj_5
+CTOF_DEL    ---     0.101      R9C14C.A1 to      R9C14C.F1 SLICE_88
+ROUTE         1     0.143      R9C14C.F1 to      R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    1.224   (35.6% logic, 64.4% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to    R10C14C.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to     R9C14B.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.277ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        CmdSubmitted_411  (to PHI2_c -)
+
+   Delay:               1.249ns  (34.9% logic, 65.1% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.249ns physical path delay SLICE_19 to SLICE_20 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 1.277ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R9C14B.CLK to      R9C14B.Q0 SLICE_19 (from PHI2_c)
+ROUTE         2     0.224      R9C14B.Q0 to     R10C15A.C0 CmdEnable
+CTOF_DEL    ---     0.101     R10C15A.C0 to     R10C15A.F0 SLICE_73
+ROUTE         2     0.225     R10C15A.F0 to      R9C15B.B0 n2204
+CTOF_DEL    ---     0.101      R9C15B.B0 to      R9C15B.F0 SLICE_74
+ROUTE         2     0.221      R9C15B.F0 to      R9C17A.D1 n2220
+CTOF_DEL    ---     0.101      R9C17A.D1 to      R9C17A.F1 SLICE_89
+ROUTE         1     0.143      R9C17A.F1 to      R9C17D.CE PHI2_N_120_enable_7 (to PHI2_c)
+                  --------
+                    1.249   (34.9% logic, 65.1% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to     R9C14B.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to     R9C17D.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.277ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        Cmdn8MEGEN_410  (to PHI2_c -)
+
+   Delay:               1.249ns  (34.9% logic, 65.1% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.249ns physical path delay SLICE_19 to SLICE_24 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 1.277ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R9C14B.CLK to      R9C14B.Q0 SLICE_19 (from PHI2_c)
+ROUTE         2     0.224      R9C14B.Q0 to     R10C15A.C0 CmdEnable
+CTOF_DEL    ---     0.101     R10C15A.C0 to     R10C15A.F0 SLICE_73
+ROUTE         2     0.225     R10C15A.F0 to      R9C15B.B0 n2204
+CTOF_DEL    ---     0.101      R9C15B.B0 to      R9C15B.F0 SLICE_74
+ROUTE         2     0.221      R9C15B.F0 to      R9C17A.D0 n2220
+CTOF_DEL    ---     0.101      R9C17A.D0 to      R9C17A.F0 SLICE_89
+ROUTE         1     0.143      R9C17A.F0 to      R9C17C.CE PHI2_N_120_enable_6 (to PHI2_c)
+                  --------
+                    1.249   (34.9% logic, 65.1% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to     R9C14B.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to     R9C17C.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 5.431ns (weighted slack = 10.862ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              XOR8MEG_408  (from PHI2_c -)
+   Destination:    FF         Data in        RA11_385  (to PHI2_c +)
+
+   Delay:               0.371ns  (63.1% logic, 36.9% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.371ns physical path delay SLICE_50 to SLICE_33 meets
+     -0.013ns DIN_HLD and
+     -5.047ns delay constraint less
+      0.000ns skew requirement (totaling -5.060ns) by 5.431ns
+
+ Physical Path Details:
+
+      Data path SLICE_50 to SLICE_33:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    R10C15D.CLK to     R10C15D.Q0 SLICE_50 (from PHI2_c)
+ROUTE         1     0.137     R10C15D.Q0 to     R10C16A.C0 XOR8MEG
+CTOF_DEL    ---     0.101     R10C16A.C0 to     R10C16A.F0 SLICE_33
+ROUTE         1     0.000     R10C16A.F0 to    R10C16A.DI0 RA11_N_184 (to PHI2_c)
+                  --------
+                    0.371   (63.1% logic, 36.9% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_50:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to    R10C15D.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_33:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to    R10C16A.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 5.992ns (weighted slack = 11.984ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_412  (to PHI2_c -)
+                   FF                        CmdUFMCLK_413
+
+   Delay:               0.917ns  (47.5% logic, 52.5% route), 4 logic levels.
+
+ Constraint Details:
+
+      0.917ns physical path delay SLICE_93 to SLICE_100 meets
+     -0.028ns CE_HLD and
+     -5.047ns delay constraint less
+      0.000ns skew requirement (totaling -5.075ns) by 5.992ns
+
+ Physical Path Details:
+
+      Data path SLICE_93 to SLICE_100:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R9C16A.CLK to      R9C16A.Q0 SLICE_93 (from PHI2_c)
+ROUTE         1     0.138      R9C16A.Q0 to      R9C15A.C1 Bank_0
+CTOF_DEL    ---     0.101      R9C15A.C1 to      R9C15A.F1 SLICE_100
+ROUTE         1     0.053      R9C15A.F1 to      R9C15B.D1 n2277
+CTOF_DEL    ---     0.101      R9C15B.D1 to      R9C15B.F1 SLICE_74
+ROUTE         8     0.142      R9C15B.F1 to     R10C15A.D1 n26
+CTOF_DEL    ---     0.101     R10C15A.D1 to     R10C15A.F1 SLICE_73
+ROUTE         2     0.148     R10C15A.F1 to      R9C15A.CE PHI2_N_120_enable_8 (to PHI2_c)
+                  --------
+                    0.917   (47.5% logic, 52.5% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to     R9C16A.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_100:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to     R9C15A.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "RCLK_c" 299.401000 MHz ; |     0.000 ns|     0.304 ns|   1  
+                                        |             |             |
+FREQUENCY NET "PHI2_c" 99.079000 MHz ;  |     0.000 ns|     0.379 ns|   2  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
+   Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 335 (setup), 0 (hold)
+Score: 391939 (setup), 0 (hold)
+Cumulative negative slack: 304509 (304509+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_drc.log b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_drc.log new file mode 100644 index 0000000..d48a448 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_drc.log @@ -0,0 +1,16 @@ +Results of NGD DRC are available in RAM2GS_drc.log. +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... + + +Running DRC... + +DRC complete with no errors or warnings + +Design Results: + 309 blocks expanded +completed the first expansion +All blocks are expanded and NGD expansion is successful. +Writing NGD file RAM2GS_LCMXO2_1200HC_impl1.ngd. diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_lse.twr b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_lse.twr new file mode 100644 index 0000000..ccd5368 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_lse.twr @@ -0,0 +1,297 @@ +-------------------------------------------------------------------------------- +Lattice Synthesis Timing Report, Version +Tue Aug 15 05:03:26 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Design: RAM2GS +Constraint file: +Report level: verbose report, limited to 3 items per constraint +-------------------------------------------------------------------------------- + + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c] + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c] + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c] + 122 items scored, 119 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path violates requirements by 7.418ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK Bank_i1 (from PHI2_c +) + Destination: FD1P3AX SP CmdEnable_405 (to PHI2_c -) + + Delay: 9.633ns (30.2% logic, 69.8% route), 6 logic levels. + + Constraint Details: + + 9.633ns data_path Bank_i1 to CmdEnable_405 violates + 2.500ns delay constraint less + 0.285ns LCE_S requirement (totaling 2.215ns) by 7.418ns + + Path Details: Bank_i1 to CmdEnable_405 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.444 CK to Q Bank_i1 (from PHI2_c) +Route 1 e 0.941 Bank[1] +LUT4 --- 0.493 D to Z i8_4_lut +Route 2 e 1.141 n22 +LUT4 --- 0.493 B to Z i11_3_lut_rep_20 +Route 7 e 1.502 n2369 +LUT4 --- 0.493 A to Z i1_2_lut_rep_13_3_lut +Route 1 e 0.941 n2362 +LUT4 --- 0.493 D to Z i1_4_lut_adj_13 +Route 3 e 1.258 C1Submitted_N_237 +LUT4 --- 0.493 C to Z i34_4_lut +Route 1 e 0.941 PHI2_N_120_enable_1 + -------- + 9.633 (30.2% logic, 69.8% route), 6 logic levels. + + +Error: The following path violates requirements by 7.418ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK Bank_i4 (from PHI2_c +) + Destination: FD1P3AX SP CmdEnable_405 (to PHI2_c -) + + Delay: 9.633ns (30.2% logic, 69.8% route), 6 logic levels. + + Constraint Details: + + 9.633ns data_path Bank_i4 to CmdEnable_405 violates + 2.500ns delay constraint less + 0.285ns LCE_S requirement (totaling 2.215ns) by 7.418ns + + Path Details: Bank_i4 to CmdEnable_405 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.444 CK to Q Bank_i4 (from PHI2_c) +Route 1 e 0.941 Bank[4] +LUT4 --- 0.493 C to Z i8_4_lut +Route 2 e 1.141 n22 +LUT4 --- 0.493 B to Z i11_3_lut_rep_20 +Route 7 e 1.502 n2369 +LUT4 --- 0.493 A to Z i1_2_lut_rep_13_3_lut +Route 1 e 0.941 n2362 +LUT4 --- 0.493 D to Z i1_4_lut_adj_13 +Route 3 e 1.258 C1Submitted_N_237 +LUT4 --- 0.493 C to Z i34_4_lut +Route 1 e 0.941 PHI2_N_120_enable_1 + -------- + 9.633 (30.2% logic, 69.8% route), 6 logic levels. + + +Error: The following path violates requirements by 7.256ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK Bank_i3 (from PHI2_c +) + Destination: FD1P3AX SP CmdEnable_405 (to PHI2_c -) + + Delay: 9.471ns (30.7% logic, 69.3% route), 6 logic levels. + + Constraint Details: + + 9.471ns data_path Bank_i3 to CmdEnable_405 violates + 2.500ns delay constraint less + 0.285ns LCE_S requirement (totaling 2.215ns) by 7.256ns + + Path Details: Bank_i3 to CmdEnable_405 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.444 CK to Q Bank_i3 (from PHI2_c) +Route 1 e 0.941 Bank[3] +LUT4 --- 0.493 B to Z i1989_2_lut +Route 1 e 0.941 n2287 +LUT4 --- 0.493 C to Z i12_4_lut +Route 8 e 1.540 n26 +LUT4 --- 0.493 B to Z i1_2_lut_rep_13_3_lut +Route 1 e 0.941 n2362 +LUT4 --- 0.493 D to Z i1_4_lut_adj_13 +Route 3 e 1.258 C1Submitted_N_237 +LUT4 --- 0.493 C to Z i34_4_lut +Route 1 e 0.941 PHI2_N_120_enable_1 + -------- + 9.471 (30.7% logic, 69.3% route), 6 logic levels. + +Warning: 9.918 ns is the maximum delay for this constraint. + + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c] + 498 items scored, 186 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path violates requirements by 3.319ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK FS_610__i13 (from RCLK_c +) + Destination: FD1P3AY D nUFMCS_415 (to RCLK_c +) + + Delay: 8.159ns (29.6% logic, 70.4% route), 5 logic levels. + + Constraint Details: + + 8.159ns data_path FS_610__i13 to nUFMCS_415 violates + 5.000ns delay constraint less + 0.160ns L_S requirement (totaling 4.840ns) by 3.319ns + + Path Details: FS_610__i13 to nUFMCS_415 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.444 CK to Q FS_610__i13 (from RCLK_c) +Route 3 e 1.315 FS[13] +LUT4 --- 0.493 B to Z i3_4_lut_adj_7 +Route 5 e 1.405 n10 +LUT4 --- 0.493 C to Z i1_2_lut_rep_19_3_lut +Route 2 e 1.141 n2368 +LUT4 --- 0.493 B to Z i1_2_lut_4_lut +Route 1 e 0.941 n64 +LUT4 --- 0.493 B to Z i1448_4_lut +Route 1 e 0.941 nUFMCS_N_199 + -------- + 8.159 (29.6% logic, 70.4% route), 5 logic levels. + + +Error: The following path violates requirements by 3.319ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK FS_610__i15 (from RCLK_c +) + Destination: FD1P3AY D nUFMCS_415 (to RCLK_c +) + + Delay: 8.159ns (29.6% logic, 70.4% route), 5 logic levels. + + Constraint Details: + + 8.159ns data_path FS_610__i15 to nUFMCS_415 violates + 5.000ns delay constraint less + 0.160ns L_S requirement (totaling 4.840ns) by 3.319ns + + Path Details: FS_610__i15 to nUFMCS_415 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.444 CK to Q FS_610__i15 (from RCLK_c) +Route 3 e 1.315 FS[15] +LUT4 --- 0.493 C to Z i3_4_lut_adj_7 +Route 5 e 1.405 n10 +LUT4 --- 0.493 C to Z i1_2_lut_rep_19_3_lut +Route 2 e 1.141 n2368 +LUT4 --- 0.493 B to Z i1_2_lut_4_lut +Route 1 e 0.941 n64 +LUT4 --- 0.493 B to Z i1448_4_lut +Route 1 e 0.941 nUFMCS_N_199 + -------- + 8.159 (29.6% logic, 70.4% route), 5 logic levels. + + +Error: The following path violates requirements by 3.319ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK FS_610__i16 (from RCLK_c +) + Destination: FD1P3AY D nUFMCS_415 (to RCLK_c +) + + Delay: 8.159ns (29.6% logic, 70.4% route), 5 logic levels. + + Constraint Details: + + 8.159ns data_path FS_610__i16 to nUFMCS_415 violates + 5.000ns delay constraint less + 0.160ns L_S requirement (totaling 4.840ns) by 3.319ns + + Path Details: FS_610__i16 to nUFMCS_415 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.444 CK to Q FS_610__i16 (from RCLK_c) +Route 3 e 1.315 FS[16] +LUT4 --- 0.493 D to Z i3_4_lut_adj_7 +Route 5 e 1.405 n10 +LUT4 --- 0.493 C to Z i1_2_lut_rep_19_3_lut +Route 2 e 1.141 n2368 +LUT4 --- 0.493 B to Z i1_2_lut_4_lut +Route 1 e 0.941 n64 +LUT4 --- 0.493 B to Z i1448_4_lut +Route 1 e 0.941 nUFMCS_N_199 + -------- + 8.159 (29.6% logic, 70.4% route), 5 logic levels. + +Warning: 8.319 ns is the maximum delay for this constraint. + + +Timing Report Summary +-------------- +-------------------------------------------------------------------------------- +Constraint | Constraint| Actual|Levels +-------------------------------------------------------------------------------- + | | | +create_clock -period 5.000000 -name | | | +clk3 [get_nets nCCAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk2 [get_nets nCRAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk1 [get_nets PHI2_c] | 5.000 ns| 19.836 ns| 6 * + | | | +create_clock -period 5.000000 -name | | | +clk0 [get_nets RCLK_c] | 5.000 ns| 8.319 ns| 5 * + | | | +-------------------------------------------------------------------------------- + + +2 constraints not met. + +-------------------------------------------------------------------------------- +Critical Nets | Loads| Errors| % of total +-------------------------------------------------------------------------------- +n26 | 8| 84| 27.54% + | | | +n1997 | 1| 36| 11.80% + | | | +n1996 | 1| 35| 11.48% + | | | +n1995 | 1| 33| 10.82% + | | | +n10 | 5| 32| 10.49% + | | | +n1998 | 1| 32| 10.49% + | | | +-------------------------------------------------------------------------------- + + +Timing summary: +--------------- + +Timing errors: 305 Score: 1313492 + +Constraints cover 621 paths, 182 nets, and 471 connections (64.2% coverage) + + +Peak memory: 57921536 bytes, TRCE: 2363392 bytes, DLYMAN: 0 bytes +CPU_TIME_REPORT: 0 secs diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_lse_lsetwr.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_lse_lsetwr.html new file mode 100644 index 0000000..8da9b01 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_lse_lsetwr.html @@ -0,0 +1,362 @@ + +Lattice Synthesis Timing Report + + +
    Lattice Synthesis Timing Report
+--------------------------------------------------------------------------------
+Lattice Synthesis Timing Report, Version  
+Tue Aug 15 05:03:26 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design:     RAM2GS
+Constraint file:  
+Report level:    verbose report, limited to 3 items per constraint
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c]
+            122 items scored, 119 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 7.418ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i1  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdEnable_405  (to PHI2_c -)
+
+   Delay:                   9.633ns  (30.2% logic, 69.8% route), 6 logic levels.
+
+ Constraint Details:
+
+      9.633ns data_path Bank_i1 to CmdEnable_405 violates
+      2.500ns delay constraint less
+      0.285ns LCE_S requirement (totaling 2.215ns) by 7.418ns
+
+ Path Details: Bank_i1 to CmdEnable_405
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              Bank_i1 (from PHI2_c)
+Route         1   e 0.941                                  Bank[1]
+LUT4        ---     0.493              D to Z              i8_4_lut
+Route         2   e 1.141                                  n22
+LUT4        ---     0.493              B to Z              i11_3_lut_rep_20
+Route         7   e 1.502                                  n2369
+LUT4        ---     0.493              A to Z              i1_2_lut_rep_13_3_lut
+Route         1   e 0.941                                  n2362
+LUT4        ---     0.493              D to Z              i1_4_lut_adj_13
+Route         3   e 1.258                                  C1Submitted_N_237
+LUT4        ---     0.493              C to Z              i34_4_lut
+Route         1   e 0.941                                  PHI2_N_120_enable_1
+                  --------
+                    9.633  (30.2% logic, 69.8% route), 6 logic levels.
+
+
+Error:  The following path violates requirements by 7.418ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i4  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdEnable_405  (to PHI2_c -)
+
+   Delay:                   9.633ns  (30.2% logic, 69.8% route), 6 logic levels.
+
+ Constraint Details:
+
+      9.633ns data_path Bank_i4 to CmdEnable_405 violates
+      2.500ns delay constraint less
+      0.285ns LCE_S requirement (totaling 2.215ns) by 7.418ns
+
+ Path Details: Bank_i4 to CmdEnable_405
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              Bank_i4 (from PHI2_c)
+Route         1   e 0.941                                  Bank[4]
+LUT4        ---     0.493              C to Z              i8_4_lut
+Route         2   e 1.141                                  n22
+LUT4        ---     0.493              B to Z              i11_3_lut_rep_20
+Route         7   e 1.502                                  n2369
+LUT4        ---     0.493              A to Z              i1_2_lut_rep_13_3_lut
+Route         1   e 0.941                                  n2362
+LUT4        ---     0.493              D to Z              i1_4_lut_adj_13
+Route         3   e 1.258                                  C1Submitted_N_237
+LUT4        ---     0.493              C to Z              i34_4_lut
+Route         1   e 0.941                                  PHI2_N_120_enable_1
+                  --------
+                    9.633  (30.2% logic, 69.8% route), 6 logic levels.
+
+
+Error:  The following path violates requirements by 7.256ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i3  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdEnable_405  (to PHI2_c -)
+
+   Delay:                   9.471ns  (30.7% logic, 69.3% route), 6 logic levels.
+
+ Constraint Details:
+
+      9.471ns data_path Bank_i3 to CmdEnable_405 violates
+      2.500ns delay constraint less
+      0.285ns LCE_S requirement (totaling 2.215ns) by 7.256ns
+
+ Path Details: Bank_i3 to CmdEnable_405
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              Bank_i3 (from PHI2_c)
+Route         1   e 0.941                                  Bank[3]
+LUT4        ---     0.493              B to Z              i1989_2_lut
+Route         1   e 0.941                                  n2287
+LUT4        ---     0.493              C to Z              i12_4_lut
+Route         8   e 1.540                                  n26
+LUT4        ---     0.493              B to Z              i1_2_lut_rep_13_3_lut
+Route         1   e 0.941                                  n2362
+LUT4        ---     0.493              D to Z              i1_4_lut_adj_13
+Route         3   e 1.258                                  C1Submitted_N_237
+LUT4        ---     0.493              C to Z              i34_4_lut
+Route         1   e 0.941                                  PHI2_N_120_enable_1
+                  --------
+                    9.471  (30.7% logic, 69.3% route), 6 logic levels.
+
+Warning: 9.918 ns is the maximum delay for this constraint.
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
+            498 items scored, 186 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 3.319ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_610__i13  (from RCLK_c +)
+   Destination:    FD1P3AY    D              nUFMCS_415  (to RCLK_c +)
+
+   Delay:                   8.159ns  (29.6% logic, 70.4% route), 5 logic levels.
+
+ Constraint Details:
+
+      8.159ns data_path FS_610__i13 to nUFMCS_415 violates
+      5.000ns delay constraint less
+      0.160ns L_S requirement (totaling 4.840ns) by 3.319ns
+
+ Path Details: FS_610__i13 to nUFMCS_415
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              FS_610__i13 (from RCLK_c)
+Route         3   e 1.315                                  FS[13]
+LUT4        ---     0.493              B to Z              i3_4_lut_adj_7
+Route         5   e 1.405                                  n10
+LUT4        ---     0.493              C to Z              i1_2_lut_rep_19_3_lut
+Route         2   e 1.141                                  n2368
+LUT4        ---     0.493              B to Z              i1_2_lut_4_lut
+Route         1   e 0.941                                  n64
+LUT4        ---     0.493              B to Z              i1448_4_lut
+Route         1   e 0.941                                  nUFMCS_N_199
+                  --------
+                    8.159  (29.6% logic, 70.4% route), 5 logic levels.
+
+
+Error:  The following path violates requirements by 3.319ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_610__i15  (from RCLK_c +)
+   Destination:    FD1P3AY    D              nUFMCS_415  (to RCLK_c +)
+
+   Delay:                   8.159ns  (29.6% logic, 70.4% route), 5 logic levels.
+
+ Constraint Details:
+
+      8.159ns data_path FS_610__i15 to nUFMCS_415 violates
+      5.000ns delay constraint less
+      0.160ns L_S requirement (totaling 4.840ns) by 3.319ns
+
+ Path Details: FS_610__i15 to nUFMCS_415
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              FS_610__i15 (from RCLK_c)
+Route         3   e 1.315                                  FS[15]
+LUT4        ---     0.493              C to Z              i3_4_lut_adj_7
+Route         5   e 1.405                                  n10
+LUT4        ---     0.493              C to Z              i1_2_lut_rep_19_3_lut
+Route         2   e 1.141                                  n2368
+LUT4        ---     0.493              B to Z              i1_2_lut_4_lut
+Route         1   e 0.941                                  n64
+LUT4        ---     0.493              B to Z              i1448_4_lut
+Route         1   e 0.941                                  nUFMCS_N_199
+                  --------
+                    8.159  (29.6% logic, 70.4% route), 5 logic levels.
+
+
+Error:  The following path violates requirements by 3.319ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_610__i16  (from RCLK_c +)
+   Destination:    FD1P3AY    D              nUFMCS_415  (to RCLK_c +)
+
+   Delay:                   8.159ns  (29.6% logic, 70.4% route), 5 logic levels.
+
+ Constraint Details:
+
+      8.159ns data_path FS_610__i16 to nUFMCS_415 violates
+      5.000ns delay constraint less
+      0.160ns L_S requirement (totaling 4.840ns) by 3.319ns
+
+ Path Details: FS_610__i16 to nUFMCS_415
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              FS_610__i16 (from RCLK_c)
+Route         3   e 1.315                                  FS[16]
+LUT4        ---     0.493              D to Z              i3_4_lut_adj_7
+Route         5   e 1.405                                  n10
+LUT4        ---     0.493              C to Z              i1_2_lut_rep_19_3_lut
+Route         2   e 1.141                                  n2368
+LUT4        ---     0.493              B to Z              i1_2_lut_4_lut
+Route         1   e 0.941                                  n64
+LUT4        ---     0.493              B to Z              i1448_4_lut
+Route         1   e 0.941                                  nUFMCS_N_199
+                  --------
+                    8.159  (29.6% logic, 70.4% route), 5 logic levels.
+
+Warning: 8.319 ns is the maximum delay for this constraint.
+
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets PHI2_c]                  |     5.000 ns|    19.836 ns|     6 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |     5.000 ns|     8.319 ns|     5 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+--------------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+--------------------------------------------------------------------------------
+n26                                     |       8|      84|     27.54%
+                                        |        |        |
+n1997                                   |       1|      36|     11.80%
+                                        |        |        |
+n1996                                   |       1|      35|     11.48%
+                                        |        |        |
+n1995                                   |       1|      33|     10.82%
+                                        |        |        |
+n10                                     |       5|      32|     10.49%
+                                        |        |        |
+n1998                                   |       1|      32|     10.49%
+                                        |        |        |
+--------------------------------------------------------------------------------
+
+
+Timing summary:
+---------------
+
+Timing errors: 305  Score: 1313492
+
+Constraints cover  621 paths, 182 nets, and 471 connections (64.2% coverage)
+
+
+Peak memory: 57921536 bytes, TRCE: 2363392 bytes, DLYMAN: 0 bytes
+CPU_TIME_REPORT: 0 secs 
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_prim.v b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_prim.v new file mode 100644 index 0000000..28a3dbb --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_prim.v @@ -0,0 +1,802 @@ +// Verilog netlist produced by program LSE : version Diamond (64-bit) 3.12.1.454 +// Netlist written on Tue Aug 15 05:03:26 2023 +// +// Verilog Description of module RAM2GS +// + +module RAM2GS (PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, + LED, RBA, RA, RD, nRCS, RCLK, RCKE, nRWE, nRRAS, + nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI, UFMSDO) /* synthesis syn_module_defined=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1[8:14]) + input PHI2; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) + input [9:0]MAin; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + input [1:0]CROW; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18]) + input [7:0]Din; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + output [7:0]Dout; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + input nCCAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) + input nCRAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + input nFWE; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(36[8:12]) + output LED; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(22[9:12]) + output [1:0]RBA; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22]) + output [11:0]RA; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + inout [7:0]RD; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + output nRCS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[13:17]) + input RCLK; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12]) + output RCKE; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(45[13:17]) + output nRWE; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[45:49]) + output nRRAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[23:28]) + output nRCAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[34:39]) + output RDQMH; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[16:21]) + output RDQML; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[9:14]) + output nUFMCS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(63[13:19]) + output UFMCLK; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(64[13:19]) + output UFMSDI; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(65[13:19]) + input UFMSDO; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(66[8:14]) + + wire PHI2_c /* synthesis is_clock=1, SET_AS_NETWORK=PHI2_c */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) + wire nCCAS_c /* synthesis is_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) + wire nCRAS_c /* synthesis is_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + wire RCLK_c /* synthesis SET_AS_NETWORK=RCLK_c, is_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12]) + wire nCCAS_N_3 /* synthesis is_inv_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + wire PHI2_N_120 /* synthesis is_inv_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(38[6:13]) + wire nCRAS_c__inv /* synthesis is_inv_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + + wire GND_net, VCC_net, PHI2r, PHI2r2, PHI2r3, RASr, RASr2, + RASr3, CASr, CASr2, CASr3, FWEr, CBR, LEDEN, LED_c, + Din_c_7, Din_c_6, Din_c_5, Din_c_4, Din_c_3, Din_c_2, Din_c_1, + Din_c_0; + wire [7:0]Bank; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(31[12:16]) + + wire CROW_c_1, CROW_c_0, MAin_c_9, MAin_c_8, MAin_c_7, MAin_c_6, + MAin_c_5, MAin_c_4, MAin_c_3, MAin_c_2, MAin_c_1, MAin_c_0, + nFWE_c, n8MEGEN, XOR8MEG, RCKEEN, RCKE_c, nRCS_c, nRRAS_c, + nRCAS_c, nRWE_c, RBA_c_1, RBA_c_0, nRowColSel, RA_c, RA_0; + wire [9:0]RowA; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(51[12:16]) + + wire RA_1_9, RA_1_8, RA_1_7, RA_1_6, RA_1_5, RA_1_4, RA_1_3, + RA_1_2, RA_1_1, RA_1_0, RDQML_c, RDQMH_c; + wire [7:0]WRD; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(59[12:15]) + + wire nUFMCS_c, UFMCLK_c, UFMSDI_c, UFMSDO_c, C1Submitted, ADSubmitted, + CmdEnable, CmdSubmitted, Cmdn8MEGEN, CmdUFMCLK, CmdUFMSDI, + CmdUFMCS, InitReady, Ready, n10; + wire [17:0]FS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(86[13:15]) + + wire RA11_N_184, PHI2_N_120_enable_8, n2036, n1765, n1893, n7, + n917, n4, n2277, RCKE_N_132, nRowColSel_N_35, nRWE_N_182, + nRowColSel_N_34, nRowColSel_N_33, nRowColSel_N_32, nRCS_N_146, + n15, n2260, nRCS_N_142, n2362, nRCS_N_141, nRCAS_N_166, + nRWE_N_178, n2180, nRCS_N_139, nRCAS_N_165, nRWE_N_177, nRWE_N_176, + n14, n6, n13, n1993, n2254, Ready_N_296, RCLK_c_enable_28, + nRCS_N_137, Ready_N_292, nRCS_N_136, nRRAS_N_156, nRCAS_N_161, + nRWE_N_171, n2220, RCKEEN_N_121, n15_adj_1, n2371, ADSubmitted_N_246, + CmdEnable_N_248, C1Submitted_N_237, PHI2_N_120_enable_3, n2174, + n6_adj_2, Cmdn8MEGEN_N_264, XOR8MEG_N_110, n2204, n1996, n6_adj_3, + RCLK_c_enable_10, n2191, n2208, n22, n8MEGEN_N_91, UFMCLK_N_224, + UFMSDI_N_231, n26, nUFMCS_N_199, n2055, PHI2_N_120_enable_2, + n1999, n2287, n726, n727, n728, n729, n730, n732, n733, + n734, n735, n736, n737, n738, n2267, n1398, n2183, n1995, + PHI2_N_120_enable_1, n1060, n1408, n2228, n2447, n1406, + PHI2_N_120_enable_6, n2225, n827, n2370, n1277, n15_adj_4, + Dout_c, n78, n79, n80, n81, n82, n83, n84, n85, n86, + n87, n88, n89, n90, n91, n92, n93, n94, n95, n2382, + RCLK_c_enable_15, n9, n2369, n7_adj_5, n13_adj_6, n2381, + n2210, n2380, n2227, n2368, PHI2_N_120_enable_7, n12, n1994, + RCLK_c_enable_27, n2367, n1407, n2379, n2378, n2377, n2366, + n2365, n2376, n1998, n2375, n4_adj_7, n2374, RCLK_c_enable_6, + Dout_0, Dout_1, n984, Dout_2, n8, Dout_3, Dout_4, n1314, + Dout_5, Dout_6, RCLK_c_enable_16, n2363, n13_adj_8, n2000, + n2373, RCLK_c_enable_5, n1992, n1997, n2372, n64; + + VHI i2 (.Z(VCC_net)); + INV i2046 (.A(PHI2_c), .Z(PHI2_N_120)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) + FD1S3AX PHI2r2_377 (.D(PHI2r), .CK(RCLK_c), .Q(PHI2r2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam PHI2r2_377.GSR = "ENABLED"; + LUT4 nRCAS_I_43_4_lut (.A(nRCS_N_142), .B(RASr2), .C(nRowColSel_N_35), + .D(CBR), .Z(nRCAS_N_166)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B ((D)+!C)+!B !(C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(186[13] 231[7]) + defparam nRCAS_I_43_4_lut.init = 16'h3afa; + LUT4 nRCAS_I_0_452_3_lut_4_lut (.A(n2371), .B(nRCAS_N_165), .C(Ready), + .D(nRCAS_N_166), .Z(nRCAS_N_161)) /* synthesis lut_function=(A ((D)+!C)+!A (B ((D)+!C)+!B (C (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6]) + defparam nRCAS_I_0_452_3_lut_4_lut.init = 16'hfe0e; + LUT4 nRWE_I_0_455_4_lut (.A(n1765), .B(nRWE_N_178), .C(Ready), .D(n2371), + .Z(nRWE_N_171)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B+!(C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6]) + defparam nRWE_I_0_455_4_lut.init = 16'hcfc5; + FD1S3AX PHI2r3_378 (.D(PHI2r2), .CK(RCLK_c), .Q(PHI2r3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam PHI2r3_378.GSR = "ENABLED"; + FD1S3AX RASr_379 (.D(nCRAS_c__inv), .CK(RCLK_c), .Q(RASr)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam RASr_379.GSR = "ENABLED"; + FD1S3AX RASr2_380 (.D(RASr), .CK(RCLK_c), .Q(RASr2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam RASr2_380.GSR = "ENABLED"; + FD1S3AX RASr3_381 (.D(RASr2), .CK(RCLK_c), .Q(RASr3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam RASr3_381.GSR = "ENABLED"; + FD1S3AX CASr_382 (.D(nCCAS_N_3), .CK(RCLK_c), .Q(CASr)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam CASr_382.GSR = "ENABLED"; + FD1S3AX CASr2_383 (.D(CASr), .CK(RCLK_c), .Q(CASr2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam CASr2_383.GSR = "ENABLED"; + FD1S3AX CASr3_384 (.D(CASr2), .CK(RCLK_c), .Q(CASr3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam CASr3_384.GSR = "ENABLED"; + FD1S3IX RA11_385 (.D(RA11_N_184), .CK(PHI2_c), .CD(n2380), .Q(RA_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam RA11_385.GSR = "ENABLED"; + CCU2D FS_610_add_4_15 (.A0(FS[13]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[14]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1998), + .COUT(n1999), .S0(n82), .S1(n81)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_15.INIT0 = 16'hfaaa; + defparam FS_610_add_4_15.INIT1 = 16'hfaaa; + defparam FS_610_add_4_15.INJECT1_0 = "NO"; + defparam FS_610_add_4_15.INJECT1_1 = "NO"; + FD1S3IX RowA_i0 (.D(MAin_c_0), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i0.GSR = "ENABLED"; + FD1S3AX WRD_i0 (.D(Din_c_0), .CK(nCCAS_N_3), .Q(WRD[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i0.GSR = "ENABLED"; + FD1S3AX FWEr_389 (.D(n2373), .CK(nCRAS_c__inv), .Q(FWEr)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam FWEr_389.GSR = "ENABLED"; + FD1S3AX CBR_390 (.D(nCCAS_N_3), .CK(nCRAS_c__inv), .Q(CBR)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam CBR_390.GSR = "ENABLED"; + FD1S3AX RCKE_395 (.D(RCKE_N_132), .CK(RCLK_c), .Q(RCKE_c)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(141[9] 144[5]) + defparam RCKE_395.GSR = "ENABLED"; + FD1P3AY nRCS_396 (.D(nRCS_N_136), .SP(RCLK_c_enable_6), .CK(RCLK_c), + .Q(nRCS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRCS_396.GSR = "ENABLED"; + LUT4 i1477_2_lut (.A(nRWE_N_177), .B(nRCAS_N_165), .Z(n1765)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1477_2_lut.init = 16'heeee; + FD1P3AX nRowColSel_402 (.D(n917), .SP(RCLK_c_enable_5), .CK(RCLK_c), + .Q(nRowColSel)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRowColSel_402.GSR = "ENABLED"; + CCU2D FS_610_add_4_13 (.A0(FS[11]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[12]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1997), + .COUT(n1998), .S0(n84), .S1(n83)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_13.INIT0 = 16'hfaaa; + defparam FS_610_add_4_13.INIT1 = 16'hfaaa; + defparam FS_610_add_4_13.INJECT1_0 = "NO"; + defparam FS_610_add_4_13.INJECT1_1 = "NO"; + LUT4 i2_2_lut (.A(InitReady), .B(Ready_N_296), .Z(n6_adj_3)) /* synthesis lut_function=(A (B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam i2_2_lut.init = 16'h8888; + FD1P3AX CmdEnable_405 (.D(CmdEnable_N_248), .SP(PHI2_N_120_enable_1), + .CK(PHI2_N_120), .Q(CmdEnable)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdEnable_405.GSR = "ENABLED"; + LUT4 i4_4_lut (.A(MAin_c_1), .B(MAin_c_0), .C(CmdEnable), .D(n6_adj_2), + .Z(n2204)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ; + defparam i4_4_lut.init = 16'h4000; + FD1P3IX ADSubmitted_407 (.D(ADSubmitted_N_246), .SP(PHI2_N_120_enable_2), + .CD(C1Submitted_N_237), .CK(PHI2_N_120), .Q(ADSubmitted)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam ADSubmitted_407.GSR = "ENABLED"; + LUT4 i26_4_lut (.A(n2183), .B(n2191), .C(Din_c_5), .D(n2254), .Z(n15_adj_1)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B (C))) */ ; + defparam i26_4_lut.init = 16'hc0ca; + LUT4 i1_2_lut_3_lut_4_lut (.A(n2369), .B(n26), .C(n2204), .D(nFWE_c), + .Z(n2220)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ; + defparam i1_2_lut_3_lut_4_lut.init = 16'h0020; + FD1P3AY nRRAS_397 (.D(nRRAS_N_156), .SP(RCLK_c_enable_6), .CK(RCLK_c), + .Q(nRRAS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRRAS_397.GSR = "ENABLED"; + LUT4 nRWE_I_50_1_lut (.A(nRWE_N_177), .Z(nRWE_N_176)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(255[14] 262[8]) + defparam nRWE_I_50_1_lut.init = 16'h5555; + BB Dout_pad_7__713 (.I(WRD[7]), .T(n984), .B(RD[7]), .O(Dout_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + FD1P3AY nRCAS_398 (.D(nRCAS_N_161), .SP(RCLK_c_enable_6), .CK(RCLK_c), + .Q(nRCAS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRCAS_398.GSR = "ENABLED"; + FD1P3AY nRWE_399 (.D(nRWE_N_171), .SP(RCLK_c_enable_5), .CK(RCLK_c), + .Q(nRWE_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRWE_399.GSR = "ENABLED"; + FD1S3JX RA10_400 (.D(n2036), .CK(RCLK_c), .PD(nRWE_N_176), .Q(RA_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam RA10_400.GSR = "ENABLED"; + FD1P3AX RCKEEN_401 (.D(RCKEEN_N_121), .SP(RCLK_c_enable_6), .CK(RCLK_c), + .Q(RCKEEN)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam RCKEEN_401.GSR = "ENABLED"; + FD1S3AX FS_610__i0 (.D(n95), .CK(RCLK_c), .Q(FS[0])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i0.GSR = "ENABLED"; + FD1S3IX RBA__i1 (.D(CROW_c_0), .CK(nCRAS_c__inv), .CD(n2380), .Q(RBA_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RBA__i1.GSR = "ENABLED"; + LUT4 i1_4_lut (.A(Din_c_5), .B(n2220), .C(Din_c_4), .D(Din_c_3), + .Z(PHI2_N_120_enable_6)) /* synthesis lut_function=(A (B (C (D)))+!A (B)) */ ; + defparam i1_4_lut.init = 16'hc444; + LUT4 i29_3_lut (.A(InitReady), .B(n15_adj_4), .C(Ready), .Z(RCKEEN_N_121)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6]) + defparam i29_3_lut.init = 16'hcaca; + LUT4 Cmdn8MEGEN_I_93_4_lut (.A(Din_c_0), .B(n8MEGEN), .C(Din_c_4), + .D(n1314), .Z(Cmdn8MEGEN_N_264)) /* synthesis lut_function=(A (B ((D)+!C))+!A (B+!((D)+!C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(321[13] 335[7]) + defparam Cmdn8MEGEN_I_93_4_lut.init = 16'hcc5c; + LUT4 i1956_2_lut (.A(MAin_c_0), .B(Din_c_2), .Z(n2254)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1956_2_lut.init = 16'heeee; + FD1P3AX IS_FSM__i0 (.D(Ready_N_296), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(nRCS_N_139)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i0.GSR = "ENABLED"; + CCU2D FS_610_add_4_9 (.A0(FS[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1995), + .COUT(n1996), .S0(n88), .S1(n87)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_9.INIT0 = 16'hfaaa; + defparam FS_610_add_4_9.INIT1 = 16'hfaaa; + defparam FS_610_add_4_9.INJECT1_0 = "NO"; + defparam FS_610_add_4_9.INJECT1_1 = "NO"; + FD1S3JX C1Submitted_406 (.D(n1398), .CK(PHI2_N_120), .PD(C1Submitted_N_237), + .Q(C1Submitted)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam C1Submitted_406.GSR = "ENABLED"; + FD1P3AY nUFMCS_415 (.D(nUFMCS_N_199), .SP(RCLK_c_enable_10), .CK(RCLK_c), + .Q(nUFMCS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam nUFMCS_415.GSR = "ENABLED"; + LUT4 i2_4_lut (.A(n2220), .B(Din_c_4), .C(Din_c_3), .D(Din_c_5), + .Z(PHI2_N_120_enable_7)) /* synthesis lut_function=(A (B (C+!(D)))) */ ; + defparam i2_4_lut.init = 16'h8088; + FD1S3AX S_FSM_i1 (.D(n2374), .CK(RCLK_c), .Q(nRowColSel_N_35)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam S_FSM_i1.GSR = "ENABLED"; + CCU2D FS_610_add_4_7 (.A0(FS[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1994), + .COUT(n1995), .S0(n90), .S1(n89)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_7.INIT0 = 16'hfaaa; + defparam FS_610_add_4_7.INIT1 = 16'hfaaa; + defparam FS_610_add_4_7.INJECT1_0 = "NO"; + defparam FS_610_add_4_7.INJECT1_1 = "NO"; + LUT4 i1_2_lut (.A(Din_c_6), .B(Din_c_3), .Z(n2183)) /* synthesis lut_function=(!((B)+!A)) */ ; + defparam i1_2_lut.init = 16'h2222; + LUT4 i1_2_lut_rep_15_4_lut (.A(FS[10]), .B(FS[11]), .C(n2368), .D(InitReady), + .Z(RCLK_c_enable_16)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ; + defparam i1_2_lut_rep_15_4_lut.init = 16'h0008; + CCU2D FS_610_add_4_3 (.A0(FS[1]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1992), + .COUT(n1993), .S0(n94), .S1(n93)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_3.INIT0 = 16'hfaaa; + defparam FS_610_add_4_3.INIT1 = 16'hfaaa; + defparam FS_610_add_4_3.INJECT1_0 = "NO"; + defparam FS_610_add_4_3.INJECT1_1 = "NO"; + LUT4 RA11_I_54_3_lut (.A(Din_c_6), .B(XOR8MEG), .C(n8MEGEN), .Z(RA11_N_184)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A (B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(99[22:51]) + defparam RA11_I_54_3_lut.init = 16'hc6c6; + LUT4 i9_2_lut_3_lut (.A(FWEr), .B(CBR), .C(RASr2), .Z(n9)) /* synthesis lut_function=(!(A (C)+!A (B (C)))) */ ; + defparam i9_2_lut_3_lut.init = 16'h1f1f; + LUT4 i1491_2_lut_rep_30 (.A(RCKE_c), .B(RASr2), .Z(n2379)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1491_2_lut_rep_30.init = 16'heeee; + LUT4 nRCS_I_31_3_lut_4_lut (.A(RCKE_c), .B(RASr2), .C(nRowColSel_N_35), + .D(nRCS_N_142), .Z(nRCS_N_141)) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C+(D))))) */ ; + defparam nRCS_I_31_3_lut_4_lut.init = 16'h1f10; + FD1P3IX UFMCLK_416 (.D(UFMCLK_N_224), .SP(RCLK_c_enable_10), .CD(n2366), + .CK(RCLK_c), .Q(UFMCLK_c)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam UFMCLK_416.GSR = "ENABLED"; + LUT4 MAin_9__I_0_427_i10_3_lut (.A(RowA[9]), .B(MAin_c_9), .C(nRowColSel), + .Z(RA_1_9)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i10_3_lut.init = 16'hcaca; + LUT4 i3_4_lut (.A(Din_c_2), .B(Din_c_3), .C(Din_c_6), .D(MAin_c_0), + .Z(n2191)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ; + defparam i3_4_lut.init = 16'h0800; + LUT4 i1_2_lut_rep_21_3_lut (.A(Din_c_7), .B(Din_c_1), .C(Din_c_0), + .Z(n2370)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) + defparam i1_2_lut_rep_21_3_lut.init = 16'h2020; + LUT4 MAin_9__I_0_427_i9_3_lut (.A(RowA[8]), .B(MAin_c_8), .C(nRowColSel), + .Z(RA_1_8)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i9_3_lut.init = 16'hcaca; + LUT4 MAin_9__I_0_427_i8_3_lut (.A(RowA[7]), .B(MAin_c_7), .C(nRowColSel), + .Z(RA_1_7)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i8_3_lut.init = 16'hcaca; + LUT4 MAin_9__I_0_427_i7_3_lut (.A(RowA[6]), .B(MAin_c_6), .C(nRowColSel), + .Z(RA_1_6)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i7_3_lut.init = 16'hcaca; + LUT4 MAin_9__I_0_427_i6_3_lut (.A(RowA[5]), .B(MAin_c_5), .C(nRowColSel), + .Z(RA_1_5)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i6_3_lut.init = 16'hcaca; + CCU2D FS_610_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .COUT(n1992), + .S1(n95)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_1.INIT0 = 16'hF000; + defparam FS_610_add_4_1.INIT1 = 16'h0555; + defparam FS_610_add_4_1.INJECT1_0 = "NO"; + defparam FS_610_add_4_1.INJECT1_1 = "NO"; + LUT4 MAin_9__I_0_427_i5_3_lut (.A(RowA[4]), .B(MAin_c_4), .C(nRowColSel), + .Z(RA_1_4)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i5_3_lut.init = 16'hcaca; + FD1S3AX PHI2r_376 (.D(PHI2_c), .CK(RCLK_c), .Q(PHI2r)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam PHI2r_376.GSR = "ENABLED"; + LUT4 i1962_4_lut (.A(Din_c_4), .B(Din_c_1), .C(n1314), .D(LEDEN), + .Z(n2260)) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ; + defparam i1962_4_lut.init = 16'hfefa; + LUT4 i1423_2_lut (.A(RCKE_c), .B(RASr2), .Z(nRWE_N_182)) /* synthesis lut_function=((B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(168[14] 184[8]) + defparam i1423_2_lut.init = 16'hdddd; + LUT4 MAin_9__I_0_427_i4_3_lut (.A(RowA[3]), .B(MAin_c_3), .C(nRowColSel), + .Z(RA_1_3)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i4_3_lut.init = 16'hcaca; + FD1S3IX S_FSM_i3 (.D(n1406), .CK(RCLK_c), .CD(n1407), .Q(nRowColSel_N_33)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam S_FSM_i3.GSR = "ENABLED"; + FD1S3IX S_FSM_i4 (.D(n827), .CK(RCLK_c), .CD(n2374), .Q(nRowColSel_N_32)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam S_FSM_i4.GSR = "ENABLED"; + LUT4 i1_2_lut_3_lut_4_lut_adj_1 (.A(Din_c_7), .B(Din_c_1), .C(Din_c_4), + .D(Din_c_0), .Z(n2208)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) + defparam i1_2_lut_3_lut_4_lut_adj_1.init = 16'h0200; + LUT4 MAin_c_0_bdd_4_lut (.A(n2369), .B(n26), .C(nFWE_c), .D(MAin_c_1), + .Z(PHI2_N_120_enable_2)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ; + defparam MAin_c_0_bdd_4_lut.init = 16'h0200; + FD1P3IX UFMSDI_417 (.D(UFMSDI_N_231), .SP(RCLK_c_enable_10), .CD(n2366), + .CK(RCLK_c), .Q(UFMSDI_c)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam UFMSDI_417.GSR = "ENABLED"; + LUT4 MAin_9__I_0_427_i3_3_lut (.A(RowA[2]), .B(MAin_c_2), .C(nRowColSel), + .Z(RA_1_2)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i3_3_lut.init = 16'hcaca; + LUT4 MAin_9__I_0_427_i2_3_lut (.A(RowA[1]), .B(MAin_c_1), .C(nRowColSel), + .Z(RA_1_1)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i2_3_lut.init = 16'hcaca; + LUT4 i1448_4_lut (.A(n13_adj_6), .B(n64), .C(CmdUFMCS), .D(InitReady), + .Z(nUFMCS_N_199)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B (C+!(D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(345[12] 409[6]) + defparam i1448_4_lut.init = 16'h3fbb; + LUT4 i2_3_lut_rep_18_4_lut (.A(n10), .B(n2375), .C(FS[11]), .D(FS[10]), + .Z(n2367)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ; + defparam i2_3_lut_rep_18_4_lut.init = 16'h1000; + LUT4 i3_4_lut_adj_2 (.A(nRCS_N_139), .B(InitReady), .C(nRowColSel_N_35), + .D(RASr2), .Z(nRCS_N_137)) /* synthesis lut_function=(A+!(B (C (D)))) */ ; + defparam i3_4_lut_adj_2.init = 16'hbfff; + LUT4 MAin_9__I_0_427_i1_3_lut (.A(RowA[0]), .B(MAin_c_0), .C(nRowColSel), + .Z(RA_1_0)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i1_3_lut.init = 16'hcaca; + LUT4 i1416_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQMH_c)) /* synthesis lut_function=(A+!(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(58[17:46]) + defparam i1416_2_lut.init = 16'hbbbb; + LUT4 i2001_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQML_c)) /* synthesis lut_function=(!(A (B))) */ ; + defparam i2001_2_lut.init = 16'h7777; + LUT4 i2_3_lut_4_lut (.A(n2363), .B(MAin_c_1), .C(n2208), .D(n15_adj_1), + .Z(CmdEnable_N_248)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ; + defparam i2_3_lut_4_lut.init = 16'h4000; + LUT4 i2005_3_lut_rep_17_4_lut (.A(n10), .B(n2375), .C(InitReady), + .D(FS[11]), .Z(n2366)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ; + defparam i2005_3_lut_rep_17_4_lut.init = 16'h0001; + FD1S3AX Bank_i0 (.D(Din_c_0), .CK(PHI2_c), .Q(Bank[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i0.GSR = "ENABLED"; + LUT4 i1427_4_lut (.A(nRCS_N_146), .B(nRowColSel_N_34), .C(n2378), + .D(nRowColSel_N_33), .Z(nRCS_N_142)) /* synthesis lut_function=(A (B+(C (D)))+!A (B+(C+!(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(195[13] 231[7]) + defparam i1427_4_lut.init = 16'hfcdd; + LUT4 i3_3_lut_4_lut (.A(Din_c_7), .B(Din_c_1), .C(Din_c_6), .D(Din_c_4), + .Z(n8)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) + defparam i3_3_lut_4_lut.init = 16'h0002; + LUT4 i1_2_lut_adj_3 (.A(FS[10]), .B(n13_adj_6), .Z(RCLK_c_enable_28)) /* synthesis lut_function=(A (B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i1_2_lut_adj_3.init = 16'h8888; + LUT4 i1119_1_lut (.A(nRowColSel_N_35), .Z(n1408)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i1119_1_lut.init = 16'h5555; + LUT4 nRCS_N_146_bdd_4_lut (.A(nRCS_N_146), .B(n1060), .C(nRWE_N_182), + .D(nRowColSel_N_35), .Z(nRWE_N_178)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))+!A (C+!(D))) */ ; + defparam nRCS_N_146_bdd_4_lut.init = 16'hf0dd; + LUT4 i11_3_lut_rep_20 (.A(MAin_c_2), .B(n22), .C(MAin_c_5), .Z(n2369)) /* synthesis lut_function=(A (B (C))) */ ; + defparam i11_3_lut_rep_20.init = 16'h8080; + LUT4 i13_2_lut_rep_16_4_lut (.A(MAin_c_2), .B(n22), .C(MAin_c_5), + .D(n26), .Z(n2365)) /* synthesis lut_function=((((D)+!C)+!B)+!A) */ ; + defparam i13_2_lut_rep_16_4_lut.init = 16'hff7f; + GSR GSR_INST (.GSR(VCC_net)); + LUT4 i1_4_lut_adj_4 (.A(n2180), .B(n2225), .C(n8), .D(n2382), .Z(ADSubmitted_N_246)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) + defparam i1_4_lut_adj_4.init = 16'h2000; + LUT4 i6_4_lut (.A(FS[11]), .B(n12), .C(FS[14]), .D(FS[17]), .Z(n13_adj_6)) /* synthesis lut_function=(A (B (C (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i6_4_lut.init = 16'h8000; + LUT4 i8_4_lut (.A(MAin_c_7), .B(MAin_c_3), .C(Bank[4]), .D(Bank[1]), + .Z(n22)) /* synthesis lut_function=(A (B (C (D)))) */ ; + defparam i8_4_lut.init = 16'h8000; + LUT4 i1_2_lut_3_lut_4_lut_adj_5 (.A(n2369), .B(n26), .C(MAin_c_0), + .D(MAin_c_1), .Z(n2225)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ; + defparam i1_2_lut_3_lut_4_lut_adj_5.init = 16'hdfff; + LUT4 i5_4_lut (.A(FS[13]), .B(FS[12]), .C(FS[15]), .D(FS[16]), .Z(n12)) /* synthesis lut_function=(A (B (C (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i5_4_lut.init = 16'h8000; + LUT4 i12_4_lut (.A(Bank[2]), .B(n2277), .C(n2287), .D(Bank[5]), + .Z(n26)) /* synthesis lut_function=(A+!(B (C (D)))) */ ; + defparam i12_4_lut.init = 16'hbfff; + LUT4 i2_3_lut_4_lut_adj_6 (.A(n2369), .B(n26), .C(MAin_c_0), .D(MAin_c_1), + .Z(n1277)) /* synthesis lut_function=((B+((D)+!C))+!A) */ ; + defparam i2_3_lut_4_lut_adj_6.init = 16'hffdf; + LUT4 i637_1_lut_rep_31 (.A(Ready), .Z(n2380)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i637_1_lut_rep_31.init = 16'h5555; + LUT4 i1573_4_lut (.A(n2367), .B(n2377), .C(InitReady), .D(n4_adj_7), + .Z(RCLK_c_enable_15)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(83[6:15]) + defparam i1573_4_lut.init = 16'hcac0; + LUT4 i3_4_lut_adj_7 (.A(FS[17]), .B(FS[13]), .C(FS[15]), .D(FS[16]), + .Z(n10)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i3_4_lut_adj_7.init = 16'hfffe; + LUT4 i786_2_lut (.A(nRowColSel_N_33), .B(nRowColSel_N_34), .Z(n1060)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(195[13] 231[7]) + defparam i786_2_lut.init = 16'heeee; + LUT4 i1_4_lut_adj_8 (.A(FS[4]), .B(n15), .C(n13), .D(n14), .Z(n4_adj_7)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ; + defparam i1_4_lut_adj_8.init = 16'h0002; + LUT4 i2_2_lut_3_lut_4_lut (.A(nRCS_N_139), .B(n2381), .C(Ready), .D(nRCAS_N_165), + .Z(n2036)) /* synthesis lut_function=(A+((C+(D))+!B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam i2_2_lut_3_lut_4_lut.init = 16'hfffb; + LUT4 i2_3_lut_4_lut_4_lut (.A(Ready), .B(n1060), .C(nRowColSel_N_32), + .D(nRowColSel_N_35), .Z(RCLK_c_enable_5)) /* synthesis lut_function=((B+(C+(D)))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i2_3_lut_4_lut_4_lut.init = 16'hfffd; + CCU2D FS_610_add_4_11 (.A0(FS[9]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[10]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1996), + .COUT(n1997), .S0(n86), .S1(n85)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_11.INIT0 = 16'hfaaa; + defparam FS_610_add_4_11.INIT1 = 16'hfaaa; + defparam FS_610_add_4_11.INJECT1_0 = "NO"; + defparam FS_610_add_4_11.INJECT1_1 = "NO"; + LUT4 i1603_3_lut (.A(n1893), .B(CmdUFMCLK), .C(InitReady), .Z(UFMCLK_N_224)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(83[6:15]) + defparam i1603_3_lut.init = 16'hcaca; + LUT4 i1979_4_lut (.A(MAin_c_6), .B(MAin_c_4), .C(Bank[7]), .D(Bank[0]), + .Z(n2277)) /* synthesis lut_function=(A (B (C (D)))) */ ; + defparam i1979_4_lut.init = 16'h8000; + FD1P3AX IS_FSM__i15 (.D(n726), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(Ready_N_296)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i15.GSR = "ENABLED"; + LUT4 i771_2_lut_rep_23_2_lut (.A(Ready), .B(nRowColSel_N_35), .Z(n2372)) /* synthesis lut_function=((B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i771_2_lut_rep_23_2_lut.init = 16'hdddd; + LUT4 i6_4_lut_adj_9 (.A(FS[5]), .B(FS[7]), .C(FS[1]), .D(FS[2]), + .Z(n15)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; + defparam i6_4_lut_adj_9.init = 16'hfffe; + LUT4 i1970_4_lut (.A(FS[4]), .B(n13_adj_6), .C(n2267), .D(FS[1]), + .Z(n1893)) /* synthesis lut_function=(!(A (B (C)+!B !((D)+!C))+!A (B+!(C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(86[13:15]) + defparam i1970_4_lut.init = 16'h3a0a; + LUT4 i1_2_lut_2_lut (.A(Ready), .B(nRowColSel_N_34), .Z(n6)) /* synthesis lut_function=((B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i1_2_lut_2_lut.init = 16'hdddd; + PFUMX i30 (.BLUT(n13_adj_8), .ALUT(n9), .C0(nRowColSel_N_35), .Z(n15_adj_4)); + FD1P3AX IS_FSM__i14 (.D(n727), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n726)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i14.GSR = "ENABLED"; + FD1P3AX IS_FSM__i13 (.D(n728), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n727)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i13.GSR = "ENABLED"; + LUT4 i1989_2_lut (.A(Bank[6]), .B(Bank[3]), .Z(n2287)) /* synthesis lut_function=(A (B)) */ ; + defparam i1989_2_lut.init = 16'h8888; + LUT4 i2_3_lut_rep_32 (.A(RASr2), .B(InitReady), .C(nRowColSel_N_35), + .Z(n2381)) /* synthesis lut_function=(A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(233[8:20]) + defparam i2_3_lut_rep_32.init = 16'h8080; + LUT4 i1_2_lut_rep_22_4_lut (.A(RASr2), .B(InitReady), .C(nRowColSel_N_35), + .D(nRCS_N_139), .Z(n2371)) /* synthesis lut_function=((((D)+!C)+!B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(233[8:20]) + defparam i1_2_lut_rep_22_4_lut.init = 16'hff7f; + FD1P3AX IS_FSM__i12 (.D(n729), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n728)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i12.GSR = "ENABLED"; + FD1P3AX XOR8MEG_408 (.D(XOR8MEG_N_110), .SP(PHI2_N_120_enable_3), .CK(PHI2_N_120), + .Q(XOR8MEG)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam XOR8MEG_408.GSR = "ENABLED"; + FD1P3AX n8MEGEN_418 (.D(n8MEGEN_N_91), .SP(RCLK_c_enable_15), .CK(RCLK_c), + .Q(n8MEGEN)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam n8MEGEN_418.GSR = "ENABLED"; + CCU2D FS_610_add_4_19 (.A0(FS[17]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2000), + .S0(n78)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_19.INIT0 = 16'hfaaa; + defparam FS_610_add_4_19.INIT1 = 16'h0000; + defparam FS_610_add_4_19.INJECT1_0 = "NO"; + defparam FS_610_add_4_19.INJECT1_1 = "NO"; + FD1P3AX LEDEN_419 (.D(n2447), .SP(RCLK_c_enable_16), .CK(RCLK_c), + .Q(LEDEN)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam LEDEN_419.GSR = "ENABLED"; + FD1P3AX Ready_404 (.D(n2447), .SP(Ready_N_292), .CK(RCLK_c), .Q(Ready)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam Ready_404.GSR = "ENABLED"; + FD1P3AX CmdUFMCLK_413 (.D(Din_c_1), .SP(PHI2_N_120_enable_8), .CK(PHI2_N_120), + .Q(CmdUFMCLK)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdUFMCLK_413.GSR = "ENABLED"; + FD1P3AX CmdUFMSDI_414 (.D(Din_c_0), .SP(PHI2_N_120_enable_8), .CK(PHI2_N_120), + .Q(CmdUFMSDI)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdUFMSDI_414.GSR = "ENABLED"; + FD1P3AX Cmdn8MEGEN_410 (.D(Cmdn8MEGEN_N_264), .SP(PHI2_N_120_enable_6), + .CK(PHI2_N_120), .Q(Cmdn8MEGEN)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam Cmdn8MEGEN_410.GSR = "ENABLED"; + FD1P3AX CmdSubmitted_411 (.D(n2447), .SP(PHI2_N_120_enable_7), .CK(PHI2_N_120), + .Q(CmdSubmitted)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdSubmitted_411.GSR = "ENABLED"; + FD1P3AX CmdUFMCS_412 (.D(Din_c_2), .SP(PHI2_N_120_enable_8), .CK(PHI2_N_120), + .Q(CmdUFMCS)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdUFMCS_412.GSR = "ENABLED"; + FD1P3AX IS_FSM__i11 (.D(n730), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n729)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i11.GSR = "ENABLED"; + LUT4 i2008_2_lut_4_lut (.A(RASr2), .B(InitReady), .C(nRowColSel_N_35), + .D(Ready), .Z(RCLK_c_enable_27)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(233[8:20]) + defparam i2008_2_lut_4_lut.init = 16'h0080; + LUT4 i1404_4_lut (.A(RASr), .B(RCKEEN), .C(RASr2), .D(RASr3), .Z(RCKE_N_132)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B (C+(D))+!B !(C+!(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(15[12:17]) + defparam i1404_4_lut.init = 16'hcfc8; + LUT4 i1118_1_lut (.A(nRowColSel_N_34), .Z(n1407)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i1118_1_lut.init = 16'h5555; + FD1P3AX IS_FSM__i10 (.D(nRWE_N_177), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n730)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i10.GSR = "ENABLED"; + LUT4 i1_2_lut_adj_10 (.A(RASr2), .B(nRowColSel_N_32), .Z(n1406)) /* synthesis lut_function=(!((B)+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam i1_2_lut_adj_10.init = 16'h2222; + LUT4 i1439_2_lut (.A(nRowColSel_N_33), .B(nRowColSel_N_32), .Z(n827)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i1439_2_lut.init = 16'heeee; + FD1P3AX IS_FSM__i9 (.D(n732), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(nRWE_N_177)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i9.GSR = "ENABLED"; + LUT4 i1432_4_lut (.A(FWEr), .B(n2372), .C(n1060), .D(n2376), .Z(n917)) /* synthesis lut_function=(!(A (B+!(C+!(D)))+!A (B+!(C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i1432_4_lut.init = 16'h3032; + LUT4 i1_2_lut_rep_33 (.A(Din_c_0), .B(Din_c_2), .Z(n2382)) /* synthesis lut_function=(A (B)) */ ; + defparam i1_2_lut_rep_33.init = 16'h8888; + LUT4 i1_4_lut_4_lut (.A(CBR), .B(n2227), .C(FWEr), .D(nRowColSel_N_34), + .Z(n13_adj_8)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(23[27:31]) + defparam i1_4_lut_4_lut.init = 16'h5540; + LUT4 i4_2_lut (.A(FS[8]), .B(FS[0]), .Z(n13)) /* synthesis lut_function=(A+(B)) */ ; + defparam i4_2_lut.init = 16'heeee; + LUT4 i1589_4_lut (.A(n2174), .B(CmdUFMSDI), .C(InitReady), .D(n4), + .Z(UFMSDI_N_231)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(83[6:15]) + defparam i1589_4_lut.init = 16'hcac0; + LUT4 i2_1_lut_rep_24 (.A(nFWE_c), .Z(n2373)) /* synthesis lut_function=(!(A)) */ ; + defparam i2_1_lut_rep_24.init = 16'h5555; + LUT4 i2_3_lut_4_lut_adj_11 (.A(Din_c_0), .B(Din_c_2), .C(n2260), .D(Din_c_3), + .Z(XOR8MEG_N_110)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ; + defparam i2_3_lut_4_lut_adj_11.init = 16'h0008; + FD1P3AX IS_FSM__i8 (.D(n733), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n732)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i8.GSR = "ENABLED"; + FD1P3AX IS_FSM__i7 (.D(n734), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n733)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i7.GSR = "ENABLED"; + FD1P3AX IS_FSM__i6 (.D(n735), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n734)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i6.GSR = "ENABLED"; + FD1P3AX IS_FSM__i5 (.D(n736), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n735)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i5.GSR = "ENABLED"; + FD1P3AX IS_FSM__i4 (.D(n737), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n736)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i4.GSR = "ENABLED"; + FD1P3AX IS_FSM__i3 (.D(n738), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n737)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i3.GSR = "ENABLED"; + FD1P3AX IS_FSM__i2 (.D(nRCAS_N_165), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n738)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i2.GSR = "ENABLED"; + FD1P3AX IS_FSM__i1 (.D(nRCS_N_139), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(nRCAS_N_165)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i1.GSR = "ENABLED"; + FD1S3IX RBA__i2 (.D(CROW_c_1), .CK(nCRAS_c__inv), .CD(n2380), .Q(RBA_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RBA__i2.GSR = "ENABLED"; + FD1S3AX FS_610__i17 (.D(n78), .CK(RCLK_c), .Q(FS[17])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i17.GSR = "ENABLED"; + FD1S3AX FS_610__i16 (.D(n79), .CK(RCLK_c), .Q(FS[16])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i16.GSR = "ENABLED"; + FD1S3AX FS_610__i15 (.D(n80), .CK(RCLK_c), .Q(FS[15])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i15.GSR = "ENABLED"; + FD1S3AX FS_610__i14 (.D(n81), .CK(RCLK_c), .Q(FS[14])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i14.GSR = "ENABLED"; + FD1S3AX FS_610__i13 (.D(n82), .CK(RCLK_c), .Q(FS[13])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i13.GSR = "ENABLED"; + FD1S3AX FS_610__i12 (.D(n83), .CK(RCLK_c), .Q(FS[12])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i12.GSR = "ENABLED"; + FD1S3AX FS_610__i11 (.D(n84), .CK(RCLK_c), .Q(FS[11])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i11.GSR = "ENABLED"; + FD1S3AX FS_610__i10 (.D(n85), .CK(RCLK_c), .Q(FS[10])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i10.GSR = "ENABLED"; + FD1S3AX FS_610__i9 (.D(n86), .CK(RCLK_c), .Q(FS[9])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i9.GSR = "ENABLED"; + FD1S3AX FS_610__i8 (.D(n87), .CK(RCLK_c), .Q(FS[8])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i8.GSR = "ENABLED"; + FD1S3AX FS_610__i7 (.D(n88), .CK(RCLK_c), .Q(FS[7])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i7.GSR = "ENABLED"; + FD1S3AX FS_610__i6 (.D(n89), .CK(RCLK_c), .Q(FS[6])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i6.GSR = "ENABLED"; + FD1S3AX FS_610__i5 (.D(n90), .CK(RCLK_c), .Q(FS[5])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i5.GSR = "ENABLED"; + FD1S3AX FS_610__i4 (.D(n91), .CK(RCLK_c), .Q(FS[4])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i4.GSR = "ENABLED"; + FD1S3AX FS_610__i3 (.D(n92), .CK(RCLK_c), .Q(FS[3])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i3.GSR = "ENABLED"; + FD1S3AX FS_610__i2 (.D(n93), .CK(RCLK_c), .Q(FS[2])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i2.GSR = "ENABLED"; + FD1S3AX FS_610__i1 (.D(n94), .CK(RCLK_c), .Q(FS[1])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i1.GSR = "ENABLED"; + FD1S3AX WRD_i7 (.D(Din_c_7), .CK(nCCAS_N_3), .Q(WRD[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i7.GSR = "ENABLED"; + FD1S3AX WRD_i6 (.D(Din_c_6), .CK(nCCAS_N_3), .Q(WRD[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i6.GSR = "ENABLED"; + FD1S3AX WRD_i5 (.D(Din_c_5), .CK(nCCAS_N_3), .Q(WRD[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i5.GSR = "ENABLED"; + FD1S3AX WRD_i4 (.D(Din_c_4), .CK(nCCAS_N_3), .Q(WRD[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i4.GSR = "ENABLED"; + FD1S3AX WRD_i3 (.D(Din_c_3), .CK(nCCAS_N_3), .Q(WRD[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i3.GSR = "ENABLED"; + FD1S3AX WRD_i2 (.D(Din_c_2), .CK(nCCAS_N_3), .Q(WRD[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i2.GSR = "ENABLED"; + FD1S3AX WRD_i1 (.D(Din_c_1), .CK(nCCAS_N_3), .Q(WRD[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i1.GSR = "ENABLED"; + FD1S3JX RowA_i9 (.D(MAin_c_9), .CK(nCRAS_c__inv), .PD(n2380), .Q(RowA[9])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i9.GSR = "ENABLED"; + FD1S3IX RowA_i8 (.D(MAin_c_8), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[8])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i8.GSR = "ENABLED"; + FD1S3IX RowA_i7 (.D(MAin_c_7), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i7.GSR = "ENABLED"; + FD1S3IX RowA_i6 (.D(MAin_c_6), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i6.GSR = "ENABLED"; + FD1S3JX RowA_i5 (.D(MAin_c_5), .CK(nCRAS_c__inv), .PD(n2380), .Q(RowA[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i5.GSR = "ENABLED"; + FD1S3IX RowA_i4 (.D(MAin_c_4), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i4.GSR = "ENABLED"; + FD1S3IX RowA_i3 (.D(MAin_c_3), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i3.GSR = "ENABLED"; + FD1S3IX RowA_i2 (.D(MAin_c_2), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i2.GSR = "ENABLED"; + FD1S3IX RowA_i1 (.D(MAin_c_1), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i1.GSR = "ENABLED"; + FD1S3AX Bank_i7 (.D(Din_c_7), .CK(PHI2_c), .Q(Bank[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i7.GSR = "ENABLED"; + LUT4 i2_3_lut_3_lut (.A(nFWE_c), .B(Din_c_5), .C(Din_c_3), .Z(n2180)) /* synthesis lut_function=(!(A+!(B (C)))) */ ; + defparam i2_3_lut_3_lut.init = 16'h4040; + LUT4 i1_2_lut_3_lut (.A(Din_c_6), .B(Din_c_7), .C(Din_c_4), .Z(n6_adj_2)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(315[17:31]) + defparam i1_2_lut_3_lut.init = 16'h1010; + LUT4 RASr2_I_0_1_lut_rep_25 (.A(RASr2), .Z(n2374)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(143[40:46]) + defparam RASr2_I_0_1_lut_rep_25.init = 16'h5555; + LUT4 i1_4_lut_4_lut_adj_12 (.A(RASr2), .B(n6_adj_3), .C(nRowColSel_N_32), + .D(Ready), .Z(Ready_N_292)) /* synthesis lut_function=(A (D)+!A (B (C+(D))+!B (D))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(143[40:46]) + defparam i1_4_lut_4_lut_adj_12.init = 16'hff40; + LUT4 i1_4_lut_adj_13 (.A(Din_c_2), .B(n2055), .C(MAin_c_0), .D(n2362), + .Z(C1Submitted_N_237)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ; + defparam i1_4_lut_adj_13.init = 16'h0004; + FD1S3AX Bank_i6 (.D(Din_c_6), .CK(PHI2_c), .Q(Bank[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i6.GSR = "ENABLED"; + FD1S3AX Bank_i5 (.D(Din_c_5), .CK(PHI2_c), .Q(Bank[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i5.GSR = "ENABLED"; + FD1S3AX Bank_i4 (.D(Din_c_4), .CK(PHI2_c), .Q(Bank[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i4.GSR = "ENABLED"; + FD1S3AX Bank_i3 (.D(Din_c_3), .CK(PHI2_c), .Q(Bank[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i3.GSR = "ENABLED"; + FD1S3AX Bank_i2 (.D(Din_c_2), .CK(PHI2_c), .Q(Bank[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i2.GSR = "ENABLED"; + FD1S3AX Bank_i1 (.D(Din_c_1), .CK(PHI2_c), .Q(Bank[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i1.GSR = "ENABLED"; + CCU2D FS_610_add_4_5 (.A0(FS[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1993), + .COUT(n1994), .S0(n92), .S1(n91)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_5.INIT0 = 16'hfaaa; + defparam FS_610_add_4_5.INIT1 = 16'hfaaa; + defparam FS_610_add_4_5.INJECT1_0 = "NO"; + defparam FS_610_add_4_5.INJECT1_1 = "NO"; + BB Dout_pad_6__714 (.I(WRD[6]), .T(n984), .B(RD[6]), .O(Dout_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + LUT4 i2_3_lut_4_lut_adj_14 (.A(n2369), .B(n26), .C(n2180), .D(n2204), + .Z(PHI2_N_120_enable_8)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ; + defparam i2_3_lut_4_lut_adj_14.init = 16'h2000; + BB Dout_pad_5__715 (.I(WRD[5]), .T(n984), .B(RD[5]), .O(Dout_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + BB Dout_pad_4__716 (.I(WRD[4]), .T(n984), .B(RD[4]), .O(Dout_2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + BB Dout_pad_3__717 (.I(WRD[3]), .T(n984), .B(RD[3]), .O(Dout_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + BB Dout_pad_2__718 (.I(WRD[2]), .T(n984), .B(RD[2]), .O(Dout_4)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + LUT4 i1_2_lut_3_lut_adj_15 (.A(Din_c_6), .B(Din_c_7), .C(Din_c_5), + .Z(n1314)) /* synthesis lut_function=(A+(B+(C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(315[17:31]) + defparam i1_2_lut_3_lut_adj_15.init = 16'hfefe; + BB Dout_pad_1__719 (.I(WRD[1]), .T(n984), .B(RD[1]), .O(Dout_5)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + BB Dout_pad_0__720 (.I(WRD[0]), .T(n984), .B(RD[0]), .O(Dout_6)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + OB Dout_pad_7 (.I(Dout_c), .O(Dout[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_6 (.I(Dout_0), .O(Dout[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_5 (.I(Dout_1), .O(Dout[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_4 (.I(Dout_2), .O(Dout[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_3 (.I(Dout_3), .O(Dout[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_2 (.I(Dout_4), .O(Dout[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_1 (.I(Dout_5), .O(Dout[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_0 (.I(Dout_6), .O(Dout[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB LED_pad (.I(LED_c), .O(LED)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(22[9:12]) + OB RBA_pad_1 (.I(RBA_c_1), .O(RBA[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22]) + OB RBA_pad_0 (.I(RBA_c_0), .O(RBA[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22]) + OB RA_pad_11 (.I(RA_c), .O(RA[11])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_10 (.I(RA_0), .O(RA[10])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_9 (.I(RA_1_9), .O(RA[9])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_8 (.I(RA_1_8), .O(RA[8])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_7 (.I(RA_1_7), .O(RA[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_6 (.I(RA_1_6), .O(RA[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_5 (.I(RA_1_5), .O(RA[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_4 (.I(RA_1_4), .O(RA[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_3 (.I(RA_1_3), .O(RA[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_2 (.I(RA_1_2), .O(RA[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_1 (.I(RA_1_1), .O(RA[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_0 (.I(RA_1_0), .O(RA[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB nRCS_pad (.I(nRCS_c), .O(nRCS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[13:17]) + OB RCKE_pad (.I(RCKE_c), .O(RCKE)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(45[13:17]) + OB nRWE_pad (.I(nRWE_c), .O(nRWE)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[45:49]) + OB nRRAS_pad (.I(nRRAS_c), .O(nRRAS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[23:28]) + OB nRCAS_pad (.I(nRCAS_c), .O(nRCAS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[34:39]) + OB RDQMH_pad (.I(RDQMH_c), .O(RDQMH)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[16:21]) + OB RDQML_pad (.I(RDQML_c), .O(RDQML)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[9:14]) + OB nUFMCS_pad (.I(nUFMCS_c), .O(nUFMCS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(63[13:19]) + OB UFMCLK_pad (.I(UFMCLK_c), .O(UFMCLK)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(64[13:19]) + OB UFMSDI_pad (.I(UFMSDI_c), .O(UFMSDI)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(65[13:19]) + IB PHI2_pad (.I(PHI2), .O(PHI2_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) + IB MAin_pad_9 (.I(MAin[9]), .O(MAin_c_9)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_8 (.I(MAin[8]), .O(MAin_c_8)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_7 (.I(MAin[7]), .O(MAin_c_7)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_6 (.I(MAin[6]), .O(MAin_c_6)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_5 (.I(MAin[5]), .O(MAin_c_5)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_4 (.I(MAin[4]), .O(MAin_c_4)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_3 (.I(MAin[3]), .O(MAin_c_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_2 (.I(MAin[2]), .O(MAin_c_2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_1 (.I(MAin[1]), .O(MAin_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_0 (.I(MAin[0]), .O(MAin_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB CROW_pad_1 (.I(CROW[1]), .O(CROW_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18]) + IB CROW_pad_0 (.I(CROW[0]), .O(CROW_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18]) + IB Din_pad_7 (.I(Din[7]), .O(Din_c_7)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_6 (.I(Din[6]), .O(Din_c_6)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_5 (.I(Din[5]), .O(Din_c_5)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_4 (.I(Din[4]), .O(Din_c_4)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_3 (.I(Din[3]), .O(Din_c_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_2 (.I(Din[2]), .O(Din_c_2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_1 (.I(Din[1]), .O(Din_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_0 (.I(Din[0]), .O(Din_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB nCCAS_pad (.I(nCCAS), .O(nCCAS_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) + IB nCRAS_pad (.I(nCRAS), .O(nCRAS_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + IB nFWE_pad (.I(nFWE), .O(nFWE_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(36[8:12]) + IB RCLK_pad (.I(RCLK), .O(RCLK_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12]) + IB UFMSDO_pad (.I(UFMSDO), .O(UFMSDO_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(66[8:14]) + CCU2D FS_610_add_4_17 (.A0(FS[15]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[16]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1999), + .COUT(n2000), .S0(n80), .S1(n79)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_17.INIT0 = 16'hfaaa; + defparam FS_610_add_4_17.INIT1 = 16'hfaaa; + defparam FS_610_add_4_17.INJECT1_0 = "NO"; + defparam FS_610_add_4_17.INJECT1_1 = "NO"; + LUT4 i1_2_lut_rep_14_3_lut (.A(n2369), .B(n26), .C(nFWE_c), .Z(n2363)) /* synthesis lut_function=((B+(C))+!A) */ ; + defparam i1_2_lut_rep_14_3_lut.init = 16'hfdfd; + LUT4 i1_2_lut_rep_13_3_lut (.A(n2369), .B(n26), .C(MAin_c_1), .Z(n2362)) /* synthesis lut_function=((B+!(C))+!A) */ ; + defparam i1_2_lut_rep_13_3_lut.init = 16'hdfdf; + LUT4 i2010_3_lut_3_lut (.A(nCRAS_c), .B(LEDEN), .C(CBR), .Z(LED_c)) /* synthesis lut_function=(A+((C)+!B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(23[17:23]) + defparam i2010_3_lut_3_lut.init = 16'hfbfb; + LUT4 i5_3_lut (.A(FS[3]), .B(FS[9]), .C(FS[6]), .Z(n14)) /* synthesis lut_function=(A+(B+(C))) */ ; + defparam i5_3_lut.init = 16'hfefe; + LUT4 i4_4_lut_adj_16 (.A(nRowColSel_N_35), .B(nRowColSel_N_33), .C(nRowColSel_N_32), + .D(n6), .Z(RCLK_c_enable_6)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; + defparam i4_4_lut_adj_16.init = 16'hfffe; + LUT4 i4_4_lut_adj_17 (.A(n7), .B(FS[8]), .C(FS[10]), .D(n10), .Z(n2174)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i4_4_lut_adj_17.init = 16'h0002; + LUT4 i34_4_lut (.A(n7_adj_5), .B(ADSubmitted), .C(C1Submitted_N_237), + .D(n2363), .Z(PHI2_N_120_enable_1)) /* synthesis lut_function=(A (B (C))+!A (B (C+!(D))+!B !(C+(D)))) */ ; + defparam i34_4_lut.init = 16'hc0c5; + LUT4 i13_3_lut (.A(MAin_c_0), .B(n2210), .C(MAin_c_1), .Z(n7_adj_5)) /* synthesis lut_function=(A (B (C))+!A (B+!(C))) */ ; + defparam i13_3_lut.init = 16'hc5c5; + LUT4 i1_2_lut_4_lut (.A(FS[11]), .B(n2368), .C(InitReady), .D(FS[10]), + .Z(n64)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; + defparam i1_2_lut_4_lut.init = 16'hfffe; + LUT4 nRCS_N_137_I_0_4_lut (.A(nRCS_N_137), .B(n2379), .C(Ready), .D(nRowColSel_N_35), + .Z(nRRAS_N_156)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B ((D)+!C)+!B !(C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6]) + defparam nRCS_N_137_I_0_4_lut.init = 16'h3afa; + LUT4 i3_4_lut_adj_18 (.A(Din_c_5), .B(n2228), .C(n2183), .D(n2370), + .Z(n2055)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) + defparam i3_4_lut_adj_18.init = 16'h1000; + LUT4 i1930_2_lut (.A(nFWE_c), .B(Din_c_4), .Z(n2228)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1930_2_lut.init = 16'heeee; + LUT4 i1110_2_lut_3_lut_4_lut (.A(nFWE_c), .B(n2365), .C(C1Submitted), + .D(MAin_c_1), .Z(n1398)) /* synthesis lut_function=(A (C)+!A (B (C)+!B !((D)+!C))) */ ; + defparam i1110_2_lut_3_lut_4_lut.init = 16'he0f0; + LUT4 i1_2_lut_adj_19 (.A(FS[11]), .B(FS[6]), .Z(n4)) /* synthesis lut_function=(A (B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i1_2_lut_adj_19.init = 16'h8888; + LUT4 i2_4_lut_adj_20 (.A(n2375), .B(FS[7]), .C(FS[9]), .D(FS[5]), + .Z(n7)) /* synthesis lut_function=(!(A+(B (C)+!B !(C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i2_4_lut_adj_20.init = 16'h1404; + LUT4 i1417_2_lut (.A(nCCAS_c), .B(nFWE_c), .Z(n984)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1417_2_lut.init = 16'heeee; + LUT4 i2_4_lut_adj_21 (.A(n2228), .B(CmdEnable), .C(n1277), .D(n1314), + .Z(PHI2_N_120_enable_3)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ; + defparam i2_4_lut_adj_21.init = 16'h0004; + LUT4 i3_4_lut_adj_22 (.A(Din_c_5), .B(n2191), .C(C1Submitted), .D(n2208), + .Z(n2210)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ; + defparam i3_4_lut_adj_22.init = 16'h0800; + LUT4 i1_2_lut_adj_23 (.A(nRowColSel_N_33), .B(CASr2), .Z(n2227)) /* synthesis lut_function=(A+!(B)) */ ; + defparam i1_2_lut_adj_23.init = 16'hbbbb; + FD1P3AX InitReady_394 (.D(n2447), .SP(RCLK_c_enable_28), .CK(RCLK_c), + .Q(InitReady)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(134[9] 138[5]) + defparam InitReady_394.GSR = "ENABLED"; + LUT4 nRCS_I_0_448_3_lut (.A(nRCS_N_137), .B(nRCS_N_141), .C(Ready), + .Z(nRCS_N_136)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6]) + defparam nRCS_I_0_448_3_lut.init = 16'hcaca; + LUT4 i1969_2_lut_3_lut_4_lut (.A(FS[12]), .B(FS[14]), .C(FS[11]), + .D(n10), .Z(n2267)) /* synthesis lut_function=(A+(B+((D)+!C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i1969_2_lut_3_lut_4_lut.init = 16'hffef; + LUT4 i1_2_lut_rep_19_3_lut (.A(FS[12]), .B(FS[14]), .C(n10), .Z(n2368)) /* synthesis lut_function=(A+(B+(C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i1_2_lut_rep_19_3_lut.init = 16'hfefe; + LUT4 i2_3_lut_4_lut_adj_24 (.A(CBR), .B(CASr3), .C(FWEr), .D(CASr2), + .Z(nRCS_N_146)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam i2_3_lut_4_lut_adj_24.init = 16'h1000; + LUT4 i3_2_lut_rep_26 (.A(FS[12]), .B(FS[14]), .Z(n2375)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i3_2_lut_rep_26.init = 16'heeee; + LUT4 i1_2_lut_rep_27 (.A(CBR), .B(CASr3), .Z(n2376)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam i1_2_lut_rep_27.init = 16'heeee; + LUT4 i2_3_lut_rep_28 (.A(PHI2r3), .B(PHI2r2), .C(CmdSubmitted), .Z(n2377)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(402[16:47]) + defparam i2_3_lut_rep_28.init = 16'h2020; + INV i2044 (.A(nCRAS_c), .Z(nCRAS_c__inv)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + FD1S3IX S_FSM_i2 (.D(n1406), .CK(RCLK_c), .CD(n1408), .Q(nRowColSel_N_34)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam S_FSM_i2.GSR = "ENABLED"; + INV i2045 (.A(nCCAS_c), .Z(nCCAS_N_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) + VLO i1 (.Z(GND_net)); + TSALL TSALL_INST (.TSALL(GND_net)); + PUR PUR_INST (.PUR(VCC_net)); + defparam PUR_INST.RST_PULSE = 1; + LUT4 i1_2_lut_4_lut_adj_25 (.A(PHI2r3), .B(PHI2r2), .C(CmdSubmitted), + .D(InitReady), .Z(RCLK_c_enable_10)) /* synthesis lut_function=(!(A (B (D)+!B !(C+!(D)))+!A (D))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(402[16:47]) + defparam i1_2_lut_4_lut_adj_25.init = 16'h20ff; + LUT4 i1_2_lut_rep_29 (.A(FWEr), .B(CBR), .Z(n2378)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1_2_lut_rep_29.init = 16'heeee; + LUT4 m1_lut (.Z(n2447)) /* synthesis lut_function=1, syn_instantiated=1 */ ; + defparam m1_lut.init = 16'hffff; + LUT4 n8MEGEN_I_14_3_lut_4_lut (.A(InitReady), .B(n2367), .C(UFMSDO_c), + .D(Cmdn8MEGEN), .Z(n8MEGEN_N_91)) /* synthesis lut_function=(A (D)+!A !(B (C)+!B !(D))) */ ; + defparam n8MEGEN_I_14_3_lut_4_lut.init = 16'hbf04; + +endmodule +// +// Verilog Description of module TSALL +// module not written out since it is a black-box. +// + +// +// Verilog Description of module PUR +// module not written out since it is a black-box. +// + diff --git a/CPLD/LCMXO2-1200HC/impl1/automake.log b/CPLD/LCMXO2-1200HC/impl1/automake.log new file mode 100644 index 0000000..bdf40a5 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/automake.log @@ -0,0 +1,1111 @@ + +synthesis -f "RAM2GS_LCMXO2_1200HC_impl1_lattice.synproj" +synthesis: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:25 2023 + + +Command Line: synthesis -f RAM2GS_LCMXO2_1200HC_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml + + +Synthesis options: +The -a option is MachXO2. +The -s option is 4. +The -t option is TQFP100. +The -d option is LCMXO2-1200HC. +Using package TQFP100. +Using performance grade 4. + + +########################################################## + +### Lattice Family : MachXO2 + +### Device : LCMXO2-1200HC + +### Package : TQFP100 + +### Speed : 4 + +########################################################## + + + + +Optimization goal = Balanced +Top-level module name = RAM2GS. +Target frequency = 200.000000 MHz. +Maximum fanout = 1000. +Timing path count = 3 +BRAM utilization = 100.000000 % +DSP usage = true +DSP utilization = 100.000000 % +fsm_encoding_style = auto +resolve_mixed_drivers = 0 +fix_gated_clocks = 1 + +Mux style = Auto +Use Carry Chain = true +carry_chain_length = 0 +Loop Limit = 1950. +Use IO Insertion = TRUE +Use IO Reg = AUTO + +Resource Sharing = TRUE +Propagate Constants = TRUE +Remove Duplicate Registers = TRUE +force_gsr = auto +ROM style = auto +RAM style = auto +The -comp option is FALSE. +The -syn option is FALSE. +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC (searchpath added) +-p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added) +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1 (searchpath added) +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC (searchpath added) +Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v +NGD file = RAM2GS_LCMXO2_1200HC_impl1.ngd +-sdc option: SDC file input not used. +-lpf option: Output file option is ON. +Hardtimer checking is enabled (default). The -dt option is not used. +The -r option is OFF. [ Remove LOC Properties is OFF. ] +Technology check ok... + +Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 +Compile design. +Compile Design Begin +Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482 +Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 +Top module name (Verilog): RAM2GS + + + + +Last elaborated design is RAM2GS() +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... +Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.44. +Top-level module name = RAM2GS. + +original encoding -> new encoding (one-hot encoding) + + 0000 -> 0000000000000001 + + 0001 -> 0000000000000010 + + 0010 -> 0000000000000100 + + 0011 -> 0000000000001000 + + 0100 -> 0000000000010000 + + 0101 -> 0000000000100000 + + 0110 -> 0000000001000000 + + 0111 -> 0000000010000000 + + 1000 -> 0000000100000000 + + 1001 -> 0000001000000000 + + 1010 -> 0000010000000000 + + 1011 -> 0000100000000000 + + 1100 -> 0001000000000000 + + 1101 -> 0010000000000000 + + 1110 -> 0100000000000000 + + 1111 -> 1000000000000000 + + +original encoding -> new encoding (one-hot encoding) + + 00 -> 0001 + + 01 -> 0010 + + 10 -> 0100 + + 11 -> 1000 + + + + +GSR will not be inferred because no asynchronous signal was found in the netlist. + +Applying 200.000000 MHz constraint to all clocks + + +Results of NGD DRC are available in RAM2GS_drc.log. +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... + + +Running DRC... + +DRC complete with no errors or warnings + +Design Results: + 309 blocks expanded +completed the first expansion +All blocks are expanded and NGD expansion is successful. +Writing NGD file RAM2GS_LCMXO2_1200HC_impl1.ngd. + +################### Begin Area Report (RAM2GS)###################### +Number of register bits => 102 of 1520 (6 % ) +BB => 8 +CCU2D => 10 +FD1P3AX => 29 +FD1P3AY => 5 +FD1P3IX => 3 +FD1S3AX => 47 +FD1S3IX => 14 +FD1S3JX => 4 +GSR => 1 +IB => 26 +INV => 3 +LUT4 => 122 +OB => 33 +PFUMX => 1 +################### End Area Report ################## + +################### Begin BlackBox Report ###################### +TSALL => 1 +################### End BlackBox Report ################## + +################### Begin Clock Report ###################### +Clock Nets +Number of Clocks: 4 + Net : RCLK_c, loads : 62 + Net : PHI2_c, loads : 11 + Net : nCCAS_c, loads : 2 + Net : nCRAS_c, loads : 2 +Clock Enable Nets +Number of Clock Enables: 14 +Top 10 highest fanout Clock Enables: + Net : RCLK_c_enable_27, loads : 16 + Net : RCLK_c_enable_6, loads : 4 + Net : PHI2_N_120_enable_8, loads : 3 + Net : RCLK_c_enable_10, loads : 3 + Net : RCLK_c_enable_5, loads : 2 + Net : PHI2_N_120_enable_3, loads : 1 + Net : Ready_N_292, loads : 1 + Net : PHI2_N_120_enable_2, loads : 1 + Net : RCLK_c_enable_15, loads : 1 + Net : PHI2_N_120_enable_6, loads : 1 +Highest fanout non-clock nets +Top 10 highest fanout non-clock nets: + Net : RCLK_c_enable_27, loads : 16 + Net : InitReady, loads : 15 + Net : nCRAS_c__inv, loads : 15 + Net : RASr2, loads : 14 + Net : nRowColSel_N_35, loads : 13 + Net : n2380, loads : 13 + Net : nRowColSel, loads : 12 + Net : Ready, loads : 12 + Net : Din_c_4, loads : 10 + Net : MAin_c_1, loads : 10 +################### End Clock Report ################## + +Timing Report Summary +-------------- +-------------------------------------------------------------------------------- +Constraint | Constraint| Actual|Levels +-------------------------------------------------------------------------------- + | | | +create_clock -period 5.000000 -name | | | +clk3 [get_nets nCCAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk2 [get_nets nCRAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk1 [get_nets PHI2_c] | 200.000 MHz| 50.413 MHz| 6 * + | | | +create_clock -period 5.000000 -name | | | +clk0 [get_nets RCLK_c] | 200.000 MHz| 120.207 MHz| 5 * + | | | +-------------------------------------------------------------------------------- + + +2 constraints not met. + + +Peak Memory Usage: 55.238 MB + +-------------------------------------------------------------- +Elapsed CPU time for LSE flow : 0.891 secs +-------------------------------------------------------------- + +map -a "MachXO2" -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial "RAM2GS_LCMXO2_1200HC_impl1.ngd" -o "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" -pr "RAM2GS_LCMXO2_1200HC_impl1.prf" -mp "RAM2GS_LCMXO2_1200HC_impl1.mrp" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.lpf" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.lpf" -c 0 +map: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + Process the file: RAM2GS_LCMXO2_1200HC_impl1.ngd + Picdevice="LCMXO2-1200HC" + + Pictype="TQFP100" + + Picspeed=4 + + Remove unused logic + + Do not produce over sized NCDs. + +Part used: LCMXO2-1200HCTQFP100, Performance used: 4. + +Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.44. + +Running general design DRC... + +Removing unused logic... + +Optimizing... + + + + +Design Summary: + Number of registers: 102 out of 1520 (7%) + PFU registers: 102 out of 1280 (8%) + PIO registers: 0 out of 240 (0%) + Number of SLICEs: 75 out of 640 (12%) + SLICEs as Logic/ROM: 75 out of 640 (12%) + SLICEs as RAM: 0 out of 480 (0%) + SLICEs as Carry: 10 out of 640 (2%) + Number of LUT4s: 143 out of 1280 (11%) + Number used as logic LUTs: 123 + Number used as distributed RAM: 0 + Number used as ripple logic: 20 + Number used as shift registers: 0 + Number of PIO sites used: 67 + 4(JTAG) out of 80 (89%) + Number of block RAMs: 0 out of 7 (0%) + Number of GSRs: 0 out of 1 (0%) + EFB used : No + JTAG used : No + Readback used : No + Oscillator used : No + Startup used : No + POR : On + Bandgap : On + Number of Power Controller: 0 out of 1 (0%) + Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) + Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%) + Number of DCCA: 0 out of 8 (0%) + Number of DCMA: 0 out of 2 (0%) + Number of PLLs: 0 out of 1 (0%) + Number of DQSDLLs: 0 out of 2 (0%) + Number of CLKDIVC: 0 out of 4 (0%) + Number of ECLKSYNCA: 0 out of 4 (0%) + Number of ECLKBRIDGECS: 0 out of 2 (0%) + Notes:- + 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) + 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. + Number of clocks: 4 + Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK ) + Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 ) + Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) + Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS ) + Number of Clock Enables: 14 + Net RCLK_c_enable_6: 4 loads, 4 LSLICEs + Net RCLK_c_enable_5: 2 loads, 2 LSLICEs + Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_2: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_6: 1 loads, 1 LSLICEs + Net RCLK_c_enable_27: 8 loads, 8 LSLICEs + Net RCLK_c_enable_10: 3 loads, 3 LSLICEs + Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs + Net RCLK_c_enable_16: 1 loads, 1 LSLICEs + Net RCLK_c_enable_28: 1 loads, 1 LSLICEs + Net RCLK_c_enable_15: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_3: 1 loads, 1 LSLICEs + Net Ready_N_292: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_8: 2 loads, 2 LSLICEs + Number of LSRs: 7 + Net RASr2: 1 loads, 1 LSLICEs + Net nRowColSel_N_35: 1 loads, 1 LSLICEs + Net Ready: 7 loads, 7 LSLICEs + Net nRWE_N_177: 1 loads, 1 LSLICEs + Net C1Submitted_N_237: 2 loads, 2 LSLICEs + Net n2366: 2 loads, 2 LSLICEs + Net nRowColSel_N_34: 1 loads, 1 LSLICEs + Number of nets driven by tri-state buffers: 0 + Top 10 highest fanout non-clock nets: + Net Ready: 18 loads + Net InitReady: 15 loads + Net RASr2: 15 loads + Net nRowColSel_N_35: 13 loads + Net nRowColSel: 12 loads + Net Din_c_4: 10 loads + Net MAin_c_1: 10 loads + Net Din_c_5: 9 loads + Net MAin_c_0: 9 loads + Net Din_c_0: 8 loads + + + Number of warnings: 0 + Number of errors: 0 + + + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 41 MB + +Dumping design to file RAM2GS_LCMXO2_1200HC_impl1_map.ncd. + +ncd2vdb "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" ".vdbs/RAM2GS_LCMXO2_1200HC_impl1_map.vdb" + +Loading device for application ncd2vdb from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. + +trce -f "RAM2GS_LCMXO2_1200HC_impl1.mt" -o "RAM2GS_LCMXO2_1200HC_impl1.tw1" "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" "RAM2GS_LCMXO2_1200HC_impl1.prf" +trce: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Loading design for application trce from file ram2gs_lcmxo2_1200hc_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 4 +Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:28 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_1200HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.prf +Design file: ram2gs_lcmxo2_1200hc_impl1_map.ncd +Preference file: ram2gs_lcmxo2_1200hc_impl1.prf +Device,speed: LCMXO2-1200HC,4 +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +Report Type: based on TRACE automatically generated preferences +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Setup): +--------------- + +Timing errors: 349 Score: 848079 +Cumulative negative slack: 584487 + +Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:28 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_1200HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.prf +Design file: ram2gs_lcmxo2_1200hc_impl1_map.ncd +Preference file: ram2gs_lcmxo2_1200hc_impl1.prf +Device,speed: LCMXO2-1200HC,M +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 349 (setup), 0 (hold) +Score: 848079 (setup), 0 (hold) +Cumulative negative slack: 584487 (584487+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 48 MB + + +ldbanno "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" -n Verilog -o "RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo" -w -neg +ldbanno: version Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Writing a Verilog netlist using the orca library type based on the RAM2GS_LCMXO2_1200HC_impl1_map design file. + + +Loading design for application ldbanno from file RAM2GS_LCMXO2_1200HC_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 4 +Loading device for application ldbanno from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +Converting design RAM2GS_LCMXO2_1200HC_impl1_map.ncd into .ldb format. +Writing Verilog netlist to file RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo +Writing SDF timing to file RAM2GS_LCMXO2_1200HC_impl1_mapvo.sdf + +Total CPU Time: 1 secs +Total REAL Time: 2 secs +Peak Memory Usage: 41 MB + +ldbanno "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" -n VHDL -o "RAM2GS_LCMXO2_1200HC_impl1_mapvho.vho" -w -neg +ldbanno: version Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Writing a VHDL netlist using the orca library type based on the RAM2GS_LCMXO2_1200HC_impl1_map design file. + + +Loading design for application ldbanno from file RAM2GS_LCMXO2_1200HC_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 4 +Loading device for application ldbanno from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +Converting design RAM2GS_LCMXO2_1200HC_impl1_map.ncd into .ldb format. +Writing VHDL netlist to file RAM2GS_LCMXO2_1200HC_impl1_mapvho.vho +Writing SDF timing to file RAM2GS_LCMXO2_1200HC_impl1_mapvho.sdf + +Total CPU Time: 1 secs +Total REAL Time: 0 secs +Peak Memory Usage: 40 MB + +mpartrce -p "RAM2GS_LCMXO2_1200HC_impl1.p2t" -f "RAM2GS_LCMXO2_1200HC_impl1.p3t" -tf "RAM2GS_LCMXO2_1200HC_impl1.pt" "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" "RAM2GS_LCMXO2_1200HC_impl1.ncd" + +---- MParTrce Tool ---- +Removing old design directory at request of -rem command line option to this program. +Running par. Please wait . . . + +Lattice Place and Route Report for Design "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" +Tue Aug 15 05:03:31 2023 + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf +Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf. +Placement level-cost: 5-1. +Routing Iterations: 6 + +Loading design for application par from file RAM2GS_LCMXO2_1200HC_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 4 +Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +License checked out. + + +Ignore Preference Error(s): True +Device utilization summary: + + PIO (prelim) 67+4(JTAG)/108 66% used + 67+4(JTAG)/80 89% bonded + + SLICE 75/640 11% used + + + +Number of Signals: 285 +Number of Connections: 674 + + +Pin Constraint Summary: + 66 out of 67 pins locked (98% locked). + +The following 2 signals are selected to use the primary clock routing resources: + RCLK_c (driver: RCLK, clk load #: 40) + PHI2_c (driver: PHI2, clk load #: 13) + + + + +The following 1 signal is selected to use the secondary clock routing resources: + nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0) + + +No signal is selected as Global Set/Reset. +. +Starting Placer Phase 0. +.......... +Finished Placer Phase 0. REAL time: 0 secs + +Starting Placer Phase 1. +................... +Placer score = 143529. +Finished Placer Phase 1. REAL time: 4 secs + +Starting Placer Phase 2. +. +Placer score = 143450 +Finished Placer Phase 2. REAL time: 4 secs + + +------------------ Clock Report ------------------ + +Global Clock Resources: + CLK_PIN : 0 out of 8 (0%) + General PIO: 3 out of 108 (2%) + PLL : 0 out of 1 (0%) + DCM : 0 out of 2 (0%) + DCC : 0 out of 8 (0%) + +Global Clocks: + PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 40 + PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3D)", clk load = 13 + SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL8B)", clk load = 7, ce load = 0, sr load = 0 + + PRIMARY : 2 out of 8 (25%) + SECONDARY: 1 out of 8 (12%) + +Edge Clocks: + No edge clock selected. + +--------------- End of Clock Report --------------- + + +I/O Usage Summary (final): + 67 + 4(JTAG) out of 108 (65.7%) PIO sites used. + 67 + 4(JTAG) out of 80 (88.8%) bonded PIO sites used. + Number of PIO comps: 67; differential: 0. + Number of Vref pins used: 0. + +I/O Bank Usage Summary: ++----------+----------------+------------+-----------+ +| I/O Bank | Usage | Bank Vccio | Bank Vref | ++----------+----------------+------------+-----------+ +| 0 | 13 / 19 ( 68%) | 2.5V | - | +| 1 | 20 / 21 ( 95%) | 2.5V | - | +| 2 | 17 / 20 ( 85%) | 2.5V | - | +| 3 | 17 / 20 ( 85%) | 2.5V | - | ++----------+----------------+------------+-----------+ + +Total placer CPU time: 4 secs + +Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd. + +0 connections routed; 674 unrouted. +Starting router resource preassignment + + + + + +Completed router resource preassignment. Real time: 7 secs + +Start NBR router at 05:03:38 08/15/23 + +***************************************************************** +Info: NBR allows conflicts(one node used by more than one signal) + in the earlier iterations. In each iteration, it tries to + solve the conflicts while keeping the critical connections + routed as short as possible. The routing process is said to + be completed when no conflicts exist and all connections + are routed. +Note: NBR uses a different method to calculate timing slacks. The + worst slack and total negative slack may not be the same as + that in TRCE report. You should always run TRCE to verify + your design. +***************************************************************** + +Start NBR special constraint process at 05:03:38 08/15/23 + +Start NBR section for initial routing at 05:03:38 08/15/23 +Level 1, iteration 1 +2(0.00%) conflicts; 537(79.67%) untouched conns; 468417 (nbr) score; +Estimated worst slack/total negative slack: -5.186ns/-468.418ns; real time: 7 secs +Level 2, iteration 1 +11(0.01%) conflicts; 474(70.33%) untouched conns; 377050 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-377.051ns; real time: 8 secs +Level 3, iteration 1 +20(0.02%) conflicts; 254(37.69%) untouched conns; 373495 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-373.496ns; real time: 8 secs +Level 4, iteration 1 +11(0.01%) conflicts; 0(0.00%) untouched conn; 386254 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-386.255ns; real time: 8 secs + +Info: Initial congestion level at 75% usage is 0 +Info: Initial congestion area at 75% usage is 0 (0.00%) + +Start NBR section for normal routing at 05:03:39 08/15/23 +Level 1, iteration 1 +7(0.01%) conflicts; 4(0.59%) untouched conns; 379537 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-379.537ns; real time: 8 secs +Level 4, iteration 1 +9(0.01%) conflicts; 0(0.00%) untouched conn; 380799 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-380.800ns; real time: 8 secs +Level 4, iteration 2 +6(0.01%) conflicts; 0(0.00%) untouched conn; 390586 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-390.587ns; real time: 8 secs +Level 4, iteration 3 +6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-384.719ns; real time: 8 secs +Level 4, iteration 4 +6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-384.719ns; real time: 8 secs +Level 4, iteration 5 +4(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.014ns; real time: 8 secs +Level 4, iteration 6 +3(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.014ns; real time: 8 secs +Level 4, iteration 7 +3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.875ns; real time: 8 secs +Level 4, iteration 8 +3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.875ns; real time: 8 secs +Level 4, iteration 9 +2(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-409.289ns; real time: 8 secs +Level 4, iteration 10 +3(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-409.289ns; real time: 8 secs +Level 4, iteration 11 +3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.036ns; real time: 8 secs +Level 4, iteration 12 +3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.036ns; real time: 8 secs +Level 4, iteration 13 +2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score; +Estimated worst slack/total negative slack: -4.574ns/-404.327ns; real time: 8 secs +Level 4, iteration 14 +2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score; +Estimated worst slack/total negative slack: -4.574ns/-404.327ns; real time: 8 secs +Level 4, iteration 15 +2(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 16 +3(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 17 +2(0.00%) conflicts; 0(0.00%) untouched conn; 404668 (nbr) score; +Estimated worst slack/total negative slack: -4.574ns/-404.669ns; real time: 8 secs +Level 4, iteration 18 +1(0.00%) conflict; 0(0.00%) untouched conn; 404668 (nbr) score; +Estimated worst slack/total negative slack: -4.574ns/-404.669ns; real time: 8 secs +Level 4, iteration 19 +1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 20 +1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 21 +1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 22 +1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 23 +1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.277ns; real time: 8 secs +Level 4, iteration 24 +1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.277ns; real time: 8 secs +Level 4, iteration 25 +0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 8 secs + +Start NBR section for performance tuning (iteration 1) at 05:03:39 08/15/23 +Level 4, iteration 1 +1(0.00%) conflict; 0(0.00%) untouched conn; 405829 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-405.830ns; real time: 8 secs +Level 4, iteration 2 +0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 8 secs + +Start NBR section for re-routing at 05:03:39 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 8 secs + +Start NBR section for post-routing at 05:03:39 08/15/23 + +End NBR router with 0 unrouted connection + +NBR Summary +----------- + Number of unrouted connections : 0 (0.00%) + Number of connections with timing violations : 254 (37.69%) + Estimated worst slack : -4.650ns + Timing score : 391939 +----------- +Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. + + + + + +Total CPU time 7 secs +Total REAL time: 8 secs +Completely routed. +End of route. 674 routed (100.00%); 0 unrouted. + +Hold time timing score: 0, hold timing errors: 0 + +Timing score: 391939 + +Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd. + + +PAR_SUMMARY::Run status = Completed +PAR_SUMMARY::Number of unrouted conns = 0 +PAR_SUMMARY::Worst slack> = -4.650 +PAR_SUMMARY::Timing score> = 391.939 +PAR_SUMMARY::Worst slack> = 0.304 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Number of errors = 0 + +Total CPU time to completion: 8 secs +Total REAL time to completion: 8 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Exiting par with exit code 0 +Exiting mpartrce with exit code 0 + +trce -f "RAM2GS_LCMXO2_1200HC_impl1.pt" -o "RAM2GS_LCMXO2_1200HC_impl1.twr" "RAM2GS_LCMXO2_1200HC_impl1.ncd" "RAM2GS_LCMXO2_1200HC_impl1.prf" +trce: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Loading design for application trce from file ram2gs_lcmxo2_1200hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 4 +Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:40 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_1200HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf +Design file: ram2gs_lcmxo2_1200hc_impl1.ncd +Preference file: ram2gs_lcmxo2_1200hc_impl1.prf +Device,speed: LCMXO2-1200HC,4 +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +Report Type: based on TRACE automatically generated preferences +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Setup): +--------------- + +Timing errors: 335 Score: 391939 +Cumulative negative slack: 304509 + +Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:40 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_1200HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf +Design file: ram2gs_lcmxo2_1200hc_impl1.ncd +Preference file: ram2gs_lcmxo2_1200hc_impl1.prf +Device,speed: LCMXO2-1200HC,m +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 335 (setup), 0 (hold) +Score: 391939 (setup), 0 (hold) +Cumulative negative slack: 304509 (304509+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 46 MB + + +iotiming "RAM2GS_LCMXO2_1200HC_impl1.ncd" "RAM2GS_LCMXO2_1200HC_impl1.prf" +I/O Timing Report: +: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 4 +Loading device for application iotiming from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +Running Performance Grade: 4 +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... + +Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 5 +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +Running Performance Grade: 5 +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... + +Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 6 +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +Running Performance Grade: 6 +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... + +Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: M +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +Running Performance Grade: M +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... +Done. + +tmcheck -par "RAM2GS_LCMXO2_1200HC_impl1.par" + +bitgen -f "RAM2GS_LCMXO2_1200HC_impl1.t2b" -w "RAM2GS_LCMXO2_1200HC_impl1.ncd" -jedec "RAM2GS_LCMXO2_1200HC_impl1.prf" + + +BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + + +Loading design for application Bitgen from file RAM2GS_LCMXO2_1200HC_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 4 +Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. + +Running DRC. +DRC detected 0 errors and 0 warnings. +Reading Preference File from RAM2GS_LCMXO2_1200HC_impl1.prf. + +Preference Summary: ++---------------------------------+---------------------------------+ +| Preference | Current Setting | ++---------------------------------+---------------------------------+ +| RamCfg | Reset** | ++---------------------------------+---------------------------------+ +| MCCLK_FREQ | 2.08** | ++---------------------------------+---------------------------------+ +| CONFIG_SECURE | OFF** | ++---------------------------------+---------------------------------+ +| INBUF | ON** | ++---------------------------------+---------------------------------+ +| JTAG_PORT | ENABLE** | ++---------------------------------+---------------------------------+ +| SDM_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| SLAVE_SPI_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| MASTER_SPI_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| I2C_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| MUX_CONFIGURATION_PORTS | DISABLE** | ++---------------------------------+---------------------------------+ +| CONFIGURATION | CFG** | ++---------------------------------+---------------------------------+ +| COMPRESS_CONFIG | ON** | ++---------------------------------+---------------------------------+ +| MY_ASSP | OFF** | ++---------------------------------+---------------------------------+ +| ONE_TIME_PROGRAM | OFF** | ++---------------------------------+---------------------------------+ +| ENABLE_TRANSFR | DISABLE** | ++---------------------------------+---------------------------------+ +| SHAREDEBRINIT | DISABLE** | ++---------------------------------+---------------------------------+ +| BACKGROUND_RECONFIG | OFF** | ++---------------------------------+---------------------------------+ + * Default setting. + ** The specified setting matches the default setting. + + +Creating bit map... + +Bitstream Status: Final Version 1.95. + +Saving bit stream in "RAM2GS_LCMXO2_1200HC_impl1.jed". + +=========== +UFM Summary. +=========== +UFM Size: 511 Pages (128*511 Bits). +UFM Utilization: General Purpose Flash Memory. + +Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510). +Initialized UFM Pages: 0 Page. + +Total CPU Time: 2 secs +Total REAL Time: 3 secs +Peak Memory Usage: 253 MB diff --git a/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html new file mode 100644 index 0000000..2f2bbe3 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html @@ -0,0 +1,9 @@ + 
    Setting log file to 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html'.
+Starting: parse design source files
+(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v'
+(VERI-1482) Analyzing Verilog file 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v'
+INFO - D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
+INFO - D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v(1,1-411,10) (VERI-9000) elaborating module 'RAM2GS'
+Done: design load finished with (0) errors, and (0) warnings
+
+
    \ No newline at end of file diff --git a/CPLD/LCMXO2-1200HC/impl1/impl1.xcf b/CPLD/LCMXO2-1200HC/impl1/impl1.xcf new file mode 100644 index 0000000..9cdf76b --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/impl1.xcf @@ -0,0 +1,55 @@ + + + + + + JTAG + + + 1 + Lattice + MachXO2 + LCMXO2-1200HC + 0x012ba043 + All + LCMXO2-1200HC + + 8 + 11111111 + 1 + 0 + + D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.jed + 08/15/23 05:01:25 + 0x680B + FLASH Erase,Program,Verify + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB + EzUSB-0 + \\?\usb#vid_1134&amp;pid_8001#5&amp;887acb0&amp;0&amp;13# + + TRST ABSENT; + ISPEN ABSENT; + + + diff --git a/CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1.ior b/CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1.ior new file mode 100644 index 0000000..c8edb74 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1.ior @@ -0,0 +1,139 @@ +Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 5 +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 6 +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: M +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +// Design: RAM2GS +// Package: TQFP100 +// ncd File: ram2gs_lcmxo2_1200hc_impl1.ncd +// Version: Diamond (64-bit) 3.12.1.454 +// Written on Tue Aug 15 05:03:41 2023 +// M: Minimum Performance Grade +// iotiming RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml + +I/O Timing Report (All units are in ns) + +Worst Case Results across Performance Grades (M, 6, 5, 4): + +// Input Setup and Hold Times + +Port Clock Edge Setup Performance_Grade Hold Performance_Grade +---------------------------------------------------------------------- +CROW[0] nCRAS F 0.891 4 0.676 4 +CROW[1] nCRAS F 0.281 4 1.216 4 +Din[0] PHI2 F 7.907 4 0.089 6 +Din[0] nCCAS F 1.465 4 0.158 4 +Din[1] PHI2 F 7.300 4 1.026 4 +Din[1] nCCAS F 1.035 4 0.527 4 +Din[2] PHI2 F 6.237 4 1.467 4 +Din[2] nCCAS F 1.719 4 -0.108 M +Din[3] PHI2 F 6.623 4 0.176 6 +Din[3] nCCAS F 0.339 4 0.916 4 +Din[4] PHI2 F 6.902 4 1.033 4 +Din[4] nCCAS F 0.687 4 0.951 4 +Din[5] PHI2 F 6.837 4 1.369 4 +Din[5] nCCAS F 2.810 4 -0.220 M +Din[6] PHI2 F 7.648 4 -0.050 M +Din[6] nCCAS F 1.281 4 0.266 4 +Din[7] PHI2 F 7.823 4 -0.159 M +Din[7] nCCAS F 1.810 4 -0.096 M +MAin[0] PHI2 F 6.751 4 -0.273 M +MAin[0] nCRAS F 1.765 4 -0.033 4 +MAin[1] PHI2 F 5.718 4 0.117 M +MAin[1] nCRAS F 1.814 4 -0.051 M +MAin[2] PHI2 F 5.759 4 -0.021 M +MAin[2] nCRAS F 1.323 4 0.309 4 +MAin[3] PHI2 F 6.165 4 -0.235 M +MAin[3] nCRAS F 0.694 4 0.836 4 +MAin[4] PHI2 F 5.236 4 -0.147 M +MAin[4] nCRAS F 0.730 4 0.835 4 +MAin[5] PHI2 F 6.024 4 0.135 M +MAin[5] nCRAS F 0.734 4 0.868 4 +MAin[6] PHI2 F 5.689 4 -0.277 M +MAin[6] nCRAS F 0.288 4 1.210 4 +MAin[7] PHI2 F 6.398 4 -0.307 M +MAin[7] nCRAS F 1.215 4 0.401 4 +MAin[8] nCRAS F 0.817 4 0.727 4 +MAin[9] nCRAS F 0.941 4 0.601 4 +PHI2 RCLK R 0.771 4 1.143 4 +UFMSDO RCLK R -0.238 M 2.305 4 +nCCAS RCLK R 1.651 4 0.388 4 +nCCAS nCRAS F 5.028 4 -0.828 M +nCRAS RCLK R 0.593 4 1.309 4 +nFWE PHI2 F 5.741 4 0.781 4 +nFWE nCRAS F 0.578 4 0.996 4 + + +// Clock to Output Delay + +Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade +------------------------------------------------------------------------ +LED RCLK R 14.758 4 4.129 M +LED nCRAS F 12.396 4 3.434 M +RA[0] RCLK R 13.780 4 3.894 M +RA[0] nCRAS F 11.795 4 3.277 M +RA[10] RCLK R 12.425 4 3.587 M +RA[11] PHI2 R 10.432 4 3.084 M +RA[1] RCLK R 15.081 4 4.198 M +RA[1] nCRAS F 12.364 4 3.447 M +RA[2] RCLK R 14.518 4 4.082 M +RA[2] nCRAS F 11.696 4 3.275 M +RA[3] RCLK R 13.789 4 3.897 M +RA[3] nCRAS F 12.223 4 3.392 M +RA[4] RCLK R 15.175 4 4.228 M +RA[4] nCRAS F 12.424 4 3.464 M +RA[5] RCLK R 13.789 4 3.897 M +RA[5] nCRAS F 12.359 4 3.437 M +RA[6] RCLK R 15.420 4 4.299 M +RA[6] nCRAS F 12.865 4 3.560 M +RA[7] RCLK R 14.672 4 4.127 M +RA[7] nCRAS F 12.253 4 3.386 M +RA[8] RCLK R 14.952 4 4.191 M +RA[8] nCRAS F 12.244 4 3.383 M +RA[9] RCLK R 14.092 4 3.978 M +RA[9] nCRAS F 13.164 4 3.653 M +RBA[0] nCRAS F 10.278 4 2.970 M +RBA[1] nCRAS F 10.474 4 3.030 M +RCKE RCLK R 12.407 4 3.610 M +RDQMH RCLK R 13.754 4 3.857 M +RDQML RCLK R 13.482 4 3.833 M +RD[0] nCCAS F 10.515 4 3.076 M +RD[1] nCCAS F 10.118 4 2.965 M +RD[2] nCCAS F 9.759 4 2.886 M +RD[3] nCCAS F 9.798 4 2.878 M +RD[4] nCCAS F 10.979 4 3.178 M +RD[5] nCCAS F 11.063 4 3.207 M +RD[6] nCCAS F 10.317 4 3.018 M +RD[7] nCCAS F 10.232 4 2.986 M +UFMCLK RCLK R 12.402 4 3.606 M +UFMSDI RCLK R 11.975 4 3.501 M +nRCAS RCLK R 12.350 4 3.564 M +nRCS RCLK R 11.923 4 3.459 M +nRRAS RCLK R 11.995 4 3.494 M +nRWE RCLK R 11.975 4 3.501 M +nUFMCS RCLK R 11.818 4 3.434 M +WARNING: you must also run trce with hold speed: 4 +WARNING: you must also run trce with hold speed: 6 +WARNING: you must also run trce with setup speed: M diff --git a/CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1_trce.asd b/CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1_trce.asd new file mode 100644 index 0000000..0894708 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1_trce.asd @@ -0,0 +1,13 @@ +[ActiveSupport TRCE] +; Setup Analysis +Fmax_0 = 174.216 MHz (299.401 MHz); +Fmax_1 = 67.833 MHz (99.079 MHz); +Failed = 2 (Total 2); +Clock_ports = 4; +Clock_nets = 4; +; Hold Analysis +Fmax_0 = 0.304 ns (0.000 ns); +Fmax_1 = 0.379 ns (0.000 ns); +Failed = 0 (Total 2); +Clock_ports = 4; +Clock_nets = 4; diff --git a/CPLD/LCMXO2-1200HC/impl1/synthesis.log b/CPLD/LCMXO2-1200HC/impl1/synthesis.log new file mode 100644 index 0000000..fee4113 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/synthesis.log @@ -0,0 +1,239 @@ +synthesis: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:25 2023 + + +Command Line: synthesis -f RAM2GS_LCMXO2_1200HC_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml + +Synthesis options: +The -a option is MachXO2. +The -s option is 4. +The -t option is TQFP100. +The -d option is LCMXO2-1200HC. +Using package TQFP100. +Using performance grade 4. + + +########################################################## + +### Lattice Family : MachXO2 + +### Device : LCMXO2-1200HC + +### Package : TQFP100 + +### Speed : 4 + +########################################################## + + + +INFO - synthesis: User-Selected Strategy Settings +Optimization goal = Balanced +Top-level module name = RAM2GS. +Target frequency = 200.000000 MHz. +Maximum fanout = 1000. +Timing path count = 3 +BRAM utilization = 100.000000 % +DSP usage = true +DSP utilization = 100.000000 % +fsm_encoding_style = auto +resolve_mixed_drivers = 0 +fix_gated_clocks = 1 + +Mux style = Auto +Use Carry Chain = true +carry_chain_length = 0 +Loop Limit = 1950. +Use IO Insertion = TRUE +Use IO Reg = AUTO + +Resource Sharing = TRUE +Propagate Constants = TRUE +Remove Duplicate Registers = TRUE +force_gsr = auto +ROM style = auto +RAM style = auto +The -comp option is FALSE. +The -syn option is FALSE. +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC (searchpath added) +-p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added) +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1 (searchpath added) +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC (searchpath added) +Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v +NGD file = RAM2GS_LCMXO2_1200HC_impl1.ngd +-sdc option: SDC file input not used. +-lpf option: Output file option is ON. +Hardtimer checking is enabled (default). The -dt option is not used. +The -r option is OFF. [ Remove LOC Properties is OFF. ] +Technology check ok... + +Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 +Compile design. +Compile Design Begin +Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482 +Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 +Top module name (Verilog): RAM2GS +INFO - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1): compiling module RAM2GS. VERI-1018 +WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131): expression size 32 truncated to fit in target size 2. VERI-1209 +WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136): expression size 32 truncated to fit in target size 18. VERI-1209 +WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263): expression size 32 truncated to fit in target size 4. VERI-1209 +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... +Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.44. +Top-level module name = RAM2GS. +INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding +original encoding -> new encoding (one-hot encoding) + + 0000 -> 0000000000000001 + + 0001 -> 0000000000000010 + + 0010 -> 0000000000000100 + + 0011 -> 0000000000001000 + + 0100 -> 0000000000010000 + + 0101 -> 0000000000100000 + + 0110 -> 0000000001000000 + + 0111 -> 0000000010000000 + + 1000 -> 0000000100000000 + + 1001 -> 0000001000000000 + + 1010 -> 0000010000000000 + + 1011 -> 0000100000000000 + + 1100 -> 0001000000000000 + + 1101 -> 0010000000000000 + + 1110 -> 0100000000000000 + + 1111 -> 1000000000000000 + +INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding +original encoding -> new encoding (one-hot encoding) + + 00 -> 0001 + + 01 -> 0010 + + 10 -> 0100 + + 11 -> 1000 + + + + +GSR will not be inferred because no asynchronous signal was found in the netlist. +WARNING - synthesis: Initial value found on instance C1Submitted_406 will be ignored. +Applying 200.000000 MHz constraint to all clocks + +WARNING - synthesis: No user .sdc file. +Results of NGD DRC are available in RAM2GS_drc.log. +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... +All blocks are expanded and NGD expansion is successful. +Writing NGD file RAM2GS_LCMXO2_1200HC_impl1.ngd. + +################### Begin Area Report (RAM2GS)###################### +Number of register bits => 102 of 1520 (6 % ) +BB => 8 +CCU2D => 10 +FD1P3AX => 29 +FD1P3AY => 5 +FD1P3IX => 3 +FD1S3AX => 47 +FD1S3IX => 14 +FD1S3JX => 4 +GSR => 1 +IB => 26 +INV => 3 +LUT4 => 122 +OB => 33 +PFUMX => 1 +################### End Area Report ################## + +################### Begin BlackBox Report ###################### +TSALL => 1 +################### End BlackBox Report ################## + +################### Begin Clock Report ###################### +Clock Nets +Number of Clocks: 4 + Net : RCLK_c, loads : 62 + Net : PHI2_c, loads : 11 + Net : nCCAS_c, loads : 2 + Net : nCRAS_c, loads : 2 +Clock Enable Nets +Number of Clock Enables: 14 +Top 10 highest fanout Clock Enables: + Net : RCLK_c_enable_27, loads : 16 + Net : RCLK_c_enable_6, loads : 4 + Net : PHI2_N_120_enable_8, loads : 3 + Net : RCLK_c_enable_10, loads : 3 + Net : RCLK_c_enable_5, loads : 2 + Net : PHI2_N_120_enable_3, loads : 1 + Net : Ready_N_292, loads : 1 + Net : PHI2_N_120_enable_2, loads : 1 + Net : RCLK_c_enable_15, loads : 1 + Net : PHI2_N_120_enable_6, loads : 1 +Highest fanout non-clock nets +Top 10 highest fanout non-clock nets: + Net : RCLK_c_enable_27, loads : 16 + Net : InitReady, loads : 15 + Net : nCRAS_c__inv, loads : 15 + Net : RASr2, loads : 14 + Net : nRowColSel_N_35, loads : 13 + Net : n2380, loads : 13 + Net : nRowColSel, loads : 12 + Net : Ready, loads : 12 + Net : Din_c_4, loads : 10 + Net : MAin_c_1, loads : 10 +################### End Clock Report ################## + +Timing Report Summary +-------------- +-------------------------------------------------------------------------------- +Constraint | Constraint| Actual|Levels +-------------------------------------------------------------------------------- + | | | +create_clock -period 5.000000 -name | | | +clk3 [get_nets nCCAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk2 [get_nets nCRAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk1 [get_nets PHI2_c] | 200.000 MHz| 50.413 MHz| 6 * + | | | +create_clock -period 5.000000 -name | | | +clk0 [get_nets RCLK_c] | 200.000 MHz| 120.207 MHz| 5 * + | | | +-------------------------------------------------------------------------------- + + +2 constraints not met. + + +Peak Memory Usage: 55.238 MB + +-------------------------------------------------------------- +Elapsed CPU time for LSE flow : 0.891 secs +-------------------------------------------------------------- diff --git a/CPLD/LCMXO2-1200HC/impl1/synthesis_lse.html b/CPLD/LCMXO2-1200HC/impl1/synthesis_lse.html new file mode 100644 index 0000000..1a480d5 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/synthesis_lse.html @@ -0,0 +1,304 @@ + +Synthesis and Ngdbuild Report + + +
    Synthesis and Ngdbuild  Report
+synthesis:  version Diamond (64-bit) 3.12.1.454
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 15 05:03:25 2023
+
+
+Command Line:  synthesis -f RAM2GS_LCMXO2_1200HC_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml 
+
+Synthesis options:
+The -a option is MachXO2.
+The -s option is 4.
+The -t option is TQFP100.
+The -d option is LCMXO2-1200HC.
+Using package TQFP100.
+Using performance grade 4.
+                                                          
+
+##########################################################
+
+### Lattice Family : MachXO2
+
+### Device  : LCMXO2-1200HC
+
+### Package : TQFP100
+
+### Speed   : 4
+
+##########################################################
+
+                                                          
+
+INFO - synthesis: User-Selected Strategy Settings
+Optimization goal = Balanced
+Top-level module name = RAM2GS.
+Target frequency = 200.000000 MHz.
+Maximum fanout = 1000.
+Timing path count = 3
+BRAM utilization = 100.000000 %
+DSP usage = true
+DSP utilization = 100.000000 %
+fsm_encoding_style = auto
+resolve_mixed_drivers = 0
+fix_gated_clocks = 1
+
+Mux style = Auto
+Use Carry Chain = true
+carry_chain_length = 0
+Loop Limit = 1950.
+Use IO Insertion = TRUE
+Use IO Reg = AUTO
+
+Resource Sharing = TRUE
+Propagate Constants = TRUE
+Remove Duplicate Registers = TRUE
+force_gsr = auto
+ROM style = auto
+RAM style = auto
+The -comp option is FALSE.
+The -syn option is FALSE.
+-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC (searchpath added)
+-p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
+-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1 (searchpath added)
+-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC (searchpath added)
+Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v
+NGD file = RAM2GS_LCMXO2_1200HC_impl1.ngd
+-sdc option: SDC file input not used.
+-lpf option: Output file option is ON.
+Hardtimer checking is enabled (default). The -dt option is not used.
+The -r option is OFF. [ Remove LOC Properties is OFF. ]
+Technology check ok...
+
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
+Compile design.
+Compile Design Begin
+Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
+Top module name (Verilog): RAM2GS
+INFO - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1): compiling module RAM2GS. VERI-1018
+WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131): expression size 32 truncated to fit in target size 2. VERI-1209
+WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136): expression size 32 truncated to fit in target size 18. VERI-1209
+WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263): expression size 32 truncated to fit in target size 4. VERI-1209
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.44.
+Top-level module name = RAM2GS.
+INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 0000 -> 0000000000000001
+
+ 0001 -> 0000000000000010
+
+ 0010 -> 0000000000000100
+
+ 0011 -> 0000000000001000
+
+ 0100 -> 0000000000010000
+
+ 0101 -> 0000000000100000
+
+ 0110 -> 0000000001000000
+
+ 0111 -> 0000000010000000
+
+ 1000 -> 0000000100000000
+
+ 1001 -> 0000001000000000
+
+ 1010 -> 0000010000000000
+
+ 1011 -> 0000100000000000
+
+ 1100 -> 0001000000000000
+
+ 1101 -> 0010000000000000
+
+ 1110 -> 0100000000000000
+
+ 1111 -> 1000000000000000
+
+INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 00 -> 0001
+
+ 01 -> 0010
+
+ 10 -> 0100
+
+ 11 -> 1000
+
+
+
+
+GSR will not be inferred because no asynchronous signal was found in the netlist.
+WARNING - synthesis: Initial value found on instance C1Submitted_406 will be ignored.
+Applying 200.000000 MHz constraint to all clocks
+
+WARNING - synthesis: No user .sdc file.
+Results of NGD DRC are available in RAM2GS_drc.log.
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+All blocks are expanded and NGD expansion is successful.
+Writing NGD file RAM2GS_LCMXO2_1200HC_impl1.ngd.
+
+################### Begin Area Report (RAM2GS)######################
+Number of register bits => 102 of 1520 (6 % )
+BB => 8
+CCU2D => 10
+FD1P3AX => 29
+FD1P3AY => 5
+FD1P3IX => 3
+FD1S3AX => 47
+FD1S3IX => 14
+FD1S3JX => 4
+GSR => 1
+IB => 26
+INV => 3
+LUT4 => 122
+OB => 33
+PFUMX => 1
+################### End Area Report ##################
+
+################### Begin BlackBox Report ######################
+TSALL => 1
+################### End BlackBox Report ##################
+
+################### Begin Clock Report ######################
+Clock Nets
+Number of Clocks: 4
+  Net : RCLK_c, loads : 62
+  Net : PHI2_c, loads : 11
+  Net : nCCAS_c, loads : 2
+  Net : nCRAS_c, loads : 2
+Clock Enable Nets
+Number of Clock Enables: 14
+Top 10 highest fanout Clock Enables:
+  Net : RCLK_c_enable_27, loads : 16
+  Net : RCLK_c_enable_6, loads : 4
+  Net : PHI2_N_120_enable_8, loads : 3
+  Net : RCLK_c_enable_10, loads : 3
+  Net : RCLK_c_enable_5, loads : 2
+  Net : PHI2_N_120_enable_3, loads : 1
+  Net : Ready_N_292, loads : 1
+  Net : PHI2_N_120_enable_2, loads : 1
+  Net : RCLK_c_enable_15, loads : 1
+  Net : PHI2_N_120_enable_6, loads : 1
+Highest fanout non-clock nets
+Top 10 highest fanout non-clock nets:
+  Net : RCLK_c_enable_27, loads : 16
+  Net : InitReady, loads : 15
+  Net : nCRAS_c__inv, loads : 15
+  Net : RASr2, loads : 14
+  Net : nRowColSel_N_35, loads : 13
+  Net : n2380, loads : 13
+  Net : nRowColSel, loads : 12
+  Net : Ready, loads : 12
+  Net : Din_c_4, loads : 10
+  Net : MAin_c_1, loads : 10
+################### End Clock Report ##################
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets PHI2_c]                  |  200.000 MHz|   50.413 MHz|     6 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |  200.000 MHz|  120.207 MHz|     5 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+
+Peak Memory Usage: 55.238  MB
+
+--------------------------------------------------------------
+Elapsed CPU time for LSE flow : 0.891  secs
+--------------------------------------------------------------
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO2-1200HC/impl1/xxx_lse_cp_file_list b/CPLD/LCMXO2-1200HC/impl1/xxx_lse_cp_file_list new file mode 100644 index 0000000..1c1a02c --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/xxx_lse_cp_file_list @@ -0,0 +1,250 @@ +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v diff --git a/CPLD/LCMXO2-1200HC/impl1/xxx_lse_sign_file b/CPLD/LCMXO2-1200HC/impl1/xxx_lse_sign_file new file mode 100644 index 0000000..7e27975 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/xxx_lse_sign_file @@ -0,0 +1,250 @@ +LSE_CPS_ID_1 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:8[8:12]" +LSE_CPS_ID_2 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_3 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:186[13] 231[7]" +LSE_CPS_ID_4 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]" +LSE_CPS_ID_5 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]" +LSE_CPS_ID_6 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_7 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_8 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_9 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_10 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_11 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_12 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_13 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_14 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_15 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_16 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_17 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_18 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_19 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:141[9] 144[5]" +LSE_CPS_ID_20 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_21 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_22 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_23 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_24 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_25 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_26 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_27 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:255[14] 262[8]" +LSE_CPS_ID_28 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_29 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_30 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_31 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_32 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_33 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_34 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_35 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]" +LSE_CPS_ID_36 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:321[13] 335[7]" +LSE_CPS_ID_37 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_38 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_39 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_40 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_41 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_42 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_43 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_44 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:99[22:51]" +LSE_CPS_ID_45 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_46 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_47 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" +LSE_CPS_ID_48 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_49 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_50 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_51 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_52 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_53 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_54 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_55 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:168[14] 184[8]" +LSE_CPS_ID_56 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_57 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_58 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_59 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" +LSE_CPS_ID_60 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_61 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_62 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_63 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:345[12] 409[6]" +LSE_CPS_ID_64 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_65 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:58[17:46]" +LSE_CPS_ID_66 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_67 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:195[13] 231[7]" +LSE_CPS_ID_68 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" +LSE_CPS_ID_69 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_70 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_71 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" +LSE_CPS_ID_72 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_73 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_74 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_75 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:83[6:15]" +LSE_CPS_ID_76 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_77 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:195[13] 231[7]" +LSE_CPS_ID_78 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_79 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_80 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_81 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:83[6:15]" +LSE_CPS_ID_82 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_83 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_84 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:86[13:15]" +LSE_CPS_ID_85 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_86 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_87 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_88 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:233[8:20]" +LSE_CPS_ID_89 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:233[8:20]" +LSE_CPS_ID_90 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_91 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_92 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_93 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_94 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_95 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_96 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_97 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_98 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_99 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_100 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_101 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_102 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:233[8:20]" +LSE_CPS_ID_103 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:15[12:17]" +LSE_CPS_ID_104 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_105 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_106 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_107 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_108 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_109 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_110 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:23[27:31]" +LSE_CPS_ID_111 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:83[6:15]" +LSE_CPS_ID_112 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_113 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_114 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_115 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_116 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_117 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_118 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_119 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_120 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_121 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_122 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_123 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_124 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_125 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_126 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_127 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_128 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_129 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_130 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_131 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_132 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_133 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_134 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_135 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_136 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_137 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_138 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_139 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_140 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_141 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_142 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_143 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_144 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_145 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_146 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_147 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_148 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_149 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_150 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_151 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_152 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_153 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_154 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_155 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:315[17:31]" +LSE_CPS_ID_156 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:143[40:46]" +LSE_CPS_ID_157 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:143[40:46]" +LSE_CPS_ID_158 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_159 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_160 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_161 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_162 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_163 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_164 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_165 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_166 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_167 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_168 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_169 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_170 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:315[17:31]" +LSE_CPS_ID_171 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_172 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_173 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_174 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_175 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_176 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_177 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_178 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_179 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_180 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_181 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:22[9:12]" +LSE_CPS_ID_182 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:47[19:22]" +LSE_CPS_ID_183 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:47[19:22]" +LSE_CPS_ID_184 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_185 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_186 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_187 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_188 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_189 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_190 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_191 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_192 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_193 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_194 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_195 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_196 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[13:17]" +LSE_CPS_ID_197 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:45[13:17]" +LSE_CPS_ID_198 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[45:49]" +LSE_CPS_ID_199 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[23:28]" +LSE_CPS_ID_200 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[34:39]" +LSE_CPS_ID_201 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:56[16:21]" +LSE_CPS_ID_202 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:56[9:14]" +LSE_CPS_ID_203 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:63[13:19]" +LSE_CPS_ID_204 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:64[13:19]" +LSE_CPS_ID_205 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:65[13:19]" +LSE_CPS_ID_206 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:8[8:12]" +LSE_CPS_ID_207 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_208 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_209 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_210 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_211 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_212 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_213 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_214 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_215 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_216 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_217 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:34[14:18]" +LSE_CPS_ID_218 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:34[14:18]" +LSE_CPS_ID_219 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_220 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_221 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_222 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_223 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_224 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_225 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_226 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_227 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[8:13]" +LSE_CPS_ID_228 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[15:20]" +LSE_CPS_ID_229 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:36[8:12]" +LSE_CPS_ID_230 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:41[8:12]" +LSE_CPS_ID_231 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:66[8:14]" +LSE_CPS_ID_232 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_233 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:23[17:23]" +LSE_CPS_ID_234 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_235 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]" +LSE_CPS_ID_236 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" +LSE_CPS_ID_237 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_238 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_239 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:134[9] 138[5]" +LSE_CPS_ID_240 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]" +LSE_CPS_ID_241 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_242 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_243 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_244 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_245 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_246 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:402[16:47]" +LSE_CPS_ID_247 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[15:20]" +LSE_CPS_ID_248 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_249 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[8:13]" +LSE_CPS_ID_250 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:402[16:47]" diff --git a/CPLD/LCMXO2-640HC/.run_manager.ini b/CPLD/LCMXO2-640HC/.run_manager.ini new file mode 100644 index 0000000..8c0aa7b --- /dev/null +++ b/CPLD/LCMXO2-640HC/.run_manager.ini @@ -0,0 +1,9 @@ +[Runmanager] +Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0) +windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) +headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0) + +[impl1%3CStrategy1%3E] +isChecked=false +isHidden=false +isExpanded=false diff --git a/CPLD/LCMXO2-640HC/.setting.ini b/CPLD/LCMXO2-640HC/.setting.ini new file mode 100644 index 0000000..713c9cf --- /dev/null +++ b/CPLD/LCMXO2-640HC/.setting.ini @@ -0,0 +1,4 @@ +[General] +Export.auto_tasks=Jedecgen +PAR.auto_tasks=PARTrace, IOTiming +Map.auto_tasks=MapTrace, MapVerilogSimFile, MapVHDLSimFile diff --git a/CPLD/LCMXO2-640HC/.spread_sheet.ini b/CPLD/LCMXO2-640HC/.spread_sheet.ini new file mode 100644 index 0000000..6c511f4 --- /dev/null +++ b/CPLD/LCMXO2-640HC/.spread_sheet.ini @@ -0,0 +1,3 @@ +[General] +COLUMN_POS_INFO_NAME_-1_0=Prioritize +COLUMN_POS_INFO_NAME_-1_1=PIO Register diff --git a/CPLD/LCMXO2-640HC/.spreadsheet_view.ini b/CPLD/LCMXO2-640HC/.spreadsheet_view.ini new file mode 100644 index 0000000..f26306f --- /dev/null +++ b/CPLD/LCMXO2-640HC/.spreadsheet_view.ini @@ -0,0 +1,76 @@ +[General] +pin_sort_type=0 +pin_sort_ascending=true +sig_sort_type=0 +sig_sort_ascending=true +active_Sheet=Port Assignments + +[Port%20Assignments] +Name="164,0" +Group%20By="84,1" +Pin="50,2" +BANK="62,3" +BANK_VCC="90,4" +VREF="60,5" +IO_TYPE="147,6" +PULLMODE="97,7" +DRIVE="67,8" +SLEWRATE="92,9" +CLAMP="71,10" +OPENDRAIN="97,11" +DIFFRESISTOR="114,12" +DIFFDRIVE="92,13" +HYSTERESIS="101,14" +Outload%20%28pF%29="103,15" +MaxSkew="87,16" +Clock%20Load%20Only="121,17" +SwitchingID="100,18" +Ground%20plane%20PCB%20noise%20%28mV%29="196,19" +Power%20plane%20PCB%20noise%20%28mV%29="190,20" +SSO%20Allowance%28%25%29="138,21" +sort_columns="Name,Ascending" + +[Pin%20Assignments] +Pin="90,0" +Pad%20Name="89,1" +Dual%20Function="158,2" +Polarity="77,3" +BANK="0,4" +BANK_VCC="90,5" +IO_TYPE="147,6" +Signal%20Name="123,7" +Signal%20Type="115,8" +sort_columns="Pin,Ascending" + +[Clock%20Resource] +Clock%20Type="100,ELLIPSIS" +Clock%20Name="100,ELLIPSIS" +Selection="100,ELLIPSIS" + +[Global%20Preferences] +Preference%20Name="231,ELLIPSIS" +Preference%20Value="236,ELLIPSIS" + +[Cell%20Mapping] +Type="100,ELLIPSIS" +Name="100,ELLIPSIS" +Din\Dout="100,ELLIPSIS" +PIO%20Register="100,ELLIPSIS" + +[Route%20Priority] +Type="100,ELLIPSIS" +Name="100,ELLIPSIS" +Prioritize="100,ELLIPSIS" + +[Timing%20Preferences] +Preference%20Name="129,ELLIPSIS" +Preference%20Value="105,ELLIPSIS" +Preference%20Unit="98,ELLIPSIS" + +[Group] +Group%20Type\Name="134,ELLIPSIS" +Value="39,ELLIPSIS" + +[Misc%20Preferences] +Preference%20Name="117,ELLIPSIS" +Preference%20Value="105,ELLIPSIS" diff --git a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ccl b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ccl new file mode 100644 index 0000000..dcf391b --- /dev/null +++ b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ccl @@ -0,0 +1 @@ +VERSION=20110520 diff --git a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf new file mode 100644 index 0000000..49c9e13 --- /dev/null +++ b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf new file mode 100644 index 0000000..63de512 --- /dev/null +++ b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf @@ -0,0 +1,68 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +LOCATE COMP "CROW[0]" SITE "10" ; +LOCATE COMP "CROW[1]" SITE "16" ; +LOCATE COMP "PHI2" SITE "8" ; +LOCATE COMP "RCLK" SITE "62" ; +LOCATE COMP "nCCAS" SITE "9" ; +LOCATE COMP "nCRAS" SITE "17" ; +LOCATE COMP "Din[0]" SITE "3" ; +LOCATE COMP "Din[6]" SITE "2" ; +LOCATE COMP "Din[7]" SITE "1" ; +LOCATE COMP "Din[4]" SITE "99" ; +LOCATE COMP "Din[5]" SITE "98" ; +LOCATE COMP "Din[3]" SITE "97" ; +LOCATE COMP "Din[1]" SITE "96" ; +LOCATE COMP "Din[2]" SITE "88" ; +LOCATE COMP "MAin[0]" SITE "14" ; +LOCATE COMP "MAin[1]" SITE "12" ; +LOCATE COMP "MAin[2]" SITE "13" ; +LOCATE COMP "MAin[3]" SITE "21" ; +LOCATE COMP "MAin[4]" SITE "20" ; +LOCATE COMP "MAin[5]" SITE "19" ; +LOCATE COMP "MAin[6]" SITE "24" ; +LOCATE COMP "MAin[7]" SITE "18" ; +LOCATE COMP "MAin[8]" SITE "25" ; +LOCATE COMP "MAin[9]" SITE "32" ; +LOCATE COMP "UFMSDO" SITE "27" ; +LOCATE COMP "nFWE" SITE "28" ; +LOCATE COMP "Dout[0]" SITE "76" ; +LOCATE COMP "Dout[1]" SITE "86" ; +LOCATE COMP "Dout[2]" SITE "87" ; +LOCATE COMP "Dout[3]" SITE "85" ; +LOCATE COMP "Dout[4]" SITE "83" ; +LOCATE COMP "Dout[5]" SITE "84" ; +LOCATE COMP "Dout[6]" SITE "78" ; +LOCATE COMP "Dout[7]" SITE "82" ; +LOCATE COMP "LED" SITE "34" ; +LOCATE COMP "RA[0]" SITE "66" ; +LOCATE COMP "RA[1]" SITE "67" ; +LOCATE COMP "RA[2]" SITE "69" ; +LOCATE COMP "RA[3]" SITE "71" ; +LOCATE COMP "RA[4]" SITE "74" ; +LOCATE COMP "RA[5]" SITE "70" ; +LOCATE COMP "RA[6]" SITE "68" ; +LOCATE COMP "RA[7]" SITE "75" ; +LOCATE COMP "RA[8]" SITE "65" ; +LOCATE COMP "RA[9]" SITE "63" ; +LOCATE COMP "RA[10]" SITE "64" ; +LOCATE COMP "RA[11]" SITE "59" ; +LOCATE COMP "RBA[0]" SITE "58" ; +LOCATE COMP "RBA[1]" SITE "60" ; +LOCATE COMP "RCKE" SITE "53" ; +LOCATE COMP "RDQMH" SITE "51" ; +LOCATE COMP "RDQML" SITE "48" ; +LOCATE COMP "UFMCLK" SITE "29" ; +LOCATE COMP "UFMSDI" SITE "30" ; +LOCATE COMP "nRCAS" SITE "52" ; +LOCATE COMP "nRCS" SITE "57" ; +LOCATE COMP "nRRAS" SITE "54" ; +LOCATE COMP "nRWE" SITE "49" ; +LOCATE COMP "RD[0]" SITE "36" ; +LOCATE COMP "RD[1]" SITE "37" ; +LOCATE COMP "RD[2]" SITE "38" ; +LOCATE COMP "RD[3]" SITE "39" ; +LOCATE COMP "RD[4]" SITE "40" ; +LOCATE COMP "RD[5]" SITE "41" ; +LOCATE COMP "RD[6]" SITE "42" ; +LOCATE COMP "RD[7]" SITE "43" ; diff --git a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC1.sty b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC1.sty new file mode 100644 index 0000000..feec63c --- /dev/null +++ b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC1.sty @@ -0,0 +1,205 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcl.html b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcl.html new file mode 100644 index 0000000..b1bb2c0 --- /dev/null +++ b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcl.html @@ -0,0 +1,82 @@ + +Lattice TCL Log + + +
    pn230815045824
+#Start recording tcl command: 8/15/2023 04:58:13
+#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
+D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC
+RAM2GS_LCMXO2_1200HC
+#Start recording tcl command: 8/15/2023 04:58:24
+#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC; Project name: RAM2GS_LCMXO2_1200HC
+prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
+prj_project saveas -name "RAM2GS_LCMXO2_1200HC" -dir "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC"
+#Stop recording: 8/15/2023 04:58:24
+
+
+
+pn230815050055
+#Start recording tcl command: 8/15/2023 05:00:44
+#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
+prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
+#Stop recording: 8/15/2023 05:00:55
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn230815045824.tcr b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn230815045824.tcr new file mode 100644 index 0000000..a9d6771 --- /dev/null +++ b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn230815045824.tcr @@ -0,0 +1,9 @@ +#Start recording tcl command: 8/15/2023 04:58:13 +#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC +D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC +RAM2GS_LCMXO2_1200HC +#Start recording tcl command: 8/15/2023 04:58:24 +#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC; Project name: RAM2GS_LCMXO2_1200HC +prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf" +prj_project saveas -name "RAM2GS_LCMXO2_1200HC" -dir "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC" +#Stop recording: 8/15/2023 04:58:24 diff --git a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn230815050055.tcr b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn230815050055.tcr new file mode 100644 index 0000000..4ca6762 --- /dev/null +++ b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn230815050055.tcr @@ -0,0 +1,4 @@ +#Start recording tcl command: 8/15/2023 05:00:44 +#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC +prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf" +#Stop recording: 8/15/2023 05:00:55 diff --git a/CPLD/LCMXO2-640HC/hdlparser.log b/CPLD/LCMXO2-640HC/hdlparser.log new file mode 100644 index 0000000..fa8401f --- /dev/null +++ b/CPLD/LCMXO2-640HC/hdlparser.log @@ -0,0 +1,3 @@ +-- all messages logged in file hdlparser.log +-- Analyzing Verilog file 'C:/lscc/diamond/3.12/cae_library/synthesis/verilog/machxo2.v' (VERI-1482) +-- Analyzing Verilog file 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v' (VERI-1482) diff --git a/CPLD/LCMXO2-640HC/impl1/.build_status b/CPLD/LCMXO2-640HC/impl1/.build_status new file mode 100644 index 0000000..96c9059 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/.build_status @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb b/CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb new file mode 100644 index 0000000000000000000000000000000000000000..049dfbef5444309286d0db9105f390f910f11764 GIT binary patch literal 67964 zcmd6Q`F~u;apwatgNvLQfPhSh5y?3KW(L?z3{cEU3C9}8W@0I}wVSihR955j#5F_Qj@B6-!&GA=czu!Kqdj|gO0>jVl{4mv3 zUGG(Qb$3;DzkdBLeDM6(WRkp+;8***?>Ik}`tpbV^vRKtx166&z59vBo+Le~%_hBM z{NSbLjrDy4K%HsG-zU0t&_<@JXXnq)RPURu@SEX~IYn5aOGTt*zdB*gZ!R=BnF_BxCoSo@H_* z_3-0g{Z#rRPrvZo({9y&iBJBB*CwP{kQ>1mrBSkqB2 z;Ie<6;JeH*IKQ(u8)f8p&)7Q4|9BgkLC>-s9OHI5>%4Wx>ew4-KuA_e$5nVw7zar4ae7Td=1CfuzX|r z`8jjRSk5I!>o?qeY-;S(7o4%2Gd{Vn_MoNSGpmweC;Y!?#j*KWDq-JspR%dCqtz`fRrlAVb7$vfbiqcGRAYPnHB-oRUS`xqMp0%oMMgnpw0%aZvA3;n zi?+|rSv92Uf}Ho{rYEP`K0S8URC-jE5Pu^ls;U#5k=7@s#rv zZ~DamZBN!G)cb}z7qBhpp^xhTvdtf;q@qc7by9W}MRZ;aYV za?i!Jv*)W9A2@$*zB)U9W`1qq^Q&hs8pgNW+26ZeyYu?(JFoA-&|lx!-}>>|-W`?e z`_xqRo>OycvPXrKxSpw(uWj!iR?*R9N)_hf`I%W$iV4_dfhwx%%IEGqGaCv%Q4MLa z=}3` z4F>5{b!P3#^#ZIDVBG*~2Us(} z>H*dWu$@{xD2v2eL0&JwIsw)Vuy%ko1FRlk4T()u^3~j2b;fptdZ9s)yq2n_8ZFtmrj&>jLqdk75eAuzOu$EbsRr~`>Y2NH!2Bnll! z6grS7bRbdaK%me;-IoG=Qex-_A`ksQVCV+|Lq8B0`hmdE4+MsOATaa;k4>O;9z5my zK`um5?l4!P>HIyj`pVGUrgMkT^Q(p*v)FV_ASd$GbJdFrs|#zcBqwrxq}25-({m6? zU%&3s=`#!G&2V8>R2b(=>^J8FHm-RfwI#Jl$~Cn?DPU< zr}rp3{ij@UX@mrZPA@QYdV!(S3k;oJVCeJ$L#G!QI=#Tq={=@8y)PPdkQXRBy+GON z1h?&;;u>hbjN#Fy((7ru>h?l>c#<@;?q!{>Nd;|2RzfAB!3Pb1L*d4%Pn0 zq1yjARQn%?YX9Re+q1yjARQn%?YX9RiNRQ|_d z%Ktb_`5%WV|Kl*_e;lU#kHw7tu|=EE{>Py(A@DyA%>}6PKPqp4{~1K5|FQQ{{>LK1 z|2UHOKbA!Qqsy)Rk4-E8qnV8Vv54_M4rS2wR#ODHBkg}&uJ%6;)&9q!+W$CI`yYpD z|Km{Ye=Mr~k1Z}c{ij?-#+CnZdCLDdO!*&&DgWaz<$oNe{Ex$w|8bb|KNd6o#}>`_ zABSrH<52B?9IE|~L$&{LsP;b&)&9q#+W**6u+s-RkeKp6j#K#`hbjN#Fy((7ru>h? zl>c#<@;?@{{>S3p|CCqnkEZpK(&v9V2cJGTbpG@8TzH=<7dZWV@IJesIaP`Yg_ux` z3Hg|iiwTRxNXkk~sKkWjm{5)hrI=8N3B{O@j|sV$u$Yfa8WSopVL2w0V?rq=6kgO0BI%R!R`Gl@bJPr367+DM8RyN)WV_5(I6f1VLLVLC{u85VVyN1Z|}R zL0c(7&{j$iw3QMBZKVW3TPZ6$=e&-*Tf|!@`WnxfM7Y1>nAN1`?yy6 zNtJ%mazCluPb&433jL&FKPlf&%Jq{L^ZljoCn3g-HGw!cCLzv?Nr?3#Qnub!=BT#+ zn$UH&F_5~`9K^djklGqZ?G2=M22#5NsqKN(=0IwFAhj`&x}!~Iq=(&s)Yd?1Zy?o} z;^@A{Xh&3I-Xp4U1QFG^jEHKSOGwRVFH~K7P>h|7_Er&5d$owDyo?v1UPcSiwCzzPT6HH9v2_`1- z1QU~Zf{95y!NeqzKsjIwtYBj!8VO zV-knkIl1YAu4g^y31&|231&|231&|231&|231&|231&|231&|231&|231&|231&|2 z31&|231&|231&|231&|231&|23A$$qeV949=P+|}PcUJV*;ouMgSGd5BG%{oiCDw$ zCt~i`PsALtpNP3+KM`}ze&Wg?BIdCDoS5tO6EP?5Ct~j0PsAL%k2ra4W3z_G%%3zZ ztzu=nCJ2wO7NOlDA@+@-_uDl$V3_cFY`Rh7N~@&Q`zXymO1qEJ?W1)1D7~1%VA_RN zI+%7Sqi%=jiHNh(6KW#jP)l5KPQ0 zTomXemTwxh=JsuKHSu<>Bi|5=VE5S2E&i=ebR25d+TR(q(j?*#mp2&%6 zNQ<8yjsN(@Ha9{XvMn^7q&ARE3E@;t?6*vR0YvBt6P|qL1u`-B;JJIT`B4?nzX5`` zOs?oTpB@!OCt<% zX#^@RjZns=5$w1$!XcMNz~s_cX>)0;#kq7-q}w9h73q#hH)^k~JH3f?Q>5D>-4*GM zNcTj#CDOYhz2nnqxT*(j7fiv5ibD7_ET^NxX1X-2rAxz3x-=}LOSeRNSEP4*nuS=i zg_ywl&AFM`RiliFa|;2wuqx592k)6BV>JBM22vk%3m14vNnM6bb`xe*#fY1vrMsu-ZuZ>^}ok@;fw{NtJVJn@@&sE=QlX;&k`eeZ;OFmil$z`9c_~eRDF1jSg z*{6&+jx(3WICE)?Gnd9Vb7_n-m&Q1AX^b-9%b$8_{mu^@X8Ln* zHD~88zD3;}J4x}vltaeunZ0P}W2^VMEirF$C=IxB=z#<9m|#4*mh|p4hos9fgyB+f)J~NwK_~2eCg8E z*}qRPS%b{*_JYuNd#L9#+}Gu+-blf3=L?Hf_)J)!URSR?)n zxA!Z^R`+=C=j?rF*UroC7}H`QN-?1v z5o`+~D#VK&;oHfc5UXemn|2S=Pwh*2&(!Yvh6`R=BHa_|j!1V!x-HU8k*7|& zR-Ci`9>!20SWa{~sh#!hb<<)fo=>+#x+l^dk?x9gTcn#JT^H$wNbj!iX;okoV@sra zBHa<`u1L2ln|rqAc-?H@r3X$oQqA=PH48yJld6k! z!>32DYgOXSTo=8JZh4vwb5f0K;$9-%6zOY&i*Zeq^qQ~1*eO>rByDve$ZNSS(oK6S?Eige?e?>%*qZi;kUq`M;B5$T>tw?ukZq<4H8UjLNq&gkd@DGCIt z@MEto(oK6S?E`n2jv%DdjY8NEs?2z~bB^yx!irM=(Jg36{SCa8zy3+<2d2(1z=(<~ChlEWo0~a%+T1aCtN+C8 zx%*ca?wNTIr8D_r<~@Gn&enl{MR7C0wk0-k{w&ITZo%ARVl_Y~n+JR7@3-^_!7jsg zh>s%^sxudlV+;rkL&9U}1yRz;)&{nb`OL{)gm)sm8{zE;Z$@}M!W$9Z<%*e*-;VHR zgsZ)Ug1-^wK_C)P~*CV_c;q3_TMtCQ}dlB9WaW=|z)A)!`@0mS|RU&)- z1tQPAo2tDKlx*%FeDbz6_mkJI-??Sibg-5*uG`x3>YiY*wCW}nQC-L&3aBx5V>5b% zR}lKf*nP8yzQUWr!3f6YDjV<9V;E3M9$uZn+!gna3ZY+-ucB!sQbzG|FQZ1Vr%Xv?h_sOD97F^ObShzNks++cp$j!mz_CWHeKQY9g zG19c*+i2URx-Qjmsh&%_!J(p_Pl)8m77<=)YR1o4ZI)-`rVdE21UOS8TldI|4{+(N!f!B{n zv552<*47X8{8NV17{cR!&KjI!J1O1@d(1iy)&oJthq>Gf^HngPne;u&+Eb2 z5(ZC`d(~)K!~h7;Z|~hXFc}I!jVG$7PtV~%gm4lW(&Czq-@M5q3=Y%h_#ssl@y6t> zo6zp|_Uoq1<6A$rwY9H@M0i93N-aE)Ej7+MioJy(#N{2EJ=|N21rb?_(TmZLKgq>Q zy@q$Tglm|r2|}OLQ)dpJM}CO+9H;lZrq0?4E!;Q`S=iSZaAD&co1Zpp3PYUa^3wAQ z51z8qgo)fd;y;h(L$ny8g%B-;XgNfeL$ng2xp}N=Nx1=vRV|rY2+>lAmP2$oL@Obh zJL~U^$R!`5#SkroXemU?A-Wu*l>i;zL;Pl%0FM*Z=EetRP5trY>Kyh@KA<`cBH#`1 z)_o{ArK*tkQTUXqq9iC4NP<$4Bq$Y1f>N<0VDWHfP7+iT3Bu$ax{)gvf=-sR5tlO; zms1i{IVC}rQxa4;B|()_5>z=QL6uVwR5@L_P|hfLos5IqIQWf&<2ZPZgX=i>j)U{= z-oBp-pgipeZ$@}M!W$tzzPI(7)jGQHS*#UXofE}e%cH5yz0EtSU!jvBM0e}7sm%?O z0c*hnemq7Kqp{G$Oq@lxoj-5=#KgJP*;R|8*WTK?b+EZ{+j@)17SJ04??reg!n+aP zj__uL*CV_U;#21q=2y?&XA20m?`<6H$pURi9H$zdTR6KqA6&3^un}A!aaH4&HxGOb zp?a?nw8XqeLq$&RVY5MVvuV%go4&QRx4wNKD3dY1A@fHPUV(##f-53?L*N6%*Zaf^ ziV`nzig&mZ?*Ud1)fnXei_F7o` zd$H7iZr&3n7S7?MGb5aPZT9V*F()=Z97S~R`Pox4#tJF122wBG-n@2Le1*Y3e{SJk zyNr`Q>ku#SM0IWr1|kp{(_*36G<0j@Gl`vmSl-s?bpnDN>P1i2Zr)tSju;UqMWk48 z`t<3U)z1)~k8h|u8nITVh+G%u5U5J6#!5DP+)rX z5vWd${TCYA|f3Di=^}ToA|Uq#^G(Rzi#i$1v;Qs zKO5Tz9!oVh+=B1~^zq`=8T(e@#O0L`t%T@uh?YaN6rzO?Erw`5L~|jUzx3eQwOLhs zY$Cawlj!)Htv4RMVi#A&-|PigC&0P^)()^{fYk%6Auu+;tZoe~z@up#f;PLZHI9WC zXk51?M)jW8_efGx*WzFib(SgXG@k8p!`6l!=nq{k4jd-W6bll6}kKmOrH z=Go^y@pQ(dpJ{(z^XkVk_2!Guf4u$l3(sbr?_O;@`}~V9WG+0LD`BJS+h902RqSR`G8w!Wl zS91_4`s(!Vm0GP)@6`^j!>wpBs%XzuG}|7oq(UUA<0NH@*xfojl{UM9N?U_eT9PX54Y#7O#X&D^x{797 z!DCx5MCGE?+7y{xf2R{Nm9(RaTo#Yt*Mo z7>I=i9BigA)Dg)&!G1(eH@r@Z*m*s~ZrYJ@vh_haT^2gc?he;)tVDhz=lw=@XSkvk zLs8Q^UZ**1Rv(^D8@p1cIqc>f;GrsBsi|yzxHZj(H9b-BO3f6o8Gm?HZSMqC#k)ZR zs=DH@`a4yskMl=%!FEVc;&6Xv*NgK{h<#==i?b15#vXTTBLvn zsT2xyAuB7zBl-}&P~weyu98DJo^LjfB6b1uxWyAzCV4s9aji6^V zpL+j$(Vh6;uC=dZ@_1usc(UrPKvuW*#fT!c#QGH-M^57H0`-9lDtI)rD81&;6uc97 z&)l+9aDLVl1cTNUWSsA0dPNK=R^ZD{zMUtV2(zC!Sl{HUowCi(I=V78{K}Nkvd=&F%!glGc=qGAUGWNvD8{1ncf;#of!~{{*D+yw_^GF^yyqS7 zKX~Lln?@lhtSiZQw!!z*Ttn1q(8!zh_N%S>8y$e7H3yBDXpVcZ#_&yhW^nYvXrL7ygk9zIH$~x_*GFnklcgz*@wB+U75!bDAE3|EqxZ&^uGIpeI>O!MKTJ=c8W85|7QKbFcXMfRXd>4-|@2`FML zO*R@ho4LNepIMOskv7tu`m1;#)9y8oW~8&bK~yv^BQU0$wdR$~N;m^Wk6F2dj&`&z zn%xa&pv6M<6VEq{S8(ncOAJEGdUj*&;}_CLblzw->d(Bn^TzJZ5o@kzV9q>tU>@sG za<;=)xrgiu%kX`|6{sGK$dr7~O}URSc+ z81I#O1!o&N>bK)ax&K!8)m|N1?jB9QxtyM#*nxBpQ0x9n-ua0P1iAi zZf)^-V5S_%Q{hJMjqYyqnKzrLZ2PFgh_AzYfm2%Ni>^B(8WGxV>)6|9`=QH~{Dorv zQu&D1B3IDU1FPs0I@T%W@SG}xMUQ^(7N^M>FL?{`}b1xD)zwC{~9RrU)2rzHKvQIh1W^lRIum(Fun1bPpk= zeg>V%OWXXmH{lL?Z?t!hHe|E)z%;9lgcal*mRK?+Dd(Zf=&XhOrR9|)`hae~pi(tg zSzq!}>BtR>bw17mE)%i;=_cd!B|`|xp}vLc2I`Y&fh-UgPgW^!^h zWoW&n5v;0Ax6oVk9t9hLcD!;&GxGn61C~%q;eV7<(i3ay$w%IW@<=?C?n9=bZ9!?>kS;yX(lgf|;LWkh~GRo*#q4#PBqv;$>%f6g+Z1am-Vqfa&+Y^n!FAwf8=J@ZQHZpL}fp(M%v$_Ru`3`SL9Q0JxxERxa@B5D0~u65^o$_uN|1K z)e5TH3#&Vntp#{Y5d=*+pf-|G%ea-{*SQte8P7Cjo$=_%HSuV6H#F-*Y2ua8q)%d( ziY&m6D8P8OH(=GE*L}6oeWTqyY9Ct;R}J2RN&4dtKcSWl@ChzhmnNRr>}L?wh;coP zs%H@~ia|YzT{EiYCskl+4d_rhRz^j@)_P9wVuII}6TC*tH#1^|psIH1`na zNAsdqt%fI%V}>w@}40r+tXPXvFkmM2Rj$uwxm|I~)yLXo9Fk+4o(n2IIj( zxBkX1g0>?Chj@e_O^mYd#cH9*AiN^i(T38yv#oG3O}#U4-|Cs_>U<^_EUOG-=w=(? znu^-CucaBS?+6WJ_uyTy9{JFEoKXAubs4gqyC4sb;H9%Xq4t3Wb;hnr*Q-Xe-Qjlm zQrP8ln6~@Q?raLyZe0<^GnM|prG?p!UR*lHylYV4Qc)edIQ)*?3_G^kerG!N^6;hg zLTMPR)oRelD2~(cB(^REeri}&doePjWn)GgcP9|wi$5X`oG58=nMK)uj%&2Dm@0_? zJKJ_!@6^-JqFf_5wyb8bG@!z}Zmnkn+qP&!>k{xVLbPk^F2o;|DE{E~ToZrn-UV?h zkvP6yVZ)ukG->~H+y}kOk$u8953PN|KEJD(vTWaDKD@~yHWgjTOq~jtO<1Sj5v>XL z6V&&(oeK{nf>qwra;2MTtN<te9!+peS@ zcRyPWH;{#xD8e1goLbA22CY~hR~nu>$|mM~ObIIoZqE3a<1P|sF+^m4(lcQF?{-3C zmyXkMD!UuJu3&YHw^g~%3ESk4_81sjs{$R5;~m27{nxNRaFA;~wzS1a8eZgsG#j-B z^=%Av?#C_xwq(dYHI5hjSl{~Hk%s*pfix@{`}!h`ckMfgi1n^$94lHu39ycc5@hr% zB+&}Wah03xsVdkNlySV3Mp+fPVtCx?JvL9ukz*#Gc&=joomvWCl*aeiBJqe?4AwJs zVf;B{{Vp=ok@4W&H7xw!-3c4>QP^0pll{9Rt{91fEf&jFc*^f;Jc$QTvMa0ot;g7{ zm@9^JKeeIOZeLr0len5~-kq_7NmVd*5Hr$N;AsN;gLSvoB^=ih%yMKh z$`=-~JFk2+AD8U~CPVFw;8yIbRZN@J&WP$_m4}36mgSVIHk>+U@gP)K4=yXSibl!U zsP2@U$}Gy5)w%fNZe_-5kSKuIUu@s=!v5ld>}5lfjH#ZGtU`4z!pYuNskm8#Pz9bQ zMvKD7JV0b6S`@~P7r!X%_lSxjq%h8djUmHYUMPeUn0tWwqL>{!SF@eFBfK06&sBoP zuuahl^>7#F$AxHq%%dyJ{J47;#FZj(JU~K=Gvg3147qWLg{8YtgvF=`2*gYgGML7R zsp3$Ui17?pj68KdfUa+5WvHfgH!!UWIvm2A^DUfj!N=pZo!X;U)^B9W(y~5udAW1} zuh^^{)u3Y^kEoql++RkpZ9DLeXik{bp;mckP?d4WOI+nju<&oJ$FVncVrYu0<3yrT zb$*VAtGX8)r?@dh92(RJqA_dRk6Vx&rHB=RlTG``9&gxXa#8$!JpbJY;&0Q*U@>Bi zFW(i7_d<;qpm7|37-*bNL!8Djl?y}g;lvTSQWSw#bRdC!NkKR|Bx%@+Et_{@*+gdf zp|)&&P|LzN$1Ph5%}42Y{R#UY#TYXE3HCUWs$IhrryrtmckYV17bA7!nFFK5Y~!wk z-FTfKXk0vUP+@mrsEykm)VNr0iPW4a4z+QyxwpS@F_(&@n#SdeJEC#xcSYU#NZpvK ztHy2K6=}st8fNOMahHeMxV=G*i{-6I%^950=VKeJ#2jzrV%vIu<6>GKNi~gIl8u|f z%28k_hZWD`9n)Yi!7i(PL%VlJ+)5-4hS@K~Oz}Cn>(8k2aA#4KXcmP%A9m`ZmfZ?+ z{(9_ZF4zYq8rwWZ?3kx5Q``+JYTCIAA$vIr*?Ab8eTa7##4ShScvg{|r1;}+M>BZ9 zCx_K?{z55#DYtyY1rmOp*l*Uy0fv=owNicd!=J!QqA$!nfwdkUzH86h9nE$E!-a7E zSmJZ#&|+bU9`cv_hLbl98W3SW$b*ZYL~W7)CoUmvSuo_suX`ItkE`;o=E z$#f$UZV!Qnl?w#F4W}c#y7NZ!h{q%3@}b-bS{Iy%qsO;6ZXVVxko(Z(Vv$c@Dy5?Z z7rA06cuE^q?BlSa-P!gqYr_>?h(v3fDnz@3^kLK@(JT22%lS*iBQ8EK1%91vj7`5T)~TxVC^)$VEai2*e`ulh_heE?AVBor2U%I4$}*^pO1k3 z8m{1cBv?C3FW7#n0tRfjf{T%0?I^uq`&kT_ui*+VM1r-G^n&dtIAFYnE4UO1)(+AO zwx9ce=^C!!awJ$gM=RKUS_FnGl8f_uco@o2eH3<#2A!H=7!M54hRc1%1a@nn-11T7 z;<%MQxje?l$~B)%f!T`WE|xBoOGmHo${@KAW(>9aJPXWLBp8R<7K%p~yci0eqGM9h zoMiJY7}za+euT4Ii-ilN!qFvTqmWd!kql`@vitB13|AyMUt}n-eAG|?Xa4m`R?>`Q z_mvx1u0ZnJ@Cp<{zFy~O??7SWRKH*)ObZrY)Pd;=B&#SF1FCSu6(t;q6^NeJ1BxH; zF|z&ldtki=$}SyMHjY1(`c|^FI3wGCEeHl|pzQKdWtRuY*5b5m_iZAWut0M4GPdxp zTsq=uPB{RRQVMo*swtGLzfW{VDYeg#IrVWJar&?S_gf6>TiYnZ!W=* z4OjR|BwPo6Qn>%Z6O7q#g)c_Jb?_&J`|nBd^>MkK=-6t{>9a)ayQR}Q0F=W0*Q;RC zhATWD3D-fO6z;#31*zaGv;%jj*aFJ|;#W3y5M_m?P3}sL0XF@MtHIIbEr|Dqc^oO@x zxOPm@IsH{IYu={x;~*j0eFqQ5ZMdTIk!bxSNQibH-GgZxuIOSUT0aC5qTLt%VAzH$ zx)6!h&wqqy_c=kBwc&~`MWXeiA0gU(yAVcgxT4FEXuVV>M7s|q!lVsX^l~IxFHSnq z{;Q0zXMyD7exsoh3D$Ekd;(HiGyerh*s?(Iu}>;r87LXwo79rs=O$su0>NtSd-sjr z5fA&xErxPcbj(j%8nO1vmM~($ehDMCe&pkq!|f7EEM;l2;v^N6_C2 z_+n1Nqq;Nu29Vc?Snezk$`Gw?$Oew~3|Z{Rl=_)P|~d@RQ|8~7~- zeyf4sZs316@H-6rP6NNo!0$Hje;D{Z27cJUrwx3@z~>D7UIV|+z!wbsp9WHoEZ+?S zZyLA@n2hVwlab;t^?CSXee!^;AN5bU#CgADnr}Dh<066aH+B(!lvw~|9nS%>j!Bx| zbkU#xO_CYjnkpn4RagSFqIg*zI4|SnRL$oCQWZ;pR0W|e3L!tQ{VX8wcNK6Ekg8yj zS>+|bO+e-oCOI7SeXjc4^Q+IjFpIN|^fzXcB+I^LZ^(l2#w-va3seMTfr#6Ju}vz# zSpXK8f+^@4AS*_JWv0zJrjh!$#!M!ixz0xcodkpVI?NH6U zXC9CjQ46YPq}8W2fblm+rE)+}8N7_G`Hco=$0D7#A*7NCsa!(dmU>{T^16>2_`HEH z0xp40Wi#Kx9{|qlY~84I>WPqiEx_ai_dkYp9Ayt?VLscyBwfbCaH}t+PL^p2*-B41 zm5zhJeM8!)oSlH`(LCH167oeRmXo zcYpIy5cyMuW{=_B2$K{K|6>+@W7I#X91Vm^fE;Z}nje6)gL0H2Iat`bDtn4!1ZVS_ zuP&S6O_NADguEkrtdh40$e%LUHkVKje%sBJT_Ksh<*NYmfE?VE`?6wJ-=ze`pDI1s zs7+?)4NRu_VDy&yE(1vXDLt@fv3!Jd74Dnc81+wr^jo0Q1b&TyUu)p|4SdSL4;aY% zkpJ5NS!Ak+_?CgU41C4Fx`7P?n}A8`T{YJpN>-4Cz~>G8I3P_AM+xb?O_E;0TDR-aUjz!he{iq&!piY@q*2qY@pk6VhjR*(`=1D0S7Di5kP8}-GD5MHTu>G(D;-7G9bJ#PDFrlu^+TI!+;~064Xe>FcA4^ z${?NP{|*D623!J8!^MLCB49GjZ~F!wUX`BL@ZN+8j;U84GJ77n#p@^5oTSO zfV5zQG^~WYkdRiMW0X&{km65ikNGUbFEAe;c8IK}G9e6kXvyhOSds4nWWzA@Nm8x) zj=LkfDOJfL6T??#c z5rlO>4ogDfG!?`NiPK~dSEeJ44H|B=Pf_fbBYVj}vVA*nYJkBY#}Y?B#}G$9=^Xv! z80|=WeZmWz4Z_8{8c^l&PHoTm-*OyloBO~%SvS}rFc`{b=hJflPk?Pl(1)s@Y zLL#k%%A9gv`~Lb_PikzqsLK!jB|{QsQ(t_NuRDgVr2NM_!QJ&(I~SMttD8qdVSXq03&Eg_3e!O1Mokvb&jzq`~L_R{|Ex=@K+1+f4H{-=D4qGA*$eXgal1|8*67r^myjk8r;_9aKhFD_( z%Abk?{sDYTKzLt5t35*2jrV6~`WCp$BFY_*GywT!A4hDhjaLj&{*{SZXbAU>7Eb-Tx zT*9`&I|g>2oj2L6zNDv*KZxb+&B^Edh={wR%7e*`d5r8fH{$iPz5=ab=A$e>go z`g%HA=Km7&)5~~1A83UZpIRYIQV8(&0r^umCzTifICD?(Yvi}g$GpgbpVBP71n)tZ zjO&kmF%v&^7t+}~RID^sUUUUum-{MY(mN5d00%ZyQ$B!Hwk%;Dkc$C{igfuP1Zn=1 zqW%my^b(AT5*3MJyC-w;Q>9=A>+-r{CQZ*1~LjE&d`OBk_Z`% z5Go1NJT@%|e{i2&txYck>glp zVh-&4h-&GtHP;df-|hke)!&%Oen!X<#nw(vawi&f%S}YU`BS%i2DvN_VKRfm4hFTc z>Y(i4Y^!fEkUAo+uAJojNZy-Pl{qvPzYdtpRSpk%Samzpo+5L)6i-H<2ASm~Oi~@u zew4%pSrU+~&A~&MqF;t*Z}wAPZ4_;Y}4Q??~XrX9I;;Be_;mNdZ%J`OT( zN66c=si+Q`B0@II5+G+5gq(aO=@k(bjj>6Xod+a4r4vtP@b=oEKB9UPIoKz@j-08w z&^ue{F;JHbWHH#2cwgO0P0y{o7P(moLXLOEl`h7u^Hs=Z>yQnLRB<-R%w{8E#uqjo zGue3R+OdMqWbH|0Q zVUjogb8{n(ggkJL1VSp80@>r206z&xfrO;j0h5V*{|)~Z8F}Q{8`{?5g{0dXSjZA` zXuZN4rgO42Spl-K&vGOtWWt;B-U%eKjxP1Uoz`|R>P=^Iw4HP+dDhRRei@Dx2%9@QZTwhnAhTfZ6W{WRvL#i<=N`neUW>$e*&_-wH04ijZd6@1G_I z`y6wq#or{ycr$1>=Cd`Z72R&lu-%kd{v*S|(Lhd)1}faPqi#PORxivlYhv5)XThJ0 zBUe0`V2}Bzxu5Ra^}g$E-~KsXk6mV5c`3L)pu$EwOz3--!1W9ubx%4R^0MtPs+ZeL z!emlKlsFIzY5vs1KaMu)UU7`&oUCyg>2+kXL8wrwf$>MI_GK=*XiY{VtVf*$9__b8>?R0r4b8g;ERx$U{d@sDgs=MxR3K$Y)phdB6lK z74E$Xph`nG4a2V*2KV}dWw4(1*T|4A$U;*^)|T78OTWrzQty8B?bndvPxVROhN_~z z@rWgkUexe@8F|zX?adM(M`wah1|K@^IR5kC;qYdp!g0r8{VX6A&KnS_;hkO)?W5|> zY_`3UGwR1a8-s41d4$Ofj^sErMrFrijQSyR!qECYq&fl1#v2jl0a-bgN!fxiZqitDRyn;3VAF9h^De52=^_s0 z493nbvZ+j!JyvuhLm8nRWag2nMqL_jaJ#29YPS3YvX_ue$W|vCaWzoJyM4W*fqa&f z^{3sCy@z(g_8yg=#!_M^?yJr138`y}A!I4xMkG7$Mz(^1tRdM66+7&ulumouH2fb` zx2s^sUZ5y;={(p>Hn!EdY^s@^lyy_th#=(MSsK=zI&yapHO=)JUar<{(v`Rm(@3xp zm9aqd_Qj99z19u97-yrbo#L43e1_Q;IoOkFfUubA=TGX{AJ!C_E!S$S32hQ1CuN(`#kkpNJ$Q3kl_Xt>qdWF!-do8Y^^c-hZ5l)NHyiVK zx$KQJPxSOkZfZ9w6?0iC!eqP`)QP2Lot6OE!i*T>I&&nk*eXA@BkoSwHp)Q0#u-yogxx!~&2I8<`pH|E#aTdH=^#qYWbxZbm-ct4aG)~j>o$iZ3 zrorH(pXLk;aFt+ulgMjTX1aopQw7;yXR-;C6UDx#s;bjpMJ7x6&19NeIkZa3NqodG z(-`t1)q$qmxuc-)r}`jSsBaZ3PWLbOvdumK9@+<0_mhu2{M1ud-t&(4ANV*)O)H)P z7kkt<8K|sDs?qknhxcL&vVSPQm1;)0&zW38nB}-n)BUp`rcXd>u1%~IHtzy znc1x3l7Y#nH-XHfVdtHd8d7ahEOxsa$YqyT#Y%NWE~~^`R*5i4bwn<&-8I+h+@8qg zwan$Ugh{F;a(OLPNVz(9SLE_q=JHylX!Z0uez@|dhC>ZxwPYb4u229o-UoO9n2as@ zZcCl8Pt(8=VinR`KiUWq*{5}8K3vG61K^c}*c#=cmW#e5UpH0~| z`v+AvUI_Quy!w;o>K{_sWxQePMmx32KEwg1!r*i<4%`@Wu_M|jIexIn3bW#SygTBc zIG;6U{-;!avoD`jX8vuJ&re~54=!0}=I^U~o;V-ov(n6eP33p`@>y%?SCO-3GjV@+;2!d5wb}MseM8=68ldJ zP~QlzEg;FC+9B}whS7$?l*|hVd4rD{$eA2*2B?G_GK6d>LL~r`Y`tF}1pY=@)PDj8 zgP3mzOh&yKWG`U2L21g~V7ZAwS;#?qK@Qzd@b+lfjXs9#JhGKpNh6|k*=nLhi@|L6 zHr|C!F3HxfzkcnNMx*f)Eqrg$1rr>UA3{C{C86P~58|VdCm*5VYYyW3X2VCA+|z8l z@QLcvSHJgaOgML7J{1>h_21baAqM8MWmaZtF4nU% zS|b(9s0`Lyo_gZ3$7}Dp@+DWEc=!Xg$DXRai9@5V?W^WUMwTt_0TM|+uRB)@1z54X zuMg&R2VsHtUs&EdgLxbF?O{D&{a2Rt=gB%B_b$Ibc;o@g`3nO%{Wj;3 z2QB9>4(2pR*g*Q{Th3o1XI}>pJGDl>z_R}GA*^oq)5vAZ`YQuj#q#4w)w2HTKvuC3 zIr28k`fFtE8(VUxz{o?E_tyvV%7>UEHOu=O19|1j`pDZY?{AW~ueJOe7b9Ot&JTd; zx5(LVixw~O^G3+RZ{!`8`L_o%`_nqW{7%dKJA;}1=^9|ZVwrz;Fta}m1I%A!nSXCE zvp>B8%wKGoe}6EuKWzfc@3PE)Fqqk&4guzeE%P4^X7;B!fcX*2{6~YC{pkx}{u0al z$Ag*uX$fF{w`Km5!OZ@212DhGGXLpdW`7z1nBQxe|BTFiJ^9Vn8;@QwTMb7ZwY+~m zn71c*|Fz})i^06^{d|<+-&o$i9L(!ps0Z(tTHe1J%eW5n$n(43c{Wq?!wf@r+zVU)Q-+p~p>*3Eo`UUuBje%@2TXFS!rY}DG z%G#Q}HfH(W3w^8C@7c5G4#PY3Z|q&QX8k~~e?M_<$LW)I=$)KCbMxtQC!DdWck{x@ zQ>!+gxpVJstFr#7^zW>N$=1;Wk2~y}9UiyLa_8!==J~G}jyz~A$4Xkgdb!TCH>QsmITqdgk$`Jk);b8K;~)wRxfI&?62!s&V9zhaPgGC$jReLytQ6sfQlc zIP}P44?FsZ#!>%rOg@<985LiXG5+>QQZwdxf9KkP{&gGI?zPKmY+NyNo@M{2X7CXH zwJbjwR2K3R;+He*ON)JGS=TX#zUbiN4nE@G=YOPo^~Sw64Xj?bdgI#t^2VW3*mg3s zwud^hj%*-ny>{lBgFS)PYZsI6^U3#xW_sQh@RQ%pj)K_~)my+q0^hkOoeUiGQUos%cV@0-itdbK;Y$w@XvPQC2 zvV&xuq$6vY4As*nSC+L*S6p)y*FwcLUvVu~Tr(BdZ0br)lI0X7U!ji;q+S{*%PF8S zBY}zL%5sWr%y3|$@v@xCFlHz)(Ue(E6&W)am}uB6r{auRADC$7ET=k+*(EU1=vi)+ zOs;o^@g|VvE9K~DcW;n@AW?&Zj${uv1pp}`=#>zSp5>S**GL)?YP~i#jV#B2#(3sp z1IlvDYm65tHnS|p_{I$Ciz+)d#w@347~>Ten{1ZTaE$TFjtx7@X;#L#fnxK|avGg6 zRvy(!=j7BG)5lM3K5OT;iA^U@P3Mgxq_V9(oVRU@O$L&dWFU#nUUBO$9Y6NlWpy!r zbUw_OYgxfBAhr`M!{RpG&?^C*LQN?^DJ1 zSgkGj@t#V1#}oC9be<$(1bMRLDUw4Z%mMj{`VeI89ft{@Dmh$2(>hXel;mlWr%MKk zVeavAmBXC7e3)~W4|DGFVa{DX%(=^lId}Om=dLYb(A&?_tJMcjwlD4+tU8CQ&Y`Mv zr0N{4I>+7lxRB6T#W`g2UuXbJndP(vV~X-bh8AK>QJ%=qZj33)6B$~QF-3VILmM-uC{JW)dBzmwi45)07%NZ9 zBysT9f|>B!U-CaBnv5$PF&$8Fa}|#C3HLuGS<6C&BiDor+;WIBJM+ zM@zDnnF>d}67IRi%~m+9LAbzeDY#AYqg;ghUy@9{;!IF~Es$i8fPoyWl6VsG`I4+Q zTqTc|ALR2SS#79Fk`JN{KWAEa7>`#1;J&5oB znFDic+h*nBRLNeQ8+*>z7csGRvz$^Ib6#L#U1vFEH|BkTi8Y_))QBSuzWH5y>mV+f@4}Nr_3nWX&9%7=K z1g<*vkUrrqk}Ms2$Ti%B##P52%1WGpE5{y&0@5Me#gcUFfkU5gA-!_!fx{0jgsYA{ z_|akCFG`)KH}`QF>=sCnI4IeYRV+LS6gFLyz$YR;cNwuIY+vvf`RbTpia=s?BT9#N+9>c4~=xi&}ol z&n|J#EO9R`anCPtFD!A-EpbmTaZfIBPc3n8QU9ytZ;5+miF`J&`Yk}pfXBDqWQRmt6wuSxEad|h&{poU(6*}$;D8`QZ&ol z<%@ZD`C{H(zLh z_@Lu29sk|&*N(q){JrBJ9seZEsv~=r(|7Za>BHG{oX>K4b^g(kO-KDKzaEybq@bA7 zIUvg!2`sF$>5P!&j1d-=Tq_g>^QaNwS== z$kL^@6gHh#vYb)M!aAGIGFi^}Wnrmtg-z$2EN5i1u+FA4P?j_1Sy-&5u(Qd0kmZbq z7S`ExcFJC4h&Kv2kJF3xi1H4ABEvM|3|1b*~NMkmd7M*;e4fg>gQWZ=q$IUIh3 zVEm$jAylEQvi~-2+8L~GM%ZKz5zoI*DbKhY3;MaBR z^jzcE`Nj*6z4&2o)bPTwGub|PxSKQor#t1f)`N5Hj!T{*IYd%y#?)F5mGdykQzeH> z$`^i*SIO0aeDUnAhp`jBUkK-mXLmK-h^DBw3rnWU?~}>*srbFM ztiRTmn+2l-m-tK{)&$!jF9m9&Z69ILn1`Z{^NUh)RX8zuRro`+iN zo8^3qIET<60ydyBt zTv<-hjCp%tqVckv0vmHOOlrz3r|kKQ^ajLT(g{pVvMCz89I6v z8pk~UsZZ5`qr(nI=zT6G%ikWhMSr$^g&j_<_N6nu|oF8DrmjqB7}rsCjIYrR0#aG~TP$;FbE$&!1& z+?Pl$l}t+Frdw8PotAS(vPCj0DZANKAtMiaU#n7OSx$cJVd8`OqS`DfFw4oNQI`d( zsLm`W_eL!Ss;Jy7r%*;M1gfa&ET??-R8yqo6`$o4+o&R~f}%EzD$*(_t0Wd{mR4z^ zET2*!+u4EnxHJe15Sn3#09iypZ zBy|j>j^WfXm^$jIV}l-K%N(SRvD7i1I!05+Na`3$9mA<(Fm=>RN9(m)uCZ!T<+NTq zn|z;1zW?W+dNHe5x@QhpbXMWR=n(tCS8|rF6(Dr9)OJ9kNR4kX1^D ztWr8AQirTkGO|kPkX1^DtWr8;mC_-rlnz;?bjT{vfmIIj%E2n-_jp7DYyEee6Zn^LeKbu6RY_&iIPNo$(ckJL4-7cg9yF?u@TU+!y`Ya>)NciK=r$ z)ma~{=Bnx(t~!UR&XKBfwCWtMI>)NciK=r$)ma~}=Bnx(t~!UR&JlNp&639PRC=-+ z$a01@+x^(3#i(L!pm$7>+Bs0gNnKvk>!lN7HUnPiq(f+>qKh%Kox6|EN7&)P}>EnSeaxw1GrJE z168b3vYc_nXjbiA;N7;_6B-X(F>CFmbJ=H#CuH3ru-*l)2LK-5Qv9fKBga zB2x=YdEkn9)xxv{rraK6wlyXXOu0SC9BfP$m~wm2W@ferACgMwRVV6;{&HsNyrFMp zuZk3tw^3!UiWGCYQDv`+6jQxXWv_}9D*&U)UKJ@821b>=DpIT$j4FFoq*z86Rrab# zvAQs->{XFs(P32Ct0Ki(#Hg}YMT#YgQDv`+6e|~_%3c*I7Bohcy(&_ybBro`Ris${ z7*+PFNUpnv*

    rZtGp6WOkzpxkOwp?%!vfEkqE|(RWuGxcuZj$dL1T(u6&aR@#uU9OGAta8 zDSB08SWX&K^s30P$TY@!)soF{{Mejc-=dG?UFCsPlKj}54qSCJob(AdXyK{{n8`Ka z0#|N^6DMUQ+^~f!H^bqmA;JZ&+zf}KUI{m1;o@d^)&hq$2p72WT_qegB;0O`CNsA%mBP?WcfEkjOM#w-W?kjcABNLn@_1DU+5grr9ha@;~D z2bdx0NrVh!@~#q+9!SXDEoAbp5|W-v$Ur9VDk16dgnYDxOx{&OGExvSkjcABNJbb! z?r9;Dca@NgOoR+%@~#q+5si==EoAbp5|WXSkbz9zRYEd?5^`?~nY^onWaK4eAd`2M zkc`-be5{2`-c>>}(i1X}$-7EOW(Y#=V z@g&+uS+w<$;%zQPp?5)!8aY@c=|Dsq$l)r9Cm|ncA&06Y9SCy5$dM{ZA0gU6j#f!L zAw#s|RT59gP?WJMi6?1p5@xlDDoO8x+{4HXRgw-ww1KRTR%!@OLO#Yq4pvDz5aeD) z4p&L~2+;;|s7m4q8KNDjl6VsB0T%6Om81hfKF-MTDoGz9+CYv~NjwR;zlEHrlJpVC z{fyjDCFur48_4>2rH1f?4ABl&NjxD#QHHA|o{+(0Lsb$_Ua>x2s529h%>SHg%G@^+ zn#sy{tQ|UNaO8oBh*Rp4qIm$DP7{W zdP&??Gl|>kCUINsByOvp#QlHpPTe}jrB-1rp<|Q|RaWUxMU@U!Qt40yl@3)-=}^T) z2OZn3jgp%r zH%mSvxkYlTuQ zb;-SwZ%Do=`Ih9{l7EwYNAg|CeUk4rf zbD)YjM|*;i+9^=Q43y=xQj2iMKo#?m_5>rfE>Oknq&>k%?GUJ9uF{@hq}B$in7Onk z7^yW-!N_bMm^iCxM=&zm1t!jM+7OJ)>cGSqPy2z9SrwQ#|7klgGAjcUXG84< zMrI%|acNF$+laXfYbPm_C?Z}z6(-~c-wj*cuUZHzj;@q!o!pND$SLkhK$uaO* zdS>$#*Oqg?&Xz{btj>S9l;IdCEu7iCdT@yW)Ht(z_23c%t8r%g>cJ%jT;t68)q_h6 z#KxKZm#inUoI%-6A6W}nvbxA}#%rUk4Rm@N@MS@kGn5-`t)SCeK|wRh8*S~N)7wEo zGXWTFEuqs}LP0Y(7;SB#)7wHpGi?}ct)bIfLqRj67;WvLx_-%W<{D$IMO0TaS^l%g zTASzyZNk?kSt*J`>g`5e34Ti5r8BEk{OUJ zgA@#;_#l-8Qk5VT4q_G%>wy>mwd8m!K-xwcA7lYdI}0BIAR6T=8W&YYq$J6GL1V zX1ck{8J|qz>QRq!k?{#At}(Nm)r`evjaKJ`;!-rrS?m~PtzB;rONzCSQ9eHwOWQ1G zsbrMTs>KpG%UMYo<#TbdRL*i1T1NQ{UM#7zoOPH{KJV*^?NYN+ma|MV%0`l8iJs-G z;*2uestJ|P$GsDSn7M zFIrU}cdVZQR2J+nxi_fif(y>Ru(;G`*KH?l2N(ylMuS)y&*L-6Lh?%Y{~hp>v9*v? z<2{~QlB0Y*$@lm|lJD^qB;VspN503`jC_wT7Wp1uCGtJKJmhWn{J#TUSmmI?LjQdSyv!=GgPK)JhpbXMbf}?p=omxk(7}b$p`!|=Lx&SehmIqZ z4jn)!9XfJQI&{dObm&+?>Ci!f(xJ_&(xHK`bZCGq9U4eWhX&lzp@F${XaFxA>MPNK zRgN~RgguAyd%S@S|9DRu-{Wm=e2;g&@jV`G<@d*tX?5`rQ}tT zS4&mE@z6k4Zi* zxmxlG$tNYBl3XLXR`O}db&~5PH%M-j+$6bK@)^l3l3OLWNp6>XR`NN?=OuSY?v#8% zGFWV993xk`o#8Iu&TyCi%Z9srJHuVRo#8Iu&TyA+XSmC^GlHww&Twbk&Twbk&Twbk z&Twbk&Twbk&Twbk&Twbk&Twbk&TwZu0O-zm0MMQB0H8bL0YG=g1Ay*~2LRm}4*6k|SDp1J*G5V`fzYJ7zK#Xo|)PsRa4v5jajrv8Pk^^FNdZT_GsN{ecV}VgW3siDI zj3L6Pp9U&9AjZgH)K3DH91vqbG3tRpB?rV9XN>xBpppY(3_nKwC{W1(F-9e$ei*3a zfEa_7QTGQbIUvRuX4DS?r7{0_t9bpRO{BgbD9r$oV#Kph-wTxHgGezD8g*ZwG&@9! z@zJR721;{9q!>1h`c9xUb3}^K)Tn<8RI%pDat2wWz718bz_Og7*O+ewCa%Y_oB`RG zZw4l=&UA-XWWEuYxK`60T9LUoFmdIkJG3J6^}xh+obJ$y%sqjLt2*7G6`8LECa&=` z_(taLz{C}w?$CE){H89Riv2hj4FFoq?iPaDtlF=m>Z2MdsU>E zGL0&GRiv0njVgOpq?llhDtlF=n0JjTdsU>Ej*TjNRiv1ujVgOpq?o*oDtlF=nA43a zdsU>SB31UPNKHqo>{XGPiB#FEBDEz_MXx$YElYp-Y-EaF6`2o2rs!3XnTt%(t0FTW znW9%kW+5^~uZqlKWQtxDnad(m^s2~wFfv82ip=GaDSB08J`@@2RmDTF{s9!?SbZ45 zgV@nlH`>>Rd2wWtb7L=YKSFsz@gMTEPaZ=VlU#dADEtWJ8IKEG?YqZN#w3?s5(+;; zc}2t}vi9*~C}Wb_EeM4lp}b<_B3thTVkl$M^I`B$#y{+an0iJ$eBY!x>dej)xHrPr`YREFPZpPAP^nD!s^p zaCj2VJ9+U0rq@(4oKfjD7KFo-a6WDnk8yhQ6~h@-OAdw+4o|}QP*gk%>SbCCXH+dY z7DhNc3Fo6*@j$8fb1|Gzwd7D3;qWA!517SMss0ThhBHe4Nm3k;Asn8B^D(%1wAFtW z#BfH{k^^Cc!;^46tQXJ6`e%h0&Zt^)9E@;y63%Ce;vqZBuZiJ|swIcP2!|)(eDW!t z)O8V93};j=ISNKNJPG$>2@`*O!q+8Z^0A@Fs9JImjBt1o&Zo#?&p;QK#c)Q|l4D?m z!;^46>lPai`j65W&Zt^)2#j!e63!>`V)sIKq{VPX)siD%gu|0?Ka;3@#TJPE?N&Zk zKBH>M0WiYhNjP6_6#FRp|KAwSs9JLTi*R@n&Q~zSW=xh}6~h@-OAdb#4o|}QqNv!> z$?_{>IHPLG(J#W`NjP6;7285t{*f5Ys9JLHi*R@n&X;cbXPP*^d^mTiwmX z{~()CgMa)U_a(~9)$^9uwrYDuQf!~(Ew7jJ4U+Qz(8Ir=#iJ1J^1TDU_{H}Q!hbJy zBw5RHlCb~Fc&omMDVN=rF#nhFmcYbp>!Jk0G{h8PLLqcXLS!t=l2hmSaS-rr#Fwld z4)mBfuot-U)Hz2<@#DPS@fI$gI?vxIrybWbf5lk7j%Xj=WLG#p?9+N&-#liISLJE9 zc-8^e=Y@ST#= zC1*&^l$<4bm*i~8yCvsHl9OAVUGI^{xsvxv-X}Rva=zpO$%T@OBo|BCblTD1l;>Gz z*ZbvliR4nrq-07mEt!#Qk<3ayAjvQFI_d11mvcd~D7j4XLCNKk4@s_&d|2`kNqO~m zIARos6Lhr4-Z-n3>ggCdgK<_b)iFxfo4|4|!fK{EV(EsH$XeYj zJtcB!WUY3Vo)V##SskxtEr`@L~I10Hmt5Hr$puyu#3|fP#_V2Bm}0ipm)gflm}yp zoe{9a%keYI8EK5MOqZi;UG0YgN+;Uvcaz;2~%qZpP zpXH2y#+Wh7IU>s$9gVR@P|hS-&e&;;HJ)<5$#O7`;ac=ZOl|6nbWw>+dW>B%EqYve7t zJX$1`wS-PQ$*Wb8UuqSiU+8LCA!oa!G-m#~g8zp;59wXUX@>t2^B>PCpOJ$pN>z4n5CH|0VJ~r_zrTpY&GtSCa?ZR13^RwaBN?7gCSx&<=*2-Az-dRqQHP%YG zbahN)HrC3ybahNKH`YqJbahMzFxJYtbc&#B7;B|nIz?EgVFI!8R;GwO6tIJ-0SY7n zkYqqI1CnKsf`Jqt^oCuohUs=TaadyMltQO8#v5GRbI5YKtT9%&bTv$eHpVI?T@BOS zjj_s1SHlbj#+VVxfiTM%DvUAXmBVG0Gmsc#Vd&kSeZOz z15+MJp|*{ATVTo~DcB(FW(TG`l7eN7c}rl*BPrO+m^TL|Zrf`RiOib67C%qu6kPx)*xKq%G+Xizd+szcQWD9xBrl2kbr?q zZi|7$laQM&WO4uik}N`=Vq|h#3?%s=+CU~}03h*%4ACaH#X#c8+mKT&+TymD{B?5M z>kuO-FruA>E0XNF8ITV?1??rjC)+@weO;y`kLXXwwg}`KADS zA!DgyJavqwj*-++T!~Bs!zoj2MZhe(v$Dmv4|t@AM=barPicfljiY59brku>vm$(t z$4&Si53KM#9(mz=+@9cjJa&`r+;ny=%F35XJ}9|d@*&9;k`GHhBDqp>m89I+>FoNb z+#i#CTynMK6OvC#J|($Ea;@akl49qlv+H^}Z;;$5xk+-fMBk!hiEEoR@-`QDil9sa<{(7u0;#hUSOoY z8mOW@YXdP-cLl0w-P(1G)K>ykv~_J&M(WFfDq6nwHzW0>Ko$K!o1&5WVxW>sz_F%f z{tJOBb_Mm)JyLfDD%oPg_7>`nKo$K*zEEtj6}3@pvC%q=Dr%#kXf#F@wNX&CC8LVk zC@7kkQAKSO6fMuFqBaVO25D4L8wEu>HL9qMf};5vRn$g7S*xbVRvYQo;dKhs#g-uq zNMMloL9zgnOOS$qlog~pKxz!MN-cY>j(Lf&4aSgm(YLdl&SQ*axEulWkMNPPQkLU{ z&SOQ!s-_%GbmA&9R-fgVqcc^JF(a_FI$9akUrv{{9GKKv{*b&G+bFQTfa&bB@K2L{e0 z>5ks+ZVD`)jlrkBI{37nf7OLYnM%)w4XD&stzCn=vuFG5$t{~UXPuuSW(2R&4zn3&%w27)u@Fsbe&CjHHgC)G?eo22)2pb&T!3 zY9mGH>p$RtnyOtlUdd-)GKga|b&RBrq0}*)ItEimy>zr*ecqK;qrC&W?@n#BUiAL+ zta>_n#>S}P*7Gk49=!vPdX#CLe^m(bs69gv?6lD=w`QlpXCU|tKf-->+-Z+csQ&Ht z*@tM_)hmtX@Dm|7tDf)#vyE~iKPsblRimNe+lNu-UT}3uG0rvkFzSke z>ga1c5sD9$roHv3gU`O$yMJd_rYdcb)FiEvHpvP}yQD+XDe025UUkKl=XuY}Te{`b zE75`PRo)xhJNo3&FBy=ml&q4hmTV{4Ucz~~3u4RfSR{1f*Z98j&zhR#nm!oF{%Eew`li*JirzV}X3d&f_Bi9)VK%O` zp>4kxitiB;y>g>ap+(mR^0s=vMr0yYIVi3~%Kt+UI~VVR_uW zB-Vl5_uH@LzsT&h;-lE=b#&g4-43!F$F7}+OCm%!wkeLft482L+3Q0Sp2@MI5JP*~ zn{fN6WiPbCbj@gmaBkzut1dX(291hJh^lL`sEf)G&O#Mv%yD9ZRNu3LWAPW z&rUZkNmET!J=IxHb@DvR*uEB##}-s#`QLu#@hj1(uWvk!6#0lLMxAKL;f-7CSbM1E zs9sU?S7iMiNHhkT&{aC6JDyMT~RP{GF z*l+XG_IsroVSm(`ddx}3c8wR13LmkTv>txcf#+O6wXLz{%TR~umFr{CeZA@aRWHSL zA+Ytf!A)_o)U%@T5_Dc;IuDpmeWKczKS0!>o41~=!C?#TQ%$vF3w5l1Xnw(#?ez^q z3|NU*O>?d1=uM>d7E3MUHs8~k<6%xVCginaX0~DXTcXgjs&OI;eAKenSn4ZgXB&qd zb|7?bf8!)*K5E%ZYl3XWmRZ*M&>aIQ9g5j8gK;JsSG$5mAHoNPma8v>QZ>GVs86$~ zuWKRdzAe+C&o*WhK~U>$Y(|Zbn1jB_xut6DJ2Xy3jgQzL2kJv%T$(xQ_{|%qPd;-s z>DC^VYKFnGcSLntXng`hgi7z2-!j*T>k8$V^D>QhSsJcDQ=~5ubpD$zM)cxTO{wOC}E0(>de*U`8Fg{!SZAvc|4L(1@;zHXAnT&WSNvxg|u z$~5YpbKaM!&EOvfzxhcKWHDj7$Ec-U)>2Q2ch7um58j>zwrhNn)cB}npJMvYdKR`; zx(OvdqLTG?dXzQ2zQ)Zc@DaxpoA(EYH1SWZ-FKa7ZI^0=D(z|tswuse0jP-SmyHMmKPM$q;Tj&0(DDe?!AH!#Y0!vF zqqCyn&1^h1Tjwrm9Ii21(b%<##z?B6a(|0_d_T!Y-=Zq0y58AtxbXwj_=vrtZ+bi2pPc7{dzcWt6GTGgpnbdq&a>_xrp zW~>IkwjC!AUt;NT<4-T8!5w$w&v2y628e$$oV}(snKL2bOQ2}U^u3>Qm zjnG7Fo>|lqLi3C|)^3SG)Q8+49@w&(2JTcYL-b>1xX!U?oy4RnV-6C}_6^E`e&^D>&R4{GoVV3P6YFl* z=qGtT;@o57(WYpPwY#JmVQ%fN5AqyhOCyTeQPJ^fgA@ym*4@)sLNPlx(6Qo*L2Khx z+OnjQca7C;qnLC>EUwv2uE=kv?I2$9%Fg z!x<3@+&QL2tc^f-GUbHzY3GD_DyNBO#}-z#%4O;|B@>Xt#II{oeqrcIeEX*5TMj)5 z({lB><~l}})t=NyeI&GtM5T9Bo|{iO@%S^>o^*OxtF$!+X%0`f=8&waTe(zjO>d~BoLR#M_kAZj5mv} zXRNUiO+I3Dee<&#@(w-npaYLO|F9#@``5B1*QtP$HcwBVeENxVdkzjPORefpsJ?|t ze2fZ8)-sqT+dqfeVTT@f+`&g2bnMj^oc-c5;r{6gH+f#d4U8^RFst%3g;jOeOp5UG zGLcmyOX*ep32kFvvA@#3wy`%A$449;`{owi@^i7Bts86XgBl<4X?ef~Tn&@EY+}=5 z%8zA4|>((ab; zfb>_?LTY`}G5bZs9a!JkpCtLHWlz$l9=RvCYTr`Zgc=`FEp)gd!By)TPe6r_*eCnu znLb-` zU<_4^*)6S@-VHn$?CFKSu&kB7En8Hx;T4HWm@xH`YL*geV8g_cEG1-psA-n0wWV1a zm{=OgWSOnri8Q|n(KlPkZ^G1vs`*VQ+XGC70M(Fnqcl79;cB)&P-bReY-vstvUe=a zX+rePRC1ay_2Ftx6RJmDt1`?et2QuHvN~AJ>g7pR$CqX`A$!NutR_U?VkN5yQy;8m zHKm4qwUbnAZABQYpO*B=m0NrmE4%MU%M7ocbvEs13Ew}tq(>**z@V=qiyoDd!%h}` zDk1CRTI&>DYH;A$WGF0f>SHOjsz0H+Cq#K^6Yt*fbUDk&?Hi1JQ+kLfOPvJipA?gp zIN^Gx#l`U}@$VfP9NAQqG$lqv6s1gvuK5^~y%5!w;`m1r z=f_u&yBq5&AuWx<{yHwE*Rg%$6e8lImYrhhg&d7|j@FHCt)xlILq}ZcPjB3^%-9(9HOYF+|m`2YA3DG^gRTgYOsAOTN%tB|9g^4l?iFc27G>XC|{+(g2SMrHx_uy8^+rU;y zez;7&o+Lk3CZBj~)+v)u{5!FXJsBmQeN*YAY?F(u{SP$kGzWb%t`?f-c4a2|W}OL5 zG-2vv{$|iSLqhdV_=yb5PC|4oYMu*ee1=vMrnasb`G)ut-|h)bmL7NF-MPWMRm+K| zbuDc!TyW)8cJQS$4A0|w%QiKCK3*Ikq_Fj$9rvEB>dB9MhhY`-6^`J6_?)`Du6#OM{$@2Cs5F*VEMtVxl%II{U8Jjp{CE<`FD!xl3=>HCFBejNkn)3+ zAAFf?_YvXC9be)2O2=0@zS{9Mj<0omo#X2r-{AO0$2U2?+3_uoZ*_c|=v- zFLJ!t@%@gMI9}>F={V&$?KtDO#c|g01CDc!^NtISi;kB$e$er9N3Om2nC#6R7a+go zMLXdKzd+i&% zJwWUMVh<2|fY<}X9w7Dru?L7fK;YmA5PN{w1H>L6 z_5iU5h&@2;0b&mjdw|#jq<>$dk^GIqX9(Zm_dAA4t$#9QI1DC z9^rVn;~k#v4UX3f8DApej~l&@X}tZC@EW=A7GCT4X~*jvuXnt`@kYm+9B+2~jN>hi zw>sYDc)R0g9Y5#zdB-~(?{xfv;};#j<^`j=ykx(D9d!zjFL{$6q`C z#__j~zjOS(;~yOV=!l)~aXW+98N|*Yb_TICh@C;~3}R;xJA>F6#Lggg2C*}Uok8pj zVrLLLgV-6w&LDOMu``IBLF^1-XAnDs*crsmAa(|^Gl-o*>F6#Lggg2C*}Uok8pjVrLLLgV-6w&LDOMu``IBLF^1-XAnDs*crsm z;GZ0^^L=vDpF!*lVrLLLgV-6w&LDOMu``IBLF^1-XAnDs*crsmAa(|^Gl-o*>F6#Lggg2C*}Uok8pjVrLLLgV-6w&LDOMu``IB zLF^1-XAnDs*crsmAa(|^Gl-o*>F6#Lggg2C*}Uok8pjVrLLLgV-6w&LDOMu``IB zLF^1-XAnDs*crsmAa(|^Gl-o*>F6#Lggg z2C*}Uok8pjVrLLLgV-6w&LDOMu``IBLF^1-XAnDs*crsmAmcVjzXq}Q&O+=BVs8+8 zgV-Cy-XQh{u{VglLF^4;ZxDNf*c-&&Aod2aH;BDK>= zu`7sOLF@`*R}i~`*cHUCAa(_@D~Me|>=u`7sOLF@`*R}i~`*cHUCAa(_@D~LTo>cr$L^lL7t~Uo~J>cr$L^lL7t~Uo~J>cr$L^lLH1Wb z_E$jmS3vexK=xNa_E$jmS3vexK=xNa_E$jmS3vexK=xNa_E$ij-$9<=L7v}1p5H;9 z-$9<=L7v}1p5H;9-$9<=L7v}1p5H;9-$9<=L7v}1p5H;9-$9<=L7v}1p5H;9-$9<= zL7v}1p5H;9-$9<=L7v}1p5H;9-$9<=L7v}1`t4(d^jnaA3({{v`YlMm1?jgS{T8I( zg7jOEehboXLHaF7zXj>HApI7k--7g8kbVo&Z$bJkNWTT?w;=r%q~C({TabPW(r-cf zEl9rw>9-*L7Np;T^jnaA3({{v`YlMm1?jgS{T8I(g7jOEehboXLHaF7zXj>HApI7k z--7g8kbVo&Z$bJkNWTT?w;=r%WIy>Z;fv)y+>!kf-0Yu#?5BY2uYl~gyh_M^%}a!z za(tHKGll3y#QzoAZ~c4WD;;0u$UZs#?305p7yeJz1MvqLPhRMFjN`G6$2q>#@s+~Y zYk%)G!b6phw+Rn(e5&K&j_@Zq55j}^zuo;o^g;aJ>HZ-3niW!B>H%aw3%u6xI>+lB zZ*aWP@g~Qcg)dWiZxK=tAoT`PZy@ysQg0yj1M=PhB>ZQEga-)^5*{QxNO+L&AmQ#5 z5)LFBNH~yiAmKpL13#_ue_42)IXbS;qDRg>p|dIj{Msi?z0pAUgtr05FUKG@IE2!?2nFra{P;zk$onji_gNtCv%vEld7s7m z9^PZ|{s-iJ5Xk!>koQF(?~g#K29-MXLZg||}m-kiV7bL$R`31=@NPa=`3zA>( z9)Caab;o-hzv1{z$8R})+wtEVzvK8_$NL<==lFfcA2{Cc_(R7ZIsVx30mq*>{?zej zjz4$&h2w*czjXYSyz@e^eH1Zl@0?HHsTgS6wU zHZ@OQU3K*E891JMUb42I9{P9MZi;NV*{Df}{(QE=al{`36ZJWMKQWkoy0MyYF)M zSA{(I^WudE3pQ}U``jNS{GS~ka;&K#;NRxB!m-`4)3MvJ$FbM3&#~^fy^wtHpvnX6 zkh?+Bd4%Jr&~D_U3K*E891DSY1^8W|Nb`2o7S2K{<6;cl=mpV-FS3&EGRC1=YJ>+1D+DFWD z6!JLvGi7Gs&Y~ev3Nk3jQF$%yaCy;4poSy$JfrLY3dgKgboceCHDxU?^%#knNjO_E zUEDy?yDBKvi2J8X9%YnJW~Rr z#K%leeD5K?w&LIBdj^7TCwFP0OCD|&eq6{~RFF;%(#b(OImz$n$rC4WvwFzd?BWZu zx@v8Ry9M3b#gPxwA*=SU2`jq#`-}Qv(LppUIzkrhADwyzf==u26wUqO$m*{>I&=xc z0wpAEVOFgTVXR8O?_qxKVNAC*{!{yku7Lrv&`Qbgl?u82j^hI!WI>qK{Mwrpohw%s zAzmPc3_a-hTMxmBm#nS$uay zLE?Oh#|aWANSq*X63*i+uSd)BmBhKD$9bH`2@>Za9w$hgAaR1kNjQ(QyksrQS1Hc+ zojlGLd7L0|zSc)rn$Rh7W8^c0=zCn{6>V9*T5+w|SseBFVj=Yi64&cIE=H}hu^Ek@u;Ie#s%Cue_`FN?2e1OD(z273FOeYD6 z>l`8a7FWDXZmj}qgj*xnN0P6SYZnI3%FS|F%MK#hGBzM+jE!@w=HCg!%r9yIx zUDm?oT@4i0l?r2fzum7l>giv<-o`U}9BaHi%i0<@t)r+JRTtd`g^i`cXhnfOfWls- z!bnAd293gFN`;|{0<9B;y-S7RiULgzg~yf(gB1nZ6AF(j73viQ8Vd^hlnUYI!yb96 zlDY-Snfk6Uufvp9$%OiJ{kDAp6fvweEkGnlN zyuYG%*Ik*3yJ%DwiltGVrGbr^_&bij_5ttDj=9gsJ&r3K*9w`Td0x%hlmE3^(YxDj zq|(|DafwnP_F0epDj}hGTF&e~#wU@>EI&xFBa2d2e;^AxkkuQ=N(*Ea1+ruUSq6bD zZQ4{HmkWRE&*k`E?>y(^aC1%$Wd9gs{}?>dk^N)b>>q>dAHPZX40p3nj6cusAkXh0 z&+j1h0kU!dZ85!~y!vNF&m$knI9X$+`iwF|_2i0-Y9Z0gZl!#(m~4;yU_lG!`hvco zK`}DB+46~e+cQ594dVEtYfwO2qHjF&u%L2iRQa>3P|vpQk3FcA zHj4UUX;Pp}2~cD#z}owj@&_3Pv(|VI+lsC|_f*h)g7{JAsU~aXUIL4`YvV@fN6FW! ziN|i#u(JkH-H58&OwjD<-)k@O(83T)uj42D=824<7OgkPq$n`FqQI~Jxq_}wO%xbH zQQ(IIT|rl>CJGFbC|p)5=$h3;fuRtE50(nLdNomCxI^LcQbE_TCJGE`DDWeRo(Emg znkX=Ap}_Aex`M84O%xcKP~fK-T|rm5CJGEcDDbO}rjT4Po8`NUvCE%P(bcZSb+cLi zXs8=Jw5a0p*(~1!>c)~PuAg5nlz&qi@+ZI(X< z>Xwo!uCUGWy`gR`sp3Lg{Q?ivZ6#G)Z=2elF!%M#1-${B+8*ih{3~{A9|rh=T7g`Kgp=4Fx|?@ZsOdo*_RCaZeXm-~FwR z2#meiitwK`&q8O9{Fzbbcdo;@oUI7|XY-t(^X#bed)Hyi&Q^r~Mf`hovi$D^HhX@X zG`f@j#kJ97pmDIg?Snb4#(2cW6XO+c_!wDuvzCNh)$bvnOh`V8kZf@g@;DE94Iw)# z*L|$0H=aT`J_y%_ehe2=exbrKoxDm&4xS~z94~f9WQX4bNrBy1U}|&)*mEr zoiOVx{;$~LuQ%9Gvk&6$BpeTU#Q#3Wiydbi7acz$ME?`+j_u?|xwFpV-;_NaHr^V1 z6zT8)NIK^^zTa_+<7JLl3Q6aa?v8DZegCW@{h!MfeGT^Y?4wAA=U$R|uj56I(~b*{ z9~P3#)j}rCUkRzU8-!VFyfC-DJG~88rTLvqc(hd5w|Rl^4{{$*%U2M;_oh3&%GQJY zqg2^ai$UH&khbzJl%DjiS%sln&?rfcMoBVf5~gz|y;xI?`GIKH2dpj)yps2lNjUlEIuL*ak_SPHEA!~eC+vJGSCl!dN#cLdIQDEGkb!4X;_g%s#D&T#N_X~gL zOLF$tNaT|tvz;7yB3>RKi5DbZka$7j1&Q|{j~67~-ur|}-|@$zg*ydd#{#0wHH zNW4$-ctPU*LmBTv8ZSq($S;qb#0wHHNW38Ng2a2U#|skgAIo^>(s()IMZ7$b5-&)+ zAn}643li^>JzkJ_|5V01oyNBa{cDVu zwdkJfyqUFfLXK!ZA+;|{ZL{zm;X|eRM54|?I@Gzh5%p7DU46m+@y^z)W$c`{L;X{( zewwT2rTTahJIC@+zsA+y>FO<|`e>rg={?l1b@kI-y;iD^l-mAPbo3wTW z>=L$?!G_9UwbMNqMI~5UsWzOb@h_RgP7zUCQK}7=YORc5s8O_-iHD@#UaHqi^%_GJ z>J$z2j#5o|v|A*5`Wk;H);?@Rx<|v;&e8?fI}Qmc$RmXp$bT>Qf2_NiGu|(M#^pB) zpCObjRlwDEsA@ENc79#nL<-ivNzg`xRrR``Q(gZX5BKTA2Ka z0nKBCS%>a}+e!n5>H9b|>Vw0T%SIoGryc^x)Qk0y-~=UwD&sl0*m*eJd&t5$}7Kb;2~EK^7Ue6=w z-K=r&XMF_P(yH5X7=8%BBe6Om@JdByPjp?2v+*|vK1fScVPB^R-s};*RhV@xY^6ip z!ch!MtZUYFCeQm&63>Yq&&d|g%vL(Y14le$KI&=%ak$Q}gD$H~fCza-Vm#^`-sCl+6iHrAfWRe?O*$Rp} zLQbvWQTwHkwu&fiLyEE5IVNUU!=Gl{?e&Mc(A{#L%zOz)+@7*;~WLpNs(@RDD`dt%6Hfc~i zqg2#y;WbfY%Lc_WOGW)MUK2$&a8Nv}RMhX}HBn?c2gP@liu%>OCW^PZ;@PF5enYQ` z;%%<@?ov^|sMkdCc2_(nDz+{xOmb3#zm_-3msL5B8&?Ul)|r`-y;I{gD}HXc2<&Xa ze!*Gpy)d>%+pbgG?%&WY_qOi$1_VnSA0vexZNP4&Mf*XExLj-Un#H*$alz6U?b(31 zw$dUli$f(ht@;6DgL~^YJk%J+26a)CEx(ktPpbgT@7KrWR{enSri$0O;ti$ZXj8@O zUGc_Jaipo@4X$`osW{YB@kUp?xl|l(s(6ztex_6$Y^r#(E8bEn)|)DR#uaakihcV1 zJY8ij`_AyI7O@&{alPA0z1e1Zx4Pc#rQS?4z1v*xv!&i*Grikg?{lTzd^5ezy58qY zy@h6apL4xCO1-&edY^Z_J4?OkW_owH-WN)}$!2==GMeEROTDRPdh|E+zEtQfR_>R( zGMU_XNa2y6ZHugLzNsFQ2|P2v_2_ji%-L1r`bmo?<5m~hq>r2Qomqp|LYkDe(qVFg zV=Lx!L8thM4<7|unU!w!cy1Rm-q1&xG#|tItZTk$yy&t;5#pWRN{9TxQHC3YS$)Zc z@UIG$()nj8u&qF)3^=ZGTyQ{a6d>!F zvRVr7_Kx#5K}=tDEsB-Z^$Qs3#ra-O9n{m^Qly?br3iLA_Bi%B_BqxaZJ}KsT0Y`? zJmMA)P;+c`Y;#=U$YE15&>_tD`GWAHCZ1PoRQD=MY{TN82KZ~op9`~|^cPONDrz)W zwD*z1w}n(3Rg?8ho3%p4MSEe}s71EXCc9bBmTB5SwVH|hJ07QHx~?CGXj0AA9Pg7N zrTe4fpB;JGiT__6c{hkV^V-OT6xsSscYTy*W5225dA8?~?<)|U>waO@HM>AwlXhrJ zeK;cek?G7d)qz9j0n=G*ssl%D{?v5lm+F|E;HWza3sN|c!e(KGUjB-M8`wr442fYM zG(}sbH&;Y~T>Q!u^*cOG>fNda1(K#dv!2-|W@J=}4e7T;*E6$>7A%SW-n15*XwiUR zNfFCwlwDdu*3YRJ1`ZmT27~c180dFb4kK#s=rj?O=s0?2aV1@fe|Vxqm7-+Lv}>~I zh(YzELyyb47Prtmcsc#LWW1o=p+j%X>iWT%W)*t1I4TlFx@)GNI@-Elphe-)vVPGu z*R&ESJUWa#DxWoN`z3(15-2=M3`<$}MDt3Z@F+26WnEKED}lnJ!+54~y=f&-cyt)+ zG`TEa2^1bh219H}Z}n z>mF-f2^5}w#S4(Ed%SriP9WkQR0 zE?IqO`KqFdP&^F9uBoM!u!5fNF`*6fD z>NxH=AtZg`&UDr3(#1zBf!Vwx@UD)J5MntZ%ewTaxTHZ5W=I@E;)v;#zh2{w&Q?os z#1rEqe)Yhu;$z%^Lzj$e0o2qsF&+w)>1x%bg|QKqOjBZNQKN9v#7G1kYB=kfY?@fC zIci@=dKTx3r)i!H*xzI`*KE={nXq>_%bsjtrxTW^0K&4h8rZpn{erXXkOphdF15Cm z5o?lvUQ=e>L(MCK3P6c>m}>1!D}o9@=Lx1W)wCk00CXDYv`)>G6*2AEq#_P9b~0gS zoTVZHJDspwoTVZHJD0Gt&QcM^c8}Wj-VASWKkBm=eTUT%3zvOJzI%LYCE6;R&#aPy z(#Y0I!~{tv*w11b+FFTL3Q1i&5v8v32Y2E+5*>^}OJ+<1!>~2n+(;M)r7&zwH#HK* zK_?7bTWpeBI*Vf*bZpq_Jz!{WT|BIf5PmGlUM^^5fwid13xrPL+zqct=>cpL!!psza`o|+`ML~Q5Jyqmbz=PX|tzBc?7gmhTY@MXA7zurNf1p z?gVZ+NKoA<*-68$$)?p#b)$165ov3iQE+LsQ{Ctsg^qrwp!saUEP>Y3(5eqFKU*+M zp!jqYv7&xOtBDn<$d^gYUY=mZt<|t1YA-L0d*a?P8hy9C2(@b5seu#_?Lm>m09lyutBC$D16VCCqfk zIn|jQmAcqRhu5i3|GiY``2T3CL(8bP(*04P`@hWb6^^eYXnn|*gvH^g$z=Wf&r)DW zAYe8yyi6MQLgjx-h3p({s)Ng@T6Rz&J1=s4iQ`KNS|46MJI|8>*&$#y5LR(p*G?eW}1=h zf_P7Gy-OXZ9H$*;9JdIy@3crfjVXRJYl}C2%6gJm3PCJc-_)|Hz1?HG!0{r-iyhzZ zc!^M{O7M0yw&S}U&vAT@FzcVOIxWwQ#(HJdMhx_7N|5y}G)vLO zDN;a>5^B4|HlT`wq8~^`DYAefRiFvPwzP_qp7V(!c|?&q%2rNU9@FEq(}^zSK-cO~ zKkS9onwN)ipo#snzPV+~Lpji+eQ4)n`SMT>6lp-3ftD{1^aE=}Oemz^@BXk%ONV3Q%! zIt4=|YBsX=&uydF6clVtEM|_)`lq*1Y>JB}vv9U@ew)RnxafWy-M%eT^q(bTu2nk4MURxn^9^Jm#Ws6O5(c`f|ZFl)%Q(P2pG{v#yi%oG+ya`1e$FVV0XUGolftM$VTf{LD z-ex-bK~TosQpfi3;FyfK^aAA8C~%D<|Fwvl`vtV?v@{NTMEIApa!^t`cg$khj8VUM-zFJ)JLFIYZ3l?OxH?JE)B}Q)Ar&P2%4nwx0PZp8vzY^u#n- zvwd4ERbX1Z{3K&>yez7*1c644l4QMu&D5SD=02&BweOQ=FF&8TRcvGpnu7kw)cAG9 zt<;F^evi%6dbVsa^Vm;{de+*A43={K#ql9WE>y#xf7I2g3B&zM{2@H=KK9K2fb0Lk z@sEywa{RN9%*IS(Y}_5XWSZ?vd*ytgx%jApvpv6eZtI_85MSjp?9M!9(W%5OS(6aHeXL6Z*ksq`egEf~d9Wkv%FcP8@ z#^=dp@=l)7`rmb&-ES2|7{+I3W_Qn?9w>!7Zc2#3XuN?tZr}hGP$~ud;6st}p$UXU z@X8Ma(TXSptxz>2UbIP@(%zWV2nJM?Z&2``5JeCSsDOy@duF$_O-_69+nt$b_B?xL z&%UQ;-W^2~&1ly4F3(aa)+pgZs*(44U0w1ll_C)tDx-LpXQ>pY_>r)tcX^g3#IQ=& zDBk5+s<6xy6OpyO%d=F9$I6?j?OmRwQncnD;ym&WzY&J_RGy_$EGM=q18PKU)w>|i z(u6qAEmc8b*fXWY=T)Bdt>ZXXt0o$2dzWXaChGM_Myc&xo}~)Ulva91@h;C&X_Wwe z(5~rSo~6+W0uQ=9Z4>HsQ%g;01{LW{kW@iD3;5Z<%>njN5H$hgH>_{nA2QA9G?$um z9!Tbc_%Yxg2W|nd%^-RL7~kA7Yj0Shg-#2pNf&`+F^HD{|0Hlv0sAzFo&m;x@%g}~ z71@i7U8?G3p}M81{j*5bnJF))CR+hY&w}(hkgNpp^T4kHt`*qTAX)>A8_bI4pqo^? zS+%}>UF*QB+T)2Nq4q!h9(I>#z{R7kU zfiuz6gR0?lzEty}&|IW-Hkk2WQEoU4#vK9mUxTsVfHB{K%281F9VmYfvSXlh9Hb{e zauUR+fIkh~8DP(X=o}y_b^NHUGyVs*?mVy;K=hNUZBIU-n$h&oWUcgjV9S#el@}U~y{_Ij)H|y$a_OfA2N?WQZGVNfhm{mYp8ZhU z-)g(5HqXNY`Qdogx?xGn;V_M6{4G=sx52o7K>Zys_FpjOE~xwm>h6Iu*Q3cIP_iI( zAn_oMflq)-fh~b31IBZU&tIA+-hF3pF`e6Je2dhJq+TrblA!J$oStSFmrAfqg5?sd zkf7Wb2C27ts3UkswpOxrlD#0=i$T_}M_H=FWiLs#NwUq7y(}3kYxL#jm#sUxW23td-pNb+ literal 0 HcmV?d00001 diff --git a/CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_tech.vdb b/CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_tech.vdb new file mode 100644 index 0000000000000000000000000000000000000000..936bc08922eb32652ad3492b2d6f7efc41adf6f9 GIT binary patch literal 67453 zcmdU&2b^8Sk+07UlSjHU8i9lWX@UUF3`qhE29LQy3@8}%cGv5KZA7vGd!3B~U?dRH zAX$Jw0uyFNk|$srgLj_{IBt5o>l}91#sQ~IZ=G}G{lDt&6YjlpN6Eak^t-1|S5;Sc zS5;S6_vv%y$X72aG)K{ck^Ysx^Y%rB;(4b(d2udx@S@h@^DbIAt*{rU4i#lid`)kJ!9ou-wtdX%zH{CkE;kK?> zH%)FF?Ye2x;j@nHiaJKq|29vK6qhW&eEI4JM@LtVt$W3T%g?-U&4rf^KR7nBdHliE zYuBB#e0cSPD_356?t|~yc2eh|rM`jo-osBjtaIKT*LYg@jhk=XIBTEEHf_Fj?6#XX z-FR%2^PT_w)B2~bZ`?f6K5}#Kt?Nf;U3cT=4YU0Hwd3y`+jw)__3Nzb*WI+~wpmAB z*E~CyD->F8x_SNh&70QW_;l0Fx81mL^rp$yRp%^UTR!*PRV%OcmCRYaYVGivRjbRZ z&b@5)x^v2FFS#_=9pxgEd_n5icP?o~=5pn0#jJI5bj^yh%9D?M=zit0y3XZhwaoAA zSg>sV2@B^|W25LLvX!Sn6r=p;a-+ya`H^s!+u%XD+w3N9SJipxs#gtPK77vbMUS+d zcFJKxopTq=T{i#JT*DsLmXC59XXbqB!nuKS6k*j*7ow)9AsXSnGKH_x)0 zd{j_(hV8!1LB?FJ(dEX|xhB!BHF%Vptu)u7%RvD0V*y?YaFb_#JiuvFu3Z;vL4Gp8 zX<5EW7w9!mJ--Q$kMgqwqYOC5b1KHQdKl$hJ9Y%VbUg>&;JM=E!)u3|8JlNqoEk|h zC}khcVCw70Q$jz3pVP*ZJ)1=&y`Z@l={G$9(9!5FW zrd_ewQjU5sX@}bx<1krZ;H79AjK%@Yq<- z29A-fHh9)Jp~b)*E-_9F5E$iLJz3)f2F|rD7-w#!Ksm}9ysnMKl8-0a$&u+)k!z~2 z_I>tSZCwjHDrUiksAX^U-7t;5Um!t9b6($VF6SLrqsw{6Qm9_2%R2qAf(!JMoAjT^7Ui^{!Rpd5S+Ue7`%M}t9l3mIKAx@tNLIq-uut30o+ zjPlZh^)+-0wOpZJN?orF@HZPgR@dv4Eg4ylxle+S;+Fmb^nZX-%Q>iv!h!`GG zKC3ohsLj=zs14Ns1Lx`rYRkPrAe$fzUQacNCcJ7UR!*#(Q8jxVUGAA5eSw;-?q^h! zjy2Z{YpS`)=;BF#1EuhNH|U2dZq!esHH?^R$uW|y*AFo}d{B*xEy3Xj;gMF)Q67ev zUAn zwfRXe6O-k4IG(=TE|+s-tUcufx2RrI-F>tmae}v#W3=6?AF6w|eks-6p`68Mcj@K` z{qE5Z6*{`0!rYw#nTqe$4XWO*Us{bgIe1XVHvQ703>@X)>u^DhQ62{e4E58-C?7_d zGaKr`Y-m@M56;oWeZVjcE0@G?&Z`21sR^Xe9fCVoBfX=fL-qz_ZmVEsRfecH0L;o>@XT=H+%6!6biC7sfAJY%9I(|W{&g_AKbLGNN%6&v2 z6S=|bi9C_87r7+j^TETdqu8Q$O~Omt5L*nk#D666FrJo4j2!8(R50w*DcQKI~P# zYR#&dRGyc!+RI5WA5VgQB#jMQ&s>h^KRBqT1UF^=8wAOO_00hPuEAp^e+xLua_~gS zC=wVr$19Aa+;;>rMH;-GA`@wN@l3LVHO*$`A9~-$yCm;~{LG(O{)BxShfD9mC>@B#NT!v*K$ zaPT4qaJXciCk6lp&b2R@=fMF3XZ0oXeC|hr*$T-J_4J#l)9ZJ1a>nh9{o3Tsnt!7j zDsA`}(B;z8N+G9?5T&*1CZ)AvfVUVt)>;GbBShM4@K|e&$`+3F@Ft~{BhGPr6D=}m zC=1TmDxuC^dlfV`p8N8mr6Zr;#kBm;cX%R0;57@dVJFB~464pH~mll5) z-C_{T*G)?Na|8SkgU8}O2sj40z~Djr&dA}x065feiO8AN;RDWuM*v4C0|t+Ud?auL;^0{! z!-Fz|RwfZLf`p!O4i|)+TLM4u2Cpl~SZ=W(CnjbPBLr z@tXZa;JB1i4IYd2B;dG?XB#|-HTNuK^SBP+41HHF5iRyh9fRh)J1f`lS=-Le&puak z4e!hOHM~=0TPg?|MgS=3f9WPQCeBjUR@-erAU)?@hxSir?PJnuaeo?e@;g z5C?{GnQl^s@^WQud*>3}UR!zBhpzyXYMu78OEVR*Ea`m8OL1_Y1>TgMXv zay|(lH5%7KvdwdW;AUNhsApY?F@?Ec*Nh8;12`9Ct;^@8oeSPVw~*8|x=C5dTLb(Z z29K@dZ2^9@!DDN9J8-PzDuZXW4-Ct2Ws*4n_W=x?t0&PuIAGvh+k*CUR|;%%fWhmj zVl^4RX}_icTwy#28)+aKN5I=X9YY;1gLbZR7ZHm2dU!%kVS zD06KI21q%K%;B;I2n-kF+8zwh&0n+!_vz|O+z)OG80D-_Y4?L~q62ss zhfM7<H?H=XSx({TQO2%_m0Wt!nj}8P}}`(Ea#n$;b5B$<5``q3Af>Lc8zP zP0BhZfFs@a8$7m($pC+!!DB0!0*>|_Jga?p!|P!ylV~4JK~FhXPojNrz`(h3LHoIf z1kQmscs*4llJ}}u@jqAT-RrC#IZNmDtZVw@ z%pdS&GNXJtUZxx{%DJ|MapEFd>S1bexMad&+5ra6>Psf9+*5+vv}1^R`cKsD^{?kc zGYzld>kUkCcV>*e(exaL`#(x4F4gT8Tv8I0-=znSOShGI^jz)iF z@I<3%4c_qjjp4Eyg%3DaE(|`WHDK^`ZOCdA7&yl>Xf*e8fo;$lyq?k$9R;PWnejpD zehpf$rkaD+E>R(>hZkycxU33+fphH(Ds-v`2F~hB4a!!*O}~bytKV3i z!6}c9?wVl_Y`%pj{jR~@L1f(2Kr?NkHvi)aKz@|iMTO#cu>a)RwgTM=qcxLLELUv4;VPt zwlGL?#|vz#F!&6r@RHA!-zrAgwf?k6to543vZaTJUiCzUgXVSGEsf`2=Ct+FLxPvw zG2_(sKhjGsN0=!3Ec%yt$uk1{Y=g%Jup+=$8ay_DGlAooRvA2N0Pw~Wt}$F<02l}S z!L2r2VgTT%1DxX-48VCpVASWzWxXUYa8_T+OAZTeUeXZtEN4xu&M=5~g;6cOwNK~o z*FlF`UNU{q;e|AvLG&`+r1bQn0Dq~$V?DhXID^N*gPz>L0tU|U3cAXjM;Uya!Rv`f zn`l`dw|e#HOp)CIe30U&{+f}!4;gAcNNH5xB)rTvRr*27#Rz~n{4oqYFaMy%IVG*=4#x@X(Qewb2CyxJ@KzFkX13_r+Oq0V9@o z?Mns=N`ogj*T!V9Fp#JRo~~Wl!2*mp-^wL}#XWKZ2+}Gn#2Zt&O9i(@fFbIcN@5v) zB#r%%o{71NE~DfdbdxfUtAV4;4F->m;~fEht-)hsxF*1_Gk8|{@Su+C4VU$l@Bz2c zaEbC!FuX7>Yj2`=$^m0sTe+0p?-Ja`wIS;1 zJyEmQ`^e1W`T$M=*~NW!otT{h{LEVOfvLl#r+{$;fVSSNo0Jty1o-<59&3Lxz~681 zSnE>({;ARRh=jElQ(Ou1hP`;dB+WDM6f#A#SboIHM40@wg-)Ps_ zDQ8$LNLB=bb99r^eS@+V$hGJO+n8ne*ajK{zSZMr8$Py$Ch+K{&Erdk&)NjM8OiO2 z%i08du?fnj13~l-jM3`KB{soG2G*q1^(WYb^D6X#`a0p6jBrE z76)~cvaUYhSk+MmkF9EPfG;t4Y)wZ1$C~;Lp0y%)P{)AbvQ`8iaIRd|vjBsqE0rvCXEAs^rHzgT9eJg#*1!LsQO~nzIwC(!Hz`$|3>@oyj=_T}oY_Om zm~gmQ9j8);!DjG!Vn}-J#jt$lcc}L30gQKlW5a4)6gAp4yhP$~=?5@p&=ESg$~qs% zGAn@N6;~QO2qkx>vbH=vTQ_(ahmQp_OgV%JzVg*MV0Z#oCb3hVKLewjYe%rt+*$BL z&<3w3=tQo;NsLYZr5^tv<{5mG;ZNxZ1M$VWNm<{Y0mmv|Xz*Cj&j-!`e38L}fSpxB z3onODoB;zD80B0&LCComzz@8^>j_fhHhzq9tqQd23D->C_5dCq^Fct(-Cl=FKhe5? zZXt@xbdwV6g#mu4!DF#r1RQa{!r(!yxr>1#wpSWF5h;spXsN^Df=JzZ8W`nVJ;81r z4j4Gsw%}iLmk4aCFnC>6#F7s-J+fw|kb1v%U9!%jUUcRiOU>xat8m(l_ctN{oXb0O zlTzB70{lvY$4Yy%vbOR5R^6byxB2ucql=Yz1#~zO=n(wdeR{RgB}&DiK!XEwbtOtg z;qXV{l&=iEfZ@bkxu8_He+~?uu3ur&bYqsb!qeK44!szZ0AXqcQ@b*65!_-VL)0~u z*fPAStcd~Q8`XUJ*`PZ2a+86b7B{naOP1`PG-lWlmqE$M8GpB<66ZZc^rO zD{$2PE`!JBaGSCgnQzez_&W?A%)p78GR$kY8!k~j>ZKfJ;&6%TF$-X*(6uEQ&y=Gc zwB&F>^|{Rgo01G(Pf3YRyppC?PR(>g?f}kFe$0B;>T>C~?e3=|C}O8>Qi^y$S$kn* zhi(v#!^aAF5Il+)(+vWGF8Mf;QwTW9I$WX$O_@TbP~t#SGq|F{e1!cmj;i8{eIvG`w@c&tIs_g;Ex(S5iphuEp>d*a6!OM zG0@{I9WJqW{1Py5t_{KB-RuSooNIS*cDWA-Y_pre>nSbKkyo1Dyzr5S*w%Jg2XJ51 z%~I)o(T~$~#Ps*NNvYx!z!CZ189b=Mi4PcJaAjh3{4He=p~35kA?bCn-S~04iq{sy z0gSi2uinFW>r-?K5q-%-5w90M9pGOyco0$UGr;k~Uodzqp3eeDq@Oo<)>?t#pIw>6 zTJg`o5Vxx*YpuY*xwZvs&3#T_Q-#6nsbW_wd9Mn6cWWm9ykGHFb`s5ozV#+ikE{8V z%lY;6Q?73y0Q~xY=_X~@Pbq7Qxqs6QO8rm6$IAOAc;MgF4a)j=!^cYe7I@&_(G3dw z55s4b2@a*eBmJzCu>p*7)Sr&CP&6>+3)kkLOgH9e2S(-U3$Dj)HvywQ>q}*v1(1ox zn5N>aZwqcSjUnopNMaG*M3&Ed%Dt$L>}8yle4EW1#U8|2PVwp0{V(Viir2@7CE$3p z{!&>}>~D30Ab)T8Sn5_RgfK})k1GBdZCwelM;H1vL^J|xnCl+)&{D`^?UQf`8Tyy0sRA3JeR2HLLm#9@s zlz;cOaCgrm{w{aC-RKd8{^dA(*^=*?KW|RQ!uk31am%LD4(?gn-L)WBew_&Syzclb zNhi1(qTC$2QDt?$n{4+hy$ro(uU9toV_ z&EWO)l(gA*LR&b0B+>66oy6!*%y#~0;0Wb-gU5s9m_WbG;PD_iHqb9Mcrr*3AUvq! z1j8lX2psebAjdBZ66fK7fpg`ODTsjw44i9sn1XW032d>3!Rsk4(NR2+gpUJ?ZSAmc zzux`Lda>++-REjPF7>#~n-|$bmD9ibdphD^0$QV+lrJnRYrgPI-GEc=$TiHaRAtA1ec zbnOo6chL!LVDhuJrX!G}JP@aB1(OKG?H>UIX)P_p57}}n1UHv$hi)# zPGXn+$ZoYj^+ox6wuQUcjqkbhp4+p?oVVXXp7EUY zQZ~8{IJWT$gU7acL4aRk@YohF1dhEpcw&Rt61?H{N-LAtAodA86Z^j9(uF&;egkki=isq` z-yAw;@Oqs~`m$Hno(@nFYu^VO??~JDD*gLI3U;w1C9jwg?0N)+SG-;~DZy?4jt6q^ zSg;#`@H zn8Z{1n8dBYvN1_||6>HZC(3w8H>q(ls;upQyhk_SrwkvDmoa7SMUGv%VTKr2%6OYJ zy4dsYP}Y{q6S`sCIec~ofCo70O0U!ykHCl~T>Fw4fSH3jah~vwQs22|b^t~>*X|?= zfhTPsmM~m83SsF75TsR@L?OAIf?J?rh`LNO8zRYD@QHSti26EIM6w)hE|?2%tnLWIBGtc%&v5N z&YQ|&;~Z8xKIhLEI-avse+YR#hj1{Xuj?jdMxR&Ko}~S&ZZMZG8$LFtFDPr~^e?(W zU4iZ^Mi-mY7nQYj&p+!1K2I7xF(cFp4wHjd+T&niz|boE(`JNo07l)e?THz|llEdN zU$b&qGop>)z6vgFMiiuh*u6uh4i{o$06`kpWZmO7bOF*-Yfd3PT$uZk;AVh^sAqu7 zV|&}HDYcMV6vb2Oo=>D5e)sD2YWp6>F#5)Khp5%BdVgO@e_AeAzIxBO)@3&L&{LzF zePq1+Hl$qMirJP|=n@sjw%+v!e|50Ay}4P^h?<_W_@qr6I}QUjdrn`UgAE$&mr{q3 z^k=gJ+3b>RwlACQ$!2@A+3sw%l+AXZ^z6fzb-JeY_PVB(3|45crZs+e#}jLZ?=gzb z1q+~P{O}Z@#y~KU$xUW*x(kQmvdCW0JvHgRt$T3S@ z5%jdoG&k?C7}Dt=y+?V-p@$vsI@NK|DW|}uVP1f=%yy8*-P`WF_d~8VU8kRJx>0Kc zLm0EV%4K!mE{58A&+Y`Z926HrJshK&XP3_a#YMeoDy|*ga-SdmEv>(hANZAizt-z{hroO(|VNCulT`-AKm6hW-gxxqF-Ut#x6e^o0=O0Xwt7)zZU&k^=s3w zUB6lS6)(SR-92FtHP05LL%&Y_=IGa@-(39;((hpX3LSHnd5g{E7YWd#Up_X{w)S4- z7wdO~en;welzvO}>(_5Uzd`+u*6$eoj@2)J&!gUcnwpPOeyM)T^gBVn6ZJbuzh~)p zvVLVgm8?KuSXX^FA2~z~1AV35jX&r9hX!cfv17bEc2V%UEe+-Kge&vs!wS)Vi^QIm zsF#;tc5ZpHJU&_8THd`S7+X`BKQvPQcc}C2Yu625zH;qlYs#V>xL*IZ-LT=>J2u>U z{WksXx#5Ou@3`UGExNs4nQOPX>Bv5^~xo^H0eQ-787vs7QS zKhzmO(II2wHxBg;aqSuEUD7vH8k##Km*dQ|y|MfsH0Ut(yrMxz74@&H?di_8r{_cs z#ZLXY+H~LcbVn-N(N@(O3nkT>-AQW#D4OG>GBGh(9+hAiQ7@O|v!YnyBynr1_Zw~v zqLC^xVrq460!Zc5a*~o}<+_JR`QPwN4p6K4h)=EpdrQ++ZTR&9l z9vE7>z-ES7<(nYpQYg+HEss35ZTsC1Y%QO&{G#O-UViDhv8@@} z=H<(mui-Dhc8pAi*`x-A{gpuN_g6wT*xeOQB!H-P{+h==Ks~v%V_&sD?8da zI$XZz(GObx8p>BfLyVOfc+ESJzb4FAS7^DZw76$z*__Twc=N>0@p5qXs`@tAz6-Xw z_H&oNs?2yQue$WyTq!lYo2OJL%poeo9##2pMo~qf?wb=mwJ{2Nhx+^bx;Kix!t9%h z#W`&awFVTMmJtYvh0?k*_L$SAcKe07wJ3NqH1SoTl;F&%ac|GP*mzytFF6gY;5DL*N!jk z>Ug_4TVXw=7bUuEah`mjcVo5f;H+`f&N)0V)}=)9=LA(W=)#6by@Uq zmA6pNRNmc&?L1oJK6BMNBE$pRaY}|t8Dy(mpvp{@ zci+ok&UJ0txc;3RhIWjOuHP_p)5!SHrX3@>?v$r$>fSgsq_E1|UTV_tmR(Du2VZ}E zYVM6AkE)s8&Ynn)O^F->C^Bp98Cu-Cv3i1^m$g<|Y6F&A%R2RSQdRJC&K>!{hND~p zMF+Xz(6d;!uyFn%^A8)`r^n2g#d&|4GGR?J>%1!izOCi^G<1M!h-8yoMQ*z2GX75z2xq9{Tlx6%8 zxcSmR+5vWV)^dR9Q86(xsW~^SmE^*ok7({O(PXFUwA1j0?!x-43-2K4zUKy_%V{D? zJ8dfMe=^a207cCs!)4QyEz>&6*Wre^R4OVp8fWkLV^ox%k8AmgwqlX>z?`;Pv!5NC zmh?WBNH2iG_*Lk-`KD1@pY#sZ8byA3VOiv2|C-Z_ol{p$4<$7PP&9k|k5T3}*Yynb zG1ql>cUWM2@CoIMFfuL`%e4iG&kjqaX^q<6#E`J=ON13b(d_he@Al5KW9A^a&{V9U z$f9Q8W3SPuj$4vC0w|g@I$pkT)kPtu*g09tu=Xh&_LBlrL(fom4@+H5*OFF66gfyI zri+r86MWEAvumTgwWY4TA?aEGMXgivQEv0*j_Oz@9nRUpyhkgxjYIvtZdpFGcqr`L zc0KFllPffQKxR$v499E4aZ;>}!vq9@V=Q3iQoZ)4LUc+V55bk~+H;-U=q3DJiuK^!E&n z_Rc+YQRUu|g`j;yy#qBvP(||ERJ1+Cc;oEWE!7)m_F}%|wLBSN0ThDVo?h)*FqF06 z8fOyXTusGLZnlxEL0q*|uum+gf|HU80w@gO$!AKK&Er09y9*DUjj7WMBsIvwyZU4c zM#^U^@Wu^I+BI1#@2qk`VXf?g&guM}R>oLwPa-V)Qinic2X*!873It_%w*fEXR=`zE!vob3C8;`-5qYXG^BJNS-T%hZ&9wMnrLJB>C*C(AoV;;?(XJRz4dT-}K| z-iEa#mUoh-YdmkVuS=>k?@2lnK(>#6{igMEE|u>~KV$L3NTIHqMYKut*P^KPC~T37 z&DpiIeIWu;1>|}XHO)4WefU)E*^;y;fU?3JAFg)E5-wq{Uk#{+nhRMC6+H5lNe%Xu zU4d9$h6#WTQg-FCapyj5S)07NhZc8tcW-0@%Cg*-olU=;%giw~IZ}SW9$!=&09(mn z^^-_`54Mu+v(ggCMTv|8DC!s;OPStCt@WNZ62h{wdLvK^j9tk81qtr}iVk*D?^I&k zW99K$HOz6*iJY?Es;&{I*jMINQ8}q7fTHHdcI%ngqr2}!Xwi@;^iJPoto%tSzuLS~ zQ?b0~v@0A9M*26HR4a>fD;&RMo2p@1CCSW5K=ThBuQ}weB^ItVT8sNgo0z^kL#a%f>%z>8-UPwSRNr+^H(*)N;dK zE`G1Nwp{qrO_Ixx6o~lEar;X_0!5wL`v}`=-9!C70~>jckX7=&_z>^Kd-|6+FWy)x z|CvUCT`FeS>PJ#I^!S<7^pB+MZ&axhPbU2eph(-N!Pn|+#q?TtQ%B8*sj?lU_D>0S z`=e+`trcq>D^Km(G5j}G;@YSEsM)(x?X6}1`#t;Act|%kyt%6NGTPJ*YOMgy{`Q`v z@S#L70hE3cn8Yd77S-W4a@$iG4KF#q3D?H5fCU=kDq-LT%pusi;?Ii)v3dG3b6M~qisEVOzCvLc(A4c?o)hQ z>P==SR<$Uld2abXQ3{s|rR;Nb=${DmX3Tcue^w3D{S6M=6f5kZ*a!90ljqgT4nM8d z6VKF`Ya8tD3lFzzZNsEUON*aj@2SwTY9lqA^P2Xxx~gMeEsL#(I?g;p|62MawH?>3 zziAocrs9l9`ozwx9&yxP2s>=SDLM}@gMerCiFj_;(mf)cJ*qvi2e#k2{k~mmSD&+O z2G$)TqF%k~^2>+MS#jC!nd#fdL~l>GXQpk_qHxcQt<#;7aN~E7eT!<-Pd)hY@n+36 zuohgV@GBD67C>%eq;E(%a_+Ugvs9`W!N<6@O3fh9uQLrd%^H6fZ#l}bzBH*lfL!g} zLxTryt=z_AxjmW|OQr6i8+7v0Nw|9>`}5g(ORj6*o{-y|)jPDfM?$UM0@$Z`v{lc^ z+@|){`m?>CFMFxGdZOxPlgO=R;{(ceL{~vy?ftK@@zHVAcV?o#0Me1GWGbkA24J6N z7<-cK!c~^$OfZKonm4b)EcM*nj#nqqu}*@pF<4{YYjjfIolz&2C7lQ$w-Ozzc~Eel zG!`!X-%}3C2T#iS9MstyH_PF?%k^r7ToPs37et!s)S8BdsD)k`Q97_wE?nM z1sEuMRe%ArR|Ob2dsTn|v{wZfNPAU)0ku~J7+8B#piyGgYYeZ^7)n1PX_WA4fhD3^ zUcmktdaD0`&N z1tOh`%BP9aE)@ZZud2?2+!6QGc224)4~h<+NS?EdlzGK!jQ5&|eU=wqSn?t z4@#4org;!P=@+j5Eou0D^8kvPWU#diq)7%_6E1_T375gvgv(%S!ey|v;Ik+G5T~QU zGQIkARKTQ9M+MlPzssdnpx&VvsPzuTL49c*vS_M(q+$Obo9U%EHDXDvMrf;6sJ@!0 zeo#F%QG=j*YoQL(DdrI4_QXrU6RQS;+r`ofxAv0>eVj!u0d3K1@6_gBeRrfS&l#)*bT0)} zP&zBG06IZd0G${sfKG@NKqtZqpc7yP(1|YtY^LYDnfUBPdIsZdqM=HdUQ#+efwdqC zdl74S6;S7>S5yG)-S*)MpuOIHb^>g5?cuGBRTWToPI^rR)SWszCxKe)dEwe#!~U|j zVW&6FOWSMh0qita1$Mft0z2(hft~)Uz)pizV5h?>u+w4{*y*tf>@-;gcGP?{qkup{ zFCBFSxK-cIK-l498IHJBpU8BB_-Mmv3CwKGeFR}`0xk7F!&~EF#@xSI)Sg`E1(4+QU+vAYcK6iP z&TG|r;=0cDznOL-QUe!KayL&*r?FP=ARXsOev1Wxec`~UYfZWcT&a({*R}p;f`+Pf)Oz7Iy zuCZOUUr!^k$Ph2UzWU7AexD2QCs_L2v%zdk&hDWL#^d7{Y`xnVBI5M$e6vao6MVT= zn&$0zZ%hFcUij4BO0^!`Q}EOqm(#tDJfT-BsoL2Pe9VH#|O)R2kWA#BY);9jISDm$?Khaz3kgtE7Q0kffA#TmEw9eND>`Xw| z)OAllbc&;v1#qS_ym;%rClZ^RtgY5UaLuTF^x!WNOBnSaqTyIrc&zH-vri8U6iLTy z^+rVvw)U_<$6Gkb=RVZJd!w}<7HC7j4p;wq(t!X9=ZO0`pjV6SI9~_U=k{+JsUN1%6hMlZqMq|%lr2H zSYOYX%Oup&P`*LJFW;g|50vejHRI)7lkW90LhEY3a6r!a)EG{Sd9SD1zBz-K zd~c!FjH#8Q&6q0^^9!Kxnw~~cdfuZv$lZu z;C-fsC6u#>+?5Mo>|BngidyXu^!@j5+0B=%qUdzH`lHbwa(_Q$$Y2L8sWbw{^Jvwk z2ye~ErG^h(C7*f{aJt9IYu32K(S52ZoPG5m%?^o_YkQD=QeGp6Lr2b`YlW)7NXHs& zv}Hc&mFw=%`H$tpm#fLY>RNaR{;;vLe3n3V(aT8gi*sk_ zW|vfUS5bc=RebLB=@y>?e~aK-mEPm=cPo9D^6yd#-RUZSyH6=k9(q#BlR{59=t-dq ze7~>!9mc@M0eW6^yLr?vo9U%{XvoBA*p?&m=_K^Y) z{e05HNr98n9{NE$prgH{)CV3oDR5HYfu5A|8`W;=BZV(1aO6Qb=qQJN;71Ca6gc$2 zNr96Br#x^{_y_q0_}zj#3+e1Ubu$^6{!c~tLft<%A4UH}D&V*nMvW`WVUH%?{JfRx z&Rto)bU4>N``wQ|{K3bz>ur-Q<;S+~_Eh>l;P=GnAu+g5=_{3fU+GdYdQ!YDS4#f5 zJ{|Jub9{Q5Pfzvfvwivr@%fR;y+~=)w1My3xy^-KszvGqbzGw|(C$>aUg=h)u8cmu zxj+mm%1jA;qi86*-j^MtOoP3bYa^&__H0H@{s-bm-{|9uX-i}B#lTrzj;II`$bR7` z#0cVb%Kw>IjKH|jeXS182Oa7P6_$8n3Pb#-fw&l+^E9^V=#{7nkX#^=muaB?QYri| zR2ntd7wvwwFy%z1n7? zZSCk#K_}XaMMCo~F*fwZzUkH8>1c}JULo91)Rg33fDf}o! zOIe!xAhbokCFh#Z*+~-`VfR{*U^SB>;cw&8qhYoBX{A5*toYVJ4i*J{b2MrP%vhl@{BK1 zxiOW)Ft;g1`wfo7#QEB#ig!am_I5W~Bb9-)esDdq26 z-f0!|Wh!W+0$j~OzD490D^H8xuJjt;V$``s`7^`_k$+R^JC(Nj27KCApilRj2&1N+ zOhqj)#vI%C~t2pAZ}oKzD@T7b=fv_q9!|-aQeJY4`;JmPo6-p7s)m}t2 z;3&~i(T@a=no1dlEg*g@1PtFH!smNN6#NUpNpbJ5S4xYH@D;vSDI)lWQe>_#HTR#y zqf`c5d&iE&WfRWk56807U2}!qO+I^o@Y{Bfjb< z;(fDNyjyjZXhbt#5vZiN!c*L2Ja+o;4A^rP`IAqpmJbW_F{K|>%3rD^#)S8)RC2y} zFEQS`vLy>p?(&qc_I30d<&G?65z6<7@-W|3c>jejF<>R8YLpoFykFxf2bIDBnMBPK z*%A#e7Umy>p{@yE^0g|lLhyf7o_-u{bxmeVTI;5KiP!nMj!}AeT-SJw5)b;6h5nO|uYl6ZsXaGX-7c^ET$w%&Q z_a%>4dad%eDW(7aTlk;Ji+o;bi)#9e(se5LF{KQ(4=Q!GlB%hd8r~!h7mEUS!n}n$ z!Ma|h^rxO9H9P^{*Vvq@ftLM1aNG?+B%eCB$2@8X{5J>=UmWaW@8^g`8k9d)={r;& zH%9#S8qw3kPbs|~`q1(w|Aj!Cg=Zb19%;sWP*^4=X3p;^eM))fLj2nqj{3+Wq0T>$ zqW*7D)7J3#DPJAsg31J)rxVZ;vXK&(krHT;UgT3E8}dXeq(ma5uUC4t(oH_yuFe5p zr1Vy$Z}jjhl#;*BryG?XqWtw9e}huW-RRS9m4B)74=PXkmma=VDSWO`O1(e#@DQ*+ z;`0kt9{dlLM_JeUJb?)1Z})VE3r@X<`SehqF7W9gKArE=c|JYZrw93Tu1~vsI>)D- zKJ8FSduID|mQUM#+UC<%pSJk4*{4lD{k_@^pWpZt^C16!efn=c{jN{HuJk_Pcc?t+ z2b8D3F8Fs}@-%B|Kl*6dQIvnVESaDj+e0a4`QZWm@lnIGL`C$>oPhEP+b$6EHwsQP z&4?hHrd<56e`%DzO>m3>`gNj@Y!#%>)GvqF6QETHE{X}l!+lSH`9N?n1U4r9F#(Uq ztiWGr3aU*mKn*RY7OHGl0Ub8@+TDhC#>5$PB_7+`18*60cx8Rn{>Fus3@YEAfOY7 z&E`S^m`Va#34u+0{Ar3x0=feMGoHmRl?3#gHrRyLq{B~@1PBNY%wyu9zu!PtQjJ8C z5HM|7>{3a9$RV&mHN2i;R^X8!_?H=8-)67CBS7#kH~eT79{GVkAG}6>au!Dd1n~+X{>G0U2$B;# zBKW)?W)NOtHRwQzP6sn4+e@dNX7-FjVp({&(rZ;+#Ghvo(Lww*A~6Bast$bFF`1~u zvj_u!hQm)*;#p&XU*YiMm3Wpw;LmjUu}VBE9q_{rKT?TjAp-tvhaauPv)%x|5_~fb zHa@-N9U$`>VtS>gNS$O-sPHnCWk!YKQcsaO)#NFdYoWNzQ>4zVNRG^=*9pVl8hQwd zw)jio-EK3Xvpg)YT`Zh=opJ;}teaWhGTOJOj#SC6j`zVz4Y*y&t-7bFS3%U0`8>M5 z>u|P!c8PZv-X^*WL{G%_ePQo{S9|&uNAuou$}1_#B`*3?6=6j;q9OxAOi;8nd6&|; z{qiabayQZ`wL3>b7z}XH|4&q zJbfeFgYI6z`R@A3N}o{rWx>;bRjl!|0{*jr7}L8&H10e4E#>c1o*k5TDrF1jF$(MN zKaD)G``&MHe|%KjtjfNxdlt5zQi^vW#`~n_i}y*>^O#_x@X&wO(-RwhCZV55)59Nn z7VUwam=b~0Zt?pvXs^nTr^;J@DE}$XpK`>s zEK;do^kXUdM#4PmIWtucu`um;i|AQ!Qtm0?saNH7_BEDY%UP*%#L^hl9ZKmp<)>60 z!(-nE!$YnZ8ttL|Y-M`AjHdWDv9k)Cc08$+T^P#KA7b}+2#;Q=@9zXh{_u_XGgC_! z1oggDkUIsY7@|B>|4GO?AstSkuRwrXE{SHkiX1xMTFEM^1cf4!$rPH=x+*5EvGAg zmHP6pj=U!!x6OMNS8#{yDKYdC>8&7JBsARa5f|j_EALLo>`?&*T4KI4oEmQ8wk~-u0i)VK5iN+ z>E)D#Lwqjvza4S$c!_zr?ynLta|9{ApA@IAKlId7>fN-NTk-yg1cWnV3y2s$YFIMR z-@VC@LT?oK%>s`o#b-thJ&OmsHiEr#rKF{gZvqOD`&h%7$# zEoK*}D63Ay`g&+eOVH?zH!Z#Kwob+3n|?`)G;c8$wu;~jO3zdJRWW^B=_{4~AEi8) zU{b)?Z&Au*@%MtiQ~B>GeVfu>C}k^+iHfZ@CaRMq5hkB0;lHBv&B{NZRE;(L@<%gH zC$GkyDjZATSNJ-kQeVx+HnL*ap+?*x!oOAl%=KTC^5?vAzHz@+p30fQ?1l3hy*5T4 z5CI#U+f;C?XNcpVm-w0A2~SD|5g##`j?p6`pd}P&5Ci7ON#AY8Aq?5q|1FGKlP~f; zo4m%`PgVK-qPbWpBEQ`?CMqmR43YVj0gXp=UPLEi5}P_m8|k_@hk|y2o0jP0iB~YkKtb) zkXpaw`9GnQxPw2;Wp4u$ns;VSx2 zq++&_7#iz+ncpbIc;F?SSC+{i>1h`zHMdjfOLYAmm0=1XW-?vpr((asSi!XM{}@(O z=t&CVt#IE=%Fal77BBAJ6g<*4p_v5kR?1WpHS{e>*$|~~6Z#CLSJUpc0UfYe=+4qD zYZ5@*=`4F-2nK00XTBBUj$LErRp+i)zIK(ix5IX+;CZ|mkpT{vP&sN%j@<^+{JPf_ zCW*JfpE|qht!hHPNnK}*!SIJv-8xli47P^=gIh$yE}8nGH@7g*utVkzl-eM=#)!JB zEF=G6A+ZFAuCv-ksc)DZVaF_L&z0dcPiJGzeV$U)v4H{{@JUzmhT>c^v&`ShDo1#v2HqEoUv)7Rpepahs zKh}1u@(eSYA9eLi8#&}D%t{x#LIxTh{qjX&^sHBVna95>^Rro54|4d9+0@z-1=YX& zJYi1IJ!-iU1|5@AW2WEmC82)brEkju-YE*Ygcze)C4D?&Vfa{-k7e>75E1GpflkbdlP>@nem+ z4I898;x!IcY7a+LPkD_)MQ5YJK&*roT-WCW{G{O5tHNWHM;S~*H1lW`LMe|6&$Rjz zG5fsoO~Ui+txtXZpwg&)=T0|c$6HXUT7T%-wjl5>#I&H38+N<` z%i|!hP({Vb3T%tVLKPJ!DzL2{3zei%fo=0xs3eUFY`e!oC23S(i8yE#R8j+hUhqO} zwy_WKE}0Q4kElU^t1gKE-XI8DgDhvv;WhN6Ym=LwhDi%c;Gh8JvZpDeZ?&*5>*gFU!tmrZqHW3pH@1dl!bvhP*Uu37q_x# z0wdNJ_bVmT7dkza!j0#{9O9zk-xG!HPB!%S^~Hm-p;zE3p%LN_#Eq0tft2Zr)MAka z{b91Wtp&tGl>Tm^Kj2eqMAyLd{cjgBvpW4ZU*4dgDsD=?RV`(l;}@9j7#X|PhVIgz z-}#yz0o%?RTM?AL<*;q-0zs-L=?>P=uN8{)bxQA3dXrKXdl&fpt9)9L6u=+v)8l-4 ztWS9e#N>Xo&ky=^z^DBlzeFj)z?f2nH-sBIRfYcLUm&UN&^=p4&X}}ZjfI;3xp#Ox z`Zraz^i{?)w~BrO?vRpQhU`s{)ESWM>M06Okd%CjFUb~OROm~P zlnhAr>9oj8kd$PGrp|eW97vFq49NM0>`#!CWTaA(jWbCoK~gdx*&d4uixVUz8S9i} zQ%n+CoRLsKvIQmyB}huLjG!bNUYe~FBy|QP+gp-Qf}|u15lXVDB?%=+N(LlbS&~qK zq~xS8d81OTT?doM*Cwe*Wr&Duuyst-4rFXj|DqT$YArsqY-qhU zmN+HiG6Jj(qNQSu=#&^|5$P7b?m6U*6qAfP5Ff=sD;%rDd7+)fe$Gm z4k^J5DPapKVGJpO3MnB8DZvLRVFoDy1u3BeX}eEn`E<5Yf`(*R*bdWUVp|gCA)#5q zVEiJhoO^#QFlu4?lijD5m9`gpzrddtdb3qBSc#q#_)ZD&uN`yHqfq);Vnp{mgL8Ec zq?`DVN_||V&J%NDY*LHJwI7@GB+t^8sQR^HNt~ml4wbx``cw(i>4O5VR3!u%L`M}H zAa4;EMdH2{_N01Xp~?d){Ssl=xt;KBBG^EDQM3Cf{bW3F*9-Hn!mv~8I@OnASYRBT zBu4nTts+CPHp`ddcwz%zuw8Z<+|?X*`EF4GmQ&XVM*2pdviX3%Z-BNzM@PDrx%n}7 zoFKVHLNP~1jiXg_XIU(nJ69`J(SfAs(ohtVsBxsKC{OMwy2ce!?-8|2q@XJHrTky6NxfHb>m(nGTpvNIsfayW;SLe2?D z(;{b(Qpm1=G+l6ZI)$7YkS6UWojpn+4+=;V5a*6k$b$pYL{JD{9g1>?2gIM4?DYMi z@a-Xus(|}bhZ{}ddIIjxd^r{LhnRA`0rz}gE`?hhaDNVt=cN9#K2h$7fO>&L=>XZX zKEb4fBLnJ%4yB`G0d-VBy~v?-Xe^+X1k{TiYDt3X4=6k1#7K%u4FuGAu9S|51%`tG z^-_oGO;AS%)XN-7$HGFXV*<*~Gw}>EMjaba=ToYf?C9rC37B<;Ngi+Io)a(^I86LN zA@|&XxzO5>+V0Jj1L`7=3P&NM+!+CNv7u6DrE+Hm)Fp;WowLfF6;Q7L)tEXv6y;V1 z+$#;2-gU~Y4!BDVm)>j2Jul!c16O3HR;m8wekPxp`-<)^2h$|0;S)lj1ph@qzRDp7 z)5u>1me84y2L43CPzt8W|xTgz!d(ETxgTfP7OZ$!C*HKv6CqkZ%qpQ^;aKUI9`kQ=ZWGi+sU` zfP0I>O{H*60rysin@HiB1MY1OH<`k<1l-#lZajr+4Y(^EZY+gs3%IKsZX|_k54fux zZZw6P6>#qW*I+M8`tHpOsB1h*??igkApx}>RFUKQ9&>2GY%mN@dpzdUfVmb-qdV#5 zapwlyb>KRtrdgS>=}lNqtn&kOzs+^4((^_3G00j5!9BKW|3{7Zy-Df z$P+ehQd1j5#A5Kdh47kRQ`CG&v)si3T^bM7rQtALiihh`Sg1>WkuJGzU7{j!jZOP1 z^kqG$XnInY#;@tp@RTmaZ|hR{t}gli&?Wa@x(Z>|Mol?g8uPj| z6m%&TbtyFHl5f-{*Q867_cMB1)cQ;1TYjZW^RIPj`i(A)ztyGTce)gRuS?-+UGicc z<#N`du4T`*)3TDyT%no{)}?WtE)DZ_DITIrVSz6BLv_g=rc0E+=TVF50W9TsU;C^w zAC|F8A(Eo={?J!vH0MN7b)KY4$Fp=Povh33Q*@d2Y+c$<)urt;U0R=`OUsZh&Ck`P z>2zHh%epiy*QI!dE`=4kS4H>`^)*=m)~F29h; zDAzirrzmBeYQDpH2DQ6g&y)n)Sw(H$wW$&i6;a%Y-s)bA}(W+G%@J*g)v){#=wew*4idy_7+HtW*5?ywO~#D$yk;Vmnc9)cjA*Yr2u=@-;!JKQ ztR(js66F&?HT1-`q(&EddYq>#Ma4^1taO1cE$ej2ov({F4`aOc3i};L)}{Rey0kr_OY5V$w0uyP=D*aX>92HY{NK7X?AE3D qAzccO>5_k3m)sM&sK&)f?fuDpaVl6js+tIftqlLlN4|Pd;r{`jh2zx# literal 0 HcmV?d00001 diff --git a/CPLD/LCMXO2-640HC/impl1/.vdbs/dbStat.txt b/CPLD/LCMXO2-640HC/impl1/.vdbs/dbStat.txt new file mode 100644 index 0000000..0a575a4 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/.vdbs/dbStat.txt @@ -0,0 +1 @@ +RAM2GS_rtl.vdb diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.alt b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.alt new file mode 100644 index 0000000..4bf1035 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.alt @@ -0,0 +1,75 @@ +NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * +NOTE All Rights Reserved * +NOTE DATE CREATED: Tue Aug 15 05:03:41 2023 * +NOTE DESIGN NAME: RAM2GS * +NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100 * +NOTE PIN ASSIGNMENTS * +NOTE PINS RD[7] : 43 : inout * +NOTE PINS RD[6] : 42 : inout * +NOTE PINS RD[5] : 41 : inout * +NOTE PINS RD[4] : 40 : inout * +NOTE PINS RD[3] : 39 : inout * +NOTE PINS RD[2] : 38 : inout * +NOTE PINS RD[1] : 37 : inout * +NOTE PINS RD[0] : 36 : inout * +NOTE PINS Dout[7] : 82 : out * +NOTE PINS Dout[6] : 78 : out * +NOTE PINS Dout[5] : 84 : out * +NOTE PINS Dout[4] : 83 : out * +NOTE PINS Dout[3] : 85 : out * +NOTE PINS Dout[2] : 87 : out * +NOTE PINS Dout[1] : 86 : out * +NOTE PINS Dout[0] : 76 : out * +NOTE PINS LED : 34 : out * +NOTE PINS RBA[1] : 60 : out * +NOTE PINS RBA[0] : 58 : out * +NOTE PINS RA[11] : 59 : out * +NOTE PINS RA[10] : 64 : out * +NOTE PINS RA[9] : 63 : out * +NOTE PINS RA[8] : 65 : out * +NOTE PINS RA[7] : 75 : out * +NOTE PINS RA[6] : 68 : out * +NOTE PINS RA[5] : 70 : out * +NOTE PINS RA[4] : 74 : out * +NOTE PINS RA[3] : 71 : out * +NOTE PINS RA[2] : 69 : out * +NOTE PINS RA[1] : 67 : out * +NOTE PINS RA[0] : 66 : out * +NOTE PINS nRCS : 57 : out * +NOTE PINS RCKE : 53 : out * +NOTE PINS nRWE : 49 : out * +NOTE PINS nRRAS : 54 : out * +NOTE PINS nRCAS : 52 : out * +NOTE PINS RDQMH : 51 : out * +NOTE PINS RDQML : 48 : out * +NOTE PINS nUFMCS : 77 : out * +NOTE PINS UFMCLK : 29 : out * +NOTE PINS UFMSDI : 30 : out * +NOTE PINS PHI2 : 8 : in * +NOTE PINS MAin[9] : 32 : in * +NOTE PINS MAin[8] : 25 : in * +NOTE PINS MAin[7] : 18 : in * +NOTE PINS MAin[6] : 24 : in * +NOTE PINS MAin[5] : 19 : in * +NOTE PINS MAin[4] : 20 : in * +NOTE PINS MAin[3] : 21 : in * +NOTE PINS MAin[2] : 13 : in * +NOTE PINS MAin[1] : 12 : in * +NOTE PINS MAin[0] : 14 : in * +NOTE PINS CROW[1] : 16 : in * +NOTE PINS CROW[0] : 10 : in * +NOTE PINS Din[7] : 1 : in * +NOTE PINS Din[6] : 2 : in * +NOTE PINS Din[5] : 98 : in * +NOTE PINS Din[4] : 99 : in * +NOTE PINS Din[3] : 97 : in * +NOTE PINS Din[2] : 88 : in * +NOTE PINS Din[1] : 96 : in * +NOTE PINS Din[0] : 3 : in * +NOTE PINS nCCAS : 9 : in * +NOTE PINS nCRAS : 17 : in * +NOTE PINS nFWE : 28 : in * +NOTE PINS RCLK : 62 : in * +NOTE PINS UFMSDO : 27 : in * +NOTE CONFIGURATION MODE: NONE * +NOTE COMPRESSION: on * diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.arearep b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.arearep new file mode 100644 index 0000000..e4fda17 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.arearep @@ -0,0 +1,21 @@ +---------------------------------------------------------------------- +Report for cell RAM2GS.TECH +Register bits: 102 of 877 (11.631%) +I/O cells: 67 + Cell usage: + cell count Res Usage(%) + BB 8 100.0 + CCU2D 10 100.0 + FD1P3AX 29 100.0 + FD1P3AY 5 100.0 + FD1P3IX 3 100.0 + FD1S3AX 47 100.0 + FD1S3IX 14 100.0 + FD1S3JX 4 100.0 + GSR 1 100.0 + IB 26 100.0 + INV 3 100.0 + LUT4 122 100.0 + OB 33 100.0 + PFUMX 1 100.0 + TOTAL 306 diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bgn b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bgn new file mode 100644 index 0000000..e34c8b7 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bgn @@ -0,0 +1,86 @@ +BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:39 2023 + + +Command: bitgen -g RamCfg:Reset -path D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf + +Loading design for application Bitgen from file RAM2GS_LCMXO2_640HC_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. + +Running DRC. +DRC detected 0 errors and 0 warnings. +Reading Preference File from RAM2GS_LCMXO2_640HC_impl1.prf. + +Preference Summary: ++---------------------------------+---------------------------------+ +| Preference | Current Setting | ++---------------------------------+---------------------------------+ +| RamCfg | Reset** | ++---------------------------------+---------------------------------+ +| MCCLK_FREQ | 2.08** | ++---------------------------------+---------------------------------+ +| CONFIG_SECURE | OFF** | ++---------------------------------+---------------------------------+ +| INBUF | ON** | ++---------------------------------+---------------------------------+ +| JTAG_PORT | ENABLE** | ++---------------------------------+---------------------------------+ +| SDM_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| SLAVE_SPI_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| MASTER_SPI_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| I2C_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| MUX_CONFIGURATION_PORTS | DISABLE** | ++---------------------------------+---------------------------------+ +| CONFIGURATION | CFG** | ++---------------------------------+---------------------------------+ +| COMPRESS_CONFIG | ON** | ++---------------------------------+---------------------------------+ +| MY_ASSP | OFF** | ++---------------------------------+---------------------------------+ +| ONE_TIME_PROGRAM | OFF** | ++---------------------------------+---------------------------------+ +| ENABLE_TRANSFR | DISABLE** | ++---------------------------------+---------------------------------+ +| SHAREDEBRINIT | DISABLE** | ++---------------------------------+---------------------------------+ +| BACKGROUND_RECONFIG | OFF** | ++---------------------------------+---------------------------------+ + * Default setting. + ** The specified setting matches the default setting. + + +Creating bit map... + +Bitstream Status: Final Version 1.95. + +Saving bit stream in "RAM2GS_LCMXO2_640HC_impl1.jed". + +=========== +UFM Summary. +=========== +UFM Size: 191 Pages (128*191 Bits). +UFM Utilization: General Purpose Flash Memory. + +Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190). +Initialized UFM Pages: 0 Page. + +Total CPU Time: 1 secs +Total REAL Time: 2 secs +Peak Memory Usage: 245 MB diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd new file mode 100644 index 0000000000000000000000000000000000000000..f841f9031ef51586d90adaa5aa327f17523d9888 GIT binary patch literal 194841 zcmeEv34C2uwf;?qwCN0#c?uM0OF?ooHbs;)X-gz+O43qBV}XKU2(zdt7Eurd6&2B^ zGKk`c^Y9!{ad--f$m1a@$dpz@M3Sl~Lv#P%x7J=~?|tsMfN-1AKllEAJ6UJ#wWqb$ zT6^u`?6dv$Lqk>d_x>O^HaE7XZE5|I-rNcIy!x1`T-6&-uRp%7F4xt*^oZ{I{hJ%> z4r$M=IBfCqJdlk!{I=tt=ly#OCFF9GI=dIH?CtD0VnMzNk2Qjv?2&cE=F(W9tx99- zGie)$osgz&B(^$@Z6bDj8rw|lxHPtfSTG5HgZj=Vc1#-EO03q`H(07WF-2OR+2DF< zaJmuol0&)?_0r&UBkHBW=|y zxIrp5ImMg?so116Rw|a3oCc{_n!OFu6UsuzrkpoPgVT*@k_M+6(IgE{H=-%C zhns>P_EiX!$|D1v^2k7?Jkn{@_(c1bwJlxbY{=5K{((8I3+m=Vm2#@I z#%a4t@=c9aoH}5;TCbXp)6YF8lP_w=o+Vz``YiFn*Jp_r#y(5DaQ0c^)xealzwkDd zKH#2Kza;n6E>7%O*p?}DY9LETtJL%$ahAxc$(&d+TBW9Bv`S6MXqB2MI%v0cOUZVt zfh}1zwX~(9MJ7u}t13oS3q(?laOu>~&QvwarBe%2C-ih=O1s+WlCi?lC^q1z3UWz~ zss)b{2W?hMUNTnrSu$4GSu$37I*JV{t=bh=I*3-~DjBW1RWe%Gm9pqFx_TG&wJ-1O zTiUj~Z*gbWB6?q2z4482>^t@BHGOCIpES^SV*jaYWOUf3`;0Ybtv;uJ;H292(+5uI zKd1ln0g_K@?_RoeQBQkkTbIz)Ebm+g>D4hYgbQja?zNHa;D?|>l9CH2Dtg0!5dOCAsu@j>`JexSX*tv428 z5uiXu(-PDmLX4C>E@dLU4I;hc1{SYcBw6|h>9w(4i#k$x6;_OT+0w4V-sB`c-3Xl_ zOzA;#)s{3HbmR*NigHkKO>#(Utj-`NC-G@<)47C?cg#w}RkST&W?GnZ{PXFH;)SI? zJ}qlH>G1JsQPb&%k55aQj)6WtEoeF=@$qQ}>nP~s)BM$G%A}r-Y-Q7NFo`Z|y$ER% z?HZpjS4>sF+%$7^C`^*4d81=t5}js^PH&RvG-q_4lSHQ(qZ6JaI?b0Rsr$Hro_5u~ zL{*x^zK-i@?>aQrl_rr?L>!t@t|qal$SSRMO-{voOi>fYNf`m-(wu2_D&AwpA*o)o z$m95)j>DE764$R;bX;O|wDf62%c}=gE?$~$ZL{b{HDl84Z59qOs<)#vRg~0Uqq-$3 zX_+u7XqoHOBwlzG#JgTi;)P{Fyz5rRuQ+n~q6Na3F`dhjQUxnaF)Z7y*ofGpOHd2{ ziZc=B6{Cf5#b{w#Fg2SX>ny8#C}F zSfE2;27L(@=*X8rFDyv#i5z4Lq>gV1bs`8lvCF`h;DTF5E8>ohUm5w7;DU}<8T6_O z3%#WgxzzD#Oc7eez@ZZsWGkPJLPdG#=u?bVeM*<8qfIfja=nPUMC)~MDH1&$T8f#X zBTELpga~9?868ZDbJ3wB17AV}noHOM9YZqmDZzy1sG3RVMYb@(My4>qMpj^QZ|4%3 z6)s=d!&&2m!`s{Y2G*SOmc7PYf4~7iyvSeG8dK5vCwaMVN*#9bpE-RtQ@oY=bZpVOs?5-E5Dr1Hz67J0a|hunWSj z2)iNdj!=uR2g05Rvk>+|*c)LVgxLsl5auH6i?Bb!D-g(tI)pqzJwgKlH;kGP<|DKs zEI>FA;gtvnA-oFV)d&Y8v>_}+Xh-NkScI?`VF|(^2%QM8K{ym)8A3P0a)iSWdJuXM zRv@fII2>UW!Vw5ZA{>QqG{P|m$0EEIp%3A82&)l}LpUDc1cWsRCnB7L@Op%Pgp(0Y zK{yrRG=u?!(-GKDXCj=1a5lm@2Kw_aeLx;r$3#AbbGfg9sl&xDw&R2v;F|1mU9y z|Ap`|gpVV90^w?eYY?tQxDMfy2-hQg3gOcTHz0fl;j;*zL-;(x7ZARPa3jK(5WbA? z6@;%Md=2622;V^XCc?K6zK!tT2;V{YF2eT^zK?Jd!VeIBi0~tXn-PAD@DqfeBK!>D ze-M6-@C$@n5N<{ICBm-|ZbSGr!tDsZLAV3qe-Z9P_&Jb>^Z!b1py2BVT3;;Jc95Sghvtnitrf1-w+;07(y6E*nseN zgnuCX6X6Mje6((p&DTV!bF4`gh>dK z5vCwaMVN*#9bpE-RtQ@oY=bZpVOxal5Vl9y0bxgkoe*|L*acx%gxwH!N2o>E17S~u zSqOU}?2WJw!fb>&2y+qkMVN=MAHx0!uRu5ep$;LBP>;}n(1_54(2UT6Fdv~6VFAK{ z2(Lsq2;o%-uSPf+p$%anLOVhS!Xkvl2ulzSLFhzy4Z@)aT?k7NmLYT_EJrvDp$DNC zVFkiUgu@Y5Asm5lB*IY$MrYb z6ogX|PD2<#I33{(gfkJ&LO2`Y9E5Wb-hgmk4t9BQZ(no1uCK2@5B8|O^M4oto&^!p zU5eEwoY2?Umj^S0$RIm#Jv#zj5k#c2iz_iHsU7+%NaXS8zW_fisvG(>i1TUUDtkO+ zBA}1+Dph{mN}pHU$T+XKjWw9up4HITFh6Fq&k7=3vRb8zkDDI!N}O4W`EhPRs<`#3 zRB>6p-f=TMK5l2snz(C%8kCHPJ1teUxZczH^N`q6&poGa^$92UrK-`7E|55(h*&y~O zHe|4CTXbf~barXV7)=XuY0Rf29}LM0L)anpX<;yK3C~#JwNh*RnTSfkS~4I**t5na;j6HTQf1iYwRn)<)Xstab9&aSKH*KsJ+5T+X;OcZtrc4Q zsln1VSk{=2YbVkZr``$z1+i6`$Y>?j>d?xTIG-9~!J7GTJ7f@A?xYS9es<66Pt4=UJP=d2oWYx##iM6|Ym;}m~BujL>9Cg}nw=DOPLwhd9CPGs(u&&&= z4cn=irKANzRBTSR2Gd&22#QgS&8Jl_9#y<+kP_jK1TcEZI5EfP?O=CK*;A_hOK3$%wd%cYx>u!bKYvxt4$UbI6!C9L0P$ zq*i%q`Wv#0Y4xg}j=ui5M8(BCq`50L#kB0jSWO>Gmf~W;ij7yj(_J=iE&uShlUdoY z-_!+V^jiMmPqUBpT5&PoO6T`%Rl}5C1eGPNuEbs7kg;s0+L^^NPSWb;J3CT} zqj6E%ytt$t#X`3BsmoU10%4t`OG{+qvWAIiW}Bo>V=I`lDsks#IRUA;y?5%wzQpnjtJK<*<#NI?$m(rxcVb=f z_&EO^ih3ezZ07KQC8A=B;IoaJ?eTGU6c?8@xtQ3W<@s^>Cz-&-T3eiLONJ(pmn~V7 zMwc^A+Q4;;C3T7xin&l@YWOcMvpJ*8VyZ0j;p92)GKYMw{>n1>#ihC-jLNf?fB16+ z#H@74*vu5?m$e2`OqC^}u7KD`IAqNG*dEy=nl)d`Km3VcW=-szflF~zz2=ys95joq zf>%me#)~zcg4EzvSXqm;{KKD5MOAKyo8xsN=D5elOrOr9xP51=KB2FrudgK~mpD## zbPKj+!om~!X41!nkiNMTeG}>9!b#s$ioTKbF>6WRSc<-Z^fA{--%yIap7gP6L;Cts z^m)?9T}1kPDSB)!wWPdm($~fGlM;T$RiB_oq)QRUd{N>Q=Y7sG)0H^Ic26Als1m1m z?uldBQ{oiEJ#k7IrGY7Kd*axlYtAWFd*XOlP~sGyCt!(~Vjc;z9ElF4yN2#1l_4&^ zT8==+eUXsHg$rq_Y&gN1X*yRPoKENJNYlB3G?gnBd?nYkNVXl_8s}+*X<2VOdVV%x zEQ#ZB`Z{FxV^ja^yIqbL*CA!tt`42|_=Fxb@f! zN*+0mDCMkik>(M$GWJ*DQ%p@x3$DlrgGM|xMCCN ziBmZXaVqB;yyhht#~oNLZ-2%4CZuuq32CbL64JQygf!K632EGQLYnHigf#9rAx-sL zLK=6QkfwSqA&prpq^UkjNMptdX_~L{T2zs8y0@i5Ev}K*pt2~jmk{akM7|bPM5r%I zg*n0|V}h2pAo@Z`NT<7e-9?o4T0}_uUhHD-%G!j#TW{^{>TF-sSC^B6rSg#LX>On2 zA&9Y{{l?PnjztUF+gH}t_AFYGUofkC8G$+h4$Ch%toE=v{8^k|u()<{9sVro?OD*# z+1s`d&Q2}bv2^7T3-GVDeG#F2ZEug{*w%aGvi91p-k$Dd#Md!XiCBz$+PfDZ)UwnC z3wrAgs(a&!t5>hyuQ%_Y1q&7exnDc~bnwqY#O&A3KOOi}%X6jUn47k1%%OP$TuaBX zE#$s@#~vjP5W;HwFhPgf(LpJIq+LPf-&NtvfW2y6aQ5HdPt1|>%W?eTBNBAAGDQ=R#uYZv_~Wu&>dPCyv@S_L!SPP1YTCM1*7q%4*|kES$AXnE zXEKzn9-AAts-xR@0nqBSsx3i}CmiDIT_uQba2X=0Lo-8%tzOmP>xKtkX*|>?wZ=n3 z@-P9p`b2#4srclR@yVxSSvdBh)nQrTLw)$rkUU6P(UVUlWkqp5-T02>xCzIKYNuq| zLl1>pA9x0PJa|0K-ahW^=*zonS48THBjuF3${{1ChAHKA|2XM5s^j=&OFBE`rK0Q6 zi|$$8CiyRC}UV?Fla*)vl?i_UNj%zP(vOwcSkz z;ytEEZGCYvOSM1eRasQ~v;J9Bdw*4J=Sd~1-SV<=$R~T%p7ioj?I{)29%a=QZ7ZeP z@|tP(sO_%!%W%lQ;8j^v`}6);3aeMuZq#XlSM7x_mr;9~SM8}UAJv{-QSDJy?Pqhy z8=l1>*9!)+M(rCc(Gh=T=Ci) zN6N)3*}nOFSs2e!?az2s7S+DNKZ|M)sA{*QRJ+xy_SMkV=c`PcUYVO+7^drr zHoMxm&-KD~yksv+nTO4T?Or}gynRK9H=z=b%h>S}J#$&yDEo;oZF{R62^v^Qp z{z`SbHKp6Fe$xE^`Pq|Qyl(IO^3m;GE4n?py6yIvOPoDPEp>;wUEiQn?2K{xI$`wA!FuEHs}r*InXD4c=& z3Ae`Ggfnq3;dZ!_a0lE+xD)Oo+y(a#?uI)EYjOYJp16B(FWfu05AGbCllzvq=w01Q zI@@ax%`aGRNdBNX7qsm==YoX@?fZ7jojbSoP`J~F)EzVjs1Cul5z9?HJ<#^N&az?6 z4yU~in$@}NaCfY&eG!kc;SA6M{Ier&0Qia8Hd&2o9~_*bEq6k z+fA&5JI0f^?zJxygP{|a%3(Ek!i~q%HpPjSaDhxeP2h+7Fs@lIL&bT@^pY`J>;$dFI9Q4aDEP%&iXUfK3Yds_Fc2w%_!6VIy?tV7FwB z(DN%wSQ(+qF+!_@9W7OrUa8*OX-<3$w6Q&(Hy8UQr8=#ds$;0#c53-A{zWnoU-*t=krE z=w8tF;vLiHyv*qNd!w&3Z}dR#jlRlzqX$*AxuVVG(B_Gv&GA4e?xIaqqo_vx6t0`A zP6;j~O1ZFMR4ES@ABBvp13pBVJc|cA(LYO-YMk|mFF1kqNXB7rJ#<5OTp6ad-_Ece zIQP-MFSdMaRy$`7kBM~5oyR>Qx5)JZPJ$%%!yg*MTo(^|rp$TOFY5f*!Dd%po#`dC zRqRT|u9U;B=n`1Chx}|8qqMm5W5sJ=^Ic4O_Is+g4dPk6**}Zz*vr|9_{Nk*KilO= zQ*||PAy}DKz`l}UD!2x|aNi4X$}}++I65|`?O>P+93lIUSHwrbMzouaSeR)eIx04z zVk0(NoZOcWdc%s$h6rT1u+so_RnG@ra2=KFO%blnJtNhMxtED z(chn8ByheI4h0QGbQ;~AF>QaLM&bo;bz=gy*o?rUOe3(QVgxEipnOIknq@SV-YXNe z%|3^wucH+k0qSsYAu2vQpFB%$ZgsCAUKhveUY&m_g-6Y~g+2kULU|6FUK?5g_wor| zMv)g&Xa%rmE?ee2dd>r9JYI*nfL;p2m6r5H%g=HKCUF@`Ez3X8Wr=Wo{t#ysz}nXc zD4S%R6{}FO3Y*3%17pttmtDo^fBW=T5vmgGN8)9eW7YjV|*YDQ*XbmD5N*DUkXc96=DV49dUQQKHM*YTpJhZ|;A}*C=H23bZu;AJXB0ZG_$% zQQ}2#yyFqR2+kM8+ubW4d`TRp!@1$%!Sm-jskX`NM6cP2o=iKjqGBg1cA|WCBAlJ) z^?ffh24PgaUKf+KLf0&wfll0GZ{dU9GSJFYZSSAOQgo@MXo`;vz?%py1?@yRy@|{> z!FZMxZ+g?20DviaaI974?esUC8Syjp7k+a@so6U6mc;{n5h?pku*1zbtjshHt18B! zVjRk09E#rrYZXT!OU79C&ipC!!&PRHYyx|^fZe|G&-`BvJ$o}uLQ?mOhLj&8bPOb=gD;k8gQqLYR% zuFY}Ors^;JY|o3?k~_w9{^(4dKenRt6`e1K&KEBZ)IZA#dvsbbTzW6DDL>v@1@#vE zvsj5e)k-v{zfhRZ7vKF*K3Cv#rL2S)2pR_&^E)u+tE~u*^I!!L2E=yhH;--TGu!am zOxy6fifyRahH}`3@p4``JbY6hOzpXF7_A62x~=@Qs}OucL5x6a$_Q-hj6m^GUvC7s ziNLi4z5T5m^MR~4Sa~!@u7DF?Akca)5PBDa`v|hPAT$5XV*`#e8?ZXl1{`0p0Tmli zJ{u6}xj%f9-aDvIKD(5*0Xuu07aMSxe-=kzcV`3QeMC+dYzN*S&nw@}7WzSlc$0vt z?@#aQ+yK*mTx}tf1DFUN@7;`=zs5BGgiOspv7-4E%`czkhois$7OI}h2`2#VylzVG zF1u_gB35&B6c5m;g|(W4*@;AP?no69A(`4%`EuyIt_FmoeZDTa)v;)_*C{=R!lH>n zi+g!6eOBOoUjHTa$^KdF!S>D`6d%wno(q)kHk(go*nw{;IwFvuJ;()Bbp4kh1{q z4fx~v_ zXMLqP`-smOHprizsrYAB6u+YQn?~{L8%qx5Z%V262mCXK@+$X5hvs){yEz;`z)u~*x@)=KzYONoQh^wG`k#{&13cPW?jCi z@@TK3DD z=Fh>#9^b&_bw2U(AN>R_`eE^Zb8q&YXLjNZnI6C!D|Vt{C(2*n$K48|n^l`X3+sp?eU&I4C)bb5M>w|Bejz089M5upVE2vhPCT zSihinn>CC=_u?Zs@lX8q3@1IDoxizQMK$^`*VZwIIiojbv0)ZF%-AKpJ$hT>ghT5N z&Es2=`c#ciO(qZH+ZQEpwJtX()i~7DrlpT{n4?^Z}Z|0_)$SNT@sCi_-n#_U`_*i>{GM%8D%-pQDJ zg?|=3Y;ihReD21tw&|&xa!$$TXXqfm!>U)uhoi8}%@-%H-DT(DcR#H+8HY`GVbU#P&D$VP6OkM>u^nbxY?zvV)`0PIc~^p%TPd^Z`0lG=sg&D z1t$66*>h>)1*VB_t!QFJ6E~eE>by`sA1DjW>7!-8c1jf=CBs6qS1P^W2^U4l@++l@&+B}^1tniYU2Dq!HmCd;n%^#LVM zR*X)?=xidRRULlm9}mGE#Hx<^WK#e!4aoyF$S2~H zPbJzFQTlW&YoVhaqt z9Drk`d!>Jtk>0(p(h{Fy;|W#2x)7dFQ`yu)Len@^_Wk{|J$>mUFod-lmRg+iL(#!SplS8bB zt`^6pA$N>_mht#4{#nN3H@fjSJ`vXx-g;%%V3zMK_pA?EVbqnI>k^ychGJM0S^j_N z8jlZ{@wmbpj}Lj{@xhAms2GoO7>}&i;AF#2R}za3)71rQkg@-8s5b(V!Lj~XjKq8V zvlxj>)JV*Cj+{K@dT=$KcQ5SLtnzJM9GJ0EfJ<-#r$RRexl(X}>{&dQyZ&KQ)GM8$ zR@`-PAV)_#bjvI5`ipee_4~B(^tr?>)rWgc6Hk6$r)jP~oTfFWzX!!BLHSOgW(~*D z`zU%D9Z#fU)-1QsyoA^EKVn*bl^>4(%MZsNtqjMN;kX>baj`GoT=M19`7*5faXOp< z%nz2`;$ixTlyL|a_$9yde7p?PXFB5%ADwH?zNmUU*4N5$di75k!?YdIkx|*!06K!L z!2e&C@;`32=40O0T-oo`Go#LQUA*YDT){ln1SG?%`>7GLchje{+shMPtm)5L^(_!97_mp&gN^k&oytj z*0lT@r{$G-LuKBOqh4>?W&RVrUdiOZ-Ag+^K0}CUxPN)oPR5t-<<%c$jPJ6@&te6clqweKRCn0 za2HW-w~Y=4CAZ*n9q_q^?Hf$RKV2END@XrrOTYZXcJa$^_4>AY)@P_%oC>Eeq3ZXF zC}aI>r-?ibCDe8Jn1FL^t1W5teC z>_|E6NXAP7{>v7{F28>2(i@p@jcA<<(hKQGuzW92!j~5$rwX-qt!9v&=KONA^ zviQ~_PZgHK#@vx%WB9o&tTFIwcUV~9hj92mFgNZvFYdxFpHq@$c*^LXe8ud_m%Uy2 znzt)ot=N@{T`7lM$v8LEkgPIfY#uZuE=qcm@-uH9#C+`FpT$M_s(%*q@fBx2;=_dv z?Ja)6l4}V(n#@X;XG8MdEb}2dlJHRQAGQNu(@wpm$omA;uJEjbJ_uELmM}N5CHaO~ zlCOJ9@-1&kzFDy(6-%;-EQ!C0E5nk6m-fYzo!~VgT9RB~X~dFzJ!MJ0rk12NK7okW zhP)*y|BKE)&afo9zri=1qxXjBeh6xduowSr_Tt;#UVPWvi|m2Wu{6Cb_An-G4kV{bxm zrdFPJsMcqg82?%CV9ho81mLEf-n`%s1-yXu+3%Yb`kuE!Kk!!QrivA+SfO%Qp^W)Y zlUM|Q9y8j4Z4&dK3oEhLa=bSgGXL4eKTDb)_-8RGH#w6MAIRi)#Jt;L6Cl3r%$=kc z|6b{j#EG6+PQ@dX{zM*$sGEuPwOKNU0V2s<|l@oaa<9KGBFx zKEDF*=dgMk(TiU#%bdgV9%BrFfg&!XR+eRbY?EAI_G?r8+nnOVVgHSQa?| z4qJ{nY{pu8UKHQYVWV}ie6rma?C{IwW%E+XAAE&Grm7$D@lwE5&N#$J5pl<1KFd1j z5WR`41HYW$x903^$Ct2m_+PUQcX;dYf8ILWS+Nck>rf8skg;Z-PYx3n@Ao$(FG8x* z5YDXi8^4*WU)kP7?p5Ak$jrLeKZ`*LUVRjU@(E{9;=_s9?>C1(m%AZjo-8jq!8^FS zqVyG|FNe}+e4ex9s#t5F@$t&_tG%|0_8#Y-MSCw&ZOzxkCjjvQCBIN+R~(n`g~*$q zw*lzDodXBL!j3d zWexhRCAYi|_J%?X#~J=v49DC3vkdzen<0tM`89?wCD?nDd?kUKUN3$g@wE&?f+cm@ zjBqXi3!<2^SdmS!S^h_}9QS(5alf}5_f;%M#d4Ixa%4;;{9Dx-uNpKZZ!{IpCG@mk zmRV^oaV=|`HyUD8di=8(mH+Y2VpM))MkRgHuQ^EYjXBrhT5yd->?cQjJ zQCa4nCB-lNv*i7AGb-sbeZjYq?DTN?wj?t>m9~9xA9T1K0^em}8Rt8j!c$pqMrEBh zDi3?3@~4VXsTh?_WK^0(ze{Y1G>fulp9XG9Zih;rC(lG^Eg_{#nYo)jx|- zxy6i1`p94OPPR^f=&6+Fm4x4COn;&q=5fS<7s$YEDT|X*ynZseAD({1Y|o#)?RnJO zp1)LVPsR3>!}ers$LfocC2WuGs;KRW)?cf(_I84Hq-qcUEOz9({#oqEcg&8&2N!YK zynnUHpO+dZ3n?#t#?z8vNBF_|WU?cdH{gng=XF}@G1Jn&IxP)$NCX^H`FvyL^NnpC z{;QAF+5i0WjTxt<8wd%D`M1m^abDoR@P8B?jj3>Vrt{t9Fg`KKFkA zECcg@`Dd{lAMNQly5(5;rfk*n&hFguh534aqT#aTZ5L@ik?m$Cg8)0+Rko# z^$LFT@|9g(RPuv5x>qgRucN2)@I?pB->E(&YzrFRSfn zThV4&bk`oxZX8HhzJ$omWyrC%yMwS6Rol6&M;?WsHkX^68!uIHpTJcreHbql zf(grQ$c+UNp}*%QxDu6S97}ZMlBI*C%mnYh=EdUUC)7>pc&jxTKY7;PC~WWLoy$5q zI14(U$UxW2O0%n8)K|GZ!29MD@68>`<+eoL|0Ci3KS!VU#Yc(r&7wq^%)brHZ%Q%W z&IW9m%zq+b{=Y__`5AjG`rctC^KS?98&k};t&c5}`TtIs|K#X1zh10PycR7-XEK@p z8!*2iW`6Si=9bC)rxNBrJ^IXV$Y6eHn|}wGU!P+BmTmK&NtnNJ^qJq7!F<`G$&~#6 z1@rSM=5N_HeDJT9KdA0Ma`O*4vUkOzo<+T#y$3C8E9L7){{8dw z=&Nv#ntJqAV@IFQ+h*`tW=@%W{;lvia_U$3S598yd>)tZ87J9BTb{Se;IkaJ$>j6h z!sp0;hdg_8@{*S4>V(e|MxW2yXYjf7Ea`W`=g3tDpZ%EmlIHWogwHjj&*vR7_$=GC znezO5;dA7buSi}ce~FuoNeP=Lk3O4s%wTirsm~vT&5{4TA~_!O5@++2gw0b&pUpdE zu(|Xk=N@5m@GL7>eyA~-^-3ocKXZ;cvWo*(rzj>R{XK`%?i%U-q@9SCE7EjH4lC#h+ zaW2nHxV-J?b9s*pE|;DK-cK$^_M&G?k!5^($jS2dqtE3%Gq_xO4){P1L^&G#dYZQo zj~QQRaa`VU^tn7MgUh97fDe+(u`D-jAza=m;quO-&*i-`xLkVv_Yk<;8ZO%PH2Kx) zm$ZMeOTy$`N1w@iXE3?+bDL|jt)BX)Ndh7 zu1%P{$LKS8b_SD6PyE({$=^5W&2YT9j<&dkccJ?%H zAw0&7kxr2FqtD}(3?7%B@IBVke(0i*$H}c!FY&d``h>>~qtD~k3?7%B@BM9{XI04K zh55!UM35U3CO3^flNV$#x%7PR@qwP6w#ZtvY$3iybHe17(P#338B8uc-y4EOPBD24 z@h#>jOl}>0CcmnQaP*mcPzIAr&-XTv$z1`H zVU)KJQGR8@<%33_%dg7da_I@*-v?GMUK;suI2Evkuo<`VIw$VcqtE77XRx{SlD0UEbkf%qEZZ-Gs3h-zX215Cyx^JnO6LoCi?gaDVcw$AXI?IYd8KD_|61DCKM?Pd zE(|vOHxK_7C;VG7`uwZP;9u#P+P{T=(FSN&i`VhZ!@olk{&kK%|HfqSuk)AZ~driW>Lr0%~8Q=A)D?Pt@O86ITTXrSaTjg?_hksoO|CWwE|1xeM$(P>RT_%`W!{W4W1{|dstX!ozH$uEO$9{wGk@Nd=V^RK4Zf6?n~viMh(6aGaT zdtJdP!_C9LBNF}{Ir{vYl)=A}^N*^k_MYxl@$Pe1aCm<6@b9REe@Bl#|8P$b?&68Z z-;(o>sxiX9SpI^I<;}ytV-o%yJNo>alEJ@{^N*^r9hm;c(~sb2<>q1EYZLbMjXwLP zX0Wg1^rLDV*%!|~f}>`ehkdV0*tdH0**C42ef1@0A64VYzG(8XVzV#49G9@~_|a$I z^bGcuoP1POlYP6BG8GH2Un@ zDuaC`_fV=Pl6}$4V@2}y=FPS8^7@2*{iDymtuxqHa&x4rhU|+b9xFEc!pq4C`%W2s z_HC2FzLL8hRg=iR*zXI@A8($K_tb=ar;R@QW@fOj^t@y8Kzn>Hr7Jk|x_P)akZ|wx z(dXW-8Qd#9>zFdo9v_|R+U#!28435!9DVNXmchN!bB?J4i{sOMjsES7%_DkeCCoc} z^qIGN2J=eKIHvW)=N5XJHurAZISKR59ew7_FJ@jt>G{TVIgrpD9Z1;Ri+yiM*mvIO zvu|Mr`%2F@X54x!&l;SC^_kq_9IkfbrSrL5bD=Oa10PYSI;@T{{B57h?fRQSVdEE; z<`t2{xA5>YO8mc}P#EEr%J}X2eUe%dVl2K;c;x?bxp5CF&fuNb<#H4MN?a~y@XUWA zkJA-ru;rV}QEB>)XY3NKH!sY;ESJ0T6)53GIV7P;@fYQJd z;F170worKd*QvDQ6gT*@fNs3Qg=wo@ej(k2TyFZpLLo{!(UlR_rN+^P`At#W#wUYv zw<;7KJh)I8J~qH@oy+a_TJSEU+eZ6h=>C9irqV^Y?X--M^8z~S`tt+a4w^P9cSo&D zRPIjNwvA!hU6d~o-L6`{h%dWo8BxFO?#jIV~w@VxHWgpicVcX^rhsDmPf-+vAX`^-=pgf3p55=NvMD1u)x~M;(os`L_ z9c^0f)U`pms0ZaBlIPbjzf}GDRVQYyEfns18{!Y4yc1_I(-ax})Dfe5Tb9{MRVAqa_FD^f+pNAzsha;c={dJAo_@wfb ztuT7LUM1}r~=)n0hIM?VUg{XX)$UvUO=2rwM; zBOUWFoWab`a8~a0eZkkUnxDaJ$H;lUT((zi{Q17zjeuq7ak!-1#VAACi#j-%$Ui+DVbU2cDVJ?@vMcQcEbSGXms9d~NXk$?53N={E6(_=bvJooI|xg;DR~i{ zkbZNz0$B9J;byLdZ}H!ZqutYX7_7EhabY`*_iP7YmTNfDQQz42D&q#@|1pLO>;~js z?E&iGVAe0}50NX_P;D>%3#|F6et3B%|CIO2zY+LJIv!X%e0!&&?fkL5gxOxhS$ipe z)^7$=t_-LALz#yd{|sjR42MISD+`6E=J<9~kA4AL`V{Pv+D55LL`V5b(@{403-eQ4 zoS&u*>9pOFwhNBzKYX0v7CW4aBkrKz0e3CvT%6S9`=qn7NCo&?4kvLA*UGdOM;yMq zHi7`TvwS@cbV4s=xvDeqf0d^fx>Fp^#R-nKjC3x}a8;KA=i&r+BAy+N|M~mCT(xIa zE{?cM4=fa(8TN5TH?)h7Bksyw;YDAqbc_=m#-2xR^l_Lea9?-&^0uD7_O9;sLwh@y zENknk0H9rkemx6kEv+ZxsUAimY+e&&JRy)Z$U z^Ys}&_b|Wcj<$qql4hX!A>RqecZK4p#v`9`<^%uvv-s_Q2@$v!+P6U(z@4Z>t-PFHYyK8|MK$SW+}t1zA2Cz zX1(#Iwjv(PYcJx#9$t{#>|sNb&&wtSPj~h9Xzg>kS(^Xg$2yYyO$5K=i!@Xqg0r27 z_4!)BAhO9rKldm%A6P%u=hdtxys)>I@K@> zS^SJ{&zeHvZ^tXnU`oc&&lP8M+usW%TCO;Qr9FKaxH~d%-%(sxm%)!I&dQhx#iuRg z&tNeCuDu2uA4wP1c|#L1aeLQc{>NWf=Z!ZhE=)U&v4B6T-|Y88qduWHgGFQZP@LsA zX#@D;44A@&!e9OdoHHZ}gU7#uA^H>38f<;9`7v+SLHtKo7q*jiRn<~D;@Bq9WY;#U zmuRx9A93UdamE*>CC{1GcrUy}-w-!~|NIFKeJD8Bmx4oI3(oa9%b=X7I{CDeG18f= zG41eI703Vl2@d^AI+f>vp3~23KmF9+HK)SNHb_?|p}58u zX{dneRmzVIvlb@V8|pycqPfCA#}2UN-H?(yiBpLhI>{=obkcLqfR5llf0kyKkHGqf zq~>x48+}N(EgC-auaY!p@U|x*4ZR@z44w(^@|pV;XE5{Ia9{>5RhJ#my=Gwy7Ag6* zrj2md#Q9D7JUpRKE6!jJ>%%Us)rG5;gQ>dA{sz*1LDL#MZzk&Otc1a$QO?~kI>ABc z__MrO=XDTQ{)}!O#^)qI2Q%&Pp-N|IXG7?2|BT`cp7mDL+4Z@>OuK%6rPKDp>fC^K z+(n$hurxm^6#n`v#VKquqG_#M*4gs2dWj`+^|LlnTdi$Y2eCS?F2rpBKg8-dz6cI{ z6P)9pl_yrhrM3Q2)zSKqZWw(nR>JkU;LxvvbNx%)1}EeE&!6DX*Q8VVYhNf1MVDHY ziJ+MQi*hw4Ods;z4ICcHIm4>#?)BLWL7Uf9LmlZgHLr$X-6wp)gB7*D#wRpX;2Q3N zx}h7jZctJ9L{l*_B2M8#;U5$5br?*Nh%_jNgPzu!874RJo7!p87wSxU7OI| zfrb9_9i4->oetH$S8)c)oQ=JbEF2uMht5^H zY6mmF^)+#Rg4bGrm~ciA#7uexU7wb3Cy6%YuY!ht+{NtBch^a8eh! z27^L!8k>V_*INjkKEFBFE;m=^r zhM0l+h88JcnHJ3qG0HK+;p2;EM>~2yy4Ka^3SXOQ=4grWAG4&P?>L-;Y1JS4g5nI8 zT3wNW+fi{64_Im);*dsglGd|Q{E%*K&v<095QgkpFs9F24D&1pW-3bs!AMTOH29 zGWP7DIBUnuAA;`diZhsF-V;AmoWkIX@JDf$kBnh1KdZm=vTKL&NO02Lo;9macoQ>O zu6@o9;no`Ze7L{Z_nhrJcw1e>9(ilvFWS<{FTJRnXiV_ZVlHYhCct>eco}$twN8NE z=@Z&i_GT|r`+`}pio*{Ewb)O`oRM%wU9YtrTpG}|IKMS;QVn%{K!(1ORn^cjHfQ!G zUla3O5Aba_)DrKDqtm3mVF6B{l;^qJ{yUiJqt39#BNX<7@n3`o=`n>Ke$d*@zC$}m z_q4T}7^K0r!{AbDH*tusL*9?Ob{|g+(xFatqP3BVdmNT}=y9tnalT&jb_$$32U7rt zZdN*r7e{DTF>V;11Ao>|nU*@7!4%XDOO!6c9Z-xLzDaSG->hD5CJkm?Y$UP#ID$U% zQB7+w`A7$hKTEsgd>DuKD9&I}q<3cECd9bvJb37o+2H9IiJ#s|=?s?s`=#QP4%6qK zn$jDLdO$XwK>xAd6fP7Vc$J@OD{OM3`Dxp*WpI?W*I+ozAGW?U*yJm$3*-fLeyX52 zgH7hby8LbpKK;DVtfBpow#NqHCP6#gp6E7&w$HR)fpkEfbB7;wN zbY{9i;KFVvdN+ur4Z^Ch2K>*T#akR|kZ)-gx1qT{qSrZvG+47{ZoKD@{Aiiar(RzttXxP*cNW*_DsQvH zI^BsBUqYR3XHFj81%~7PuPM%8smE1{Gg#^*xTH?fM=N}tYF(Xz#dM$~;hVDiXk90g zz#%k7NnselHH}ul;w{eYeKat3r4~LGASUf($jJM=Z)XGepdYc!Yx|>LD&kZUKTVAP zFe17l<6$bRZbGQy5}q~*)497ft-+#%gNoBM$P1NHI)hcgNB*dEmPQm;(po(JAA=xt za-O#D_`bgWfj2PS;hyW;Xx)d_d(8lf930*@o9jdCkp!9%E^QBQYiYDv7Ei7-4oAeW z!NC8kJkPD@N4;-lMNjuj@7rt68*le=>5LJ1KJ+Lmb84zG(_LlopFfM2b@XAy87vh{ z(apRYyp~F13hH3eZFI74Fqxz{Hm-pgAK@9>j7rTw=S}qzWlgyyHPtan{QnxdjPeNE ztuR#nO&BA^zIk}+>v0_5N2J5};NaO9)1GkRW3W{97Ns*-sx3GYJZg1cs&#W+>+qjHix{@tfSCP(Ocqgcn4rm5joislyj}n`d>++^FY8hmpNboUUg262+-(aur z&x0LnrhDZx)NF6gW$D2Zqc$jba6i_@VAOt3v_$-S4@-;1jHGb0nHD9p)`*u{3!TFu zUT{L!)0WS3xSrq0G{<`Jje$Zs!=a=|@(*Zy1Bb&iqSL_4 zU-PU=K!>F{;--dat&QP1&z-dm(HT~lT23SjyL;U@h*d$c;Za;js^G$^bZFA(=;tEE zMaMiBYq8NWRM=!TElS&>tbO<^SdIMw%7cNMx>j)tI~F-yL^l%9jW{~N<#KzW+a85G zNI9}&X9g>KHLd0M_;<-(#VM@pHC#wH)s;&+&NZ|fEI*7hSgqv|MjMwDR({xVsE5De z=rGT=V|#Mc?|kbnpWma`ATRLUjz=oY_OicHbca}b5ihW#yC;PGRd;Pseuf z2&lC~VWkV(!TPc8b}UX|ZHFC;3;V;4R(M8rcQ_1wJR)_s#3}Cf%YehC(A^S89FBARn{>W>!EI2S#Syn?9@B!} z#SvG9v{jd5gG%xx#&DiqaA)H0Sw2p1r#PI86CC@QbS{p#99*-iix6C#;Qp*Qiz5#{ zay(@0?})WHhkF|4Cy4{@eIEqfp^DSp2*Qx@BQ1_4z_@`&ldiNlhwGuivpB`cagE(o zUJAP_&UE1(SZCe9#JpZ$%=zJ<=whhB`2QJO3^f>f4fpj4XOb008Q-NjLmB_kv979~ zHnrY;#Y0E1dHz})8-qQ2;7S_wZZ?F!3H$>oN9{*0!vCji@Nm@cwp66k!)QE6AUPpU z(z-NL2Oz~CCJx+o@Cm;F?o`DYeCb@YR8~W9;LX82D5nP$7Wek$Wn6!qwnn@!RPJi9 z@HRiLqt3J(q07^xsEt4I)9X&v-*v%^+x$bx5A1G4!MC%52E(6hKm{qHz$uKJVTLyT zB&H)yoe`h*(F@=voUL>UgXQ%$TQ(Tgf~nCNyym@rtTjl}YI)Wo#c3LA5^-dfcn!xX zvz#9z%=*3eB8^$Wej~gaTC761->9t9(h5g=zX%nl>o9nuM;Vvz@$0_uFUcw`6?rm+ zu~cBNaW+_rkyBVIFzCU)!qJM;G>X%sX_iKD8=d7hx_^HJY~DrFDy&=Jw~JgE3~lQ} zUBuxwSXn>lG|%cac^tIS$)v&47Qn0f6U)G;>R?*?f+&yG75^!RJ1d>VD{qNYy28;) zXYFNI4m!uo>LOi!kJ4#-2lB10vW9cK*K7;6^j_=?>9yih2x6eoAA*}8vO8ZBAlwbtwY zMclyrJpY|oTyn5NW+iXz=oD(Ea4xr$d?!kVbVMa@bR};jvBkTR1;-1%ureb{kSA&J zG)yoa@9x3aaAM?i!!}Y2Hw61C`$C<54b*t=`|b}uFNCBX?01V`$Cz+9*t3E-iKp^S zzpiqiR(9yi?a7KL`w@9f{e?HBhI+v3y?M;RF=01AY9lz1qA}+x6F9hSzzj|6tvHR> z!Fp(p;y9QO%_$TQvYgErozIEA$?y5ZyLo;=yN&0wwv z+KC~9sW?O5)clkVqtMnyXRr#^(3eRU*Kg`CGH?$lPTK|(cP&icFNrf)d8LP{jh8A( zwg_)+SAo;CG-<;y?J99vhSgt1PU)zcLti$TGdc>J30;7Dz~S(p^9w2uPFw7?Y-i=)#$c^*fwExQtzJD1^=H2XWT+dwL9og2 zB_7qTY!A)GYluP-E4(8xOB<&(R&RLQFA)ba%wVQLVWi`o;;=)9FVUQbFCi6R;Hd1h z*&DEEMjSovZNH=*_fD%7N6&nx)rG>3UxT>&6{m2a@TZ3%6w4K-Fqx0?7st4JUx`i{ zRGh*pv>R`U^Lz5WnB5F1&fw~HlrfPwoDXvF^m$lD6yZQS9W3p>HG@vvNk<3R_#?_B z<-w0R*2*v#|My2*j%0oYgIAEz#~xLj!pcYEsit8bINRim!UoK0esfg`+$!t>J7e@u zf#Hke|6^h(47R>X8A8C<C{eMqJ8eM#f7@fH()O=~$KXV81U(;992MN(TT#c@mFxBbAmIASeL%`!;b=}Kqt#EH;| zX^Jzr`m5+g@kqc$2lJ(l+s{)vgRLxhE;x7vCn}da#kUX^PmT}1-Fr<$fh*I#mgO}8 zk6B+~hP6+7ecIP74YRj+iz5#AjGV>)r)tsF0IleNxqIj`_0aX+9ht4Dk)_`EFw`1v z$>3yhxLEgPk2+XU>$mj@w_*)YtE<_is3o@TlJk-d-uK;Djl*1(KZALq!Hz2%%o7cE zl-OXdK@VN8X$?2?he&&y;tVF;$kGhl8pS2$u7{&>mEvYOc*nJH2+mfV!5lExxq&>y zt#=z!RxhrNTm7sK#93VghdKz()y48w?rOQjF>m6u41S1@tI-Yhq&Urs*Y>()xbZ?S zUO=&cjbBZRmysfV1o0(3@!Y}dKyPKXVSRX9o z@9i2KIHa#oR46*9=<>y#=SOM}HQKgZIO@y&l@bpW#mUJeHom zt~i4)U5dft_lh(4GI;!Vp07BAtv$qA-g4Z-m0|T4fpYDzx)P^#wpZpFnwih(UU=A9 z*Fv;|8J+9D;u)Qh;(Sz{&8xIhoVBr1I(zf+tgzzrN|L@c1FMfabxoht;tVfEEfDl~ zz*#xnpMQX@pzM!a)V_#S=5JROnZY|e%IbQXM`5PJstiBuQDT#<2pGjN=-%&Wp479E zi>xfgk$r=ASYe8jmcYhHE1j(&Zuns_k8bBZBS-O=+-|PfAO>Bl3OZ z8cl2PJmB>8fn3gDE1#4`$8+TmK~4BGn4{AJe^i{o*2a)-Hnw{2eW%hH%(Co2iNVGT z7y`bDDJJ2}Vv!0K1y5Fey!V5VX43)3Pvj3Q-M`rj6_+vZeV3(DI%>i?xGfe(tfgsw zH|XD_bOxUS&As;ql3Ecl-cYdz$5^Fs0E(SA%K16gSYC7e=4$WeiS?95*@1k9p?TT$MfM4V?t0 zV@w-zY+x}%S7}G^KYtc)adwlEnXM)goujoF3-DE1i{S@-EoxoYc6;k%6+6wNTsN`_ z!w({pPogf5Fmt3PE4nQgj~fEZ$P)hN&(iDydNT|LOZ`)HGqI@okfr6Cw_?<9y%p<@Jdf*s9+)6=E8G5RR<>} z;8lb7GchNV$$fC1+fcy?F_;l9dklTf&*TjioYY>T_CL(tP{Etkv&aS~cVI4^g`vd` z=io^@!E)cFIE9@~eIWz)lQ=D%g-7mDoWZj$0=EuSoWazy!7DRxH!3bHcf(x8SzUQ@ zoF&L7OG=;mFbk+{^AVzYlv-Jaa2TVB(7COw56Px)3XEUXb zTz~z<;andX&sBPv7Lv?<0M7*{yw|iFFigqnityfesnV+TGkz$}_(GnK3_6_S3uoU$ zpEDU|sg55vJDlTzwVfW5@xac2U$w zFdM{Z#GE%i=+)b{t`73b2H9d>g#cBrRUf?0uWL0a)yBI#s#B@L_w{yQ)j=uM<;)WN z7ca?R#9{neCquc%Jqou%&&Xpe5?FbtZ>D*=f8K-r`9EnH3S(USp}mk}F#aEAGgX7N z+>N65aT$Zxx%?!J(iILW#*M6TI9J}Jk3gT?%8J3&Emkh#9Lzq}{5(!POJ{=&Cf&vd zwG8DE>LPvYaU*LKr*%<%VjAsb(kYJR5ohgSeg$Xj4JW&3*I7q1rSVA1FkX>v-6yQ8 zNkm2AmCwcMhd@Y|VAX|akZ-;Tuc=2tKx4<@O4sK#GRItCYqxRfL@W%8`I_`wq8>l)N z8!ig&uA|+C;H5De27-MNLj~4+jwT!mHaAUOTl_MlscWbA@^A=5D)BS#3%*kQ;Nig4 zG*sYfqC^Un@(ll#)p*6}a-h$95{^wg@iWpvgB{HGXdibtgXx_QJEtVVnS<%liuQ{_ z`ut=Na07#tG4q4Ae(qw4`=Xh#7+V?D2xra5a!Lv>Q@24uxV3{m_ zGerky*H+!=>=GuOy=)hz9bUw=#y`hX$1A2`JRLKoQ)|aNRcP((ZWU{j;IP~y@*@3j z`k^>FX50edbi?|b{W^jbJk=1=`MR=PtF!TvWoTNh3kN{Kx&APIFs<$@D_sG7NIL!( zBPsHv<(gbcT_7u}D5TR_0F^(3XKKIjKYtcqeX}`V7&jbT{b_T)fOGJU0~mG1 zL}SUz!Siad%6Yx!XE6C`Wf409f#3$3`&OTDvc8Y;RzDVy z6W5}jg2e}8&iA|rOE%)Cl=y!cQn13 z#n+e43Q0D`5;Ck!9#YLE%E-i>rbA zKc!O`rVee?G7NSyva8Z*JdOwb*3&7>IZP+r=;WB4C#zl zf`fe!obZa}YTH%XwSLTR=zE%<^1ux>^^AYJx2@ZP=IzMuQg2&LRfGE|#I_nGmU+Py zd(lW?oUuhRJ=<+C=-K*NzD65nX^j*&P+woy$jFPlU1iy*PPpK0)d{YRG|Lg#mkF*E zNsJm|;oFXMDGWV46@7|6XP+wU`qcH6(LFHV%d5h!B~7jjwhF_$oXm7MkquZcu@#bE zTSxD?$DP)H&N*vNpaaw>4$wP1<0paXSEJ)D_DlOjL7t|5D?Pj#DgNVR!_-r>9+bhU z-?B6gC-J~Z9C7lBS2Vne2)xtRghm&0-tdiJtI1`4M`64xKq!%715#Y-a4hUHSCPvc zPU3Y%!sb9+op@q7S0_M^tqpdB!mh%Swmly)u0b5ri?zCxL-Pg#=g6viaj*qu!_v3_ z$D|8U@7w$V6S3<+(`z^h|IfgGaiUz6E_Thj*fooGdYs~>naAPMi1+YK((x!Jyb8dy z2}8Fj&hoB-4OEtZ&cW3fGN+uVbP99L8g}bi;tbY0X}K|Os?^Vyr_E&AKo0qMiSKul zz{~u~tT8AUMkg{A3Z|^Gk6{$2u5mbl(U>FcIx&Os|0*1ex>xBG2JTY$(bWzoFmR_8 z3V*!B;T${(GNR{yVe}m=j7$t3mN$;w%kK^Yqs#&f>KOhSPYh0&!?b ztN2})`j+gkm6&a|T5x0<;qFCNbdl%DUZ-a`{rs)xgmv>#{tUbE>$M)$>hk)j-(N7)y~R|)Yw+e+ zUg2HYJ=ivD1pa>>jX6tka+LLpuBxoTzwLBWhLn#sScLDTtbZH4ZXyickiz#PGKCw{R!s4BZ^ZPb>=bLlVjYI zUqjxvDo$Z%sD2ybAbZGby4VB{i-sIUx)?X@wZvE*T)Dz4(7AR_fVSC9r3O#9(BD+5 zFr3%7pnlF4DeUq~;r?_F+?v_0T!GZ&4XPWm>eG zx&WSwE;!yRFP$7Xo{D1$XImUg;UCi?fJb5_9Ir&rz$4Kk$1BP2r!GG!*V^fD(q6b- zP2zUF#}5TyB#lJqjF_qgZdYI!Io?di;Wza~JUrpmHWc6mLkCZIs|^LfIk>tT>_QRz z87wRkJAnMiF2KSr!42e_WUWMu<7K|;tS1KV;m5oKYgG?s;v5k0Q%czJS``0?;tZA| zpV`}0}MJ>-XaO4&m7NSKr*QahAoqd zKt@d}f-@*46#>dbAUIuZsKBi?sR-_`-(ESQ)kU>20ND&lVR)3gp=U2~bP~^j0g^CV zaSFTMZiwlmM?_UDAC)pYkr1ZU#cQhrjQmI8POaAb6lNZ<3^yoFVdm!tAFH!S%tw_@ zVJ%nBNXK-;MGEtw%{^JLj^aUzeX83eWCZRoQ7+S3x%7WLe1SksBoe1 z)2TRaEhCS?pxXyoEmyuMjM>&hSah#doWa}uDwmrBFOollx5Gqs!Xk%r@TB9+LBNDV zVB}9(TdZ^u&JE~>+X%XvM@a|gL132_^&w8{0vZ21-gkPh;uNNHV<#>QR{67Qt*x$; zc0&FB!L+EKz?e8+i1ILzW*G{zT*#Nx)ufESd%8af>}32JO&j69O5T}kKbEEe|~C*!Vug8R0^N&U234$UlA z>j$T%9@FJq?)|C?9PiCG2OAjX&Hu))RU0aJqs~d2Sjq=sEv^kLrNHPdY!^NAPHl<8 zM`m$1+)i;~DvZ;?jd1kJI$1^j&X>4qZ=VLRZy?^#HY% z&x6%>ooT6*PF_FgcR0lH$3xdlbNB*VJ@@dN@Asz!4Sq8=C+(D=!I#5xx&0K)&tNM{ z-xF(L^d^4_=+IoQ6)U8v_rxY>uCiu?Y14F!kV6X;*E&hx6Vp_RTW}XF z*ptY~#Sv?1YT&xsrOF1k?tm5^=kjxK{uXeqQ*j1czUZ-5J;-vUHl_x2ummE%!3z)8 zm_yiID>ScMt}B;o*&daSu}gEg#yg6z%W}E;JBzU0aQUAs!ooc7_;eBWFuc$M*DF<8 zk9)B$u0t)WXwAU?_ab~pt1YaAK@v9OKYuM#n6I@)agG0@IBkpK>VKg)ZHeM`{+r^o z9g5p=NO9T<#clt2#c3N9C$ImZTzR3;)kR*{I~O=OQLGbxg1a2;cX=eZ$G|C9mf`Nk zz+`nIPP!WTS=|#H^0PK3IOJ!%FdXwUo(WGKFL!N!8`l{@qilYJKmhtMkPj~Q;|qq6Gsi0rvHvNYx!b^F*FIz z(OH@$7`E=aOz8|h6^rS2ZB(4W7eGpHcdnhmS777Dq`+V+i)}P_`6IrGwc5n+bn>Yf zYx3x%_}yS<^VvkcJi(9Z*e$e&??Y-!rPW-8c{gpo#Sv?1cn7zA=*?h`boXHZ;?Lk^ zzelt8R-D0>FPc+dr|;T*)VBsJ)p8mnxZ9N|cnDc{yDBN-{{h2#sg^@8fcLj*8i#Z7 z7RS3?^(E{7DlR&>+qF-7_^~f%$%+*IC<=nhZ-rAH9{ZG~(!$w)oTOVEv6iOpD%)_+ zH4gN>8_A5uE1J8yQkI7#c$$U8|g9=i8` z0CPCfD}y}D;b;&l$e+O+j_!rY;?H0XNA{Mh!B)O)fi*J0b=vO90MX{(tuEREn*^oC zv^PA~G@Sy4Ic0GF)3&1qwQQrc3;)kZ?TX#tYIK9r$*u~Pv@~azR?+|mk(>QdM<+0j!J%vS zc!lB=#^T8Np!>Mu6viYN=64TFo>>=#L5I1?ly#0yU{oKzyB#aic!&V(K($-!P#AUo zF4?bX4fneyzqq3?>bxKF{G-x^ID1{i(n@}g2Zs9_%CLndgpb)xrsP5s^H#o0$8369PZzs48hHp0_opBrB!?X51YD?@M(Ih?cuLW#bg23UpD*Jb)Lt&7%K zcbpp-{Yh0fT8?)@Yavdl9cK(?vbq)Q|C%BNAHbcbMNWUEf7f7tSBoyc$772015ahB zV5|C-?f~`WelK|m^MVBoZpq(88>cl!%|C03q~r83CNy#k8~^ze8#~>yA;!{x(NrEN z32_QTk?w_pz^@@rVRU{!RxlSUPGJ>6Jq8z--#V{h$4s1O;SYD%WytlO02dtm0lHO~w#oUY^_-|^@c^sMn9SUv|ve9Ld zKMN*vOQXbpbhur?BZXp&l0uzxqVcd4??9!Uuqf<0L+EUSSBAk)`6|uUDcZ&-yB8l( z$LjJ2(G-_Ecx^{2WwiK@N^BGpG@jN*8Wjt>zJ|QaX90wMj;Mpn4*yySz z*;~A;w%~L)tS2WvtEJZfyck9gPH$>Bv>pyV&ayvMk#gm|Jg%f;yb5msgYA;>D44pm zX~L<$_9J8m>lzPqHueSgmY81|oY|{o?XAZ6e^zQZyu^wp6&ue&tT5tG7fwUaav5pK z0sJf zsw-DPJf-2Vde65a{GFx!PPfmMeqVg=imug2Or)|aRzgF!oJyT zune#0(~y6E!EkD~#wu+6taPH2w>zCQKBG;1?Lq}u%Qb$e1RGA0l>Qyhis{u>Z^f}Y*1;5O#fd{bxC8a5 z)!fqR>Zw-U)A9a!t-H~I&6jBz{Ldd(9|y6-uC*tIWsrAF%m2jry6!Lq;vnt~JT(W; ze8ev#Z?zF`=X?(b2(xg5D9f#)&2+G}k!2WeHri-2eS@u@A>E``fzGL&!4xyDB&X^0 zWEH$$qkZdRzjUy6=$%hr{k5D0gwH3q;=C=g*88}3i21GP4jPic#d{T z-Qbyn=$BV%T7xIyx%$tFQ`q{2xa3+msqN=g8OT}6;kE41!xEovrgm<4NsjGr2gjVD zMKX|l+MgmZnLf|Yn5JokvjVbAp8b{8{`yNBaAU43-W})1BajYaa)b zPQN|w^W!(%huXCagZG2&e{8+t3}#xpR>kt;w|MpBDFoQTV)s7n(z-OVR4G3nzM$Pf|85LA?drHYh=M&CywuNDU#%l%_{P4Wf{R;Z?6myw|8nEK z!RoN;H;fIYlZ)KH&iWaw_S@cM*L;u%6k_nw47xRn(|FKH~lRg)>Me&jROnMXc||FsS$Fivm3-sH+) ztT$Z%+~rEAFtSE_>@b_=gZ#*s>y%FOfdTj@2FR`+{^rLMK210TLk)-iVL~gn&q18Y7R$OXV4mfCEZ{A}}~GD2f=6m+;F!i{%Ki z7RX4Z!*Wb%{H>XZjojO%@>eTal zVDN`TdVc2cNOYfQIJdVZ$%;O>+}Uu$xuD&7kG_ZY*}N1{!V}M8zJO3nadVI*7`#>rAgIP*5Gx+6xGpGboB0WHC>GOk#HYI)pqmgs;zc>#y#eHtl_lX6Z^8fBgi8g&q~5+}UQh}(VShY!X> zm)LKd76au^i%NF{|5wq|s>gRpnhDY%kMD{V;b$WJ6pFy?$m=*s%W#LS`w-#87?uB1 zVsL=qf(yi`?}=_HU%I(LaV2dCFDWDoTam&LIz1f5NAvV;(pZha1{^2J{Ny6l8iwW) z85KUz%fFBtIP{P-r^EYs-p4dHKjWG&J}3znnSa7Cgh#{c$w5e%%T`X$*fKGu<6wUW zd$@j{MOc$Ml_RV8B*wY3y?U$XjX#IE=3SV-4tkCxDwqX73rahIiGlkeayyo2@0+7@ zBn~6harhwl+B;u~JFoLf3f#HGolCru0$SoNQJ>?R%EQ=s4R+Zytkcg*d9eTzD-~Ci zg`^RzT1Z#TKiJ}+S#jd`3UtP2MB|zUeSSqrz6eL{T!pZuq6xF6$WIzyP7jN6R}p6i z&B^NBe30lW4Yr%l`4GQE&um8`IK;nh07JA;Ll5s!YIi7@A}hL92nuD z)StFGK&0k=?Oxd7<$Bvt=IZqDdozrAOmU5=2PT|+5w26L{@fK$vA*^h@ij5eVtOsK z{X|nblFI3k*4$6DX2sV$JZX_0+^ZOP?{3#Y^~Eadp!#Cf-b$tZJk?y8h~C@EQT22? zL#Ka4xqnjWATUy)4#uVqlE!-p%SMSNtX|uDTPq*$CHOm5!b;EIbyC`r)OnD`??16p z%|{E@dz-~)9`s0}UH+o9%b|z_7pdi2Pt*))gM8~rybg~03D zcQ&Qp;`fH4Miz&kR$_7V=(fW_i?GOfpBTdKY0tU(w32fkrH?$n3;1G`?xvTo9(MYC`QM$Si>LvX9%4E}|>J3=0 z;#3zK>|j(EF5oM1w5m7AKco^hZ!CM}Ia}v>jxkU@&ufgyl>?4p+=x{wQUcZ9ywS;s zra1Yvm9s>PudQInxax~oy?9JC;emmlejmeoSV&_mN*)Z|#Dv*c`+%Lx6_@*Uoy(Co z+?%c!T4}NBe7tB%M?I=}Un`B9&3dg|o6T=On|wWWdfEq6z6I0mqWi=@?h`URT(J+6 z;&MQ?kGpII4?PN#V+>>bGadrkfA@=K+<77z;4Y#WyADcRE_`BwhT)O<3d3@~iV@;C z(S%V)cVU;tK22cIqW;7uUAkS0CS9_A*)T;5AL%|>5bHE(JxL4wNguJg2t8R>)={{g zp(|KrIeY)5E;9s~aPGs&%X8%PjE94D@3H8erd;iOeuXjdc+ zRL}5DlIT5GRvj(15`usmUY!n=8Y3@Ed3&?RC>-9{rdVr(1H;-7R;%i{QZ)1NyEv~s zEt)W<+@QHd3M&tfhvs9t{&1GCYSP~-G%af7P30ks@dxA0JLifftUGG@24TT$X?}ps zvJU$K@?FHZX!VK1vwfBn>qB*5y|9I?LC>PmwtUnZ$7a^3%Es2Ba8(x56OA&cwn(uq zU0tN{YAlRfN5_3?L3A=$#dMp86gSTep;{zyLzq=|fI69wBkQ8BzTaDLXl9o9czKuM zoMNs0Vq@Yc(M#epj?z`M0i+Y9i}YF-@F&Jd@+%c;J*1O`YQ9tE^qYcuJVdDGK+(fh zg62DrdbA{@99*8`Y(P;YnZsjm8onj}jJc-lXIG7#hF-EI_x+NPJ~R4AoT;o%Y=acz z^^oE~ZmHU99#!5nI6z#@Ii)5zcA~zO9)3?N{ZCkJzLy4rd=U=Iw*+*Qn>1nZHRrU_ zc$xmK?0>>)Tg{`y7Y@Y`iRC<^55ZE$?6Bf%&JmyTfJK|cG#)6;(R!&2n)Ol{G%KNc zwzP7rd$5+)cTS~*z$%RA}Hi!p@WqQVJ7K`)`x9VnV`Dl4X?PFsa@ z9x-HK>5H|hmqh76Mu{IRZ54B9I)y#;k`{|h+8|3>;&nI$Vxp4?9x91u0xb{j+EX3m z!QJpmF*wHWbf(oUNB7q)Nk$9%UFlOZ7Ap7M&=yh%2~8e&O3~UNErOvlKWV+ zVtA%&s(HUX%j#|2oCk{&F+PVFCnzJ~^qkWB2#*T=FZ#*d$%pwy^X}|3LE}7l8Ur6G z;$YGnliTVUFz>xok8GuJ7AIm{1#uQLrGhs*5<^__8E-btZ~S0AA@NSD;WS;NxW=)2 zv4?2Jv6B%rZzWBcNRCH~>|4X2-T+6SnqH6uv;5-7V$Lu~@K2n$V)y~n;}fD8GtU=C zie{{2NaGUSK?m}r#-y07{jNx`Wme`uX~ZN=hvxTaZ^TiX7#o*81@+y;q=8vW*ymN8 zq(!*HNaIKwgVOJnH_NmqBEm(g2c^t=%|P|^m7TROSG2V7iVlI`0cfmMo|tciJZlCd z51ad%FRQt)`Lbw=gN=mweu~8yzu)mwEXMfV9fxVoQe0tpY2U?2aJ^{4>ORiHH0nsQ zWL2ERIFGeeLwzjk^8*9Fnm71m9uy88un9xCY-y>8U(F`BV@asEg1!v22op_laH0ds z_M2A1IAQc7+)esF;uFSaE>~b8wNNzSyw1LiwD^{3^vTCdaqL5N6)${$2n?UCzq)8& zJ4{`0H+FO-7Tk%6pZlb7CtO{uWE4hPa6$S}k!+;G7J;;UC^RI0 zLXy+{IU8na2k5c&ew@9%9m+PX%TsOUnsje*PB4FAH|)8kkTz!S&IP}lBez&dhvS82 zJOFzZZXJGuFTzpNyOhTSgmF#>we80QggMnklYCBbjfcGe+7C&C^PSjvF%R*fiJyv5 z0yROJaBA**gV64+X`ISp@^Tw#1@H9PLNlgy>PcTBYUO)bE15^o?oC?c0TpH(sggP1 z8rQ`6QFs4cS{?Ndd(wYWv1KRdj>M`TwcNHC!X(TLm2Zq<-%VO_!?N*a#i}2P#@i0O zSr)XkdXB>fzkS5Vc+Sm;d%oftUkGQze8x`KwuU}AR?O&Fb#W1eT=Ap>NYhBRXqR4_Z6T?J$A z>-fyIF*~Dm<#O_DxYn^CQ{q?yd5E&CLra-mHlDumYJf1y%Q|38>j=Nc7F|gntfQhA zl@sNi?((vJ*(=u5Dt|I4u>?2F z>I#BM)fEJjsu%8TmaAI{7!B!j*I$$y&vIBi{61QaVMd96kfp<~G>GVzQ*i!@Mh){T zb4pq?r9<XOnTzb#bC6j$W>$=h9OfjBW~gm zs2p7bLJLZ4-PW@F5ys0$KZGGCrb#~fANa`=j4!s2} z^vC&4Y_(oFw8YF>wD99#b~`$r zEP12iVlAw3Xh_9Sdo~Q$064sZprvmYrCFlVP@Z!*V4=xOY#C2kMhsO0+mxLQm$6#X-H16k zJ_j$PGo3WVrq{NOQz6CS9NhfwfiX5R&c%X#rYDR=|9fzv`16Wu%(o&Jg-?sROx!sa zr;)?&hJF%v!jIR3KAir?>;RW$`p+&?m09f07^JIb58p#+%!%J?@h?0^W1Q0(f?fQR#3xMa zz+^-dcG9F}GYyHJkwnY~&4bPK`GZ=TsfDVZGc&1r=MwqF=u?e#8!LMysh0WtF`~tQ zg+WYFk`FEW`D4^tdq#-HR@^f}E%&({MPti-4l_2kR=s**3}d|?(oFYA7!EPixAHE< z6;Aa`5Uu9ZMuFnIg=N1LPawUO;uFSy-vz_GN;F~6H~{Bh%sd$P&Era3;mmh0#f@s2 zkkyj11Z}UR1z+@psHi`drbGR6zEQo>^(nSrxa=!idO|M6iW$a&-d+?Zxu16|iiD@D zcEQyNj0cet!r1Z@2gN}P8eE{GovN=|)V5}9_?^rY=ZTTCb zg^hm$lNO9qw&B8PxsSkJ-zz@hEb8v9v~Vr%7fm?%Vvd_`$o)x6SwdyIr+k@S&^QsH z8Y6DB+)(1uQmxPpjb8n3KH3%A+px!5TJDAtNz90_0RI+}mfR0ImS}8ET~C&|5y2Xo>tY=BKA$hNsOxz6 zY~dm0^OBNzpQjeS^uU%D?xUd99Dfg4sQv@W;u1?Z9r9N930%VJAjl??h>d>ffok+i zj~0!-YY$4SRFV&ke(BLUB&;V|3<>M0(cAp9(Law7`z6fgJC78fFlO&)Tb{!RLwL+# zJOelF&9hO{xveBjJ~ZY7l%Dh87jV5-F050G`q-5*$`R#hjmwVc;Ym1a>OS#FE-JUk zCmF18@kNc^mo*x3qq9YQ{;9M&Q~>)=eNbX$*w&St!DOh?C# z4~ftCYYm*IoFkesJ0NAs4j8))FBDa{16EgO-~qC&_1#|fJ31L3WR#@`9gW*Xx&dR1 zsqUvecQD2;nzE<5!sw_cLx*Q5Jz=DQCee3$<`EdQ5P`Jplp*;tNlqj4MRm$0Q(8Ku zyIb{;P+0d{J$fxkpt+zR}yFqL!B?MrEVn)E}Tb zS$$;8pIdrcj{IUqq;5nyh*>4~bB-k%TlQ91gkcXHgRp3!5eGXIFxh{J9%GCmE-8+h z@i-XI%`Q`V#_V;Y!=d94D9m0rI+{aAhw)YDeH(|7!Ar4;FTWL5Asj?J?w;6k;(5#u z&DQn*9%*NNWQ?}M$y>e8G%9bURi8@r>RWa2X+ue^$VlXE^sAeamY5I1`H2GK(a%Av zUE(v2TU{R#O?-IDx`{@D5>Ttc*o*3=2QQki8l8>;L2ArA_zlar9Tw?19KYz#;=}X0 zd+*6adP^H&`DiFFFZ<^%@`L3R7xe{k#EIW8AcjZDz@Wi==#4RB{4(nY88@Eo!^Mbw zV%Ga&$sda^+=%Y2&a;BVa=f@xSp$vy&57Ud!VISQHl_+*+=+Qf9mGn8lvvW4Othlp zjj0*uA@x(Su;E+*>93x}-hi>piQj7w0}D|>OU#ccuS|K2N5Gb?{ib|kE=A~NXDyWw zD?6r_<~F2!NmA0>{)^1*;>j)Mma-oUNva(T&cQ%>y}D-U;#6~iXn{^r=63N+W{=o# zF8Z!^!lKdKE`~=a)gz?XDI{R%N;TI;J2J5uhpTuW;<_MU=%-8txUzGW- zvGd~TpDBCBd}pOf$Zj-2-Kbu(0*O7Pr@qp*y+)k+oO5Q)?%H!OqQFjh5sRI#=K?1~ zu{DVGVW6c8pqHmg9P^XY>F|2@(s88ds`t`y=s>Sv@ct?(#u!arMP3+zNE3Emq;;dG z&pP9?hoAgeobi|()w@cCXXAC@E2j$+Y!<$LN^m=o2KFxo(4-^F{9+<%5FMlU>f)_o zRV3P1wd)<;O{)BG{5BvwmRb2{JZ34Hb5s+C)5N2HiiOPE#Ai&U4IC+&A=*%;9qH}gnjY_nuazb7Fqi;eVK$ELbg$w%ZK<))29P#s{N3?iiltS zIox6Ewx<}qUM=k@r5LC-1uRAN!E*PnY7Kp7_zlOSN~({2xbZwvb}~LF>FU+jsyz*0 z(y{fer9j3Zd@RtF@XLinAo{r#mlbTQ~Zo?f;D?Qm7!ilz^Te8h?0%MkoR-l`@|y2DBwE%`w5 z6&$TPXz444M6XLC`l;v3v3vE?ExzJ#t)qUCmp7G#CK^bF8Cmnoa<$; zV&Q@A;j8C}7VhI^%nK#FEcqf_?xVeCx{rPPqP8#_UiFyxggI42O>ZWeuui-9#u872 z_{NfN(l{>NO}T|~LsvcvS-4)76C#C+X89Z^w4Hph<^|&{ot3in!#!o$lwQ^f;zX@P z+;AzQPX1b2iCxO-`(mG#Be>BM@9I+aBU#M(YL{}Oha8I{4!5P%nzcnuyZ~!YrWr59`jJ|AM~5-f z9lm+VgV=e|i=Q0d%nKLsEtQhGoFu{PSGqA0bI#qY-f`Jc4RlTQ&M6~;tLOUi)?4nu zQxQE!sZf4Lf(7i^5vMa@AYQm$g%$=MCcZsMTg!KlT}Z?UjD@lZc4v(hw|R1=mvOq_ zF8H{haVL!R>M#>%mxib*i zT9&9QbK)0L$aEN^N}j|LQm#h|%SyiWrsC2P5_e%*=XV#3L)r()htg8@z#)0i zx^?sL9}=3P?1dV^z&Mzjv83EQ94B+yoL|;?Ff(Gh11A#h_5tsJ8mLpX;c)WabK~uKOJzN$Z+SgQE11CdPZ;N)X0>Q_xuw+O#!? z6a@;4&-cm97jLCvWTmo%vC(rL<}9y>CJfr$<@SOwd<;~w&-@8X;jVPb)r1iYMIWW~ zB&%qaIrhBfyXfTO&5md#??|cZgGLQPsmFfPD6in|b}Z3&x{P1TaTuwN6DQT?iqCk#Jw7f4 zPbu-j8JLCLDL!MSyEsM~dPTy{OJzJrWgIAF#PG|G(_g*Pd1gn)5tG|ynpH3BKLhq? z9O@-{0JwK1w_{1B_;Sy(62^LToLw(1&WrIOFQWOLq`1aTL-t}a0vq@rTOaKOx?*_9 z)y<7A8Tfh`2&)&g`Sq%0mPC;ebdgJ949g0aTQ@HX=CGrc!B(1Aff!EA>}ne0NCcK{ z=84^(iBEns8ts)Z$cd@J=g0l0LYtcxxrOsQ;ZDrQSQfiK=EBCZ#G=`LO`+2a-L6&d zbVv;kZ?OHQ>a7|~C|I`Mi_3NEv|oyhWuDRK4B@yHJOYE9KM!I|_4Qs%(FskN?jbMLpYzRJm#usyU0LsqX%Y^xOOHOC1e^&DK?Cxo7v zas5`2)p1?1@EGPON`Lif;#it=wx|r$r4~AnAW9c|21uB{tVo4tg<`>DZRG+Fe-9e! zC8QP1G`wu+aB8Lh$E|#wqsoY39NN3Cm2WiW0{UDr+=j%=Lr))-d`I6{(ld5>n4;yP z(k!3Tks_6^Wr!L~SuDR)Nj~~zT$*gWr}QJLpKbQY;zGDaE-PCU)vToVNUlRd)!$Lp z#`NcPDoB1laflVGH3f%=LF*1#HYlS&Zp| zWApAw(S#B95hjy-fkBI;No#%AVNyueStRpxxH^oziDrBKrkd{pi%(S#9(vB<}6g+Yrn$cI@`Y_>OsN<^vzJ&>Cgebu^z zJLPSqBHynL_~N!@ugMz$l|MC%nK(WCqQ`jY!Z;T7?-!pjTc&+1^F<53O?;+}UJ1pF z5zUz2VtnCuq8T&pizo#DoKEzFOwZw@)qIqJG|7SmdBksQC{=M7d_h zgmXwgw!a!q!cIFfOb~3cSDA$2s2%OCd1LTn-1Tr`zBhNWg}~l(VDe!J=#wn1F@DiR z3ytZJ=JYrz;7qGAth80G$f6gGs6NEtMcV2^4AcX&2~PYr(K~KUT42y94*bfs;$R^q z#0gsWq>1~`!)**NirqL9toAwFfgdQN9hx?~L4B5BXy!s`u7G04L7Hbo6NWOkh7DON zny@77dZ3kW6;?|+e=eFZdKj|Q9*MDflQ;jvHawuxIX(8a*Y~riOpjlX4rOmtlnn+p zrTQ3@OI&@lV6Dj_Ct_TRUn@4S&L8+WD4tnZb6ghhaTO&*d^|-A8tOhyyfnIsI3J}r z(9=fk7WCm_1lEc}PBvp`J!?Q1*&pINWX37Z!<9G>r#M0Do*3P1L=k2#ly?z^mbvAg zFzqO+zUQZ94JI3+I1&7YhZbY}qAGfRs*Hu53~79xYASvkBb7BvhmOiot^O`4NpLE9 zt5 zOv9pdkk$z$J>gWsEzAS?!ZqQGH!2V*4o}4dpYvlaIp6T5!=Kx@R1{`sRDbQy(L^HB z>odywS+*K+BF5(soY`S`CrE@Oi7a#^1$KfXlzpC@dRs- zyFznH!&%#kVGPekE8Y(BN| z7d}3OvGmi7iRofsq=nwoYo9RlV*}C)>5w6@3Z%HvQ16vu>NW1(>s%!AQCTqu8r80> z>g>OjRXvApWj#{Pw^&)#k(XLo@bLIW^q%p|xZqIGDA9z`3Lk|MZYRw+m2h<{AI+@& zF5y(_BjR&@p`aU+Mr8qqvV!I~sjP_W{8CwwZ?yCZ`tqyDMt?aSlDj zLyMMfPW-|GdGk(KR!8S(jFHSQm<;7McG9F_G@BY`bF(7OY$S{^ysz3$v^bR^NQ*5_ zaGz;$j5E9J^dSa1eUvI_$a-Ih`P9(V+v2q|4hW&X2o-@`D zSZd)EC;NPegFYYP1TAVNI{la;k8R?4WpBjtRQCXDn~2uQJ1pLb7KURAy6-Crr##Hj zHG}>T@&pYdscL46A`TXp!thq#Z6;|tY+tp3UX7)FSRCT>LEfqn1`XE0o7TckhT?FB z7&WtH$(qZ@aB=EoOOh};G^@KVl{IcIqz4DNryO7 zVskPi+Nwyjx7tempphl2zND5Cv8^=UL5v&l>!uqRJ>_j|v;0sJ34@0c#YDsyzbtIf zTIY!xD#jMctg8!3D~2K>diDNat*Z;56G&)XMeZ9oO6o7d!LxOxzrf(5v@!35F^+M4 zoTOnML#3zQV@ewai4Cpy+hv}!r5Zr}A}16~u6kc=xMZO=dyhf7*TN3Q3V^X%b?>*6 zFT&OOHJBO01INtDgPAY}EA)STZQ5Ard6UU}oD09RiSiIullJ?Y?A^WJmiU&1&75yp zvbWTH+{jWfnI1kai2rZAw^Zfyoi;VKtR^#?^zURr}`og1+_eZ+d1N7`su+Aj~w;gj1NgqJ=ORcte<= z;Z!ez8ru|Mva{72cNV5P!&(V5Fa(190IIfT0>cRY3LS2RG8Rr@_OFE5KZOYzXE@;- zjxXYj)}BE@XFt!V zaOEso_r!hToy*4dC2tzdi@;RvyxNXdJFnRT#EBToi)|1Fjm9Zm6JgM3sDhRUHx4=w z8fffLvY(B*hry}+MrVI;St%Vty_plgr{Q1p0%Po9--La#bHyhN8pdzG0V525`m3tVP<8jcZuM8Q-n(Ce6GmiDuputOz0|$*=ia4CN!3Nf6nB4BFlQvmb;zW$A5F^eo z8EanlRu8i_&bE^)`O$XfXWI!{chuCbMHaLp)>Qor9Z9IE{s+sdMUDjGMDSZsP42-O zvj+Mflp2hc3~6X1(PH0Ma>gP$Roz>ClfrG}^zyn*cxC3q?|-6=c{smGF5zRP6+>v&ZEt^R#j&fK5h%3ZZrg&d6uGxohiz-_s7Lg7 zeixGOV63$TfzhUhRkk3oY(ZZ%ZDS`*8N)V(C$>kC2SzyN=hX>0%TsNtRMw#HZ;0_S zWC}ZL49DjN%tn9Ae2i0u+eD*n>bouF2^wlOJdiz$G~AIu@2k)2xmH)L)9%a(3k{oN zX+ry}vR3g+X%vn67(Sae;CkM$`% zlBR>y_Dw3Y;

    &r!Y5Q42--Cpg2j3aEFoB{=M?3!bwFEPLm-??J!!B>Vs3&)?Hse zVl21PGP6tYOW`j`K_VPenf{zIX9456OmlEzU7H7(o zu+V##yf>BaU#pU&F?@rn6!51&74 z-XVt{G5_$na~h4qPCjwLdAuYOkFGbS7QuE#ipZ_rrQJfA)EmiZP{fJgZz9I@lmT*a z139KD_~oC&`90EC?-$KDrZ&OX-c@4M*hj)~oW$IkU8Qz5Fu`DB>VK*1a?egHReftX zH;)t>yMS7STJrHM%BK#{Rjz3Tl zg)xi!5Aaw;R`1(V2SoCZE%F-9NAfFV{=)6=5xiXgZ3k}>Jv+`S>VX{y}4{^3iEJo zDWot8*;N%XFbeP#3K>pf!6RUcR7j+om^P^STq+~tKp97y&p4IQLq3!wF~4ad<_KIXzN+DCsL$y|UV9KW#rujV)= z3|jD~G%+vPzeuwiO7d0wtE!2lnfSNsI?|XE$A-3Yoqz_2~t*q(BTw2NV&vlcQa)qwOS5tp21*T7FJ12GDIed-I)Q<8jE&Ezy`F zXvIL{5K|n{a8x5cYuK1x#DR&U|6I@HZ1t+W?`%%uM2z*=s98c|Xyy^$Mlnun7Me9q zYZkQbSYn(}WSOgRr#^#bS*qRC%0=rv5`zq6@CvjrT(Akq=Ss;Z3=51Jb!Qe%neG)| zSlfG3zM!G=g%dfmNH~M-3s&?0mNg1D_w9@4os}m}#DM4Abrf>}W^>;j|JdB|8?+4H z5R09|{zo)p^M@%2ea&i@<{QOEQa~i#b;qEcuj?BK#+pRe$(b{x>AJ&Fl9u5i!IPCV zz?6pkA)f9AnKc&GhTbIL!L#LfE<@_@q z0cqC0Z=5(JjJT-1unr$;m#{Kc6dEV1+Kg3}1?z|d(7I2>@bJyZT^)t8I9&Zf(inp; z_{j%p!VrA8NW-xU{zkJ}@3J&iTUx6xaw50wkoscf9I0;)ItvhO$>H!j4#1iHABj&m zPeVQ~TAYS_9C0aO#D#?62hM4iu$qN?z^&eP&tV9I_G^D?!Wh3e@}R4E#z+r+S#PV)I&9u2=ASe_rcfU#l3%FX!^;ohT?0CL z@rN3S^_=Rp*7R5}Jq(8A5M4E1ew?^DLi2S~MIp`Mx@zn<(si96wTT?EG;kb>?7FqST6$v^f3ao_gCQO=I38|g-nVu`lz65M)PhLkdlRL9}v4!`SQyz_XJI=i3oMEEwo{gy{S(ruJPVSU_}y!i+{!wF`_KFS~TM*A@WiQF_d>S4s9>t*NX#n z2=2Tu{(qJbEwAtErG%3nRtXhLxks+2BBcydi&UJktI-Rt7oYL;GteUcB$_cxweowS z8M9Q&|3frm=cN)xe><#{@B^A{)Pn?C`PhF9UP3eD_gg4s4iaPkq7o{Wa_7-}-otYk zsgA=(2Hhf!CtT+JMLdv|cmhs~YJU;5#9JPV8-gb*4`b)062=Vl@b(f`7r;J-7s20Y zD`EI4Swhs!)|ZwNZrP_2DpplO^f`w`2{XR;eLheN`*yo5Jf-+c~C zAc=V$!2 zT`=!h>0@x11|;U#+IL$>6Js#3k|qtS1A9kP`FIhBYftb}>qS?KQ>_lXhtbW6->VQ~ zdeRc}gsIN*>Buc{h;uvn3J!6CHv5dTzo5H|pD6NpY-s)X*%9as7`S)4zQu{#P$|c# zfSLEyp{V!MM4NzF-EOcbiY40n=HUA`eV}C+sg6U7vE&W$8S}pE;=hV!JON|iqOhGv zC-L^n;c;#uKI8Fd_2Z8c&Di*wqdf5tmu1$R{T2;*^>O^w+= ze8%tnIjkZUdH82MW+^nZP&8x9nHq|=dQ{Pn$DvjYeH{6rQ?1iB(muop1Px7ksAy;m z8aUgAVo3t#yfflBj8w-7t!yejV`@OJ3`-lt)WEhIi_du6!?+T zk?y;3Cyt@%a{@3si95SsicVBq`&OlS(`S|GjJ0 zxv}%gQpNyqY$>J3v({3=Rt$s8>$Kvm-x$eIzhiDLr5tvvN~u^?DgOy6Wf-ZB!;(Ff z{oI(ou`QhO5O|xa7tY z_9!JccK-3?b-aquIKC7d>WTZO)!l((u&VPJlxb$mh?a98F(cCFG0rZel;A#r+>Rw0 zPx(Ft|5srujpMMt>Qn_=D=|Ep@8UN`FJr6=Z{j(SF;<)-U8dJPYu1dzRi61O4@F$a zr6hEwi(8hGHj=MVFWJM=#&~}szWpolutvfeBixzuE84!~TZaZWoy+w7$5nhE(QLE7 zdaH8_r5mmWOpvl84Xi(-*W~PyZ&!Iz%1*TR{v2vv>Fg9&<>TrW%6V}JUV9;`HZdGTBk3==)Gr|;tFFC;X6nZhKzi|_;0Mo z^glux^3SxHo_A!7S#P2_4t^hZ-0oS2xf!0IW;hJ#VdlX_$`=l9X@(mkp<~x+OXz^n zmZ}d1nN)q7XV=W~*{a38FB|on6>SoF$aJi=%&BNxc|;LfS}T2P%-#Cx*6$Wvw`%0U zzfI75hQ5I~vr9D#yF}zdk3SLB34b+I`>bffmY+1HhxP5(AQ#pBrf9~Y?w~2X=YNSZ zVZpX1o3*gZsklsU)e@u!J?RKT!76*rhdfc%zVHf+S&l+mTaKSOJ;)z8%W<62>wFBm zXk#%iI}dvse-X`CIwK9%5#Gq#V+RHvUx}j*PlzULohfcf4_yo0o`1v76SmIQP47>4 zl1pj-3A0hk&d-SQuTD?-Dm`NBjC?b1fLA@d@H4&N8XL?+Ck1zXV7-?6Y&9%KM476{4iL-TwF+GL%jCYu5d}s6p)LAU(k55|k zIW7FZfS$&`S_glCAHzTDl$bhLbfaj-9EYENuV}`6GkfVc(Tqo5kG2qP66P{7H+1!3 zsdZ@EW_k<po;^PW+yO7%}t}+<6RgPgld3HcyY1f-f=cm1sDRFmX?cv!IBxyE3VtiJ*k=P`auQ z1m`Fo>s1&HNA@BZjyL~|W9t>}YS7-#=uUBV`(V{ycCkC}W_2Vz!lhrtnzQ*zY{TqI3LZ@#8|3r4I6 z$B3y_SzwG{{nt2-3ZQU@f%a|(6D`}s!DJhOOjyTNwSYuFcI2MzvWXQ@ZYY(&Z(EPt z({Uu5!r5mS_WvQ: -4.914ns/-481.988ns; real time: 7 secs +Level 2, iteration 1 +7(0.02%) conflicts; 473(70.18%) untouched conns; 424953 (nbr) score; +Estimated worst slack/total negative slack: -4.988ns/-424.953ns; real time: 7 secs +Level 3, iteration 1 +12(0.03%) conflicts; 254(37.69%) untouched conns; 455640 (nbr) score; +Estimated worst slack/total negative slack: -5.118ns/-455.640ns; real time: 7 secs +Level 4, iteration 1 +6(0.01%) conflicts; 0(0.00%) untouched conn; 465237 (nbr) score; +Estimated worst slack/total negative slack: -5.122ns/-465.237ns; real time: 7 secs + +Info: Initial congestion level at 75% usage is 0 +Info: Initial congestion area at 75% usage is 0 (0.00%) + +Start NBR section for normal routing at 05:03:35 08/15/23 +Level 4, iteration 1 +6(0.01%) conflicts; 0(0.00%) untouched conn; 461186 (nbr) score; +Estimated worst slack/total negative slack: -4.992ns/-461.186ns; real time: 7 secs +Level 4, iteration 2 +3(0.01%) conflicts; 0(0.00%) untouched conn; 460933 (nbr) score; +Estimated worst slack/total negative slack: -4.992ns/-460.933ns; real time: 7 secs +Level 4, iteration 3 +2(0.00%) conflicts; 0(0.00%) untouched conn; 461063 (nbr) score; +Estimated worst slack/total negative slack: -4.992ns/-461.063ns; real time: 7 secs +Level 4, iteration 4 +1(0.00%) conflict; 0(0.00%) untouched conn; 461063 (nbr) score; +Estimated worst slack/total negative slack: -4.992ns/-461.063ns; real time: 7 secs +Level 4, iteration 5 +0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; +Estimated worst slack/total negative slack: -5.122ns/-468.515ns; real time: 7 secs + +Start NBR section for performance tuning (iteration 1) at 05:03:35 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; +Estimated worst slack/total negative slack: -5.122ns/-468.515ns; real time: 7 secs + +Start NBR section for re-routing at 05:03:35 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; +Estimated worst slack/total negative slack: -5.122ns/-468.515ns; real time: 7 secs + +Start NBR section for post-routing at 05:03:35 08/15/23 + +End NBR router with 0 unrouted connection + +NBR Summary +----------- + Number of unrouted connections : 0 (0.00%) + Number of connections with timing violations : 260 (38.58%) + Estimated worst slack : -5.122ns + Timing score : 452301 +----------- +Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. + + + +WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. + Signal=nCCAS_c loads=6 clock_loads=4 + +Total CPU time 7 secs +Total REAL time: 7 secs +Completely routed. +End of route. 674 routed (100.00%); 0 unrouted. + +Hold time timing score: 0, hold timing errors: 0 + +Timing score: 452301 + +Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd. + + +All signals are completely routed. + + +PAR_SUMMARY::Run status = Completed +PAR_SUMMARY::Number of unrouted conns = 0 +PAR_SUMMARY::Worst slack> = -5.122 +PAR_SUMMARY::Timing score> = 452.301 +PAR_SUMMARY::Worst slack> = 0.304 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Number of errors = 0 + +Total CPU time to completion: 7 secs +Total REAL time to completion: 7 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1_par.asd b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1_par.asd new file mode 100644 index 0000000..cf7ea22 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1_par.asd @@ -0,0 +1,38 @@ +[ActiveSupport PAR] +; Global primary clocks +GLOBAL_PRIMARY_USED = 2; +; Global primary clock #0 +GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c; +GLOBAL_PRIMARY_0_DRIVERTYPE = PIO; +GLOBAL_PRIMARY_0_LOADNUM = 40; +; Global primary clock #1 +GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c; +GLOBAL_PRIMARY_1_DRIVERTYPE = PIO; +GLOBAL_PRIMARY_1_LOADNUM = 13; +; # of global secondary clocks +GLOBAL_SECONDARY_USED = 1; +; Global secondary clock #0 +GLOBAL_SECONDARY_0_SIGNALNAME = nCRAS_c; +GLOBAL_SECONDARY_0_DRIVERTYPE = PIO; +GLOBAL_SECONDARY_0_LOADNUM = 9; +GLOBAL_SECONDARY_0_SIGTYPE = CLK; +; I/O Bank 0 Usage +BANK_0_USED = 14; +BANK_0_AVAIL = 19; +BANK_0_VCCIO = 2.5V; +BANK_0_VREF1 = NA; +; I/O Bank 1 Usage +BANK_1_USED = 20; +BANK_1_AVAIL = 20; +BANK_1_VCCIO = 2.5V; +BANK_1_VREF1 = NA; +; I/O Bank 2 Usage +BANK_2_USED = 16; +BANK_2_AVAIL = 20; +BANK_2_VCCIO = 2.5V; +BANK_2_VREF1 = NA; +; I/O Bank 3 Usage +BANK_3_USED = 17; +BANK_3_AVAIL = 20; +BANK_3_VCCIO = 2.5V; +BANK_3_VREF1 = NA; diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/RAM2GS_LCMXO2_640HC_impl1.par b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/RAM2GS_LCMXO2_640HC_impl1.par new file mode 100644 index 0000000..6a48b30 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/RAM2GS_LCMXO2_640HC_impl1.par @@ -0,0 +1,28 @@ +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:28 2023 + +C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_640HC_impl1.p2t +RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir +RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset +D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml + + +Preference file: RAM2GS_LCMXO2_640HC_impl1.prf. + +Level/ Number Worst Timing Worst Timing Run NCD +Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status +---------- -------- ----- ------ ----------- ----------- ---- ------ +5_1 * 0 -5.122 452301 0.304 0 07 Completed + +* : Design saved. + +Total (real) run time for 1-seed: 7 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.drc b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.drc new file mode 100644 index 0000000..ec074a2 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.drc @@ -0,0 +1 @@ +DRC detected 0 errors and 0 warnings. diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.jed b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.jed new file mode 100644 index 0000000..94c4dd3 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.jed @@ -0,0 +1,1435 @@ +* +NOTE Diamond (64-bit) 3.12.1.454 JEDEC Compatible Fuse File.* +NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.* +NOTE All Rights Reserved.* +NOTE DATE CREATED: Tue Aug 15 05:03:40 2023* +NOTE DESIGN NAME: RAM2GS_LCMXO2_640HC_impl1.ncd* +NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100* +NOTE JEDEC FILE STATUS: Final Version 1.95* +NOTE PIN ASSIGNMENTS* +NOTE PINS RD[7] : 43 : inout* +NOTE PINS RD[6] : 42 : inout* +NOTE PINS RD[5] : 41 : inout* +NOTE PINS RD[4] : 40 : inout* +NOTE PINS RD[3] : 39 : inout* +NOTE PINS RD[2] : 38 : inout* +NOTE PINS RD[1] : 37 : inout* +NOTE PINS RD[0] : 36 : inout* +NOTE PINS Dout[7] : 82 : out* +NOTE PINS Dout[6] : 78 : out* +NOTE PINS Dout[5] : 84 : out* +NOTE PINS Dout[4] : 83 : out* +NOTE PINS Dout[3] : 85 : out* +NOTE PINS Dout[2] : 87 : out* +NOTE PINS Dout[1] : 86 : out* +NOTE PINS Dout[0] : 76 : out* +NOTE PINS LED : 34 : out* +NOTE PINS RBA[1] : 60 : out* +NOTE PINS RBA[0] : 58 : out* +NOTE PINS RA[11] : 59 : out* +NOTE PINS RA[10] : 64 : out* +NOTE PINS RA[9] : 63 : out* +NOTE PINS RA[8] : 65 : out* +NOTE PINS RA[7] : 75 : out* +NOTE PINS RA[6] : 68 : out* +NOTE PINS RA[5] : 70 : out* +NOTE PINS RA[4] : 74 : out* +NOTE PINS RA[3] : 71 : out* +NOTE PINS RA[2] : 69 : out* +NOTE PINS RA[1] : 67 : out* +NOTE PINS RA[0] : 66 : out* +NOTE PINS nRCS : 57 : out* +NOTE PINS RCKE : 53 : out* +NOTE PINS nRWE : 49 : out* +NOTE PINS nRRAS : 54 : out* +NOTE PINS nRCAS : 52 : out* +NOTE PINS RDQMH : 51 : out* +NOTE PINS RDQML : 48 : out* +NOTE PINS nUFMCS : 77 : out* +NOTE PINS UFMCLK : 29 : out* +NOTE PINS UFMSDI : 30 : out* +NOTE PINS PHI2 : 8 : in* +NOTE PINS MAin[9] : 32 : in* +NOTE PINS MAin[8] : 25 : in* +NOTE PINS MAin[7] : 18 : in* +NOTE PINS MAin[6] : 24 : in* +NOTE PINS MAin[5] : 19 : in* +NOTE PINS MAin[4] : 20 : in* +NOTE PINS MAin[3] : 21 : in* +NOTE PINS MAin[2] : 13 : in* +NOTE PINS MAin[1] : 12 : in* +NOTE PINS MAin[0] : 14 : in* +NOTE PINS CROW[1] : 16 : in* +NOTE PINS CROW[0] : 10 : in* +NOTE PINS Din[7] : 1 : in* +NOTE PINS Din[6] : 2 : in* +NOTE PINS Din[5] : 98 : in* +NOTE PINS Din[4] : 99 : in* +NOTE PINS Din[3] : 97 : in* +NOTE PINS Din[2] : 88 : in* +NOTE PINS Din[1] : 96 : in* +NOTE PINS Din[0] : 3 : in* +NOTE PINS nCCAS : 9 : in* +NOTE PINS nCRAS : 17 : in* +NOTE PINS nFWE : 28 : in* +NOTE PINS RCLK : 62 : in* +NOTE PINS UFMSDO : 27 : in* +QP100* +QF171904* +G0* +F0* +L000000 +11111111111111111011110110110011111111111111111100111011000000000000000000000000000000100000000000000000000000000000011000001001 +00110000000001010101000000101000010010001111111101000110000000000000000000000000101110001110000000000000110101110000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000010001000000000000000000000000100010000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000010010000000000000000000000000100100000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000100001000000000000000000000000000000000000001001001011010 +00001100100100010011100100100100010000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000 +00000000000010001001001100000010110100100101000000000000000010010000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000001001010000000010001110011001001000000000000001000001011100000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000100101100011000000010011000100101110001010001001100000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000010110100000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000010000100000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000001001110000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000010101100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000010010100000000000101001000000000000000000000000000000000000000000000000000000000000000000000 +00000000101100000101011000000010110000000000100001000000100011000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000010000000000100010100111000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000001001110000100010000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000010001000000000000010100100000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000001001110000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000001011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000010010000000000000000000000000000000000000000000000000000000000000000000000000000000010 +01010000000000000010111000000100000000000000000001001010000000000000000000000000000000000000000000000000000000000000000000000000 +00000010001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000001000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000001000000000000000000000000000011100000010000000000001001010000000000000000000000000000000000000000000000000000000000000000 +00000000000000010001000000000000000000000001000100000000000000100011000000000000000000000000000000000000000000000000000000000000 +00000000000000000000001001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000100101000000000000000010111110011100000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000101001000000000000000000000000000000000000000000000000000000000000 +00000100001100111000000000000000001000110000000000000000000000000000000000100110000000000000000000000000000000000000000000000000 +00000000001001010000000000000000001001010000000000000000000000000000100110100110000000000000000000000000000000000000000000000000 +00000000000000000000010010000000000000000000000000000000000000000000000000100100100100000000000000000000000000000000000000000000 +00000000000001001000000000100010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +00110000000000000000010001100001000101001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000100001000000000000000000001001010000000000000000000000000000000000000110000011100000000000000000000000000000 +00000000000000100101000000000000000001001100000010011100000000001001000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000010011000000000000000000000000000000000000000000000001001000000000000000000 +00000000000000000000000000000000000000000000000001001110100011000000000000000000000000000000000000000000000000000000000000000010 +00011001110000000000000000000000000000000000000000000100001000000000000000000000000000000000000000000011000001110000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000001010110000001010010010001010011101001000010000000000100010000001000100000000000000000000000000000000000000000 +00000000000000000000000000000000000010101100000000000000000001001010010000100000010011100000100111000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000010011000000000000100001100111001010100000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000100011000000000000000000000000000000000000000000000000 +00000000001001110000010010000000000000000000000000000000000000001001010000000000000000000000000000010001100000000000000000000000 +00000000000110000011100000000000000100111000000000000000000000000000000000000000000000000000000001001110000000000000000000000000 +00000000000000000000000000000000100101010000100000000010101000000000000000000000000000000000000000000000100111010000100000000100 +10100000000000000000000000000000000000000000000000000000000000000000000000000000000000100100000000000000000001000010000000000000 +00000000000000000000000000000000011000001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000001000100100110000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000001011010111001000000000000000000000000000000000000000000000001011100000000000000000000000000 +00000000000000000000000000000000000000000010010000100011010010000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000001000101001010101111100101100011100010100001110100010010000000000001001010000000000000000100001000000000000000000 +10010100000000000000000000000000000000000000000000000000000000000100111010001010110110011001001111000011001110000110010001000100 +01100000000000000000000000100011000000000001001000000000001001100000000000000000000000000000000000000000000000000000010001011100 +01000110010010010011011010001001000101110000100010010111100010100010011101000111001110100111101010000000000000000000000000000000 +00001001100000000000000000000000000000000000000000000000000000000000000001010011000001000011000000011100000111000001000010100001 +00001000011010100000000000000000100000000000100110000000000001001000000000000000000000000000000000000000000000000000000000000010 +00100011000110001001000100010100111010010110001100000100101001100010100100111000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000100001100111000010011101001101011111101100000101011000110100001011011000000001001101000 +01010001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000010000101001111011 +00000100011001001101100011000110000101011100110001001111110100000100110000000000000000000000000000000000000110000111000000000000 +00000000000000000000000000000000000000000000001000010010011000100011001000111000001000010010010010010101000011000010100100000000 +00000000000000000000000000000000000110110000000000000000000000000000000000000000000000000000010000100001110001000100100100011100 +00010011110011001001001001000111001100011100100000000000100110000000000000000000000000000001010110000000001001001000010000000000 +00000000000000000000000000000000000000100000000111011001101001111011010100101111001000010011010010111110001101001101000010010010 +01101100100001110000001010010000100000000000000000000000000000000000000000000000000000000000000100111000000000000000000000000000 +00000011000110001001010010000100100001100011100101000011100010000100001000000000000000000000000000000000000011000011100000010001 +00000000000000000001000100000000000000000000000000000000010001001001110100011100010110110000001000110100001110000101010011010011 +00110100001000000110000001100100010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +01001111010010101111100100010000110011101000101001101111000000100000001001101001101001110000011100100000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000010001100010110110010010011110110001001101110100000110001001001000111 +00000010001101011011000011000001100100010001001000010000100000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000001101000100001001001000010100110010010110111111000100101001010100001100111110001100010010010001101000011 +00111000000000000000000000000000010001010011100000000000000000000000000000000000000000000000000000000000000010011000001001000100 +10011100000011110001000100011100010000010001110001001000001100100010100111100110010011000010011000000000000000000000000000000000 +00100111000000000000000000000000000000000010001000000000000000000000100100110001100011000010101100100001001000011000110010011000 +01001111001010010111000010011100000000000000000000000000000011000011100000000000000100111000000000000000000000000001001110000000 +00001001110100011001100000011100001100100011000100101010011110000010010011001110000010100001110100000100010000011000100101001111 +00111010010100100001000000000000000000000000000000000000000000000010000100000000000000000000000000000000000000000000000100101010 +00001001010011000000111000011111000101010010100100001100111110010001000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000010001000100110000000101110100110100110010011001001001001001100001100110001100000011000100011001 +10101011010001000000000000000000000000000000000001100001110000000000011011000000100110000000000000000000000000000000000000001010 +01000000000010001111000100101011101100101010111000000100011000101000011010010011001010000100111000001001110000000000000000000000 +00000000000000000000010001000000000000000000000000000000000000000000000000000010011011010000010100011001001011011011101000001111 +10000001110010000010110001001000000000000000000000000000000000000000000001111000000000001001010000000000000000000000000000000000 +00000000000000011000101001100100100111100000011001000011100010010010101110001011100010001011000000111000010000000001000010000000 +00000000000000000000000000000000011110000001001000010001001010010000000000000000000000000000000000000000000000000110000001110010 +01101000110001000000010000101110010000001000100010001000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000001110111111111111101101010001101100110100110101000101000001111110111010100011111111010100000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001011111010001010001101110000111111101111 +11001100110000111011001100111110111011110110010010001010100010010110100011111111001101110100100000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000010111110100010100011011000001101111111111000100011000011 +10101100110101010110110110010011111110111100001100011111101001101110000110010111000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000001101010101111110111001010001110001000101011101100110101010101010001010001001100 +11111101011000011100001111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +11000000111001001100001100111100000000110001101110010011000011001111000000001100000011101101110000110011110001000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000010010100100111000000000100101100011001011111000010010 +00010100101011010001001000111100100001100100100100000000000000000000000000010000000000000000000000000000000000000000000000000000 +00000011010000101001100000010001001001100100111110000101010011010100100010000110011010010101110001000100111100011010010101001001 +00001110010001011110000001100100010000000000000000000000000000010010000000000000000010000110011000000000000000000000000000000000 +00000000000001001000100110111001000000001010010100000001000110100110100001110100000100101001100000000100011100000010010100000000 +00000000000000000000001001010000000000000000000000000000000000000000000000000010001000000100000110000101001000111100000111011001 +00001100001101101100001000100001000100000110001000110000110011000011001000010101011010010100000000000000000000000000000100100000 +00000000000000000000000000000000000000000000000000010100110011100100000011100001001110000100100000110001010010011101001000110000 +11101010101000000110101100000001001000001001110000000000000000000000000000000000000000000000000000000000000000000000001000110000 +10001100000000100001110100000110011000010000101001100010110100010000100100001111100000010001100010000010011100000000000000000000 +00000000000000000000000000000000000000000000000000000010010100001001010000001011001000100110100010000100111001101101010100101000 +11001001001001101000101001110000010001011110000001000010000100110000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000100000010010010111110001001100010001100001100110001001011000001000011010100010011010000001001010001110000001 +10100110101001001000000000000000000000000000000000000000000000000000000000000000000000000000000001001110000000001000100110001100 +01011111011000110010001001000001011111010010100001111000001011010010011101100001111001000010010101000101010100111001010000010110 +01001101110011000100111000000010000000000000000000001000100000000000000000000000000000000000000000000000100010000000000100111010 +01101110010000001100000011010110110011000100111010011010011001000100100110100000100000101100011101010010011011000000010111000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000010011101001011001100110010000100110111001000 +01011001000111000111001001001000001101100010100111100100100000011100010000100110000000000000000000000000010000100000000000000000 +00000000000000000000000000000000000000000100010001100001100101100010010001011000101111011100101000010111010000010111010011010011 +11000110110001101010010010010110011010001010001010000010011110001010011000000001000010000000000000000000000000000000000000000000 +00000000000000000000000000000000000000100100010011101101010010110001000110011010011001110010010111100110011100101011001101101000 +10010011111000100101110010001110001011010001101010011001010100000110110000100000000010000000100010000000000000000000000000000000 +00000000000000000000000000000000000000000010011100010000000111011000010000011010001001001101100000011000100110101110100100100101 +10011011001001011001101101000001000000111001000000000000000100000000000000000000000000000000000000000000000000000000000000000000 +00000000000100011001001001000010000011100110000101101011100000101001101001111001001001100101110010010110001110011001110000001100 +01101000110000000100001000000000000000000000000000000000000000000000000000000000000000000000000001000100010011101000010011000100 +10100111110000101000001000101000111011101001000100011100001011010100101001101001010100010010111001001010000000000000000000000000 +00000000000010011000000000000000000000000000000000000000010000000000001000011110000001110010101011011001001111001000100101110000 +11001010101001011001001010010100010011000010101110010000010000110000011001001100110110000000100100000000000000000000000000000000 +10000100000000000000100011000000000000000000000000000000000000000010010100000100100010011000010011001000000100110010010100001100 +00101011000110001001110110101000110001000010000111110000100000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000010001101001011000000110010100111001001000100111101001011010011011001101011100100101001100100101100111000100 +10110011111000011001000111000110000000000000000000000000001001100000000000000000000000000000000000000000000000000000000000010011 +10011000100011001110100110100101001000111000010100000101111100110111000100001000111000010110001000101001110100010100000100000100 +11110011000000000000000000000000000000000000000000000000000000000000000000000000000000000001000010010000010110010011011101000000 +01001111011001100000011010001011010010101111000000100100001100001100110010001001001100001100001010100101000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000100000010101010110110010010001000100111110100010110000101001100 +10010110001110010001110010000111101100010001101110000100100010010001110110000100101111001100000000000000000000000000000000000000 +00000001000000000000000000000000000000000000000000000001000000010001111000010101001011001001100010100000100011001001011001110100 +00110010101100100001001011011001101001010100000010011110010100000000000000000000000000000000000000000001000010000000000000000000 +00000000000000000000001000100001000011001101001110011100010001000011101001010101001010011010001011100001011100001010100110010001 +01000101101001001110110000110011010000000100110001001000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000101000001010111110101010011110001001010001001101100000011010000110100010011101100000011111111110001010000011000000111111 +11101001111101111111110111100111101111101111111011111100100000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000010010010100000101011011011100001111000100101000110000101001111111101100100101000010001111000000111010001101110000 +11111011111001111100001110011000010101101110000111110110110100000111101111101111001000010101000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000100100001000100101000100101110110011011100110011100001110101000110000110010110111 +11001100100001100011101000111110001011011100001000100101111111111111011110010101101100000011110100011000110101011101101110001011 +11010001000110000000000000000000000000000000000000000000000000000000000000000000000000000000000100001000110101010100110111111111 +11001000100110111101111111111111001000011111001100110000111001111111110111110111010000111111101111001110101000111100101001000001 +11101110110011001110101111100001110001011111111111101001100000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000010001000100001100111100011111100000000110001101011101000001000111111000101001100010001010001111110001000011000000 +11100100100011111100000000001000001001100010010000000000000000000000000000000000000000000000000000000000000000000000000000000100 +00000000000000100011011000011100100100011010100101000110100111000101010100000110010000100101010000100111100100000000000000000000 +00000000000000000000000000000000000000000000000000000010001100000100011100001100001100110000010000111010000100001010011000010000 +01101000010110110100000100000100011100001100011110010001000001001110000000000000000000100011000000000000000000000100110100110000 +00000000000000000000000000000000000000100101000100111000010011010011110101001001100111001000011100001001111000000100010101101010 +00110010000011010000100111100000010100110100101010010011000100100100110000000000000000010011000000000000010001100000000000000000 +00000000000000000000001001010000000001000110001100011001100001100011000100000100001100011001001111101000001100000001011110110100 +00010000010000001001100000000000000000000000000000000100110000000000000000001000100000000000000000000000000000000001100001100011 +00110100100010011110100000000100001110101001001011001001100011101110001010101000101010011000101100010010110010001010011110000000 +10010000100000100110000000000000000000000000100011000000000000000000000000001000000000000000001000110000000000000000000011001000 +10110100000101001111001111001000010010101000111110010000110010001011001000100100111100010010000111100000011001010100111100111100 +00111001001000000010001100100111000000000000000000000010011000000000000001000100000000000000000000000010010100000000000000000101 +01000011010000100100110010010101001001001110110100001000100111110001100001011100010011111100001001001111001101010010110010001010 +11000100110010001010011000101010000000000000000000000010101000000010101011000001110000000000000000000000000000000000000000000000 +00000011000100010101011100100100010010000000001111000000110100010110000111001001000110100010010011010000000010001011100010101110 +00000110000100001100100001010010010001000000000000000000000000000000000000000000000000001001100000000000000000000000000000100101 +00100011110110000101000011100010100111000001010110110010010101010011110010111001000011001010011011000101000100111000001010011101 +00111100010100110110001101000001001011101011000100011000000000000000000000000000000000000010010000000000000001000110000000000000 +00000000000000000110110010111010010011000011000000011001001001110000010100000110000001100101010110000110110011011001110001001011 +00110110100101010101010001010010101001101011100010000010011001000101000011101100000110000001100000000000000000000000000000000000 +01000100000010000000000000000000101011000000000000000000000010011001000111000000010111010010101100010001111000001010100100100010 +01001010010110011100010010011100110001001001011101100011010110110000101010100010001110000001010010000000000000000000000000000001 +10000011100000000000000100001000000000000000000000000000000000000000100000100110001000000100001000100100100011100001110100000111 +10100000100110110001000110001110011001110110000100110000010000110011110001101100010001010011000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000100011110000101001001100110101001010000010011001001101100010100100001100111110010 +01100101010100010001000011001010100001010110010010001001101001110100010100001000000000000000000000000000000000000000000000000000 +00000000000000000000000000000001101100000100011001110010000100111010000111100100000100110011010001100100111011101100000101010010 +01100111011000011010000101001101110000010011000110001000011001100100011000000000000000000000000000100110000000000000101001001011 +00000000000000000000000000000000000000000000100100100011110100100110011001000101110010000110010001010101110010111100100010010010 +01001111100010100110000110011101000001001011000011000000100001111000110101000111100001100100011110001000101001100000000000000000 +00000000000001010010000000000000000000000000000000000000000000000000010000110011110001110000000001011111100100100101011010001101 +01110010010110101100010000101001001001001000111100011010111000100001001011001011000001101100000001001000000000000000000000000000 +10001100000000000100010100111000000000000000000000000000000000001001100000010011100110011100001011001001101110001010110001010001 +00101110000101110011000001100010010100000110010000101000110110001001000011000110000000010001100000000000000000000000000000000011 +00000111000010001100000000000000000000000000000000010010000000000000100100011011000001000001001111001101001001001001101000101111 +01001011000101001101001110100001100001110100011001100001010110101001001001111011101110100000101110010011001000010000000000000000 +00000000000000000000000000001000011001110000000000000010101000000000000000000000000000100010000100100100000110100001001110001010 +01110010000110000110010001010011011010100111100001010011010100111110010000010011010011011000101000110100010001001001001101100010 +10001011010000100001100111000000000000000000000000000000010001000100110000000000000000000000000000000000000001000100000101110001 +10001001010001110001000111101001000100101100000010010110101101100010101110100011010000000100001001001100100001100011100011110000 +11010000000000000000000000000000000011000001110000000001001110000000000000000000000010001000000010001101010010001001110100100110 +00110011011110010000110100110001001101100001001100010100100011100001000010000010000101010110010100110001011011000001000010100011 +10000110011010010100000000000000000000000000000000000000000000010010100000000000000000000000010011100000100110000000111010000000 +10011010011110000111011010100111001000011001001011001010100011111110000010000010110111010101001001011110101000110100010010011110 +01111000110100101111100000010011110111110001000100101111000010011000100101001111000110000010001100000000000100011000000000000000 +01001100001000100100110000000000000000000000000000000000000010010010010101001010011000101001001101100101001100011111000001011001 +00010100100110001000111001000101000001011101101000010110001001010111010010011010100101000101110010010100100110000110010000000111 +01010000100010110011000100100110000000000000000001001010000010000110010000000000000001001010100011000000000000000000000000000000 +00000100010100000001100101001101110100101001100001100010000101001001100010001001100100100100111110001100001000101100001010100100 +10011011010000101000110110010010011010000100010011001000111100100101000000010010100000000000000000000000000000000100110000000000 +00000000000000000000000000000000000101000010100011100110010101011101000100001110000110011111100000110101001110011110000111000011 +11110011100110011010100011000100011000011110111111100101100110011111100001000011010001111110000010100010100001111101111111110111 +01001100000000000000000000000000000000000000000000000000000000000000000000000000000001001101010000110011111111100100011000111010 +11111111110111011100000010001111010111110110111000011001100111111111001101010110111111111000100011101110000111011111110010111001 +00110100110011011101001110111111001111110111101000100100101000111000100010001100000000000000000000000000000000000000000000000000 +00000000000000000000000000000111011000101100110100011111110010010000111011100001010001100011111110000110010100011111100001101110 +00011001110011010001100001110110100010011001000101101110000111111011101100101110111110111101101110000101101111111100110101010100 +00100101011111010001000110000000000000000000000000000000011110000000000000000000000000000000000000000000000000110001000100100011 +11111110010100100010000101110011111100110110111111101000011100111001111011111110101111011101111111101110100001101000100001101011 +10100010110110000111001111111111111001101011110111111100100010111110100010101100000000000000000000000000000000000000000000000000 +00000000000000000000000000001100000011100100100011111100000000100000011000011001111000101001100010011101101101100110100011100110 +00110111011011000111111000111001100001010111010000010110011010001110010000001000111111000000001100011000000000000000000000000000 +00000000010011000000000000000000000000000000000000000000001001011000100010001010011110000100000000000000000000100010100111010011 +00001000000000000000000000000000000000010010100001001110000000000000000000000000000000000000000001000110010001000110000001101100 +10011011010000100000100001100110000010000110011000001000011001100001100011100010010111010000011000010000000000000000000000000000 +01001000000000000010011000000000000000000000000000000000000000001010101001101010101001101001100010000001001111001100100110000100 +11000000100110000100110010011010001000100110010001111001000100000000000000000000000000000001000110000000000000000000000000000000 +00000000000000000000010001110000010000100100001010000010000101001000010000000000100000000010010010000001000000001101000001100001 +00000000000000000000000000000001001100000000000000000000000000000000000000000000000000100011000001100010100010101010011101001010 +01100101001100010111001000000001000000000001001000000000000000000000000000000000000000000000000000000000000000000000000000000100 +01100000000110010001011010000100000100001100110000100100100011100010100011000100001100110010000100100001100110100101000001001010 +00000000000000000000000000000000000000000000000000000000000000000000010011000000101010000001010100001001101000010010011010011010 +01101101000010010010100100110000001001101001100000000000000000000000000000000000000011000011110000000000000000000000000000000000 +00000000000000001001110001100100101000010010010000010000100001000000000010000000010010100010010100000000000000000000000000000000 +00000000000000000000000011010000010000000000000000000000000000000110001100000100100110000101010001100000000001000100000000000001 +00001010001100000000000000000000000000000000000000100100000000000000010001100000000000000000000000000001000110010000011100100000 +01110000001100110110010110101000000000000000100010000001000100000011100001001100000011000000000000000000000000000000000000000000 +00000000000000000000000000000000000000100111001000101001110110010010010001100000010110000010000000000000010100101010010100101010 +01110000000000000000000000000000001100001111000000000000000000001000100000000000000000000000000000000100000101011011100000101000 +00110001001010000101010110000000101010000100111000001001110010000110011100000000000000000000000000000000000000000000100110001000 +10000000000000000000000000000000000000000000100011010000001110000110001001111000100100111010101001000011001110100001000100111000 +10001000010001100000000000000000000000000000000000001000110001001110000000000000000000000000000000000000100111101001001001011110 +01000001011111001110100011010000011001010011001010001001000000010001000010011010000000010011000000000000000000000000000000000000 +00010011100000000000000000000000000000000000000000000000000001001010010001001110001000100110011011010000000010101100100010111001 +00000101011100000010011000000000000000000000000000000000000100100000000000000000000000000000000000000000001000010101001000010001 +01100010010110000101010101101001010110010001000100100000001111010000000000000100110110001001100000000000000000000000000000000000 +00100111010000000000000000000000000000000000000010001100000100111000001001101000111000001110011000100101000100011100010010011110 +00001100010100111000001011100001000100111101010001000100100111000001001010000000000000000000000000100000000001100001111000000000 +00000000000000000000000000000010011000000000101010001000011001011100010010110100000111000011011100100100011011000001001111001100 +10010110001110010101001100110000110010000110010001001100110000110000100110010011111010001000000000000000000000000000000000000000 +00001101010010000000000000000000000000000000000000000100001100010000001000101001110100000100111100000100010011100001000010011010 +00100100011010011001000100100011010011000100011001001100000000000000000000000000100010000000000000000000000000000000000000000000 +00000000000100010010011010011100010001101111000100101111100110010011110011011010000101101000010100110111000101010011100100100010 +01011001111000010100100010010110011100100001010010010011100000000000000000000000000000011000011110000000000001000100000000000000 +00000000000000000000000001000011000000010001000011000010101001111000011011001001101001110001110000010010000010001010001001001111 +01010100000010001001001110000010010100000000000000000000000000000000000000000100100010100100000000000000000000100011000000000000 +00010011110010101000001000000101101010011011000110001001110110001001010010101001101000101000111000011001010100110010001110001110 +01010100110000001000000100110000000000000100111000000000000000000000000000000000000000000000000000000000000000000000100000100010 +01000010110100110010100111100101001001011000100000010001110000110011010001110001011010010011000110110100010010011111010001001010 +01100011010001010011100100000100110000000000000100001000000000000010001000000000001001000011010001000111010000000000000000000000 +00010011000000000000000100010010011000110110101001001110111000100011000100011001000010011011000000110010010111101000000010010001 +00101100110001001000100101010010010011101001100000000000000000000000000001001110000000000000000000000000000000000000000000000000 +00000111110111100011000100011001101011011110100000010111010100001100110011111111000010010010100011111111001101001001110011111111 +11111100111001001011001111111111111100110100100111001111111111111100111001001011001111111100000011101001010100000101000000000000 +00000000000000000000000000000000000000000000000000000000000000000000011111000000001100010001110000111011001101011110100000100100 +11010011011010000001101110000101000011000011010011101100000011000011010011101100000101000100011011110011000011111111011001010000 +00000000000000000000000000000000000000000000000000000000000000000000000000000110010011100011000100011100001110011111100001001001 +10011001111111101101010101111101111111110000011011100000011000011010011101100000011000011010011101100000111111110010001101111111 +11000111111100110101000000000000000000000000000000000000000000000000000000000000000000000000000000000110010011100011110111011010 +11111111000011010001000101110111111011010011010100010010110000111001111111111111100110100000111001111111111111100111000001011001 +11111111111110011010000011100111111111111110011100000101100111111111111110010101101010000011111110011010110000000000000000000000 +00000000000000000000000000000000000000000000000000000000000011000000111001000000110001101110010010001111110001000010000001000111 +11100010011011010001000001111010011100100100011111100010011011010001000001111010011100100100011111100010011011010001000001111010 +00000100111001000110000000000000000000000000000000000000000001000000000000000000000000000000000000000001001101000101001110000000 +00000000000000000000000000000000000000000000000000000000010100110010100000000000000000000000000000000000000000000100001100100000 +00000000001001100000000000000000000000010001100000000000000000000000000000100100000000000010011000100010000000000000000000000000 +00000000000010001001001110000000000100111000000000000000001000000000010001000000000000100010100110000000000000000010011011100010 +00000000000000000000000000000000000000000000000000100111111000001000000000001000010100011000000000000000010000100000011101000000 +00000000001110010000000000000000000011000100101001100000000000000000000000000000000000000000000000000000000000000000100001100000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011100010010100000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101100000000000001000001 +00001000000000000000000000000000100011000000000000000000000110000111100000000000000000000000000000000000000000000000000010001000 +01000000000000000000000000000000000000000001000000000000000000000000000000000000000000001000000000000000000000000000001010010101 +00100000000010001101001100000010000100000010011000000000001000100000000000000000000000000000000000100100100001000000000000000000 +00000000000000000000000000000010011010010001001011000010000000000000000000110000001100010011100000000000000000000000000000000000 +00000000000000000000000000000000000000000100110010001100000010011101001001001010100100000000001001100001110010000010001100100010 +10101000100111000000000000000000000000000000000110000111100000000001000010000000000001000100000000000000000000000001000100100111 +00000100001000100010010011110101100001000000010001100100001001001010010000000100001001000011001110000000000000000000000000000000 +00000000000000000000000000000000000000000000000000001000011001110000100101001000010000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000010011000000000000000000000000000000000000000000000000000 +00010011100000000000000000000000000000000000000000000000100000000000000100000001001000000010101100000000101100000000000000000000 +00000000000000000001001000000000000000000000000000000000000000000000000010000100000010001100000000000000000000000000000000000000 +00000000000000000010011100000000000000000000000000000000000000000000100111000000000000000000000000000000000000000000000000000000 +00000000011000011110000000000000000000000000000000000000000000000000001000010000000000010011000000000000000000000000000000000000 +00000000000000000000000000000000000100111000000000000000000000000000000000000000000000000001001010000000000000000000000000000000 +00000000000000000000000000000000001000010000000000000000000000000000000000000000000000010010000010010000000000000000000000000000 +00000000000000000000001100001111000001000110101001000000000000000000000100011000000001000000000010011000000000100010010101100000 +00000000000000000000000000000000000000000000000000000000000001001000000000000000000000000010010000000000010010101101100100011101 +10000100100000000100101010011001000100000000000000000000001001100000000000011001001000000000000000000000000000000000000100101000 +00000000000000000000000000000010001000000000110000001111000110010001001110000000000000000000001000100000000000000000000000000000 +00000000001001000011010001000100110000000000000000000000110001100000000000000001001100000000001101000100011001000010000000000000 +00000000000000000000110010010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000001000010000000000000000000000010000100000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000100001000001100110010000000000000000001000010000011 +00110010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000010010110000100000000001001011000010000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000010011000000000000100110000000000001001100000000000000000000000000000 +00000001001100000000000000000000000000000000000000000000000000000000100111000000000001001110000000000010011100000000000000000000 +00010011100000000000100111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000001011111100011000000000000010111111000110000000000 +00000000000000000000000000010000110001101001111001110000000000000000000000000000000000000000000010000100000000000000101111110001 +10000000000000101111110001100000000000000000000000001000011000110100111100111000000010000110001101001111001110000000000000000000 +00000000000000000000010011100000000000000000100111000000000000000000000000000000000000000000010111111000110001000001110000001100 +11100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000011000110100111100111000000 +00000001011111100011000100000111000000110011100000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011110001100100011001000110100111 +10001101001111000110100111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000010010100000000000000011100010100000000101001001110111011111111111111111111111111111111 +11111111111111111111111111111111110000101000000000000000000000000000000000000000000000000000000000101010101001110010001000000000 +00000000000000000100000000000000000000000000000011111111111111111111111111111111111111111111111101011110000000000000000000000000 +11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 +* +NOTE END CONFIG DATA* +L41088 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +* +C5769* +NOTE FEATURE_ROW* +E0000000000000000000000000000000000000000000000000000000000000000 +0000010001100000* +NOTE User Electronic Signature Data* +UH00000000* +0994 diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.log b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.log new file mode 100644 index 0000000..d0353b8 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.log @@ -0,0 +1,4 @@ +---- MParTrce Tool Log File ---- + +==== Par Standard Out ==== +==== End of Par Standard Out ==== diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lpf b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lpf new file mode 100644 index 0000000..2743d95 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lpf @@ -0,0 +1,4 @@ +#BLOCK ASYNCPATHS; +#BLOCK RESETPATHS; + +#FREQUENCY 200.000000 MHz; diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lsedata b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lsedata new file mode 100644 index 0000000..83564a7 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lsedata @@ -0,0 +1,6331 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp new file mode 100644 index 0000000..36bafd6 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp @@ -0,0 +1,336 @@ + + Lattice Mapping Report File for Design Module 'RAM2GS' + + +Design Information +------------------ + +Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial + RAM2GS_LCMXO2_640HC_impl1.ngd -o RAM2GS_LCMXO2_640HC_impl1_map.ncd -pr + RAM2GS_LCMXO2_640HC_impl1.prf -mp RAM2GS_LCMXO2_640HC_impl1.mrp -lpf D:/One + Drive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_i + mpl1.lpf -lpf D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_ + LCMXO2_640HC.lpf -c 0 -gui -msgset + D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml +Target Vendor: LATTICE +Target Device: LCMXO2-640HCTQFP100 +Target Performance: 4 +Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454 +Mapped on: 08/15/23 05:03:24 + +Design Summary +-------------- + + Number of registers: 102 out of 877 (12%) + PFU registers: 102 out of 640 (16%) + PIO registers: 0 out of 237 (0%) + Number of SLICEs: 75 out of 320 (23%) + SLICEs as Logic/ROM: 75 out of 320 (23%) + SLICEs as RAM: 0 out of 240 (0%) + SLICEs as Carry: 10 out of 320 (3%) + Number of LUT4s: 143 out of 640 (22%) + Number used as logic LUTs: 123 + Number used as distributed RAM: 0 + Number used as ripple logic: 20 + Number used as shift registers: 0 + Number of PIO sites used: 67 + 4(JTAG) out of 79 (90%) + Number of block RAMs: 0 out of 2 (0%) + Number of GSRs: 0 out of 1 (0%) + EFB used : No + JTAG used : No + Readback used : No + Oscillator used : No + Startup used : No + POR : On + Bandgap : On + Number of Power Controller: 0 out of 1 (0%) + Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) + Number of DCCA: 0 out of 8 (0%) + Number of DCMA: 0 out of 2 (0%) + Notes:- + 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of + distributed RAMs) + 2*(Number of ripple logic) + 2. Number of logic LUT4s does not include count of distributed RAM and + ripple logic. + Number of clocks: 4 + Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK ) + Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 ) + Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) + Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS ) + Number of Clock Enables: 14 + Net RCLK_c_enable_6: 4 loads, 4 LSLICEs + Net RCLK_c_enable_5: 2 loads, 2 LSLICEs + + Page 1 + + + + +Design: RAM2GS Date: 08/15/23 05:03:24 + +Design Summary (cont) +--------------------- + Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_2: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_6: 1 loads, 1 LSLICEs + Net RCLK_c_enable_27: 8 loads, 8 LSLICEs + Net RCLK_c_enable_10: 3 loads, 3 LSLICEs + Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs + Net RCLK_c_enable_16: 1 loads, 1 LSLICEs + Net RCLK_c_enable_28: 1 loads, 1 LSLICEs + Net RCLK_c_enable_15: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_3: 1 loads, 1 LSLICEs + Net Ready_N_292: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_8: 2 loads, 2 LSLICEs + Number of LSRs: 7 + Net RASr2: 1 loads, 1 LSLICEs + Net nRowColSel_N_35: 1 loads, 1 LSLICEs + Net Ready: 7 loads, 7 LSLICEs + Net nRWE_N_177: 1 loads, 1 LSLICEs + Net C1Submitted_N_237: 2 loads, 2 LSLICEs + Net n2366: 2 loads, 2 LSLICEs + Net nRowColSel_N_34: 1 loads, 1 LSLICEs + Number of nets driven by tri-state buffers: 0 + Top 10 highest fanout non-clock nets: + Net Ready: 18 loads + Net InitReady: 15 loads + Net RASr2: 15 loads + Net nRowColSel_N_35: 13 loads + Net nRowColSel: 12 loads + Net Din_c_4: 10 loads + Net MAin_c_1: 10 loads + Net Din_c_5: 9 loads + Net MAin_c_0: 9 loads + Net Din_c_0: 8 loads + + + + + Number of warnings: 0 + Number of errors: 0 + + +Design Errors/Warnings +---------------------- + + No errors or warnings present. + +IO (PIO) Attributes +------------------- + ++---------------------+-----------+-----------+------------+ +| IO Name | Direction | Levelmode | IO | +| | | IO_TYPE | Register | ++---------------------+-----------+-----------+------------+ +| RD[7] | BIDIR | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RD[6] | BIDIR | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ + + Page 2 + + + + +Design: RAM2GS Date: 08/15/23 05:03:24 + +IO (PIO) Attributes (cont) +-------------------------- +| RD[5] | BIDIR | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RD[4] | BIDIR | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RD[3] | BIDIR | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RD[2] | BIDIR | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RD[1] | BIDIR | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RD[0] | BIDIR | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Dout[7] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Dout[6] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Dout[5] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Dout[4] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Dout[3] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Dout[2] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Dout[1] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Dout[0] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| LED | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RBA[1] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RBA[0] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[11] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[10] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[9] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[8] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[7] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[6] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[5] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[4] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[3] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[2] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[1] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ + + Page 3 + + + + +Design: RAM2GS Date: 08/15/23 05:03:24 + +IO (PIO) Attributes (cont) +-------------------------- +| RA[0] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| nRCS | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RCKE | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| nRWE | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| nRRAS | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| nRCAS | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RDQMH | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RDQML | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| nUFMCS | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| UFMCLK | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| UFMSDI | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| PHI2 | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[9] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[8] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[7] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[6] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[5] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[4] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[3] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[2] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[1] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[0] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| CROW[1] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| CROW[0] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Din[7] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Din[6] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Din[5] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Din[4] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ + + Page 4 + + + + +Design: RAM2GS Date: 08/15/23 05:03:24 + +IO (PIO) Attributes (cont) +-------------------------- +| Din[3] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Din[2] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Din[1] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Din[0] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| nCCAS | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| nCRAS | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| nFWE | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RCLK | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| UFMSDO | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ + +Removed logic +------------- + +Block i2 undriven or does not drive anything - clipped. +Block GSR_INST undriven or does not drive anything - clipped. +Signal PHI2_N_120 was merged into signal PHI2_c +Signal n1407 was merged into signal nRowColSel_N_34 +Signal n2380 was merged into signal Ready +Signal n1408 was merged into signal nRowColSel_N_35 +Signal nRWE_N_176 was merged into signal nRWE_N_177 +Signal GND_net undriven or does not drive anything - clipped. +Signal VCC_net undriven or does not drive anything - clipped. +Signal FS_610_add_4_19/S1 undriven or does not drive anything - clipped. +Signal FS_610_add_4_19/CO undriven or does not drive anything - clipped. +Signal FS_610_add_4_1/S0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_1/CI undriven or does not drive anything - clipped. +Block i2046 was optimized away. +Block i1118_1_lut was optimized away. +Block i637_1_lut_rep_31 was optimized away. +Block i1119_1_lut was optimized away. +Block nRWE_I_50_1_lut was optimized away. +Block i1 was optimized away. + + + +Run Time and Memory Usage +------------------------- + + Total CPU Time: 0 secs + Total REAL Time: 0 secs + Peak Memory Usage: 35 MB + + + + + + + + Page 5 + + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. + Copyright (c) 1995 AT&T Corp. All rights reserved. + Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. + Copyright (c) 2001 Agere Systems All rights reserved. + Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights + reserved. diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mt b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mt new file mode 100644 index 0000000..2d70ad1 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mt @@ -0,0 +1,9 @@ +-v +1 + + +-gt + + +-mapchkpnt 0 +-sethld diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ncd b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ncd new file mode 100644 index 0000000000000000000000000000000000000000..f841f9031ef51586d90adaa5aa327f17523d9888 GIT binary patch literal 194841 zcmeEv34C2uwf;?qwCN0#c?uM0OF?ooHbs;)X-gz+O43qBV}XKU2(zdt7Eurd6&2B^ zGKk`c^Y9!{ad--f$m1a@$dpz@M3Sl~Lv#P%x7J=~?|tsMfN-1AKllEAJ6UJ#wWqb$ zT6^u`?6dv$Lqk>d_x>O^HaE7XZE5|I-rNcIy!x1`T-6&-uRp%7F4xt*^oZ{I{hJ%> z4r$M=IBfCqJdlk!{I=tt=ly#OCFF9GI=dIH?CtD0VnMzNk2Qjv?2&cE=F(W9tx99- zGie)$osgz&B(^$@Z6bDj8rw|lxHPtfSTG5HgZj=Vc1#-EO03q`H(07WF-2OR+2DF< zaJmuol0&)?_0r&UBkHBW=|y zxIrp5ImMg?so116Rw|a3oCc{_n!OFu6UsuzrkpoPgVT*@k_M+6(IgE{H=-%C zhns>P_EiX!$|D1v^2k7?Jkn{@_(c1bwJlxbY{=5K{((8I3+m=Vm2#@I z#%a4t@=c9aoH}5;TCbXp)6YF8lP_w=o+Vz``YiFn*Jp_r#y(5DaQ0c^)xealzwkDd zKH#2Kza;n6E>7%O*p?}DY9LETtJL%$ahAxc$(&d+TBW9Bv`S6MXqB2MI%v0cOUZVt zfh}1zwX~(9MJ7u}t13oS3q(?laOu>~&QvwarBe%2C-ih=O1s+WlCi?lC^q1z3UWz~ zss)b{2W?hMUNTnrSu$4GSu$37I*JV{t=bh=I*3-~DjBW1RWe%Gm9pqFx_TG&wJ-1O zTiUj~Z*gbWB6?q2z4482>^t@BHGOCIpES^SV*jaYWOUf3`;0Ybtv;uJ;H292(+5uI zKd1ln0g_K@?_RoeQBQkkTbIz)Ebm+g>D4hYgbQja?zNHa;D?|>l9CH2Dtg0!5dOCAsu@j>`JexSX*tv428 z5uiXu(-PDmLX4C>E@dLU4I;hc1{SYcBw6|h>9w(4i#k$x6;_OT+0w4V-sB`c-3Xl_ zOzA;#)s{3HbmR*NigHkKO>#(Utj-`NC-G@<)47C?cg#w}RkST&W?GnZ{PXFH;)SI? zJ}qlH>G1JsQPb&%k55aQj)6WtEoeF=@$qQ}>nP~s)BM$G%A}r-Y-Q7NFo`Z|y$ER% z?HZpjS4>sF+%$7^C`^*4d81=t5}js^PH&RvG-q_4lSHQ(qZ6JaI?b0Rsr$Hro_5u~ zL{*x^zK-i@?>aQrl_rr?L>!t@t|qal$SSRMO-{voOi>fYNf`m-(wu2_D&AwpA*o)o z$m95)j>DE764$R;bX;O|wDf62%c}=gE?$~$ZL{b{HDl84Z59qOs<)#vRg~0Uqq-$3 zX_+u7XqoHOBwlzG#JgTi;)P{Fyz5rRuQ+n~q6Na3F`dhjQUxnaF)Z7y*ofGpOHd2{ ziZc=B6{Cf5#b{w#Fg2SX>ny8#C}F zSfE2;27L(@=*X8rFDyv#i5z4Lq>gV1bs`8lvCF`h;DTF5E8>ohUm5w7;DU}<8T6_O z3%#WgxzzD#Oc7eez@ZZsWGkPJLPdG#=u?bVeM*<8qfIfja=nPUMC)~MDH1&$T8f#X zBTELpga~9?868ZDbJ3wB17AV}noHOM9YZqmDZzy1sG3RVMYb@(My4>qMpj^QZ|4%3 z6)s=d!&&2m!`s{Y2G*SOmc7PYf4~7iyvSeG8dK5vCwaMVN*#9bpE-RtQ@oY=bZpVOs?5-E5Dr1Hz67J0a|hunWSj z2)iNdj!=uR2g05Rvk>+|*c)LVgxLsl5auH6i?Bb!D-g(tI)pqzJwgKlH;kGP<|DKs zEI>FA;gtvnA-oFV)d&Y8v>_}+Xh-NkScI?`VF|(^2%QM8K{ym)8A3P0a)iSWdJuXM zRv@fII2>UW!Vw5ZA{>QqG{P|m$0EEIp%3A82&)l}LpUDc1cWsRCnB7L@Op%Pgp(0Y zK{yrRG=u?!(-GKDXCj=1a5lm@2Kw_aeLx;r$3#AbbGfg9sl&xDw&R2v;F|1mU9y z|Ap`|gpVV90^w?eYY?tQxDMfy2-hQg3gOcTHz0fl;j;*zL-;(x7ZARPa3jK(5WbA? z6@;%Md=2622;V^XCc?K6zK!tT2;V{YF2eT^zK?Jd!VeIBi0~tXn-PAD@DqfeBK!>D ze-M6-@C$@n5N<{ICBm-|ZbSGr!tDsZLAV3qe-Z9P_&Jb>^Z!b1py2BVT3;;Jc95Sghvtnitrf1-w+;07(y6E*nseN zgnuCX6X6Mje6((p&DTV!bF4`gh>dK z5vCwaMVN*#9bpE-RtQ@oY=bZpVOxal5Vl9y0bxgkoe*|L*acx%gxwH!N2o>E17S~u zSqOU}?2WJw!fb>&2y+qkMVN=MAHx0!uRu5ep$;LBP>;}n(1_54(2UT6Fdv~6VFAK{ z2(Lsq2;o%-uSPf+p$%anLOVhS!Xkvl2ulzSLFhzy4Z@)aT?k7NmLYT_EJrvDp$DNC zVFkiUgu@Y5Asm5lB*IY$MrYb z6ogX|PD2<#I33{(gfkJ&LO2`Y9E5Wb-hgmk4t9BQZ(no1uCK2@5B8|O^M4oto&^!p zU5eEwoY2?Umj^S0$RIm#Jv#zj5k#c2iz_iHsU7+%NaXS8zW_fisvG(>i1TUUDtkO+ zBA}1+Dph{mN}pHU$T+XKjWw9up4HITFh6Fq&k7=3vRb8zkDDI!N}O4W`EhPRs<`#3 zRB>6p-f=TMK5l2snz(C%8kCHPJ1teUxZczH^N`q6&poGa^$92UrK-`7E|55(h*&y~O zHe|4CTXbf~barXV7)=XuY0Rf29}LM0L)anpX<;yK3C~#JwNh*RnTSfkS~4I**t5na;j6HTQf1iYwRn)<)Xstab9&aSKH*KsJ+5T+X;OcZtrc4Q zsln1VSk{=2YbVkZr``$z1+i6`$Y>?j>d?xTIG-9~!J7GTJ7f@A?xYS9es<66Pt4=UJP=d2oWYx##iM6|Ym;}m~BujL>9Cg}nw=DOPLwhd9CPGs(u&&&= z4cn=irKANzRBTSR2Gd&22#QgS&8Jl_9#y<+kP_jK1TcEZI5EfP?O=CK*;A_hOK3$%wd%cYx>u!bKYvxt4$UbI6!C9L0P$ zq*i%q`Wv#0Y4xg}j=ui5M8(BCq`50L#kB0jSWO>Gmf~W;ij7yj(_J=iE&uShlUdoY z-_!+V^jiMmPqUBpT5&PoO6T`%Rl}5C1eGPNuEbs7kg;s0+L^^NPSWb;J3CT} zqj6E%ytt$t#X`3BsmoU10%4t`OG{+qvWAIiW}Bo>V=I`lDsks#IRUA;y?5%wzQpnjtJK<*<#NI?$m(rxcVb=f z_&EO^ih3ezZ07KQC8A=B;IoaJ?eTGU6c?8@xtQ3W<@s^>Cz-&-T3eiLONJ(pmn~V7 zMwc^A+Q4;;C3T7xin&l@YWOcMvpJ*8VyZ0j;p92)GKYMw{>n1>#ihC-jLNf?fB16+ z#H@74*vu5?m$e2`OqC^}u7KD`IAqNG*dEy=nl)d`Km3VcW=-szflF~zz2=ys95joq zf>%me#)~zcg4EzvSXqm;{KKD5MOAKyo8xsN=D5elOrOr9xP51=KB2FrudgK~mpD## zbPKj+!om~!X41!nkiNMTeG}>9!b#s$ioTKbF>6WRSc<-Z^fA{--%yIap7gP6L;Cts z^m)?9T}1kPDSB)!wWPdm($~fGlM;T$RiB_oq)QRUd{N>Q=Y7sG)0H^Ic26Als1m1m z?uldBQ{oiEJ#k7IrGY7Kd*axlYtAWFd*XOlP~sGyCt!(~Vjc;z9ElF4yN2#1l_4&^ zT8==+eUXsHg$rq_Y&gN1X*yRPoKENJNYlB3G?gnBd?nYkNVXl_8s}+*X<2VOdVV%x zEQ#ZB`Z{FxV^ja^yIqbL*CA!tt`42|_=Fxb@f! zN*+0mDCMkik>(M$GWJ*DQ%p@x3$DlrgGM|xMCCN ziBmZXaVqB;yyhht#~oNLZ-2%4CZuuq32CbL64JQygf!K632EGQLYnHigf#9rAx-sL zLK=6QkfwSqA&prpq^UkjNMptdX_~L{T2zs8y0@i5Ev}K*pt2~jmk{akM7|bPM5r%I zg*n0|V}h2pAo@Z`NT<7e-9?o4T0}_uUhHD-%G!j#TW{^{>TF-sSC^B6rSg#LX>On2 zA&9Y{{l?PnjztUF+gH}t_AFYGUofkC8G$+h4$Ch%toE=v{8^k|u()<{9sVro?OD*# z+1s`d&Q2}bv2^7T3-GVDeG#F2ZEug{*w%aGvi91p-k$Dd#Md!XiCBz$+PfDZ)UwnC z3wrAgs(a&!t5>hyuQ%_Y1q&7exnDc~bnwqY#O&A3KOOi}%X6jUn47k1%%OP$TuaBX zE#$s@#~vjP5W;HwFhPgf(LpJIq+LPf-&NtvfW2y6aQ5HdPt1|>%W?eTBNBAAGDQ=R#uYZv_~Wu&>dPCyv@S_L!SPP1YTCM1*7q%4*|kES$AXnE zXEKzn9-AAts-xR@0nqBSsx3i}CmiDIT_uQba2X=0Lo-8%tzOmP>xKtkX*|>?wZ=n3 z@-P9p`b2#4srclR@yVxSSvdBh)nQrTLw)$rkUU6P(UVUlWkqp5-T02>xCzIKYNuq| zLl1>pA9x0PJa|0K-ahW^=*zonS48THBjuF3${{1ChAHKA|2XM5s^j=&OFBE`rK0Q6 zi|$$8CiyRC}UV?Fla*)vl?i_UNj%zP(vOwcSkz z;ytEEZGCYvOSM1eRasQ~v;J9Bdw*4J=Sd~1-SV<=$R~T%p7ioj?I{)29%a=QZ7ZeP z@|tP(sO_%!%W%lQ;8j^v`}6);3aeMuZq#XlSM7x_mr;9~SM8}UAJv{-QSDJy?Pqhy z8=l1>*9!)+M(rCc(Gh=T=Ci) zN6N)3*}nOFSs2e!?az2s7S+DNKZ|M)sA{*QRJ+xy_SMkV=c`PcUYVO+7^drr zHoMxm&-KD~yksv+nTO4T?Or}gynRK9H=z=b%h>S}J#$&yDEo;oZF{R62^v^Qp z{z`SbHKp6Fe$xE^`Pq|Qyl(IO^3m;GE4n?py6yIvOPoDPEp>;wUEiQn?2K{xI$`wA!FuEHs}r*InXD4c=& z3Ae`Ggfnq3;dZ!_a0lE+xD)Oo+y(a#?uI)EYjOYJp16B(FWfu05AGbCllzvq=w01Q zI@@ax%`aGRNdBNX7qsm==YoX@?fZ7jojbSoP`J~F)EzVjs1Cul5z9?HJ<#^N&az?6 z4yU~in$@}NaCfY&eG!kc;SA6M{Ier&0Qia8Hd&2o9~_*bEq6k z+fA&5JI0f^?zJxygP{|a%3(Ek!i~q%HpPjSaDhxeP2h+7Fs@lIL&bT@^pY`J>;$dFI9Q4aDEP%&iXUfK3Yds_Fc2w%_!6VIy?tV7FwB z(DN%wSQ(+qF+!_@9W7OrUa8*OX-<3$w6Q&(Hy8UQr8=#ds$;0#c53-A{zWnoU-*t=krE z=w8tF;vLiHyv*qNd!w&3Z}dR#jlRlzqX$*AxuVVG(B_Gv&GA4e?xIaqqo_vx6t0`A zP6;j~O1ZFMR4ES@ABBvp13pBVJc|cA(LYO-YMk|mFF1kqNXB7rJ#<5OTp6ad-_Ece zIQP-MFSdMaRy$`7kBM~5oyR>Qx5)JZPJ$%%!yg*MTo(^|rp$TOFY5f*!Dd%po#`dC zRqRT|u9U;B=n`1Chx}|8qqMm5W5sJ=^Ic4O_Is+g4dPk6**}Zz*vr|9_{Nk*KilO= zQ*||PAy}DKz`l}UD!2x|aNi4X$}}++I65|`?O>P+93lIUSHwrbMzouaSeR)eIx04z zVk0(NoZOcWdc%s$h6rT1u+so_RnG@ra2=KFO%blnJtNhMxtED z(chn8ByheI4h0QGbQ;~AF>QaLM&bo;bz=gy*o?rUOe3(QVgxEipnOIknq@SV-YXNe z%|3^wucH+k0qSsYAu2vQpFB%$ZgsCAUKhveUY&m_g-6Y~g+2kULU|6FUK?5g_wor| zMv)g&Xa%rmE?ee2dd>r9JYI*nfL;p2m6r5H%g=HKCUF@`Ez3X8Wr=Wo{t#ysz}nXc zD4S%R6{}FO3Y*3%17pttmtDo^fBW=T5vmgGN8)9eW7YjV|*YDQ*XbmD5N*DUkXc96=DV49dUQQKHM*YTpJhZ|;A}*C=H23bZu;AJXB0ZG_$% zQQ}2#yyFqR2+kM8+ubW4d`TRp!@1$%!Sm-jskX`NM6cP2o=iKjqGBg1cA|WCBAlJ) z^?ffh24PgaUKf+KLf0&wfll0GZ{dU9GSJFYZSSAOQgo@MXo`;vz?%py1?@yRy@|{> z!FZMxZ+g?20DviaaI974?esUC8Syjp7k+a@so6U6mc;{n5h?pku*1zbtjshHt18B! zVjRk09E#rrYZXT!OU79C&ipC!!&PRHYyx|^fZe|G&-`BvJ$o}uLQ?mOhLj&8bPOb=gD;k8gQqLYR% zuFY}Ors^;JY|o3?k~_w9{^(4dKenRt6`e1K&KEBZ)IZA#dvsbbTzW6DDL>v@1@#vE zvsj5e)k-v{zfhRZ7vKF*K3Cv#rL2S)2pR_&^E)u+tE~u*^I!!L2E=yhH;--TGu!am zOxy6fifyRahH}`3@p4``JbY6hOzpXF7_A62x~=@Qs}OucL5x6a$_Q-hj6m^GUvC7s ziNLi4z5T5m^MR~4Sa~!@u7DF?Akca)5PBDa`v|hPAT$5XV*`#e8?ZXl1{`0p0Tmli zJ{u6}xj%f9-aDvIKD(5*0Xuu07aMSxe-=kzcV`3QeMC+dYzN*S&nw@}7WzSlc$0vt z?@#aQ+yK*mTx}tf1DFUN@7;`=zs5BGgiOspv7-4E%`czkhois$7OI}h2`2#VylzVG zF1u_gB35&B6c5m;g|(W4*@;AP?no69A(`4%`EuyIt_FmoeZDTa)v;)_*C{=R!lH>n zi+g!6eOBOoUjHTa$^KdF!S>D`6d%wno(q)kHk(go*nw{;IwFvuJ;()Bbp4kh1{q z4fx~v_ zXMLqP`-smOHprizsrYAB6u+YQn?~{L8%qx5Z%V262mCXK@+$X5hvs){yEz;`z)u~*x@)=KzYONoQh^wG`k#{&13cPW?jCi z@@TK3DD z=Fh>#9^b&_bw2U(AN>R_`eE^Zb8q&YXLjNZnI6C!D|Vt{C(2*n$K48|n^l`X3+sp?eU&I4C)bb5M>w|Bejz089M5upVE2vhPCT zSihinn>CC=_u?Zs@lX8q3@1IDoxizQMK$^`*VZwIIiojbv0)ZF%-AKpJ$hT>ghT5N z&Es2=`c#ciO(qZH+ZQEpwJtX()i~7DrlpT{n4?^Z}Z|0_)$SNT@sCi_-n#_U`_*i>{GM%8D%-pQDJ zg?|=3Y;ihReD21tw&|&xa!$$TXXqfm!>U)uhoi8}%@-%H-DT(DcR#H+8HY`GVbU#P&D$VP6OkM>u^nbxY?zvV)`0PIc~^p%TPd^Z`0lG=sg&D z1t$66*>h>)1*VB_t!QFJ6E~eE>by`sA1DjW>7!-8c1jf=CBs6qS1P^W2^U4l@++l@&+B}^1tniYU2Dq!HmCd;n%^#LVM zR*X)?=xidRRULlm9}mGE#Hx<^WK#e!4aoyF$S2~H zPbJzFQTlW&YoVhaqt z9Drk`d!>Jtk>0(p(h{Fy;|W#2x)7dFQ`yu)Len@^_Wk{|J$>mUFod-lmRg+iL(#!SplS8bB zt`^6pA$N>_mht#4{#nN3H@fjSJ`vXx-g;%%V3zMK_pA?EVbqnI>k^ychGJM0S^j_N z8jlZ{@wmbpj}Lj{@xhAms2GoO7>}&i;AF#2R}za3)71rQkg@-8s5b(V!Lj~XjKq8V zvlxj>)JV*Cj+{K@dT=$KcQ5SLtnzJM9GJ0EfJ<-#r$RRexl(X}>{&dQyZ&KQ)GM8$ zR@`-PAV)_#bjvI5`ipee_4~B(^tr?>)rWgc6Hk6$r)jP~oTfFWzX!!BLHSOgW(~*D z`zU%D9Z#fU)-1QsyoA^EKVn*bl^>4(%MZsNtqjMN;kX>baj`GoT=M19`7*5faXOp< z%nz2`;$ixTlyL|a_$9yde7p?PXFB5%ADwH?zNmUU*4N5$di75k!?YdIkx|*!06K!L z!2e&C@;`32=40O0T-oo`Go#LQUA*YDT){ln1SG?%`>7GLchje{+shMPtm)5L^(_!97_mp&gN^k&oytj z*0lT@r{$G-LuKBOqh4>?W&RVrUdiOZ-Ag+^K0}CUxPN)oPR5t-<<%c$jPJ6@&te6clqweKRCn0 za2HW-w~Y=4CAZ*n9q_q^?Hf$RKV2END@XrrOTYZXcJa$^_4>AY)@P_%oC>Eeq3ZXF zC}aI>r-?ibCDe8Jn1FL^t1W5teC z>_|E6NXAP7{>v7{F28>2(i@p@jcA<<(hKQGuzW92!j~5$rwX-qt!9v&=KONA^ zviQ~_PZgHK#@vx%WB9o&tTFIwcUV~9hj92mFgNZvFYdxFpHq@$c*^LXe8ud_m%Uy2 znzt)ot=N@{T`7lM$v8LEkgPIfY#uZuE=qcm@-uH9#C+`FpT$M_s(%*q@fBx2;=_dv z?Ja)6l4}V(n#@X;XG8MdEb}2dlJHRQAGQNu(@wpm$omA;uJEjbJ_uELmM}N5CHaO~ zlCOJ9@-1&kzFDy(6-%;-EQ!C0E5nk6m-fYzo!~VgT9RB~X~dFzJ!MJ0rk12NK7okW zhP)*y|BKE)&afo9zri=1qxXjBeh6xduowSr_Tt;#UVPWvi|m2Wu{6Cb_An-G4kV{bxm zrdFPJsMcqg82?%CV9ho81mLEf-n`%s1-yXu+3%Yb`kuE!Kk!!QrivA+SfO%Qp^W)Y zlUM|Q9y8j4Z4&dK3oEhLa=bSgGXL4eKTDb)_-8RGH#w6MAIRi)#Jt;L6Cl3r%$=kc z|6b{j#EG6+PQ@dX{zM*$sGEuPwOKNU0V2s<|l@oaa<9KGBFx zKEDF*=dgMk(TiU#%bdgV9%BrFfg&!XR+eRbY?EAI_G?r8+nnOVVgHSQa?| z4qJ{nY{pu8UKHQYVWV}ie6rma?C{IwW%E+XAAE&Grm7$D@lwE5&N#$J5pl<1KFd1j z5WR`41HYW$x903^$Ct2m_+PUQcX;dYf8ILWS+Nck>rf8skg;Z-PYx3n@Ao$(FG8x* z5YDXi8^4*WU)kP7?p5Ak$jrLeKZ`*LUVRjU@(E{9;=_s9?>C1(m%AZjo-8jq!8^FS zqVyG|FNe}+e4ex9s#t5F@$t&_tG%|0_8#Y-MSCw&ZOzxkCjjvQCBIN+R~(n`g~*$q zw*lzDodXBL!j3d zWexhRCAYi|_J%?X#~J=v49DC3vkdzen<0tM`89?wCD?nDd?kUKUN3$g@wE&?f+cm@ zjBqXi3!<2^SdmS!S^h_}9QS(5alf}5_f;%M#d4Ixa%4;;{9Dx-uNpKZZ!{IpCG@mk zmRV^oaV=|`HyUD8di=8(mH+Y2VpM))MkRgHuQ^EYjXBrhT5yd->?cQjJ zQCa4nCB-lNv*i7AGb-sbeZjYq?DTN?wj?t>m9~9xA9T1K0^em}8Rt8j!c$pqMrEBh zDi3?3@~4VXsTh?_WK^0(ze{Y1G>fulp9XG9Zih;rC(lG^Eg_{#nYo)jx|- zxy6i1`p94OPPR^f=&6+Fm4x4COn;&q=5fS<7s$YEDT|X*ynZseAD({1Y|o#)?RnJO zp1)LVPsR3>!}ers$LfocC2WuGs;KRW)?cf(_I84Hq-qcUEOz9({#oqEcg&8&2N!YK zynnUHpO+dZ3n?#t#?z8vNBF_|WU?cdH{gng=XF}@G1Jn&IxP)$NCX^H`FvyL^NnpC z{;QAF+5i0WjTxt<8wd%D`M1m^abDoR@P8B?jj3>Vrt{t9Fg`KKFkA zECcg@`Dd{lAMNQly5(5;rfk*n&hFguh534aqT#aTZ5L@ik?m$Cg8)0+Rko# z^$LFT@|9g(RPuv5x>qgRucN2)@I?pB->E(&YzrFRSfn zThV4&bk`oxZX8HhzJ$omWyrC%yMwS6Rol6&M;?WsHkX^68!uIHpTJcreHbql zf(grQ$c+UNp}*%QxDu6S97}ZMlBI*C%mnYh=EdUUC)7>pc&jxTKY7;PC~WWLoy$5q zI14(U$UxW2O0%n8)K|GZ!29MD@68>`<+eoL|0Ci3KS!VU#Yc(r&7wq^%)brHZ%Q%W z&IW9m%zq+b{=Y__`5AjG`rctC^KS?98&k};t&c5}`TtIs|K#X1zh10PycR7-XEK@p z8!*2iW`6Si=9bC)rxNBrJ^IXV$Y6eHn|}wGU!P+BmTmK&NtnNJ^qJq7!F<`G$&~#6 z1@rSM=5N_HeDJT9KdA0Ma`O*4vUkOzo<+T#y$3C8E9L7){{8dw z=&Nv#ntJqAV@IFQ+h*`tW=@%W{;lvia_U$3S598yd>)tZ87J9BTb{Se;IkaJ$>j6h z!sp0;hdg_8@{*S4>V(e|MxW2yXYjf7Ea`W`=g3tDpZ%EmlIHWogwHjj&*vR7_$=GC znezO5;dA7buSi}ce~FuoNeP=Lk3O4s%wTirsm~vT&5{4TA~_!O5@++2gw0b&pUpdE zu(|Xk=N@5m@GL7>eyA~-^-3ocKXZ;cvWo*(rzj>R{XK`%?i%U-q@9SCE7EjH4lC#h+ zaW2nHxV-J?b9s*pE|;DK-cK$^_M&G?k!5^($jS2dqtE3%Gq_xO4){P1L^&G#dYZQo zj~QQRaa`VU^tn7MgUh97fDe+(u`D-jAza=m;quO-&*i-`xLkVv_Yk<;8ZO%PH2Kx) zm$ZMeOTy$`N1w@iXE3?+bDL|jt)BX)Ndh7 zu1%P{$LKS8b_SD6PyE({$=^5W&2YT9j<&dkccJ?%H zAw0&7kxr2FqtD}(3?7%B@IBVke(0i*$H}c!FY&d``h>>~qtD~k3?7%B@BM9{XI04K zh55!UM35U3CO3^flNV$#x%7PR@qwP6w#ZtvY$3iybHe17(P#338B8uc-y4EOPBD24 z@h#>jOl}>0CcmnQaP*mcPzIAr&-XTv$z1`H zVU)KJQGR8@<%33_%dg7da_I@*-v?GMUK;suI2Evkuo<`VIw$VcqtE77XRx{SlD0UEbkf%qEZZ-Gs3h-zX215Cyx^JnO6LoCi?gaDVcw$AXI?IYd8KD_|61DCKM?Pd zE(|vOHxK_7C;VG7`uwZP;9u#P+P{T=(FSN&i`VhZ!@olk{&kK%|HfqSuk)AZ~driW>Lr0%~8Q=A)D?Pt@O86ITTXrSaTjg?_hksoO|CWwE|1xeM$(P>RT_%`W!{W4W1{|dstX!ozH$uEO$9{wGk@Nd=V^RK4Zf6?n~viMh(6aGaT zdtJdP!_C9LBNF}{Ir{vYl)=A}^N*^k_MYxl@$Pe1aCm<6@b9REe@Bl#|8P$b?&68Z z-;(o>sxiX9SpI^I<;}ytV-o%yJNo>alEJ@{^N*^r9hm;c(~sb2<>q1EYZLbMjXwLP zX0Wg1^rLDV*%!|~f}>`ehkdV0*tdH0**C42ef1@0A64VYzG(8XVzV#49G9@~_|a$I z^bGcuoP1POlYP6BG8GH2Un@ zDuaC`_fV=Pl6}$4V@2}y=FPS8^7@2*{iDymtuxqHa&x4rhU|+b9xFEc!pq4C`%W2s z_HC2FzLL8hRg=iR*zXI@A8($K_tb=ar;R@QW@fOj^t@y8Kzn>Hr7Jk|x_P)akZ|wx z(dXW-8Qd#9>zFdo9v_|R+U#!28435!9DVNXmchN!bB?J4i{sOMjsES7%_DkeCCoc} z^qIGN2J=eKIHvW)=N5XJHurAZISKR59ew7_FJ@jt>G{TVIgrpD9Z1;Ri+yiM*mvIO zvu|Mr`%2F@X54x!&l;SC^_kq_9IkfbrSrL5bD=Oa10PYSI;@T{{B57h?fRQSVdEE; z<`t2{xA5>YO8mc}P#EEr%J}X2eUe%dVl2K;c;x?bxp5CF&fuNb<#H4MN?a~y@XUWA zkJA-ru;rV}QEB>)XY3NKH!sY;ESJ0T6)53GIV7P;@fYQJd z;F170worKd*QvDQ6gT*@fNs3Qg=wo@ej(k2TyFZpLLo{!(UlR_rN+^P`At#W#wUYv zw<;7KJh)I8J~qH@oy+a_TJSEU+eZ6h=>C9irqV^Y?X--M^8z~S`tt+a4w^P9cSo&D zRPIjNwvA!hU6d~o-L6`{h%dWo8BxFO?#jIV~w@VxHWgpicVcX^rhsDmPf-+vAX`^-=pgf3p55=NvMD1u)x~M;(os`L_ z9c^0f)U`pms0ZaBlIPbjzf}GDRVQYyEfns18{!Y4yc1_I(-ax})Dfe5Tb9{MRVAqa_FD^f+pNAzsha;c={dJAo_@wfb ztuT7LUM1}r~=)n0hIM?VUg{XX)$UvUO=2rwM; zBOUWFoWab`a8~a0eZkkUnxDaJ$H;lUT((zi{Q17zjeuq7ak!-1#VAACi#j-%$Ui+DVbU2cDVJ?@vMcQcEbSGXms9d~NXk$?53N={E6(_=bvJooI|xg;DR~i{ zkbZNz0$B9J;byLdZ}H!ZqutYX7_7EhabY`*_iP7YmTNfDQQz42D&q#@|1pLO>;~js z?E&iGVAe0}50NX_P;D>%3#|F6et3B%|CIO2zY+LJIv!X%e0!&&?fkL5gxOxhS$ipe z)^7$=t_-LALz#yd{|sjR42MISD+`6E=J<9~kA4AL`V{Pv+D55LL`V5b(@{403-eQ4 zoS&u*>9pOFwhNBzKYX0v7CW4aBkrKz0e3CvT%6S9`=qn7NCo&?4kvLA*UGdOM;yMq zHi7`TvwS@cbV4s=xvDeqf0d^fx>Fp^#R-nKjC3x}a8;KA=i&r+BAy+N|M~mCT(xIa zE{?cM4=fa(8TN5TH?)h7Bksyw;YDAqbc_=m#-2xR^l_Lea9?-&^0uD7_O9;sLwh@y zENknk0H9rkemx6kEv+ZxsUAimY+e&&JRy)Z$U z^Ys}&_b|Wcj<$qql4hX!A>RqecZK4p#v`9`<^%uvv-s_Q2@$v!+P6U(z@4Z>t-PFHYyK8|MK$SW+}t1zA2Cz zX1(#Iwjv(PYcJx#9$t{#>|sNb&&wtSPj~h9Xzg>kS(^Xg$2yYyO$5K=i!@Xqg0r27 z_4!)BAhO9rKldm%A6P%u=hdtxys)>I@K@> zS^SJ{&zeHvZ^tXnU`oc&&lP8M+usW%TCO;Qr9FKaxH~d%-%(sxm%)!I&dQhx#iuRg z&tNeCuDu2uA4wP1c|#L1aeLQc{>NWf=Z!ZhE=)U&v4B6T-|Y88qduWHgGFQZP@LsA zX#@D;44A@&!e9OdoHHZ}gU7#uA^H>38f<;9`7v+SLHtKo7q*jiRn<~D;@Bq9WY;#U zmuRx9A93UdamE*>CC{1GcrUy}-w-!~|NIFKeJD8Bmx4oI3(oa9%b=X7I{CDeG18f= zG41eI703Vl2@d^AI+f>vp3~23KmF9+HK)SNHb_?|p}58u zX{dneRmzVIvlb@V8|pycqPfCA#}2UN-H?(yiBpLhI>{=obkcLqfR5llf0kyKkHGqf zq~>x48+}N(EgC-auaY!p@U|x*4ZR@z44w(^@|pV;XE5{Ia9{>5RhJ#my=Gwy7Ag6* zrj2md#Q9D7JUpRKE6!jJ>%%Us)rG5;gQ>dA{sz*1LDL#MZzk&Otc1a$QO?~kI>ABc z__MrO=XDTQ{)}!O#^)qI2Q%&Pp-N|IXG7?2|BT`cp7mDL+4Z@>OuK%6rPKDp>fC^K z+(n$hurxm^6#n`v#VKquqG_#M*4gs2dWj`+^|LlnTdi$Y2eCS?F2rpBKg8-dz6cI{ z6P)9pl_yrhrM3Q2)zSKqZWw(nR>JkU;LxvvbNx%)1}EeE&!6DX*Q8VVYhNf1MVDHY ziJ+MQi*hw4Ods;z4ICcHIm4>#?)BLWL7Uf9LmlZgHLr$X-6wp)gB7*D#wRpX;2Q3N zx}h7jZctJ9L{l*_B2M8#;U5$5br?*Nh%_jNgPzu!874RJo7!p87wSxU7OI| zfrb9_9i4->oetH$S8)c)oQ=JbEF2uMht5^H zY6mmF^)+#Rg4bGrm~ciA#7uexU7wb3Cy6%YuY!ht+{NtBch^a8eh! z27^L!8k>V_*INjkKEFBFE;m=^r zhM0l+h88JcnHJ3qG0HK+;p2;EM>~2yy4Ka^3SXOQ=4grWAG4&P?>L-;Y1JS4g5nI8 zT3wNW+fi{64_Im);*dsglGd|Q{E%*K&v<095QgkpFs9F24D&1pW-3bs!AMTOH29 zGWP7DIBUnuAA;`diZhsF-V;AmoWkIX@JDf$kBnh1KdZm=vTKL&NO02Lo;9macoQ>O zu6@o9;no`Ze7L{Z_nhrJcw1e>9(ilvFWS<{FTJRnXiV_ZVlHYhCct>eco}$twN8NE z=@Z&i_GT|r`+`}pio*{Ewb)O`oRM%wU9YtrTpG}|IKMS;QVn%{K!(1ORn^cjHfQ!G zUla3O5Aba_)DrKDqtm3mVF6B{l;^qJ{yUiJqt39#BNX<7@n3`o=`n>Ke$d*@zC$}m z_q4T}7^K0r!{AbDH*tusL*9?Ob{|g+(xFatqP3BVdmNT}=y9tnalT&jb_$$32U7rt zZdN*r7e{DTF>V;11Ao>|nU*@7!4%XDOO!6c9Z-xLzDaSG->hD5CJkm?Y$UP#ID$U% zQB7+w`A7$hKTEsgd>DuKD9&I}q<3cECd9bvJb37o+2H9IiJ#s|=?s?s`=#QP4%6qK zn$jDLdO$XwK>xAd6fP7Vc$J@OD{OM3`Dxp*WpI?W*I+ozAGW?U*yJm$3*-fLeyX52 zgH7hby8LbpKK;DVtfBpow#NqHCP6#gp6E7&w$HR)fpkEfbB7;wN zbY{9i;KFVvdN+ur4Z^Ch2K>*T#akR|kZ)-gx1qT{qSrZvG+47{ZoKD@{Aiiar(RzttXxP*cNW*_DsQvH zI^BsBUqYR3XHFj81%~7PuPM%8smE1{Gg#^*xTH?fM=N}tYF(Xz#dM$~;hVDiXk90g zz#%k7NnselHH}ul;w{eYeKat3r4~LGASUf($jJM=Z)XGepdYc!Yx|>LD&kZUKTVAP zFe17l<6$bRZbGQy5}q~*)497ft-+#%gNoBM$P1NHI)hcgNB*dEmPQm;(po(JAA=xt za-O#D_`bgWfj2PS;hyW;Xx)d_d(8lf930*@o9jdCkp!9%E^QBQYiYDv7Ei7-4oAeW z!NC8kJkPD@N4;-lMNjuj@7rt68*le=>5LJ1KJ+Lmb84zG(_LlopFfM2b@XAy87vh{ z(apRYyp~F13hH3eZFI74Fqxz{Hm-pgAK@9>j7rTw=S}qzWlgyyHPtan{QnxdjPeNE ztuR#nO&BA^zIk}+>v0_5N2J5};NaO9)1GkRW3W{97Ns*-sx3GYJZg1cs&#W+>+qjHix{@tfSCP(Ocqgcn4rm5joislyj}n`d>++^FY8hmpNboUUg262+-(aur z&x0LnrhDZx)NF6gW$D2Zqc$jba6i_@VAOt3v_$-S4@-;1jHGb0nHD9p)`*u{3!TFu zUT{L!)0WS3xSrq0G{<`Jje$Zs!=a=|@(*Zy1Bb&iqSL_4 zU-PU=K!>F{;--dat&QP1&z-dm(HT~lT23SjyL;U@h*d$c;Za;js^G$^bZFA(=;tEE zMaMiBYq8NWRM=!TElS&>tbO<^SdIMw%7cNMx>j)tI~F-yL^l%9jW{~N<#KzW+a85G zNI9}&X9g>KHLd0M_;<-(#VM@pHC#wH)s;&+&NZ|fEI*7hSgqv|MjMwDR({xVsE5De z=rGT=V|#Mc?|kbnpWma`ATRLUjz=oY_OicHbca}b5ihW#yC;PGRd;Pseuf z2&lC~VWkV(!TPc8b}UX|ZHFC;3;V;4R(M8rcQ_1wJR)_s#3}Cf%YehC(A^S89FBARn{>W>!EI2S#Syn?9@B!} z#SvG9v{jd5gG%xx#&DiqaA)H0Sw2p1r#PI86CC@QbS{p#99*-iix6C#;Qp*Qiz5#{ zay(@0?})WHhkF|4Cy4{@eIEqfp^DSp2*Qx@BQ1_4z_@`&ldiNlhwGuivpB`cagE(o zUJAP_&UE1(SZCe9#JpZ$%=zJ<=whhB`2QJO3^f>f4fpj4XOb008Q-NjLmB_kv979~ zHnrY;#Y0E1dHz})8-qQ2;7S_wZZ?F!3H$>oN9{*0!vCji@Nm@cwp66k!)QE6AUPpU z(z-NL2Oz~CCJx+o@Cm;F?o`DYeCb@YR8~W9;LX82D5nP$7Wek$Wn6!qwnn@!RPJi9 z@HRiLqt3J(q07^xsEt4I)9X&v-*v%^+x$bx5A1G4!MC%52E(6hKm{qHz$uKJVTLyT zB&H)yoe`h*(F@=voUL>UgXQ%$TQ(Tgf~nCNyym@rtTjl}YI)Wo#c3LA5^-dfcn!xX zvz#9z%=*3eB8^$Wej~gaTC761->9t9(h5g=zX%nl>o9nuM;Vvz@$0_uFUcw`6?rm+ zu~cBNaW+_rkyBVIFzCU)!qJM;G>X%sX_iKD8=d7hx_^HJY~DrFDy&=Jw~JgE3~lQ} zUBuxwSXn>lG|%cac^tIS$)v&47Qn0f6U)G;>R?*?f+&yG75^!RJ1d>VD{qNYy28;) zXYFNI4m!uo>LOi!kJ4#-2lB10vW9cK*K7;6^j_=?>9yih2x6eoAA*}8vO8ZBAlwbtwY zMclyrJpY|oTyn5NW+iXz=oD(Ea4xr$d?!kVbVMa@bR};jvBkTR1;-1%ureb{kSA&J zG)yoa@9x3aaAM?i!!}Y2Hw61C`$C<54b*t=`|b}uFNCBX?01V`$Cz+9*t3E-iKp^S zzpiqiR(9yi?a7KL`w@9f{e?HBhI+v3y?M;RF=01AY9lz1qA}+x6F9hSzzj|6tvHR> z!Fp(p;y9QO%_$TQvYgErozIEA$?y5ZyLo;=yN&0wwv z+KC~9sW?O5)clkVqtMnyXRr#^(3eRU*Kg`CGH?$lPTK|(cP&icFNrf)d8LP{jh8A( zwg_)+SAo;CG-<;y?J99vhSgt1PU)zcLti$TGdc>J30;7Dz~S(p^9w2uPFw7?Y-i=)#$c^*fwExQtzJD1^=H2XWT+dwL9og2 zB_7qTY!A)GYluP-E4(8xOB<&(R&RLQFA)ba%wVQLVWi`o;;=)9FVUQbFCi6R;Hd1h z*&DEEMjSovZNH=*_fD%7N6&nx)rG>3UxT>&6{m2a@TZ3%6w4K-Fqx0?7st4JUx`i{ zRGh*pv>R`U^Lz5WnB5F1&fw~HlrfPwoDXvF^m$lD6yZQS9W3p>HG@vvNk<3R_#?_B z<-w0R*2*v#|My2*j%0oYgIAEz#~xLj!pcYEsit8bINRim!UoK0esfg`+$!t>J7e@u zf#Hke|6^h(47R>X8A8C<C{eMqJ8eM#f7@fH()O=~$KXV81U(;992MN(TT#c@mFxBbAmIASeL%`!;b=}Kqt#EH;| zX^Jzr`m5+g@kqc$2lJ(l+s{)vgRLxhE;x7vCn}da#kUX^PmT}1-Fr<$fh*I#mgO}8 zk6B+~hP6+7ecIP74YRj+iz5#AjGV>)r)tsF0IleNxqIj`_0aX+9ht4Dk)_`EFw`1v z$>3yhxLEgPk2+XU>$mj@w_*)YtE<_is3o@TlJk-d-uK;Djl*1(KZALq!Hz2%%o7cE zl-OXdK@VN8X$?2?he&&y;tVF;$kGhl8pS2$u7{&>mEvYOc*nJH2+mfV!5lExxq&>y zt#=z!RxhrNTm7sK#93VghdKz()y48w?rOQjF>m6u41S1@tI-Yhq&Urs*Y>()xbZ?S zUO=&cjbBZRmysfV1o0(3@!Y}dKyPKXVSRX9o z@9i2KIHa#oR46*9=<>y#=SOM}HQKgZIO@y&l@bpW#mUJeHom zt~i4)U5dft_lh(4GI;!Vp07BAtv$qA-g4Z-m0|T4fpYDzx)P^#wpZpFnwih(UU=A9 z*Fv;|8J+9D;u)Qh;(Sz{&8xIhoVBr1I(zf+tgzzrN|L@c1FMfabxoht;tVfEEfDl~ zz*#xnpMQX@pzM!a)V_#S=5JROnZY|e%IbQXM`5PJstiBuQDT#<2pGjN=-%&Wp479E zi>xfgk$r=ASYe8jmcYhHE1j(&Zuns_k8bBZBS-O=+-|PfAO>Bl3OZ z8cl2PJmB>8fn3gDE1#4`$8+TmK~4BGn4{AJe^i{o*2a)-Hnw{2eW%hH%(Co2iNVGT z7y`bDDJJ2}Vv!0K1y5Fey!V5VX43)3Pvj3Q-M`rj6_+vZeV3(DI%>i?xGfe(tfgsw zH|XD_bOxUS&As;ql3Ecl-cYdz$5^Fs0E(SA%K16gSYC7e=4$WeiS?95*@1k9p?TT$MfM4V?t0 zV@w-zY+x}%S7}G^KYtc)adwlEnXM)goujoF3-DE1i{S@-EoxoYc6;k%6+6wNTsN`_ z!w({pPogf5Fmt3PE4nQgj~fEZ$P)hN&(iDydNT|LOZ`)HGqI@okfr6Cw_?<9y%p<@Jdf*s9+)6=E8G5RR<>} z;8lb7GchNV$$fC1+fcy?F_;l9dklTf&*TjioYY>T_CL(tP{Etkv&aS~cVI4^g`vd` z=io^@!E)cFIE9@~eIWz)lQ=D%g-7mDoWZj$0=EuSoWazy!7DRxH!3bHcf(x8SzUQ@ zoF&L7OG=;mFbk+{^AVzYlv-Jaa2TVB(7COw56Px)3XEUXb zTz~z<;andX&sBPv7Lv?<0M7*{yw|iFFigqnityfesnV+TGkz$}_(GnK3_6_S3uoU$ zpEDU|sg55vJDlTzwVfW5@xac2U$w zFdM{Z#GE%i=+)b{t`73b2H9d>g#cBrRUf?0uWL0a)yBI#s#B@L_w{yQ)j=uM<;)WN z7ca?R#9{neCquc%Jqou%&&Xpe5?FbtZ>D*=f8K-r`9EnH3S(USp}mk}F#aEAGgX7N z+>N65aT$Zxx%?!J(iILW#*M6TI9J}Jk3gT?%8J3&Emkh#9Lzq}{5(!POJ{=&Cf&vd zwG8DE>LPvYaU*LKr*%<%VjAsb(kYJR5ohgSeg$Xj4JW&3*I7q1rSVA1FkX>v-6yQ8 zNkm2AmCwcMhd@Y|VAX|akZ-;Tuc=2tKx4<@O4sK#GRItCYqxRfL@W%8`I_`wq8>l)N z8!ig&uA|+C;H5De27-MNLj~4+jwT!mHaAUOTl_MlscWbA@^A=5D)BS#3%*kQ;Nig4 zG*sYfqC^Un@(ll#)p*6}a-h$95{^wg@iWpvgB{HGXdibtgXx_QJEtVVnS<%liuQ{_ z`ut=Na07#tG4q4Ae(qw4`=Xh#7+V?D2xra5a!Lv>Q@24uxV3{m_ zGerky*H+!=>=GuOy=)hz9bUw=#y`hX$1A2`JRLKoQ)|aNRcP((ZWU{j;IP~y@*@3j z`k^>FX50edbi?|b{W^jbJk=1=`MR=PtF!TvWoTNh3kN{Kx&APIFs<$@D_sG7NIL!( zBPsHv<(gbcT_7u}D5TR_0F^(3XKKIjKYtcqeX}`V7&jbT{b_T)fOGJU0~mG1 zL}SUz!Siad%6Yx!XE6C`Wf409f#3$3`&OTDvc8Y;RzDVy z6W5}jg2e}8&iA|rOE%)Cl=y!cQn13 z#n+e43Q0D`5;Ck!9#YLE%E-i>rbA zKc!O`rVee?G7NSyva8Z*JdOwb*3&7>IZP+r=;WB4C#zl zf`fe!obZa}YTH%XwSLTR=zE%<^1ux>^^AYJx2@ZP=IzMuQg2&LRfGE|#I_nGmU+Py zd(lW?oUuhRJ=<+C=-K*NzD65nX^j*&P+woy$jFPlU1iy*PPpK0)d{YRG|Lg#mkF*E zNsJm|;oFXMDGWV46@7|6XP+wU`qcH6(LFHV%d5h!B~7jjwhF_$oXm7MkquZcu@#bE zTSxD?$DP)H&N*vNpaaw>4$wP1<0paXSEJ)D_DlOjL7t|5D?Pj#DgNVR!_-r>9+bhU z-?B6gC-J~Z9C7lBS2Vne2)xtRghm&0-tdiJtI1`4M`64xKq!%715#Y-a4hUHSCPvc zPU3Y%!sb9+op@q7S0_M^tqpdB!mh%Swmly)u0b5ri?zCxL-Pg#=g6viaj*qu!_v3_ z$D|8U@7w$V6S3<+(`z^h|IfgGaiUz6E_Thj*fooGdYs~>naAPMi1+YK((x!Jyb8dy z2}8Fj&hoB-4OEtZ&cW3fGN+uVbP99L8g}bi;tbY0X}K|Os?^Vyr_E&AKo0qMiSKul zz{~u~tT8AUMkg{A3Z|^Gk6{$2u5mbl(U>FcIx&Os|0*1ex>xBG2JTY$(bWzoFmR_8 z3V*!B;T${(GNR{yVe}m=j7$t3mN$;w%kK^Yqs#&f>KOhSPYh0&!?b ztN2})`j+gkm6&a|T5x0<;qFCNbdl%DUZ-a`{rs)xgmv>#{tUbE>$M)$>hk)j-(N7)y~R|)Yw+e+ zUg2HYJ=ivD1pa>>jX6tka+LLpuBxoTzwLBWhLn#sScLDTtbZH4ZXyickiz#PGKCw{R!s4BZ^ZPb>=bLlVjYI zUqjxvDo$Z%sD2ybAbZGby4VB{i-sIUx)?X@wZvE*T)Dz4(7AR_fVSC9r3O#9(BD+5 zFr3%7pnlF4DeUq~;r?_F+?v_0T!GZ&4XPWm>eG zx&WSwE;!yRFP$7Xo{D1$XImUg;UCi?fJb5_9Ir&rz$4Kk$1BP2r!GG!*V^fD(q6b- zP2zUF#}5TyB#lJqjF_qgZdYI!Io?di;Wza~JUrpmHWc6mLkCZIs|^LfIk>tT>_QRz z87wRkJAnMiF2KSr!42e_WUWMu<7K|;tS1KV;m5oKYgG?s;v5k0Q%czJS``0?;tZA| zpV`}0}MJ>-XaO4&m7NSKr*QahAoqd zKt@d}f-@*46#>dbAUIuZsKBi?sR-_`-(ESQ)kU>20ND&lVR)3gp=U2~bP~^j0g^CV zaSFTMZiwlmM?_UDAC)pYkr1ZU#cQhrjQmI8POaAb6lNZ<3^yoFVdm!tAFH!S%tw_@ zVJ%nBNXK-;MGEtw%{^JLj^aUzeX83eWCZRoQ7+S3x%7WLe1SksBoe1 z)2TRaEhCS?pxXyoEmyuMjM>&hSah#doWa}uDwmrBFOollx5Gqs!Xk%r@TB9+LBNDV zVB}9(TdZ^u&JE~>+X%XvM@a|gL132_^&w8{0vZ21-gkPh;uNNHV<#>QR{67Qt*x$; zc0&FB!L+EKz?e8+i1ILzW*G{zT*#Nx)ufESd%8af>}32JO&j69O5T}kKbEEe|~C*!Vug8R0^N&U234$UlA z>j$T%9@FJq?)|C?9PiCG2OAjX&Hu))RU0aJqs~d2Sjq=sEv^kLrNHPdY!^NAPHl<8 zM`m$1+)i;~DvZ;?jd1kJI$1^j&X>4qZ=VLRZy?^#HY% z&x6%>ooT6*PF_FgcR0lH$3xdlbNB*VJ@@dN@Asz!4Sq8=C+(D=!I#5xx&0K)&tNM{ z-xF(L^d^4_=+IoQ6)U8v_rxY>uCiu?Y14F!kV6X;*E&hx6Vp_RTW}XF z*ptY~#Sv?1YT&xsrOF1k?tm5^=kjxK{uXeqQ*j1czUZ-5J;-vUHl_x2ummE%!3z)8 zm_yiID>ScMt}B;o*&daSu}gEg#yg6z%W}E;JBzU0aQUAs!ooc7_;eBWFuc$M*DF<8 zk9)B$u0t)WXwAU?_ab~pt1YaAK@v9OKYuM#n6I@)agG0@IBkpK>VKg)ZHeM`{+r^o z9g5p=NO9T<#clt2#c3N9C$ImZTzR3;)kR*{I~O=OQLGbxg1a2;cX=eZ$G|C9mf`Nk zz+`nIPP!WTS=|#H^0PK3IOJ!%FdXwUo(WGKFL!N!8`l{@qilYJKmhtMkPj~Q;|qq6Gsi0rvHvNYx!b^F*FIz z(OH@$7`E=aOz8|h6^rS2ZB(4W7eGpHcdnhmS777Dq`+V+i)}P_`6IrGwc5n+bn>Yf zYx3x%_}yS<^VvkcJi(9Z*e$e&??Y-!rPW-8c{gpo#Sv?1cn7zA=*?h`boXHZ;?Lk^ zzelt8R-D0>FPc+dr|;T*)VBsJ)p8mnxZ9N|cnDc{yDBN-{{h2#sg^@8fcLj*8i#Z7 z7RS3?^(E{7DlR&>+qF-7_^~f%$%+*IC<=nhZ-rAH9{ZG~(!$w)oTOVEv6iOpD%)_+ zH4gN>8_A5uE1J8yQkI7#c$$U8|g9=i8` z0CPCfD}y}D;b;&l$e+O+j_!rY;?H0XNA{Mh!B)O)fi*J0b=vO90MX{(tuEREn*^oC zv^PA~G@Sy4Ic0GF)3&1qwQQrc3;)kZ?TX#tYIK9r$*u~Pv@~azR?+|mk(>QdM<+0j!J%vS zc!lB=#^T8Np!>Mu6viYN=64TFo>>=#L5I1?ly#0yU{oKzyB#aic!&V(K($-!P#AUo zF4?bX4fneyzqq3?>bxKF{G-x^ID1{i(n@}g2Zs9_%CLndgpb)xrsP5s^H#o0$8369PZzs48hHp0_opBrB!?X51YD?@M(Ih?cuLW#bg23UpD*Jb)Lt&7%K zcbpp-{Yh0fT8?)@Yavdl9cK(?vbq)Q|C%BNAHbcbMNWUEf7f7tSBoyc$772015ahB zV5|C-?f~`WelK|m^MVBoZpq(88>cl!%|C03q~r83CNy#k8~^ze8#~>yA;!{x(NrEN z32_QTk?w_pz^@@rVRU{!RxlSUPGJ>6Jq8z--#V{h$4s1O;SYD%WytlO02dtm0lHO~w#oUY^_-|^@c^sMn9SUv|ve9Ld zKMN*vOQXbpbhur?BZXp&l0uzxqVcd4??9!Uuqf<0L+EUSSBAk)`6|uUDcZ&-yB8l( z$LjJ2(G-_Ecx^{2WwiK@N^BGpG@jN*8Wjt>zJ|QaX90wMj;Mpn4*yySz z*;~A;w%~L)tS2WvtEJZfyck9gPH$>Bv>pyV&ayvMk#gm|Jg%f;yb5msgYA;>D44pm zX~L<$_9J8m>lzPqHueSgmY81|oY|{o?XAZ6e^zQZyu^wp6&ue&tT5tG7fwUaav5pK z0sJf zsw-DPJf-2Vde65a{GFx!PPfmMeqVg=imug2Or)|aRzgF!oJyT zune#0(~y6E!EkD~#wu+6taPH2w>zCQKBG;1?Lq}u%Qb$e1RGA0l>Qyhis{u>Z^f}Y*1;5O#fd{bxC8a5 z)!fqR>Zw-U)A9a!t-H~I&6jBz{Ldd(9|y6-uC*tIWsrAF%m2jry6!Lq;vnt~JT(W; ze8ev#Z?zF`=X?(b2(xg5D9f#)&2+G}k!2WeHri-2eS@u@A>E``fzGL&!4xyDB&X^0 zWEH$$qkZdRzjUy6=$%hr{k5D0gwH3q;=C=g*88}3i21GP4jPic#d{T z-Qbyn=$BV%T7xIyx%$tFQ`q{2xa3+msqN=g8OT}6;kE41!xEovrgm<4NsjGr2gjVD zMKX|l+MgmZnLf|Yn5JokvjVbAp8b{8{`yNBaAU43-W})1BajYaa)b zPQN|w^W!(%huXCagZG2&e{8+t3}#xpR>kt;w|MpBDFoQTV)s7n(z-OVR4G3nzM$Pf|85LA?drHYh=M&CywuNDU#%l%_{P4Wf{R;Z?6myw|8nEK z!RoN;H;fIYlZ)KH&iWaw_S@cM*L;u%6k_nw47xRn(|FKH~lRg)>Me&jROnMXc||FsS$Fivm3-sH+) ztT$Z%+~rEAFtSE_>@b_=gZ#*s>y%FOfdTj@2FR`+{^rLMK210TLk)-iVL~gn&q18Y7R$OXV4mfCEZ{A}}~GD2f=6m+;F!i{%Ki z7RX4Z!*Wb%{H>XZjojO%@>eTal zVDN`TdVc2cNOYfQIJdVZ$%;O>+}Uu$xuD&7kG_ZY*}N1{!V}M8zJO3nadVI*7`#>rAgIP*5Gx+6xGpGboB0WHC>GOk#HYI)pqmgs;zc>#y#eHtl_lX6Z^8fBgi8g&q~5+}UQh}(VShY!X> zm)LKd76au^i%NF{|5wq|s>gRpnhDY%kMD{V;b$WJ6pFy?$m=*s%W#LS`w-#87?uB1 zVsL=qf(yi`?}=_HU%I(LaV2dCFDWDoTam&LIz1f5NAvV;(pZha1{^2J{Ny6l8iwW) z85KUz%fFBtIP{P-r^EYs-p4dHKjWG&J}3znnSa7Cgh#{c$w5e%%T`X$*fKGu<6wUW zd$@j{MOc$Ml_RV8B*wY3y?U$XjX#IE=3SV-4tkCxDwqX73rahIiGlkeayyo2@0+7@ zBn~6harhwl+B;u~JFoLf3f#HGolCru0$SoNQJ>?R%EQ=s4R+Zytkcg*d9eTzD-~Ci zg`^RzT1Z#TKiJ}+S#jd`3UtP2MB|zUeSSqrz6eL{T!pZuq6xF6$WIzyP7jN6R}p6i z&B^NBe30lW4Yr%l`4GQE&um8`IK;nh07JA;Ll5s!YIi7@A}hL92nuD z)StFGK&0k=?Oxd7<$Bvt=IZqDdozrAOmU5=2PT|+5w26L{@fK$vA*^h@ij5eVtOsK z{X|nblFI3k*4$6DX2sV$JZX_0+^ZOP?{3#Y^~Eadp!#Cf-b$tZJk?y8h~C@EQT22? zL#Ka4xqnjWATUy)4#uVqlE!-p%SMSNtX|uDTPq*$CHOm5!b;EIbyC`r)OnD`??16p z%|{E@dz-~)9`s0}UH+o9%b|z_7pdi2Pt*))gM8~rybg~03D zcQ&Qp;`fH4Miz&kR$_7V=(fW_i?GOfpBTdKY0tU(w32fkrH?$n3;1G`?xvTo9(MYC`QM$Si>LvX9%4E}|>J3=0 z;#3zK>|j(EF5oM1w5m7AKco^hZ!CM}Ia}v>jxkU@&ufgyl>?4p+=x{wQUcZ9ywS;s zra1Yvm9s>PudQInxax~oy?9JC;emmlejmeoSV&_mN*)Z|#Dv*c`+%Lx6_@*Uoy(Co z+?%c!T4}NBe7tB%M?I=}Un`B9&3dg|o6T=On|wWWdfEq6z6I0mqWi=@?h`URT(J+6 z;&MQ?kGpII4?PN#V+>>bGadrkfA@=K+<77z;4Y#WyADcRE_`BwhT)O<3d3@~iV@;C z(S%V)cVU;tK22cIqW;7uUAkS0CS9_A*)T;5AL%|>5bHE(JxL4wNguJg2t8R>)={{g zp(|KrIeY)5E;9s~aPGs&%X8%PjE94D@3H8erd;iOeuXjdc+ zRL}5DlIT5GRvj(15`usmUY!n=8Y3@Ed3&?RC>-9{rdVr(1H;-7R;%i{QZ)1NyEv~s zEt)W<+@QHd3M&tfhvs9t{&1GCYSP~-G%af7P30ks@dxA0JLifftUGG@24TT$X?}ps zvJU$K@?FHZX!VK1vwfBn>qB*5y|9I?LC>PmwtUnZ$7a^3%Es2Ba8(x56OA&cwn(uq zU0tN{YAlRfN5_3?L3A=$#dMp86gSTep;{zyLzq=|fI69wBkQ8BzTaDLXl9o9czKuM zoMNs0Vq@Yc(M#epj?z`M0i+Y9i}YF-@F&Jd@+%c;J*1O`YQ9tE^qYcuJVdDGK+(fh zg62DrdbA{@99*8`Y(P;YnZsjm8onj}jJc-lXIG7#hF-EI_x+NPJ~R4AoT;o%Y=acz z^^oE~ZmHU99#!5nI6z#@Ii)5zcA~zO9)3?N{ZCkJzLy4rd=U=Iw*+*Qn>1nZHRrU_ zc$xmK?0>>)Tg{`y7Y@Y`iRC<^55ZE$?6Bf%&JmyTfJK|cG#)6;(R!&2n)Ol{G%KNc zwzP7rd$5+)cTS~*z$%RA}Hi!p@WqQVJ7K`)`x9VnV`Dl4X?PFsa@ z9x-HK>5H|hmqh76Mu{IRZ54B9I)y#;k`{|h+8|3>;&nI$Vxp4?9x91u0xb{j+EX3m z!QJpmF*wHWbf(oUNB7q)Nk$9%UFlOZ7Ap7M&=yh%2~8e&O3~UNErOvlKWV+ zVtA%&s(HUX%j#|2oCk{&F+PVFCnzJ~^qkWB2#*T=FZ#*d$%pwy^X}|3LE}7l8Ur6G z;$YGnliTVUFz>xok8GuJ7AIm{1#uQLrGhs*5<^__8E-btZ~S0AA@NSD;WS;NxW=)2 zv4?2Jv6B%rZzWBcNRCH~>|4X2-T+6SnqH6uv;5-7V$Lu~@K2n$V)y~n;}fD8GtU=C zie{{2NaGUSK?m}r#-y07{jNx`Wme`uX~ZN=hvxTaZ^TiX7#o*81@+y;q=8vW*ymN8 zq(!*HNaIKwgVOJnH_NmqBEm(g2c^t=%|P|^m7TROSG2V7iVlI`0cfmMo|tciJZlCd z51ad%FRQt)`Lbw=gN=mweu~8yzu)mwEXMfV9fxVoQe0tpY2U?2aJ^{4>ORiHH0nsQ zWL2ERIFGeeLwzjk^8*9Fnm71m9uy88un9xCY-y>8U(F`BV@asEg1!v22op_laH0ds z_M2A1IAQc7+)esF;uFSaE>~b8wNNzSyw1LiwD^{3^vTCdaqL5N6)${$2n?UCzq)8& zJ4{`0H+FO-7Tk%6pZlb7CtO{uWE4hPa6$S}k!+;G7J;;UC^RI0 zLXy+{IU8na2k5c&ew@9%9m+PX%TsOUnsje*PB4FAH|)8kkTz!S&IP}lBez&dhvS82 zJOFzZZXJGuFTzpNyOhTSgmF#>we80QggMnklYCBbjfcGe+7C&C^PSjvF%R*fiJyv5 z0yROJaBA**gV64+X`ISp@^Tw#1@H9PLNlgy>PcTBYUO)bE15^o?oC?c0TpH(sggP1 z8rQ`6QFs4cS{?Ndd(wYWv1KRdj>M`TwcNHC!X(TLm2Zq<-%VO_!?N*a#i}2P#@i0O zSr)XkdXB>fzkS5Vc+Sm;d%oftUkGQze8x`KwuU}AR?O&Fb#W1eT=Ap>NYhBRXqR4_Z6T?J$A z>-fyIF*~Dm<#O_DxYn^CQ{q?yd5E&CLra-mHlDumYJf1y%Q|38>j=Nc7F|gntfQhA zl@sNi?((vJ*(=u5Dt|I4u>?2F z>I#BM)fEJjsu%8TmaAI{7!B!j*I$$y&vIBi{61QaVMd96kfp<~G>GVzQ*i!@Mh){T zb4pq?r9<XOnTzb#bC6j$W>$=h9OfjBW~gm zs2p7bLJLZ4-PW@F5ys0$KZGGCrb#~fANa`=j4!s2} z^vC&4Y_(oFw8YF>wD99#b~`$r zEP12iVlAw3Xh_9Sdo~Q$064sZprvmYrCFlVP@Z!*V4=xOY#C2kMhsO0+mxLQm$6#X-H16k zJ_j$PGo3WVrq{NOQz6CS9NhfwfiX5R&c%X#rYDR=|9fzv`16Wu%(o&Jg-?sROx!sa zr;)?&hJF%v!jIR3KAir?>;RW$`p+&?m09f07^JIb58p#+%!%J?@h?0^W1Q0(f?fQR#3xMa zz+^-dcG9F}GYyHJkwnY~&4bPK`GZ=TsfDVZGc&1r=MwqF=u?e#8!LMysh0WtF`~tQ zg+WYFk`FEW`D4^tdq#-HR@^f}E%&({MPti-4l_2kR=s**3}d|?(oFYA7!EPixAHE< z6;Aa`5Uu9ZMuFnIg=N1LPawUO;uFSy-vz_GN;F~6H~{Bh%sd$P&Era3;mmh0#f@s2 zkkyj11Z}UR1z+@psHi`drbGR6zEQo>^(nSrxa=!idO|M6iW$a&-d+?Zxu16|iiD@D zcEQyNj0cet!r1Z@2gN}P8eE{GovN=|)V5}9_?^rY=ZTTCb zg^hm$lNO9qw&B8PxsSkJ-zz@hEb8v9v~Vr%7fm?%Vvd_`$o)x6SwdyIr+k@S&^QsH z8Y6DB+)(1uQmxPpjb8n3KH3%A+px!5TJDAtNz90_0RI+}mfR0ImS}8ET~C&|5y2Xo>tY=BKA$hNsOxz6 zY~dm0^OBNzpQjeS^uU%D?xUd99Dfg4sQv@W;u1?Z9r9N930%VJAjl??h>d>ffok+i zj~0!-YY$4SRFV&ke(BLUB&;V|3<>M0(cAp9(Law7`z6fgJC78fFlO&)Tb{!RLwL+# zJOelF&9hO{xveBjJ~ZY7l%Dh87jV5-F050G`q-5*$`R#hjmwVc;Ym1a>OS#FE-JUk zCmF18@kNc^mo*x3qq9YQ{;9M&Q~>)=eNbX$*w&St!DOh?C# z4~ftCYYm*IoFkesJ0NAs4j8))FBDa{16EgO-~qC&_1#|fJ31L3WR#@`9gW*Xx&dR1 zsqUvecQD2;nzE<5!sw_cLx*Q5Jz=DQCee3$<`EdQ5P`Jplp*;tNlqj4MRm$0Q(8Ku zyIb{;P+0d{J$fxkpt+zR}yFqL!B?MrEVn)E}Tb zS$$;8pIdrcj{IUqq;5nyh*>4~bB-k%TlQ91gkcXHgRp3!5eGXIFxh{J9%GCmE-8+h z@i-XI%`Q`V#_V;Y!=d94D9m0rI+{aAhw)YDeH(|7!Ar4;FTWL5Asj?J?w;6k;(5#u z&DQn*9%*NNWQ?}M$y>e8G%9bURi8@r>RWa2X+ue^$VlXE^sAeamY5I1`H2GK(a%Av zUE(v2TU{R#O?-IDx`{@D5>Ttc*o*3=2QQki8l8>;L2ArA_zlar9Tw?19KYz#;=}X0 zd+*6adP^H&`DiFFFZ<^%@`L3R7xe{k#EIW8AcjZDz@Wi==#4RB{4(nY88@Eo!^Mbw zV%Ga&$sda^+=%Y2&a;BVa=f@xSp$vy&57Ud!VISQHl_+*+=+Qf9mGn8lvvW4Othlp zjj0*uA@x(Su;E+*>93x}-hi>piQj7w0}D|>OU#ccuS|K2N5Gb?{ib|kE=A~NXDyWw zD?6r_<~F2!NmA0>{)^1*;>j)Mma-oUNva(T&cQ%>y}D-U;#6~iXn{^r=63N+W{=o# zF8Z!^!lKdKE`~=a)gz?XDI{R%N;TI;J2J5uhpTuW;<_MU=%-8txUzGW- zvGd~TpDBCBd}pOf$Zj-2-Kbu(0*O7Pr@qp*y+)k+oO5Q)?%H!OqQFjh5sRI#=K?1~ zu{DVGVW6c8pqHmg9P^XY>F|2@(s88ds`t`y=s>Sv@ct?(#u!arMP3+zNE3Emq;;dG z&pP9?hoAgeobi|()w@cCXXAC@E2j$+Y!<$LN^m=o2KFxo(4-^F{9+<%5FMlU>f)_o zRV3P1wd)<;O{)BG{5BvwmRb2{JZ34Hb5s+C)5N2HiiOPE#Ai&U4IC+&A=*%;9qH}gnjY_nuazb7Fqi;eVK$ELbg$w%ZK<))29P#s{N3?iiltS zIox6Ewx<}qUM=k@r5LC-1uRAN!E*PnY7Kp7_zlOSN~({2xbZwvb}~LF>FU+jsyz*0 z(y{fer9j3Zd@RtF@XLinAo{r#mlbTQ~Zo?f;D?Qm7!ilz^Te8h?0%MkoR-l`@|y2DBwE%`w5 z6&$TPXz444M6XLC`l;v3v3vE?ExzJ#t)qUCmp7G#CK^bF8Cmnoa<$; zV&Q@A;j8C}7VhI^%nK#FEcqf_?xVeCx{rPPqP8#_UiFyxggI42O>ZWeuui-9#u872 z_{NfN(l{>NO}T|~LsvcvS-4)76C#C+X89Z^w4Hph<^|&{ot3in!#!o$lwQ^f;zX@P z+;AzQPX1b2iCxO-`(mG#Be>BM@9I+aBU#M(YL{}Oha8I{4!5P%nzcnuyZ~!YrWr59`jJ|AM~5-f z9lm+VgV=e|i=Q0d%nKLsEtQhGoFu{PSGqA0bI#qY-f`Jc4RlTQ&M6~;tLOUi)?4nu zQxQE!sZf4Lf(7i^5vMa@AYQm$g%$=MCcZsMTg!KlT}Z?UjD@lZc4v(hw|R1=mvOq_ zF8H{haVL!R>M#>%mxib*i zT9&9QbK)0L$aEN^N}j|LQm#h|%SyiWrsC2P5_e%*=XV#3L)r()htg8@z#)0i zx^?sL9}=3P?1dV^z&Mzjv83EQ94B+yoL|;?Ff(Gh11A#h_5tsJ8mLpX;c)WabK~uKOJzN$Z+SgQE11CdPZ;N)X0>Q_xuw+O#!? z6a@;4&-cm97jLCvWTmo%vC(rL<}9y>CJfr$<@SOwd<;~w&-@8X;jVPb)r1iYMIWW~ zB&%qaIrhBfyXfTO&5md#??|cZgGLQPsmFfPD6in|b}Z3&x{P1TaTuwN6DQT?iqCk#Jw7f4 zPbu-j8JLCLDL!MSyEsM~dPTy{OJzJrWgIAF#PG|G(_g*Pd1gn)5tG|ynpH3BKLhq? z9O@-{0JwK1w_{1B_;Sy(62^LToLw(1&WrIOFQWOLq`1aTL-t}a0vq@rTOaKOx?*_9 z)y<7A8Tfh`2&)&g`Sq%0mPC;ebdgJ949g0aTQ@HX=CGrc!B(1Aff!EA>}ne0NCcK{ z=84^(iBEns8ts)Z$cd@J=g0l0LYtcxxrOsQ;ZDrQSQfiK=EBCZ#G=`LO`+2a-L6&d zbVv;kZ?OHQ>a7|~C|I`Mi_3NEv|oyhWuDRK4B@yHJOYE9KM!I|_4Qs%(FskN?jbMLpYzRJm#usyU0LsqX%Y^xOOHOC1e^&DK?Cxo7v zas5`2)p1?1@EGPON`Lif;#it=wx|r$r4~AnAW9c|21uB{tVo4tg<`>DZRG+Fe-9e! zC8QP1G`wu+aB8Lh$E|#wqsoY39NN3Cm2WiW0{UDr+=j%=Lr))-d`I6{(ld5>n4;yP z(k!3Tks_6^Wr!L~SuDR)Nj~~zT$*gWr}QJLpKbQY;zGDaE-PCU)vToVNUlRd)!$Lp z#`NcPDoB1laflVGH3f%=LF*1#HYlS&Zp| zWApAw(S#B95hjy-fkBI;No#%AVNyueStRpxxH^oziDrBKrkd{pi%(S#9(vB<}6g+Yrn$cI@`Y_>OsN<^vzJ&>Cgebu^z zJLPSqBHynL_~N!@ugMz$l|MC%nK(WCqQ`jY!Z;T7?-!pjTc&+1^F<53O?;+}UJ1pF z5zUz2VtnCuq8T&pizo#DoKEzFOwZw@)qIqJG|7SmdBksQC{=M7d_h zgmXwgw!a!q!cIFfOb~3cSDA$2s2%OCd1LTn-1Tr`zBhNWg}~l(VDe!J=#wn1F@DiR z3ytZJ=JYrz;7qGAth80G$f6gGs6NEtMcV2^4AcX&2~PYr(K~KUT42y94*bfs;$R^q z#0gsWq>1~`!)**NirqL9toAwFfgdQN9hx?~L4B5BXy!s`u7G04L7Hbo6NWOkh7DON zny@77dZ3kW6;?|+e=eFZdKj|Q9*MDflQ;jvHawuxIX(8a*Y~riOpjlX4rOmtlnn+p zrTQ3@OI&@lV6Dj_Ct_TRUn@4S&L8+WD4tnZb6ghhaTO&*d^|-A8tOhyyfnIsI3J}r z(9=fk7WCm_1lEc}PBvp`J!?Q1*&pINWX37Z!<9G>r#M0Do*3P1L=k2#ly?z^mbvAg zFzqO+zUQZ94JI3+I1&7YhZbY}qAGfRs*Hu53~79xYASvkBb7BvhmOiot^O`4NpLE9 zt5 zOv9pdkk$z$J>gWsEzAS?!ZqQGH!2V*4o}4dpYvlaIp6T5!=Kx@R1{`sRDbQy(L^HB z>odywS+*K+BF5(soY`S`CrE@Oi7a#^1$KfXlzpC@dRs- zyFznH!&%#kVGPekE8Y(BN| z7d}3OvGmi7iRofsq=nwoYo9RlV*}C)>5w6@3Z%HvQ16vu>NW1(>s%!AQCTqu8r80> z>g>OjRXvApWj#{Pw^&)#k(XLo@bLIW^q%p|xZqIGDA9z`3Lk|MZYRw+m2h<{AI+@& zF5y(_BjR&@p`aU+Mr8qqvV!I~sjP_W{8CwwZ?yCZ`tqyDMt?aSlDj zLyMMfPW-|GdGk(KR!8S(jFHSQm<;7McG9F_G@BY`bF(7OY$S{^ysz3$v^bR^NQ*5_ zaGz;$j5E9J^dSa1eUvI_$a-Ih`P9(V+v2q|4hW&X2o-@`D zSZd)EC;NPegFYYP1TAVNI{la;k8R?4WpBjtRQCXDn~2uQJ1pLb7KURAy6-Crr##Hj zHG}>T@&pYdscL46A`TXp!thq#Z6;|tY+tp3UX7)FSRCT>LEfqn1`XE0o7TckhT?FB z7&WtH$(qZ@aB=EoOOh};G^@KVl{IcIqz4DNryO7 zVskPi+Nwyjx7tempphl2zND5Cv8^=UL5v&l>!uqRJ>_j|v;0sJ34@0c#YDsyzbtIf zTIY!xD#jMctg8!3D~2K>diDNat*Z;56G&)XMeZ9oO6o7d!LxOxzrf(5v@!35F^+M4 zoTOnML#3zQV@ewai4Cpy+hv}!r5Zr}A}16~u6kc=xMZO=dyhf7*TN3Q3V^X%b?>*6 zFT&OOHJBO01INtDgPAY}EA)STZQ5Ard6UU}oD09RiSiIullJ?Y?A^WJmiU&1&75yp zvbWTH+{jWfnI1kai2rZAw^Zfyoi;VKtR^#?^zURr}`og1+_eZ+d1N7`su+Aj~w;gj1NgqJ=ORcte<= z;Z!ez8ru|Mva{72cNV5P!&(V5Fa(190IIfT0>cRY3LS2RG8Rr@_OFE5KZOYzXE@;- zjxXYj)}BE@XFt!V zaOEso_r!hToy*4dC2tzdi@;RvyxNXdJFnRT#EBToi)|1Fjm9Zm6JgM3sDhRUHx4=w z8fffLvY(B*hry}+MrVI;St%Vty_plgr{Q1p0%Po9--La#bHyhN8pdzG0V525`m3tVP<8jcZuM8Q-n(Ce6GmiDuputOz0|$*=ia4CN!3Nf6nB4BFlQvmb;zW$A5F^eo z8EanlRu8i_&bE^)`O$XfXWI!{chuCbMHaLp)>Qor9Z9IE{s+sdMUDjGMDSZsP42-O zvj+Mflp2hc3~6X1(PH0Ma>gP$Roz>ClfrG}^zyn*cxC3q?|-6=c{smGF5zRP6+>v&ZEt^R#j&fK5h%3ZZrg&d6uGxohiz-_s7Lg7 zeixGOV63$TfzhUhRkk3oY(ZZ%ZDS`*8N)V(C$>kC2SzyN=hX>0%TsNtRMw#HZ;0_S zWC}ZL49DjN%tn9Ae2i0u+eD*n>bouF2^wlOJdiz$G~AIu@2k)2xmH)L)9%a(3k{oN zX+ry}vR3g+X%vn67(Sae;CkM$`% zlBR>y_Dw3Y;

    &r!Y5Q42--Cpg2j3aEFoB{=M?3!bwFEPLm-??J!!B>Vs3&)?Hse zVl21PGP6tYOW`j`K_VPenf{zIX9456OmlEzU7H7(o zu+V##yf>BaU#pU&F?@rn6!51&74 z-XVt{G5_$na~h4qPCjwLdAuYOkFGbS7QuE#ipZ_rrQJfA)EmiZP{fJgZz9I@lmT*a z139KD_~oC&`90EC?-$KDrZ&OX-c@4M*hj)~oW$IkU8Qz5Fu`DB>VK*1a?egHReftX zH;)t>yMS7STJrHM%BK#{Rjz3Tl zg)xi!5Aaw;R`1(V2SoCZE%F-9NAfFV{=)6=5xiXgZ3k}>Jv+`S>VX{y}4{^3iEJo zDWot8*;N%XFbeP#3K>pf!6RUcR7j+om^P^STq+~tKp97y&p4IQLq3!wF~4ad<_KIXzN+DCsL$y|UV9KW#rujV)= z3|jD~G%+vPzeuwiO7d0wtE!2lnfSNsI?|XE$A-3Yoqz_2~t*q(BTw2NV&vlcQa)qwOS5tp21*T7FJ12GDIed-I)Q<8jE&Ezy`F zXvIL{5K|n{a8x5cYuK1x#DR&U|6I@HZ1t+W?`%%uM2z*=s98c|Xyy^$Mlnun7Me9q zYZkQbSYn(}WSOgRr#^#bS*qRC%0=rv5`zq6@CvjrT(Akq=Ss;Z3=51Jb!Qe%neG)| zSlfG3zM!G=g%dfmNH~M-3s&?0mNg1D_w9@4os}m}#DM4Abrf>}W^>;j|JdB|8?+4H z5R09|{zo)p^M@%2ea&i@<{QOEQa~i#b;qEcuj?BK#+pRe$(b{x>AJ&Fl9u5i!IPCV zz?6pkA)f9AnKc&GhTbIL!L#LfE<@_@q z0cqC0Z=5(JjJT-1unr$;m#{Kc6dEV1+Kg3}1?z|d(7I2>@bJyZT^)t8I9&Zf(inp; z_{j%p!VrA8NW-xU{zkJ}@3J&iTUx6xaw50wkoscf9I0;)ItvhO$>H!j4#1iHABj&m zPeVQ~TAYS_9C0aO#D#?62hM4iu$qN?z^&eP&tV9I_G^D?!Wh3e@}R4E#z+r+S#PV)I&9u2=ASe_rcfU#l3%FX!^;ohT?0CL z@rN3S^_=Rp*7R5}Jq(8A5M4E1ew?^DLi2S~MIp`Mx@zn<(si96wTT?EG;kb>?7FqST6$v^f3ao_gCQO=I38|g-nVu`lz65M)PhLkdlRL9}v4!`SQyz_XJI=i3oMEEwo{gy{S(ruJPVSU_}y!i+{!wF`_KFS~TM*A@WiQF_d>S4s9>t*NX#n z2=2Tu{(qJbEwAtErG%3nRtXhLxks+2BBcydi&UJktI-Rt7oYL;GteUcB$_cxweowS z8M9Q&|3frm=cN)xe><#{@B^A{)Pn?C`PhF9UP3eD_gg4s4iaPkq7o{Wa_7-}-otYk zsgA=(2Hhf!CtT+JMLdv|cmhs~YJU;5#9JPV8-gb*4`b)062=Vl@b(f`7r;J-7s20Y zD`EI4Swhs!)|ZwNZrP_2DpplO^f`w`2{XR;eLheN`*yo5Jf-+c~C zAc=V$!2 zT`=!h>0@x11|;U#+IL$>6Js#3k|qtS1A9kP`FIhBYftb}>qS?KQ>_lXhtbW6->VQ~ zdeRc}gsIN*>Buc{h;uvn3J!6CHv5dTzo5H|pD6NpY-s)X*%9as7`S)4zQu{#P$|c# zfSLEyp{V!MM4NzF-EOcbiY40n=HUA`eV}C+sg6U7vE&W$8S}pE;=hV!JON|iqOhGv zC-L^n;c;#uKI8Fd_2Z8c&Di*wqdf5tmu1$R{T2;*^>O^w+= ze8%tnIjkZUdH82MW+^nZP&8x9nHq|=dQ{Pn$DvjYeH{6rQ?1iB(muop1Px7ksAy;m z8aUgAVo3t#yfflBj8w-7t!yejV`@OJ3`-lt)WEhIi_du6!?+T zk?y;3Cyt@%a{@3si95SsicVBq`&OlS(`S|GjJ0 zxv}%gQpNyqY$>J3v({3=Rt$s8>$Kvm-x$eIzhiDLr5tvvN~u^?DgOy6Wf-ZB!;(Ff z{oI(ou`QhO5O|xa7tY z_9!JccK-3?b-aquIKC7d>WTZO)!l((u&VPJlxb$mh?a98F(cCFG0rZel;A#r+>Rw0 zPx(Ft|5srujpMMt>Qn_=D=|Ep@8UN`FJr6=Z{j(SF;<)-U8dJPYu1dzRi61O4@F$a zr6hEwi(8hGHj=MVFWJM=#&~}szWpolutvfeBixzuE84!~TZaZWoy+w7$5nhE(QLE7 zdaH8_r5mmWOpvl84Xi(-*W~PyZ&!Iz%1*TR{v2vv>Fg9&<>TrW%6V}JUV9;`HZdGTBk3==)Gr|;tFFC;X6nZhKzi|_;0Mo z^glux^3SxHo_A!7S#P2_4t^hZ-0oS2xf!0IW;hJ#VdlX_$`=l9X@(mkp<~x+OXz^n zmZ}d1nN)q7XV=W~*{a38FB|on6>SoF$aJi=%&BNxc|;LfS}T2P%-#Cx*6$Wvw`%0U zzfI75hQ5I~vr9D#yF}zdk3SLB34b+I`>bffmY+1HhxP5(AQ#pBrf9~Y?w~2X=YNSZ zVZpX1o3*gZsklsU)e@u!J?RKT!76*rhdfc%zVHf+S&l+mTaKSOJ;)z8%W<62>wFBm zXk#%iI}dvse-X`CIwK9%5#Gq#V+RHvUx}j*PlzULohfcf4_yo0o`1v76SmIQP47>4 zl1pj-3A0hk&d-SQuTD?-Dm`NBjC?b1fLA@d@H4&N8XL?+Ck1zXV7-?6Y&9%KM476{4iL-TwF+GL%jCYu5d}s6p)LAU(k55|k zIW7FZfS$&`S_glCAHzTDl$bhLbfaj-9EYENuV}`6GkfVc(Tqo5kG2qP66P{7H+1!3 zsdZ@EW_k<po;^PW+yO7%}t}+<6RgPgld3HcyY1f-f=cm1sDRFmX?cv!IBxyE3VtiJ*k=P`auQ z1m`Fo>s1&HNA@BZjyL~|W9t>}YS7-#=uUBV`(V{ycCkC}W_2Vz!lhrtnzQ*zY{TqI3LZ@#8|3r4I6 z$B3y_SzwG{{nt2-3ZQU@f%a|(6D`}s!DJhOOjyTNwSYuFcI2MzvWXQ@ZYY(&Z(EPt z({Uu5!r5mS_WvQ`oFOuoQ!-7QF>ndI!;r>9fcX0tEi=dsk1=% z3?5!LboPQ%_cChtt*+U(df&QXbqPP0b69NY;+i?B6twJ5vTEtlrMZQt%*&m!;J8J( z`3n}#1IM(;nR3*`sp+v(GE;KX$4+dRG?^89WK14Cq2|yjlygbKrd)k?N^ZjFY;Ig; zJPgduvJ@jTX7cFCM}eN{D7t>ak&|kM4zEk4>j5?@p@y;3Gxf?TgEIA#$Bv#lHa9gh zVeFKtqbFpk%p_yXw9NR1IG)+x1>QsO>0>8P$xNC^twv0G^yEXwP8~hDJ`KiEPC27~ zLWB4;pbD-TbKg2-W>190Wq@&DT8ugmfb8$|q+1Lk4jOSV)2X6uWu;KR3N-5*zigkO ziA3)M{mfL8bx$5Wv%30NRC&EJWkGeWCb#gkQ**WI|2qB;<|!U!7gdiKJ`B_hiuPDk zUq6}wUtlU~@(c#-VjM$o^5Qe<7cZPLZ(+hu-{B}|+PDezQ*sk?)uTqiaW;F^Fx~7o z%=Rd=_~c>7F$;1#f(tEDq-oaNgunE$B%o!B<}IE>GJTsHlbC~wPc#(}R*afzVQcz! z!9`Uaa@Wtyfh5dVP-4SS-vt>|wr_Sc!k>Oipb}*@z+Zx7+&flM3;b)d5=U}pE^^B7 zx)ju8PWJ?!F_!TdQ4Q$iKr(>zNWKI>MC( zucK-6T;WevIrA4w1VAwa!(di!2TCAyh$#;T0#inZ<6L!St#rbL2KN zlBgXulAahL61cL|RY*OPWKJ%(VA1KQbA}DD$D(l@fpYs8N&-ZXMSmu@id0hj%>@kPyn zEsZaGff$T$eANsHHpoe~B5G>Y@P4JCsNqUKhr_J}7*Ruyb^}wjJj}`r4LG$F+bQ7G zFi--|)sAG#tg`}Y1R|LJ+|U$Te{D$7tzM4iQOn4X zqKW6Zng_4aYb;IC&W%Hgwp?!uuX-e#|C)eT!!>65Ygc%+!>Q!~5Quh7?Qq6^m8mJ% zl783;s1XQO`Y8}1$r!EkGzB};zNIPp_g@f{tl^xS{z+3KK{fuz6JG6b*qMIK5vpc5 zn`28?Q}q1`JD^hZ?>bG@P;z8QK{7Wgq!`Z)Aw^r>brNDr3cTDwWpKH4JrUY(r7d!j?76fX78$ zdbO*0^zPn}Vmn_PQjEjBww9znZpdT&?lm-z?VNOk8aawByBb8IYC(;jbJE`!3K$*& z|Fsk_G6dEuiA5?n_c>%Ps^;9|r-Oc8U6-Os*SNwPrg{a3xVz0b!oX|@kU9oF(-UlJ zV_5nba!jdL0=zE8r1DJR)GECU#TG^!p(WqCf-uedngJKbYngpw5eF5sn@ zX1VDuc_#%6z4W~v$pxe0OMU3u*j8{5EoBf}v9GJ(5hI6-JfMMwKqK_o!pZZRay7Lf zzr|Gix-iT?*$Nn5J3>~QITom84*p;%PPo*}9poq=C@bM+%8xJtL3L&Vpw_AsWJsUz z6dtZTat%ftP#S9(%Ta>Yg=Y7$D+Ez<`V+GPM)BMsl`!YI+$dMXL+^7Fw4|I`sbJC4 zuPl))ol$dR1P;}AGn=7~64wBA+6B{J;b^Gv~0bad&Ts=Sg?Y8fnsAa!%&OUp*w8YcES6ji-C<^&Av)m0&V zzH)&Xlu;4KApE@@0HP$wp-lf0xzcvX-0ex3QGzp`t{|}_riqzL1IcKh`Opx_R4V8q zaC3wcVAZLhrofEcky^Tr;h3W3>Ns}njzV-ll^PlJSA7!kWyl#8=wmBYkI=m?)6Z2! zs|8T;=E!usr(m|`L?@7lGP62zca$A)rA2~z8-KJ)U@n=eIsATGiNl@7U(6D5(WMG0 z3+#X!S)i6Qw`)A8H8Tuyh(mnD;Yv9--K@aXYH1g{5|3tvhuunUaAJiB?E_}4E@dox zT`*$AZK$r**^yrDl$2795shnI*ss^ph}~C}HPX4UW{FA~QbYVuqXMty`sKf+^06MH zS|9n8o9dJljhdr|++JNNQ2vv92#Uty5;RTv9jgQ`ua#rhJOd&u@sTFT z_Bi^W6%^Kt3VG;&aAsdis;b5$rk71$8yXv>vD}mZLxwbft1=nGy9{Qrj*#%LdzYe8 z|Bw}-0jTV{4=r%|z_QT^f90nh2)G0@m6)<;)s7BORd@_cMxm8O0CBm&^+Ouq{usKO z@K@CuA$#xoz)Ml}TN|97Qo&$o3nO%HqZgJLLJs9O4875cqf|C#@2JqKE8RGIh%$o~ zoIA?_Bk*^ywoci0fEN})`wUq@yMs0nLRA2Fl=MY*Bt3=($(lKANVL1iLyuC_!0@bd zqf+7}RRjku6@O(jw&8HVS&=S)ZsWU>u`9sa6O9%$tt-BVtSVKMNoTW^D> zS`n2?Y6h%T2RmUg6=Nx}>i3>5(M5VH^^C@Ke|6)f#kfGj^<=4rWt~h1UF8W*tdQ6m zuvWfcfF*|N9;BUEHOT@G3K>6owQ7h9AoN(Jo9Njv^lfmc2ZQ~p^DPkzGB}Ljs!QyM zp+Y#v0f17FR6Qa{VM)|8JTO^3nL{KQ|6oT2n2C(Z%F`@>y|kcs&O~{PxYn*)0R_&T z=V->>Xl$K&vF@{Sxu+$D#B+DU(2s4+kfQ9#G-PjP7ux4FuoJy$%ibzkZ#F`Ch^eYX zJV*+ZS^8v0C=-tYI$34Tu2S6*Z6KqVL~58BS0MUjEM$~dzUsu-?C>$Q?1199#!+IG zT3l}&R1zCkrMl~lxV|t4F{(1{7zjrH8aF1jcQiCB3EgM4tkacj&`q!V$cuBOikJc& zR>ptTK!{44NAm!4l*X-yV!p~SO60WJ{;C_zN(L*7xhcYE?1Bebm3YyNLL+)Qr8+n! z(+1TVOHDAt2CN8wi8nK?KoLV5j!UTGx_`tt!Dx(CH-J4chC8jGH$SaQ9gDOM_JM+4z#<7cMk(SlA8q7+p$%A8F}n3I|1k~ck_!J=Tg zrH;o>0zTKkG1tIT8Wia&R(*YL(Y#Z^ZYF))w29NEjKw|3T%ALQEALGNm#$t@mRQ%qHd(kDDOSR?^b>Z-=V{`jPDt{C zzybqgkI8asHj_lvUqfwNyhaVP=TAUGX0Dfk{lXdvO*F*r9CGk z8S%Hwkfg=G0R>g_X3ag5i8P8G=|Za%gVIcs5n`bBib>S*s(J1Yj^dAbpaKr@k z#?0|nz)!J!rx{XGe{MTl5J<~7m;N}AA;MwqJ2#Y&GU@e}M$+mw|Mo^i%l+!vHV|b) z8X7jZAwTfivVioP+%OoK!NA{dC<%^Zb8_<*&6>S%UXB-{azpKqA(}7nLLihx_Gg-{ zN}S!`Yru$jsb*d>z1yv1aJEc8)I|vlk+>9ZcTs|MFOD%7WJ}8h-cADz8^&O>4|7yy z-+Tucdi~+tw{xzg1VH3!M^WRsUI<_k=gr96PHqTEB=U9$U`)^4VQ6yfM9%y*?ALcW zF|aO0=uS6+V5}cX1jgQDEB=_#XbFTPw{=LPT7_)pX$d0G+4yECGe^;C8BT|>M}R}g zYEzfUEuamPK?VU~R(|G1WRPOd+X@i1=eD&JDSBD+HgN!>cWzrVCV{lbZ5;>Dc)6`1 z5ZYD^e{)-SF@%k|wHpI4mgjbeOR&h6W=uk@;?8yh1g)Jj>=>I_`>+=P)j3X#Q!F88 zj)GU|R{{#r5=B2Swki7uD!FhUaEq(5;(lJ&gjg(MtFzYI$GiYtiZMkL$$ zE;rz&&>&x$LcpXT)s8U&1fwN(#MuF*2LI_^K#gRE$f6Rvhj;uNmW7Ll$w0<6gf4tszF^dJw% zI>jcAp1=ueOJY^oanmL+<4!OXmCn?h4C-_%q~JO?38i0)1b|?Sx%Ppg2pu&gQ_r)6 z%;|1a3glulB(X6~?VVf{NiZgNKmaD7QZ>7!^fG}%@J@Ef!+ZeY-HZ_6R2T}wxXeN~ zvqS-QiH0UQIaFk%2KNxus^)By+5@7OUQ zRkHi_kw|t_PPVJ!P7k(;1ozL<9Zpy_E)Z>0eb(+$U__|l1-DCqa5zan<#j0#+~9`& z&vz{_Jgnkvt4j^xji>a-c9#O--QV=PT?+);Rbj*9Zr2)u+xlpS(V+@1e>Mz#&(I~J zwZ}pwqaRerG;m>*IW#JWNgR9qy|5sbA((xgkXEy^n$Gq&OF=akjw+K>6X^j)sic~5 z>)ldNP0eGhQc%s22braynqbEnrJ$NQ$CQC;3VhEBC4*IzpE)GL)CC7KDu`9shM^xg zVVU40eZ$c8kxY0_e6SVDsq^3i?T}Vy!t0C}9jvE5iLg4o{26D4a_W3|ofD&Vxd;o^ zR`A1v+yE|{2BTrP7#Rydy53Bz&S13_ql1w(V}_Vo1AOGh=s<=eYoZ|-R`M5 zk=^Zbl$LGhm7|>Vc5us3wc~iF3R#TMnOz`S;<4Jve1=tyLUePx4CF@7%(iAZN{6?# z%25WVS2?P-Hg9Z}%W`ra=$4~&ZA+&dWpFmK%TYGwQnMTdIKV0g8HGOOqH6WtuL5Pv zds>Ooh^bXmf4dyz?Dk)y9HqI53R$?8ez#nfPZp$$UYUmB4Em`6OInQ+<@ZK8NClr; z`!B7gaZSGOZP|)Uetr z(@@JUc$Zg>GM^r-KslDJg=mRywG8^bW;x2*Y1A>P{cR$52s94?Ezc@u+(0N-ck;7|7tGdm5J8yv9;Wh6~c84#MKorox8>^*MU&x zrc|Kp$GI65Ff%we$tc&sbk9u(TH;9!pSj4*uqt3yInk|v(bT!ajS3hM&5fym`JhYY zBCA3g!bemHtEb(vc7-sVOgrUpErUJ5tAOeIfo=s%-wyy<>N}rG$PIHUV0ts!tbplz zom~O5eSZVAR5v&5=k|5WVfE0>g+@8d8i!V*^nE|KTv#PqszREnn%mo~kY)o9bt+)$ z-pj6l>Eymv1x#=DGb>>FzL!@4)17^RmWG5E@^gE+TIsDSDG_Lb7~au>5g8eV38XH~!u z-oz+FtGQCmZ4R`=n`)jPIpryLiBjbat3Yg&@WLCiR z-S8@48n~rh0W*M`Ipr`<6mnZzQv!(ZiO_2x2iySvXI*rvZYRrr0?6> z6)+>UO{Fx`VXI1Mdb6EXp@bpXsuD)yWX?4!q#?YCTY=K`jl6PLJwMssu7DZsft4_Q z-_)#-rjtpp0%r1T2DCI%d<-o&(5!&z`^HuU%t-a}Dqy(N=sD#ucVagdjdGZafyQs` za+pip#{X2ne9|x1+bWmlL({o_Kug`>2}iD{Qvovr`??h{BG~v}y8>oRdRi4Q4gArl zfDx+3pY3vZ7^-ai#Vd#T3|ZrkP6dp>X7WJG+=1{n*UZTu(uHYKK0$Lgo zuHYI!tCVI-c3KtE^!+oZ0;buYx)m^;{Gb9>&uuQNfT`m%s3^0K@%zNAfa&CiRyoWS zT;n>o0;ccltO}S;ehRd-N}hT&uCJ74q&}^L+50|pDwNRo^_4L5a(M+z9q$_DI(QMS z@y$wMc#~OSmP@n3cPfSHUvev? z*)}gb6)+-|sjh_S&IqqUn!fK-0dobH*{4E@df0b}U9Lnu(OXjqGfVcXgb}LDu3m)_ z8dz;qz;vhLWT9F;1HQXiA&u6_oMBhMtkI}I>HCRRISjDD0obnrSF3~lPb-wvxGA~e zxN$p6y%R+}x_pug!DYN$j8X*;L=|4X#GRG71!(&8iwYV)wn4ouVoOb_U0Jg%NZ&d> zeB;uVZh~ntwn6rJWp*+G8vBLn)Y-&QM0!91*UP_j18#5~{9=oAX3>IE)h|8<~Wfppn>j@(>6Q}3u$4{!~184h*sJ5K#wv7w9$QeGu*!YrJf-(PIw@V-<@C#lE z#Ma)#EP)uh#+ORPnBx+yFo5i7uR0|qnGBnk7UbjIxmA!#)MqB;WYcTo%Qonk^(eNh zRSGfPj50B1&t6Wc9Ft@*v0gAt2kd^YLYflyUq%L5bS0aF1})b1`>oT7h#le-p-#GSn15;RBdTFMSk$c#+GRJ_|O z^PmB!3MJ4@GHb~v5p^#pO0TvmU?$j4l`s-2{h(PPjdaP4tdv$)47YPD#8oFd(F5K% zuAzEL?dT&>+Z&{{ZP*^i9J$nrVZm^~)Jy^nWdj^7-1wFg!=Zy-tanQ=bd&TmMhpsy zL(&5pYQ-IALS_lXS>_|B1Y#BMyCo32*e6yA#E!VmD1q3~Kd?(6xZL=bSpspxWuxbo zV$}AYRf@6F_W{Km;8>Db;RTo)S>AU_B~a)MyA)y^-*Zbb^o8`DPJp5I%$iaG@^7~T zJ_n*IBOp{0d;~(-MT7cl7A#Ibpb55il@*9_+)DrCYKjV%*_uMJ%a1eZbDvD)#vx6ZakQ;>hdpB&K3#vUJa1&hMnvJ*TlBo7)KZickltIwSY zxhh+OoK$jsB9c~a9FYvs#%3tY$n*ylGyz+rhZmB}_#gqUcDnA$;dm>1G&W5h%wq}9fVudEmyY;gE2!orOa6P-{_ZH)Nbh|xj0F91mt zXNDUij&MRuZKBNDA+5GWd>*F*JzsmFOt=~Ha0^&JMmkusrXK}>+K^OgdsJ>;N7L-= z%#i);IKm_u>c$b~$$nNGVXEwF#t|m}5Ic@A756PcI2ew#0vSmJwt4z7jln_=k+-{n z3}}uw*P9W|k@pTOqG4O+t{9)A?^-+JGmA%i0WFWKtTZAvv-l$`Vh4-pv=>6mOtt^# zP_qP6yN4P8so07)Dp~7ojj5eF<2_BP4y!UhZIoatohOxIDw_{8OXO5CuXi;T=JJG4 zOr`QzTT7@+ZV0(5kv|H#!S?D6LqBv9ffr#KA7*GsW%2uNLl-(Ic@ey3r;8vx_|7Hus*M>QV$RUBo_gzOycO zvjJesdhTSu#8N!nB3OOB<|<_Jq#4p-bGv~?aRMAu*z*UMLX7qpTT6wH*K8QN&W%95 zx$GWGW6;l%<6I4Jj~KT9ft332%n12jNUJU9=sX*SzHfwJm|bZ=i5@gmo<6~j5D&&K4A*67?nJrG;gvq8`1;eh%K z&bV$+Ctp45$4;7@Y2Yc_?+x&(>c>pRnK!&?{JW)O>!)#SI?Dkus2&7!b0G*N3JZSp zcsyp-q7&7ic)zJw)nRgA-#7=q-`WaC(^1_D5KsV$nY_#iDYPrIcxlMTK27xwz{@=) z6Vr>lQFpdaGZhEAVDv9831!U!Dq3QI%+}-ROmYU*qtVl=Z5&qBN4mgX;Q%x0>G(H_ zEjoBw@&j3cPPo$eON@_kzVQbm;xnfbW<IG_I7iTJ25{UgXgKh$M5aYGWd zXST6Il5yMuR3Hr9=^x#YguCgVy^v&>O_F`b@T!S=zGLDz^px}$kr1a=`S`82Vjdh;4KOF;C68kSDPTJMmIz` zz&=jvud>TI@HPU~=Yu=iBw3vb2A=q)&qI`CO~8rw$Nd9N zP8yu`$vx?9^w$MuF>|!92nmaEArH#LUDXQw2bKiL&5uy3>M?g6Jy5`Pfz;gW^&^^JO zrwp>m-3;WcS>UFNCP>C_&Ro_z%m~Q2^GVj)0Xcg9!R)9XVx6%*PSNFjTK1;A8v?i-&foxrQXl4jabSZ~WdB5)WBZ zvu6ldJD)~oPFLjM(Z=9023{61n6JCoWsI>4j&~seiaZc_fe04Hnd?xT+EXc>F{U3< z(c(?-+!nG;2Eo=*NNzO_!^bcDgDXdiGrn$ncNwLY(-x``r zuhI{Z3t_~EUj5qx302i8b(P{_P>P&SGS^@Qqzj8I3PsBF<3`*%rsYYIFg(TbUGXo?lM!gKjdE}mi zIx~aFV4cdMTyK&+p;h6d!0Fo9PEIGSk4F48jT^(@c>j9pY)8mjr& zWW6n2B5Gmf%NxK0Rq@6TEJ&}n!44Fvsz(}H9wJB+rKB?enI(hkrPd&6!X%>IM>|rO z66A}ORD(nHG8x>d_DW?+lQNLXHJDn8Rs^XVC{oIUR9$03Zex|(lE0BKEzj%?Hr)^M zyCmV`@rXJDOI<*%y;Uit^`MaM2TyVlQ8DeJVO zL2lmX#N~sw3LR9*MU6pg#C(^AW0ki#aeh3{R2u%<20QdX#;P@DtVj^@AY-6c1B}-O z2a@P);(yp6>DN8rJqHiQi?w#)d$iI&8UU&Q;N?<5-xE%zH${aL#Q;TeHBk}qn0kJ8 zwKPH&Iz#a~FUC1Gq!VqSejK+bDjA}P;TY!Rno)r_Ovu(;~I}~ws3`K%LK$>fj z4P2>>H-pZk$OEbqOVS@&C{o3+por3ve%y$lu;1v!?xGvf=NnKY(T8eO)Lb*Bg7Ff2 zq|VH6JK~OEeoE&IspYQzuwyW%}Tp423f2n#tS zjL=wB>d~;2u8jGli>|eG(O9wt%*^gA$_%K;ahTfqCkI^o`hNtg{wBxjpy~ugsBaMU z!$)}zHhIXe^LRW<2o4UhgM)+dnI6SDNF)2}gF`}=HTT6`rcrHFZ`FKxLf3Dras0M@ zY-@IMJiqNaPzT!NU6}RTF3-YT zOHr=hc2Nq~8cb4u0kx__9z^upE;al%2fmC=kawN!x3z+oQIZ!qr~$T&bIH3HwO`*N zS1|mxwsybm&+T%7(r+sme%rN#4T{%d!oLJ~4tWl0_>&3BCiPcn`BS@}$tvn9!*9Exh#Hh+OS|88Rf~KH2{Ft1 zZC69fWF>jE2g#&-l?0J6{kChec>jSxoi`Q{QH_s(3X-baBTdi?$(f2;oAlcrYKNqv?rZVe))et>A&*+_hvcnU zPzI@o4b%Y1nLY(H5GQD%W> zU3|cQ{I(}ezwKp|I>DfhH?n@)J0=R-F&$g)vtyIr_6%6hCZR)B_JrlPy#}*RbXe@I zq~G>l6BH}zaT`k7!86HwDFxHWOOSdUnqJJ}nwR3e0P3k0`E&`i6#cg6QSKzA<%CHZ~| z#zFG87I|LQZ~G)G_sIRWFIxPz^$v6<$omri-UnqHq&`SO+LiCp_-$Xge%p@;`IL>{ z_ARInYM^aGE_S-(|kexF) zvcPMX*EsoY|1teG-#~pf%YAI1&MYXGR3~cq3RJVDcrAY0cPU)jHA!t~LRn~OR@6Em zUpw*qayqVb+Jv}_o(61qTDF(+kP;BbjS-Y z5NBxl0X1AgEro#&`UZ4fVUXIm!!K;+`k5;gl`#FbUr_D}>MU&9;uoq6xisk)HcI-1 z{s~Zuw@s5@*by_j{@HPSOT8q5RL2YTteLugj z4UqmG9vf4R?;4kqiFRmdlF!rlg`@{RAn7Q{tqs5Jr>vj(vrWmqkle_Y&&9wN z$1iMA^fP}E$rkWH{ner5rUq;=<&$vG;QDPpC*{4HII>YoLcSe^qbAgj`fgNOdO_!A zsP7h2`QShrI@@hhTO|ELPw;M5lKoIaZ}50ViI|v(V2ivL43f5A=m+Xf#p{(qIaj`0 zg)-pvPRi~Qc!Y9&I{eH%O6PzqqSOS+rp{{c2B6$sCaHZqzp!0O?yLHRon5~$xG3*w z@e6xdeqmP&R|u8lZtZ?y7w}elEVnnP-3|GIieK2z_6tK=*r^2wB)MMn3)`ah zowM?KIKPnUfX)v20vyU1sNIo$Vt!$e2kY8p+ZW2YsG&tZWrLb+*xCfjRaPhb!k#Gi zphYTW`GxJ1;3>;$f&9kvGd$Jx3q}eQ*2=4GQbS?OULCkgtaw9RzffbyTjX%m0^gJJ zT|~dIn+eLsnY}8vC$%)m=ac-x9w@g*R(2Kng?+)>+mt;-pd8qOa;sg|SK9=th;pjF zZ9K#UHQbRPZ-);2vp`v-b~ItDBb$B@2_o&dD5@j}LCa2tywuJw9N;1v(Bi6choSa~ z;5}eaOM~qf#&^gEfBeEY(=SYbmU|U14J~z9`R18lIMnb9`zKJJ&2l3wAT6LAQfbdG z3`@yZ)BHlc;};HrmbFqt(k~p`A)o6*xemW@7_5HEVz~(>YH;PFPtbsJ6QT1_Rc@?> z`kLf5n$QWW$3f@gCd(ZR-e^x=f94m4+xVA6xdeHKqrSs!*#`jsihf}fbUy5mHwpiS z7a^&rk?nqAqzTF+?+_EwhtB71Qe!*dRRV8Gb5*$}zi^-T;TOynNG8ZT$i}~a}@V_HyyqGqq8wr?LFPkq#(N-i-@M54B`LdDM9%w9EkIIi!wC;-4*V(eYcCKuazq zFQD^V=evIEY)jr_>bD+W^jjOD^F7+qIGbIy6A? zB-c-`Hz;{xi{H8kHLSBp9SbU#l@E{ktw*K&){_lTE_uhagNJgTDC#H&S|GVzm9s$2 zO8V+Gnttm-&u=}YNj`!G4ba&L>I;ur7UJKr(D{W!>NwP3r66gNTIBexC$!6_+hDPc ze@Xe4p5HpJ$!|Rx)Yl10Hd#Ot^8G8|kZkI}{UW9F=puNYd}<6!L;zx8z6Z@s8pZh-o&D=feD3|Rf&1k0V<;`HtUu z0c%jyg{be$7Wv+m-}?KM-+ES7K4J%*MZfi8Lq4I0`aJlDvAnNMotHF0FL?b8QY)b4 z53YPA%x_(4`mLve>T8mBp69o&Y?rTwfdX=VN?FK` zP2W z>9?M3%cly=H226PTJ$osp6vbKD@5IhfB+U1jde(PU4{MG_&8D>-Rh8Dl|Pg(h< zqThNQsLL(HB|+X_P1sYE?@0QsSAh37TfRi;x87(#iz6SL1O?tTmVB5JHCV8-UA|0- zxHQ3|r0iuueJFQ%hrA!vZ*9r?t$#G-)0c=z0u~tZQB2_Ne(RrI`4}j?DWZ00d0$!G z;v!}V?7&ubUICq#rsVzT@CLjq!IKeemFKr!<;dI8VPgjy|OZ@s5UKFx?SO@8amu6)uFk}ZDg16BgRsziP8UOo`K@+Tm!;W>#OxNL9` zvhNTN9|5E?$N=&RSA6Ht}DrYzgd2Kf05j$s3rF|yU^Kp;LDplCX#=2 zwB!Ls7m|IB|Kd2V_E7s}o|ZJbs=c@M!E%cdyb7r$59+G+UW1ZVcL$QLmKfJ7MR`uU7VoQ;{&eoD+y3(0QK6naOQSj&@ zCzP~9o#}*bqpHMbb50h?i^Ir|^SY2s9J&37D@3xbUF$s53?&=znRjXTz9)?A@t{Z+ z3@w?CbVibWmOs~v^EKOuf0XYHi7s^Z?$e`c7fRrYZ)oROs|(3qr`|H~bdkKl=3mA$ zZFC{obMnC}OiJ*oF8@+;d{=h%n7ZSsn~UVtO3!RC+?F|h=`%9L8*}{`;9ud3R<6mMk zY#tG7Gx?X;Q3j8Q-B{#b);tY=f^qK1s1F^#Vd@x>d_dKrY;?PjOl-EtjCzs0%jI86 z9%Y7-(+%C`184ty{9z*bpra+HN3}UDJ?nG>O!*b=$c&vows*r$yr_L>@%Wp$_CNthLVkmE_C+ZX8W^) zzJ8CTby{W@lD)QSsrpoO-V{pC?8?rbJ6b30Es~EkX`M%RWoM5;`%D`tl53Npq|-(1 zRi};LVJnfmuSHAF^tzBtOm~c>B6)vUdt+p$74`L=MLf%nAMaxDZ!cuX%tWX&lI+vt z;KaWu0ZCOmC6DP!XYaFa-~T6({F}$WO498@XRnjDAH=f_=)5!3Y1v&!_MF(~=!-@2 z5&ls+7jz}rN5uY-;$J0a@`%_y9sEmdp35U8=kPDF+3JYc8au?) z5wRPUf0Ua~CVsqg!@tDl@BlyFzu{k1hdLtmf~T?LEFKYiw}pQxH`m}1u_u&$RXF6^ zq5EJkI@rXG6b}a{y1~H-j(Tj&=fh##McvcS&9eMl&Y8L4j9a0lr{8&FD!7%4awl2P zmT$&2>35*&1e4UtY;Z4!mF8EvyqAMR1h7|7fOmpWNI+E#!NpGQZ5v0vuI>dvhh{Fq z0Zg~335Rq^UcpTw`1OEDW}%hnEiU2h%{W+O;UDbJECI6#hG$N4;kXfcblQQ#CqO|j zzw_^Q;8AZx!KT&c*>cZmkw>c8lY34}3{t1yTK&^a+V?ZSdl6?qa~<-U5Q(P(Z?!Vs zz=FaAe#{}Ivh8u3YBi=5^JW&5YfOcfx3uzSgmS8qwikdkHBnAEzSymFe6a_A7uqq$ zPclQtXHA^_F$(wgJ1;QH9Y5WW+hpSSxhc6#rtHfvapg9dH2M-WGjFen(CyBr+&TOgVnKRoZ*cL|UnC+->h2 zb+dUTO850U&)1%_Ls-n&lhMepp&_OBo(AupO~Po1qxD*NPZNhQI_$mdj3=iAjP>3f zF6%#7dhcmLi9ieQj6xF&blZE+K(oN2a6mfsS6$lS-i@oFv7g_GOCYkRC3NXjOYXOd zOG~qHmzEWI_m#%PTzVM+J~aSiE**aJ!fE2t(yWxwF5w<-ep!)Nw=SLRmb$bQS^2+P zX=#sf`$A)Xzw@tNxl5C9Bzr86ClPhw!$O0@8_0F1e`-SQXf>~%WVJKrA@xucN{bhz_j6(yL1*>>790+c#B)&E-i<i$;Shp@=xmePd zR=}YD-AX4veToT<8~L4WM!8GNY}s}oiD#E2-gOQ)A)sWum1yBITfkT=ZTob?HsX?< z(oAvbDZ|fS=Md}GrDbJ_x7_(PmzK{yU{`3|*zdfyrQD?(;KXZ&Zl%kNcq{$c;!X-0 z6H7c=ctdD)*h*uYw!c7Jy3CLgx-b39@$-MSh;{4ISyAGhV`Jo6Ve)+eIOui|AG~d2 zFKFDv@BD`oxTNzae`OL**xIEV&@OMd*z#d=5WmQk4InDo`D;9G0O3zfSSMK!;f@ig z5HQwe*&mL-Ol|PV-{5Gb(%JT$MZFr6c6`zGp`BQ_POq>MdSl^P4t!k(Bh|rj16xZH zK$gP^b#Ru6m@pn^TRgyO^cpK%!t_cH{SftR>UUn22tu)uJTL`6in6C=nL+0-gm<50 zp}`^5VhME)3j6u1OrbcY`1!v;a=jzZdO@;7cxSrgU0?*|glbWgdae*Pcxq>idKA;o zud;pF8Dp~CHPFeOF}AAVx)gWDB=D<3U(5W~fJoc>DVi*xJY5C_SsJb}WxB#zER87# z6n2%VG35rg?Z6d{aX=S+Egd1|YU~0-V;oXM?t&JLo$V3(5^h|GBN{D_VZw47Os`AbdNStJ9~ zg-tT$tMtrY-yTo-zkv5a5MnG&CFP6o;Zl>f(XX&iAC;YRx7x6kzpzO&l}?rN*SBj- zQvSmZ1Y5~Oc{`dasjUv(JZZ!1jM`w9|C6Pe;?k#x%e7fz-MeIk?WjEYz5Q!04Lx$k?a;V6 zhAy<_pBx;cXRC(DpI4NfUgFZF?b43o(q%2&_XTM*Qs`3A#%j1IV65d%_<4u1(sGvu zCG=?gndRp%Yhi(IUHZLI>e9L9uemh%=*fMdaSOlG(W7zb(iJIb7jfyLY}}>G(WhR_ ziuIvOTn1c`5-{e{u6rDY0B~`7QBXp=#Ph<-Dc`+I=UR!ruqa$o{{b$YhaoicJNMUo z8+XEKlc0J_zw@SSd2>02Y`zoU{@f9tJg)}t+j8HqTQBbzG_|Co9XRr=w`B7CbBAV1 z27YY#`KwidZky|OUg+CO7cSAa1s;8~_}UyCbUTY~ZqE1!^=;*M{y|S2x*779H_7I~ z^Gu9<`9Gj{eV0S(6-C!uAVjc}G+xMurDpl55p^Kw0ULP)M~{MD7+ zk8-~ICp6<@a8=G}TWy{T(}dVL?K;HZudaZ|LXUF;Pv-v=w%!s$wQ#dLqGrfR6x2Vq zJNi2RG`q|Gm>R7a{7Y0-+s3ozR-2eQ%e}}6yX5%^*nNqKJ(oP_wrQ6Qtv0P{uP&e&5wA95ZjfG9S z^U`J5`uq$+bFrhD(zKtO7>kR7dx`GAL zEr!|@8!V6>NXSOwb4-@I8(O}DkFr2&N4a%g0>9V-snhadvVidg(j`faMGK^BnlyF} z4rD>&v}jBgNZ+($f^#(%Es*}04KZ+~?D_2)ixx3z% zv896r(!Y~*S7Wk3`VuMB?g|FM3(U$ZS{K+z`3sHM6|IZhu!rwG@~HkOy&W!sSkXW& zJ^Z$m>@b!dexE5jj8#|5-(+)#G3$->@bxJ_e_KjG-NXM~^z-+b8e3wh?%M1g_~r?Z z6V$(w9=>&Uv0Ug1xKR(s#%5GaSoQFWqfuOS>~My<$ojRezSDAZH>la(@BFiNJnZWK zaAm`^jN<=9X8zEkNAWcd=F?&@i{@`ia{DyxiFI}Cx6c2=6;OBeAJI<#Y}Z)W)%&bD zY$NrQLw=2;nX0REV>YxC>$a=6n3bdWl@=PCqxj`c*v6YbJaR4c?11YHx-07|ta%qZ z`Zj~Ov~imyD`GSg^6!=w*&B|L7u16Y$}b&ygul6iyTKFqMeWb+<4`D|Zhx+l+boSK z#mcu^S~RBA7ZN6`(3naxZaL52+(AsW_EmN`XI}yD)SRu>BUdM|Nu9_E4yrZPnO^D5 zhhyK|ttZs%h&j6@NOL{u=I?f8E4#FIYf-kcpKa3VTe0bJt9IS?1vB3EfA_etoxdtv z5tg+m_r*h@fI-_AwrRq&RMePK%sui@uCXv5`X|pmNAjUyYNq7F#+IM|yGN|se7MxB z%!kX(ARn&x!hG2J&Ewd;cJezfvZG*}Xw%^W_H=Fnhb13wbYy?NYPS5HrtHs`eE55l z?9Z3+;4TEJM-$D9<-C&g@a>+Y##AMIcp<;mA*S-* zal`yCU9(ON_n$Os}*XdA>CdcwjP8oaX#p_K)S-b|xizN6tDHiF>XybDArebKO2cNn6%oKP3 zf}s8pU19{xt@b|sJk8)=GSR$Ja%S@Mr^=bq&Of=xYmYqD&NqjXINl%x2XBEE9^jqF ze(nmp^g>qS_NO(W;4XgWC8?-oZ#3AMU0WVvX?IB7+9VILNUGlopZT2Ptu}f0T70Ah zdSEN2K~fo` zHd}G#c&ORc@4U*598{eqe+QEFO=ytReV{3xx_>j`sr&Z?pVFZ{QR?zRJ*W^cp1Kc& z4u+|_=RynmxF-Lbp$karZVpfXP6(cMb7%RMXqi&lac@Gr{`bk|5o-?MMS|UM2G(Bg z{exL~dN5d~nDH}`+mYZ=$GyLWPbJaDnD@LV_+S8P?|DY@Pg4ZdtcTRaef1;8)ci}l zzrCoL;{6s-a(@f4ZoU6!bYeQgH81?g>$JS!$GeFvQWE~P`T zx+UJy_Z0aY8BL2?nva_0Z*v6HEzKeN4ohQUp6|8$zzGtF)j{Zja29%{5V;}?bnEmQ zH$351m-X&OORIx!Te|j(0bfJo9$1AJ1E-M~Cs}O2``YCpIBDs-n&NKW+rdZTXiRij zk5A2^kbtqa-S+nR4~t88HEE`_V_&r6y-G{BF0D30m(&&K)z+_FaXxhU5*O9%iOYJ) z@^<`3R-WAxmsVp$=|G5Nsrf2e^>t*4B=18QkOxptyd4K*abl4bFy`R60rRhwi+rmM z&6HKhftZsAIFfLy>7A~v?Us(S=ln?ehZ_$I3o<8%B zBW3%0!73>K9MW8;)mP$m?E@_<0slEpcaUaI|2qO z)#B*6qQ;cs!ag3AYfP!oom!0@o^IIuA-xoUmL{j#Fh^tQiT_#^5TwYj$^jdPyrm{fm6&An>$7T={%w7t5(N@DSg>jQM!ZHh(U zb9nn?hk!Z)djosQ)Rv*1^X0&1VO&HDK#LTrflb>_gg7dLOiJwtU?B zmn+wPWd3=+L!SDTQS4zeJ}|!u-gXYnh~^(YoSy%eD_}7H6jB|2{`n4#h4asDU({F0 zVEwSEnTv3so-WS6stR;FZml&-Zw^0*RQ~_m9L~IW@&~AMsNeaF6@((Z_W6=4k2Nnd zU{wBXTdrEF3yArrTY_ttG&uhn0)uOq>eZWm{`D4l0QyXayk`=^JJVHEQ&3J(&!!X= zT>E^)P>)In*FOK1l}Dw|F|%e{XDXa)j0RW+!eo}mA=cB6$@Vb8BSt{9=Pv+ zpge`1T?||eC$Z4iq-1mg%FdVZG#FQrI_kZGKuYpGkBR1tjvmIEA2g877{R))MwA#^zxty zJ( zvQJYmqUATVVC{pxq{g!RC&-T-EL4p!YjX?xqS0UU1dI>fZxB++5e?ptWi=KJ-Vb$X zOa||L9Urb}EE>GuPKFq`GVs4^YAhPOJ3~1cylb2Md@-fvWbo#I{vEW$2k&h>AMR>Q z2Jam@d^jx_68etHQ;zf2fa1t&?&=pZ1#6dsu=6**f&%x~%Tg zUxL~{q5Jf|Q+y8#sz$`MxrM`!5$mB=vP2C;YO(a5p|Pk>d!ELkKD{B7lRn*G`}vPe zEf@9aPntr^g%hfduRM)KeR`dtG3nFeOh4~MWl;hzTS4ouQ;tLnvO^6&|7D0tpB`cP z`G2RVPqqHNm8Y2L`y9+x_d3xjX8Hjj!6QNqKlB@f!o&SeT*eA7fl24~+vA=410?gX zl)j$u9>Tu6p%eXm7xR}*D`JVxuI{%BsJnXF^Yb4#8e3w})xF#O{Cmo+k{-VMMv02< zuQFb3e0|@g67kuq?BT8%^zes_(A8xpnD3&@2=s70OW|stxcVXHkdNB+Lgdp_@J>1d z_T_z3w!BN9{>0f@K3ry2YkdD)P}kk~{_dHGnS zmv|X&(4Y?|!Uo-F;h{UB%qYL}pL&Q2hinhg{uYCTc=7Z3{Cj?_Yr}ooAi*q z9@KlFq=H6}y$Tkvgth{=#Wq64dzBIT67 zPrBiq8g)zk52l<&r60wCLb|<}d#p8aGSuwvcmB(cW-V27{$q6CI#-`Ze2VVN^N6!e zhTz|zCbsCaiqEb1^79K5BWe?^i``_OU}DT`7chQS@u{ORrMNK6p>mCdXBrzFe9U}V zrhaZ|<{}*6%~F=1|H35J?K1Uox9e+#>4%MIP{ZdC!o)c0s^R~H!UO!ycB_0)>$KII zvx3C<3Kop^bYgsv;x00s3ZEtY!tf+5i#h{eyp`{?1q`yQa4=l>ijYc=B?jE$>j(26 zq%?*Gkq*-D=s8aj)W4_?47dIKXR0=p6Hj!}2OhQbpyr0IuDEdEgHU#$-}zW7N&p$u zzOm#Yne>4#4OyHi`|@8PISfblfzLbS;+ph<&k&+5Et(i}oR`kN2|(>Q7j9n~A{fL_ zE%3f**BBf}FpB5{pLb|X`T#d2d}b3<{ytpU#_1>EZ~Bo~8{hL11h`D+=%>9;_YBUu+zBn!aP3XcB zL$z@`*439e`D<~~LB z9=gEiWQ%$aUC_=yw#0mHP8xhG9nFZf^Q0ypDg@L%k23t`WQ)d@7`iY27-FH%dl=Kv zg3&MXdAtQBC>pf$vvxN=Ki^F|C%510_b8018)w0#?cChkQE$`>#;+gR)f@H1=jPt2 zn9uqDSbV=8t%&)&zvn}RfZFE+Q)v5kjfFl#oyJ0+XB=<#C#Zjs&!*v{M&hcSpZB`) z`8lKOcAhYJ_}3^r8tq)+a}~Ti2y>U}ip@RHmIoDs+-~ks(#~5TI-{FtMa<`eY`?iG z^iTTp=!6eNA{eORm<@Fr3w@sQ=e`FJ)W68*FenKDFv^}_-(%j2cCt`AeIRBG} zChrJNy_z=%uXhr5BlOx_bqe$~Dj^uZobpbG##T7&Vjd#dH^h_!3fnkPh=^H`<9k`* ziY}|1QF4i}ta3@!`%6*FMW8dxK;7?;?!fq$)YuXOE~q{*AdExU2X=q3 zdNu|1kCBjh{0Ik%UE-<_yk>+q!PHgK*Suf5O1gOd{QXh70p}_mfzzD%EC%=&#^?q|`B8Fz{ z@+B4Nm+Z>(%Qu4A8Q&laS0vNk-0U~dGuH3CxhZf&pN=$dY0IT;8NvEmu@y=4X2_f& zErH9;1JTZt5HuCt<~}Gl)1-N^w!}qkC=^h)CDtd+eJzbGF_@0~Assg(q!L#}l&?fZ z6&jN!%%b!4v583&niWGgJ|Ban*sExCJw@X)XQAUq+`iWjC_E0!?PAn|vIhOxiJgZv z_iK-zZTm44mV+7K&;N&Phi+yon>^+23vPwG8SX?#zivkE#?LNx{9*1HD10bRJIhyL&HYUE9@(ImCM@+H*`Sy9 zH{!kY=M>*6ODiJh`5IcN5Ky;l*7chcmd4;bvX(Pde;kQhq0eJdC*DX<|016oT|_lS zT>1P)bT5NjY|<|y;nZH66C6})cCni~bMMjzP&$p}wh;|YDyN#O;Pezr_tKsijGo10 zeYOcpn>X{+3v#8mHTQ4f3v&5WPD@J8Y{&ErVR0txv*Y@ml#@Q&vq>|RPQG*(dNsBP z2YB&s3K3D^?6x1j5)Dnt=~wJub9%q+C(nTPjNiGorQGQOsC1g4o!%%IngXYr}as<@5&QWaRqQ;gOY*~(W16_@&=(T+g$9sAjlTqwQ$45oP zREodT#i&ik)ph@vzXP|ocm?HfzjJlPsJ#bL`A07>u6fUFY^Qp&0e?5L^{Bl=Ql9CM zQG2I$KF}cM=_#O)gdck}38?+u+VG)PV@nMB+ZVnWuEr!=Htz77cSveX{N1L>Z{De$ znDY0{=w`IKWE5URdf)i9i%7}rIh#Vwc)xQ^N7Ur1=H^XJ^=fL_?%TX2+zc-wHSbW2 zT|{c$u_Hb^?`ZKQ)?#t^q{eiFU{h1T*hM6$)tKZuE+Rp>#=_1q;i`?0R?lR8)TNoy z5spj&vxs%u5#Fxs2r|sSi}>hStz?*g`N%_{Z~|806(=NHBPvIs@nt&S7Oj>`=@XJ& zFcgFrk(vkLWva84WwF#hD(N?GZ9=)~{7Omdl6JpYEh`na#6T*jVSbmCmP3PZIB0hF z*mn3S1obZ*=3D2xK58Vca^hXPqVtQ-Z$VF2J}(%w(-M(>& z8vUR9UfrtK)$|O%e}A7ced;ae+T(kyVSCD5P(0}JHq6T%r8T18rbp2zO=ak-ov zhIHZ28R0Re62Ndcdw@ll6#l+fy-fX>6W$g#)H~qIgHA)8G)B7_jdtbZp{9KJd!V;3 z9vR$_X1&8P_C7OMZ=aO9B&rf#Pel3Y22s)UuF45#sHs5Ky9`)ggE6U>E`B=0ea58T zmcFn{pU^I{6MFi*(=$iqq~4FsYQ0dad*50TMl`e3i5~0Q10R9ZMcRH(7%yf3vx%ggh{y{ z7}X*DfyE&mshs=eP)gGautxLZD*IQc9A@Y$_xA+e!$94|RQ9(OsH+@iFxF^D%9wcW zTJRWw{Haj6@%|Hc;{)_>r1DfBs~nFosd96oN@d;FenWfUur4c6=V(!W9Lefx7k_gA zI{h;89TGwOj!5g1Q9ob4TSG0ho#6@kl_Z}}4@Yc&TSQBm1@foo5OjfA0t?8gX+&BT z45GP(R+#;K##Ew8V2}1&{w6hR*KNsVA z_eFfJNd@Gbl&vS`0Yx?SNJ7p)Q>AH{L!AC{iKghW@$!_I_jMH*G)XV|K(mZB8npbN zNoPQjG1LE^?u=2ZUKGnx3>i}BzOGxsC^7P?MLw(=qac(39JGW z!r3pUHiXuoI0ho@u*|@pFn+iNMCS$r3ksB{X9z^x>)7X^ohHl2VxbK_C|k*&DqA9~ z=HjtrRp+5HTsW%)ZDAfNMI&_M>67k6gNsD@iA>y=`4o z(5^>12U_Z6QVAaq6D>&+r$~4Uoj#^Y3JjX0i*(L}P-LS4i_-N-XDa?uB9-uAzCag@ z$xiYoW`r|dVoErY4Tk6x{c$byREJr(I2sDC)1K;ZYW>15(BcwNev)U~aON2bse2b# zcnXV$r6zl|r-8TA5EWe?m%g+9ZE13~U-};VS?@zp`B+hYiYHqBrLQv@fl4bU<-KV>y^M!? zio8d6N}!kmrCo@b<861q>Ng1F520|QIyie5iw11?Ar$^p2bawp@O5|ue-Nr1yTlgG zG@p)1rDeZr_L=pS8)RdFKY~EE3iYp`&Qb_;Ko1c7{DU^AY5=0nHS9G8=UEX`;Z7?XPGb(hXWgD|Q0 zYp+`GHwa|8O#a3S^&VwS{~zis!|$tjwhdQ{qoIjTaMj9bN=d#!i5!y<&Ww_}8mF9n zkViWvXh&B_r?#U*<|>+xgPJKNRge`omdZgM;Zo|CTbXFT zN(55B_Cu+=KefXU)TtNcx2?Eq$N0L`i8)>B+@z8!ZSRaS)pn2)eh6~Z8N?(me2lL^ zb}b2?7#c&`kluFY%uRAR*?bFa4UIAxQ=z=V63!tOVN$O!dC=l_z1xZFA1{epmiySe z{h3|)gZ1N^tR_@y5arD*m>L09jMcJ0JjNeYLeI0(545YecDI)>lSo{w_}p-v^b!Ri=xQO#T>OIAc?aD4YLy#Nwn3V~qwB$kab3#H9J@bzja* zi_6JQ=s_dSG=hR~tInCTT1j{-l0i5(wkAU1gU?%+N9E&08TaDE7PRBBh@-P>HN-|0 zME=warw#F)5rLJL!yd8B@Yn z6oq4&jH$Szspp_HVKVOiXH};Z5-wAUruT?>@LRTGR~GS zPzx6D6QH-zWWAH%uajLxj~BG`20~{HVHC;Ag!B$SXJ%*vsh8f&=8UtsoYK1}jWvVG zn9@sQbP_>d|9pm>n<5@A+}P<5F)G0~ElyDjpQ*6Sd@bB$vM{jLQ zY2cePa1xt1QItP7?&F3#J0`s_>)GH^I8A-yV-k;oRz26%_VE<%? zfj$1m0i#goBvCH&VlVXXEUan1_u0QQY(20K!xZ^}#d;4b=z%>O>emO9xiJ~ovkc-F z4P*-J88%~5uMF(NOva+XKCHl)^6xKF!kO(6CiVVc^Mn~agHf(>{|6UwVApA@+#N4n zF#(lN7Uh?VfuqA!?yQ{l!*ZuCL5~ukPvk!O!MHOkr$A{TQssD=EuD9eMT7ql3SH{p zQCIeUKYkDb)xmQUy`P95luGGAx8Oh@Qd+lzSFLnM^6XBgrgSGibg_BIpaW6)6u7u5 zS5M2(?k>A{HiGz4e3PDV=3qd7W3!9rAo$PlIi%;>^tws3s@X*D;!evbkVE?H65Nz# zOg1bxALgVOQ$u(i>^a9}Ou6{74AxFIVM_Q`T)e#p;hjM;ba6)@!8(7&ZGC2-@(NM@ zsA??N`)aCHxof_wGMVJ(V2PezIUG_N2 zR_}9_{G6i;+Iv$Rtc0Rx%sLA!dJvG}8RqPv2Hfl^kcBtd5NI6aFN zT`(qv)8m5B5n)nzr>(^G_CAE~U}|x_y%`Gco7?kxR9-F0?`Pt|kHaMUCj6*8z7T$d zpMy-c0Bg`?8TR;6m?1iGKhmQIJrSp9KubZ#B^AiRDM}aS7?Z;3&Ckw)B4bK8?SCvS zFeZgJZ_XeJJi?^#WTN73(z>1D=>MM|=XP3m#wN76MwDMF1oq(DGo1s9>gB!b42pSN zV3SWz*x=H)g+_2!C@Kr*n2h?i-jd&ZwV`#cEQzxbS?^qrjy1qmAE$9^jr_LMl;70d zqz+E)TK0GOZqg;FCvx)6O4PGbLcTiKmOZ2~{w^vd@QLmw&2NH*4hStNNz1!G7pGLg z;Ee$iTWB!05r3#VOpnPhCS|nrC1E~eQjDy7iXCDe*KNRGDj!K;CE@92Bz?RsAbxZ_O^Jk_>E@M(Ky(`&C`wBzBowqXH>8`Z8T}>_QwciHpGV_QF zQTsGe{-+nXIo!WlW~etWtFT|}sy8n;8sO&~4F}N#E@RM{XVPzmh(#3W`SqS~mZ7kc zFB{2kEFfN7#$;1+%0Aj;41ul|Ee#JXrk$nm6Xx`m!%cx6>41#*owt(Hw{~8cD9j#$ zIvCw=RZZE)ViebTJi<@%^xI^YVZ5JX@d!UAAzwTm2*<_(7V1PL65cX7g*m6Fz@W*N zB}L(!8>`irQWX5U3l_=F}uJGZ9gn~-MZ1c zqQyp0{@9M3EIV{8xb-YIxUI%H+0`BxVuE4-`*b>_3u3f)W_u(v$jDwm8q!K1AgBn4wZ}o24x-Lf5L?-Vpt?L4>@d8c1 zyL7(;HuOV-r;G9zR-hTfK&?~ik(Hu+emp`s%GoC%=+90Pm&l_sXV+&G7PLuANB$&pDD_(r{ls;z<|8~c2arka7$e`frk*Q*r3awm*T;k&L}fT zPR_|G%6G&m5-t~Ld{$r$MjV@fz>#gkKnNk{j#YQ%N- zL?m2~>xB!_KcMniqWmGx%VAs}j`14BbsBz**59WgQ#nP&g+oNf_2B`?;%NPyrgAbm z8x8pn9#`h|r+&jvMO^QAUC$rGBlshV>x&TArzPo_l)Jm1*ba23AS}E2mAlR9O_SH6 z*x91|St3eOdwArv`S6TwppHS`nr!+lbueo?SV3#U_f#LxPAH)raKJ<+tLHCBQxggd z8fiHcGMjA1Qu9rF^CKRYAUp~vwu48Z9v`6q$ zhEqyhVGaHe`JbUL>X8K2NWMM2O3{1R?TH?7^O1X@#kHbb#C&_Ti@*6wyMtv+-htUR znIsc)k0u(IDzq5~E{AzgR~LOA9Cv0~fx76kT*kr~=lGo(gBfRq#Rmh?u$*lWR#S90 zP*$ND?fS?E^ivAfuHf#sOMgma=Zf+xRTB+toBx^5nFxR7&xh$`U^#0Gw5vxHv}^;= z`59pVc|dM7f%%Lz8uAb>dcHF86$1G~6%bYQkK^s~=E8UR0R2m->^6TP%(u2cn2hJ{ zes%tl*ZF#xTK>^4`0ey{vK5urVHKr?vzk}IRQ_IGC0^|P$R#2e!_P?g+Av*Fq?1Qt z5s8;~vu!jL7>JjP!_y7MWK(jOt_{nDnol?Oucw0ii8MFa!dX!yTx#CeuGTCs`0eFs zn!onL$tLs6ln+sPJzQLhPd2M^x@H^SXj!Z@=V3ODS^alDV;-Z(zt%wuSO?>x*l zMtmHv#yCDdOkP;HYU3DVL>tGLa53VEhL*gtrf^oL6{wHnQwfp*8;;{+jgzlYE63Fy zA6$b!FqON)IZukNIgaFsD^`p~Wze6|Yi?W}Jt3M+n@)uj2 z#hQ{hBTjSbJ~g8rJtsLj=VRq{P~ey_bt6z5zNao|B!4poe^ZhLhU#av9`mw%0G)Gc zh7Zb?TW0wJtrJ#LeZT1b{z~-*xVL@QQ1|fS$I$c!Yz297^=shK-@2@R9X#<%gVmpA z>%Pwv>4`7IQS<$c7!GR!ldyW)kzGgSDt&)er!Ma*-=AjlL8blxm`mLuQd50zuW~b_ zx4*T`kiG_@VZGVLPit52y><*b--yi+9tPoN$i{-&?Unlq&N^RhW5@-CgOE_08mKIs zpJPza7Khpl$yn;!xh@?$9f^aEo$JX|;Rf~Ow=-3}U^8TWTI6pl@@5DIpmSD=H$%=T z!Y%lwHbZEC{A@dckG2`Iq9~k=1qEt9tp#z$)LO_-gK(O$jrc=thWy-POv;cO8X1c* zDMn(a=R(Zmy1#H4i#9{}Oanhy@=-3I&j^Pv@W^)%stIk#rw7Y<5dmMKM&NSwbK?9J zws6iVG6vK?T&<$EcAD_Ho-A4HFi19fsy?QT`wo9}U0y z8Vw6f;cT!7t2r8mST)oSwA)j^Hoq_3ApJ93?$Boa)#wl2@^tmMY?;3^!|KmY>gvx$ zkiVHCjxqJ?Jq2esF9lL2YNNs4}yW)&V(m5 zO?nnh|6G(msmg?yfm$Zy*!OE(k-wtE>KhCCJb(!=&*`1#0eSD?c`gwrKg%U?-c2Gq zhFIwP38Q9QqUM3d0#}f}m%D0NldziV2iNlb0JA;y^*tsmLesy%P71Gn!nOPbNKId) zSpBuOuKrh+u0H39{Oyusb8tBZ&qHV5V{H(JMu8vO#S{T;bg<$4%P2|*NpK>{VxsG zN-*y8m%GAI`~5Z5@9Wl3-`{9Y{mSh5=c2!?D3_4;E6-xDgx-E>_C2;av~hna@*K_- zf}DS$OTYM1yu)$d3+k^7l}6+Kq9h9p)sOzJ&u^4^-kf6f%ZtLf(4`7B)%Uk5m;C+x z_C#;Iqu)%l_)BalR=FHI(fP~Jf(m%tDxxjCa@e~O1M=m zoNm#n8wtvxaP1bIeZL<1Ix1g?{bN569^RsJc}m|n#cbSij7L31e#~Q@cP>vUP|Bfz zcDzYf_FhgPe+Y#xb#U>LxgGcb{YxkWs)N?tJ>H5RR4zU`Cmc6P$E4CBZsmX;=C?PX z)3er`jM^8$$8J1};iRki3zrA9gVkyOBIoc;zCNI@vuNlOjc7pAo41_HG797wj0QBH z?8~Mg5LbVWD6U6ee@$b03tHhUMp@xHiyEmppt16f|Exkib9kg3xp$WK@Zm!;lWa72 zF)nMS0?i19RltOE6~gT80>?E@m*n+(6}uPN^h^rWR4Qc!8IxBLCVeG`gS9s>DO z5z=Q*AMyhqpnoH|3*qsrGK5LFBV%*aP&l>i1$m~pQyBmuN&Goxjb(aI+Pthx8Rm#=<$O^Xqei?d9u=d~gl^z>94WX6j-~ z&5%xc)jl3;BS=Sqd+6h_ZkVcf?NPTI8ovyhbAe{guFe&<_8eO0>NH)#7G8p5;$`>m@AYH51%3)4O#kUteMePChaEIvU0hB2K#39Vh@5++qnu&doW z%7S~x!4;u!v@u||Vpn8JWhS%T=1(;iO(fxYF$wHtC&R|z+&-Mh7C z4WBWwi$I+#@N1e<+`Yd+${LvC4Bb>x&!AK8eHfbf6oEswrI&{_VVXFQLzH`WG_jjn zVhoz-kmEHj-}pU&{Hbv7np1YWpAXQ#k$W*2IuA!G$8IG<%Nu16bT#*CH_D!wOVD=I zuSEGBJMP~5APHkOSZHA*2`9?z-iIu;-c;_rCn@qctqvl+P@spbD4uMJ{4F`*+$V{K zrpVJ7a^6=3gNEg*^C62dHF^;*&OJ%Sq`g}fLU^G-m~`(ruiCwGp|#q>izodsTaC0% z+y`~8#E&?Vf!=U^b%&w7pVhh3N30c9r>sIg&E^h6fzmL_dAnXU?XLv#htNj$?3l4V z=q{J=LkFQt)tvvp;LYI?{6VM`*j%y&IM6XA(5ezR>yI`DE(Gci{vYz(316YkuSMxc z7Rc6sS+WcV-w1C*RXHr_WaF z$-B~ga1H*z=C~!CM`VRslW+a&c7^ErSKRhQ54d9KCbWLFC@0c!(Z4T<{H-vX68%t7 z7kv}PZ?ye;pEQr63kR!Fhw~-p_XXA<8)ZO%@+iqRDdi8HCjo z{bHr3>t9N=CwkqOGn&xiHKN?J6c>G$hgk?_Q=)H1DvFj_%@v-07@}{riJInVc9eA!1ou^}J?BidNC(GSt z5msAt+|%$=+Y9Q3HKS=(yiSypRiYnEV(+rRqVM;0(RX7Z7KwfgCDoanCK@Bac`y_h zh4=kFX`nnDithX!9^@;}5${g%LFH*=M&~ivNKMhNxs{&A-5BkN-fQRji_y*XqKrmk z+k5xJ(l~br!uzI*G5rW;EKRgc=23LRF@0l3IBF$90wd8k6 zw7f0<(X;|}(f4N<3q^NWa{Plz^z9}eRHDgp1&P%Z{fb@b=~rRmw!?ew>APNlZf+Fi z-BWQ-KkBL5GNhB7mXt2qE$O0v4--6{QgqqV^0tddJq7BbTY`dGc=wvsb(9kAmbiix zEiLzZldzhi|CtCy(_<*>|LNiaD6LCY;*T|^yq6CDy9ZFPw>Mn57(^j5SFUUa0G@ zB;76PQ`S&fJ*z!Q>30qp3Q0GK^3IvKq&pEBxOxysy2sWf-CLwz z&!ML7r7H_qz!O$EnT)(=r=CjEJvJXylGbH}b8nHbnv&kNDkZ%O8@C;J!_GYO2();! zD0j)lCEbHG^1jWIeuwcDO&Aggyq<7ktbn;1yrlZAMkTt8u(gP{{emB9AZY%1NUW33_BpFT8=aBS3iWpW* z`4eB-=VK-5HtCTt@Z^siU-PI!O-XO~m6F~Bp|-u${k56n(PCbddne;wdNzZNJD(-J zp425hVbTxKiHs)cKZv7eGYZtaG~w)_k10v7C;6cA68+}<36rqelI%)JZ@cYD+Hb*% zpU`5nDDRPuOM0?|_s^pRmGPd*>5`r*(xW4Yj3()uq;Q@rDNvKtkURBQCFz+QA5@ac zmT;ab5>`{vyI!TFx6Jk=bt?_-j22rU$&X8V+N582v7~2xUD9)D`hA%q7-qb63E@0# zDo~TO*P!j5Rg#|d`Jj{}f8O<6ny{LZP-6#7D|8#XOyY00>!mfPPQ4s0-YUumBavV2 z;_q-?db*%~!lu0BRY>}yK|i%aY0XRdGt-b1=+q?5ePO_%N|NWR8l1#&oznTEL0D}` zW~C&*T}dYtJNH71w~6wB#kizru;;O#&t7`U(!KO-f_C?aOcZ!6qv54z3T1`vPe9!5M+_(m&F=q`&9r z$2CMola#{Hc!4m0nxt;e^g2^X`iBg%Fyql1pq;-M5W!4rWIg1~DT;R@%k zvO-NsA6u1P`k-AeO&f9458!a8C=W`+CE;>k%gE46FD7+Ke=E=rq7?g3QcoEDpD6`u zlFs`1nwiQ=FDCh*3cL|1;rva?tSRZexR>Dnw&$hoPa3%%-P|S0`xoMp{*uD}Nhs+r zt}f{x9{tow5oAgEYfHlUOSPoKigW9fq`$bT2B(J&aO*#0D>Wr;HY&ZerQN_={{G=) zrMnS$rMRT$KpX44U@Sdf;iczGBF~rBLrFPLIL}Fj6=SLKl-a==@A*nE<$rAm=lK%J ztSRYzyHe8oUVC0T{=2NpGV? zc<7LHT+#~}^(;vx>G2|H!Ryk#&YwKdk|Zv=q&Z0>@r(jBN%Q8f#OmR-0@7iqSGLmp zBfRt{k1EuZ^r2NLX>+@QH@|-UDQNLNQQoI26IKGl#=pSd$55|SWQVE$Gr5h+1^+>?c%e3g%l?baT>C>2`lF^=|GjHCRrrHOP@v6M^$DF!$rN+|pwl3)<3n%euBBP~; zeu$$#<`k%TY3MyCJ4({?HXl@8!ot{j$s(+#B%Hxiti(U@+LJV;W!Uy;@j+1@UzPD* zG1R3xCF!M#^zdpzs+9Dp z+n%J^S4{giT6{>95Ax!H_jgE|5Y9_4mUJ(@iu9m1LNrO!!SL?}F{}u@^#k{NQ%QQU z#0Qlm>>fI=`h?Z?k{?RCllJjGN7T|EwfFI6CeAtyE&g7VC-Ye1q2au2swc85FTIvl zo0oTig1}R<^v%l;J$h>^QH!>z>AkCHLV=pk_FI|$huXY+EzJjIn{xA#J4p!O{)I@Liyl#aO{e{T~qaE9ShlY?Xw~Q|cv`*z}ivGf@6#c2+ zp6HXi?nm3ykBD-=VqA1Np&s|BL~p4OUG{a+o0IfTPok!Yo?r;4OjuR=p!=1*_JU#k}^mR&fs}w_nI}-gxfh#D{6Ma}NLs(7Gr6|1R znEnEuZhK7E^=a50E&f52;h5O>zk_d4c)w|)WFR3FJr$Pv$VKCo zp6>PNoM}q*XW_wUOurLiO7y|DaNac0Ms3j|=4oNH=jr;~j<=x2$3%H}IxZTw#?ufPZ#ZD^iT7Mnik$mio$s}bS5kZpW;s2wM&l2uVv{f%=;<2S6T>iD%y6BRjd;0Yfy(5aKMWXYK1>t;37`d3vnw6*L8G96iF>Uj~ zNOZ|yOo?8Mh`TqcJU~tpBzvdbbn$H=>(Ait;dCdW2KfCx&`*r}FgskQsUU zV-SzV^t)IA*ZYcYIHq?+czmLjaCAHTJ$Zepwd)+COesQ=arFA;Zm;!tYmPuP`CMj^Y(rj^ut z1$CF+8lS$Ea_W?<(V%Z1Ae;x6__now8T9mRw4*{+R+o41y;o2ma*dB_Ep(bz$}uLJ zlDDXRK#&aW)t3Cn@dm#+_F9Ps|D(89_pcq}3+G=3!F2yx{WsP3QP+P(Zv4uQ?!>JB z21syOe94vpJEHQRMR{Z{uK8b3N$1i^^M8`cm6E9QhNaHnBn#&QIQFL^v5>=5X{Iyl ze}(##X4*jbPf`^O?g5nNc5hgWg_`#`b1h-vC)C`MK*Jwo=z!Gxm0NvtG2Mh&|Fs`! z*6+rgJ#XZ}sQjcT59CQGyc-iMH2HG~rE7DE-a$z{MY`kK=}97x1rYm z;07c3$4Kw=Zabz?=V|2MR9x>{7;^p6toJ|2u?3U$zJdJvfyH-5d|niJoX!XL6~E<+ zmhJ&%*4sj7x^EG^NN@fj=>1QLu||Wml@RZ56d99x^PUfFAtv=U|1X91d@3g${heEp zgc}mzM%lRb8RF>|uKGJ_KO@Q$i-Gbm3BL(%Mtfp!RV3lJ)AURp>R3DJrIGt)L4n#_ z({W(K7b*$AmEnVH@Q28+EePlBG+{N9@K3RM+DV1kW2Dq7}tOwo?H=WH9lkE{XQU-bpD?leBT>obFN* z+Tepq(kg>mBCM9AhJ;xu>3g?5Nz1;Tx+hxv3r=GSF-h4S)B2v+|4d!dt_Yj+Z6c$2 z343Cwq(Dv5PNyztQeOI>$p@9Bji$)%N>EKn^{7&@C-&cV18?>8saK=L=S6u;GA7CS z-q!ZSvYjd%~vO9WoQ8R&$_G}tlv;$=YYR{$t zamFNddcF+kGqw?b$Y;|)1Y=T$e0Jm4VL2&A*6kR!Cnd?})%;N8x*NTqJ?AHaKoF;= zKCqTq83Bomohz}?84^kuJRLleCg+h{#-w1nC=1aF!+o0DhfBD+`wXmJwzGu#<3=3( zwJmSw3>P)$Pg&`s=HGEei(QP+yu$#eEGps>4}N>&(znh@ytdE}ru^)7a8%3uu_u;K{F-{`|#Hqj#bG7h8*J4mX8DHq-fncwQ03zhh=3lI*A*eDq(EKL zPBBRjAS!p0SS0BWDaec@?GT*^}$h>x-g1*bH(hOLBh9(Iu^b zjq~5M?xp{F7-*2I2HGx$$g6wew1Gy~vVP1}NkT)6DK9;V*#56aSS0CB7^J%xgh?;$ z7?ZS}+lHjEoyIq#;!C2uUnV9gy9*@Yf=Q4&c17|I125Y(Et(%NSklf#k$=D?2AU*X z%R&QUs9ks!Xin}U>xpTBuq-`6iNyow%M>frHoDp6#ltvLuX`@Ac^$+ zcKLOv{4&ns6Ok-+p7))rpT&Ql)Xw6wJ6mcQEk|@VX^WPjfr2n?(7C{OE>R1|j@+dA zKFL_4feb{u8EB3%WF;!@cq0}Z^EH9|AyoF(GSU|4k#MQGb8N8fYPI3U8M)b~q2epJ zU|>ahWe#_~FVST@c4I=1%xni&G(Vi=!PbhB>Sr{X8|nJp_a&l5RHOWnNHeC~_!#td za0!dtct4`GRo0b~V28hcfg$EIVFvK?*ws@Y^oT|GTAcgTq5 z2foSKahld7U`wzZZ391(@eW#Ni<&}dzNq0lSNuOxkzU&bxpLT zzUJ#wkP=xq84eW1Vs}iulGoPg%zOUWf1|N~it;!f`%K6A+N9M0)9GV~=F6n$hz`x~ zC{{`5w}!~}F$hx*w=1oKsjN1guES2e9Ti{4m3JPqOebp;Xl7$NdxFlDDe6U|gSiUD z6v)=OswlF18iXl2ekGmV+H%%%e~gccZ(sw#j618BMY9sq>1T;%7ey=RV4lhLvJ}X4 za;C`klbEE_#j2#!r7i0Wc&q;bXzfi=UQ!i1gAn9TVT8+&$nNcl=BrKBGaE2ZbHt#) zgG|TG2o$D*icZWrU5z%J)#LqxEod;Z|)58Uwz%L;k%I~{d)O8ff zH^X8*T*4%sUEE6R?BcgU$L!SOBvgD$lowi6bYPvwILBoNVtH{(iF(mu2YD*Hd(1l5 zfa1Uu6_j*#vn%N!>C_J8vzPXJ1r^^G<@xcEmF-)ijKtQ#MeXKma@31PhjL8cfFnCA zS3vAYijqz@uaXXCo7!|nrcboc!#kpUR4#6vAqiN=W;%u`nlF#jc?xuf5Jk;dca$*N zOu{6c-D9!S-D-o*!98~W0u|pC<)u}0_RZ1n$(T-W(D5wlMY9fm7?#~P;Kvo@T`948&M^F~M{OS)%!mw(6NjR`W~fdZ4R7w$2kS z2ERp^q|?o;q_am`v2*x{es!q$z9?IEoX%cY=5)w0ou0O6{=G}RXx8Zt>+D6CW}SNy zBHPm@Ow#FTRnqCzma}Fo*!~$*{6Lf!6ykKc`J!cPIM9b=MDslv>P4e7))v`rz5>}g zzr)BHA`417NZP?7MGdI#UK_DI>gW_I3VahtO*xB7}!#dq_-TI*7W>KDN#_8-~iWW1BoxVxY{HRI2Xmm_N zWcLU_rsIK5-y{{3bb7?-^sw5XbFh63t#>{a<;AHuo!$l9G?roO3`iq(eCkD`GcAoA zQ&1q&c?1?4kS0vh+1;y*ot|x3=Zq)zn2d^BMES_7*y)xLElUli(;uPyL`wC{;ni}a zi%`xekm=kBI{hW4tP`Wt%WK0rJI>o~f3)_AD9@-G==&u>Cv+A@MDy>=7@c}gWcN!} z(s?o?vfVwxB%M9|O6zp9+n}>(dFmom{8W@@=i<)VCnfUBEw;`9p!25!^%6NNe-h~I zlTsjC=Z{H|J-{PO(m_;L4D`Nc8+7VEKlW`@{I@6{U*)U;9v&$bT4#R~r&J~CMWb^p z!gheCK&JDDoXGBP5+>;wb|oFdZ-Y+a;p2}-#m_`}Y9el(9C0s}owy=Zh6 zBX)Yktn(P0)t|~KI(^+rI(^%6)(Lyh&!FOekayfTojnSo`M(9GgJzm2 zsOt`#FPr~lVxZfEN$c$6#pqaVSm&TE=3-R*98+l3B(WF9(pRB%_AB9J(WhP_>ok94 zAmx!Bjn3^Ugm;NBNvEGtNvB_1&g!sbDGl^5METfE+&cT&cy4A$XJ|?^-zR&C=(Oya zMAtTT9a-m*qR0+S5hm&E6|>I1i8idWYS`$1pkhgsmsMG3f26^#COd1eA(|gbQ!g5w z-C&*l3ku{=z8*dR^PmCm?Q?nZN}*&OZa(GXr1neq`Lz{gj47Y z3p;Kl#gVP^qK`Q%O_-wNRa$57w&?V@e|ttt6OIg zatzfckm4@1TOigJBb>`XRA zGZyT@hRO&e#nC?XqR|;v64}Y70-4SsrpS(v7L#-a#hf*;EoTkB;rLzA+IONnGa0we zp`i2YFz+0MmGhh+YB`jfuOw&1=u9v~_8^H#I#_@3dPiDkU|Y^Q;I$$D0-f(g`Oqq7 z4M()x5Ym|p>(qHDt6S#^Uu1_{3S{d{PQhZ4b^0eN=?pU3aMswHyZngOe!!VT6`dIg z(fq4$WQ{4(o#LwJ&^i~VMRo>Z;K+2QCJ;MC!lZSu_N}na{$3k&b~R7whl>BhmVp&_ z)&y5HUy|b3NoD9BZt6vgor^t@o!}~v=`2Bbr!s^|Is;>|vwvIGIV#(I11kQAy}@*x z&S5Fhd}ER6%mAJFaqHX!I)|mG>&QB3U^6s2Mx}N7w?(JV+7qroV?SXtt`w(}g0ozo z=}g7yry=M$bk^ktEJ17{I&_C~cB)O7v`&AslFojKHk{S9ZwEuRRW>tmI)}ko`OrF} zOLRwa0w2v;H`uU_t3YI_Q9rRh4%RLRS8@&DI&6 zq?_=l7mdy(E(Uc$fk8pKsV+M@NtmQFAW>l|!|=HKR+ z&J>>>3Z;4uopotRWDhnJ7!;((KV_%*gh@JsV{`_aZO~b@dHs6O*$!#Yt)i0?&A%xy zo#7bhoinQEkWMq=!Z%HTRR$6C>*9M)vXC+Prolc^Bc-2533+r6( zGM#al-{;sdIxVooSfi5895`znLCQMAy-GU6-8SeL&yU{$bha1ebSiG0>9EePJf<@> zNf$Y(7cF+KNQmt8n059xF|v|WP+DiCT}fv|q76F3r!;m&2Rn!|vP^9EYg7u(GMUb3 z4D`-E^`g6jSkS6NJFl0~-` zs-DBxxy2S)(^VkT8Rm=ZB#SUfXGA=9{5Gu9`+)_wgU(K(TvwHM#-~N|tr?~>4WT@^ zq-3Fcgdn~^VbUI^0rD~v$FfmDl)|rUd=@;}I z(z!N+wT)Rxr&n5JCniHWL*ubywLxd!`J-`;-eG5ia+R|Vfpsnm>EPmI%Y>ZjIiz!G zQe+PaII?xHeV-kd3F(Z8)A8D%bE-RN4d`?c<%X((KF$}-7y0b0kr?)0q~dfCJL7x> z1_kNKyxEZkVJei3N@pElwn1n0PF*d~*#&v06c6Q*80gm~n9f97V zfI-3hpItc1rh<~r&_pGjk!@M0=ltX>bg(O|Q$=S6taD3}=}aw&{Ik@FPUl*Tq8Yvd znalFqQ0by7wf*6H1P#5w4oE4B=haqAr7iRSClOlQ1Dzfw^>hq2RaB6d6l z1_kN&DB1B6lXQm1VrO_;bWVEVfPaF{ZrI38$LW|zgSUB1X9B+cJsG2OA7aN$RnVb_ zoMtCTOwt+SRyu2x-G+5m+0&MT4lI+c8d+lzJFkbKoWhKLw;QALY!P!-u7Xbfu@aVK zK4Fs1_{w`z8^+lGfA^-Ib>(VY)9$dlD6h8z!-e;zPAbx~{P^C~1L4(=;nfXpB7wz4 zCb-8GghckhwEDK*qHnV>9xf^Hy{TA$M(<6`&NhR39+jNu%5TBFsY`s^B#JR`mqEvl zPRX|@sv9=5N4x5ogSPD97%;m5rNBJFbo1*nm?(-0)bC9_&|^$er+Z03pRtYj1Kk2U zFwK~hkw4oeDU6-#a=C@25c3$DZ8Eko#OAq-o$ph*_md*K1b-1}`QF5Ye3v4G64nve zMib@oR~8`NWlRdr=V6dziV91J2Hcese?vpVC~QX1ug4k=qFssOEV_~Nlvm~=6Li=^ zlz+iV19#x8ve8Yp&eCt>Tx@7Ja%R(*oOeM)od6mlixHl$&rs);w{D^d1qSyo%3C)V z8;mvLFCj;D+G1?ACB-}5aoHmeB#=L364_h+^c?j_xD50OMzz#2ejs(M8A@HTa*+vw zdx~-s2XZKN0mAcppYOS?hwvW|$dX@nE;#P)vD70A^fMdkJSKHPT7kOMdW$jHR12Mw z%q2)_45cn>8F8jWga1WRJzr#xED$WEjtf&vbc@}1a^^vj7 za1stRFUbhZ0<3u<))Pm-0+MLSdKy!?Rns?uOcqan+6KQ_R6506%;Y#yX+)K9=%1GAkChT*^DKCLwcTrwz1bHfy zdW5a+pnY6VijIvPam&h*-)-@|z%QZYWDO zMNdjYb6hTzda`}O{RHwSlDY|Oj`9hYQb$`=kzBXEr=-?(#2>++9Wbw7PjKlW%0D*) zsmwLI$W*U0Q&NvK)r*59zw8l^x-1j?U@W^3MsbQPysn7HOs0rR%AbB4JYR!PVhBt878$R5J?aS)an$f$*^l z&qIqHdLo?NxbWE+nD@YsN_c%yy?#XU%PzC&p^_|ojv?}EQY`#fkKWv&c(N7q_rc?{ z3kqc6y*!bvm*mNTvSE78BpT;(O86>>oMSMiQr0cNj`awW!Y6oDj&3-_4q|!=SwLmy zL&pxg4|;ov@=6}QOffq@C-RTLnM&`x6mG9%TG^%e);-dTlJzL52J-?>G=G;<^tiG7 zJ#g0i0A#(pT9|%Qs$ihE`F|;a#u-z3DIL!V>ncZopAp#w9+i`Nv5>2pjm$)#cajnrsFJ$XF+8y}|10#{N0iS@#Y6d6 zNd3%UsSOyz`{0}8mrY}weq(beA7iP&R<1o9p?q42sAyxj3^yK|Rv^2!FN8OkjLC-S zWin`-G3imCEa zy+rxkc=Br6m=^g4)RQsYbdxVyrW6C=O&21uy_pJxH{A>qJiRKj^p8HFT9!$(7(|*hK0~IVN&Jv>T%pK-3(IJVOHqX?Z?;s7tQn)<&%uK zSN~yYDx2QOi2NDg(r6&hG`-=AmLWy<>Z|Z-xW;UHCWR;O5|fw(n*L!akiEJBo_Qm~ zm~6OZc$yk#OnDXS&Zbvw##A^P@cuI?!ld5AjH+<1yU2#jX+{*zb(eUd@MRCvK3s=> zqI?<)XZJQeW@rhl>CLpZ!fN`LOYgs;ek1obBT1o>0y#;Ia0RL|264*0sV(cCCXhcB z?mhOq-EfU4`b6%%At%r^9g%Vm^{V7HOeJx%+(>T2^vKWWw4Cq)C`0Nm({Vq)g@|oP z2fUrG@cMxmuV9Q{R_u{hi%sbWXGn=2UmJ{Grw$Xh4A}{Y80WCgxS=XHZF5SkiT_O^W7s zefH|TmdLM%$CXzfgja{c9@5~Bmw?C9L`AazvI`niAX}gdew%S^k}+5S6@LK_-fJv;qzz0-{3!Q1E#07A(sDjbYuU>A$;WvFN=ho(VKyzrh)SfF<{;8qg-Icvc9p2k94i9o^MX$9Kcmz@V1=W-Fa1Htx zB+6%TiVk-GhQXoX$}&4EDOzT`K@4V>fDf%KDbiX;OvAU&C9^1;X)T!@CLKf0QVDEa z5oh~JB28GML9(!xM01S6UUbOu4%vD1j}i_3N2rYJ=5mpGq>u7=qDphak)-fQBhuV3 z*AD}H)!2=jKwy7SKH01s(5)lP0=@7;(QO?u+oPA1D59++4l~sZO)hO6fhB8xO=y9! zh>!D9#3`~s^Opr`P=Or$pXI1o#*_uh7B$Y8ikMX>H;Eu=4mF@JL$_mH!ldwdZng03 z4ameCS;wal`j1Dgu7^H~_69?EF$!>6UAB%Ghp`+9$Avvj_(VgOiq>&%MJ!@c$0Zf0 zO9c;EFmQIBWKA>}3!Oc(lzEXr{)EnM>6>XCQRfq`0^F<8tj-{?K@n=!&mhk0+I=~g z4iV)I9N5>;BPK9%NR9G@0X><8I#UNMx-tnQ_em)MIF&cMY&leT&_VH=6R8DeKE3f%u!ho zJOCq`vstj#Y#nh3&E0{K%Rx9elOEaC(7Zy473tNhjxvkbzd z+yz?+>t`(tWo%YNVf|-9)S~3b9tR$a_J(0QvuY^Mz)=2&sd%Fo$o*%I!+JF2Hhb*r zIVq99RI<>-zYL)>l0=Q@%DmnDtVInm2JsjHm!sTh{H4l;F5YcJuP+JYPo(+mQtOC0 zDZ-UzJAAecJ#?{Q5qhIPYCrmF&8L&cqqh;Fyuyz17Y(7-5mT_9Jjzm2GO}qwP08n* zGFAH`pD98Mx<>X*)4QVar}8*e$E#@z)Pw@HC*6!OI{k(wV``BPQkx>b#74aOj8V(T zk+8_@G+{L-XzW}ErxFeG4P0~jnT`Kl7x{I-%Au!%*ny&aDyJ)I4^%q{s(}RZyiWjq zI^b)=0=H_UG#ul?o=4eH=rkPdg`sm&%ekMR?kG_{FBzZyrW$(a%qZ!hbC9P(N7;KW zg6tdgphnR+SbuO*aSD?L1=3VQfqEd#2<_a6qbiUN^0=Jz2i7_mwn2lzyx%e^hYTz0 z%J^AWy`J6bS=m`rdZD2XqeVHx(|wo-Ct`3=mZvC3s!m5&a9T&qw6HT6PzW_q_MVty zu4-^l=AWEqtkIC;#__scIpcW(`BRY@&MQ`*vZ+LPnoV6(C8g5ifQj}BSNLkx-f&bR z^y=Z}F0Vu77z7Td`wr}#u^8rgpPJ-hPF%q7o}pL>MW0~2tApL=S&u}AsH)5%>fnk| z=3n9m;W%}0&rIDr@q)HZbKPLF}WL5Ns498$OMaw8dN;oq*qorC zY8V&xN+=g%GGg;C{5Gnf8Vn*fe{=S)V?9qe)a14VjV1X7mLfba0o^+0Y)Y$vXN1_^ePwO~`vjc8_Ut2qYq z(jC&4su@(mk%VY+GTbg1d8J8MHmzf8WVx)z7zN8M=Si`*TD-#&(&bL=RL<=43^_tO`JoNFEY6Sjpf+}gAvPLrgW?kB}7xBr(=p`V_L@)OH4Dt zC(iOYIFTZ<%9dT;?>iAJC$yTq3{k$Jzzt|Df9Wz9vE0CrOa_YOsU-%foMO4g)G@_! zQ<5=axlQrbCAaGUu$@<8s^F`(fA2^wImI zR&yR~bZdzlkT1DY(SD}IVAT8Cw2rCX*M*h0x%cr+%il%slUvPnNtAE)xlyh6vkDAG zy`P)XG1dFIE@Ru=`{WPnpG5Bmx0-Wc`8zyrKV1Q+W2*O!9%I|w`<|B`d;@wv1loO3ZZ^09t@m{{gHiAH zRxE#m%jLGY_wI?_FQa#})m(%edwpn7t@m3hdQvfeg~2@$Bc=T}7GvD|_BAp*GO*=` zX@19RY?XT1Kbi81lDksNh$0SPcNrvUFS1KwD5Sy ziixNGCd@!I@zmdDVO4y+iNYO^>@oG1U^ERwu^`GQ23;i+vrt%b;>M z+Kl0pLfy*NbR9!jRRqtKY`P)E;Q!5$(=XoPUYPCBR&$DlEN^ftnj%1;?3N-oszvvWNd_ZES6e!!!sz-mW82*O zF2$~s(EE&5^VlQ;JM2j7eN%~Bje5Vlpku1{D{_o&bMJHSSkf82&ulf1K@htxH=ylA}g@0X-?O!fXNhU8Lvo95CJ-<@cgWg*F0gb=MQ1*#V}U(<#)y%&n!Mo! zv&IT&(FvKMU{u#?9$|{|uMBQLTLIndF-VNo_{8Yy3VSpfTtfXz~>9o!N_ixh6M>zcDvNo%PG6vSYnJAZBr`l*mdr2 z!DtS0N=cM&EOG-{D*mm>AoZ?N@nuOJQ>pm6jE<>P?B;Y#rQ+*79aE|J%5(*W61Zoj zpkpc(Ux_2?11>=-zQ@opm5Lu{NT%J5Cbjqbu#YGe7d$Q)kFaCrh?z(B`2f^~lR`XzF z=L?Onh3H)Wai2krWlF~s%Ug3grdU3b)G@{Kk1k{E`*v0{EBtP6?!6aS&c_^56y;09 zMzt~XK!IB&mdfMJMI8&qOiIU;cmEh-aqoU$)$s1o6AwNSjE=(6Jpo28H>!E}&Ju%c zH~vol64q$wh{DKj`iIH|-t`$LmJP1O+hFvk+E9|q`Mlrx(Vm~6wFRx_?35^97OIox zy2GH5@@#I5Iw-h=-J8)dl^pN&8H1D50}q-WwHVuG2hMx6`zc^_bgQ{AC(74&+<@l5 z-xV1oM#_PYS1?izyw%XlDF@!h(6%nqR``3IlKK{m7PgvmGgy`s!WN>1(i3S0BSv?d zI;I%iU(zwf=&>AQY@=;CC0yZ8%ub#UTF11SQ{lR6eQrfF)FU>7L`zY)%hIqQw-qYr zD_Zv_xg67KXY6gVQa=pLg3+Q@bBQg=(NaQVbf3$uMuz&GrDKZagP~EVoMQAyiOX#> zqlM!apA1HeadzQi1`Qj~R@i?iaI2Ax9?IyL>iy9oW8C|;xM`EM+uEZCfx;4O8d*5S zNOCKhQEpE&7*Tl8(6GQwuUQ%v80AkPMzpj(Xp-OA#l?@1#VPJ zNYA(oO7r_P=3gl3Sfe3xLj|_lBJ3qDCKH!RNPiAHiL>nF)nGZ%8}a~HF2(7IFUrsO zVXM(}^NP!0#PVM$9aAiyP3jo2)IU^Lv3%ZOJkGL9q6W+3pPRDG@An$JSfK^7V>x>cr}=TukkIc~tJN83w6ebz=4Rl!gT-R!mS!y4<0_gu zW?R(9tH}scKHQd+x5D4k+~*^h?YLI+XiS)YcexeKk#Bko5`E>gzZ5hqNO@6ZDyJM- z49jg}Xsz%w<_whWupDdGqA1^Ib4MDZCvyx^Pb#$j>g$+d`BX;76r+DuFw&E-Vbn+* zlTxE;t~?&QZb^hzi5u01J&yKSbo6$3g#4<<{!p(5%VoPPhTIM(x0*+#L^)b$ zYO(*7&%H$~KPc%Ku@p@oS~{j;|I>cCN zMc;oaFcp2@q`1AfUk@^C`1PdQ7IuflR^ZyOFUrw!UGu9baI2AD-*ogZ^+m_$jTrSSCrpFI`XqUafvJtj)MLF7> z)mVOKa;u>&olX^u6w7Z*db!#j|AC8DtuAV^9Q;a`JXoHNc^jksg;dx=xVmt5sOVkV z(n;pHATe(=$d=z%U^Q7fNt9NfZMNm$F=zY%EYHBc7+6LNy2zH!_HNLq=JD?eIwn~< z+oyD_Cd;P(T3l|MS?=9>ngf<+wweplu%*WhXe>KaFjBVcXmG*MmQKfjai(VHV1X^6x@(Xe;n9JZ_a3sWs5sMIDoCAZN!4Oy*i=*Q8!fu7RBG z7?Qq`Yal04QTJSrBIu_Q7o>jG8t8jN!-6%?4;dYkC%{f8kFjVC^n($x{J%LMn2uOq+^YS91EU~ zsqwL$uVZR_bS*Nr%`6WpG+qRj8(K~LDzp4xh8xgW4hq4D<^E|dNLZsmEDcY`6wAGm zI;L3eQ(%l;{C`;c54!H;N5OYvt7#!KKV0OdBwsZj?PfAa+~nHd>8A4t{Jd95FQ?*R z@329s6$ON|x5ee+R;@Xn&-4%51eSKIc^by^?>ufmvuY2MLD`c}J@sNpMrfl!*uE(S zsa(yh)M}nl#NLj@4QMQfg{?*`dwX0kVmZjyF~zdGrDKX^|0H8^mbFJur+!a@ zrPFGjXNvNpHaDQLG|~)4EW4F-tkIAoDx+hy8{j(x?BEphhw)MxpfnaSBX39L8%_78IQbI&>7 z@649$ZgMY}BVGjycG=#>-151+Jji8_r>DOPZ7=rN44BKu9Be@5vWbOIyKG}nCgzeZ zfA6w|gSllcHwAtpZIyS#3~;#y=F;Yc$79%lxI8wFP`hmBCkiH9^2D(&%~ShjTSRhx z)qdI5?^ot>^9Cnii?@uAJPTZ2;<0lb_y9KNchy_`I2)mM8MP==E|2$%MV@lml+nE6 z(UV6eTvl{faQ2dsO~B=)9$N+b<>M|k(02uirdfnSUA^-)OH#G~R^Si(Sjfuf=td)8 zjux+<*$C7x^VmF#7oLb?1F|KLVF>jcwK6HIHiY_NB`(z*HODlvC7VIET6S|8v?W`e zH{c|2xz=N68F00T_3-Myr$qBewae}$j+D#32F+70JD8NIE!oXyWiB@be!q2oo0&Vn z<>ek*0!PI&7B(d=TbDRe@6XW)CJN`mC0zs)F6knea@oj0UheWUGhmA^d13Ht;Bp=8 zZ{YG-U!1t?2M+&t3L&vA)dZ=B+Hiz%TlK1vIk_VWjB{WbJ=`A6$n-(;cN}>&)Z|zfVk{bqOP`h?>r{r zT=K-g5*ED0yEs@|?s8kuTz2_=P)~4qrN`#O7XQe^2E=7&7oncZ9wpAJ4KbI)BQ#IV zWk*Jtn#(>WvND&OZgv8;_%QqUN5JKJIC|hb_-z~;5SLw}2(`W+|&S#9Vf@DJ$-mj56i2 zOAJ~0Tn4(VGpqdt;PPsZofqSUPi$;JT*9?banUXZl{i-}#Vv~ruY>*4Fy(R@rtNlC5Bwdt^ViIcgUd}GJ3r40yIjA6p3CVmgxclA5>{}P|Tu#YSrd*D8kO`L+ zeG)kO^OYHJX~R=;n9Dc(ruvh>M5_|@WrlDxDT+$M`AS=`3GfrO2(}7Bo;W2=*>Y1d zmooK9;B2deIU;X5{Hqq(57u~M3M(RU22`H}CT8R*+h&No$rdvIlfZ=Odlt+xMPAI+ zc@=&V*l|jeB`{+*!L@FL7v6QS0okro4TQqEdWV^0Q&tTbJTab87JMX+^z+L0zTm6K z0bkeq16dNIA4rR*a)FfqU?>hw%x$B-BK`2~S^km}P*^R{e z;4L0IBgP9~S=fMlMq}Ct#ayaq_h*(c^|WGU>1d#cCq@}qTQ+Z-13w*{H6ZpCI7-2} z1(AxlvNwJrd~x}@YbE>XP3FG34G7%|N9xcz-1bq(;K|NT`lLI zr%%fw)GlX7C=)JuVx~!%+PWi4YSp>rbWAIM&#T#J1e~YGh3CEiE;H~+5}W~d#QYBW z-DFl0p>{dKq)fRy!!O3Ugkv{O^OVaoqsYqUGI)zO>pA6VaCs~2gDx+8p2Y@ai;u`5 z)GlL){vX$33nN%8TyA_O7TT-$>wDt2nqgi2S&ofQ<{Nnv#T)W%aBIML;X5n?P5kS! zi7`>6+T3c3vT8$Y=#@Fj)O5{rkx3))k#DWP4Aw1N|4eXnyT=w~;Wof;N)Fj&aqKD_ zsYCW`Ur8`^$j;8wyalkr6XGXoso2q8vj<%Sj<$O2%s4OPd~xDvaSXd^N9Wj-DMx3S zlqpA+flN3eUxW^ROxN|%^(uyx&* z;)Hw`e2fOi>E{MEAp79_7($`0j*5ARy-R-fZ za8$T{1LElHI8{=PR!1mPj^>r*siWe2Kd)j(M{Zxt!BN&@RunGV9TXyt7DN&1Ia-E@ z%+W#%p`N374w-ON(Z%n`>z2WVOw~Q$$bpMr0~?Tw-&I+JLP=fxE^{eU7rz(AC{q`| z7dn)wi{H3OnY#F0lq_M6*y0!2l*zBbB^JX^)B;|L7r)D?uKHDg#QAy5(-*(z<|tDa zze`A7g%@nySG3;*Gj^}XE`+`6vm`bp+wfcyq27iIeI>!vUUfF6$?dB4s+E3i#d}qF zNe}2$^)HWI6oT7-f0)G4atEcfqooFA%F&VtWy;Y~e~1-3iVbdY3^=;aW9L}B@Qs5_ ziK7)ZLhWcl2~&=$voudRs$s|~cGPt3-nW3G`{5i4bM#{#8xTjAI0&_)>n+NZqpM8H zl%u4BtYSy!*ynfyN0-{jDt6Rx>$0uj=wWzl30sZFumN#&afy<0v^Ix{+RVqs}1339sH{n zk*8co;;WfUR0#C7p1m~crKbXm@n zOFM$R;(f6G`eBe;^|;4s@-UY+HX!@p6>)?@UG0MjlQMPYSmRQr_Q4zcys~)<{^iX6 zy~9_6qbEGJISvnm{3#;ywgH9IdmZTV#EpL9KcBbDENocjGWZwI4p>yL8eBf?$0o2SQiclvNwJre6Pk>u&HxD&D${yguT6!SUF2a29@_sNo;4OV}1t zy>-_|C{tVah8$&T>n40wHg7dwIswP-5x=v#;OHrj**S2O#HM84)>{bmyj>fktlAJ; z{L(08>e$`jQl^fI&2eO9E`#ql7kxSP4{-Uk$JQo!;R6F35SQ1LsH?4eqm7Bexo}CB zzu&so*_d1AvL+u2n9HRr4*wKfKI5@e6kKMp0daY)gHX@qMn4f<^2A0)^VD2k;ZmmN za#IpnnakiKrNOeg`+>`6!KDLVX2@d$;&Mw2p?102PehlPBVGj)F6knea`{k@%is^^ zR&`!F4%$BFu^Vh&_}J2o{YQZJ_+7Qjl#7Yzk|!Q8DN}QKSA;U*5t%mb2iwyu-!ZGMAeJe{nth$T4?<)blWx5uX2Z zPc9$ErsNEMi-8bb^2DQ2%G6xm%qUZHxiyJQxUA@5`Ths*Ev|K5@Yw1sFEsQUkaxaK z26h#W)H~lDamv)Waa)YC1+c;s5Bqr)J6d?d@=@UEMUSOjUI_V3iK7RzR7p8{AV-;U zbdyP$a&(V@tYSy=Hw}cMs+T;rj`2dHJT@SXwmAs(9Nk>vQaMV;Xr6NPkb$gXM=kob z-Ul508|Em+3-uz{fH=CL&`O9HsnP!IY!hOoSCX>bzyz4si6c$F72{7V(9M zqx*fR9o_4ql6G`wlrrV$F~7EAM?H)YTfosP9=plp1t{|u|6TuHA8AK7I87~s>jwucwsLC8<07AB!*Bsx;IXl+G@8m%9Nw5&nkA*vrgkXz|m`P zb?)%OK~Zc<9XSZKql}-Z=g7{}Jmu&?h7285_RC-6mP}m-wsIc3EY1sca@d8~x+RHF zTliOuu;Opuq#eSFyLZM$hPG<`fa1iLPY@IJI$R2ccwryEX-Hg^s0VYYICj;JZqHJt zCgnaGS;guLw)MCa)Zg&frEs_(ZeatWeyb0)`kgi=3Z~Q_^;yO0b^DDM7X@#6>`K^e z>-)nb>M%FOMXTRsQKr=I&LOKqpR&O$E`fN~t$75SyuR9`wLPY)f zI6|$y!%x)ePcY1@SiR{1)%`&IU3lBe@xs9|Y(UhX$s^S2+mn>3?fz^IS;guj?0J1b zeTT_+1Qk-XAx?3$E8fE zKWQMVSpEFZTfGSC?|bZWgBLpZlSkCI`(3sAvnDDDrqrKDBtK!V=#p^28_`EW{R24O zVdjss{0{nD_o~mdy8iWbt^P_96DuBjt6AaiLH$D*dzKeEn%IDh{c#^^^(RWUh8p|7 z{k)3R7v9@pA*g@kv0LGYgG1k6{PVni7NgZ)k6@l2`^&zgiq*%gt~wIbKla!L*zPU- z24w6nMyZmz76%#c;AK5blVE2!`ESc36FpBOeE>aWHTYW2rU94Ymu9L%d&z4_Y17J>R_ zaOoc7g=4TDUj2RkX&b3le=A9uQh(J&R9Y2(fcjUk*X4Mjn=eGv-!ibPR(~T$nNoinQRVM4C$4KG z)W7!FwXn~3ar_Q?uY1KnsMTNhXIanu+b-te*ekisILke2*_fGN;Tw-_jPgQH3%iip zj5irVZQ-35Va3}FCr(&#hxpt<_D^iBF&mHByF1w01&^!qywD_qU5Kr(OoZCjkBqRQ zt#7H-qAec9ynkk^;qZk&fUR%gCdB21V{_Pr*edu;+xnUz1Xi?Fa0x5g`qCfgKeM&> zuHJuvt?xW`F&x1scLLAvYv2~VPl{{oK*!tdM*MxYX zyMbMZtuJhZ+SYfJ6=&;X%8Ik~KEv97Vrz}r{N|A_gRLLHR+1Om#;^;qrJtv2TRW4O zsAub2hp?h8*F^TuZ1qge6t~wu!pQ(mMO~uUh1mMShuYRp4kl__Klx)4d1@nmVqxAt zv$cGEzfZwd-ecFpzGax$h1lBVGi}SW5Nca_gRr8l9eHH`%+{$p4qXnm3UJk>2SDdZgY}NXBq{W;Ap9M!h!DTb-R;_JpO5RG`5+!xvx+{)} zdRu)LMJ6VNeqR5L8}JEGo91;t19c9cgu8IF7QqJO^MFsY2&IxMo=xYIlvNvoL7(Cx z^5&bkrd|b8Puf2)@F!(1FP;|U^00W1uHe#xn|YX{_P#iA`GF6$%kLwoB$#sfo=I7- z%g^GNSLSllXJ)`$hA$oQ61e;ie4=acLem&FATD>g2+<|3i&u16&VpTjnaA8RmlvOI z2e_V<^)q~a%6OrjKTP8CdkedwOP=61Wz~k*;$LSe6E1n;Q%0HE;y=Jo)Kczp zMv%*;+Z+B2F8>Qpp!0B?MzH~L`JvCW%kT3DaV~k{y&PrAiXp35z40&2js^8!;qxch-+D)} z0a5?VMX1%kv?!D6HT&4eDpnsEKW7K1|K_pBEnbKk*np^i>|65HYwG%Wf+_VnS%ej< zk3MhwU{L>`$DT9c8o_U%)obd-u&b}0_=8cV)b~eJ`33lKJ(_x;{=3IsjPXL}h~FXP z-}e2_Lg=g4)M1n<_5FNS@z^Ja$BR$-{_xnHQFv?3V^cl$#D7eLzIx)n24zw`@!upe zpG-KHt{G2Kqa?HGBJAh59lBTGvGUNfK*S@zRs*VQ_A(KQ3CP-l?OQUi z1+L8V2L_iD>c4!d2{~9RjF30`;J>%PdiQK7{>OHYJqbHb6OhBj|BAxzCL-ZTsqbx2 zRt;-B@gLuj$eV8p_D7cHsgvq&QDn7ESA&~RfnzFM<+0my@b2ki9ht6uErfcys(b<8 zaN-xg*q^S%UvaFh&B$p>hV=s@VUInXgoE40I%*`3P#f82cOx|i`b-=7rD7vJcZ`pL zk-a?jD9lJphML+);?E>P-$>$DC{l}_kzXBTzLA;+2C~{_WY}$E4+SH2;B@EmLNk8= z+DJ`<-Hp`j@1lTjq~-wMoHkNFhk3#X*^@V)>jqrJu$i-d07rX!Y+D2_2(cbs{XO|N z8>z3J_+NywY6IkI>YJ2_J((_|R_@6)5es>3)78MNcRrY_>#=|3;kMeuIz3&9|K$-1 z0d?SqVw9;vugXT|Pglb8Yil#I@G%oEPr~&)wjJK0yZZgLk(#iD0@}y{4rR(n-8eGe zNX_9nWPfX9`dZdLGw^#bvX9694Tn@$7wdrWA?j3kpp8%%x!V$(CS2J_L12{|`UINo z>#=*Xyl|p#RtqG4X1fa6lQV~@Z_p5XVQ0(%%i(`cmv zv)hHmHaHMYxQrLZ#IcSDG|nT`Bhb(DY8%0MQ|7gWW)Zk@b9iBF5_=JW6MUux42G~a zfmy%xsRPXp^4Mc0FHG5!z;Qm*0!LIVF#Y!)mw~{+9=p%tg#rF-kP#eXqgyR-q%T_A z2*%9rJOi2?;<5W-H|=L&FCx%%4+70iOsq|yx^w4F(5xX`1i>~iEvzE~NBK;Tppl5o&>>Tx7KgoW1jm7&JQ^&P6sa3};wJ1P=D0 z7HI4{sZC(WvJo#rvm-p_xV$hax(9(HvIw=n@iAnz2~2kn82|!D!fpy980}&m89~E1 zLM_n5XSE5mtUu`xXm*sxwwk;!(869spjiZ=7C6*FR+~WoadTQjv!g*E&kIA7SVsho zi6Ybjttu9n`}8OmnjHh%0FHyxAjZXi%RJseqy<_qWVMapC?UaBvo(9zkOZS#1J~ey%Gvvf;6(;&8I_ zdyx?w6~|^;pjjSSZ36RJj(ZcD9p|w-EM7R(??nWf`EIp9>u99{jcbD#<8%Eme(aC8iz7C6C0R-3?HjrUy!&6>hq zl!eO{f8<1<)gA=eL@E`Svm>?znl*#7X%42yz&aw(GKo-+ptX&xwh=Tqy3^)rk?&Ru9O8@CCa~YLJ@0{LEj;!>lo!UcJqSed2(`eWF=Vv~jM!A~91v*f zv1b{at{to+BY-Qv;-UpQ+Q|N1V52eOfNpi6*$Hr6l;?$!7S<7g{#k@tpr47XHh}?b zi3`nI!3ba@kI!Kp5g6nk)B>GNWVH!Q4b6HBnze>=k;4nq7}gPio<7t9?fg;ICeSZ> zTrX(W#$zwRUNk7O2Z8>35a{Bw+61QB$3oL^Tey5Tc%lEErl_rns(J)HD;_~xvqc{e zXb1ObNw})mlfXdiFF$KhcbT32#M(yC#W<=r2(*XW*brR&`euRQZESZN74!(Aab&d# zoZZlb(T1b&4VAfs>;MwZOoN1$r$$a}6}>0QbqT4JPEV7ZLFLlPT(JVPb6~ z7`LTvV`$b9P8AL>Fy9yvIN8Q#dIX((C$$MQ8nD;?(5#ck9*n_W#IP3;=#oW91R}_4 z6R2L$_m7}%XlFc^$YbB z4cNm7`bIFZwh=7-_+W8$-OXbUhj>Bn@?-=ZeN{bzPFAG?3qNl!t}42N0GujLcCd~J zFdLy3ILSm-+X#BcrwxZ@Jv{b$loy7?v5p9Iiy_nk{c^}^6X^Ov^;BqflE>bF-E=6H z!K=TUwqr=OK#vHr+63Z1cMzA3Jw5i70UO!DIwGLIZK(zHv$xs=>UCT;3!3%v*juoX zr<;2aIMGF@1=<_PY7-bg^rY87ptr}q&cShz$2u|s{Z#@j(8I#S+60=e9d!pZ>*KL+ zOc=qQ1O~d;Obhh&6KfM_|JagmL4bik9xi?(*o%yykAqMPbn{tl0{b-IcNjG5>#4^e7{KyS5((Ws9CCK;4f!y2!NnUu}<*Ax}Cvuu&4 zcj0oEt66}{A#2-Q2`&eE>{U3(R$Hp2_!mFwsTmhTs9jDoDN`=tj9gqqUa-s2SMsPXEV;_ZhArZj_#O35TLhW*bpD0+hA?9doNnWtaF_5j6QkQ&l;Kyd2 zUOmVImnVBH2V49+zX5SM$|^RMmw#%D4=-_~Tn^6DykM7OUCb+USrhojG*7tekTkd) z?6EiFyl^4I2E^q=AL_XrUBZ;hQMBhZp z%!yzF;&Mz9p>{bkN?Elb98D=@6)vEE}a+t?n2A7L0Y(QL& zh#}N2$0CyZs&Y9oi%{eR@0Y_}%qw-tgZIn%+h&Mc@Zqq<;Y_qRiVcX%Q}^ISW0 z#bY_j)LfooQl{o|goCWi<$2G<1Lm^p6OHx;mm@s(p3MtO88*-^SFhULf&Up>pLI*F0GA^@_L{{DvrTM3TyC%s3UzrVT77+z zvT6hN%hi|UD3f!!`U;CO=JIWeGBuamqsU5K^5DOSb6`zm5V#!eu^&Ucu+YE;#N}f?)GptTVWMEd zC0zs)F6knea`}Ocyws)FHt=t-Rwd7W99)j^*ei?|F80NV%MbI|)pwaVz@$vLB6I7036BVS6p{5(eU zl*_+d%B0JhHWsq7x!fH1Um5P_jXnxoPVks(!h4T{4ai(pGlbgZGZD(F4O~;NB2T!a zi(txSk34eWvZC)pkA30z4dC(=cqkErqsPSt@(V}mK5B}MP$;co(0cW~7G-k;tLcqM zU5CONuNmaeZ~43h{zsMJ!+TobXd*mhfPL^Bzk!~&nl}D8{duby96@=(stut&8Ig1p zG;dzJetur5ORw#7X23q!VDXfm;Bu13zIS=yOy+mMeb8&ivIxfstuvu z1O8Qu$P1p!Aui^Xy9~UtXq`VqJXSi@WA8_KVPy;(P?r`$?XsssnR3~YQKsgygGrg1 z%OQx$&pN?p@S#(VY6UK*cI~wo7*TLcAubj;b*V@>i3as-Xb1gW|5nX!idX+G> z#XDxPp~zEPygNe%hn3g%W4Rih1($yLl0#-6u`~B_#3`bqjU`o~dZOqPLxAw}Mt@VOfcD#{olM=UrI zj#vpVg4?jb?X+H`$OR|D5^LeJJ@#GTly52@(`U9US`0-_kiALH3eN%ATiX5>Ni+-@=$^|gx(V(K6Vj@Q@#og#fTdagH1SLDD z=z3S=h^1JRmn-3mcww0tRFq~iNf&+Z2oPS)3v->IqOGd4$Wwd7E>{*MKq+wJKJJeR ziHioQ`rmwC~Z@t~r6b7e)lECIr6z37rqP?1w! z^t~;MF888W1Wx(GrpOTs&K{F1>%8a%EJ*1NQ{;#Ri(I*Kg%>?1a7@p{MUGgCML#%l zCFw<1M1z!`jEEeu6pOxbIeL(e;5v_e4aFSg^GU%Y-9!%-5wP=Vks*9#N^5r*dyGaqK9)LM=Zr6u2ydJq6sIc=yqEs>7t(u0m8Ny zy~GGAddLzvVks(lj$FA3wv!!Hv^64f#8NE!*^w(Z!yb_hD%!?Gj#zL^j$FCLi>?U; z72Row9I>E1ORl86=rSv)=yg}*h^1Imu;ohHi(ZurD*8Ana>PI%N5FB>9b^=_7r#Df&e}lQ=_}QDMuZofE0pIm}1#n%SzC23sj6uWUOPQg1JiR$b z@UY+K?E<_HPuniR{fF)|1Mt2)oub(T7c5%|xIP%PNcQoE&AScoems3+lHe|{PW%yY z1D@WJCHOQpSzNO1&(j-if{*-j*8PAFfZ;dQ3b-XtKf(w;VQ~HZ0iOW9U4r*r&>{}F6;D4ACAiDHX$IidJpC`)WWPV> z2q$fL`l&3J=IQ%rlfFw1 z6u!HF?+D3mb>xJ`fV=Ya{UMFRp=T$FgXBb>zKsm0>Xhq7ehs)AV25OP{&0C6z}=w< zF&LgdC-f%Z9z18%#&eew%^`vC64)7!EHcU;*<7-T$sXOiI44>!do?#t89*&0_ZT32TX;C?*4 z!-dySs6S6{&&y~4Prv8LXdpcMS8NbZf5ap^nWtZg$Y?N6znhfN5T5=dE~BB4mzB{l zo_z^!q9r4UsL`7@q#XlF?Y`Cxg&9p8nX7 z;dto6WHf=NbBdk9({G!SP2}l!n2aXz^uHY$O@=(>;8bvLNH&G1Usk$PVQiLU(_mg? z5Sq@@udB#}*-$^7!P8&GB%I09U)wS|ji*0V(JY>J9m!7T>HoPOQF`4(PhwCv9(YUm+W%b9_pv- zc>4F4WLNM^14~9po;f5hqbq@_Xgz2!$*$t*KO-`_nrBoHx&}JCl5Kzy#bk6X0 zcxErfuIHJ(6}tgOnUr}Od1fCKZGt>Uvdxeek?*oQ$?YXIn;h z@JxrSjJ83Sq>S$5nKp45-NiF4Y#H6nGe<^bl;xRbu8i)1NCu&MdFF(i4FAP59Ss@X z2cA{M{SaA_JpdJ|^MgFoJSN#gJkyHF=wZ;XWb_C`c^N$l<4|25}j4Eo|8X)hG#~oif4JIb4;@5c&3L8Lfd)f>Cs#)A@XTNtgx=+up0*5kKo?c<9?uMk zN%lU^oTQ=;fH{(V$TKV{qmOu|S42i1LzI`%C*UtGBbR6TIWqc`XU67aw3BD17&7{d zXGXa)`kZG@WitALXU3?0U-HZ()$c1{D*75~lQQoc=x54k7tfsH$mm<1nJRiLd@zk8GjOu`ch>Z5;smUs;%TuQd6soGnQ}LXP_5tR~ zXkVT>)0Rho|REUo;p`KIFzTB8j>BxQc}zw}@YFg(Mn{4_S4Kzi z)WwP&%~O{+k{!cSi&fN^r)reiu{?EYRQ}Z9sdH3x98X=S@|y6}MYjCu@!%jYqo$yi zlu?VmZ+bez*8%tlC|QgL{3JndCD?m)CRibWz-gaYRae` zPhH^3s69`eZ^tOuD4{=8!ECg>cdkRrNMaW+L&a0 zdFm=tM*Voo&daDjPu*(CXaH2$G8)KJH<&US1iD!noeZubG8znBaxxmiQ&%$?4dtm# zhKz>s)D}lZ!=baP7y)AwC{#6)r>>03XcSLvP%Oq%*V&SdhDiN%40MS}HkPNHxQxc} z)ZIB5jpwN>lhFj8dNL`aQ+Vn*#U{c}vyx4MS`mb*CiB#@s`gZ#y3dwu3Qs*2k: -4.914ns/-481.988ns; real time: 7 secs +Level 2, iteration 1 +7(0.02%) conflicts; 473(70.18%) untouched conns; 424953 (nbr) score; +Estimated worst slack/total negative slack: -4.988ns/-424.953ns; real time: 7 secs +Level 3, iteration 1 +12(0.03%) conflicts; 254(37.69%) untouched conns; 455640 (nbr) score; +Estimated worst slack/total negative slack: -5.118ns/-455.640ns; real time: 7 secs +Level 4, iteration 1 +6(0.01%) conflicts; 0(0.00%) untouched conn; 465237 (nbr) score; +Estimated worst slack/total negative slack: -5.122ns/-465.237ns; real time: 7 secs + +Info: Initial congestion level at 75% usage is 0 +Info: Initial congestion area at 75% usage is 0 (0.00%) + +Start NBR section for normal routing at 05:03:35 08/15/23 +Level 4, iteration 1 +6(0.01%) conflicts; 0(0.00%) untouched conn; 461186 (nbr) score; +Estimated worst slack/total negative slack: -4.992ns/-461.186ns; real time: 7 secs +Level 4, iteration 2 +3(0.01%) conflicts; 0(0.00%) untouched conn; 460933 (nbr) score; +Estimated worst slack/total negative slack: -4.992ns/-460.933ns; real time: 7 secs +Level 4, iteration 3 +2(0.00%) conflicts; 0(0.00%) untouched conn; 461063 (nbr) score; +Estimated worst slack/total negative slack: -4.992ns/-461.063ns; real time: 7 secs +Level 4, iteration 4 +1(0.00%) conflict; 0(0.00%) untouched conn; 461063 (nbr) score; +Estimated worst slack/total negative slack: -4.992ns/-461.063ns; real time: 7 secs +Level 4, iteration 5 +0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; +Estimated worst slack/total negative slack: -5.122ns/-468.515ns; real time: 7 secs + +Start NBR section for performance tuning (iteration 1) at 05:03:35 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; +Estimated worst slack/total negative slack: -5.122ns/-468.515ns; real time: 7 secs + +Start NBR section for re-routing at 05:03:35 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; +Estimated worst slack/total negative slack: -5.122ns/-468.515ns; real time: 7 secs + +Start NBR section for post-routing at 05:03:35 08/15/23 + +End NBR router with 0 unrouted connection + +NBR Summary +----------- + Number of unrouted connections : 0 (0.00%) + Number of connections with timing violations : 260 (38.58%) + Estimated worst slack : -5.122ns + Timing score : 452301 +----------- +Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. + + + +WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. + Signal=nCCAS_c loads=6 clock_loads=4 + +Total CPU time 7 secs +Total REAL time: 7 secs +Completely routed. +End of route. 674 routed (100.00%); 0 unrouted. + +Hold time timing score: 0, hold timing errors: 0 + +Timing score: 452301 + +Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd. + + +All signals are completely routed. + + +PAR_SUMMARY::Run status = Completed +PAR_SUMMARY::Number of unrouted conns = 0 +PAR_SUMMARY::Worst slack> = -5.122 +PAR_SUMMARY::Timing score> = 452.301 +PAR_SUMMARY::Worst slack> = 0.304 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Number of errors = 0 + +Total CPU time to completion: 7 secs +Total REAL time to completion: 7 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.prf b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.prf new file mode 100644 index 0000000..ccdc34a --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.prf @@ -0,0 +1,80 @@ +SCHEMATIC START ; +# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:03:24 2023 + +SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ; +LOCATE COMP "RD[7]" SITE "43" ; +LOCATE COMP "RD[6]" SITE "42" ; +LOCATE COMP "RD[5]" SITE "41" ; +LOCATE COMP "RD[4]" SITE "40" ; +LOCATE COMP "RD[3]" SITE "39" ; +LOCATE COMP "RD[2]" SITE "38" ; +LOCATE COMP "RD[1]" SITE "37" ; +LOCATE COMP "RD[0]" SITE "36" ; +LOCATE COMP "Dout[7]" SITE "82" ; +LOCATE COMP "Dout[6]" SITE "78" ; +LOCATE COMP "Dout[5]" SITE "84" ; +LOCATE COMP "Dout[4]" SITE "83" ; +LOCATE COMP "Dout[3]" SITE "85" ; +LOCATE COMP "Dout[2]" SITE "87" ; +LOCATE COMP "Dout[1]" SITE "86" ; +LOCATE COMP "Dout[0]" SITE "76" ; +LOCATE COMP "LED" SITE "34" ; +LOCATE COMP "RBA[1]" SITE "60" ; +LOCATE COMP "RBA[0]" SITE "58" ; +LOCATE COMP "RA[11]" SITE "59" ; +LOCATE COMP "RA[10]" SITE "64" ; +LOCATE COMP "RA[9]" SITE "63" ; +LOCATE COMP "RA[8]" SITE "65" ; +LOCATE COMP "RA[7]" SITE "75" ; +LOCATE COMP "RA[6]" SITE "68" ; +LOCATE COMP "RA[5]" SITE "70" ; +LOCATE COMP "RA[4]" SITE "74" ; +LOCATE COMP "RA[3]" SITE "71" ; +LOCATE COMP "RA[2]" SITE "69" ; +LOCATE COMP "RA[1]" SITE "67" ; +LOCATE COMP "RA[0]" SITE "66" ; +LOCATE COMP "nRCS" SITE "57" ; +LOCATE COMP "RCKE" SITE "53" ; +LOCATE COMP "nRWE" SITE "49" ; +LOCATE COMP "nRRAS" SITE "54" ; +LOCATE COMP "nRCAS" SITE "52" ; +LOCATE COMP "RDQMH" SITE "51" ; +LOCATE COMP "RDQML" SITE "48" ; +LOCATE COMP "UFMCLK" SITE "29" ; +LOCATE COMP "UFMSDI" SITE "30" ; +LOCATE COMP "PHI2" SITE "8" ; +LOCATE COMP "MAin[9]" SITE "32" ; +LOCATE COMP "MAin[8]" SITE "25" ; +LOCATE COMP "MAin[7]" SITE "18" ; +LOCATE COMP "MAin[6]" SITE "24" ; +LOCATE COMP "MAin[5]" SITE "19" ; +LOCATE COMP "MAin[4]" SITE "20" ; +LOCATE COMP "MAin[3]" SITE "21" ; +LOCATE COMP "MAin[2]" SITE "13" ; +LOCATE COMP "MAin[1]" SITE "12" ; +LOCATE COMP "MAin[0]" SITE "14" ; +LOCATE COMP "CROW[1]" SITE "16" ; +LOCATE COMP "CROW[0]" SITE "10" ; +LOCATE COMP "Din[7]" SITE "1" ; +LOCATE COMP "Din[6]" SITE "2" ; +LOCATE COMP "Din[5]" SITE "98" ; +LOCATE COMP "Din[4]" SITE "99" ; +LOCATE COMP "Din[3]" SITE "97" ; +LOCATE COMP "Din[2]" SITE "88" ; +LOCATE COMP "Din[1]" SITE "96" ; +LOCATE COMP "Din[0]" SITE "3" ; +LOCATE COMP "nCCAS" SITE "9" ; +LOCATE COMP "nCRAS" SITE "17" ; +LOCATE COMP "nFWE" SITE "28" ; +LOCATE COMP "RCLK" SITE "62" ; +LOCATE COMP "UFMSDO" SITE "27" ; +SCHEMATIC END ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +COMMERCIAL ; + +// No timing preferences found. TRCE invokes auto-generation of timing preferences +// Section Autogen +FREQUENCY NET "RCLK_c" 299.401 MHz ; +FREQUENCY NET "PHI2_c" 99.079 MHz ; +// End Section Autogen diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.pt b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.pt new file mode 100644 index 0000000..e5e32de --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.pt @@ -0,0 +1,10 @@ +-v +10 + + + + +-gt +-sethld +-sp 4 +-sphld m diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.t2b b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.t2b new file mode 100644 index 0000000..a0ffb20 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.t2b @@ -0,0 +1,5 @@ + + +-g RamCfg:Reset + +-path "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC" diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.tw1 b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.tw1 new file mode 100644 index 0000000..4d39d68 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.tw1 @@ -0,0 +1,349 @@ + +Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:25 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf +Design file: ram2gs_lcmxo2_640hc_impl1_map.ncd +Preference file: ram2gs_lcmxo2_640hc_impl1.prf +Device,speed: LCMXO2-640HC,4 +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +Report Type: based on TRACE automatically generated preferences +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ; + 459 items scored, 245 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path exceeds requirements by 3.815ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i13 (from RCLK_c +) + Destination: FF Data in n8MEGEN_418 (to RCLK_c +) + + Delay: 6.873ns (28.2% logic, 71.8% route), 4 logic levels. + + Constraint Details: + + 6.873ns physical path delay SLICE_0 to SLICE_57 exceeds + 3.340ns delay constraint less + 0.282ns CE_SET requirement (totaling 3.058ns) by 3.815ns + + Physical Path Details: + + Data path SLICE_0 to SLICE_57: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 SLICE_0.CLK to SLICE_0.Q0 SLICE_0 (from RCLK_c) +ROUTE 3 e 1.234 SLICE_0.Q0 to SLICE_85.B0 FS_13 +CTOF_DEL --- 0.495 SLICE_85.B0 to SLICE_85.F0 SLICE_85 +ROUTE 5 e 1.234 SLICE_85.F0 to SLICE_57.A1 n10 +CTOF_DEL --- 0.495 SLICE_57.A1 to SLICE_57.F1 SLICE_57 +ROUTE 2 e 1.234 SLICE_57.F1 to SLICE_84.A0 n2367 +CTOF_DEL --- 0.495 SLICE_84.A0 to SLICE_84.F0 SLICE_84 +ROUTE 1 e 1.234 SLICE_84.F0 to SLICE_57.CE RCLK_c_enable_15 (to RCLK_c) + -------- + 6.873 (28.2% logic, 71.8% route), 4 logic levels. + +Warning: 139.762MHz is the maximum frequency for this preference. + + +================================================================================ +Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ; + 113 items scored, 104 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path exceeds requirements by 4.837ns (weighted slack = -9.674ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 9.577ns (30.6% logic, 69.4% route), 6 logic levels. + + Constraint Details: + + 9.577ns physical path delay SLICE_101 to SLICE_19 exceeds + 5.047ns delay constraint less + 0.307ns CE_SET requirement (totaling 4.740ns) by 4.837ns + + Physical Path Details: + + Data path SLICE_101 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 SLICE_101.CLK to SLICE_101.Q1 SLICE_101 (from PHI2_c) +ROUTE 1 e 1.234 SLICE_101.Q1 to SLICE_100.C1 Bank_7 +CTOF_DEL --- 0.495 SLICE_100.C1 to SLICE_100.F1 SLICE_100 +ROUTE 1 e 1.234 SLICE_100.F1 to SLICE_74.B1 n2277 +CTOF_DEL --- 0.495 SLICE_74.B1 to SLICE_74.F1 SLICE_74 +ROUTE 8 e 1.234 SLICE_74.F1 to SLICE_91.B1 n26 +CTOF_DEL --- 0.495 SLICE_91.B1 to SLICE_91.F1 SLICE_91 +ROUTE 1 e 1.234 SLICE_91.F1 to SLICE_88.D0 n2362 +CTOF_DEL --- 0.495 SLICE_88.D0 to SLICE_88.F0 SLICE_88 +ROUTE 3 e 0.480 SLICE_88.F0 to SLICE_88.C1 C1Submitted_N_237 +CTOF_DEL --- 0.495 SLICE_88.C1 to SLICE_88.F1 SLICE_88 +ROUTE 1 e 1.234 SLICE_88.F1 to SLICE_19.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 9.577 (30.6% logic, 69.4% route), 6 logic levels. + +Warning: 50.592MHz is the maximum frequency for this preference. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY NET "RCLK_c" 299.401000 MHz ; | 299.401 MHz| 139.762 MHz| 4 * + | | | +FREQUENCY NET "PHI2_c" 99.079000 MHz ; | 99.079 MHz| 50.592 MHz| 6 * + | | | +---------------------------------------------------------------------------- + + +2 preferences(marked by "*" above) not met. + +---------------------------------------------------------------------------- +Critical Nets | Loads| Errors| % of total +---------------------------------------------------------------------------- +n26 | 8| 78| 22.35% + | | | +---------------------------------------------------------------------------- + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 + Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Setup): +--------------- + +Timing errors: 349 Score: 848079 +Cumulative negative slack: 584487 + +Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:25 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf +Design file: ram2gs_lcmxo2_640hc_impl1_map.ncd +Preference file: ram2gs_lcmxo2_640hc_impl1.prf +Device,speed: LCMXO2-640HC,M +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ; + 459 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.351ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i4 (from RCLK_c +) + Destination: FF Data in IS_FSM__i5 (to RCLK_c +) + + Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels. + + Constraint Details: + + 0.332ns physical path delay SLICE_106 to SLICE_106 meets + -0.019ns M_HLD and + 0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns + + Physical Path Details: + + Data path SLICE_106 to SLICE_106: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 SLICE_106.CLK to SLICE_106.Q0 SLICE_106 (from RCLK_c) +ROUTE 1 e 0.199 SLICE_106.Q0 to SLICE_106.M1 n736 (to RCLK_c) + -------- + 0.332 (40.1% logic, 59.9% route), 1 logic levels. + + +================================================================================ +Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ; + 113 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.447ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted_406 (from PHI2_c -) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels. + + Constraint Details: + + 0.434ns physical path delay SLICE_15 to SLICE_15 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns + + Physical Path Details: + + Data path SLICE_15 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 SLICE_15.CLK to SLICE_15.Q0 SLICE_15 (from PHI2_c) +ROUTE 2 e 0.199 SLICE_15.Q0 to SLICE_15.C0 C1Submitted +CTOF_DEL --- 0.101 SLICE_15.C0 to SLICE_15.F0 SLICE_15 +ROUTE 1 e 0.001 SLICE_15.F0 to SLICE_15.DI0 n1398 (to PHI2_c) + -------- + 0.434 (53.9% logic, 46.1% route), 2 logic levels. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference(MIN Delays) | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY NET "RCLK_c" 299.401000 MHz ; | 0.000 ns| 0.351 ns| 1 + | | | +FREQUENCY NET "PHI2_c" 99.079000 MHz ; | 0.000 ns| 0.447 ns| 2 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 + Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 349 (setup), 0 (hold) +Score: 848079 (setup), 0 (hold) +Cumulative negative slack: 584487 (584487+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.twr b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.twr new file mode 100644 index 0000000..813d789 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.twr @@ -0,0 +1,2164 @@ + +Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:36 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf +Design file: ram2gs_lcmxo2_640hc_impl1.ncd +Preference file: ram2gs_lcmxo2_640hc_impl1.prf +Device,speed: LCMXO2-640HC,4 +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +Report Type: based on TRACE automatically generated preferences +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ; + 459 items scored, 264 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path exceeds requirements by 2.902ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i12 (from RCLK_c +) + Destination: FF Data in UFMSDI_417 (to RCLK_c +) + + Delay: 6.076ns (40.0% logic, 60.0% route), 5 logic levels. + + Constraint Details: + + 6.076ns physical path delay SLICE_1 to SLICE_45 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.902ns + + Physical Path Details: + + Data path SLICE_1 to SLICE_45: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C8C.CLK to R6C8C.Q1 SLICE_1 (from RCLK_c) +ROUTE 5 0.984 R6C8C.Q1 to R4C8D.D1 FS_12 +CTOF_DEL --- 0.495 R4C8D.D1 to R4C8D.F1 SLICE_80 +ROUTE 3 1.598 R4C8D.F1 to R4C7B.C1 n2375 +CTOF_DEL --- 0.495 R4C7B.C1 to R4C7B.F1 SLICE_95 +ROUTE 1 0.436 R4C7B.F1 to R4C7A.C1 n7 +CTOF_DEL --- 0.495 R4C7A.C1 to R4C7A.F1 SLICE_45 +ROUTE 1 0.626 R4C7A.F1 to R4C7A.D0 n2174 +CTOF_DEL --- 0.495 R4C7A.D0 to R4C7A.F0 SLICE_45 +ROUTE 1 0.000 R4C7A.F0 to R4C7A.DI0 UFMSDI_N_231 (to RCLK_c) + -------- + 6.076 (40.0% logic, 60.0% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R6C8C.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_45: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R4C7A.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.710ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i14 (from RCLK_c +) + Destination: FF Data in UFMSDI_417 (to RCLK_c +) + + Delay: 5.884ns (41.3% logic, 58.7% route), 5 logic levels. + + Constraint Details: + + 5.884ns physical path delay SLICE_0 to SLICE_45 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.710ns + + Physical Path Details: + + Data path SLICE_0 to SLICE_45: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C8D.CLK to R6C8D.Q1 SLICE_0 (from RCLK_c) +ROUTE 5 0.792 R6C8D.Q1 to R4C8D.C1 FS_14 +CTOF_DEL --- 0.495 R4C8D.C1 to R4C8D.F1 SLICE_80 +ROUTE 3 1.598 R4C8D.F1 to R4C7B.C1 n2375 +CTOF_DEL --- 0.495 R4C7B.C1 to R4C7B.F1 SLICE_95 +ROUTE 1 0.436 R4C7B.F1 to R4C7A.C1 n7 +CTOF_DEL --- 0.495 R4C7A.C1 to R4C7A.F1 SLICE_45 +ROUTE 1 0.626 R4C7A.F1 to R4C7A.D0 n2174 +CTOF_DEL --- 0.495 R4C7A.D0 to R4C7A.F0 SLICE_45 +ROUTE 1 0.000 R4C7A.F0 to R4C7A.DI0 UFMSDI_N_231 (to RCLK_c) + -------- + 5.884 (41.3% logic, 58.7% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_0: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R6C8D.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_45: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R4C7A.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.665ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CASr2_383 (from RCLK_c +) + Destination: FF Data in nRCS_396 (to RCLK_c +) + + Delay: 5.839ns (41.7% logic, 58.3% route), 5 logic levels. + + Constraint Details: + + 5.839ns physical path delay SLICE_16 to SLICE_61 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.665ns + + Physical Path Details: + + Data path SLICE_16 to SLICE_61: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R4C9B.CLK to R4C9B.Q1 SLICE_16 (from RCLK_c) +ROUTE 3 1.000 R4C9B.Q1 to R6C9D.A0 CASr2 +CTOF_DEL --- 0.495 R6C9D.A0 to R6C9D.F0 SLICE_96 +ROUTE 2 0.976 R6C9D.F0 to R6C9C.A0 nRCS_N_146 +CTOF_DEL --- 0.495 R6C9C.A0 to R6C9C.F0 SLICE_81 +ROUTE 2 0.995 R6C9C.F0 to R6C11D.A1 nRCS_N_142 +CTOF_DEL --- 0.495 R6C11D.A1 to R6C11D.F1 SLICE_61 +ROUTE 1 0.436 R6C11D.F1 to R6C11D.C0 nRCS_N_141 +CTOF_DEL --- 0.495 R6C11D.C0 to R6C11D.F0 SLICE_61 +ROUTE 1 0.000 R6C11D.F0 to R6C11D.DI0 nRCS_N_136 (to RCLK_c) + -------- + 5.839 (41.7% logic, 58.3% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_16: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R4C9B.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_61: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R6C11D.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.621ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i15 (from RCLK_c +) + Destination: FF Data in n8MEGEN_418 (to RCLK_c +) + + Delay: 5.679ns (34.1% logic, 65.9% route), 4 logic levels. + + Constraint Details: + + 5.679ns physical path delay SLICE_9 to SLICE_57 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.282ns CE_SET requirement (totaling 3.058ns) by 2.621ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_57: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C9A.CLK to R6C9A.Q0 SLICE_9 (from RCLK_c) +ROUTE 3 1.320 R6C9A.Q0 to R4C8A.A0 FS_15 +CTOF_DEL --- 0.495 R4C8A.A0 to R4C8A.F0 SLICE_85 +ROUTE 5 0.793 R4C8A.F0 to R4C8B.C1 n10 +CTOF_DEL --- 0.495 R4C8B.C1 to R4C8B.F1 SLICE_57 +ROUTE 2 0.976 R4C8B.F1 to R4C8C.A0 n2367 +CTOF_DEL --- 0.495 R4C8C.A0 to R4C8C.F0 SLICE_84 +ROUTE 1 0.653 R4C8C.F0 to R4C8B.CE RCLK_c_enable_15 (to RCLK_c) + -------- + 5.679 (34.1% logic, 65.9% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R6C9A.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_57: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R4C8B.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.513ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i12 (from RCLK_c +) + Destination: FF Data in n8MEGEN_418 (to RCLK_c +) + + Delay: 5.571ns (34.8% logic, 65.2% route), 4 logic levels. + + Constraint Details: + + 5.571ns physical path delay SLICE_1 to SLICE_57 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.282ns CE_SET requirement (totaling 3.058ns) by 2.513ns + + Physical Path Details: + + Data path SLICE_1 to SLICE_57: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C8C.CLK to R6C8C.Q1 SLICE_1 (from RCLK_c) +ROUTE 5 0.984 R6C8C.Q1 to R4C8D.D1 FS_12 +CTOF_DEL --- 0.495 R4C8D.D1 to R4C8D.F1 SLICE_80 +ROUTE 3 1.021 R4C8D.F1 to R4C8B.B1 n2375 +CTOF_DEL --- 0.495 R4C8B.B1 to R4C8B.F1 SLICE_57 +ROUTE 2 0.976 R4C8B.F1 to R4C8C.A0 n2367 +CTOF_DEL --- 0.495 R4C8C.A0 to R4C8C.F0 SLICE_84 +ROUTE 1 0.653 R4C8C.F0 to R4C8B.CE RCLK_c_enable_15 (to RCLK_c) + -------- + 5.571 (34.8% logic, 65.2% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R6C8C.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_57: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R4C8B.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.487ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i3 (from RCLK_c +) + Destination: FF Data in n8MEGEN_418 (to RCLK_c +) + + Delay: 5.545ns (34.9% logic, 65.1% route), 4 logic levels. + + Constraint Details: + + 5.545ns physical path delay SLICE_8 to SLICE_57 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.282ns CE_SET requirement (totaling 3.058ns) by 2.487ns + + Physical Path Details: + + Data path SLICE_8 to SLICE_57: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C7C.CLK to R6C7C.Q0 SLICE_8 (from RCLK_c) +ROUTE 2 1.306 R6C7C.Q0 to R4C7D.A1 FS_3 +CTOF_DEL --- 0.495 R4C7D.A1 to R4C7D.F1 SLICE_86 +ROUTE 1 1.004 R4C7D.F1 to R4C7D.B0 n14 +CTOF_DEL --- 0.495 R4C7D.B0 to R4C7D.F0 SLICE_86 +ROUTE 1 0.645 R4C7D.F0 to R4C8C.D0 n4_adj_7 +CTOF_DEL --- 0.495 R4C8C.D0 to R4C8C.F0 SLICE_84 +ROUTE 1 0.653 R4C8C.F0 to R4C8B.CE RCLK_c_enable_15 (to RCLK_c) + -------- + 5.545 (34.9% logic, 65.1% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_8: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R6C7C.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_57: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R4C8B.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.479ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i15 (from RCLK_c +) + Destination: FF Data in nUFMCS_415 (to RCLK_c +) + + Delay: 5.653ns (43.0% logic, 57.0% route), 5 logic levels. + + Constraint Details: + + 5.653ns physical path delay SLICE_9 to SLICE_70 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.479ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_70: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C9A.CLK to R6C9A.Q0 SLICE_9 (from RCLK_c) +ROUTE 3 1.320 R6C9A.Q0 to R4C8A.A0 FS_15 +CTOF_DEL --- 0.495 R4C8A.A0 to R4C8A.F0 SLICE_85 +ROUTE 5 0.640 R4C8A.F0 to R4C9D.D1 n10 +CTOF_DEL --- 0.495 R4C9D.D1 to R4C9D.F1 SLICE_76 +ROUTE 2 0.635 R4C9D.F1 to R4C9A.D1 n2368 +CTOF_DEL --- 0.495 R4C9A.D1 to R4C9A.F1 SLICE_70 +ROUTE 1 0.626 R4C9A.F1 to R4C9A.D0 n64 +CTOF_DEL --- 0.495 R4C9A.D0 to R4C9A.F0 SLICE_70 +ROUTE 1 0.000 R4C9A.F0 to R4C9A.DI0 nUFMCS_N_199 (to RCLK_c) + -------- + 5.653 (43.0% logic, 57.0% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R6C9A.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_70: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R4C9A.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.452ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i15 (from RCLK_c +) + Destination: FF Data in UFMCLK_416 (to RCLK_c +) + + Delay: 5.626ns (43.2% logic, 56.8% route), 5 logic levels. + + Constraint Details: + + 5.626ns physical path delay SLICE_9 to SLICE_44 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.452ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_44: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C9A.CLK to R6C9A.Q0 SLICE_9 (from RCLK_c) +ROUTE 3 1.320 R6C9A.Q0 to R4C8A.A0 FS_15 +CTOF_DEL --- 0.495 R4C8A.A0 to R4C8A.F0 SLICE_85 +ROUTE 5 0.672 R4C8A.F0 to R4C8A.D1 n10 +CTOF_DEL --- 0.495 R4C8A.D1 to R4C8A.F1 SLICE_85 +ROUTE 1 0.766 R4C8A.F1 to R4C6B.C1 n2267 +CTOF_DEL --- 0.495 R4C6B.C1 to R4C6B.F1 SLICE_44 +ROUTE 1 0.436 R4C6B.F1 to R4C6B.C0 n1893 +CTOF_DEL --- 0.495 R4C6B.C0 to R4C6B.F0 SLICE_44 +ROUTE 1 0.000 R4C6B.F0 to R4C6B.DI0 UFMCLK_N_224 (to RCLK_c) + -------- + 5.626 (43.2% logic, 56.8% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R6C9A.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_44: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R4C6B.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.438ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CASr3_384 (from RCLK_c +) + Destination: FF Data in nRCS_396 (to RCLK_c +) + + Delay: 5.612ns (43.3% logic, 56.7% route), 5 logic levels. + + Constraint Details: + + 5.612ns physical path delay SLICE_5 to SLICE_61 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.438ns + + Physical Path Details: + + Data path SLICE_5 to SLICE_61: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C7A.CLK to R6C7A.Q0 SLICE_5 (from RCLK_c) +ROUTE 2 0.773 R6C7A.Q0 to R6C9D.C0 CASr3 +CTOF_DEL --- 0.495 R6C9D.C0 to R6C9D.F0 SLICE_96 +ROUTE 2 0.976 R6C9D.F0 to R6C9C.A0 nRCS_N_146 +CTOF_DEL --- 0.495 R6C9C.A0 to R6C9C.F0 SLICE_81 +ROUTE 2 0.995 R6C9C.F0 to R6C11D.A1 nRCS_N_142 +CTOF_DEL --- 0.495 R6C11D.A1 to R6C11D.F1 SLICE_61 +ROUTE 1 0.436 R6C11D.F1 to R6C11D.C0 nRCS_N_141 +CTOF_DEL --- 0.495 R6C11D.C0 to R6C11D.F0 SLICE_61 +ROUTE 1 0.000 R6C11D.F0 to R6C11D.DI0 nRCS_N_136 (to RCLK_c) + -------- + 5.612 (43.3% logic, 56.7% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_5: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R6C7A.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_61: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R6C11D.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.423ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i13 (from RCLK_c +) + Destination: FF Data in UFMCLK_416 (to RCLK_c +) + + Delay: 5.597ns (43.5% logic, 56.5% route), 5 logic levels. + + Constraint Details: + + 5.597ns physical path delay SLICE_0 to SLICE_44 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.423ns + + Physical Path Details: + + Data path SLICE_0 to SLICE_44: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C8D.CLK to R6C8D.Q0 SLICE_0 (from RCLK_c) +ROUTE 3 1.433 R6C8D.Q0 to R6C6C.B0 FS_13 +CTOF_DEL --- 0.495 R6C6C.B0 to R6C6C.F0 SLICE_105 +ROUTE 1 0.315 R6C6C.F0 to R6C6A.D1 n12 +CTOF_DEL --- 0.495 R6C6A.D1 to R6C6A.F1 SLICE_82 +ROUTE 3 0.981 R6C6A.F1 to R4C6B.D1 n13_adj_6 +CTOF_DEL --- 0.495 R4C6B.D1 to R4C6B.F1 SLICE_44 +ROUTE 1 0.436 R4C6B.F1 to R4C6B.C0 n1893 +CTOF_DEL --- 0.495 R4C6B.C0 to R4C6B.F0 SLICE_44 +ROUTE 1 0.000 R4C6B.F0 to R4C6B.DI0 UFMCLK_N_224 (to RCLK_c) + -------- + 5.597 (43.5% logic, 56.5% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_0: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R6C8D.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_44: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R4C6B.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + +Warning: 160.205MHz is the maximum frequency for this preference. + + +================================================================================ +Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ; + 113 items scored, 85 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path exceeds requirements by 2.561ns (weighted slack = -5.122ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i3 (from PHI2_c +) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 7.301ns (40.1% logic, 59.9% route), 6 logic levels. + + Constraint Details: + + 7.301ns physical path delay SLICE_103 to SLICE_19 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.307ns CE_SET requirement (totaling 4.740ns) by 2.561ns + + Physical Path Details: + + Data path SLICE_103 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R5C9B.CLK to R5C9B.Q1 SLICE_103 (from PHI2_c) +ROUTE 1 1.023 R5C9B.Q1 to R5C7A.B0 Bank_3 +CTOF_DEL --- 0.495 R5C7A.B0 to R5C7A.F0 SLICE_68 +ROUTE 1 0.626 R5C7A.F0 to R5C7D.D1 n2287 +CTOF_DEL --- 0.495 R5C7D.D1 to R5C7D.F1 SLICE_74 +ROUTE 8 0.693 R5C7D.F1 to R5C8A.D1 n26 +CTOF_DEL --- 0.495 R5C8A.D1 to R5C8A.F1 SLICE_91 +ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 +CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 +ROUTE 3 0.635 R5C9A.F0 to R5C9A.D1 C1Submitted_N_237 +CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_88 +ROUTE 1 0.653 R5C9A.F1 to R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 7.301 (40.1% logic, 59.9% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_103: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R5C9B.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R5C9D.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.184ns (weighted slack = -4.368ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i3 (from PHI2_c +) + Destination: FF Data in ADSubmitted_407 (to PHI2_c -) + + Delay: 6.946ns (35.0% logic, 65.0% route), 5 logic levels. + + Constraint Details: + + 6.946ns physical path delay SLICE_103 to SLICE_10 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.285ns LSR_SET requirement (totaling 4.762ns) by 2.184ns + + Physical Path Details: + + Data path SLICE_103 to SLICE_10: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R5C9B.CLK to R5C9B.Q1 SLICE_103 (from PHI2_c) +ROUTE 1 1.023 R5C9B.Q1 to R5C7A.B0 Bank_3 +CTOF_DEL --- 0.495 R5C7A.B0 to R5C7A.F0 SLICE_68 +ROUTE 1 0.626 R5C7A.F0 to R5C7D.D1 n2287 +CTOF_DEL --- 0.495 R5C7D.D1 to R5C7D.F1 SLICE_74 +ROUTE 8 0.693 R5C7D.F1 to R5C8A.D1 n26 +CTOF_DEL --- 0.495 R5C8A.D1 to R5C8A.F1 SLICE_91 +ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 +CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 +ROUTE 3 1.428 R5C9A.F0 to R3C8A.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 6.946 (35.0% logic, 65.0% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_103: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R5C9B.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_10: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R3C8A.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.184ns (weighted slack = -4.368ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i3 (from PHI2_c +) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 6.946ns (35.0% logic, 65.0% route), 5 logic levels. + + Constraint Details: + + 6.946ns physical path delay SLICE_103 to SLICE_15 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.285ns LSR_SET requirement (totaling 4.762ns) by 2.184ns + + Physical Path Details: + + Data path SLICE_103 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R5C9B.CLK to R5C9B.Q1 SLICE_103 (from PHI2_c) +ROUTE 1 1.023 R5C9B.Q1 to R5C7A.B0 Bank_3 +CTOF_DEL --- 0.495 R5C7A.B0 to R5C7A.F0 SLICE_68 +ROUTE 1 0.626 R5C7A.F0 to R5C7D.D1 n2287 +CTOF_DEL --- 0.495 R5C7D.D1 to R5C7D.F1 SLICE_74 +ROUTE 8 0.693 R5C7D.F1 to R5C8A.D1 n26 +CTOF_DEL --- 0.495 R5C8A.D1 to R5C8A.F1 SLICE_91 +ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 +CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 +ROUTE 3 1.428 R5C9A.F0 to R3C8B.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 6.946 (35.0% logic, 65.0% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_103: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R5C9B.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R3C8B.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.161ns (weighted slack = -4.322ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i6 (from PHI2_c +) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 6.901ns (42.4% logic, 57.6% route), 6 logic levels. + + Constraint Details: + + 6.901ns physical path delay SLICE_101 to SLICE_19 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.307ns CE_SET requirement (totaling 4.740ns) by 2.161ns + + Physical Path Details: + + Data path SLICE_101 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R4C7C.CLK to R4C7C.Q0 SLICE_101 (from PHI2_c) +ROUTE 1 0.623 R4C7C.Q0 to R5C7A.D0 Bank_6 +CTOF_DEL --- 0.495 R5C7A.D0 to R5C7A.F0 SLICE_68 +ROUTE 1 0.626 R5C7A.F0 to R5C7D.D1 n2287 +CTOF_DEL --- 0.495 R5C7D.D1 to R5C7D.F1 SLICE_74 +ROUTE 8 0.693 R5C7D.F1 to R5C8A.D1 n26 +CTOF_DEL --- 0.495 R5C8A.D1 to R5C8A.F1 SLICE_91 +ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 +CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 +ROUTE 3 0.635 R5C9A.F0 to R5C9A.D1 C1Submitted_N_237 +CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_88 +ROUTE 1 0.653 R5C9A.F1 to R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 6.901 (42.4% logic, 57.6% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_101: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R4C7C.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R5C9D.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.092ns (weighted slack = -4.184ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 6.832ns (42.8% logic, 57.2% route), 6 logic levels. + + Constraint Details: + + 6.832ns physical path delay SLICE_101 to SLICE_19 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.307ns CE_SET requirement (totaling 4.740ns) by 2.092ns + + Physical Path Details: + + Data path SLICE_101 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R4C7C.CLK to R4C7C.Q1 SLICE_101 (from PHI2_c) +ROUTE 1 0.744 R4C7C.Q1 to R5C7B.C1 Bank_7 +CTOF_DEL --- 0.495 R5C7B.C1 to R5C7B.F1 SLICE_100 +ROUTE 1 0.436 R5C7B.F1 to R5C7D.C1 n2277 +CTOF_DEL --- 0.495 R5C7D.C1 to R5C7D.F1 SLICE_74 +ROUTE 8 0.693 R5C7D.F1 to R5C8A.D1 n26 +CTOF_DEL --- 0.495 R5C8A.D1 to R5C8A.F1 SLICE_91 +ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 +CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 +ROUTE 3 0.635 R5C9A.F0 to R5C9A.D1 C1Submitted_N_237 +CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_88 +ROUTE 1 0.653 R5C9A.F1 to R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 6.832 (42.8% logic, 57.2% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_101: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R4C7C.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R5C9D.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.081ns (weighted slack = -4.162ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i4 (from PHI2_c +) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 6.821ns (42.9% logic, 57.1% route), 6 logic levels. + + Constraint Details: + + 6.821ns physical path delay SLICE_102 to SLICE_19 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.307ns CE_SET requirement (totaling 4.740ns) by 2.081ns + + Physical Path Details: + + Data path SLICE_102 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R5C6A.CLK to R5C6A.Q0 SLICE_102 (from PHI2_c) +ROUTE 1 0.766 R5C6A.Q0 to R5C8D.C1 Bank_4 +CTOF_DEL --- 0.495 R5C8D.C1 to R5C8D.F1 SLICE_99 +ROUTE 2 0.635 R5C8D.F1 to R5C8B.D1 n22 +CTOF_DEL --- 0.495 R5C8B.D1 to R5C8B.F1 SLICE_79 +ROUTE 7 0.461 R5C8B.F1 to R5C8A.C1 n2369 +CTOF_DEL --- 0.495 R5C8A.C1 to R5C8A.F1 SLICE_91 +ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 +CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 +ROUTE 3 0.635 R5C9A.F0 to R5C9A.D1 C1Submitted_N_237 +CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_88 +ROUTE 1 0.653 R5C9A.F1 to R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 6.821 (42.9% logic, 57.1% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_102: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R5C6A.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R5C9D.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 1.971ns (weighted slack = -3.942ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i0 (from PHI2_c +) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 6.711ns (43.6% logic, 56.4% route), 6 logic levels. + + Constraint Details: + + 6.711ns physical path delay SLICE_93 to SLICE_19 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.307ns CE_SET requirement (totaling 4.740ns) by 1.971ns + + Physical Path Details: + + Data path SLICE_93 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R5C8C.CLK to R5C8C.Q0 SLICE_93 (from PHI2_c) +ROUTE 1 0.623 R5C8C.Q0 to R5C7B.D1 Bank_0 +CTOF_DEL --- 0.495 R5C7B.D1 to R5C7B.F1 SLICE_100 +ROUTE 1 0.436 R5C7B.F1 to R5C7D.C1 n2277 +CTOF_DEL --- 0.495 R5C7D.C1 to R5C7D.F1 SLICE_74 +ROUTE 8 0.693 R5C7D.F1 to R5C8A.D1 n26 +CTOF_DEL --- 0.495 R5C8A.D1 to R5C8A.F1 SLICE_91 +ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 +CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 +ROUTE 3 0.635 R5C9A.F0 to R5C9A.D1 C1Submitted_N_237 +CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_88 +ROUTE 1 0.653 R5C9A.F1 to R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 6.711 (43.6% logic, 56.4% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R5C8C.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R5C9D.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 1.941ns (weighted slack = -3.882ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i1 (from PHI2_c +) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 6.681ns (43.8% logic, 56.2% route), 6 logic levels. + + Constraint Details: + + 6.681ns physical path delay SLICE_93 to SLICE_19 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.307ns CE_SET requirement (totaling 4.740ns) by 1.941ns + + Physical Path Details: + + Data path SLICE_93 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R5C8C.CLK to R5C8C.Q1 SLICE_93 (from PHI2_c) +ROUTE 1 0.626 R5C8C.Q1 to R5C8D.D1 Bank_1 +CTOF_DEL --- 0.495 R5C8D.D1 to R5C8D.F1 SLICE_99 +ROUTE 2 0.635 R5C8D.F1 to R5C8B.D1 n22 +CTOF_DEL --- 0.495 R5C8B.D1 to R5C8B.F1 SLICE_79 +ROUTE 7 0.461 R5C8B.F1 to R5C8A.C1 n2369 +CTOF_DEL --- 0.495 R5C8A.C1 to R5C8A.F1 SLICE_91 +ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 +CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 +ROUTE 3 0.635 R5C9A.F0 to R5C9A.D1 C1Submitted_N_237 +CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_88 +ROUTE 1 0.653 R5C9A.F1 to R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 6.681 (43.8% logic, 56.2% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R5C8C.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R5C9D.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 1.784ns (weighted slack = -3.568ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i6 (from PHI2_c +) + Destination: FF Data in ADSubmitted_407 (to PHI2_c -) + + Delay: 6.546ns (37.2% logic, 62.8% route), 5 logic levels. + + Constraint Details: + + 6.546ns physical path delay SLICE_101 to SLICE_10 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.285ns LSR_SET requirement (totaling 4.762ns) by 1.784ns + + Physical Path Details: + + Data path SLICE_101 to SLICE_10: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R4C7C.CLK to R4C7C.Q0 SLICE_101 (from PHI2_c) +ROUTE 1 0.623 R4C7C.Q0 to R5C7A.D0 Bank_6 +CTOF_DEL --- 0.495 R5C7A.D0 to R5C7A.F0 SLICE_68 +ROUTE 1 0.626 R5C7A.F0 to R5C7D.D1 n2287 +CTOF_DEL --- 0.495 R5C7D.D1 to R5C7D.F1 SLICE_74 +ROUTE 8 0.693 R5C7D.F1 to R5C8A.D1 n26 +CTOF_DEL --- 0.495 R5C8A.D1 to R5C8A.F1 SLICE_91 +ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 +CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 +ROUTE 3 1.428 R5C9A.F0 to R3C8A.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 6.546 (37.2% logic, 62.8% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_101: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R4C7C.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_10: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R3C8A.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 1.784ns (weighted slack = -3.568ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i6 (from PHI2_c +) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 6.546ns (37.2% logic, 62.8% route), 5 logic levels. + + Constraint Details: + + 6.546ns physical path delay SLICE_101 to SLICE_15 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.285ns LSR_SET requirement (totaling 4.762ns) by 1.784ns + + Physical Path Details: + + Data path SLICE_101 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R4C7C.CLK to R4C7C.Q0 SLICE_101 (from PHI2_c) +ROUTE 1 0.623 R4C7C.Q0 to R5C7A.D0 Bank_6 +CTOF_DEL --- 0.495 R5C7A.D0 to R5C7A.F0 SLICE_68 +ROUTE 1 0.626 R5C7A.F0 to R5C7D.D1 n2287 +CTOF_DEL --- 0.495 R5C7D.D1 to R5C7D.F1 SLICE_74 +ROUTE 8 0.693 R5C7D.F1 to R5C8A.D1 n26 +CTOF_DEL --- 0.495 R5C8A.D1 to R5C8A.F1 SLICE_91 +ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 +CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 +ROUTE 3 1.428 R5C9A.F0 to R3C8B.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 6.546 (37.2% logic, 62.8% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_101: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R4C7C.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R3C8B.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + +Warning: 65.729MHz is the maximum frequency for this preference. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY NET "RCLK_c" 299.401000 MHz ; | 299.401 MHz| 160.205 MHz| 5 * + | | | +FREQUENCY NET "PHI2_c" 99.079000 MHz ; | 99.079 MHz| 65.729 MHz| 6 * + | | | +---------------------------------------------------------------------------- + + +2 preferences(marked by "*" above) not met. + +---------------------------------------------------------------------------- +Critical Nets | Loads| Errors| % of total +---------------------------------------------------------------------------- +n26 | 8| 63| 18.05% + | | | +n1996 | 1| 49| 14.04% + | | | +n1997 | 1| 46| 13.18% + | | | +n1995 | 1| 45| 12.89% + | | | +n1998 | 1| 38| 10.89% + | | | +n1994 | 1| 37| 10.60% + | | | +---------------------------------------------------------------------------- + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 + Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Setup): +--------------- + +Timing errors: 349 Score: 452301 +Cumulative negative slack: 370485 + +Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:36 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf +Design file: ram2gs_lcmxo2_640hc_impl1.ncd +Preference file: ram2gs_lcmxo2_640hc_impl1.prf +Device,speed: LCMXO2-640HC,m +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ; + 459 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.304ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i4 (from RCLK_c +) + Destination: FF Data in IS_FSM__i5 (to RCLK_c +) + + Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. + + Constraint Details: + + 0.285ns physical path delay SLICE_106 to SLICE_106 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.304ns + + Physical Path Details: + + Data path SLICE_106 to SLICE_106: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R3C8D.CLK to R3C8D.Q0 SLICE_106 (from RCLK_c) +ROUTE 1 0.152 R3C8D.Q0 to R3C8D.M1 n736 (to RCLK_c) + -------- + 0.285 (46.7% logic, 53.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_106: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R3C8D.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_106: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R3C8D.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.304ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CASr_382 (from RCLK_c +) + Destination: FF Data in CASr2_383 (to RCLK_c +) + + Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. + + Constraint Details: + + 0.285ns physical path delay SLICE_16 to SLICE_16 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.304ns + + Physical Path Details: + + Data path SLICE_16 to SLICE_16: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R4C9B.CLK to R4C9B.Q0 SLICE_16 (from RCLK_c) +ROUTE 1 0.152 R4C9B.Q0 to R4C9B.M1 CASr (to RCLK_c) + -------- + 0.285 (46.7% logic, 53.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_16: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R4C9B.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_16: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R4C9B.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.304ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i8 (from RCLK_c +) + Destination: FF Data in IS_FSM__i9 (to RCLK_c +) + + Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. + + Constraint Details: + + 0.285ns physical path delay SLICE_75 to SLICE_75 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.304ns + + Physical Path Details: + + Data path SLICE_75 to SLICE_75: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R3C9D.CLK to R3C9D.Q0 SLICE_75 (from RCLK_c) +ROUTE 1 0.152 R3C9D.Q0 to R3C9D.M1 n732 (to RCLK_c) + -------- + 0.285 (46.7% logic, 53.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_75: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R3C9D.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_75: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R3C9D.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.304ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i10 (from RCLK_c +) + Destination: FF Data in IS_FSM__i11 (to RCLK_c +) + + Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. + + Constraint Details: + + 0.285ns physical path delay SLICE_79 to SLICE_79 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.304ns + + Physical Path Details: + + Data path SLICE_79 to SLICE_79: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C8B.CLK to R5C8B.Q0 SLICE_79 (from RCLK_c) +ROUTE 1 0.152 R5C8B.Q0 to R5C8B.M1 n730 (to RCLK_c) + -------- + 0.285 (46.7% logic, 53.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_79: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R5C8B.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_79: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R5C8B.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.304ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i14 (from RCLK_c +) + Destination: FF Data in IS_FSM__i15 (to RCLK_c +) + + Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. + + Constraint Details: + + 0.285ns physical path delay SLICE_81 to SLICE_81 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.304ns + + Physical Path Details: + + Data path SLICE_81 to SLICE_81: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R6C9C.CLK to R6C9C.Q0 SLICE_81 (from RCLK_c) +ROUTE 1 0.152 R6C9C.Q0 to R6C9C.M1 n726 (to RCLK_c) + -------- + 0.285 (46.7% logic, 53.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_81: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R6C9C.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_81: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R6C9C.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.304ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i7 (from RCLK_c +) + Destination: FF Data in IS_FSM__i8 (to RCLK_c +) + + Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. + + Constraint Details: + + 0.285ns physical path delay SLICE_97 to SLICE_75 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.304ns + + Physical Path Details: + + Data path SLICE_97 to SLICE_75: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R3C9A.CLK to R3C9A.Q1 SLICE_97 (from RCLK_c) +ROUTE 1 0.152 R3C9A.Q1 to R3C9D.M0 n733 (to RCLK_c) + -------- + 0.285 (46.7% logic, 53.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_97: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R3C9A.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_75: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R3C9D.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.304ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i6 (from RCLK_c +) + Destination: FF Data in IS_FSM__i7 (to RCLK_c +) + + Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. + + Constraint Details: + + 0.285ns physical path delay SLICE_97 to SLICE_97 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.304ns + + Physical Path Details: + + Data path SLICE_97 to SLICE_97: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R3C9A.CLK to R3C9A.Q0 SLICE_97 (from RCLK_c) +ROUTE 1 0.152 R3C9A.Q0 to R3C9A.M1 n734 (to RCLK_c) + -------- + 0.285 (46.7% logic, 53.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_97: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R3C9A.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_97: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R3C9A.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.306ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RASr_379 (from RCLK_c +) + Destination: FF Data in RASr2_380 (to RCLK_c +) + + Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. + + Constraint Details: + + 0.287ns physical path delay SLICE_30 to SLICE_30 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.306ns + + Physical Path Details: + + Data path SLICE_30 to SLICE_30: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C10B.CLK to R5C10B.Q0 SLICE_30 (from RCLK_c) +ROUTE 2 0.154 R5C10B.Q0 to R5C10B.M1 RASr (to RCLK_c) + -------- + 0.287 (46.3% logic, 53.7% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_30: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R5C10B.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_30: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R5C10B.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.306ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q PHI2r2_377 (from RCLK_c +) + Destination: FF Data in PHI2r3_378 (to RCLK_c +) + + Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. + + Constraint Details: + + 0.287ns physical path delay SLICE_36 to SLICE_69 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.306ns + + Physical Path Details: + + Data path SLICE_36 to SLICE_69: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R4C10A.CLK to R4C10A.Q1 SLICE_36 (from RCLK_c) +ROUTE 3 0.154 R4C10A.Q1 to R4C10C.M1 PHI2r2 (to RCLK_c) + -------- + 0.287 (46.3% logic, 53.7% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_36: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R4C10A.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_69: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R4C10C.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.307ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i0 (from RCLK_c +) + Destination: FF Data in IS_FSM__i1 (to RCLK_c +) + + Delay: 0.288ns (46.2% logic, 53.8% route), 1 logic levels. + + Constraint Details: + + 0.288ns physical path delay SLICE_98 to SLICE_98 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.307ns + + Physical Path Details: + + Data path SLICE_98 to SLICE_98: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R6C11A.CLK to R6C11A.Q0 SLICE_98 (from RCLK_c) +ROUTE 4 0.155 R6C11A.Q0 to R6C11A.M1 nRCS_N_139 (to RCLK_c) + -------- + 0.288 (46.2% logic, 53.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_98: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R6C11A.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_98: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R6C11A.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +================================================================================ +Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ; + 113 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted_406 (from PHI2_c -) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_15 to SLICE_15 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_15 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R3C8B.CLK to R3C8B.Q0 SLICE_15 (from PHI2_c) +ROUTE 2 0.132 R3C8B.Q0 to R3C8B.A0 C1Submitted +CTOF_DEL --- 0.101 R3C8B.A0 to R3C8B.F0 SLICE_15 +ROUTE 1 0.000 R3C8B.F0 to R3C8B.DI0 n1398 (to PHI2_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R3C8B.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R3C8B.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.851ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in XOR8MEG_408 (to PHI2_c -) + + Delay: 0.823ns (28.4% logic, 71.6% route), 2 logic levels. + + Constraint Details: + + 0.823ns physical path delay SLICE_19 to SLICE_50 meets + -0.028ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.028ns) by 0.851ns + + Physical Path Details: + + Data path SLICE_19 to SLICE_50: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C9D.CLK to R5C9D.Q0 SLICE_19 (from PHI2_c) +ROUTE 2 0.332 R5C9D.Q0 to R5C6B.D1 CmdEnable +CTOF_DEL --- 0.101 R5C6B.D1 to R5C6B.F1 SLICE_83 +ROUTE 1 0.257 R5C6B.F1 to R4C6A.CE PHI2_N_120_enable_3 (to PHI2_c) + -------- + 0.823 (28.4% logic, 71.6% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R5C9D.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_50: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R4C6A.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.906ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q ADSubmitted_407 (from PHI2_c -) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 0.878ns (26.7% logic, 73.3% route), 2 logic levels. + + Constraint Details: + + 0.878ns physical path delay SLICE_10 to SLICE_19 meets + -0.028ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.028ns) by 0.906ns + + Physical Path Details: + + Data path SLICE_10 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R3C8A.CLK to R3C8A.Q0 SLICE_10 (from PHI2_c) +ROUTE 1 0.501 R3C8A.Q0 to R5C9A.B1 ADSubmitted +CTOF_DEL --- 0.101 R5C9A.B1 to R5C9A.F1 SLICE_88 +ROUTE 1 0.143 R5C9A.F1 to R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 0.878 (26.7% logic, 73.3% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_10: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R3C8A.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R5C9D.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.937ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted_406 (from PHI2_c -) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 0.909ns (48.0% logic, 52.0% route), 4 logic levels. + + Constraint Details: + + 0.909ns physical path delay SLICE_15 to SLICE_19 meets + -0.028ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.028ns) by 0.937ns + + Physical Path Details: + + Data path SLICE_15 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R3C8B.CLK to R3C8B.Q0 SLICE_15 (from PHI2_c) +ROUTE 2 0.136 R3C8B.Q0 to R3C9B.D1 C1Submitted +CTOF_DEL --- 0.101 R3C9B.D1 to R3C9B.F1 SLICE_77 +ROUTE 1 0.056 R3C9B.F1 to R3C9A.C1 n2210 +CTOF_DEL --- 0.101 R3C9A.C1 to R3C9A.F1 SLICE_97 +ROUTE 1 0.138 R3C9A.F1 to R5C9A.C1 n7_adj_5 +CTOF_DEL --- 0.101 R5C9A.C1 to R5C9A.F1 SLICE_88 +ROUTE 1 0.143 R5C9A.F1 to R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 0.909 (48.0% logic, 52.0% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R3C8B.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R5C9D.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.059ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in CmdUFMCS_412 (to PHI2_c -) + FF CmdUFMCLK_413 + + Delay: 1.031ns (32.5% logic, 67.5% route), 3 logic levels. + + Constraint Details: + + 1.031ns physical path delay SLICE_19 to SLICE_100 meets + -0.028ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.028ns) by 1.059ns + + Physical Path Details: + + Data path SLICE_19 to SLICE_100: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C9D.CLK to R5C9D.Q0 SLICE_19 (from PHI2_c) +ROUTE 2 0.224 R5C9D.Q0 to R5C6D.C0 CmdEnable +CTOF_DEL --- 0.101 R5C6D.C0 to R5C6D.F0 SLICE_73 +ROUTE 2 0.212 R5C6D.F0 to R5C6D.A1 n2204 +CTOF_DEL --- 0.101 R5C6D.A1 to R5C6D.F1 SLICE_73 +ROUTE 2 0.260 R5C6D.F1 to R5C7B.CE PHI2_N_120_enable_8 (to PHI2_c) + -------- + 1.031 (32.5% logic, 67.5% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R5C9D.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_100: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R5C7B.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.059ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in CmdUFMSDI_414 (to PHI2_c -) + + Delay: 1.031ns (32.5% logic, 67.5% route), 3 logic levels. + + Constraint Details: + + 1.031ns physical path delay SLICE_19 to SLICE_99 meets + -0.028ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.028ns) by 1.059ns + + Physical Path Details: + + Data path SLICE_19 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C9D.CLK to R5C9D.Q0 SLICE_19 (from PHI2_c) +ROUTE 2 0.224 R5C9D.Q0 to R5C6D.C0 CmdEnable +CTOF_DEL --- 0.101 R5C6D.C0 to R5C6D.F0 SLICE_73 +ROUTE 2 0.212 R5C6D.F0 to R5C6D.A1 n2204 +CTOF_DEL --- 0.101 R5C6D.A1 to R5C6D.F1 SLICE_73 +ROUTE 2 0.260 R5C6D.F1 to R5C8D.CE PHI2_N_120_enable_8 (to PHI2_c) + -------- + 1.031 (32.5% logic, 67.5% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R5C9D.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R5C8D.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.106ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in CmdSubmitted_411 (to PHI2_c -) + + Delay: 1.078ns (40.4% logic, 59.6% route), 4 logic levels. + + Constraint Details: + + 1.078ns physical path delay SLICE_19 to SLICE_20 meets + -0.028ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.028ns) by 1.106ns + + Physical Path Details: + + Data path SLICE_19 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C9D.CLK to R5C9D.Q0 SLICE_19 (from PHI2_c) +ROUTE 2 0.224 R5C9D.Q0 to R5C6D.C0 CmdEnable +CTOF_DEL --- 0.101 R5C6D.C0 to R5C6D.F0 SLICE_73 +ROUTE 2 0.137 R5C6D.F0 to R5C7D.D0 n2204 +CTOF_DEL --- 0.101 R5C7D.D0 to R5C7D.F0 SLICE_74 +ROUTE 2 0.138 R5C7D.F0 to R3C7C.D1 n2220 +CTOF_DEL --- 0.101 R3C7C.D1 to R3C7C.F1 SLICE_89 +ROUTE 1 0.143 R3C7C.F1 to R3C7D.CE PHI2_N_120_enable_7 (to PHI2_c) + -------- + 1.078 (40.4% logic, 59.6% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R5C9D.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R3C7D.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.106ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in Cmdn8MEGEN_410 (to PHI2_c -) + + Delay: 1.078ns (40.4% logic, 59.6% route), 4 logic levels. + + Constraint Details: + + 1.078ns physical path delay SLICE_19 to SLICE_24 meets + -0.028ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.028ns) by 1.106ns + + Physical Path Details: + + Data path SLICE_19 to SLICE_24: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C9D.CLK to R5C9D.Q0 SLICE_19 (from PHI2_c) +ROUTE 2 0.224 R5C9D.Q0 to R5C6D.C0 CmdEnable +CTOF_DEL --- 0.101 R5C6D.C0 to R5C6D.F0 SLICE_73 +ROUTE 2 0.137 R5C6D.F0 to R5C7D.D0 n2204 +CTOF_DEL --- 0.101 R5C7D.D0 to R5C7D.F0 SLICE_74 +ROUTE 2 0.138 R5C7D.F0 to R3C7C.D0 n2220 +CTOF_DEL --- 0.101 R3C7C.D0 to R3C7C.F0 SLICE_89 +ROUTE 1 0.143 R3C7C.F0 to R3C7B.CE PHI2_N_120_enable_6 (to PHI2_c) + -------- + 1.078 (40.4% logic, 59.6% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R5C9D.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_24: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R3C7B.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 5.504ns (weighted slack = 11.008ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q XOR8MEG_408 (from PHI2_c -) + Destination: FF Data in RA11_385 (to PHI2_c +) + + Delay: 0.444ns (52.7% logic, 47.3% route), 2 logic levels. + + Constraint Details: + + 0.444ns physical path delay SLICE_50 to SLICE_33 meets + -0.013ns DIN_HLD and + -5.047ns delay constraint less + 0.000ns skew requirement (totaling -5.060ns) by 5.504ns + + Physical Path Details: + + Data path SLICE_50 to SLICE_33: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R4C6A.CLK to R4C6A.Q0 SLICE_50 (from PHI2_c) +ROUTE 1 0.210 R4C6A.Q0 to R4C6C.A0 XOR8MEG +CTOF_DEL --- 0.101 R4C6C.A0 to R4C6C.F0 SLICE_33 +ROUTE 1 0.000 R4C6C.F0 to R4C6C.DI0 RA11_N_184 (to PHI2_c) + -------- + 0.444 (52.7% logic, 47.3% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_50: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R4C6A.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_33: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R4C6C.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 5.899ns (weighted slack = 11.798ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i1 (from PHI2_c +) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 0.839ns (52.0% logic, 48.0% route), 4 logic levels. + + Constraint Details: + + 0.839ns physical path delay SLICE_93 to SLICE_15 meets + -0.013ns DIN_HLD and + -5.047ns delay constraint less + 0.000ns skew requirement (totaling -5.060ns) by 5.899ns + + Physical Path Details: + + Data path SLICE_93 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C8C.CLK to R5C8C.Q1 SLICE_93 (from PHI2_c) +ROUTE 1 0.133 R5C8C.Q1 to R5C8D.D1 Bank_1 +CTOF_DEL --- 0.101 R5C8D.D1 to R5C8D.F1 SLICE_99 +ROUTE 2 0.214 R5C8D.F1 to R3C8B.A1 n22 +CTOF_DEL --- 0.101 R3C8B.A1 to R3C8B.F1 SLICE_15 +ROUTE 1 0.056 R3C8B.F1 to R3C8B.C0 n2365 +CTOF_DEL --- 0.101 R3C8B.C0 to R3C8B.F0 SLICE_15 +ROUTE 1 0.000 R3C8B.F0 to R3C8B.DI0 n1398 (to PHI2_c) + -------- + 0.839 (52.0% logic, 48.0% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R5C8C.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R3C8B.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference(MIN Delays) | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY NET "RCLK_c" 299.401000 MHz ; | 0.000 ns| 0.304 ns| 1 + | | | +FREQUENCY NET "PHI2_c" 99.079000 MHz ; | 0.000 ns| 0.379 ns| 2 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 + Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 349 (setup), 0 (hold) +Score: 452301 (setup), 0 (hold) +Cumulative negative slack: 370485 (370485+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_bgn.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_bgn.html new file mode 100644 index 0000000..7144090 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_bgn.html @@ -0,0 +1,152 @@ + +Bitgen Report + + +

    BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 15 05:00:22 2023
+
+
+Command: bitgen -g RamCfg:Reset -path D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+
+Loading design for application Bitgen from file RAM2GS_LCMXO2_640HC_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from RAM2GS_LCMXO2_640HC_impl1.prf.
+
+
+Preference Summary:
+
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                         RamCfg  |                        Reset**  |
++---------------------------------+---------------------------------+
+|                     MCCLK_FREQ  |                         2.08**  |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                      JTAG_PORT  |                       ENABLE**  |
++---------------------------------+---------------------------------+
+|                       SDM_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                 SLAVE_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                MASTER_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                       I2C_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|        MUX_CONFIGURATION_PORTS  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  CONFIGURATION  |                          CFG**  |
++---------------------------------+---------------------------------+
+|                COMPRESS_CONFIG  |                           ON**  |
++---------------------------------+---------------------------------+
+|                        MY_ASSP  |                          OFF**  |
++---------------------------------+---------------------------------+
+|               ONE_TIME_PROGRAM  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                 ENABLE_TRANSFR  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  SHAREDEBRINIT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|            BACKGROUND_RECONFIG  |                          OFF**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+ 
+Bitstream Status: Final           Version 1.95.
+ 
+Saving bit stream in "RAM2GS_LCMXO2_640HC_impl1.jed".
+ 
+===========
+UFM Summary.
+===========
+UFM Size:        191 Pages (128*191 Bits).
+UFM Utilization: General Purpose Flash Memory.
+ 
+Available General Purpose Flash Memory:  191 Pages (Page 0 to Page 190).
+Initialized UFM Pages:                     0 Page.
+ 
+Total CPU Time: 1 secs 
+Total REAL Time: 2 secs 
+Peak Memory Usage: 245 MB
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_iotiming.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_iotiming.html new file mode 100644 index 0000000..85916f1 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_iotiming.html @@ -0,0 +1,204 @@ + +I/O Timing Report + + +
    I/O Timing Report
+Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 5
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 6
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: M
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+// Design: RAM2GS
+// Package: TQFP100
+// ncd File: ram2gs_lcmxo2_640hc_impl1.ncd
+// Version: Diamond (64-bit) 3.12.1.454
+// Written on Tue Aug 15 05:03:37 2023
+// M: Minimum Performance Grade
+// iotiming RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
+
+I/O Timing Report (All units are in ns)
+
+Worst Case Results across Performance Grades (M, 6, 5, 4):
+
+// Input Setup and Hold Times
+
+Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
+----------------------------------------------------------------------
+CROW[0] nCRAS F     0.993      4       0.541     4
+CROW[1] nCRAS F     0.293      4       1.148     4
+Din[0]  PHI2  F     4.804      4       1.483     4
+Din[0]  nCCAS F     1.539      4      -0.150     M
+Din[1]  PHI2  F     4.733      4       0.702     4
+Din[1]  nCCAS F     1.638      4      -0.177     M
+Din[2]  PHI2  F     4.046      4       1.702     4
+Din[2]  nCCAS F     1.651      4      -0.121     M
+Din[3]  PHI2  F     4.770      4       1.575     4
+Din[3]  nCCAS F     1.973      4      -0.207     M
+Din[4]  PHI2  F     5.656      4       0.720     4
+Din[4]  nCCAS F     1.606      4      -0.156     M
+Din[5]  PHI2  F     4.165      4       1.131     4
+Din[5]  nCCAS F     0.618      4       0.435     4
+Din[6]  PHI2  F     5.309      4       1.478     4
+Din[6]  nCCAS F     1.331      4      -0.053     M
+Din[7]  PHI2  F     5.874      4       1.774     4
+Din[7]  nCCAS F     2.023      4      -0.205     M
+MAin[0] PHI2  F     5.149      4       0.137     M
+MAin[0] nCRAS F    -0.022      M       1.415     4
+MAin[1] PHI2  F     4.216      4       1.539     4
+MAin[1] nCRAS F     1.716      4      -0.018     M
+MAin[2] PHI2  F     3.754      4       0.553     4
+MAin[2] nCRAS F    -0.164      M       1.715     4
+MAin[3] PHI2  F     5.957      4      -0.100     M
+MAin[3] nCRAS F     0.033      4       1.356     4
+MAin[4] PHI2  F     5.652      4      -0.180     M
+MAin[4] nCRAS F    -0.173      M       1.726     4
+MAin[5] PHI2  F     4.938      4       0.693     6
+MAin[5] nCRAS F     0.005      4       1.395     4
+MAin[6] PHI2  F     5.535      4      -0.147     M
+MAin[6] nCRAS F     0.012      4       1.387     4
+MAin[7] PHI2  F     5.951      4      -0.083     M
+MAin[7] nCRAS F     0.858      4       0.664     4
+MAin[8] nCRAS F     0.526      4       0.915     4
+MAin[9] nCRAS F     0.038      4       1.342     4
+PHI2    RCLK  R     2.772      4      -0.342     M
+UFMSDO  RCLK  R     0.780      4       0.632     4
+nCCAS   RCLK  R     0.557      4       0.872     4
+nCCAS   nCRAS F     2.108      4      -0.053     M
+nCRAS   RCLK  R     2.536      4      -0.169     M
+nFWE    PHI2  F     5.830      4       0.629     4
+nFWE    nCRAS F     1.386      4       0.176     4
+
+
+// Clock to Output Delay
+
+Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
+------------------------------------------------------------------------
+LED    RCLK  R    11.611         4        3.288          M
+LED    nCRAS F    12.009         4        3.367          M
+RA[0]  RCLK  R    12.268         4        3.492          M
+RA[0]  nCRAS F    11.741         4        3.284          M
+RA[10] RCLK  R    10.004         4        2.964          M
+RA[11] PHI2  R    10.669         4        3.160          M
+RA[1]  RCLK  R    12.975         4        3.665          M
+RA[1]  nCRAS F    11.918         4        3.321          M
+RA[2]  RCLK  R    12.531         4        3.533          M
+RA[2]  nCRAS F    11.755         4        3.277          M
+RA[3]  RCLK  R    11.851         4        3.375          M
+RA[3]  nCRAS F    12.624         4        3.513          M
+RA[4]  RCLK  R    13.380         4        3.775          M
+RA[4]  nCRAS F    12.857         4        3.569          M
+RA[5]  RCLK  R    12.767         4        3.632          M
+RA[5]  nCRAS F    12.469         4        3.456          M
+RA[6]  RCLK  R    12.163         4        3.468          M
+RA[6]  nCRAS F    12.141         4        3.394          M
+RA[7]  RCLK  R    11.990         4        3.375          M
+RA[7]  nCRAS F    12.172         4        3.381          M
+RA[8]  RCLK  R    11.712         4        3.314          M
+RA[8]  nCRAS F    12.431         4        3.457          M
+RA[9]  RCLK  R    11.412         4        3.233          M
+RA[9]  nCRAS F    12.128         4        3.377          M
+RBA[0] nCRAS F    10.844         4        3.124          M
+RBA[1] nCRAS F    10.216         4        2.967          M
+RCKE   RCLK  R    10.964         4        3.209          M
+RDQMH  RCLK  R    12.109         4        3.426          M
+RDQML  RCLK  R    10.974         4        3.140          M
+RD[0]  nCCAS F     8.747         4        2.603          M
+RD[1]  nCCAS F     8.747         4        2.603          M
+RD[2]  nCCAS F     8.737         4        2.605          M
+RD[3]  nCCAS F     9.239         4        2.740          M
+RD[4]  nCCAS F     9.283         4        2.726          M
+RD[5]  nCCAS F     9.355         4        2.761          M
+RD[6]  nCCAS F     9.106         4        2.681          M
+RD[7]  nCCAS F     9.181         4        2.711          M
+UFMCLK RCLK  R    10.078         4        3.002          M
+UFMSDI RCLK  R    10.108         4        2.996          M
+nRCAS  RCLK  R    10.525         4        3.100          M
+nRCS   RCLK  R    10.119         4        2.984          M
+nRRAS  RCLK  R    10.200         4        3.024          M
+nRWE   RCLK  R     9.984         4        2.972          M
+nUFMCS RCLK  R    10.165         4        3.020          M
+WARNING: you must also run trce with hold speed: 4
+WARNING: you must also run trce with hold speed: 6
+WARNING: you must also run trce with setup speed: M
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_lattice.synproj b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_lattice.synproj new file mode 100644 index 0000000..c4e5990 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_lattice.synproj @@ -0,0 +1,41 @@ +-a "MachXO2" +-d LCMXO2-640HC +-t TQFP100 +-s 4 +-frequency 200 +-optimization_goal Balanced +-bram_utilization 100 +-ramstyle Auto +-romstyle auto +-dsp_utilization 100 +-use_dsp 1 +-use_carry_chain 1 +-carry_chain_length 0 +-force_gsr Auto +-resource_sharing 1 +-propagate_constants 1 +-remove_duplicate_regs 1 +-mux_style Auto +-max_fanout 1000 +-fsm_encoding_style Auto +-twr_paths 3 +-fix_gated_clocks 1 +-loop_limit 1950 + + + +-use_io_insertion 1 +-resolve_mixed_drivers 0 +-use_io_reg auto + + +-lpf 1 +-p "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC" +-ver "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v" +-top RAM2GS + + +-p "C:/lscc/diamond/3.12/ispfpga/xo2c00/data" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC" + +-ngd "RAM2GS_LCMXO2_640HC_impl1.ngd" + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.asd b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.asd new file mode 100644 index 0000000..bcf1f47 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.asd @@ -0,0 +1,15 @@ +[ActiveSupport MAP] +Device = LCMXO2-640HC; +Package = TQFP100; +Performance = 4; +LUTS_avail = 640; +LUTS_used = 143; +FF_avail = 719; +FF_used = 102; +INPUT_LVCMOS25 = 26; +OUTPUT_LVCMOS25 = 33; +BIDI_LVCMOS25 = 8; +IO_avail = 79; +IO_used = 67; +EBR_avail = 2; +EBR_used = 0; diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.cam b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.cam new file mode 100644 index 0000000..5798330 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.cam @@ -0,0 +1,88 @@ +[ START MERGED ] +n2380 Ready +PHI2_N_120 PHI2_c +nRWE_N_176 nRWE_N_177 +n1407 nRowColSel_N_34 +n1408 nRowColSel_N_35 +[ END MERGED ] +[ START CLIPPED ] +GND_net +VCC_net +FS_610_add_4_19/S1 +FS_610_add_4_19/CO +FS_610_add_4_1/S0 +FS_610_add_4_1/CI +[ END CLIPPED ] +[ START DESIGN PREFS ] +SCHEMATIC START ; +# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:03:24 2023 + +SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ; +LOCATE COMP "RD[7]" SITE "43" ; +LOCATE COMP "RD[6]" SITE "42" ; +LOCATE COMP "RD[5]" SITE "41" ; +LOCATE COMP "RD[4]" SITE "40" ; +LOCATE COMP "RD[3]" SITE "39" ; +LOCATE COMP "RD[2]" SITE "38" ; +LOCATE COMP "RD[1]" SITE "37" ; +LOCATE COMP "RD[0]" SITE "36" ; +LOCATE COMP "Dout[7]" SITE "82" ; +LOCATE COMP "Dout[6]" SITE "78" ; +LOCATE COMP "Dout[5]" SITE "84" ; +LOCATE COMP "Dout[4]" SITE "83" ; +LOCATE COMP "Dout[3]" SITE "85" ; +LOCATE COMP "Dout[2]" SITE "87" ; +LOCATE COMP "Dout[1]" SITE "86" ; +LOCATE COMP "Dout[0]" SITE "76" ; +LOCATE COMP "LED" SITE "34" ; +LOCATE COMP "RBA[1]" SITE "60" ; +LOCATE COMP "RBA[0]" SITE "58" ; +LOCATE COMP "RA[11]" SITE "59" ; +LOCATE COMP "RA[10]" SITE "64" ; +LOCATE COMP "RA[9]" SITE "63" ; +LOCATE COMP "RA[8]" SITE "65" ; +LOCATE COMP "RA[7]" SITE "75" ; +LOCATE COMP "RA[6]" SITE "68" ; +LOCATE COMP "RA[5]" SITE "70" ; +LOCATE COMP "RA[4]" SITE "74" ; +LOCATE COMP "RA[3]" SITE "71" ; +LOCATE COMP "RA[2]" SITE "69" ; +LOCATE COMP "RA[1]" SITE "67" ; +LOCATE COMP "RA[0]" SITE "66" ; +LOCATE COMP "nRCS" SITE "57" ; +LOCATE COMP "RCKE" SITE "53" ; +LOCATE COMP "nRWE" SITE "49" ; +LOCATE COMP "nRRAS" SITE "54" ; +LOCATE COMP "nRCAS" SITE "52" ; +LOCATE COMP "RDQMH" SITE "51" ; +LOCATE COMP "RDQML" SITE "48" ; +LOCATE COMP "UFMCLK" SITE "29" ; +LOCATE COMP "UFMSDI" SITE "30" ; +LOCATE COMP "PHI2" SITE "8" ; +LOCATE COMP "MAin[9]" SITE "32" ; +LOCATE COMP "MAin[8]" SITE "25" ; +LOCATE COMP "MAin[7]" SITE "18" ; +LOCATE COMP "MAin[6]" SITE "24" ; +LOCATE COMP "MAin[5]" SITE "19" ; +LOCATE COMP "MAin[4]" SITE "20" ; +LOCATE COMP "MAin[3]" SITE "21" ; +LOCATE COMP "MAin[2]" SITE "13" ; +LOCATE COMP "MAin[1]" SITE "12" ; +LOCATE COMP "MAin[0]" SITE "14" ; +LOCATE COMP "CROW[1]" SITE "16" ; +LOCATE COMP "CROW[0]" SITE "10" ; +LOCATE COMP "Din[7]" SITE "1" ; +LOCATE COMP "Din[6]" SITE "2" ; +LOCATE COMP "Din[5]" SITE "98" ; +LOCATE COMP "Din[4]" SITE "99" ; +LOCATE COMP "Din[3]" SITE "97" ; +LOCATE COMP "Din[2]" SITE "88" ; +LOCATE COMP "Din[1]" SITE "96" ; +LOCATE COMP "Din[0]" SITE "3" ; +LOCATE COMP "nCCAS" SITE "9" ; +LOCATE COMP "nCRAS" SITE "17" ; +LOCATE COMP "nFWE" SITE "28" ; +LOCATE COMP "RCLK" SITE "62" ; +LOCATE COMP "UFMSDO" SITE "27" ; +SCHEMATIC END ; +[ END DESIGN PREFS ] diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.hrr b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.hrr new file mode 100644 index 0000000..a9cd083 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.hrr @@ -0,0 +1,10 @@ +--------------------------------------------------- +Report for cell RAM2GS + Instance path: RAM2GS + Cell usage: + cell count Res Usage(%) + SLIC 75.00 100.0 + LUT4 123.00 100.0 + IOBUF 67 100.0 + PFUREG 102 100.0 + RIPPLE 10 100.0 diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.ncd b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.ncd new file mode 100644 index 0000000000000000000000000000000000000000..3b0a349a8f4a8a9d395c9d3450b234324d65587a GIT binary patch literal 137575 zcmeHQ1$Z1svfedHwqu7J2QLa60!z|La-2kHE0!#KB}3>GCw3Agj+{#zI>_mmnVFfH zncn3v$B<)w$IMT!s(QNq>7E|j=SZvQJo;R+rlz~PySo0WrkPo`?03J*m+t;xZgy^V ztz)3Hb||;w+vi`J&*g91UAnSR$n|#(Y#S_{)lw;}>&gvp>fKl*W+g{INAa)y{`obP zkjpLT8|>UX)YrYOy_l!VMqw@lv%uV(&y}=!pIZv1Ei-q%pSHr>c|Nz9xpRGP3v=iA z+$wWPN%T8b-&W?%^0{ryHT6Y}R~8&Q%5`;90`gZ)O7q``h8 zO44Az5hZD`uk?~M*mMw@7SwrJxW0h0RLt+;vQ%uLr<}4>Y=O^}iusmPmWui6ElW=r zMWVVvW2i_^_}Z;VPx#ucNKg3Mtw@7??N+2TU%M4)u&8MH=i|Lq!^#sIN5G z)E5m7+Ih1y*l$F$G}v!MvozRmM02o*n`1qUD#SnqW(-qc#vlb|gs8cSz6~7%J&_L? z=olSa-qv1NK~T=+7Kt-4x21)R>G!3rja{|Dt;>s{{L<>Z+?Vz@bW`!wPe?Z$gGcJID+A>`opF%qw~f`*D09eUjmvCE zy=|-}^|rB^)Z4~toZGQ>n{G*Mw{ftkRWqJ8{kGU-`fUS6r)n{iG)_1@_uiFi+;Vzu zQR@6!chK66pH96iDs}G0G-?bvRinm(JDFo`Hl957uIMxMuBbEhuJp8XH&$tbF1OOL z+Xh^zw+*&ZZ;QG-kA7(XP|rx$#-Wjcj*TO|ef>Q=`a0~k+in}#b<@s~n?|o58@Xz9 z*G`EJM-1Mu^TzFaM#rvh>e@ZFV|35x?lDfjplfhopr_W=*U>NO8aMWB5Lak|S< zC6_OuV-eT$5(+(+EpIc?XMxREl#HKkZ!{L7XQAO7w$Lv_oXLszvADQuEhPae_#3%_e=hL=}g>@6rid%?T3n6 zz5FH&A-}I56NeVD9}g?Y1fp01UqfbW9ZTS=$PBY%349%y5qB(suOu`0jwSH5WX9pK z1iqb^A$cr8LJy+nxno^j9Yd}Wivh)K)VH9r7%}CnMLE@a%VNEA#(KB*h)CR!UYp(D z)9vw%u~O6vTe}H+3-!L=2s1-iRHN($ExsB|{E7RbQr!1#%}hFQ-#0Zg{lI)iUa2*%}(iI&JCD4#dBxp%;CZHwSz9^diX+aem` zTSMJ_UQtqib8Ap;Y0E@Ov6e-hs`o`#vHMZ4>U~jJ?0(d(e1G_&jXmw6m|1-rv{d1W zQY@F-ZMaTiuv1ct{*ppOc}cb?F3A?9CE22|BwMtVWQ&rLY|)Knt46}rHeuK%*0!7I zJ9}{Ru=c2^$^_j2Us@mFOY;MKX@7t(3JCB;0|CCMAixjnAlyeLP$qO>qGXb7Vq`)! zW@ebIiiwQ@eu@fAC=8@eQGtnkf%KvR<*OZp4bsFnO|6DtCUyaSiWZ_}w1jp{{0hiP z(SnIrf%FCno$xebmnJ^VO0bO?L~K<-7ES_?&ZyaSwm;w~>I^!-E?q=!a$HZ{S} zVGa?ma?T@~Pt-uvNVI@xA<-hDLx>g=Eg?FT=rE$giH;yTl4vOr@7*jTI-2MhqGO4U zBRZbw1fu&8ok-L~bQ00YM5hp)N^~00=|pD`Ehkz*w36s7qO*xu5e1?mQHiKb#2ZG< zM6E<^MD0YYiOwZjLv$X|`9v2Gbr5wDbrE$F^$_(EttDDV)JJq7(R!i{M1w>di8c|{ zh=z!Ui8d2$A=*l`jp!nxi-|5Fx|HZLqWcn!5M55Ro#+apD~Wax?IgO2=xU;Ch(?L7 zCAyAi7t!@ZV??`&xS#GvbR*GCM0<#CCc1^_RwC}$+ld}P^gyBq5#2%bV4`uNhY&rK z=wU<;Cwc_YBZ(eG^k|~T5IvUYaYT$cy_M)~L~kd02hlr;-bM6oqW2KJm*{;&?MD$^zj}U#7=wn15 zC;9}@Cy72q^gl$OCc2a8Gen;y`W(^ciM~MeMWVZizC`q8qOTBrmFR0kUnlwo(Km^{ zMf7c=yNSL-^j)Iw5q+QN2Sh(4`VrBOiGD)#Q=*>{{ha6*ME^_lOQK&9{hH`EM875a z9ntTJ{y_9cqCXM+ndmP>eLc&47~Gs`hOPDY@#_tbBX2= z%_nLgY9v}fw2){K(IG^OiIxx@N^}^};Y3Fe9Z9s5=qRFPL`M@HLv$?BaYV-xoj`OS zq7#Xlh)yCpndlUvQ;AL^I-TeYqUA&@h*lD)KbTQE-M3)j>Ms#1I5u(e9wi8`JbS2RaqMbxn5nWAm z4bdpkwM5qu?IOCKXpCq#(G5iRBf633CZat=Hxu1LbZd_Ma_`VcOR+FAGFl|{7`*fU z@f)PG*o`Goj_o^kj8sO7q|DgOm^jjU_y%=F?1m@Kt;7PY9raZ#6Zq7BG5%twZq%=_ zd&uKf8GN#dSbA4hTKR4(A$_iPa$WhTCag)!ce79xal^?z(x;$o3uAj(F7=r7nl8)}7o3FTjbkClhWby@9=(5pbk?>QJylE1SB6LMbZrpjpNU_D#!!4z&7%#_QpN}U;3I(Mn(j26eFREnPElR}E35bltYZwyvjqBE}WxYU|{HPEUutKGHw z`CXm0k#d_`hN?-}B7habJ!{n@dKERXRatJ!I9_C^B1P6MdI+kE~%!~ZRe4s%Xn7=5TxeE z+Ag~$OM918lM0>OqMvd8#Xn1kTcpl!u9!+PZ=8Se4=&pv z+{k}4+(j|6m_T+EEpE6qkYu41R4KY897Bub9YbW1q`7A5#}sdRs7+Q0d96lsx7_B+ zKAacejp#~i$V{XAWisrPavLN`xy|jlBZa$Rq*$&R@rgcPOo0#m;3AW1ONb{^b~})2 zyR|1$L~}@mgp6v{0F=#YoPY5T)sZrm+gz_gon0x1I(xxrwY4Q6X7N~U_pM#KcMa{_ zMRwp;S%kF(GA&V;!I7fmhR24Xk=~(!kx>^wZWb?q*etFfHe5oA_$F@gIRE0G20}`J z8>e?S`jSMg85#VT(_ZFC) z6vDS#wb`R(H{ji$+COJ)$1u&Ca<`AuFZpS(QG>6>g+;&EAscgqQ5IeGuqulhhzH5@Tr1vl6txIN?ii+`3l81wwff<9veBcpDgfbYTu zAxnH%2!LLaP~eMd?-m&`-SQf2<+&x}{EL6wCY9VCVsk1*171!%&cFCa-BG1wXi!rgOH{32hnnq5A=9t7{HDHdc zA2ULcLS3&c`U&TXL%QU4M69Z=UB_;?NCbM>=ecTY7!3{jBMWflM@&~X5Bg#-k^z9* z$|aNnSS-0(Bo#DQLlKg58M&f3*Fb>@*Wkc+8|el&H;U23t*s?;)$x|FosRP_{&A;_ zZebA#^S0KyM@HQe4bRmfySt<-X3w7Fn*6S18J=rcuJbBI*yZMp^Dq86 z)_U1^znLK@-yY{*{A0wsxHddjZ|U;(RyCT^i=lE!CW`11basI_W3%Rt&|M2xV|Kgwdo!iH*ON2ke zbQS44g=C$VjaI9Uj|+u~#nv}TpSoVq^D1uVh6VxN+#Z8E@h`4DlUHhM4h=bJU=ZqU z_#GE3;JfmVPV_`5HgkBOC8DH9fLOQL;Je+CEG{&;Xc!HR{CN3CCvYxmlVYm@B(N^4 zp-E#TnNHf!(9yNjMW#@i3st=EpDeQ_P-Ze!$bCfi>~>ki+*f~vTz<0DD1brKQN)xGPF>?E3NKF+`RM+`GGv5Op>r%^L%b~VaD zGwBroN?FEp5zmHHj#gN?7UTSje~^ozTy~oSOt=~c-&Oh&K8ibX!}c8`)sc~^XP0!G z?2;;N%ft)U^evp;Eripzq@{1>^lsstzBw&@h10vL<@A-b^kq)(YMs-U)6$nXy*sqw z^rf`)MNaQ_5vMPvrKioMsyFK9^aVHl0@bHm_4($AbXsCpFD9|4c}RAZZW4QHM`E`} zO=3^yNbK64N$e>ci9Ik%13hgcvFp)|WKY#d?1lxC*wgcTS|VmMcZ^w%M8~bWk%yNI z2DkWmas=A#3r*@4E=j$zX%K9L`cnDev@bPE>Pw}ho>W@!6{)^Sc3jft%Crf6Tkp7} zHJs43#JP0(+H(R{qHBem(6d3C(6vBL=-Ho5=vp5q^lZ;2bS;k)dUj_Mx>m;tJ)5%$ z-Ok~JUf_PR16#dkxq^r$J0gYmVUyyvYbf? z5kjK%*g#4?a_pp(v&ISJkSF6K$cdEw;gr0rkJ9Z5nqRy0h5f^9kneQVFiCwIj#2(s^*u|Sk>>&<`UCf!p9_o~`QhdHTzht4ZDNlcZknX;QcIB&pYTn$+z&N$T~SCUrYb zl6w87N!@Ofq+YLSQdhN-)ax@%>MB-}`g)beq7vYYo|cNExKSR13Z>2&cretp)80_w8@9NrIYO3|DEw-OBxPkvD$RC@E?VFl573f!QvAwscw?Mzv4%OPb z`-VC?X`ItUO&Hj`t)2dB>gwUYicLc`k=QYG(T1+3{-N672Id!7sNCo!IbDP8L`__3 zd;3sfP2skywr}5l=1?*EtG&IGm}hqJuWtU;Nq5fd;$PkLtBH@4&S7b$Nwd}$?H^Gi z=WttC3A1wir&vNhH*1qkw<$_Di_TJrR%Z1^oY~Yq!4?Z z+Ni1K4EAn|B+l*KrtEn}DJBD_i3)45`iaC2puD*Q1IoLl(I*#Eucf;Dg zZh4;QWz>t&wLD1lQe4Zy`6UL`Q4bzmsGbW{&pCKdJugGGgWRb{wLC#$Vo4I!@*qhV z)#fp`5UO7R6bq_fj%z{n(FWC#(>=IQ-2hb2KX_2xn4!A9s5Xylrl2}{wSkNo{a9_D zlnkNzH9)bT`qj7=RG(!~9gUw3E>tfBsuvtQs9uzzy3VK;prxT&9w`mS>gaWTff4xY zfMP-QYjG`wl?LnSf>x}BXjlj!$8G)Pk2!vwwn}A|L^&4?5 zsBSi>ZVsaQBWbH;?X-^7O)FF0irIlKmdWBz`@p_d&3X%kf>|{yG&eW5w|B@|*(5EU z9R`RWdhkH}@C@Qp4smAzOyhPzmeu0-%qvk4)8qHdTbn`vKLmglfS-M$%%Hj& zMD+`uupRAf$+p%c?PvvevM4wg5<6KPyoq&S+gY+vW%Ncn14kV^_+6IacM9=4C$OC* z5DP=J&CI0(^W_%-l9KQlwy&#ceX+fLU2)CwJGxgczoUz& zb7jYh6)T$7(`a{HVa;-4$GE(eW)73>*Eup;NTZWhYfkCguq8TD*44wu$msk{JN;*m zm(iaigIjuPBj&C-WM-1ZPnrb|iqX*d#N4d)awP0N0_W%mjgG9F4iaRW`9yY5EIM7r zN5iJ#NJ)Iv%6t(3Avu1p#k_-*&NBKN&s6~|+pHc5lX>#xxRw+b;ac3l@e!oMYuO(S zK$`HpitxPZ4g&P5Za|u#-nGi$x?@!*gI!?V-cJ7w^$f2e+Rt;MNqiS48{Q{dc%Kx6 z_bC~?s%J+~4X;W+ zG7eP}W$)-<2vQ`DHl7e>ac29TEN;nB?p(?7Hj1hI0LK13a*+(BG#K8G$1lQz;^j7Ko)L_iD>4{oFrEw; zC!;1Fp6~~_n>{?9fNR0yu?COy@Ox;^dP^LSCTdDJi%&=Q5+WxNUhyb-W)NOyW$?=2 zH5u@lm6$!Y#r9h@yvh9W5fOaCCm3H8hffsFmh4rAxo zFm`qjXN3%B8O|mHXMxR_s(^|gM)enP%r}{M0mr}7rY9x**tZg~PKL5y#a5MAuc4k6fhK&$?_LC&wjgNQGtgw9nGDd( zPL3kYTO?$71BJt)hrs-%NZ!IdS`M6%^1q|y0Sg5T7n7b^PJA+{E&cK|3d1}C1+{>xj zVzc?;dthbPe3w3XG_M8d6*PYo*MjE75t_rRw@(hB`Ht>Y@ng02uq`3l94;_1djC%k z+|yMeT88blXzdB2b!~>$46T!gR%d+OoW9p0_zE8iGEc-L(YgZYWVF)9tljZ-wDMFA zFW0^}j@IZ5ygeJwN8|PE4;`-M!#{i`iAKTZg%L8c7SvALxxIA}dI`}N%Ac~w(wCt( zL+{j}w^)cK&dJenF?Lvi_e$f_V+FQ9bbburD#6yD9?y<~?Y(~Ccpw-@H)Kf6kT@Ag z44e&$y_#4*@v!uc_+i&c7^-3!$sTmQM{7qL?ErQ# z2)s=h@G{^{2Jn(=N0k`x{4+tV62$DyUkD|0m_zdCk8Ni>U>A|(&@j($D!*k4+$CrqrgB21<`Q-`b;V)g# zRUk6ojHTt7>;u6i0_}kv1*94HMHY+PCC?oZ z7{kwLzAXSo9@pC77>#S)xod<Ei zu{1u|5WRLthPd&8a3~~CW4yh>Vs(2Et5;@N&9FLoSatA-qYM6WaY?_C;bZkUU{kQV z3D*)>PmHh{-s3SZ&32cCdH9RNgl0^92XFM4mz&^#1093-&)*F;3A5Fm7NI+W2)!yp zXok?qLuh;{7oU|gryAk|-{|O0X84^9{F<3+ zeDqr^L`Y0xv{@gT^P}q%fJ#Pb{#0BGO8X*|hIee7Blz}EFK>?e=j`|L2C*n+P8lZS zFKW0xh{>@GlNlx_1CxP|#1v%SX%9Tahr-RVXIyoJE9*&*2L>f_u8S}j{zl9j1Ci1h z;R28LIQ{;;IrE+aGxUMR@Ow3Huu*e&5TWTMaIGeA!Upp#psW>+-)aA}J^)aH(P2LV!5VwE z=`-i%eNyw+7uFZ)Q%&Y-9(~D4FXndj=->0qv44|l4%IZ0IJb8j(wGyAND~#-KzZeJ zPv*{Cc~g}AyP(-%v+q ze@}Ol84&RoE-8!moy&W$O`vbf)X`ov`f2a&Z3+jraf{LiM<}IW_fYv$7DXPC&7rb6 z)MU(|l1Imj-lNaXMqjgpHlAR`)-nX%{ulIi0{${AJQUX=<3kbr!-r==&pd1J^B%~u zyA1an^!q+Ua{x$wxJB~AfaFI4$&bj8oFREKkQ`XvEa(P9@*{i2qQDYsC2^dW>=#jd zl$U{GSu8mo*COtjxE7Q@F+zFxsLiheLEb*NrRyf~S9Rg-T;zeG58KAx(=`L*{G+XR zcoe+DW8obhlX-{CJ4}&xz&lO?-l3wK9Og`q;~gr3_2j`j?``(^t;E5Bc`@`_uje_*_`O#LnpWcr|>uCNu(;P{=22=$tq{_^_Ow z@GzhCyO)lDpJ)O11jM)}BgQ=`i*Z?un+(925wLU8O`q)W&y~088Mx%<0NZ3j8+yw~ zuM6SarMQ*=_dr}rfV(XUaN%=0`}LuRD7Mjl;^ZxEP02j>sTSo=0m`2als_#)d4}@I zKzZo#5!p^Lt5W`x(#1k-JpS;sRcA^9+_NnlpM?PTTm-o1WC1PlEc`R)W@q@ zB~T&q#RtEwu_YWg@NM%@99z{DdAH)e1it%4C=Va$`Dq~V*&_+g8$;q7HUBN^x6iju z;dyWhFN9NgLFN=Pr!W~#A^Ca3VnyHa6~?(VL6^$-scXwhp$)4qnxFSc-eQ3S_q$eazCa}2<# zUE9410FZHU^iI6i@ZqKp2O_2(U~)D-@#dcBGh(676CJ>|=adYPUuwbk62!unBNo0a zi-lP%oT6A*^pLT%2S-Zg(aF%k_-ceT|5YHPK#WAs zGa|%hW9Xs{T}}3Zr}jeA0UQr}wFT;{5Hw$lp!u3CXl6lk zGJ~JL9}NYdxtI0h!gL)jUFGJq{(r}L!^D5(Q6CA)>;Q-!} zIe^RoOojsp9F!>QOgOM)T-KoPkIz2=91G5m#5f z*cq@V1K6SMU!A@u2lK_)(GUORb0zgKNprL>>_7Ck23Qwga3QY67aWFb3IFemd_nk7 z*iQn!K)x>{3*NEaujsQg!k)q~k53$vub_)Hr}S;uVpsU+dSq}*Pi=%gA*JhlCdYv+ z_PyV_i}%4@d=T#91DU(X+{I+Li@?yoS)hxPV$Kd(v*6fF{@roFmB6+P{g1%4kqq4#x+eqOfx$pQ zz-af}9BiA1byI*}5zwZr`spz-*CjjvkQblwXk1Gz-hpe8{`SZvgb#zgDdZA5SMe(n z?UW$;;Oitm<2b3icptaW{}`bENkIP-8T2#gPX_b@i~8ohroeZ6;odyOANmGBOKgVV z!h1E~EASr1wZMBTt_9woiQpYR>ed#5HxKC*-OJ7M%k=Qa{v7c99}BckML^3AcxDGY zr{I96IoA@$QdPsDKcj9H93)RoUk{`Rl5UKU50IYO|vFrniW_-Eeb+0&2rXQincxoXPSN@(|E64yz;WKnz96fGv~1AzTaaV^0kU@Lv!CKYV8Dm4V4&aNopP zE2S^bM8_xg@4Ji1!xDP~KEJ20eW1V}T$S3TzRUb;7Vlq;@E%*Up#c8%4DT7nsZ(*#X>Zu&w`#Tz6!H0~eS-L# z7R28`(Ec`p_O~(+XCR&o5C?WR3i>|AWY9M6xd;X3w$vSt3xH@r_zk!ggg+G55}F@r z5g$I#^wt345r${bCgyi6#P0^gzXynaH-mTv@yURAU|f!85d)``oAs%MM=qfA~n#e+~M7VA215p#Mie{|__tXXu|Q^n0^%XKk%T zqkjPXg3uuP1mSr#FUlw7C~kBfMWXB+l|O1`qu*8Qs@A#rJOr)E$IKWMSu8k(>DVne`f<)k2dil z*;LH&>-$l{Usxycb2y1#!b$vZ<|HyFF&R!Gu>EG9T1s&eW_8{;31=}ce>ecmfX|yo#i`g^7}e(@@osHUqx_=t&7W_v$78nWgjBy=*IVp z7+nAPhlm2_P0U^w2T1=gV^xRL4w7;^fD}Q}i54m0vstg%7gFx!Cry59vH2T>y5A$z z{Vof2S*V+$P=^oj2G+vjPxd+h&7a@`H1}j&OQ?G;t_9-HsdZmcy-Yq|lHb@jnA_M{ zEOqPGOdh|nqr1DWU4AzW*ZO$Bh%bhl`UdH96SPyjadUq^gM3Z*;MNUicGvp0^sH$; zbEv;(Ypr9rXU$Om;MOy{`a1?Tt{L3W)ZH=MVMPo!ZK?J2whz*N@y4~x?At&Rn+Ci2 zZ&OrL--eo8N`j_bZeeb&R7L8Sn`cs)i@8!E+DFd)Avc>6@n3(;&5uenY36W=QF0L( z{VioGAD_|S;@vB%n@N`=HL~Ito^l!$cG||i4Sn7Gf`oGtp0p&(mQnSbzRI0Mx^MAx z-zD-n-AvT|pH%mMuD|Y+rzVRnax5dL{Lhi{n?2=s&S>TTMV0^8`YS)+q|C!bLFIpe zlwa|b-!Y?=|2I|s-|MgZl6W0=y;M#%1eO0qQhwQ0eqm<2{C}wO|5<c5R@%{dd==1amWiz7B&#u3omj?7KGpC@Qzb1Ni2KB?mBFy|= zt>-za=ehOQ^HBjk%h`>fp1&@7cE;~y&oe~N^Hk6C>#yf!0X?VBlD;8&c82PtXT;2V zwLLeeo*V10=c5C9ma~XKd;X^A*%_4&w_#9zuU7K{RrA97tNECKn$xE~-x4)DJb2Xxw~6{Z-r)P;vU?@Vm9n4tHu^ zYndUVxg%A}OY5)YlLA^!p9Ox8we0wd+Dx%!`lv)?%ggGo<&y(iPM-sQzec9)1ixC# z3>jn4EBzxaA5(uVpAyh=`V8;~tYz1hn`elYk5w%nSAQ*^8qjk3{O^aP<+k{uU9EYB z1i#}|$tTob$)^RBoId&c5h=OVRq_mpefLo%pICn-pB_+h`qb~oq-5uyL#;GJl-#6B zKB@jnJ|m#y^oie3NXgFPXRSO#eDcYvssFv*Ku`*j4ev4<8u9V+!oMr`h4##r^5O>k8N?u)mC9er6IeotO2Uc=_Ov&VwXNW1Et6E-De=VOE z&~o~O?~h}fdk5lUI8iu1Qgp9g9HLjHM&q~h>#yPS0~$`B?fr=r+`m3<$TP)`>8*E> zmOJXNH6c_0sP=DSsSJ@r>!E}*>hiQHcYI!4Fb4bsloUjOvyuUGZAw*LCd z2lSUdN&B1V&)NIzuL9%KqrY{kzrOnGZ&pBm>GQ9@i~gK#&HmVlp6SsaeHc0lG3)EE zzrbgP3h7g;e~A8^9n1bIMx@iDzkb!hU>cuPnzeV6Q?qCaOdvOl(7I6eBKm-$8Z zH&}oDnYWL}AH^*d(x!tdt#>o56M;*$BSPf&jo zqCaQjufG{9pwpwjEvmn*_19lxa{OZ6WE0X~J}3Hf_VoH=2Mni2f7?`l7u8>X3j+E} zoqy!>UA4ij?#6R}?A-kH=zo<&l3H)_7~ezo*w;Os`|UE z{`y-K&|m8OBR{*FroZm=BX+8CdenDcRo_Vc)ptlheW}xr{2W%FJNt;8GMgUtU9Rfe zUVrs1PO7hzI{V1aW%W6ekKt)we7Qo^cV+$6w&b(s=xA13@9&s#<95Oo?ECjPxo%y9#!7W^;ceNQhDX{ z`Nk4CkTB>RNSN*+%Pp$DTkEgB&Vc&T=NpIKc_*JWxRKUpa=kfvt6MI|)be2Z$^p}+ zLhgL}k66q2l4+o5S;Wod*my^-iK`Zmx~suM zqPDOrSuX0X<$|S#h^nZ4^$*poy41cpRKBV!z=HfUw4=1C%PkAlSJUcL@oF9DjdL}l zrUFaFizdfvyKn88E1pg#|_nPGKmh-j5+ z2-Vd_!79Mgx+zRhkqc~z$Ox8ZlQ|%2xw59-o76m=2OM=yKD{{4++jrc~ ze{3}69zlO>S{=x$U5=V4N??g#sa>rL2xIkgY>3Q2%xhD~I<=ar)b2jz87akTi7`bv}WOVEnW^6&t)JLIa%JOT*!IracMZGjF@S-e)A&s@3&RL+ebQ>z9 zQ4Gk}>_9$OBPZ)m9Ig1`B2-F;%V?9bVr^27jf%3M92uiD^I}v=v!j{H3gng%$t5N` zkES#&+BDaK0ZvIr5pZ1>*i>H2xr);2OVMhTh&pO^*eO_QNYdz9N3qD}-&*0z%g}W7 zbx@|VV#*XDY`SJ@)@=kVA@-h$iN{i~T<}O|YPP_(EH;!~7~mZe;4KdDmIQcO&sZ79 z1=6X>p)b}1l63`m-2q-tfY%$~tqt%*jkOM=#F0QRpmXm_Q{LW*iSIvy^*U&Wog$!j zXrw6Sak-JeHkh-eL4vXX%VwJj7Sm^0NTr2{v0PyandcM&>(cDXI@7XX=!GOp!xlzQ zsGZ7^s*Dxe+Qe;N361GIzqbp@v8D8OVU2(#uz)uHV+RDNc47i_a-I;-Dwy9H%8oE) zi}!Ie)+zzxs!(pU6uH6UI`i=G1$d!diEc&u(ljetgy z`e@^mmcGc*jrtJO^f=odu-YvPicl7YM9P9v)u(`^E(NR$t$42?TWj4$57$BuS_t$& zo_6WGCMNFeOnQYe8o!HIxDFCD2Ew~5%ePWmaletfWS7a#c-OS3z)4zvwR@e;Kx4{6 zck2uX4cB0Wj9dX)0$eX+wX%TjdNfBz3TTe9{N{)dSw|c*0(jn`snH-EvZG$7X&cpk zb(9E0xz0G~FFzpA713%)S*ByV(Eu$B4Nz9H0lW}8vU60PlB%sEhOIhc z?CP=MLPyhJX?b8_ilP~%A7oKSRCvEY6QIItjVA7XT1XSou)E3%o#!NZ` zjLlG*Y%|e2y21ufncB7$rI4FYS2b3sTUmQox6Cy57)d-pKhM?!lC)}2qzVViR81FO z`0{2W_7M70GeDW@MgR(B0ZpB@K1ii3q*DKbR2b1He$}@k6|dI7IuPRh*m|1A&7fA3_(U6hCn<9Ny#>d zle*Qkft{vS7?!Op6r!~QOKS&~Rs}4r3L?CylgBt>|F@Z{@aoSztEku*N9&Rt8qm?74p^x9TjGTX|CXzOm6gx?b}DBZJp^53>z`J*by}nXBW2i6{#p z8@m|Vnq#eaSiag8WT|^ZiE3^zBxS*BbWsPgwA+zUyB(F#i9T4mEQ4+b%T=Z*k|ukl zHVGOJH0oq8rZE_%sda>0btJxnZ5i3V<61Kve-QdvCBQW*3mTJd?z(kk3qp{xd~=hjD9vX}1sfp6l{^^Ibo7bzEX-2U5ZoUy6SjbRsBI(kM+he7FB8S4}pAR$ZZ2-a$A`vDeAxWlFb ztJku;_Kq3z5O?@c^utn{9Q~lpK+$3zW2I6-e9*(t2bvZ}p)6oqwSaCBi5=ZTH(zo6 z=$<`0cQ7C-0*HsBatpL_>JyZ;Z zM`|`Po@Pat`MTiiN1@(YN!Ymx@jJOxG>-n!COdl-9m=8EYP*PAn#!xzSgF`17 z%{BypRTivQS-`M@3@m9IL8MtA@;G##Vl<$C6k@U$o5hEV!XFP2ss?~mSqYGqTVyTe z2_`#lj=}IX5-CWbjFm}cXh!HqT@_fXlNrI%64xbDMJf~2Khac|N10j?v{r!xg=q`W z>6#HPSz7>>wg4=xZitm^0aBS3(A3;489oV(c-+Lq2ODW6;9|#~wH?r&8gGcDWoy&W z-P$xbRn>8T1vOom+7sm9xkXPl&0y!D<-&Ls4p4)#U`<9d{AxO0*KU?Reu|OHLth=V zL9ViV&n_>xGYWocKmxqt^=6{`)dwagy1afPPWMpJ{|qC5 z4OP_*L$w0daTSK`JikAet1ct4E_Wc8tK5~~Zph_IUrulbbGhUGp5SiG<&ODhg1d

    lsbaH_cqL1G7R2Zh2fAs@bkkk; z56Q4ldNxGpOdcY3(Joq%niyPXE0}ei=Rkr^N?>iu@~w@Q{{;lk4P-|JMob%i{ib9a zcx9_+16zGb{P^=ANT)rhhq4m&5HYOH=LZC!Cc0(@IC7@kSet~{7a;Roi+h->vby`! z)ktod{fib}XtJ{_(6oSyvVeO%I0Ano0{JOVyA=E))M?x-1rrv6CnmnJJu&=PU^RxYv&6FCVs!|O5y^2j z6%?aB5*d{RT`3DK*JWmi$M8dkpX$^-Gce7S$^T1DbJ=q}Vq)U%=Omh|p$H{uLlAd# zXoZq=Xa$xw1R0eD@j6GwI7-)}z!C#WPAMg(ybN}r@_{b&mbY{o4Yb4zUJemw*nS)A z-KMHlh@y2;qp{Y3p0z#XuXDLq7!eE;U7>(AYAqlDHlxKDnZ7pW>uEs31)+mwI zY$b@k!4$#+*V(p;u{B#QC9!5p0>n$b5dva~b!U7YglY^lHE5MazA2Pl`%fkM;2dj} zZg_Jjx9TI7TX|9I%Vt~uEy%C)7q|vx`K5PZ4Ta^s)kt9%saaqQ%0hHh-vEbZ>LssM z`Hojw46jFk?osWE}21%ef?Ho3)I?j3G2B{sL-e?h5{2^02c4L|yEBCO3PpIW{S9s4O&A9U4@k;nu4yl_7(?kD~c15S^nebdCzdutA#7`=KK7V`#HZ zCu5*fkqOX|0GZZ&90FpAHMYi(?8R0C`cH(iYv-%P1Zqv;pA6+zGmPa{p0s}3V2vja z{P(9I;kab4De^EPGU_AWEpFq}$gYkW_IRR|=x4Xj1Bv0>2^o6)1TvK6$uKYA<{3mu zyys^iMGXtatE_|~30Y$NpEdazS-R&M$RFEEQQ*gTqMfK}5^Fyfs1{Ih=2g3_V za`sJh{CS8_SiR`m54SNMZy=11Rj9jJTdX@)2KvuT}|a;D6Mj#cVz)zowkR; zlG14zt2iQMe-X9U{Lt&=W~JnpZ%ht0OlXk-#$84RZzep%gqCAo5)Lh>hK3gSLRhoH z0TDu3?b;-TAy}FUaYR|ta8qls>o1|!kD8eH?)wrmQVocx;&HZcu(WV=1XxZOU%E?Roy)6~CxbJ7Y0hGK+YhX`GH2MoKcX2UQP z3EwahI6~fPn)cm(r)eq#?NAmhTT4g3qP0@cH&Ip1kJetnt)+$ZU!=5F+~Kz%Ld!!( zsvU(}D-ynq*4}1XdsoS6tqMVFl@)5OYct|uq@cS|Rn3pqk{9OIF8F*(Yh@1c9f;5& z82VPR9&W8j_^y$_F7|fQ+Pl{~t;G~mF^k0+WohZ?TP+=GLU&8q-$U&+F%+=FDBy^n zrYJz7=l3B(tAOtA-Mev%gdZ3QY~1%Z3ixWpQGm(?ZneAM?X;*+Yo(wcqNR+HOEh^N7Qqa#)RZWbhUS+y)>Cci~I999_1oOWz61WRbv5kcUWyMB&r`lvNKT)9j z=(AMsmqz%!xNz9VNmdYi)XBJY5uwwbU&Z2(w$7}~dX+TNE~{2TNg#u%!lL$naprOxa<_{qyy z`gjUZmI2pqp{--B6lhCXzP2JU6ex1J-vvZKO*c(Ud~{$h!*$X0?;&Eftp!A=y~BE> z%c3EWNce-1z_H|k28X}C+QFg55(v>)0+yBzi`UXUdy`-)W&aVi*TnE-R~u+9`a%+# zGEkCk_!C5|R0U}Ns?SD6MFCO;$^U2M*Tks8HKqy;pG#I@tXP)wOX4B^Vx+J$)5rrU zIv<20PPcW1ht!O~fYf!&Y+C&l71hirLRnsB+Wz7R;t)&v8zg8fgwIw9K9Y(ObpCEK zvzuzRbq|@ls$Q3+pn4rl1HU@^g&tJA2SA=S$Oz;gP_|}=CbV2ATT?+fx>SSO8D-N9 zT}HM4G=;FwSBarQ)Nkmv7FuE?+TAG;`!9&q^$Lj9nRA7l%v0&+$e;bj!VS@pg zcEhN#;CY`-TCjYA(42+&Kgj6R-c=d9S;oY~7j6&B=r=MZAOmx6m2pEZH(U;TGhT1x zP?)EGvh75F>ofp1roI}Q&;YqiYN;e(f)&ubx@Je6i2OmqbY)2Lzk@%iqLQgc^WRkqP%o$i431TT7CiAtl2{n z)##$^#a8wJ`Gu&^p~(uV@?nj7o)nHal1OKIS>hs8Xthez(p6$YKV_L+Da;PsyCw~a|22T7U@l5`B^`E9aj!PD_3H>0+}b~*5%ELee# zsln0)!0e5!m_q!nGkZ{?6$Gk5{zPQfl;|d9c}k{U zmX|f;n~?oTs~cojmRE7oEN_YAPcpe#v-50j;7eK1nbrrGQGNM_*eZ_VWK>Y)L9@#8 zr@~{c0-;kvxmC5X+{&Y-@QXBBWm__TD)OsQKt0Mr10{PjF`~D1l8#P;2z4URk&5s% zEIv$7bUO0u5FFO4B7N;uOQOCrkXr{?C|y}t29pM`6A%Zw9NBf?g7)i($E!TACQ98` zAiMf+WY@O)b(fm2L|z?TqT`k2d%vozH|5VnZXJX{YiPHQJ50N)W}J9dD7Pk6fu7c+ z&!p~WBR~2~^DD?bvyuEVSvd#!5x3MtHNUU+YDrL8KyDo!qV1@?R!G_&ZKd-vZc#>l zMTj}hf*T#6EFXEvqgB$R5~OM9fhnjo&xPZ7tvo!JFGGrYebh-=ex1fjg@UxHg8Vwh zh#iv95nSSsgqg)OBRi6+8kLnSzETl9v>^ZCNtG(g&yOda1(a1t(S=N?@@OmAQ)RMW zWJ=U(gzoN;>mk!x~#ZK$G(fZNdpOwWLEo|!2*pH&AZryEVwY%9f2r zDa+4I{#YE#dB~3C0(A`Pj}y_JMzpMq^O0Q_%F)?p*a~^wLXWP>`NsSO$gW+8?8@@o z+L(+}I*?b#?SZ_0&8ubc9-YYDVQUGO2DNEF*e;W@yF$4&sS5O!UX}O9(l@;I{oWTQ z%SLV$Xv>x!>j~x7q$)63wscr8a;sgU-N>y1ZP|kDwV~XaR0VovM^6~ZRB|08P}BKE zTt775CCHsWA+J-`IP3|j$rDB*qYpAPHQI2gS^xXtGn4CoV{$Spe%R-TkiqiZqx4JJFgW=#uU zp)9~nN7tCQh(La5Q;cyC71HHRNVHE^1|9}v2{NGG2nlUTFxV$CQzQr&H-#jq0_;

    lLP0^F10SPn|X%jYv9{n!xrh$(@M{{M#hMd!AHp-!(o6_@Cf$TdJuS#H9cnY5wPhlP7 zt**fF`P6jU87ElOA0VmYzpi0^Xff^RIH zM!gtMF&pD)3u8QKqU`Grnl^4ncRpca;{6K~Ct!78?5`KefZ_^d*M%2Y1BP(gaHHd@ ztm=trUkM31_JIWLbuR?bl0Z@X&JJYP(-6q660tsHDo~ "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q); + end Structure; + +-- entity vcc + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity vcc is + port (PWR1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vcc : ENTITY IS TRUE; + + end vcc; + + architecture Structure of vcc is + begin + INST1: VHI + port map (Z=>PWR1); + end Structure; + +-- entity gnd + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity gnd is + port (PWR0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF gnd : ENTITY IS TRUE; + + end gnd; + + architecture Structure of gnd is + begin + INST1: VLO + port map (Z=>PWR0); + end Structure; + +-- entity ccu2B0 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity ccu2B0 is + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF ccu2B0 : ENTITY IS TRUE; + + end ccu2B0; + + architecture Structure of ccu2B0 is + begin + inst1: CCU2D + generic map (INIT0 => X"faaa", INIT1 => X"faaa", INJECT1_0 => "NO", + INJECT1_1 => "NO") + port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, + C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); + end Structure; + +-- entity SLICE_0 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_0 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_0"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_0 : ENTITY IS TRUE; + + end SLICE_0; + + architecture Structure of SLICE_0 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i14: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i13: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_15: ccu2B0 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_1 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_1 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_1"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_1 : ENTITY IS TRUE; + + end SLICE_1; + + architecture Structure of SLICE_1 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i12: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i11: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_13: ccu2B0 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_2 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_2 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_2"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_2 : ENTITY IS TRUE; + + end SLICE_2; + + architecture Structure of SLICE_2 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i8: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i7: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_9: ccu2B0 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_3 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_3 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_3"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_3 : ENTITY IS TRUE; + + end SLICE_3; + + architecture Structure of SLICE_3 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i6: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i5: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_7: ccu2B0 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_4 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_4 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_4"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_4 : ENTITY IS TRUE; + + end SLICE_4; + + architecture Structure of SLICE_4 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i2: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i1: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_3: ccu2B0 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity ccu20001 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity ccu20001 is + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF ccu20001 : ENTITY IS TRUE; + + end ccu20001; + + architecture Structure of ccu20001 is + begin + inst1: CCU2D + generic map (INIT0 => X"F000", INIT1 => X"0555", INJECT1_0 => "NO", + INJECT1_1 => "NO") + port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, + C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); + end Structure; + +-- entity SLICE_5 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_5 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_5"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; DI1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_5 : ENTITY IS TRUE; + + end SLICE_5; + + architecture Structure of SLICE_5 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu20001 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i0: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CASr3_384: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_1: ccu20001 + port map (A0=>GNDI, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>GNDI, S0=>open, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, DI1_dly, M0_dly, CLK_dly, Q0_out, F1_out, + Q1_out, FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_6 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_6 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_6"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_6 : ENTITY IS TRUE; + + end SLICE_6; + + architecture Structure of SLICE_6 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i10: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i9: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_11: ccu2B0 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity ccu20002 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity ccu20002 is + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF ccu20002 : ENTITY IS TRUE; + + end ccu20002; + + architecture Structure of ccu20002 is + begin + inst1: CCU2D + generic map (INIT0 => X"faaa", INIT1 => X"0000", INJECT1_0 => "NO", + INJECT1_1 => "NO") + port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, + C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); + end Structure; + +-- entity SLICE_7 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_7 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_7"; + + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_7 : ENTITY IS TRUE; + + end SLICE_7; + + architecture Structure of SLICE_7 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu20002 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i17: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_add_4_19: ccu20002 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>GNDI, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>open, + CO1=>open); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A0_ipd, DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_8 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_8 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_8"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_8 : ENTITY IS TRUE; + + end SLICE_8; + + architecture Structure of SLICE_8 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i4: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i3: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_5: ccu2B0 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_9 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_9 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_9"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_9 : ENTITY IS TRUE; + + end SLICE_9; + + architecture Structure of SLICE_9 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i16: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i15: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_17: ccu2B0 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut4 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut4 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut4 : ENTITY IS TRUE; + + end lut4; + + architecture Structure of lut4 is + begin + INST10: ROM16X1A + generic map (initval => X"0002") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40003 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40003 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40003 : ENTITY IS TRUE; + + end lut40003; + + architecture Structure of lut40003 is + begin + INST10: ROM16X1A + generic map (initval => X"2000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity vmuxregsre0004 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity vmuxregsre0004 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre0004 : ENTITY IS TRUE; + + end vmuxregsre0004; + + architecture Structure of vmuxregsre0004 is + begin + INST01: FL1P3IY + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q); + end Structure; + +-- entity inverter + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity inverter is + port (I: in Std_logic; Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF inverter : ENTITY IS TRUE; + + end inverter; + + architecture Structure of inverter is + begin + INST1: INV + port map (A=>I, Z=>Z); + end Structure; + +-- entity SLICE_10 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_10 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_10"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_10 : ENTITY IS TRUE; + + end SLICE_10; + + architecture Structure of SLICE_10 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40003 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + begin + i3_3_lut_4_lut: lut4 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_4_lut_adj_4: lut40003 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + ADSubmitted_407: vmuxregsre0004 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, + F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40005 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40005 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40005 : ENTITY IS TRUE; + + end lut40005; + + architecture Structure of lut40005 is + begin + INST10: ROM16X1A + generic map (initval => X"FF7F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40006 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40006 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40006 : ENTITY IS TRUE; + + end lut40006; + + architecture Structure of lut40006 is + begin + INST10: ROM16X1A + generic map (initval => X"E0F0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity vmuxregsre0007 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity vmuxregsre0007 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre0007 : ENTITY IS TRUE; + + end vmuxregsre0007; + + architecture Structure of vmuxregsre0007 is + begin + INST01: FL1P3JY + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q); + end Structure; + +-- entity SLICE_15 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_15 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_15"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_15 : ENTITY IS TRUE; + + end SLICE_15; + + architecture Structure of SLICE_15 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40005 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40006 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0007 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + begin + i13_2_lut_rep_16_4_lut: lut40005 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1110_2_lut_3_lut_4_lut: lut40006 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + C1Submitted_406: vmuxregsre0007 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40008 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40008 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40008 : ENTITY IS TRUE; + + end lut40008; + + architecture Structure of lut40008 is + begin + INST10: ROM16X1A + generic map (initval => X"5555") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_16 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_16 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_16"; + + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_16 : ENTITY IS TRUE; + + end SLICE_16; + + architecture Structure of SLICE_16 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40008 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2045: lut40008 + port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CASr2_383: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CASr_382: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, + Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40009 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40009 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40009 : ENTITY IS TRUE; + + end lut40009; + + architecture Structure of lut40009 is + begin + INST10: ROM16X1A + generic map (initval => X"C0CA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40010 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40010 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40010 : ENTITY IS TRUE; + + end lut40010; + + architecture Structure of lut40010 is + begin + INST10: ROM16X1A + generic map (initval => X"4000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_19 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_19 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_19"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_19 : ENTITY IS TRUE; + + end SLICE_19; + + architecture Structure of SLICE_19 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40009 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40010 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i26_4_lut: lut40009 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i2_3_lut_4_lut: lut40010 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CmdEnable_405: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40011 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40011 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40011 : ENTITY IS TRUE; + + end lut40011; + + architecture Structure of lut40011 is + begin + INST10: ROM16X1A + generic map (initval => X"FFFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_20 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_20 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_20"; + + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_20 : ENTITY IS TRUE; + + end SLICE_20; + + architecture Structure of SLICE_20 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40011 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + n2447_001_BUF1_BUF1: lut40011 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CmdSubmitted_411: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0 <= F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40012 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40012 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40012 : ENTITY IS TRUE; + + end lut40012; + + architecture Structure of lut40012 is + begin + INST10: ROM16X1A + generic map (initval => X"FEFE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40013 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40013 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40013 : ENTITY IS TRUE; + + end lut40013; + + architecture Structure of lut40013 is + begin + INST10: ROM16X1A + generic map (initval => X"CC5C") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_24 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_24 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_24"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_24 : ENTITY IS TRUE; + + end SLICE_24; + + architecture Structure of SLICE_24 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40012 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40013 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_3_lut_adj_15: lut40012 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + Cmdn8MEGEN_I_93_4_lut: lut40013 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + Cmdn8MEGEN_410: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40014 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40014 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40014 : ENTITY IS TRUE; + + end lut40014; + + architecture Structure of lut40014 is + begin + INST10: ROM16X1A + generic map (initval => X"4040") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_25 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_25 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_25"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_25 : ENTITY IS TRUE; + + end SLICE_25; + + architecture Structure of SLICE_25 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40008 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40014 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_3_lut: lut40014 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_1_lut_rep_24: lut40008 + port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + CBR_390: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + FWEr_389: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, A0_ipd, DI0_dly, M1_dly, + CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_26 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_26 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_26"; + + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_26 : ENTITY IS TRUE; + + end SLICE_26; + + architecture Structure of SLICE_26 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40011 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + n2447_000_BUF1_BUF1: lut40011 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + InitReady_394: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0 <= F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_27 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_27 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_27"; + + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_27 : ENTITY IS TRUE; + + end SLICE_27; + + architecture Structure of SLICE_27 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40011 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + m1_lut: lut40011 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + LEDEN_419: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0 <= F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40015 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40015 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40015 : ENTITY IS TRUE; + + end lut40015; + + architecture Structure of lut40015 is + begin + INST10: ROM16X1A + generic map (initval => X"FBFB") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_30 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_30 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_30"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_30 : ENTITY IS TRUE; + + end SLICE_30; + + architecture Structure of SLICE_30 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40008 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40015 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2010_3_lut_3_lut: lut40015 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2044: lut40008 + port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + RASr2_380: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + RASr_379: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, A0_ipd, DI0_dly, M1_dly, + CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40016 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40016 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40016 : ENTITY IS TRUE; + + end lut40016; + + architecture Structure of lut40016 is + begin + INST10: ROM16X1A + generic map (initval => X"8080") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40017 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40017 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40017 : ENTITY IS TRUE; + + end lut40017; + + architecture Structure of lut40017 is + begin + INST10: ROM16X1A + generic map (initval => X"FFFB") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_32 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_32 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_32"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_32 : ENTITY IS TRUE; + + end SLICE_32; + + architecture Structure of SLICE_32 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component vmuxregsre0007 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40016 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40017 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_rep_32: lut40016 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_2_lut_3_lut_4_lut: lut40017 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RA10_400: vmuxregsre0007 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40018 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40018 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40018 : ENTITY IS TRUE; + + end lut40018; + + architecture Structure of lut40018 is + begin + INST10: ROM16X1A + generic map (initval => X"1010") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40019 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40019 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40019 : ENTITY IS TRUE; + + end lut40019; + + architecture Structure of lut40019 is + begin + INST10: ROM16X1A + generic map (initval => X"C6C6") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_33 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_33 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_33"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_33 : ENTITY IS TRUE; + + end SLICE_33; + + architecture Structure of SLICE_33 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40019 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_3_lut: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RA11_I_54_3_lut: lut40019 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + RA11_385: vmuxregsre0004 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40020 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40020 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40020 : ENTITY IS TRUE; + + end lut40020; + + architecture Structure of lut40020 is + begin + INST10: ROM16X1A + generic map (initval => X"20FF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40021 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40021 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40021 : ENTITY IS TRUE; + + end lut40021; + + architecture Structure of lut40021 is + begin + INST10: ROM16X1A + generic map (initval => X"CACA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_35 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_35 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_35"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_35 : ENTITY IS TRUE; + + end SLICE_35; + + architecture Structure of SLICE_35 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40020 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_4_lut_adj_25: lut40020 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i29_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RCKEEN_401: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40022 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40022 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40022 : ENTITY IS TRUE; + + end lut40022; + + architecture Structure of lut40022 is + begin + INST10: ROM16X1A + generic map (initval => X"CFC8") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_36 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_36 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_36"; + + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_36 : ENTITY IS TRUE; + + end SLICE_36; + + architecture Structure of SLICE_36 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40022 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1404_4_lut: lut40022 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + PHI2r2_377: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RCKE_395: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, M1_dly, + CLK_dly, F0_out, Q0_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_37 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_37 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_37"; + + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_37 : ENTITY IS TRUE; + + end SLICE_37; + + architecture Structure of SLICE_37 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40011 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + n2447_002_BUF1_BUF1: lut40011 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + Ready_404: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0 <= F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40023 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40023 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40023 : ENTITY IS TRUE; + + end lut40023; + + architecture Structure of lut40023 is + begin + INST10: ROM16X1A + generic map (initval => X"3A0A") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_44 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_44 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_44"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_44 : ENTITY IS TRUE; + + end SLICE_44; + + architecture Structure of SLICE_44 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40023 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1970_4_lut: lut40023 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1603_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + UFMCLK_416: vmuxregsre0004 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40024 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40024 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40024 : ENTITY IS TRUE; + + end lut40024; + + architecture Structure of lut40024 is + begin + INST10: ROM16X1A + generic map (initval => X"CAC0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_45 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_45 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_45"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_45 : ENTITY IS TRUE; + + end SLICE_45; + + architecture Structure of SLICE_45 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40024 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i4_4_lut_adj_17: lut4 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1589_4_lut: lut40024 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + UFMSDI_417: vmuxregsre0004 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, + F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40025 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40025 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40025 : ENTITY IS TRUE; + + end lut40025; + + architecture Structure of lut40025 is + begin + INST10: ROM16X1A + generic map (initval => X"FEFA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40026 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40026 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40026 : ENTITY IS TRUE; + + end lut40026; + + architecture Structure of lut40026 is + begin + INST10: ROM16X1A + generic map (initval => X"0008") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_50 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_50 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_50"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_50 : ENTITY IS TRUE; + + end SLICE_50; + + architecture Structure of SLICE_50 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40025 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40026 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1962_4_lut: lut40025 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i2_3_lut_4_lut_adj_11: lut40026 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + XOR8MEG_408: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40027 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40027 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40027 : ENTITY IS TRUE; + + end lut40027; + + architecture Structure of lut40027 is + begin + INST10: ROM16X1A + generic map (initval => X"1000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40028 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40028 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40028 : ENTITY IS TRUE; + + end lut40028; + + architecture Structure of lut40028 is + begin + INST10: ROM16X1A + generic map (initval => X"BF04") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_57 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_57 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_57"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_57 : ENTITY IS TRUE; + + end SLICE_57; + + architecture Structure of SLICE_57 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40027 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40028 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_rep_18_4_lut: lut40027 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + n8MEGEN_I_14_3_lut_4_lut: lut40028 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + n8MEGEN_418: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40029 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40029 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40029 : ENTITY IS TRUE; + + end lut40029; + + architecture Structure of lut40029 is + begin + INST10: ROM16X1A + generic map (initval => X"3AFA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40030 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40030 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40030 : ENTITY IS TRUE; + + end lut40030; + + architecture Structure of lut40030 is + begin + INST10: ROM16X1A + generic map (initval => X"FE0E") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity vmuxregsre0031 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity vmuxregsre0031 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre0031 : ENTITY IS TRUE; + + end vmuxregsre0031; + + architecture Structure of vmuxregsre0031 is + begin + INST01: FL1P3BX + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q); + end Structure; + +-- entity SLICE_59 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_59 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_59"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_59 : ENTITY IS TRUE; + + end SLICE_59; + + architecture Structure of SLICE_59 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40029 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40030 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0031 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + begin + nRCAS_I_43_4_lut: lut40029 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + nRCAS_I_0_452_3_lut_4_lut: lut40030 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nRCAS_398: vmuxregsre0031 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40032 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40032 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40032 : ENTITY IS TRUE; + + end lut40032; + + architecture Structure of lut40032 is + begin + INST10: ROM16X1A + generic map (initval => X"1F10") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_61 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_61 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_61"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_61 : ENTITY IS TRUE; + + end SLICE_61; + + architecture Structure of SLICE_61 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0031 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40032 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRCS_I_31_3_lut_4_lut: lut40032 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + nRCS_I_0_448_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + nRCS_396: vmuxregsre0031 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40033 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40033 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40033 : ENTITY IS TRUE; + + end lut40033; + + architecture Structure of lut40033 is + begin + INST10: ROM16X1A + generic map (initval => X"BFFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_62 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_62 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_62"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_62 : ENTITY IS TRUE; + + end SLICE_62; + + architecture Structure of SLICE_62 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40029 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0031 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40033 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i3_4_lut_adj_2: lut40033 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + nRCS_N_137_I_0_4_lut: lut40029 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nRRAS_397: vmuxregsre0031 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40034 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40034 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40034 : ENTITY IS TRUE; + + end lut40034; + + architecture Structure of lut40034 is + begin + INST10: ROM16X1A + generic map (initval => X"EEEE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40035 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40035 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40035 : ENTITY IS TRUE; + + end lut40035; + + architecture Structure of lut40035 is + begin + INST10: ROM16X1A + generic map (initval => X"CFC5") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_64 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_64 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_64"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_64 : ENTITY IS TRUE; + + end SLICE_64; + + architecture Structure of SLICE_64 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0031 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40035 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1477_2_lut: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + nRWE_I_0_455_4_lut: lut40035 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nRWE_399: vmuxregsre0031 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40036 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40036 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40036 : ENTITY IS TRUE; + + end lut40036; + + architecture Structure of lut40036 is + begin + INST10: ROM16X1A + generic map (initval => X"3032") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_65 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_65 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_65"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_65 : ENTITY IS TRUE; + + end SLICE_65; + + architecture Structure of SLICE_65 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40036 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i786_2_lut: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1432_4_lut: lut40036 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nRowColSel_402: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40037 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40037 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40037 : ENTITY IS TRUE; + + end lut40037; + + architecture Structure of lut40037 is + begin + INST10: ROM16X1A + generic map (initval => X"BBBB") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_66 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_66 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_66"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_66 : ENTITY IS TRUE; + + end SLICE_66; + + architecture Structure of SLICE_66 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40037 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_adj_23: lut40037 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1439_2_lut: lut40034 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + S_FSM_i4: vmuxregsre0004 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI0_dly, LSR_dly, + CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40038 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40038 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40038 : ENTITY IS TRUE; + + end lut40038; + + architecture Structure of lut40038 is + begin + INST10: ROM16X1A + generic map (initval => X"2222") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_67 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_67 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_67"; + + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_67 : ENTITY IS TRUE; + + end SLICE_67; + + architecture Structure of SLICE_67 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40038 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_adj_10: lut40038 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + S_FSM_i3: vmuxregsre0004 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, + Q0_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40039 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40039 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40039 : ENTITY IS TRUE; + + end lut40039; + + architecture Structure of lut40039 is + begin + INST10: ROM16X1A + generic map (initval => X"8888") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_68 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_68 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_68"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_68 : ENTITY IS TRUE; + + end SLICE_68; + + architecture Structure of SLICE_68 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i4_2_lut: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1989_2_lut: lut40039 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + S_FSM_i2: vmuxregsre0004 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, M0_dly, LSR_dly, + CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_69 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_69 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_69"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_69 : ENTITY IS TRUE; + + end SLICE_69; + + architecture Structure of SLICE_69 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40008 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1491_2_lut_rep_30: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RASr2_I_0_1_lut_rep_25: lut40008 + port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + PHI2r3_378: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + S_FSM_i1: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, + F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40040 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40040 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40040 : ENTITY IS TRUE; + + end lut40040; + + architecture Structure of lut40040 is + begin + INST10: ROM16X1A + generic map (initval => X"FFFE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40041 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40041 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40041 : ENTITY IS TRUE; + + end lut40041; + + architecture Structure of lut40041 is + begin + INST10: ROM16X1A + generic map (initval => X"3FBB") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_70 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_70 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_70"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_70 : ENTITY IS TRUE; + + end SLICE_70; + + architecture Structure of SLICE_70 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0031 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40040 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40041 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_4_lut: lut40040 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1448_4_lut: lut40041 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nUFMCS_415: vmuxregsre0031 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40042 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40042 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40042 : ENTITY IS TRUE; + + end lut40042; + + architecture Structure of lut40042 is + begin + INST10: ROM16X1A + generic map (initval => X"1F1F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40043 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40043 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40043 : ENTITY IS TRUE; + + end lut40043; + + architecture Structure of lut40043 is + begin + INST10: ROM16X1A + generic map (initval => X"5540") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity selmux2 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity selmux2 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF selmux2 : ENTITY IS TRUE; + + end selmux2; + + architecture Structure of selmux2 is + begin + INST1: MUX21 + port map (D0=>D0, D1=>D1, SD=>SD, Z=>Z); + end Structure; + +-- entity i30_SLICE_71 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity i30_SLICE_71 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "i30_SLICE_71"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF i30_SLICE_71 : ENTITY IS TRUE; + + end i30_SLICE_71; + + architecture Structure of i30_SLICE_71 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal i30_SLICE_71_i30_SLICE_71_K1_H1: Std_logic; + signal i30_SLICE_71_i30_GATE_H0: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40042 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40043 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + begin + i30_SLICE_71_K1: lut40042 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, + Z=>i30_SLICE_71_i30_SLICE_71_K1_H1); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i30_GATE: lut40043 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, + Z=>i30_SLICE_71_i30_GATE_H0); + i30_SLICE_71_K0K1MUX: selmux2 + port map (D0=>i30_SLICE_71_i30_GATE_H0, + D1=>i30_SLICE_71_i30_SLICE_71_K1_H1, SD=>M0_ipd, Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M0_ipd, OFX0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + OFX0_zd := OFX0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 7 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40044 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40044 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40044 : ENTITY IS TRUE; + + end lut40044; + + architecture Structure of lut40044 is + begin + INST10: ROM16X1A + generic map (initval => X"FF40") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_72 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_72 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_72"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_72 : ENTITY IS TRUE; + + end SLICE_72; + + architecture Structure of SLICE_72 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40044 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_4_lut_4_lut_adj_12: lut40044 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i2_2_lut: lut40039 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_73 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_73 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_73"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_73 : ENTITY IS TRUE; + + end SLICE_73; + + architecture Structure of SLICE_73 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40003 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40010 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_4_lut_adj_14: lut40003 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i4_4_lut: lut40010 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40045 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40045 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40045 : ENTITY IS TRUE; + + end lut40045; + + architecture Structure of lut40045 is + begin + INST10: ROM16X1A + generic map (initval => X"0020") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_74 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_74 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_74"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_74 : ENTITY IS TRUE; + + end SLICE_74; + + architecture Structure of SLICE_74 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40033 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40045 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i12_4_lut: lut40033 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut_3_lut_4_lut: lut40045 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RowA_i1: vmuxregsre0004 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i0: vmuxregsre0004 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, + Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_75 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_75 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_75"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_75 : ENTITY IS TRUE; + + end SLICE_75; + + architecture Structure of SLICE_75 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40027 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40038 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i3_4_lut_adj_18: lut40027 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut: lut40038 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_FSM_i9: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i8: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_76 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_76 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_76"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_76 : ENTITY IS TRUE; + + end SLICE_76; + + architecture Structure of SLICE_76 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component vmuxregsre0007 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40012 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40026 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_19_3_lut: lut40012 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1_2_lut_rep_15_4_lut: lut40026 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RowA_i9: vmuxregsre0007 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i8: vmuxregsre0004 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40046 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40046 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40046 : ENTITY IS TRUE; + + end lut40046; + + architecture Structure of lut40046 is + begin + INST10: ROM16X1A + generic map (initval => X"0800") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_77 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_77 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_77"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_77 : ENTITY IS TRUE; + + end SLICE_77; + + architecture Structure of SLICE_77 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40046 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i3_4_lut_adj_22: lut40046 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i3_4_lut: lut40046 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40047 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40047 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40047 : ENTITY IS TRUE; + + end lut40047; + + architecture Structure of lut40047 is + begin + INST10: ROM16X1A + generic map (initval => X"F0DD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40048 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40048 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40048 : ENTITY IS TRUE; + + end lut40048; + + architecture Structure of lut40048 is + begin + INST10: ROM16X1A + generic map (initval => X"DDDD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_78 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_78 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_78"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_78 : ENTITY IS TRUE; + + end SLICE_78; + + architecture Structure of SLICE_78 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40047 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40048 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRCS_N_146_bdd_4_lut: lut40047 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1423_2_lut: lut40048 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_FSM_i13: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i12: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40049 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40049 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40049 : ENTITY IS TRUE; + + end lut40049; + + architecture Structure of lut40049 is + begin + INST10: ROM16X1A + generic map (initval => X"0200") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_79 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_79 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_79"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_79 : ENTITY IS TRUE; + + end SLICE_79; + + architecture Structure of SLICE_79 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40016 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40049 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i11_3_lut_rep_20: lut40016 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_c_0_bdd_4_lut: lut40049 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + IS_FSM_i11: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i10: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40050 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40050 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40050 : ENTITY IS TRUE; + + end lut40050; + + architecture Structure of lut40050 is + begin + INST10: ROM16X1A + generic map (initval => X"0001") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_80 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_80 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_80"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_80 : ENTITY IS TRUE; + + end SLICE_80; + + architecture Structure of SLICE_80 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40050 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i3_2_lut_rep_26: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2005_3_lut_rep_17_4_lut: lut40050 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40051 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40051 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40051 : ENTITY IS TRUE; + + end lut40051; + + architecture Structure of lut40051 is + begin + INST10: ROM16X1A + generic map (initval => X"FCDD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_81 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_81 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_81"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_81 : ENTITY IS TRUE; + + end SLICE_81; + + architecture Structure of SLICE_81 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40051 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_29: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1427_4_lut: lut40051 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + IS_FSM_i15: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i14: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40052 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40052 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40052 : ENTITY IS TRUE; + + end lut40052; + + architecture Structure of lut40052 is + begin + INST10: ROM16X1A + generic map (initval => X"8000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_82 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_82 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_82"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_82 : ENTITY IS TRUE; + + end SLICE_82; + + architecture Structure of SLICE_82 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component vmuxregsre0007 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40052 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i6_4_lut: lut40052 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut_adj_3: lut40039 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RowA_i5: vmuxregsre0007 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i4: vmuxregsre0004 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40053 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40053 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40053 : ENTITY IS TRUE; + + end lut40053; + + architecture Structure of lut40053 is + begin + INST10: ROM16X1A + generic map (initval => X"0004") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40054 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40054 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40054 : ENTITY IS TRUE; + + end lut40054; + + architecture Structure of lut40054 is + begin + INST10: ROM16X1A + generic map (initval => X"FFDF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_83 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_83 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_83"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_83 : ENTITY IS TRUE; + + end SLICE_83; + + architecture Structure of SLICE_83 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40053 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40054 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_4_lut_adj_21: lut40053 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i2_3_lut_4_lut_adj_6: lut40054 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40055 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40055 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40055 : ENTITY IS TRUE; + + end lut40055; + + architecture Structure of lut40055 is + begin + INST10: ROM16X1A + generic map (initval => X"2020") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_84 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_84 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_84"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_84 : ENTITY IS TRUE; + + end SLICE_84; + + architecture Structure of SLICE_84 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40024 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40055 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_rep_28: lut40055 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1573_4_lut: lut40024 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + IS_FSM_i3: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i2: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40056 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40056 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40056 : ENTITY IS TRUE; + + end lut40056; + + architecture Structure of lut40056 is + begin + INST10: ROM16X1A + generic map (initval => X"FFEF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_85 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_85 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_85"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_85 : ENTITY IS TRUE; + + end SLICE_85; + + architecture Structure of SLICE_85 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40040 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40056 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1969_2_lut_3_lut_4_lut: lut40056 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i3_4_lut_adj_7: lut40040 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_86 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_86 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_86"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_86 : ENTITY IS TRUE; + + end SLICE_86; + + architecture Structure of SLICE_86 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40012 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i5_3_lut: lut40012 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1_4_lut_adj_8: lut4 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RASr3_381: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + PHI2r_376: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_87 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_87 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_87"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_87 : ENTITY IS TRUE; + + end SLICE_87; + + architecture Structure of SLICE_87 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40040 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40048 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i4_4_lut_adj_16: lut40040 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut_2_lut: lut40048 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RBA_i2: vmuxregsre0004 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RBA_i1: vmuxregsre0004 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40057 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40057 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40057 : ENTITY IS TRUE; + + end lut40057; + + architecture Structure of lut40057 is + begin + INST10: ROM16X1A + generic map (initval => X"C0C5") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_88 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_88 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_88"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_88 : ENTITY IS TRUE; + + end SLICE_88; + + architecture Structure of SLICE_88 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40053 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40057 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i34_4_lut: lut40057 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_4_lut_adj_13: lut40053 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + WRD_i7: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + WRD_i6: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40058 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40058 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40058 : ENTITY IS TRUE; + + end lut40058; + + architecture Structure of lut40058 is + begin + INST10: ROM16X1A + generic map (initval => X"8088") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40059 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40059 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40059 : ENTITY IS TRUE; + + end lut40059; + + architecture Structure of lut40059 is + begin + INST10: ROM16X1A + generic map (initval => X"C444") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_89 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_89 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_89"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_89 : ENTITY IS TRUE; + + end SLICE_89; + + architecture Structure of SLICE_89 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40058 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40059 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_4_lut: lut40058 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_4_lut: lut40059 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + WRD_i5: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + WRD_i4: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_90 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_90 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_90"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_90 : ENTITY IS TRUE; + + end SLICE_90; + + architecture Structure of SLICE_90 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40049 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40055 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_3_lut_4_lut_adj_1: lut40049 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut_rep_21_3_lut: lut40055 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + WRD_i1: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + WRD_i0: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40060 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40060 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40060 : ENTITY IS TRUE; + + end lut40060; + + architecture Structure of lut40060 is + begin + INST10: ROM16X1A + generic map (initval => X"DFDF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40061 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40061 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40061 : ENTITY IS TRUE; + + end lut40061; + + architecture Structure of lut40061 is + begin + INST10: ROM16X1A + generic map (initval => X"DFFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_91 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_91 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_91"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_91 : ENTITY IS TRUE; + + end SLICE_91; + + architecture Structure of SLICE_91 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40060 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40061 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_13_3_lut: lut40060 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1_2_lut_3_lut_4_lut_adj_5: lut40061 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RowA_i3: vmuxregsre0004 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i2: vmuxregsre0004 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40062 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40062 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40062 : ENTITY IS TRUE; + + end lut40062; + + architecture Structure of lut40062 is + begin + INST10: ROM16X1A + generic map (initval => X"0080") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_92 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_92 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_92"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_92 : ENTITY IS TRUE; + + end SLICE_92; + + architecture Structure of SLICE_92 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40005 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40062 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2008_2_lut_4_lut: lut40062 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut_rep_22_4_lut: lut40005 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + WRD_i3: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + WRD_i2: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40063 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40063 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40063 : ENTITY IS TRUE; + + end lut40063; + + architecture Structure of lut40063 is + begin + INST10: ROM16X1A + generic map (initval => X"7777") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_93 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_93 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_93"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_93 : ENTITY IS TRUE; + + end SLICE_93; + + architecture Structure of SLICE_93 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40063 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2001_2_lut: lut40063 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_9_I_0_427_i10_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + Bank_i1: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + Bank_i0: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, + M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40064 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40064 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40064 : ENTITY IS TRUE; + + end lut40064; + + architecture Structure of lut40064 is + begin + INST10: ROM16X1A + generic map (initval => X"FFFD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_94 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_94 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_94"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_94 : ENTITY IS TRUE; + + end SLICE_94; + + architecture Structure of SLICE_94 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40048 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40064 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i771_2_lut_rep_23_2_lut: lut40048 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_3_lut_4_lut_4_lut: lut40064 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40065 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40065 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40065 : ENTITY IS TRUE; + + end lut40065; + + architecture Structure of lut40065 is + begin + INST10: ROM16X1A + generic map (initval => X"1404") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_95 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_95 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_95"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_95 : ENTITY IS TRUE; + + end SLICE_95; + + architecture Structure of SLICE_95 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40040 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40065 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_4_lut_adj_20: lut40065 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i6_4_lut_adj_9: lut40040 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_96 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_96 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_96"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_96 : ENTITY IS TRUE; + + end SLICE_96; + + architecture Structure of SLICE_96 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40027 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_27: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_3_lut_4_lut_adj_24: lut40027 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40066 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40066 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40066 : ENTITY IS TRUE; + + end lut40066; + + architecture Structure of lut40066 is + begin + INST10: ROM16X1A + generic map (initval => X"C5C5") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_97 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_97 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_97"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_97 : ENTITY IS TRUE; + + end SLICE_97; + + architecture Structure of SLICE_97 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40066 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i13_3_lut: lut40066 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1956_2_lut: lut40034 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + IS_FSM_i7: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i6: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, M1_dly, + M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_98 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_98 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_98"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_98 : ENTITY IS TRUE; + + end SLICE_98; + + architecture Structure of SLICE_98 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40037 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1416_2_lut: lut40037 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_9_I_0_427_i9_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + IS_FSM_i1: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i0: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, + M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_99 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_99 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_99"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_99 : ENTITY IS TRUE; + + end SLICE_99; + + architecture Structure of SLICE_99 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40052 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i8_4_lut: lut40052 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + MAin_9_I_0_427_i8_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CmdUFMSDI_414: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_100 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_100 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_100"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_100 : ENTITY IS TRUE; + + end SLICE_100; + + architecture Structure of SLICE_100 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40052 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1979_4_lut: lut40052 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + MAin_9_I_0_427_i7_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CmdUFMCS_412: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + CmdUFMCLK_413: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_101 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_101 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_101"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_101 : ENTITY IS TRUE; + + end SLICE_101; + + architecture Structure of SLICE_101 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i1_3_lut: lut40021 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_9_I_0_427_i6_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + Bank_i7: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + Bank_i6: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_102 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_102 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_102"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_102 : ENTITY IS TRUE; + + end SLICE_102; + + architecture Structure of SLICE_102 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i2_3_lut: lut40021 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_9_I_0_427_i5_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + Bank_i5: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + Bank_i4: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_103 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_103 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_103"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_103 : ENTITY IS TRUE; + + end SLICE_103; + + architecture Structure of SLICE_103 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i3_3_lut: lut40021 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_9_I_0_427_i4_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + Bank_i3: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + Bank_i2: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40067 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40067 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40067 : ENTITY IS TRUE; + + end lut40067; + + architecture Structure of lut40067 is + begin + INST10: ROM16X1A + generic map (initval => X"FDFD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_104 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_104 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_104"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_104 : ENTITY IS TRUE; + + end SLICE_104; + + architecture Structure of SLICE_104 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40067 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1417_2_lut: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1_2_lut_rep_14_3_lut: lut40067 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + RowA_i7: vmuxregsre0004 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i6: vmuxregsre0004 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, + M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_105 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_105 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_105"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_105 : ENTITY IS TRUE; + + end SLICE_105; + + architecture Structure of SLICE_105 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40052 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_adj_19: lut40039 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i5_4_lut: lut40052 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_106 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_106 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_106"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_106 : ENTITY IS TRUE; + + end SLICE_106; + + architecture Structure of SLICE_106 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_33: lut40039 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1930_2_lut: lut40034 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + IS_FSM_i5: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i4: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, + CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity xo2iobuf + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity xo2iobuf is + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + + ATTRIBUTE Vital_Level0 OF xo2iobuf : ENTITY IS TRUE; + + end xo2iobuf; + + architecture Structure of xo2iobuf is + begin + INST1: IBPD + port map (I=>PADI, O=>Z); + INST2: OBZPD + port map (I=>I, T=>T, O=>PAD); + end Structure; + +-- entity RD_7_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_7_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD7 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD7_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD7 : VitalDelayType := 0 ns; + tpw_RD7_posedge : VitalDelayType := 0 ns; + tpw_RD7_negedge : VitalDelayType := 0 ns; + tpd_RD7_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD7: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_7_B : ENTITY IS TRUE; + + end RD_7_B; + + architecture Structure of RD_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD7_ipd : std_logic := 'X'; + signal RD7_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_7_713: xo2iobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD7_out, + PADI=>RD7_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD7_ipd, RD7, tipd_RD7); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD7_ipd, RD7_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD7_zd : std_logic := 'X'; + VARIABLE RD7_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD7_RD7 : x01 := '0'; + VARIABLE periodcheckinfo_RD7 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD7_ipd, + TestSignalName => "RD7", + Period => tperiod_RD7, + PulseWidthHigh => tpw_RD7_posedge, + PulseWidthLow => tpw_RD7_negedge, + PeriodData => periodcheckinfo_RD7, + Violation => tviol_RD7_RD7, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD7_zd := RD7_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD7_ipd'last_event, + PathDelay => tpd_RD7_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD7, OutSignalName => "RD7", OutTemp => RD7_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD7, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD7, + PathCondition => TRUE)), + GlitchData => RD7_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_6_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_6_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD6 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD6_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD6 : VitalDelayType := 0 ns; + tpw_RD6_posedge : VitalDelayType := 0 ns; + tpw_RD6_negedge : VitalDelayType := 0 ns; + tpd_RD6_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD6: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_6_B : ENTITY IS TRUE; + + end RD_6_B; + + architecture Structure of RD_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD6_ipd : std_logic := 'X'; + signal RD6_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_6_714: xo2iobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD6_out, + PADI=>RD6_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD6_ipd, RD6, tipd_RD6); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD6_ipd, RD6_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD6_zd : std_logic := 'X'; + VARIABLE RD6_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD6_RD6 : x01 := '0'; + VARIABLE periodcheckinfo_RD6 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD6_ipd, + TestSignalName => "RD6", + Period => tperiod_RD6, + PulseWidthHigh => tpw_RD6_posedge, + PulseWidthLow => tpw_RD6_negedge, + PeriodData => periodcheckinfo_RD6, + Violation => tviol_RD6_RD6, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD6_zd := RD6_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD6_ipd'last_event, + PathDelay => tpd_RD6_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD6, OutSignalName => "RD6", OutTemp => RD6_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD6, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD6, + PathCondition => TRUE)), + GlitchData => RD6_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_5_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_5_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD5 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD5_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD5 : VitalDelayType := 0 ns; + tpw_RD5_posedge : VitalDelayType := 0 ns; + tpw_RD5_negedge : VitalDelayType := 0 ns; + tpd_RD5_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD5: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_5_B : ENTITY IS TRUE; + + end RD_5_B; + + architecture Structure of RD_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD5_ipd : std_logic := 'X'; + signal RD5_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_5_715: xo2iobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD5_out, + PADI=>RD5_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD5_ipd, RD5, tipd_RD5); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD5_ipd, RD5_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD5_zd : std_logic := 'X'; + VARIABLE RD5_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD5_RD5 : x01 := '0'; + VARIABLE periodcheckinfo_RD5 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD5_ipd, + TestSignalName => "RD5", + Period => tperiod_RD5, + PulseWidthHigh => tpw_RD5_posedge, + PulseWidthLow => tpw_RD5_negedge, + PeriodData => periodcheckinfo_RD5, + Violation => tviol_RD5_RD5, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD5_zd := RD5_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD5_ipd'last_event, + PathDelay => tpd_RD5_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD5, OutSignalName => "RD5", OutTemp => RD5_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD5, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD5, + PathCondition => TRUE)), + GlitchData => RD5_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_4_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_4_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD4 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD4_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD4 : VitalDelayType := 0 ns; + tpw_RD4_posedge : VitalDelayType := 0 ns; + tpw_RD4_negedge : VitalDelayType := 0 ns; + tpd_RD4_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD4: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_4_B : ENTITY IS TRUE; + + end RD_4_B; + + architecture Structure of RD_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD4_ipd : std_logic := 'X'; + signal RD4_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_4_716: xo2iobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD4_out, + PADI=>RD4_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD4_ipd, RD4, tipd_RD4); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD4_ipd, RD4_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD4_zd : std_logic := 'X'; + VARIABLE RD4_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD4_RD4 : x01 := '0'; + VARIABLE periodcheckinfo_RD4 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD4_ipd, + TestSignalName => "RD4", + Period => tperiod_RD4, + PulseWidthHigh => tpw_RD4_posedge, + PulseWidthLow => tpw_RD4_negedge, + PeriodData => periodcheckinfo_RD4, + Violation => tviol_RD4_RD4, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD4_zd := RD4_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD4_ipd'last_event, + PathDelay => tpd_RD4_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD4, OutSignalName => "RD4", OutTemp => RD4_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD4, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD4, + PathCondition => TRUE)), + GlitchData => RD4_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_3_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_3_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD3 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD3_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD3 : VitalDelayType := 0 ns; + tpw_RD3_posedge : VitalDelayType := 0 ns; + tpw_RD3_negedge : VitalDelayType := 0 ns; + tpd_RD3_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD3: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_3_B : ENTITY IS TRUE; + + end RD_3_B; + + architecture Structure of RD_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD3_ipd : std_logic := 'X'; + signal RD3_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_3_717: xo2iobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD3_out, + PADI=>RD3_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD3_ipd, RD3, tipd_RD3); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD3_ipd, RD3_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD3_zd : std_logic := 'X'; + VARIABLE RD3_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD3_RD3 : x01 := '0'; + VARIABLE periodcheckinfo_RD3 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD3_ipd, + TestSignalName => "RD3", + Period => tperiod_RD3, + PulseWidthHigh => tpw_RD3_posedge, + PulseWidthLow => tpw_RD3_negedge, + PeriodData => periodcheckinfo_RD3, + Violation => tviol_RD3_RD3, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD3_zd := RD3_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD3_ipd'last_event, + PathDelay => tpd_RD3_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD3, OutSignalName => "RD3", OutTemp => RD3_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD3, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD3, + PathCondition => TRUE)), + GlitchData => RD3_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_2_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_2_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD2 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD2_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD2 : VitalDelayType := 0 ns; + tpw_RD2_posedge : VitalDelayType := 0 ns; + tpw_RD2_negedge : VitalDelayType := 0 ns; + tpd_RD2_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD2: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_2_B : ENTITY IS TRUE; + + end RD_2_B; + + architecture Structure of RD_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD2_ipd : std_logic := 'X'; + signal RD2_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_2_718: xo2iobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD2_out, + PADI=>RD2_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD2_ipd, RD2, tipd_RD2); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD2_ipd, RD2_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD2_zd : std_logic := 'X'; + VARIABLE RD2_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD2_RD2 : x01 := '0'; + VARIABLE periodcheckinfo_RD2 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD2_ipd, + TestSignalName => "RD2", + Period => tperiod_RD2, + PulseWidthHigh => tpw_RD2_posedge, + PulseWidthLow => tpw_RD2_negedge, + PeriodData => periodcheckinfo_RD2, + Violation => tviol_RD2_RD2, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD2_zd := RD2_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD2_ipd'last_event, + PathDelay => tpd_RD2_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD2, OutSignalName => "RD2", OutTemp => RD2_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD2, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD2, + PathCondition => TRUE)), + GlitchData => RD2_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_1_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD1 : VitalDelayType := 0 ns; + tpw_RD1_posedge : VitalDelayType := 0 ns; + tpw_RD1_negedge : VitalDelayType := 0 ns; + tpd_RD1_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD1: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_1_B : ENTITY IS TRUE; + + end RD_1_B; + + architecture Structure of RD_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD1_ipd : std_logic := 'X'; + signal RD1_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_1_719: xo2iobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD1_out, + PADI=>RD1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD1_ipd, RD1, tipd_RD1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD1_ipd, RD1_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD1_zd : std_logic := 'X'; + VARIABLE RD1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD1_RD1 : x01 := '0'; + VARIABLE periodcheckinfo_RD1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD1_ipd, + TestSignalName => "RD1", + Period => tperiod_RD1, + PulseWidthHigh => tpw_RD1_posedge, + PulseWidthLow => tpw_RD1_negedge, + PeriodData => periodcheckinfo_RD1, + Violation => tviol_RD1_RD1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD1_zd := RD1_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD1_ipd'last_event, + PathDelay => tpd_RD1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD1, OutSignalName => "RD1", OutTemp => RD1_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD1, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD1, + PathCondition => TRUE)), + GlitchData => RD1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_0_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD0 : VitalDelayType := 0 ns; + tpw_RD0_posedge : VitalDelayType := 0 ns; + tpw_RD0_negedge : VitalDelayType := 0 ns; + tpd_RD0_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD0: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_0_B : ENTITY IS TRUE; + + end RD_0_B; + + architecture Structure of RD_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD0_ipd : std_logic := 'X'; + signal RD0_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_0_720: xo2iobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD0_out, + PADI=>RD0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD0_ipd, RD0, tipd_RD0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD0_ipd, RD0_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD0_zd : std_logic := 'X'; + VARIABLE RD0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD0_RD0 : x01 := '0'; + VARIABLE periodcheckinfo_RD0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD0_ipd, + TestSignalName => "RD0", + Period => tperiod_RD0, + PulseWidthHigh => tpw_RD0_posedge, + PulseWidthLow => tpw_RD0_negedge, + PeriodData => periodcheckinfo_RD0, + Violation => tviol_RD0_RD0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD0_zd := RD0_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD0_ipd'last_event, + PathDelay => tpd_RD0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD0, OutSignalName => "RD0", OutTemp => RD0_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD0, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD0, + PathCondition => TRUE)), + GlitchData => RD0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity xo2iobuf0068 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity xo2iobuf0068 is + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + + ATTRIBUTE Vital_Level0 OF xo2iobuf0068 : ENTITY IS TRUE; + + end xo2iobuf0068; + + architecture Structure of xo2iobuf0068 is + begin + INST5: OBZPD + port map (I=>I, T=>T, O=>PAD); + end Structure; + +-- entity Dout_7_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_7_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout7 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout7: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_7_B : ENTITY IS TRUE; + + end Dout_7_B; + + architecture Structure of Dout_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout7_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_7: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout7_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout7_out) + VARIABLE Dout7_zd : std_logic := 'X'; + VARIABLE Dout7_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout7_zd := Dout7_out; + + VitalPathDelay01 ( + OutSignal => Dout7, OutSignalName => "Dout7", OutTemp => Dout7_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout7, + PathCondition => TRUE)), + GlitchData => Dout7_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_6_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_6_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout6 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout6: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_6_B : ENTITY IS TRUE; + + end Dout_6_B; + + architecture Structure of Dout_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout6_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_6: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout6_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout6_out) + VARIABLE Dout6_zd : std_logic := 'X'; + VARIABLE Dout6_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout6_zd := Dout6_out; + + VitalPathDelay01 ( + OutSignal => Dout6, OutSignalName => "Dout6", OutTemp => Dout6_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout6, + PathCondition => TRUE)), + GlitchData => Dout6_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_5_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_5_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout5 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout5: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_5_B : ENTITY IS TRUE; + + end Dout_5_B; + + architecture Structure of Dout_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout5_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_5: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout5_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout5_out) + VARIABLE Dout5_zd : std_logic := 'X'; + VARIABLE Dout5_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout5_zd := Dout5_out; + + VitalPathDelay01 ( + OutSignal => Dout5, OutSignalName => "Dout5", OutTemp => Dout5_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout5, + PathCondition => TRUE)), + GlitchData => Dout5_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_4_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_4_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout4 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout4: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_4_B : ENTITY IS TRUE; + + end Dout_4_B; + + architecture Structure of Dout_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout4_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_4: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout4_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout4_out) + VARIABLE Dout4_zd : std_logic := 'X'; + VARIABLE Dout4_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout4_zd := Dout4_out; + + VitalPathDelay01 ( + OutSignal => Dout4, OutSignalName => "Dout4", OutTemp => Dout4_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout4, + PathCondition => TRUE)), + GlitchData => Dout4_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_3_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_3_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout3 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout3: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_3_B : ENTITY IS TRUE; + + end Dout_3_B; + + architecture Structure of Dout_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout3_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_3: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout3_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout3_out) + VARIABLE Dout3_zd : std_logic := 'X'; + VARIABLE Dout3_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout3_zd := Dout3_out; + + VitalPathDelay01 ( + OutSignal => Dout3, OutSignalName => "Dout3", OutTemp => Dout3_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout3, + PathCondition => TRUE)), + GlitchData => Dout3_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_2_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_2_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout2 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout2: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_2_B : ENTITY IS TRUE; + + end Dout_2_B; + + architecture Structure of Dout_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout2_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_2: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout2_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout2_out) + VARIABLE Dout2_zd : std_logic := 'X'; + VARIABLE Dout2_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout2_zd := Dout2_out; + + VitalPathDelay01 ( + OutSignal => Dout2, OutSignalName => "Dout2", OutTemp => Dout2_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout2, + PathCondition => TRUE)), + GlitchData => Dout2_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_1_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout1 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_1_B : ENTITY IS TRUE; + + end Dout_1_B; + + architecture Structure of Dout_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_1: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout1_out) + VARIABLE Dout1_zd : std_logic := 'X'; + VARIABLE Dout1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout1_zd := Dout1_out; + + VitalPathDelay01 ( + OutSignal => Dout1, OutSignalName => "Dout1", OutTemp => Dout1_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout1, + PathCondition => TRUE)), + GlitchData => Dout1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_0_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_0_B : ENTITY IS TRUE; + + end Dout_0_B; + + architecture Structure of Dout_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_0: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout0_out) + VARIABLE Dout0_zd : std_logic := 'X'; + VARIABLE Dout0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout0_zd := Dout0_out; + + VitalPathDelay01 ( + OutSignal => Dout0, OutSignalName => "Dout0", OutTemp => Dout0_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout0, + PathCondition => TRUE)), + GlitchData => Dout0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity LEDB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity LEDB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "LEDB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_LEDS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; LEDS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF LEDB : ENTITY IS TRUE; + + end LEDB; + + architecture Structure of LEDB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal LEDS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + LED_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>LEDS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, LEDS_out) + VARIABLE LEDS_zd : std_logic := 'X'; + VARIABLE LEDS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + LEDS_zd := LEDS_out; + + VitalPathDelay01 ( + OutSignal => LEDS, OutSignalName => "LEDS", OutTemp => LEDS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_LEDS, + PathCondition => TRUE)), + GlitchData => LEDS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RBA_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RBA_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RBA_1_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RBA1 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RBA1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RBA_1_B : ENTITY IS TRUE; + + end RBA_1_B; + + architecture Structure of RBA_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RBA1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RBA_pad_1: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RBA1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RBA1_out) + VARIABLE RBA1_zd : std_logic := 'X'; + VARIABLE RBA1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RBA1_zd := RBA1_out; + + VitalPathDelay01 ( + OutSignal => RBA1, OutSignalName => "RBA1", OutTemp => RBA1_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RBA1, + PathCondition => TRUE)), + GlitchData => RBA1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RBA_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RBA_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RBA_0_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RBA0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RBA0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RBA_0_B : ENTITY IS TRUE; + + end RBA_0_B; + + architecture Structure of RBA_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RBA0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RBA_pad_0: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RBA0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RBA0_out) + VARIABLE RBA0_zd : std_logic := 'X'; + VARIABLE RBA0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RBA0_zd := RBA0_out; + + VitalPathDelay01 ( + OutSignal => RBA0, OutSignalName => "RBA0", OutTemp => RBA0_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RBA0, + PathCondition => TRUE)), + GlitchData => RBA0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_11_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_11_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_11_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA11 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA11: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_11_B : ENTITY IS TRUE; + + end RA_11_B; + + architecture Structure of RA_11_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA11_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_11: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA11_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA11_out) + VARIABLE RA11_zd : std_logic := 'X'; + VARIABLE RA11_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA11_zd := RA11_out; + + VitalPathDelay01 ( + OutSignal => RA11, OutSignalName => "RA11", OutTemp => RA11_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA11, + PathCondition => TRUE)), + GlitchData => RA11_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_10_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_10_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_10_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA10 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA10: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_10_B : ENTITY IS TRUE; + + end RA_10_B; + + architecture Structure of RA_10_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA10_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_10: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA10_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA10_out) + VARIABLE RA10_zd : std_logic := 'X'; + VARIABLE RA10_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA10_zd := RA10_out; + + VitalPathDelay01 ( + OutSignal => RA10, OutSignalName => "RA10", OutTemp => RA10_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA10, + PathCondition => TRUE)), + GlitchData => RA10_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_9_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_9_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_9_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA9 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA9: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_9_B : ENTITY IS TRUE; + + end RA_9_B; + + architecture Structure of RA_9_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA9_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_9: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA9_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA9_out) + VARIABLE RA9_zd : std_logic := 'X'; + VARIABLE RA9_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA9_zd := RA9_out; + + VitalPathDelay01 ( + OutSignal => RA9, OutSignalName => "RA9", OutTemp => RA9_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA9, + PathCondition => TRUE)), + GlitchData => RA9_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_8_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_8_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_8_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA8 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA8: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_8_B : ENTITY IS TRUE; + + end RA_8_B; + + architecture Structure of RA_8_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA8_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_8: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA8_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA8_out) + VARIABLE RA8_zd : std_logic := 'X'; + VARIABLE RA8_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA8_zd := RA8_out; + + VitalPathDelay01 ( + OutSignal => RA8, OutSignalName => "RA8", OutTemp => RA8_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA8, + PathCondition => TRUE)), + GlitchData => RA8_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_7_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_7_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA7 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA7: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_7_B : ENTITY IS TRUE; + + end RA_7_B; + + architecture Structure of RA_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA7_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_7: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA7_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA7_out) + VARIABLE RA7_zd : std_logic := 'X'; + VARIABLE RA7_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA7_zd := RA7_out; + + VitalPathDelay01 ( + OutSignal => RA7, OutSignalName => "RA7", OutTemp => RA7_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA7, + PathCondition => TRUE)), + GlitchData => RA7_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_6_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_6_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA6 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA6: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_6_B : ENTITY IS TRUE; + + end RA_6_B; + + architecture Structure of RA_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA6_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_6: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA6_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA6_out) + VARIABLE RA6_zd : std_logic := 'X'; + VARIABLE RA6_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA6_zd := RA6_out; + + VitalPathDelay01 ( + OutSignal => RA6, OutSignalName => "RA6", OutTemp => RA6_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA6, + PathCondition => TRUE)), + GlitchData => RA6_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_5_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_5_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA5 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA5: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_5_B : ENTITY IS TRUE; + + end RA_5_B; + + architecture Structure of RA_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA5_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_5: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA5_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA5_out) + VARIABLE RA5_zd : std_logic := 'X'; + VARIABLE RA5_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA5_zd := RA5_out; + + VitalPathDelay01 ( + OutSignal => RA5, OutSignalName => "RA5", OutTemp => RA5_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA5, + PathCondition => TRUE)), + GlitchData => RA5_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_4_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_4_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA4 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA4: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_4_B : ENTITY IS TRUE; + + end RA_4_B; + + architecture Structure of RA_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA4_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_4: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA4_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA4_out) + VARIABLE RA4_zd : std_logic := 'X'; + VARIABLE RA4_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA4_zd := RA4_out; + + VitalPathDelay01 ( + OutSignal => RA4, OutSignalName => "RA4", OutTemp => RA4_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA4, + PathCondition => TRUE)), + GlitchData => RA4_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_3_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_3_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA3 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA3: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_3_B : ENTITY IS TRUE; + + end RA_3_B; + + architecture Structure of RA_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA3_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_3: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA3_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA3_out) + VARIABLE RA3_zd : std_logic := 'X'; + VARIABLE RA3_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA3_zd := RA3_out; + + VitalPathDelay01 ( + OutSignal => RA3, OutSignalName => "RA3", OutTemp => RA3_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA3, + PathCondition => TRUE)), + GlitchData => RA3_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_2_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_2_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA2 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA2: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_2_B : ENTITY IS TRUE; + + end RA_2_B; + + architecture Structure of RA_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA2_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_2: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA2_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA2_out) + VARIABLE RA2_zd : std_logic := 'X'; + VARIABLE RA2_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA2_zd := RA2_out; + + VitalPathDelay01 ( + OutSignal => RA2, OutSignalName => "RA2", OutTemp => RA2_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA2, + PathCondition => TRUE)), + GlitchData => RA2_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_1_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA1 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_1_B : ENTITY IS TRUE; + + end RA_1_B; + + architecture Structure of RA_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_1: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA1_out) + VARIABLE RA1_zd : std_logic := 'X'; + VARIABLE RA1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA1_zd := RA1_out; + + VitalPathDelay01 ( + OutSignal => RA1, OutSignalName => "RA1", OutTemp => RA1_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA1, + PathCondition => TRUE)), + GlitchData => RA1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_0_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_0_B : ENTITY IS TRUE; + + end RA_0_B; + + architecture Structure of RA_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_0: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA0_out) + VARIABLE RA0_zd : std_logic := 'X'; + VARIABLE RA0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA0_zd := RA0_out; + + VitalPathDelay01 ( + OutSignal => RA0, OutSignalName => "RA0", OutTemp => RA0_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA0, + PathCondition => TRUE)), + GlitchData => RA0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRCSB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRCSB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRCSB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nRCSS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; nRCSS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRCSB : ENTITY IS TRUE; + + end nRCSB; + + architecture Structure of nRCSB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nRCSS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nRCS_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRCSS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nRCSS_out) + VARIABLE nRCSS_zd : std_logic := 'X'; + VARIABLE nRCSS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRCSS_zd := nRCSS_out; + + VitalPathDelay01 ( + OutSignal => nRCSS, OutSignalName => "nRCSS", OutTemp => nRCSS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nRCSS, + PathCondition => TRUE)), + GlitchData => nRCSS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RCKEB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RCKEB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RCKEB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RCKES : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RCKES: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RCKEB : ENTITY IS TRUE; + + end RCKEB; + + architecture Structure of RCKEB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RCKES_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RCKE_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RCKES_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RCKES_out) + VARIABLE RCKES_zd : std_logic := 'X'; + VARIABLE RCKES_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RCKES_zd := RCKES_out; + + VitalPathDelay01 ( + OutSignal => RCKES, OutSignalName => "RCKES", OutTemp => RCKES_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RCKES, + PathCondition => TRUE)), + GlitchData => RCKES_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRWEB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRWEB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRWEB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nRWES : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; nRWES: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRWEB : ENTITY IS TRUE; + + end nRWEB; + + architecture Structure of nRWEB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nRWES_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nRWE_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRWES_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nRWES_out) + VARIABLE nRWES_zd : std_logic := 'X'; + VARIABLE nRWES_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRWES_zd := nRWES_out; + + VitalPathDelay01 ( + OutSignal => nRWES, OutSignalName => "nRWES", OutTemp => nRWES_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nRWES, + PathCondition => TRUE)), + GlitchData => nRWES_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRRASB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRRASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRRASB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nRRASS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; nRRASS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRRASB : ENTITY IS TRUE; + + end nRRASB; + + architecture Structure of nRRASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nRRASS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nRRAS_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRRASS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nRRASS_out) + VARIABLE nRRASS_zd : std_logic := 'X'; + VARIABLE nRRASS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRRASS_zd := nRRASS_out; + + VitalPathDelay01 ( + OutSignal => nRRASS, OutSignalName => "nRRASS", OutTemp => nRRASS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nRRASS, + PathCondition => TRUE)), + GlitchData => nRRASS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRCASB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRCASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRCASB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nRCASS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; nRCASS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRCASB : ENTITY IS TRUE; + + end nRCASB; + + architecture Structure of nRCASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nRCASS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nRCAS_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRCASS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nRCASS_out) + VARIABLE nRCASS_zd : std_logic := 'X'; + VARIABLE nRCASS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRCASS_zd := nRCASS_out; + + VitalPathDelay01 ( + OutSignal => nRCASS, OutSignalName => "nRCASS", OutTemp => nRCASS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nRCASS, + PathCondition => TRUE)), + GlitchData => nRCASS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RDQMHB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RDQMHB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RDQMHB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RDQMHS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RDQMHS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RDQMHB : ENTITY IS TRUE; + + end RDQMHB; + + architecture Structure of RDQMHB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RDQMHS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RDQMH_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RDQMHS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RDQMHS_out) + VARIABLE RDQMHS_zd : std_logic := 'X'; + VARIABLE RDQMHS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RDQMHS_zd := RDQMHS_out; + + VitalPathDelay01 ( + OutSignal => RDQMHS, OutSignalName => "RDQMHS", OutTemp => RDQMHS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RDQMHS, + PathCondition => TRUE)), + GlitchData => RDQMHS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RDQMLB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RDQMLB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RDQMLB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RDQMLS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RDQMLS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RDQMLB : ENTITY IS TRUE; + + end RDQMLB; + + architecture Structure of RDQMLB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RDQMLS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RDQML_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RDQMLS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RDQMLS_out) + VARIABLE RDQMLS_zd : std_logic := 'X'; + VARIABLE RDQMLS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RDQMLS_zd := RDQMLS_out; + + VitalPathDelay01 ( + OutSignal => RDQMLS, OutSignalName => "RDQMLS", OutTemp => RDQMLS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RDQMLS, + PathCondition => TRUE)), + GlitchData => RDQMLS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nUFMCSB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nUFMCSB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nUFMCSB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nUFMCSS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; nUFMCSS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nUFMCSB : ENTITY IS TRUE; + + end nUFMCSB; + + architecture Structure of nUFMCSB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nUFMCSS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nUFMCS_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nUFMCSS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nUFMCSS_out) + VARIABLE nUFMCSS_zd : std_logic := 'X'; + VARIABLE nUFMCSS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nUFMCSS_zd := nUFMCSS_out; + + VitalPathDelay01 ( + OutSignal => nUFMCSS, OutSignalName => "nUFMCSS", OutTemp => nUFMCSS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nUFMCSS, + PathCondition => TRUE)), + GlitchData => nUFMCSS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity UFMCLKB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity UFMCLKB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "UFMCLKB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_UFMCLKS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; UFMCLKS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF UFMCLKB : ENTITY IS TRUE; + + end UFMCLKB; + + architecture Structure of UFMCLKB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal UFMCLKS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + UFMCLK_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>UFMCLKS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, UFMCLKS_out) + VARIABLE UFMCLKS_zd : std_logic := 'X'; + VARIABLE UFMCLKS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + UFMCLKS_zd := UFMCLKS_out; + + VitalPathDelay01 ( + OutSignal => UFMCLKS, OutSignalName => "UFMCLKS", OutTemp => UFMCLKS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_UFMCLKS, + PathCondition => TRUE)), + GlitchData => UFMCLKS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity UFMSDIB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity UFMSDIB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "UFMSDIB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_UFMSDIS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; UFMSDIS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF UFMSDIB : ENTITY IS TRUE; + + end UFMSDIB; + + architecture Structure of UFMSDIB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal UFMSDIS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + UFMSDI_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>UFMSDIS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, UFMSDIS_out) + VARIABLE UFMSDIS_zd : std_logic := 'X'; + VARIABLE UFMSDIS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + UFMSDIS_zd := UFMSDIS_out; + + VitalPathDelay01 ( + OutSignal => UFMSDIS, OutSignalName => "UFMSDIS", OutTemp => UFMSDIS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_UFMSDIS, + PathCondition => TRUE)), + GlitchData => UFMSDIS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity xo2iobuf0069 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity xo2iobuf0069 is + port (Z: out Std_logic; PAD: in Std_logic); + + ATTRIBUTE Vital_Level0 OF xo2iobuf0069 : ENTITY IS TRUE; + + end xo2iobuf0069; + + architecture Structure of xo2iobuf0069 is + begin + INST1: IBPD + port map (I=>PAD, O=>Z); + end Structure; + +-- entity PHI2B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity PHI2B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "PHI2B"; + + tipd_PHI2S : VitalDelayType01 := (0 ns, 0 ns); + tpd_PHI2S_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_PHI2S : VitalDelayType := 0 ns; + tpw_PHI2S_posedge : VitalDelayType := 0 ns; + tpw_PHI2S_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; PHI2S: in Std_logic); + + ATTRIBUTE Vital_Level0 OF PHI2B : ENTITY IS TRUE; + + end PHI2B; + + architecture Structure of PHI2B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PHI2S_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + PHI2_pad: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>PHI2S_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PHI2S_ipd, PHI2S, tipd_PHI2S); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PHI2S_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_PHI2S_PHI2S : x01 := '0'; + VARIABLE periodcheckinfo_PHI2S : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => PHI2S_ipd, + TestSignalName => "PHI2S", + Period => tperiod_PHI2S, + PulseWidthHigh => tpw_PHI2S_posedge, + PulseWidthLow => tpw_PHI2S_negedge, + PeriodData => periodcheckinfo_PHI2S, + Violation => tviol_PHI2S_PHI2S, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => PHI2S_ipd'last_event, + PathDelay => tpd_PHI2S_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_9_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_9_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_9_B"; + + tipd_MAin9 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin9_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin9 : VitalDelayType := 0 ns; + tpw_MAin9_posedge : VitalDelayType := 0 ns; + tpw_MAin9_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin9: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_9_B : ENTITY IS TRUE; + + end MAin_9_B; + + architecture Structure of MAin_9_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin9_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_9: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin9_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin9_ipd, MAin9, tipd_MAin9); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin9_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin9_MAin9 : x01 := '0'; + VARIABLE periodcheckinfo_MAin9 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin9_ipd, + TestSignalName => "MAin9", + Period => tperiod_MAin9, + PulseWidthHigh => tpw_MAin9_posedge, + PulseWidthLow => tpw_MAin9_negedge, + PeriodData => periodcheckinfo_MAin9, + Violation => tviol_MAin9_MAin9, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin9_ipd'last_event, + PathDelay => tpd_MAin9_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_8_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_8_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_8_B"; + + tipd_MAin8 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin8_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin8 : VitalDelayType := 0 ns; + tpw_MAin8_posedge : VitalDelayType := 0 ns; + tpw_MAin8_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin8: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_8_B : ENTITY IS TRUE; + + end MAin_8_B; + + architecture Structure of MAin_8_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin8_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_8: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin8_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin8_ipd, MAin8, tipd_MAin8); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin8_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin8_MAin8 : x01 := '0'; + VARIABLE periodcheckinfo_MAin8 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin8_ipd, + TestSignalName => "MAin8", + Period => tperiod_MAin8, + PulseWidthHigh => tpw_MAin8_posedge, + PulseWidthLow => tpw_MAin8_negedge, + PeriodData => periodcheckinfo_MAin8, + Violation => tviol_MAin8_MAin8, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin8_ipd'last_event, + PathDelay => tpd_MAin8_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_7_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_7_B"; + + tipd_MAin7 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin7_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin7 : VitalDelayType := 0 ns; + tpw_MAin7_posedge : VitalDelayType := 0 ns; + tpw_MAin7_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin7: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_7_B : ENTITY IS TRUE; + + end MAin_7_B; + + architecture Structure of MAin_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin7_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_7: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin7_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin7_ipd, MAin7, tipd_MAin7); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin7_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin7_MAin7 : x01 := '0'; + VARIABLE periodcheckinfo_MAin7 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin7_ipd, + TestSignalName => "MAin7", + Period => tperiod_MAin7, + PulseWidthHigh => tpw_MAin7_posedge, + PulseWidthLow => tpw_MAin7_negedge, + PeriodData => periodcheckinfo_MAin7, + Violation => tviol_MAin7_MAin7, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin7_ipd'last_event, + PathDelay => tpd_MAin7_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_6_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_6_B"; + + tipd_MAin6 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin6_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin6 : VitalDelayType := 0 ns; + tpw_MAin6_posedge : VitalDelayType := 0 ns; + tpw_MAin6_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin6: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_6_B : ENTITY IS TRUE; + + end MAin_6_B; + + architecture Structure of MAin_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin6_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_6: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin6_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin6_ipd, MAin6, tipd_MAin6); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin6_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin6_MAin6 : x01 := '0'; + VARIABLE periodcheckinfo_MAin6 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin6_ipd, + TestSignalName => "MAin6", + Period => tperiod_MAin6, + PulseWidthHigh => tpw_MAin6_posedge, + PulseWidthLow => tpw_MAin6_negedge, + PeriodData => periodcheckinfo_MAin6, + Violation => tviol_MAin6_MAin6, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin6_ipd'last_event, + PathDelay => tpd_MAin6_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_5_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_5_B"; + + tipd_MAin5 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin5_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin5 : VitalDelayType := 0 ns; + tpw_MAin5_posedge : VitalDelayType := 0 ns; + tpw_MAin5_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin5: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_5_B : ENTITY IS TRUE; + + end MAin_5_B; + + architecture Structure of MAin_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin5_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_5: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin5_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin5_ipd, MAin5, tipd_MAin5); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin5_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin5_MAin5 : x01 := '0'; + VARIABLE periodcheckinfo_MAin5 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin5_ipd, + TestSignalName => "MAin5", + Period => tperiod_MAin5, + PulseWidthHigh => tpw_MAin5_posedge, + PulseWidthLow => tpw_MAin5_negedge, + PeriodData => periodcheckinfo_MAin5, + Violation => tviol_MAin5_MAin5, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin5_ipd'last_event, + PathDelay => tpd_MAin5_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_4_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_4_B"; + + tipd_MAin4 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin4_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin4 : VitalDelayType := 0 ns; + tpw_MAin4_posedge : VitalDelayType := 0 ns; + tpw_MAin4_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin4: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_4_B : ENTITY IS TRUE; + + end MAin_4_B; + + architecture Structure of MAin_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin4_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_4: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin4_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin4_ipd, MAin4, tipd_MAin4); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin4_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin4_MAin4 : x01 := '0'; + VARIABLE periodcheckinfo_MAin4 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin4_ipd, + TestSignalName => "MAin4", + Period => tperiod_MAin4, + PulseWidthHigh => tpw_MAin4_posedge, + PulseWidthLow => tpw_MAin4_negedge, + PeriodData => periodcheckinfo_MAin4, + Violation => tviol_MAin4_MAin4, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin4_ipd'last_event, + PathDelay => tpd_MAin4_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_3_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_3_B"; + + tipd_MAin3 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin3_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin3 : VitalDelayType := 0 ns; + tpw_MAin3_posedge : VitalDelayType := 0 ns; + tpw_MAin3_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin3: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_3_B : ENTITY IS TRUE; + + end MAin_3_B; + + architecture Structure of MAin_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin3_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_3: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin3_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin3_ipd, MAin3, tipd_MAin3); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin3_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin3_MAin3 : x01 := '0'; + VARIABLE periodcheckinfo_MAin3 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin3_ipd, + TestSignalName => "MAin3", + Period => tperiod_MAin3, + PulseWidthHigh => tpw_MAin3_posedge, + PulseWidthLow => tpw_MAin3_negedge, + PeriodData => periodcheckinfo_MAin3, + Violation => tviol_MAin3_MAin3, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin3_ipd'last_event, + PathDelay => tpd_MAin3_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_2_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_2_B"; + + tipd_MAin2 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin2_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin2 : VitalDelayType := 0 ns; + tpw_MAin2_posedge : VitalDelayType := 0 ns; + tpw_MAin2_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin2: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_2_B : ENTITY IS TRUE; + + end MAin_2_B; + + architecture Structure of MAin_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin2_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_2: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin2_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin2_ipd, MAin2, tipd_MAin2); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin2_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin2_MAin2 : x01 := '0'; + VARIABLE periodcheckinfo_MAin2 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin2_ipd, + TestSignalName => "MAin2", + Period => tperiod_MAin2, + PulseWidthHigh => tpw_MAin2_posedge, + PulseWidthLow => tpw_MAin2_negedge, + PeriodData => periodcheckinfo_MAin2, + Violation => tviol_MAin2_MAin2, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin2_ipd'last_event, + PathDelay => tpd_MAin2_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_1_B"; + + tipd_MAin1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin1 : VitalDelayType := 0 ns; + tpw_MAin1_posedge : VitalDelayType := 0 ns; + tpw_MAin1_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin1: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_1_B : ENTITY IS TRUE; + + end MAin_1_B; + + architecture Structure of MAin_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin1_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_1: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin1_ipd, MAin1, tipd_MAin1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin1_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin1_MAin1 : x01 := '0'; + VARIABLE periodcheckinfo_MAin1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin1_ipd, + TestSignalName => "MAin1", + Period => tperiod_MAin1, + PulseWidthHigh => tpw_MAin1_posedge, + PulseWidthLow => tpw_MAin1_negedge, + PeriodData => periodcheckinfo_MAin1, + Violation => tviol_MAin1_MAin1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin1_ipd'last_event, + PathDelay => tpd_MAin1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_0_B"; + + tipd_MAin0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin0 : VitalDelayType := 0 ns; + tpw_MAin0_posedge : VitalDelayType := 0 ns; + tpw_MAin0_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin0: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_0_B : ENTITY IS TRUE; + + end MAin_0_B; + + architecture Structure of MAin_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin0_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_0: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin0_ipd, MAin0, tipd_MAin0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin0_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin0_MAin0 : x01 := '0'; + VARIABLE periodcheckinfo_MAin0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin0_ipd, + TestSignalName => "MAin0", + Period => tperiod_MAin0, + PulseWidthHigh => tpw_MAin0_posedge, + PulseWidthLow => tpw_MAin0_negedge, + PeriodData => periodcheckinfo_MAin0, + Violation => tviol_MAin0_MAin0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin0_ipd'last_event, + PathDelay => tpd_MAin0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity CROW_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity CROW_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "CROW_1_B"; + + tipd_CROW1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CROW1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CROW1 : VitalDelayType := 0 ns; + tpw_CROW1_posedge : VitalDelayType := 0 ns; + tpw_CROW1_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; CROW1: in Std_logic); + + ATTRIBUTE Vital_Level0 OF CROW_1_B : ENTITY IS TRUE; + + end CROW_1_B; + + architecture Structure of CROW_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal CROW1_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + CROW_pad_1: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>CROW1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(CROW1_ipd, CROW1, tipd_CROW1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, CROW1_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_CROW1_CROW1 : x01 := '0'; + VARIABLE periodcheckinfo_CROW1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => CROW1_ipd, + TestSignalName => "CROW1", + Period => tperiod_CROW1, + PulseWidthHigh => tpw_CROW1_posedge, + PulseWidthLow => tpw_CROW1_negedge, + PeriodData => periodcheckinfo_CROW1, + Violation => tviol_CROW1_CROW1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => CROW1_ipd'last_event, + PathDelay => tpd_CROW1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity CROW_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity CROW_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "CROW_0_B"; + + tipd_CROW0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CROW0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CROW0 : VitalDelayType := 0 ns; + tpw_CROW0_posedge : VitalDelayType := 0 ns; + tpw_CROW0_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; CROW0: in Std_logic); + + ATTRIBUTE Vital_Level0 OF CROW_0_B : ENTITY IS TRUE; + + end CROW_0_B; + + architecture Structure of CROW_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal CROW0_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + CROW_pad_0: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>CROW0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(CROW0_ipd, CROW0, tipd_CROW0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, CROW0_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_CROW0_CROW0 : x01 := '0'; + VARIABLE periodcheckinfo_CROW0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => CROW0_ipd, + TestSignalName => "CROW0", + Period => tperiod_CROW0, + PulseWidthHigh => tpw_CROW0_posedge, + PulseWidthLow => tpw_CROW0_negedge, + PeriodData => periodcheckinfo_CROW0, + Violation => tviol_CROW0_CROW0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => CROW0_ipd'last_event, + PathDelay => tpd_CROW0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_7_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_7_B"; + + tipd_Din7 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din7_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din7 : VitalDelayType := 0 ns; + tpw_Din7_posedge : VitalDelayType := 0 ns; + tpw_Din7_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din7: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_7_B : ENTITY IS TRUE; + + end Din_7_B; + + architecture Structure of Din_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din7_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_7: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>Din7_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din7_ipd, Din7, tipd_Din7); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din7_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din7_Din7 : x01 := '0'; + VARIABLE periodcheckinfo_Din7 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din7_ipd, + TestSignalName => "Din7", + Period => tperiod_Din7, + PulseWidthHigh => tpw_Din7_posedge, + PulseWidthLow => tpw_Din7_negedge, + PeriodData => periodcheckinfo_Din7, + Violation => tviol_Din7_Din7, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din7_ipd'last_event, + PathDelay => tpd_Din7_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_6_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_6_B"; + + tipd_Din6 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din6_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din6 : VitalDelayType := 0 ns; + tpw_Din6_posedge : VitalDelayType := 0 ns; + tpw_Din6_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din6: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_6_B : ENTITY IS TRUE; + + end Din_6_B; + + architecture Structure of Din_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din6_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_6: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>Din6_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din6_ipd, Din6, tipd_Din6); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din6_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din6_Din6 : x01 := '0'; + VARIABLE periodcheckinfo_Din6 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din6_ipd, + TestSignalName => "Din6", + Period => tperiod_Din6, + PulseWidthHigh => tpw_Din6_posedge, + PulseWidthLow => tpw_Din6_negedge, + PeriodData => periodcheckinfo_Din6, + Violation => tviol_Din6_Din6, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din6_ipd'last_event, + PathDelay => tpd_Din6_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_5_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_5_B"; + + tipd_Din5 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din5_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din5 : VitalDelayType := 0 ns; + tpw_Din5_posedge : VitalDelayType := 0 ns; + tpw_Din5_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din5: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_5_B : ENTITY IS TRUE; + + end Din_5_B; + + architecture Structure of Din_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din5_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_5: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>Din5_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din5_ipd, Din5, tipd_Din5); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din5_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din5_Din5 : x01 := '0'; + VARIABLE periodcheckinfo_Din5 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din5_ipd, + TestSignalName => "Din5", + Period => tperiod_Din5, + PulseWidthHigh => tpw_Din5_posedge, + PulseWidthLow => tpw_Din5_negedge, + PeriodData => periodcheckinfo_Din5, + Violation => tviol_Din5_Din5, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din5_ipd'last_event, + PathDelay => tpd_Din5_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_4_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_4_B"; + + tipd_Din4 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din4_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din4 : VitalDelayType := 0 ns; + tpw_Din4_posedge : VitalDelayType := 0 ns; + tpw_Din4_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din4: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_4_B : ENTITY IS TRUE; + + end Din_4_B; + + architecture Structure of Din_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din4_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_4: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>Din4_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din4_ipd, Din4, tipd_Din4); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din4_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din4_Din4 : x01 := '0'; + VARIABLE periodcheckinfo_Din4 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din4_ipd, + TestSignalName => "Din4", + Period => tperiod_Din4, + PulseWidthHigh => tpw_Din4_posedge, + PulseWidthLow => tpw_Din4_negedge, + PeriodData => periodcheckinfo_Din4, + Violation => tviol_Din4_Din4, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din4_ipd'last_event, + PathDelay => tpd_Din4_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_3_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_3_B"; + + tipd_Din3 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din3_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din3 : VitalDelayType := 0 ns; + tpw_Din3_posedge : VitalDelayType := 0 ns; + tpw_Din3_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din3: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_3_B : ENTITY IS TRUE; + + end Din_3_B; + + architecture Structure of Din_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din3_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_3: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>Din3_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din3_ipd, Din3, tipd_Din3); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din3_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din3_Din3 : x01 := '0'; + VARIABLE periodcheckinfo_Din3 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din3_ipd, + TestSignalName => "Din3", + Period => tperiod_Din3, + PulseWidthHigh => tpw_Din3_posedge, + PulseWidthLow => tpw_Din3_negedge, + PeriodData => periodcheckinfo_Din3, + Violation => tviol_Din3_Din3, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din3_ipd'last_event, + PathDelay => tpd_Din3_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_2_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_2_B"; + + tipd_Din2 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din2_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din2 : VitalDelayType := 0 ns; + tpw_Din2_posedge : VitalDelayType := 0 ns; + tpw_Din2_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din2: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_2_B : ENTITY IS TRUE; + + end Din_2_B; + + architecture Structure of Din_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din2_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_2: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>Din2_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din2_ipd, Din2, tipd_Din2); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din2_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din2_Din2 : x01 := '0'; + VARIABLE periodcheckinfo_Din2 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din2_ipd, + TestSignalName => "Din2", + Period => tperiod_Din2, + PulseWidthHigh => tpw_Din2_posedge, + PulseWidthLow => tpw_Din2_negedge, + PeriodData => periodcheckinfo_Din2, + Violation => tviol_Din2_Din2, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din2_ipd'last_event, + PathDelay => tpd_Din2_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_1_B"; + + tipd_Din1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din1 : VitalDelayType := 0 ns; + tpw_Din1_posedge : VitalDelayType := 0 ns; + tpw_Din1_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din1: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_1_B : ENTITY IS TRUE; + + end Din_1_B; + + architecture Structure of Din_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din1_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_1: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>Din1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din1_ipd, Din1, tipd_Din1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din1_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din1_Din1 : x01 := '0'; + VARIABLE periodcheckinfo_Din1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din1_ipd, + TestSignalName => "Din1", + Period => tperiod_Din1, + PulseWidthHigh => tpw_Din1_posedge, + PulseWidthLow => tpw_Din1_negedge, + PeriodData => periodcheckinfo_Din1, + Violation => tviol_Din1_Din1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din1_ipd'last_event, + PathDelay => tpd_Din1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_0_B"; + + tipd_Din0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din0 : VitalDelayType := 0 ns; + tpw_Din0_posedge : VitalDelayType := 0 ns; + tpw_Din0_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din0: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_0_B : ENTITY IS TRUE; + + end Din_0_B; + + architecture Structure of Din_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din0_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_0: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>Din0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din0_ipd, Din0, tipd_Din0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din0_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din0_Din0 : x01 := '0'; + VARIABLE periodcheckinfo_Din0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din0_ipd, + TestSignalName => "Din0", + Period => tperiod_Din0, + PulseWidthHigh => tpw_Din0_posedge, + PulseWidthLow => tpw_Din0_negedge, + PeriodData => periodcheckinfo_Din0, + Violation => tviol_Din0_Din0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din0_ipd'last_event, + PathDelay => tpd_Din0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nCCASB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nCCASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nCCASB"; + + tipd_nCCASS : VitalDelayType01 := (0 ns, 0 ns); + tpd_nCCASS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nCCASS : VitalDelayType := 0 ns; + tpw_nCCASS_posedge : VitalDelayType := 0 ns; + tpw_nCCASS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; nCCASS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nCCASB : ENTITY IS TRUE; + + end nCCASB; + + architecture Structure of nCCASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal nCCASS_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + nCCAS_pad: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>nCCASS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(nCCASS_ipd, nCCASS, tipd_nCCASS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, nCCASS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_nCCASS_nCCASS : x01 := '0'; + VARIABLE periodcheckinfo_nCCASS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => nCCASS_ipd, + TestSignalName => "nCCASS", + Period => tperiod_nCCASS, + PulseWidthHigh => tpw_nCCASS_posedge, + PulseWidthLow => tpw_nCCASS_negedge, + PeriodData => periodcheckinfo_nCCASS, + Violation => tviol_nCCASS_nCCASS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => nCCASS_ipd'last_event, + PathDelay => tpd_nCCASS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nCRASB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nCRASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nCRASB"; + + tipd_nCRASS : VitalDelayType01 := (0 ns, 0 ns); + tpd_nCRASS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nCRASS : VitalDelayType := 0 ns; + tpw_nCRASS_posedge : VitalDelayType := 0 ns; + tpw_nCRASS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; nCRASS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nCRASB : ENTITY IS TRUE; + + end nCRASB; + + architecture Structure of nCRASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal nCRASS_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + nCRAS_pad: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>nCRASS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(nCRASS_ipd, nCRASS, tipd_nCRASS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, nCRASS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_nCRASS_nCRASS : x01 := '0'; + VARIABLE periodcheckinfo_nCRASS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => nCRASS_ipd, + TestSignalName => "nCRASS", + Period => tperiod_nCRASS, + PulseWidthHigh => tpw_nCRASS_posedge, + PulseWidthLow => tpw_nCRASS_negedge, + PeriodData => periodcheckinfo_nCRASS, + Violation => tviol_nCRASS_nCRASS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => nCRASS_ipd'last_event, + PathDelay => tpd_nCRASS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nFWEB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nFWEB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nFWEB"; + + tipd_nFWES : VitalDelayType01 := (0 ns, 0 ns); + tpd_nFWES_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nFWES : VitalDelayType := 0 ns; + tpw_nFWES_posedge : VitalDelayType := 0 ns; + tpw_nFWES_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; nFWES: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nFWEB : ENTITY IS TRUE; + + end nFWEB; + + architecture Structure of nFWEB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal nFWES_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + nFWE_pad: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>nFWES_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(nFWES_ipd, nFWES, tipd_nFWES); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, nFWES_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_nFWES_nFWES : x01 := '0'; + VARIABLE periodcheckinfo_nFWES : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => nFWES_ipd, + TestSignalName => "nFWES", + Period => tperiod_nFWES, + PulseWidthHigh => tpw_nFWES_posedge, + PulseWidthLow => tpw_nFWES_negedge, + PeriodData => periodcheckinfo_nFWES, + Violation => tviol_nFWES_nFWES, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => nFWES_ipd'last_event, + PathDelay => tpd_nFWES_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RCLKB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RCLKB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RCLKB"; + + tipd_RCLKS : VitalDelayType01 := (0 ns, 0 ns); + tpd_RCLKS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RCLKS : VitalDelayType := 0 ns; + tpw_RCLKS_posedge : VitalDelayType := 0 ns; + tpw_RCLKS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; RCLKS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RCLKB : ENTITY IS TRUE; + + end RCLKB; + + architecture Structure of RCLKB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal RCLKS_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + RCLK_pad: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>RCLKS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(RCLKS_ipd, RCLKS, tipd_RCLKS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, RCLKS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RCLKS_RCLKS : x01 := '0'; + VARIABLE periodcheckinfo_RCLKS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RCLKS_ipd, + TestSignalName => "RCLKS", + Period => tperiod_RCLKS, + PulseWidthHigh => tpw_RCLKS_posedge, + PulseWidthLow => tpw_RCLKS_negedge, + PeriodData => periodcheckinfo_RCLKS, + Violation => tviol_RCLKS_RCLKS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RCLKS_ipd'last_event, + PathDelay => tpd_RCLKS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity UFMSDOB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity UFMSDOB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "UFMSDOB"; + + tipd_UFMSDOS : VitalDelayType01 := (0 ns, 0 ns); + tpd_UFMSDOS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_UFMSDOS : VitalDelayType := 0 ns; + tpw_UFMSDOS_posedge : VitalDelayType := 0 ns; + tpw_UFMSDOS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; UFMSDOS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF UFMSDOB : ENTITY IS TRUE; + + end UFMSDOB; + + architecture Structure of UFMSDOB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal UFMSDOS_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + UFMSDO_pad: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>UFMSDOS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(UFMSDOS_ipd, UFMSDOS, tipd_UFMSDOS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, UFMSDOS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_UFMSDOS_UFMSDOS : x01 := '0'; + VARIABLE periodcheckinfo_UFMSDOS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => UFMSDOS_ipd, + TestSignalName => "UFMSDOS", + Period => tperiod_UFMSDOS, + PulseWidthHigh => tpw_UFMSDOS_posedge, + PulseWidthLow => tpw_UFMSDOS_negedge, + PeriodData => periodcheckinfo_UFMSDOS, + Violation => tviol_UFMSDOS_UFMSDOS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => UFMSDOS_ipd'last_event, + PathDelay => tpd_UFMSDOS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RAM2GS + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RAM2GS is + port (PHI2: in Std_logic; MAin: in Std_logic_vector (9 downto 0); + CROW: in Std_logic_vector (1 downto 0); + Din: in Std_logic_vector (7 downto 0); + Dout: out Std_logic_vector (7 downto 0); nCCAS: in Std_logic; + nCRAS: in Std_logic; nFWE: in Std_logic; LED: out Std_logic; + RBA: out Std_logic_vector (1 downto 0); + RA: out Std_logic_vector (11 downto 0); + RD: inout Std_logic_vector (7 downto 0); nRCS: out Std_logic; + RCLK: in Std_logic; RCKE: out Std_logic; nRWE: out Std_logic; + nRRAS: out Std_logic; nRCAS: out Std_logic; RDQMH: out Std_logic; + RDQML: out Std_logic; nUFMCS: out Std_logic; UFMCLK: out Std_logic; + UFMSDI: out Std_logic; UFMSDO: in Std_logic); + + + + end RAM2GS; + + architecture Structure of RAM2GS is + signal FS_14: Std_logic; + signal FS_13: Std_logic; + signal n81: Std_logic; + signal n82: Std_logic; + signal RCLK_c: Std_logic; + signal n1998: Std_logic; + signal n1999: Std_logic; + signal FS_12: Std_logic; + signal FS_11: Std_logic; + signal n83: Std_logic; + signal n84: Std_logic; + signal n1997: Std_logic; + signal FS_8: Std_logic; + signal FS_7: Std_logic; + signal n87: Std_logic; + signal n88: Std_logic; + signal n1995: Std_logic; + signal n1996: Std_logic; + signal FS_6: Std_logic; + signal FS_5: Std_logic; + signal n89: Std_logic; + signal n90: Std_logic; + signal n1994: Std_logic; + signal FS_2: Std_logic; + signal FS_1: Std_logic; + signal n93: Std_logic; + signal n94: Std_logic; + signal n1992: Std_logic; + signal n1993: Std_logic; + signal FS_0: Std_logic; + signal n95: Std_logic; + signal CASr2: Std_logic; + signal CASr3: Std_logic; + signal FS_10: Std_logic; + signal FS_9: Std_logic; + signal n85: Std_logic; + signal n86: Std_logic; + signal FS_17: Std_logic; + signal n78: Std_logic; + signal n2000: Std_logic; + signal FS_4: Std_logic; + signal FS_3: Std_logic; + signal n91: Std_logic; + signal n92: Std_logic; + signal FS_16: Std_logic; + signal FS_15: Std_logic; + signal n79: Std_logic; + signal n80: Std_logic; + signal Din_c_4: Std_logic; + signal Din_c_6: Std_logic; + signal Din_c_1: Std_logic; + signal Din_c_7: Std_logic; + signal n2382: Std_logic; + signal n8: Std_logic; + signal n2225: Std_logic; + signal n2180: Std_logic; + signal ADSubmitted_N_246: Std_logic; + signal PHI2_N_120_enable_2: Std_logic; + signal C1Submitted_N_237: Std_logic; + signal PHI2_c: Std_logic; + signal ADSubmitted: Std_logic; + signal n26: Std_logic; + signal MAin_c_5: Std_logic; + signal n22: Std_logic; + signal MAin_c_2: Std_logic; + signal MAin_c_1: Std_logic; + signal C1Submitted: Std_logic; + signal n2365: Std_logic; + signal nFWE_c: Std_logic; + signal n1398: Std_logic; + signal nCCAS_c: Std_logic; + signal nCCAS_N_3: Std_logic; + signal CASr: Std_logic; + signal n2254: Std_logic; + signal Din_c_5: Std_logic; + signal n2191: Std_logic; + signal n2183: Std_logic; + signal n15_adj_1: Std_logic; + signal n2208: Std_logic; + signal n2363: Std_logic; + signal CmdEnable_N_248: Std_logic; + signal PHI2_N_120_enable_1: Std_logic; + signal CmdEnable: Std_logic; + signal n2447_001_BUF1: Std_logic; + signal PHI2_N_120_enable_7: Std_logic; + signal CmdSubmitted: Std_logic; + signal n1314: Std_logic; + signal n8MEGEN: Std_logic; + signal Din_c_0: Std_logic; + signal Cmdn8MEGEN_N_264: Std_logic; + signal PHI2_N_120_enable_6: Std_logic; + signal Cmdn8MEGEN: Std_logic; + signal Din_c_3: Std_logic; + signal n2373: Std_logic; + signal nCRAS_c: Std_logic; + signal FWEr: Std_logic; + signal CBR: Std_logic; + signal n2447_000_BUF1: Std_logic; + signal RCLK_c_enable_28: Std_logic; + signal InitReady: Std_logic; + signal n2447: Std_logic; + signal RCLK_c_enable_16: Std_logic; + signal LEDEN: Std_logic; + signal nCRAS_c_inv: Std_logic; + signal RASr: Std_logic; + signal LED_c: Std_logic; + signal RASr2: Std_logic; + signal nRowColSel_N_35: Std_logic; + signal nRCAS_N_165: Std_logic; + signal Ready: Std_logic; + signal n2381: Std_logic; + signal nRCS_N_139: Std_logic; + signal n2036: Std_logic; + signal nRWE_N_177: Std_logic; + signal RA_0S: Std_logic; + signal XOR8MEG: Std_logic; + signal RA11_N_184: Std_logic; + signal RA_c: Std_logic; + signal n6_adj_2: Std_logic; + signal PHI2r2: Std_logic; + signal PHI2r3: Std_logic; + signal n15_adj_4: Std_logic; + signal RCKEEN_N_121: Std_logic; + signal RCLK_c_enable_6: Std_logic; + signal RCKEEN: Std_logic; + signal RCLK_c_enable_10: Std_logic; + signal RASr3: Std_logic; + signal RCKE_N_132: Std_logic; + signal PHI2r: Std_logic; + signal RCKE_c: Std_logic; + signal n2447_002_BUF1: Std_logic; + signal Ready_N_292: Std_logic; + signal n2267: Std_logic; + signal n13_adj_6: Std_logic; + signal CmdUFMCLK: Std_logic; + signal n1893: Std_logic; + signal UFMCLK_N_224: Std_logic; + signal n2366: Std_logic; + signal UFMCLK_c: Std_logic; + signal n10: Std_logic; + signal n7: Std_logic; + signal n4: Std_logic; + signal CmdUFMSDI: Std_logic; + signal n2174: Std_logic; + signal UFMSDI_N_231: Std_logic; + signal UFMSDI_c: Std_logic; + signal n2260: Std_logic; + signal Din_c_2: Std_logic; + signal XOR8MEG_N_110: Std_logic; + signal PHI2_N_120_enable_3: Std_logic; + signal n2375: Std_logic; + signal UFMSDO_c: Std_logic; + signal n2367: Std_logic; + signal n8MEGEN_N_91: Std_logic; + signal RCLK_c_enable_15: Std_logic; + signal nRCS_N_142: Std_logic; + signal nRCAS_N_166: Std_logic; + signal n2371: Std_logic; + signal nRCAS_N_161: Std_logic; + signal nRCAS_c: Std_logic; + signal nRCS_N_141: Std_logic; + signal nRCS_N_137: Std_logic; + signal nRCS_N_136: Std_logic; + signal nRCS_c: Std_logic; + signal n2379: Std_logic; + signal nRRAS_N_156: Std_logic; + signal nRRAS_c: Std_logic; + signal nRWE_N_178: Std_logic; + signal n1765: Std_logic; + signal nRWE_N_171: Std_logic; + signal RCLK_c_enable_5: Std_logic; + signal nRWE_c: Std_logic; + signal nRowColSel_N_34: Std_logic; + signal nRowColSel_N_33: Std_logic; + signal n2376: Std_logic; + signal n1060: Std_logic; + signal n2372: Std_logic; + signal n917: Std_logic; + signal nRowColSel: Std_logic; + signal nRowColSel_N_32: Std_logic; + signal n827: Std_logic; + signal n2227: Std_logic; + signal n1406: Std_logic; + signal Bank_3: Std_logic; + signal Bank_6: Std_logic; + signal n2287: Std_logic; + signal n13: Std_logic; + signal n2374: Std_logic; + signal n2368: Std_logic; + signal CmdUFMCS: Std_logic; + signal n64: Std_logic; + signal nUFMCS_N_199: Std_logic; + signal nUFMCS_c: Std_logic; + signal n6_adj_3: Std_logic; + signal Ready_N_296: Std_logic; + signal n2204: Std_logic; + signal n2369: Std_logic; + signal MAin_c_0: Std_logic; + signal PHI2_N_120_enable_8: Std_logic; + signal Bank_5: Std_logic; + signal n2277: Std_logic; + signal Bank_2: Std_logic; + signal n2220: Std_logic; + signal RowA_0: Std_logic; + signal RowA_1: Std_logic; + signal n2370: Std_logic; + signal n2228: Std_logic; + signal n732: Std_logic; + signal n733: Std_logic; + signal RCLK_c_enable_27: Std_logic; + signal n2055: Std_logic; + signal MAin_c_9: Std_logic; + signal MAin_c_8: Std_logic; + signal RowA_8: Std_logic; + signal RowA_9: Std_logic; + signal n2210: Std_logic; + signal nRWE_N_182: Std_logic; + signal nRCS_N_146: Std_logic; + signal n728: Std_logic; + signal n729: Std_logic; + signal n727: Std_logic; + signal n730: Std_logic; + signal n2378: Std_logic; + signal n726: Std_logic; + signal n12: Std_logic; + signal MAin_c_4: Std_logic; + signal RowA_4: Std_logic; + signal RowA_5: Std_logic; + signal n1277: Std_logic; + signal n4_adj_7: Std_logic; + signal n2377: Std_logic; + signal n738: Std_logic; + signal n737: Std_logic; + signal n14: Std_logic; + signal n15: Std_logic; + signal n6: Std_logic; + signal CROW_c_1: Std_logic; + signal CROW_c_0: Std_logic; + signal RBA_c_0: Std_logic; + signal RBA_c_1: Std_logic; + signal n7_adj_5: Std_logic; + signal n2362: Std_logic; + signal WRD_6: Std_logic; + signal WRD_7: Std_logic; + signal WRD_4: Std_logic; + signal WRD_5: Std_logic; + signal WRD_0: Std_logic; + signal WRD_1: Std_logic; + signal MAin_c_3: Std_logic; + signal RowA_2: Std_logic; + signal RowA_3: Std_logic; + signal WRD_2: Std_logic; + signal WRD_3: Std_logic; + signal RA_1_9: Std_logic; + signal Bank_0: Std_logic; + signal RDQML_c: Std_logic; + signal Bank_1: Std_logic; + signal n734: Std_logic; + signal n735: Std_logic; + signal RA_1_8: Std_logic; + signal RDQMH_c: Std_logic; + signal Bank_4: Std_logic; + signal MAin_c_7: Std_logic; + signal RowA_7: Std_logic; + signal RA_1_7: Std_logic; + signal Bank_7: Std_logic; + signal MAin_c_6: Std_logic; + signal RowA_6: Std_logic; + signal RA_1_6: Std_logic; + signal RA_1_5: Std_logic; + signal RA_1_0: Std_logic; + signal RA_1_4: Std_logic; + signal RA_1_1: Std_logic; + signal RA_1_3: Std_logic; + signal RA_1_2: Std_logic; + signal n984: Std_logic; + signal n736: Std_logic; + signal Dout_c: Std_logic; + signal Dout_0S: Std_logic; + signal Dout_1S: Std_logic; + signal Dout_2S: Std_logic; + signal Dout_3S: Std_logic; + signal Dout_4S: Std_logic; + signal Dout_5S: Std_logic; + signal Dout_6S: Std_logic; + signal VCCI: Std_logic; + component SLICE_0 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_1 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_2 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_3 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_4 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_5 + port (A1: in Std_logic; DI1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_6 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_7 + port (A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_8 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_9 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_10 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_15 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_16 + port (A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_19 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_20 + port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_24 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_25 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_26 + port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_27 + port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_30 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_32 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_33 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_35 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_36 + port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_37 + port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_44 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_45 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_50 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_57 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_59 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_61 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_62 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_64 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_65 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_66 + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_67 + port (B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic); + end component; + component SLICE_68 + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_69 + port (B1: in Std_logic; A1: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_70 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component i30_SLICE_71 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); + end component; + component SLICE_72 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_73 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_74 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_75 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_76 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_77 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_78 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_79 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_80 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_81 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_82 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_83 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_84 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_85 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_86 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_87 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_88 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_89 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_90 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_91 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_92 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_93 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_94 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_95 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_96 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_97 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_98 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_99 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_100 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_101 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_102 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_103 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_104 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_105 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_106 + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component RD_7_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD7: inout Std_logic); + end component; + component RD_6_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD6: inout Std_logic); + end component; + component RD_5_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD5: inout Std_logic); + end component; + component RD_4_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD4: inout Std_logic); + end component; + component RD_3_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD3: inout Std_logic); + end component; + component RD_2_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD2: inout Std_logic); + end component; + component RD_1_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD1: inout Std_logic); + end component; + component RD_0_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD0: inout Std_logic); + end component; + component Dout_7_B + port (PADDO: in Std_logic; Dout7: out Std_logic); + end component; + component Dout_6_B + port (PADDO: in Std_logic; Dout6: out Std_logic); + end component; + component Dout_5_B + port (PADDO: in Std_logic; Dout5: out Std_logic); + end component; + component Dout_4_B + port (PADDO: in Std_logic; Dout4: out Std_logic); + end component; + component Dout_3_B + port (PADDO: in Std_logic; Dout3: out Std_logic); + end component; + component Dout_2_B + port (PADDO: in Std_logic; Dout2: out Std_logic); + end component; + component Dout_1_B + port (PADDO: in Std_logic; Dout1: out Std_logic); + end component; + component Dout_0_B + port (PADDO: in Std_logic; Dout0: out Std_logic); + end component; + component LEDB + port (PADDO: in Std_logic; LEDS: out Std_logic); + end component; + component RBA_1_B + port (PADDO: in Std_logic; RBA1: out Std_logic); + end component; + component RBA_0_B + port (PADDO: in Std_logic; RBA0: out Std_logic); + end component; + component RA_11_B + port (PADDO: in Std_logic; RA11: out Std_logic); + end component; + component RA_10_B + port (PADDO: in Std_logic; RA10: out Std_logic); + end component; + component RA_9_B + port (PADDO: in Std_logic; RA9: out Std_logic); + end component; + component RA_8_B + port (PADDO: in Std_logic; RA8: out Std_logic); + end component; + component RA_7_B + port (PADDO: in Std_logic; RA7: out Std_logic); + end component; + component RA_6_B + port (PADDO: in Std_logic; RA6: out Std_logic); + end component; + component RA_5_B + port (PADDO: in Std_logic; RA5: out Std_logic); + end component; + component RA_4_B + port (PADDO: in Std_logic; RA4: out Std_logic); + end component; + component RA_3_B + port (PADDO: in Std_logic; RA3: out Std_logic); + end component; + component RA_2_B + port (PADDO: in Std_logic; RA2: out Std_logic); + end component; + component RA_1_B + port (PADDO: in Std_logic; RA1: out Std_logic); + end component; + component RA_0_B + port (PADDO: in Std_logic; RA0: out Std_logic); + end component; + component nRCSB + port (PADDO: in Std_logic; nRCSS: out Std_logic); + end component; + component RCKEB + port (PADDO: in Std_logic; RCKES: out Std_logic); + end component; + component nRWEB + port (PADDO: in Std_logic; nRWES: out Std_logic); + end component; + component nRRASB + port (PADDO: in Std_logic; nRRASS: out Std_logic); + end component; + component nRCASB + port (PADDO: in Std_logic; nRCASS: out Std_logic); + end component; + component RDQMHB + port (PADDO: in Std_logic; RDQMHS: out Std_logic); + end component; + component RDQMLB + port (PADDO: in Std_logic; RDQMLS: out Std_logic); + end component; + component nUFMCSB + port (PADDO: in Std_logic; nUFMCSS: out Std_logic); + end component; + component UFMCLKB + port (PADDO: in Std_logic; UFMCLKS: out Std_logic); + end component; + component UFMSDIB + port (PADDO: in Std_logic; UFMSDIS: out Std_logic); + end component; + component PHI2B + port (PADDI: out Std_logic; PHI2S: in Std_logic); + end component; + component MAin_9_B + port (PADDI: out Std_logic; MAin9: in Std_logic); + end component; + component MAin_8_B + port (PADDI: out Std_logic; MAin8: in Std_logic); + end component; + component MAin_7_B + port (PADDI: out Std_logic; MAin7: in Std_logic); + end component; + component MAin_6_B + port (PADDI: out Std_logic; MAin6: in Std_logic); + end component; + component MAin_5_B + port (PADDI: out Std_logic; MAin5: in Std_logic); + end component; + component MAin_4_B + port (PADDI: out Std_logic; MAin4: in Std_logic); + end component; + component MAin_3_B + port (PADDI: out Std_logic; MAin3: in Std_logic); + end component; + component MAin_2_B + port (PADDI: out Std_logic; MAin2: in Std_logic); + end component; + component MAin_1_B + port (PADDI: out Std_logic; MAin1: in Std_logic); + end component; + component MAin_0_B + port (PADDI: out Std_logic; MAin0: in Std_logic); + end component; + component CROW_1_B + port (PADDI: out Std_logic; CROW1: in Std_logic); + end component; + component CROW_0_B + port (PADDI: out Std_logic; CROW0: in Std_logic); + end component; + component Din_7_B + port (PADDI: out Std_logic; Din7: in Std_logic); + end component; + component Din_6_B + port (PADDI: out Std_logic; Din6: in Std_logic); + end component; + component Din_5_B + port (PADDI: out Std_logic; Din5: in Std_logic); + end component; + component Din_4_B + port (PADDI: out Std_logic; Din4: in Std_logic); + end component; + component Din_3_B + port (PADDI: out Std_logic; Din3: in Std_logic); + end component; + component Din_2_B + port (PADDI: out Std_logic; Din2: in Std_logic); + end component; + component Din_1_B + port (PADDI: out Std_logic; Din1: in Std_logic); + end component; + component Din_0_B + port (PADDI: out Std_logic; Din0: in Std_logic); + end component; + component nCCASB + port (PADDI: out Std_logic; nCCASS: in Std_logic); + end component; + component nCRASB + port (PADDI: out Std_logic; nCRASS: in Std_logic); + end component; + component nFWEB + port (PADDI: out Std_logic; nFWES: in Std_logic); + end component; + component RCLKB + port (PADDI: out Std_logic; RCLKS: in Std_logic); + end component; + component UFMSDOB + port (PADDI: out Std_logic; UFMSDOS: in Std_logic); + end component; + begin + SLICE_0I: SLICE_0 + port map (A1=>FS_14, A0=>FS_13, DI1=>n81, DI0=>n82, CLK=>RCLK_c, + FCI=>n1998, F0=>n82, Q0=>FS_13, F1=>n81, Q1=>FS_14, FCO=>n1999); + SLICE_1I: SLICE_1 + port map (A1=>FS_12, A0=>FS_11, DI1=>n83, DI0=>n84, CLK=>RCLK_c, + FCI=>n1997, F0=>n84, Q0=>FS_11, F1=>n83, Q1=>FS_12, FCO=>n1998); + SLICE_2I: SLICE_2 + port map (A1=>FS_8, A0=>FS_7, DI1=>n87, DI0=>n88, CLK=>RCLK_c, + FCI=>n1995, F0=>n88, Q0=>FS_7, F1=>n87, Q1=>FS_8, FCO=>n1996); + SLICE_3I: SLICE_3 + port map (A1=>FS_6, A0=>FS_5, DI1=>n89, DI0=>n90, CLK=>RCLK_c, + FCI=>n1994, F0=>n90, Q0=>FS_5, F1=>n89, Q1=>FS_6, FCO=>n1995); + SLICE_4I: SLICE_4 + port map (A1=>FS_2, A0=>FS_1, DI1=>n93, DI0=>n94, CLK=>RCLK_c, + FCI=>n1992, F0=>n94, Q0=>FS_1, F1=>n93, Q1=>FS_2, FCO=>n1993); + SLICE_5I: SLICE_5 + port map (A1=>FS_0, DI1=>n95, M0=>CASr2, CLK=>RCLK_c, Q0=>CASr3, F1=>n95, + Q1=>FS_0, FCO=>n1992); + SLICE_6I: SLICE_6 + port map (A1=>FS_10, A0=>FS_9, DI1=>n85, DI0=>n86, CLK=>RCLK_c, + FCI=>n1996, F0=>n86, Q0=>FS_9, F1=>n85, Q1=>FS_10, FCO=>n1997); + SLICE_7I: SLICE_7 + port map (A0=>FS_17, DI0=>n78, CLK=>RCLK_c, FCI=>n2000, F0=>n78, + Q0=>FS_17); + SLICE_8I: SLICE_8 + port map (A1=>FS_4, A0=>FS_3, DI1=>n91, DI0=>n92, CLK=>RCLK_c, + FCI=>n1993, F0=>n92, Q0=>FS_3, F1=>n91, Q1=>FS_4, FCO=>n1994); + SLICE_9I: SLICE_9 + port map (A1=>FS_16, A0=>FS_15, DI1=>n79, DI0=>n80, CLK=>RCLK_c, + FCI=>n1999, F0=>n80, Q0=>FS_15, F1=>n79, Q1=>FS_16, FCO=>n2000); + SLICE_10I: SLICE_10 + port map (D1=>Din_c_4, C1=>Din_c_6, B1=>Din_c_1, A1=>Din_c_7, D0=>n2382, + C0=>n8, B0=>n2225, A0=>n2180, DI0=>ADSubmitted_N_246, + CE=>PHI2_N_120_enable_2, LSR=>C1Submitted_N_237, CLK=>PHI2_c, + F0=>ADSubmitted_N_246, Q0=>ADSubmitted, F1=>n8); + SLICE_15I: SLICE_15 + port map (D1=>n26, C1=>MAin_c_5, B1=>n22, A1=>MAin_c_2, D0=>MAin_c_1, + C0=>C1Submitted, B0=>n2365, A0=>nFWE_c, DI0=>n1398, + LSR=>C1Submitted_N_237, CLK=>PHI2_c, F0=>n1398, + Q0=>C1Submitted, F1=>n2365); + SLICE_16I: SLICE_16 + port map (A0=>nCCAS_c, DI0=>nCCAS_N_3, M1=>CASr, CLK=>RCLK_c, + F0=>nCCAS_N_3, Q0=>CASr, Q1=>CASr2); + SLICE_19I: SLICE_19 + port map (D1=>n2254, C1=>Din_c_5, B1=>n2191, A1=>n2183, D0=>n15_adj_1, + C0=>n2208, B0=>MAin_c_1, A0=>n2363, DI0=>CmdEnable_N_248, + CE=>PHI2_N_120_enable_1, CLK=>PHI2_c, F0=>CmdEnable_N_248, + Q0=>CmdEnable, F1=>n15_adj_1); + SLICE_20I: SLICE_20 + port map (DI0=>n2447_001_BUF1, CE=>PHI2_N_120_enable_7, CLK=>PHI2_c, + F0=>n2447_001_BUF1, Q0=>CmdSubmitted); + SLICE_24I: SLICE_24 + port map (C1=>Din_c_5, B1=>Din_c_7, A1=>Din_c_6, D0=>n1314, C0=>Din_c_4, + B0=>n8MEGEN, A0=>Din_c_0, DI0=>Cmdn8MEGEN_N_264, + CE=>PHI2_N_120_enable_6, CLK=>PHI2_c, F0=>Cmdn8MEGEN_N_264, + Q0=>Cmdn8MEGEN, F1=>n1314); + SLICE_25I: SLICE_25 + port map (C1=>Din_c_3, B1=>Din_c_5, A1=>nFWE_c, A0=>nFWE_c, DI0=>n2373, + M1=>nCCAS_N_3, CLK=>nCRAS_c, F0=>n2373, Q0=>FWEr, F1=>n2180, + Q1=>CBR); + SLICE_26I: SLICE_26 + port map (DI0=>n2447_000_BUF1, CE=>RCLK_c_enable_28, CLK=>RCLK_c, + F0=>n2447_000_BUF1, Q0=>InitReady); + SLICE_27I: SLICE_27 + port map (DI0=>n2447, CE=>RCLK_c_enable_16, CLK=>RCLK_c, F0=>n2447, + Q0=>LEDEN); + SLICE_30I: SLICE_30 + port map (C1=>CBR, B1=>LEDEN, A1=>nCRAS_c, A0=>nCRAS_c, DI0=>nCRAS_c_inv, + M1=>RASr, CLK=>RCLK_c, F0=>nCRAS_c_inv, Q0=>RASr, F1=>LED_c, + Q1=>RASr2); + SLICE_32I: SLICE_32 + port map (C1=>nRowColSel_N_35, B1=>InitReady, A1=>RASr2, D0=>nRCAS_N_165, + C0=>Ready, B0=>n2381, A0=>nRCS_N_139, DI0=>n2036, + LSR=>nRWE_N_177, CLK=>RCLK_c, F0=>n2036, Q0=>RA_0S, F1=>n2381); + SLICE_33I: SLICE_33 + port map (C1=>Din_c_4, B1=>Din_c_7, A1=>Din_c_6, C0=>n8MEGEN, + B0=>XOR8MEG, A0=>Din_c_6, DI0=>RA11_N_184, LSR=>Ready, + CLK=>PHI2_c, F0=>RA11_N_184, Q0=>RA_c, F1=>n6_adj_2); + SLICE_35I: SLICE_35 + port map (D1=>InitReady, C1=>CmdSubmitted, B1=>PHI2r2, A1=>PHI2r3, + C0=>Ready, B0=>n15_adj_4, A0=>InitReady, DI0=>RCKEEN_N_121, + CE=>RCLK_c_enable_6, CLK=>RCLK_c, F0=>RCKEEN_N_121, Q0=>RCKEEN, + F1=>RCLK_c_enable_10); + SLICE_36I: SLICE_36 + port map (D0=>RASr3, C0=>RASr2, B0=>RCKEEN, A0=>RASr, DI0=>RCKE_N_132, + M1=>PHI2r, CLK=>RCLK_c, F0=>RCKE_N_132, Q0=>RCKE_c, Q1=>PHI2r2); + SLICE_37I: SLICE_37 + port map (DI0=>n2447_002_BUF1, CE=>Ready_N_292, CLK=>RCLK_c, + F0=>n2447_002_BUF1, Q0=>Ready); + SLICE_44I: SLICE_44 + port map (D1=>FS_1, C1=>n2267, B1=>n13_adj_6, A1=>FS_4, C0=>InitReady, + B0=>CmdUFMCLK, A0=>n1893, DI0=>UFMCLK_N_224, + CE=>RCLK_c_enable_10, LSR=>n2366, CLK=>RCLK_c, + F0=>UFMCLK_N_224, Q0=>UFMCLK_c, F1=>n1893); + SLICE_45I: SLICE_45 + port map (D1=>n10, C1=>FS_10, B1=>FS_8, A1=>n7, D0=>n4, C0=>InitReady, + B0=>CmdUFMSDI, A0=>n2174, DI0=>UFMSDI_N_231, + CE=>RCLK_c_enable_10, LSR=>n2366, CLK=>RCLK_c, + F0=>UFMSDI_N_231, Q0=>UFMSDI_c, F1=>n2174); + SLICE_50I: SLICE_50 + port map (D1=>LEDEN, C1=>n1314, B1=>Din_c_1, A1=>Din_c_4, D0=>Din_c_3, + C0=>n2260, B0=>Din_c_2, A0=>Din_c_0, DI0=>XOR8MEG_N_110, + CE=>PHI2_N_120_enable_3, CLK=>PHI2_c, F0=>XOR8MEG_N_110, + Q0=>XOR8MEG, F1=>n2260); + SLICE_57I: SLICE_57 + port map (D1=>FS_10, C1=>FS_11, B1=>n2375, A1=>n10, D0=>Cmdn8MEGEN, + C0=>UFMSDO_c, B0=>n2367, A0=>InitReady, DI0=>n8MEGEN_N_91, + CE=>RCLK_c_enable_15, CLK=>RCLK_c, F0=>n8MEGEN_N_91, + Q0=>n8MEGEN, F1=>n2367); + SLICE_59I: SLICE_59 + port map (D1=>CBR, C1=>nRowColSel_N_35, B1=>RASr2, A1=>nRCS_N_142, + D0=>nRCAS_N_166, C0=>Ready, B0=>nRCAS_N_165, A0=>n2371, + DI0=>nRCAS_N_161, CE=>RCLK_c_enable_6, CLK=>RCLK_c, + F0=>nRCAS_N_161, Q0=>nRCAS_c, F1=>nRCAS_N_166); + SLICE_61I: SLICE_61 + port map (D1=>nRCS_N_142, C1=>nRowColSel_N_35, B1=>RASr2, A1=>RCKE_c, + C0=>Ready, B0=>nRCS_N_141, A0=>nRCS_N_137, DI0=>nRCS_N_136, + CE=>RCLK_c_enable_6, CLK=>RCLK_c, F0=>nRCS_N_136, Q0=>nRCS_c, + F1=>nRCS_N_141); + SLICE_62I: SLICE_62 + port map (D1=>RASr2, C1=>nRowColSel_N_35, B1=>InitReady, A1=>nRCS_N_139, + D0=>nRowColSel_N_35, C0=>Ready, B0=>n2379, A0=>nRCS_N_137, + DI0=>nRRAS_N_156, CE=>RCLK_c_enable_6, CLK=>RCLK_c, + F0=>nRRAS_N_156, Q0=>nRRAS_c, F1=>nRCS_N_137); + SLICE_64I: SLICE_64 + port map (B1=>nRCAS_N_165, A1=>nRWE_N_177, D0=>n2371, C0=>Ready, + B0=>nRWE_N_178, A0=>n1765, DI0=>nRWE_N_171, + CE=>RCLK_c_enable_5, CLK=>RCLK_c, F0=>nRWE_N_171, Q0=>nRWE_c, + F1=>n1765); + SLICE_65I: SLICE_65 + port map (B1=>nRowColSel_N_34, A1=>nRowColSel_N_33, D0=>n2376, C0=>n1060, + B0=>n2372, A0=>FWEr, DI0=>n917, CE=>RCLK_c_enable_5, + CLK=>RCLK_c, F0=>n917, Q0=>nRowColSel, F1=>n1060); + SLICE_66I: SLICE_66 + port map (B1=>CASr2, A1=>nRowColSel_N_33, B0=>nRowColSel_N_32, + A0=>nRowColSel_N_33, DI0=>n827, LSR=>RASr2, CLK=>RCLK_c, + F0=>n827, Q0=>nRowColSel_N_32, F1=>n2227); + SLICE_67I: SLICE_67 + port map (B0=>nRowColSel_N_32, A0=>RASr2, DI0=>n1406, + LSR=>nRowColSel_N_34, CLK=>RCLK_c, F0=>n1406, + Q0=>nRowColSel_N_33); + SLICE_68I: SLICE_68 + port map (B1=>FS_0, A1=>FS_8, B0=>Bank_3, A0=>Bank_6, M0=>n1406, + LSR=>nRowColSel_N_35, CLK=>RCLK_c, F0=>n2287, + Q0=>nRowColSel_N_34, F1=>n13); + SLICE_69I: SLICE_69 + port map (B1=>RASr2, A1=>RCKE_c, A0=>RASr2, DI0=>n2374, M1=>PHI2r2, + CLK=>RCLK_c, F0=>n2374, Q0=>nRowColSel_N_35, F1=>n2379, + Q1=>PHI2r3); + SLICE_70I: SLICE_70 + port map (D1=>FS_10, C1=>InitReady, B1=>n2368, A1=>FS_11, D0=>InitReady, + C0=>CmdUFMCS, B0=>n64, A0=>n13_adj_6, DI0=>nUFMCS_N_199, + CE=>RCLK_c_enable_10, CLK=>RCLK_c, F0=>nUFMCS_N_199, + Q0=>nUFMCS_c, F1=>n64); + i30_SLICE_71I: i30_SLICE_71 + port map (C1=>RASr2, B1=>FWEr, A1=>CBR, D0=>nRowColSel_N_34, C0=>FWEr, + B0=>n2227, A0=>CBR, M0=>nRowColSel_N_35, OFX0=>n15_adj_4); + SLICE_72I: SLICE_72 + port map (D1=>Ready, C1=>nRowColSel_N_32, B1=>n6_adj_3, A1=>RASr2, + B0=>Ready_N_296, A0=>InitReady, F0=>n6_adj_3, F1=>Ready_N_292); + SLICE_73I: SLICE_73 + port map (D1=>n2204, C1=>n2180, B1=>n26, A1=>n2369, D0=>n6_adj_2, + C0=>CmdEnable, B0=>MAin_c_0, A0=>MAin_c_1, F0=>n2204, + F1=>PHI2_N_120_enable_8); + SLICE_74I: SLICE_74 + port map (D1=>Bank_5, C1=>n2287, B1=>n2277, A1=>Bank_2, D0=>nFWE_c, + C0=>n2204, B0=>n26, A0=>n2369, M1=>MAin_c_1, M0=>MAin_c_0, + LSR=>Ready, CLK=>nCRAS_c, F0=>n2220, Q0=>RowA_0, F1=>n26, + Q1=>RowA_1); + SLICE_75I: SLICE_75 + port map (D1=>n2370, C1=>n2183, B1=>n2228, A1=>Din_c_5, B0=>Din_c_3, + A0=>Din_c_6, M1=>n732, M0=>n733, CE=>RCLK_c_enable_27, + CLK=>RCLK_c, F0=>n2183, Q0=>n732, F1=>n2055, Q1=>nRWE_N_177); + SLICE_76I: SLICE_76 + port map (C1=>n10, B1=>FS_14, A1=>FS_12, D0=>InitReady, C0=>n2368, + B0=>FS_11, A0=>FS_10, M1=>MAin_c_9, M0=>MAin_c_8, LSR=>Ready, + CLK=>nCRAS_c, F0=>RCLK_c_enable_16, Q0=>RowA_8, F1=>n2368, + Q1=>RowA_9); + SLICE_77I: SLICE_77 + port map (D1=>n2208, C1=>C1Submitted, B1=>n2191, A1=>Din_c_5, + D0=>MAin_c_0, C0=>Din_c_6, B0=>Din_c_3, A0=>Din_c_2, F0=>n2191, + F1=>n2210); + SLICE_78I: SLICE_78 + port map (D1=>nRowColSel_N_35, C1=>nRWE_N_182, B1=>n1060, A1=>nRCS_N_146, + B0=>RASr2, A0=>RCKE_c, M1=>n728, M0=>n729, + CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>nRWE_N_182, Q0=>n728, + F1=>nRWE_N_178, Q1=>n727); + SLICE_79I: SLICE_79 + port map (C1=>MAin_c_5, B1=>n22, A1=>MAin_c_2, D0=>MAin_c_1, C0=>nFWE_c, + B0=>n26, A0=>n2369, M1=>n730, M0=>nRWE_N_177, + CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>PHI2_N_120_enable_2, + Q0=>n730, F1=>n2369, Q1=>n729); + SLICE_80I: SLICE_80 + port map (B1=>FS_14, A1=>FS_12, D0=>FS_11, C0=>InitReady, B0=>n2375, + A0=>n10, F0=>n2366, F1=>n2375); + SLICE_81I: SLICE_81 + port map (B1=>CBR, A1=>FWEr, D0=>nRowColSel_N_33, C0=>n2378, + B0=>nRowColSel_N_34, A0=>nRCS_N_146, M1=>n726, M0=>n727, + CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>nRCS_N_142, Q0=>n726, + F1=>n2378, Q1=>Ready_N_296); + SLICE_82I: SLICE_82 + port map (D1=>FS_17, C1=>FS_14, B1=>n12, A1=>FS_11, B0=>n13_adj_6, + A0=>FS_10, M1=>MAin_c_5, M0=>MAin_c_4, LSR=>Ready, + CLK=>nCRAS_c, F0=>RCLK_c_enable_28, Q0=>RowA_4, F1=>n13_adj_6, + Q1=>RowA_5); + SLICE_83I: SLICE_83 + port map (D1=>n1314, C1=>n1277, B1=>CmdEnable, A1=>n2228, D0=>MAin_c_1, + C0=>MAin_c_0, B0=>n26, A0=>n2369, F0=>n1277, + F1=>PHI2_N_120_enable_3); + SLICE_84I: SLICE_84 + port map (C1=>CmdSubmitted, B1=>PHI2r2, A1=>PHI2r3, D0=>n4_adj_7, + C0=>InitReady, B0=>n2377, A0=>n2367, M1=>n738, M0=>nRCAS_N_165, + CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>RCLK_c_enable_15, + Q0=>n738, F1=>n2377, Q1=>n737); + SLICE_85I: SLICE_85 + port map (D1=>n10, C1=>FS_11, B1=>FS_14, A1=>FS_12, D0=>FS_16, C0=>FS_15, + B0=>FS_13, A0=>FS_17, F0=>n10, F1=>n2267); + SLICE_86I: SLICE_86 + port map (C1=>FS_6, B1=>FS_9, A1=>FS_3, D0=>n14, C0=>n13, B0=>n15, + A0=>FS_4, M1=>RASr2, M0=>PHI2_c, CLK=>RCLK_c, F0=>n4_adj_7, + Q0=>PHI2r, F1=>n14, Q1=>RASr3); + SLICE_87I: SLICE_87 + port map (D1=>n6, C1=>nRowColSel_N_32, B1=>nRowColSel_N_33, + A1=>nRowColSel_N_35, B0=>nRowColSel_N_34, A0=>Ready, + M1=>CROW_c_1, M0=>CROW_c_0, LSR=>Ready, CLK=>nCRAS_c, F0=>n6, + Q0=>RBA_c_0, F1=>RCLK_c_enable_6, Q1=>RBA_c_1); + SLICE_88I: SLICE_88 + port map (D1=>n2363, C1=>C1Submitted_N_237, B1=>ADSubmitted, + A1=>n7_adj_5, D0=>n2362, C0=>MAin_c_0, B0=>n2055, A0=>Din_c_2, + M1=>Din_c_7, M0=>Din_c_6, CLK=>nCCAS_c, F0=>C1Submitted_N_237, + Q0=>WRD_6, F1=>PHI2_N_120_enable_1, Q1=>WRD_7); + SLICE_89I: SLICE_89 + port map (D1=>Din_c_5, C1=>Din_c_3, B1=>Din_c_4, A1=>n2220, D0=>Din_c_3, + C0=>Din_c_4, B0=>n2220, A0=>Din_c_5, M1=>Din_c_5, M0=>Din_c_4, + CLK=>nCCAS_c, F0=>PHI2_N_120_enable_6, Q0=>WRD_4, + F1=>PHI2_N_120_enable_7, Q1=>WRD_5); + SLICE_90I: SLICE_90 + port map (D1=>Din_c_0, C1=>Din_c_4, B1=>Din_c_1, A1=>Din_c_7, + C0=>Din_c_0, B0=>Din_c_1, A0=>Din_c_7, M1=>Din_c_1, + M0=>Din_c_0, CLK=>nCCAS_c, F0=>n2370, Q0=>WRD_0, F1=>n2208, + Q1=>WRD_1); + SLICE_91I: SLICE_91 + port map (C1=>MAin_c_1, B1=>n26, A1=>n2369, D0=>MAin_c_1, C0=>MAin_c_0, + B0=>n26, A0=>n2369, M1=>MAin_c_3, M0=>MAin_c_2, LSR=>Ready, + CLK=>nCRAS_c, F0=>n2225, Q0=>RowA_2, F1=>n2362, Q1=>RowA_3); + SLICE_92I: SLICE_92 + port map (D1=>Ready, C1=>nRowColSel_N_35, B1=>InitReady, A1=>RASr2, + D0=>nRCS_N_139, C0=>nRowColSel_N_35, B0=>InitReady, A0=>RASr2, + M1=>Din_c_3, M0=>Din_c_2, CLK=>nCCAS_c, F0=>n2371, Q0=>WRD_2, + F1=>RCLK_c_enable_27, Q1=>WRD_3); + SLICE_93I: SLICE_93 + port map (B1=>nRowColSel, A1=>MAin_c_9, C0=>nRowColSel, B0=>MAin_c_9, + A0=>RowA_9, M1=>Din_c_1, M0=>Din_c_0, CLK=>PHI2_c, F0=>RA_1_9, + Q0=>Bank_0, F1=>RDQML_c, Q1=>Bank_1); + SLICE_94I: SLICE_94 + port map (B1=>nRowColSel_N_35, A1=>Ready, D0=>nRowColSel_N_35, + C0=>nRowColSel_N_32, B0=>n1060, A0=>Ready, F0=>RCLK_c_enable_5, + F1=>n2372); + SLICE_95I: SLICE_95 + port map (D1=>FS_5, C1=>FS_9, B1=>FS_7, A1=>n2375, D0=>FS_2, C0=>FS_1, + B0=>FS_7, A0=>FS_5, F0=>n15, F1=>n7); + SLICE_96I: SLICE_96 + port map (B1=>CASr3, A1=>CBR, D0=>CASr2, C0=>FWEr, B0=>CASr3, A0=>CBR, + F0=>nRCS_N_146, F1=>n2376); + SLICE_97I: SLICE_97 + port map (C1=>MAin_c_1, B1=>n2210, A1=>MAin_c_0, B0=>Din_c_2, + A0=>MAin_c_0, M1=>n734, M0=>n735, CE=>RCLK_c_enable_27, + CLK=>RCLK_c, F0=>n2254, Q0=>n734, F1=>n7_adj_5, Q1=>n733); + SLICE_98I: SLICE_98 + port map (B1=>nRowColSel, A1=>MAin_c_9, C0=>nRowColSel, B0=>MAin_c_8, + A0=>RowA_8, M1=>nRCS_N_139, M0=>Ready_N_296, + CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>RA_1_8, Q0=>nRCS_N_139, + F1=>RDQMH_c, Q1=>nRCAS_N_165); + SLICE_99I: SLICE_99 + port map (D1=>Bank_1, C1=>Bank_4, B1=>MAin_c_3, A1=>MAin_c_7, + C0=>nRowColSel, B0=>MAin_c_7, A0=>RowA_7, M0=>Din_c_0, + CE=>PHI2_N_120_enable_8, CLK=>PHI2_c, F0=>RA_1_7, + Q0=>CmdUFMSDI, F1=>n22); + SLICE_100I: SLICE_100 + port map (D1=>Bank_0, C1=>Bank_7, B1=>MAin_c_4, A1=>MAin_c_6, + C0=>nRowColSel, B0=>MAin_c_6, A0=>RowA_6, M1=>Din_c_2, + M0=>Din_c_1, CE=>PHI2_N_120_enable_8, CLK=>PHI2_c, F0=>RA_1_6, + Q0=>CmdUFMCLK, F1=>n2277, Q1=>CmdUFMCS); + SLICE_101I: SLICE_101 + port map (C1=>nRowColSel, B1=>MAin_c_0, A1=>RowA_0, C0=>nRowColSel, + B0=>MAin_c_5, A0=>RowA_5, M1=>Din_c_7, M0=>Din_c_6, + CLK=>PHI2_c, F0=>RA_1_5, Q0=>Bank_6, F1=>RA_1_0, Q1=>Bank_7); + SLICE_102I: SLICE_102 + port map (C1=>nRowColSel, B1=>MAin_c_1, A1=>RowA_1, C0=>nRowColSel, + B0=>MAin_c_4, A0=>RowA_4, M1=>Din_c_5, M0=>Din_c_4, + CLK=>PHI2_c, F0=>RA_1_4, Q0=>Bank_4, F1=>RA_1_1, Q1=>Bank_5); + SLICE_103I: SLICE_103 + port map (C1=>nRowColSel, B1=>MAin_c_2, A1=>RowA_2, C0=>nRowColSel, + B0=>MAin_c_3, A0=>RowA_3, M1=>Din_c_3, M0=>Din_c_2, + CLK=>PHI2_c, F0=>RA_1_3, Q0=>Bank_2, F1=>RA_1_2, Q1=>Bank_3); + SLICE_104I: SLICE_104 + port map (B1=>nFWE_c, A1=>nCCAS_c, C0=>nFWE_c, B0=>n26, A0=>n2369, + M1=>MAin_c_7, M0=>MAin_c_6, LSR=>Ready, CLK=>nCRAS_c, + F0=>n2363, Q0=>RowA_6, F1=>n984, Q1=>RowA_7); + SLICE_105I: SLICE_105 + port map (B1=>FS_6, A1=>FS_11, D0=>FS_16, C0=>FS_15, B0=>FS_12, + A0=>FS_13, F0=>n12, F1=>n4); + SLICE_106I: SLICE_106 + port map (B1=>Din_c_2, A1=>Din_c_0, B0=>Din_c_4, A0=>nFWE_c, M1=>n736, + M0=>n737, CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>n2228, + Q0=>n736, F1=>n2382, Q1=>n735); + RD_7_I: RD_7_B + port map (PADDI=>Dout_c, PADDT=>n984, PADDO=>WRD_7, RD7=>RD(7)); + RD_6_I: RD_6_B + port map (PADDI=>Dout_0S, PADDT=>n984, PADDO=>WRD_6, RD6=>RD(6)); + RD_5_I: RD_5_B + port map (PADDI=>Dout_1S, PADDT=>n984, PADDO=>WRD_5, RD5=>RD(5)); + RD_4_I: RD_4_B + port map (PADDI=>Dout_2S, PADDT=>n984, PADDO=>WRD_4, RD4=>RD(4)); + RD_3_I: RD_3_B + port map (PADDI=>Dout_3S, PADDT=>n984, PADDO=>WRD_3, RD3=>RD(3)); + RD_2_I: RD_2_B + port map (PADDI=>Dout_4S, PADDT=>n984, PADDO=>WRD_2, RD2=>RD(2)); + RD_1_I: RD_1_B + port map (PADDI=>Dout_5S, PADDT=>n984, PADDO=>WRD_1, RD1=>RD(1)); + RD_0_I: RD_0_B + port map (PADDI=>Dout_6S, PADDT=>n984, PADDO=>WRD_0, RD0=>RD(0)); + Dout_7_I: Dout_7_B + port map (PADDO=>Dout_c, Dout7=>Dout(7)); + Dout_6_I: Dout_6_B + port map (PADDO=>Dout_0S, Dout6=>Dout(6)); + Dout_5_I: Dout_5_B + port map (PADDO=>Dout_1S, Dout5=>Dout(5)); + Dout_4_I: Dout_4_B + port map (PADDO=>Dout_2S, Dout4=>Dout(4)); + Dout_3_I: Dout_3_B + port map (PADDO=>Dout_3S, Dout3=>Dout(3)); + Dout_2_I: Dout_2_B + port map (PADDO=>Dout_4S, Dout2=>Dout(2)); + Dout_1_I: Dout_1_B + port map (PADDO=>Dout_5S, Dout1=>Dout(1)); + Dout_0_I: Dout_0_B + port map (PADDO=>Dout_6S, Dout0=>Dout(0)); + LEDI: LEDB + port map (PADDO=>LED_c, LEDS=>LED); + RBA_1_I: RBA_1_B + port map (PADDO=>RBA_c_1, RBA1=>RBA(1)); + RBA_0_I: RBA_0_B + port map (PADDO=>RBA_c_0, RBA0=>RBA(0)); + RA_11_I: RA_11_B + port map (PADDO=>RA_c, RA11=>RA(11)); + RA_10_I: RA_10_B + port map (PADDO=>RA_0S, RA10=>RA(10)); + RA_9_I: RA_9_B + port map (PADDO=>RA_1_9, RA9=>RA(9)); + RA_8_I: RA_8_B + port map (PADDO=>RA_1_8, RA8=>RA(8)); + RA_7_I: RA_7_B + port map (PADDO=>RA_1_7, RA7=>RA(7)); + RA_6_I: RA_6_B + port map (PADDO=>RA_1_6, RA6=>RA(6)); + RA_5_I: RA_5_B + port map (PADDO=>RA_1_5, RA5=>RA(5)); + RA_4_I: RA_4_B + port map (PADDO=>RA_1_4, RA4=>RA(4)); + RA_3_I: RA_3_B + port map (PADDO=>RA_1_3, RA3=>RA(3)); + RA_2_I: RA_2_B + port map (PADDO=>RA_1_2, RA2=>RA(2)); + RA_1_I: RA_1_B + port map (PADDO=>RA_1_1, RA1=>RA(1)); + RA_0_I: RA_0_B + port map (PADDO=>RA_1_0, RA0=>RA(0)); + nRCSI: nRCSB + port map (PADDO=>nRCS_c, nRCSS=>nRCS); + RCKEI: RCKEB + port map (PADDO=>RCKE_c, RCKES=>RCKE); + nRWEI: nRWEB + port map (PADDO=>nRWE_c, nRWES=>nRWE); + nRRASI: nRRASB + port map (PADDO=>nRRAS_c, nRRASS=>nRRAS); + nRCASI: nRCASB + port map (PADDO=>nRCAS_c, nRCASS=>nRCAS); + RDQMHI: RDQMHB + port map (PADDO=>RDQMH_c, RDQMHS=>RDQMH); + RDQMLI: RDQMLB + port map (PADDO=>RDQML_c, RDQMLS=>RDQML); + nUFMCSI: nUFMCSB + port map (PADDO=>nUFMCS_c, nUFMCSS=>nUFMCS); + UFMCLKI: UFMCLKB + port map (PADDO=>UFMCLK_c, UFMCLKS=>UFMCLK); + UFMSDII: UFMSDIB + port map (PADDO=>UFMSDI_c, UFMSDIS=>UFMSDI); + PHI2I: PHI2B + port map (PADDI=>PHI2_c, PHI2S=>PHI2); + MAin_9_I: MAin_9_B + port map (PADDI=>MAin_c_9, MAin9=>MAin(9)); + MAin_8_I: MAin_8_B + port map (PADDI=>MAin_c_8, MAin8=>MAin(8)); + MAin_7_I: MAin_7_B + port map (PADDI=>MAin_c_7, MAin7=>MAin(7)); + MAin_6_I: MAin_6_B + port map (PADDI=>MAin_c_6, MAin6=>MAin(6)); + MAin_5_I: MAin_5_B + port map (PADDI=>MAin_c_5, MAin5=>MAin(5)); + MAin_4_I: MAin_4_B + port map (PADDI=>MAin_c_4, MAin4=>MAin(4)); + MAin_3_I: MAin_3_B + port map (PADDI=>MAin_c_3, MAin3=>MAin(3)); + MAin_2_I: MAin_2_B + port map (PADDI=>MAin_c_2, MAin2=>MAin(2)); + MAin_1_I: MAin_1_B + port map (PADDI=>MAin_c_1, MAin1=>MAin(1)); + MAin_0_I: MAin_0_B + port map (PADDI=>MAin_c_0, MAin0=>MAin(0)); + CROW_1_I: CROW_1_B + port map (PADDI=>CROW_c_1, CROW1=>CROW(1)); + CROW_0_I: CROW_0_B + port map (PADDI=>CROW_c_0, CROW0=>CROW(0)); + Din_7_I: Din_7_B + port map (PADDI=>Din_c_7, Din7=>Din(7)); + Din_6_I: Din_6_B + port map (PADDI=>Din_c_6, Din6=>Din(6)); + Din_5_I: Din_5_B + port map (PADDI=>Din_c_5, Din5=>Din(5)); + Din_4_I: Din_4_B + port map (PADDI=>Din_c_4, Din4=>Din(4)); + Din_3_I: Din_3_B + port map (PADDI=>Din_c_3, Din3=>Din(3)); + Din_2_I: Din_2_B + port map (PADDI=>Din_c_2, Din2=>Din(2)); + Din_1_I: Din_1_B + port map (PADDI=>Din_c_1, Din1=>Din(1)); + Din_0_I: Din_0_B + port map (PADDI=>Din_c_0, Din0=>Din(0)); + nCCASI: nCCASB + port map (PADDI=>nCCAS_c, nCCASS=>nCCAS); + nCRASI: nCRASB + port map (PADDI=>nCRAS_c, nCRASS=>nCRAS); + nFWEI: nFWEB + port map (PADDI=>nFWE_c, nFWES=>nFWE); + RCLKI: RCLKB + port map (PADDI=>RCLK_c, RCLKS=>RCLK); + UFMSDOI: UFMSDOB + port map (PADDI=>UFMSDO_c, UFMSDOS=>UFMSDO); + VHI_INST: VHI + port map (Z=>VCCI); + PUR_INST: PUR + port map (PUR=>VCCI); + GSR_INST: GSR + port map (GSR=>VCCI); + end Structure; + + + + library IEEE, vital2000, MACHXO2; + configuration Structure_CON of RAM2GS is + for Structure + end for; + end Structure_CON; + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.sdf b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.sdf new file mode 100644 index 0000000..76a02d9 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.sdf @@ -0,0 +1,3176 @@ +(DELAYFILE + (SDFVERSION "3.0") + (DESIGN "RAM2GS") + (DATE "Tue Aug 15 05:03:26 2023") + (VENDOR "Lattice") + (PROGRAM "ldbanno") + (VERSION "Diamond (64-bit) 3.12.1.454") + (DIVIDER /) + (VOLTAGE 1.26:1.20:1.14) + (PROCESS "default") + (TEMPERATURE -40:25:85) + (TIMESCALE 1ps) + (CELL + (CELLTYPE "SLICE_0") + (INSTANCE SLICE_0) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_1") + (INSTANCE SLICE_1) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_2") + (INSTANCE SLICE_2) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_3") + (INSTANCE SLICE_3) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_4") + (INSTANCE SLICE_4) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_5") + (INSTANCE SLICE_5) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_6") + (INSTANCE SLICE_6) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_7") + (INSTANCE SLICE_7) + (DELAY + (ABSOLUTE + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_8") + (INSTANCE SLICE_8) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_9") + (INSTANCE SLICE_9) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_10") + (INSTANCE SLICE_10) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_15") + (INSTANCE SLICE_15) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_16") + (INSTANCE SLICE_16) + (DELAY + (ABSOLUTE + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_19") + (INSTANCE SLICE_19) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_20") + (INSTANCE SLICE_20) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_24") + (INSTANCE SLICE_24) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_25") + (INSTANCE SLICE_25) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_26") + (INSTANCE SLICE_26) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_27") + (INSTANCE SLICE_27) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_30") + (INSTANCE SLICE_30) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_32") + (INSTANCE SLICE_32) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_33") + (INSTANCE SLICE_33) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_35") + (INSTANCE SLICE_35) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_36") + (INSTANCE SLICE_36) + (DELAY + (ABSOLUTE + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_37") + (INSTANCE SLICE_37) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_44") + (INSTANCE SLICE_44) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_45") + (INSTANCE SLICE_45) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_50") + (INSTANCE SLICE_50) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_57") + (INSTANCE SLICE_57) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_59") + (INSTANCE SLICE_59) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_61") + (INSTANCE SLICE_61) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_62") + (INSTANCE SLICE_62) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_64") + (INSTANCE SLICE_64) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_65") + (INSTANCE SLICE_65) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_66") + (INSTANCE SLICE_66) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_67") + (INSTANCE SLICE_67) + (DELAY + (ABSOLUTE + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_68") + (INSTANCE SLICE_68) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_69") + (INSTANCE SLICE_69) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_70") + (INSTANCE SLICE_70) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "i30_SLICE_71") + (INSTANCE i30\/SLICE_71) + (DELAY + (ABSOLUTE + (IOPATH C1 OFX0 (457:589:721)(457:589:721)) + (IOPATH B1 OFX0 (457:589:721)(457:589:721)) + (IOPATH A1 OFX0 (457:589:721)(457:589:721)) + (IOPATH D0 OFX0 (457:589:721)(457:589:721)) + (IOPATH C0 OFX0 (457:589:721)(457:589:721)) + (IOPATH B0 OFX0 (457:589:721)(457:589:721)) + (IOPATH A0 OFX0 (457:589:721)(457:589:721)) + (IOPATH M0 OFX0 (322:349:376)(322:349:376)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_72") + (INSTANCE SLICE_72) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_73") + (INSTANCE SLICE_73) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_74") + (INSTANCE SLICE_74) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_75") + (INSTANCE SLICE_75) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_76") + (INSTANCE SLICE_76) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_77") + (INSTANCE SLICE_77) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_78") + (INSTANCE SLICE_78) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_79") + (INSTANCE SLICE_79) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_80") + (INSTANCE SLICE_80) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_81") + (INSTANCE SLICE_81) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_82") + (INSTANCE SLICE_82) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_83") + (INSTANCE SLICE_83) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_84") + (INSTANCE SLICE_84) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_85") + (INSTANCE SLICE_85) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_86") + (INSTANCE SLICE_86) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_87") + (INSTANCE SLICE_87) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_88") + (INSTANCE SLICE_88) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_89") + (INSTANCE SLICE_89) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_90") + (INSTANCE SLICE_90) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_91") + (INSTANCE SLICE_91) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_92") + (INSTANCE SLICE_92) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_93") + (INSTANCE SLICE_93) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_94") + (INSTANCE SLICE_94) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_95") + (INSTANCE SLICE_95) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_96") + (INSTANCE SLICE_96) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_97") + (INSTANCE SLICE_97) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_98") + (INSTANCE SLICE_98) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_99") + (INSTANCE SLICE_99) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_100") + (INSTANCE SLICE_100) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_101") + (INSTANCE SLICE_101) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_102") + (INSTANCE SLICE_102) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_103") + (INSTANCE SLICE_103) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_104") + (INSTANCE SLICE_104) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_105") + (INSTANCE SLICE_105) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_106") + (INSTANCE SLICE_106) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_7_") + (INSTANCE RD\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD7 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD7 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD7 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD7) (3330:3330:3330)) + (WIDTH (negedge RD7) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_6_") + (INSTANCE RD\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD6 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD6 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD6 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD6) (3330:3330:3330)) + (WIDTH (negedge RD6) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_5_") + (INSTANCE RD\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD5 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD5 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD5 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD5) (3330:3330:3330)) + (WIDTH (negedge RD5) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_4_") + (INSTANCE RD\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD4 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD4 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD4 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD4) (3330:3330:3330)) + (WIDTH (negedge RD4) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_3_") + (INSTANCE RD\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD3 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD3 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD3 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD3) (3330:3330:3330)) + (WIDTH (negedge RD3) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_2_") + (INSTANCE RD\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD2 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD2 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD2 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD2) (3330:3330:3330)) + (WIDTH (negedge RD2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_1_") + (INSTANCE RD\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD1 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD1 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD1 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD1) (3330:3330:3330)) + (WIDTH (negedge RD1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_0_") + (INSTANCE RD\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD0 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD0 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD0 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD0) (3330:3330:3330)) + (WIDTH (negedge RD0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Dout_7_") + (INSTANCE Dout\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout7 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_6_") + (INSTANCE Dout\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout6 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_5_") + (INSTANCE Dout\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout5 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_4_") + (INSTANCE Dout\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout4 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_3_") + (INSTANCE Dout\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout3 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_2_") + (INSTANCE Dout\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout2 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_1_") + (INSTANCE Dout\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout1 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_0_") + (INSTANCE Dout\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout0 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "LED") + (INSTANCE LED_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO LED (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_1_") + (INSTANCE RBA\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RBA1 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_0_") + (INSTANCE RBA\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RBA0 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_11_") + (INSTANCE RA\[11\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA11 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_10_") + (INSTANCE RA\[10\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA10 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_9_") + (INSTANCE RA\[9\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA9 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_8_") + (INSTANCE RA\[8\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA8 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_7_") + (INSTANCE RA\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA7 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_6_") + (INSTANCE RA\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA6 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_5_") + (INSTANCE RA\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA5 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_4_") + (INSTANCE RA\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA4 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_3_") + (INSTANCE RA\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA3 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_2_") + (INSTANCE RA\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA2 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_1_") + (INSTANCE RA\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA1 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_0_") + (INSTANCE RA\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA0 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nRCS") + (INSTANCE nRCS_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRCS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RCKE") + (INSTANCE RCKE_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RCKE (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nRWE") + (INSTANCE nRWE_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRWE (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nRRAS") + (INSTANCE nRRAS_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRRAS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nRCAS") + (INSTANCE nRCAS_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRCAS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RDQMH") + (INSTANCE RDQMH_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RDQMH (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RDQML") + (INSTANCE RDQML_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RDQML (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nUFMCS") + (INSTANCE nUFMCS_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nUFMCS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "UFMCLK") + (INSTANCE UFMCLK_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO UFMCLK (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "UFMSDI") + (INSTANCE UFMSDI_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO UFMSDI (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "PHI2") + (INSTANCE PHI2_I) + (DELAY + (ABSOLUTE + (IOPATH PHI2 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge PHI2) (3330:3330:3330)) + (WIDTH (negedge PHI2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_9_") + (INSTANCE MAin\[9\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin9 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin9) (3330:3330:3330)) + (WIDTH (negedge MAin9) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_8_") + (INSTANCE MAin\[8\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin8 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin8) (3330:3330:3330)) + (WIDTH (negedge MAin8) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_7_") + (INSTANCE MAin\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin7 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin7) (3330:3330:3330)) + (WIDTH (negedge MAin7) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_6_") + (INSTANCE MAin\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin6 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin6) (3330:3330:3330)) + (WIDTH (negedge MAin6) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_5_") + (INSTANCE MAin\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin5 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin5) (3330:3330:3330)) + (WIDTH (negedge MAin5) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_4_") + (INSTANCE MAin\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin4 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin4) (3330:3330:3330)) + (WIDTH (negedge MAin4) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_3_") + (INSTANCE MAin\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin3 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin3) (3330:3330:3330)) + (WIDTH (negedge MAin3) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_2_") + (INSTANCE MAin\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin2 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin2) (3330:3330:3330)) + (WIDTH (negedge MAin2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_1_") + (INSTANCE MAin\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin1 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin1) (3330:3330:3330)) + (WIDTH (negedge MAin1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_0_") + (INSTANCE MAin\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin0 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin0) (3330:3330:3330)) + (WIDTH (negedge MAin0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "CROW_1_") + (INSTANCE CROW\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH CROW1 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW1) (3330:3330:3330)) + (WIDTH (negedge CROW1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "CROW_0_") + (INSTANCE CROW\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH CROW0 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW0) (3330:3330:3330)) + (WIDTH (negedge CROW0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_7_") + (INSTANCE Din\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din7 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din7) (3330:3330:3330)) + (WIDTH (negedge Din7) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_6_") + (INSTANCE Din\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din6 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din6) (3330:3330:3330)) + (WIDTH (negedge Din6) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_5_") + (INSTANCE Din\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din5 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din5) (3330:3330:3330)) + (WIDTH (negedge Din5) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_4_") + (INSTANCE Din\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din4 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din4) (3330:3330:3330)) + (WIDTH (negedge Din4) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_3_") + (INSTANCE Din\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din3 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din3) (3330:3330:3330)) + (WIDTH (negedge Din3) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_2_") + (INSTANCE Din\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din2 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din2) (3330:3330:3330)) + (WIDTH (negedge Din2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_1_") + (INSTANCE Din\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din1 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din1) (3330:3330:3330)) + (WIDTH (negedge Din1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_0_") + (INSTANCE Din\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din0 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din0) (3330:3330:3330)) + (WIDTH (negedge Din0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nCCAS") + (INSTANCE nCCAS_I) + (DELAY + (ABSOLUTE + (IOPATH nCCAS PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nCCAS) (3330:3330:3330)) + (WIDTH (negedge nCCAS) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nCRAS") + (INSTANCE nCRAS_I) + (DELAY + (ABSOLUTE + (IOPATH nCRAS PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nCRAS) (3330:3330:3330)) + (WIDTH (negedge nCRAS) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nFWE") + (INSTANCE nFWE_I) + (DELAY + (ABSOLUTE + (IOPATH nFWE PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nFWE) (3330:3330:3330)) + (WIDTH (negedge nFWE) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RCLK") + (INSTANCE RCLK_I) + (DELAY + (ABSOLUTE + (IOPATH RCLK PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RCLK) (3330:3330:3330)) + (WIDTH (negedge RCLK) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "UFMSDO") + (INSTANCE UFMSDO_I) + (DELAY + (ABSOLUTE + (IOPATH UFMSDO PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge UFMSDO) (3330:3330:3330)) + (WIDTH (negedge UFMSDO) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RAM2GS") + (INSTANCE ) + (DELAY + (ABSOLUTE + (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_76/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_80/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_82/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_85/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q0 SLICE_0/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q0 SLICE_85/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q0 SLICE_105/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/F1 SLICE_0/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/F0 SLICE_0/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_0/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_1/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_2/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_3/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_4/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_5/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_6/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_7/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_8/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_9/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_16/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_26/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_27/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_30/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_32/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_35/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_36/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_37/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_44/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_45/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_57/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_59/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_61/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_62/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_64/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_65/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_66/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_67/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_68/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_69/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_70/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_75/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_78/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_79/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_81/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_84/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_86/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_97/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_98/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_106/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/FCO SLICE_0/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/FCO SLICE_9/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_1/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_76/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_80/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_85/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_105/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_57/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_70/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_76/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_80/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_82/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_85/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_105/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/F1 SLICE_1/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/F0 SLICE_1/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/FCO SLICE_1/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_45/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_68/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_95/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_95/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/F1 SLICE_2/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/F0 SLICE_2/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/FCO SLICE_2/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/FCO SLICE_6/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_86/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_105/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_95/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_95/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/F1 SLICE_3/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/F0 SLICE_3/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/FCO SLICE_3/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_95/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q0 SLICE_44/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q0 SLICE_95/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/F1 SLICE_4/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/F0 SLICE_4/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/FCO SLICE_4/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/FCO SLICE_8/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_68/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/F1 SLICE_5/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/Q1 SLICE_5/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/Q1 SLICE_66/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/Q1 SLICE_96/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_96/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_96/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_6/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_45/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_57/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_70/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_76/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_82/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q0 SLICE_6/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q0 SLICE_86/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q0 SLICE_95/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/F1 SLICE_6/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/F0 SLICE_6/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q0 SLICE_7/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q0 SLICE_82/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q0 SLICE_85/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/F0 SLICE_7/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/FCO SLICE_7/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q1 SLICE_8/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q1 SLICE_44/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q1 SLICE_86/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q0 SLICE_8/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q0 SLICE_86/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/F1 SLICE_8/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/F0 SLICE_8/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q1 SLICE_9/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q1 SLICE_85/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q1 SLICE_105/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q0 SLICE_9/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q0 SLICE_85/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q0 SLICE_105/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/F1 SLICE_9/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/F0 SLICE_9/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_10/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_24/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_33/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_50/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_89/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_89/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_89/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_90/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_102/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_106/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_10/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_24/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_33/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_33/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_75/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_77/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_88/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_101/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_10/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_50/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_90/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_90/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_90/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_93/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_100/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_10/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_24/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_33/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_88/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_90/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_90/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_101/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106/F1 SLICE_10/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_10/F1 SLICE_10/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/F0 SLICE_10/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_10/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_73/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_10/F0 SLICE_10/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F0 SLICE_10/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F0 SLICE_10/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F0 SLICE_15/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F0 SLICE_88/C1 (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_10/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_15/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_19/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_20/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_24/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_33/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_50/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_86/M0 (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_93/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_99/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_100/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_101/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_102/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_103/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_10/Q0 SLICE_88/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_15/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_73/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_74/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_79/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_83/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_91/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_91/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_104/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_15/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_79/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_82/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_101/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/F1 SLICE_15/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/F1 SLICE_79/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_15/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_79/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_91/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_103/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_15/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_19/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_73/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_74/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_79/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_83/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_91/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_91/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_97/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_102/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_15/Q0 SLICE_15/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_15/Q0 SLICE_77/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_15/F1 SLICE_15/B0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_15/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_25/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_25/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_74/D0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_79/C0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_104/B1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_104/C0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_106/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_15/F0 SLICE_15/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_16/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_88/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_89/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_90/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_92/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_104/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/F0 SLICE_16/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/F0 SLICE_25/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/Q0 SLICE_16/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/F0 SLICE_19/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_19/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_24/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_25/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_75/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_77/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_89/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_89/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_89/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_102/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/F0 SLICE_19/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/F0 SLICE_77/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/F0 SLICE_19/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/F0 SLICE_75/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/F1 SLICE_19/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/F1 SLICE_19/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/F1 SLICE_77/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F0 SLICE_19/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F0 SLICE_88/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/F0 SLICE_19/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F1 SLICE_19/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/Q0 SLICE_73/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/Q0 SLICE_83/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_20/F0 SLICE_20/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/F1 SLICE_20/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_20/Q0 SLICE_35/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_20/Q0 SLICE_84/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24/F1 SLICE_24/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24/F1 SLICE_50/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24/F1 SLICE_83/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57/Q0 SLICE_24/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57/Q0 SLICE_33/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_24/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_50/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_90/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_90/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_90/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_93/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_99/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_106/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24/F0 SLICE_24/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/F0 SLICE_24/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24/Q0 SLICE_57/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_25/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_50/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_75/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_77/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_89/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_89/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_92/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_103/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F0 SLICE_25/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_25/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_30/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_30/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_74/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_76/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_82/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_87/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_91/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_104/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_65/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 i30\/SLICE_71/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 i30\/SLICE_71/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_81/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_96/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q1 SLICE_30/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q1 SLICE_59/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q1 i30\/SLICE_71/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q1 i30\/SLICE_71/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q1 SLICE_81/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q1 SLICE_96/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q1 SLICE_96/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/F0 SLICE_26/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F0 SLICE_26/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_32/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_35/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_35/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_44/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_45/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_57/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_62/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_70/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_70/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_72/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_76/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_80/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_84/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_92/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_92/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_27/F0 SLICE_27/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/F0 SLICE_27/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_27/Q0 SLICE_30/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_27/Q0 SLICE_50/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/F0 SLICE_30/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q0 SLICE_30/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q0 SLICE_36/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/F1 LED_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_32/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_36/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_59/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_61/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_62/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_66/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_67/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_69/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_69/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 i30\/SLICE_71/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_72/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_78/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_86/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_92/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_92/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_32/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_59/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_61/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_62/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_62/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_68/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 i30\/SLICE_71/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_78/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_87/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_92/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_92/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_94/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_94/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 SLICE_32/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 SLICE_59/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 SLICE_64/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 SLICE_84/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_32/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_33/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_35/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_59/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_61/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_62/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_64/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_72/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_74/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_76/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_82/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_87/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_87/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_91/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_92/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_94/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_94/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_104/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32/F1 SLICE_32/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_32/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_62/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_92/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_98/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32/F0 SLICE_32/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/Q1 SLICE_32/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/Q1 SLICE_64/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/Q1 SLICE_79/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32/Q0 RA\[10\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_50/Q0 SLICE_33/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_33/F0 SLICE_33/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_33/Q0 RA\[11\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_33/F1 SLICE_73/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q1 SLICE_35/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q1 SLICE_69/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q1 SLICE_84/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q1 SLICE_35/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q1 SLICE_84/A1 (0:0:0)(0:0:0)) + (INTERCONNECT i30\/SLICE_71/OFX0 SLICE_35/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/F0 SLICE_35/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/F1 SLICE_35/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/F1 SLICE_59/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/F1 SLICE_61/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/F1 SLICE_62/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/Q0 SLICE_36/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/F1 SLICE_44/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/F1 SLICE_45/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/F1 SLICE_70/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/Q1 SLICE_36/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/F0 SLICE_36/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/Q0 SLICE_36/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_61/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_69/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_78/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 RCKE_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/F0 SLICE_37/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_72/F1 SLICE_37/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F1 SLICE_44/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F1 SLICE_44/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F1 SLICE_70/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F1 SLICE_82/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/Q0 SLICE_44/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/F1 SLICE_44/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/F0 SLICE_44/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F0 SLICE_44/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F0 SLICE_45/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/Q0 UFMCLK_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F0 SLICE_45/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F0 SLICE_57/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F0 SLICE_76/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F0 SLICE_80/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F0 SLICE_85/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95/F1 SLICE_45/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 SLICE_45/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/Q0 SLICE_45/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_45/F1 SLICE_45/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_45/F0 SLICE_45/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_45/Q0 UFMSDI_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_50/F1 SLICE_50/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_50/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_77/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_88/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_92/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_97/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_100/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_103/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_106/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_50/F0 SLICE_50/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/F1 SLICE_50/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F1 SLICE_57/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F1 SLICE_80/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F1 SLICE_95/A1 (0:0:0)(0:0:0)) + (INTERCONNECT UFMSDO_I/PADDI SLICE_57/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57/F1 SLICE_57/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57/F1 SLICE_84/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57/F0 SLICE_57/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/F0 SLICE_57/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F0 SLICE_59/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F0 SLICE_61/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_59/F1 SLICE_59/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F0 SLICE_59/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F0 SLICE_64/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_59/F0 SLICE_59/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_59/Q0 nRCAS_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61/F1 SLICE_61/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62/F1 SLICE_61/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62/F1 SLICE_62/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61/F0 SLICE_61/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61/Q0 nRCS_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/F1 SLICE_62/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62/F0 SLICE_62/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62/Q0 nRRAS_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/F1 SLICE_64/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/F1 SLICE_64/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/F0 SLICE_64/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94/F0 SLICE_64/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94/F0 SLICE_65/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 nRWE_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_65/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_67/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 i30\/SLICE_71/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_81/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_87/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_65/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_66/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_66/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_81/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_87/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/F1 SLICE_65/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/F1 SLICE_65/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/F1 SLICE_78/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/F1 SLICE_94/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94/F1 SLICE_65/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/F0 SLICE_65/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_93/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_93/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_98/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_98/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_99/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_100/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_101/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_101/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_102/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_102/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_103/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_103/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_66/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_67/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_72/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_87/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_94/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/F0 SLICE_66/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/F1 i30\/SLICE_71/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/F0 SLICE_67/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/F0 SLICE_68/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/Q1 SLICE_68/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/Q0 SLICE_68/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/F0 SLICE_74/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/F1 SLICE_86/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/F0 SLICE_69/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/F1 SLICE_70/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/F1 SLICE_76/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/Q1 SLICE_70/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_70/F1 SLICE_70/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_70/F0 SLICE_70/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_70/Q0 nUFMCS_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_72/F0 SLICE_72/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/Q1 SLICE_72/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/Q1 SLICE_98/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73/F0 SLICE_73/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73/F0 SLICE_74/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_73/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_74/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_79/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_83/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_91/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_91/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_104/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_73/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_74/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_77/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_83/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_88/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_91/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_97/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_97/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_101/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73/F1 SLICE_99/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73/F1 SLICE_100/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/Q1 SLICE_74/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F1 SLICE_74/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/Q0 SLICE_74/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F0 SLICE_89/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F0 SLICE_89/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_101/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q1 SLICE_102/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/F0 SLICE_75/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106/F0 SLICE_75/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106/F0 SLICE_83/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/Q0 SLICE_75/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/Q1 SLICE_75/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_75/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_78/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_79/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_81/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_84/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_97/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_98/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_106/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/F1 SLICE_88/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_76/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_93/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_93/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_98/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[8\]_I/PADDI SLICE_76/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[8\]_I/PADDI SLICE_98/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/Q0 SLICE_98/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/Q1 SLICE_93/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/F1 SLICE_97/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/F0 SLICE_78/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/F0 SLICE_78/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/F0 SLICE_81/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/Q0 SLICE_78/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/Q1 SLICE_78/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/Q1 SLICE_81/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/Q0 SLICE_79/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F1 SLICE_81/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/Q0 SLICE_81/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F0 SLICE_82/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_82/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_100/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_102/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/Q0 SLICE_102/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/Q1 SLICE_101/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/F0 SLICE_83/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/F0 SLICE_84/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/F1 SLICE_84/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/Q0 SLICE_84/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/Q1 SLICE_106/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/F1 SLICE_86/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95/F0 SLICE_86/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/F0 SLICE_87/D1 (0:0:0)(0:0:0)) + (INTERCONNECT CROW\[1\]_I/PADDI SLICE_87/M1 (0:0:0)(0:0:0)) + (INTERCONNECT CROW\[0\]_I/PADDI SLICE_87/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q0 RBA\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q1 RBA\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/F1 SLICE_88/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/F1 SLICE_88/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/Q0 RD\[6\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/Q1 RD\[7\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/Q0 RD\[4\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/Q1 RD\[5\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/Q0 RD\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/Q1 RD\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_91/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_99/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_103/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/Q0 SLICE_103/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/Q1 SLICE_103/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/Q0 RD\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/Q1 RD\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/F0 RA\[9\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/Q0 SLICE_100/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/F1 RDQML_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/Q1 SLICE_99/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/Q0 SLICE_97/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106/Q1 SLICE_97/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/F0 RA\[8\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/F1 RDQMH_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/Q0 SLICE_99/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_99/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_99/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_104/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/Q1 SLICE_99/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/F0 RA\[7\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/Q1 SLICE_100/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_100/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_100/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_104/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/Q0 SLICE_100/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F0 RA\[6\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/F0 RA\[5\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/F1 RA\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/F0 RA\[4\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/F1 RA\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/F0 RA\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/F1 RA\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 RD\[7\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 RD\[6\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 RD\[5\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 RD\[4\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 RD\[3\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 RD\[2\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 RD\[1\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 RD\[0\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106/Q0 SLICE_106/M1 (0:0:0)(0:0:0)) + (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (0:0:0)(0:0:0)) + ) + ) + ) +) diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.vo b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.vo new file mode 100644 index 0000000..49fcc79 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.vo @@ -0,0 +1,3692 @@ + +// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 + +// ldbanno -n Verilog -o RAM2GS_LCMXO2_640HC_impl1_mapvo.vo -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd +// Netlist created on Tue Aug 15 05:03:24 2023 +// Netlist written on Tue Aug 15 05:03:26 2023 +// Design is for device LCMXO2-640HC +// Design is for package TQFP100 +// Design is for performance grade 4 + +`timescale 1 ns / 1 ps + +module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, + RD, nRCS, RCLK, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, + UFMCLK, UFMSDI, UFMSDO ); + input PHI2; + input [9:0] MAin; + input [1:0] CROW; + input [7:0] Din; + input nCCAS, nCRAS, nFWE, RCLK, UFMSDO; + output [7:0] Dout; + output LED; + output [1:0] RBA; + output [11:0] RA; + output nRCS, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI; + inout [7:0] RD; + wire FS_14, FS_13, n81, n82, RCLK_c, n1998, n1999, FS_12, FS_11, n83, n84, + n1997, FS_8, FS_7, n87, n88, n1995, n1996, FS_6, FS_5, n89, n90, + n1994, FS_2, FS_1, n93, n94, n1992, n1993, FS_0, n95, CASr2, CASr3, + FS_10, FS_9, n85, n86, FS_17, n78, n2000, FS_4, FS_3, n91, n92, FS_16, + FS_15, n79, n80, Din_c_4, Din_c_6, Din_c_1, Din_c_7, n2382, n8, n2225, + n2180, ADSubmitted_N_246, PHI2_N_120_enable_2, C1Submitted_N_237, + PHI2_c, ADSubmitted, n26, MAin_c_5, n22, MAin_c_2, MAin_c_1, + C1Submitted, n2365, nFWE_c, n1398, nCCAS_c, nCCAS_N_3, CASr, n2254, + Din_c_5, n2191, n2183, n15_adj_1, n2208, n2363, CmdEnable_N_248, + PHI2_N_120_enable_1, CmdEnable, \n2447\001/BUF1 , PHI2_N_120_enable_7, + CmdSubmitted, n1314, n8MEGEN, Din_c_0, Cmdn8MEGEN_N_264, + PHI2_N_120_enable_6, Cmdn8MEGEN, Din_c_3, n2373, nCRAS_c, FWEr, CBR, + \n2447\000/BUF1 , RCLK_c_enable_28, InitReady, n2447, + RCLK_c_enable_16, LEDEN, nCRAS_c__inv, RASr, LED_c, RASr2, + nRowColSel_N_35, nRCAS_N_165, Ready, n2381, nRCS_N_139, n2036, + nRWE_N_177, RA_0, XOR8MEG, RA11_N_184, RA_c, n6_adj_2, PHI2r2, PHI2r3, + n15_adj_4, RCKEEN_N_121, RCLK_c_enable_6, RCKEEN, RCLK_c_enable_10, + RASr3, RCKE_N_132, PHI2r, RCKE_c, \n2447\002/BUF1 , Ready_N_292, + n2267, n13_adj_6, CmdUFMCLK, n1893, UFMCLK_N_224, n2366, UFMCLK_c, + n10, n7, n4, CmdUFMSDI, n2174, UFMSDI_N_231, UFMSDI_c, n2260, Din_c_2, + XOR8MEG_N_110, PHI2_N_120_enable_3, n2375, UFMSDO_c, n2367, + n8MEGEN_N_91, RCLK_c_enable_15, nRCS_N_142, nRCAS_N_166, n2371, + nRCAS_N_161, nRCAS_c, nRCS_N_141, nRCS_N_137, nRCS_N_136, nRCS_c, + n2379, nRRAS_N_156, nRRAS_c, nRWE_N_178, n1765, nRWE_N_171, + RCLK_c_enable_5, nRWE_c, nRowColSel_N_34, nRowColSel_N_33, n2376, + n1060, n2372, n917, nRowColSel, nRowColSel_N_32, n827, n2227, n1406, + Bank_3, Bank_6, n2287, n13, n2374, n2368, CmdUFMCS, n64, nUFMCS_N_199, + nUFMCS_c, n6_adj_3, Ready_N_296, n2204, n2369, MAin_c_0, + PHI2_N_120_enable_8, Bank_5, n2277, Bank_2, n2220, RowA_0, RowA_1, + n2370, n2228, n732, n733, RCLK_c_enable_27, n2055, MAin_c_9, MAin_c_8, + RowA_8, RowA_9, n2210, nRWE_N_182, nRCS_N_146, n728, n729, n727, n730, + n2378, n726, n12, MAin_c_4, RowA_4, RowA_5, n1277, n4_adj_7, n2377, + n738, n737, n14, n15, n6, CROW_c_1, CROW_c_0, RBA_c_0, RBA_c_1, + n7_adj_5, n2362, WRD_6, WRD_7, WRD_4, WRD_5, WRD_0, WRD_1, MAin_c_3, + RowA_2, RowA_3, WRD_2, WRD_3, RA_1_9, Bank_0, RDQML_c, Bank_1, n734, + n735, RA_1_8, RDQMH_c, Bank_4, MAin_c_7, RowA_7, RA_1_7, Bank_7, + MAin_c_6, RowA_6, RA_1_6, RA_1_5, RA_1_0, RA_1_4, RA_1_1, RA_1_3, + RA_1_2, n984, n736, Dout_c, Dout_0, Dout_1, Dout_2, Dout_3, Dout_4, + Dout_5, Dout_6, VCCI; + + SLICE_0 SLICE_0( .A1(FS_14), .A0(FS_13), .DI1(n81), .DI0(n82), .CLK(RCLK_c), + .FCI(n1998), .F0(n82), .Q0(FS_13), .F1(n81), .Q1(FS_14), .FCO(n1999)); + SLICE_1 SLICE_1( .A1(FS_12), .A0(FS_11), .DI1(n83), .DI0(n84), .CLK(RCLK_c), + .FCI(n1997), .F0(n84), .Q0(FS_11), .F1(n83), .Q1(FS_12), .FCO(n1998)); + SLICE_2 SLICE_2( .A1(FS_8), .A0(FS_7), .DI1(n87), .DI0(n88), .CLK(RCLK_c), + .FCI(n1995), .F0(n88), .Q0(FS_7), .F1(n87), .Q1(FS_8), .FCO(n1996)); + SLICE_3 SLICE_3( .A1(FS_6), .A0(FS_5), .DI1(n89), .DI0(n90), .CLK(RCLK_c), + .FCI(n1994), .F0(n90), .Q0(FS_5), .F1(n89), .Q1(FS_6), .FCO(n1995)); + SLICE_4 SLICE_4( .A1(FS_2), .A0(FS_1), .DI1(n93), .DI0(n94), .CLK(RCLK_c), + .FCI(n1992), .F0(n94), .Q0(FS_1), .F1(n93), .Q1(FS_2), .FCO(n1993)); + SLICE_5 SLICE_5( .A1(FS_0), .DI1(n95), .M0(CASr2), .CLK(RCLK_c), .Q0(CASr3), + .F1(n95), .Q1(FS_0), .FCO(n1992)); + SLICE_6 SLICE_6( .A1(FS_10), .A0(FS_9), .DI1(n85), .DI0(n86), .CLK(RCLK_c), + .FCI(n1996), .F0(n86), .Q0(FS_9), .F1(n85), .Q1(FS_10), .FCO(n1997)); + SLICE_7 SLICE_7( .A0(FS_17), .DI0(n78), .CLK(RCLK_c), .FCI(n2000), .F0(n78), + .Q0(FS_17)); + SLICE_8 SLICE_8( .A1(FS_4), .A0(FS_3), .DI1(n91), .DI0(n92), .CLK(RCLK_c), + .FCI(n1993), .F0(n92), .Q0(FS_3), .F1(n91), .Q1(FS_4), .FCO(n1994)); + SLICE_9 SLICE_9( .A1(FS_16), .A0(FS_15), .DI1(n79), .DI0(n80), .CLK(RCLK_c), + .FCI(n1999), .F0(n80), .Q0(FS_15), .F1(n79), .Q1(FS_16), .FCO(n2000)); + SLICE_10 SLICE_10( .D1(Din_c_4), .C1(Din_c_6), .B1(Din_c_1), .A1(Din_c_7), + .D0(n2382), .C0(n8), .B0(n2225), .A0(n2180), .DI0(ADSubmitted_N_246), + .CE(PHI2_N_120_enable_2), .LSR(C1Submitted_N_237), .CLK(PHI2_c), + .F0(ADSubmitted_N_246), .Q0(ADSubmitted), .F1(n8)); + SLICE_15 SLICE_15( .D1(n26), .C1(MAin_c_5), .B1(n22), .A1(MAin_c_2), + .D0(MAin_c_1), .C0(C1Submitted), .B0(n2365), .A0(nFWE_c), .DI0(n1398), + .LSR(C1Submitted_N_237), .CLK(PHI2_c), .F0(n1398), .Q0(C1Submitted), + .F1(n2365)); + SLICE_16 SLICE_16( .A0(nCCAS_c), .DI0(nCCAS_N_3), .M1(CASr), .CLK(RCLK_c), + .F0(nCCAS_N_3), .Q0(CASr), .Q1(CASr2)); + SLICE_19 SLICE_19( .D1(n2254), .C1(Din_c_5), .B1(n2191), .A1(n2183), + .D0(n15_adj_1), .C0(n2208), .B0(MAin_c_1), .A0(n2363), + .DI0(CmdEnable_N_248), .CE(PHI2_N_120_enable_1), .CLK(PHI2_c), + .F0(CmdEnable_N_248), .Q0(CmdEnable), .F1(n15_adj_1)); + SLICE_20 SLICE_20( .DI0(\n2447\001/BUF1 ), .CE(PHI2_N_120_enable_7), + .CLK(PHI2_c), .F0(\n2447\001/BUF1 ), .Q0(CmdSubmitted)); + SLICE_24 SLICE_24( .C1(Din_c_5), .B1(Din_c_7), .A1(Din_c_6), .D0(n1314), + .C0(Din_c_4), .B0(n8MEGEN), .A0(Din_c_0), .DI0(Cmdn8MEGEN_N_264), + .CE(PHI2_N_120_enable_6), .CLK(PHI2_c), .F0(Cmdn8MEGEN_N_264), + .Q0(Cmdn8MEGEN), .F1(n1314)); + SLICE_25 SLICE_25( .C1(Din_c_3), .B1(Din_c_5), .A1(nFWE_c), .A0(nFWE_c), + .DI0(n2373), .M1(nCCAS_N_3), .CLK(nCRAS_c), .F0(n2373), .Q0(FWEr), + .F1(n2180), .Q1(CBR)); + SLICE_26 SLICE_26( .DI0(\n2447\000/BUF1 ), .CE(RCLK_c_enable_28), + .CLK(RCLK_c), .F0(\n2447\000/BUF1 ), .Q0(InitReady)); + SLICE_27 SLICE_27( .DI0(n2447), .CE(RCLK_c_enable_16), .CLK(RCLK_c), + .F0(n2447), .Q0(LEDEN)); + SLICE_30 SLICE_30( .C1(CBR), .B1(LEDEN), .A1(nCRAS_c), .A0(nCRAS_c), + .DI0(nCRAS_c__inv), .M1(RASr), .CLK(RCLK_c), .F0(nCRAS_c__inv), .Q0(RASr), + .F1(LED_c), .Q1(RASr2)); + SLICE_32 SLICE_32( .C1(nRowColSel_N_35), .B1(InitReady), .A1(RASr2), + .D0(nRCAS_N_165), .C0(Ready), .B0(n2381), .A0(nRCS_N_139), .DI0(n2036), + .LSR(nRWE_N_177), .CLK(RCLK_c), .F0(n2036), .Q0(RA_0), .F1(n2381)); + SLICE_33 SLICE_33( .C1(Din_c_4), .B1(Din_c_7), .A1(Din_c_6), .C0(n8MEGEN), + .B0(XOR8MEG), .A0(Din_c_6), .DI0(RA11_N_184), .LSR(Ready), .CLK(PHI2_c), + .F0(RA11_N_184), .Q0(RA_c), .F1(n6_adj_2)); + SLICE_35 SLICE_35( .D1(InitReady), .C1(CmdSubmitted), .B1(PHI2r2), + .A1(PHI2r3), .C0(Ready), .B0(n15_adj_4), .A0(InitReady), + .DI0(RCKEEN_N_121), .CE(RCLK_c_enable_6), .CLK(RCLK_c), .F0(RCKEEN_N_121), + .Q0(RCKEEN), .F1(RCLK_c_enable_10)); + SLICE_36 SLICE_36( .D0(RASr3), .C0(RASr2), .B0(RCKEEN), .A0(RASr), + .DI0(RCKE_N_132), .M1(PHI2r), .CLK(RCLK_c), .F0(RCKE_N_132), .Q0(RCKE_c), + .Q1(PHI2r2)); + SLICE_37 SLICE_37( .DI0(\n2447\002/BUF1 ), .CE(Ready_N_292), .CLK(RCLK_c), + .F0(\n2447\002/BUF1 ), .Q0(Ready)); + SLICE_44 SLICE_44( .D1(FS_1), .C1(n2267), .B1(n13_adj_6), .A1(FS_4), + .C0(InitReady), .B0(CmdUFMCLK), .A0(n1893), .DI0(UFMCLK_N_224), + .CE(RCLK_c_enable_10), .LSR(n2366), .CLK(RCLK_c), .F0(UFMCLK_N_224), + .Q0(UFMCLK_c), .F1(n1893)); + SLICE_45 SLICE_45( .D1(n10), .C1(FS_10), .B1(FS_8), .A1(n7), .D0(n4), + .C0(InitReady), .B0(CmdUFMSDI), .A0(n2174), .DI0(UFMSDI_N_231), + .CE(RCLK_c_enable_10), .LSR(n2366), .CLK(RCLK_c), .F0(UFMSDI_N_231), + .Q0(UFMSDI_c), .F1(n2174)); + SLICE_50 SLICE_50( .D1(LEDEN), .C1(n1314), .B1(Din_c_1), .A1(Din_c_4), + .D0(Din_c_3), .C0(n2260), .B0(Din_c_2), .A0(Din_c_0), .DI0(XOR8MEG_N_110), + .CE(PHI2_N_120_enable_3), .CLK(PHI2_c), .F0(XOR8MEG_N_110), .Q0(XOR8MEG), + .F1(n2260)); + SLICE_57 SLICE_57( .D1(FS_10), .C1(FS_11), .B1(n2375), .A1(n10), + .D0(Cmdn8MEGEN), .C0(UFMSDO_c), .B0(n2367), .A0(InitReady), + .DI0(n8MEGEN_N_91), .CE(RCLK_c_enable_15), .CLK(RCLK_c), .F0(n8MEGEN_N_91), + .Q0(n8MEGEN), .F1(n2367)); + SLICE_59 SLICE_59( .D1(CBR), .C1(nRowColSel_N_35), .B1(RASr2), + .A1(nRCS_N_142), .D0(nRCAS_N_166), .C0(Ready), .B0(nRCAS_N_165), + .A0(n2371), .DI0(nRCAS_N_161), .CE(RCLK_c_enable_6), .CLK(RCLK_c), + .F0(nRCAS_N_161), .Q0(nRCAS_c), .F1(nRCAS_N_166)); + SLICE_61 SLICE_61( .D1(nRCS_N_142), .C1(nRowColSel_N_35), .B1(RASr2), + .A1(RCKE_c), .C0(Ready), .B0(nRCS_N_141), .A0(nRCS_N_137), + .DI0(nRCS_N_136), .CE(RCLK_c_enable_6), .CLK(RCLK_c), .F0(nRCS_N_136), + .Q0(nRCS_c), .F1(nRCS_N_141)); + SLICE_62 SLICE_62( .D1(RASr2), .C1(nRowColSel_N_35), .B1(InitReady), + .A1(nRCS_N_139), .D0(nRowColSel_N_35), .C0(Ready), .B0(n2379), + .A0(nRCS_N_137), .DI0(nRRAS_N_156), .CE(RCLK_c_enable_6), .CLK(RCLK_c), + .F0(nRRAS_N_156), .Q0(nRRAS_c), .F1(nRCS_N_137)); + SLICE_64 SLICE_64( .B1(nRCAS_N_165), .A1(nRWE_N_177), .D0(n2371), .C0(Ready), + .B0(nRWE_N_178), .A0(n1765), .DI0(nRWE_N_171), .CE(RCLK_c_enable_5), + .CLK(RCLK_c), .F0(nRWE_N_171), .Q0(nRWE_c), .F1(n1765)); + SLICE_65 SLICE_65( .B1(nRowColSel_N_34), .A1(nRowColSel_N_33), .D0(n2376), + .C0(n1060), .B0(n2372), .A0(FWEr), .DI0(n917), .CE(RCLK_c_enable_5), + .CLK(RCLK_c), .F0(n917), .Q0(nRowColSel), .F1(n1060)); + SLICE_66 SLICE_66( .B1(CASr2), .A1(nRowColSel_N_33), .B0(nRowColSel_N_32), + .A0(nRowColSel_N_33), .DI0(n827), .LSR(RASr2), .CLK(RCLK_c), .F0(n827), + .Q0(nRowColSel_N_32), .F1(n2227)); + SLICE_67 SLICE_67( .B0(nRowColSel_N_32), .A0(RASr2), .DI0(n1406), + .LSR(nRowColSel_N_34), .CLK(RCLK_c), .F0(n1406), .Q0(nRowColSel_N_33)); + SLICE_68 SLICE_68( .B1(FS_0), .A1(FS_8), .B0(Bank_3), .A0(Bank_6), + .M0(n1406), .LSR(nRowColSel_N_35), .CLK(RCLK_c), .F0(n2287), + .Q0(nRowColSel_N_34), .F1(n13)); + SLICE_69 SLICE_69( .B1(RASr2), .A1(RCKE_c), .A0(RASr2), .DI0(n2374), + .M1(PHI2r2), .CLK(RCLK_c), .F0(n2374), .Q0(nRowColSel_N_35), .F1(n2379), + .Q1(PHI2r3)); + SLICE_70 SLICE_70( .D1(FS_10), .C1(InitReady), .B1(n2368), .A1(FS_11), + .D0(InitReady), .C0(CmdUFMCS), .B0(n64), .A0(n13_adj_6), + .DI0(nUFMCS_N_199), .CE(RCLK_c_enable_10), .CLK(RCLK_c), .F0(nUFMCS_N_199), + .Q0(nUFMCS_c), .F1(n64)); + i30_SLICE_71 \i30/SLICE_71 ( .C1(RASr2), .B1(FWEr), .A1(CBR), + .D0(nRowColSel_N_34), .C0(FWEr), .B0(n2227), .A0(CBR), + .M0(nRowColSel_N_35), .OFX0(n15_adj_4)); + SLICE_72 SLICE_72( .D1(Ready), .C1(nRowColSel_N_32), .B1(n6_adj_3), + .A1(RASr2), .B0(Ready_N_296), .A0(InitReady), .F0(n6_adj_3), + .F1(Ready_N_292)); + SLICE_73 SLICE_73( .D1(n2204), .C1(n2180), .B1(n26), .A1(n2369), + .D0(n6_adj_2), .C0(CmdEnable), .B0(MAin_c_0), .A0(MAin_c_1), .F0(n2204), + .F1(PHI2_N_120_enable_8)); + SLICE_74 SLICE_74( .D1(Bank_5), .C1(n2287), .B1(n2277), .A1(Bank_2), + .D0(nFWE_c), .C0(n2204), .B0(n26), .A0(n2369), .M1(MAin_c_1), + .M0(MAin_c_0), .LSR(Ready), .CLK(nCRAS_c), .F0(n2220), .Q0(RowA_0), + .F1(n26), .Q1(RowA_1)); + SLICE_75 SLICE_75( .D1(n2370), .C1(n2183), .B1(n2228), .A1(Din_c_5), + .B0(Din_c_3), .A0(Din_c_6), .M1(n732), .M0(n733), .CE(RCLK_c_enable_27), + .CLK(RCLK_c), .F0(n2183), .Q0(n732), .F1(n2055), .Q1(nRWE_N_177)); + SLICE_76 SLICE_76( .C1(n10), .B1(FS_14), .A1(FS_12), .D0(InitReady), + .C0(n2368), .B0(FS_11), .A0(FS_10), .M1(MAin_c_9), .M0(MAin_c_8), + .LSR(Ready), .CLK(nCRAS_c), .F0(RCLK_c_enable_16), .Q0(RowA_8), .F1(n2368), + .Q1(RowA_9)); + SLICE_77 SLICE_77( .D1(n2208), .C1(C1Submitted), .B1(n2191), .A1(Din_c_5), + .D0(MAin_c_0), .C0(Din_c_6), .B0(Din_c_3), .A0(Din_c_2), .F0(n2191), + .F1(n2210)); + SLICE_78 SLICE_78( .D1(nRowColSel_N_35), .C1(nRWE_N_182), .B1(n1060), + .A1(nRCS_N_146), .B0(RASr2), .A0(RCKE_c), .M1(n728), .M0(n729), + .CE(RCLK_c_enable_27), .CLK(RCLK_c), .F0(nRWE_N_182), .Q0(n728), + .F1(nRWE_N_178), .Q1(n727)); + SLICE_79 SLICE_79( .C1(MAin_c_5), .B1(n22), .A1(MAin_c_2), .D0(MAin_c_1), + .C0(nFWE_c), .B0(n26), .A0(n2369), .M1(n730), .M0(nRWE_N_177), + .CE(RCLK_c_enable_27), .CLK(RCLK_c), .F0(PHI2_N_120_enable_2), .Q0(n730), + .F1(n2369), .Q1(n729)); + SLICE_80 SLICE_80( .B1(FS_14), .A1(FS_12), .D0(FS_11), .C0(InitReady), + .B0(n2375), .A0(n10), .F0(n2366), .F1(n2375)); + SLICE_81 SLICE_81( .B1(CBR), .A1(FWEr), .D0(nRowColSel_N_33), .C0(n2378), + .B0(nRowColSel_N_34), .A0(nRCS_N_146), .M1(n726), .M0(n727), + .CE(RCLK_c_enable_27), .CLK(RCLK_c), .F0(nRCS_N_142), .Q0(n726), + .F1(n2378), .Q1(Ready_N_296)); + SLICE_82 SLICE_82( .D1(FS_17), .C1(FS_14), .B1(n12), .A1(FS_11), + .B0(n13_adj_6), .A0(FS_10), .M1(MAin_c_5), .M0(MAin_c_4), .LSR(Ready), + .CLK(nCRAS_c), .F0(RCLK_c_enable_28), .Q0(RowA_4), .F1(n13_adj_6), + .Q1(RowA_5)); + SLICE_83 SLICE_83( .D1(n1314), .C1(n1277), .B1(CmdEnable), .A1(n2228), + .D0(MAin_c_1), .C0(MAin_c_0), .B0(n26), .A0(n2369), .F0(n1277), + .F1(PHI2_N_120_enable_3)); + SLICE_84 SLICE_84( .C1(CmdSubmitted), .B1(PHI2r2), .A1(PHI2r3), + .D0(n4_adj_7), .C0(InitReady), .B0(n2377), .A0(n2367), .M1(n738), + .M0(nRCAS_N_165), .CE(RCLK_c_enable_27), .CLK(RCLK_c), + .F0(RCLK_c_enable_15), .Q0(n738), .F1(n2377), .Q1(n737)); + SLICE_85 SLICE_85( .D1(n10), .C1(FS_11), .B1(FS_14), .A1(FS_12), .D0(FS_16), + .C0(FS_15), .B0(FS_13), .A0(FS_17), .F0(n10), .F1(n2267)); + SLICE_86 SLICE_86( .C1(FS_6), .B1(FS_9), .A1(FS_3), .D0(n14), .C0(n13), + .B0(n15), .A0(FS_4), .M1(RASr2), .M0(PHI2_c), .CLK(RCLK_c), .F0(n4_adj_7), + .Q0(PHI2r), .F1(n14), .Q1(RASr3)); + SLICE_87 SLICE_87( .D1(n6), .C1(nRowColSel_N_32), .B1(nRowColSel_N_33), + .A1(nRowColSel_N_35), .B0(nRowColSel_N_34), .A0(Ready), .M1(CROW_c_1), + .M0(CROW_c_0), .LSR(Ready), .CLK(nCRAS_c), .F0(n6), .Q0(RBA_c_0), + .F1(RCLK_c_enable_6), .Q1(RBA_c_1)); + SLICE_88 SLICE_88( .D1(n2363), .C1(C1Submitted_N_237), .B1(ADSubmitted), + .A1(n7_adj_5), .D0(n2362), .C0(MAin_c_0), .B0(n2055), .A0(Din_c_2), + .M1(Din_c_7), .M0(Din_c_6), .CLK(nCCAS_c), .F0(C1Submitted_N_237), + .Q0(WRD_6), .F1(PHI2_N_120_enable_1), .Q1(WRD_7)); + SLICE_89 SLICE_89( .D1(Din_c_5), .C1(Din_c_3), .B1(Din_c_4), .A1(n2220), + .D0(Din_c_3), .C0(Din_c_4), .B0(n2220), .A0(Din_c_5), .M1(Din_c_5), + .M0(Din_c_4), .CLK(nCCAS_c), .F0(PHI2_N_120_enable_6), .Q0(WRD_4), + .F1(PHI2_N_120_enable_7), .Q1(WRD_5)); + SLICE_90 SLICE_90( .D1(Din_c_0), .C1(Din_c_4), .B1(Din_c_1), .A1(Din_c_7), + .C0(Din_c_0), .B0(Din_c_1), .A0(Din_c_7), .M1(Din_c_1), .M0(Din_c_0), + .CLK(nCCAS_c), .F0(n2370), .Q0(WRD_0), .F1(n2208), .Q1(WRD_1)); + SLICE_91 SLICE_91( .C1(MAin_c_1), .B1(n26), .A1(n2369), .D0(MAin_c_1), + .C0(MAin_c_0), .B0(n26), .A0(n2369), .M1(MAin_c_3), .M0(MAin_c_2), + .LSR(Ready), .CLK(nCRAS_c), .F0(n2225), .Q0(RowA_2), .F1(n2362), + .Q1(RowA_3)); + SLICE_92 SLICE_92( .D1(Ready), .C1(nRowColSel_N_35), .B1(InitReady), + .A1(RASr2), .D0(nRCS_N_139), .C0(nRowColSel_N_35), .B0(InitReady), + .A0(RASr2), .M1(Din_c_3), .M0(Din_c_2), .CLK(nCCAS_c), .F0(n2371), + .Q0(WRD_2), .F1(RCLK_c_enable_27), .Q1(WRD_3)); + SLICE_93 SLICE_93( .B1(nRowColSel), .A1(MAin_c_9), .C0(nRowColSel), + .B0(MAin_c_9), .A0(RowA_9), .M1(Din_c_1), .M0(Din_c_0), .CLK(PHI2_c), + .F0(RA_1_9), .Q0(Bank_0), .F1(RDQML_c), .Q1(Bank_1)); + SLICE_94 SLICE_94( .B1(nRowColSel_N_35), .A1(Ready), .D0(nRowColSel_N_35), + .C0(nRowColSel_N_32), .B0(n1060), .A0(Ready), .F0(RCLK_c_enable_5), + .F1(n2372)); + SLICE_95 SLICE_95( .D1(FS_5), .C1(FS_9), .B1(FS_7), .A1(n2375), .D0(FS_2), + .C0(FS_1), .B0(FS_7), .A0(FS_5), .F0(n15), .F1(n7)); + SLICE_96 SLICE_96( .B1(CASr3), .A1(CBR), .D0(CASr2), .C0(FWEr), .B0(CASr3), + .A0(CBR), .F0(nRCS_N_146), .F1(n2376)); + SLICE_97 SLICE_97( .C1(MAin_c_1), .B1(n2210), .A1(MAin_c_0), .B0(Din_c_2), + .A0(MAin_c_0), .M1(n734), .M0(n735), .CE(RCLK_c_enable_27), .CLK(RCLK_c), + .F0(n2254), .Q0(n734), .F1(n7_adj_5), .Q1(n733)); + SLICE_98 SLICE_98( .B1(nRowColSel), .A1(MAin_c_9), .C0(nRowColSel), + .B0(MAin_c_8), .A0(RowA_8), .M1(nRCS_N_139), .M0(Ready_N_296), + .CE(RCLK_c_enable_27), .CLK(RCLK_c), .F0(RA_1_8), .Q0(nRCS_N_139), + .F1(RDQMH_c), .Q1(nRCAS_N_165)); + SLICE_99 SLICE_99( .D1(Bank_1), .C1(Bank_4), .B1(MAin_c_3), .A1(MAin_c_7), + .C0(nRowColSel), .B0(MAin_c_7), .A0(RowA_7), .M0(Din_c_0), + .CE(PHI2_N_120_enable_8), .CLK(PHI2_c), .F0(RA_1_7), .Q0(CmdUFMSDI), + .F1(n22)); + SLICE_100 SLICE_100( .D1(Bank_0), .C1(Bank_7), .B1(MAin_c_4), .A1(MAin_c_6), + .C0(nRowColSel), .B0(MAin_c_6), .A0(RowA_6), .M1(Din_c_2), .M0(Din_c_1), + .CE(PHI2_N_120_enable_8), .CLK(PHI2_c), .F0(RA_1_6), .Q0(CmdUFMCLK), + .F1(n2277), .Q1(CmdUFMCS)); + SLICE_101 SLICE_101( .C1(nRowColSel), .B1(MAin_c_0), .A1(RowA_0), + .C0(nRowColSel), .B0(MAin_c_5), .A0(RowA_5), .M1(Din_c_7), .M0(Din_c_6), + .CLK(PHI2_c), .F0(RA_1_5), .Q0(Bank_6), .F1(RA_1_0), .Q1(Bank_7)); + SLICE_102 SLICE_102( .C1(nRowColSel), .B1(MAin_c_1), .A1(RowA_1), + .C0(nRowColSel), .B0(MAin_c_4), .A0(RowA_4), .M1(Din_c_5), .M0(Din_c_4), + .CLK(PHI2_c), .F0(RA_1_4), .Q0(Bank_4), .F1(RA_1_1), .Q1(Bank_5)); + SLICE_103 SLICE_103( .C1(nRowColSel), .B1(MAin_c_2), .A1(RowA_2), + .C0(nRowColSel), .B0(MAin_c_3), .A0(RowA_3), .M1(Din_c_3), .M0(Din_c_2), + .CLK(PHI2_c), .F0(RA_1_3), .Q0(Bank_2), .F1(RA_1_2), .Q1(Bank_3)); + SLICE_104 SLICE_104( .B1(nFWE_c), .A1(nCCAS_c), .C0(nFWE_c), .B0(n26), + .A0(n2369), .M1(MAin_c_7), .M0(MAin_c_6), .LSR(Ready), .CLK(nCRAS_c), + .F0(n2363), .Q0(RowA_6), .F1(n984), .Q1(RowA_7)); + SLICE_105 SLICE_105( .B1(FS_6), .A1(FS_11), .D0(FS_16), .C0(FS_15), + .B0(FS_12), .A0(FS_13), .F0(n12), .F1(n4)); + SLICE_106 SLICE_106( .B1(Din_c_2), .A1(Din_c_0), .B0(Din_c_4), .A0(nFWE_c), + .M1(n736), .M0(n737), .CE(RCLK_c_enable_27), .CLK(RCLK_c), .F0(n2228), + .Q0(n736), .F1(n2382), .Q1(n735)); + RD_7_ \RD[7]_I ( .PADDI(Dout_c), .PADDT(n984), .PADDO(WRD_7), .RD7(RD[7])); + RD_6_ \RD[6]_I ( .PADDI(Dout_0), .PADDT(n984), .PADDO(WRD_6), .RD6(RD[6])); + RD_5_ \RD[5]_I ( .PADDI(Dout_1), .PADDT(n984), .PADDO(WRD_5), .RD5(RD[5])); + RD_4_ \RD[4]_I ( .PADDI(Dout_2), .PADDT(n984), .PADDO(WRD_4), .RD4(RD[4])); + RD_3_ \RD[3]_I ( .PADDI(Dout_3), .PADDT(n984), .PADDO(WRD_3), .RD3(RD[3])); + RD_2_ \RD[2]_I ( .PADDI(Dout_4), .PADDT(n984), .PADDO(WRD_2), .RD2(RD[2])); + RD_1_ \RD[1]_I ( .PADDI(Dout_5), .PADDT(n984), .PADDO(WRD_1), .RD1(RD[1])); + RD_0_ \RD[0]_I ( .PADDI(Dout_6), .PADDT(n984), .PADDO(WRD_0), .RD0(RD[0])); + Dout_7_ \Dout[7]_I ( .PADDO(Dout_c), .Dout7(Dout[7])); + Dout_6_ \Dout[6]_I ( .PADDO(Dout_0), .Dout6(Dout[6])); + Dout_5_ \Dout[5]_I ( .PADDO(Dout_1), .Dout5(Dout[5])); + Dout_4_ \Dout[4]_I ( .PADDO(Dout_2), .Dout4(Dout[4])); + Dout_3_ \Dout[3]_I ( .PADDO(Dout_3), .Dout3(Dout[3])); + Dout_2_ \Dout[2]_I ( .PADDO(Dout_4), .Dout2(Dout[2])); + Dout_1_ \Dout[1]_I ( .PADDO(Dout_5), .Dout1(Dout[1])); + Dout_0_ \Dout[0]_I ( .PADDO(Dout_6), .Dout0(Dout[0])); + LED LED_I( .PADDO(LED_c), .LED(LED)); + RBA_1_ \RBA[1]_I ( .PADDO(RBA_c_1), .RBA1(RBA[1])); + RBA_0_ \RBA[0]_I ( .PADDO(RBA_c_0), .RBA0(RBA[0])); + RA_11_ \RA[11]_I ( .PADDO(RA_c), .RA11(RA[11])); + RA_10_ \RA[10]_I ( .PADDO(RA_0), .RA10(RA[10])); + RA_9_ \RA[9]_I ( .PADDO(RA_1_9), .RA9(RA[9])); + RA_8_ \RA[8]_I ( .PADDO(RA_1_8), .RA8(RA[8])); + RA_7_ \RA[7]_I ( .PADDO(RA_1_7), .RA7(RA[7])); + RA_6_ \RA[6]_I ( .PADDO(RA_1_6), .RA6(RA[6])); + RA_5_ \RA[5]_I ( .PADDO(RA_1_5), .RA5(RA[5])); + RA_4_ \RA[4]_I ( .PADDO(RA_1_4), .RA4(RA[4])); + RA_3_ \RA[3]_I ( .PADDO(RA_1_3), .RA3(RA[3])); + RA_2_ \RA[2]_I ( .PADDO(RA_1_2), .RA2(RA[2])); + RA_1_ \RA[1]_I ( .PADDO(RA_1_1), .RA1(RA[1])); + RA_0_ \RA[0]_I ( .PADDO(RA_1_0), .RA0(RA[0])); + nRCS nRCS_I( .PADDO(nRCS_c), .nRCS(nRCS)); + RCKE RCKE_I( .PADDO(RCKE_c), .RCKE(RCKE)); + nRWE nRWE_I( .PADDO(nRWE_c), .nRWE(nRWE)); + nRRAS nRRAS_I( .PADDO(nRRAS_c), .nRRAS(nRRAS)); + nRCAS nRCAS_I( .PADDO(nRCAS_c), .nRCAS(nRCAS)); + RDQMH RDQMH_I( .PADDO(RDQMH_c), .RDQMH(RDQMH)); + RDQML RDQML_I( .PADDO(RDQML_c), .RDQML(RDQML)); + nUFMCS nUFMCS_I( .PADDO(nUFMCS_c), .nUFMCS(nUFMCS)); + UFMCLK UFMCLK_I( .PADDO(UFMCLK_c), .UFMCLK(UFMCLK)); + UFMSDI UFMSDI_I( .PADDO(UFMSDI_c), .UFMSDI(UFMSDI)); + PHI2 PHI2_I( .PADDI(PHI2_c), .PHI2(PHI2)); + MAin_9_ \MAin[9]_I ( .PADDI(MAin_c_9), .MAin9(MAin[9])); + MAin_8_ \MAin[8]_I ( .PADDI(MAin_c_8), .MAin8(MAin[8])); + MAin_7_ \MAin[7]_I ( .PADDI(MAin_c_7), .MAin7(MAin[7])); + MAin_6_ \MAin[6]_I ( .PADDI(MAin_c_6), .MAin6(MAin[6])); + MAin_5_ \MAin[5]_I ( .PADDI(MAin_c_5), .MAin5(MAin[5])); + MAin_4_ \MAin[4]_I ( .PADDI(MAin_c_4), .MAin4(MAin[4])); + MAin_3_ \MAin[3]_I ( .PADDI(MAin_c_3), .MAin3(MAin[3])); + MAin_2_ \MAin[2]_I ( .PADDI(MAin_c_2), .MAin2(MAin[2])); + MAin_1_ \MAin[1]_I ( .PADDI(MAin_c_1), .MAin1(MAin[1])); + MAin_0_ \MAin[0]_I ( .PADDI(MAin_c_0), .MAin0(MAin[0])); + CROW_1_ \CROW[1]_I ( .PADDI(CROW_c_1), .CROW1(CROW[1])); + CROW_0_ \CROW[0]_I ( .PADDI(CROW_c_0), .CROW0(CROW[0])); + Din_7_ \Din[7]_I ( .PADDI(Din_c_7), .Din7(Din[7])); + Din_6_ \Din[6]_I ( .PADDI(Din_c_6), .Din6(Din[6])); + Din_5_ \Din[5]_I ( .PADDI(Din_c_5), .Din5(Din[5])); + Din_4_ \Din[4]_I ( .PADDI(Din_c_4), .Din4(Din[4])); + Din_3_ \Din[3]_I ( .PADDI(Din_c_3), .Din3(Din[3])); + Din_2_ \Din[2]_I ( .PADDI(Din_c_2), .Din2(Din[2])); + Din_1_ \Din[1]_I ( .PADDI(Din_c_1), .Din1(Din[1])); + Din_0_ \Din[0]_I ( .PADDI(Din_c_0), .Din0(Din[0])); + nCCAS nCCAS_I( .PADDI(nCCAS_c), .nCCAS(nCCAS)); + nCRAS nCRAS_I( .PADDI(nCRAS_c), .nCRAS(nCRAS)); + nFWE nFWE_I( .PADDI(nFWE_c), .nFWE(nFWE)); + RCLK RCLK_I( .PADDI(RCLK_c), .RCLK(RCLK)); + UFMSDO UFMSDO_I( .PADDI(UFMSDO_c), .UFMSDO(UFMSDO)); + VHI VHI_INST( .Z(VCCI)); + PUR PUR_INST( .PUR(VCCI)); + GSR GSR_INST( .GSR(VCCI)); +endmodule + +module SLICE_0 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre FS_610__i14( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i13( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_15( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module vcc ( output PWR1 ); + + VHI INST1( .Z(PWR1)); +endmodule + +module gnd ( output PWR0 ); + + VLO INST1( .Z(PWR0)); +endmodule + +module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'hfaaa; + defparam inst1.INIT1 = 16'hfaaa; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_1 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre FS_610__i12( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i11( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_13( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_2 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre FS_610__i8( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i7( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_9( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_3 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre FS_610__i6( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i5( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_7( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_4 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre FS_610__i2( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i1( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_3( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_5 ( input A1, DI1, M0, CLK, output Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, M0_dly; + + vmuxregsre FS_610__i0( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CASr3_384( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20001 FS_610_add_4_1( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'hF000; + defparam inst1.INIT1 = 16'h0555; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_6 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre FS_610__i10( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i9( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_11( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_7 ( input A0, DI0, CLK, FCI, output F0, Q0 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; + + vmuxregsre FS_610__i17( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + ccu20002 FS_610_add_4_19( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(GNDI), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), + .CO1()); + + specify + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module ccu20002 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'hfaaa; + defparam inst1.INIT1 = 16'h0000; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_8 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre FS_610__i4( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i3( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_5( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_9 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre FS_610__i16( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i15( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_17( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_10 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut4 i3_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40003 i1_4_lut_adj_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0004 ADSubmitted_407( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut4 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40003 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0004 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module inverter ( input I, output Z ); + + INV INST1( .A(I), .Z(Z)); +endmodule + +module SLICE_15 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output + F0, Q0, F1 ); + wire VCCI, CLK_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40005 i13_2_lut_rep_16_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40006 i1110_2_lut_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0007 C1Submitted_406( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40005 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40006 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hE0F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0007 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3JY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module SLICE_16 ( input A0, DI0, M1, CLK, output F0, Q0, Q1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; + + lut40008 i2045( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CASr2_383( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre CASr_382( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40008 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_19 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40009 i26_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40010 i2_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdEnable_405( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40009 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC0CA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40010 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_20 ( input DI0, CE, CLK, output F0, Q0 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; + + lut40011 \n2447\001/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CmdSubmitted_411( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40011 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_24 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; + + lut40012 i1_2_lut_3_lut_adj_15( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40013 Cmdn8MEGEN_I_93_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre Cmdn8MEGEN_410( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40012 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40013 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCC5C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_25 ( input C1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, M1_dly; + + lut40014 i2_3_lut_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40008 i2_1_lut_rep_24( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre CBR_390( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre FWEr_389( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + endspecify + +endmodule + +module lut40014 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_26 ( input DI0, CE, CLK, output F0, Q0 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40011 \n2447\000/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre InitReady_394( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_27 ( input DI0, CE, CLK, output F0, Q0 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40011 m1_lut( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre LEDEN_419( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_30 ( input C1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; + + lut40015 i2010_3_lut_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40008 i2044( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre RASr2_380( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre RASr_379( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40015 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFBFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_32 ( input C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40016 i2_3_lut_rep_32( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40017 i2_2_lut_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0007 RA10_400( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40016 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40017 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_33 ( input C1, B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40018 i1_2_lut_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40019 RA11_I_54_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0004 RA11_385( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40018 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40019 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC6C6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_35 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40020 i1_2_lut_4_lut_adj_25( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40021 i29_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre RCKEEN_401( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40020 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h20FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40021 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_36 ( input D0, C0, B0, A0, DI0, M1, CLK, output F0, Q0, Q1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, M1_dly; + + lut40022 i1404_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre PHI2r2_377( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre RCKE_395( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40022 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCFC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_37 ( input DI0, CE, CLK, output F0, Q0 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40011 \n2447\002/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre Ready_404( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_44 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, CLK, output + F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40023 i1970_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40021 i1603_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 UFMCLK_416( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40023 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3A0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_45 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut4 i4_4_lut_adj_17( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40024 i1589_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0004 UFMSDI_417( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40024 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_50 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40025 i1962_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40026 i2_3_lut_4_lut_adj_11( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre XOR8MEG_408( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40025 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40026 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40027 i2_3_lut_rep_18_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40028 n8MEGEN_I_14_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre n8MEGEN_418( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40027 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40028 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBF04) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40029 nRCAS_I_43_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40030 nRCAS_I_0_452_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0031 nRCAS_398( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40029 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3AFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40030 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFE0E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0031 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module SLICE_61 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40032 nRCS_I_31_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40021 nRCS_I_0_448_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0031 nRCS_396( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40032 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1F10) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40033 i3_4_lut_adj_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40029 nRCS_N_137_I_0_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0031 nRRAS_397( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40033 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_64 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40034 i1477_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40035 nRWE_I_0_455_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0031 nRWE_399( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40034 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40035 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCFC5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_65 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40034 i786_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40036 i1432_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre nRowColSel_402( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40036 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3032) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_66 ( input B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40037 i1_2_lut_adj_23( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40034 i1439_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0004 S_FSM_i4( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40037 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_67 ( input B0, A0, DI0, LSR, CLK, output F0, Q0 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40038 i1_2_lut_adj_10( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 S_FSM_i3( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40038 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_68 ( input B1, A1, B0, A0, M0, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, LSR_dly; + + lut40034 i4_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40039 i1989_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0004 S_FSM_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40039 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_69 ( input B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; + + lut40034 i1491_2_lut_rep_30( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40008 RASr2_I_0_1_lut_rep_25( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), + .Z(F0)); + vmuxregsre PHI2r3_378( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre S_FSM_i1( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_70 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40040 i1_2_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40041 i1448_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0031 nUFMCS_415( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40040 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40041 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3FBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module i30_SLICE_71 ( input C1, B1, A1, D0, C0, B0, A0, M0, output OFX0 ); + wire GNDI, \i30/SLICE_71/i30/SLICE_71_K1_H1 , \i30/SLICE_71/i30/GATE_H0 ; + + lut40042 \i30/SLICE_71_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(\i30/SLICE_71/i30/SLICE_71_K1_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40043 \i30/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\i30/SLICE_71/i30/GATE_H0 )); + selmux2 \i30/SLICE_71_K0K1MUX ( .D0(\i30/SLICE_71/i30/GATE_H0 ), + .D1(\i30/SLICE_71/i30/SLICE_71_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40042 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1F1F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40043 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5540) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module selmux2 ( input D0, D1, SD, output Z ); + + MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); +endmodule + +module SLICE_72 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); + wire GNDI; + + lut40044 i1_4_lut_4_lut_adj_12( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40039 i2_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40044 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40003 i2_3_lut_4_lut_adj_14( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40010 i4_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_74 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40033 i12_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40045 i1_2_lut_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0004 RowA_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 RowA_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40045 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_75 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40027 i3_4_lut_adj_18( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40038 i1_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre IS_FSM__i9( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i8( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_76 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40012 i1_2_lut_rep_19_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40026 i1_2_lut_rep_15_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0007 RowA_i9( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 RowA_i8( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_77 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40046 i3_4_lut_adj_22( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40046 i3_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40046 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_78 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40047 nRCS_N_146_bdd_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40048 i1423_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre IS_FSM__i13( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i12( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40047 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF0DD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40048 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_79 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40016 i11_3_lut_rep_20( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40049 MAin_c_0_bdd_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre IS_FSM__i11( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i10( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40049 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_80 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40034 i3_2_lut_rep_26( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40050 i2005_3_lut_rep_17_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40050 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_81 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40034 i1_2_lut_rep_29( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40051 i1427_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre IS_FSM__i15( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i14( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40051 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFCDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_82 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40052 i6_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40039 i1_2_lut_adj_3( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0007 RowA_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 RowA_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40052 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_83 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40053 i2_4_lut_adj_21( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40054 i2_3_lut_4_lut_adj_6( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40053 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40054 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_84 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40055 i2_3_lut_rep_28( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40024 i1573_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre IS_FSM__i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40055 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40056 i1969_2_lut_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40040 i3_4_lut_adj_7( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40056 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_86 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40012 i5_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut4 i1_4_lut_adj_8( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre RASr3_381( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre PHI2r_376( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_87 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40040 i4_4_lut_adj_16( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40048 i1_2_lut_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 RBA__i2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 RBA__i1( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_88 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40057 i34_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40053 i1_4_lut_adj_13( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre WRD_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre WRD_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module lut40057 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC0C5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_89 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40058 i2_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40059 i1_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre WRD_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre WRD_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module lut40058 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8088) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40059 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_90 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40049 i1_2_lut_3_lut_4_lut_adj_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40055 i1_2_lut_rep_21_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre WRD_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre WRD_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module SLICE_91 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40060 i1_2_lut_rep_13_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40061 i1_2_lut_3_lut_4_lut_adj_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0004 RowA_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 RowA_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40060 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40061 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_92 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40062 i2008_2_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40005 i1_2_lut_rep_22_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre WRD_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre WRD_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module lut40062 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_93 ( input B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40063 i2001_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40021 MAin_9__I_0_427_i10_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre Bank_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre Bank_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40063 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_94 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40048 i771_2_lut_rep_23_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40064 i2_3_lut_4_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40064 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_95 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40065 i2_4_lut_adj_20( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40040 i6_4_lut_adj_9( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40065 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_96 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40034 i1_2_lut_rep_27( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40027 i2_3_lut_4_lut_adj_24( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_97 ( input C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40066 i13_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40034 i1956_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre IS_FSM__i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40066 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC5C5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_98 ( input B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40037 i1416_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40021 MAin_9__I_0_427_i9_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre IS_FSM__i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_99 ( input D1, C1, B1, A1, C0, B0, A0, M0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; + + lut40052 i8_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40021 MAin_9__I_0_427_i8_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CmdUFMSDI_414( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_100 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40052 i1979_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40021 MAin_9__I_0_427_i7_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CmdUFMCS_412( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre CmdUFMCLK_413( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_101 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40021 MAin_9__I_0_427_i1_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40021 MAin_9__I_0_427_i6_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre Bank_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre Bank_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_102 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40021 MAin_9__I_0_427_i2_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40021 MAin_9__I_0_427_i5_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre Bank_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre Bank_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_103 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40021 MAin_9__I_0_427_i3_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40021 MAin_9__I_0_427_i4_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre Bank_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre Bank_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_104 ( input B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40034 i1417_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40067 i1_2_lut_rep_14_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0004 RowA_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 RowA_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40067 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_105 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40039 i1_2_lut_adj_19( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40052 i5_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_106 ( input B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40039 i1_2_lut_rep_33( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40034 i1930_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre IS_FSM__i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 ); + + xo2iobuf Dout_pad_7__713( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), + .PADI(RD7)); + + specify + (PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD7) = (0:0:0,0:0:0); + (RD7 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD7, 0:0:0); + $width (negedge RD7, 0:0:0); + endspecify + +endmodule + +module xo2iobuf ( input I, T, output Z, PAD, input PADI ); + + IBPD INST1( .I(PADI), .O(Z)); + OBZPD INST2( .I(I), .T(T), .O(PAD)); +endmodule + +module RD_6_ ( output PADDI, input PADDT, PADDO, inout RD6 ); + + xo2iobuf Dout_pad_6__714( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD6), + .PADI(RD6)); + + specify + (PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD6) = (0:0:0,0:0:0); + (RD6 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD6, 0:0:0); + $width (negedge RD6, 0:0:0); + endspecify + +endmodule + +module RD_5_ ( output PADDI, input PADDT, PADDO, inout RD5 ); + + xo2iobuf Dout_pad_5__715( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD5), + .PADI(RD5)); + + specify + (PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD5) = (0:0:0,0:0:0); + (RD5 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD5, 0:0:0); + $width (negedge RD5, 0:0:0); + endspecify + +endmodule + +module RD_4_ ( output PADDI, input PADDT, PADDO, inout RD4 ); + + xo2iobuf Dout_pad_4__716( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD4), + .PADI(RD4)); + + specify + (PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD4) = (0:0:0,0:0:0); + (RD4 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD4, 0:0:0); + $width (negedge RD4, 0:0:0); + endspecify + +endmodule + +module RD_3_ ( output PADDI, input PADDT, PADDO, inout RD3 ); + + xo2iobuf Dout_pad_3__717( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD3), + .PADI(RD3)); + + specify + (PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD3) = (0:0:0,0:0:0); + (RD3 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD3, 0:0:0); + $width (negedge RD3, 0:0:0); + endspecify + +endmodule + +module RD_2_ ( output PADDI, input PADDT, PADDO, inout RD2 ); + + xo2iobuf Dout_pad_2__718( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD2), + .PADI(RD2)); + + specify + (PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD2) = (0:0:0,0:0:0); + (RD2 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD2, 0:0:0); + $width (negedge RD2, 0:0:0); + endspecify + +endmodule + +module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 ); + + xo2iobuf Dout_pad_1__719( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD1), + .PADI(RD1)); + + specify + (PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD1) = (0:0:0,0:0:0); + (RD1 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD1, 0:0:0); + $width (negedge RD1, 0:0:0); + endspecify + +endmodule + +module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 ); + + xo2iobuf Dout_pad_0__720( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), + .PADI(RD0)); + + specify + (PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD0) = (0:0:0,0:0:0); + (RD0 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD0, 0:0:0); + $width (negedge RD0, 0:0:0); + endspecify + +endmodule + +module Dout_7_ ( input PADDO, output Dout7 ); + wire GNDI; + + xo2iobuf0068 Dout_pad_7( .I(PADDO), .T(GNDI), .PAD(Dout7)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module xo2iobuf0068 ( input I, T, output PAD ); + + OBZPD INST5( .I(I), .T(T), .O(PAD)); +endmodule + +module Dout_6_ ( input PADDO, output Dout6 ); + wire GNDI; + + xo2iobuf0068 Dout_pad_6( .I(PADDO), .T(GNDI), .PAD(Dout6)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_5_ ( input PADDO, output Dout5 ); + wire GNDI; + + xo2iobuf0068 Dout_pad_5( .I(PADDO), .T(GNDI), .PAD(Dout5)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_4_ ( input PADDO, output Dout4 ); + wire GNDI; + + xo2iobuf0068 Dout_pad_4( .I(PADDO), .T(GNDI), .PAD(Dout4)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_3_ ( input PADDO, output Dout3 ); + wire GNDI; + + xo2iobuf0068 Dout_pad_3( .I(PADDO), .T(GNDI), .PAD(Dout3)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_2_ ( input PADDO, output Dout2 ); + wire GNDI; + + xo2iobuf0068 Dout_pad_2( .I(PADDO), .T(GNDI), .PAD(Dout2)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_1_ ( input PADDO, output Dout1 ); + wire GNDI; + + xo2iobuf0068 Dout_pad_1( .I(PADDO), .T(GNDI), .PAD(Dout1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_0_ ( input PADDO, output Dout0 ); + wire GNDI; + + xo2iobuf0068 Dout_pad_0( .I(PADDO), .T(GNDI), .PAD(Dout0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module LED ( input PADDO, output LED ); + wire GNDI; + + xo2iobuf0068 LED_pad( .I(PADDO), .T(GNDI), .PAD(LED)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => LED) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RBA_1_ ( input PADDO, output RBA1 ); + wire GNDI; + + xo2iobuf0068 RBA_pad_1( .I(PADDO), .T(GNDI), .PAD(RBA1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RBA1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RBA_0_ ( input PADDO, output RBA0 ); + wire GNDI; + + xo2iobuf0068 RBA_pad_0( .I(PADDO), .T(GNDI), .PAD(RBA0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RBA0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_11_ ( input PADDO, output RA11 ); + wire GNDI; + + xo2iobuf0068 RA_pad_11( .I(PADDO), .T(GNDI), .PAD(RA11)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA11) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_10_ ( input PADDO, output RA10 ); + wire GNDI; + + xo2iobuf0068 RA_pad_10( .I(PADDO), .T(GNDI), .PAD(RA10)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA10) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_9_ ( input PADDO, output RA9 ); + wire GNDI; + + xo2iobuf0068 RA_pad_9( .I(PADDO), .T(GNDI), .PAD(RA9)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA9) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_8_ ( input PADDO, output RA8 ); + wire GNDI; + + xo2iobuf0068 RA_pad_8( .I(PADDO), .T(GNDI), .PAD(RA8)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA8) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_7_ ( input PADDO, output RA7 ); + wire GNDI; + + xo2iobuf0068 RA_pad_7( .I(PADDO), .T(GNDI), .PAD(RA7)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_6_ ( input PADDO, output RA6 ); + wire GNDI; + + xo2iobuf0068 RA_pad_6( .I(PADDO), .T(GNDI), .PAD(RA6)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_5_ ( input PADDO, output RA5 ); + wire GNDI; + + xo2iobuf0068 RA_pad_5( .I(PADDO), .T(GNDI), .PAD(RA5)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_4_ ( input PADDO, output RA4 ); + wire GNDI; + + xo2iobuf0068 RA_pad_4( .I(PADDO), .T(GNDI), .PAD(RA4)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_3_ ( input PADDO, output RA3 ); + wire GNDI; + + xo2iobuf0068 RA_pad_3( .I(PADDO), .T(GNDI), .PAD(RA3)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_2_ ( input PADDO, output RA2 ); + wire GNDI; + + xo2iobuf0068 RA_pad_2( .I(PADDO), .T(GNDI), .PAD(RA2)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_1_ ( input PADDO, output RA1 ); + wire GNDI; + + xo2iobuf0068 RA_pad_1( .I(PADDO), .T(GNDI), .PAD(RA1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_0_ ( input PADDO, output RA0 ); + wire GNDI; + + xo2iobuf0068 RA_pad_0( .I(PADDO), .T(GNDI), .PAD(RA0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRCS ( input PADDO, output nRCS ); + wire GNDI; + + xo2iobuf0068 nRCS_pad( .I(PADDO), .T(GNDI), .PAD(nRCS)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nRCS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RCKE ( input PADDO, output RCKE ); + wire GNDI; + + xo2iobuf0068 RCKE_pad( .I(PADDO), .T(GNDI), .PAD(RCKE)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RCKE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRWE ( input PADDO, output nRWE ); + wire GNDI; + + xo2iobuf0068 nRWE_pad( .I(PADDO), .T(GNDI), .PAD(nRWE)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nRWE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRRAS ( input PADDO, output nRRAS ); + wire GNDI; + + xo2iobuf0068 nRRAS_pad( .I(PADDO), .T(GNDI), .PAD(nRRAS)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nRRAS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRCAS ( input PADDO, output nRCAS ); + wire GNDI; + + xo2iobuf0068 nRCAS_pad( .I(PADDO), .T(GNDI), .PAD(nRCAS)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nRCAS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RDQMH ( input PADDO, output RDQMH ); + wire GNDI; + + xo2iobuf0068 RDQMH_pad( .I(PADDO), .T(GNDI), .PAD(RDQMH)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RDQMH) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RDQML ( input PADDO, output RDQML ); + wire GNDI; + + xo2iobuf0068 RDQML_pad( .I(PADDO), .T(GNDI), .PAD(RDQML)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RDQML) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nUFMCS ( input PADDO, output nUFMCS ); + wire GNDI; + + xo2iobuf0068 nUFMCS_pad( .I(PADDO), .T(GNDI), .PAD(nUFMCS)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nUFMCS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module UFMCLK ( input PADDO, output UFMCLK ); + wire GNDI; + + xo2iobuf0068 UFMCLK_pad( .I(PADDO), .T(GNDI), .PAD(UFMCLK)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => UFMCLK) = (0:0:0,0:0:0); + endspecify + +endmodule + +module UFMSDI ( input PADDO, output UFMSDI ); + wire GNDI; + + xo2iobuf0068 UFMSDI_pad( .I(PADDO), .T(GNDI), .PAD(UFMSDI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => UFMSDI) = (0:0:0,0:0:0); + endspecify + +endmodule + +module PHI2 ( output PADDI, input PHI2 ); + + xo2iobuf0069 PHI2_pad( .Z(PADDI), .PAD(PHI2)); + + specify + (PHI2 => PADDI) = (0:0:0,0:0:0); + $width (posedge PHI2, 0:0:0); + $width (negedge PHI2, 0:0:0); + endspecify + +endmodule + +module xo2iobuf0069 ( output Z, input PAD ); + + IBPD INST1( .I(PAD), .O(Z)); +endmodule + +module MAin_9_ ( output PADDI, input MAin9 ); + + xo2iobuf0069 MAin_pad_9( .Z(PADDI), .PAD(MAin9)); + + specify + (MAin9 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin9, 0:0:0); + $width (negedge MAin9, 0:0:0); + endspecify + +endmodule + +module MAin_8_ ( output PADDI, input MAin8 ); + + xo2iobuf0069 MAin_pad_8( .Z(PADDI), .PAD(MAin8)); + + specify + (MAin8 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin8, 0:0:0); + $width (negedge MAin8, 0:0:0); + endspecify + +endmodule + +module MAin_7_ ( output PADDI, input MAin7 ); + + xo2iobuf0069 MAin_pad_7( .Z(PADDI), .PAD(MAin7)); + + specify + (MAin7 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin7, 0:0:0); + $width (negedge MAin7, 0:0:0); + endspecify + +endmodule + +module MAin_6_ ( output PADDI, input MAin6 ); + + xo2iobuf0069 MAin_pad_6( .Z(PADDI), .PAD(MAin6)); + + specify + (MAin6 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin6, 0:0:0); + $width (negedge MAin6, 0:0:0); + endspecify + +endmodule + +module MAin_5_ ( output PADDI, input MAin5 ); + + xo2iobuf0069 MAin_pad_5( .Z(PADDI), .PAD(MAin5)); + + specify + (MAin5 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin5, 0:0:0); + $width (negedge MAin5, 0:0:0); + endspecify + +endmodule + +module MAin_4_ ( output PADDI, input MAin4 ); + + xo2iobuf0069 MAin_pad_4( .Z(PADDI), .PAD(MAin4)); + + specify + (MAin4 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin4, 0:0:0); + $width (negedge MAin4, 0:0:0); + endspecify + +endmodule + +module MAin_3_ ( output PADDI, input MAin3 ); + + xo2iobuf0069 MAin_pad_3( .Z(PADDI), .PAD(MAin3)); + + specify + (MAin3 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin3, 0:0:0); + $width (negedge MAin3, 0:0:0); + endspecify + +endmodule + +module MAin_2_ ( output PADDI, input MAin2 ); + + xo2iobuf0069 MAin_pad_2( .Z(PADDI), .PAD(MAin2)); + + specify + (MAin2 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin2, 0:0:0); + $width (negedge MAin2, 0:0:0); + endspecify + +endmodule + +module MAin_1_ ( output PADDI, input MAin1 ); + + xo2iobuf0069 MAin_pad_1( .Z(PADDI), .PAD(MAin1)); + + specify + (MAin1 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin1, 0:0:0); + $width (negedge MAin1, 0:0:0); + endspecify + +endmodule + +module MAin_0_ ( output PADDI, input MAin0 ); + + xo2iobuf0069 MAin_pad_0( .Z(PADDI), .PAD(MAin0)); + + specify + (MAin0 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin0, 0:0:0); + $width (negedge MAin0, 0:0:0); + endspecify + +endmodule + +module CROW_1_ ( output PADDI, input CROW1 ); + + xo2iobuf0069 CROW_pad_1( .Z(PADDI), .PAD(CROW1)); + + specify + (CROW1 => PADDI) = (0:0:0,0:0:0); + $width (posedge CROW1, 0:0:0); + $width (negedge CROW1, 0:0:0); + endspecify + +endmodule + +module CROW_0_ ( output PADDI, input CROW0 ); + + xo2iobuf0069 CROW_pad_0( .Z(PADDI), .PAD(CROW0)); + + specify + (CROW0 => PADDI) = (0:0:0,0:0:0); + $width (posedge CROW0, 0:0:0); + $width (negedge CROW0, 0:0:0); + endspecify + +endmodule + +module Din_7_ ( output PADDI, input Din7 ); + + xo2iobuf0069 Din_pad_7( .Z(PADDI), .PAD(Din7)); + + specify + (Din7 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din7, 0:0:0); + $width (negedge Din7, 0:0:0); + endspecify + +endmodule + +module Din_6_ ( output PADDI, input Din6 ); + + xo2iobuf0069 Din_pad_6( .Z(PADDI), .PAD(Din6)); + + specify + (Din6 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din6, 0:0:0); + $width (negedge Din6, 0:0:0); + endspecify + +endmodule + +module Din_5_ ( output PADDI, input Din5 ); + + xo2iobuf0069 Din_pad_5( .Z(PADDI), .PAD(Din5)); + + specify + (Din5 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din5, 0:0:0); + $width (negedge Din5, 0:0:0); + endspecify + +endmodule + +module Din_4_ ( output PADDI, input Din4 ); + + xo2iobuf0069 Din_pad_4( .Z(PADDI), .PAD(Din4)); + + specify + (Din4 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din4, 0:0:0); + $width (negedge Din4, 0:0:0); + endspecify + +endmodule + +module Din_3_ ( output PADDI, input Din3 ); + + xo2iobuf0069 Din_pad_3( .Z(PADDI), .PAD(Din3)); + + specify + (Din3 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din3, 0:0:0); + $width (negedge Din3, 0:0:0); + endspecify + +endmodule + +module Din_2_ ( output PADDI, input Din2 ); + + xo2iobuf0069 Din_pad_2( .Z(PADDI), .PAD(Din2)); + + specify + (Din2 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din2, 0:0:0); + $width (negedge Din2, 0:0:0); + endspecify + +endmodule + +module Din_1_ ( output PADDI, input Din1 ); + + xo2iobuf0069 Din_pad_1( .Z(PADDI), .PAD(Din1)); + + specify + (Din1 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din1, 0:0:0); + $width (negedge Din1, 0:0:0); + endspecify + +endmodule + +module Din_0_ ( output PADDI, input Din0 ); + + xo2iobuf0069 Din_pad_0( .Z(PADDI), .PAD(Din0)); + + specify + (Din0 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din0, 0:0:0); + $width (negedge Din0, 0:0:0); + endspecify + +endmodule + +module nCCAS ( output PADDI, input nCCAS ); + + xo2iobuf0069 nCCAS_pad( .Z(PADDI), .PAD(nCCAS)); + + specify + (nCCAS => PADDI) = (0:0:0,0:0:0); + $width (posedge nCCAS, 0:0:0); + $width (negedge nCCAS, 0:0:0); + endspecify + +endmodule + +module nCRAS ( output PADDI, input nCRAS ); + + xo2iobuf0069 nCRAS_pad( .Z(PADDI), .PAD(nCRAS)); + + specify + (nCRAS => PADDI) = (0:0:0,0:0:0); + $width (posedge nCRAS, 0:0:0); + $width (negedge nCRAS, 0:0:0); + endspecify + +endmodule + +module nFWE ( output PADDI, input nFWE ); + + xo2iobuf0069 nFWE_pad( .Z(PADDI), .PAD(nFWE)); + + specify + (nFWE => PADDI) = (0:0:0,0:0:0); + $width (posedge nFWE, 0:0:0); + $width (negedge nFWE, 0:0:0); + endspecify + +endmodule + +module RCLK ( output PADDI, input RCLK ); + + xo2iobuf0069 RCLK_pad( .Z(PADDI), .PAD(RCLK)); + + specify + (RCLK => PADDI) = (0:0:0,0:0:0); + $width (posedge RCLK, 0:0:0); + $width (negedge RCLK, 0:0:0); + endspecify + +endmodule + +module UFMSDO ( output PADDI, input UFMSDO ); + + xo2iobuf0069 UFMSDO_pad( .Z(PADDI), .PAD(UFMSDO)); + + specify + (UFMSDO => PADDI) = (0:0:0,0:0:0); + $width (posedge UFMSDO, 0:0:0); + $width (negedge UFMSDO, 0:0:0); + endspecify + +endmodule diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html new file mode 100644 index 0000000..06c3af4 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html @@ -0,0 +1,368 @@ + +Project Summary + + +

    
+            Lattice Mapping Report File for Design Module 'RAM2GS'
+
+
+
+Design Information
+
+Command line:   map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
+     RAM2GS_LCMXO2_640HC_impl1.ngd -o RAM2GS_LCMXO2_640HC_impl1_map.ncd -pr
+     RAM2GS_LCMXO2_640HC_impl1.prf -mp RAM2GS_LCMXO2_640HC_impl1.mrp -lpf D:/One
+     Drive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_i
+     mpl1.lpf -lpf D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_
+     LCMXO2_640HC.lpf -c 0 -gui -msgset
+     D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml 
+Target Vendor:  LATTICE
+Target Device:  LCMXO2-640HCTQFP100
+Target Performance:   4
+Mapper:  xo2c00,  version:  Diamond (64-bit) 3.12.1.454
+Mapped on:  08/15/23  05:03:24
+
+
+Design Summary
+   Number of registers:    102 out of   877 (12%)
+      PFU registers:          102 out of   640 (16%)
+      PIO registers:            0 out of   237 (0%)
+   Number of SLICEs:        75 out of   320 (23%)
+      SLICEs as Logic/ROM:     75 out of   320 (23%)
+      SLICEs as RAM:            0 out of   240 (0%)
+      SLICEs as Carry:         10 out of   320 (3%)
+   Number of LUT4s:        143 out of   640 (22%)
+      Number used as logic LUTs:        123
+      Number used as distributed RAM:     0
+      Number used as ripple logic:       20
+      Number used as shift registers:     0
+   Number of PIO sites used: 67 + 4(JTAG) out of 79 (90%)
+   Number of block RAMs:  0 out of 2 (0%)
+   Number of GSRs:        0 out of 1 (0%)
+   EFB used :        No
+   JTAG used :       No
+   Readback used :   No
+   Oscillator used : No
+   Startup used :    No
+   POR :             On
+   Bandgap :         On
+   Number of Power Controller:  0 out of 1 (0%)
+   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
+   Number of DCCA:  0 out of 8 (0%)
+   Number of DCMA:  0 out of 2 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
+     distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and
+     ripple logic.
+   Number of clocks:  4
+     Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK )
+     Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
+     Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
+     Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
+   Number of Clock Enables:  14
+     Net RCLK_c_enable_6: 4 loads, 4 LSLICEs
+     Net RCLK_c_enable_5: 2 loads, 2 LSLICEs
+
+     Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs
+     Net PHI2_N_120_enable_2: 1 loads, 1 LSLICEs
+     Net PHI2_N_120_enable_6: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_27: 8 loads, 8 LSLICEs
+     Net RCLK_c_enable_10: 3 loads, 3 LSLICEs
+     Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_16: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_28: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_15: 1 loads, 1 LSLICEs
+     Net PHI2_N_120_enable_3: 1 loads, 1 LSLICEs
+     Net Ready_N_292: 1 loads, 1 LSLICEs
+     Net PHI2_N_120_enable_8: 2 loads, 2 LSLICEs
+   Number of LSRs:  7
+     Net RASr2: 1 loads, 1 LSLICEs
+     Net nRowColSel_N_35: 1 loads, 1 LSLICEs
+     Net Ready: 7 loads, 7 LSLICEs
+     Net nRWE_N_177: 1 loads, 1 LSLICEs
+     Net C1Submitted_N_237: 2 loads, 2 LSLICEs
+     Net n2366: 2 loads, 2 LSLICEs
+     Net nRowColSel_N_34: 1 loads, 1 LSLICEs
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+     Net Ready: 18 loads
+     Net InitReady: 15 loads
+     Net RASr2: 15 loads
+     Net nRowColSel_N_35: 13 loads
+     Net nRowColSel: 12 loads
+     Net Din_c_4: 10 loads
+     Net MAin_c_1: 10 loads
+     Net Din_c_5: 9 loads
+     Net MAin_c_0: 9 loads
+     Net Din_c_0: 8 loads
+
+
+
+
+   Number of warnings:  0
+   Number of errors:    0
+     
+
+
+
+
+Design Errors/Warnings
+
+   No errors or warnings present.
+
+
+
+IO (PIO) Attributes
+
++---------------------+-----------+-----------+------------+
+| IO Name             | Direction | Levelmode | IO         |
+|                     |           |  IO_TYPE  | Register   |
++---------------------+-----------+-----------+------------+
+| RD[7]               | BIDIR     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RD[6]               | BIDIR     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+
+| RD[5]               | BIDIR     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RD[4]               | BIDIR     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RD[3]               | BIDIR     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RD[2]               | BIDIR     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RD[1]               | BIDIR     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RD[0]               | BIDIR     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Dout[7]             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Dout[6]             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Dout[5]             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Dout[4]             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Dout[3]             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Dout[2]             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Dout[1]             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Dout[0]             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| LED                 | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RBA[1]              | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RBA[0]              | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[11]              | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[10]              | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[9]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[8]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[7]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[6]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[5]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[4]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[3]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[2]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[1]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+
+| RA[0]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| nRCS                | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RCKE                | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| nRWE                | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| nRRAS               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| nRCAS               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RDQMH               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RDQML               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| nUFMCS              | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| UFMCLK              | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| UFMSDI              | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| PHI2                | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[9]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[8]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[7]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[6]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[5]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[4]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[3]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[2]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[1]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[0]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| CROW[1]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| CROW[0]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Din[7]              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Din[6]              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Din[5]              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Din[4]              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+
+| Din[3]              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Din[2]              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Din[1]              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Din[0]              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| nCCAS               | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| nCRAS               | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| nFWE                | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RCLK                | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| UFMSDO              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+
+
+
+Removed logic
+
+Block i2 undriven or does not drive anything - clipped.
+Block GSR_INST undriven or does not drive anything - clipped.
+Signal PHI2_N_120 was merged into signal PHI2_c
+Signal n1407 was merged into signal nRowColSel_N_34
+Signal n2380 was merged into signal Ready
+Signal n1408 was merged into signal nRowColSel_N_35
+Signal nRWE_N_176 was merged into signal nRWE_N_177
+Signal GND_net undriven or does not drive anything - clipped.
+Signal VCC_net undriven or does not drive anything - clipped.
+Signal FS_610_add_4_19/S1 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_19/CO undriven or does not drive anything - clipped.
+Signal FS_610_add_4_1/S0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_1/CI undriven or does not drive anything - clipped.
+Block i2046 was optimized away.
+Block i1118_1_lut was optimized away.
+Block i637_1_lut_rep_31 was optimized away.
+Block i1119_1_lut was optimized away.
+Block nRWE_I_50_1_lut was optimized away.
+Block i1 was optimized away.
+
+     
+
+
+
+Run Time and Memory Usage
+-------------------------
+
+   Total CPU Time: 0 secs  
+   Total REAL Time: 0 secs  
+   Peak Memory Usage: 35 MB
+        
+
+
+
+
+
+
+
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+     Copyright (c) 1995 AT&T Corp.   All rights reserved.
+     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+     Copyright (c) 2001 Agere Systems   All rights reserved.
+     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
+     reserved.
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_pad.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_pad.html new file mode 100644 index 0000000..635ff81 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_pad.html @@ -0,0 +1,346 @@ + +PAD Specification File + + +
    PAD Specification File
+***************************
+
+PART TYPE:        LCMXO2-640HC
+Performance Grade:      4
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.39
+
+Tue Aug 15 05:03:32 2023
+
+Pinout by Port Name:
++-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+
+| Port Name | Pin/Bank | Buffer Type   | Site  | PG Enable | BC Enable | Properties                                               |
++-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+
+| CROW[0]   | 10/3     | LVCMOS25_IN   | PL3D  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| CROW[1]   | 16/3     | LVCMOS25_IN   | PL6A  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Din[0]    | 3/3      | LVCMOS25_IN   | PL2C  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Din[1]    | 96/0     | LVCMOS25_IN   | PT6D  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Din[2]    | 88/0     | LVCMOS25_IN   | PT9A  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Din[3]    | 97/0     | LVCMOS25_IN   | PT6C  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Din[4]    | 99/0     | LVCMOS25_IN   | PT6A  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Din[5]    | 98/0     | LVCMOS25_IN   | PT6B  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Din[6]    | 2/3      | LVCMOS25_IN   | PL2B  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Din[7]    | 1/3      | LVCMOS25_IN   | PL2A  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Dout[0]   | 76/0     | LVCMOS25_OUT  | PT11D |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| Dout[1]   | 86/0     | LVCMOS25_OUT  | PT9C  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| Dout[2]   | 87/0     | LVCMOS25_OUT  | PT9B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| Dout[3]   | 85/0     | LVCMOS25_OUT  | PT9D  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| Dout[4]   | 83/0     | LVCMOS25_OUT  | PT10B |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| Dout[5]   | 84/0     | LVCMOS25_OUT  | PT10A |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| Dout[6]   | 78/0     | LVCMOS25_OUT  | PT11A |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| Dout[7]   | 82/0     | LVCMOS25_OUT  | PT10C |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| LED       | 34/2     | LVCMOS25_OUT  | PB6C  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| MAin[0]   | 14/3     | LVCMOS25_IN   | PL5C  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[1]   | 12/3     | LVCMOS25_IN   | PL5A  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[2]   | 13/3     | LVCMOS25_IN   | PL5B  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[3]   | 21/3     | LVCMOS25_IN   | PL7B  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[4]   | 20/3     | LVCMOS25_IN   | PL7A  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[5]   | 19/3     | LVCMOS25_IN   | PL6D  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[6]   | 24/3     | LVCMOS25_IN   | PL7C  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[7]   | 18/3     | LVCMOS25_IN   | PL6C  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[8]   | 25/3     | LVCMOS25_IN   | PL7D  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[9]   | 32/2     | LVCMOS25_IN   | PB6B  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| PHI2      | 8/3      | LVCMOS25_IN   | PL3B  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| RA[0]     | 66/1     | LVCMOS25_OUT  | PR3D  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[10]    | 64/1     | LVCMOS25_OUT  | PR5B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[11]    | 59/1     | LVCMOS25_OUT  | PR6B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[1]     | 67/1     | LVCMOS25_OUT  | PR3C  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[2]     | 69/1     | LVCMOS25_OUT  | PR3A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[3]     | 71/1     | LVCMOS25_OUT  | PR2C  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[4]     | 74/1     | LVCMOS25_OUT  | PR2B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[5]     | 70/1     | LVCMOS25_OUT  | PR2D  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[6]     | 68/1     | LVCMOS25_OUT  | PR3B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[7]     | 75/1     | LVCMOS25_OUT  | PR2A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[8]     | 65/1     | LVCMOS25_OUT  | PR5A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[9]     | 63/1     | LVCMOS25_OUT  | PR5C  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RBA[0]    | 58/1     | LVCMOS25_OUT  | PR6C  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RBA[1]    | 60/1     | LVCMOS25_OUT  | PR6A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RCKE      | 53/1     | LVCMOS25_OUT  | PR7B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RCLK      | 62/1     | LVCMOS25_IN   | PR5D  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| RDQMH     | 51/1     | LVCMOS25_OUT  | PR7D  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RDQML     | 48/2     | LVCMOS25_OUT  | PB14C |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RD[0]     | 36/2     | LVCMOS25_BIDI | PB10A |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[1]     | 37/2     | LVCMOS25_BIDI | PB10B |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[2]     | 38/2     | LVCMOS25_BIDI | PB10C |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[3]     | 39/2     | LVCMOS25_BIDI | PB10D |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[4]     | 40/2     | LVCMOS25_BIDI | PB12A |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[5]     | 41/2     | LVCMOS25_BIDI | PB12B |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[6]     | 42/2     | LVCMOS25_BIDI | PB12C |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[7]     | 43/2     | LVCMOS25_BIDI | PB12D |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| UFMCLK    | 29/2     | LVCMOS25_OUT  | PB4C  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| UFMSDI    | 30/2     | LVCMOS25_OUT  | PB4D  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| UFMSDO    | 27/2     | LVCMOS25_IN   | PB4A  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| nCCAS     | 9/3      | LVCMOS25_IN   | PL3C  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| nCRAS     | 17/3     | LVCMOS25_IN   | PL6B  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| nFWE      | 28/2     | LVCMOS25_IN   | PB4B  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| nRCAS     | 52/1     | LVCMOS25_OUT  | PR7C  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| nRCS      | 57/1     | LVCMOS25_OUT  | PR6D  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| nRRAS     | 54/1     | LVCMOS25_OUT  | PR7A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| nRWE      | 49/2     | LVCMOS25_OUT  | PB14D |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| nUFMCS    | 77/0     | LVCMOS25_OUT  | PT11C |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
++-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 2.5V  |
+| 1    | 2.5V  |
+| 2    | 2.5V  |
+| 3    | 2.5V  |
++------+-------+
+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+| Pin/Bank | Pin Info              | Preference | Buffer Type   | Site  | Dual Function | PG Enable | BC Enable |
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+| 1/3      | Din[7]                | LOCATED    | LVCMOS25_IN   | PL2A  |               |           |           |
+| 2/3      | Din[6]                | LOCATED    | LVCMOS25_IN   | PL2B  |               |           |           |
+| 3/3      | Din[0]                | LOCATED    | LVCMOS25_IN   | PL2C  | PCLKT3_2      |           |           |
+| 4/3      |     unused, PULL:DOWN |            |               | PL2D  | PCLKC3_2      |           |           |
+| 7/3      |     unused, PULL:DOWN |            |               | PL3A  |               |           |           |
+| 8/3      | PHI2                  | LOCATED    | LVCMOS25_IN   | PL3B  |               |           |           |
+| 9/3      | nCCAS                 | LOCATED    | LVCMOS25_IN   | PL3C  |               |           |           |
+| 10/3     | CROW[0]               | LOCATED    | LVCMOS25_IN   | PL3D  |               |           |           |
+| 12/3     | MAin[1]               | LOCATED    | LVCMOS25_IN   | PL5A  | PCLKT3_1      |           |           |
+| 13/3     | MAin[2]               | LOCATED    | LVCMOS25_IN   | PL5B  | PCLKC3_1      |           |           |
+| 14/3     | MAin[0]               | LOCATED    | LVCMOS25_IN   | PL5C  |               |           |           |
+| 15/3     |     unused, PULL:DOWN |            |               | PL5D  |               |           |           |
+| 16/3     | CROW[1]               | LOCATED    | LVCMOS25_IN   | PL6A  |               |           |           |
+| 17/3     | nCRAS                 | LOCATED    | LVCMOS25_IN   | PL6B  |               |           |           |
+| 18/3     | MAin[7]               | LOCATED    | LVCMOS25_IN   | PL6C  |               |           |           |
+| 19/3     | MAin[5]               | LOCATED    | LVCMOS25_IN   | PL6D  |               |           |           |
+| 20/3     | MAin[4]               | LOCATED    | LVCMOS25_IN   | PL7A  | PCLKT3_0      |           |           |
+| 21/3     | MAin[3]               | LOCATED    | LVCMOS25_IN   | PL7B  | PCLKC3_0      |           |           |
+| 24/3     | MAin[6]               | LOCATED    | LVCMOS25_IN   | PL7C  |               |           |           |
+| 25/3     | MAin[8]               | LOCATED    | LVCMOS25_IN   | PL7D  |               |           |           |
+| 27/2     | UFMSDO                | LOCATED    | LVCMOS25_IN   | PB4A  | CSSPIN        |           |           |
+| 28/2     | nFWE                  | LOCATED    | LVCMOS25_IN   | PB4B  |               |           |           |
+| 29/2     | UFMCLK                | LOCATED    | LVCMOS25_OUT  | PB4C  |               |           |           |
+| 30/2     | UFMSDI                | LOCATED    | LVCMOS25_OUT  | PB4D  |               |           |           |
+| 31/2     |     unused, PULL:DOWN |            |               | PB6A  | MCLK/CCLK     |           |           |
+| 32/2     | MAin[9]               | LOCATED    | LVCMOS25_IN   | PB6B  | SO/SPISO      |           |           |
+| 34/2     | LED                   | LOCATED    | LVCMOS25_OUT  | PB6C  | PCLKT2_0      |           |           |
+| 35/2     |     unused, PULL:DOWN |            |               | PB6D  | PCLKC2_0      |           |           |
+| 36/2     | RD[0]                 | LOCATED    | LVCMOS25_BIDI | PB10A |               |           |           |
+| 37/2     | RD[1]                 | LOCATED    | LVCMOS25_BIDI | PB10B |               |           |           |
+| 38/2     | RD[2]                 | LOCATED    | LVCMOS25_BIDI | PB10C | PCLKT2_1      |           |           |
+| 39/2     | RD[3]                 | LOCATED    | LVCMOS25_BIDI | PB10D | PCLKC2_1      |           |           |
+| 40/2     | RD[4]                 | LOCATED    | LVCMOS25_BIDI | PB12A |               |           |           |
+| 41/2     | RD[5]                 | LOCATED    | LVCMOS25_BIDI | PB12B |               |           |           |
+| 42/2     | RD[6]                 | LOCATED    | LVCMOS25_BIDI | PB12C |               |           |           |
+| 43/2     | RD[7]                 | LOCATED    | LVCMOS25_BIDI | PB12D |               |           |           |
+| 45/2     |     unused, PULL:DOWN |            |               | PB14A |               |           |           |
+| 47/2     |     unused, PULL:DOWN |            |               | PB14B |               |           |           |
+| 48/2     | RDQML                 | LOCATED    | LVCMOS25_OUT  | PB14C | SN            |           |           |
+| 49/2     | nRWE                  | LOCATED    | LVCMOS25_OUT  | PB14D | SI/SISPI      |           |           |
+| 51/1     | RDQMH                 | LOCATED    | LVCMOS25_OUT  | PR7D  |               |           |           |
+| 52/1     | nRCAS                 | LOCATED    | LVCMOS25_OUT  | PR7C  |               |           |           |
+| 53/1     | RCKE                  | LOCATED    | LVCMOS25_OUT  | PR7B  |               |           |           |
+| 54/1     | nRRAS                 | LOCATED    | LVCMOS25_OUT  | PR7A  |               |           |           |
+| 57/1     | nRCS                  | LOCATED    | LVCMOS25_OUT  | PR6D  |               |           |           |
+| 58/1     | RBA[0]                | LOCATED    | LVCMOS25_OUT  | PR6C  |               |           |           |
+| 59/1     | RA[11]                | LOCATED    | LVCMOS25_OUT  | PR6B  |               |           |           |
+| 60/1     | RBA[1]                | LOCATED    | LVCMOS25_OUT  | PR6A  |               |           |           |
+| 62/1     | RCLK                  | LOCATED    | LVCMOS25_IN   | PR5D  | PCLKC1_0      |           |           |
+| 63/1     | RA[9]                 | LOCATED    | LVCMOS25_OUT  | PR5C  | PCLKT1_0      |           |           |
+| 64/1     | RA[10]                | LOCATED    | LVCMOS25_OUT  | PR5B  |               |           |           |
+| 65/1     | RA[8]                 | LOCATED    | LVCMOS25_OUT  | PR5A  |               |           |           |
+| 66/1     | RA[0]                 | LOCATED    | LVCMOS25_OUT  | PR3D  |               |           |           |
+| 67/1     | RA[1]                 | LOCATED    | LVCMOS25_OUT  | PR3C  |               |           |           |
+| 68/1     | RA[6]                 | LOCATED    | LVCMOS25_OUT  | PR3B  |               |           |           |
+| 69/1     | RA[2]                 | LOCATED    | LVCMOS25_OUT  | PR3A  |               |           |           |
+| 70/1     | RA[5]                 | LOCATED    | LVCMOS25_OUT  | PR2D  |               |           |           |
+| 71/1     | RA[3]                 | LOCATED    | LVCMOS25_OUT  | PR2C  |               |           |           |
+| 74/1     | RA[4]                 | LOCATED    | LVCMOS25_OUT  | PR2B  |               |           |           |
+| 75/1     | RA[7]                 | LOCATED    | LVCMOS25_OUT  | PR2A  |               |           |           |
+| 76/0     | Dout[0]               | LOCATED    | LVCMOS25_OUT  | PT11D | DONE          |           |           |
+| 77/0     | nUFMCS                |            | LVCMOS25_OUT  | PT11C | INITN         |           |           |
+| 78/0     | Dout[6]               | LOCATED    | LVCMOS25_OUT  | PT11A |               |           |           |
+| 81/0     |     unused, PULL:DOWN |            |               | PT10D | PROGRAMN      |           |           |
+| 82/0     | Dout[7]               | LOCATED    | LVCMOS25_OUT  | PT10C | JTAGENB       |           |           |
+| 83/0     | Dout[4]               | LOCATED    | LVCMOS25_OUT  | PT10B |               |           |           |
+| 84/0     | Dout[5]               | LOCATED    | LVCMOS25_OUT  | PT10A |               |           |           |
+| 85/0     | Dout[3]               | LOCATED    | LVCMOS25_OUT  | PT9D  | SDA/PCLKC0_0  |           |           |
+| 86/0     | Dout[1]               | LOCATED    | LVCMOS25_OUT  | PT9C  | SCL/PCLKT0_0  |           |           |
+| 87/0     | Dout[2]               | LOCATED    | LVCMOS25_OUT  | PT9B  | PCLKC0_1      |           |           |
+| 88/0     | Din[2]                | LOCATED    | LVCMOS25_IN   | PT9A  | PCLKT0_1      |           |           |
+| 90/0     | Reserved: sysCONFIG   |            |               | PT7D  | TMS           |           |           |
+| 91/0     | Reserved: sysCONFIG   |            |               | PT7C  | TCK           |           |           |
+| 94/0     | Reserved: sysCONFIG   |            |               | PT7B  | TDI           |           |           |
+| 95/0     | Reserved: sysCONFIG   |            |               | PT7A  | TDO           |           |           |
+| 96/0     | Din[1]                | LOCATED    | LVCMOS25_IN   | PT6D  |               |           |           |
+| 97/0     | Din[3]                | LOCATED    | LVCMOS25_IN   | PT6C  |               |           |           |
+| 98/0     | Din[5]                | LOCATED    | LVCMOS25_IN   | PT6B  |               |           |           |
+| 99/0     | Din[4]                | LOCATED    | LVCMOS25_IN   | PT6A  |               |           |           |
+| PT11B/0  |     unused, PULL:DOWN |            |               | PT11B |               |           |           |
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+
+sysCONFIG Pins:
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode  |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| PT7D     | TMS                | JTAG_PORT=ENABLE   | 90/0     |             | PULLUP            |
+| PT7C     | TCK/TEST_CLK       | JTAG_PORT=ENABLE   | 91/0     |             | NO pull up/down   |
+| PT7B     | TDI/MD7            | JTAG_PORT=ENABLE   | 94/0     |             | PULLUP            |
+| PT7A     | TDO                | JTAG_PORT=ENABLE   | 95/0     |             | PULLUP            |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+
+Dedicated sysCONFIG Pins:
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "CROW[0]"  SITE  "10";
+LOCATE  COMP  "CROW[1]"  SITE  "16";
+LOCATE  COMP  "Din[0]"  SITE  "3";
+LOCATE  COMP  "Din[1]"  SITE  "96";
+LOCATE  COMP  "Din[2]"  SITE  "88";
+LOCATE  COMP  "Din[3]"  SITE  "97";
+LOCATE  COMP  "Din[4]"  SITE  "99";
+LOCATE  COMP  "Din[5]"  SITE  "98";
+LOCATE  COMP  "Din[6]"  SITE  "2";
+LOCATE  COMP  "Din[7]"  SITE  "1";
+LOCATE  COMP  "Dout[0]"  SITE  "76";
+LOCATE  COMP  "Dout[1]"  SITE  "86";
+LOCATE  COMP  "Dout[2]"  SITE  "87";
+LOCATE  COMP  "Dout[3]"  SITE  "85";
+LOCATE  COMP  "Dout[4]"  SITE  "83";
+LOCATE  COMP  "Dout[5]"  SITE  "84";
+LOCATE  COMP  "Dout[6]"  SITE  "78";
+LOCATE  COMP  "Dout[7]"  SITE  "82";
+LOCATE  COMP  "LED"  SITE  "34";
+LOCATE  COMP  "MAin[0]"  SITE  "14";
+LOCATE  COMP  "MAin[1]"  SITE  "12";
+LOCATE  COMP  "MAin[2]"  SITE  "13";
+LOCATE  COMP  "MAin[3]"  SITE  "21";
+LOCATE  COMP  "MAin[4]"  SITE  "20";
+LOCATE  COMP  "MAin[5]"  SITE  "19";
+LOCATE  COMP  "MAin[6]"  SITE  "24";
+LOCATE  COMP  "MAin[7]"  SITE  "18";
+LOCATE  COMP  "MAin[8]"  SITE  "25";
+LOCATE  COMP  "MAin[9]"  SITE  "32";
+LOCATE  COMP  "PHI2"  SITE  "8";
+LOCATE  COMP  "RA[0]"  SITE  "66";
+LOCATE  COMP  "RA[10]"  SITE  "64";
+LOCATE  COMP  "RA[11]"  SITE  "59";
+LOCATE  COMP  "RA[1]"  SITE  "67";
+LOCATE  COMP  "RA[2]"  SITE  "69";
+LOCATE  COMP  "RA[3]"  SITE  "71";
+LOCATE  COMP  "RA[4]"  SITE  "74";
+LOCATE  COMP  "RA[5]"  SITE  "70";
+LOCATE  COMP  "RA[6]"  SITE  "68";
+LOCATE  COMP  "RA[7]"  SITE  "75";
+LOCATE  COMP  "RA[8]"  SITE  "65";
+LOCATE  COMP  "RA[9]"  SITE  "63";
+LOCATE  COMP  "RBA[0]"  SITE  "58";
+LOCATE  COMP  "RBA[1]"  SITE  "60";
+LOCATE  COMP  "RCKE"  SITE  "53";
+LOCATE  COMP  "RCLK"  SITE  "62";
+LOCATE  COMP  "RDQMH"  SITE  "51";
+LOCATE  COMP  "RDQML"  SITE  "48";
+LOCATE  COMP  "RD[0]"  SITE  "36";
+LOCATE  COMP  "RD[1]"  SITE  "37";
+LOCATE  COMP  "RD[2]"  SITE  "38";
+LOCATE  COMP  "RD[3]"  SITE  "39";
+LOCATE  COMP  "RD[4]"  SITE  "40";
+LOCATE  COMP  "RD[5]"  SITE  "41";
+LOCATE  COMP  "RD[6]"  SITE  "42";
+LOCATE  COMP  "RD[7]"  SITE  "43";
+LOCATE  COMP  "UFMCLK"  SITE  "29";
+LOCATE  COMP  "UFMSDI"  SITE  "30";
+LOCATE  COMP  "UFMSDO"  SITE  "27";
+LOCATE  COMP  "nCCAS"  SITE  "9";
+LOCATE  COMP  "nCRAS"  SITE  "17";
+LOCATE  COMP  "nFWE"  SITE  "28";
+LOCATE  COMP  "nRCAS"  SITE  "52";
+LOCATE  COMP  "nRCS"  SITE  "57";
+LOCATE  COMP  "nRRAS"  SITE  "54";
+LOCATE  COMP  "nRWE"  SITE  "49";
+LOCATE  COMP  "nUFMCS"  SITE  "77";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 15 05:03:34 2023
+
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_par.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_par.html new file mode 100644 index 0000000..f7c9130 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_par.html @@ -0,0 +1,327 @@ + +Place & Route Report + + +
    PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 15 05:03:28 2023
+
+C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_640HC_impl1.p2t
+RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir
+RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset
+D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
+
+
+Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
+
+Cost Table Summary
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            -5.122       452301       0.304        0            07           Completed
+* : Design saved.
+
+Total (real) run time for 1-seed: 7 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd"
+Tue Aug 15 05:03:28 2023
+
+
+Best Par Run
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
+Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file RAM2GS_LCMXO2_640HC_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+
+Device utilization summary:
+
+   PIO (prelim)   67+4(JTAG)/80      89% used
+                  67+4(JTAG)/79      90% bonded
+
+   SLICE             75/320          23% used
+
+
+
+Number of Signals: 285
+Number of Connections: 674
+WARNING - par: Placement timing preferences are hard to meet. However, placement will continue. Use static timing analysis to identify errors.
+
+Pin Constraint Summary:
+   66 out of 67 pins locked (98% locked).
+
+The following 2 signals are selected to use the primary clock routing resources:
+    RCLK_c (driver: RCLK, clk load #: 40)
+    PHI2_c (driver: PHI2, clk load #: 13)
+
+WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+
+The following 1 signal is selected to use the secondary clock routing resources:
+    nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0)
+
+WARNING - par: Signal "nCRAS_c" is selected to use Secondary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+No signal is selected as Global Set/Reset.
+.
+Starting Placer Phase 0.
+.............
+Finished Placer Phase 0.  REAL time: 0 secs 
+
+Starting Placer Phase 1.
+...............
+Placer score = 121531.
+Finished Placer Phase 1.  REAL time: 4 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  119079
+Finished Placer Phase 2.  REAL time: 4 secs 
+
+
+
+Clock Report
+
+Global Clock Resources:
+  CLK_PIN    : 0 out of 8 (0%)
+  General PIO: 3 out of 80 (3%)
+  DCM        : 0 out of 2 (0%)
+  DCC        : 0 out of 8 (0%)
+
+Global Clocks:
+  PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 40
+  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 13
+  SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 7, ce load = 0, sr load = 0
+
+  PRIMARY  : 2 out of 8 (25%)
+  SECONDARY: 1 out of 8 (12%)
+
+
+
+
+I/O Usage Summary (final):
+   67 + 4(JTAG) out of 80 (88.8%) PIO sites used.
+   67 + 4(JTAG) out of 79 (89.9%) bonded PIO sites used.
+   Number of PIO comps: 67; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+-----------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref |
++----------+----------------+------------+-----------+
+| 0        | 14 / 19 ( 73%) | 2.5V       | -         |
+| 1        | 20 / 20 (100%) | 2.5V       | -         |
+| 2        | 16 / 20 ( 80%) | 2.5V       | -         |
+| 3        | 17 / 20 ( 85%) | 2.5V       | -         |
++----------+----------------+------------+-----------+
+
+Total placer CPU time: 3 secs 
+
+Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
+
+0 connections routed; 674 unrouted.
+Starting router resource preassignment
+WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
+WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=nCCAS_c loads=6 clock_loads=4
+
+Completed router resource preassignment. Real time: 7 secs 
+
+Start NBR router at 05:03:35 08/15/23
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 05:03:35 08/15/23
+
+Start NBR section for initial routing at 05:03:35 08/15/23
+Level 1, iteration 1
+2(0.00%) conflicts; 536(79.53%) untouched conns; 481988 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.914ns/-481.988ns; real time: 7 secs 
+Level 2, iteration 1
+7(0.02%) conflicts; 473(70.18%) untouched conns; 424953 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.988ns/-424.953ns; real time: 7 secs 
+Level 3, iteration 1
+12(0.03%) conflicts; 254(37.69%) untouched conns; 455640 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -5.118ns/-455.640ns; real time: 7 secs 
+Level 4, iteration 1
+6(0.01%) conflicts; 0(0.00%) untouched conn; 465237 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -5.122ns/-465.237ns; real time: 7 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 05:03:35 08/15/23
+Level 4, iteration 1
+6(0.01%) conflicts; 0(0.00%) untouched conn; 461186 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.992ns/-461.186ns; real time: 7 secs 
+Level 4, iteration 2
+3(0.01%) conflicts; 0(0.00%) untouched conn; 460933 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.992ns/-460.933ns; real time: 7 secs 
+Level 4, iteration 3
+2(0.00%) conflicts; 0(0.00%) untouched conn; 461063 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.992ns/-461.063ns; real time: 7 secs 
+Level 4, iteration 4
+1(0.00%) conflict; 0(0.00%) untouched conn; 461063 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.992ns/-461.063ns; real time: 7 secs 
+Level 4, iteration 5
+0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -5.122ns/-468.515ns; real time: 7 secs 
+
+Start NBR section for performance tuning (iteration 1) at 05:03:35 08/15/23
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -5.122ns/-468.515ns; real time: 7 secs 
+
+Start NBR section for re-routing at 05:03:35 08/15/23
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -5.122ns/-468.515ns; real time: 7 secs 
+
+Start NBR section for post-routing at 05:03:35 08/15/23
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 260 (38.58%)
+  Estimated worst slack<setup> : -5.122ns
+  Timing score<setup> : 452301
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=nCCAS_c loads=6 clock_loads=4
+
+Total CPU time 7 secs 
+Total REAL time: 7 secs 
+Completely routed.
+End of route.  674 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 452301 
+
+Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack<setup/<ns>> = -5.122
+PAR_SUMMARY::Timing score<setup/<ns>> = 452.301
+PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.304
+PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 7 secs 
+Total REAL time to completion: 7 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html new file mode 100644 index 0000000..d0630a7 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html @@ -0,0 +1,83 @@ + +Project Summary + + +
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    RAM2GS_LCMXO2_640HC project summary
    Module Name:RAM2GS_LCMXO2_640HCSynthesis:Lattice LSE
    Implementation Name:impl1Strategy Name:Strategy1
    Last Process:JEDEC FileState:Passed
    Target Device:LCMXO2-640HC-4TG100CDevice Family:MachXO2
    Device Type:LCMXO2-640HCPackage Type:TQFP100
    Performance grade:4Operating conditions:COM
    Logic preference file:RAM2GS_LCMXO2_640HC.lpf
    Physical Preference file:impl1/RAM2GS_LCMXO2_640HC_impl1.prf
    Product Version:3.12.1.454Patch Version:
    Updated:2023/08/15 05:03:41
    Implementation Location:D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1
    Project File:D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html new file mode 100644 index 0000000..ea92308 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html @@ -0,0 +1,430 @@ + +Lattice Map TRACE Report + + +
    Map TRACE Report
+
+Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
+Tue Aug 15 05:03:25 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_640hc_impl1_map.ncd
+Preference file: ram2gs_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,4
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "RCLK_c" 299.401000 MHz (245 errors)
    • 
+                459 items scored, 245 timing errors detected.
+Warning: 139.762MHz is the maximum frequency for this preference.
+
+
  • FREQUENCY NET "PHI2_c" 99.079000 MHz (104 errors)
    • 
+                113 items scored, 104 timing errors detected.
+Warning:  50.592MHz is the maximum frequency for this preference.
+
+Report Type:     based on TRACE automatically generated preferences
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
+            459 items scored, 245 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 3.815ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i13  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_418  (to RCLK_c +)
+
+   Delay:               6.873ns  (28.2% logic, 71.8% route), 4 logic levels.
+
+ Constraint Details:
+
+      6.873ns physical path delay SLICE_0 to SLICE_57 exceeds
+      3.340ns delay constraint less
+      0.282ns CE_SET requirement (totaling 3.058ns) by 3.815ns
+
+ Physical Path Details:
+
+      Data path SLICE_0 to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452    SLICE_0.CLK to     SLICE_0.Q0 SLICE_0 (from RCLK_c)
+ROUTE         3   e 1.234     SLICE_0.Q0 to    SLICE_85.B0 FS_13
+CTOF_DEL    ---     0.495    SLICE_85.B0 to    SLICE_85.F0 SLICE_85
+ROUTE         5   e 1.234    SLICE_85.F0 to    SLICE_57.A1 n10
+CTOF_DEL    ---     0.495    SLICE_57.A1 to    SLICE_57.F1 SLICE_57
+ROUTE         2   e 1.234    SLICE_57.F1 to    SLICE_84.A0 n2367
+CTOF_DEL    ---     0.495    SLICE_84.A0 to    SLICE_84.F0 SLICE_84
+ROUTE         1   e 1.234    SLICE_84.F0 to    SLICE_57.CE RCLK_c_enable_15 (to RCLK_c)
+                  --------
+                    6.873   (28.2% logic, 71.8% route), 4 logic levels.
+
+Warning: 139.762MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
+            113 items scored, 104 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 4.837ns (weighted slack = -9.674ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               9.577ns  (30.6% logic, 69.4% route), 6 logic levels.
+
+ Constraint Details:
+
+      9.577ns physical path delay SLICE_101 to SLICE_19 exceeds
+      5.047ns delay constraint less
+      0.307ns CE_SET requirement (totaling 4.740ns) by 4.837ns
+
+ Physical Path Details:
+
+      Data path SLICE_101 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452  SLICE_101.CLK to   SLICE_101.Q1 SLICE_101 (from PHI2_c)
+ROUTE         1   e 1.234   SLICE_101.Q1 to   SLICE_100.C1 Bank_7
+CTOF_DEL    ---     0.495   SLICE_100.C1 to   SLICE_100.F1 SLICE_100
+ROUTE         1   e 1.234   SLICE_100.F1 to    SLICE_74.B1 n2277
+CTOF_DEL    ---     0.495    SLICE_74.B1 to    SLICE_74.F1 SLICE_74
+ROUTE         8   e 1.234    SLICE_74.F1 to    SLICE_91.B1 n26
+CTOF_DEL    ---     0.495    SLICE_91.B1 to    SLICE_91.F1 SLICE_91
+ROUTE         1   e 1.234    SLICE_91.F1 to    SLICE_88.D0 n2362
+CTOF_DEL    ---     0.495    SLICE_88.D0 to    SLICE_88.F0 SLICE_88
+ROUTE         3   e 0.480    SLICE_88.F0 to    SLICE_88.C1 C1Submitted_N_237
+CTOF_DEL    ---     0.495    SLICE_88.C1 to    SLICE_88.F1 SLICE_88
+ROUTE         1   e 1.234    SLICE_88.F1 to    SLICE_19.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    9.577   (30.6% logic, 69.4% route), 6 logic levels.
+
+Warning:  50.592MHz is the maximum frequency for this preference.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "RCLK_c" 299.401000 MHz ; |  299.401 MHz|  139.762 MHz|   4 *
+                                        |             |             |
+FREQUENCY NET "PHI2_c" 99.079000 MHz ;  |   99.079 MHz|   50.592 MHz|   6 *
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+2 preferences(marked by "*" above) not met.
+
+----------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+----------------------------------------------------------------------------
+n26                                     |       8|      78|     22.35%
+                                        |        |        |
+----------------------------------------------------------------------------
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
+   Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 349  Score: 848079
+Cumulative negative slack: 584487
+
+Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
+Tue Aug 15 05:03:25 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_640hc_impl1_map.ncd
+Preference file: ram2gs_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,M
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "RCLK_c" 299.401000 MHz (0 errors)
    •             459 items scored, 0 timing errors detected.
+
+
  • FREQUENCY NET "PHI2_c" 99.079000 MHz (0 errors)
    •             113 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
+            459 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.351ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i4  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i5  (to RCLK_c +)
+
+   Delay:               0.332ns  (40.1% logic, 59.9% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.332ns physical path delay SLICE_106 to SLICE_106 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
+
+ Physical Path Details:
+
+      Data path SLICE_106 to SLICE_106:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133  SLICE_106.CLK to   SLICE_106.Q0 SLICE_106 (from RCLK_c)
+ROUTE         1   e 0.199   SLICE_106.Q0 to   SLICE_106.M1 n736 (to RCLK_c)
+                  --------
+                    0.332   (40.1% logic, 59.9% route), 1 logic levels.
+
+
+================================================================================
+Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
+            113 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.447ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_406  (from PHI2_c -)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               0.434ns  (53.9% logic, 46.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.434ns physical path delay SLICE_15 to SLICE_15 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
+
+ Physical Path Details:
+
+      Data path SLICE_15 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_15.CLK to    SLICE_15.Q0 SLICE_15 (from PHI2_c)
+ROUTE         2   e 0.199    SLICE_15.Q0 to    SLICE_15.C0 C1Submitted
+CTOF_DEL    ---     0.101    SLICE_15.C0 to    SLICE_15.F0 SLICE_15
+ROUTE         1   e 0.001    SLICE_15.F0 to   SLICE_15.DI0 n1398 (to PHI2_c)
+                  --------
+                    0.434   (53.9% logic, 46.1% route), 2 logic levels.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "RCLK_c" 299.401000 MHz ; |     0.000 ns|     0.351 ns|   1  
+                                        |             |             |
+FREQUENCY NET "PHI2_c" 99.079000 MHz ;  |     0.000 ns|     0.447 ns|   2  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
+   Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 349 (setup), 0 (hold)
+Score: 848079 (setup), 0 (hold)
+Cumulative negative slack: 584487 (584487+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html new file mode 100644 index 0000000..7c66cde --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html @@ -0,0 +1,2245 @@ + +Lattice TRACE Report + + +
    Place & Route TRACE Report
+
+Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
+Tue Aug 15 05:03:36 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_640hc_impl1.ncd
+Preference file: ram2gs_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,4
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "RCLK_c" 299.401000 MHz (264 errors)
    • 
+                459 items scored, 264 timing errors detected.
+Warning: 160.205MHz is the maximum frequency for this preference.
+
+
  • FREQUENCY NET "PHI2_c" 99.079000 MHz (85 errors)
    • 
+                113 items scored, 85 timing errors detected.
+Warning:  65.729MHz is the maximum frequency for this preference.
+
+Report Type:     based on TRACE automatically generated preferences
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
+            459 items scored, 264 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 2.902ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i12  (from RCLK_c +)
+   Destination:    FF         Data in        UFMSDI_417  (to RCLK_c +)
+
+   Delay:               6.076ns  (40.0% logic, 60.0% route), 5 logic levels.
+
+ Constraint Details:
+
+      6.076ns physical path delay SLICE_1 to SLICE_45 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.902ns
+
+ Physical Path Details:
+
+      Data path SLICE_1 to SLICE_45:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C8C.CLK to       R6C8C.Q1 SLICE_1 (from RCLK_c)
+ROUTE         5     0.984       R6C8C.Q1 to       R4C8D.D1 FS_12
+CTOF_DEL    ---     0.495       R4C8D.D1 to       R4C8D.F1 SLICE_80
+ROUTE         3     1.598       R4C8D.F1 to       R4C7B.C1 n2375
+CTOF_DEL    ---     0.495       R4C7B.C1 to       R4C7B.F1 SLICE_95
+ROUTE         1     0.436       R4C7B.F1 to       R4C7A.C1 n7
+CTOF_DEL    ---     0.495       R4C7A.C1 to       R4C7A.F1 SLICE_45
+ROUTE         1     0.626       R4C7A.F1 to       R4C7A.D0 n2174
+CTOF_DEL    ---     0.495       R4C7A.D0 to       R4C7A.F0 SLICE_45
+ROUTE         1     0.000       R4C7A.F0 to      R4C7A.DI0 UFMSDI_N_231 (to RCLK_c)
+                  --------
+                    6.076   (40.0% logic, 60.0% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R6C8C.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_45:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R4C7A.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.710ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i14  (from RCLK_c +)
+   Destination:    FF         Data in        UFMSDI_417  (to RCLK_c +)
+
+   Delay:               5.884ns  (41.3% logic, 58.7% route), 5 logic levels.
+
+ Constraint Details:
+
+      5.884ns physical path delay SLICE_0 to SLICE_45 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.710ns
+
+ Physical Path Details:
+
+      Data path SLICE_0 to SLICE_45:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C8D.CLK to       R6C8D.Q1 SLICE_0 (from RCLK_c)
+ROUTE         5     0.792       R6C8D.Q1 to       R4C8D.C1 FS_14
+CTOF_DEL    ---     0.495       R4C8D.C1 to       R4C8D.F1 SLICE_80
+ROUTE         3     1.598       R4C8D.F1 to       R4C7B.C1 n2375
+CTOF_DEL    ---     0.495       R4C7B.C1 to       R4C7B.F1 SLICE_95
+ROUTE         1     0.436       R4C7B.F1 to       R4C7A.C1 n7
+CTOF_DEL    ---     0.495       R4C7A.C1 to       R4C7A.F1 SLICE_45
+ROUTE         1     0.626       R4C7A.F1 to       R4C7A.D0 n2174
+CTOF_DEL    ---     0.495       R4C7A.D0 to       R4C7A.F0 SLICE_45
+ROUTE         1     0.000       R4C7A.F0 to      R4C7A.DI0 UFMSDI_N_231 (to RCLK_c)
+                  --------
+                    5.884   (41.3% logic, 58.7% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R6C8D.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_45:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R4C7A.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.665ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CASr2_383  (from RCLK_c +)
+   Destination:    FF         Data in        nRCS_396  (to RCLK_c +)
+
+   Delay:               5.839ns  (41.7% logic, 58.3% route), 5 logic levels.
+
+ Constraint Details:
+
+      5.839ns physical path delay SLICE_16 to SLICE_61 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.665ns
+
+ Physical Path Details:
+
+      Data path SLICE_16 to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R4C9B.CLK to       R4C9B.Q1 SLICE_16 (from RCLK_c)
+ROUTE         3     1.000       R4C9B.Q1 to       R6C9D.A0 CASr2
+CTOF_DEL    ---     0.495       R6C9D.A0 to       R6C9D.F0 SLICE_96
+ROUTE         2     0.976       R6C9D.F0 to       R6C9C.A0 nRCS_N_146
+CTOF_DEL    ---     0.495       R6C9C.A0 to       R6C9C.F0 SLICE_81
+ROUTE         2     0.995       R6C9C.F0 to      R6C11D.A1 nRCS_N_142
+CTOF_DEL    ---     0.495      R6C11D.A1 to      R6C11D.F1 SLICE_61
+ROUTE         1     0.436      R6C11D.F1 to      R6C11D.C0 nRCS_N_141
+CTOF_DEL    ---     0.495      R6C11D.C0 to      R6C11D.F0 SLICE_61
+ROUTE         1     0.000      R6C11D.F0 to     R6C11D.DI0 nRCS_N_136 (to RCLK_c)
+                  --------
+                    5.839   (41.7% logic, 58.3% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R4C9B.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to     R6C11D.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.621ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i15  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_418  (to RCLK_c +)
+
+   Delay:               5.679ns  (34.1% logic, 65.9% route), 4 logic levels.
+
+ Constraint Details:
+
+      5.679ns physical path delay SLICE_9 to SLICE_57 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.282ns CE_SET requirement (totaling 3.058ns) by 2.621ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C9A.CLK to       R6C9A.Q0 SLICE_9 (from RCLK_c)
+ROUTE         3     1.320       R6C9A.Q0 to       R4C8A.A0 FS_15
+CTOF_DEL    ---     0.495       R4C8A.A0 to       R4C8A.F0 SLICE_85
+ROUTE         5     0.793       R4C8A.F0 to       R4C8B.C1 n10
+CTOF_DEL    ---     0.495       R4C8B.C1 to       R4C8B.F1 SLICE_57
+ROUTE         2     0.976       R4C8B.F1 to       R4C8C.A0 n2367
+CTOF_DEL    ---     0.495       R4C8C.A0 to       R4C8C.F0 SLICE_84
+ROUTE         1     0.653       R4C8C.F0 to       R4C8B.CE RCLK_c_enable_15 (to RCLK_c)
+                  --------
+                    5.679   (34.1% logic, 65.9% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R6C9A.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R4C8B.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.513ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i12  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_418  (to RCLK_c +)
+
+   Delay:               5.571ns  (34.8% logic, 65.2% route), 4 logic levels.
+
+ Constraint Details:
+
+      5.571ns physical path delay SLICE_1 to SLICE_57 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.282ns CE_SET requirement (totaling 3.058ns) by 2.513ns
+
+ Physical Path Details:
+
+      Data path SLICE_1 to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C8C.CLK to       R6C8C.Q1 SLICE_1 (from RCLK_c)
+ROUTE         5     0.984       R6C8C.Q1 to       R4C8D.D1 FS_12
+CTOF_DEL    ---     0.495       R4C8D.D1 to       R4C8D.F1 SLICE_80
+ROUTE         3     1.021       R4C8D.F1 to       R4C8B.B1 n2375
+CTOF_DEL    ---     0.495       R4C8B.B1 to       R4C8B.F1 SLICE_57
+ROUTE         2     0.976       R4C8B.F1 to       R4C8C.A0 n2367
+CTOF_DEL    ---     0.495       R4C8C.A0 to       R4C8C.F0 SLICE_84
+ROUTE         1     0.653       R4C8C.F0 to       R4C8B.CE RCLK_c_enable_15 (to RCLK_c)
+                  --------
+                    5.571   (34.8% logic, 65.2% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R6C8C.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R4C8B.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.487ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i3  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_418  (to RCLK_c +)
+
+   Delay:               5.545ns  (34.9% logic, 65.1% route), 4 logic levels.
+
+ Constraint Details:
+
+      5.545ns physical path delay SLICE_8 to SLICE_57 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.282ns CE_SET requirement (totaling 3.058ns) by 2.487ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C7C.CLK to       R6C7C.Q0 SLICE_8 (from RCLK_c)
+ROUTE         2     1.306       R6C7C.Q0 to       R4C7D.A1 FS_3
+CTOF_DEL    ---     0.495       R4C7D.A1 to       R4C7D.F1 SLICE_86
+ROUTE         1     1.004       R4C7D.F1 to       R4C7D.B0 n14
+CTOF_DEL    ---     0.495       R4C7D.B0 to       R4C7D.F0 SLICE_86
+ROUTE         1     0.645       R4C7D.F0 to       R4C8C.D0 n4_adj_7
+CTOF_DEL    ---     0.495       R4C8C.D0 to       R4C8C.F0 SLICE_84
+ROUTE         1     0.653       R4C8C.F0 to       R4C8B.CE RCLK_c_enable_15 (to RCLK_c)
+                  --------
+                    5.545   (34.9% logic, 65.1% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R6C7C.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R4C8B.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.479ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i15  (from RCLK_c +)
+   Destination:    FF         Data in        nUFMCS_415  (to RCLK_c +)
+
+   Delay:               5.653ns  (43.0% logic, 57.0% route), 5 logic levels.
+
+ Constraint Details:
+
+      5.653ns physical path delay SLICE_9 to SLICE_70 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.479ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C9A.CLK to       R6C9A.Q0 SLICE_9 (from RCLK_c)
+ROUTE         3     1.320       R6C9A.Q0 to       R4C8A.A0 FS_15
+CTOF_DEL    ---     0.495       R4C8A.A0 to       R4C8A.F0 SLICE_85
+ROUTE         5     0.640       R4C8A.F0 to       R4C9D.D1 n10
+CTOF_DEL    ---     0.495       R4C9D.D1 to       R4C9D.F1 SLICE_76
+ROUTE         2     0.635       R4C9D.F1 to       R4C9A.D1 n2368
+CTOF_DEL    ---     0.495       R4C9A.D1 to       R4C9A.F1 SLICE_70
+ROUTE         1     0.626       R4C9A.F1 to       R4C9A.D0 n64
+CTOF_DEL    ---     0.495       R4C9A.D0 to       R4C9A.F0 SLICE_70
+ROUTE         1     0.000       R4C9A.F0 to      R4C9A.DI0 nUFMCS_N_199 (to RCLK_c)
+                  --------
+                    5.653   (43.0% logic, 57.0% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R6C9A.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R4C9A.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.452ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i15  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
+
+   Delay:               5.626ns  (43.2% logic, 56.8% route), 5 logic levels.
+
+ Constraint Details:
+
+      5.626ns physical path delay SLICE_9 to SLICE_44 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.452ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C9A.CLK to       R6C9A.Q0 SLICE_9 (from RCLK_c)
+ROUTE         3     1.320       R6C9A.Q0 to       R4C8A.A0 FS_15
+CTOF_DEL    ---     0.495       R4C8A.A0 to       R4C8A.F0 SLICE_85
+ROUTE         5     0.672       R4C8A.F0 to       R4C8A.D1 n10
+CTOF_DEL    ---     0.495       R4C8A.D1 to       R4C8A.F1 SLICE_85
+ROUTE         1     0.766       R4C8A.F1 to       R4C6B.C1 n2267
+CTOF_DEL    ---     0.495       R4C6B.C1 to       R4C6B.F1 SLICE_44
+ROUTE         1     0.436       R4C6B.F1 to       R4C6B.C0 n1893
+CTOF_DEL    ---     0.495       R4C6B.C0 to       R4C6B.F0 SLICE_44
+ROUTE         1     0.000       R4C6B.F0 to      R4C6B.DI0 UFMCLK_N_224 (to RCLK_c)
+                  --------
+                    5.626   (43.2% logic, 56.8% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R6C9A.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R4C6B.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.438ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CASr3_384  (from RCLK_c +)
+   Destination:    FF         Data in        nRCS_396  (to RCLK_c +)
+
+   Delay:               5.612ns  (43.3% logic, 56.7% route), 5 logic levels.
+
+ Constraint Details:
+
+      5.612ns physical path delay SLICE_5 to SLICE_61 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.438ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C7A.CLK to       R6C7A.Q0 SLICE_5 (from RCLK_c)
+ROUTE         2     0.773       R6C7A.Q0 to       R6C9D.C0 CASr3
+CTOF_DEL    ---     0.495       R6C9D.C0 to       R6C9D.F0 SLICE_96
+ROUTE         2     0.976       R6C9D.F0 to       R6C9C.A0 nRCS_N_146
+CTOF_DEL    ---     0.495       R6C9C.A0 to       R6C9C.F0 SLICE_81
+ROUTE         2     0.995       R6C9C.F0 to      R6C11D.A1 nRCS_N_142
+CTOF_DEL    ---     0.495      R6C11D.A1 to      R6C11D.F1 SLICE_61
+ROUTE         1     0.436      R6C11D.F1 to      R6C11D.C0 nRCS_N_141
+CTOF_DEL    ---     0.495      R6C11D.C0 to      R6C11D.F0 SLICE_61
+ROUTE         1     0.000      R6C11D.F0 to     R6C11D.DI0 nRCS_N_136 (to RCLK_c)
+                  --------
+                    5.612   (43.3% logic, 56.7% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R6C7A.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to     R6C11D.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.423ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i13  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
+
+   Delay:               5.597ns  (43.5% logic, 56.5% route), 5 logic levels.
+
+ Constraint Details:
+
+      5.597ns physical path delay SLICE_0 to SLICE_44 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.423ns
+
+ Physical Path Details:
+
+      Data path SLICE_0 to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C8D.CLK to       R6C8D.Q0 SLICE_0 (from RCLK_c)
+ROUTE         3     1.433       R6C8D.Q0 to       R6C6C.B0 FS_13
+CTOF_DEL    ---     0.495       R6C6C.B0 to       R6C6C.F0 SLICE_105
+ROUTE         1     0.315       R6C6C.F0 to       R6C6A.D1 n12
+CTOF_DEL    ---     0.495       R6C6A.D1 to       R6C6A.F1 SLICE_82
+ROUTE         3     0.981       R6C6A.F1 to       R4C6B.D1 n13_adj_6
+CTOF_DEL    ---     0.495       R4C6B.D1 to       R4C6B.F1 SLICE_44
+ROUTE         1     0.436       R4C6B.F1 to       R4C6B.C0 n1893
+CTOF_DEL    ---     0.495       R4C6B.C0 to       R4C6B.F0 SLICE_44
+ROUTE         1     0.000       R4C6B.F0 to      R4C6B.DI0 UFMCLK_N_224 (to RCLK_c)
+                  --------
+                    5.597   (43.5% logic, 56.5% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R6C8D.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R4C6B.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+Warning: 160.205MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
+            113 items scored, 85 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 2.561ns (weighted slack = -5.122ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i3  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               7.301ns  (40.1% logic, 59.9% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.301ns physical path delay SLICE_103 to SLICE_19 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 4.740ns) by 2.561ns
+
+ Physical Path Details:
+
+      Data path SLICE_103 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q1 SLICE_103 (from PHI2_c)
+ROUTE         1     1.023       R5C9B.Q1 to       R5C7A.B0 Bank_3
+CTOF_DEL    ---     0.495       R5C7A.B0 to       R5C7A.F0 SLICE_68
+ROUTE         1     0.626       R5C7A.F0 to       R5C7D.D1 n2287
+CTOF_DEL    ---     0.495       R5C7D.D1 to       R5C7D.F1 SLICE_74
+ROUTE         8     0.693       R5C7D.F1 to       R5C8A.D1 n26
+CTOF_DEL    ---     0.495       R5C8A.D1 to       R5C8A.F1 SLICE_91
+ROUTE         1     0.744       R5C8A.F1 to       R5C9A.C0 n2362
+CTOF_DEL    ---     0.495       R5C9A.C0 to       R5C9A.F0 SLICE_88
+ROUTE         3     0.635       R5C9A.F0 to       R5C9A.D1 C1Submitted_N_237
+CTOF_DEL    ---     0.495       R5C9A.D1 to       R5C9A.F1 SLICE_88
+ROUTE         1     0.653       R5C9A.F1 to       R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    7.301   (40.1% logic, 59.9% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_103:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.184ns (weighted slack = -4.368ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i3  (from PHI2_c +)
+   Destination:    FF         Data in        ADSubmitted_407  (to PHI2_c -)
+
+   Delay:               6.946ns  (35.0% logic, 65.0% route), 5 logic levels.
+
+ Constraint Details:
+
+      6.946ns physical path delay SLICE_103 to SLICE_10 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.285ns LSR_SET requirement (totaling 4.762ns) by 2.184ns
+
+ Physical Path Details:
+
+      Data path SLICE_103 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q1 SLICE_103 (from PHI2_c)
+ROUTE         1     1.023       R5C9B.Q1 to       R5C7A.B0 Bank_3
+CTOF_DEL    ---     0.495       R5C7A.B0 to       R5C7A.F0 SLICE_68
+ROUTE         1     0.626       R5C7A.F0 to       R5C7D.D1 n2287
+CTOF_DEL    ---     0.495       R5C7D.D1 to       R5C7D.F1 SLICE_74
+ROUTE         8     0.693       R5C7D.F1 to       R5C8A.D1 n26
+CTOF_DEL    ---     0.495       R5C8A.D1 to       R5C8A.F1 SLICE_91
+ROUTE         1     0.744       R5C8A.F1 to       R5C9A.C0 n2362
+CTOF_DEL    ---     0.495       R5C9A.C0 to       R5C9A.F0 SLICE_88
+ROUTE         3     1.428       R5C9A.F0 to      R3C8A.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    6.946   (35.0% logic, 65.0% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_103:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R3C8A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.184ns (weighted slack = -4.368ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i3  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               6.946ns  (35.0% logic, 65.0% route), 5 logic levels.
+
+ Constraint Details:
+
+      6.946ns physical path delay SLICE_103 to SLICE_15 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.285ns LSR_SET requirement (totaling 4.762ns) by 2.184ns
+
+ Physical Path Details:
+
+      Data path SLICE_103 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q1 SLICE_103 (from PHI2_c)
+ROUTE         1     1.023       R5C9B.Q1 to       R5C7A.B0 Bank_3
+CTOF_DEL    ---     0.495       R5C7A.B0 to       R5C7A.F0 SLICE_68
+ROUTE         1     0.626       R5C7A.F0 to       R5C7D.D1 n2287
+CTOF_DEL    ---     0.495       R5C7D.D1 to       R5C7D.F1 SLICE_74
+ROUTE         8     0.693       R5C7D.F1 to       R5C8A.D1 n26
+CTOF_DEL    ---     0.495       R5C8A.D1 to       R5C8A.F1 SLICE_91
+ROUTE         1     0.744       R5C8A.F1 to       R5C9A.C0 n2362
+CTOF_DEL    ---     0.495       R5C9A.C0 to       R5C9A.F0 SLICE_88
+ROUTE         3     1.428       R5C9A.F0 to      R3C8B.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    6.946   (35.0% logic, 65.0% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_103:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R3C8B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.161ns (weighted slack = -4.322ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               6.901ns  (42.4% logic, 57.6% route), 6 logic levels.
+
+ Constraint Details:
+
+      6.901ns physical path delay SLICE_101 to SLICE_19 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 4.740ns) by 2.161ns
+
+ Physical Path Details:
+
+      Data path SLICE_101 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R4C7C.CLK to       R4C7C.Q0 SLICE_101 (from PHI2_c)
+ROUTE         1     0.623       R4C7C.Q0 to       R5C7A.D0 Bank_6
+CTOF_DEL    ---     0.495       R5C7A.D0 to       R5C7A.F0 SLICE_68
+ROUTE         1     0.626       R5C7A.F0 to       R5C7D.D1 n2287
+CTOF_DEL    ---     0.495       R5C7D.D1 to       R5C7D.F1 SLICE_74
+ROUTE         8     0.693       R5C7D.F1 to       R5C8A.D1 n26
+CTOF_DEL    ---     0.495       R5C8A.D1 to       R5C8A.F1 SLICE_91
+ROUTE         1     0.744       R5C8A.F1 to       R5C9A.C0 n2362
+CTOF_DEL    ---     0.495       R5C9A.C0 to       R5C9A.F0 SLICE_88
+ROUTE         3     0.635       R5C9A.F0 to       R5C9A.D1 C1Submitted_N_237
+CTOF_DEL    ---     0.495       R5C9A.D1 to       R5C9A.F1 SLICE_88
+ROUTE         1     0.653       R5C9A.F1 to       R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    6.901   (42.4% logic, 57.6% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_101:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R4C7C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.092ns (weighted slack = -4.184ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               6.832ns  (42.8% logic, 57.2% route), 6 logic levels.
+
+ Constraint Details:
+
+      6.832ns physical path delay SLICE_101 to SLICE_19 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 4.740ns) by 2.092ns
+
+ Physical Path Details:
+
+      Data path SLICE_101 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R4C7C.CLK to       R4C7C.Q1 SLICE_101 (from PHI2_c)
+ROUTE         1     0.744       R4C7C.Q1 to       R5C7B.C1 Bank_7
+CTOF_DEL    ---     0.495       R5C7B.C1 to       R5C7B.F1 SLICE_100
+ROUTE         1     0.436       R5C7B.F1 to       R5C7D.C1 n2277
+CTOF_DEL    ---     0.495       R5C7D.C1 to       R5C7D.F1 SLICE_74
+ROUTE         8     0.693       R5C7D.F1 to       R5C8A.D1 n26
+CTOF_DEL    ---     0.495       R5C8A.D1 to       R5C8A.F1 SLICE_91
+ROUTE         1     0.744       R5C8A.F1 to       R5C9A.C0 n2362
+CTOF_DEL    ---     0.495       R5C9A.C0 to       R5C9A.F0 SLICE_88
+ROUTE         3     0.635       R5C9A.F0 to       R5C9A.D1 C1Submitted_N_237
+CTOF_DEL    ---     0.495       R5C9A.D1 to       R5C9A.F1 SLICE_88
+ROUTE         1     0.653       R5C9A.F1 to       R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    6.832   (42.8% logic, 57.2% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_101:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R4C7C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.081ns (weighted slack = -4.162ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i4  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               6.821ns  (42.9% logic, 57.1% route), 6 logic levels.
+
+ Constraint Details:
+
+      6.821ns physical path delay SLICE_102 to SLICE_19 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 4.740ns) by 2.081ns
+
+ Physical Path Details:
+
+      Data path SLICE_102 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C6A.CLK to       R5C6A.Q0 SLICE_102 (from PHI2_c)
+ROUTE         1     0.766       R5C6A.Q0 to       R5C8D.C1 Bank_4
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_99
+ROUTE         2     0.635       R5C8D.F1 to       R5C8B.D1 n22
+CTOF_DEL    ---     0.495       R5C8B.D1 to       R5C8B.F1 SLICE_79
+ROUTE         7     0.461       R5C8B.F1 to       R5C8A.C1 n2369
+CTOF_DEL    ---     0.495       R5C8A.C1 to       R5C8A.F1 SLICE_91
+ROUTE         1     0.744       R5C8A.F1 to       R5C9A.C0 n2362
+CTOF_DEL    ---     0.495       R5C9A.C0 to       R5C9A.F0 SLICE_88
+ROUTE         3     0.635       R5C9A.F0 to       R5C9A.D1 C1Submitted_N_237
+CTOF_DEL    ---     0.495       R5C9A.D1 to       R5C9A.F1 SLICE_88
+ROUTE         1     0.653       R5C9A.F1 to       R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    6.821   (42.9% logic, 57.1% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_102:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.971ns (weighted slack = -3.942ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               6.711ns  (43.6% logic, 56.4% route), 6 logic levels.
+
+ Constraint Details:
+
+      6.711ns physical path delay SLICE_93 to SLICE_19 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 4.740ns) by 1.971ns
+
+ Physical Path Details:
+
+      Data path SLICE_93 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C8C.CLK to       R5C8C.Q0 SLICE_93 (from PHI2_c)
+ROUTE         1     0.623       R5C8C.Q0 to       R5C7B.D1 Bank_0
+CTOF_DEL    ---     0.495       R5C7B.D1 to       R5C7B.F1 SLICE_100
+ROUTE         1     0.436       R5C7B.F1 to       R5C7D.C1 n2277
+CTOF_DEL    ---     0.495       R5C7D.C1 to       R5C7D.F1 SLICE_74
+ROUTE         8     0.693       R5C7D.F1 to       R5C8A.D1 n26
+CTOF_DEL    ---     0.495       R5C8A.D1 to       R5C8A.F1 SLICE_91
+ROUTE         1     0.744       R5C8A.F1 to       R5C9A.C0 n2362
+CTOF_DEL    ---     0.495       R5C9A.C0 to       R5C9A.F0 SLICE_88
+ROUTE         3     0.635       R5C9A.F0 to       R5C9A.D1 C1Submitted_N_237
+CTOF_DEL    ---     0.495       R5C9A.D1 to       R5C9A.F1 SLICE_88
+ROUTE         1     0.653       R5C9A.F1 to       R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    6.711   (43.6% logic, 56.4% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C8C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.941ns (weighted slack = -3.882ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i1  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               6.681ns  (43.8% logic, 56.2% route), 6 logic levels.
+
+ Constraint Details:
+
+      6.681ns physical path delay SLICE_93 to SLICE_19 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 4.740ns) by 1.941ns
+
+ Physical Path Details:
+
+      Data path SLICE_93 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C8C.CLK to       R5C8C.Q1 SLICE_93 (from PHI2_c)
+ROUTE         1     0.626       R5C8C.Q1 to       R5C8D.D1 Bank_1
+CTOF_DEL    ---     0.495       R5C8D.D1 to       R5C8D.F1 SLICE_99
+ROUTE         2     0.635       R5C8D.F1 to       R5C8B.D1 n22
+CTOF_DEL    ---     0.495       R5C8B.D1 to       R5C8B.F1 SLICE_79
+ROUTE         7     0.461       R5C8B.F1 to       R5C8A.C1 n2369
+CTOF_DEL    ---     0.495       R5C8A.C1 to       R5C8A.F1 SLICE_91
+ROUTE         1     0.744       R5C8A.F1 to       R5C9A.C0 n2362
+CTOF_DEL    ---     0.495       R5C9A.C0 to       R5C9A.F0 SLICE_88
+ROUTE         3     0.635       R5C9A.F0 to       R5C9A.D1 C1Submitted_N_237
+CTOF_DEL    ---     0.495       R5C9A.D1 to       R5C9A.F1 SLICE_88
+ROUTE         1     0.653       R5C9A.F1 to       R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    6.681   (43.8% logic, 56.2% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C8C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.784ns (weighted slack = -3.568ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        ADSubmitted_407  (to PHI2_c -)
+
+   Delay:               6.546ns  (37.2% logic, 62.8% route), 5 logic levels.
+
+ Constraint Details:
+
+      6.546ns physical path delay SLICE_101 to SLICE_10 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.285ns LSR_SET requirement (totaling 4.762ns) by 1.784ns
+
+ Physical Path Details:
+
+      Data path SLICE_101 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R4C7C.CLK to       R4C7C.Q0 SLICE_101 (from PHI2_c)
+ROUTE         1     0.623       R4C7C.Q0 to       R5C7A.D0 Bank_6
+CTOF_DEL    ---     0.495       R5C7A.D0 to       R5C7A.F0 SLICE_68
+ROUTE         1     0.626       R5C7A.F0 to       R5C7D.D1 n2287
+CTOF_DEL    ---     0.495       R5C7D.D1 to       R5C7D.F1 SLICE_74
+ROUTE         8     0.693       R5C7D.F1 to       R5C8A.D1 n26
+CTOF_DEL    ---     0.495       R5C8A.D1 to       R5C8A.F1 SLICE_91
+ROUTE         1     0.744       R5C8A.F1 to       R5C9A.C0 n2362
+CTOF_DEL    ---     0.495       R5C9A.C0 to       R5C9A.F0 SLICE_88
+ROUTE         3     1.428       R5C9A.F0 to      R3C8A.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    6.546   (37.2% logic, 62.8% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_101:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R4C7C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R3C8A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.784ns (weighted slack = -3.568ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               6.546ns  (37.2% logic, 62.8% route), 5 logic levels.
+
+ Constraint Details:
+
+      6.546ns physical path delay SLICE_101 to SLICE_15 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.285ns LSR_SET requirement (totaling 4.762ns) by 1.784ns
+
+ Physical Path Details:
+
+      Data path SLICE_101 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R4C7C.CLK to       R4C7C.Q0 SLICE_101 (from PHI2_c)
+ROUTE         1     0.623       R4C7C.Q0 to       R5C7A.D0 Bank_6
+CTOF_DEL    ---     0.495       R5C7A.D0 to       R5C7A.F0 SLICE_68
+ROUTE         1     0.626       R5C7A.F0 to       R5C7D.D1 n2287
+CTOF_DEL    ---     0.495       R5C7D.D1 to       R5C7D.F1 SLICE_74
+ROUTE         8     0.693       R5C7D.F1 to       R5C8A.D1 n26
+CTOF_DEL    ---     0.495       R5C8A.D1 to       R5C8A.F1 SLICE_91
+ROUTE         1     0.744       R5C8A.F1 to       R5C9A.C0 n2362
+CTOF_DEL    ---     0.495       R5C9A.C0 to       R5C9A.F0 SLICE_88
+ROUTE         3     1.428       R5C9A.F0 to      R3C8B.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    6.546   (37.2% logic, 62.8% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_101:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R4C7C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R3C8B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+Warning:  65.729MHz is the maximum frequency for this preference.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "RCLK_c" 299.401000 MHz ; |  299.401 MHz|  160.205 MHz|   5 *
+                                        |             |             |
+FREQUENCY NET "PHI2_c" 99.079000 MHz ;  |   99.079 MHz|   65.729 MHz|   6 *
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+2 preferences(marked by "*" above) not met.
+
+----------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+----------------------------------------------------------------------------
+n26                                     |       8|      63|     18.05%
+                                        |        |        |
+n1996                                   |       1|      49|     14.04%
+                                        |        |        |
+n1997                                   |       1|      46|     13.18%
+                                        |        |        |
+n1995                                   |       1|      45|     12.89%
+                                        |        |        |
+n1998                                   |       1|      38|     10.89%
+                                        |        |        |
+n1994                                   |       1|      37|     10.60%
+                                        |        |        |
+----------------------------------------------------------------------------
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
+   Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 349  Score: 452301
+Cumulative negative slack: 370485
+
+Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
+Tue Aug 15 05:03:36 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_640hc_impl1.ncd
+Preference file: ram2gs_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,m
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "RCLK_c" 299.401000 MHz (0 errors)
    •             459 items scored, 0 timing errors detected.
+
+
  • FREQUENCY NET "PHI2_c" 99.079000 MHz (0 errors)
    •             113 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
+            459 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i4  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i5  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_106 to SLICE_106 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_106 to SLICE_106:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C8D.CLK to       R3C8D.Q0 SLICE_106 (from RCLK_c)
+ROUTE         1     0.152       R3C8D.Q0 to       R3C8D.M1 n736 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_106:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to      R3C8D.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_106:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to      R3C8D.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CASr_382  (from RCLK_c +)
+   Destination:    FF         Data in        CASr2_383  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_16 to SLICE_16 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_16 to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R4C9B.CLK to       R4C9B.Q0 SLICE_16 (from RCLK_c)
+ROUTE         1     0.152       R4C9B.Q0 to       R4C9B.M1 CASr (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to      R4C9B.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to      R4C9B.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i8  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i9  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_75 to SLICE_75 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_75 to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9D.CLK to       R3C9D.Q0 SLICE_75 (from RCLK_c)
+ROUTE         1     0.152       R3C9D.Q0 to       R3C9D.M1 n732 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to      R3C9D.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to      R3C9D.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i10  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i11  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_79 to SLICE_79 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_79 to SLICE_79:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C8B.CLK to       R5C8B.Q0 SLICE_79 (from RCLK_c)
+ROUTE         1     0.152       R5C8B.Q0 to       R5C8B.M1 n730 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_79:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to      R5C8B.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_79:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to      R5C8B.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i14  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i15  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_81 to SLICE_81 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_81 to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R6C9C.CLK to       R6C9C.Q0 SLICE_81 (from RCLK_c)
+ROUTE         1     0.152       R6C9C.Q0 to       R6C9C.M1 n726 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to      R6C9C.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to      R6C9C.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i7  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i8  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_97 to SLICE_75 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_97 to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9A.CLK to       R3C9A.Q1 SLICE_97 (from RCLK_c)
+ROUTE         1     0.152       R3C9A.Q1 to       R3C9D.M0 n733 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to      R3C9A.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to      R3C9D.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i6  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i7  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_97 to SLICE_97 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_97 to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9A.CLK to       R3C9A.Q0 SLICE_97 (from RCLK_c)
+ROUTE         1     0.152       R3C9A.Q0 to       R3C9A.M1 n734 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to      R3C9A.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to      R3C9A.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.306ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RASr_379  (from RCLK_c +)
+   Destination:    FF         Data in        RASr2_380  (to RCLK_c +)
+
+   Delay:               0.287ns  (46.3% logic, 53.7% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.287ns physical path delay SLICE_30 to SLICE_30 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.306ns
+
+ Physical Path Details:
+
+      Data path SLICE_30 to SLICE_30:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10B.CLK to      R5C10B.Q0 SLICE_30 (from RCLK_c)
+ROUTE         2     0.154      R5C10B.Q0 to      R5C10B.M1 RASr (to RCLK_c)
+                  --------
+                    0.287   (46.3% logic, 53.7% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_30:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to     R5C10B.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_30:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to     R5C10B.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.306ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              PHI2r2_377  (from RCLK_c +)
+   Destination:    FF         Data in        PHI2r3_378  (to RCLK_c +)
+
+   Delay:               0.287ns  (46.3% logic, 53.7% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.287ns physical path delay SLICE_36 to SLICE_69 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.306ns
+
+ Physical Path Details:
+
+      Data path SLICE_36 to SLICE_69:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R4C10A.CLK to      R4C10A.Q1 SLICE_36 (from RCLK_c)
+ROUTE         3     0.154      R4C10A.Q1 to      R4C10C.M1 PHI2r2 (to RCLK_c)
+                  --------
+                    0.287   (46.3% logic, 53.7% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_36:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to     R4C10A.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_69:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to     R4C10C.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.307ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i0  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i1  (to RCLK_c +)
+
+   Delay:               0.288ns  (46.2% logic, 53.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.288ns physical path delay SLICE_98 to SLICE_98 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.307ns
+
+ Physical Path Details:
+
+      Data path SLICE_98 to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R6C11A.CLK to      R6C11A.Q0 SLICE_98 (from RCLK_c)
+ROUTE         4     0.155      R6C11A.Q0 to      R6C11A.M1 nRCS_N_139 (to RCLK_c)
+                  --------
+                    0.288   (46.2% logic, 53.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to     R6C11A.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to     R6C11A.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
+            113 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_406  (from PHI2_c -)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_15 to SLICE_15 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_15 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C8B.CLK to       R3C8B.Q0 SLICE_15 (from PHI2_c)
+ROUTE         2     0.132       R3C8B.Q0 to       R3C8B.A0 C1Submitted
+CTOF_DEL    ---     0.101       R3C8B.A0 to       R3C8B.F0 SLICE_15
+ROUTE         1     0.000       R3C8B.F0 to      R3C8B.DI0 n1398 (to PHI2_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C8B.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C8B.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.851ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        XOR8MEG_408  (to PHI2_c -)
+
+   Delay:               0.823ns  (28.4% logic, 71.6% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.823ns physical path delay SLICE_19 to SLICE_50 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 0.851ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_50:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C9D.CLK to       R5C9D.Q0 SLICE_19 (from PHI2_c)
+ROUTE         2     0.332       R5C9D.Q0 to       R5C6B.D1 CmdEnable
+CTOF_DEL    ---     0.101       R5C6B.D1 to       R5C6B.F1 SLICE_83
+ROUTE         1     0.257       R5C6B.F1 to       R4C6A.CE PHI2_N_120_enable_3 (to PHI2_c)
+                  --------
+                    0.823   (28.4% logic, 71.6% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_50:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R4C6A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.906ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_407  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               0.878ns  (26.7% logic, 73.3% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.878ns physical path delay SLICE_10 to SLICE_19 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 0.906ns
+
+ Physical Path Details:
+
+      Data path SLICE_10 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C8A.CLK to       R3C8A.Q0 SLICE_10 (from PHI2_c)
+ROUTE         1     0.501       R3C8A.Q0 to       R5C9A.B1 ADSubmitted
+CTOF_DEL    ---     0.101       R5C9A.B1 to       R5C9A.F1 SLICE_88
+ROUTE         1     0.143       R5C9A.F1 to       R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    0.878   (26.7% logic, 73.3% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C8A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.937ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_406  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               0.909ns  (48.0% logic, 52.0% route), 4 logic levels.
+
+ Constraint Details:
+
+      0.909ns physical path delay SLICE_15 to SLICE_19 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 0.937ns
+
+ Physical Path Details:
+
+      Data path SLICE_15 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C8B.CLK to       R3C8B.Q0 SLICE_15 (from PHI2_c)
+ROUTE         2     0.136       R3C8B.Q0 to       R3C9B.D1 C1Submitted
+CTOF_DEL    ---     0.101       R3C9B.D1 to       R3C9B.F1 SLICE_77
+ROUTE         1     0.056       R3C9B.F1 to       R3C9A.C1 n2210
+CTOF_DEL    ---     0.101       R3C9A.C1 to       R3C9A.F1 SLICE_97
+ROUTE         1     0.138       R3C9A.F1 to       R5C9A.C1 n7_adj_5
+CTOF_DEL    ---     0.101       R5C9A.C1 to       R5C9A.F1 SLICE_88
+ROUTE         1     0.143       R5C9A.F1 to       R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    0.909   (48.0% logic, 52.0% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C8B.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.059ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMCS_412  (to PHI2_c -)
+                   FF                        CmdUFMCLK_413
+
+   Delay:               1.031ns  (32.5% logic, 67.5% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.031ns physical path delay SLICE_19 to SLICE_100 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 1.059ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_100:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C9D.CLK to       R5C9D.Q0 SLICE_19 (from PHI2_c)
+ROUTE         2     0.224       R5C9D.Q0 to       R5C6D.C0 CmdEnable
+CTOF_DEL    ---     0.101       R5C6D.C0 to       R5C6D.F0 SLICE_73
+ROUTE         2     0.212       R5C6D.F0 to       R5C6D.A1 n2204
+CTOF_DEL    ---     0.101       R5C6D.A1 to       R5C6D.F1 SLICE_73
+ROUTE         2     0.260       R5C6D.F1 to       R5C7B.CE PHI2_N_120_enable_8 (to PHI2_c)
+                  --------
+                    1.031   (32.5% logic, 67.5% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_100:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C7B.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.059ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMSDI_414  (to PHI2_c -)
+
+   Delay:               1.031ns  (32.5% logic, 67.5% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.031ns physical path delay SLICE_19 to SLICE_99 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 1.059ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C9D.CLK to       R5C9D.Q0 SLICE_19 (from PHI2_c)
+ROUTE         2     0.224       R5C9D.Q0 to       R5C6D.C0 CmdEnable
+CTOF_DEL    ---     0.101       R5C6D.C0 to       R5C6D.F0 SLICE_73
+ROUTE         2     0.212       R5C6D.F0 to       R5C6D.A1 n2204
+CTOF_DEL    ---     0.101       R5C6D.A1 to       R5C6D.F1 SLICE_73
+ROUTE         2     0.260       R5C6D.F1 to       R5C8D.CE PHI2_N_120_enable_8 (to PHI2_c)
+                  --------
+                    1.031   (32.5% logic, 67.5% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C8D.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.106ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        CmdSubmitted_411  (to PHI2_c -)
+
+   Delay:               1.078ns  (40.4% logic, 59.6% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.078ns physical path delay SLICE_19 to SLICE_20 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 1.106ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C9D.CLK to       R5C9D.Q0 SLICE_19 (from PHI2_c)
+ROUTE         2     0.224       R5C9D.Q0 to       R5C6D.C0 CmdEnable
+CTOF_DEL    ---     0.101       R5C6D.C0 to       R5C6D.F0 SLICE_73
+ROUTE         2     0.137       R5C6D.F0 to       R5C7D.D0 n2204
+CTOF_DEL    ---     0.101       R5C7D.D0 to       R5C7D.F0 SLICE_74
+ROUTE         2     0.138       R5C7D.F0 to       R3C7C.D1 n2220
+CTOF_DEL    ---     0.101       R3C7C.D1 to       R3C7C.F1 SLICE_89
+ROUTE         1     0.143       R3C7C.F1 to       R3C7D.CE PHI2_N_120_enable_7 (to PHI2_c)
+                  --------
+                    1.078   (40.4% logic, 59.6% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C7D.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.106ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        Cmdn8MEGEN_410  (to PHI2_c -)
+
+   Delay:               1.078ns  (40.4% logic, 59.6% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.078ns physical path delay SLICE_19 to SLICE_24 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 1.106ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C9D.CLK to       R5C9D.Q0 SLICE_19 (from PHI2_c)
+ROUTE         2     0.224       R5C9D.Q0 to       R5C6D.C0 CmdEnable
+CTOF_DEL    ---     0.101       R5C6D.C0 to       R5C6D.F0 SLICE_73
+ROUTE         2     0.137       R5C6D.F0 to       R5C7D.D0 n2204
+CTOF_DEL    ---     0.101       R5C7D.D0 to       R5C7D.F0 SLICE_74
+ROUTE         2     0.138       R5C7D.F0 to       R3C7C.D0 n2220
+CTOF_DEL    ---     0.101       R3C7C.D0 to       R3C7C.F0 SLICE_89
+ROUTE         1     0.143       R3C7C.F0 to       R3C7B.CE PHI2_N_120_enable_6 (to PHI2_c)
+                  --------
+                    1.078   (40.4% logic, 59.6% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C7B.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 5.504ns (weighted slack = 11.008ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              XOR8MEG_408  (from PHI2_c -)
+   Destination:    FF         Data in        RA11_385  (to PHI2_c +)
+
+   Delay:               0.444ns  (52.7% logic, 47.3% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.444ns physical path delay SLICE_50 to SLICE_33 meets
+     -0.013ns DIN_HLD and
+     -5.047ns delay constraint less
+      0.000ns skew requirement (totaling -5.060ns) by 5.504ns
+
+ Physical Path Details:
+
+      Data path SLICE_50 to SLICE_33:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R4C6A.CLK to       R4C6A.Q0 SLICE_50 (from PHI2_c)
+ROUTE         1     0.210       R4C6A.Q0 to       R4C6C.A0 XOR8MEG
+CTOF_DEL    ---     0.101       R4C6C.A0 to       R4C6C.F0 SLICE_33
+ROUTE         1     0.000       R4C6C.F0 to      R4C6C.DI0 RA11_N_184 (to PHI2_c)
+                  --------
+                    0.444   (52.7% logic, 47.3% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_50:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R4C6A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_33:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R4C6C.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 5.899ns (weighted slack = 11.798ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i1  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               0.839ns  (52.0% logic, 48.0% route), 4 logic levels.
+
+ Constraint Details:
+
+      0.839ns physical path delay SLICE_93 to SLICE_15 meets
+     -0.013ns DIN_HLD and
+     -5.047ns delay constraint less
+      0.000ns skew requirement (totaling -5.060ns) by 5.899ns
+
+ Physical Path Details:
+
+      Data path SLICE_93 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C8C.CLK to       R5C8C.Q1 SLICE_93 (from PHI2_c)
+ROUTE         1     0.133       R5C8C.Q1 to       R5C8D.D1 Bank_1
+CTOF_DEL    ---     0.101       R5C8D.D1 to       R5C8D.F1 SLICE_99
+ROUTE         2     0.214       R5C8D.F1 to       R3C8B.A1 n22
+CTOF_DEL    ---     0.101       R3C8B.A1 to       R3C8B.F1 SLICE_15
+ROUTE         1     0.056       R3C8B.F1 to       R3C8B.C0 n2365
+CTOF_DEL    ---     0.101       R3C8B.C0 to       R3C8B.F0 SLICE_15
+ROUTE         1     0.000       R3C8B.F0 to      R3C8B.DI0 n1398 (to PHI2_c)
+                  --------
+                    0.839   (52.0% logic, 48.0% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C8C.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C8B.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "RCLK_c" 299.401000 MHz ; |     0.000 ns|     0.304 ns|   1  
+                                        |             |             |
+FREQUENCY NET "PHI2_c" 99.079000 MHz ;  |     0.000 ns|     0.379 ns|   2  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
+   Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 349 (setup), 0 (hold)
+Score: 452301 (setup), 0 (hold)
+Cumulative negative slack: 370485 (370485+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_drc.log b/CPLD/LCMXO2-640HC/impl1/RAM2GS_drc.log new file mode 100644 index 0000000..e161627 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_drc.log @@ -0,0 +1,15 @@ +Results of NGD DRC are available in RAM2GS_drc.log. +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... + + +Running DRC... + +DRC complete with no errors or warnings + +Design Results: + 309 blocks expanded +completed the first expansion +All blocks are expanded and NGD expansion is successful. +Writing NGD file RAM2GS_LCMXO2_640HC_impl1.ngd. diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_lse.twr b/CPLD/LCMXO2-640HC/impl1/RAM2GS_lse.twr new file mode 100644 index 0000000..4586322 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_lse.twr @@ -0,0 +1,297 @@ +-------------------------------------------------------------------------------- +Lattice Synthesis Timing Report, Version +Tue Aug 15 05:03:23 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Design: RAM2GS +Constraint file: +Report level: verbose report, limited to 3 items per constraint +-------------------------------------------------------------------------------- + + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c] + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c] + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c] + 122 items scored, 119 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path violates requirements by 7.418ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK Bank_i1 (from PHI2_c +) + Destination: FD1P3AX SP CmdEnable_405 (to PHI2_c -) + + Delay: 9.633ns (30.2% logic, 69.8% route), 6 logic levels. + + Constraint Details: + + 9.633ns data_path Bank_i1 to CmdEnable_405 violates + 2.500ns delay constraint less + 0.285ns LCE_S requirement (totaling 2.215ns) by 7.418ns + + Path Details: Bank_i1 to CmdEnable_405 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.444 CK to Q Bank_i1 (from PHI2_c) +Route 1 e 0.941 Bank[1] +LUT4 --- 0.493 D to Z i8_4_lut +Route 2 e 1.141 n22 +LUT4 --- 0.493 B to Z i11_3_lut_rep_20 +Route 7 e 1.502 n2369 +LUT4 --- 0.493 A to Z i1_2_lut_rep_13_3_lut +Route 1 e 0.941 n2362 +LUT4 --- 0.493 D to Z i1_4_lut_adj_13 +Route 3 e 1.258 C1Submitted_N_237 +LUT4 --- 0.493 C to Z i34_4_lut +Route 1 e 0.941 PHI2_N_120_enable_1 + -------- + 9.633 (30.2% logic, 69.8% route), 6 logic levels. + + +Error: The following path violates requirements by 7.418ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK Bank_i4 (from PHI2_c +) + Destination: FD1P3AX SP CmdEnable_405 (to PHI2_c -) + + Delay: 9.633ns (30.2% logic, 69.8% route), 6 logic levels. + + Constraint Details: + + 9.633ns data_path Bank_i4 to CmdEnable_405 violates + 2.500ns delay constraint less + 0.285ns LCE_S requirement (totaling 2.215ns) by 7.418ns + + Path Details: Bank_i4 to CmdEnable_405 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.444 CK to Q Bank_i4 (from PHI2_c) +Route 1 e 0.941 Bank[4] +LUT4 --- 0.493 C to Z i8_4_lut +Route 2 e 1.141 n22 +LUT4 --- 0.493 B to Z i11_3_lut_rep_20 +Route 7 e 1.502 n2369 +LUT4 --- 0.493 A to Z i1_2_lut_rep_13_3_lut +Route 1 e 0.941 n2362 +LUT4 --- 0.493 D to Z i1_4_lut_adj_13 +Route 3 e 1.258 C1Submitted_N_237 +LUT4 --- 0.493 C to Z i34_4_lut +Route 1 e 0.941 PHI2_N_120_enable_1 + -------- + 9.633 (30.2% logic, 69.8% route), 6 logic levels. + + +Error: The following path violates requirements by 7.256ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK Bank_i3 (from PHI2_c +) + Destination: FD1P3AX SP CmdEnable_405 (to PHI2_c -) + + Delay: 9.471ns (30.7% logic, 69.3% route), 6 logic levels. + + Constraint Details: + + 9.471ns data_path Bank_i3 to CmdEnable_405 violates + 2.500ns delay constraint less + 0.285ns LCE_S requirement (totaling 2.215ns) by 7.256ns + + Path Details: Bank_i3 to CmdEnable_405 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.444 CK to Q Bank_i3 (from PHI2_c) +Route 1 e 0.941 Bank[3] +LUT4 --- 0.493 B to Z i1989_2_lut +Route 1 e 0.941 n2287 +LUT4 --- 0.493 C to Z i12_4_lut +Route 8 e 1.540 n26 +LUT4 --- 0.493 B to Z i1_2_lut_rep_13_3_lut +Route 1 e 0.941 n2362 +LUT4 --- 0.493 D to Z i1_4_lut_adj_13 +Route 3 e 1.258 C1Submitted_N_237 +LUT4 --- 0.493 C to Z i34_4_lut +Route 1 e 0.941 PHI2_N_120_enable_1 + -------- + 9.471 (30.7% logic, 69.3% route), 6 logic levels. + +Warning: 9.918 ns is the maximum delay for this constraint. + + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c] + 498 items scored, 186 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path violates requirements by 3.319ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK FS_610__i13 (from RCLK_c +) + Destination: FD1P3AY D nUFMCS_415 (to RCLK_c +) + + Delay: 8.159ns (29.6% logic, 70.4% route), 5 logic levels. + + Constraint Details: + + 8.159ns data_path FS_610__i13 to nUFMCS_415 violates + 5.000ns delay constraint less + 0.160ns L_S requirement (totaling 4.840ns) by 3.319ns + + Path Details: FS_610__i13 to nUFMCS_415 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.444 CK to Q FS_610__i13 (from RCLK_c) +Route 3 e 1.315 FS[13] +LUT4 --- 0.493 B to Z i3_4_lut_adj_7 +Route 5 e 1.405 n10 +LUT4 --- 0.493 C to Z i1_2_lut_rep_19_3_lut +Route 2 e 1.141 n2368 +LUT4 --- 0.493 B to Z i1_2_lut_4_lut +Route 1 e 0.941 n64 +LUT4 --- 0.493 B to Z i1448_4_lut +Route 1 e 0.941 nUFMCS_N_199 + -------- + 8.159 (29.6% logic, 70.4% route), 5 logic levels. + + +Error: The following path violates requirements by 3.319ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK FS_610__i15 (from RCLK_c +) + Destination: FD1P3AY D nUFMCS_415 (to RCLK_c +) + + Delay: 8.159ns (29.6% logic, 70.4% route), 5 logic levels. + + Constraint Details: + + 8.159ns data_path FS_610__i15 to nUFMCS_415 violates + 5.000ns delay constraint less + 0.160ns L_S requirement (totaling 4.840ns) by 3.319ns + + Path Details: FS_610__i15 to nUFMCS_415 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.444 CK to Q FS_610__i15 (from RCLK_c) +Route 3 e 1.315 FS[15] +LUT4 --- 0.493 C to Z i3_4_lut_adj_7 +Route 5 e 1.405 n10 +LUT4 --- 0.493 C to Z i1_2_lut_rep_19_3_lut +Route 2 e 1.141 n2368 +LUT4 --- 0.493 B to Z i1_2_lut_4_lut +Route 1 e 0.941 n64 +LUT4 --- 0.493 B to Z i1448_4_lut +Route 1 e 0.941 nUFMCS_N_199 + -------- + 8.159 (29.6% logic, 70.4% route), 5 logic levels. + + +Error: The following path violates requirements by 3.319ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK FS_610__i16 (from RCLK_c +) + Destination: FD1P3AY D nUFMCS_415 (to RCLK_c +) + + Delay: 8.159ns (29.6% logic, 70.4% route), 5 logic levels. + + Constraint Details: + + 8.159ns data_path FS_610__i16 to nUFMCS_415 violates + 5.000ns delay constraint less + 0.160ns L_S requirement (totaling 4.840ns) by 3.319ns + + Path Details: FS_610__i16 to nUFMCS_415 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.444 CK to Q FS_610__i16 (from RCLK_c) +Route 3 e 1.315 FS[16] +LUT4 --- 0.493 D to Z i3_4_lut_adj_7 +Route 5 e 1.405 n10 +LUT4 --- 0.493 C to Z i1_2_lut_rep_19_3_lut +Route 2 e 1.141 n2368 +LUT4 --- 0.493 B to Z i1_2_lut_4_lut +Route 1 e 0.941 n64 +LUT4 --- 0.493 B to Z i1448_4_lut +Route 1 e 0.941 nUFMCS_N_199 + -------- + 8.159 (29.6% logic, 70.4% route), 5 logic levels. + +Warning: 8.319 ns is the maximum delay for this constraint. + + +Timing Report Summary +-------------- +-------------------------------------------------------------------------------- +Constraint | Constraint| Actual|Levels +-------------------------------------------------------------------------------- + | | | +create_clock -period 5.000000 -name | | | +clk3 [get_nets nCCAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk2 [get_nets nCRAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk1 [get_nets PHI2_c] | 5.000 ns| 19.836 ns| 6 * + | | | +create_clock -period 5.000000 -name | | | +clk0 [get_nets RCLK_c] | 5.000 ns| 8.319 ns| 5 * + | | | +-------------------------------------------------------------------------------- + + +2 constraints not met. + +-------------------------------------------------------------------------------- +Critical Nets | Loads| Errors| % of total +-------------------------------------------------------------------------------- +n26 | 8| 84| 27.54% + | | | +n1997 | 1| 36| 11.80% + | | | +n1996 | 1| 35| 11.48% + | | | +n1995 | 1| 33| 10.82% + | | | +n10 | 5| 32| 10.49% + | | | +n1998 | 1| 32| 10.49% + | | | +-------------------------------------------------------------------------------- + + +Timing summary: +--------------- + +Timing errors: 305 Score: 1313492 + +Constraints cover 621 paths, 182 nets, and 471 connections (64.2% coverage) + + +Peak memory: 56156160 bytes, TRCE: 2355200 bytes, DLYMAN: 0 bytes +CPU_TIME_REPORT: 0 secs diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_lse_lsetwr.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_lse_lsetwr.html new file mode 100644 index 0000000..22e783c --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_lse_lsetwr.html @@ -0,0 +1,362 @@ + +Lattice Synthesis Timing Report + + +
    Lattice Synthesis Timing Report
+--------------------------------------------------------------------------------
+Lattice Synthesis Timing Report, Version  
+Tue Aug 15 05:03:23 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design:     RAM2GS
+Constraint file:  
+Report level:    verbose report, limited to 3 items per constraint
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c]
+            122 items scored, 119 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 7.418ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i1  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdEnable_405  (to PHI2_c -)
+
+   Delay:                   9.633ns  (30.2% logic, 69.8% route), 6 logic levels.
+
+ Constraint Details:
+
+      9.633ns data_path Bank_i1 to CmdEnable_405 violates
+      2.500ns delay constraint less
+      0.285ns LCE_S requirement (totaling 2.215ns) by 7.418ns
+
+ Path Details: Bank_i1 to CmdEnable_405
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              Bank_i1 (from PHI2_c)
+Route         1   e 0.941                                  Bank[1]
+LUT4        ---     0.493              D to Z              i8_4_lut
+Route         2   e 1.141                                  n22
+LUT4        ---     0.493              B to Z              i11_3_lut_rep_20
+Route         7   e 1.502                                  n2369
+LUT4        ---     0.493              A to Z              i1_2_lut_rep_13_3_lut
+Route         1   e 0.941                                  n2362
+LUT4        ---     0.493              D to Z              i1_4_lut_adj_13
+Route         3   e 1.258                                  C1Submitted_N_237
+LUT4        ---     0.493              C to Z              i34_4_lut
+Route         1   e 0.941                                  PHI2_N_120_enable_1
+                  --------
+                    9.633  (30.2% logic, 69.8% route), 6 logic levels.
+
+
+Error:  The following path violates requirements by 7.418ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i4  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdEnable_405  (to PHI2_c -)
+
+   Delay:                   9.633ns  (30.2% logic, 69.8% route), 6 logic levels.
+
+ Constraint Details:
+
+      9.633ns data_path Bank_i4 to CmdEnable_405 violates
+      2.500ns delay constraint less
+      0.285ns LCE_S requirement (totaling 2.215ns) by 7.418ns
+
+ Path Details: Bank_i4 to CmdEnable_405
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              Bank_i4 (from PHI2_c)
+Route         1   e 0.941                                  Bank[4]
+LUT4        ---     0.493              C to Z              i8_4_lut
+Route         2   e 1.141                                  n22
+LUT4        ---     0.493              B to Z              i11_3_lut_rep_20
+Route         7   e 1.502                                  n2369
+LUT4        ---     0.493              A to Z              i1_2_lut_rep_13_3_lut
+Route         1   e 0.941                                  n2362
+LUT4        ---     0.493              D to Z              i1_4_lut_adj_13
+Route         3   e 1.258                                  C1Submitted_N_237
+LUT4        ---     0.493              C to Z              i34_4_lut
+Route         1   e 0.941                                  PHI2_N_120_enable_1
+                  --------
+                    9.633  (30.2% logic, 69.8% route), 6 logic levels.
+
+
+Error:  The following path violates requirements by 7.256ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i3  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdEnable_405  (to PHI2_c -)
+
+   Delay:                   9.471ns  (30.7% logic, 69.3% route), 6 logic levels.
+
+ Constraint Details:
+
+      9.471ns data_path Bank_i3 to CmdEnable_405 violates
+      2.500ns delay constraint less
+      0.285ns LCE_S requirement (totaling 2.215ns) by 7.256ns
+
+ Path Details: Bank_i3 to CmdEnable_405
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              Bank_i3 (from PHI2_c)
+Route         1   e 0.941                                  Bank[3]
+LUT4        ---     0.493              B to Z              i1989_2_lut
+Route         1   e 0.941                                  n2287
+LUT4        ---     0.493              C to Z              i12_4_lut
+Route         8   e 1.540                                  n26
+LUT4        ---     0.493              B to Z              i1_2_lut_rep_13_3_lut
+Route         1   e 0.941                                  n2362
+LUT4        ---     0.493              D to Z              i1_4_lut_adj_13
+Route         3   e 1.258                                  C1Submitted_N_237
+LUT4        ---     0.493              C to Z              i34_4_lut
+Route         1   e 0.941                                  PHI2_N_120_enable_1
+                  --------
+                    9.471  (30.7% logic, 69.3% route), 6 logic levels.
+
+Warning: 9.918 ns is the maximum delay for this constraint.
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
+            498 items scored, 186 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 3.319ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_610__i13  (from RCLK_c +)
+   Destination:    FD1P3AY    D              nUFMCS_415  (to RCLK_c +)
+
+   Delay:                   8.159ns  (29.6% logic, 70.4% route), 5 logic levels.
+
+ Constraint Details:
+
+      8.159ns data_path FS_610__i13 to nUFMCS_415 violates
+      5.000ns delay constraint less
+      0.160ns L_S requirement (totaling 4.840ns) by 3.319ns
+
+ Path Details: FS_610__i13 to nUFMCS_415
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              FS_610__i13 (from RCLK_c)
+Route         3   e 1.315                                  FS[13]
+LUT4        ---     0.493              B to Z              i3_4_lut_adj_7
+Route         5   e 1.405                                  n10
+LUT4        ---     0.493              C to Z              i1_2_lut_rep_19_3_lut
+Route         2   e 1.141                                  n2368
+LUT4        ---     0.493              B to Z              i1_2_lut_4_lut
+Route         1   e 0.941                                  n64
+LUT4        ---     0.493              B to Z              i1448_4_lut
+Route         1   e 0.941                                  nUFMCS_N_199
+                  --------
+                    8.159  (29.6% logic, 70.4% route), 5 logic levels.
+
+
+Error:  The following path violates requirements by 3.319ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_610__i15  (from RCLK_c +)
+   Destination:    FD1P3AY    D              nUFMCS_415  (to RCLK_c +)
+
+   Delay:                   8.159ns  (29.6% logic, 70.4% route), 5 logic levels.
+
+ Constraint Details:
+
+      8.159ns data_path FS_610__i15 to nUFMCS_415 violates
+      5.000ns delay constraint less
+      0.160ns L_S requirement (totaling 4.840ns) by 3.319ns
+
+ Path Details: FS_610__i15 to nUFMCS_415
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              FS_610__i15 (from RCLK_c)
+Route         3   e 1.315                                  FS[15]
+LUT4        ---     0.493              C to Z              i3_4_lut_adj_7
+Route         5   e 1.405                                  n10
+LUT4        ---     0.493              C to Z              i1_2_lut_rep_19_3_lut
+Route         2   e 1.141                                  n2368
+LUT4        ---     0.493              B to Z              i1_2_lut_4_lut
+Route         1   e 0.941                                  n64
+LUT4        ---     0.493              B to Z              i1448_4_lut
+Route         1   e 0.941                                  nUFMCS_N_199
+                  --------
+                    8.159  (29.6% logic, 70.4% route), 5 logic levels.
+
+
+Error:  The following path violates requirements by 3.319ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_610__i16  (from RCLK_c +)
+   Destination:    FD1P3AY    D              nUFMCS_415  (to RCLK_c +)
+
+   Delay:                   8.159ns  (29.6% logic, 70.4% route), 5 logic levels.
+
+ Constraint Details:
+
+      8.159ns data_path FS_610__i16 to nUFMCS_415 violates
+      5.000ns delay constraint less
+      0.160ns L_S requirement (totaling 4.840ns) by 3.319ns
+
+ Path Details: FS_610__i16 to nUFMCS_415
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              FS_610__i16 (from RCLK_c)
+Route         3   e 1.315                                  FS[16]
+LUT4        ---     0.493              D to Z              i3_4_lut_adj_7
+Route         5   e 1.405                                  n10
+LUT4        ---     0.493              C to Z              i1_2_lut_rep_19_3_lut
+Route         2   e 1.141                                  n2368
+LUT4        ---     0.493              B to Z              i1_2_lut_4_lut
+Route         1   e 0.941                                  n64
+LUT4        ---     0.493              B to Z              i1448_4_lut
+Route         1   e 0.941                                  nUFMCS_N_199
+                  --------
+                    8.159  (29.6% logic, 70.4% route), 5 logic levels.
+
+Warning: 8.319 ns is the maximum delay for this constraint.
+
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets PHI2_c]                  |     5.000 ns|    19.836 ns|     6 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |     5.000 ns|     8.319 ns|     5 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+--------------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+--------------------------------------------------------------------------------
+n26                                     |       8|      84|     27.54%
+                                        |        |        |
+n1997                                   |       1|      36|     11.80%
+                                        |        |        |
+n1996                                   |       1|      35|     11.48%
+                                        |        |        |
+n1995                                   |       1|      33|     10.82%
+                                        |        |        |
+n10                                     |       5|      32|     10.49%
+                                        |        |        |
+n1998                                   |       1|      32|     10.49%
+                                        |        |        |
+--------------------------------------------------------------------------------
+
+
+Timing summary:
+---------------
+
+Timing errors: 305  Score: 1313492
+
+Constraints cover  621 paths, 182 nets, and 471 connections (64.2% coverage)
+
+
+Peak memory: 56156160 bytes, TRCE: 2355200 bytes, DLYMAN: 0 bytes
+CPU_TIME_REPORT: 0 secs 
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_prim.v b/CPLD/LCMXO2-640HC/impl1/RAM2GS_prim.v new file mode 100644 index 0000000..c5879ca --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_prim.v @@ -0,0 +1,802 @@ +// Verilog netlist produced by program LSE : version Diamond (64-bit) 3.12.1.454 +// Netlist written on Tue Aug 15 05:03:23 2023 +// +// Verilog Description of module RAM2GS +// + +module RAM2GS (PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, + LED, RBA, RA, RD, nRCS, RCLK, RCKE, nRWE, nRRAS, + nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI, UFMSDO) /* synthesis syn_module_defined=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1[8:14]) + input PHI2; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) + input [9:0]MAin; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + input [1:0]CROW; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18]) + input [7:0]Din; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + output [7:0]Dout; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + input nCCAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) + input nCRAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + input nFWE; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(36[8:12]) + output LED; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(22[9:12]) + output [1:0]RBA; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22]) + output [11:0]RA; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + inout [7:0]RD; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + output nRCS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[13:17]) + input RCLK; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12]) + output RCKE; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(45[13:17]) + output nRWE; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[45:49]) + output nRRAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[23:28]) + output nRCAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[34:39]) + output RDQMH; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[16:21]) + output RDQML; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[9:14]) + output nUFMCS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(63[13:19]) + output UFMCLK; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(64[13:19]) + output UFMSDI; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(65[13:19]) + input UFMSDO; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(66[8:14]) + + wire PHI2_c /* synthesis is_clock=1, SET_AS_NETWORK=PHI2_c */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) + wire nCCAS_c /* synthesis is_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) + wire nCRAS_c /* synthesis is_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + wire RCLK_c /* synthesis SET_AS_NETWORK=RCLK_c, is_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12]) + wire nCCAS_N_3 /* synthesis is_inv_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + wire PHI2_N_120 /* synthesis is_inv_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(38[6:13]) + wire nCRAS_c__inv /* synthesis is_inv_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + + wire GND_net, VCC_net, PHI2r, PHI2r2, PHI2r3, RASr, RASr2, + RASr3, CASr, CASr2, CASr3, FWEr, CBR, LEDEN, LED_c, + Din_c_7, Din_c_6, Din_c_5, Din_c_4, Din_c_3, Din_c_2, Din_c_1, + Din_c_0; + wire [7:0]Bank; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(31[12:16]) + + wire CROW_c_1, CROW_c_0, MAin_c_9, MAin_c_8, MAin_c_7, MAin_c_6, + MAin_c_5, MAin_c_4, MAin_c_3, MAin_c_2, MAin_c_1, MAin_c_0, + nFWE_c, n8MEGEN, XOR8MEG, RCKEEN, RCKE_c, nRCS_c, nRRAS_c, + nRCAS_c, nRWE_c, RBA_c_1, RBA_c_0, nRowColSel, RA_c, RA_0; + wire [9:0]RowA; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(51[12:16]) + + wire RA_1_9, RA_1_8, RA_1_7, RA_1_6, RA_1_5, RA_1_4, RA_1_3, + RA_1_2, RA_1_1, RA_1_0, RDQML_c, RDQMH_c; + wire [7:0]WRD; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(59[12:15]) + + wire nUFMCS_c, UFMCLK_c, UFMSDI_c, UFMSDO_c, C1Submitted, ADSubmitted, + CmdEnable, CmdSubmitted, Cmdn8MEGEN, CmdUFMCLK, CmdUFMSDI, + CmdUFMCS, InitReady, Ready, n10; + wire [17:0]FS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(86[13:15]) + + wire RA11_N_184, PHI2_N_120_enable_8, n2036, n1765, n1893, n7, + n917, n4, n2277, RCKE_N_132, nRowColSel_N_35, nRWE_N_182, + nRowColSel_N_34, nRowColSel_N_33, nRowColSel_N_32, nRCS_N_146, + n15, n2260, nRCS_N_142, n2362, nRCS_N_141, nRCAS_N_166, + nRWE_N_178, n2180, nRCS_N_139, nRCAS_N_165, nRWE_N_177, nRWE_N_176, + n14, n6, n13, n1993, n2254, Ready_N_296, RCLK_c_enable_28, + nRCS_N_137, Ready_N_292, nRCS_N_136, nRRAS_N_156, nRCAS_N_161, + nRWE_N_171, n2220, RCKEEN_N_121, n15_adj_1, n2371, ADSubmitted_N_246, + CmdEnable_N_248, C1Submitted_N_237, PHI2_N_120_enable_3, n2174, + n6_adj_2, Cmdn8MEGEN_N_264, XOR8MEG_N_110, n2204, n1996, n6_adj_3, + RCLK_c_enable_10, n2191, n2208, n22, n8MEGEN_N_91, UFMCLK_N_224, + UFMSDI_N_231, n26, nUFMCS_N_199, n2055, PHI2_N_120_enable_2, + n1999, n2287, n726, n727, n728, n729, n730, n732, n733, + n734, n735, n736, n737, n738, n2267, n1398, n2183, n1995, + PHI2_N_120_enable_1, n1060, n1408, n2228, n2447, n1406, + PHI2_N_120_enable_6, n2225, n827, n2370, n1277, n15_adj_4, + Dout_c, n78, n79, n80, n81, n82, n83, n84, n85, n86, + n87, n88, n89, n90, n91, n92, n93, n94, n95, n2382, + RCLK_c_enable_15, n9, n2369, n7_adj_5, n13_adj_6, n2381, + n2210, n2380, n2227, n2368, PHI2_N_120_enable_7, n12, n1994, + RCLK_c_enable_27, n2367, n1407, n2379, n2378, n2377, n2366, + n2365, n2376, n1998, n2375, n4_adj_7, n2374, RCLK_c_enable_6, + Dout_0, Dout_1, n984, Dout_2, n8, Dout_3, Dout_4, n1314, + Dout_5, Dout_6, RCLK_c_enable_16, n2363, n13_adj_8, n2000, + n2373, RCLK_c_enable_5, n1992, n1997, n2372, n64; + + VHI i2 (.Z(VCC_net)); + INV i2046 (.A(PHI2_c), .Z(PHI2_N_120)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) + FD1S3AX PHI2r2_377 (.D(PHI2r), .CK(RCLK_c), .Q(PHI2r2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam PHI2r2_377.GSR = "ENABLED"; + LUT4 nRCAS_I_43_4_lut (.A(nRCS_N_142), .B(RASr2), .C(nRowColSel_N_35), + .D(CBR), .Z(nRCAS_N_166)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B ((D)+!C)+!B !(C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(186[13] 231[7]) + defparam nRCAS_I_43_4_lut.init = 16'h3afa; + LUT4 nRCAS_I_0_452_3_lut_4_lut (.A(n2371), .B(nRCAS_N_165), .C(Ready), + .D(nRCAS_N_166), .Z(nRCAS_N_161)) /* synthesis lut_function=(A ((D)+!C)+!A (B ((D)+!C)+!B (C (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6]) + defparam nRCAS_I_0_452_3_lut_4_lut.init = 16'hfe0e; + LUT4 nRWE_I_0_455_4_lut (.A(n1765), .B(nRWE_N_178), .C(Ready), .D(n2371), + .Z(nRWE_N_171)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B+!(C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6]) + defparam nRWE_I_0_455_4_lut.init = 16'hcfc5; + FD1S3AX PHI2r3_378 (.D(PHI2r2), .CK(RCLK_c), .Q(PHI2r3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam PHI2r3_378.GSR = "ENABLED"; + FD1S3AX RASr_379 (.D(nCRAS_c__inv), .CK(RCLK_c), .Q(RASr)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam RASr_379.GSR = "ENABLED"; + FD1S3AX RASr2_380 (.D(RASr), .CK(RCLK_c), .Q(RASr2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam RASr2_380.GSR = "ENABLED"; + FD1S3AX RASr3_381 (.D(RASr2), .CK(RCLK_c), .Q(RASr3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam RASr3_381.GSR = "ENABLED"; + FD1S3AX CASr_382 (.D(nCCAS_N_3), .CK(RCLK_c), .Q(CASr)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam CASr_382.GSR = "ENABLED"; + FD1S3AX CASr2_383 (.D(CASr), .CK(RCLK_c), .Q(CASr2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam CASr2_383.GSR = "ENABLED"; + FD1S3AX CASr3_384 (.D(CASr2), .CK(RCLK_c), .Q(CASr3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam CASr3_384.GSR = "ENABLED"; + FD1S3IX RA11_385 (.D(RA11_N_184), .CK(PHI2_c), .CD(n2380), .Q(RA_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam RA11_385.GSR = "ENABLED"; + CCU2D FS_610_add_4_15 (.A0(FS[13]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[14]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1998), + .COUT(n1999), .S0(n82), .S1(n81)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_15.INIT0 = 16'hfaaa; + defparam FS_610_add_4_15.INIT1 = 16'hfaaa; + defparam FS_610_add_4_15.INJECT1_0 = "NO"; + defparam FS_610_add_4_15.INJECT1_1 = "NO"; + FD1S3IX RowA_i0 (.D(MAin_c_0), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i0.GSR = "ENABLED"; + FD1S3AX WRD_i0 (.D(Din_c_0), .CK(nCCAS_N_3), .Q(WRD[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i0.GSR = "ENABLED"; + FD1S3AX FWEr_389 (.D(n2373), .CK(nCRAS_c__inv), .Q(FWEr)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam FWEr_389.GSR = "ENABLED"; + FD1S3AX CBR_390 (.D(nCCAS_N_3), .CK(nCRAS_c__inv), .Q(CBR)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam CBR_390.GSR = "ENABLED"; + FD1S3AX RCKE_395 (.D(RCKE_N_132), .CK(RCLK_c), .Q(RCKE_c)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(141[9] 144[5]) + defparam RCKE_395.GSR = "ENABLED"; + FD1P3AY nRCS_396 (.D(nRCS_N_136), .SP(RCLK_c_enable_6), .CK(RCLK_c), + .Q(nRCS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRCS_396.GSR = "ENABLED"; + LUT4 i1477_2_lut (.A(nRWE_N_177), .B(nRCAS_N_165), .Z(n1765)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1477_2_lut.init = 16'heeee; + FD1P3AX nRowColSel_402 (.D(n917), .SP(RCLK_c_enable_5), .CK(RCLK_c), + .Q(nRowColSel)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRowColSel_402.GSR = "ENABLED"; + CCU2D FS_610_add_4_13 (.A0(FS[11]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[12]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1997), + .COUT(n1998), .S0(n84), .S1(n83)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_13.INIT0 = 16'hfaaa; + defparam FS_610_add_4_13.INIT1 = 16'hfaaa; + defparam FS_610_add_4_13.INJECT1_0 = "NO"; + defparam FS_610_add_4_13.INJECT1_1 = "NO"; + LUT4 i2_2_lut (.A(InitReady), .B(Ready_N_296), .Z(n6_adj_3)) /* synthesis lut_function=(A (B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam i2_2_lut.init = 16'h8888; + FD1P3AX CmdEnable_405 (.D(CmdEnable_N_248), .SP(PHI2_N_120_enable_1), + .CK(PHI2_N_120), .Q(CmdEnable)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdEnable_405.GSR = "ENABLED"; + LUT4 i4_4_lut (.A(MAin_c_1), .B(MAin_c_0), .C(CmdEnable), .D(n6_adj_2), + .Z(n2204)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ; + defparam i4_4_lut.init = 16'h4000; + FD1P3IX ADSubmitted_407 (.D(ADSubmitted_N_246), .SP(PHI2_N_120_enable_2), + .CD(C1Submitted_N_237), .CK(PHI2_N_120), .Q(ADSubmitted)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam ADSubmitted_407.GSR = "ENABLED"; + LUT4 i26_4_lut (.A(n2183), .B(n2191), .C(Din_c_5), .D(n2254), .Z(n15_adj_1)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B (C))) */ ; + defparam i26_4_lut.init = 16'hc0ca; + LUT4 i1_2_lut_3_lut_4_lut (.A(n2369), .B(n26), .C(n2204), .D(nFWE_c), + .Z(n2220)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ; + defparam i1_2_lut_3_lut_4_lut.init = 16'h0020; + FD1P3AY nRRAS_397 (.D(nRRAS_N_156), .SP(RCLK_c_enable_6), .CK(RCLK_c), + .Q(nRRAS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRRAS_397.GSR = "ENABLED"; + LUT4 nRWE_I_50_1_lut (.A(nRWE_N_177), .Z(nRWE_N_176)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(255[14] 262[8]) + defparam nRWE_I_50_1_lut.init = 16'h5555; + BB Dout_pad_7__713 (.I(WRD[7]), .T(n984), .B(RD[7]), .O(Dout_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + FD1P3AY nRCAS_398 (.D(nRCAS_N_161), .SP(RCLK_c_enable_6), .CK(RCLK_c), + .Q(nRCAS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRCAS_398.GSR = "ENABLED"; + FD1P3AY nRWE_399 (.D(nRWE_N_171), .SP(RCLK_c_enable_5), .CK(RCLK_c), + .Q(nRWE_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRWE_399.GSR = "ENABLED"; + FD1S3JX RA10_400 (.D(n2036), .CK(RCLK_c), .PD(nRWE_N_176), .Q(RA_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam RA10_400.GSR = "ENABLED"; + FD1P3AX RCKEEN_401 (.D(RCKEEN_N_121), .SP(RCLK_c_enable_6), .CK(RCLK_c), + .Q(RCKEEN)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam RCKEEN_401.GSR = "ENABLED"; + FD1S3AX FS_610__i0 (.D(n95), .CK(RCLK_c), .Q(FS[0])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i0.GSR = "ENABLED"; + FD1S3IX RBA__i1 (.D(CROW_c_0), .CK(nCRAS_c__inv), .CD(n2380), .Q(RBA_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RBA__i1.GSR = "ENABLED"; + LUT4 i1_4_lut (.A(Din_c_5), .B(n2220), .C(Din_c_4), .D(Din_c_3), + .Z(PHI2_N_120_enable_6)) /* synthesis lut_function=(A (B (C (D)))+!A (B)) */ ; + defparam i1_4_lut.init = 16'hc444; + LUT4 i29_3_lut (.A(InitReady), .B(n15_adj_4), .C(Ready), .Z(RCKEEN_N_121)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6]) + defparam i29_3_lut.init = 16'hcaca; + LUT4 Cmdn8MEGEN_I_93_4_lut (.A(Din_c_0), .B(n8MEGEN), .C(Din_c_4), + .D(n1314), .Z(Cmdn8MEGEN_N_264)) /* synthesis lut_function=(A (B ((D)+!C))+!A (B+!((D)+!C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(321[13] 335[7]) + defparam Cmdn8MEGEN_I_93_4_lut.init = 16'hcc5c; + LUT4 i1956_2_lut (.A(MAin_c_0), .B(Din_c_2), .Z(n2254)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1956_2_lut.init = 16'heeee; + FD1P3AX IS_FSM__i0 (.D(Ready_N_296), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(nRCS_N_139)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i0.GSR = "ENABLED"; + CCU2D FS_610_add_4_9 (.A0(FS[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1995), + .COUT(n1996), .S0(n88), .S1(n87)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_9.INIT0 = 16'hfaaa; + defparam FS_610_add_4_9.INIT1 = 16'hfaaa; + defparam FS_610_add_4_9.INJECT1_0 = "NO"; + defparam FS_610_add_4_9.INJECT1_1 = "NO"; + FD1S3JX C1Submitted_406 (.D(n1398), .CK(PHI2_N_120), .PD(C1Submitted_N_237), + .Q(C1Submitted)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam C1Submitted_406.GSR = "ENABLED"; + FD1P3AY nUFMCS_415 (.D(nUFMCS_N_199), .SP(RCLK_c_enable_10), .CK(RCLK_c), + .Q(nUFMCS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam nUFMCS_415.GSR = "ENABLED"; + LUT4 i2_4_lut (.A(n2220), .B(Din_c_4), .C(Din_c_3), .D(Din_c_5), + .Z(PHI2_N_120_enable_7)) /* synthesis lut_function=(A (B (C+!(D)))) */ ; + defparam i2_4_lut.init = 16'h8088; + FD1S3AX S_FSM_i1 (.D(n2374), .CK(RCLK_c), .Q(nRowColSel_N_35)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam S_FSM_i1.GSR = "ENABLED"; + CCU2D FS_610_add_4_7 (.A0(FS[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1994), + .COUT(n1995), .S0(n90), .S1(n89)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_7.INIT0 = 16'hfaaa; + defparam FS_610_add_4_7.INIT1 = 16'hfaaa; + defparam FS_610_add_4_7.INJECT1_0 = "NO"; + defparam FS_610_add_4_7.INJECT1_1 = "NO"; + LUT4 i1_2_lut (.A(Din_c_6), .B(Din_c_3), .Z(n2183)) /* synthesis lut_function=(!((B)+!A)) */ ; + defparam i1_2_lut.init = 16'h2222; + LUT4 i1_2_lut_rep_15_4_lut (.A(FS[10]), .B(FS[11]), .C(n2368), .D(InitReady), + .Z(RCLK_c_enable_16)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ; + defparam i1_2_lut_rep_15_4_lut.init = 16'h0008; + CCU2D FS_610_add_4_3 (.A0(FS[1]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1992), + .COUT(n1993), .S0(n94), .S1(n93)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_3.INIT0 = 16'hfaaa; + defparam FS_610_add_4_3.INIT1 = 16'hfaaa; + defparam FS_610_add_4_3.INJECT1_0 = "NO"; + defparam FS_610_add_4_3.INJECT1_1 = "NO"; + LUT4 RA11_I_54_3_lut (.A(Din_c_6), .B(XOR8MEG), .C(n8MEGEN), .Z(RA11_N_184)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A (B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(99[22:51]) + defparam RA11_I_54_3_lut.init = 16'hc6c6; + LUT4 i9_2_lut_3_lut (.A(FWEr), .B(CBR), .C(RASr2), .Z(n9)) /* synthesis lut_function=(!(A (C)+!A (B (C)))) */ ; + defparam i9_2_lut_3_lut.init = 16'h1f1f; + LUT4 i1491_2_lut_rep_30 (.A(RCKE_c), .B(RASr2), .Z(n2379)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1491_2_lut_rep_30.init = 16'heeee; + LUT4 nRCS_I_31_3_lut_4_lut (.A(RCKE_c), .B(RASr2), .C(nRowColSel_N_35), + .D(nRCS_N_142), .Z(nRCS_N_141)) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C+(D))))) */ ; + defparam nRCS_I_31_3_lut_4_lut.init = 16'h1f10; + FD1P3IX UFMCLK_416 (.D(UFMCLK_N_224), .SP(RCLK_c_enable_10), .CD(n2366), + .CK(RCLK_c), .Q(UFMCLK_c)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam UFMCLK_416.GSR = "ENABLED"; + LUT4 MAin_9__I_0_427_i10_3_lut (.A(RowA[9]), .B(MAin_c_9), .C(nRowColSel), + .Z(RA_1_9)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i10_3_lut.init = 16'hcaca; + LUT4 i3_4_lut (.A(Din_c_2), .B(Din_c_3), .C(Din_c_6), .D(MAin_c_0), + .Z(n2191)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ; + defparam i3_4_lut.init = 16'h0800; + LUT4 i1_2_lut_rep_21_3_lut (.A(Din_c_7), .B(Din_c_1), .C(Din_c_0), + .Z(n2370)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) + defparam i1_2_lut_rep_21_3_lut.init = 16'h2020; + LUT4 MAin_9__I_0_427_i9_3_lut (.A(RowA[8]), .B(MAin_c_8), .C(nRowColSel), + .Z(RA_1_8)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i9_3_lut.init = 16'hcaca; + LUT4 MAin_9__I_0_427_i8_3_lut (.A(RowA[7]), .B(MAin_c_7), .C(nRowColSel), + .Z(RA_1_7)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i8_3_lut.init = 16'hcaca; + LUT4 MAin_9__I_0_427_i7_3_lut (.A(RowA[6]), .B(MAin_c_6), .C(nRowColSel), + .Z(RA_1_6)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i7_3_lut.init = 16'hcaca; + LUT4 MAin_9__I_0_427_i6_3_lut (.A(RowA[5]), .B(MAin_c_5), .C(nRowColSel), + .Z(RA_1_5)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i6_3_lut.init = 16'hcaca; + CCU2D FS_610_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .COUT(n1992), + .S1(n95)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_1.INIT0 = 16'hF000; + defparam FS_610_add_4_1.INIT1 = 16'h0555; + defparam FS_610_add_4_1.INJECT1_0 = "NO"; + defparam FS_610_add_4_1.INJECT1_1 = "NO"; + LUT4 MAin_9__I_0_427_i5_3_lut (.A(RowA[4]), .B(MAin_c_4), .C(nRowColSel), + .Z(RA_1_4)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i5_3_lut.init = 16'hcaca; + FD1S3AX PHI2r_376 (.D(PHI2_c), .CK(RCLK_c), .Q(PHI2r)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam PHI2r_376.GSR = "ENABLED"; + LUT4 i1962_4_lut (.A(Din_c_4), .B(Din_c_1), .C(n1314), .D(LEDEN), + .Z(n2260)) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ; + defparam i1962_4_lut.init = 16'hfefa; + LUT4 i1423_2_lut (.A(RCKE_c), .B(RASr2), .Z(nRWE_N_182)) /* synthesis lut_function=((B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(168[14] 184[8]) + defparam i1423_2_lut.init = 16'hdddd; + LUT4 MAin_9__I_0_427_i4_3_lut (.A(RowA[3]), .B(MAin_c_3), .C(nRowColSel), + .Z(RA_1_3)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i4_3_lut.init = 16'hcaca; + FD1S3IX S_FSM_i3 (.D(n1406), .CK(RCLK_c), .CD(n1407), .Q(nRowColSel_N_33)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam S_FSM_i3.GSR = "ENABLED"; + FD1S3IX S_FSM_i4 (.D(n827), .CK(RCLK_c), .CD(n2374), .Q(nRowColSel_N_32)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam S_FSM_i4.GSR = "ENABLED"; + LUT4 i1_2_lut_3_lut_4_lut_adj_1 (.A(Din_c_7), .B(Din_c_1), .C(Din_c_4), + .D(Din_c_0), .Z(n2208)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) + defparam i1_2_lut_3_lut_4_lut_adj_1.init = 16'h0200; + LUT4 MAin_c_0_bdd_4_lut (.A(n2369), .B(n26), .C(nFWE_c), .D(MAin_c_1), + .Z(PHI2_N_120_enable_2)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ; + defparam MAin_c_0_bdd_4_lut.init = 16'h0200; + FD1P3IX UFMSDI_417 (.D(UFMSDI_N_231), .SP(RCLK_c_enable_10), .CD(n2366), + .CK(RCLK_c), .Q(UFMSDI_c)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam UFMSDI_417.GSR = "ENABLED"; + LUT4 MAin_9__I_0_427_i3_3_lut (.A(RowA[2]), .B(MAin_c_2), .C(nRowColSel), + .Z(RA_1_2)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i3_3_lut.init = 16'hcaca; + LUT4 MAin_9__I_0_427_i2_3_lut (.A(RowA[1]), .B(MAin_c_1), .C(nRowColSel), + .Z(RA_1_1)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i2_3_lut.init = 16'hcaca; + LUT4 i1448_4_lut (.A(n13_adj_6), .B(n64), .C(CmdUFMCS), .D(InitReady), + .Z(nUFMCS_N_199)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B (C+!(D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(345[12] 409[6]) + defparam i1448_4_lut.init = 16'h3fbb; + LUT4 i2_3_lut_rep_18_4_lut (.A(n10), .B(n2375), .C(FS[11]), .D(FS[10]), + .Z(n2367)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ; + defparam i2_3_lut_rep_18_4_lut.init = 16'h1000; + LUT4 i3_4_lut_adj_2 (.A(nRCS_N_139), .B(InitReady), .C(nRowColSel_N_35), + .D(RASr2), .Z(nRCS_N_137)) /* synthesis lut_function=(A+!(B (C (D)))) */ ; + defparam i3_4_lut_adj_2.init = 16'hbfff; + LUT4 MAin_9__I_0_427_i1_3_lut (.A(RowA[0]), .B(MAin_c_0), .C(nRowColSel), + .Z(RA_1_0)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i1_3_lut.init = 16'hcaca; + LUT4 i1416_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQMH_c)) /* synthesis lut_function=(A+!(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(58[17:46]) + defparam i1416_2_lut.init = 16'hbbbb; + LUT4 i2001_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQML_c)) /* synthesis lut_function=(!(A (B))) */ ; + defparam i2001_2_lut.init = 16'h7777; + LUT4 i2_3_lut_4_lut (.A(n2363), .B(MAin_c_1), .C(n2208), .D(n15_adj_1), + .Z(CmdEnable_N_248)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ; + defparam i2_3_lut_4_lut.init = 16'h4000; + LUT4 i2005_3_lut_rep_17_4_lut (.A(n10), .B(n2375), .C(InitReady), + .D(FS[11]), .Z(n2366)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ; + defparam i2005_3_lut_rep_17_4_lut.init = 16'h0001; + FD1S3AX Bank_i0 (.D(Din_c_0), .CK(PHI2_c), .Q(Bank[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i0.GSR = "ENABLED"; + LUT4 i1427_4_lut (.A(nRCS_N_146), .B(nRowColSel_N_34), .C(n2378), + .D(nRowColSel_N_33), .Z(nRCS_N_142)) /* synthesis lut_function=(A (B+(C (D)))+!A (B+(C+!(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(195[13] 231[7]) + defparam i1427_4_lut.init = 16'hfcdd; + LUT4 i3_3_lut_4_lut (.A(Din_c_7), .B(Din_c_1), .C(Din_c_6), .D(Din_c_4), + .Z(n8)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) + defparam i3_3_lut_4_lut.init = 16'h0002; + LUT4 i1_2_lut_adj_3 (.A(FS[10]), .B(n13_adj_6), .Z(RCLK_c_enable_28)) /* synthesis lut_function=(A (B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i1_2_lut_adj_3.init = 16'h8888; + LUT4 i1119_1_lut (.A(nRowColSel_N_35), .Z(n1408)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i1119_1_lut.init = 16'h5555; + LUT4 nRCS_N_146_bdd_4_lut (.A(nRCS_N_146), .B(n1060), .C(nRWE_N_182), + .D(nRowColSel_N_35), .Z(nRWE_N_178)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))+!A (C+!(D))) */ ; + defparam nRCS_N_146_bdd_4_lut.init = 16'hf0dd; + LUT4 i11_3_lut_rep_20 (.A(MAin_c_2), .B(n22), .C(MAin_c_5), .Z(n2369)) /* synthesis lut_function=(A (B (C))) */ ; + defparam i11_3_lut_rep_20.init = 16'h8080; + LUT4 i13_2_lut_rep_16_4_lut (.A(MAin_c_2), .B(n22), .C(MAin_c_5), + .D(n26), .Z(n2365)) /* synthesis lut_function=((((D)+!C)+!B)+!A) */ ; + defparam i13_2_lut_rep_16_4_lut.init = 16'hff7f; + GSR GSR_INST (.GSR(VCC_net)); + LUT4 i1_4_lut_adj_4 (.A(n2180), .B(n2225), .C(n8), .D(n2382), .Z(ADSubmitted_N_246)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) + defparam i1_4_lut_adj_4.init = 16'h2000; + LUT4 i6_4_lut (.A(FS[11]), .B(n12), .C(FS[14]), .D(FS[17]), .Z(n13_adj_6)) /* synthesis lut_function=(A (B (C (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i6_4_lut.init = 16'h8000; + LUT4 i8_4_lut (.A(MAin_c_7), .B(MAin_c_3), .C(Bank[4]), .D(Bank[1]), + .Z(n22)) /* synthesis lut_function=(A (B (C (D)))) */ ; + defparam i8_4_lut.init = 16'h8000; + LUT4 i1_2_lut_3_lut_4_lut_adj_5 (.A(n2369), .B(n26), .C(MAin_c_0), + .D(MAin_c_1), .Z(n2225)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ; + defparam i1_2_lut_3_lut_4_lut_adj_5.init = 16'hdfff; + LUT4 i5_4_lut (.A(FS[13]), .B(FS[12]), .C(FS[15]), .D(FS[16]), .Z(n12)) /* synthesis lut_function=(A (B (C (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i5_4_lut.init = 16'h8000; + LUT4 i12_4_lut (.A(Bank[2]), .B(n2277), .C(n2287), .D(Bank[5]), + .Z(n26)) /* synthesis lut_function=(A+!(B (C (D)))) */ ; + defparam i12_4_lut.init = 16'hbfff; + LUT4 i2_3_lut_4_lut_adj_6 (.A(n2369), .B(n26), .C(MAin_c_0), .D(MAin_c_1), + .Z(n1277)) /* synthesis lut_function=((B+((D)+!C))+!A) */ ; + defparam i2_3_lut_4_lut_adj_6.init = 16'hffdf; + LUT4 i637_1_lut_rep_31 (.A(Ready), .Z(n2380)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i637_1_lut_rep_31.init = 16'h5555; + LUT4 i1573_4_lut (.A(n2367), .B(n2377), .C(InitReady), .D(n4_adj_7), + .Z(RCLK_c_enable_15)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(83[6:15]) + defparam i1573_4_lut.init = 16'hcac0; + LUT4 i3_4_lut_adj_7 (.A(FS[17]), .B(FS[13]), .C(FS[15]), .D(FS[16]), + .Z(n10)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i3_4_lut_adj_7.init = 16'hfffe; + LUT4 i786_2_lut (.A(nRowColSel_N_33), .B(nRowColSel_N_34), .Z(n1060)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(195[13] 231[7]) + defparam i786_2_lut.init = 16'heeee; + LUT4 i1_4_lut_adj_8 (.A(FS[4]), .B(n15), .C(n13), .D(n14), .Z(n4_adj_7)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ; + defparam i1_4_lut_adj_8.init = 16'h0002; + LUT4 i2_2_lut_3_lut_4_lut (.A(nRCS_N_139), .B(n2381), .C(Ready), .D(nRCAS_N_165), + .Z(n2036)) /* synthesis lut_function=(A+((C+(D))+!B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam i2_2_lut_3_lut_4_lut.init = 16'hfffb; + LUT4 i2_3_lut_4_lut_4_lut (.A(Ready), .B(n1060), .C(nRowColSel_N_32), + .D(nRowColSel_N_35), .Z(RCLK_c_enable_5)) /* synthesis lut_function=((B+(C+(D)))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i2_3_lut_4_lut_4_lut.init = 16'hfffd; + CCU2D FS_610_add_4_11 (.A0(FS[9]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[10]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1996), + .COUT(n1997), .S0(n86), .S1(n85)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_11.INIT0 = 16'hfaaa; + defparam FS_610_add_4_11.INIT1 = 16'hfaaa; + defparam FS_610_add_4_11.INJECT1_0 = "NO"; + defparam FS_610_add_4_11.INJECT1_1 = "NO"; + LUT4 i1603_3_lut (.A(n1893), .B(CmdUFMCLK), .C(InitReady), .Z(UFMCLK_N_224)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(83[6:15]) + defparam i1603_3_lut.init = 16'hcaca; + LUT4 i1979_4_lut (.A(MAin_c_6), .B(MAin_c_4), .C(Bank[7]), .D(Bank[0]), + .Z(n2277)) /* synthesis lut_function=(A (B (C (D)))) */ ; + defparam i1979_4_lut.init = 16'h8000; + FD1P3AX IS_FSM__i15 (.D(n726), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(Ready_N_296)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i15.GSR = "ENABLED"; + LUT4 i771_2_lut_rep_23_2_lut (.A(Ready), .B(nRowColSel_N_35), .Z(n2372)) /* synthesis lut_function=((B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i771_2_lut_rep_23_2_lut.init = 16'hdddd; + LUT4 i6_4_lut_adj_9 (.A(FS[5]), .B(FS[7]), .C(FS[1]), .D(FS[2]), + .Z(n15)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; + defparam i6_4_lut_adj_9.init = 16'hfffe; + LUT4 i1970_4_lut (.A(FS[4]), .B(n13_adj_6), .C(n2267), .D(FS[1]), + .Z(n1893)) /* synthesis lut_function=(!(A (B (C)+!B !((D)+!C))+!A (B+!(C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(86[13:15]) + defparam i1970_4_lut.init = 16'h3a0a; + LUT4 i1_2_lut_2_lut (.A(Ready), .B(nRowColSel_N_34), .Z(n6)) /* synthesis lut_function=((B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i1_2_lut_2_lut.init = 16'hdddd; + PFUMX i30 (.BLUT(n13_adj_8), .ALUT(n9), .C0(nRowColSel_N_35), .Z(n15_adj_4)); + FD1P3AX IS_FSM__i14 (.D(n727), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n726)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i14.GSR = "ENABLED"; + FD1P3AX IS_FSM__i13 (.D(n728), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n727)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i13.GSR = "ENABLED"; + LUT4 i1989_2_lut (.A(Bank[6]), .B(Bank[3]), .Z(n2287)) /* synthesis lut_function=(A (B)) */ ; + defparam i1989_2_lut.init = 16'h8888; + LUT4 i2_3_lut_rep_32 (.A(RASr2), .B(InitReady), .C(nRowColSel_N_35), + .Z(n2381)) /* synthesis lut_function=(A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(233[8:20]) + defparam i2_3_lut_rep_32.init = 16'h8080; + LUT4 i1_2_lut_rep_22_4_lut (.A(RASr2), .B(InitReady), .C(nRowColSel_N_35), + .D(nRCS_N_139), .Z(n2371)) /* synthesis lut_function=((((D)+!C)+!B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(233[8:20]) + defparam i1_2_lut_rep_22_4_lut.init = 16'hff7f; + FD1P3AX IS_FSM__i12 (.D(n729), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n728)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i12.GSR = "ENABLED"; + FD1P3AX XOR8MEG_408 (.D(XOR8MEG_N_110), .SP(PHI2_N_120_enable_3), .CK(PHI2_N_120), + .Q(XOR8MEG)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam XOR8MEG_408.GSR = "ENABLED"; + FD1P3AX n8MEGEN_418 (.D(n8MEGEN_N_91), .SP(RCLK_c_enable_15), .CK(RCLK_c), + .Q(n8MEGEN)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam n8MEGEN_418.GSR = "ENABLED"; + CCU2D FS_610_add_4_19 (.A0(FS[17]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2000), + .S0(n78)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_19.INIT0 = 16'hfaaa; + defparam FS_610_add_4_19.INIT1 = 16'h0000; + defparam FS_610_add_4_19.INJECT1_0 = "NO"; + defparam FS_610_add_4_19.INJECT1_1 = "NO"; + FD1P3AX LEDEN_419 (.D(n2447), .SP(RCLK_c_enable_16), .CK(RCLK_c), + .Q(LEDEN)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam LEDEN_419.GSR = "ENABLED"; + FD1P3AX Ready_404 (.D(n2447), .SP(Ready_N_292), .CK(RCLK_c), .Q(Ready)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam Ready_404.GSR = "ENABLED"; + FD1P3AX CmdUFMCLK_413 (.D(Din_c_1), .SP(PHI2_N_120_enable_8), .CK(PHI2_N_120), + .Q(CmdUFMCLK)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdUFMCLK_413.GSR = "ENABLED"; + FD1P3AX CmdUFMSDI_414 (.D(Din_c_0), .SP(PHI2_N_120_enable_8), .CK(PHI2_N_120), + .Q(CmdUFMSDI)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdUFMSDI_414.GSR = "ENABLED"; + FD1P3AX Cmdn8MEGEN_410 (.D(Cmdn8MEGEN_N_264), .SP(PHI2_N_120_enable_6), + .CK(PHI2_N_120), .Q(Cmdn8MEGEN)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam Cmdn8MEGEN_410.GSR = "ENABLED"; + FD1P3AX CmdSubmitted_411 (.D(n2447), .SP(PHI2_N_120_enable_7), .CK(PHI2_N_120), + .Q(CmdSubmitted)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdSubmitted_411.GSR = "ENABLED"; + FD1P3AX CmdUFMCS_412 (.D(Din_c_2), .SP(PHI2_N_120_enable_8), .CK(PHI2_N_120), + .Q(CmdUFMCS)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdUFMCS_412.GSR = "ENABLED"; + FD1P3AX IS_FSM__i11 (.D(n730), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n729)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i11.GSR = "ENABLED"; + LUT4 i2008_2_lut_4_lut (.A(RASr2), .B(InitReady), .C(nRowColSel_N_35), + .D(Ready), .Z(RCLK_c_enable_27)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(233[8:20]) + defparam i2008_2_lut_4_lut.init = 16'h0080; + LUT4 i1404_4_lut (.A(RASr), .B(RCKEEN), .C(RASr2), .D(RASr3), .Z(RCKE_N_132)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B (C+(D))+!B !(C+!(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(15[12:17]) + defparam i1404_4_lut.init = 16'hcfc8; + LUT4 i1118_1_lut (.A(nRowColSel_N_34), .Z(n1407)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i1118_1_lut.init = 16'h5555; + FD1P3AX IS_FSM__i10 (.D(nRWE_N_177), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n730)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i10.GSR = "ENABLED"; + LUT4 i1_2_lut_adj_10 (.A(RASr2), .B(nRowColSel_N_32), .Z(n1406)) /* synthesis lut_function=(!((B)+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam i1_2_lut_adj_10.init = 16'h2222; + LUT4 i1439_2_lut (.A(nRowColSel_N_33), .B(nRowColSel_N_32), .Z(n827)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i1439_2_lut.init = 16'heeee; + FD1P3AX IS_FSM__i9 (.D(n732), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(nRWE_N_177)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i9.GSR = "ENABLED"; + LUT4 i1432_4_lut (.A(FWEr), .B(n2372), .C(n1060), .D(n2376), .Z(n917)) /* synthesis lut_function=(!(A (B+!(C+!(D)))+!A (B+!(C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i1432_4_lut.init = 16'h3032; + LUT4 i1_2_lut_rep_33 (.A(Din_c_0), .B(Din_c_2), .Z(n2382)) /* synthesis lut_function=(A (B)) */ ; + defparam i1_2_lut_rep_33.init = 16'h8888; + LUT4 i1_4_lut_4_lut (.A(CBR), .B(n2227), .C(FWEr), .D(nRowColSel_N_34), + .Z(n13_adj_8)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(23[27:31]) + defparam i1_4_lut_4_lut.init = 16'h5540; + LUT4 i4_2_lut (.A(FS[8]), .B(FS[0]), .Z(n13)) /* synthesis lut_function=(A+(B)) */ ; + defparam i4_2_lut.init = 16'heeee; + LUT4 i1589_4_lut (.A(n2174), .B(CmdUFMSDI), .C(InitReady), .D(n4), + .Z(UFMSDI_N_231)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(83[6:15]) + defparam i1589_4_lut.init = 16'hcac0; + LUT4 i2_1_lut_rep_24 (.A(nFWE_c), .Z(n2373)) /* synthesis lut_function=(!(A)) */ ; + defparam i2_1_lut_rep_24.init = 16'h5555; + LUT4 i2_3_lut_4_lut_adj_11 (.A(Din_c_0), .B(Din_c_2), .C(n2260), .D(Din_c_3), + .Z(XOR8MEG_N_110)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ; + defparam i2_3_lut_4_lut_adj_11.init = 16'h0008; + FD1P3AX IS_FSM__i8 (.D(n733), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n732)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i8.GSR = "ENABLED"; + FD1P3AX IS_FSM__i7 (.D(n734), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n733)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i7.GSR = "ENABLED"; + FD1P3AX IS_FSM__i6 (.D(n735), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n734)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i6.GSR = "ENABLED"; + FD1P3AX IS_FSM__i5 (.D(n736), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n735)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i5.GSR = "ENABLED"; + FD1P3AX IS_FSM__i4 (.D(n737), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n736)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i4.GSR = "ENABLED"; + FD1P3AX IS_FSM__i3 (.D(n738), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n737)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i3.GSR = "ENABLED"; + FD1P3AX IS_FSM__i2 (.D(nRCAS_N_165), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n738)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i2.GSR = "ENABLED"; + FD1P3AX IS_FSM__i1 (.D(nRCS_N_139), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(nRCAS_N_165)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i1.GSR = "ENABLED"; + FD1S3IX RBA__i2 (.D(CROW_c_1), .CK(nCRAS_c__inv), .CD(n2380), .Q(RBA_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RBA__i2.GSR = "ENABLED"; + FD1S3AX FS_610__i17 (.D(n78), .CK(RCLK_c), .Q(FS[17])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i17.GSR = "ENABLED"; + FD1S3AX FS_610__i16 (.D(n79), .CK(RCLK_c), .Q(FS[16])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i16.GSR = "ENABLED"; + FD1S3AX FS_610__i15 (.D(n80), .CK(RCLK_c), .Q(FS[15])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i15.GSR = "ENABLED"; + FD1S3AX FS_610__i14 (.D(n81), .CK(RCLK_c), .Q(FS[14])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i14.GSR = "ENABLED"; + FD1S3AX FS_610__i13 (.D(n82), .CK(RCLK_c), .Q(FS[13])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i13.GSR = "ENABLED"; + FD1S3AX FS_610__i12 (.D(n83), .CK(RCLK_c), .Q(FS[12])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i12.GSR = "ENABLED"; + FD1S3AX FS_610__i11 (.D(n84), .CK(RCLK_c), .Q(FS[11])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i11.GSR = "ENABLED"; + FD1S3AX FS_610__i10 (.D(n85), .CK(RCLK_c), .Q(FS[10])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i10.GSR = "ENABLED"; + FD1S3AX FS_610__i9 (.D(n86), .CK(RCLK_c), .Q(FS[9])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i9.GSR = "ENABLED"; + FD1S3AX FS_610__i8 (.D(n87), .CK(RCLK_c), .Q(FS[8])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i8.GSR = "ENABLED"; + FD1S3AX FS_610__i7 (.D(n88), .CK(RCLK_c), .Q(FS[7])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i7.GSR = "ENABLED"; + FD1S3AX FS_610__i6 (.D(n89), .CK(RCLK_c), .Q(FS[6])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i6.GSR = "ENABLED"; + FD1S3AX FS_610__i5 (.D(n90), .CK(RCLK_c), .Q(FS[5])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i5.GSR = "ENABLED"; + FD1S3AX FS_610__i4 (.D(n91), .CK(RCLK_c), .Q(FS[4])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i4.GSR = "ENABLED"; + FD1S3AX FS_610__i3 (.D(n92), .CK(RCLK_c), .Q(FS[3])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i3.GSR = "ENABLED"; + FD1S3AX FS_610__i2 (.D(n93), .CK(RCLK_c), .Q(FS[2])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i2.GSR = "ENABLED"; + FD1S3AX FS_610__i1 (.D(n94), .CK(RCLK_c), .Q(FS[1])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i1.GSR = "ENABLED"; + FD1S3AX WRD_i7 (.D(Din_c_7), .CK(nCCAS_N_3), .Q(WRD[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i7.GSR = "ENABLED"; + FD1S3AX WRD_i6 (.D(Din_c_6), .CK(nCCAS_N_3), .Q(WRD[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i6.GSR = "ENABLED"; + FD1S3AX WRD_i5 (.D(Din_c_5), .CK(nCCAS_N_3), .Q(WRD[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i5.GSR = "ENABLED"; + FD1S3AX WRD_i4 (.D(Din_c_4), .CK(nCCAS_N_3), .Q(WRD[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i4.GSR = "ENABLED"; + FD1S3AX WRD_i3 (.D(Din_c_3), .CK(nCCAS_N_3), .Q(WRD[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i3.GSR = "ENABLED"; + FD1S3AX WRD_i2 (.D(Din_c_2), .CK(nCCAS_N_3), .Q(WRD[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i2.GSR = "ENABLED"; + FD1S3AX WRD_i1 (.D(Din_c_1), .CK(nCCAS_N_3), .Q(WRD[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i1.GSR = "ENABLED"; + FD1S3JX RowA_i9 (.D(MAin_c_9), .CK(nCRAS_c__inv), .PD(n2380), .Q(RowA[9])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i9.GSR = "ENABLED"; + FD1S3IX RowA_i8 (.D(MAin_c_8), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[8])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i8.GSR = "ENABLED"; + FD1S3IX RowA_i7 (.D(MAin_c_7), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i7.GSR = "ENABLED"; + FD1S3IX RowA_i6 (.D(MAin_c_6), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i6.GSR = "ENABLED"; + FD1S3JX RowA_i5 (.D(MAin_c_5), .CK(nCRAS_c__inv), .PD(n2380), .Q(RowA[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i5.GSR = "ENABLED"; + FD1S3IX RowA_i4 (.D(MAin_c_4), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i4.GSR = "ENABLED"; + FD1S3IX RowA_i3 (.D(MAin_c_3), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i3.GSR = "ENABLED"; + FD1S3IX RowA_i2 (.D(MAin_c_2), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i2.GSR = "ENABLED"; + FD1S3IX RowA_i1 (.D(MAin_c_1), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i1.GSR = "ENABLED"; + FD1S3AX Bank_i7 (.D(Din_c_7), .CK(PHI2_c), .Q(Bank[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i7.GSR = "ENABLED"; + LUT4 i2_3_lut_3_lut (.A(nFWE_c), .B(Din_c_5), .C(Din_c_3), .Z(n2180)) /* synthesis lut_function=(!(A+!(B (C)))) */ ; + defparam i2_3_lut_3_lut.init = 16'h4040; + LUT4 i1_2_lut_3_lut (.A(Din_c_6), .B(Din_c_7), .C(Din_c_4), .Z(n6_adj_2)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(315[17:31]) + defparam i1_2_lut_3_lut.init = 16'h1010; + LUT4 RASr2_I_0_1_lut_rep_25 (.A(RASr2), .Z(n2374)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(143[40:46]) + defparam RASr2_I_0_1_lut_rep_25.init = 16'h5555; + LUT4 i1_4_lut_4_lut_adj_12 (.A(RASr2), .B(n6_adj_3), .C(nRowColSel_N_32), + .D(Ready), .Z(Ready_N_292)) /* synthesis lut_function=(A (D)+!A (B (C+(D))+!B (D))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(143[40:46]) + defparam i1_4_lut_4_lut_adj_12.init = 16'hff40; + LUT4 i1_4_lut_adj_13 (.A(Din_c_2), .B(n2055), .C(MAin_c_0), .D(n2362), + .Z(C1Submitted_N_237)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ; + defparam i1_4_lut_adj_13.init = 16'h0004; + FD1S3AX Bank_i6 (.D(Din_c_6), .CK(PHI2_c), .Q(Bank[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i6.GSR = "ENABLED"; + FD1S3AX Bank_i5 (.D(Din_c_5), .CK(PHI2_c), .Q(Bank[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i5.GSR = "ENABLED"; + FD1S3AX Bank_i4 (.D(Din_c_4), .CK(PHI2_c), .Q(Bank[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i4.GSR = "ENABLED"; + FD1S3AX Bank_i3 (.D(Din_c_3), .CK(PHI2_c), .Q(Bank[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i3.GSR = "ENABLED"; + FD1S3AX Bank_i2 (.D(Din_c_2), .CK(PHI2_c), .Q(Bank[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i2.GSR = "ENABLED"; + FD1S3AX Bank_i1 (.D(Din_c_1), .CK(PHI2_c), .Q(Bank[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i1.GSR = "ENABLED"; + CCU2D FS_610_add_4_5 (.A0(FS[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1993), + .COUT(n1994), .S0(n92), .S1(n91)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_5.INIT0 = 16'hfaaa; + defparam FS_610_add_4_5.INIT1 = 16'hfaaa; + defparam FS_610_add_4_5.INJECT1_0 = "NO"; + defparam FS_610_add_4_5.INJECT1_1 = "NO"; + BB Dout_pad_6__714 (.I(WRD[6]), .T(n984), .B(RD[6]), .O(Dout_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + LUT4 i2_3_lut_4_lut_adj_14 (.A(n2369), .B(n26), .C(n2180), .D(n2204), + .Z(PHI2_N_120_enable_8)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ; + defparam i2_3_lut_4_lut_adj_14.init = 16'h2000; + BB Dout_pad_5__715 (.I(WRD[5]), .T(n984), .B(RD[5]), .O(Dout_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + BB Dout_pad_4__716 (.I(WRD[4]), .T(n984), .B(RD[4]), .O(Dout_2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + BB Dout_pad_3__717 (.I(WRD[3]), .T(n984), .B(RD[3]), .O(Dout_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + BB Dout_pad_2__718 (.I(WRD[2]), .T(n984), .B(RD[2]), .O(Dout_4)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + LUT4 i1_2_lut_3_lut_adj_15 (.A(Din_c_6), .B(Din_c_7), .C(Din_c_5), + .Z(n1314)) /* synthesis lut_function=(A+(B+(C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(315[17:31]) + defparam i1_2_lut_3_lut_adj_15.init = 16'hfefe; + BB Dout_pad_1__719 (.I(WRD[1]), .T(n984), .B(RD[1]), .O(Dout_5)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + BB Dout_pad_0__720 (.I(WRD[0]), .T(n984), .B(RD[0]), .O(Dout_6)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + OB Dout_pad_7 (.I(Dout_c), .O(Dout[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_6 (.I(Dout_0), .O(Dout[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_5 (.I(Dout_1), .O(Dout[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_4 (.I(Dout_2), .O(Dout[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_3 (.I(Dout_3), .O(Dout[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_2 (.I(Dout_4), .O(Dout[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_1 (.I(Dout_5), .O(Dout[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_0 (.I(Dout_6), .O(Dout[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB LED_pad (.I(LED_c), .O(LED)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(22[9:12]) + OB RBA_pad_1 (.I(RBA_c_1), .O(RBA[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22]) + OB RBA_pad_0 (.I(RBA_c_0), .O(RBA[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22]) + OB RA_pad_11 (.I(RA_c), .O(RA[11])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_10 (.I(RA_0), .O(RA[10])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_9 (.I(RA_1_9), .O(RA[9])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_8 (.I(RA_1_8), .O(RA[8])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_7 (.I(RA_1_7), .O(RA[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_6 (.I(RA_1_6), .O(RA[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_5 (.I(RA_1_5), .O(RA[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_4 (.I(RA_1_4), .O(RA[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_3 (.I(RA_1_3), .O(RA[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_2 (.I(RA_1_2), .O(RA[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_1 (.I(RA_1_1), .O(RA[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_0 (.I(RA_1_0), .O(RA[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB nRCS_pad (.I(nRCS_c), .O(nRCS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[13:17]) + OB RCKE_pad (.I(RCKE_c), .O(RCKE)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(45[13:17]) + OB nRWE_pad (.I(nRWE_c), .O(nRWE)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[45:49]) + OB nRRAS_pad (.I(nRRAS_c), .O(nRRAS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[23:28]) + OB nRCAS_pad (.I(nRCAS_c), .O(nRCAS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[34:39]) + OB RDQMH_pad (.I(RDQMH_c), .O(RDQMH)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[16:21]) + OB RDQML_pad (.I(RDQML_c), .O(RDQML)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[9:14]) + OB nUFMCS_pad (.I(nUFMCS_c), .O(nUFMCS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(63[13:19]) + OB UFMCLK_pad (.I(UFMCLK_c), .O(UFMCLK)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(64[13:19]) + OB UFMSDI_pad (.I(UFMSDI_c), .O(UFMSDI)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(65[13:19]) + IB PHI2_pad (.I(PHI2), .O(PHI2_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) + IB MAin_pad_9 (.I(MAin[9]), .O(MAin_c_9)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_8 (.I(MAin[8]), .O(MAin_c_8)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_7 (.I(MAin[7]), .O(MAin_c_7)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_6 (.I(MAin[6]), .O(MAin_c_6)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_5 (.I(MAin[5]), .O(MAin_c_5)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_4 (.I(MAin[4]), .O(MAin_c_4)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_3 (.I(MAin[3]), .O(MAin_c_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_2 (.I(MAin[2]), .O(MAin_c_2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_1 (.I(MAin[1]), .O(MAin_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_0 (.I(MAin[0]), .O(MAin_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB CROW_pad_1 (.I(CROW[1]), .O(CROW_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18]) + IB CROW_pad_0 (.I(CROW[0]), .O(CROW_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18]) + IB Din_pad_7 (.I(Din[7]), .O(Din_c_7)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_6 (.I(Din[6]), .O(Din_c_6)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_5 (.I(Din[5]), .O(Din_c_5)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_4 (.I(Din[4]), .O(Din_c_4)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_3 (.I(Din[3]), .O(Din_c_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_2 (.I(Din[2]), .O(Din_c_2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_1 (.I(Din[1]), .O(Din_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_0 (.I(Din[0]), .O(Din_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB nCCAS_pad (.I(nCCAS), .O(nCCAS_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) + IB nCRAS_pad (.I(nCRAS), .O(nCRAS_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + IB nFWE_pad (.I(nFWE), .O(nFWE_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(36[8:12]) + IB RCLK_pad (.I(RCLK), .O(RCLK_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12]) + IB UFMSDO_pad (.I(UFMSDO), .O(UFMSDO_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(66[8:14]) + CCU2D FS_610_add_4_17 (.A0(FS[15]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[16]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1999), + .COUT(n2000), .S0(n80), .S1(n79)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_17.INIT0 = 16'hfaaa; + defparam FS_610_add_4_17.INIT1 = 16'hfaaa; + defparam FS_610_add_4_17.INJECT1_0 = "NO"; + defparam FS_610_add_4_17.INJECT1_1 = "NO"; + LUT4 i1_2_lut_rep_14_3_lut (.A(n2369), .B(n26), .C(nFWE_c), .Z(n2363)) /* synthesis lut_function=((B+(C))+!A) */ ; + defparam i1_2_lut_rep_14_3_lut.init = 16'hfdfd; + LUT4 i1_2_lut_rep_13_3_lut (.A(n2369), .B(n26), .C(MAin_c_1), .Z(n2362)) /* synthesis lut_function=((B+!(C))+!A) */ ; + defparam i1_2_lut_rep_13_3_lut.init = 16'hdfdf; + LUT4 i2010_3_lut_3_lut (.A(nCRAS_c), .B(LEDEN), .C(CBR), .Z(LED_c)) /* synthesis lut_function=(A+((C)+!B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(23[17:23]) + defparam i2010_3_lut_3_lut.init = 16'hfbfb; + LUT4 i5_3_lut (.A(FS[3]), .B(FS[9]), .C(FS[6]), .Z(n14)) /* synthesis lut_function=(A+(B+(C))) */ ; + defparam i5_3_lut.init = 16'hfefe; + LUT4 i4_4_lut_adj_16 (.A(nRowColSel_N_35), .B(nRowColSel_N_33), .C(nRowColSel_N_32), + .D(n6), .Z(RCLK_c_enable_6)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; + defparam i4_4_lut_adj_16.init = 16'hfffe; + LUT4 i4_4_lut_adj_17 (.A(n7), .B(FS[8]), .C(FS[10]), .D(n10), .Z(n2174)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i4_4_lut_adj_17.init = 16'h0002; + LUT4 i34_4_lut (.A(n7_adj_5), .B(ADSubmitted), .C(C1Submitted_N_237), + .D(n2363), .Z(PHI2_N_120_enable_1)) /* synthesis lut_function=(A (B (C))+!A (B (C+!(D))+!B !(C+(D)))) */ ; + defparam i34_4_lut.init = 16'hc0c5; + LUT4 i13_3_lut (.A(MAin_c_0), .B(n2210), .C(MAin_c_1), .Z(n7_adj_5)) /* synthesis lut_function=(A (B (C))+!A (B+!(C))) */ ; + defparam i13_3_lut.init = 16'hc5c5; + LUT4 i1_2_lut_4_lut (.A(FS[11]), .B(n2368), .C(InitReady), .D(FS[10]), + .Z(n64)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; + defparam i1_2_lut_4_lut.init = 16'hfffe; + LUT4 nRCS_N_137_I_0_4_lut (.A(nRCS_N_137), .B(n2379), .C(Ready), .D(nRowColSel_N_35), + .Z(nRRAS_N_156)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B ((D)+!C)+!B !(C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6]) + defparam nRCS_N_137_I_0_4_lut.init = 16'h3afa; + LUT4 i3_4_lut_adj_18 (.A(Din_c_5), .B(n2228), .C(n2183), .D(n2370), + .Z(n2055)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) + defparam i3_4_lut_adj_18.init = 16'h1000; + LUT4 i1930_2_lut (.A(nFWE_c), .B(Din_c_4), .Z(n2228)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1930_2_lut.init = 16'heeee; + LUT4 i1110_2_lut_3_lut_4_lut (.A(nFWE_c), .B(n2365), .C(C1Submitted), + .D(MAin_c_1), .Z(n1398)) /* synthesis lut_function=(A (C)+!A (B (C)+!B !((D)+!C))) */ ; + defparam i1110_2_lut_3_lut_4_lut.init = 16'he0f0; + LUT4 i1_2_lut_adj_19 (.A(FS[11]), .B(FS[6]), .Z(n4)) /* synthesis lut_function=(A (B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i1_2_lut_adj_19.init = 16'h8888; + LUT4 i2_4_lut_adj_20 (.A(n2375), .B(FS[7]), .C(FS[9]), .D(FS[5]), + .Z(n7)) /* synthesis lut_function=(!(A+(B (C)+!B !(C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i2_4_lut_adj_20.init = 16'h1404; + LUT4 i1417_2_lut (.A(nCCAS_c), .B(nFWE_c), .Z(n984)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1417_2_lut.init = 16'heeee; + LUT4 i2_4_lut_adj_21 (.A(n2228), .B(CmdEnable), .C(n1277), .D(n1314), + .Z(PHI2_N_120_enable_3)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ; + defparam i2_4_lut_adj_21.init = 16'h0004; + LUT4 i3_4_lut_adj_22 (.A(Din_c_5), .B(n2191), .C(C1Submitted), .D(n2208), + .Z(n2210)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ; + defparam i3_4_lut_adj_22.init = 16'h0800; + LUT4 i1_2_lut_adj_23 (.A(nRowColSel_N_33), .B(CASr2), .Z(n2227)) /* synthesis lut_function=(A+!(B)) */ ; + defparam i1_2_lut_adj_23.init = 16'hbbbb; + FD1P3AX InitReady_394 (.D(n2447), .SP(RCLK_c_enable_28), .CK(RCLK_c), + .Q(InitReady)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(134[9] 138[5]) + defparam InitReady_394.GSR = "ENABLED"; + LUT4 nRCS_I_0_448_3_lut (.A(nRCS_N_137), .B(nRCS_N_141), .C(Ready), + .Z(nRCS_N_136)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6]) + defparam nRCS_I_0_448_3_lut.init = 16'hcaca; + LUT4 i1969_2_lut_3_lut_4_lut (.A(FS[12]), .B(FS[14]), .C(FS[11]), + .D(n10), .Z(n2267)) /* synthesis lut_function=(A+(B+((D)+!C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i1969_2_lut_3_lut_4_lut.init = 16'hffef; + LUT4 i1_2_lut_rep_19_3_lut (.A(FS[12]), .B(FS[14]), .C(n10), .Z(n2368)) /* synthesis lut_function=(A+(B+(C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i1_2_lut_rep_19_3_lut.init = 16'hfefe; + LUT4 i2_3_lut_4_lut_adj_24 (.A(CBR), .B(CASr3), .C(FWEr), .D(CASr2), + .Z(nRCS_N_146)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam i2_3_lut_4_lut_adj_24.init = 16'h1000; + LUT4 i3_2_lut_rep_26 (.A(FS[12]), .B(FS[14]), .Z(n2375)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i3_2_lut_rep_26.init = 16'heeee; + LUT4 i1_2_lut_rep_27 (.A(CBR), .B(CASr3), .Z(n2376)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam i1_2_lut_rep_27.init = 16'heeee; + LUT4 i2_3_lut_rep_28 (.A(PHI2r3), .B(PHI2r2), .C(CmdSubmitted), .Z(n2377)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(402[16:47]) + defparam i2_3_lut_rep_28.init = 16'h2020; + INV i2044 (.A(nCRAS_c), .Z(nCRAS_c__inv)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + FD1S3IX S_FSM_i2 (.D(n1406), .CK(RCLK_c), .CD(n1408), .Q(nRowColSel_N_34)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam S_FSM_i2.GSR = "ENABLED"; + INV i2045 (.A(nCCAS_c), .Z(nCCAS_N_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) + VLO i1 (.Z(GND_net)); + TSALL TSALL_INST (.TSALL(GND_net)); + PUR PUR_INST (.PUR(VCC_net)); + defparam PUR_INST.RST_PULSE = 1; + LUT4 i1_2_lut_4_lut_adj_25 (.A(PHI2r3), .B(PHI2r2), .C(CmdSubmitted), + .D(InitReady), .Z(RCLK_c_enable_10)) /* synthesis lut_function=(!(A (B (D)+!B !(C+!(D)))+!A (D))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(402[16:47]) + defparam i1_2_lut_4_lut_adj_25.init = 16'h20ff; + LUT4 i1_2_lut_rep_29 (.A(FWEr), .B(CBR), .Z(n2378)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1_2_lut_rep_29.init = 16'heeee; + LUT4 m1_lut (.Z(n2447)) /* synthesis lut_function=1, syn_instantiated=1 */ ; + defparam m1_lut.init = 16'hffff; + LUT4 n8MEGEN_I_14_3_lut_4_lut (.A(InitReady), .B(n2367), .C(UFMSDO_c), + .D(Cmdn8MEGEN), .Z(n8MEGEN_N_91)) /* synthesis lut_function=(A (D)+!A !(B (C)+!B !(D))) */ ; + defparam n8MEGEN_I_14_3_lut_4_lut.init = 16'hbf04; + +endmodule +// +// Verilog Description of module TSALL +// module not written out since it is a black-box. +// + +// +// Verilog Description of module PUR +// module not written out since it is a black-box. +// + diff --git a/CPLD/LCMXO2-640HC/impl1/automake.log b/CPLD/LCMXO2-640HC/impl1/automake.log new file mode 100644 index 0000000..93ca373 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/automake.log @@ -0,0 +1,1033 @@ + +synthesis -f "RAM2GS_LCMXO2_640HC_impl1_lattice.synproj" +synthesis: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:22 2023 + + +Command Line: synthesis -f RAM2GS_LCMXO2_640HC_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml + + +Synthesis options: +The -a option is MachXO2. +The -s option is 4. +The -t option is TQFP100. +The -d option is LCMXO2-640HC. +Using package TQFP100. +Using performance grade 4. + + +########################################################## + +### Lattice Family : MachXO2 + +### Device : LCMXO2-640HC + +### Package : TQFP100 + +### Speed : 4 + +########################################################## + + + + +Optimization goal = Balanced +Top-level module name = RAM2GS. +Target frequency = 200.000000 MHz. +Maximum fanout = 1000. +Timing path count = 3 +BRAM utilization = 100.000000 % +DSP usage = true +DSP utilization = 100.000000 % +fsm_encoding_style = auto +resolve_mixed_drivers = 0 +fix_gated_clocks = 1 + +Mux style = Auto +Use Carry Chain = true +carry_chain_length = 0 +Loop Limit = 1950. +Use IO Insertion = TRUE +Use IO Reg = AUTO + +Resource Sharing = TRUE +Propagate Constants = TRUE +Remove Duplicate Registers = TRUE +force_gsr = auto +ROM style = auto +RAM style = auto +The -comp option is FALSE. +The -syn option is FALSE. +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC (searchpath added) +-p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added) +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1 (searchpath added) +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC (searchpath added) +Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v +NGD file = RAM2GS_LCMXO2_640HC_impl1.ngd +-sdc option: SDC file input not used. +-lpf option: Output file option is ON. +Hardtimer checking is enabled (default). The -dt option is not used. +The -r option is OFF. [ Remove LOC Properties is OFF. ] +Technology check ok... + +Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 +Compile design. +Compile Design Begin +Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482 +Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 +Top module name (Verilog): RAM2GS + + + + +Last elaborated design is RAM2GS() +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... +Loading device for application map from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Top-level module name = RAM2GS. + +original encoding -> new encoding (one-hot encoding) + + 0000 -> 0000000000000001 + + 0001 -> 0000000000000010 + + 0010 -> 0000000000000100 + + 0011 -> 0000000000001000 + + 0100 -> 0000000000010000 + + 0101 -> 0000000000100000 + + 0110 -> 0000000001000000 + + 0111 -> 0000000010000000 + + 1000 -> 0000000100000000 + + 1001 -> 0000001000000000 + + 1010 -> 0000010000000000 + + 1011 -> 0000100000000000 + + 1100 -> 0001000000000000 + + 1101 -> 0010000000000000 + + 1110 -> 0100000000000000 + + 1111 -> 1000000000000000 + + +original encoding -> new encoding (one-hot encoding) + + 00 -> 0001 + + 01 -> 0010 + + 10 -> 0100 + + 11 -> 1000 + + + + +GSR will not be inferred because no asynchronous signal was found in the netlist. + +Applying 200.000000 MHz constraint to all clocks + + +Results of NGD DRC are available in RAM2GS_drc.log. +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... + + +Running DRC... + +DRC complete with no errors or warnings + +Design Results: + 309 blocks expanded +completed the first expansion +All blocks are expanded and NGD expansion is successful. +Writing NGD file RAM2GS_LCMXO2_640HC_impl1.ngd. + +################### Begin Area Report (RAM2GS)###################### +Number of register bits => 102 of 877 (11 % ) +BB => 8 +CCU2D => 10 +FD1P3AX => 29 +FD1P3AY => 5 +FD1P3IX => 3 +FD1S3AX => 47 +FD1S3IX => 14 +FD1S3JX => 4 +GSR => 1 +IB => 26 +INV => 3 +LUT4 => 122 +OB => 33 +PFUMX => 1 +################### End Area Report ################## + +################### Begin BlackBox Report ###################### +TSALL => 1 +################### End BlackBox Report ################## + +################### Begin Clock Report ###################### +Clock Nets +Number of Clocks: 4 + Net : RCLK_c, loads : 62 + Net : PHI2_c, loads : 11 + Net : nCCAS_c, loads : 2 + Net : nCRAS_c, loads : 2 +Clock Enable Nets +Number of Clock Enables: 14 +Top 10 highest fanout Clock Enables: + Net : RCLK_c_enable_27, loads : 16 + Net : RCLK_c_enable_6, loads : 4 + Net : PHI2_N_120_enable_8, loads : 3 + Net : RCLK_c_enable_10, loads : 3 + Net : RCLK_c_enable_5, loads : 2 + Net : PHI2_N_120_enable_3, loads : 1 + Net : Ready_N_292, loads : 1 + Net : PHI2_N_120_enable_2, loads : 1 + Net : RCLK_c_enable_15, loads : 1 + Net : PHI2_N_120_enable_6, loads : 1 +Highest fanout non-clock nets +Top 10 highest fanout non-clock nets: + Net : RCLK_c_enable_27, loads : 16 + Net : InitReady, loads : 15 + Net : nCRAS_c__inv, loads : 15 + Net : RASr2, loads : 14 + Net : nRowColSel_N_35, loads : 13 + Net : n2380, loads : 13 + Net : nRowColSel, loads : 12 + Net : Ready, loads : 12 + Net : Din_c_4, loads : 10 + Net : MAin_c_1, loads : 10 +################### End Clock Report ################## + +Timing Report Summary +-------------- +-------------------------------------------------------------------------------- +Constraint | Constraint| Actual|Levels +-------------------------------------------------------------------------------- + | | | +create_clock -period 5.000000 -name | | | +clk3 [get_nets nCCAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk2 [get_nets nCRAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk1 [get_nets PHI2_c] | 200.000 MHz| 50.413 MHz| 6 * + | | | +create_clock -period 5.000000 -name | | | +clk0 [get_nets RCLK_c] | 200.000 MHz| 120.207 MHz| 5 * + | | | +-------------------------------------------------------------------------------- + + +2 constraints not met. + + +Peak Memory Usage: 53.555 MB + +-------------------------------------------------------------- +Elapsed CPU time for LSE flow : 0.828 secs +-------------------------------------------------------------- + +map -a "MachXO2" -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial "RAM2GS_LCMXO2_640HC_impl1.ngd" -o "RAM2GS_LCMXO2_640HC_impl1_map.ncd" -pr "RAM2GS_LCMXO2_640HC_impl1.prf" -mp "RAM2GS_LCMXO2_640HC_impl1.mrp" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lpf" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf" -c 0 +map: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + Process the file: RAM2GS_LCMXO2_640HC_impl1.ngd + Picdevice="LCMXO2-640HC" + + Pictype="TQFP100" + + Picspeed=4 + + Remove unused logic + + Do not produce over sized NCDs. + +Part used: LCMXO2-640HCTQFP100, Performance used: 4. + +Loading device for application map from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. + +Running general design DRC... + +Removing unused logic... + +Optimizing... + + + + +Design Summary: + Number of registers: 102 out of 877 (12%) + PFU registers: 102 out of 640 (16%) + PIO registers: 0 out of 237 (0%) + Number of SLICEs: 75 out of 320 (23%) + SLICEs as Logic/ROM: 75 out of 320 (23%) + SLICEs as RAM: 0 out of 240 (0%) + SLICEs as Carry: 10 out of 320 (3%) + Number of LUT4s: 143 out of 640 (22%) + Number used as logic LUTs: 123 + Number used as distributed RAM: 0 + Number used as ripple logic: 20 + Number used as shift registers: 0 + Number of PIO sites used: 67 + 4(JTAG) out of 79 (90%) + Number of block RAMs: 0 out of 2 (0%) + Number of GSRs: 0 out of 1 (0%) + EFB used : No + JTAG used : No + Readback used : No + Oscillator used : No + Startup used : No + POR : On + Bandgap : On + Number of Power Controller: 0 out of 1 (0%) + Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) + Number of DCCA: 0 out of 8 (0%) + Number of DCMA: 0 out of 2 (0%) + Notes:- + 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) + 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. + Number of clocks: 4 + Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK ) + Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 ) + Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) + Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS ) + Number of Clock Enables: 14 + Net RCLK_c_enable_6: 4 loads, 4 LSLICEs + Net RCLK_c_enable_5: 2 loads, 2 LSLICEs + Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_2: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_6: 1 loads, 1 LSLICEs + Net RCLK_c_enable_27: 8 loads, 8 LSLICEs + Net RCLK_c_enable_10: 3 loads, 3 LSLICEs + Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs + Net RCLK_c_enable_16: 1 loads, 1 LSLICEs + Net RCLK_c_enable_28: 1 loads, 1 LSLICEs + Net RCLK_c_enable_15: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_3: 1 loads, 1 LSLICEs + Net Ready_N_292: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_8: 2 loads, 2 LSLICEs + Number of LSRs: 7 + Net RASr2: 1 loads, 1 LSLICEs + Net nRowColSel_N_35: 1 loads, 1 LSLICEs + Net Ready: 7 loads, 7 LSLICEs + Net nRWE_N_177: 1 loads, 1 LSLICEs + Net C1Submitted_N_237: 2 loads, 2 LSLICEs + Net n2366: 2 loads, 2 LSLICEs + Net nRowColSel_N_34: 1 loads, 1 LSLICEs + Number of nets driven by tri-state buffers: 0 + Top 10 highest fanout non-clock nets: + Net Ready: 18 loads + Net InitReady: 15 loads + Net RASr2: 15 loads + Net nRowColSel_N_35: 13 loads + Net nRowColSel: 12 loads + Net Din_c_4: 10 loads + Net MAin_c_1: 10 loads + Net Din_c_5: 9 loads + Net MAin_c_0: 9 loads + Net Din_c_0: 8 loads + + + Number of warnings: 0 + Number of errors: 0 + + + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 35 MB + +Dumping design to file RAM2GS_LCMXO2_640HC_impl1_map.ncd. + +ncd2vdb "RAM2GS_LCMXO2_640HC_impl1_map.ncd" ".vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb" + +Loading device for application ncd2vdb from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. + +trce -f "RAM2GS_LCMXO2_640HC_impl1.mt" -o "RAM2GS_LCMXO2_640HC_impl1.tw1" "RAM2GS_LCMXO2_640HC_impl1_map.ncd" "RAM2GS_LCMXO2_640HC_impl1.prf" +trce: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:25 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf +Design file: ram2gs_lcmxo2_640hc_impl1_map.ncd +Preference file: ram2gs_lcmxo2_640hc_impl1.prf +Device,speed: LCMXO2-640HC,4 +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +Report Type: based on TRACE automatically generated preferences +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Setup): +--------------- + +Timing errors: 349 Score: 848079 +Cumulative negative slack: 584487 + +Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:25 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf +Design file: ram2gs_lcmxo2_640hc_impl1_map.ncd +Preference file: ram2gs_lcmxo2_640hc_impl1.prf +Device,speed: LCMXO2-640HC,M +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 349 (setup), 0 (hold) +Score: 848079 (setup), 0 (hold) +Cumulative negative slack: 584487 (584487+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 41 MB + + +ldbanno "RAM2GS_LCMXO2_640HC_impl1_map.ncd" -n Verilog -o "RAM2GS_LCMXO2_640HC_impl1_mapvo.vo" -w -neg +ldbanno: version Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Writing a Verilog netlist using the orca library type based on the RAM2GS_LCMXO2_640HC_impl1_map design file. + + +Loading design for application ldbanno from file RAM2GS_LCMXO2_640HC_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application ldbanno from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Converting design RAM2GS_LCMXO2_640HC_impl1_map.ncd into .ldb format. +Writing Verilog netlist to file RAM2GS_LCMXO2_640HC_impl1_mapvo.vo +Writing SDF timing to file RAM2GS_LCMXO2_640HC_impl1_mapvo.sdf + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 37 MB + +ldbanno "RAM2GS_LCMXO2_640HC_impl1_map.ncd" -n VHDL -o "RAM2GS_LCMXO2_640HC_impl1_mapvho.vho" -w -neg +ldbanno: version Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Writing a VHDL netlist using the orca library type based on the RAM2GS_LCMXO2_640HC_impl1_map design file. + + +Loading design for application ldbanno from file RAM2GS_LCMXO2_640HC_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application ldbanno from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Converting design RAM2GS_LCMXO2_640HC_impl1_map.ncd into .ldb format. +Writing VHDL netlist to file RAM2GS_LCMXO2_640HC_impl1_mapvho.vho +Writing SDF timing to file RAM2GS_LCMXO2_640HC_impl1_mapvho.sdf + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 36 MB + +mpartrce -p "RAM2GS_LCMXO2_640HC_impl1.p2t" -f "RAM2GS_LCMXO2_640HC_impl1.p3t" -tf "RAM2GS_LCMXO2_640HC_impl1.pt" "RAM2GS_LCMXO2_640HC_impl1_map.ncd" "RAM2GS_LCMXO2_640HC_impl1.ncd" + +---- MParTrce Tool ---- +Removing old design directory at request of -rem command line option to this program. +Running par. Please wait . . . + +Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd" +Tue Aug 15 05:03:28 2023 + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf +Preference file: RAM2GS_LCMXO2_640HC_impl1.prf. +Placement level-cost: 5-1. +Routing Iterations: 6 + +Loading design for application par from file RAM2GS_LCMXO2_640HC_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +License checked out. + + +Ignore Preference Error(s): True +Device utilization summary: + + PIO (prelim) 67+4(JTAG)/80 89% used + 67+4(JTAG)/79 90% bonded + + SLICE 75/320 23% used + + + +Number of Signals: 285 +Number of Connections: 674 + + +Pin Constraint Summary: + 66 out of 67 pins locked (98% locked). + +The following 2 signals are selected to use the primary clock routing resources: + RCLK_c (driver: RCLK, clk load #: 40) + PHI2_c (driver: PHI2, clk load #: 13) + + + + +The following 1 signal is selected to use the secondary clock routing resources: + nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0) + + +No signal is selected as Global Set/Reset. +. +Starting Placer Phase 0. +............. +Finished Placer Phase 0. REAL time: 0 secs + +Starting Placer Phase 1. +............... +Placer score = 121531. +Finished Placer Phase 1. REAL time: 4 secs + +Starting Placer Phase 2. +. +Placer score = 119079 +Finished Placer Phase 2. REAL time: 4 secs + + +------------------ Clock Report ------------------ + +Global Clock Resources: + CLK_PIN : 0 out of 8 (0%) + General PIO: 3 out of 80 (3%) + DCM : 0 out of 2 (0%) + DCC : 0 out of 8 (0%) + +Global Clocks: + PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 40 + PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 13 + SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 7, ce load = 0, sr load = 0 + + PRIMARY : 2 out of 8 (25%) + SECONDARY: 1 out of 8 (12%) + +--------------- End of Clock Report --------------- + + +I/O Usage Summary (final): + 67 + 4(JTAG) out of 80 (88.8%) PIO sites used. + 67 + 4(JTAG) out of 79 (89.9%) bonded PIO sites used. + Number of PIO comps: 67; differential: 0. + Number of Vref pins used: 0. + +I/O Bank Usage Summary: ++----------+----------------+------------+-----------+ +| I/O Bank | Usage | Bank Vccio | Bank Vref | ++----------+----------------+------------+-----------+ +| 0 | 14 / 19 ( 73%) | 2.5V | - | +| 1 | 20 / 20 (100%) | 2.5V | - | +| 2 | 16 / 20 ( 80%) | 2.5V | - | +| 3 | 17 / 20 ( 85%) | 2.5V | - | ++----------+----------------+------------+-----------+ + +Total placer CPU time: 3 secs + +Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd. + +0 connections routed; 674 unrouted. +Starting router resource preassignment + + + + + +Completed router resource preassignment. Real time: 7 secs + +Start NBR router at 05:03:35 08/15/23 + +***************************************************************** +Info: NBR allows conflicts(one node used by more than one signal) + in the earlier iterations. In each iteration, it tries to + solve the conflicts while keeping the critical connections + routed as short as possible. The routing process is said to + be completed when no conflicts exist and all connections + are routed. +Note: NBR uses a different method to calculate timing slacks. The + worst slack and total negative slack may not be the same as + that in TRCE report. You should always run TRCE to verify + your design. +***************************************************************** + +Start NBR special constraint process at 05:03:35 08/15/23 + +Start NBR section for initial routing at 05:03:35 08/15/23 +Level 1, iteration 1 +2(0.00%) conflicts; 536(79.53%) untouched conns; 481988 (nbr) score; +Estimated worst slack/total negative slack: -4.914ns/-481.988ns; real time: 7 secs +Level 2, iteration 1 +7(0.02%) conflicts; 473(70.18%) untouched conns; 424953 (nbr) score; +Estimated worst slack/total negative slack: -4.988ns/-424.953ns; real time: 7 secs +Level 3, iteration 1 +12(0.03%) conflicts; 254(37.69%) untouched conns; 455640 (nbr) score; +Estimated worst slack/total negative slack: -5.118ns/-455.640ns; real time: 7 secs +Level 4, iteration 1 +6(0.01%) conflicts; 0(0.00%) untouched conn; 465237 (nbr) score; +Estimated worst slack/total negative slack: -5.122ns/-465.237ns; real time: 7 secs + +Info: Initial congestion level at 75% usage is 0 +Info: Initial congestion area at 75% usage is 0 (0.00%) + +Start NBR section for normal routing at 05:03:35 08/15/23 +Level 4, iteration 1 +6(0.01%) conflicts; 0(0.00%) untouched conn; 461186 (nbr) score; +Estimated worst slack/total negative slack: -4.992ns/-461.186ns; real time: 7 secs +Level 4, iteration 2 +3(0.01%) conflicts; 0(0.00%) untouched conn; 460933 (nbr) score; +Estimated worst slack/total negative slack: -4.992ns/-460.933ns; real time: 7 secs +Level 4, iteration 3 +2(0.00%) conflicts; 0(0.00%) untouched conn; 461063 (nbr) score; +Estimated worst slack/total negative slack: -4.992ns/-461.063ns; real time: 7 secs +Level 4, iteration 4 +1(0.00%) conflict; 0(0.00%) untouched conn; 461063 (nbr) score; +Estimated worst slack/total negative slack: -4.992ns/-461.063ns; real time: 7 secs +Level 4, iteration 5 +0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; +Estimated worst slack/total negative slack: -5.122ns/-468.515ns; real time: 7 secs + +Start NBR section for performance tuning (iteration 1) at 05:03:35 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; +Estimated worst slack/total negative slack: -5.122ns/-468.515ns; real time: 7 secs + +Start NBR section for re-routing at 05:03:35 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; +Estimated worst slack/total negative slack: -5.122ns/-468.515ns; real time: 7 secs + +Start NBR section for post-routing at 05:03:35 08/15/23 + +End NBR router with 0 unrouted connection + +NBR Summary +----------- + Number of unrouted connections : 0 (0.00%) + Number of connections with timing violations : 260 (38.58%) + Estimated worst slack : -5.122ns + Timing score : 452301 +----------- +Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. + + + + + +Total CPU time 7 secs +Total REAL time: 7 secs +Completely routed. +End of route. 674 routed (100.00%); 0 unrouted. + +Hold time timing score: 0, hold timing errors: 0 + +Timing score: 452301 + +Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd. + + +PAR_SUMMARY::Run status = Completed +PAR_SUMMARY::Number of unrouted conns = 0 +PAR_SUMMARY::Worst slack> = -5.122 +PAR_SUMMARY::Timing score> = 452.301 +PAR_SUMMARY::Worst slack> = 0.304 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Number of errors = 0 + +Total CPU time to completion: 7 secs +Total REAL time to completion: 7 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Exiting par with exit code 0 +Exiting mpartrce with exit code 0 + +trce -f "RAM2GS_LCMXO2_640HC_impl1.pt" -o "RAM2GS_LCMXO2_640HC_impl1.twr" "RAM2GS_LCMXO2_640HC_impl1.ncd" "RAM2GS_LCMXO2_640HC_impl1.prf" +trce: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:36 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf +Design file: ram2gs_lcmxo2_640hc_impl1.ncd +Preference file: ram2gs_lcmxo2_640hc_impl1.prf +Device,speed: LCMXO2-640HC,4 +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +Report Type: based on TRACE automatically generated preferences +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Setup): +--------------- + +Timing errors: 349 Score: 452301 +Cumulative negative slack: 370485 + +Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:36 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf +Design file: ram2gs_lcmxo2_640hc_impl1.ncd +Preference file: ram2gs_lcmxo2_640hc_impl1.prf +Device,speed: LCMXO2-640HC,m +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 349 (setup), 0 (hold) +Score: 452301 (setup), 0 (hold) +Cumulative negative slack: 370485 (370485+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 40 MB + + +iotiming "RAM2GS_LCMXO2_640HC_impl1.ncd" "RAM2GS_LCMXO2_640HC_impl1.prf" +I/O Timing Report: +: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application iotiming from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Running Performance Grade: 4 +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... + +Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 5 +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Running Performance Grade: 5 +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... + +Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 6 +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Running Performance Grade: 6 +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... + +Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: M +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Running Performance Grade: M +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... +Done. + +tmcheck -par "RAM2GS_LCMXO2_640HC_impl1.par" + +bitgen -f "RAM2GS_LCMXO2_640HC_impl1.t2b" -w "RAM2GS_LCMXO2_640HC_impl1.ncd" -jedec "RAM2GS_LCMXO2_640HC_impl1.prf" + + +BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + + +Loading design for application Bitgen from file RAM2GS_LCMXO2_640HC_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. + +Running DRC. +DRC detected 0 errors and 0 warnings. +Reading Preference File from RAM2GS_LCMXO2_640HC_impl1.prf. + +Preference Summary: ++---------------------------------+---------------------------------+ +| Preference | Current Setting | ++---------------------------------+---------------------------------+ +| RamCfg | Reset** | ++---------------------------------+---------------------------------+ +| MCCLK_FREQ | 2.08** | ++---------------------------------+---------------------------------+ +| CONFIG_SECURE | OFF** | ++---------------------------------+---------------------------------+ +| INBUF | ON** | ++---------------------------------+---------------------------------+ +| JTAG_PORT | ENABLE** | ++---------------------------------+---------------------------------+ +| SDM_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| SLAVE_SPI_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| MASTER_SPI_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| I2C_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| MUX_CONFIGURATION_PORTS | DISABLE** | ++---------------------------------+---------------------------------+ +| CONFIGURATION | CFG** | ++---------------------------------+---------------------------------+ +| COMPRESS_CONFIG | ON** | ++---------------------------------+---------------------------------+ +| MY_ASSP | OFF** | ++---------------------------------+---------------------------------+ +| ONE_TIME_PROGRAM | OFF** | ++---------------------------------+---------------------------------+ +| ENABLE_TRANSFR | DISABLE** | ++---------------------------------+---------------------------------+ +| SHAREDEBRINIT | DISABLE** | ++---------------------------------+---------------------------------+ +| BACKGROUND_RECONFIG | OFF** | ++---------------------------------+---------------------------------+ + * Default setting. + ** The specified setting matches the default setting. + + +Creating bit map... + +Bitstream Status: Final Version 1.95. + +Saving bit stream in "RAM2GS_LCMXO2_640HC_impl1.jed". + +=========== +UFM Summary. +=========== +UFM Size: 191 Pages (128*191 Bits). +UFM Utilization: General Purpose Flash Memory. + +Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190). +Initialized UFM Pages: 0 Page. + +Total CPU Time: 1 secs +Total REAL Time: 2 secs +Peak Memory Usage: 245 MB diff --git a/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html new file mode 100644 index 0000000..659885d --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html @@ -0,0 +1,9 @@ + 
    Setting log file to 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html'.
+Starting: parse design source files
+(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v'
+(VERI-1482) Analyzing Verilog file 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v'
+INFO - D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
+INFO - D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v(1,1-411,10) (VERI-9000) elaborating module 'RAM2GS'
+Done: design load finished with (0) errors, and (0) warnings
+
+
    \ No newline at end of file diff --git a/CPLD/LCMXO2-640HC/impl1/impl1.xcf b/CPLD/LCMXO2-640HC/impl1/impl1.xcf new file mode 100644 index 0000000..de47345 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/impl1.xcf @@ -0,0 +1,56 @@ + + + + + + JTAG + + + 1 + Lattice + MachXO2 + LCMXO2-640HC + 0x012b9043 + All + LCMXO2-640HC + + 8 + 11111111 + 1 + 0 + + D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.jed + 08/15/23 04:55:55 + 0x5769 + FLASH Erase,Program,Verify + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB + EzUSB-0 + \\?\usb#vid_1134&amp;pid_8001#5&amp;887acb0&amp;0&amp;13# + + TRST ABSENT; + ISPEN ABSENT; + + + diff --git a/CPLD/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1.ior b/CPLD/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1.ior new file mode 100644 index 0000000..81484d3 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1.ior @@ -0,0 +1,139 @@ +Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 5 +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 6 +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: M +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +// Design: RAM2GS +// Package: TQFP100 +// ncd File: ram2gs_lcmxo2_640hc_impl1.ncd +// Version: Diamond (64-bit) 3.12.1.454 +// Written on Tue Aug 15 05:03:37 2023 +// M: Minimum Performance Grade +// iotiming RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml + +I/O Timing Report (All units are in ns) + +Worst Case Results across Performance Grades (M, 6, 5, 4): + +// Input Setup and Hold Times + +Port Clock Edge Setup Performance_Grade Hold Performance_Grade +---------------------------------------------------------------------- +CROW[0] nCRAS F 0.993 4 0.541 4 +CROW[1] nCRAS F 0.293 4 1.148 4 +Din[0] PHI2 F 4.804 4 1.483 4 +Din[0] nCCAS F 1.539 4 -0.150 M +Din[1] PHI2 F 4.733 4 0.702 4 +Din[1] nCCAS F 1.638 4 -0.177 M +Din[2] PHI2 F 4.046 4 1.702 4 +Din[2] nCCAS F 1.651 4 -0.121 M +Din[3] PHI2 F 4.770 4 1.575 4 +Din[3] nCCAS F 1.973 4 -0.207 M +Din[4] PHI2 F 5.656 4 0.720 4 +Din[4] nCCAS F 1.606 4 -0.156 M +Din[5] PHI2 F 4.165 4 1.131 4 +Din[5] nCCAS F 0.618 4 0.435 4 +Din[6] PHI2 F 5.309 4 1.478 4 +Din[6] nCCAS F 1.331 4 -0.053 M +Din[7] PHI2 F 5.874 4 1.774 4 +Din[7] nCCAS F 2.023 4 -0.205 M +MAin[0] PHI2 F 5.149 4 0.137 M +MAin[0] nCRAS F -0.022 M 1.415 4 +MAin[1] PHI2 F 4.216 4 1.539 4 +MAin[1] nCRAS F 1.716 4 -0.018 M +MAin[2] PHI2 F 3.754 4 0.553 4 +MAin[2] nCRAS F -0.164 M 1.715 4 +MAin[3] PHI2 F 5.957 4 -0.100 M +MAin[3] nCRAS F 0.033 4 1.356 4 +MAin[4] PHI2 F 5.652 4 -0.180 M +MAin[4] nCRAS F -0.173 M 1.726 4 +MAin[5] PHI2 F 4.938 4 0.693 6 +MAin[5] nCRAS F 0.005 4 1.395 4 +MAin[6] PHI2 F 5.535 4 -0.147 M +MAin[6] nCRAS F 0.012 4 1.387 4 +MAin[7] PHI2 F 5.951 4 -0.083 M +MAin[7] nCRAS F 0.858 4 0.664 4 +MAin[8] nCRAS F 0.526 4 0.915 4 +MAin[9] nCRAS F 0.038 4 1.342 4 +PHI2 RCLK R 2.772 4 -0.342 M +UFMSDO RCLK R 0.780 4 0.632 4 +nCCAS RCLK R 0.557 4 0.872 4 +nCCAS nCRAS F 2.108 4 -0.053 M +nCRAS RCLK R 2.536 4 -0.169 M +nFWE PHI2 F 5.830 4 0.629 4 +nFWE nCRAS F 1.386 4 0.176 4 + + +// Clock to Output Delay + +Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade +------------------------------------------------------------------------ +LED RCLK R 11.611 4 3.288 M +LED nCRAS F 12.009 4 3.367 M +RA[0] RCLK R 12.268 4 3.492 M +RA[0] nCRAS F 11.741 4 3.284 M +RA[10] RCLK R 10.004 4 2.964 M +RA[11] PHI2 R 10.669 4 3.160 M +RA[1] RCLK R 12.975 4 3.665 M +RA[1] nCRAS F 11.918 4 3.321 M +RA[2] RCLK R 12.531 4 3.533 M +RA[2] nCRAS F 11.755 4 3.277 M +RA[3] RCLK R 11.851 4 3.375 M +RA[3] nCRAS F 12.624 4 3.513 M +RA[4] RCLK R 13.380 4 3.775 M +RA[4] nCRAS F 12.857 4 3.569 M +RA[5] RCLK R 12.767 4 3.632 M +RA[5] nCRAS F 12.469 4 3.456 M +RA[6] RCLK R 12.163 4 3.468 M +RA[6] nCRAS F 12.141 4 3.394 M +RA[7] RCLK R 11.990 4 3.375 M +RA[7] nCRAS F 12.172 4 3.381 M +RA[8] RCLK R 11.712 4 3.314 M +RA[8] nCRAS F 12.431 4 3.457 M +RA[9] RCLK R 11.412 4 3.233 M +RA[9] nCRAS F 12.128 4 3.377 M +RBA[0] nCRAS F 10.844 4 3.124 M +RBA[1] nCRAS F 10.216 4 2.967 M +RCKE RCLK R 10.964 4 3.209 M +RDQMH RCLK R 12.109 4 3.426 M +RDQML RCLK R 10.974 4 3.140 M +RD[0] nCCAS F 8.747 4 2.603 M +RD[1] nCCAS F 8.747 4 2.603 M +RD[2] nCCAS F 8.737 4 2.605 M +RD[3] nCCAS F 9.239 4 2.740 M +RD[4] nCCAS F 9.283 4 2.726 M +RD[5] nCCAS F 9.355 4 2.761 M +RD[6] nCCAS F 9.106 4 2.681 M +RD[7] nCCAS F 9.181 4 2.711 M +UFMCLK RCLK R 10.078 4 3.002 M +UFMSDI RCLK R 10.108 4 2.996 M +nRCAS RCLK R 10.525 4 3.100 M +nRCS RCLK R 10.119 4 2.984 M +nRRAS RCLK R 10.200 4 3.024 M +nRWE RCLK R 9.984 4 2.972 M +nUFMCS RCLK R 10.165 4 3.020 M +WARNING: you must also run trce with hold speed: 4 +WARNING: you must also run trce with hold speed: 6 +WARNING: you must also run trce with setup speed: M diff --git a/CPLD/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1_trce.asd b/CPLD/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1_trce.asd new file mode 100644 index 0000000..018a633 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1_trce.asd @@ -0,0 +1,13 @@ +[ActiveSupport TRCE] +; Setup Analysis +Fmax_0 = 160.205 MHz (299.401 MHz); +Fmax_1 = 65.729 MHz (99.079 MHz); +Failed = 2 (Total 2); +Clock_ports = 4; +Clock_nets = 4; +; Hold Analysis +Fmax_0 = 0.304 ns (0.000 ns); +Fmax_1 = 0.379 ns (0.000 ns); +Failed = 0 (Total 2); +Clock_ports = 4; +Clock_nets = 4; diff --git a/CPLD/LCMXO2-640HC/impl1/synthesis.log b/CPLD/LCMXO2-640HC/impl1/synthesis.log new file mode 100644 index 0000000..c8e59c3 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/synthesis.log @@ -0,0 +1,237 @@ +synthesis: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:22 2023 + + +Command Line: synthesis -f RAM2GS_LCMXO2_640HC_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml + +Synthesis options: +The -a option is MachXO2. +The -s option is 4. +The -t option is TQFP100. +The -d option is LCMXO2-640HC. +Using package TQFP100. +Using performance grade 4. + + +########################################################## + +### Lattice Family : MachXO2 + +### Device : LCMXO2-640HC + +### Package : TQFP100 + +### Speed : 4 + +########################################################## + + + +INFO - synthesis: User-Selected Strategy Settings +Optimization goal = Balanced +Top-level module name = RAM2GS. +Target frequency = 200.000000 MHz. +Maximum fanout = 1000. +Timing path count = 3 +BRAM utilization = 100.000000 % +DSP usage = true +DSP utilization = 100.000000 % +fsm_encoding_style = auto +resolve_mixed_drivers = 0 +fix_gated_clocks = 1 + +Mux style = Auto +Use Carry Chain = true +carry_chain_length = 0 +Loop Limit = 1950. +Use IO Insertion = TRUE +Use IO Reg = AUTO + +Resource Sharing = TRUE +Propagate Constants = TRUE +Remove Duplicate Registers = TRUE +force_gsr = auto +ROM style = auto +RAM style = auto +The -comp option is FALSE. +The -syn option is FALSE. +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC (searchpath added) +-p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added) +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1 (searchpath added) +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC (searchpath added) +Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v +NGD file = RAM2GS_LCMXO2_640HC_impl1.ngd +-sdc option: SDC file input not used. +-lpf option: Output file option is ON. +Hardtimer checking is enabled (default). The -dt option is not used. +The -r option is OFF. [ Remove LOC Properties is OFF. ] +Technology check ok... + +Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 +Compile design. +Compile Design Begin +Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482 +Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 +Top module name (Verilog): RAM2GS +INFO - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1): compiling module RAM2GS. VERI-1018 +WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131): expression size 32 truncated to fit in target size 2. VERI-1209 +WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136): expression size 32 truncated to fit in target size 18. VERI-1209 +WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263): expression size 32 truncated to fit in target size 4. VERI-1209 +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... +Loading device for application map from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Top-level module name = RAM2GS. +INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding +original encoding -> new encoding (one-hot encoding) + + 0000 -> 0000000000000001 + + 0001 -> 0000000000000010 + + 0010 -> 0000000000000100 + + 0011 -> 0000000000001000 + + 0100 -> 0000000000010000 + + 0101 -> 0000000000100000 + + 0110 -> 0000000001000000 + + 0111 -> 0000000010000000 + + 1000 -> 0000000100000000 + + 1001 -> 0000001000000000 + + 1010 -> 0000010000000000 + + 1011 -> 0000100000000000 + + 1100 -> 0001000000000000 + + 1101 -> 0010000000000000 + + 1110 -> 0100000000000000 + + 1111 -> 1000000000000000 + +INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding +original encoding -> new encoding (one-hot encoding) + + 00 -> 0001 + + 01 -> 0010 + + 10 -> 0100 + + 11 -> 1000 + + + + +GSR will not be inferred because no asynchronous signal was found in the netlist. +WARNING - synthesis: Initial value found on instance C1Submitted_406 will be ignored. +Applying 200.000000 MHz constraint to all clocks + +WARNING - synthesis: No user .sdc file. +Results of NGD DRC are available in RAM2GS_drc.log. +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... +All blocks are expanded and NGD expansion is successful. +Writing NGD file RAM2GS_LCMXO2_640HC_impl1.ngd. + +################### Begin Area Report (RAM2GS)###################### +Number of register bits => 102 of 877 (11 % ) +BB => 8 +CCU2D => 10 +FD1P3AX => 29 +FD1P3AY => 5 +FD1P3IX => 3 +FD1S3AX => 47 +FD1S3IX => 14 +FD1S3JX => 4 +GSR => 1 +IB => 26 +INV => 3 +LUT4 => 122 +OB => 33 +PFUMX => 1 +################### End Area Report ################## + +################### Begin BlackBox Report ###################### +TSALL => 1 +################### End BlackBox Report ################## + +################### Begin Clock Report ###################### +Clock Nets +Number of Clocks: 4 + Net : RCLK_c, loads : 62 + Net : PHI2_c, loads : 11 + Net : nCCAS_c, loads : 2 + Net : nCRAS_c, loads : 2 +Clock Enable Nets +Number of Clock Enables: 14 +Top 10 highest fanout Clock Enables: + Net : RCLK_c_enable_27, loads : 16 + Net : RCLK_c_enable_6, loads : 4 + Net : PHI2_N_120_enable_8, loads : 3 + Net : RCLK_c_enable_10, loads : 3 + Net : RCLK_c_enable_5, loads : 2 + Net : PHI2_N_120_enable_3, loads : 1 + Net : Ready_N_292, loads : 1 + Net : PHI2_N_120_enable_2, loads : 1 + Net : RCLK_c_enable_15, loads : 1 + Net : PHI2_N_120_enable_6, loads : 1 +Highest fanout non-clock nets +Top 10 highest fanout non-clock nets: + Net : RCLK_c_enable_27, loads : 16 + Net : InitReady, loads : 15 + Net : nCRAS_c__inv, loads : 15 + Net : RASr2, loads : 14 + Net : nRowColSel_N_35, loads : 13 + Net : n2380, loads : 13 + Net : nRowColSel, loads : 12 + Net : Ready, loads : 12 + Net : Din_c_4, loads : 10 + Net : MAin_c_1, loads : 10 +################### End Clock Report ################## + +Timing Report Summary +-------------- +-------------------------------------------------------------------------------- +Constraint | Constraint| Actual|Levels +-------------------------------------------------------------------------------- + | | | +create_clock -period 5.000000 -name | | | +clk3 [get_nets nCCAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk2 [get_nets nCRAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk1 [get_nets PHI2_c] | 200.000 MHz| 50.413 MHz| 6 * + | | | +create_clock -period 5.000000 -name | | | +clk0 [get_nets RCLK_c] | 200.000 MHz| 120.207 MHz| 5 * + | | | +-------------------------------------------------------------------------------- + + +2 constraints not met. + + +Peak Memory Usage: 53.555 MB + +-------------------------------------------------------------- +Elapsed CPU time for LSE flow : 0.828 secs +-------------------------------------------------------------- diff --git a/CPLD/LCMXO2-640HC/impl1/synthesis_lse.html b/CPLD/LCMXO2-640HC/impl1/synthesis_lse.html new file mode 100644 index 0000000..c8b6b6a --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/synthesis_lse.html @@ -0,0 +1,302 @@ + +Synthesis and Ngdbuild Report + + +
    Synthesis and Ngdbuild  Report
+synthesis:  version Diamond (64-bit) 3.12.1.454
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 15 05:03:22 2023
+
+
+Command Line:  synthesis -f RAM2GS_LCMXO2_640HC_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml 
+
+Synthesis options:
+The -a option is MachXO2.
+The -s option is 4.
+The -t option is TQFP100.
+The -d option is LCMXO2-640HC.
+Using package TQFP100.
+Using performance grade 4.
+                                                          
+
+##########################################################
+
+### Lattice Family : MachXO2
+
+### Device  : LCMXO2-640HC
+
+### Package : TQFP100
+
+### Speed   : 4
+
+##########################################################
+
+                                                          
+
+INFO - synthesis: User-Selected Strategy Settings
+Optimization goal = Balanced
+Top-level module name = RAM2GS.
+Target frequency = 200.000000 MHz.
+Maximum fanout = 1000.
+Timing path count = 3
+BRAM utilization = 100.000000 %
+DSP usage = true
+DSP utilization = 100.000000 %
+fsm_encoding_style = auto
+resolve_mixed_drivers = 0
+fix_gated_clocks = 1
+
+Mux style = Auto
+Use Carry Chain = true
+carry_chain_length = 0
+Loop Limit = 1950.
+Use IO Insertion = TRUE
+Use IO Reg = AUTO
+
+Resource Sharing = TRUE
+Propagate Constants = TRUE
+Remove Duplicate Registers = TRUE
+force_gsr = auto
+ROM style = auto
+RAM style = auto
+The -comp option is FALSE.
+The -syn option is FALSE.
+-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC (searchpath added)
+-p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
+-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1 (searchpath added)
+-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC (searchpath added)
+Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v
+NGD file = RAM2GS_LCMXO2_640HC_impl1.ngd
+-sdc option: SDC file input not used.
+-lpf option: Output file option is ON.
+Hardtimer checking is enabled (default). The -dt option is not used.
+The -r option is OFF. [ Remove LOC Properties is OFF. ]
+Technology check ok...
+
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
+Compile design.
+Compile Design Begin
+Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
+Top module name (Verilog): RAM2GS
+INFO - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1): compiling module RAM2GS. VERI-1018
+WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131): expression size 32 truncated to fit in target size 2. VERI-1209
+WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136): expression size 32 truncated to fit in target size 18. VERI-1209
+WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263): expression size 32 truncated to fit in target size 4. VERI-1209
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+Loading device for application map from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Top-level module name = RAM2GS.
+INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 0000 -> 0000000000000001
+
+ 0001 -> 0000000000000010
+
+ 0010 -> 0000000000000100
+
+ 0011 -> 0000000000001000
+
+ 0100 -> 0000000000010000
+
+ 0101 -> 0000000000100000
+
+ 0110 -> 0000000001000000
+
+ 0111 -> 0000000010000000
+
+ 1000 -> 0000000100000000
+
+ 1001 -> 0000001000000000
+
+ 1010 -> 0000010000000000
+
+ 1011 -> 0000100000000000
+
+ 1100 -> 0001000000000000
+
+ 1101 -> 0010000000000000
+
+ 1110 -> 0100000000000000
+
+ 1111 -> 1000000000000000
+
+INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 00 -> 0001
+
+ 01 -> 0010
+
+ 10 -> 0100
+
+ 11 -> 1000
+
+
+
+
+GSR will not be inferred because no asynchronous signal was found in the netlist.
+WARNING - synthesis: Initial value found on instance C1Submitted_406 will be ignored.
+Applying 200.000000 MHz constraint to all clocks
+
+WARNING - synthesis: No user .sdc file.
+Results of NGD DRC are available in RAM2GS_drc.log.
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+All blocks are expanded and NGD expansion is successful.
+Writing NGD file RAM2GS_LCMXO2_640HC_impl1.ngd.
+
+################### Begin Area Report (RAM2GS)######################
+Number of register bits => 102 of 877 (11 % )
+BB => 8
+CCU2D => 10
+FD1P3AX => 29
+FD1P3AY => 5
+FD1P3IX => 3
+FD1S3AX => 47
+FD1S3IX => 14
+FD1S3JX => 4
+GSR => 1
+IB => 26
+INV => 3
+LUT4 => 122
+OB => 33
+PFUMX => 1
+################### End Area Report ##################
+
+################### Begin BlackBox Report ######################
+TSALL => 1
+################### End BlackBox Report ##################
+
+################### Begin Clock Report ######################
+Clock Nets
+Number of Clocks: 4
+  Net : RCLK_c, loads : 62
+  Net : PHI2_c, loads : 11
+  Net : nCCAS_c, loads : 2
+  Net : nCRAS_c, loads : 2
+Clock Enable Nets
+Number of Clock Enables: 14
+Top 10 highest fanout Clock Enables:
+  Net : RCLK_c_enable_27, loads : 16
+  Net : RCLK_c_enable_6, loads : 4
+  Net : PHI2_N_120_enable_8, loads : 3
+  Net : RCLK_c_enable_10, loads : 3
+  Net : RCLK_c_enable_5, loads : 2
+  Net : PHI2_N_120_enable_3, loads : 1
+  Net : Ready_N_292, loads : 1
+  Net : PHI2_N_120_enable_2, loads : 1
+  Net : RCLK_c_enable_15, loads : 1
+  Net : PHI2_N_120_enable_6, loads : 1
+Highest fanout non-clock nets
+Top 10 highest fanout non-clock nets:
+  Net : RCLK_c_enable_27, loads : 16
+  Net : InitReady, loads : 15
+  Net : nCRAS_c__inv, loads : 15
+  Net : RASr2, loads : 14
+  Net : nRowColSel_N_35, loads : 13
+  Net : n2380, loads : 13
+  Net : nRowColSel, loads : 12
+  Net : Ready, loads : 12
+  Net : Din_c_4, loads : 10
+  Net : MAin_c_1, loads : 10
+################### End Clock Report ##################
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets PHI2_c]                  |  200.000 MHz|   50.413 MHz|     6 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |  200.000 MHz|  120.207 MHz|     5 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+
+Peak Memory Usage: 53.555  MB
+
+--------------------------------------------------------------
+Elapsed CPU time for LSE flow : 0.828  secs
+--------------------------------------------------------------
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO2-640HC/impl1/xxx_lse_cp_file_list b/CPLD/LCMXO2-640HC/impl1/xxx_lse_cp_file_list new file mode 100644 index 0000000..1c1a02c --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/xxx_lse_cp_file_list @@ -0,0 +1,250 @@ +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v diff --git a/CPLD/LCMXO2-640HC/impl1/xxx_lse_sign_file b/CPLD/LCMXO2-640HC/impl1/xxx_lse_sign_file new file mode 100644 index 0000000..7e27975 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/xxx_lse_sign_file @@ -0,0 +1,250 @@ +LSE_CPS_ID_1 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:8[8:12]" +LSE_CPS_ID_2 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_3 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:186[13] 231[7]" +LSE_CPS_ID_4 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]" +LSE_CPS_ID_5 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]" +LSE_CPS_ID_6 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_7 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_8 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_9 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_10 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_11 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_12 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_13 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_14 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_15 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_16 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_17 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_18 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_19 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:141[9] 144[5]" +LSE_CPS_ID_20 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_21 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_22 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_23 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_24 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_25 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_26 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_27 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:255[14] 262[8]" +LSE_CPS_ID_28 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_29 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_30 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_31 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_32 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_33 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_34 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_35 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]" +LSE_CPS_ID_36 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:321[13] 335[7]" +LSE_CPS_ID_37 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_38 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_39 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_40 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_41 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_42 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_43 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_44 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:99[22:51]" +LSE_CPS_ID_45 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_46 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_47 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" +LSE_CPS_ID_48 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_49 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_50 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_51 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_52 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_53 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_54 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_55 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:168[14] 184[8]" +LSE_CPS_ID_56 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_57 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_58 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_59 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" +LSE_CPS_ID_60 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_61 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_62 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_63 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:345[12] 409[6]" +LSE_CPS_ID_64 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_65 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:58[17:46]" +LSE_CPS_ID_66 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_67 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:195[13] 231[7]" +LSE_CPS_ID_68 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" +LSE_CPS_ID_69 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_70 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_71 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" +LSE_CPS_ID_72 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_73 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_74 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_75 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:83[6:15]" +LSE_CPS_ID_76 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_77 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:195[13] 231[7]" +LSE_CPS_ID_78 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_79 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_80 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_81 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:83[6:15]" +LSE_CPS_ID_82 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_83 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_84 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:86[13:15]" +LSE_CPS_ID_85 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_86 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_87 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_88 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:233[8:20]" +LSE_CPS_ID_89 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:233[8:20]" +LSE_CPS_ID_90 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_91 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_92 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_93 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_94 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_95 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_96 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_97 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_98 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_99 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_100 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_101 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_102 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:233[8:20]" +LSE_CPS_ID_103 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:15[12:17]" +LSE_CPS_ID_104 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_105 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_106 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_107 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_108 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_109 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_110 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:23[27:31]" +LSE_CPS_ID_111 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:83[6:15]" +LSE_CPS_ID_112 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_113 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_114 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_115 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_116 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_117 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_118 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_119 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_120 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_121 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_122 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_123 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_124 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_125 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_126 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_127 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_128 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_129 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_130 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_131 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_132 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_133 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_134 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_135 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_136 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_137 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_138 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_139 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_140 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_141 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_142 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_143 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_144 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_145 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_146 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_147 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_148 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_149 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_150 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_151 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_152 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_153 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_154 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_155 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:315[17:31]" +LSE_CPS_ID_156 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:143[40:46]" +LSE_CPS_ID_157 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:143[40:46]" +LSE_CPS_ID_158 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_159 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_160 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_161 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_162 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_163 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_164 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_165 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_166 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_167 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_168 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_169 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_170 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:315[17:31]" +LSE_CPS_ID_171 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_172 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_173 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_174 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_175 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_176 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_177 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_178 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_179 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_180 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_181 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:22[9:12]" +LSE_CPS_ID_182 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:47[19:22]" +LSE_CPS_ID_183 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:47[19:22]" +LSE_CPS_ID_184 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_185 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_186 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_187 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_188 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_189 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_190 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_191 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_192 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_193 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_194 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_195 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_196 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[13:17]" +LSE_CPS_ID_197 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:45[13:17]" +LSE_CPS_ID_198 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[45:49]" +LSE_CPS_ID_199 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[23:28]" +LSE_CPS_ID_200 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[34:39]" +LSE_CPS_ID_201 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:56[16:21]" +LSE_CPS_ID_202 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:56[9:14]" +LSE_CPS_ID_203 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:63[13:19]" +LSE_CPS_ID_204 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:64[13:19]" +LSE_CPS_ID_205 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:65[13:19]" +LSE_CPS_ID_206 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:8[8:12]" +LSE_CPS_ID_207 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_208 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_209 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_210 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_211 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_212 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_213 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_214 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_215 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_216 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_217 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:34[14:18]" +LSE_CPS_ID_218 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:34[14:18]" +LSE_CPS_ID_219 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_220 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_221 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_222 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_223 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_224 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_225 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_226 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_227 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[8:13]" +LSE_CPS_ID_228 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[15:20]" +LSE_CPS_ID_229 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:36[8:12]" +LSE_CPS_ID_230 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:41[8:12]" +LSE_CPS_ID_231 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:66[8:14]" +LSE_CPS_ID_232 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_233 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:23[17:23]" +LSE_CPS_ID_234 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_235 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]" +LSE_CPS_ID_236 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" +LSE_CPS_ID_237 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_238 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_239 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:134[9] 138[5]" +LSE_CPS_ID_240 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]" +LSE_CPS_ID_241 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_242 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_243 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_244 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_245 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_246 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:402[16:47]" +LSE_CPS_ID_247 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[15:20]" +LSE_CPS_ID_248 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_249 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[8:13]" +LSE_CPS_ID_250 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:402[16:47]" diff --git a/CPLD/LCMXO256C/.run_manager.ini b/CPLD/LCMXO256C/.run_manager.ini new file mode 100644 index 0000000..8c0aa7b --- /dev/null +++ b/CPLD/LCMXO256C/.run_manager.ini @@ -0,0 +1,9 @@ +[Runmanager] +Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0) +windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) +headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0) + +[impl1%3CStrategy1%3E] +isChecked=false +isHidden=false +isExpanded=false diff --git a/CPLD/LCMXO256C/.setting.ini b/CPLD/LCMXO256C/.setting.ini new file mode 100644 index 0000000..42d73b0 --- /dev/null +++ b/CPLD/LCMXO256C/.setting.ini @@ -0,0 +1,5 @@ +[General] +AutoAssign=false +Map.auto_tasks=MapEqu, MapTrace, MapVerilogSimFile, MapVHDLSimFile +Export.auto_tasks=Bitgen +PAR.auto_tasks=PARTrace, IOTiming diff --git a/CPLD/LCMXO256C/.spread_sheet.ini b/CPLD/LCMXO256C/.spread_sheet.ini new file mode 100644 index 0000000..6c511f4 --- /dev/null +++ b/CPLD/LCMXO256C/.spread_sheet.ini @@ -0,0 +1,3 @@ +[General] +COLUMN_POS_INFO_NAME_-1_0=Prioritize +COLUMN_POS_INFO_NAME_-1_1=PIO Register diff --git a/CPLD/LCMXO256C/.spreadsheet_view.ini b/CPLD/LCMXO256C/.spreadsheet_view.ini new file mode 100644 index 0000000..3815c07 --- /dev/null +++ b/CPLD/LCMXO256C/.spreadsheet_view.ini @@ -0,0 +1,65 @@ +[General] +pin_sort_type=0 +pin_sort_ascending=true +sig_sort_type=0 +sig_sort_ascending=true +active_Sheet=Port Assignments + +[Port%20Assignments] +Name="166,0" +Group%20By="84,1" +Pin="63,2" +BANK="62,3" +IO_TYPE="147,4" +PULLMODE="92,5" +DRIVE="67,6" +SLEWRATE="92,7" +OPENDRAIN="97,8" +Outload%20%28pF%29="103,9" +MaxSkew="87,10" +Clock%20Load%20Only="121,11" +sort_columns="Name,Ascending" + +[Pin%20Assignments] +Pin="90,0" +Pad%20Name="89,1" +Dual%20Function="109,2" +Polarity="77,3" +BANK="0,4" +IO_TYPE="147,5" +Signal%20Name="123,6" +Signal%20Type="115,7" +sort_columns="Pin,Ascending" + +[Clock%20Resource] +Clock%20Type="100,ELLIPSIS" +Clock%20Name="100,ELLIPSIS" +Selection="100,ELLIPSIS" + +[Global%20Preferences] +Preference%20Name="222,ELLIPSIS" +Preference%20Value="236,ELLIPSIS" + +[Cell%20Mapping] +Type="100,ELLIPSIS" +Name="100,ELLIPSIS" +Din\Dout="100,ELLIPSIS" +PIO%20Register="100,ELLIPSIS" + +[Route%20Priority] +Type="100,ELLIPSIS" +Name="100,ELLIPSIS" +Prioritize="100,ELLIPSIS" + +[Timing%20Preferences] +Preference%20Name="129,ELLIPSIS" +Preference%20Value="105,ELLIPSIS" +Preference%20Unit="98,ELLIPSIS" + +[Group] +Group%20Type\Name="134,ELLIPSIS" +Value="39,ELLIPSIS" + +[Misc%20Preferences] +Preference%20Name="117,ELLIPSIS" +Preference%20Value="105,ELLIPSIS" diff --git a/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ccl b/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ccl new file mode 100644 index 0000000..dcf391b --- /dev/null +++ b/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ccl @@ -0,0 +1 @@ +VERSION=20110520 diff --git a/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ldf b/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ldf new file mode 100644 index 0000000..e3d6ead --- /dev/null +++ b/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ldf @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO256C/RAM2GS_LCMXO256C.lpf b/CPLD/LCMXO256C/RAM2GS_LCMXO256C.lpf new file mode 100644 index 0000000..64fb54f --- /dev/null +++ b/CPLD/LCMXO256C/RAM2GS_LCMXO256C.lpf @@ -0,0 +1,137 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +IOBUF ALLPORTS PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "CROW[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "CROW[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "PHI2" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RCLK" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "nCCAS" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "nCRAS" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Din[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Din[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Din[2]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Din[3]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Din[4]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Din[5]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Din[6]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Din[7]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[2]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[3]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[4]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[5]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[6]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[7]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[8]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[9]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "UFMSDO" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "nFWE" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dout[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dout[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dout[2]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dout[3]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dout[4]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dout[5]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dout[6]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dout[7]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "LED" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[2]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[3]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[4]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[5]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[6]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[7]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[8]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[9]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[10]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[11]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RBA[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RBA[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RCKE" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RDQMH" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RDQML" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "UFMCLK" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "UFMSDI" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "nRCAS" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "nRCS" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "nRRAS" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "nRWE" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "nUFMCS" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RD[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RD[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RD[2]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RD[3]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RD[4]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RD[5]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RD[6]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RD[7]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +LOCATE COMP "Dout[0]" SITE "1" ; +LOCATE COMP "Dout[6]" SITE "2" ; +LOCATE COMP "Dout[7]" SITE "3" ; +LOCATE COMP "Dout[4]" SITE "4" ; +LOCATE COMP "Dout[5]" SITE "5" ; +LOCATE COMP "Dout[1]" SITE "7" ; +LOCATE COMP "Dout[2]" SITE "8" ; +LOCATE COMP "Dout[3]" SITE "6" ; +LOCATE COMP "LED" SITE "57" ; +LOCATE COMP "RA[0]" SITE "98" ; +LOCATE COMP "RA[1]" SITE "89" ; +LOCATE COMP "RA[2]" SITE "94" ; +LOCATE COMP "RA[3]" SITE "97" ; +LOCATE COMP "RA[4]" SITE "99" ; +LOCATE COMP "RA[5]" SITE "95" ; +LOCATE COMP "RA[6]" SITE "91" ; +LOCATE COMP "RA[7]" SITE "100" ; +LOCATE COMP "RA[8]" SITE "96" ; +LOCATE COMP "RA[9]" SITE "85" ; +LOCATE COMP "RA[10]" SITE "87" ; +LOCATE COMP "RA[11]" SITE "79" ; +LOCATE COMP "RBA[0]" SITE "63" ; +LOCATE COMP "RBA[1]" SITE "83" ; +LOCATE COMP "RCKE" SITE "82" ; +LOCATE COMP "RDQMH" SITE "76" ; +LOCATE COMP "RDQML" SITE "61" ; +LOCATE COMP "UFMCLK" SITE "58" ; +LOCATE COMP "nUFMCS" SITE "53" ; +LOCATE COMP "nRWE" SITE "72" ; +LOCATE COMP "UFMSDI" SITE "56" ; +LOCATE COMP "nRCS" SITE "77" ; +LOCATE COMP "nRRAS" SITE "73" ; +LOCATE COMP "nRCAS" SITE "78" ; +LOCATE COMP "CROW[0]" SITE "32" ; +LOCATE COMP "CROW[1]" SITE "34" ; +LOCATE COMP "PHI2" SITE "39" ; +LOCATE COMP "nCRAS" SITE "43" ; +LOCATE COMP "RCLK" SITE "86" ; +LOCATE COMP "nCCAS" SITE "27" ; +LOCATE COMP "Din[0]" SITE "21" ; +LOCATE COMP "Din[1]" SITE "15" ; +LOCATE COMP "Din[2]" SITE "14" ; +LOCATE COMP "Din[3]" SITE "16" ; +LOCATE COMP "Din[4]" SITE "18" ; +LOCATE COMP "Din[5]" SITE "17" ; +LOCATE COMP "Din[6]" SITE "20" ; +LOCATE COMP "Din[7]" SITE "19" ; +LOCATE COMP "MAin[0]" SITE "23" ; +LOCATE COMP "MAin[1]" SITE "38" ; +LOCATE COMP "MAin[2]" SITE "37" ; +LOCATE COMP "MAin[3]" SITE "47" ; +LOCATE COMP "MAin[4]" SITE "46" ; +LOCATE COMP "MAin[5]" SITE "45" ; +LOCATE COMP "MAin[6]" SITE "49" ; +LOCATE COMP "MAin[7]" SITE "44" ; +LOCATE COMP "MAin[8]" SITE "50" ; +LOCATE COMP "MAin[9]" SITE "51" ; +LOCATE COMP "UFMSDO" SITE "55" ; +LOCATE COMP "nFWE" SITE "22" ; +LOCATE COMP "RD[0]" SITE "64" ; +LOCATE COMP "RD[1]" SITE "65" ; +LOCATE COMP "RD[2]" SITE "66" ; +LOCATE COMP "RD[3]" SITE "67" ; +LOCATE COMP "RD[4]" SITE "68" ; +LOCATE COMP "RD[5]" SITE "69" ; +LOCATE COMP "RD[6]" SITE "70" ; +LOCATE COMP "RD[7]" SITE "71" ; diff --git a/CPLD/LCMXO256C/RAM2GS_LCMXO256C1.sty b/CPLD/LCMXO256C/RAM2GS_LCMXO256C1.sty new file mode 100644 index 0000000..feec63c --- /dev/null +++ b/CPLD/LCMXO256C/RAM2GS_LCMXO256C1.sty @@ -0,0 +1,205 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcl.html b/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcl.html new file mode 100644 index 0000000..f31653f --- /dev/null +++ b/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcl.html @@ -0,0 +1,94 @@ + +Lattice TCL Log + + +
    pn230815043617
+#Start recording tcl command: 8/15/2023 04:36:06
+#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C; Project name: RAM2GS_LCMXO256C
+D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C
+RAM2GS_LCMXO640C
+#Start recording tcl command: 8/15/2023 04:36:17
+#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C; Project name: RAM2GS_LCMXO640C
+prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ldf"
+prj_project saveas -name "RAM2GS_LCMXO640C" -dir "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C"
+#Stop recording: 8/15/2023 04:36:17
+
+
+
+pn230815044855
+#Start recording tcl command: 8/15/2023 04:40:11
+#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C; Project name: RAM2GS_LCMXO256C
+prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ldf"
+prj_run Export -impl impl1
+pgr_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1/impl1.xcf"
+pgr_program run
+prj_project close
+#Stop recording: 8/15/2023 04:48:55
+
+
+
+pn230815050150
+#Start recording tcl command: 8/15/2023 05:01:45
+#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C; Project name: RAM2GS_LCMXO256C
+prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ldf"
+#Stop recording: 8/15/2023 05:01:50
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230815043617.tcr b/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230815043617.tcr new file mode 100644 index 0000000..418d2c6 --- /dev/null +++ b/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230815043617.tcr @@ -0,0 +1,9 @@ +#Start recording tcl command: 8/15/2023 04:36:06 +#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C; Project name: RAM2GS_LCMXO256C +D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C +RAM2GS_LCMXO640C +#Start recording tcl command: 8/15/2023 04:36:17 +#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C; Project name: RAM2GS_LCMXO640C +prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ldf" +prj_project saveas -name "RAM2GS_LCMXO640C" -dir "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C" +#Stop recording: 8/15/2023 04:36:17 diff --git a/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230815044855.tcr b/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230815044855.tcr new file mode 100644 index 0000000..d2c430a --- /dev/null +++ b/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230815044855.tcr @@ -0,0 +1,8 @@ +#Start recording tcl command: 8/15/2023 04:40:11 +#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C; Project name: RAM2GS_LCMXO256C +prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ldf" +prj_run Export -impl impl1 +pgr_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1/impl1.xcf" +pgr_program run +prj_project close +#Stop recording: 8/15/2023 04:48:55 diff --git a/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230815050150.tcr b/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230815050150.tcr new file mode 100644 index 0000000..d106ad4 --- /dev/null +++ b/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230815050150.tcr @@ -0,0 +1,4 @@ +#Start recording tcl command: 8/15/2023 05:01:45 +#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C; Project name: RAM2GS_LCMXO256C +prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ldf" +#Stop recording: 8/15/2023 05:01:50 diff --git a/CPLD/LCMXO256C/hdlparser.log b/CPLD/LCMXO256C/hdlparser.log new file mode 100644 index 0000000..0c6993f --- /dev/null +++ b/CPLD/LCMXO256C/hdlparser.log @@ -0,0 +1,3 @@ +-- all messages logged in file hdlparser.log +-- Analyzing Verilog file 'C:/lscc/diamond/3.12/cae_library/synthesis/verilog/machxo.v' (VERI-1482) +-- Analyzing Verilog file 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v' (VERI-1482) diff --git a/CPLD/LCMXO256C/impl1/.build_status b/CPLD/LCMXO256C/impl1/.build_status new file mode 100644 index 0000000..67a7f04 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/.build_status @@ -0,0 +1,49 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO256C/impl1/.vdbs/RAM2GS_LCMXO256C_impl1_map.vdb b/CPLD/LCMXO256C/impl1/.vdbs/RAM2GS_LCMXO256C_impl1_map.vdb new file mode 100644 index 0000000000000000000000000000000000000000..b00bbf803d286f2dcabcdfbfc7b8f556ba8e5ca1 GIT binary patch literal 62815 zcmd6Qd3apcb>CnxgN>XSfPhSh;W7(8eS<+40W?#o=2%a*nTU#Qb#K#Em7La=-KJ~O zrc1QY7QKiHLeU0Ek<`op&@5RfLXIJZ%)Td1_cUv>@B5xKi~IZC_1yO!{PhC{{W^cl zz31HX-nsYObI&>VzWeUG?*k`BCo-8=GWbP5^JOPSb6@z-kGyAOHjmAnm~I}OY4SoKG9hN9c=_7ujp+L2D>tuQ zzkYcwck|M%ReArBOolc1jK19bk4!{c+b>1e)*_7<$pnb_O-EOj@7?L1*$hk7ZALQV z$7iQcc+he?7_D7;>E`vDmn6poGR}2;X71i&hmXze#M#^(GMR|hwr|RN2Z;E6M`xCg z?R3wP%-GA<*Iv51rf#0KEJmiH%WIdeZ%ZCARGdqGerE3Q@=kn?X0oj->h2@RX>QD2 zbhuTUYdgBOqiZ|5wxt^_&&`@kMoTW6ZC!KsvANMhZ#iNqr(HIC+1@?Zfe1)2k~{mv z7d@5#;4?2g|I7%x`LMn0p2IUK1amX?zPa|-UA?J@vzcuBs>{7*b1jE!SzNB=uNggd zLN^B5HD|J@!7;|vnx_VCYuryuXpa{i&wUGs(3at zsVZ~w#Iza$Fv#N=4Fa@m4>XV8dt@eL9LL33kKKUj*_k=4lO{;C@c7B)SPLa4&L(%` z_V$h~9LcES1Phw8P>2$fV4=*V@N?;YXezqBwR$^dR|8c1#`%*g(%X8q{QiBS3y6R&=*cWv#~PW69NW(+EJ z>Dsnsx%Ik$sLjo}qsyjnLaB-;o}4~8J^P>_m}*B`SFWszJ503_m`(!IO&-Lgg_f9QxW0&w#9 zoVf)6-(|Mj5+f zpk4s=1E?E7od9YDP&n}BnTNu5HgS;WFSGvK!T8g03m~xuLX2cLeK+I20aiE^guw+0|7w~1Oz=05cEJm z&;t*Rqjw%W`D#3jDo*8{*IGppP9q{F4Ll5JfFA3m4xp};Ka(;P!#nt3M zDS^sey=*iGhUw~6m(L%WKVh!RX7WdlcwoHz=H&-$>tMmC^!GbbrSt-%(hHDEFF-22 z0IBo>q|ytJO7B4`{cEneG(rM`(hCSmFCZwrfS~jOg3=2JN-rQNy?~(f9#Ts0t40}= z1xTeAAeCN#RC)nY=>ISRk0>Lk{Li6;|B;x4|GD^o>3=Q;{>MSe|2Rnb9|tM_;~?dK9Hjh@gOvYq zkn%qcQvSz5%KtbBU9cKCNckTJDgWaj<$oNc{Evf_|8bD=KMqp<$3e>fSjhOFL!tk1 zp!Pow)c(hT+W$CE`yU5t|KmXIe=Ml|kF5oV;uR?a2`T^MD3$+lkn%qcQvSz5%Ktb> z`5y-<|6?KJe{9v%P@HW#Q2QSTYX9Rv?SCAo{f`5+|8b!9KNi&f$JRpo9|tM_;~?dK z9Hjh@gOvYqkn%qcQvSz5%Ktb>`5y}z|6{8*uKkY#VM5@499RlK<$qLJivLN&)Bo6e zDgR>u;eQ;;`yY#<|Izi<{>SE(|ItLo|5(8I9|vmx<3I*o_nR8QJ8A#pO11xSp!Pow z)c(hT+W$CE`yUHx|6{AG{f~o`|8bD=KMqp<$3e>fI7s;)2PyyKAmx7?r2LPCjQ_D! zGycbc+W$CE`yU5t|KmXIe;la&j{~*;v7q)pwiep|I7s;)2PyyKAmx7?r2LPAl>c#% z@;?qz{>MSe|5(WS9}9c`Q(t~_Y_ULM68@*R{mJbe=RaS}N&IBJqGp~)?Goc;Esm(f z5!E=N97mMmh=pp5%TgS%7)LbXhOJydK^)U zBPwx3HI6995v3SnVq^98>Xp~8=@nlr&}_!w^%y*e!MzyVkHOs-+=;=h7~GD*>n$!| z`1%cEa4!b;V{kVHcVciW2Dd|ad;#l7(@w9)mqKtc1REh(55ZapRzk2Eg5?k_1t6v^ z)Gw^3tk|U>IF|&fnnYESs9F+LPof%0)M65~lte8gPzT$sh`o$ut}VOFb+DC!>!jei zDY$+Lu9w6aE48v5vr+<~t&~7$D#xKxiu^ z5ZX!!gtk%wp{Nzxm|c%JhjCx|)tIr=v@$=mU71d;iK@b7g+{0lRckp8wpr zWgiEX0x*AkXDbRi76#3x{6^5 z@1?zbh@Uj;zm6#pcs4udOs+v-f@B)bI=X-%zXFli=pld4%(Mf>-@I~i-a9PI$d%`h zH?b6L?m3Dj0+Y2diK!7DVC$Ka6&VmFCh-&|Ch-UplX!%QNj$>DBpzX65|1!3iAR{2 z#3M{h;t?h$@dy)>c!Y^bJi^2z9${hwuAK?+cjU$u|25f*dA1KY!9kAwg=T5+k9q7VB z%u{Vxn9aDbFvQxhFvQxhFvQxhFvQxhFvQxhFvQxhFvQxhFvQxhFvQxhFvQxhFvQxh zFvQxhFvQxhFvQxhFvQxhFvQxhFvQxhFvQxhFvQxhFvQxhFu>Zd5GyHm)|JiJurNfL zurNfLurNfLurNfLurNfLurNfLurNfLurNfLurNR#Y)3D>aq%)9H(}9M#TePl!Bz^c zlY;A};QA@JUJ7oIf?H3)ZKmKhlDGoa)$e`a&^(@0*;oucgSGc066^CxB-ZegNX-3` zNX!wFNX#XZNX$8t$fYzS=CDah%ypAU%!!jo%$<`+%&`;5iHn!kB0OgPxan!VJbsdSHv;~6}nqlU0 zA=*vaLbRK-1!$}ZqXH*pMUAm0oIq6*sBup9y!ktTOAenrJ|j@7!D{EiEcYJpn!Zh_cgn`zE(vc!YVt?lcVja;D$$LHQeAe_9B<`arW?i<~@x)tsl6^M9!Mpurk z>{OlTOL^%fqp`JY1j4 z!#TP<+^5S!%Um8V*yZ7*T^?@S<>BaE9-)BCBUo^GgcB~0fWzexlDIsA7MDj@dm`VCUSD-`6ZwwFcSXK0@;#9si2S<9Z;Jee&*$Nk z9<-YobJ$udD&h06kq!^*=<=|OE)R?7^00+2zb^8dBERADti+0~#5h)Jj!(}l8)1we zpAW$KWeJWxc+U(8!(lbLl8SxMEm7dL26Y*>(~X<;6T@zTHuc8pnhi9vSM3-c#b!B0 zgf~pC+P6tYv1!gAG0yI{*|N`8eYWDWHJ`2fY{O?4eRj!b7hIO(>@~xVj22O|vsBG*KOR))71h{Ww7 zx6g8WD^+>>?Q5~y3q<1f=%LSYd)t5V_Lpv5i`CvE61T@<@MpQbUn;h;KN#KKzI>aJ zxOihTfsC^mKe;@A^3dGOPOR#g?7;fR>|o7kXLfMW*%_UuIuQ!j;`bAI*zX6 z=sK1z*Fw~0?>*%AAXDFXEX~gtcDXiUJeT*?z&n#xXpCA?=IE1&MI)I3%_J%ANY4`8*^16b+w z09H9YfE7*;V0F_0xsBCJRta;PBEK&31Cj5Ed|%|dBHt1DmdLk#9_>5iDuMP1pe})$ z1S%4!N}w!(k^piW7e)I-eqH1TBHt7FzQ}h)z9aH2k#GBa9^#+1F(DkL03d!>0`XsQ zqkL23*F}CH@;#C7i+oq)J0jl_`L@radWT#kP(1-adaeZ06V(&>b&(&4d{5;2BHtDH zj>xw}zU}j))6M`P`=A+Xxz6ggHG{d9$hSovZ%1w!`q4xFE{DWjE{eN|d|Tu%`n%*- zjnxZ-^xVZ%^!PO9<15G1ev$Bk@k2Y6M@9br6uwmk?)FpU*vltKM?tKk>3>g z4WCC)cj(xx5|#?;1OWB$B^Y)dz<~4shN=fJh&_Pe?SNc+RkTm!J0jl|`M${aM1COh z>mt7?@*6&n_D#D=a143?qtgR0n;w8c^#Dw*2VjIf0Q2mC>}5TKIkU3Ut?X5gv$HKF zX%#A04j+!aohmVLZ;|U>zrN$!sYf!oOWrL{wDCUdrPV9eq))VBa3_R=mo&$=J|!+4 zzjylZ+_ZUR7Zc6-*<(jNIEDdo`-UBjW7lq9-uCb0zAT~9*$4F;6CQdFL%_OggyuJO zWC7*7=NL+?CN4|hga9TkUcG(8wU*1JpSo$=iidJ+n}peR2~#!#W&@Ae7V$mg2aYiU zG__FsB5u7Qp&NFP+K$9K(rZ^jr!NrkZX8{nncd0hbCxrshoWCf(-G@hc!WR#8E2!y z*qNP=5*Wh?6Sm*PQ5yc(3=v?yW}2UE+njIu&G`I7AmVl6{OGeZ-OiqT)A8c}v7^UU zfhki(*Fd0}z@q^axoM$omp@(x7!c`0XIMHiefj#OtI@61 zYti4pUA z5~xX_B7v#|$`UAfU>tlp-50E79|xxZtcPGN1S=s}4Z(52clqTtThH9( z*Bw5;JiW4V!4LtM@xbRCz2A57VF8S7uU)(PhP^XS%>iiTbLq;qhjN`uAGb<64tZQS zH*L3{j-Or%!Nm}4gkU`cYav((!DwHThRs^uHke^f@62r?>u(KdZ4kp zg8=FUP(OgW0n`bgRsgjH#15Fzy#W`4u5keR?5dVH4vm1sbzfps-}Lex$wVJvH{cC4 zbu*!pnwV^6mW&prR*GX;}>w)@e}xepgw zoeSqb)_vxM=L+Zh=i1MmzwkogzUNAdcp^GG*Q_p|m}$;0AD&u26GiRTAlklK+#D{a zr5LAy<5a+-F4VzPVXsZ%t_ujLV@zRjGwMf=KKig})t{jhGkC{Oh;)OGQ-&wf1uQ}e zkshd*&o!H+a-+F?q}U#=OiQ6m57a!XLLCp6h9}hCKnk^lXWq5ubI(0(+GV6#4Wv5U zrY?j{o$5LDL5B~u|4P^oAo_2r?>H68cuF@snYPxYOpAjwMXgAYwuURxawyUR6|X(T z&Tv^(W2~y4RiTXMokJArrW9%k+c;7bwI-$79j^LRV(Qa!>Qn6Vnd$HhO$~cLgrXKZ zfdUoEc;-Arx%Q=8r`oPnX6)Akkq%dTDlzRTd+mWthdTIcF;*qPYIC^Vw-k0CZF!2S zHl$oz!&TLCOjWzCQ;VJ9a;nBSbv&moHxCSNP*kw@Ne+sBFer?&E=r;HhO0sKP=ls6 zd{YO*<g6^a^=2y`BZ6Xcf1P9E!hc2@u~N{8$09pkHZSi6zbAx4Xt^-z6oaY=`CEC3}#tkXs@{FknI>J{3lRar0hgB0y`T`qS zsG}<9pMUo03-ix?%vJ+SE`e)L^y z1dZS{ zdGAw?oqgB)9(nxHSI)lw%#)9veeCg9UVXHP$*oj%ya4;+`F4{kQE67KK46%;){hlx zfl{hkw7RdZx9;?i?5-C5KqKcm(dT1|8XF5s0o!+|#^336yU*V3w(hh#yJfu@u)aqR zhRQ+{yTj)1oj1BW=K6C_pI_;myD(S4yUoeQ*O#i~xmerfQcIB=Aia&9 zV`ukOm+Sv-)IDQF07@@{LRDHLSl=40Z)LZZz7tp>WeO|Jg<7e4u24_w^HRCSW|wM} z-I@DhFX;2h1x!nh&tpB-v=v*sZ>BOBYb^|;1 z*1N6NtAjiJ&E3hlR0++O9mR-f&K2Ox_d&IwN(T6 zav?~qFVK*bcPn%qfmq#|tSrG@x3R!pzzZ~j8J}l?S*@l#M0wZNnp@z#eogc+w%FW4 zNiG3KLuy*E5IEt2;fmDSNDZ4_?^Qgb>h^bO42#`Bbq{GLw1H@ZgGKb`K=fy>pryV z@qeKnM!9=?tXb>@QSMwnZF*HpllPwcydRUd3U}4C%E)_D$U9qD3?idpS=RL+IGS8S zxT*F6m@2dfzRPn3yiu6cyFJ@izBVTO=K%hb`xgo|>C@hN7s37D&gO3C^8LV@mGIK7 zjqGbpx3+@`zY9%r1w9$C3O+1>>uHM(P9`qjUVZ760hY6>`_jF91CsdVQBuoNi!1@6}TrJ`7u|)|w^EbeaoIZvQDP3}5OSfz(wvj6-g%q_Gph z59eYlm{;i-d5^sg7Z5HOz+_mnf{^rFp*H*`Lw$szO<>Exwe73Xwsp~>$z#P{5Fibw z$@MTwQWMH*bFt24Asi$qlv&L}_9$Tnmg~ed*Iuusx!NgUq!z2dpdMMw( zVD8aHmFl6HL_8WOQ*jU~@Q^~!QX|x1yF$Q69>w*L8hlShEe~K_X4vZ64~*jkc6i9P!hAUcHFi)s-@Q&|3V~fRhH-GF z*b6$;EH1Tn>)7jIS59i%55*~z15pl1Rg0}ano~W@lJt&LZT${o#YJt_!?Qu{dXCS} z-!r4O;v#;QwpcxyT&(VXaU6y~*ri##ZhLQxtFF^QY~50Q{K}wnCWBwL*be&Oq0_bM zeT%0SO1oS&FO|YhFcGBaTx=PPyL6Nhzf|1Z2X;#_cHF9?*%=*%qWcyX z7UU$^Ed1`R!NrYWs;u{V9$h}tT%IdbgN2Y`h_~1YS3%TvPtDD=cT==?0#8TMwijSW z9G@7}OS^pHipM0u_JZ-nbIs}A3oCf2yf5tV%z;D2j^6QxVYeOxlzSbhrNuC!G%K2z za@rNmO0#~hfTx^(*zT1lHloPkI-^4Zyjd_K8~%eia6QR!k0!a;3pnc6CX9tz8a}tpkehmQBCt>`(Zji7D|8B`i}$)Z zUn+-w;b6xGzuf$^7}(_@u`I3!rnykT0yW-nJ$mE;zxNA$@0}6WnF4D$4F6E7hV4F} zc64j;7rXnwuM*>@wsi;HjR&Ky&Dn!$9xz;Uq9!WNoNT~!!JOE~=UB*g+{cRDU_!aW+bO<57zWWni+lS}g?g+Ce7VP}boBN3}Z`Isev<(4k^W z*he?rZf|%!!UMxp$?kbFhOJnEA}yHNQD=YHRb%XyG`m70lT;>{gY{%W|Pg>tAiw3ymNXwg-(qCzzoq{CTg?*wCXvVk28?dsg;oG_ylGk<53 zuyHDQjm&MX-Rmf=g|Cy1;jMLyoMLZ(xYc9a;CGZw80tzVmiDA3;h~$=B>7r`5H2=u z$oauTryI5V7R#rWcKgH^MnF`+JOQkh@%DOQNiwpXxYxN)aWi08s9_>9H;c~(iHQg{ z(>P_y!juj3VM?hQTVmJq>z;egEO<}g5li4)hZMk->M<)-H%4)=KkOPYb~VFpBY32| z*VUrZLijYf1Ta`UzzV+faC@}DJV4qnlc=?+n%Ui7=L2jT4vYT8F&g_LV7wg?IJt@u z@aF!oTZ*y6Y=aA&g<8xs?QJgzp05Z2&+AR9*rKqG*h1~G-@qRG)oVu1SYL2scC4UH zXDo2qYb=2YvaAu~M76HFu|HB?h)EeCu#z&Kfk`#q>yDc=DdUujbScAlIw?;SusY{! zVh!}3r923vJh8zQP@G#+z&5*m;KsA){V*OcVN=`6p_xJ>TrJq6kg?fSFfpo(XFo9^ z7aDTG5l=DqHh?e_Pjbb~BF5DWAiN~!yB2Rm1&(J(v$|4jR);4eoYmo3{C;pl5D{2K zJQz`P$i<=d?Rr|@;z3(X%7xNU`xXxZl6{NSt{7L{x08I~Rh&H3+J_~Ia%_o$2j!SW zna)12!;T`^x9YSUvm#OnW*=%rWUnvpVr#3A_T0Lg&FVc}e1+Udnk(y0(i6qbz9@Dz zrq~GI)G+Gq3%5#)8=^NgjFzOF_iU`NRZEE2m`F^pVhUYY8mjlh^WY>`tWn3fn$G3p z1J}8DNqAqxU5kkuv7GAM-o9|F$G9PsBRA7vKEH4co+xha&qNomRm-tF2KjSZy|F*s z7Gm6BG}ZFgQ1uEMrILDu34Bbi3Ja2}e&Vv;~1+1q6_+nOXNKK)Sh>mEv^S+d#~(Ei{YS#4uF3n!QURS zn#Hy|8Gr4W|5A*9o&4(w{`OSYES{zfmH$GFe}nvSv`kF?_8?j8qSSK^vpl-z_H)|; zrYd%66fX#Yeui~iTtYx{`RKK`f&9w}{`Q34Y_U6B z{*@U2QWgA5G5+#U;B2uUtHDB<$6YM$^0O#F%#y%>6;tuy=aZ!`Zt%_Br2x6!vbam0<3V#fGsPF7tAXc{|439>NVP z7chP+-l2bW<4$L{TY0M?-*I{uoG+utw>a(_)-B-s(CKQG@5n9Ib{AZfDk0-ZZCJ4Z z!?Jc~i^Hr9mvt@1TH92?+8tyLqZVVmRKBlKK2_c2bD~l`#v1c~N_^V4+Mb#YlQvw| zjTmc$$&$4{q8;{ZxSSV5&J!C-w^z4p1Zj_hhbAJ-#3IYq*T7F~-_i zddBus0We_0Wn76d){fFMwx1<{`5G?cT8y!FlAf{s1OklLa2eNQjJ1RGjP2(ZV7i9O zxDjKloug&!KJ5U*72~^DzOPa~g=hP_Jl{XYmth#sVbF%leMSOyE0u43w|tjU`0{um z%h!Ce0%j}5cLB%S)pp9aJO<2`KHh2kr^f6S{Y)#TJDQ=Fl z`4$K4R*dsP<-S^F_ngbAoWad-b|3zL;firCR~ZU4b{h&*Q#dPbhO_(12rO5?`K@C>w@dGM`xBq?$tXC@U z+HQH*Q+R83hPVG(3k+B)@A__eH&S?OcAB^QHVjNyz`1!En=zM8?eetX(qhPWg7W4Y zKbouj3Jq*n!1$rlh(xe>Sl{hCxJx1HDIN52tAl0kzj*^gHeBWlG3Gk(lg#}Wc3{l( zaXa3a?XBe{eI}4KW@gnyGWXx}fjt{8^Ky*24ge){|Mei4wBa(Z#+d6MP%`)5DuPuT zF7rx^xef#+bN^)|7`EXu#}Tl>+JO!RC3F8BCRn!NGRHoxfVmC`C3FAPCz!V3GRF&y z0dpM`O6L9>Q?PEsWxg0=t^-5K+<(yu7A}?fZqMc|EybAYmcM>;Yt33X|NSgjxZyHi zh%whK_sqrDx?te+;YZHEAuNVzZ|rtixTH^LvIcHaKNGre&O8zlp9X_@8!qc|jJ19o zBv`xekiobOmvuG9T0aRAtldY?VA_Vux)Nip9|8&1?h9)$Y{O+;i?Px@QO=aA!t@!FQu7EuXVP;f{h&!dWKwE9>0U7D1(UvL z(p8gwrAaTEl-kAXE}8TbCS5b>Ws_bp=~a`yY|?8cy>8MQCVj=E)LPzu)1(v^;hsq; z7s6j<(yuWoyOj8wCS{ir-ZClWO8A?QX2$f%Ajt8Tqui~|eH7*Fa?(>}6n(CPkDdbH zZaV09X+C6v;cy?0#)S?%?;0+8*;eu3Z_)s4WzU(Hl?UpPLVRTql6-5g+7UtqPdHd z!|@xCX7Y_{#hJ!Qj*5?%VzOoZKa7-@TRhniPc}?>d#1cSZ_6|@(Fz-+4Avi@gm!^< zW&?O<_JX}L8^#9l&MapG$eA2S$2;?SrnDorA>Rl%lds?~awlOn#Ij+U8Pl&#BFCRn z0;&k*M3v#~wW{#s29n^XsH_w@kSIMWHarH-A7s_|D^a6}X5Ba*c~g!*67Vv@Oj*ux zMwsJ_(&G4H%5intq?9Jd7uj)K@wzrrwwZi*y{c@U#~|8jDD%T&ijM3uIUZ_*l)o%1 z$w9)Ks8ZF28J6Lv^qpw(=9nfKdGqeN$?C{OK>Uqz$g!BbSj@}56=`OQkCSewPlEvB zFB{?SD^T{iCZ$<)Uz>*bsO!Iuat?3y6;rAPQ>q42_7PKBU8cMrQ+fubUu{wjHdfu5 zi#H6ODnhz%HYt5wCih6>`dZ0{cYPEEKg80pcC?Dqcah^yl~ds;d_8j1Hw9E-CNod* z(#EowIzWNEXke!7Ti%}Xq;9ZJnUbE@5pQ*aDaQeIgypowET^vUzUxS-Gfa8kK2j<$ zZ7Si{Ov*5WFe3=2cTCD=@cz^x-sjtp@>A3@!Wd_-jKW#*#*{i!N}CtlLQ3VNw3%{1 zGNrUL`BHOsR9W|UcXUbMuO=n8xO1(z$-VpNq zO;F^#m=|3zDMd$O-h`rKN|-kx9aAz>H_PLI9B2Eo5ztgWs;M#=Gdzv!xc^vQ*>WBw zDaR6pN>ZlO*vtX(Wj%oWDI-E6vSrF4Lra&*wY>*XRL=p+%G#6zER$<_Dm6-3%BC@8 zFTRA7^3v4&yf*;;aum>)qm=h#${LW0f>2&5hlATKwHng&hrBma)>GXxU#(WWWsMA) z3fu!(W{Tevy`erZ0*JqCgg+V+ic;AcjCejF1jwJN81bwKQ{IcpP9^y{q?sx1i@u?r zW&+|b8{v;MyeHF){jlA6=q*k;V&nKzu{5pcTL5r`F{N5CRTrW%d`t?EKc%6T`Oosk zd7Kg*ss)1|@@1OIFW>;)3&`-N;z*8PssM}GBy!J8`SZI0@mFMjkcR!il+9+!-g^Tn zuVqU79g}jbvT0Ow;+YbrK_kqRFbx}Fn|>?c%)}#+_~<;^%0WG02K6UMG3CF}28cf; z4-RjA~KGL-e z{#66hs1eTqkg7-{#`K$z@;*$-_gj!=@^ul#Wa<3Lj^wHZ2XRcp4f{C?Aol&LQ6+8|Jnax$ zLzB(cGv#$O*-VuQhT{1N5tPI=8lrrIEgjqSZg_pB3Oj%jphIq0e ztSgD7J6DU*2xyY?HuiFMe1?VtYaYn)H%a{+Gx|$|OZu+4t&KPa_AzDsNym06g`dW`lV{)k_Jqv*6$*p_;rF?gviA4>SnNXiXW^urr*WKngPTIWJM#lVyd$cV7502yQsG;sXy zas6d1fc&W#z;frsY?c~_SnKjmPj!Ul@ol_U9P2cM$cv9XjArNd~NjiTwLl-MZh4pRz&rk2vR<3}}iv{AnR9Dl0z_9nV| z)gbhpqLmqemEj0x$V(}7kP_ZNO0G;<3p=IyYQSvHHd4}alrmL*7;{rEJvBHuomqMydhJmXit9f_Jg7>atQre-}6wK4l|A z$U#O^lo@XX(or+{KS2Teg2s=E^)aNB24^^gnG&Xy2-}nuC7x0u-b%}+-w1qWd@*1+ z#_srI6p$eqF|~{+M;b@ofT_AcereH*TM3Hfl*HE}&E)Yupr4@7qw#9$;CHY%*WcWD z3@LxgoPIm7X92L3>35p+yG;7sCjB0hey>Tt&!nG5N=L>wQ;_3N1!BA(xqd&(5Ac1W zQZ)UU+R++<*g(S}88~C7+9U0jO7+%X! ztcoXkDcpVs6tp6wpkjSJQr=LF=dn)o&c`0U2#`P34IJ;(Y%+%Lj5E9oG@GZ3mqY}n z^pj|gP*ptE3+_$@Wg9urRrv%L3;8S^2>z5Z{ShcA6-GaLE{`_`Sc;#jAPd+{KS%;r zFtimMSmeNzlA+yW`)`tbVm(Ddzl9P?rjL{@r%c&IH3ShdC42Dq42A7Ero02w%ve8Y zHFbimW*c;QD=4Q_=+#+gRi5W}QEVrVMnE&nVV5ywll0(U5KjS=>}g|J|MN%@9M^>M zGj^uj*eq3y9qY+v{Wd5ldMgOq*Ge%b`YBiZuDOCr#e4G#)|6>xY(3FXij;!T9=6W8*lo(TvNZW8u zGpI96$?G;!I5laEBU4N+Dj*y;A0`LPpQ@`3FsX~Y53P4*x{pt1yGb0*P$oHk*$986 zq;+AM85<-7L;{stwa`K$@B8GeQ^fIR^pn%$oiHDaJM;xiCuk@y@L3 z%jymrp~~lJy?+BGYy>Gd=6MBm=nbU2k}2=p65fTJNl(r{qRKY|&QyJSA6@s&kn<=x z|0b@aG)T$8rYOfY15S~_lhcnXPU`_Dw$W<2vTqoqvZlPAcwYZwygpx*Pa{~&0mn{K z12606l58XceJZ+&M)M6ZVAO1q3dc(sgK~VSVL98_QA^cDB%+p5rI{)LAAI!eQ%{|F z*W2H>?FW$3HR>|Ehbe`mr-0RXO<2sDP;*J9<_44c^aCG!D*l|zkc9CG#m{gYqh%>( zUKv5MO>7&+c>1hXnR8Z&4SC6=%6#O@@hZN8Vk#7id1H1PCT}7(&PKpo1Dd0hX(o?% z*`0|~6UnE6=3SUlO=-#~A8pcV@tNYYDCSI&M>(~zh&5k8`X12WJh*W_FTS^6H%`yn`Wbe?x&@7WDh0Ai;I}|AK?42KH zdA=53L8ri=EM5!ZS&N@g<=xnn374EWxY<`Vw5U)#NvzfM<-)zd`%_N@J{}jvf_%fzb%WMP;0|r);)-7{@hXI6h zH?=c~){#2PaZOdE0ubiK6cN+R7&wc^j1(b7%yN1ZmdEQxJnQz;EYDZsw(D7-c{x*B zVA?Fg+ICgq#_1f2slz1C9H=H1g_Q1c5L0(Ak|@6@LTy#N3N(ie*E=)$@{*7iC$Z~5 zvnHxIH|VTe>!rHtt5C`j$&^oBN7xW?xd3dHb&*LDt`#gNA*;nki3} z-E@pu#zD;yqspdnfLhv$YBn+yY(68?Ol~t~G(Kc_Fr}b*Ki-$725Xd}x$IqXr8cPM z<~Bts+rm-`Lm3>*_uU&_z-1%+(T`Iazoc%yAui|5zsB5LU7lZR)I+sp9LI6PG&AYG z4FZ5a)f=>z6c{aEX40M7%X0h_39G>N>Cva+TOUrSZ3w&x%_f}|Rt&nnPuNCQl5J$l zfY!ZB22iP!ZR0PKAYYd@g8fDt!T#>B7+(sCc^~D#Ifdb>pdEYU#TuzGhqe_YIwH$TNpCdvq>*lo zL`pQXi=W-0kce9O5i*?A2k};X)WDHP5z*u*cbV&o8dF>76RC=-#<{*IWj9%m$rPKT zL@BTRCUdPW9f(q1%TmgMDTaV3<+U_~cl9B#-kh zeKG4mk+b-_R56aG_r<*07Js)Y#>rT|m{(h8|2?W0TXKCdueQbCtBP?lh%e^Vp9Gq` zzfTv-C65T`*MX*?VoHk}Uzuc!c=>-)<*h_Ho5b?}tjarya<+-(|3#JaYc1i*CmY4` z|EkJ)zGGOuDbM5o}<_n$X>BUpCw1xPMoCd|n zJCXa2bW(e49H^R>RE_iGUF`{PAbqPPRbxI$Y7b)r=|h%OjsGO6JvR-cktJ2OAW3SE zI0Na!mXsqXMFRFTGLXK_k}4aKysJGp45V+jq@U(p52whLC+?vLzma!X;_pu?Dc(nO7kGd`qlsP?Ff6Q3c{hEU_|3Nn(Gd6o}7SVr89@ z#QqE@5I<^(m8nV+`!kzB`~{X+*{#{QoN@4xk?}h%;SV5_dDBx*KK?}X$eAxV^W@q0 zM~^=h-Nh+A7q<-UyDY8pg-Kd>kP#~IZcF=vJKWbE{{z~`EbR}a)3yceU$V46OxmQb zEu6BuSV#V{CH;|fQhOQ?YVcPq>5rz9+VgWj`d2OKkEN5^6K_EJ*DR@81WDG_o>2qR zzivr?JpHcrR2h)|4NLkH>7@1?7?A!=OZt=Pr1s<%kp3-8`cvto_N*02y+i zItobtwk1^)uDQ5&`Mq-^f5%e(EN_~i^v?iC{;s9`xpYeRz;fj8S<0U$WkUY$ln+$& z?_1Je*n!kNDjoR;mh=}>NyRK{d1%Kyj{miAXtX=R8q z@}#Bx)l^!!+A;DTOZ#i2P4t1^Xg%^pr2GO9{W>X=wrJthg>%zKQH0;fKeEKXkxuN7 zM*#6Zw#2`gPVA2}0P%Y*@o%LQ`{M^d{60(k+v&vqxBw78Wr=?$o!GzL590S*;@?dt z_OIiE_yd;s_tJ^|>+>M~Czkm4(~14-?jZiBmiQ0SiT&&8ApT-Y{D z*-}b(``5og{Ld}%ACWkr$#>W9Ja)!xUKsfomiCX+X$OM#Us~EfNvCx$M57M>%F_O6 zI<0$y8MOb}(takL*1d8J+Ap!R8N~D{ZFBDkgZ4`;E%*PV(7Km;LHlnkEti~AXx&@5 zp#8U&mRsu6tQy{AMFD;zUuH=;1xX`yPya^#oh9WHz~tEXJ10l}y`|*t$t0!UK{)as cEG6GmOSVexCm#8amX>>p)i1j511CoR4{Gqn*8l(j literal 0 HcmV?d00001 diff --git a/CPLD/LCMXO256C/impl1/.vdbs/RAM2GS_rtl.vdb b/CPLD/LCMXO256C/impl1/.vdbs/RAM2GS_rtl.vdb new file mode 100644 index 0000000000000000000000000000000000000000..c710a280429e0918515e9c2a924a2335b80612c9 GIT binary patch literal 74340 zcmeFa2bg75neM-LovN-}r>eW5n&)6tn!_-?zTC_uAE`8SdPfdG7OnZavR;-m}*G zt@y39*Iu>G9xq*6>&UV#nf@9-eDm5`>+=r!){F9d$F*IpPkZ4pFTy`-3}lPhvMb*= zebG6W*H-PbKFjxA=v%pV@1DJP8s4RUeea4@YX^G$`$=;Rfk@Zide`haDwvHZr{J}?TnVNdi{8NtHa`2O0@YEL^d+3(w$+PFS z9C7q9M;?6W5nB#B?AW8Wd~nnHO^fr>mwn=*O&4$3eDTLNZ3(&Aa>#M-KmO47Z8`S% zqYppwxWkUwyyfth9Qwk|haY{}mJe>;Z}O-Y9C_%L|NVgNXP+^B=4of0nq|3{`fm^F zPlZ0^?8% z`k#-@2eUk*%4;&ie>{@ZfO+2Exq6^~&HB~*?6wl?R?M4c84ch;{A*c$3aBjPC&n*l z+Lspl%(AXyRo}-SdgP%m{8;zO_4{lXSh;59`qc;Ijl-qzFp}xWI;Xl z!=n2E((&Vf-BuRkN9V(gxt6s|9c(e>>Ll@7 z(YK6A6Y0AAvc{(KE;#S<^FNb!{}-jvy?)on$AWkz45-V8J{7Y_FDk#!C*K#6?{mrb z>E!!l@_j1#K6BL}UKzw+exFaiFC^dRlJC>W_sQh@RPjAlYfFBDr_$c>M13QjCrKDV zo-BEa5yGcRo+hDb9VIzh@^r~FBm>1T_XN4hVa{DX%(=^lId}Om z=Pn=S+~vcZyL^~)*VZuT9boCz>Vv1)7k3U;ox@eq1qCAnIg&0$m zCo;4fV~X-bhSp?EQJ%=q#*8V-6B$~bF-3VILwhvF%F{AQ9Q?IlCj1^R`JWO^#ubj3 z4lKC23P<{c`zJ}(vQXj3HQ@p`U*RY#;f|4HEsGV78Y0{=lB{K>!cnh;d%khA6%K0< zE^u25ZiD*7zgJ=Ue zQYG<(4AG8ONj&$HyhxJO#!GU4_k{dsBgZ0{KU3};1tTi6U-!g@Q%{)NvT?)onP=q< zn&QKlC%UpOt@fC$X&{PQ-(z3nd+c3&kNt`7u?O+}KXYJiZQH0^oF+M4@@~l)l43A! zZDSh7u4hZ$BRNOX^`ATdhjFyU2Vi&k0PL>j18^87S6ZEf`pk05V`ISgQ)^(Osc4Iyem{{{!PK_Az{=h^#WVzK7BiVU@iB<^<_PinAA_s?{qKK$SV~QL^ zhUzt@$U$VNbYqGfLwtd_TWb++ALW*_7D@@ByiQShx7?|p=9aUL$2X2Fs?fG zP*&m$TsihI6p#+#E|R2U4;=c03+a_(4;+4QAzXFr!H*7mu_PIL^7qPV9oC2}Yb%$l z?W3W?=KDTWN6mX5icJ=)t<9H|Cz2uc>$nIqXLSMl`2BWSvhG`(t3?x`j2t?GZ3{4H_MEO9R`anCPtFD!A-EpbmTaZfIBPgUIQ2d>-qgy|Db_Udgv zaH8rQt2)Q4&e5uKr0N{1I)|&y!K$;KI%9KdshzrU(zDju_9=b)wB$3At0Y%TT9dk6 zJNQ}oTqC(wa-HOQ$qkYlC7+YrB)M5~i{w_x=Otf|d{J_nV4E?>;M%NO(R^2NNnd@ga9 z&n52ixg@xX#k@P?V&0u`G4IZ}n0IGf%)2u#=G_?=^X`m`d3R3u+TNY(s?Pdwc*Jma zu<9JHI)|#xk*agF>Kv~+$EwbWs&ie{Ss$wAs^V-s3A?3ZSeDcN@=xmH!N8RxT9(r; zTi|{r0skgZ_;Q@fa@uVx+>a&TFC8Cn{Hsu5%F!^(Y3Cj2{y+lW>v*5zFC2g4_&dix zI{rndILk3L%jq}$#Pxj%c#q=`9e?Eb6UU!A{><^`j`utM+VS5Uf9v>r$3Hm!$??y^ ztU9u1Iej<(gg%^2$N4O$SLYuu*>u#;@@ruUOA3lPoddF*k-)+_o6ZPX&KO}~$)&=k z^Fx+1dRSOz)7c`+Z;W9nslujnN0u|Qm%W_6)3+rq;<7GKxxP_$^ zD{MOdWjUj}g*CP^8)o?(F(@4&tIUmA&U|1YolIuREN7yyMCnQjnarD6{*4&Y$z&GI za;6pwNoQ2ZWKPX;<{V4Y$z+Dj^1EY5y0bzi^KF(hOIb)Kli4@RnZ7Jd1_Xsn=He`8 zUbB!!CJXZ`Mc_xTWOUMOcQl~C7C2I(PX?}Bn8V>mI7Y&BVGc*x;27z$mU3YZM~x9@ z;L3$L9DZ;i&T>-#4nN{#bk17Jg*hDdgJVR^TFQkv9Ib*ljY~HLAn_z1!+2IpHU%JQ zi;#@Zl}!Oi8adGhGT9V>#1k?^n`{a|;t6R5sU@2Nka&`&%}?p303@9fl8GX#6`KOV zR`hnF4dg`JF$g4{gnU4f)z(!>#u&)o8Cf4b3)G)A0R}Ik4dh^z#1k?^J6t94BwCwB zYeQ9%@f4CdE~|}H$v?=CXahM~CGjMr&9t@gD#`Q!X;WrxtV%K~5p5tRswAF}A=-6S z5>Lobl=@JmhVXR%{N|r+(i$2qlOoboyqpW z!`+wH}&lcUt8{|hignO=qD~D$|^a&TZa(ITrZ$IJRS-3bn=SRwE+aKmH zo0PqveZ;pv8qZX?huY-GS3VS*Y=N|8`N@h)NoKWoo_eBx%_rlRsrY4!eQB}J%3etC z-s{(_S+Qg{q%~``w_tNu9pMqsw94<3$@i(^JNqTaC%Y%p71w0NHI=wJLb$_U=xJ%K z1e>@mY~r@ig}d#YC!Sf9o&Cn=dtu3R`F%3^J{7;Wmi5>Aiag6+DS4IT)sotD@gQGo zeT_U`D|wyd^^!J`8)Nm>THheAH%i_ld9x(n;(4gGzE#e*N!~7bheX>}en{Xrxymua zT|Q>G%OALdix-p8Bw0>&^W*h#D$$e%%5n-}%)0^;&6VX8&6sxvCK@lxDX=l8z@(|~+R3DZS4~WssSx%i8XKC>uSaQ^rah4hnbR|a}8fWQMn?RORo%zf3VJTJ{M3z(0 z##)+sC`+14mSX~AEmbX^E36rZm@VC;>16p^gaBpZZiCI6C6c7v+tkl*Gdr zA?U`vS=)g_`_|(q(WWJK;uuUF_0%!6?_e4xaSWzRy>ztd9N1x@^wv&~vF{w;iKi*} z9?x9xed;RLskKbS!KK!^S=DfXKI8KL#bmpbquDCdg@rG2iYKIHN_0rLL_13Gbnp8QhSI;KjXOi##`KMmYDkl{smsLuKtWr8; zmC_-rlnz;?bjT{DLslsrvP$WYRZ54fQaWUn(jlvqj)~MEtCWnaQaWUn(jlvq4q2si z$SS2nRw*5_N_1eAL%edZO8Gq=(ZE{&9cP8s4qm0cd9~!Tl4~T_O0JV!FS$W-qvUgv znevOY%+0-I8xfiYKnM zgWs0(JCg58{#Eil$@eAqNPZysq2x!BdnG@X{6z9o$$gTaNq#Q*h2)o#UrFwl{95uG z$-hZ{EBT$|0m<(re~|o9@+ZlkC5;9)i7U4M=u@7D``Kv^)$E(h4`);D^C6RCQjiq(!@-$be}P{rCO%b8&;!rnj?E1@iB z;xVcxP{q0^%bAai>JC(~O42KvNOc9OSTpH;O{6-Z$`zE})kLNvFmXMl_cW1d4@_KL z=_O5MmIWrRwe*H2GHrn=kB%}|TE1HY6A!TI-ArU^fhiAMF|S&fmcW$TgUq(Zt?X5iV)8bs>{XFsPB*ITRgq$&Ja zkzxg4RN1Q{#lpa-vR6fl^@34luZk4Q2&2kg6)9F1MwPuPQY<=*DtlF=Sc@1{_Nqv+ zL@}!DRgq%lVpQ3yBE^EnsIpf@igk`rWv_}9%O9i4UKJ@;MMjmqDpD+#j4FFoq*y~4 zRrab#v9vO(>{XFs#bs34t0Kih%&4MQ9YS-GC(AQqie42N7H!59y(%&+<%}tMRb*J; z8B_GC$gu1)rs!3XVKHb-(W@fE6498VS4D<}qcKIViVVw1V~SoC85WtwSg%^L8IB*D z(`#Gwk-V!sm`ai#o6~`-ZibUS;RY>S^#C)uCS2gk&2ZwRtb`l3aOGw=95qC^z?GZf zaMUZ|Ml4+149{BNum<4*SH7!+!-j<0gK+7)N=Qskz(6MNDj{hxgnWdBOb#$Z($WYS z$mCrmBrTMXV-_-bR|!eWCS)L!ca@Oz2ttlq$m9SsBt40cflS_2Lec{Xxu=Cp-c>@< za|s#9Ol97p!flS_2LNcNea=nF2 z-c>>}5)v|y$-7EOMo>cTYax?&m5_|QgbZZzt`d?Fn~;ySkjcABNJe@>1~Pe93CRpW z$o(v2@~#q+nT3#n94udCLNX%}a(@dsTqT*w2pPzslH}zNeU6Yr7ILIY(y<5`$k8f^ zCn0yYkmFU7t_8Wy$gwI({~_8yPE<)eAw#t5swAF7`zVXHK2p5Rr6}|+$WbE)t0WzW zXahN1CGjNWBQ4}mm81hfP8c~-CFvtX8_3Zri6>-;cDzdB2^oqqRweNy%?-k=Hc=(% zU66YjxvommfrvJc_0dWV;YrBHSjfRDNe6=5$H?I-NgpBFKn_(&JRw80BUKVlqCL=} z9j%gdAjroVIbJ2{BSag>u_}otAs=rcC#ocU1o8kQ*HuZn0nrAsK3=IIJRw80gH;kw z$WWBwDv2j#FxgO*#FJO7PY~+NL?rXSJehO-f6Jn@Ae{_z!`{;`kpmG3ll!mH|38BQqTn zr^=c-Roc?IOy!L){&KxqoUOQKDz3$fYrf)IsJQ-P@0vTk4mM7?ojbi25|2<1iASi3 z#3R&2;t^^i@d)*ic!U}$JUT+16z{NgrjgPmZmXBXZ8ej)t!@&x)lTBJ`bpgX2k+Fa zV{EYsYY82rbf~gQhbpRcsFF&DDyVd*a!Q9PCOYUC&(HYd?ci+keJ1(7n0%j4zAq%- z<4e`>_OXmJzMu_nAKkw^12C}sS`9VVNv@aNAh}WUImu0unXyEE>XyEE>XyEE>XyEE>XyEE>X zyEE>XyEE>X2j@2PiuMFmgLckhH&s(Q%V zH?NF(7jAh8|+tF=7COBx6g1O@ z(bgI|y)_gxGm6pH9;)k?EN8AU)>=e$HIwDPh^)1Vj?gB2ZIb28PZri%h5kb$SqWu1 zGncW}E;>THD8e$Q8EY*=|DjO{%WP+?wT-2R%$Ns_wbrrpkQpBmrKpNLySIZGv@d{!-%z*){p$|#?Ui=}dwv(Pfi zXYgW4o#m{q)-H7m|FBuORszUpn$VzGmcm ze6h&)_$ra_@#P`k=VSP&#xRp>*f~Lg~YR+SD7 ze5FGJWa-dAS~@h~mJSWfr9%UF=}=#Z4yRi zoFF+-a+2g^$tjX|O5P8e930X1(FLT7fCLbTq4;bnUqXPrX@3yt&&;E2PJcodC7ugQF5u|Ly`|m zJ|Zd3cCQ`0OwNx=J|?+ba)spMl21rJDY;VeDaofLpOIW8xmxmB$u*K|CD%!=m)sz^ zQSv#-O_G}>w@7Z4d|vVe$rmNJNp6>XNitY$XB;b6xt-xI-_CHC|I3EEd^^KkzMbJN z-_CHCZ)dp6w=;sP*v@cg+|F=k+|F=k+|F=k+|F=k+|F=k+|F=k+|F=k+|F=kJOJp< zcmU9y@c^JZ;{iZ-#sh%vj0XVS84m!uGadkRXFLGt&UgUOo$&ymJL3UBcg6#N?u-Wj zgR^04nq)Phf1Z(r^W*jLZ6sGkQaIUvT!Vbsq8l^hUbKr!mRKqUvn z7-x+7X`qq=Vhle<{UlJy0Wn4;qkbHy6X(bTAa4OFq_ z%5nx-qrMAOuE4UKq1Tx21SYP>vYY|gm~RIruFiCaR%E^vn7CHc9a@pOJ1}wOraQDE z^Uc7-b)4?dip*VsiK{x@p%s~L1SYQWH26m5&cMVKpYG6#%+~`G*MC`V69`@B4wz&$ znB`0+`AhUs_Np+`WI1z;QDv`+)O#aU_Nqvo8>zBaMT&{aA}o7Vq?o^qDtlF=nAVIc zdsU>E?TjjWRiu~%jVgOpq?j9xDtlF=m@ENsTIdRiv0;jVgOpq?mV&DtlF= zn2wDqdsU>ErHv|kRiv1_jVgOpq?pry zr02y5h9|+?QgNNG7Y#9(F}38d7{Tx)n43N>_4Vc=1~aCXoD?G%o&@u@6rUFKDkKIo zCcV;vV0aSD8|Q3cvzucuV`|A6F@oVqFmLVgnMH4FVlZQB$pJBf;Yl#-KDI{?o_q8H zD26ktmK+Zw9G-;p9$7p*>77yxXHx`{oOkl#2~4l4VmPDHYb*$dC*geDC?4bV z<|~FXs+JrKBOIQD^P#AC7SzkM7|y6#ax9E+coNP>x8i|P@8@DTqiV^aFv8(UI3F;J zr&9eJKn!P;{*$CQAVWAj3Fl*Q@o206EQsNZswD@)2!|)(d{{4@kM++AF`QAgC9`qljF`QAgjyqm$*A$8bi~lA~XQ!;^5n&MLNrvixH)oKdyp z;1}WWB%CkZ^v^VLeEDb$XH+dY_C+{63FoUpZ5zgLm&I^KmHWwhB@07fWAsoyn4J6S zo*N$8fSi2t2@m@phxz~bHm%j;+P1oziT@!sp$7l>J?=}Cm#gP3uW!}%jHK8;$y?qi z=bI$u|DlI}L5oKr+~s=*e({U%9fbd0>PWJdzp~yuq$;e%Pn=xW0MJ9+D0KUg}|D0X>zvm=d^$l#UTjKsNK0(Iw@blF&WPDXQA!4;qJsm@1GS2FudOC(iW}MYT z^>hr4&p4}#>ggC7rEyjp)zdLFR^zNbs;6UU#Ku{TR8PmyxQ(+qsh*CZ(Hm#AQav3* zXE4s{r8-9GdJ|aAMOe*LM=afN5?QO8rKd!;MAm9&=_wIV$iO|oDwVGObO2kG0YQyTPa!O=Q0lPSz0R<8P zNHQRq0m(8*!9a=+Qb{0H33`VtPkAtw*cky!yc|EXoRP*D%XB%)W;x@KF;>`eEY5O9 zDPydX$`L!u8N-aR$}PwBEN6r>#*9*q{#nlWXN(!MoFlTF(a{)d1m#SU<&2%iSmP<@ zn=EH!HOA^d^;#}Jdh3JfX^4k=uTqOzyYWE|t; zf4OUV)Eu6)u_E+{S(DnbpOY=zJ{u1Hy^vZy-4CB|-=hT(1@3tSdD%gMdn z1{A_-IzPr^rEJDn7{ybXuWdNo6ZG$0r|19af!VlGGLG*{*LLOAWvukd%gR_=rB{sM zPA?Uc!K*jW{X1)syyZcaNlzZ>S|e}C<&m(*si->dBK0=N2lh6lEiF7Oq-FI>QBPN8pIHT46f- z6t_-pb4Xxf^Vd%+M&^luiJc+Ksc4Js;K0PL zk>ymsF^#~)j*{gV#h8Nv6T3~8V=7~w5SVfp!+^$YfT^ymv84@TR-&|nWjQuB&dQW_ zw=Bo@##yP-&X?u13FE9>X;;j0+KO>jvg*p3He{TYtvcM&wv4mVRfk*JoN-pZY8TFO znx74~R>EqB&T<;2u~x=v_s(*ftg%+grK@8av$0mrrK@9_xv^H#rK@8)fU#EArBei5 z!&ocr(ka3^4HJl!w=zZSrGOnw4NxEvfFuKw8IUZ46bz*Jpf~JtHB7g&iNg|0rxZG+ zG2Y1vqnZj4oCx*BFMFvg5f4uo0GP+^Q2uN*G3oPop` zE05}=TpIPvR;IhBsY^VJ^S1r^(cAxj{`%#=sH%>Y949$m@)F5QB`=e_TvBY@ws*Wj z&R0raC3&^vHImm#UMG3Iq`z2XKh%b6xife0d`Q>5% zUB7-gsIk91l0psI{_~0YBBnf&LcJPuLSV`xDb%(x?+8qJBn2CU-R!`WM^dniF>eb@ zc_amU8S~b_#BF;GB9VDZV9LF5vn_k$Zw^enOHpsn3DXc$lqc?uV|-(Z@MX+Fjj<%wZvRK^tLi40B6n4&z9p#d6Wg-i|rK$1nsQ;ke+i-9B`L>tKD z3;-makRjUSwirk}c^h(?MO)k!lfOZ3dmUm#Wz=r>U$lJKH$3w?WUZdv*QGlV6RBe? zb&RKu(bO@LI{qW~MXxJ2IokAtY`!VLUdUML7*8FesbeH{6jve>!EnkHTM;nZ-C5b{ z+Xp;S#3L4bkEb-kqsB3^jyj6`<5>~D$Kxh^j|W!x9*?~6J#J6%Js!JBcWyen7G>p2 zB_EP}Sn?6cWs;9dJ|?+ba)qSa+3D>1xZIzRd{T0yOTe+FW&TTnDs~0+(mhhQ2P)ZO!}b>Hwm=pAN4`*O zu@$vZY_ZWgj4EoQplCEk6}3@Nv?Zg8+9)WRm{CP-6cjDbsG>FsiUw&^Q5ywCJ2k4P zje?^28dcOrL0PM&$W|Na*5Ne@)Wwz|3`k&*_(8G&l1q?+fRq)aIzVa+v`Q^|t&Vw# zunoqLcG0)9oX%s6Ww;yx^pEh7u~L@fgwA6{#;T?qO?2WaGFG4En4>dQkuf8%v^qu^ z)n87Rwj7w{%JEC*q9SAFE=Rd6XE?Ah)<)O~KgJ@{*`~-?9aMJ0mrYIT*LjZ2+aJbL z0}@tT-WcvwurFhKO@2wyX_Ps z%<|_Q^sN^?*x*XWtZ`urpSA*Poj&jVAN$*b4?ft@)6r2=+4=Rgvrg&X1;4)KBO}3Y z!u;}ORz12Rpz0j2I!CL{k*ag3>Kv{*2dmC{)j7ED{=2Rp2w58*4q2<4Ur)#yyCg>+ zy4f@a)~rE;%@KLkqr!Z}wNP=*Rb0~**JQ;tmAI&n>A5pkkZOI!&O56qsT#-4Z#Bu{ z9IZM>s?MRRbGYi%Ee49dh^n4C+xG4s7&wchJ9@jjDX@Ij2cP=N;M02k6&DvR5cn{|@`@M>K7#qEBaE@L6`{ri(84RLISWgAOv= zC^zz>GJ01u8Y;eh7@8U@*+=pi$-a`uN**U^*?hUTpZ1RZ~l^crQIk0Ngs#^9q=e4DOFaGN`?3RQw_5q8pV{)=_USsq5 z7h~xDF@gocqVqmpH~)}K-<0%^I{eC`j@k60V?t|OvD@Pw7jsb`8y?v}ib^uh0V^I0 zzhLRr*Ntw&@3H6p`^WHBzM_2&7!#Jq-AiH}*z)IW}liR6qLqUx#6da9F~EMxmyL>^mEiRFLi zStl$)u=T4?=%G%C;a%*MwqGR>xNPzVOO(E>HYA>k~s8hNsk3QqMto z4lVKQn4Y!Jn^MIg4?U22j(F(QvtwSNCnv+irYygJEWbF(vQ^@4t9M$x%Y=>8gQJZX zqQggQrCpe{vDol+$BtvEN~oO9kx|v(;9$SaPdo0DYJ~k!Yw9s49Xm8$L@Ip5Uefxs zqYplJGu5`rnlD2grdO_yL-&oQ`!~H5*M-2=+Xgqp#Zu3*#>>!oo$1_XI`xTaU;ZFb zhi=|_js}OVxKA_Hj;++O`l0y+TejEN4KZLPUNz0No};&r+S@F(klTE3XHI}Q#h8%S zj+xnp-EWCP&x*!LDDY9sUT3Kh--yRD|4 z67Qb**dDw+4eZePG^z1X%Ra;OpY<$kt8@cOd_*Pd?er*XdVP%>QQ#wvDK_s94r$__ zTD|`o)7l}`3RT=s$tLG0!6oO%YE~6|f#|-PMAttzA8Zk;ff(y+8h4<`N1Qx+=C;lK z*HPjl=H4c324b5G239rhM1zl*ebb;3nMP+t!<*T7YPQbZ(l}gWw4$+l6OEBnL*@Ps z`S@XykG@4!P<6et!*JtAsPPedMc@23YAeT@s4Z-xwxXgITI9g^Na*Ml`wi^YxR-SK zi0O8Zm+cIT^zYt8XSAwQujnM}q}Ypk+s#-Fer-EW9=^oV6;ErKJgFp# z<~OBTGVxo!=nbW;-GsF%F*M1#$3cpl7tJU3D7ZHUgy??XCOFZqJv?le}u4^1LR#or5v2 zspmw@YvS2A?<0D!Y|5~bE~`6XtnC!@Z%^Z=^Z`ENV6uYwMqPck4X1A0`_wZB=FbdI zz#S`7-7qBd4#qXh(1yKj`t0m$+((Rj#29-=mTE0u)%Z19d=y#}ap4~0lGY#4;v;Hx z)??++KQ+WWh{iITpnU#WH=+X2CSAkg2pXY@*gUhSC4}Y~b*w!SgQyR=K|HW!GY#CS zT!!e!%5a@y(K?A|`;cxz(?5$5Q+K`5t~}aDT&8r^mo%IXH0o9qZ_ATKb{?H37ITn# zj>jA%p6%I5Iyrg<(kB&^Hfd~&yKCE zYL&~>Z%QU0hlyX;r2N9rllb;c%eNeQ5~k(K^UQUuEUP`Kk@`qz7l}&ms602GdeRAJ ztv>mTuvTen4ALB)Va*{~RmTV0?o~knt+?C?Pk=M=39xV1#xQa45m)~<4qkpmc%*Ny zDEQb$yRBrUwY@PyG`m|gK9~jZxJ2Sdv=U+32q*gwzJc#=;t9X^LY+ z#YR?KI`m9?iZS#3J2&=3iI2FD85nOCUC&r!J(_&P==$boHRK(B)FB5Sef|+gZu*z9 zCD*BdlQ&LJpK``Yb9)aCY?oTmpHO`ZmG~GHl&obiO}2jywIdEc{`fovj&b?1vg3@o9O$23!r3yKP|8V*Rdt@d5QogdjafVlXGN%l;$ zIC~)JTb&K+JFFTA2`wd7uGo7U!X7D$exhWPK=sje%C_%@DdP#%TTe@r z5cRrk9X88DeblICxfrOEQqhyDY1K!n*}xd87_(biF}>?}FxcA*e?eI*eOtGxX2UBI zl`vuIBh@S=)WEulC0RS!+wPG%&F=lF2e#y%TAE6QXanlHY`>4^{JqcpI>ciD+f3VEVz}V89CS>nen$v{no2le9Vd}%xoF-I{x>jYFQC4kWsAP4p zn$-^{Ssh=R)r9OFPqUg3eT$W>CQN;>n$?sV_SH^Ov9)Dkuzq^dCzo&aVXW-FA1^b! za@N_jpCx?%Yfng zrA@qh$J6C3Be!ob_D$&_qAYb1q<>OOTH=K3nHCqvuf)H1XmDghQPPwc5mA&fA-d*c zO!h)lTZ+$S^xbU638n4Zy3Ky=4!bv=gBl-k4YlK}t1ZlE1i`&Gy+n$ZTCssa+Sm(DJYkx&OPAJV{{h!3jM-l7XL&ch?hgidt*18RQ+sF^b-7MXcP~#(}+huR6E;&EGg51+sR|#op6!zC~F};o*8>bQxAGPdM zOE2VT#B;P}bX$#{DMkrzSs0?~xhWUG`Z#dnM_;!yL6Tn%i_c#ld zFtnuJgUlsiU`f1t7L$S}{@o*G;cc>D141PWLuD2^lPpY> zSxCHlw4+fJHu3KabG?#JJi7H^7SP7u`>C@TeD7?eB$4UW$ei)@$8#Q zCuN&lWbMDFVW&Chn{ln+>V@XDRnCU4Xm zm#Xkta=}}JE5QD$x6{XH$LICJlZ3AoZWO*wc)F0^5_*s0dmYbpe4pcaj_-H;fa4~| z^MxN*+LOXT#XBuLUoVU2g_|5d;P`&WR_V=%uQ|3j=8jw*Ff0D&jvUjTllw!CA9lRV zk@M5=9F_(-84X_Hc%G-r-6`bj5%RxOxQFBJj_Vvp9ETl;9QlXAMTG+wgw$U|{3$>2 z^1Db^3i*~*Ezo4@ePh| zbbOQJn;qZc_*TcaIlkTT9gZhBp6GazIU5=+ZZgf1&@pQ*`JD%ZqrsI1Y z&vAUO{Gj8U zEv?0BH{(?E$1cfV2k?dw|#j#2z5_0I>&%JwWUMVh<2|fY<}X9w7Dru?L7f zK;YmA5PN{w1H>L6_5iU5h&@2;0n)#((n$Vh;WLGA za(tuX8ysKn_&UeeIuiaF3I{&j@o2}R9FKH-n&WMr?sbmW3K?G_;*T4>PiVaTitsAA z?-X9`_*utm9Ith}&hdK38ys(R{G8)WjyF5r;&`j$=N-S`_(jLt9B+60lH->hzvB2+ z$FDiw;rMmOI~~8_c$ech9l!1P9mnrF{;T8n9KY{)kK+# z_%p|!JO0A)myW-3yx;NHj=ypIH^<*P{?73M$KN~t!SRode{#gmce$NG>F6#Lggg2C*}Uok8pjVrLLLgV-6w&LDOMu``IBLF^1- zXAnDs*crsmAa(|^Gl-o*>F6#Lggg2C*}U zok8pjVrLLLgV-6w&LDOMu``IBLF^1-XYkLC*!dp0>CYf`2C*}Uok8pjVrLLLgV-6w z&LDOMu``IBLF^1-XAnDs*crsmAa(|^Gl-o*>F6#Lggg2C*}Uok8pjVrLLLgV-6w&LDOMu``IBLF^1-XAnDs*crsmAa(|^Gl-o* z>F6#Lggg2C*}Uok8pjVrLLLgV-6w&LDOMu``IBLF^1-XAnDs*crsmAa(|^Gl-o* z>F6#Lggg2C*}Uok8pjVrLLLgV-6w&LDOM zu``IBLF^1-XOM9lq+f&BdsiX$2C+AYy+P~^Vs8+8gV-Cy-XQh{u{VglLF^4;ZxDNf z*c-&&Aod2aH;BDK>=u`7sOLF@`*R}i~`*cHUCAa(_@ zD~Me|>=u`7sOLF@`*R}i~`*cHT{Aoc{Ae|H!1JpD)^&(k2!(;&~&AkWhv&(k2!(;&~& zAkWhv&(k2!(;&~&AkWhv&(k2!(;)jRAp0vI`zs*(DHApI7k--7g8kbVo&Z$bJkNWTT?w;=r%q~C({TabPW(r-cfEl9rw z>9-*L7Np;T^jnaA3({{v`YlMm1?jgS{T8I(g7jOEehboXLHaF7zXj>HApI7k--7g8 zkbVo&Z$bJkNWTT?w;=r%q~C({TabPW(r-cfEl9rw>9-*L7Np;T^jnaA3$mYlgz%+u zKh2T-65Q;cfb6G$?5}|Ax4cHke$C5-pK*M)4BeB`M)Z>#_?Lm>m09l zyutBC$Im(5hzv9Th0TJ$Nj(0fn4?Xzb<@im< zyB)vf_-#l2w+4Oc=MEwD15!UA^#f8rAoT;Dsc?4*`Sl?1Y)AfW4fi<-f4B1>JO~dy zLwJvncJ?R7KRf=_Q5TIG-{RQj*x}gc*zY*txTE7LA?zk$onji_gUa3N8V@gzK8c%y#E1t9|ZD#2;_Yc$onIZ_etQWP zEOvEwC_r_&vw(JKp2? z1IHga{>brO#~(ZX#PO$&_c{K|@#l`eaQvm?uN?1p{I%n69RJPnw~oJaq@6H+f{dRa z<0r`Y2{L|yjGrLmCrCR6X~!V#7^EF%wW)dfB7coj_3>v_@bgu{OoXp?e65fU|5hO# z9;CyAba;>s57Oa522zlL5hVOcLc)WD2MG@n9wa9Ed(hdLZF= z(M&jya3JA8!hxg*5)S0bt~udH9GN&Tllx7MAJIaO7o@y6yF$o|GZ24X;E?WBLed3E z7bIPfbV1Su$u~&)AOqWHh1CDo+)}AcfrJAI2NDh>9LU5AlK($Cwrc>vy^?{% zu8?|Axzu5TzX@7jqLMSE?Ij0O)P7=~tB}XbpD8m7cNPtaQjkGGj>_wChs%pb0yP|| z7Z_y+P&j6_th=vItto4HxyMM%Ov2f+>EZ^8-W5TqM%+JF@+hN(GBb6yEZjvwj63Y? zG5$e${-rCMQfvGl_hnu6I*Hb}S@Q;kCq8C+;(H(QwH5z1-!l+&JGn~}UGi|V@RLH` zqJngCkWLQL$w_`^Po6l5o7F?sW*1+O)fKBl+%4$dDvo@Z4q3H-O<2~|-(S=Ziw>e; z(Gjv}|LD{+5Oi99uW0TSM^=C9(Vs-FP2=O8@Waxg!2RsBPUb430zgCuY@32EH+be4) z_G86Sm^Z2Z7#w0F?e)gG!f_`dbrxnp9e;WRk!JZG0=vfac-(%Im|awq<$dz9+xA(4 z{EHG{Bmo&A4pn6DaAYLF%}4+;0<4xE{XlV+SCM6Tzq~rh@J0HMb)v!<2=se1c~!09w$hgAaR1kNjQ(QydEvfmlNmC9_R5M zCrF%!d7L0|g2V|DC*eHK@{+YIU!geLckwu1;&Fn+`FbB=X+o#Ujgik3qVI8)SF~mM zO2xHoS8>$iONG=UNL+95xEQt0ksCdaqrBKH%Xc7--8_z$c^n{dkUouzINmEn&*Lbs zgUj+ADbreUut! zEjx)k0ELyMLUPw!*0M(A<5Ae5R7h^0%UX68c_0cqmI}#zbXm(TBDw4;UsWn3H`HY< zT*1XnSo!KwA-S_IYvFz_uF1-GDixAj?6MXv?`oj1rc@Z)_nm&dQBVKcwKks7<5=VE zUDnpPX&p_?sJiGjD6B6PMk@;R0TlKr6-FuwG-wnaQz{Hq6lk3&>{}`fR}^S+C_J`Q z7_2DJo=|vPsZg&d&{$B|uT%&(ANI&omDDY;-!0<6q8dbU1!9)>Lb5n@GF<1Fhme_| zm6h(x^@TS0N+E6VwZf0fe@>_vllva|c^=j5r5@-LrBZSWWR};Y)b=4)!cK3M2Y8Yr zYwS;!fs;EU_3JqV{;&teh6Dx)3=;TCp=U3-VNwSe3CyaUGGSi=g9HW%%(bu{IJu89 z%a@63yG$g3u|0u70)qtR;#d!y++L|`@x--#R3w3E7X$_g3=){DWj%0m*JYM>h->?p zNCMMl2n-S!BruoHdf?<{%q;H|*LJx`0@I!d3=$Y5FxS(1;N%|7EbkK6c7;d+)7A(K z5*Q>f7uZ^0yF7At`KVc~6WChqjkw#B!~4s6ci)|vxQj-0fmj;V*&5iGiNELgTOaWL z;+Xr4+~c_1akY>cn&;K5J^5d&WxadsK`N~c5tk?xVxRTcuMiT7r{&D{iMri^=xN4;8dvt}p2e8Wbb5n=PNnx4rX&(IAdLxdsKaCHnfajtDA; zN0q<03T3wi{`#|?7F3=ZRsQNKREu(=|M)*FXgnoq{LM9}Fs+vCQqnPWvV2sKFH^Z@ zaPvzt@pjTIABSs?TvvG;fITeq@3j||(ne8VDoqNMDFKR%1z3B(TK*uzVAdM%VO!R< z_udMcPY^%qJk?~a+)H3FcdcI!{V4fbHSySu8g|wosvA*tn+cjd{rl`g9$FY;>2>^s z-#n2q)S~q!nG^+vR}}d5KUdK8sfhwZC<^>=peyJ~)kJ||5`{}k1zoe6C@>VF@S##c zSFa`t40kAexKz+}tce0c8VdYKqUS+Zv?dA+TPX1Rimsq*TN4F_CKUK-Mpw{Pu89J} z4+{LMqbVd8%x3wXV(ju~RCKj#aouc|KN{*f4=t*=d^XGXg1Ww>imPb#!!uAflvHss zt$wWr>c)~PuBpxPeW17n+p|$zTASsMfx4-riYsihd|#-WORBigR=>albxTPV*V|_K zGG5B(NI_F8?88Nvnykd3e=I2vWCqwjsCI2T4eq4kGB@dQi_FYmx9{* zl7|#2y~i6QD=GNylAlj`7EW!xmjt|1Mp&!G=lwYiHOee1ql7nXp zv!3+-cr6Rd8;21UA4JtbRPU22%YgG8FL9iAyiADRCxs+&zmO!Z6=q%KKM`93{f)!r zYac}dtS?C5JjczBbB-SolE5e2&H94`t`TOP#s3vs{PhMKYW6|=orL2dkN7{}c#-3b zHl0V>ua#DXCFl}Jol2!`yDTIoOWDr{HTy*t`st9{zgc(T_?<1BX9A+|QDyeNY2kl!*Ox!XKz`;1e9#H^$u%PN}2^yZebk!W}N8Chikj3$;92 zdS=w_#Lq{=@lv>$S@t4@1*8_$v3KFCr#n<%b*SU_R{iG@X(#iFTa@~Uu$YHz*qT(ZW8wM~vFeOiHd zTD;2fCI!a*c}I52ao-_)q5|IIc(3sHz9eUVjYK{jGTX_KC*tJ+l6XPl1&J3VUXXYX z@pwVv{X-e=d>Zcw9xu<9#0wHHNW38Ng2ekIj~67~KbG+>r15eji~RD~NxUHOg2W3F zFG#$Hdb}X<{;7<2E{&HXUc}22De;2D3lc9#ydd#D+2aL?_s?a#(`mdM86#dER*4rR zUXXY};suHKDIPCKyniX<)vpVbcH;;d@$wu?ydd#{#0wHHNW4rsvZiMUUaF5Lv2!dB^{ZU{-LBqJs*fh>oZdtI zYF9tQ)oZ2tNU7e&AwSe9;@!$Svq@`5z%F5H8EmKwRy)IkQB;Dpm1@I@8vl|>>=Y5T zWu@9+sn*H}h8jhSnRrm@?WKCXRIf2qp-$0I?ci8f;>{VS^oRD|6|?FoN=-I8JFKGe5O#gQ~_7srmE5C+4)U*6D>%zAkk8AqP;+F zqQ#$RaTDz&LZW?}(4$p_6wxx26D>%zAkk7$M0=s!M2kPs;wIWHLZW@U(4$qw711(= z6D>%zAkk8xM0=6kM2kPs;wIWjA<@1=Xwh=Tw_Uy*UbJNG`>Q%$B$Ke{d$HqB9KS83 zS$$2&6#qSU_bbLs_q8h~-8SMewJ`Y;1DeMQvku({w~Yo2)A#Xc)CY$vmyJFWPdx;X zsh8?IbM?#d>z!D~HERA_2;o^PsJ&7&d9>%PPHwlfA7NP?VrnC%*Xui(db5x>Y43OB z1s3l`c_dMBlvjS=z(X!0&=%ak$Q}gD$H~f zCza-Vm#_1 z-(4!|_wJe~vMqz+8Kt6r{jP~3n=~k%St{zc@R}&HWrN~brJ{ZruZbcXI4GW7D(ZLg znkcfJgW`KiMg3}C6UCcd@tjgozoFMe@fKHnZ>gwX)N7)6t1F%x6a-mdYQ6+bsz1a>xIzvL|UUKrb>ZPzJo_iyNydt3K=1A--vPmn^7 zHek2WqWz#nT&^{F)#6-}xL|3F_H000+h`G&#i5d$R{g-S!F}}`9%_tZgSsfnmS4)+ zXH@{^_iN*FtA5~kQ^jjs@w!rRw5j5?u6TW^IMP({I#;}*R2*umc)cs$SSk)TRlLC! zKUXRaHdVaQ6>lmP>rE9u=ZZH+#XkLho~|;NeP{Spi&%{}x!x_M-fT0yn_chLQg5c2 z-Yu^8`BHDOncl6g_k~h#zM0&aA;}Ax%o#=rFm#u@&=$pi}(BhmQiS%t|+VJhuuNZ|I{;nvY?9 z)-~TWUUb=_2=PvDqeK4SD8qHatiI$z_}7F=>HLcn*jAuY1{_y7u5{eNaYx5hj;n=K z0LQD8(fL?OPb5L@L{K>1gt14%5iRfzxUMKwAOQoa3EKfc_@}Xbe(b#0mL4WzcMDLGc32bw~^y3Xt_oSuKTkd&hg5Af~Uo7RAcy`UQ;i;(V{C4(jPn zDN;|JQUtpldmMWm`yA_zw$QE*Z9n3>JmMA)P;+c`Y;#=Z$YE15&>_tD`GWAHCZ1Po zRCg;%Y{TN82KZaYUkbCH^cPONDrz)WwD*(3cZF0ORg?8ho3%p4MSEe}s71EXCc9bB z)@j;7wVH|hdmg7{x~?CGXj0AA9Pg1LrTdfPUmSVaiT~dmc{hkV^V-OT6xsSscYTy* zW5225dA8?~A1V-?>t12jHM>AwlXhrJeK;ceiRsKV)qz9jKGRujssl%D{@irtm+F|E z;HWza3sN|c!e(KGUjB-M8`wr442fayH$_{eH&;Y~T>Qoq^*cOG>fNda1(K#dv!2-| zW@J=}4e0@*>zUb(7A%SW!L$~eXwiURNfFCwlwDdu*3YRJ1`ZmT27~c180dFbjv#99 z=rj?O=s0?2aV1@f|FlGjDn-efY1d@a5rgVShaQ)8EpDZG@N)VM$#_A#Lx!?qB~W-284UR;r{yKV=9NIvkylcqmJW_6GGA_?o3ymE?s=I5}3_90`Knl2qBgu zvaCywic1<4VTQypB#xL)`Rg^_=xntFM?5h;;#UvcCO*auICROl7C=pH6XT&!nXXn{ zS{NH)$uuRV7BvbtO^ig)p@y@r$)<_Lnxpo0q-Sxic$((Pfc;H2bIm5LlL>p9v+T(R zb~<5s3Lq?7tAU+M*e^ND4r#FV>{4r68L=k$=QU;4J=DA+r~s6BhpE=yv?8bgbPh6| zsiqY{1)$SFr*&$ktcYpPCKYk8v6Bfq<17^s*y)7b>MRuz*tvwAb(V@SwtLjJ_hxv5 z`*EMW=sT>ASh(y*^4;UxD$!Qid}fstlt#8yA|^;W!2uT2(6&mnQb_9Ji70iIKe!Xu zk?3F)S~6oA7>2Fk=0?IeD1~8bx~Y*c4mx4j+G>;B(penipku>U?}0=6>f&K-gz#fY z_Hsch3#>(5ZWcaOs6D>nCTf@swF^qM!6s_h548(RwR#gZ42c?h|CVU?aPyj_Mp*#b zTk5XGrp=xjD1cY&&~^^Kz0b24TM$PwzboWv0mhH9_x6VexfYNnEJf@x6i3hsr5AM3ru%SCHv1Ie9N@r#-($ zG!5tq$4@wZ((y`1j-;XYX`x^9s@iNDcI)2RY za$(jx+9W#Lx_Fal7MX7`wUK6Oj404#?ro+v)J%;kfu?JaxvY1%iCV{zs@QjkrVO(} zmKL#0bM8OyxZt?xc&SjoPc@zX4%A|3w#$h3MAzHmIORC)IODigsC}nJ;%Q9rn^{}E z@l)25#Zm}j$@-?Yo7y`)w#|+gI$q>>vEwB|r8a4)+0R^go^2E5RI$|TX=wG$m{vSS z7|TZ0!c%AGIlkZV1CE;<&lhHW)!)kUcxu$qyTw!IXF7&-=eL_KdZc@{<2jD+bv)Pc zeZs7N#_F^@HyZ1eRU0wTt0_U&x6mv_8>dJCJxZwU65D_(4vKy-8KuYqid2Cn5Zlr! zPI}HKisTVR>L^=2WqC}G&rT=0lmlI>NByuDR%>1!%7G^K&-&)JTOP`R9_>RrAKNbv z7}Ty#H)Zr|1^`p=Rv*D9UjqQ^|G2E6@ZQ(P23Wr`EqFE+(RF{}mF**OFM z=Q>|nSi%&S70A`Zr{5ym{vbqg(YyxDJESwdnTEZnxMJ7d;*e)ONRDY>JEG z^`3q@BnOdr2>A(>Ww^f1MRt0if707={f-8jDFXXLonpaEb zc2DQamd@-_9ZLs}c(@%4>bp`o2jwxfhO_q5nIpv6wm+RUwUGitl7RRmMSoWEF*a_RAV`x3>0)|W z!g07^yX_^`AJzPGSNbJNJ&W5G#hxi(iRymSn%`E-3JgoZe(U&v1mGDg&z zO?o3*vNB0p&Te|4POZ&XDb$LGw< zIcLvyp)I`eQey~2!VA3df?F=4f|iTQO{5^0Xh;N}yo<_R0~D+p5+Alno6^3R)F8$S zpj^cZ{{*5SYCr`+#m{%nX)R{A51+F$^PRKbbJ_WAcYbFyQfg|n{`rz0sWgr>Loy1;#(~bmzg4X-=p6s7dF6(v!dDQM%8Xot?ydbIrO|)1dp8@VHuwQ}b93U!nf1|B4{%f}G zTVTHf(Ro$dzI;M8qv@Wzwfd`$(73xMj=U}xS;j2n5SlrL3+n&9`d7l2t!i&omnJlG zX)e-|{Qycog7gwdE`#_d;I9DpGqAsa=vP1{bgjsQ=C1e5Sd6&x`<*JNY*!8 S(4h_v6fNvpf7MAF+T6eCkYtMh literal 0 HcmV?d00001 diff --git a/CPLD/LCMXO256C/impl1/.vdbs/RAM2GS_tech.vdb b/CPLD/LCMXO256C/impl1/.vdbs/RAM2GS_tech.vdb new file mode 100644 index 0000000000000000000000000000000000000000..74806975d53271900bc6781e8528493c010d64e8 GIT binary patch literal 72003 zcmdUY2b>(mvHr}4%XfRH6G#Y!**gIj2$BF3#K9hLSkf8EWU#Rxk0^w*$xcEUP_Qfn zCxMV|_jJBM5R$+`#?QuJqI1AFfS>)G6VBn;SpV;@h|YOGx`v?SZO zV)dljLmQp?to>Uv)SGDOT+lgZOE!D@;G56f(s}x&-Ivbq+LG&CGq7dOyi3mP?3%M> z)~xw+w|uf^M$hnIZrdZ9dhXq_@!st{TU2qjoObn{3%c&uGJnCm*=Jro>ynLIW?$2F z*~Z!Pwr%<3#^ZbEUV3KNmeD6HU$Zi|>ekiEk9AyK?SJjT50zfBrnjc|)~1yUv$czt zueqgGKQ9`%J-6gmztW4P(u-HDUR8VO;)*)gjmIlj+`4e!*3}D_?0C z&+MF+nLBs(tVKGLF>_|m>*}68Co_BQ)pIU6Gc)gs`L5@tR?MeIEnTZOKhSp;U4 z;~VNH%ou<4#Crt&sZ|t z>r~B$QWkWb*>&0WilN<)-n+JE$2QlA^?p`uwCyH0$@@l!N^32a8hmBJ%AZe0EJ zqetSRux{qVASh8D5QAM;Cse3O<4#nn}vcE`zE6ogqa6_Tkpo)!C zl*1~fT3IEy&J(!fHX(Em!0m7XVmSkEX3WFwFkB2T4|B$)v7O|-dLZl>}pHd$59Ye z_NllmWgpKN1>S*+_)c7wvQI!P?%{S4E`}%LB7Fu|pmg^{#%L6$;G&W;xNOB!x#U3{ z^KxQ=;;BHwXcVe^VZ}2~8WVXtu|V-OCc>CbmD?!ZiIHap7mY%2@szh3&-}$`5d;z` z8OA+>bY}u4CL@SqCKI*}Z88J7?pz5bQ|Z)>)@0arL+xC91nnQR$!H_d9znJGm^K+r zsXc;@X_L|E`a`~Bt8GrTmN~I~i8)=22g{t^${5Y)0$d)h3vpTIbQWT954Ur1F+5L) z7a_FF>1@VmPUqud_%>Ym=0qM;J@c~7DUB%k(qx$4_9HYI!l-$bE-)ur1!3f=>J^w1 zd9p4v{kP+CY;z)#6<~%^(7>FW7;_|$hObgK8Cz3UN+63PS;o@_>7E0a7@{DG8DiMx zv?0!!lkG0S5MMXnr46d&u4!c7#Sxtt+x2*`jO|?pex1Pm4(i>A#;K_Hl~L--ibp8Rnzz}RRr%!fQx zxdLM&Pr_&wlFl|ZS}B1|HVWr)RT9HgVNZo|d6q6?2~NJC|-G6WqQl}-LMLZ-Jp5|vFD)2T8BMnVH(KGe0s z1x7+UAdEQ4FEA2!IbdQ3f+%JOVU=q;=R@*>fS@Rhugil@*6y1)VE3#=#u&(jJPeh@^wiV zajI-am+mHjT&5LxF_na+?`G(xN}r$59FUXa(ne7@xre53v32WT52o9U6B)(?y~rGO z|Bsoqqlg>;=|N8907$1Bam@S>WGAlUF_EM{LE28a(pBuj<>7i1m*rY^Am$SPDS`Xu zwv$vIZjaz%xEoi#*%3$8skDLF(G?Iz9P_o!jyS^TLR49e*{R7G%g6G38kZ9bTu2&G zmVrD47q}2LZXu8cB}}b;=3&6ZzX+n3G3P?opiKlzIK3s9NOJVE=Hv+eMVmpSiD)y> zCZb~YJo#Bx*2C?~xGZn;9Ad7A+gET|>VF*4l4xPp#fwH(rt*N+7kRvGCjUWE&{ zRKkc;WiTT`_lE$9=mlO(^yrr@DVuf!XbJ5m?v#yI^jM*b?3Z=h2(=rI<&3a@%L-9I zf5v4A`xU}H-2RBm687&9lQ!@tft$9WgiTuVQn*0av{k|=P?e7nw)+QwM4$pMCQ!)J zlAUkM1D2G*3u^|}wuGzustTuOv;yUDrAruU>x~@nYVk%6cy+oGChKD)pBhUouL2@H zS0$=ospVgcdAtG6uuSm&Kxq$AgvT|$T<}Is7*%NXB?KO*D9wa`QGH3l85Jqjk{@v@ zooNrMlOc?%Rq4Vmj4<|UsvgFLDV{7lc~&4Sn2xjHWU7$<>W<2hKz3`wHSSNxT^Dfa z)&x<^nsQm&aI`gbW{a=R?|*BGYMy5Lr0qv{YibZ3i?k+XKQX=ZQ)o@&D3${tuVy@0 z)-)bbv6hK=AihcPzBL_$s7$dY;lTqQdn*#A5eA;toq(t;_K=Q4XHW29>tY_%_GG~Y z)6BaAqyQ(z(Pv4BgTB#2^q&T%i(pDJlR&+44j834gQx=-4VumNz4fA zLRNvM`%XMq;=YJ*51@Al+=y9;kuZu;r7BwQsBkJfr?u-*W&2IuLR4CLl~pn z-ydoCseMjpS%_0SBb>{P5Uv&>_%rk?419sW!@?mg?eiMJ8R00wk)F1xaK^v5^8uE{ z8-W)STv$d%aNQ*>#qUSgtsAixT-bGMT#4(dA7Itl+&?Vh@i^KO%^t`VXmE>%YIdzm)aV*ytNh;77Dp^)y4d zZM&(gU=^sx)p)S{$gPA^Ppbs(>+v>3W0WD`l$T0p^ryD2h@-p|&TlR&0TyuyyqLJc zlF{NC!mk8B^SZj-^{j%2s%^xBC9XROr)#}i;6_}^>_|&jt#C$E?gplz+ZA{*afEAb ztf#-T6zhqPe!(ShyLt$qttad~3Wor_tPpK!K!o7?ge>8-rB4dn2*=G4PQmmG+!stA zqB8I&oVKRY89P#wHR5Q0Dz9+2PkP#)!WkdnZUtEEPvFG_-XD^!7I+qeffDR*pWJm= z;NgBw2MLbYaqzkmFyccmyt8jrv*)bBvbc(OhsQWy?B4B|R6L46TTEN}C-KFgV zjC!B3w0!{Gv~)w$jW9GWvUeR{U}Y)%AK<|f{X@J7AvuMPecJaEMDN5O|x%(UeFJHZ7iP6NhtRKLOnDyBCij5wApe}GFE zO+(cu@RVu5SVnqZDNEofRZmMGnMy_D)~XhBB#=fWT&-2D-vBOFC5U2H6*eGkRsE%% zu-uPUrF+-VoYJhBYX7TUz`j^j92@UqRVnVk2fI)SM8#8AlqKKF2xNh!;`vraAafM1mX(zQE>waA~kXL{S7XlsN~yDDASo(LmPRj;r;v8?1NWy!ZE0?AYo z2KMBp0T+`IL@|>ITZfyu5!^~Xa1);~onk{?PW*sz4f2Sb#*$`tO-Rm`3;T}ZKd zsKh&1m%u77BAgn0r@(z{d>i4kG6gqQs7BW0!8HFNX#xwBHFdz4PT`CNx)+ll@d7WV z)@(?2TA-b!9mU+I#h-A`rF*B4v#|Gnu40AQEZ!qR@E3pP6VB%UZh`v(y&6$z-tWQ# zjZfi?VBG~w$JRo;y#UOnOBfrAN@IkoMj(VSohpZE*6uar$Fu@3Ch)LqwZMl$dvag{ zKM-*wWSDrnqZZL{9Ms(UE$hw)(9`i+FsZWjvNSItd^{v!hSRdTa|e^lUs zozp9lH+kJ6xIiVukq>bn6P!_rYCGh`_Mvcrr)Aq9j5t-kz|#^(7;%zc;A!0t0WJ+o z5XJNyR;lq+y(OJN+>hI=TC=)gg%|l$%x-3@SUnH*{sbN@U9L9pbprQwxrT7c=?;M# zT`Jj=2lcXEaAAFt4{<78pij!4F!EICj6U790E_4aUQG1akd(FPPs6W-_0|2jzOOu- zy{&pLt3WT-hX+f%n+f*-$_d|BDfNMA9UF0BWr$*7hwzAq((fpS5tR<%Av{n84-4Li+P#l>5AX-^z;L_Z zeR1DUJgst@#_te(*s7V9R!y4xDKBAEBlEYXC{!U~?4(qg120AI#&WQ{J0)Gk z@6K%4y>`Qno~mp=w)h8zv%|gCCj*i*CmugxN>qObmN?~*zj#9hVgHZ7eRcgeqB8L$ zoK8Wd3#*NJP;Ebvw1L{_Oqh;MTcr!s#vK*Hs2Y{dsLlN$z@i#~7gvp~1+ALyzV1@? zir=8otL`BpkDw}?eMs;XR^5Y0{)7ihZND?{KMUMf+wTqhF9P?~_6Nf0ZvQIqu)4^b zs{Xs+0(G&Kkw0;N6I`G!;+O|lKK`39rHf!)hJY3SHO=NW%uL@(f!6(-Eig4O;>8q!rW&&%g?3A6jl)?m~1Gf@z82|{PsELHE!FcI@+jWC~w2ACTFC89MMon;RFFlFX zqvt#X50>I58~9X#`--1p;LQT}74H%5fkl(R!-^)1URI?E6wS_&Fyd4`fue~cj5t*` zqi8n`uy|*I7gI?#Bz@CrPwOsa;`6%AIki959jA)fbIzk!J=*tic(7D5jc^a3V+8K2 zWV(SLD{!L{HCZApdA&(+VYQH+ZAIY%wXoA9j5t*WqZapQfW=`7yqM^_LsB-a0Sb9z z$1J034H;ICtzi}(EYWuw_?rdpi~dx?J&<+@+=$*ijc{7-83GTBowUqD;R3PK;t69q zm5&j-8e$SgoGP2&8cqjTT7$rgsU#bczG)4meJLe5`nSwWJN==1tx#()UrJHEmhG<2 zW@Xt=y&Vshg3ck_1L#75`wBW2(HP+u;DO;qf;Wm%ZG<@XHHv3gS>(s|^EOErD2sg! zd9jTsT%atrAHvw3D4xEu&Ied}6M+{~R(D7*T3L80p_H>w`{cTGi-{a?gk6_XkL|jy zVD+e;cjLiQ&y|SExwi#)pg7+pcwbFd5l`DD-a~ke-~%L6 z6@*b0DxFc2do{qK3V|0>MOf;-E1T6{f-BpPbLZD~W#M*Xzde0DD@(sVhHqoN6; zqE%T<+fh!C`B0e(XU2E#%>aus1zt><*{rQMt;~M>N>C;?mq+_f1;1mc-au9A<6&R( z-o$MzGzGK<50+AHC!9i6a9CLg4Vn_EV%WE%9`fgc%WeK6}&INJBcTJBOW}2_Xys%>br<1d;=cnPBsZXY}Le3 zIpmRV)r2t}^S7;u-eIkdF&Ki(8ExDq^F7$Khwh~hea51DqWy7UDOHZbq&&iguFt{IApLEOC$_pex7)?pr`P_Rz^DOpxzV2djNd_4-B6Xd|1WAvGtON-Llzw31dT3 zd;=A85s@(FsmdIvn5MyesA5%Kqhe(mgpsGD3tG1OB;e9`1yM}@vqGxY`k&K1rBVORe1R9o|7HD^ONec%1u|b8sp^imPk+kS_gHkcOLH&ePr?_4barxVS zKPB7){FegvMgKDc|CPXv=-rLMTFej~V`;V>O}QC$ib zG#sjmFya)?py3cl7;#c3tKs|taM80Mis?D5(m>C1O6c|ePwM#}thxu8I0;zOd( zBtJ{fdss*sf*@W)&z4F@bx1D}c}Q;)zQ3B91yhg_H&GF+>R=v=1%Fy0uM}2 zmt%qNL%Q&0bmUG2*&}auN|Mjf=0Ww;fUz%weaSuVdv@z|Gn$QG3C(DqCR57M*^?;` zwjzdp2p+5kkS3f)q~Lx7m`XTpNZ`e6C|n=ElPzhBZ$GZ<`GByk`!i5clFyd6% zjDffp0xU)#@Zv^bOW(~b1hW!5D0~4u8ytCBhlI!!upa+uqj~D}>3V&-UZ1Yl(8VW@ zRj-V=PBL}$@sm^pAA<0#NG!Wc*z#i!=81p=l8l`^*8fWsB(kHGsSfYxhVchZ9-E9! zAAd}&(hJA!WBiHSqdh&^oArk_Yb58W6Jh&t78hln_AKsNDwoFcAv{8B{vvL&Ykb={i)mLKtzvGZ^bDB!NUqVXS4&<$#Mx z2%?xtgthORL~m&$hS%xM_wdACt6iVpQ89Z+cQ-5RK?+;&V5$8c1Md~Mul7v_o)x%J zyHW*tP)&V;3#*=dh|38sta|dICKN7EJ=-N=#3`Oe_3mbXMM(lLt|VI@{;;m3mzn;* z_0tcqdLF910}qy39weM%d|2SVTDBSZPJtV>xDOFd@hNy%CFD(Bk4Tz8B@{d9nNH;s zRtaImsdT}8fxdxK-ksd1ZD`##^fq*O@)K@1YHn(8Lw}Cd z<0|qqc(7FRIHEBRpfBKo;nRZmRr7g7WwP^>z>R8Di(#7aNTYCpdN`pWj4Qw@zd${7 zh|Gf%YK1fEai0WO7I_6;Oa)Lh5Jo_T@UaV@L<2EMo|++YbOtT0iUgeFsex9Yt*35 z{t-r;%FAyh-vU@vB=BM?%7(OIR22GnG}!;2o{#~i#*Y)kFzp@G*a{ebCES3C?aIT-cDsZC`<)%nWH>GgC zTK>T_bX5W`CXR5;wK#BeU{(p@c-;oidTdm}7Ko-C@$5i62|>^?)#1SsY64N&L9E6D z?XXtxM!0U0cn|OjJW#+jg7*bnX7H7GpmG#GZ2wG4-c^z|Z2wG0J65=`{S!u>EL;AE zW(cG6QuQ(Rug(sz4CEclnhB=~D0pC2 zY}14hr+5WsMI2$osr-#uxl_rHc!3vFa#*Iu9}L>By?{-$ps_5o_Xno*D9<`DHI0S# zkk_$zu!MOG;p|@oUaT@G_F&-0_S#~7JB|4tZ76va5}#^Ndor>LiM{$#`kDPWl-6P` zvX5Zf@5x5wr-em+3gNWtE`j^@n=$mK3*6YR>YK=eY0eN_V8c`$>1n5mU)Y8TBTl9B zZTM7x#fAl5OzmMQYa5l=B>;RoE9`v6g=9w?8l89J!sHvB0Sj8 zGabDwqhj{yvr8ym4k)h1gQdd%L{tV0SKxv8`GWUVc`2eY;J!-WMwRYmh{`v`uEYa7 zZ{pd(tMo>#szs4E2Na~upYagJbgEpY)u=%;d9v?UJc9u>k24WQoJwZ~6z=5!%dkM; z#mp$1we_c48x|7!OHk@QbwrocD;e$ByeA0 zHxN!mDR`hD&Rhs1PVoxd8gYaXr}8%na&II*;sst@(6&t7%=?k3#7z|Zhju-vkyEk% zJjZ`%yP1!a&b27Bu?L^%xbolgnHMX-Gn1;~{WRR1L~i|^+yAv^&z_2!iVFA=r~IU; z$F5#dKasGyG0k{OjIefr-3|dsv^5-U3rAbR(dKY89ga4Iqh2_g3P-(TPna~LK^3hD zFSoI1DS_RoidOcSzQ^WuZ4`=z2@^)YYGK zQXFDWLI;gAo?rnPX|W^Cb|h^_n(T;YM^Zr~v8!i?NVK-$$RjC@#69=+h`m>H00ok(^RGE4>F!5WX&O&CMRbGG07hZdHfA!YzT5=0e&enH)kzd@g4*VzD(W()62%*8Q=XXD zwRV$k{*_g?L8L2jt-`e$*BV?O$F&yMCvdI9bqB7*&TTt-bjx&O>jAk7SA6x7M%^0A zD|!Ifi0f`#_u$%u>t0-&ac#ksSa9_v8%-ms=mjK)s}I*!T>ZE{iE9AYAg*}*m>Jq) z-Pm>jcH)ZpMp|9-Fyf!WwF}pyxOU_EG_J>ReFoQm;rcAD&*6F;S8U@BZ9nA|pGW*j zTwlQT6t1UnJ%j66T+iXkoZ>=SG2IC+0|ZvrmiC&K+{)+00;pJU_1w%*X1Gh5Uu}ke znJc$=tY+RNT?=N-ySh6Anp6V6#_Bx{)qBQN@2Rg&<(8~o(y?-3cHx>_@A8g4-1Y81 zW65yu2f;Szss!ZJsZ7+pw~GY{b8i;rPI64Ov!@=1`Iyrf9Tv$EqYLEtA9jukKwY+L?T&mzWvV^h(Ue7NFTi-fq@yquxqe~RQ;;OBnKcw(nl-ZmOvNCW_4X?F z4b@yqxm-!PIL8O7DNilws2^M<9u!1Zljz2LqK4*l$C?${4yw`XXic{*5j#$1){%S? z8bF?`%a$%(yX=-_1?DU30TA+0fshTzDa&?cHtyJ|Ie&sf>^3+hC znwsvIF{U9Oo@z}scPw6!%Pm>CXkdC{z2@$r$eFWPZntJ`=QWuHUGus!v**usQ;>R;!z8vWVs4&>ZSIC8(>c?EvId3~n9Bn63h1=Ra0wKF-?am&a;F6~jox z9ti(*>EzLQ69Sdi<+4MWxwCi8y`<;zOBA)O@iEFl4E1K#XEtxRW5cF?=|pPEGW_?G z4F9(yPn%PeS3*_Ubd>9W??8M6FC`0=sAnvwx&b-kXhcnrs&7$E9bRke5>_hgt}2$U zy=CRnb;}CPNY>23|1Vr+Pf&Rk2IOd0+t>9QWFBTX7FG$4OP6k3cFW41Wh=ot!bWjU zEla)qC}3_ts_@Oy4$^XO>S$_%2RuK=}eqLrzd-z$lGSaW$gL|U0jRAiHQv8k1T3RCck0F1U zg|do~^1#bqsKX*V4+T<2hptfd@5#)$Y)KmnTT;EUz;&>~o@J5NCugaU%Ljv849KbL z#~5PHoX$+PcQ~`_Zi*=}Hk;|)-Lv7Y&FeE~c3#$b>4N!lGmB!|HjnL%hSz6zuMg2y zbavvOc93Iz??{*{P!@CS&QR-PcP1JfyF=c=nL9+Bih-`ord@YucG36N)@K&e*YOs2 ztC!!ls$*sEZ5^xodR@scnRS!sj&R@zFX8@v7q0U1K{A>8f0Za&g8*?%%!t0)AAYa%H)QJGFfyknZAsk zls8Pt%w&t;Ew67Who_1j`0=#{WH}|sQr-+;?NVv4wFA@d#S7QK5w2>K!TJOcVm+o^ zw2BE;lvb@?vSKT{U`)ULZDaU@tDHdJBc2jMYfp#??y} z-hN9*UpBk&mW~y@1Ipg5uDw#(dpc@(+@Qv-%EgW_cJ0Ql1_blJnE&ej5Ib`May09v zDAsUCv@tZGMeERp))w}(^5Paa|2V{1CIn7hZ|2Q#MyhMbb^WoRzpYVrrFz;3o5FjO zVEwItwY&~U1($nEIyx|`li{4@7slqSER8{X1^wS%&nWbeFI9BNw|BF%F@3#OGs$k< z8Z|@PtJa_k-O}WFOUeplaTvR24nEXG&rzc`H31|H0~Aa&Bl>K4*%iw8Y@i zS&XnWf-j9Auj_)mLz%7FoLc-UtDiP4 zPqzms-RhMu)$k*Hy?p%&nmsGftN}S=2P0IrKRbJw0ICU^*U=&~+L5{x_<<4E2}fRS z;TqS{)eFb`6C)IR?ap%BGB7U471E>RtgaJosIXnghu$DPEW(@NmjOAcsX>o}^+0Lv z^+#nsLHEO3p1$^Nf;f4ww^vP61~5-NEi*Kb*=(-_6;!YW+*td$IOjKuW$xe4W(X!(wBf)TDkO$txQj?gy8P(ioX7$kK=!-$g9^$!CF~p5Mj-i{!_jX^~^M z=4CUa_XG}}Qqa3j&=VhR5t#Ps2~gB};1JHRA%pJ+d1f`pEH+|Yte|OOuqtzSJy;!S z4$n`GgZVQyb8Y^~mZ^Gp?K}ZA&T^@)t?!NMYV=UNH)24`;iVp!1;fi=iW)T*ln?f! zs)IpQ4M@q6K9~(XJejC~7^CN=^1l*bxG7+0K+c$~y(j@8@3*!pqw#b{DsbyqzaD84 zq{dPstcmhpLQwpbLGiJQDIh16@;a6+UMQ=)>@^C_Yu`Ewc<+D1mBf@6NToSaDqM`# zy)~x{(SnCHNSnJp5WE4ICWck4H)iyhYO<@8j!^WzPkOc67<{AZWEKaa7f}w>Lk_jP zsXTAg%2Owgi=ug48EDCXjF!-AzCl{@g8ff3h$|nTIhKPs-tq=@7Fy3hws)m^OGxLJ0~B71ia9eVT-PyR>{l0GgFz5zKEyLVx8WXG;Mn3;17 zDDe6E=0MCw`SpinehQS_@|3^#6Zb|narZYpaQ1`eLi75=z2~ntRa7o5QNE^~y*hev z_)fKHsk?ZYH(Kk5k?V!>hoX?{#6YeFWEyPljj|x>jN3>5W+UYTS^`ruJC;$M|30^9 zF@+}CUu*Uv+tyyqV>m%E!xs9Y!iCViVyjOqY#mbTIp*9%^>LXsY=pe!HNqp59dq5# zH)K5fb{rbI7Eb8p@04N6vA~oK2usL89h*_d(+m8q9vfquAT%_V!pQlF!VKkK!ja+6 z(V6%M8t?~c06Eny+zgpGeL~0dvBx8`yu~$Zy;A#Wti-)Bemb;s-`;|97P>1gKv}Dc z&_Sg0=;nV_qqg4)1Ykgp7%NVXwO}RF^XlcO(t$^3E~D;w%hNsPc69w5UtnWcCjBzK zLvK*92Q@rvScLpkkgWlkjkDIMS{)Xuls^+Pn=HoE3KgB@7v)jUZ9#?xWFJ&$?r2U& z?$~kkq&DpIq6Rj;qbk#E)N)6_6A%G8vMM={ z8M0SM`uifL#W-mJZD{R`RQT?G8Tu^`GV0eLr@Fb+)=-Vz)Y96Gb<)KwN=FID9G|2O zvorKNM?|!5DO7l0cUJ21{-7=fh+S!W|T&q zAEDpOJLzX-P@6^u_#g9$6OPBu+G`ZN7CmOi*v9E45!Yogn%Af7=A7B{8m#MkK|N>o zf(2b?o_6)F*QT$@nH{Isrme>AaEVG(Qwi*TMU6eGIOrZ>Xx)b&z1wA$v1^c%Y6|91 z(JLl!KC;>#xlWA#ZIoj>7X+*g2rKfXRxQC#)9#YYDROttH-W&u$Oh6IdzLqEo|(h*x8 z*khM9lxabU49F1)U|XtpYu8-`gCjG=2#t=+MzwuVGAh^3Z07*waA1(D0V!vSRUsbm zD;$PQhSi$mRMP9H;eqOaA{Kpf*#W8FKfy{5$P5UJb4~szx9H*=#~;Wc@{lQZ4_K4m z1pIMGK|rb|UI*SGh#EofjRUX3?qo?eQiZkU(g?9aRvICeok}CbYEEf{ScfQ$5Yx@l z2r*(ViLks0E;Qm;QZ)vN9oDAIYajTkMo%@$6fzA6HhxOTLxxJDN+Cn0QKgWf!KhM5 zKQyWo;@(G-LVRLyNcOcwB@JX$3D{6Zm4FRqR0-H{MwNgKXjBQ$h$_qShb4OISZS6MeVR>Y?Wwzy`cIwNZp@_W8pob_hq#Xr@OryY% zTof4ci2#>R)$io+yn=OXsJz{RTl>Q0ts}tOMu4|iaGQU#1-JR9M}Wf}%DY1>r%eyv z770f=qt0RIEwz>sw$x-~Qe;%3UfuY9(5s?Tm5$uei^^DGGjB4bJ6a+}3f9^hmv5q{ z!WjL?a>X-2Mh4`RL+VkrEQi!1;gEVH98!;jL+X)mNIeQ}ou$W{vD5iwio7LdzN^Ar zGjmSEyd0<&tD;7K!)o-mEvSA@gScFdv)OG?XR}i+M72brvaB~bY>SSbUDs%KAb4)b>m5M@DTL;ZUs+eAmH5m-1W>(QkVmP^IuED>nFmy2%mXSR z<^h!m^MFc#c|aw;5U_$Z=R1L445TM8E|PyWABMLbz8=6TS!;O#=9>jTyg%_m9#Gy% ze=!dzucd!C09L8;@C@wt^PuYG^q2FXYNzwR1E`dqZxqYx(?i;ZmEL%WRbEFoV5PYN zu+m)tSZS{Stn^m^RvIh-D;*Yql@<%YN{K<#`@hC{UT`8350Ha0-*=R_1~&dhZ3B+-0N|G z2Jb@4V5PKI@eFn8uj0wcjHZrOu8|b(&0+m*?-u{H$b;?c=9b7k#Y1HYhQ}|}`oB8n zS8yz|V3!7CI9Wqq6ez-goT_0gfhyM$wK!}Ym#A&QYVeBXix#dP|JsYZT2g5)&C>;i z&!p|uE@q87xXp99>Mu#dJh`Q$-gNMH7vx1FYui2glMr*}s2zp{fpiQAi?08c`{1dj zV7|w3U}5Xst8tY+IzMmr84K*A^MyOOZCotmrlC5dL?0o?Nf^cUn;(x_*&E;=Nn>Si zZlDeWa`Z;_;Go{f)}MyK8u8CTotcPb&Ak1e7AXi<5mlSfxvOnWb?!wSbSY>wgR|8B z@tcBj7?9dg^*U1AQ5}DR`u0p+MP?5RQC3)py;*Xs!>RCpzju{+?(*O8+(;@NZZCxv zy?6VF+%EYy6o>AQuxMn40G#RruYCL496KzoU;r>2m=_QhZ^WgT}DY%ex_J z=gw@)j(C=|b3koK@*k}96v2R;3at6cE2j}}L|Tib$!2~lOy)$3Ig2r;LfVVGYKuk5 zg8tro93kp^3Gp_yC#vh8Y+;r%<5F41)Vt_TiupTLatQX`d)MyTE%92p^VMl%wcPcL zo<9_MKTpk^qQ2v$Pu)JcT{5bcyL=|dcnx(Rp(!1?wY%?L9A6`99r?ZH(F(haKDPHv z)*@b@C45gorZSLr{vVUH-f70N*cex zFs#liY5iv2i!q#2o?EfHqjB;s=0 zKEN3thwv(dhiUpl5ii{$F`ljH*C)ATASIuVV9;t`isHj zOe8!J;XiP_1J|>N-v?f=B4qq)I{c~*zoNr0>+nlD{GtxujBp9k{R)>;ehU^K^>UDF zl?at!9%E2=(w>CSLv1G^RB7;;Q~IvFG^9NRG)&uwkbi1E6Zttwd4p71L3Ldntv~io z(6Vl<<14tFvfv|zwT+4>K_Vi{kz}qW{uAQYqcF3{xJ-Q!kem-VSS5-lH8B&D_*z4p z;5P!L5LKxZ3lWb)GuMI-N&k$Ch4~9EC+Uy=Y8n)6-HT|@H-YwEq`3%TFXA6TI1TiN zqq5||wA+x~7{KoY{vg1~^RKwh1AGGDCm{XR2$MSR-yu93@ehE05yBM+KZejr%J&Ib z-p28&46!nuhIx^v!z%TtD%IEfa{U`n%=Ygjk*dh2Dry=OO@g@p#q~VcorkQ*j@iyh;=QqNe2^*k7a5kOzvuZvoQ5RW&rQ2xVj!2gwhRa!W+QoDBy2|2;PMFQ;5$( z{C32@gZK}0ft>Q@!i?xsuF|r+RA)%Wj{(k%Yr*I~Fq($=D~R8N@CKdHod}Ocd==8a z9U&$3HiS-jI+T%!kWP#Y>%j0LEs_~pM9lCrz`qPUMR%Jn`Sm)ZOLV~~0gCQz$dIDD zANWfUI^|8F46DeH-jm^fA!NoWWPG&F@FXyr1UN-?GT;q}e;jfC+Z{8wNN4bXpMe+3 zK&*;xnvCngU;z@)9O=bqUCj8i2+4RQLZ>_xVo*-RDj>+90SqW(R^<+al<9RABNuTp zq@TyfuUn7hel#0bP5qQ9pjV!kMt(i0j#5-@LiJv-HUuVq&{9A^qx(4sS`&U@(F}jqP!gl$@^aj4}@wyhtR3$ z52uWivQty;LC8`(E|h&?%EYz0isb3&(tIA2-E6I+Nl8giPt`lut;C!Mqgz z0_9b9gVp zHPGj`5N3e?1FlJczXfsjL|q7#jaWI>vNq+&;U=V{XC>!Xc>&IxzKHO7gv{Yage=)C zgyhH)ovd>@M!TDbP@<~h;y8>6ya*%>3~VE9I*bNmGr>1ha3`Tm$@Ff(zUS5T!HXel#U&eQ?6evP}GMW zO6u4%8cXWsq(WKEPGPKYcuQ1hw0R0gvK*^12Oeo13LU9Lgv3!hkZKC=`gFqUL9`H;btA)tHT~0-l0R92l+13;Vn8` zsKXl&QZ6%5e}>}`r<~QOU#$#@HPsw`IIPZzB_M2$%4tnh3a!aMOEJw!aF}`#;2dXC z`452PPY83cLXOBu@1Mt*?!+d8jz&PbKN2s~9{dBqH-T`bJMlEaGk`c78B(hx{EJU$ z&S7XyG#?WDl?2iz^@$FRr&$sIXJNphfcZ2&s&*1`>emE65dwDgc?9ff$l<3Xs0zL! zeLCY96kP==v5#R$k3yz2ZpJ%xNMFYId>zuiGEPs;kiLBga=cK-FVG?TlPe%c_GOgw zVuVg&R>n-6rcXy=RS(WcS%Nb+-%@c&KBXU=Qtk3L$cuE3pj zA+_|A{Kpeg^}t&2i;;kpVkI9}Z1ArZc?2vq2|lj~@J|{mhLlx@xQLgtU~8FIQ>3zFjg1sRm}7vL#J;(salz5+bONc^t^KU{#P6p8<};0Fuv z6e97z5j?*AlUF{->Ks=m4aB>O)B;xNt%-7aWg5bOr2(r34knnGk1CIaT=&%f~Q!{6ZJ<})c0`g$k zQd$uWljuQh&cyH5_-`ouU_SoS8vjj&AIisbx<&pkDEvS^{xcf?ZH3R}<2lJ;`WF?x zHy{65jsLE~XY=u{#($6a3i?|AtQnjsTM@f9is^q5HX%HbwFjj-B=Ry%7NdsqAy9U% zr2L2GWt~OS6jy3q|I`%LX(K2l4qi3Du!B92xm5fAG~lTF(n3Ok3T85-^b&@p*Ik}sS(5VXEVU&dRnb}Opn+(F3$7&EJ zv`Cyv|8+`T#%|K{CiHKHq2H-9TFDG5{WmH#{aZ-So6s-A!vxfU`K%&+g(x1cJqmeU zhU@Ke6Y^%nsCSZoT-b*;s>)KCb4bq{>BlU^1KEEN#aaY874VONei_n@MR)0R)TRr;Ep7`Uem{5yiV2;W^-Q8bSwuxYhgEE?If2O=Zpp zL~fL2asd)?iJG=P55)939R6`8`DtVEZhAF}8rKhhD;{F}MjQMd6&vK)@16KM3 z^LZcWSiWI|oRczt)?4S7v*?qoAL&_s@?$y|8{u4RzwDlvAp5-Ke=Jx>L zoQ*PnE|++KJN(nH=@Yct5?ti_JuZ?z2r_QseH|f-$sH1qw_D`oPB6*0fowfY?V|{H z>SQ2qwaCe39MB|x2;oDTjJ|L^;vnZc4W=-Z1?xca?Lbqf5uXCt1f40laYu`0L+;?33dkk%Ljh*1F%lrTQ!&(!kAiO8aPLFF;3s2` zAA|C{(Ck*88|MDaMs{dPL=9m7m5EFR#?4y7K@oNWOX=iR8; zr$IYhQ^J-?TT|0&et#Fg7?suqFc*N>*E@}E>Wu3Oe4)@oMfvsAC; zR-aBFmi*bm$m}dc*gw7p;beqdEk8kr=L64vt{w4TqqNr}egrB!8R5Ao8v8RYdyPTJ zbhjaV1>xBU{{}ewNhj&yOZTgJf(*ad`v9gl;bybAxT>6(9sf;2-md@+2kcxYcsCNT zNKQ>w>Zz6-ZX*O#-$j9L0u@Ef0^{we$eLE1gsi!S@!udk2MK8LA4JHSZ9;f9(ozC+ zcry@Z$vGmxpE^pN98PO7~r$`+(0 zTmyppbV4WD*3|5+K8R@`Y1$u6fObbg+W+2ry{o6 z==1I5a}qM-;D|b;u|YEV8B;^dn1Xg{268m`up#^qiK*8o5sD$;FXyCLSSIyeB&I1H zkC3A~rzRJ{i4KDtu7u_}R)ov6D{~Fdmm(vsRbRs5RBaWz^w+G=U2qtA9B`jU*nn^z z$Y@**h;K!l+prwP{sFw$OwLA}%?O{W!V7%Tcj(uLkUN<%(OIZJ$D&+%W@1|K49&EU ziScKGc{NTjZ4Yp?@~NPu@tHJtNSfjNG@@wIjtA{j(j=Sg`cs+g59u(a&#rF67rG~_ zgKRS1hO=V6H-Ly0rXbEoNMnUfd6r?^2wsN+{3@z+n4p{U(MJLNQ=nUju5K#GDmE3Y zKL8|sFo*7Vp&?%%vERTx>9!6=epSNAE0A-H$R;4Ee=)WZ zxSB)DVeJngRTVxkPv?%8ve=arc9~UNf?W<$hMa1$i{v2>c6lcN&Mq#g@vC*XMu+Tq zn2tRXL-t4zblMU$mBxn2)_bijB}j9upe>e!f^uQ95*oJID#R^6~sTO z<6qF>Q#$0hgmfIIpmb@^&p!56Bs&;j8juJ%ner?L`T)Rm$Q(yiOKN=DK1fZma`ehQ zerZ?rL&G_7bMg;^n5aLY<=R8@0t3pGw&2wAyS|gnXQT9BCAJM@bWkLtX`!@KqZU^D zkI09<=R^Q#(i}Zgtq%HP$rdAAIf4PXQy?dTb~!@MjBv!H8LY10BhcFcz6#HD;2df> z_4th0?763P&YO)5KC_hsc)Sv2nhVNvKzXGOxrhXFwG1vnAhD(7i_(>&Vl|+m99ED?%}|blwU)C$)eT;E0(&-iNr`HD z2S{ZtX@P1vl5?4ZR4l)fOtl3D7^i(60r0M8Ow`eS>oJ4;f zcA3VK%1La^!>-j>QaOq2KsaA^A!uF4o93s zE|1y0fRY*eD$SWp)BhC)oim^nl>f2A^VD9-S;(9=jB-pE-^C z6}*V)N$hf1I*$?2af@TXKq~F|qwZ6I%79myZV+^?R)N{*js^N>2&K18rY(g^eK^jf z`;vJFW|Beb_|K3h$96n8_fdq`B7Oium_D80fqaCu9*P^+6*;()`oKr#O$^=vQjUVh zN$O@cc;jd;hR`kt_#vR#BG@zKrRKz+smTScv%Sd+P4!v6MI2XxN#((jZk()MhUBIdz^Cs4g3iH^6m$p7f!G4>Cn<&=UW^)rZU z^hWN4=_8l{bt&FEj+&VH6UR-ma)nS<*5WCD!W*aGXXp4la(EsgEsRbSJEZ~9R;cMC z0R9T$^#~tFHVq_7Hd!_yt(Z%3KLMKBr7{OwsQjn#CjiGUHW_qj&^>_2 z_sK5a-s+e713+?W!&&Jk1vxc9zTZL)2r|_kN_iH5Ovx2VC+-DErZmVQK{f?Q=J`II za#)b*0LhdFd7mJg10+*&6_0t|FUXbv$&?29fFRofBvW!$%ajiavNb?5r9o~JWP5;Q zN}4@WJ|xJg0g@>Va=Rc?Q$rG>$us2+L3#m_DGhR`Ae#at^JJr8%7+D+4vkW6WihZ2eZG+lmwI|b4t%gQVI38pSIV0wh4rksDzCsx}{E0oR^BaQ|zZ=!^3^C%OxEFK01z932}1{$hW?je|A50?eVGQ>ote34E@sL~^+IJ57rI zx2?t3L$V6sGk|W;g=2U-I5AwKL#17m*-sWb7Ur@6XbvW2@ZH!ta<9UQb1LQ{k(AQB z(Z2!*S+L)88Li8hu_xWi#q(S4!?&GFHsZ}i0N3D9}u6!r3^%F z=^*LTCMijrvY~>cEFF{nP$g{&l0IXSl7#Ieu|n%7zP)Qe;f}KPqV|Ncx;fDpKV!YW~M@7EoADFOd)8 zNyaDTFb@lvGf1(Wa_n_k$UcJ<>nMjZEaX;$6it=mOIQ}N-ylU7<=DNlke@V2k#;#` zU?B$#QUp|v9V!bsXpka;xcLN><8CvEAB*hpF(~sPD97Dya6eJFtcBZYa6i@QkWimd zavwIhpXqcK?o$T$bK*VKdaJC-+f<`lUkQWSBwiHmF}I6wZVh z)Ta&V*9wKxUUvj+7$g~F*XgZi97 z{a&GP-pimKH>f`ll?WDw-RBMFkAexdY}~IH%%2p-U$u6>W-x!2jDpWiIqo+M>Mt5) z4m&#Tw+!m9g0hZ6x!*RZzX{4ZM&*9Tp#Dx&nRPVCaldD9|0_6q^~8P2;Qk>vd(FiC zfx-QgxCGZg5#r~rAZ8d(uM)!phWwrrQGnlOkpEK1b{o0UAonO_tBqV`kPdt@*tXfo z)duM*WQ&blV~{b0Y_^dfH%K0n2ivrbTx*aCg>15spD@UzLV7lGok5ln7H*@#@jWM`8?J%<#;qEoKl*08|xXlK~*KWWwYvHySTmx}Qc@Gi~__;#{ z#TOun!bY`V9QQthY9uPbjdG27z+iY7-$`)IQe(bkFgyY7l&J%38uvqklf!Em&INOg z*bhPT9L)0+^!}4*rdTTUyw!K{5ksMaF#_9&=UE8v6m)Bv3-%iQBvLitnM74ya!<;$z%P#oVX0L929QE z{mv)nFT~M{rAi3b({A+~SYo7Tb-R`)S;q1eb?o=!Hbr0aAVgZe=&&mi#boiI3tIUx-_5 zF>dZs+?>Q)=5?-nFUkcMUhy7;ZNtrd2sbBgj`xG<8bUu# zXkzW!paS}Rcyqq{BGRJ?!hg&3Ae<(xWzZ)7TbcG+l!kM)1#_tr)nM8 zRo;PH#d_Sz@5HU_F5HqmxFt5=7T<_l>~7rLdvJ5&jWbSokX#^}2N0HT!>#Ng+>+aI zOYFccz7x0D!??MR;O4|O?vU9N0n>j?2n;r+kH|GRW4;7X!&h*t|0-^&ui;krb=+#d zfm_WtajX6oZdEVfR{3q*Dqh5`{5!aneHXXn_i#&mAGi2RxW!(^&HVvx$VC1yzNRj7 z0b+8CJ1{6LubR1UB~rC&vqKUr*%%CBRXi2Lv*7ELLq@r4vfNC~Y|T&!U`i!m;l5X| z8i68#{Z`e4i5VKu5wJ@P59!DhBulkn+pNRum@Zt9u(FMZJZwl}us`5i-7aYSftC6S zumdIu>?Wza&@m@^2L@Dxn61M)g8EhsNks-SyVgr)1P$}FR>lS;@c$($J@AR%{y`OC z!LwU+g!LOR5!P=wtNl93277gcWc?<>q74se3|VLUEV3aJA=%JYn=GqOEHTZXiIDXW zHj1PoDW~R8m}T8zxYf4cR?~`GbsKI~hvQap1a9R=;#PJPZpmr5C8pyRpMhH}ksI3c1E2zip5Il9YjP_jFR9}W8QJ< zS|g6yx13Imiul^GO8+pW7M@H@PFuCs;pd4#o|wFxN`w?8xrIk^N$xx6n{S`{UZkDw zwcbAa?(h8Uv(G;JoO=^YxOho(^NOX*>Mmcla>dfdo32^Cw7GFr-TcN?H#e?Y(!8Sa zrn;}JXl`m=wQR}C3Ex<@s)?F8bv3$R#gdh5Q}@ML=S;qOMe~_;Gp0chi!U%jVQwHt&+@7hWD*JpYm_8>Y{kH9uIf^5z?-O}T05H52BoT6*1z z=4DHpSFd8lmDkT)e)icDE?u&!c~0GU^~p09{L9xaokrk-CC#k0VD+-Pd3CFo*G-#Q zclOLVXU~{3V@BQdv!~CPa9LxzX-?hrb7xMN-*_XXY3EL#AQPBVH*?mkbIzV{*|H_q zT)kxJ4YfHmTzl<=%a<)(y=q1C?Nyzq#^+o&|FZdW>dwCHtMjJKn*gBm88S~VOh{-i zi+Oh)cLq|?bLcChrC>wgITV}l?SgH=>38_*e~CVW#RZ$j2WC{eW5KrmL5sLp#Ha7{ z3eOTW73p#GN5Q-3|Cf}j=^`NP0!-~$%AfA8J;gx8ss3@#3p!KSx z^qkEB&#KC6FRco`s5U{4PqYKCKIPTNuyHe~OWk!0P#cbp72`E-f8`kTm?5>d{SPaS zL2IH6>06&vUsZ`g(ze!KYT%C-3Fk~J%9qEo5GzZ^Jo~nZvqIlT?uQAgSvV!KNxaEQ z8vpxY(fk$iT^wy4M^sgc*r-akyik+6dMTC7Wb*by&RMv0eCr}X4Oivd^#wY%ulG-C zw0&O$W!zx=;3a~R+^G!)=ziQrDzf1&K)I4DJ>oI8tse-0L%~j}qoENR&gGcXTtjCL z&`;e~Bhrs<9YL6K_m+N9wK;NAEtja@(zdY;7E$`npo9fGs%=qk4Q-CMa{(r{R*)Xs z{&H(A$~00(SnqJbAT%?zd*aqGSHu(5$Qf|n2XwDf&TNXU3Qa0rb+z~ zQtnoC84MZV<7~n~X^NBxmE93q z_C3POhzqv+_HdhsmDCA`MM>h;Anh~Q+Tu#$8Hwkcj~AsDMw<}X0FlyH^daRkuot{9 z0hoO_9esGzFw)N~IqrzZfmd3ps3nSYw?YGKS|34Mw=t!m71SVqsnI5psmTNvGr_@VbyL2NgadP}%PwQhik(!19o{>s1BQ17(9AaEJA&P~dM zWp0b*5-*;tmZHbxRc6#NM*I1+-@8ckRv}i!(GcH5p9!H34G!9W_=X@tgNEzd-+LujSSJwLFBQ#$BZiK?Pk_aD3ozW%y6hAr8_0z9bS@PvEpFBYsy~R z-8u>rtM0+jzIkkIq-5H~oODaO|Mm{4MBhkdr}_*o zQZ~#1w=+TG-Ue!gtR@pGC~1e->JTm8^(wSOi!hkOW+g&ArnrpH&K8+uQ{w07UKH}W z^KKl54FjCF)?*wq(`&$`)iV@Wr}@}#aJ=$~&F~4AF~SnkMLM`#IZ$X*&zWq09tN0K^9DBX z;uV!mYheHzjA?_*0YCA%j;-xlZ4h=l(~!4z5~B48fDet&cN421?m*awR}3~8Yq$gc zQIwuI1BFIp89#xEC1v(}<^zHl{+tMvHax3rA>i6FZsYLBqV!}~LAs+Si1}6i))ze@ zO#IAV3UHIPwh}__yqiSli7gd{!b3Pu`I@NzAk%V<0(Qr>iZUN68Lum_iy* zpWxIKrPfKU z=YA;>$a4YvwzjYyR`U`2;PM3#JO#pKL^*#GBhL7^=(Jqav}{Y}?Ywd&aSN24^LK() zh`wk9Et|rCKiVTX%ubXf&%BrP$*n@GTBU!@CU!!npgc4XCxX@w(OrHVp!pn8D*n2- z`HM1cSDt*#&o_IPpn-JE?$`!vg4vYl7#?;vKPsq@TO^A(%02i}e5g93recE0KthsR zV(CW6Z9OQ3=I@zgO*vofuE3~ba~p0JRLD<_WtM}N5)|h?=^^%#z!rrlLWej8fxW-8 ziuyaVm|nQ2$InpoO{WQ0{H2UIguX(we`9sNdruZL5GKcZh2vuVfv?JZY5d1#irSNw zKK3wTQS#>VHhTZXRSYQ+>=mAe;tfvyxGnOi`AhLfZz;5C7qA05+CF%SSH8)?o+IE`6aYYjW4ifp@qbpEVgP%bnH_!q(WZoC9%>iCy5|bnk1YJWCb(}q8n2zYb2%^tOwde z!*S1jrUq3@#eHPAS08q~drJDgXl@?y0YMoKM;BGARSTj8EY|Ww6I!ZP(ULu~Y=aG1 z?c611EX6&DzB8m6Nr{a_`?ALIDulGG(bLa*OjeA+#0zC-Awq5sDhs9dr*2Nr8V@60 z!?%22V>U*Ck6c^ROUa)7<9D;MFRv^5B4JKdB-f#2a%@OizBK`Ad>y0C4$@;vG;?#p ztHkbZfo5#xRib%&Jd4s`#weZJE^$ku!#?|AFV$E#_wPd6sO0$&Fug?t-_B4d?-M__ zicaRcW4;I;4Jh>cr@U}M?VsB$)8rg`s_2$ah#>TmFt%kDmD{p!dz=@l4;+_q#fJ@| zAf07=QDX_}&A>a%fz@if<4cWj6S%(nZ2^i_sSjdE_!g#GJWqip1bS9BF zUw)nNlso;hM5uB}r!t1-FNWzj^B6St)6h7=g%VP?ee@WVVm!ndt?=V=LH_IdV^FIM zhO?1PwiG>i+TmkRZ#MUDDX1z>^AXE7IJHaS*;wA|&N^I)?RkT?=lM6KTEOdgol#KC zoNK1q(^rlFi!eC$+jD&<1w{4!NG`p@cy0|{tQM7HwIGR&9J)3*sn-hLQYYHmtfR{@ z;BN)G&qZ_Nkeg{#;VDe**>)i44u?9gyd~*bU41;~A<>>KW>WUy=Jcv!FCKUxK{30Y zS4;-0Ddc&=R-$xlhgHYdJX%yLwb)B2gqf7)+i_F9!58inoyx&Y3Rto=GsDPZ7iH89 z^@xA}f}nxnb<0o?6s|p33w3=7@vq0%=zP{-J@6K!VQxjt6}$3vX-jg0+Lz214xKI0 zNDI%z9n`^wh^4WD0*R4%M2CXzy=o-7rNGKJ~`J z9WAh(h;NuAje_}To!V<$s@vw)%x<-%;;@{!@s}40iiV7x$b+@m&3&}L`%aT*=o;Yo z#Ht3ld~)0}9kSLfPDu-n{P;gfp&Mc6MuuVkpAIzNVSj@{F}@MkImUe}_N)_7 zaoMIZmetUh$`0%w+x0LM{TzR5m!LrbhbJTJ)KJA_2R6Sr^g3;?=y<`Ef=aUBj7WVs z#`9qNwUM+zq{@$bXo0@2#x?$F&?U|-HTNy6#QTfKo)n#@dXfHMOM>>j{`vIPyz}38Vim-BB9sjZ zBS_(~wEs4Ao4>gUkP;T6gJU~n%I#q*@C!yioA5W+(a$0b@Y}|YvCA2i_|h6OPbs=m z{mJnDjFZf^O8OZXRPGa~!c{nx&cx11%qn&!79dN8lR=vVyWLU|-@e1Aax`gW{QcAvpBiaP~QP8EohtJmcAH54MdWfDe+ z#yC-QLVB_AaII{;gNDbtD*@a5y&X}c?idqz3$R|^{NFLMDto>!IJ+~b>+RRa1RDoAIuk>qU5htvFk)v zY77Ts=zWME`Msb48x4S|s|V)Zj&JS*Bj$3x|8}MXah`+b8(o)l0Yj(ND^5S(2?zelN`=3U`4{Xa83Mw?HkM2+Zau4%l zX7a?N-$^$W`R4vaf+1s3(NPnl9oS`hH#LoEV_WX7qWrq`Tom=U_Y`!d^3H9%&KlTl z)vO{PKaMi$f=yZLPD9*ycxm`roYvCT@V8RX5sWgCPezIRmoc>HrLuF&mli8g|-qRGf;9m-_?7+Mw7O7(MJ+A ziix%%bIE8SwOmi^eFCe3Q9M{3R}Bx_2xI28!ac=KUD}nu!?3qmAC$Jz_h4K}!{wk` zO;_>!BAj7>O#+Gco28R%Asi@&K>@kQ^&&sw_|D;N4jSXt8?ZZyx{KyI#qDq*(jVpi z{%D7^MT1it%?NW{r%cM?-x2YIyHsk$yFV{ef?ayVI(@#GF1<#CHPjf!BYj_8Q>)=REw9a(VO5Mah#}XT!bb zv?_0hbzB%yWv&S#>>}0WL0il+gi$Cqw?hLY@^rkjj?dn6#Bsz;MJcpylk?a$L=u^lGUq6z2Fx z9JJCrIKzc-A$@R)AS5@Kqd^BtB3i@FUBthTtQSb=O_)(7*`kQCNilmj%)I00p!Idy zX)kW{qJpYpq7l+=#vqHZ#7c)lr$y!)--#@R-1Z?ujUhV1dq`UPz$3r*7+Gmlq_q+f zo%|ZlS#ihzOmsBCag*`8s3GIb6pbZ%vgkZb7hYx%^YWB6;xFd*on*4IxCDmYV0Z*D zxjv$_YNd}2D(&Kc8eV<)w}VO_-}$BI@9>up|6W9akB#19C))IO;X+23m04oF_D>|`mN2^%B3!8?lG%)85DWcB=wA_o=G8`ZX-@}r}o z;@n!abvt3wvcAI)__ndar~CLF54~nhKQ#+yW!;qTdF+|FrE=BzOD1! zd9L9CNdNO*gQo%f(BO!o_j#k>D$QE%3cwfkBq%>>X#7krzWn~IWDQ*jxc>GkDkhiV zXqv(76rT5sm`!$Bt;%1NDp>`uWou7LF@8f4AMNvsW7wV0jP%f>A3UaQ61>V(tJ1Sy z|I9JXyr_lK7ed#3J1K?pszR=r=q7<(vPNIsyJ#W>QVjcw`0Ze#Baf4DgWWc4fo-I} zar~R(=${Gg-sYoU99R13^4xN%e(tLQ(f^8e|1~lmjdSCe%%VE`>Vy!!H$kP_#433< z%vVxw=@Ks63zDF!q^tfou&So{^HTfHGgpmQ=R5DW`41nd;m5H188j4Z3aK+ZD*qY6 ze->$A)OoZCSIPg4?DzMpq?lmQSwdE{UFJDB2v{t?*F1*#zmreI1v8V=u11E Tum0bPpm*FgVZv8FF4F%2`l6^f literal 0 HcmV?d00001 diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.ncd b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.ncd new file mode 100644 index 0000000000000000000000000000000000000000..113a28f9c6cae770047794648cfe230b6cdbc83c GIT binary patch literal 162296 zcmeEv3w&KwmHsVl(>85VpoKQ6K%kHG1?1kmTMOjTmPpb^((48tHg=m;XBLm5XHA1&jcgP@M!i{}4*YwdOR-shg1h9N1;-<;oX zC+n`W_G|5Luf6u;oHJ|IGtZ1GeEFi>_}uv3ww}W3zTB1{9ev`s+_*E}*mzo9U9P*M z=ft&z#-@(khV`q~<-w`X;X06ihJ8JSb|II9-W?q>!#eK`NZCL_sQ?u0%m9oUTMcDx9uFK`NY9dO<3z4dknqsq=c_rW2@_ zf~8xyUJ5ofrJQ;xSb3T&1xq8RUJ900Z@sjHD$*A>6ATT~5^3!=NK2%(+aN8G)^3AT zIIZ0V$t|tj2B~mbISo?bv~n7x!f7-#NQH~aD;3uA`U+>_yiqEgu0*3$I9-WGsc^ay zjhQXn7__i2LeQx^Gw4&E8FVSnbUkWf()-r5^{jL@q^E7$z{1vLb&JrIbGd0^O!T(Y za7yX>Qr9URy=zZcn9qtYwI1TW)PHg(vTx3cE{Z69TUw>`ZP8fi+oHSDx3xQzESl&u zj;&Tr6sPqrsW&xRaqK|tYQ3g(o^`?bnR-z>HpG2V>k#)vuS47y#SU>_G&{t7H87>i zFS<>|545MnFR4AXi<5iX+cH6?2D0>RMNKavXF*m?=H!yM6*VPqD{4yKR@6kdgL-ST zl&rTJ*pfw4OI!N3V6yaW?TS&+0!XS6E**PlrK(vj9b1$-skbu|?P{k>-W8QbcLR+o zkV|S*EqD|;sIyw~l6OU)CGUzlOWu{1j_wA9*4`BtI=HQ!tK@C%TP1Icx>6Q>-|oJZ z{T=K2`g_{e^{?vcUP?W6vj!+$-m$i)XJv0kS6jEpOF+xQB&yf?dlk2&;_EQvzJe8_UN+iw*qfT% zPgg=`2-A8IU3*Jf4Lb4#0!1k(T$2>iJyvHBQP-YrTI{x|i zMfXLe{(c&3I_dED(@@jthrgdjnvQ|~ei~>xCGq#u3f583-%smTrzz#Vo!OmD$HC-w zQSAk!$!%BpM7d(B0_CQaqeEd5J*^uZ3zOSv)#&slxt-RG&U2F6X~pP-C%K*0OQV#1 z!a#3__P(U6G>Uzl(A&{{T-;Y01*y1kT&i<5ibX|I>0a09x_Ga3)I@QTN1(X0W|~|V z?=|C)6t79}II*{Leb2FR`I@AU%N-ppeH`iKWdj>m^`vXtB>kg|chdE35)JWIUuRb; zD=EL;S}V7bnu(Hvnz=?z?u)L1`>s`!`=YYozH3(A-*D2pmCHmi`*f{Iauu#9#kj1u zawB2SE+H-YD^5g|SIid06|+TY#cWYnFo@Ws7eRj48GJpgD=(3;7k28_@aOezGxtWFDl63XX_xljdY+a(t(bW#cUlTi&UdC z!{Vao*qFgDp#mKWGvrICKu5j|c~L>aPjHY8NFCo2=>!NmvCH6>(1Ke=E7FdRUm59? z(1MOv8S>f{+P$R_TM4N+_WzDrVAnku6NPkts~L zkrkNQ*R@(^h3huPYLfvxBN^}^ZL9C;)dFY+4qW+X6v!`gL&xR}W>&F$ir4?FcIoRw1lLI2NG`;Z+F7A#@}3Agn=Hi?9x1 zJwh)+AHqh2;}K3kI1%9_giQ#qK{y%VwFvzPuS3|3a0 z0^8yYgfkHa5Y9q48{r&;a}mx*coPB}@vjgrLilThixDnCcq_togi8_LhHx3e+Yv5D zxB}rygm)lZh44;N!u1G$i*N(N z-yz(H@L`0HAl!s-Gr~s^K8Emdgij!R65$qvPa)ij@M(nG5I%!&JHlrXK8Nu42%ksz z0>T#&zJzcG!j}=gg78&@I}!c?;Vy)KM7SH_pAhar_!`2!2wz9|2Esoh+=uW@gl{4I z3&OV%?nih4;X4QqB77I&A%yQCJdE&tgdZUME5aiPI}jd4_&0T=ObKz@Fs){bFjm!`udylb^ZO@pb_ov{2%b4rGQ`QkYTqQz+iMFSFo5(GB@kKjhCXr+n( zd2x7aD=VGcGtkDn#YBe1C!5{`#VO)7v`xE;!}PZRelA74WT#vzxW8P}ful z<7T9eY+GAeR4B@JdPhD?I@UR4Ib~bk-Hj5g=s0uB%7M+NoUs)p zjgdZO0Eb&zUQ<^m2{D%VT(F6`3GEwKkqaA%3zjV*xOAJ;7 zCOxSLOgt`fVdN9;5!>-Yu9;A{G`~}OF-$7D2DY8wyLI!HxAfPy#;`9tGhc+9sQ^bq zYX+pIVC5K!XvoJZ^!k++kCEmfDnMn4w@b0{2fKDK#|=2Mgljwh@R|;89@=hf$SA_W z*iq?k?#FFJ1cJ9UIS{jH>tpCJ`FwwUOUwnT3yoQ|J8)aG1H0lREBkV;`%wi7$L&&J z{Mny;Efh3Y+yavgB#f|~e|SxnSoN)O0jFTK?_40ZB{p6OQpDCtd}0Cvb%F^D+_=c? zM6mABu^m6;nzgOD*$jqs1*bgT+%6LMGev>YP!|KGd|OLPQ$~Z7Z)?qG)wo<269Jak zJRC4kXh6%Jf-yA!Ei>QFKfDewWl1}fOdacyNIgbdY<%+Zus~cFS~6N^>WOQ6*~!tY zvEkj{_x*fBM#QYXAFFMurO=R%lb(peXv0gL*=QROCaiAT0G}(@w;g}vnu5jYwmx*+ zIR11fNpL0xC#8n{fbn`);EZBV=6W|$j9X^>Hf<`&mF0n-mXznD?ZU<%lm`phh#hNw ze=dA$4`|F9s%9oe*q1u45lV#=>RV&u!k$yypQ^a?*x%~xK%u#R8w^SD7+5*bd)9>= zXPwcv^$fIaj0P%D$4;?YaUYznoq#AU&U|uT|Ej*8{%xt2MuRpsXN;DWam}g6?fk>b zl8U=}s%Y^|aR##Nm!%a~Q$XL8QH%ZA8yW)ZSx7a9t7SYOigCht(-K!6<2o#D(MU2G z=DApZ<+=rd&KoPe(ivB=?G18Ilte6^hhTl<-0i}~pYhuYf?@ehu?rAP?ELM*#vkcx z0xRKA@InL=eA9Me<4-x#(*ay`A#6&&1;M1>yj|G%Gub>HGPd&%FPNallBR76x{lcP zc*qkrwHhmX^0wv-^-VTBF}Lmf!;9mr_N-!sAF$0zM5~|A>Yn9Y+T8uyVib6O+%4%F zwq}ixDGMB@HZ{p5ZJPa!814H3rA>_vrNsb?YgWiI6_a2B+R{@#$Ba!F6`Q3zvlB98 zI!#jL+xdsrWRBQqy}0L<^I!@ayE)FLIx#%K0GN?+Yz0!oXrRfsCk8j--i0ojRXuU? z-AsUW+0H+_=#wX7c-$z{+^s%z;keHG6Bc!WQArI-DI*-XtblC#F}SabAmwQF&tNX-y@2Z=S|`LXV3cI!g3TOZf=0PEdhmT`F|;UESU zF=BN%W?YEalPY8lk+Jihnw|Jc#IAzp$Iu4GN?EL8@82g9Yrym48p;&8Up&X+wtWTN z%7Wa~L0v3eOU9TqseSXn>HXW{JRLL6&=1_w?(7uX`G;4m*?g8~Ty{clXF4C{#o4e0 ze3=WeMmbThxBG#;U>Uaa4=-oUVq5E&G1yrp59Jt{-ri7m_3=$LW*DNH<6NeQkpnvh zh)0#Am9B7TQR`#Ks)pj!lou-ocB>Hvtr%7`F-^_{Q90ZBhnF*GI&FxJ=41?z#h9XL zY|fe@aZrMjTdFy{BE_?e>*ty!&fhWPZZ4i1X1PUP)$AhYH)|kvX=dggw=FZuXU&U> zGs+tMTt=x5rK4`#@Wtt6`LV@PS+3=zj`m(m7UEnditlh~i9K~}Zwh0)czz6-;yN^E)S*}k{kl|5<)vg=&knbp ze|V)jM5gjmI8`GZcyKdm`UN`8Wg0H{h$x>&wE z(Pv!rNqUO8lyIyU6;5g1ryMI?g;Q$x!f}hLa7yQ1IEIS~rxfmm;~t{IDQ$b<*vPAJ zO4VLC?h`7U((@!NGZW?!nB~-Ri0&!$g4r43?91eoa@-b)Xq>r-rt-#2ToX;F%CpVs zRGnx#Rfwii#mqxeO+&J6Q)`^238t~$wy7msFh=4;9FR^K0ZTDPAq7(yG{G2w6ingI z1Y`73Foiu6jFCsd6z)tgMjZuHm@~n+aVVH-8xxG1hJxvqk)_Zy*z`bfh&ElSFOuVm zRRmLA#4M7NQ^8?+ZWT2xI8hc?qZHlxZ-yjK1xIPhap0n!153tJ!bOtZ*^=1R55^E% zt4n8Z$A}|Yw_H#ptNb`!@aTzW$?~9anC@iGF^VK7$a6oTT)FtgNU=ZeXOr|XmAC_W z;kd75CCTR^LdnT|a;ZpApJ$5X_;g0GoIJA;%5f{QuXAmY zq&>M1%Dxl(r)6M7*ZueRb$4~F?61qo+0Rw-E7#lDQQs+?@sR#<@5-YiozQQ-hlHY&>xp{?&A>B$cn} z?&~E{SA+jdxUKJ`H67%xT|>U!u36Qwc3H<-{OckU|7tqB@+AB6pz4IGt6^c5E$gdW zQTOK8Z{EClXw3;jJCyEo{)@ld8xWvWm2Lp7TG@Wr1%y;2=SK$#r=t+WSTyE^;x z`h1`&Z6ZYCn{udG)ySI_K}>ySL6c|N6W6Tn>XheLJ|}s}Z+U>_v;Man*q*CUbqexO zZTO3Y>O>FK31d)|)9D#d&C6l>QcxA>WkXdT5X*wJlg6Mb4^L!3wJ;P^o#m9lDQ#7o1%_Er{k(^!$o#$kEl_=(LbW~()rP-V zs801zEgyrbJlm56RYjb5O~np?Kr7p-wv>eGtsa^p^C|yZ(mO|?+K`57eOqExzlQR> z2wzqFH~6I^{XA6n9fPVoBbfnJeF;o9RPzq1i7OD! zz6$zgmMmZ3Hjhog>Zkp0!Rjj%t4(RF*8jy~b*9Jaj4`arGrSpCb+6^g_66!wzCeUk zXOP9_#&-3K9-D&IFZkbr)k77l&1tMQcxT`*%&yMzSUqqItMZI_23GaeSf%W$Jh`vK zeA=nSV+TAion=>V_t+Gye#ZY6tRALVZAoLb(PQ;cFZ4t8+0}i`$p9;eW@H_C<@9fYY}4k`4&b;nBSYZZoXPFI!c! zst$ijY&a}i#%+fcbGz0YpWb`G(z)$Efb3s;{L0?`j+I4w5PRH2fJP3=?Q@)L7ra8S z?bfH&h~W0Yf9WuHZxvCPhg$(@AWsXn3G}ry*rh3&iRn9Vpz+vWXz{-V-umKd*-a1! z#LdHSRxGvC72unjKg4&LAbdFZ{>sq!Zd=k3AiHBReiO?J+X;CG=Vi-~M&HT}D-d-1 z>}7)M8pHJ=nYcc54A=6uoC!q`b+0(5vGSmleTIYlZ-Nx>u}DBHAZ=3{j01rYNE(Yr z^#F!%V&6YBoZ*kc$aXBg1aqy#TYbT1)=jWR)V9_cYLCoBZGH^3C2VU!Ve1#N!fBWL z@KTX&J;Z}ioYNy57*pE;%^k_Im4cCH#D)*X_Y4h2E(dgA%K!2LV!Z*ekO{r)2-Tf;HmCP|ziO+u;mJmwcI zz@}EJI5|odso((sq;3EE8GOca6c($n5~Yh(?p*APU72b!*fwUuws{P;!Kfe2lH4nm zGX{6vv7%?19`^N14OxgzuT9ma5bZ22o)?d%{e{rddPEb?!#0AWn*9tz#NYEd9j+=zJPw;Bn!!yF3%Q zE5?u;cn^^o)|c{gdnIjb^|k+5#`bUzNCD_2{#$X*_u6W4y3K|9#&iB zp^;@h`I_M@yB=*wKFT2(I%*SAHo%SC%|KzDdqEH$h&WOruT=v8CL z7Gx6v@$+1IPB9Cit-)cMWJV`=p5rkn7`;j{*if{JTks~CJF{GA(0zsB_zZu)Ck*m{ zf%pwdz+bo|brJzS@<{j)BY4>0Si|Y+Oq_O&;WY4qLti3a=Z+Mpk&SN&QVql5t%5F= zW%wER21WvE0r3a@ZyMThvmK~Yjxd(bJgC*n7>^|i9yu7!GR0T-1nMOV7rGU+z#HaP zuAHaA&IIRp3yJ(ru3)@)2YCd+eVl>&Rhi)K9s_qNN4c~WZZ2ho@!^gL!1$;~@>@KG zH#h*N_It6nW{-yHi7-0LdK6(e0KQ`n0ETO<+iL(Roo2zP9Z8_$OdMmc?d5kSVU3}; zClkGE$Ix5Cg=iH=G|R@G>LDpMcB}s_5WQR>+L&@)v0qjU(cvHJ`uH9o+J-}ma)K*a z50(iX&M5NKA|U&}*#I7mg@^Tq$aR^B>>Wd7;4FkoX8N_rtaS(dtg5*RVVqVy9uDlJ zcYUipY6Zos{BJ?=6%NIzQ(sN7r$FP(Lku*v!!fj9*b|BuW4RY+YjChu{$Um3l1@W( z2k0f2wCMsw@d?G~ysbVo*^}|qWXa87yyt?)cHufiZ~WNf5`-*|yVJHCGBLez4AX&+ z5aP2wIa8j(=eX-U9tEFk{cpkN>HfD^>ZOX;CifZ=d%Xd+E4*iGD`>OD#$VO(FG3Dr$wP%Y&!Bu^!zff_#k7(sR1H#{^2 zs>k`?0@Z{4Z!x#h;9O(8!A7Ht1v5U;Ae$Hz z!~wEWn0`qt@5yF)Uy}*v*N(wCfOE9$Xo7q}`tkm^ zApLNM?9@_Op`*bYWv>3xEDwLB;ntyzGM;U~lV@Ds4ObUnmN|dpF|-8De9N7@*KW8V zPAu~Xu8qCUu-u=C<;`PQ4zL{hy#;|>HelUH&od75H0c+(i?-J`dFV>Io&L8#**zrD zl-gZxi65h6cNizW#fTi`;o%)Xwi7eDz%QmJ9PA(u>xs$q<}m;~3g^;JH7uW!iRCS0 zSPnem$S&)9XtEY2^dt2O^TgWHCB{dUlivc_`Tn;+c7wCNsYNvG02eQ!4Szbfhtp@t z;%@jHh4{%YPsqOBAiFgavZswfHZZ>tWc7s$S&;Rw4JkhO(BO`rr5*sn7sq2T2Zx0P z%yB=2d{qJ1%(U+x}zUxEt~<_zm$o}pZb(raj;FEI+H zc$?w+4Vk!p;~1_>;o6Q)7Vjq)8cOdcE3UK5^xPQP_}+bjbRv6P!I|lzRpP)*(?#Y{ zo#C%s{L9czGPjZwOeZ_bJZXt|sdH*}XwAO|x`e-MU`K?WI`?*l|LsenU(oTjGYssf zJFvqI8xT^Cubnvt_5kdm51mhZ=;GsRjV1Rz(zd!UMs#ka|1Ap~l@8%W8_vPnoIeIX z+y^^8Gc>~0cTTy^?gb>kJ|bhy?uEaiA;Xa#srQYXZ74n~(`27BhT;Il;X6gdL9ng6 z$VX`?xqR1{AV0lpa->JE$c*>DC8PHEo4@YZadT?Zq@^QyxnB5chv6HpVKEbA% zz~_V%eBOc&HXCMAn-%pPjecgvGm#wh`J~(Mo^D@Jj2W(lErt_oh{121u_0()99S+G z152(dV)02Dt)@lh%}B|5wX?|&cKX}5Er9Hy`@srxlF zHqkpQxIqa^#g_-#anTn$W&Pj38U6)LR4+0Y|F0a1p}>oUl!@wJkGc3ITzmns-|Gpz z|KzQi!NQ7+wkLW-i&YH9S{Yl*{e79HPIZV+ZSgdOPq?aKq(3;^Y3flKqbvXo{Dx

    FTet~6=K0FZgRzuY#W47@H*+zZcde#!Qez1je%4np;r^k}tf+_a~V0=qn zd_OxfhZp<#BXedY`OxX`&Tf2fXe;Rs%crd(ttEMUud1Az(^DHGZyJYvitYv3#!C&w z+r4eP%-hDdjoHS)Hinand|mR&6n@P-RrlhN^ic&joyhsO6p zIrK~{V*$_B^#t^?v^UcD#*+6CZ_dVD91I!utBPKbdB4iQ{|*oSt3CMNIR<_KzrJE1 zvf%o%3?e+kyr*9X7sf2;qXD)u9`-1GTWryKRIbMN30aRypDFp8zb}2}9@l45TRV8f zC7dO)AM)7sa9_Hy2mePrW!c$DdW`x$oDquuOkDxY!OJ%6$IEvU^WD}#-sL;UHNJ!V z%~%HsMu%_$C_wbxBfOQ28)@HXp~tcK@!#^lWo(${e@pTc73VEQyF9`16WgTMnc;BW zWbn12$A;7uahc;TjOOrJ_Z4r!S+4Yvx zR3J>RrQ}Q?*maQJ5UeLlPH#>1h6`P9NbO%?)*CM(>$z_3Uk#@>JUDc3kT=*R9+Ez* z%ZC$2VF?g}MaoMWoe9Bp)-~SmyT%87*Z9C#*9c60=-K4!1gGBUhd6Hy77LRZfUF1> zJdP#)QU15!{GI-{SpC0oI8W`nHFVT_oOAt~mY-Iiv)(;FRQ8>raqgUd&U)QTJ!Ib` zIslFXiT{U2fa?wBAM!B2!NdG-$6#I(<^oF(^SBQrj!)XVY4$i4oPWswmIUAHe@hzI zIGm?81@Vn2@5S4uAZNW?$J{f{_wY&^eb5XpyLjx0VaIxpE{4l;4^YlyTEjnR3)vTa z_Ha0B?l&5y|IT4r)_>VjvXk@SF-!}lX%Ta|&?T26w5q4rI4|>{6wvng-vZhx4y36K zNxZhk8)G{(GyFpk-`ayQb{jJ|1Q9Pk%Gb?C=)COS^2Bd4%znh%;g5PdeDfG)1+#p6 zZ7vs?+I(VaGnQcT!9m&dQ^JiU9yfcH2e*KIv;Qq%zuEtmtZ#DQPwh=&oyCKnehAkm z^}N_{JnqMb20s>60DoIkF$*nkJVnG8yTB5lzS!S>5l=_FpjF9_TbKBl?-HN%UE&jC zU80n0l1~hI@tV9}u}pg=Cwp8A?$7nV1@{g9x8VL`4);a-tM%S9dEu`l`TEef*W)E{ zzN6(u?Favt{O(T~xNq^`{k5$zHztf8>uZ*d}P^sL3X%o_@7Vu#?XC3-dAkHf;(Q$hbsJQwnuOgC;epf zNRA2rXu!YA1OJ~q@b4Z2e&G6qtL=%0Uu^Z864a*;xgYJZE8S*?|1EJQ``?1?^$y#q zZBo2@Gdu*Z%ag-@gTM)cky?2TV-~dbq1`pLyYO)oary4OFPQ!ULI&$)>kZvF@S4!9uB^>|?qxP8mu^UY%T2$J?0 zdr5_C{-rlA3+mbyS-EjbJSN0_UG6ZE+Ft}F!j7C-=|1ZOz{cmvq?sZ)!wMALTGN;_c8Qz2PKOMU3U?rPx=nh^?2oG2uiML}@ zBRI2r>9*$|v>x*v-(w!~J?6V(J*Jdj?B7S2)nfwRA>A#S-3J)blfotsd+{n>?|)0T z_-FrHy2UqKw@B@6qFaQ1v7VhB{?qh(?iTz!bUZPH*THw$kN95COV=$Pwr=q~-z|RN zyT$j%x<$|}!lU8-99Qw%J@bCcvv~QuSukDvK7dw_dg&Eg{BP+M`}*IK!hNn+6m5nE zzPD|L>Ur|voV5M%9tI0IT6m3Z@WxMUg5rhv>?h94dNE7m=m*6|Zina`!(2FFvUzEh_ zOJ@l_R4JWhhU+Y;4OM(TBAk@y@h^UhYIu(seQl4Oh3|Y0h7i|TM(bSzqjFZ@ht?bZ z&G&{M`QGsFW4$5h4dH|#-7b@x?>32rQHwCzUE*=gvP0oi(Z>9Enm`gXf)c=;$ zKH`5%3Lmy^klIVdvB~18#qbxa_B1YFwjEC`Fb8kfIrs=TQNddLXl|tb)L{P;5Br@S z_CFhgeaUelL3Y--AiyjE`(&LdJz_MwJLz%Z)gJKDA>QbJOCcWcza`)MtwW?XVDUV5 z=qTwY1ctu^b=T02Qv7xT>_~BN7?BCZUg`@^SYO!X`@+wCU--|lz94;p7BuxZl>an9 zR$oZgYSV^(z~h#<9=Fv07F<8*e+#a^W4KQ3tzr$y)K|n2?XijjZpxmrUZ*2E<=^llW_I5}z3}iKT}A`qXM+H2W+0Df-;?F@(oe z``=>T?)1OKynVH|b5rxl@>1P#>$=wF*7YWzQ_1DdUDwvx*|kjm)^x3H-?$2}=~~;r z;iPpdS9BlW(X+O%zJ6(EZ`biFSG3f0wryzZ*?6LeudUh8+hspCAQscuuwrgs*J|GB zT66p|6{zW2)48&nl3i<%KE_$>N=t_NqTh*u3s*LIRJ%mhrGJ0EG!U)Qy!tCKrrM~W*J&Z)IIv@}pzQ>-%cl3r#i z`=3N*zZ-RxW$g1b%0gYDv&L9wb{zX0GSk`b z6P^8G)OA+Km?ep;m*}iM)|q)}FEgF}G11wdMqOw1#X8fc@e-XCBAq4P&C5(@e@=Av z{HW`!Awy^46ec>$$2xnN;%s-Kv%yipbg%^J53CyWWoi8%Dw@t4n!gC0(#_c&JuguyNx@T`vb@=tWLU1$v3Rull{(LNi%ZSkOWw;^!8;V3PG*d{PHHlA68gdI zZJVMlv?19(-s@1oQ9!4b14dmfhi0fHaCLj3mZ%5yHu^Q9y^NLv6Sd45b+sIpp_ahY z?FCq3v;@=hy{wkmiCU^gT`hAn)Dk$lR7-@G4KJPFf<<=MiRO&DTIOY_CGc~hmez2N zz2T+vTJQ-!rQP;|n46TIjZQG`3Jz>L3w~o6w(aMrh*UHiit)#r$Xk>orRx5Ez(qZNBQP;}h z8Cr>*+t{~F&SCEL9&|*al_N)8D@SB#CGc$rdOP}L(9y+&4arAS_PSDV;MPGUKk7

    U>y)T`q#e4Q0QW{5HDa$gH z5;(R4y}fN=|LJ|{oE5y|z-gs<)U~p_SS$LnCtbLOQHiv&AvxB&*E>*4qLtQB*UBq1 zv=TbDo$Gs!4Qy@iOE)!KmS|=9sB2|KhE_ty7Fy{JwbJyGZNJ(YS#3)1bu zR@VsE8!ta_eZOne>%C7#y#o(a>K!dPw+Gu3BV2EM`OVe)xKXe7_@a6j>Vm~nsdu!f z+#bwbN4VbjT8684d1zd9NA?}C0XIOyNevT=K`(>=oVUX#>&?WosV-ya*-JMa^w zy`zQU_F!5*!u4L4)O-D?*Sq);*jkj4iocE1-y^FsAQm6}D zJ*juJxZ56V8jWzhHzf7mIO_E-enV)XF7V}~-qG2F_F(yTgzJ5LQtuN+z1~wY?0Mj< zNxh>5+U{2G+mCR)PfY54(x}(FJfq&hT4P7=+7sfFOYOnd&Is50)k(cKje5POX4E_I z*QDN2d$$J*@*`aD*Ch2mdDQDYEu-Fnzt#!&JaX5%oBdpEgsc79q}u(XUhRtFYUcxY zjn$64weDtr5N(93{ko*un@7Fcl^N9z*8EuQ$XV+S7A!`%+IZ`N8@x{)^=ePgsCMA2 zvD%TZ)*T#D9pP%@t);HoTSvXx`({)-@YPuD$W`lZ8nvl6USaI2ecGs3d%uio2d)~c z9eHZqqc`(@LsIQ+qh9U(GpZeUYOHqTsC5TR*CPyayhY2k_UWTu?HL)>4jeUBI~upU zTSm=KJ0q#~nWJ9qnHkj%{Ir3Ncu%W)^j6jIswvmlXN`KT56Y-@;H3?8#QU4=4Wri9 zXD78jXVhzba7L{IA8lY&wAI}m?7fU|zdkpq^m(IR=|hSuT?jn1-gswa!|1j2`AMZO z81+iGWK=rv&t&IhZM1VTYHsP9l4@T#>eX(~sCM9=-GBe8zW#hO*3)yVa(Dz;_Y@}Q za?6j%evPW1S z<(VAwth!HmMl){hrOLB7ste^=8B`g{vpA{^&tn->9pnw<3;efQHBap?$L+VHSf{V5 z;~ie6(Wgy3??khKY-IGP#U+Z;mioVEe6)iix9WSEm z@XcYm|5#_zXvVtB!wP+m7n`GUb1rxIY&6Fi!b<3>?dV%h%|=Ug?ozpk_pvyxsO;KM zZgB8V14wTnd7hqm19-1fIit&FpxMq-p3&2nu#(ENvM%`BTyDY#lxOt3Q**gP&s3h# zt<%7JoAQjV11t`8^)xzc!69c(h(I%dYEYRpW0u~ zM2=H6p!IT>4h}x^3ZUW;xX3v3;I3KPMHcq?YA@i>H8{BQGT&>Ab%WQ$B8^ymmzP?q z5qCfAwc0`{z%K7QlCiqHR4YqAIJm3AOBrjvm+H_Q=N#ITv}31MyK$puNpo0LVP95a z5PY>(mf)Ks##jH7OD#8Uv}DM!ID>=F!j?Y!1?3t2ihTwLfA2tV^voan4rBDf8gvBY z$IIv?>vFk6o>iXFEYre1rzH^Vv zqnHaAh%iVU6b*&9dx%*z(o;9Crp?TbZ2jx>U~U zR{mX#JJ&1E=rS0qpIxauqiGa&xiK)}&3Ea!c9?n~bl;{tqstJl9&OLd=qbnKa`|h7 zl{4D#KyIj)YB4TApldH0Fl#q!2kkYQp778P!gKAxxJ-v}Ej`m4(bJm^Dsq8GIWjlA8h)?g~gw`v!8`n!=efRb3a+CTWAaGpA{3wwM&H*0Wu zPhu(;xmw-p&4^ipz}`U!~;=S%5jAODp#@ zAjPi#OgDKDWmh>}v*&+aZ0c&jlZKQ3dC^}bO@CE+mJT3&(%|4Pj-iyN=R7+&_{&d{ z2b1FH13!hh_bbon{5NvBnSdoPqg(KM=03_ZdhSWN+yZn>UPco(wSOq)HGWKayib~N zEi^07==@KSo--Rp^WMCRyc}uPdts0AtR6F;gwAFu&*<7?2L~T=a5fqq;^5ASDra=v z2L}g#;^d6BHlU=*@&EI!J}znL68FSBrt!yzlxH;Mo=5$7Svs|^M%(OEp3%~E(AK;n zUWf8b_e}@qax+d=p3$xUmdow`nDUG^jF4+_=S|7wj(E4q89fi(v}u~-IePAe-Vrcb z%)-4YXKi^H(vxW?*hbI19c{Tn<%}->4azJdeJ*EoC8nZQW}^-3jBR+*p04Rx`xEzu z11p!9D_1^i8!=a|jjSECYioL@b1_#=_rinDg(tdK(9vMoH_`|^vN9eU7v60j?*)tsZfg)uvHw@(W?Jm`CnYV|C$L-Re$?9dW#`OFTj z^~oD6kg8=ZtX|Hf9HTXprh$sY3^`Q^#6XJ~5}uDU_ehME-_^KA&uxQacdO$$dTtw_ zCT1U|#L@+?~s%+ zA&ZRvKSPYAj^}96%(r6R+mwvF=%VGUL4=8UYGktDzj#{b*$8Mbs-V7Xy9`E-w{*-1*yGF3&Q`r?Ec)X z7!~ePp3ySGyDnq2z(L}&z~?f;I$uO8^(OSWKlv3*C{V2Yb>8QisM)9_7Ch!*0LB^= zFBurFvna~5`%RzK`2e{_x9$ROoyr+)Y2DX-@@msJF;%4S2wuq!;ogsazBnD+WY; z#H*yWhwd&4(wnZjduDUM+n4DL4(|9wz}sKr?)qH7gJoq?MRHi2V%(kg1ab%HC{ufV zz=IRYxX=7B;LX-NcAp;bs#Naz-v+#D@^ZO`F9y6h8h7XFfcFZOi}HmvqfQ%^2XY5% z9#P#~U)$9j$kjN#93JovRbEu)!(4q24diNF9$|WBW!@UdEoS?oN9+uE)+Iu{9PacS z*7r!oM)jm1Zk_6&`niCIi3W908cMeo$0tJ)_lz#OX1w zo%i^BNvmCn<>(pFI`cA`m^EIK@1sF|9j*39 z@a)<=$@dOlKH4Fcm3E_gQaWGEFqSEg_JA~TQ2ksiC+?TimC>wkZAyR4%hEGi@=c{T zz1GVatz$$g-!8A0rH+>N-5JYGKiu~tqs3mieneca#D>VYTkx5ZqcpD3rZa58(Lnzrt7;El_R*NKTYoI7>t;ArJApe{cG1-#6=ozoPjyH6@!Bb?OZ z28LX&4cX8d9O)+k6--;fK8QwQCHbG1=7In3MpTA~}U=TYC8aX4K*nQDKAU6kTYw;NudTHhVjb1MV{7oo-Z~{g809e5Z6w^zv*lv3HykF!h zXWEt?{$Bwv=$nq`Xs$t&JD?gp^LEttgDPjV)CZmcFH48k&yJBKap6_i>4BM!7M*_H z#dUFLF)gm8ExK}fSRB!n#2qLUTBUa%ugU^ia!|v;`=cj4>F497nPAU>{RWpx;{V$L zX*bz5T8aS2k(bd@9O3c79PGnN?k8yOv{8Sh%YcvkZ8VLALOE>A`G((NwVjt>Yt~rj z`2Cp$jEFJqI=|v+tlPZ_T?GAebp5f92%ADRRiEjlP*f?zdcU9w@XIiDvNsb=Dphfd zhYSV;4n7V2-a?}%$#@jxcsTWBwTJ$(KeGc3o~LKt0NyWD&glFfpbw$~m(g^ac3zjkbEA*t%O$I-YgEo?cCP9lE6?gX z^ISt7 z7rhOS$A86eM^7RGu;#}@THA^r)xvA*rHzAWt{o zKzU)lbM982)k$y(SzcjWo{i#Va@_Bo2F&m>TJmuH#nKT>x%9|mI@-t@mvv$pw3R)t z8u}32I=z@K1-Bc$TrKn=7X+4z zQT;T&)k`g8wcW6|)nX`5tFI2nzx+gbbUsKQ`2E4bUrW#SbnO{{{Wg^|TAKdb%Ck7N zXJDW08z!f8{h}R_9WAiNaKy`WHS0&f>TjTU%w3vfaHLl6=Smfa_PrQugHvQrID$i&c?$GwUEIsP19y;V@bS;KcOV4Ny z-=}tNj0wB*P@b# zXPnOE|C4=%VJk(g<9&r^up!~=|GXVH^{Q3Yu1$Wz0JZRvMZ-;YTX~uw5`G8T=_JQ< zG@gA=PTm+@xXhotF}nT>SXOXm)#&_>aLDj_P0wh{pIpnY5%FxwZ**ZI8ss>QYc&7c zi7BI*-j1KEoYATc@~FT9iPx$Ir-OuUxL~!b!)vfo@ev-J+h18vjQ1!qJ^$8wPmcBI zRPQ}iscypswraA_tE#*dj4D~R!3k-&SuFSy2Y4yR+I2^FUoUIH3tkQ3z3V(bV?5O1 z=o;VJb2gwjlRXo+^=KQF=lHI|q1L~gT_!+&0?T{bV8 z%Qe5zt)Ion=SEPYEe(n5;DHqs5l=DbMmPpkC7+Ql8OyOyC!sXL3r@^wti> z=~W&R*fU2nkK}-$ONVhA(FJ(fecCgVv+|Q?^`MTZU+K2^&&%3@JZlfrC3&V(%TN24 z#ntj_2Q!}HM0=R>3=`U&lxOX#okw}5OR>wMQ<{}}-t6}yqnVYpe(7|EtJ70{*hxl4 zz-KL>gH`gRi#WOw#_2KVbQvuwdP<99w5UsXcmP<2iOs$=OOZCx*?plma#os$eE%;C zQUow0MF$X#t>8}9^wBvWkAC)S|JXMuSQ$cmnM+$aj8y3 z$$?AYXg0q+UtzSA^sOpqap&HJvYn|sqpP;V%kNR1(R{$Gex>q^ruW|HTEx;8Ex0`F zzE+8Gd)xAPo+E3K<6~QVSJ{tvz;aldU#X1r{Q$FuZ3C;!`i@A zVRw&QO%ngzJsbz)LAFzQuTwLh4)Sbxw{Sg6%(u@94zt*VJ3NSmv}NiL$^rI-NOVZ0 zLgk_ZLRQD{fY2}JWq$qHawF974wq)P~2aJS)%Rb8qH>#<9c8yS6L%bB@SuIMQ3f8UzbnMXjQMq zwe+~pYiA;iR+XpZR%0BxUU@Pz1I_e|XXy!SmaCl60zbzyIi|4?&Bn`Urf0lF4s}WP z{vEANsBuk>=XFefMstQ)q(8vg_R(2B(k!3xEIpY)F3~)UX1dr!jz zo0rj+MsBFR|K2vWE3Yp$YODSDk2RVmXny4eF72(=Y?5QKa%a9t=uI(Uz#QBBs1?dH zn*Uck?0KZQSkUSEsL_@#?C)6@w&`ZwX}*|8q36FH#xp49(asqBz|UMJYCbB7+glK$ z#_=3I1*zDIjL|$1Z_ni!EsOO(aB+dlYS4l`;q`9ayhR3;H)s*L5PnD9JdphRJ zKU6uRS(Zm#{|tFMo>Do>gU50n-=I9Bc`WB~v?MR1%dbFLU>kWE%{JJ1b20A;XDco4 z_$QFwQk65hVjXy|SDw+_M1JgZ$}^gI?0QalrUS0XKm8}=8BM+H?o077wfU19mpSDj zEpkW3d6aF$X7nM-Gg|P~qdcnz$C{^In;T7CJo|vk8O^xQ1GBuWd|b7jcBS!@CeI#W zFq&Ae{i&DZeeMM0VaItHO}WNN%1h!>?jGfd9BAu1rhNV?c6z}JJehCH)5l%q`|&ukO(*bQtm5B}%H zGP52mpV}dPNU@GLx9O-$xZyMqpELg1m!f^h3T6P{KH}FtXDMr8zaOUR-RvYdX4B|c z@AE69ScGInE3Wb^o3E_&EF^DdYJP@gNS>+LiNTB)H)ZC$&k|N1RagO-Y092gDA=#KX^rG@LT{&fp>OnFD4;-JH$1+%22b;U2z9zM%USNmfKrYY zQVGpn6TlmDPK9xDoyTbT?`mW8ai<}T4{KbbEnOTzJYnUzymy8cvJB+W=tyvKt3T+M z#^w@y=tseOJ&YB+*Q3_;wqV1+Sl4=2sgwN__TfywfCitFm*$H9-$Cw69naBK`v5a1 zE6-@2fwIT`jGl?(<4-@Saz=BJ>n9H=&uCeGMK9+S@i0X2vbeSH!4Q6<@{HzVZnkb} zw3wUoVmaYmtGuMlD2KflfDek2CU)!{07lQa$Uir3G>4H!*T1a%+ANxf@KAo?xq4W+ z#0pL#f(8}5oatnB=gx26W4 zLwrQT%H`g`8tX>CQ)Tcu&-?stL>Ks64fuR5fRCdm7X}A^<6vg=?0>+{&qJseE~6VU z3pbw8RM#{2s+^_GnV)SW8ol_<@H9T7az^LB?a$I0&Gfh<%gcBRE0OQJm1i{1-u~=V zB1R-8nF<%WndQQi^7HaW(uCAZ!$X?Eb!o~1ma=@#$4MR^vNV@bs#$8)rnN_iGXi$xwPm*@X;wQ{IM&Q&gaAi*jZJdkjJ zcDLH!`f=Xs`$cc4r!s9-R>efr@%O0jHX`X#j<&2iHe=&|L^=*rJ z96QTVcV0&G9CDRQ&uAL1+TW_2r6am>>Dhf66_c|vi2kH3(4QPRIM3@3NwR&zw;6)P zq{FuvnzHWnV_&06&3VX=kT3$gG(G%>zisa+G`jZBz>71OM$cXD2O*=S>`pHhm-Vi6 z{($jj0#jA{X}(5NZjKu`Esj=5J^QfojFt-Bt~^UeOQk%! zFBKNKfkJ(uz?&Cn?clv8yQ6`nU(DKJ&A!>MnX=E}lC98l@c)0ju{N5o^t59gMsvU% zl(7X#I$D!vYQ6ZJGq)t`rA%+~WtyR*&yL&t=mQo<(;bf#kAfU+cfgA3eI|_PTfplD z&)pLqch+G+?Vc-u_%avzu3?#f-rG&fe9+qwTUVap`vL6XqJJ*hVAxm6qj%t%sD$!l z8~*bs&>OX|QbWg^eijueV*m4nx+T6=iq)`&w?UB zE|%SE2`i8K+l^66Q#Kx|a-XXv{`0bQWbs*9IitDo`q(d&X>|E-z&lTQM)M%2%`lC& zGEvgv*8UlCZ_&6$=f8m&@af7kS{92@c3wtXeaJI8zR_;#bL5bxH2*Ka=x99BvKZ^? zYqT`0@B~ArQvR=s@pF&w?61$|nr|-Z#;%xhXTC{D?h3$rkUbD|RG0FM=KmFsdmia# z*kao!G}_YTOQ;+2b&PP4FXchR7uqy9qCplGda{maui^S3g*OaBA~Hx`)5ey45kj6#b{#` z{VzOspTpL!8$~RM!?lo~Rw&Qt1F@Y_@p0uDy|4yI->f{NEiZB{Z7nJ}1K5}CIO~kQ ztx~d!wceGu!AjnQ(gj>g@{E=R05__IyoMWMInHS;U!xhf`d*cbct2ELSYKNQi+Go3#9f=gL*Bf?@-<$q zJkzE07pGIxrSP0iO-CHyOjp8#j)doQW%`iC2&WhFs1Nc?FIIN}j?;ngPbzVkm z5y`h*{Ttn9&@%avUv5#uq$SjCh)O~B3jx$=xY z@C-QLu8u}eJrHGgpf_5|d#A=VTFNfGu7PdmC+9-8YtiA{d+%y zGl*u92&OU5zs~U-J>?i|C4XCaMoY7ul)*!;yh1s?Jdu~B&9w$Q7H>5BpMAa|H=&iEyiIvV(-Zx*>-xsyBN0Dyaz<0mwyCXrRdBUxPS^B| z=Ga!_x}MQuoByD4#^a+2_H4S*lxuYUkLg+3)al-6!NDz>UdVgi)tC24Yd2Ln^4JdK zS$kM}k!S5D?Esx?Pt~}lBkig_J+ApNuC4u9`DI4u>S1-4amnexbjkEgr`G=3Uo8)` zE9y=j|MOy*iEZYaV0;Pg1G6IMuxr>R&oIuoyRC=1J|jHzDXE9+TZSi&X^Ja8>)y!h zFZEWPh6){c_r|jW z#U%(9b*uz86igENO<%eG1l_U>8!Ac9%?ao(cN(Gu?r-V<-e|0$n*jV8aNKG?RHs|#E^ zclz`J94W=G{qmh-g~P_-DiwaaVx^Wf+(pFt8859n{^NX^wJZU?dzMvC<)~u5G@k0` ze_ouZ>;Pa{CjRFoJ5oEX=*qLSX`r6HPkBbS!V$J}J4Rdnl(e|~j?dFBuF=fjzWosL ztW$=(UBA|RBOa8;%ktn-!*durc^S>+g6A+c^D>&xdD$YO(bUiL52>8hjmFo?Y_y#F zbH>kT*4K9LERUJ@`M5^Q4&`;4htZ~Qa;2 zGTKmkrpj3yG2$++l~s(mE3?D}CbU0kT=Iw=@(e@d5o6>T)~vla0BE~$^GDW0-mZpa z5)zzMldH(}9&s8^+63qWm&!yLwpNg(o`T4o3?kTT@>Ob572)9(0?h^9yh4k^OwcYY zPQ``3I5yd7^%Ey6VX)^6kWg`hD?A3Lx{M_~-2SG=pwUw<@uPszY==RtK=Cp;o(*B& z;$?LHDOiN@$}^fh^w+J*v$$nQ%ifJ|v?%5_m9seFCR$unXAbU*vYeciORLGa?EQHX zSE>SGLXzGe?8i-Xy+7EGGo99ZZJ9y1&$CR;!OI(r6&M5*Rf-h6xsa_02eRV!VjFRY zcOl@&@DdwwG5-ITZy%$jpWNx>-2E!p7V43g(SmiXvhuRH{Dh0?-Dt|&w+4)sws8I2 z;x2fjKPzN()po>n-iFZ<_ioA7=iBdbG1t*e2V)B5I)c&C?v|b_7hmmV$K#A<9u>E1 z9-aq`y84E^-S@e&&^|(MVqcv8EI+}S%U5g;;)u<0aji~*Jy$o=k?@?Z1dk|#HooR- zW!2XAyh@RSnUON1BFM7AM{{fq>WJ> ztV|!NgKN0v40FildH&npkw;63r4QCrnl$-}`@9y8){<7=>L0MgA{Yx%9lT3v4s~E9 z#%RO?%b1Mwq7JHWwN%Kl`|vsOMDpVz=V^YZ=s(^?IW(H1`N5@%zgM2oweLZ11*&-& zO~0t}gUT~G9tK^2{COEoc{@OAG%Z5)4^=LS`y}H2T6r@a%~7%%9sw_lo5%2Ey~}9! zis!$ra$#Is%<*!lo9iJa#}BdEn~jXF*zHd-8Ev`^%R(JgZ`OQGABq{}Sv}cNZ34@M)}D{S>o| z30Y+P|0ME1!|@#5y33EkMvG1y9xRUVuGP3ki_StG;s{UT4m9;|-ttC0v~smp2Chra zDznLNj9bYsFJ1wVdc&bxev>b{WPiEK3jcZ8eY?l)O0l!=@@m9PUAE-!^Zt#Syf^&G z50>bsw5mIA@g01!%L8q|-RtFNN7l%HlJn_>mR@L zE6R=)zI?}qh2ZOyFgffxa{{vor-zqVd(2YBvg5z-q;TN<2YS{?j_2sg3BE@gZD~kc zCC8S6E!(d@-$NsPy(Ok0XInoF6r90qY2O_kfRH7i%y_5OuRMwk5%PuEVjNPsulnWu16UyGgMc;khklX8rRYhD7f^j{Dh3vLuS8- zqiw2jEp3_ox;#v8+Juyg&zKaXUtOaBn}XY1I>V~s^Y8ZkYLOdpul2`A7VG-Z?%#RV z;aZrTCwZ2Q%T=D0*R*QuJit6M1a{O8^HTi;H&0x*ZKjFk*I{={oe;@^=dy7 zEJDLp)1!Ij#{myRG%t;g|L{7k&a6Z2M=Twcqi6KYk1ZYLS)9dh1~C6qc}DX)cuzYp z7;R}#(&F-23R^ign$J>HHEMcBPdUba@6Tu}C-&M`cCK85eSsEP0eP<~h`tFM8>3Oh zPVbu><|BRfngvcCf^jr~uz;g9E~BNONH=YG^HSXR z`Ql=bk&!)kb@6nk^YgrAEMrP0sq078S13&Q+e#`A5({VYPV~ z&G-FT-!|IPm1UA@)qTWw2-_D+AZn4Hw~>653ddX|VF-hF(n%>3+a_ ziAK{#Ro==n`1`YV_?9sGfQS6>ZuEgrrw#8$&wLzk`=X|2wAjJhlxO+QM%fIiM$`V< z@|KlLE3R?vzMMo}VLZ4oNL#B;-aw&F7oI=hp@2p^2)3ni)vAuQ8c+TTuXj~Pm+{6a zp|UPcFL_KfPvV0R+nxD3VsnJN&}n7A`Ufvuj4uTFc{79S;{k-7JJ&y zm1nf3P2NDhuC<=T-)e#Aog9M9v2V9)h3}ta(Mdfmm^;)cZ^wGSi{=Jfjg8wlCT@pU z#V-JUy(Qy#E{@5Ioa4>?@!;UYC##&%bFrJVV?UKyOhw%TJquyci=gO5CUzp{oKw@I3#n zyZm`5oBv(aUZ-iI)3Pv_EMDek!iJ>a1vrlN#B`4&16S~ZKVtL$mFdYfc>B{sguogYbK|WZxLaSJb4||(WROn261G&|mwyIoux{q) zRveo#Xd5j}j*iUBXt7Mf8z|)KTX^dxUmWTavx}Xp*RDD-F)N~EFfR;-XQxONMkLt4 zost-6c7O|Yh~a-;cHi#N-r+s3x*c${2a4t2S8V5k7hb{G^6e0XyQ23;Ox3LTo`=F` zOhS25%svzYZM<`-<2jnsm&ZS=JfrJ>h5q_=vKjk4SQj+#o}ODqk15Y+&Lwt@Q=Y|b`~s%lzf+#k?A*JT zE6;SKEw4Pg&(0sp(fyM4aOJc7w4r@^)Engz{n4d?e#zs1bmvB~`5*J9gy3WIe#Kk1 zInF3t<{j2Dmx)Ls#?KH#<}#k@MXQO`PtUq&(9bU(GbjIa@|s zyHL_}#j{oR4Hcv5kk}hLjkfkNQ3(cHzg-DRWs5ahhC zFfQ=qXu}tI*4D(3wYjwe;cx9BJhX%GTzi<#wVN!HOm#R8)|{*d22Xo%48^69@gHtP^+}HBXr6hr9V(-xMQ)4bX5I%BtyiAWwO@kS z2A`MFQcG83OGkQ~OV93$7DR3!UuY4(?33Qm!tioSwBmGMW2;{9m`~zDQW7z?;6L=l z%V>Tb#8$hEmLlA#az;yWgvSODukRLL9OO+uH9Vhg#VJ0Yu9ArHH&}~yecNcs?u$Xz zpe1YJ4dff^3cUF#&6@Q)91V?uWamkK$iWyvjW%5Dy%tJw+zKYnu#ikSG_}(-V@(e+ z-~rfC52MA)xXQ`7`+R}YV|OUeXja5Jx5b_RI`3f`-HJSq_&bejbRCp(#1+ajnjcg$ z<7hPD(*Wbd%V@2*@mOQ4x$>-BT6OZ`O+s{~T<%uivZmf14>XLEvORg5U#gzOSjdPC z(S!dNV^_lO(Dlre2 z7oLWeFPVya@@cIM+x8NU@_4rI{n03o@t=jOyu+`JR8VOsckr5*{ZuMkXE9drc zoh~o@=SApnjAxDcU&nZj!&fN&;!Wgnj8}T@Iq0`2iSQiVxC7fDo0MlXTcgr-3yZ@| zzba=Djb{F~*KKk0gI>;P{;&Uo=3zARu*q1&!+6Ha$~+IJ-5*6G^D=tg9DJtrOviIH z&l%cl@Qh}cu|<}M=OzMHH+Fs7xHVer*#peOw?p|)umJHs&DZF%L;U)((c;JcN##PG zeI>{0%kRS-{xOv^dPxm7K;ExBqph8zvU~_-alNSA(R>=f9!WD=Cac$JdPYn69EPl| zwIivVwX60du4K2 z3)2kiufJOFaDu^|m*^P&wA97<)zXd|Eg4GrID+^4$#d8TJ$Ebm>j94E=(&yPU#J5w zqouu`ih2A@uYIr3=(#ug?-d$7cah%?HM$A&4|{cj(bCq|Z(JOH+O(!k^EG-VWb94z zM$2a1$&~Z;Eyv=neFM_yvbDhPZ#6xmO^@VS`S?_G-r>z?(=FvpAA(<}7c0MD)z!nw zrH#*+aFLqDMf!{%NTF;w#Ma~e6gYKECp>ON4B}Er{70;YYR7YQ;R*0>SDw-J^Wkng z^JX-UMA=l#Xcpg&RvE2DV0wI$t8|FleX)sPE)G8GS8-vkxe_=3=4d4j%H+jWulesa z3FT=5Na#CA=nThmbk#oI;2O;j_}J^Zjh;8%Kk8&OzvWzWp{8dvSLEzH1x9m4ZvKZ= z&S)zq8mqNMmeoG1m1aFwX$w?W`L<%EQ7x_X22CrMJ65^#o}wxeZkOZMMch{@w`yI) zJx;l^uZ+0e%AM8}aeI_I^~{L7M!EW8-J}fS1K+W6RY#!n&=G-N z^`9zdbi?oc8A78wzlSD2UFD3HW{W?IGmmK)ym%SSJnRkfQCwFKi3^(YjDow{w0Lhu4z6%ZFICxSpikMnJM!>Zw!KnG?a!OUuT)!+7`P7sH?~6+Du^K! z{n1z&2cX^332U8Tf7lcDZd^0iAD2OL6;Brx7~@MRtnw`QmiUC77HK$4j2#x-fVXUr z|Ne7ki;WCZ^sRrccX>dJk<&ouE{~WI2-D`RV~h;E7zuA1a2V0-Z$Ha`iflB#*_r;PvUg``xMrg-QFtj(itxU z&G%;+JALK{->{%amq(F)E3<@&Fzr|C#?HC%-JJ!>#9DW=@bpUoxC+CISL_$Gh%)_( z08yT|btYb2^n#qSV_xuq2|5bPKu4`#aJo4}3+cZqy`48pG`1XK{tn!dG-9@(1x5Ld z9WTTj8afceg+}AsDdnp%j2gr8es%96NzkdC-Mh%e72dljf2F+yvnuWm*pF02iQnRf zMU3(i(*Nm9y1I1{+3!aOwZnr=lax^SK;gtu5~u9nL_&{9h)BHP*qp_<>#%)ds%wvFFO)g*~q z3y*cGCI@JIla{A7y~i9grpFvcV%gt*7JXG(f2B&h zU~bJm@-3xp%p)NWpql86X?r%nlF%8`u8DT+s#pw)YWbd|ge7l$7(MXK9S;R!(9H3E zeH-neECh_hAI#kr{7X{b>3QU8uSmT_$+L8L;Qm?BxClS;pkoou{?w8!b3`*@&q@974ec(HVz;LBrSJgCWkpr8v}&t5L(%jiDCj z$EhD}btfl6d=J0xiB#Hn&TmmCrE4-CI3M--3-K9;SU(ocI7AFuQTI{$e?Qgz64d>3 zyHxk;)8scwQKxn10tMFhu7@7uTEd5&nt z^QXf4l-e>LI2N^aTHz}=vU;~@ZN78Sfxc4s3g#Mu)!mpfjovUZZ0|uBABW*YS_NBn zayq>z+LEs0QE`y#O=qq<|BSFLKS-5WjnHFgoYkjWR9YC8zEkphgpy}*!uut7mpmIU zUXXJjW6ITc3e%R1#EO~}YG}-7f0*JNhRV1a`c~ccX>qE%8*2^4(0)1^1~2%eGv+N= zzFEqBU?OCI7 zB)7Kkv7~?_>7Yezjnel=nKrFCil^_jxyIqNSMQ|1A}2y%^xFHl(lMTcMm^&a(To?r ztuovNhm6n>I^&QrXsb^=?o`|id?0=QZ%X+w%v#WTc6itpn#Z1Q>y6ntl_n=<2#PIK zH%)eqTW@p_CXoK!SQ@+&8cJup=MiX{`-o=DZwk80I)m}hUWoT1@fkZU3=-ai=QNd{ zA7_3bdCW1Y>;9np9KcR`Wmf~(Nl%+YX(<8@R&j&f*`gWq_r({IM$AF0-x4zB0G9Eh z=?s>pbEl+a`|LptjX}Y0&7~lcP)@DtX~)?jEj%~vJq$~5U7I#@5)*NJ_j$Ki_iW%>%|9U>5K;+ z%`;xc13$_$UdB`3feWKBA)zzg{bA5zB95K$f_Y!{^EZpnnC*%((V1`N4-rop@fgqC zgyP&ye8!XeU`M|pnlZZ;eZA#sA<9fdC`n5C#jAnWG?YJp6LA}zUWV) zyZvceHsmt;lNq_x;qrPe`!ZS=ro)~G(<8pY+l!@vpcTxED6KliA=h(-5BVAa4jF?M z^2C_tXDQF9PPp`6oBdmnXSBNfZV$!DvoQT={rjP-_vdEDJQ?K4g)!fI_GrsE%Bh($ zjsi!S1&s$tqI0`jBC>6~p&Y`ghV&qDN2Q))Ayn*ER5zJ)rPO_BjQgUdJjyp_!|}J{ z#$0geKUHDP$4R%RCdQILd=4WKNJCCWR}lO>3wxOsh3dT2r@FGN)O~cP*FhY1=kH*Y ziMeX)&y9`Q%gjDSe8wSG>8*@I#Gn;ZghFaG?v<3g1AYj1*yAwG4yFj&9X&~Rj%^Mr z%3dAqVQa%*J+PiGkrX9MDn~$JwYwd$`0PLYPcTLMiDta=b2#(>6{j;^^a;>jC7N;9 zPxF9*ao4SRz`&RvANkb+W6Q)CP3u~V;zlzJTESf~IewwQILyIi6ZuH<1i}7cA_|}V zRcs7fswE8BFS1(x4zG(~344cX@dUBiSuNE^NUo{tb4WBzVk*kg!T&}yiZrcQ3I5VW z2M_;wSLVRfc>a5GU~0_sjVv}gW1fTb@it?pMLvg}2ixI!r16}4VcBjX7vd{8iu0<8 zG~RE~UN$K>_^ub9!$cL7u=WpH@P*}G&Je%M*1Hm=FowQsby{wh>!sO0vjxG46Eedl zj-VCO8FTq%X&E#ahYXjB&p6}>TF3)~+i0v$dEAp!PnlVs>Is9oC;2E0`=_Cf*C-uh zKCxs~HlF+}WIRuN#v#|IL^BQ=SJdy^?DjQ&bY+L*fg!qx-L>i`tHxB=IkDwq>?uUMkJp=-cDoWiC26*R~w8&&Z8&t zweCV06q+$*@4H`o#>|IljwkXPVR;i@bOgUv?%0*@sod31%z?x(^%HZ8i~U}k15&gc z>P7w5m`T;g>4%7`zSFbx6)cviFCujqDZfo;+=7%Ge$g58wOTJ88B;-h!DdbKSL_pL zHz+=*!Q%18Y i5}Yn)3BXVr@@ zUy0xsnz~!%fvh#=eheyI?O(b;cCvpdRs`9AAV(_6$j;qG4E)mB-+pC@bQ%3NWa2B8 z_~`PSB%uk0#i({w>aGn+#${1=ZN>vA;su{%?AWj@I1JF~q8Te{(xPh{CVDXCSuJ_` zr)O7dd8*3*D|z~1IoQ40h#D_OOZ5}7#vwzoAjTn2(2hT9?GQJZhYs{}VCXvXM|kaO8w=uYsPT!00%Z;zdIWBAWddzXgjM$BSlceoiU|r8xhd z;vAsn-fHCr3`sB%trK>#y9iU$I>G)*hYQLrWP#>|esr`8trmWZAJWDfEqJEwZ2JC( zl4tks%E%vIJlT$d-RFXU1oKHvW7gvCUpNq5Y9;qx!%5G~SQiuBKc9PEtXjQ2bZ zi#;oY)G+3=59@Ch&6wr3;kt=@U2Ab3@d?q4=fG|}a!UzY@Ul;X_7TyHxrjObdC`oI zMi)TY>5QEp(kw&lqK7PTZw|d4&O(Ita=N$q!Yo9PXhS!DCkG9)S*}=@X3cm;+;;<$wAc;xnd|-uxZW%s2Aa)I8&%wP{I>`Plv3V-?nz&1m7JqB(9!FPi-& zK56S#x4%AqMCC9U)N4@LAMKdqxF~*_`G%&l1Kl=`hx?QSK3Y&`QGc6<2{*;q`q7Gw z-6I;uv{NctnML(HTG7g?%*bsO&ExAsDjGUI#@BawMJucH`we0cbs_whLe#HIPGgBL zn)wdC53>G1G-Js>k#G7^$Uj#!W94ZFJ~ZGqU%}+-d2|Op6z9loCBA~mXPV`sff&KC zjm|ju3a!lt`TE{c_zEUp-{qoViKfxSn9ck?L_Gd7{EHuHFMbS-@FtWUKAH$Wc=HmG zM=rLX;u{#nF$C1B{6u5JQF=L)9W_6&jG-`o=^U0Dn_h!3UWR=56EtJT z!LV&U7!ZG0Km$S?P2;EJN*v9Ev?g!9ZcIOZ)rn`UKIXX9N1wFz&2L?GOp`uCuo>u+ zbTsx+HJ4YBxwQO?b3f!%nbBvSm|$obGaL=mGru;6Xkm9Q)~?Ody`s^$5%c%I#*;=& zBlpZ*q8U40>@Hn&>8dkU(D%0~CR-f3lWEmmRr|`6jZ_N~-HKD3xM2%Z4G&0-d;dEI zq%*{4Jg^800#A!(%*(QezgcJn^GLzqr$jTRSsJ-sG-H}5(aJhZ5MHqX-=1ub`Q&q*_v7xkxP?$`UmY=(JWWgRFThN*oqz2VS*N6aWHLA+WB~D z=e|(IG1PhWEdbVM79!Cdj;57H6h8CKQACOeXgKgjXithsOxmFjCXJY{y89@ZvEwa` zC@Sd56w{69%p4*dEJBba)xk zpVcduA1TcPzjQRZ^dFv{E0@N@&*aLbaqHty+0w3!xdO&TUOMAY=aPnL zE39#pPtZaoqjWZAT{F|DrM^$*kp5k$$Rj#bvQ&5YKqbXdl8Oir(f1J1l0qw(*;`OV zGN!mIp_X*U6!%T&Wax~UhE>SH8vW*%j_VQn6AH^v$>VB|DzvC)%75ss{$|6 z{^x|rxa;T~jvBKcn2RPxXUu+Jcz@B1*$hWZbs5uwh!)ila{oT%UMb5kI+)df0Fy7< zRW*bUszDq|o~C6Kt!BwzU}CN-w1RogY3b#n8Se(M58h8SV;23YFNkK$G+YhFPM`C{ zp=Co1@Q2I|g&2c%tmcU%AxEuCa*n~q2`5hcA{kB%gH|w0&z}VtD;jdGi?xNPGTl|B z_V>s^Nr!l`HpNn}7oiV>7pZhnW z8Mht+t+YR5_Fz5;Vj6D@?JfFl%+If9e_8PvGi?963a!MWTqceFq=~O{!zjjDF+&IdpMJAoY#++nbR)LMkTA z*B1+|U~X(bf^i$2@uE+F_6O07dogD73Y9TSjA_w1?!oma?dwG|=9q{NV$vBaN2H+l z&{T7aO5s(YVbH}^S--Mnvso=i6)P@Ig!o@M{4^f?ZqC^*zLy$pJn5)vOkHsI8pK!X(YX66T#x+&#b?|FW9CEU#**@UY{PD>GPS(>AT#Vj@~#x741 zrtNeJjBXM$3h&Pt_r4Qt_%`tw(<*IWE}HoUpv{}UBAW5C_hKpKM$wF!lPya{Gp071 z=C~y)`FM8?`kY4NxzunBy0{inf29KwbvHL*!)o$?fN)E;@4{m`?C3Cb)fSQ8B2}c+mGNCA_o%KbbYl5M~X zgT|@HFnpT3OB~i5rXoya>y>E&o0w1{b5*`asS`ipnT3BAEj3_cGnYF_~H= znlV3b^P;9PuYmMnZ)28d>q>=n+>GO;hciB6=5i~nE}g?jdeQ7J@kzsgdo)U650wIo z8vn=X?`p2?ELX3qgDY;jIXtf@MV~-BTOYxlqJ$M6;{98ApH^rE&xD@)Q4-_ULl~!l zPG=m#uNTenuwC?*X|-wGVsSe(=DkDyl-8JCgOA5L?kJd&hT~Q)m9E1mo22RfD4OhM zmx{0p_$q92?}Ot?f0(dSgC3lRX(XHy3Pmx_z{i^%rwL2iA>3^jx2$ z8I;Ef!|-D3(n?5W=!3~rTI55FEW0l{X3?0xp6eYoX&Dda#xHCXpD`75YAG*cD)NGh z3t#bf`lQ;Q>yC5J6`%1;*tg#EMKcaLPn}4kef1Z+#?B8p+wviPAD`ws*~Gk4ma`o? zW9OSR%SV|PevlM3CSp~eXqGGVBjm$LMvg3--PxAV5mNVip2|)TBnFw*oBIm0U}(`j zwW^E7UPmsBm8!FirAt!{^siuUKxfRC=wCuz(;0IlvVE;+ z4$HEge4A*-T(!w)dVX2Gb;FV-?LVrwZc2Y3Ui&lB&Nawr)KfAE{J&%j@(<_u*)4h? z=k}$u5+_1jg%FG%E;MSOXc2ycR{UwHJnuF(e;Htng1yA$an$x{g^#ueIP6W( z-hSMP2OYcS%{(7Ch{f`Ql@=Dvl`MbgWZVr|JbpIrzB0$p#| zR`1AHO1cG0EYd>bA}@PoUMM&errwZ06LXK{yVAJufmVs5Boz@9E$hkTxgj4K_h8bv zAwOkxYMim-Ek!cI@5zQw5?fPuHvFP;k)eCweJ?Who|1OKlxNgcQ?Q~T zUldWKJ)<-2>Ji?v(64@NS49*)C?au`NQE?nrdI*X_97TjCPG>yz+gU`$j+c#c zWO-EN%#?Bk0%Ptu{*!DG9>PAHgRebGGQo)uSYB=4OIR?MHXnV5_>2e9A8mfEXvQ&s zETeJb7)%BY=T}cUVl59}4@ajmD<$1qQ;yA#rKBJ+=$1*HZI@ARnPh*7aL73j=Niz8 zAE}&(Y(}4Nzeb~oa5g-fdv_-PyBwcfR8DCv-Q_v1{mfAWU}C@1X`rW15iQPf0mnHm zGG5uI_I<3hYe<55|S=A0DM8vnx-6WUHy?Yl77AKUc__4*;a@2E7s;7K2c z@x`haoiU$S@4a3$W2#=?g`ycNInttKgp9o@BL#wD*SAHYw0oy?w2ac=!e_oYN>UL4 zB03NB-xpfJ9Dn(qLE~AV**+R`T(#;3g*E0Ks_xc|oqn{SA=tP^voCXlGFdW)+*IEe zp>pjL&;^I`7(s!DYX7@qNT~Ui|JhT@K!V}^%ruur5(OAimFE6x%0ddg0)wZ@T1awUu8F{E;?jeFmM zfi?K)j2TD&(W04;9i6`tFy@UabH5}$W2aB5`S_8@{{KyU#v{AIIIR@Txb< z0_w{qG=5)BE>WU%Y+>W~*;_Pr`J{10)T0<;cmquinEWi5l_2T=Xk;Pn__+0^UoM zO4Qs39i-5Tf4o}uCDDw{U&c2v%UqE19L}nS8M`4h^jvMs?67~*rD(ZjvjznnzbA{P z2oMo!yL~jY;I5~0EMv^3x~kYX<0*ei8)xja8jUhfMsm%CDf?`eC8pH-=J;{1qNdf} zN4vJki4ZSU6Xb%qI5>QrGGokdF}xpQ95sBY_>7~rgSKutXYJ zm>RkmcfdYQ--tpytpP{ccDj*~Sg-Esu+$+n>SI5AnPsVC>AlB6B#r&|`6af(O5bg4epu=wPB`|c_%gQn zh7{;v4klo{ssq<33*MbL0?jK58oxm+{xhFKYq540 z%zo}AOoZu-9S0;F8jbhNnu96gbPdWjpO=d>AaPc@`G%b@&TPKH{z`|twVRJ&kIyiL z#`O}Emi=&Q;#KgOe)6ejtUc+B)yKW{q?6CUCwR>!zT4-Q&&M1M-{w$?g{q}h=&LRk zn?*y18hqZalqL8GFQjQTrEq1tQ6J8+67u-eC5sw=4wx+ z#l^x`zGDv2LRW^ND|&N<`A|o)}yQ0-8_vy7gn1@MR~-D5O<*uLqX6PcO8m8>_O3tyZ)Tt zei(CoWA63hGv=derWtc=%8e#EV~$fr^SPbn(N7{}KjuiT<(+%hZ=oBG-|A2^>6dHB=R>v$_XcLT2C@g;I9EJ;wvp*x6F$XBV z(XrCkhQ!(*jmBq^U3CE{HZ!5AKwpx`M_M?BoiXNapSm zHGb*%u_48=U(lGT8`F=&kl`WtG!Mz77on8KpmCqcsUbB^jN7U9GRyYw7{`@Is4_IIU&6hVrA>nI3(iD<^=XFDB^Z-PQySEfkwR0<3C zs#mU1h&0-L)ivc+i7iBzc*w`l6fRa`#)D{`K5S*oKA^7*my8uP!=m}1i)}Plr9Akb z8Lzir+>faXsQjU7iw6U}l> zN;3#;8G}Br$TGAvvs33v8Hy7jP*V$DD$?MSpKY^?g!rYiKc95pzA{J+V;~OCuEDjC!)~}{eMF26Q*id}F_kcEj>sK8_ z0@$BV1#F=z!5Q-q#UFnrnla~PTi+#`vE#*@A)XBg*^f%uAtk%It)ELBcss_WGdgzR z_Efy#Gv6GdDFQ@&p7(Opkb=4i&r_Q8wrI!DYHOn#}NFITs?6HZtPq=5i2J3=uP^rsZzuM zE>grVo&7_apz*!ZFjyyN+AE-?FgfG*L>#}Ls%XF=*(}kF9j~N} z4*6}JQda8^Z;=do6tyj7(QU@Yhcmf;*^AzvE~G?b=W>vjC5(?)2|X^h(3p~YTw_dW zd&}g>*l9^}^vsRssVVsp)GEvpt9zJXUn!R!Zf#3mj1FU)^I>yPZbyLMKWe)_Xa)16 zi1!VR2hai+oEbqI#@ti%xX3tib&B|mnJcDGXKb02LzvM<^X;8EtghocM)KHV=9FaD(xlD4A*hBtBz)L(~O+I%DpmnP$vf^}IoR#>^Gdr!!^_MWbbi zj^nhYVfDaR8TiLQ_7a4EzS^7`@AI=9LL0~M z@5d6ySW%M}FQgs_&^$fmp+UU@CMsS%hMkc+9`jDfF!b0?SMGvehGfAr3;=Ev%+L!C zrASyv^zTO{957EbV?L@622x zW0A`+pzU0qAbIESH6fSXl2rU9mrp7+=5qcbhZ0}p68`;DG1e$UQ(+7(??ERqrm(`w zg*pjiGGL%rpwwwvjsA}CyPb`irGms~z7TI7=HGM7P%T!yWFcjl6Y z`3f86b}mnnyz@@pRWA9OHS0w)c%?G$0*9gm=}(QEHCZ%cYNWq@GNwlQODExyGo;nd z<+aM?JPa;KV=g0IM*UuHrn9q5>{vDzTE4TXW*I2n7E+tMa9>ziiOMdtc zhAoT0(7i_Utjzl?4UAgVGsf$Xz5jvTj{mvSjAILE)0fP_h#dib??8r*3{o5O9nHB{ ziDt}qG<#9SbjAbcV=CA(O?dPr%%4IzG4v~#TS1$@EIwmy1#P-nG-GZHQBL&etNA2% z^Oql+sx6c3}TPtTjwU9s(_+#HPN-h=L65{Sl0{y2=CBruK1IJpw`J|u%KCz9(X z%~__(V0&k3;lo10w(H5KUsAcK+;@}W<1fQ1%=YciVS0COjGu5L?`N?Ma@Edgx}4@$ zD;YNN@STX~Fwu+$pN2LdeLCZVi|i9g0`{Chg7Gr@*mOBzfOF{ zi#`F`-l7?Ef!(*r8nY}|wsdXz9$*!Urm);DLVRy0E%8if;Qs$0K4YG{_sMSK!6))l zQDZK|uwLjKw(GnMYdmQsw%*D-#n|=7u(6s9S*3QQ@H5VX@Y_5m?EoxYe46>T>NC!+ zLOW|0pK-p;{)%)Y-n?&~n~}nV$8h+{+*3h;$F4*x&s*)m;O4|H%BwwaE_iPY1fFHH zg)`=%Invs@s*(BkrkohC#yU>*)zUsHu=-p_kyD%qagJ6b7_%`q za=bcWJcMuywvY=$;DT8vKEq+m`VoyMpkwTKUW$kY9H*M=`axtt+e!V1*Zxd;;t{_g zR86D#zKs8kXzW)*_)S?=)7buDiLc8Y7f37z=uFYQbDT z!XW;>G8{G@Se3(OW6t?~W214@AL^6NIO;NJ)f@3qr5C281Jrri@_ME5H7eDOTk=rO z?uuKy2*aM|fw`J7j_zR;DT958;jlIMs z1HF8I?sv9}j+_Vq^Y5<2n6G+mJ6<9h^GM{}&x>XpdzbGQ%~;8i76-%LdEkKuzTr)$ zKqBl8Y)@IKoal(^8$+zGw|1^^hQi#cqTPyLy6I;kIO@}WL5nEUud%BWVwP=iXR@JV zWjWT@(~*Rek=q73WfLp>Hz3Fur2xk9i*3*kg(SqY(qPfZ6+dxZ1o44B=OYd frk%?+{uB5kZR;G: -9.968ns/-712.361ns; real time: 5 secs +Level 2, iteration 1 +3(0.02%) conflicts; 494(74.62%) untouched conns; 697746 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-697.746ns; real time: 5 secs +Level 3, iteration 1 +6(0.05%) conflicts; 255(38.52%) untouched conns; 756550 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-756.550ns; real time: 5 secs +Level 4, iteration 1 +17(0.14%) conflicts; 0(0.00%) untouched conn; 761255 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-761.256ns; real time: 5 secs + +Info: Initial congestion level at 75% usage is 0 +Info: Initial congestion area at 75% usage is 0 (0.00%) + +Start NBR section for normal routing at 05:03:28 08/15/23 +Level 4, iteration 1 +12(0.10%) conflicts; 0(0.00%) untouched conn; 765605 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-765.606ns; real time: 5 secs +Level 4, iteration 2 +6(0.05%) conflicts; 0(0.00%) untouched conn; 766423 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-766.424ns; real time: 5 secs +Level 4, iteration 3 +3(0.02%) conflicts; 0(0.00%) untouched conn; 769148 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-769.149ns; real time: 5 secs +Level 4, iteration 4 +3(0.02%) conflicts; 0(0.00%) untouched conn; 769148 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-769.149ns; real time: 5 secs +Level 4, iteration 5 +3(0.02%) conflicts; 0(0.00%) untouched conn; 766523 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-766.524ns; real time: 5 secs +Level 4, iteration 6 +1(0.01%) conflict; 0(0.00%) untouched conn; 766523 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-766.524ns; real time: 5 secs +Level 4, iteration 7 +1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs +Level 4, iteration 8 +1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs +Level 4, iteration 9 +1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs +Level 4, iteration 10 +0(0.00%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs + +Start NBR section for performance tuning (iteration 1) at 05:03:29 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs + +Start NBR section for re-routing at 05:03:29 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 768048 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-768.049ns; real time: 6 secs + +Start NBR section for post-routing at 05:03:29 08/15/23 + +End NBR router with 0 unrouted connection + +NBR Summary +----------- + Number of unrouted connections : 0 (0.00%) + Number of connections with timing violations : 256 (38.67%) + Estimated worst slack : -10.044ns + Timing score : 913247 +----------- +Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. + + + +WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. + Signal=nCCAS_c loads=7 clock_loads=4 + +Total CPU time 5 secs +Total REAL time: 6 secs +Completely routed. +End of route. 662 routed (100.00%); 0 unrouted. + +Hold time timing score: 0, hold timing errors: 0 + +Timing score: 913247 + +Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd. + + +All signals are completely routed. + + +PAR_SUMMARY::Run status = Completed +PAR_SUMMARY::Number of unrouted conns = 0 +PAR_SUMMARY::Worst slack> = -10.044 +PAR_SUMMARY::Timing score> = 913.247 +PAR_SUMMARY::Worst slack> = 0.273 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Number of errors = 0 + +Total CPU time to completion: 5 secs +Total REAL time to completion: 6 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1_par.asd b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1_par.asd new file mode 100644 index 0000000..34f0f5f --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1_par.asd @@ -0,0 +1,30 @@ +[ActiveSupport PAR] +; Global primary clocks +GLOBAL_PRIMARY_USED = 2; +; Global primary clock #0 +GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c; +GLOBAL_PRIMARY_0_DRIVERTYPE = CLK_PIN; +GLOBAL_PRIMARY_0_LOADNUM = 40; +; Global primary clock #1 +GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c; +GLOBAL_PRIMARY_1_DRIVERTYPE = PIO; +GLOBAL_PRIMARY_1_LOADNUM = 13; +; # of global secondary clocks +GLOBAL_SECONDARY_USED = 1; +; Global secondary clock #0 +GLOBAL_SECONDARY_0_SIGNALNAME = nCRAS_c; +GLOBAL_SECONDARY_0_DRIVERTYPE = PIO; +GLOBAL_SECONDARY_0_LOADNUM = 9; +GLOBAL_SECONDARY_0_SIGTYPE = CLK; +; I/O Bank 0 Usage +BANK_0_USED = 36; +BANK_0_AVAIL = 41; +BANK_0_VCCIO = 3.3V; +BANK_0_VREF1 = NA; +BANK_0_VREF2 = NA; +; I/O Bank 1 Usage +BANK_1_USED = 31; +BANK_1_AVAIL = 37; +BANK_1_VCCIO = 3.3V; +BANK_1_VREF1 = NA; +BANK_1_VREF2 = NA; diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/RAM2GS_LCMXO256C_impl1.par b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/RAM2GS_LCMXO256C_impl1.par new file mode 100644 index 0000000..1b6d169 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/RAM2GS_LCMXO256C_impl1.par @@ -0,0 +1,28 @@ +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:23 2023 + +C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO256C_impl1.p2t +RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir +RAM2GS_LCMXO256C_impl1.prf -gui -msgset +D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml + + +Preference file: RAM2GS_LCMXO256C_impl1.prf. + +Level/ Number Worst Timing Worst Timing Run NCD +Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status +---------- -------- ----- ------ ----------- ----------- ---- ------ +5_1 * 0 -10.044 913247 0.273 0 06 Completed + +* : Design saved. + +Total (real) run time for 1-seed: 6 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.drc b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.drc new file mode 100644 index 0000000..ec074a2 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.drc @@ -0,0 +1 @@ +DRC detected 0 errors and 0 warnings. diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.jed b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.jed new file mode 100644 index 0000000..0472a9a --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.jed @@ -0,0 +1,977 @@ + +* +NOTE JEDEC CREATED BY: Lattice Semiconductor Diamond Deployment Tool 3.12* +NOTE Version: Diamond (64-bit) 3.12.1.454* +NOTE Readback: Off* +NOTE Security: Off* +NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * +NOTE All Rights Reserved * +NOTE DATE CREATED: Tue Aug 15 05:03:33 2023 * +NOTE DESIGN NAME: RAM2GS * +NOTE DEVICE NAME: LCMXO256C-3TQFP100 * +NOTE PIN ASSIGNMENTS * +NOTE PINS RD[7] : 71 : inout * +NOTE PINS RD[6] : 70 : inout * +NOTE PINS RD[5] : 69 : inout * +NOTE PINS RD[4] : 68 : inout * +NOTE PINS RD[3] : 67 : inout * +NOTE PINS RD[2] : 66 : inout * +NOTE PINS RD[1] : 65 : inout * +NOTE PINS RD[0] : 64 : inout * +NOTE PINS Dout[7] : 3 : out * +NOTE PINS Dout[6] : 2 : out * +NOTE PINS Dout[5] : 5 : out * +NOTE PINS Dout[4] : 4 : out * +NOTE PINS Dout[3] : 6 : out * +NOTE PINS Dout[2] : 8 : out * +NOTE PINS Dout[1] : 7 : out * +NOTE PINS Dout[0] : 1 : out * +NOTE PINS LED : 57 : out * +NOTE PINS RBA[1] : 83 : out * +NOTE PINS RBA[0] : 63 : out * +NOTE PINS RA[11] : 79 : out * +NOTE PINS RA[10] : 87 : out * +NOTE PINS RA[9] : 85 : out * +NOTE PINS RA[8] : 96 : out * +NOTE PINS RA[7] : 100 : out * +NOTE PINS RA[6] : 91 : out * +NOTE PINS RA[5] : 95 : out * +NOTE PINS RA[4] : 99 : out * +NOTE PINS RA[3] : 97 : out * +NOTE PINS RA[2] : 94 : out * +NOTE PINS RA[1] : 89 : out * +NOTE PINS RA[0] : 98 : out * +NOTE PINS nRCS : 77 : out * +NOTE PINS RCKE : 82 : out * +NOTE PINS nRWE : 72 : out * +NOTE PINS nRRAS : 73 : out * +NOTE PINS nRCAS : 78 : out * +NOTE PINS RDQMH : 76 : out * +NOTE PINS RDQML : 61 : out * +NOTE PINS nUFMCS : 53 : out * +NOTE PINS UFMCLK : 58 : out * +NOTE PINS UFMSDI : 56 : out * +NOTE PINS PHI2 : 39 : in * +NOTE PINS MAin[9] : 51 : in * +NOTE PINS MAin[8] : 50 : in * +NOTE PINS MAin[7] : 44 : in * +NOTE PINS MAin[6] : 49 : in * +NOTE PINS MAin[5] : 45 : in * +NOTE PINS MAin[4] : 46 : in * +NOTE PINS MAin[3] : 47 : in * +NOTE PINS MAin[2] : 37 : in * +NOTE PINS MAin[1] : 38 : in * +NOTE PINS MAin[0] : 23 : in * +NOTE PINS CROW[1] : 34 : in * +NOTE PINS CROW[0] : 32 : in * +NOTE PINS Din[7] : 19 : in * +NOTE PINS Din[6] : 20 : in * +NOTE PINS Din[5] : 17 : in * +NOTE PINS Din[4] : 18 : in * +NOTE PINS Din[3] : 16 : in * +NOTE PINS Din[2] : 14 : in * +NOTE PINS Din[1] : 15 : in * +NOTE PINS Din[0] : 21 : in * +NOTE PINS nCCAS : 27 : in * +NOTE PINS nCRAS : 43 : in * +NOTE PINS nFWE : 22 : in * +NOTE PINS RCLK : 86 : in * +NOTE PINS UFMSDO : 55 : in * +NOTE CONFIGURATION MODE: NONE * +NOTE COMPRESSION: off * + + +QF56640* +G0* +F0* +L00000 +11111111001111111111011110111100111111111101111011110011111111110111101111001111 +11111101111011111111111111111111101111001111111111010111011100111111111101011110 +11001111111111010111101111111111 +11111111001111111111011110111100111111111101111011110011111111110111101111001111 +11111101111011111111111111111111101111001111111111010111101100111111111101011101 +11001111111111010111011111111111 +11111111111111111111111111111111111111111111111111110011111111110111101111111111 +11111111111111111111111111111111101111111111111111111111111100111111111101011101 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111110011111111110111101111111111 +11111111111111110011111111110111101111111111111111111111111100111111111101011101 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111111101111111111111111111111011111011111011111111 +11111111110111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111111110111111111111111111111101111111111011111111 +11111111111011111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111011111111111111 +11111111111111111111100111111111111111111111111111111111111111011111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111111111111111 +11111111111111111111101111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111110111111111 +11111111111111111111111111111111111111111111111110011111111111111111111111111111 +11110111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111011111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111110111111111 +11111111111111111111111111111111111111111111111100111111111101111111111111111111 +11011111111111111011111111111111 +11111111111111111111111111111111111111111111111111111111111110111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111011111111101111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111011111111111111111111111111111110111 +11111111111111111101111111111111 +11111111111111111111111111111101111111111111111111111111111110111111111111111111 +11111111111110111111111111111111111111111111111111111111111111111111111111110111 +11111111111111111111111111111111 +11111111111111111011111111111100011111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111110111111111111 +11111111111111111111111111111111111111111111111111111111111110111111111111111111 +11111111111110111110111111111111111111111111111111111111111111111110111111111011 +11111111111111111111111111111111 +11111111111111111011111111111111111111111111111111111110011111111111111111111111 +11111111111111111101111111111111111111111110111111111111111111111111111111101111 +11111111111111111011111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111101111 +11111111111111111111111111111111 +11111111111111111111111111111111111111110111111111111111111111111111111111111111 +11111111111111111111111111110111111111111011111111111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111101111101101110011111111111111111111111111110011 +11011111001011011111111111111111111111111010111111110001111111101111111011111101 +11111111111111100111011111111011 +11011111111111111111111111111101001110011010011111001111111111111111111111010010 +11011110110111001111000001111111111110011010111111100101111101111111111101111111 +11011111111111101110110111111011 +11111111111111111111111111111110000111100100111111011111111111111111111111010011 +10011110111111011111011101111111111101111111110111101111110101001111111111111111 +01111111111111101101110111111110 +11111111111111111111111111111101001111011110011101011111111111111111111111110001 +01011111110100011111111101111111111111101111011111101110111101101111111111111111 +11101111111111101111111111111111 +11111111111111111111111111111101001101011110011111111111111110111111111111010011 +11111101101111111111111111110111101111111001101011001011111101101111111111101111 +00111111111111101000100111011101 +11111111111111111111011111111110001011111111110111111111111111011111111111100011 +11111101110111001111111111111111111110101010110111111101111111111111011101110111 +01111100010111111101110111111111 +11111111111111111111111111111111001111011111110111011111111111111111111111110011 +11111011110011011111111111111111111101110001110101111101111111001111111101110111 +11111010110011011100100101111101 +11111111111111111011111111111111001111111111010011111111111111111111111111110010 +11001111110111111111111111101111110111110011010110111111111111101010001101110110 +11101111100111111101011111111111 +11111111111111111110011111111110111111111011111111111111111111111111111111101111 +11111011111111111111111001111111111111101101111110110101111110111111110101111111 +11101111110111110011111111111011 +11011111111111111111011111111110011111111101111111111111111111111111111111100100 +01011101111111111111101101111111111111100010111111011111111110101111111001111111 +11110011111111111111111111111011 +11111111111111111111111111111111001111111111111111111111111111111111111111111111 +11011111111111111111010101111111111111110011110111111111111111111111111111111111 +11110011110111111111111111111111 +11111111111111111110111111111111001111111111111111111111111111111111111111111101 +10011111011111111111111101111100111111100010010111111111111111111111111111111111 +11100011111111111101111111111111 +11110001111111111110011001111111111111111101111111111111111111111111111111111101 +11101101110111111111110111110111011111111111111010011101111111111110101011111111 +11111111111111111011111111111101 +11111011111111111110011111111111010001111111110111111111111111111111111111111111 +10011111110111101111001111111111011111110011110111011111111111111001011101111111 +11110000000011111111111111111111 +11111111111111111111111101111101001111011111111111111111111111111111111111011101 +11011011110111011111111101111111011111011101111100111101111101111011101101111111 +11011111110111011101111111111101 +11111111111111111111111101111111001111111011101111111111111111111111111111111111 +11010110101111111111111111101010011111111111100111111111111111111111010111111111 +11111101110111111101111111111101 +01111111111111111111111111111111111110111101010111111111111111111111111111110011 +11111111110110011111111111010111100101011111111110101000110111111000111101111111 +11111111110111111110011111111011 +01011111111111111111111111111101110111011011110111111111111111111111111111010011 +10011111100111110111111111110111111000011011110111001100000101111011011011111111 +11011110111111111111111111111011 +11111111111111111111111111111111111011011111111111111111111111111111111111110001 +11111111111111111111111111101111111101111011101111111101111101001111011111111111 +11111110010111111111110011111111 +11111111111111111111111111111110111111011111101111111111111111111111111111100011 +11011110111111111111111111111111111101101101110111110011111111001011011111111111 +11101111110111111111111111111110 +10111111111111111111111101111111111100111111111111111111111110110111111111111111 +11101001111111111111111101110110111111110101111111011111110001101011111111111111 +11111111101111011111111110111101 +11111111111111111111011001111110110011011111111111111111111111011111111111101110 +11000101111111111111101101110111011111100010111110011111110111101010011111111111 +11111100110111111111111101111111 +11111111111111111111111111111111110111011111111111111111111111101111111111111111 +11111001111111111010110001101111111111110011110111101101111111101111011111111111 +11111011010110101101111100011101 +11111111111111111011101111111110001111011111111111111111111111111111111111111011 +00111111111111111111011100111111111111100111011011111111101111101101111111111111 +11101110110111111111111111111111 +01111111111111111111111111110110111111111111111111111111111111111111111111101111 +01111111111111011100111011111011101101101011110110101110000110111111111111111111 +11100011111110100111111101111011 +01011111111111111111111111110110110001011111111111111111111111111111111111100010 +11111111111111111100111101111011111011100010010111011111110010111111111111111111 +11110011111111001111111111111011 +11111111111111111111111110101111110110011111111111111111111111111111111111110011 +11111111111110111100111111111101110100110111100111101111110011001111111111111111 +11110011111111111111110000111111 +11111111111111111111111111111110111111011111111111111111111111111111111111100101 +11011111111111111100101101111011111111101101110111101101111111111111111111111111 +11101111111111101111111111111111 +10111111111111111111111111111111111111111111111111111111111110111111111111110111 +11111101010111111111111111110111011111111011111101010101110111101111111100111111 +11111110011111101111111111111101 +11111111111111111111111111111111001111111111111111111111111110011011111111110010 +11111001110111111100101111110110111111110010100111011101111111101111111101111111 +11111110100111101111111111111111 +11111111111111111111111111111101001111111111111111111111111111110111011111010011 +01111111111111110100111111111111111111010111011110111111111101001111111110010111 +11010011110111111101111111011101 +11111111111111111111111111111111111111111111111111111111111111111111111111110111 +11101111101111111111110110101111111111011111111111111011101111111111101011111111 +11111101110111110111111111111101 +11111111111111111111111111111111111100111001111111111111111111111111111111110111 +10111000111111111101111111111110011111111110011111111110110111111111111001010111 +11110111011110011111111111111011 +11111111111111111111111111111111110011011101111111111111111111111111111111011100 +11011101111111110111000101111111011111011010110111111111110111111111011101110111 +11010110100111011111111111111011 +11111111111111111111111111111111110111011111111111111111111111111111111111011110 +01011111010111111111111001111110011111111001110111111110000111110111111011101111 +11110011111110111111111111111110 +11111111111111111111111111111111111111011011111111111111111111111111111111111111 +11011011110111111011011101111111011111101111100111111110111111111110011111111111 +11100011111111111111111111111111 +11111111111111111111111111111111111111010111111111111111111110110111111111010111 +11111001111011111111111110010011111111111101111011011111111011111111111101111111 +11110001111011011110110111111101 +11111111111111111111111111111111111011011101111111111111111111011111111111100011 +11011100000111101111111111100001011111101010111110011111110111111000011111111111 +11100010111110011110110011111111 +11111111111111111111111111111111110100011111111111111111111111101111111111110001 +10111110011111011111111111010010111111111011110001011111111111110111111011111111 +11110011110101111111100111111101 +11111111111111111111111111111111111111011111111111111111111111111111111111110011 +11011010101101111011111111110001111111110011011011111111111111111111011111111111 +11100011011011111111011111111111 +11111111111111111111111111111111111111111111100111111111111111111111111111100011 +11111111110011111011101111101110011111100111111111111111110111111111111001111111 +11100010011101011111111111111011 +11111111111111111111111111111111111111111111110111111111111111111111111111100000 +10011111101101101110101111110111011101100100111111111110100111111111111101111111 +11100010110111011111110101111011 +11111111111111111111111111111111111111111111111111111111111111111111111111110011 +01011111111111011110111101111110111111111111010111111111111111111111111011111111 +11110011100111111111111111111111 +11111111111111111111111111111111111111111111101111111111111111111111111111110011 +11111111111111110011110111111111111101101111111111111111111111111111111111111111 +11101101110110111111110111111111 +11111111111111111111111111111111111111011111011111011111111111111111111111110011 +10111101111011011111111110110111111111110110011111011011110111111111100101111111 +11111111111111111111111111111101 +11111111111111111111111111111111111011111111110111111111111111111111111111110110 +11011111111101011110111101111111111111110110110111011101111111111111111001111111 +11111111111111111111110111111111 +11111111111111111111101101111111111101011111111111111111111111111111111111010101 +01111111111111010110011011010011011111011111100111111111110111111111101101111111 +11010011111011011110111111111101 +11111111111111111111111111111111111111111111111110111111111111111111111111110011 +11011011111010011111111101100111111111111111111010111110101111111111110111111111 +11111111111111111111111111111101 +11111111111111111111011111111111111111111111111111111111111111010111111111110111 +01111111111111111111100111111111111111111101011110011111111111111111111111111101 +11111111111111111111111011111111 +11111111111111111111011111111101111111111111111111111111111111100111111111011110 +11011111111111110100101101111111111111011110111110011111111111111111111101111001 +01111111110111111111111011111111 +11111111111111111111111111111101101111111111111111111111111111111111111111111111 +11111111111111111100111101111111111111111111110111111111111111111111111111111011 +11111101101111111110111111111111 +11111111111111111010111111111111101111111111111111111111111111111111111111101101 +10011111111111111011011001111111111111111111111111111111111111111111101111111010 +01111111110111111110111111111111 +11111111111111111111111111111101001111111111100111111111111111111111111111110111 +10001001111111111100111110110111101111111011110110000011111111111111001011111111 +11111101111011110101111111111111 +11111111111111111111111111111110001111111111110111111111111111111111111111111110 +01011101111011111100001110010111100101111110110111001101111111111001011101111111 +11111110111111101101111111111111 +11111111111111111111111111111111101111111111111111111111111111111111111111111111 +11011101111101011100110101110111101111101111110111111111111111111111010101111111 +11111111110101111111111101111111 +11111111111111111111111111111111101111111110111111111111111111111111111111101110 +11010001111011111000111110101111100011111101000110101111111111111010011101111111 +11111111011111101011111111111111 +11111111111111111111111111111110101100011001111111111111111111010111111111100011 +10111111111001011000111101111111011111111111100110111101111111111111111000111111 +11111111111110111111111111111111 +11111111111111111111111111111110001011011101111111111111111111110111111111110011 +11011111111001111100100001111111111111111110010111011111111111111111111100111101 +11111111111111011111111111111111 +11111111111111111111111111111111001111011111111111111111111111101111111111110001 +11111111111111011100111101111110111111111111110111111011111111111111111011110111 +01111111111111111111111111111111 +11111111111111111111111111111111100111011011111111111111111111111111111111100011 +11011111111111110000011101111111111111111110110111111111111111111111111111011111 +11111111111111111111111111111111 +11111111111111111111111111111111101111111101011111111111111111111101011111110011 +11111100111010011100111110010111011111111011110011011111100011111110001110110111 +11111111110111111111111111111111 +11111111111111111111111111111111101011011111110111101111111111111111011111110011 +11011111011111011100111111100111111111111010110111011111110111111001011111111111 +11111110100111111111111111111111 +11111111111111111111111111111101100110111011111111011111111111111110111111010011 +11111110110111110100111110110111111111011111110100011111111111111111011110100111 +11111111010111111111111111111111 +11111111111111111111111111111111101101011111111111111111111111111111111111111011 +10111011111111111110111111011110111111111101000011011111111111111011010111011111 +11111101110111111111111111111111 +11111111111111111111111111111111111111111111110111111111111111110111111111111111 +01101111111111111000111111111111111111111111011001011111110111111111101101111111 +11111111111010011111111111011011 +11011111111111111111111111111111111111101111111111111111111111111111111111111100 +10010111111111111011100001111111111111011100111101011111110111111111111011111111 +11111111111101011111111111111011 +11111111111111111111111111111111111111111101111111111111111111101111111111111101 +11011111111111111111111111111111111111110011110111111110111111111111111101111111 +11111111111111011111111111111111 +11111111111111111111111111111111111111111110111111111111111111111111111111111111 +11011111111111111100111111111111111111100010110110111111101111111111110101111111 +11111111111110011111111111111110 +11111111111111111111111111111111111111111111111011111111111111010111111111111111 +11111111111111111100111110010110111111110011101101111111111011111111111111111111 +11111111111111111111111100111101 +11111111111111111111111111111111111111111111111101011111111111110111111111111111 +11111111111111111011111111110111011111100000110111011101110111111111111111111111 +11111111111111111111111111011111 +11111111111111111111111111111111111111111111111011011111111111101111111111111111 +11111111111111111111111111100111011111110001010111111111111111111111101101111111 +11111111111111111111111101111101 +11111111111111111111111111111111111111111111111011111111111111111111111111111111 +11111111111111111111111111010111011111110011110111111101111111111111111111111111 +11111111111111111111111101111111 +01111111111111111111111111111111111111101101111001111111111111010111111111111111 +11100101111110111000111111100111111111101110111011011111111111111111111101111111 +11111111111011111111111111111011 +01011111111111111111111111111111111111111111111111111111111111110111111111111111 +11110001111111111000111111110111111111101110111101111111111111111111111111111111 +11111111111111111111111111111011 +11111111111111111111111111111111111111111001111101011111111111101111111111111111 +11111101111111011100111110100111111111111111110110111111111111111111111111111111 +11111111111001011111111111111110 +11111111111111111111111111111111111111110101111111111111111111111111111111111111 +11111101111111111111111111111111111111100010010111111111111111111111111011111111 +11111111111111111111111111111111 +10111111111111111111011111111111111111111011111111111111111111100111111111111111 +11101101111111111111111110110111011111111111111011011101111111111111111111011111 +11111111111111110111111111111101 +11111100111111111111011111111111110001011101111111111111111111100111111111111111 +11110011110111111100111111100111011111111111111100111101111111111111111111110111 +11111111111011111101111111111111 +11100111111111111111111111111111111111011111111111111111111111111111111111111111 +11101101111111111000111111110111011111011111111111111101111111111111111110111111 +11111111111111001111111111111101 +11111111111111111010111111111111111110111111111111111111111111111111111111111111 +11111111101111111011111110010110111111111011111111110111111111111111111110111111 +11111111111111101111111111111111 +01111111111111111111111111111111101111101111010111111111111111111101011111111111 +11101101111111111111111110111110101101111111111111101101111111111111101001111111 +11111111111011111111111111111011 +01011111111111111111111111111101111111111111110111111111111111111111011111111111 +11111111111111111000100001011111001101111111110111111111111111111111110101111111 +11111111111101111111111111111011 +11111111111111111111111111111111111111100101101111111111111111111110111111111111 +11111001111111111100111110110111110001111111101111110001111111111111111011111111 +11111111111111111111111111111111 +11111111111111111111111111111111101111111111111111111111111111111111111111111111 +11110101111111111111111111111111111110111111111111111101111111111111111111111111 +11111111111111111111111111111110 +10111111111111111111111111111111101100111110111111111111111111111111111111111111 +11111111111111111111111110110111101111111111111001010101111111111111100101111111 +11111111111111101111111111111101 +11111111111111111111111111111111111011011111111111111111111111111111111111111111 +11111111111111111000111111110111111111111111111111011101111111111111100101111111 +11111111111111101111111111111111 +11111111111111111111111111111110111111111110110111111111111111111111111111111111 +11111101111111111100111111110111111101111111111110111011111111111111111001111111 +11111111111111110101111111111101 +11111111111111111111111111111111001111111111011111111111111111111111111111111111 +11111101111111111100111110000111110110111111111101111111111111111111111111111111 +11111111111111111111111111111111 +01111111111111111111111111111111001111111101111111111111111110111111111111111111 +11101101111111111000111111111111111101111110011010110001111111111111101001111111 +11111111111011111111111111111011 +01011111111111111111111111111111111111111111111111111111111110011111111111111100 +11111111111111111000111111111111101001111110100101000101111111111111110101111111 +11111111111111111111111111111011 +11111111111111111111111111111111111111111011111111111111111111110111111111111111 +11011001111111111100111111111111111111111101110111101111111111111111111111111111 +11111111111111011111111111111110 +11111111111111111111111111111111001111111111111111111111111111111111111111111101 +01010101111111111111111111111111111111111111110111101111111111111111111011111111 +11111111111101011111111111111111 +10111111111111111111111111111111001111111111111111111111111111111111111111111111 +11101111011111111111111110010111101111111111111001011111110011111111111111111111 +01111111111111111110111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111110111111100111111110111110111111110110111011111100111111111111101111111 +01111111111111111111111111111111 +11111111111111111111111111111101001111111111111111111111111111111111111111111111 +11110101111111111000111111100111111100111101011110111111111111111111111111111010 +11111111111111111111010111111101 +11111111111111111111111111111111001111111111111111111111111111111111111111111111 +11111101111111111011111111010111111111111111100101111111111111111111101111111111 +11111111111111111110111111111111 +11111111111111111111111111111111111101101001111111111111111111111111111111111111 +11101111111111111111111110101111111111111111111011111111110011111111111111111111 +11111111111011111111111111111111 +11111111111111111111111111111111110010011101111111111111111111111111111111111111 +11111111111111111000100001010111111111011111111111111111110111111111111111111111 +11111111111101111111111111111111 +11111111111111111111111111111111111111011101111111111111111111111111111111111111 +11111111111111111100111110110111111111111111111101111111111111111111111111111111 +11111111111111011111111111111111 +11111111111111111111111111111111110111010001111111111111111111111111111111111111 +11110111111111111111111111111111111111100111111111111111101111111111111111111111 +11111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111111111111111 +11111111110111111111111110100111111111111111111110010111111111111111111111111111 +11111111111011111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111011111111000111111110111111111101111110111001101111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111011111111111111111 +11111110111111111100111110110111111111111111101111101001111111111111111111111111 +11111111111011011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111110111111111100111111001111111111110101110110111111111111111111111111111111 +11111111111101111111111111111111 +11111111111111111111111001111111111111111101100111111111111111010111111111111111 +11101101010011111000111110111111111111101111111001001101110111111111101000111111 +11111111111001011111111111111111 +11111111111111111111111101111111111111111111110111111111111111110111111111111111 +11101101110111101000111111011111111111101111110101011111111111111111111101110111 +11111111111101011111111111111111 +11111111111111111111111011111111111111111011101111111111111111101111111111111111 +11110001101111011100111111110111111111111001111111011001111111111111110001010111 +11111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11101111111101111111111111110111111111101011100110010101101111111111111100110111 +11111111111110011111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111111111111111 +11101101111111111111111111111111111111111111111110001110100011111111101111111111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111100111111111111100 +11011111111111111100111111111111111111111101110111011111100111111111100111111111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +10011101111111111000111111111111111111011110110111111111110111111111111101111111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111111111111111 +01110001111111111011111111111111111111111111100110110111011111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111111111101111111111111111111111111111111111111011 +11101111111111111111111110101111111111111111110011111111111111111111111111111111 +11111111111010011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111010011 +11111111111111111000100001010111111111010110111101111111111111111111111111111111 +11111111111100011111111111111111 +11111110111111111111111111111111111111111101111111111111111111111111111111110011 +11100101111111111100111110110111111111110111110111111111111111111111111111111111 +11111111111111011111111111111111 +11111110111111111111111111111111111111110101111111111111111111111111111111100011 +11111111111111111111111111111111111111101011011111111111111111111111111111111111 +11111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111011 +11111111111111111111111111010111111111111111111111011011111111111111111111111111 +11111111111111011111111111111111 +11111111111111111111111111111111110001111111111111111111111111111111111111100011 +11111111111111111000111111100111111111101111111111011101111111111111111111111111 +11111111111111011111111111111111 +11111111111111111111111111111111111111011111111111111111111111111111111111110011 +11111111111111111100111111111111111111111111111110101101111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111110011 +11111111111111111100111111111111111111111111111011111111111111111111111111111111 +11111111111010111111111111111111 +11111111111111111111011111111111111111101111111111111111111111111111111111101111 +10110101111111111000111110111111111111101110011011111101110011111111111101111111 +11111111111111011111111101111111 +11111111111111111111111111111111111111110111111111111111111111111111111111101111 +11011001111111111000111111011111111111100110111111111111110111111111111111111111 +11111111111111111111111101111111 +11111111111111111110111111111111111111101101111111111111111111111111111111111111 +11111111111111111100111110110111111111111111110101111011111111111111111111111111 +11111111111111111111111110011111 +11111111111111111111111111111111111111111111111111111111111111111111111111100111 +11111111111111111111111111111111111111101111111111111111101111111111111011111111 +11111111111110111111111111011111 +11111111111111111111111111111111111111111111111111111111111110111111111111111111 +11111101111111111111111110111111111111111111010011111111100011111111111111111111 +11111111111111111111111101111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111011111011101100111111111111111111110110100111111111110111111111111111111111 +11111111111011111111111111111111 +11111111111111111111111111111111111111111111111111111111111111010111111111011111 +11111111111101011000111111110111111111011111110111011111111111111111111111111111 +11111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111011111111010111111111111101110101011111111111111111111111111111 +11111111111111111111111111111111 +01111111110111111111111111111111000111101011111011111111111111010111111111111111 +11011111111111011111111110110111111111110010101011110010111111001111101111111101 +00111011111011011111110111011011 +01011111010011111111111111111101001000001101111101111111111111110111111111111110 +11111111111111011000100000101111111111010010010101101101111101101111111111111111 +01011011111111111110110111111010 +11111111110011111111111111110111001111010101111111011111111111101111111111111111 +11011101111010111100111111110111111111110111110111101111111111101111101101111111 +01011011111100111111101101111111 +11111111100111111111111110111110101011011111111011111111111111111111111111111111 +01111101111111111111111111011111111111100001110111111101011110001111110111111110 +11110011111111111111111111111111 +10111111110111101111111011110111001111101111101111101111111111100111111111111111 +11111001011111111111111110100110111111110010111111011011110011001110100101011111 +11010011111011111110111010111101 +11111111110011110111111101100010000001111111110111011111111111110111111111111111 +11101101111111111000111111010111011111100011111111111101100110000111010001110111 +01110010110101111101110011111111 +11111111110011111111111100110111001111011101110111111111111111101111111111111111 +11111001110111111100111110110111011111110011110111111101111111001111011101110111 +11111011111111011111010101111111 +11111111110101110111111101111111001111110101110111111111111111111111111111111111 +11111111111111111100111111101111011111100011111110111111111111001111111101110111 +01110011001111011101111111111111 +01111111100111111111111111111110000111110101111111111111111111110111111111111110 +11111111111111111000111111110111111111101111011010011100010010110111111001111111 +01101011001111011111111111111011 +01011111110111111111111111111110001111111101111111111111111111111111111111111110 +11111111111111111000111111111111111111101010111101011111100110111111111101111111 +01101010110111011111111111111011 +11111111111111111111111111111111001111001101111111111111111111101111111111111111 +01011111111111111100111111100111111111111011111111111111110111110111011011111111 +11111011111110111111111111111111 +11111111111111111111111111111110111011011011111111111111111111111111111111111111 +11111111111111111111111111110111111111101111111110111101011110111111011111110110 +01111011111011111101111111111111 +10101111110011111101011111111111001111111001110111111111111110110111111111111111 +11101111110111111111111110100111011111111111101010111111110011111110111101111110 +11111111111101010111111111111101 +11101111110000110110011111111111001111111001111111101111111111000111111111111111 +11111111110111101100111111110111011111111010010111011101110011111001001101111111 +01110011111110011101111111111111 +11111111011001110111111111111101001111111111110111011111111111111111111111111111 +11111111110111011000111111110111011111011001111111111101100101111011111001110011 +01010011111111101101111111111101 +11111111111011000111111111111111111111111111111111111111111110111111111111111111 +11110111101111111011111111000110111111111111110101110111111111101111001111111111 +11111111111111101111111111111101 +01111111111011011111110101111111001101011011100111111111111110110011111111110011 +11111011110111111111111110110111001111111101101001010111110011100111101111111111 +11111101101111011111111111111011 +01011111010000111111111101111101001011111101110011011111111111100011111111010011 +11111101100111111000100000110111011111011111110111011101110101111111010111111111 +11111110010110111111111111111011 +11111111010011110111111011111101000111011111101111111111111111011101011111010011 +11111111111111111100111111100110110100110111110011011111101101111110011111111111 +11111111110111111111111111111111 +11111111010011111111111111111111001111011111111111111111111110111111111111110011 +11111110111111111111111110011011111111100101110100111111111111111111111111111111 +11111111111111111111111111111110 +10111111011011111111111111111101001111101111011111011111111111111111111111010011 +11101101111111111111111110011111101111111110011111011110110101000111111000111111 +11111111111011101110111111111101 +11111111110011110111111111111110001111011111110011011111111111111111111111100011 +10011101111111111000111111110111110111101110111110011111101110011001111101111111 +11111111111111111111011111111111 +11111111110011111111111111111111001111111101111111111111111111111111111111110011 +11111101111111111100111111110111111101110011110111111111110111001111011111111111 +11111111111111011111110111111101 +11111111110011101111111111111111000110010101111110111111111111111111111111100010 +11000001111111111100111111010111111110110110110011111111011010001111111011011111 +11111111111101010111110111111111 +01111111100011111111111111111110001100011111111111011111111111010111111111101110 +11111010011111111000111111100111111001101111101011010100100110001111111101111111 +11111111111101010111111111111011 +01011111110011111111111111110010001011011111111110001111111111100111111111101110 +11111100110111111000111111100111101101101100010111101110110110001111111011111111 +11111111111111001011111111111011 +11111111110011111111111111111111001111011111111111111111111111111111111111111111 +11011110100111111100111111110111111111111110110110101111010111001111111111111111 +11111111111111001101111111111111 +11111111110011111111111111111111000111011111111111111111111111111111111111111111 +01111110111111111111111111110111111111101111110101101101110111101111111111111111 +11111111111110001111111111111110 +10111111111111111111101010011111011111111110010001011111111111100111111111111110 +11101111110111111111111111110111101111111101101111011111110011001111111110110001 +11111110111011111110110111111101 +11111111111111111111111101111111011111111111110111111111111111110111111111111010 +11011111101111111100111111110111111111110110010111111111110111001011011111111111 +11111110010101111111110111111111 +11111111010011111111110111110001011011111111101111011111111111101111111111011001 +01011111111111111000111111101111111101011111110111111111101101001001111111001111 +00111111100111011110000111111101 +11111111110011111111111111111111011111011111011110011111111111111111111111111111 +10010111111111111011111110111111110110111111111110111111111111101110011111111111 +11111110110111011110111111111111 +11111111111101111011111111111111111111101101101111001111111111100111111111011011 +11111110011111111111111111111111111111110011111110111110010011111100100101111111 +11111111111001011111111111111111 +11111111111111111111111111111101011111110001110111011111111111110111111111010011 +11111111110111111000100001110111111111010010100111011111110101110011011101111111 +11011111111101011111111111111110 +11111111111111110011011111111101011111111101111111111111111110100111111111110011 +11111101111111111100111111110111111111110001111011011111100101111111010101111111 +11111011111111111111111101111111 +11111111111111111101111111111111111111101101111110111111111111111111111111100010 +11011101011111111111111110110111111111101011010111111111011111111011011001111111 +11101011111110111111111111111111 +11111111111111101111111111111101111111111111111111111111111111111111111111110011 +11111111111111111111111110110111111111110011111010011111111101111011110111111111 +11110110111111111111110010111111 +11111111111100110111111111111111011001111111100111111111111110111111111111100011 +11111110100111111000111111000111111111100010011111011111111010011001011101111111 +11100110010011111111110111111111 +11111111111101010111111111111111011111111111101111111111111111110111111111110011 +11111111101111111100111111111111111111110010111011011111110111111011011111111111 +11110010110111011111101111111111 +11111111111111110111111111111111111111111110111111111111111111111111111111110011 +11111110011111111100111110111111111111111011110100111111111110111110011111111111 +11110011100111111111111111111111 +11111111111111111111111111111110001111111111100111111111111111111111111111100011 +01111011100111001000111111100111011111100011111111111110100110001101101101110111 +10100110111010011111111111111111 +11111111111111111111111111111111001111011111100111111111111111111111111111100000 +11111101110111011000111111100111011111100011111111011110110110000010010001110111 +01100010111110011111111111111110 +11111111111111111111111111111111001110111111111111111111111111111111111111110011 +11011111111111111100111111110110111111110011111111111111100111000111011111111111 +11111011110101011111111111111111 +11111111111111111111111111111111001111111111111111111111111111111111111111101111 +11111111101110111111111111110011111111101111111011111111011111101111001110101111 +11101111011111011111111111111111 +11110011111111111111111111111111001111101111111011001111111111100111111111110011 +11111111111111111111111111100111111111110011111111111110110011101111101001010011 +11110111111111111111111111111111 +11111111111111111111111111111111001111110111111111011111111111110111111111110000 +11011111110111111100111111100111111111110000111111011111110011001111110001110111 +10110011111111111101111111111111 +11111100111111111111111111111101000111101101111111111111111111101111111111010001 +00011111111111111000111111111111111111010011010111111111010101001111111111101111 +01011011111111111111111111111111 +11111111111111111111111111111111101111011111111100111111111111111111111111111111 +11011110111111111011111111111111111111111110110011111111101111101111111111111101 +11111111111111101111111111111111 +11111111111111111111111110101111011110100101111111111111111111111111111111111111 +01100101111111111111111111111111111111111101111011011111111111110101101101111111 +11111111111110111111111111111111 +11111111111111111111111110110001000001010101111111111111111111111111111111011000 +11001101111111111000100001111111111111011110010111011111111111111011001101111111 +11111111111111011111110111111111 +11111111111111111111111110011111001111011011111111111111111111111111111111111101 +11010101111111111100111111110111111111011011100100011111111111111111011001111111 +11111111111111011111101111111111 +11111111111111111111111110111111010111011111111111111111111111111111111111101111 +10011011111111111111111111110111111111111110110011011111111111111110100111111111 +11111110110111011111111111111111 +11111111111101111111011101111111011110101111101011111111111111111111111111111111 +10111001111111111111111110100111111111011111011111011111111111111110101111011111 +11111111111011111111111111111111 +11111111111110111111111111111111011111011111110111011111111111111111111111101011 +11001101111111111000111111010111111111101100110111001001111111111011010110100111 +11111111111101111111111111111111 +11111111111111010111111111111110011111100100110011111111111111111111111111111011 +11111001111111111100111111101111111111111110100110101101111111111111111100100111 +11111111111111011111111101111111 +11111111111111111110101111111111011111111111111110111111111111111111111111111111 +11111111111111111100111111111111111111101111110011100011111111111001011100111111 +11111111111111011111111111111111 +11111111111111111111101001111111011111101111100111011111111111110111011111100010 +11101101100111111000111111100001011111100001101111110101110111111111111100111101 +01111111111011111111111111111111 +11111111111111111111101101111111011011011111110001011111111111100111111111100010 +11011011110111101000111111100011011111100011110111111100111011111111111001011011 +01111111111111111111111111111111 +11111111111111111111111101111111111111111111111001011111111111111110111111111110 +00010101101111011100111111111100011111110011110111111111110111111111111111111111 +01111111111101011111111111111111 +11111111111111111111110011111111111100110111101110111111111110111111111111101111 +11011101111111111111111111111111111111110011111111111011010111111111101111111010 +01111111111111011111111111111111 +11111111111111111111111111111111011101111111100111111111111111100111111111111111 +11101001111111111111111110110111111111110011110111011111111111111111111111010011 +01111110111111111101111111111111 +11111111111111100111111111111111001011111111110111111111111111110111111111111111 +11110001111111111100111110000111111111110110111110011110111011111111011111110111 +11111110111111111111111111111111 +11111111111111111111111111111101001011111111111111111111111111101111111111011111 +11111101111111111000111111110111111111010011110111111111010111111011101101101111 +11111111010111111111111111111111 +11111111111110110111111111111111011111011111101111111111111111111111111111111111 +11111101111111111011111110111111111111110011011011111111111111111110011111111111 +11111111111111111011111111111111 +01111111111111111011111111111111101011111111111111111100111111111111111111111011 +11111110101111011111111110111110001111111111101011111111111011001111101111111111 +10111111111001011111111111111011 +01011111111111111111111111111101111001111111111111010100111111111111111111011011 +11111111110111111000100110111011010110011110010111111111110001001111111111111111 +01010011111101011111111111111011 +11111111111111111011001111111111110111011111111111110100111111111111111111111011 +11111111111111111100111111110001011101111101111101111111110111111111110111111111 +11011011111111111111111111111111 +11111111111111111101111101111111111111011111111111011100111111111111111111101011 +11111110111110111111101101011011111111101111110111111111111110111111111111111111 +11110111111110111111111111111111 +10111111111111111111111011111111111111011101111111010100111111100110111111110011 +01011101100111011111111111110011111111111110101011011100101111001011101001101111 +11011111111011111011111111111101 +11111111111111111111111111111111111011011011111111111000111001100111011110110010 +11011001110111111000111111100111011111100010110100011101111110001000001001110111 +01110011110101111101111111111111 +11111111111111111111111101111110111111011111111111111100101111111111011101110011 +11011111110111111100111111111111111111111101010011011111110111001011010101110011 +11111010101111111101111111111101 +11111111111111111111111111111111110100011111111110111100111101111111011111100011 +10101111110110111100111110111111011111101111110011101011011110001111011111111111 +11110111110111111111111111111101 +11111111111111111111111110111111111011111111111111111000111111111111111111101111 +01011111101101011000111111111101111111100010001011111111111110110110111111110010 +01100011111011111101010111111011 +11011111111111111111111111111111011011011111111111111000111111111111111111110110 +11111111111110011000111111111111111111100010110111111111111110111011011111111111 +01110011111101111111100111111011 +11111111111111111111011111110111111110011111111111111100111111111111111111111111 +11011111111011011100111111111111111111110001110011011111111111001101011111111010 +01110011111111011110110111111111 +11111111111111111111011110011111111001011111111111111100111111111111111111101111 +11111111111111111111111111111111111111100011110101111111111111001011011111111101 +11110011111111011111111111111110 +11101111111111110110011111111111111011111111110111111100111011111111111101111110 +11100111110111011111111010111111101101111011111011011100100011001011111111111111 +01110011101111111111110111111101 +11101111111111111111011111111011111011111111110111111100100101111111111101111110 +01001101111110011100111100111111011001111011111100011101110111001010001111111111 +01110010010111111111100111111111 +11111111111111110111111111110101111101011111110111110111111111111111101011011111 +11010101110011111000011111010111101111011011111111011101110101001011011101111010 +11011111111111111110111111111101 +11111111111111111110111111111111111011011111101111111100011101111111111111111110 +10011111111111111011111101111101110111111011111011010111001111001101011111111111 +11111110110111111111111111111111 +01111111111111111111100101100011000111111111110111001111111011111110011111110011 +11101111010111111100111111111111100111111111011111111110110111001111111110110111 +11110110111111101111111111111011 +01011111011011111111101101110101101011011111111111010110111101111111011111010011 +11010111110111110110100001111111111111111100111111111111010001111111111101110111 +00010010011111111111111111111011 +11111111010011111111111001111111101100011101111111110110111111111111111111100011 +10111101111111111110111111111111111111111111110111111111100001101111111111110111 +11010011110111111101111111111111 +11111111110011111111110111111111001011011101101110111111111111111110111111010010 +11011101101111111000111111111111111111111111111111111111111101101111101110000111 +11010111111111110101111111111111 +10111111011111111111110101111111111111101001101011110100011010111111111111010001 +01101101111111111100111110111111111111111111111011001111110001001101101001110111 +11010010111011111111111111111101 +11111111100000110111011101111111101011111101110111111110101101011111111111101110 +11010111111111111000001001011111111111111111111110001111110110001011001001111111 +11100010110111111111111111111111 +11111111110001110111111111111110101101111101111101001110110101111111111111110011 +11011111111111111100101100110111111111111111111011010101111111101011111101111111 +11110011110011011111111111111101 +11111111111111000011111011111111001111110001111111111111011101111111111111110010 +10011011111111111000110101111111111111111111111001111111101111101110010111101111 +11111110000101111111111111111101 +01111111100011111111111111111111001110111111110011111000111111111111111111100011 +11111110111011111011011111111111111000111111011111111101111010001111111111101111 +11101011111111111111111111111111 +01011111100011111111111111111111001111011111110101111000111111111111111100101111 +11111111010101111011101111111111111101111110100111111101110110101111111111100111 +11100011111111111111111111111110 +11111111110011111111111111111111100111111110111111011100111111111111111111111011 +11111110111111001111110101111111111111111111111111111011111111001111111111111111 +01110011111111111111111111111111 +11111111100011111111111111111111101111011110100111101100111111111111111111111011 +11111110101111111011111111111111111111111110110111101111111111001111111110111111 +01111011111111111111111111111111 +10111111110111111111111111111111001101011101111111111100111110111111111111110011 +11101111110011111111111110110111111001111110011011010100111111001011101110111111 +11111111111111111111111111111111 +11111111110111111111111111111111001011011111111111111100111111111111111111110010 +11010111111111111111111111101111101101111110100111111101111111001011110111111111 +11110011111111111111111111111111 +11111111010111111111111111111101101110011111111111110100111110110111111111010010 +00111111101111110100111111010111111111111111110101011111010101001101011100010111 +11011111111111111111111111111111 +11111111110111111111111111111111101111111011111111111101111111011111111111110011 +11011111111101111111111111110111111111111110110110011010111111001011011101111111 +11111111111111111111111111111111 +11111111111111111111111111111111111101111111101111111111101110111101011111011111 +10111111110011111111111111111111111111011111111011111111111111111011101111111111 +11111110111111111111111111111111 +11111111111100111111111111111101101011111111110111111111100101111111011111011110 +11011111101101101111101101111111111111011111111111111111111101111010011111111111 +11111110110111111111111111111111 +11111111111111110111111111111111111111111101111111111111101001011110111111110101 +11111111111111011111111111111111111111111111111101111111111111111101010101111111 +11111111010111111111111111111111 +11111111111111011111111111111110111111111101111111111111111101111111111111101111 +01011111111111111111110011111111111111101111111111111111111111011011011101111111 +11111111101111111111111111011111 +11111111111111111111111111111111111011111001111111101111111110111111111111111111 +01111101111111111111111110111111111111111111111011011111111111111111111001111111 +11111110111011111111111111111111 +11111111111111111111111111111110111011011001111111001111111111111111111111101100 +11011101111111111111111111111111111111101111110111011111111111111111111101111111 +11111110111101111111111111111111 +11111111111111111111111111111111111000011111111111011111111110010111111111111111 +11011011111111111111111111010111111111111111101000011111111110111111111011111111 +11111111110111111111111111111111 +11111111111111111111111111111111111111011111111111111111111111111111111111111111 +10101111111111111111111111110111111111110110110011111111111111111111111111111111 +11111111011111111111111101111111 +11111111111111111011111111111110001100111110110111111111111111111111111111101111 +11011101111111011111111111111111111100101110111111111110101111111111111111111111 +11111111111011111111111111111111 +11111111111111111111111111111110110011011110111011011111111111111111111111101111 +11011111111111011111111111111111111101101110010111111111111111110111011111111111 +11111111111101111111111111111111 +11111111111111111111111111111111110111011111100111111111111111111111111111111111 +10011011111010111111111111111111111111111011110111111111110111111111011111111111 +11111111111111011111111111111111 +11111111111111111101111111111110111111011111011111111111111111111111111111101110 +11011111111111111111111111111111111011111111101111111111011111111010011111111111 +11111111111111011111111111111111 +11111111111111111111111111111111001100101111111111111111111111111111111111110011 +11101111111111111111110110110111111111111111111010001111110111111111111111111111 +01111111111111111111111111111111 +11111100111111111111111111111111010011011111111111011111111110111111111111111111 +11111111111111111111101101011111111111111101111110011111110111101111111111111111 +01111111111011111111111111111111 +11111111111111111111111111111101010111010101111111111111111111110111111111011111 +11110101111111111111101011111111111111011111110011011110101101111111111111111011 +11111111111111011111111111111111 +11111111111111111111111111111111111111011101111111011111111111111111111111111111 +11111101111111111111111101101111111111111111111101110111111111111111111111111110 +11111111111111111111111111111111 +11111111111111111111111111111111110111111111111111111111111111111111111111111101 +11111111111011111111111111111111111111111010011110111111111111111101111111111111 +11111111111111111110111111111111 +11111111111111111111111111111101001110011111111111111111111111111111100111111110 +01011111111111110100111111111111111111010010111111011111111111111011011111111111 +11111111111111111111111111111111 +11111111111111111111111111111101001011011111111111111111111111111111111111111110 +11011111111011110110111111110111111111011010110111111111111111111110111111111111 +11111111111111111110111111111111 +11111111111111111111111111111111001111011111111111111111111111111111100111111111 +10011111111111110111111111110111111111111011110111111111111111111011011111111111 +11111111111111111111111111111111 +11111111111111000111111111111101111111111111110111111111101111100111111111111111 +11111100111111110111101110111111111111011111111011010001111111111101111101110111 +11111110111011111111111111111111 +11111111111110110111111111111111000110011101111011111111101101110111111111111111 +11011100110111111100101111110111101111110011111110101100111111110011011011111111 +11111110110101111111111111111111 +11111111111111110111111111111111001011011111111101011111101001101111111111111111 +11111010110111111100110101010111111111111111111011011111111111111011011111111111 +11111110010111111111111111111111 +11111111111111111111111111111111001111001110111011111111110101111111111111111101 +10001110001111111011111110110111110111101111111101101111011111111110011110111111 +11111111100111111111111111111111 +11111111111111111111111111111110111111101111010111111111111111111111000101111111 +11101111110111111000101111010111111111100001111011111111111111111111111100111010 +01111111111011101001111111111111 +11111111111111111111111111111111111111111111110111111111111111111111101101111111 +11110111101111111000100111100111111111100011111111111111111111111111111010111111 +01111111111101111101111111111111 +11111111111111111111111111111111111011101101101111111111111111111110111101111111 +11111111111111011100111101110111111111110001110011011111111111111111111111010111 +01111111111111110111110111111111 +11111111111111111111111111111111111111010111111111111111111111111111101011111111 +11111111111011111111111111110111111111110011110101111111111111111111111111111011 +11111111111111111010111111111111 +11111111111111111110011111111111111011111001111111111111111110110111111111111111 +10101101111111111100111110110111111111110011111011011111111111111111111101110111 +11111110001111111111111111111111 +11111111111111111110011111111111101000011101111111111111111101000111111111111111 +11011111111111111100111111101111111111110110111111111111111111110011011001100111 +11111110110011111111111111111111 +11111111111111111111111111111101111011011011111111111111101010110111111111111111 +11100101111111110100111110110111111111010111111111111111111111110111011111111111 +11111110110111011111111111111111 +11111111111111111111111111111111111111011111111111111111111100111111111111111110 +11011011111111111111111111011111111111110011011100111111111111111100001110111111 +11111111110111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111101111111111111111111111111 +11111111111111111111111111111111011111110111111111111111111111111101110111101111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111110111110011111111101111111111111111111111111101111110111111101111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111110111111111111111111111111111 +11111111111111110111111111011111111111111111111111111111111111111111111111111111 +11111111111101011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111011111111111111111111111111111111111111111110111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111011111111111110111111111111 +11111111111111111011111111101111111111001111111100011111111111111111111011111111 +11111111111110111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111110101111111111111111111111111111111111111111101011111111111101111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111101111110111111111111111111111111111 +11111111111111110101111111010110111111011110111101111011111111111111110101101111 +11111111111101111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111010111111101111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111110111111111111111111111111111111111 +01111111111111111111100111111110001111111110001111111100111111111111111111100111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111101111111100111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111101111111111111111111111111111111110 +11111111111111111111111111111111111111111111111111111011111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111110111111111111111111111111111110111111111111111111111111111 +11111111111111111111111111111111111111111111111111011111111111111111111001111111 +11111111111111111111111111111111 +11111111111111111111110111111111111111111111111011110111111111111111111111111111 +11111111111111111111111111111111111111111111111110111111111111111111111111111011 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111011111111111011 +11111111111111111111111111111111 +11111111111111111111111110111111111111111111111011110011111111110101111011001111 +11111101011101110011111111110101100111001111111111010110101100111111111101001111 +11001111111111010011111111111111 +11111111001111111111011110111100111111111101011101110011111111110100111111111111 +11111111111011110011111111110101100111001111111111010110011100111111111101011010 +11001111111111010111101111111111 +11111111111111111111111111111111111111111111111111110011111111110100111111111111 +11111111111111110011111111110100100111111111111111111111111100111111111101011001 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111110011111111110111101111111111 +11111111111111110011111111110100111111111111111111111111111100111111111101001011 +11111111111111111111111111111111 +* +C8A2C* +N User Electronic Signature Data* +U00000000000000000000000000000000* +203C diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.log b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.log new file mode 100644 index 0000000..d0353b8 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.log @@ -0,0 +1,4 @@ +---- MParTrce Tool Log File ---- + +==== Par Standard Out ==== +==== End of Par Standard Out ==== diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.lpf b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.lpf new file mode 100644 index 0000000..2743d95 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.lpf @@ -0,0 +1,4 @@ +#BLOCK ASYNCPATHS; +#BLOCK RESETPATHS; + +#FREQUENCY 200.000000 MHz; diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.lsedata b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.lsedata new file mode 100644 index 0000000..89e99a4 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.lsedata @@ -0,0 +1,6331 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mrp b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mrp new file mode 100644 index 0000000..348c341 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mrp @@ -0,0 +1,336 @@ + + Lattice Mapping Report File for Design Module 'RAM2GS' + + +Design Information +------------------ + +Command line: map -a MachXO -p LCMXO256C -t TQFP100 -s 3 -oc Commercial + RAM2GS_LCMXO256C_impl1.ngd -o RAM2GS_LCMXO256C_impl1_map.ncd -pr + RAM2GS_LCMXO256C_impl1.prf -mp RAM2GS_LCMXO256C_impl1.mrp -lpf D:/OneDrive/ + Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.lpf + -lpf + D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.lpf -c + 0 -gui -msgset + D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml +Target Vendor: LATTICE +Target Device: LCMXO256CTQFP100 +Target Performance: 3 +Mapper: mj5g00, version: Diamond (64-bit) 3.12.1.454 +Mapped on: 08/15/23 05:03:20 + +Design Summary +-------------- + + Number of PFU registers: 102 out of 256 (40%) + Number of SLICEs: 71 out of 128 (55%) + SLICEs as Logic/ROM: 71 out of 128 (55%) + SLICEs as RAM: 0 out of 64 (0%) + SLICEs as Carry: 9 out of 128 (7%) + Number of LUT4s: 142 out of 256 (55%) + Number used as logic LUTs: 124 + Number used as distributed RAM: 0 + Number used as ripple logic: 18 + Number used as shift registers: 0 + Number of external PIOs: 67 out of 78 (86%) + Number of GSRs: 0 out of 1 (0%) + JTAG used : No + Readback used : No + Oscillator used : No + Startup used : No + Number of TSALL: 0 out of 1 (0%) + Notes:- + 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of + distributed RAMs) + 2*(Number of ripple logic) + 2. Number of logic LUT4s does not include count of distributed RAM and + ripple logic. + Number of clocks: 4 + Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK ) + Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 ) + Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS ) + Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) + Number of Clock Enables: 13 + Net PHI2_N_120_enable_4: 1 loads, 1 LSLICEs + Net RCLK_c_enable_4: 3 loads, 3 LSLICEs + Net RCLK_c_enable_23: 8 loads, 8 LSLICEs + Net RCLK_c_enable_12: 1 loads, 1 LSLICEs + Net RCLK_c_enable_3: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_5: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_6: 2 loads, 2 LSLICEs + Net RCLK_c_enable_24: 2 loads, 2 LSLICEs + Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs + Net Ready_N_292: 1 loads, 1 LSLICEs + + Page 1 + + + + +Design: RAM2GS Date: 08/15/23 05:03:20 + +Design Summary (cont) +--------------------- + Net RCLK_c_enable_11: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs + Net RCLK_c_enable_25: 1 loads, 1 LSLICEs + Number of LSRs: 9 + Net RASr2: 1 loads, 1 LSLICEs + Net Ready: 7 loads, 7 LSLICEs + Net C1Submitted_N_237: 2 loads, 2 LSLICEs + Net n2469: 1 loads, 1 LSLICEs + Net nRowColSel_N_35: 1 loads, 1 LSLICEs + Net n1846: 2 loads, 2 LSLICEs + Net LEDEN_N_82: 1 loads, 1 LSLICEs + Net nRowColSel_N_34: 1 loads, 1 LSLICEs + Net nRWE_N_177: 1 loads, 1 LSLICEs + Number of nets driven by tri-state buffers: 0 + Top 10 highest fanout non-clock nets: + Net Ready: 23 loads + Net InitReady: 17 loads + Net RASr2: 14 loads + Net nRowColSel: 13 loads + Net MAin_c_0: 12 loads + Net nRowColSel_N_35: 12 loads + Net Din_c_3: 11 loads + Net Din_c_6: 11 loads + Net MAin_c_1: 11 loads + Net Din_c_4: 10 loads + + + + + Number of warnings: 0 + Number of errors: 0 + + +Design Errors/Warnings +---------------------- + + No errors or warnings present. + +IO (PIO) Attributes +------------------- + ++---------------------+-----------+-----------+------------+------------+ +| IO Name | Direction | Levelmode | IO | FIXEDDELAY | +| | | IO_TYPE | Register | | ++---------------------+-----------+-----------+------------+------------+ +| RD[7] | BIDIR | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[6] | BIDIR | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[5] | BIDIR | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[4] | BIDIR | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[3] | BIDIR | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[2] | BIDIR | LVCMOS33 | | | + + Page 2 + + + + +Design: RAM2GS Date: 08/15/23 05:03:20 + +IO (PIO) Attributes (cont) +-------------------------- ++---------------------+-----------+-----------+------------+------------+ +| RD[1] | BIDIR | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[0] | BIDIR | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[7] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[6] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[5] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[4] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[3] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[2] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[1] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[0] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| LED | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RBA[1] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RBA[0] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[11] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[10] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[9] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[8] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[7] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[6] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[5] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[4] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[3] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[2] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[1] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[0] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nRCS | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RCKE | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nRWE | OUTPUT | LVCMOS33 | | | + + Page 3 + + + + +Design: RAM2GS Date: 08/15/23 05:03:20 + +IO (PIO) Attributes (cont) +-------------------------- ++---------------------+-----------+-----------+------------+------------+ +| nRRAS | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nRCAS | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RDQMH | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RDQML | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nUFMCS | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| UFMCLK | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| UFMSDI | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| PHI2 | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[9] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[8] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[7] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[6] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[5] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[4] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[3] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[2] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[1] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[0] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| CROW[1] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| CROW[0] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[7] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[6] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[5] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[4] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[3] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[2] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[1] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[0] | INPUT | LVCMOS33 | | | + + Page 4 + + + + +Design: RAM2GS Date: 08/15/23 05:03:20 + +IO (PIO) Attributes (cont) +-------------------------- ++---------------------+-----------+-----------+------------+------------+ +| nCCAS | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nCRAS | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nFWE | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RCLK | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| UFMSDO | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ + +Removed logic +------------- + +Block i2 undriven or does not drive anything - clipped. +Block GSR_INST undriven or does not drive anything - clipped. +Signal nCRAS_N_9 was merged into signal nCRAS_c +Signal nCCAS_N_3 was merged into signal nCCAS_c +Signal PHI2_N_120 was merged into signal PHI2_c +Signal RASr2_N_63 was merged into signal RASr2 +Signal n1426 was merged into signal nRowColSel_N_35 +Signal nRWE_N_176 was merged into signal nRWE_N_177 +Signal n1425 was merged into signal nRowColSel_N_34 +Signal nFWE_N_5 was merged into signal nFWE_c +Signal n2477 was merged into signal Ready +Signal GND_net undriven or does not drive anything - clipped. +Signal VCC_net undriven or does not drive anything - clipped. +Signal FS_610_add_4_18/CO1 undriven or does not drive anything - clipped. +Signal FS_610_add_4_18/CO0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_10/CO0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_4/CO0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_12/CO0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_2/CO0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_14/CO0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_6/CO0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_16/CO0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_8/CO0 undriven or does not drive anything - clipped. +Block i2135 was optimized away. +Block i2134 was optimized away. +Block i2136 was optimized away. +Block RASr2_I_0_1_lut was optimized away. +Block i1137_1_lut was optimized away. +Block nRWE_I_50_1_lut was optimized away. +Block i1136_1_lut was optimized away. +Block i1_1_lut was optimized away. +Block i637_1_lut_rep_34 was optimized away. +Block i1 was optimized away. + +Run Time and Memory Usage +------------------------- + + Total CPU Time: 0 secs + Total REAL Time: 0 secs + Peak Memory Usage: 29 MB + + + Page 5 + + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. + Copyright (c) 1995 AT&T Corp. All rights reserved. + Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. + Copyright (c) 2001 Agere Systems All rights reserved. + Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights + reserved. diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mt b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mt new file mode 100644 index 0000000..2d70ad1 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mt @@ -0,0 +1,9 @@ +-v +1 + + +-gt + + +-mapchkpnt 0 +-sethld diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.n2e b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.n2e new file mode 100644 index 0000000..737af10 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.n2e @@ -0,0 +1,596 @@ + +comp 0: SLICE_0 (FSLICE) + +comp 1: SLICE_1 (FSLICE) + +comp 2: SLICE_2 (FSLICE) + +comp 3: SLICE_3 (FSLICE) + +comp 4: SLICE_4 (FSLICE) + +comp 5: SLICE_5 (FSLICE) + +comp 6: SLICE_6 (FSLICE) + +comp 7: SLICE_7 (FSLICE) + +comp 8: SLICE_8 (FSLICE) + +comp 9: SLICE_9 (FSLICE) +n1413 = (~n2263*(~ADSubmitted*n2242+ADSubmitted*(~n2459+n2242))+n2263*(ADSubmitted*~n2459)) +ADSubmitted.D = n1413 +ADSubmitted.CLK = ~PHI2_c +ADSubmitted.SP = VCC +ADSubmitted.LSR = C1Submitted_N_237 +n2263 = (~MAin_c_1+(~MAin_c_0+n1326)) + +comp 10: SLICE_14 (FSLICE) +n6_adj_3 = (~MAin_c_1*C1Submitted+MAin_c_1*(C1Submitted*(nFWE_c+n1326))) +C1Submitted.D = n6_adj_3 +C1Submitted.CLK = ~PHI2_c +C1Submitted.SP = VCC +C1Submitted.LSR = C1Submitted_N_237 +n2284 = (C1Submitted+Din_c_6) + +comp 11: SLICE_18 (FSLICE) +CmdEnable_N_248 = (n15*(~n1326*(n2463*MAin_c_1))) +CmdEnable.D = CmdEnable_N_248 +CmdEnable.CLK = ~PHI2_c +CmdEnable.SP = PHI2_N_120_enable_7 +CmdEnable.LSR = GND +n1326 = (~MAin_c_5+(~n2316+(~MAin_c_2+n26))) + +comp 12: SLICE_19 (FSLICE) +n2568\001/BUF1 = VCC +CmdSubmitted.D = n2568\001/BUF1 +CmdSubmitted.CLK = ~PHI2_c +CmdSubmitted.SP = PHI2_N_120_enable_5 +CmdSubmitted.LSR = GND +n2472 = (~PHI2r2*(CmdSubmitted*PHI2r3)) + +comp 13: SLICE_23 (FSLICE) +Cmdn8MEGEN_N_264 = (~n1314*(~Din_c_4*n8MEGEN+Din_c_4*~Din_c_0)+n1314*n8MEGEN) +Cmdn8MEGEN.D = Cmdn8MEGEN_N_264 +Cmdn8MEGEN.CLK = ~PHI2_c +Cmdn8MEGEN.SP = PHI2_N_120_enable_4 +Cmdn8MEGEN.LSR = GND +n1314 = ((Din_c_6+Din_c_7)+Din_c_5) + +comp 14: SLICE_25 (FSLICE) +n2568\000/BUF1 = VCC +InitReady.D = n2568\000/BUF1 +InitReady.CLK = RCLK_c +InitReady.SP = RCLK_c_enable_25 +InitReady.LSR = GND +RCLK_c_enable_23 = (nRowColSel_N_35*(RASr2*(InitReady*~Ready))) + +comp 15: SLICE_26 (FSLICE) +n2568 = VCC +LEDEN.D = n2568 +LEDEN.CLK = RCLK_c +LEDEN.SP = RCLK_c_enable_12 +LEDEN.LSR = GND +LED_N_84 = ((~LEDEN+CBR)+nCRAS_c) + +comp 16: SLICE_31 (FSLICE) +n2209 = ((n2208+Ready)+nRCAS_N_165) +RA_0.D = n2209 +RA_0.CLK = RCLK_c +RA_0.SP = VCC +RA_0.LSR = ~nRWE_N_177 +n56 = (~Ready+nRowColSel_N_34) + +comp 17: SLICE_32 (FSLICE) +RA11_N_184 = (~n8MEGEN*(XOR8MEG@Din_c_6)+n8MEGEN*XOR8MEG) +RA_c.D = RA11_N_184 +RA_c.CLK = PHI2_c +RA_c.SP = VCC +RA_c.LSR = ~Ready +n2478 = (Din_c_6+Din_c_7) + +comp 18: SLICE_34 (FSLICE) +RCKEEN_N_121 = (~Ready*InitReady+Ready*RCKEEN_N_122) +RCKEEN.D = RCKEEN_N_121 +RCKEEN.CLK = RCLK_c +RCKEEN.SP = RCLK_c_enable_4 +RCKEEN.LSR = GND +n2467 = ((InitReady*RASr2)+Ready) + +comp 19: SLICE_35 (FSLICE) +RCKE_N_132 = (~RASr3*(~RASr2*(RCKEEN*RASr)+RASr2*RCKEEN)+RASr3*(~RASr2+RCKEEN)) +RCKE_c.D = RCKE_N_132 +RCKE_c.CLK = RCLK_c +RCKE_c.SP = VCC +RCKE_c.LSR = GND +nRWE_N_182 = (~RCKE_c+RASr2) +CASr2.D = CASr +CASr2.CLK = RCLK_c +CASr2.SP = VCC +CASr2.LSR = GND + +comp 20: SLICE_36 (FSLICE) +n2568\002/BUF1 = VCC +Ready.D = n2568\002/BUF1 +Ready.CLK = RCLK_c +Ready.SP = Ready_N_292 +Ready.LSR = GND +n2469 = (~Ready+nRowColSel_N_35) + +comp 21: SLICE_43 (FSLICE) +UFMCLK_N_224 = (~InitReady*n1160+InitReady*CmdUFMCLK) +UFMCLK_c.D = UFMCLK_N_224 +UFMCLK_c.CLK = RCLK_c +UFMCLK_c.SP = RCLK_c_enable_24 +UFMCLK_c.LSR = n1846 +n1160 = (~FS_1*(~n2462*FS_4)+FS_1*(~n2462*FS_4+n2462*~n62)) + +comp 22: SLICE_44 (FSLICE) +UFMSDI_N_231 = (~CmdUFMSDI*(~InitReady*(~n2462*n2461))+CmdUFMSDI*((~n2462*n2461)+InitReady)) +UFMSDI_c.D = UFMSDI_N_231 +UFMSDI_c.CLK = RCLK_c +UFMSDI_c.SP = RCLK_c_enable_24 +UFMSDI_c.LSR = n1846 +n2462 = (~FS_11+((n2471+n2272)+n2470)) + +comp 23: SLICE_49 (FSLICE) +XOR8MEG_N_110 = (~n2324*(Din_c_2*(~Din_c_3*Din_c_0))) +XOR8MEG.D = XOR8MEG_N_110 +XOR8MEG.CLK = ~PHI2_c +XOR8MEG.SP = PHI2_N_120_enable_1 +XOR8MEG.LSR = GND +n2324 = (~Din_c_1*(Din_c_4+n1314)+Din_c_1*((Din_c_4+LEDEN)+n1314)) + +comp 24: SLICE_56 (FSLICE) +n8MEGEN_N_91 = (~n1325*(~InitReady*~UFMSDO_c+InitReady*Cmdn8MEGEN)+n1325*Cmdn8MEGEN) +n8MEGEN.D = n8MEGEN_N_91 +n8MEGEN.CLK = RCLK_c +n8MEGEN.SP = RCLK_c_enable_11 +n8MEGEN.LSR = GND +n1325 = (~FS_10+(~FS_11+n2464)) + +comp 25: SLICE_58 (FSLICE) +nRCAS_N_161 = (((~CBR*Ready)+(n2427*~Ready)+(n2427*~CBR)+~RASr2)*nRowColSel_N_35)+((nRowColSel_N_34+~n15_adj_1+~Ready)*~nRowColSel_N_35) +nRCAS_c.D = nRCAS_N_161 +nRCAS_c.CLK = RCLK_c +nRCAS_c.SP = RCLK_c_enable_4 +nRCAS_c.LSR = GND + +comp 26: SLICE_60 (FSLICE) +nRCS_N_136 = (~nRowColSel_N_35*(~n2467+n2481)+nRowColSel_N_35*(~n13+n2481)) +nRCS_c.D = nRCS_N_136 +nRCS_c.CLK = RCLK_c +nRCS_c.SP = RCLK_c_enable_4 +nRCS_c.LSR = GND +n13 = (~Ready*(InitReady*RASr2)+Ready*(RASr2+RCKE_c)) + +comp 27: SLICE_61 (FSLICE) +n2138 = (((nRCS_N_139*~Ready)+~n13)*nRowColSel_N_35)+((n56+nRRAS_c+n6+nRowColSel_N_32)*~nRowColSel_N_35) +nRRAS_c.D = n2138 +nRRAS_c.CLK = RCLK_c +nRRAS_c.SP = VCC +nRRAS_c.LSR = GND + +comp 28: SLICE_63 (FSLICE) +nRWE_N_171 = (~n2208*(~Ready*~n33+Ready*nRWE_N_178)+n2208*(~Ready+nRWE_N_178)) +nRWE_c.D = nRWE_N_171 +nRWE_c.CLK = RCLK_c +nRWE_c.SP = RCLK_c_enable_3 +nRWE_c.LSR = GND +n2208 = ((~InitReady+(~RASr2+~nRowColSel_N_35))+nRCS_N_139) + +comp 29: SLICE_64 (FSLICE) +n1410 = (~nRowColSel_N_32*(nRowColSel+n1502)+nRowColSel_N_32*(~nRowColSel_N_28+n1502)) +nRowColSel.D = n1410 +nRowColSel.CLK = RCLK_c +nRowColSel.SP = VCC +nRowColSel.LSR = n2469 +RA_1_9 = (~nRowColSel*RowA_9+nRowColSel*MAin_c_9) + +comp 30: SLICE_65 (FSLICE) +n1503 = (nRowColSel_N_32+nRowColSel_N_33) +nRowColSel_N_32.D = n1503 +nRowColSel_N_32.CLK = RCLK_c +nRowColSel_N_32.SP = VCC +nRowColSel_N_32.LSR = ~RASr2 +n2414 = (InitReady*(Ready_N_296*(~RASr2*nRowColSel_N_32))) + +comp 31: SLICE_66 (FSLICE) +n1093 = (RASr2*~nRowColSel_N_32) +nRowColSel_N_33.D = n1093 +nRowColSel_N_33.CLK = RCLK_c +nRowColSel_N_33.SP = VCC +nRowColSel_N_33.LSR = ~nRowColSel_N_34 +RCLK_c_enable_4 = (((nRowColSel_N_32+n2469)+nRowColSel_N_34)+nRowColSel_N_33) + +comp 32: SLICE_67 (FSLICE) +n11 = (~CASr2+nRowColSel_N_33) +nRowColSel_N_34.D = n1093 +nRowColSel_N_34.CLK = RCLK_c +nRowColSel_N_34.SP = VCC +nRowColSel_N_34.LSR = ~nRowColSel_N_35 +n1417 = (~n2472*nUFMCS_c+n2472*~CmdUFMCS) + +comp 33: SLICE_68 (FSLICE) +n2322 = (((FS_0+FS_1)+FS_6)+FS_3) +nRowColSel_N_35.D = ~RASr2 +nRowColSel_N_35.CLK = RCLK_c +nRowColSel_N_35.SP = VCC +nRowColSel_N_35.LSR = GND +n2471 = (FS_17+FS_12) +CASr3.D = CASr2 +CASr3.CLK = RCLK_c +CASr3.SP = VCC +CASr3.LSR = GND + +comp 34: SLICE_69 (FSLICE) +n2164 = (~InitReady*n62+InitReady*n1417) +nUFMCS_c.D = n2164 +nUFMCS_c.CLK = RCLK_c +nUFMCS_c.SP = VCC +nUFMCS_c.LSR = LEDEN_N_82 +n62 = (FS_14*(FS_12*(n12*FS_17))) + +comp 35: RCKEEN_I_0_445/SLICE_70 (FSLICE) +RCKEEN_N_122 = (((~FWEr*~CBR)+~RASr2)*nRowColSel_N_35)+(((FWEr*n11*~CBR)+(nRowColSel_N_34*~CBR))*~nRowColSel_N_35) + +comp 36: i26/SLICE_71 (FSLICE) +n13_adj_2 = ((~n2284*n2476*MAin_c_1*MAin_c_0)*Din_c_2)+((~ADSubmitted*~MAin_c_0*n2475*~Din_c_5)*~Din_c_2) + +comp 37: i2099/SLICE_72 (FSLICE) +n2481 = (((nRowColSel_N_35*~Ready*nRCS_N_139)+(nRowColSel_N_34*~Ready*nRCS_N_139)+(~nRowColSel_N_35*~Ready)+(nRowColSel_N_34*~nRowColSel_N_35))*n15_adj_1)+(((~Ready*nRCS_N_139)+~nRowColSel_N_35)*~n15_adj_1) + +comp 38: i26_adj_28/SLICE_73 (FSLICE) +n15 = ((MAin_c_0*Din_c_2*Din_c_3*~Din_c_6)*Din_c_5)+((~MAin_c_0*~Din_c_2*~Din_c_3*Din_c_6)*~Din_c_5) + +comp 39: SLICE_74 (FSLICE) +n1 = (~CASr3*(CASr2*(FWEr*~CBR))) +RASr2.D = RASr +RASr2.CLK = RCLK_c +RASr2.SP = VCC +RASr2.LSR = GND +n15_adj_1 = (~n1*(nRowColSel_N_33*(~CBR*~FWEr))+n1*(~nRowColSel_N_33+(~CBR*~FWEr))) +RASr3.D = RASr2 +RASr3.CLK = RCLK_c +RASr3.SP = VCC +RASr3.LSR = GND + +comp 40: SLICE_75 (FSLICE) +n2214 = (FS_11*(~n2272*(~n2328*FS_10))) +RCLK_c_enable_12 = (~InitReady*(FS_11*n2214)) + +comp 41: SLICE_76 (FSLICE) +PHI2_N_120_enable_4 = (n2458*(~Din_c_4*~Din_c_5+Din_c_4*(~Din_c_5+Din_c_3))) +n732.D = n733 +n732.CLK = RCLK_c +n732.SP = RCLK_c_enable_23 +n732.LSR = GND +n2458 = (MAin_c_0*(n10*(~n1326*~nFWE_c))) +nRWE_N_177.D = n732 +nRWE_N_177.CLK = RCLK_c +nRWE_N_177.SP = RCLK_c_enable_23 +nRWE_N_177.LSR = GND + +comp 42: SLICE_77 (FSLICE) +n2290 = ((FS_2+FS_5)+FS_9) +n728.D = n729 +n728.CLK = RCLK_c +n728.SP = RCLK_c_enable_23 +n728.LSR = GND +n8 = (~FS_7*(~n2322*(FS_4*~n2290))) +n727.D = n728 +n727.CLK = RCLK_c +n727.SP = RCLK_c_enable_23 +n727.LSR = GND + +comp 43: SLICE_78 (FSLICE) +n1846 = (~InitReady*(~n2464*~FS_11)) +RowA_6.D = MAin_c_6 +RowA_6.CLK = ~nCRAS_c +RowA_6.SP = VCC +RowA_6.LSR = ~Ready +n2464 = (((FS_16+FS_14)+n2272)+n2471) +RowA_7.D = MAin_c_7 +RowA_7.CLK = ~nCRAS_c +RowA_7.SP = VCC +RowA_7.LSR = ~Ready + +comp 44: SLICE_79 (FSLICE) +C1Submitted_N_237 = (n2468*(~n1280*(n2463*~Din_c_2))) +CASr.D = ~nCCAS_c +CASr.CLK = RCLK_c +CASr.SP = VCC +CASr.LSR = GND +n2468 = (~Din_c_5*(~Din_c_3*Din_c_6)) +PHI2r2.D = PHI2r +PHI2r2.CLK = RCLK_c +PHI2r2.SP = VCC +PHI2r2.LSR = GND + +comp 45: SLICE_80 (FSLICE) +RCLK_c_enable_3 = (((~Ready+nRowColSel_N_32)+n1502)+nRowColSel_N_35) +n726.D = n727 +n726.CLK = RCLK_c +n726.SP = RCLK_c_enable_23 +n726.LSR = GND +n1502 = (nRowColSel_N_34+nRowColSel_N_33) +Ready_N_296.D = n726 +Ready_N_296.CLK = RCLK_c +Ready_N_296.SP = RCLK_c_enable_23 +Ready_N_296.LSR = GND + +comp 46: SLICE_81 (FSLICE) +n26 = (~Bank_5+(~n2278+(~n2314+Bank_2))) +CmdUFMCLK.D = Din_c_1 +CmdUFMCLK.CLK = ~PHI2_c +CmdUFMCLK.SP = PHI2_N_120_enable_6 +CmdUFMCLK.LSR = GND +n2278 = (Bank_3*Bank_6) +CmdUFMCS.D = Din_c_2 +CmdUFMCS.CLK = ~PHI2_c +CmdUFMCS.SP = PHI2_N_120_enable_6 +CmdUFMCS.LSR = GND + +comp 47: SLICE_82 (FSLICE) +n2460 = (nFWE_c+n1326) +n730.D = nRWE_N_177 +n730.CLK = RCLK_c +n730.SP = RCLK_c_enable_23 +n730.LSR = GND +PHI2_N_120_enable_7 = (~MAin_c_1*(~n14*(~n2460*MAin_c_0))+MAin_c_1*(~n14*~n2460)) +n729.D = n730 +n729.CLK = RCLK_c +n729.SP = RCLK_c_enable_23 +n729.LSR = GND + +comp 48: SLICE_83 (FSLICE) +n10 = (~MAin_c_1*(CmdEnable*(~n2478*Din_c_4))) +RASr.D = ~nCRAS_c +RASr.CLK = RCLK_c +RASr.SP = VCC +RASr.LSR = GND +PHI2_N_120_enable_6 = (n2476*(~n2460*(n10*MAin_c_0))) + +comp 49: SLICE_84 (FSLICE) +n2262 = ((~MAin_c_0+n1326)+MAin_c_1) +n738.D = nRCAS_N_165 +n738.CLK = RCLK_c +n738.SP = RCLK_c_enable_23 +n738.LSR = GND +PHI2_N_120_enable_1 = (~n1314*(~n2262*(CmdEnable*~n2473))) +n737.D = n738 +n737.CLK = RCLK_c +n737.SP = RCLK_c_enable_23 +n737.LSR = GND + +comp 50: SLICE_85 (FSLICE) +n2473 = (Din_c_4+nFWE_c) +RBA_c_0.D = CROW_c_0 +RBA_c_0.CLK = ~nCRAS_c +RBA_c_0.SP = VCC +RBA_c_0.LSR = ~Ready +n2242 = (n2474*(Din_c_5*(n2253*~n2473))) +RBA_c_1.D = CROW_c_1 +RBA_c_1.CLK = ~nCRAS_c +RBA_c_1.SP = VCC +RBA_c_1.LSR = ~Ready + +comp 51: SLICE_86 (FSLICE) +n2463 = (n2253*(~nFWE_c*~Din_c_4)) +n734.D = n735 +n734.CLK = RCLK_c +n734.SP = RCLK_c_enable_23 +n734.LSR = GND +n2253 = (~Din_c_1*(Din_c_0*Din_c_7)) +n733.D = n734 +n733.CLK = RCLK_c +n733.SP = RCLK_c_enable_23 +n733.LSR = GND + +comp 52: SLICE_87 (FSLICE) +RCLK_c_enable_11 = (~n8*(InitReady*n2472)+n8*(~InitReady*n7+InitReady*n2472)) +nRCS_N_139.D = Ready_N_296 +nRCS_N_139.CLK = RCLK_c +nRCS_N_139.SP = RCLK_c_enable_23 +nRCS_N_139.LSR = GND +n7 = (n2214*~FS_8) +nRCAS_N_165.D = nRCS_N_139 +nRCAS_N_165.CLK = RCLK_c +nRCAS_N_165.SP = RCLK_c_enable_23 +nRCAS_N_165.LSR = GND + +comp 53: SLICE_88 (FSLICE) +n2451 = (~FS_8*(~FS_5*(~FS_9*FS_7)+FS_5*(FS_9@FS_7))) +Bank_0.D = Din_c_0 +Bank_0.CLK = PHI2_c +Bank_0.SP = VCC +Bank_0.LSR = GND +n2461 = (~FS_10*(FS_6*n2451)) +Bank_1.D = Din_c_1 +Bank_1.CLK = PHI2_c +Bank_1.SP = VCC +Bank_1.LSR = GND + +comp 54: SLICE_89 (FSLICE) +n1280 = ((~MAin_c_1+n1326)+MAin_c_0) +WRD_0.D = Din_c_0 +WRD_0.CLK = ~nCCAS_c +WRD_0.SP = VCC +WRD_0.LSR = GND +n2459 = (MAin_c_1*(~n1326*~nFWE_c)) +WRD_1.D = Din_c_1 +WRD_1.CLK = ~nCCAS_c +WRD_1.SP = VCC +WRD_1.LSR = GND + +comp 55: SLICE_90 (FSLICE) +n2470 = (FS_16+FS_14) +RowA_8.D = MAin_c_8 +RowA_8.CLK = ~nCRAS_c +RowA_8.SP = VCC +RowA_8.LSR = ~Ready +n2328 = (((FS_17+FS_12)+FS_14)+FS_16) +RowA_9.D = MAin_c_9 +RowA_9.CLK = ~nCRAS_c +RowA_9.SP = VCC +RowA_9.LSR = ~Ready + +comp 56: SLICE_91 (FSLICE) +PHI2_N_120_enable_5 = (n2458*(~Din_c_5*Din_c_4+Din_c_5*(Din_c_4*Din_c_3))) +PHI2r3.D = PHI2r2 +PHI2r3.CLK = RCLK_c +PHI2r3.SP = VCC +PHI2r3.LSR = GND +n2476 = (Din_c_5*Din_c_3) +PHI2r.D = PHI2_c +PHI2r.CLK = RCLK_c +PHI2r.SP = VCC +PHI2r.LSR = GND + +comp 57: SLICE_92 (FSLICE) +n2474 = (Din_c_3*(Din_c_2*~Din_c_6)) +WRD_6.D = Din_c_6 +WRD_6.CLK = ~nCCAS_c +WRD_6.SP = VCC +WRD_6.LSR = GND +n2475 = (~Din_c_3*Din_c_6) +WRD_7.D = Din_c_7 +WRD_7.CLK = ~nCCAS_c +WRD_7.SP = VCC +WRD_7.LSR = GND + +comp 58: SLICE_93 (FSLICE) +RDQMH_c = (~nRowColSel+MAin_c_9) +CmdUFMSDI.D = Din_c_0 +CmdUFMSDI.CLK = ~PHI2_c +CmdUFMSDI.SP = PHI2_N_120_enable_6 +CmdUFMSDI.LSR = GND +RDQML_c = (~nRowColSel+~MAin_c_9) + +comp 59: SLICE_94 (FSLICE) +n12 = (FS_11*(FS_16*(FS_13*FS_15))) +n2272 = (FS_13+FS_15) + +comp 60: SLICE_95 (FSLICE) +LEDEN_N_82 = (~InitReady*(~FS_10*(~n2464*~FS_11))) +RowA_4.D = MAin_c_4 +RowA_4.CLK = ~nCRAS_c +RowA_4.SP = VCC +RowA_4.LSR = ~Ready +RCLK_c_enable_25 = (FS_10*n62) +RowA_5.D = MAin_c_5 +RowA_5.CLK = ~nCRAS_c +RowA_5.SP = VCC +RowA_5.LSR = ~Ready + +comp 61: SLICE_96 (FSLICE) +n2316 = (Bank_1*(Bank_4*(MAin_c_3*MAin_c_7))) +RowA_2.D = MAin_c_2 +RowA_2.CLK = ~nCRAS_c +RowA_2.SP = VCC +RowA_2.LSR = ~Ready +RA_1_3 = (~nRowColSel*RowA_3+nRowColSel*MAin_c_3) +RowA_3.D = MAin_c_3 +RowA_3.CLK = ~nCRAS_c +RowA_3.SP = VCC +RowA_3.LSR = ~Ready + +comp 62: SLICE_97 (FSLICE) +n2314 = (Bank_0*(Bank_7*(MAin_c_4*MAin_c_6))) +RowA_0.D = MAin_c_0 +RowA_0.CLK = ~nCRAS_c +RowA_0.SP = VCC +RowA_0.LSR = ~Ready +RA_1_4 = (~nRowColSel*RowA_4+nRowColSel*MAin_c_4) +RowA_1.D = MAin_c_1 +RowA_1.CLK = ~nCRAS_c +RowA_1.SP = VCC +RowA_1.LSR = ~Ready + +comp 63: SLICE_98 (FSLICE) +RA_1_8 = (~nRowColSel*RowA_8+nRowColSel*MAin_c_8) +CBR.D = ~nCCAS_c +CBR.CLK = ~nCRAS_c +CBR.SP = VCC +CBR.LSR = GND +RA_1_0 = (~nRowColSel*RowA_0+nRowColSel*MAin_c_0) +FWEr.D = ~nFWE_c +FWEr.CLK = ~nCRAS_c +FWEr.SP = VCC +FWEr.LSR = GND + +comp 64: SLICE_99 (FSLICE) +RA_1_7 = (~nRowColSel*RowA_7+nRowColSel*MAin_c_7) +Bank_6.D = Din_c_6 +Bank_6.CLK = PHI2_c +Bank_6.SP = VCC +Bank_6.LSR = GND +RA_1_1 = (~nRowColSel*RowA_1+nRowColSel*MAin_c_1) +Bank_7.D = Din_c_7 +Bank_7.CLK = PHI2_c +Bank_7.SP = VCC +Bank_7.LSR = GND + +comp 65: SLICE_100 (FSLICE) +RCLK_c_enable_24 = (~InitReady+(~PHI2r2*(CmdSubmitted*PHI2r3))) +n736.D = n737 +n736.CLK = RCLK_c +n736.SP = RCLK_c_enable_23 +n736.LSR = GND +n6 = (~Ready*((~InitReady+~RASr2)+nRowColSel_N_33)+Ready*nRowColSel_N_33) +n735.D = n736 +n735.CLK = RCLK_c +n735.SP = RCLK_c_enable_23 +n735.LSR = GND + +comp 66: SLICE_101 (FSLICE) +RA_1_6 = (~nRowColSel*RowA_6+nRowColSel*MAin_c_6) +Bank_4.D = Din_c_4 +Bank_4.CLK = PHI2_c +Bank_4.SP = VCC +Bank_4.LSR = GND +RA_1_2 = (~nRowColSel*RowA_2+nRowColSel*MAin_c_2) +Bank_5.D = Din_c_5 +Bank_5.CLK = PHI2_c +Bank_5.SP = VCC +Bank_5.LSR = GND + +comp 67: SLICE_102 (FSLICE) +n2427 = ((~InitReady+nRCS_N_139)+nRCAS_N_165) +Bank_2.D = Din_c_2 +Bank_2.CLK = PHI2_c +Bank_2.SP = VCC +Bank_2.LSR = GND +n33 = (nRCAS_N_165+nRWE_N_177) +Bank_3.D = Din_c_3 +Bank_3.CLK = PHI2_c +Bank_3.SP = VCC +Bank_3.LSR = GND + +comp 68: SLICE_103 (FSLICE) +nRowColSel_N_28 = ((~FWEr+CASr3)+CBR) +WRD_2.D = Din_c_2 +WRD_2.CLK = ~nCCAS_c +WRD_2.SP = VCC +WRD_2.LSR = GND +RA_1_5 = (~nRowColSel*RowA_5+nRowColSel*MAin_c_5) +WRD_3.D = Din_c_3 +WRD_3.CLK = ~nCCAS_c +WRD_3.SP = VCC +WRD_3.LSR = GND + +comp 69: SLICE_104 (FSLICE) +nRWE_N_178 = (~nRowColSel_N_35*(~n1+n1502)+nRowColSel_N_35*nRWE_N_182) +Ready_N_292 = (n2414+Ready) + +comp 70: SLICE_105 (FSLICE) +n14 = (n13_adj_2*(~Din_c_4*n2253)) +WRD_4.D = Din_c_4 +WRD_4.CLK = ~nCCAS_c +WRD_4.SP = VCC +WRD_4.LSR = GND +n984 = (nCCAS_c+nFWE_c) +WRD_5.D = Din_c_5 +WRD_5.CLK = ~nCCAS_c +WRD_5.SP = VCC +WRD_5.LSR = GND diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.ncd b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.ncd new file mode 100644 index 0000000000000000000000000000000000000000..113a28f9c6cae770047794648cfe230b6cdbc83c GIT binary patch literal 162296 zcmeEv3w&KwmHsVl(>85VpoKQ6K%kHG1?1kmTMOjTmPpb^((48tHg=m;XBLm5XHA1&jcgP@M!i{}4*YwdOR-shg1h9N1;-<;oX zC+n`W_G|5Luf6u;oHJ|IGtZ1GeEFi>_}uv3ww}W3zTB1{9ev`s+_*E}*mzo9U9P*M z=ft&z#-@(khV`q~<-w`X;X06ihJ8JSb|II9-W?q>!#eK`NZCL_sQ?u0%m9oUTMcDx9uFK`NY9dO<3z4dknqsq=c_rW2@_ zf~8xyUJ5ofrJQ;xSb3T&1xq8RUJ900Z@sjHD$*A>6ATT~5^3!=NK2%(+aN8G)^3AT zIIZ0V$t|tj2B~mbISo?bv~n7x!f7-#NQH~aD;3uA`U+>_yiqEgu0*3$I9-WGsc^ay zjhQXn7__i2LeQx^Gw4&E8FVSnbUkWf()-r5^{jL@q^E7$z{1vLb&JrIbGd0^O!T(Y za7yX>Qr9URy=zZcn9qtYwI1TW)PHg(vTx3cE{Z69TUw>`ZP8fi+oHSDx3xQzESl&u zj;&Tr6sPqrsW&xRaqK|tYQ3g(o^`?bnR-z>HpG2V>k#)vuS47y#SU>_G&{t7H87>i zFS<>|545MnFR4AXi<5iX+cH6?2D0>RMNKavXF*m?=H!yM6*VPqD{4yKR@6kdgL-ST zl&rTJ*pfw4OI!N3V6yaW?TS&+0!XS6E**PlrK(vj9b1$-skbu|?P{k>-W8QbcLR+o zkV|S*EqD|;sIyw~l6OU)CGUzlOWu{1j_wA9*4`BtI=HQ!tK@C%TP1Icx>6Q>-|oJZ z{T=K2`g_{e^{?vcUP?W6vj!+$-m$i)XJv0kS6jEpOF+xQB&yf?dlk2&;_EQvzJe8_UN+iw*qfT% zPgg=`2-A8IU3*Jf4Lb4#0!1k(T$2>iJyvHBQP-YrTI{x|i zMfXLe{(c&3I_dED(@@jthrgdjnvQ|~ei~>xCGq#u3f583-%smTrzz#Vo!OmD$HC-w zQSAk!$!%BpM7d(B0_CQaqeEd5J*^uZ3zOSv)#&slxt-RG&U2F6X~pP-C%K*0OQV#1 z!a#3__P(U6G>Uzl(A&{{T-;Y01*y1kT&i<5ibX|I>0a09x_Ga3)I@QTN1(X0W|~|V z?=|C)6t79}II*{Leb2FR`I@AU%N-ppeH`iKWdj>m^`vXtB>kg|chdE35)JWIUuRb; zD=EL;S}V7bnu(Hvnz=?z?u)L1`>s`!`=YYozH3(A-*D2pmCHmi`*f{Iauu#9#kj1u zawB2SE+H-YD^5g|SIid06|+TY#cWYnFo@Ws7eRj48GJpgD=(3;7k28_@aOezGxtWFDl63XX_xljdY+a(t(bW#cUlTi&UdC z!{Vao*qFgDp#mKWGvrICKu5j|c~L>aPjHY8NFCo2=>!NmvCH6>(1Ke=E7FdRUm59? z(1MOv8S>f{+P$R_TM4N+_WzDrVAnku6NPkts~L zkrkNQ*R@(^h3huPYLfvxBN^}^ZL9C;)dFY+4qW+X6v!`gL&xR}W>&F$ir4?FcIoRw1lLI2NG`;Z+F7A#@}3Agn=Hi?9x1 zJwh)+AHqh2;}K3kI1%9_giQ#qK{y%VwFvzPuS3|3a0 z0^8yYgfkHa5Y9q48{r&;a}mx*coPB}@vjgrLilThixDnCcq_togi8_LhHx3e+Yv5D zxB}rygm)lZh44;N!u1G$i*N(N z-yz(H@L`0HAl!s-Gr~s^K8Emdgij!R65$qvPa)ij@M(nG5I%!&JHlrXK8Nu42%ksz z0>T#&zJzcG!j}=gg78&@I}!c?;Vy)KM7SH_pAhar_!`2!2wz9|2Esoh+=uW@gl{4I z3&OV%?nih4;X4QqB77I&A%yQCJdE&tgdZUME5aiPI}jd4_&0T=ObKz@Fs){bFjm!`udylb^ZO@pb_ov{2%b4rGQ`QkYTqQz+iMFSFo5(GB@kKjhCXr+n( zd2x7aD=VGcGtkDn#YBe1C!5{`#VO)7v`xE;!}PZRelA74WT#vzxW8P}ful z<7T9eY+GAeR4B@JdPhD?I@UR4Ib~bk-Hj5g=s0uB%7M+NoUs)p zjgdZO0Eb&zUQ<^m2{D%VT(F6`3GEwKkqaA%3zjV*xOAJ;7 zCOxSLOgt`fVdN9;5!>-Yu9;A{G`~}OF-$7D2DY8wyLI!HxAfPy#;`9tGhc+9sQ^bq zYX+pIVC5K!XvoJZ^!k++kCEmfDnMn4w@b0{2fKDK#|=2Mgljwh@R|;89@=hf$SA_W z*iq?k?#FFJ1cJ9UIS{jH>tpCJ`FwwUOUwnT3yoQ|J8)aG1H0lREBkV;`%wi7$L&&J z{Mny;Efh3Y+yavgB#f|~e|SxnSoN)O0jFTK?_40ZB{p6OQpDCtd}0Cvb%F^D+_=c? zM6mABu^m6;nzgOD*$jqs1*bgT+%6LMGev>YP!|KGd|OLPQ$~Z7Z)?qG)wo<269Jak zJRC4kXh6%Jf-yA!Ei>QFKfDewWl1}fOdacyNIgbdY<%+Zus~cFS~6N^>WOQ6*~!tY zvEkj{_x*fBM#QYXAFFMurO=R%lb(peXv0gL*=QROCaiAT0G}(@w;g}vnu5jYwmx*+ zIR11fNpL0xC#8n{fbn`);EZBV=6W|$j9X^>Hf<`&mF0n-mXznD?ZU<%lm`phh#hNw ze=dA$4`|F9s%9oe*q1u45lV#=>RV&u!k$yypQ^a?*x%~xK%u#R8w^SD7+5*bd)9>= zXPwcv^$fIaj0P%D$4;?YaUYznoq#AU&U|uT|Ej*8{%xt2MuRpsXN;DWam}g6?fk>b zl8U=}s%Y^|aR##Nm!%a~Q$XL8QH%ZA8yW)ZSx7a9t7SYOigCht(-K!6<2o#D(MU2G z=DApZ<+=rd&KoPe(ivB=?G18Ilte6^hhTl<-0i}~pYhuYf?@ehu?rAP?ELM*#vkcx z0xRKA@InL=eA9Me<4-x#(*ay`A#6&&1;M1>yj|G%Gub>HGPd&%FPNallBR76x{lcP zc*qkrwHhmX^0wv-^-VTBF}Lmf!;9mr_N-!sAF$0zM5~|A>Yn9Y+T8uyVib6O+%4%F zwq}ixDGMB@HZ{p5ZJPa!814H3rA>_vrNsb?YgWiI6_a2B+R{@#$Ba!F6`Q3zvlB98 zI!#jL+xdsrWRBQqy}0L<^I!@ayE)FLIx#%K0GN?+Yz0!oXrRfsCk8j--i0ojRXuU? z-AsUW+0H+_=#wX7c-$z{+^s%z;keHG6Bc!WQArI-DI*-XtblC#F}SabAmwQF&tNX-y@2Z=S|`LXV3cI!g3TOZf=0PEdhmT`F|;UESU zF=BN%W?YEalPY8lk+Jihnw|Jc#IAzp$Iu4GN?EL8@82g9Yrym48p;&8Up&X+wtWTN z%7Wa~L0v3eOU9TqseSXn>HXW{JRLL6&=1_w?(7uX`G;4m*?g8~Ty{clXF4C{#o4e0 ze3=WeMmbThxBG#;U>Uaa4=-oUVq5E&G1yrp59Jt{-ri7m_3=$LW*DNH<6NeQkpnvh zh)0#Am9B7TQR`#Ks)pj!lou-ocB>Hvtr%7`F-^_{Q90ZBhnF*GI&FxJ=41?z#h9XL zY|fe@aZrMjTdFy{BE_?e>*ty!&fhWPZZ4i1X1PUP)$AhYH)|kvX=dggw=FZuXU&U> zGs+tMTt=x5rK4`#@Wtt6`LV@PS+3=zj`m(m7UEnditlh~i9K~}Zwh0)czz6-;yN^E)S*}k{kl|5<)vg=&knbp ze|V)jM5gjmI8`GZcyKdm`UN`8Wg0H{h$x>&wE z(Pv!rNqUO8lyIyU6;5g1ryMI?g;Q$x!f}hLa7yQ1IEIS~rxfmm;~t{IDQ$b<*vPAJ zO4VLC?h`7U((@!NGZW?!nB~-Ri0&!$g4r43?91eoa@-b)Xq>r-rt-#2ToX;F%CpVs zRGnx#Rfwii#mqxeO+&J6Q)`^238t~$wy7msFh=4;9FR^K0ZTDPAq7(yG{G2w6ingI z1Y`73Foiu6jFCsd6z)tgMjZuHm@~n+aVVH-8xxG1hJxvqk)_Zy*z`bfh&ElSFOuVm zRRmLA#4M7NQ^8?+ZWT2xI8hc?qZHlxZ-yjK1xIPhap0n!153tJ!bOtZ*^=1R55^E% zt4n8Z$A}|Yw_H#ptNb`!@aTzW$?~9anC@iGF^VK7$a6oTT)FtgNU=ZeXOr|XmAC_W z;kd75CCTR^LdnT|a;ZpApJ$5X_;g0GoIJA;%5f{QuXAmY zq&>M1%Dxl(r)6M7*ZueRb$4~F?61qo+0Rw-E7#lDQQs+?@sR#<@5-YiozQQ-hlHY&>xp{?&A>B$cn} z?&~E{SA+jdxUKJ`H67%xT|>U!u36Qwc3H<-{OckU|7tqB@+AB6pz4IGt6^c5E$gdW zQTOK8Z{EClXw3;jJCyEo{)@ld8xWvWm2Lp7TG@Wr1%y;2=SK$#r=t+WSTyE^;x z`h1`&Z6ZYCn{udG)ySI_K}>ySL6c|N6W6Tn>XheLJ|}s}Z+U>_v;Man*q*CUbqexO zZTO3Y>O>FK31d)|)9D#d&C6l>QcxA>WkXdT5X*wJlg6Mb4^L!3wJ;P^o#m9lDQ#7o1%_Er{k(^!$o#$kEl_=(LbW~()rP-V zs801zEgyrbJlm56RYjb5O~np?Kr7p-wv>eGtsa^p^C|yZ(mO|?+K`57eOqExzlQR> z2wzqFH~6I^{XA6n9fPVoBbfnJeF;o9RPzq1i7OD! zz6$zgmMmZ3Hjhog>Zkp0!Rjj%t4(RF*8jy~b*9Jaj4`arGrSpCb+6^g_66!wzCeUk zXOP9_#&-3K9-D&IFZkbr)k77l&1tMQcxT`*%&yMzSUqqItMZI_23GaeSf%W$Jh`vK zeA=nSV+TAion=>V_t+Gye#ZY6tRALVZAoLb(PQ;cFZ4t8+0}i`$p9;eW@H_C<@9fYY}4k`4&b;nBSYZZoXPFI!c! zst$ijY&a}i#%+fcbGz0YpWb`G(z)$Efb3s;{L0?`j+I4w5PRH2fJP3=?Q@)L7ra8S z?bfH&h~W0Yf9WuHZxvCPhg$(@AWsXn3G}ry*rh3&iRn9Vpz+vWXz{-V-umKd*-a1! z#LdHSRxGvC72unjKg4&LAbdFZ{>sq!Zd=k3AiHBReiO?J+X;CG=Vi-~M&HT}D-d-1 z>}7)M8pHJ=nYcc54A=6uoC!q`b+0(5vGSmleTIYlZ-Nx>u}DBHAZ=3{j01rYNE(Yr z^#F!%V&6YBoZ*kc$aXBg1aqy#TYbT1)=jWR)V9_cYLCoBZGH^3C2VU!Ve1#N!fBWL z@KTX&J;Z}ioYNy57*pE;%^k_Im4cCH#D)*X_Y4h2E(dgA%K!2LV!Z*ekO{r)2-Tf;HmCP|ziO+u;mJmwcI zz@}EJI5|odso((sq;3EE8GOca6c($n5~Yh(?p*APU72b!*fwUuws{P;!Kfe2lH4nm zGX{6vv7%?19`^N14OxgzuT9ma5bZ22o)?d%{e{rddPEb?!#0AWn*9tz#NYEd9j+=zJPw;Bn!!yF3%Q zE5?u;cn^^o)|c{gdnIjb^|k+5#`bUzNCD_2{#$X*_u6W4y3K|9#&iB zp^;@h`I_M@yB=*wKFT2(I%*SAHo%SC%|KzDdqEH$h&WOruT=v8CL z7Gx6v@$+1IPB9Cit-)cMWJV`=p5rkn7`;j{*if{JTks~CJF{GA(0zsB_zZu)Ck*m{ zf%pwdz+bo|brJzS@<{j)BY4>0Si|Y+Oq_O&;WY4qLti3a=Z+Mpk&SN&QVql5t%5F= zW%wER21WvE0r3a@ZyMThvmK~Yjxd(bJgC*n7>^|i9yu7!GR0T-1nMOV7rGU+z#HaP zuAHaA&IIRp3yJ(ru3)@)2YCd+eVl>&Rhi)K9s_qNN4c~WZZ2ho@!^gL!1$;~@>@KG zH#h*N_It6nW{-yHi7-0LdK6(e0KQ`n0ETO<+iL(Roo2zP9Z8_$OdMmc?d5kSVU3}; zClkGE$Ix5Cg=iH=G|R@G>LDpMcB}s_5WQR>+L&@)v0qjU(cvHJ`uH9o+J-}ma)K*a z50(iX&M5NKA|U&}*#I7mg@^Tq$aR^B>>Wd7;4FkoX8N_rtaS(dtg5*RVVqVy9uDlJ zcYUipY6Zos{BJ?=6%NIzQ(sN7r$FP(Lku*v!!fj9*b|BuW4RY+YjChu{$Um3l1@W( z2k0f2wCMsw@d?G~ysbVo*^}|qWXa87yyt?)cHufiZ~WNf5`-*|yVJHCGBLez4AX&+ z5aP2wIa8j(=eX-U9tEFk{cpkN>HfD^>ZOX;CifZ=d%Xd+E4*iGD`>OD#$VO(FG3Dr$wP%Y&!Bu^!zff_#k7(sR1H#{^2 zs>k`?0@Z{4Z!x#h;9O(8!A7Ht1v5U;Ae$Hz z!~wEWn0`qt@5yF)Uy}*v*N(wCfOE9$Xo7q}`tkm^ zApLNM?9@_Op`*bYWv>3xEDwLB;ntyzGM;U~lV@Ds4ObUnmN|dpF|-8De9N7@*KW8V zPAu~Xu8qCUu-u=C<;`PQ4zL{hy#;|>HelUH&od75H0c+(i?-J`dFV>Io&L8#**zrD zl-gZxi65h6cNizW#fTi`;o%)Xwi7eDz%QmJ9PA(u>xs$q<}m;~3g^;JH7uW!iRCS0 zSPnem$S&)9XtEY2^dt2O^TgWHCB{dUlivc_`Tn;+c7wCNsYNvG02eQ!4Szbfhtp@t z;%@jHh4{%YPsqOBAiFgavZswfHZZ>tWc7s$S&;Rw4JkhO(BO`rr5*sn7sq2T2Zx0P z%yB=2d{qJ1%(U+x}zUxEt~<_zm$o}pZb(raj;FEI+H zc$?w+4Vk!p;~1_>;o6Q)7Vjq)8cOdcE3UK5^xPQP_}+bjbRv6P!I|lzRpP)*(?#Y{ zo#C%s{L9czGPjZwOeZ_bJZXt|sdH*}XwAO|x`e-MU`K?WI`?*l|LsenU(oTjGYssf zJFvqI8xT^Cubnvt_5kdm51mhZ=;GsRjV1Rz(zd!UMs#ka|1Ap~l@8%W8_vPnoIeIX z+y^^8Gc>~0cTTy^?gb>kJ|bhy?uEaiA;Xa#srQYXZ74n~(`27BhT;Il;X6gdL9ng6 z$VX`?xqR1{AV0lpa->JE$c*>DC8PHEo4@YZadT?Zq@^QyxnB5chv6HpVKEbA% zz~_V%eBOc&HXCMAn-%pPjecgvGm#wh`J~(Mo^D@Jj2W(lErt_oh{121u_0()99S+G z152(dV)02Dt)@lh%}B|5wX?|&cKX}5Er9Hy`@srxlF zHqkpQxIqa^#g_-#anTn$W&Pj38U6)LR4+0Y|F0a1p}>oUl!@wJkGc3ITzmns-|Gpz z|KzQi!NQ7+wkLW-i&YH9S{Yl*{e79HPIZV+ZSgdOPq?aKq(3;^Y3flKqbvXo{Dx

    FTet~6=K0FZgRzuY#W47@H*+zZcde#!Qez1je%4np;r^k}tf+_a~V0=qn zd_OxfhZp<#BXedY`OxX`&Tf2fXe;Rs%crd(ttEMUud1Az(^DHGZyJYvitYv3#!C&w z+r4eP%-hDdjoHS)Hinand|mR&6n@P-RrlhN^ic&joyhsO6p zIrK~{V*$_B^#t^?v^UcD#*+6CZ_dVD91I!utBPKbdB4iQ{|*oSt3CMNIR<_KzrJE1 zvf%o%3?e+kyr*9X7sf2;qXD)u9`-1GTWryKRIbMN30aRypDFp8zb}2}9@l45TRV8f zC7dO)AM)7sa9_Hy2mePrW!c$DdW`x$oDquuOkDxY!OJ%6$IEvU^WD}#-sL;UHNJ!V z%~%HsMu%_$C_wbxBfOQ28)@HXp~tcK@!#^lWo(${e@pTc73VEQyF9`16WgTMnc;BW zWbn12$A;7uahc;TjOOrJ_Z4r!S+4Yvx zR3J>RrQ}Q?*maQJ5UeLlPH#>1h6`P9NbO%?)*CM(>$z_3Uk#@>JUDc3kT=*R9+Ez* z%ZC$2VF?g}MaoMWoe9Bp)-~SmyT%87*Z9C#*9c60=-K4!1gGBUhd6Hy77LRZfUF1> zJdP#)QU15!{GI-{SpC0oI8W`nHFVT_oOAt~mY-Iiv)(;FRQ8>raqgUd&U)QTJ!Ib` zIslFXiT{U2fa?wBAM!B2!NdG-$6#I(<^oF(^SBQrj!)XVY4$i4oPWswmIUAHe@hzI zIGm?81@Vn2@5S4uAZNW?$J{f{_wY&^eb5XpyLjx0VaIxpE{4l;4^YlyTEjnR3)vTa z_Ha0B?l&5y|IT4r)_>VjvXk@SF-!}lX%Ta|&?T26w5q4rI4|>{6wvng-vZhx4y36K zNxZhk8)G{(GyFpk-`ayQb{jJ|1Q9Pk%Gb?C=)COS^2Bd4%znh%;g5PdeDfG)1+#p6 zZ7vs?+I(VaGnQcT!9m&dQ^JiU9yfcH2e*KIv;Qq%zuEtmtZ#DQPwh=&oyCKnehAkm z^}N_{JnqMb20s>60DoIkF$*nkJVnG8yTB5lzS!S>5l=_FpjF9_TbKBl?-HN%UE&jC zU80n0l1~hI@tV9}u}pg=Cwp8A?$7nV1@{g9x8VL`4);a-tM%S9dEu`l`TEef*W)E{ zzN6(u?Favt{O(T~xNq^`{k5$zHztf8>uZ*d}P^sL3X%o_@7Vu#?XC3-dAkHf;(Q$hbsJQwnuOgC;epf zNRA2rXu!YA1OJ~q@b4Z2e&G6qtL=%0Uu^Z864a*;xgYJZE8S*?|1EJQ``?1?^$y#q zZBo2@Gdu*Z%ag-@gTM)cky?2TV-~dbq1`pLyYO)oary4OFPQ!ULI&$)>kZvF@S4!9uB^>|?qxP8mu^UY%T2$J?0 zdr5_C{-rlA3+mbyS-EjbJSN0_UG6ZE+Ft}F!j7C-=|1ZOz{cmvq?sZ)!wMALTGN;_c8Qz2PKOMU3U?rPx=nh^?2oG2uiML}@ zBRI2r>9*$|v>x*v-(w!~J?6V(J*Jdj?B7S2)nfwRA>A#S-3J)blfotsd+{n>?|)0T z_-FrHy2UqKw@B@6qFaQ1v7VhB{?qh(?iTz!bUZPH*THw$kN95COV=$Pwr=q~-z|RN zyT$j%x<$|}!lU8-99Qw%J@bCcvv~QuSukDvK7dw_dg&Eg{BP+M`}*IK!hNn+6m5nE zzPD|L>Ur|voV5M%9tI0IT6m3Z@WxMUg5rhv>?h94dNE7m=m*6|Zina`!(2FFvUzEh_ zOJ@l_R4JWhhU+Y;4OM(TBAk@y@h^UhYIu(seQl4Oh3|Y0h7i|TM(bSzqjFZ@ht?bZ z&G&{M`QGsFW4$5h4dH|#-7b@x?>32rQHwCzUE*=gvP0oi(Z>9Enm`gXf)c=;$ zKH`5%3Lmy^klIVdvB~18#qbxa_B1YFwjEC`Fb8kfIrs=TQNddLXl|tb)L{P;5Br@S z_CFhgeaUelL3Y--AiyjE`(&LdJz_MwJLz%Z)gJKDA>QbJOCcWcza`)MtwW?XVDUV5 z=qTwY1ctu^b=T02Qv7xT>_~BN7?BCZUg`@^SYO!X`@+wCU--|lz94;p7BuxZl>an9 zR$oZgYSV^(z~h#<9=Fv07F<8*e+#a^W4KQ3tzr$y)K|n2?XijjZpxmrUZ*2E<=^llW_I5}z3}iKT}A`qXM+H2W+0Df-;?F@(oe z``=>T?)1OKynVH|b5rxl@>1P#>$=wF*7YWzQ_1DdUDwvx*|kjm)^x3H-?$2}=~~;r z;iPpdS9BlW(X+O%zJ6(EZ`biFSG3f0wryzZ*?6LeudUh8+hspCAQscuuwrgs*J|GB zT66p|6{zW2)48&nl3i<%KE_$>N=t_NqTh*u3s*LIRJ%mhrGJ0EG!U)Qy!tCKrrM~W*J&Z)IIv@}pzQ>-%cl3r#i z`=3N*zZ-RxW$g1b%0gYDv&L9wb{zX0GSk`b z6P^8G)OA+Km?ep;m*}iM)|q)}FEgF}G11wdMqOw1#X8fc@e-XCBAq4P&C5(@e@=Av z{HW`!Awy^46ec>$$2xnN;%s-Kv%yipbg%^J53CyWWoi8%Dw@t4n!gC0(#_c&JuguyNx@T`vb@=tWLU1$v3Rull{(LNi%ZSkOWw;^!8;V3PG*d{PHHlA68gdI zZJVMlv?19(-s@1oQ9!4b14dmfhi0fHaCLj3mZ%5yHu^Q9y^NLv6Sd45b+sIpp_ahY z?FCq3v;@=hy{wkmiCU^gT`hAn)Dk$lR7-@G4KJPFf<<=MiRO&DTIOY_CGc~hmez2N zz2T+vTJQ-!rQP;|n46TIjZQG`3Jz>L3w~o6w(aMrh*UHiit)#r$Xk>orRx5Ez(qZNBQP;}h z8Cr>*+t{~F&SCEL9&|*al_N)8D@SB#CGc$rdOP}L(9y+&4arAS_PSDV;MPGUKk7

    U>y)T`q#e4Q0QW{5HDa$gH z5;(R4y}fN=|LJ|{oE5y|z-gs<)U~p_SS$LnCtbLOQHiv&AvxB&*E>*4qLtQB*UBq1 zv=TbDo$Gs!4Qy@iOE)!KmS|=9sB2|KhE_ty7Fy{JwbJyGZNJ(YS#3)1bu zR@VsE8!ta_eZOne>%C7#y#o(a>K!dPw+Gu3BV2EM`OVe)xKXe7_@a6j>Vm~nsdu!f z+#bwbN4VbjT8684d1zd9NA?}C0XIOyNevT=K`(>=oVUX#>&?WosV-ya*-JMa^w zy`zQU_F!5*!u4L4)O-D?*Sq);*jkj4iocE1-y^FsAQm6}D zJ*juJxZ56V8jWzhHzf7mIO_E-enV)XF7V}~-qG2F_F(yTgzJ5LQtuN+z1~wY?0Mj< zNxh>5+U{2G+mCR)PfY54(x}(FJfq&hT4P7=+7sfFOYOnd&Is50)k(cKje5POX4E_I z*QDN2d$$J*@*`aD*Ch2mdDQDYEu-Fnzt#!&JaX5%oBdpEgsc79q}u(XUhRtFYUcxY zjn$64weDtr5N(93{ko*un@7Fcl^N9z*8EuQ$XV+S7A!`%+IZ`N8@x{)^=ePgsCMA2 zvD%TZ)*T#D9pP%@t);HoTSvXx`({)-@YPuD$W`lZ8nvl6USaI2ecGs3d%uio2d)~c z9eHZqqc`(@LsIQ+qh9U(GpZeUYOHqTsC5TR*CPyayhY2k_UWTu?HL)>4jeUBI~upU zTSm=KJ0q#~nWJ9qnHkj%{Ir3Ncu%W)^j6jIswvmlXN`KT56Y-@;H3?8#QU4=4Wri9 zXD78jXVhzba7L{IA8lY&wAI}m?7fU|zdkpq^m(IR=|hSuT?jn1-gswa!|1j2`AMZO z81+iGWK=rv&t&IhZM1VTYHsP9l4@T#>eX(~sCM9=-GBe8zW#hO*3)yVa(Dz;_Y@}Q za?6j%evPW1S z<(VAwth!HmMl){hrOLB7ste^=8B`g{vpA{^&tn->9pnw<3;efQHBap?$L+VHSf{V5 z;~ie6(Wgy3??khKY-IGP#U+Z;mioVEe6)iix9WSEm z@XcYm|5#_zXvVtB!wP+m7n`GUb1rxIY&6Fi!b<3>?dV%h%|=Ug?ozpk_pvyxsO;KM zZgB8V14wTnd7hqm19-1fIit&FpxMq-p3&2nu#(ENvM%`BTyDY#lxOt3Q**gP&s3h# zt<%7JoAQjV11t`8^)xzc!69c(h(I%dYEYRpW0u~ zM2=H6p!IT>4h}x^3ZUW;xX3v3;I3KPMHcq?YA@i>H8{BQGT&>Ab%WQ$B8^ymmzP?q z5qCfAwc0`{z%K7QlCiqHR4YqAIJm3AOBrjvm+H_Q=N#ITv}31MyK$puNpo0LVP95a z5PY>(mf)Ks##jH7OD#8Uv}DM!ID>=F!j?Y!1?3t2ihTwLfA2tV^voan4rBDf8gvBY z$IIv?>vFk6o>iXFEYre1rzH^Vv zqnHaAh%iVU6b*&9dx%*z(o;9Crp?TbZ2jx>U~U zR{mX#JJ&1E=rS0qpIxauqiGa&xiK)}&3Ea!c9?n~bl;{tqstJl9&OLd=qbnKa`|h7 zl{4D#KyIj)YB4TApldH0Fl#q!2kkYQp778P!gKAxxJ-v}Ej`m4(bJm^Dsq8GIWjlA8h)?g~gw`v!8`n!=efRb3a+CTWAaGpA{3wwM&H*0Wu zPhu(;xmw-p&4^ipz}`U!~;=S%5jAODp#@ zAjPi#OgDKDWmh>}v*&+aZ0c&jlZKQ3dC^}bO@CE+mJT3&(%|4Pj-iyN=R7+&_{&d{ z2b1FH13!hh_bbon{5NvBnSdoPqg(KM=03_ZdhSWN+yZn>UPco(wSOq)HGWKayib~N zEi^07==@KSo--Rp^WMCRyc}uPdts0AtR6F;gwAFu&*<7?2L~T=a5fqq;^5ASDra=v z2L}g#;^d6BHlU=*@&EI!J}znL68FSBrt!yzlxH;Mo=5$7Svs|^M%(OEp3%~E(AK;n zUWf8b_e}@qax+d=p3$xUmdow`nDUG^jF4+_=S|7wj(E4q89fi(v}u~-IePAe-Vrcb z%)-4YXKi^H(vxW?*hbI19c{Tn<%}->4azJdeJ*EoC8nZQW}^-3jBR+*p04Rx`xEzu z11p!9D_1^i8!=a|jjSECYioL@b1_#=_rinDg(tdK(9vMoH_`|^vN9eU7v60j?*)tsZfg)uvHw@(W?Jm`CnYV|C$L-Re$?9dW#`OFTj z^~oD6kg8=ZtX|Hf9HTXprh$sY3^`Q^#6XJ~5}uDU_ehME-_^KA&uxQacdO$$dTtw_ zCT1U|#L@+?~s%+ zA&ZRvKSPYAj^}96%(r6R+mwvF=%VGUL4=8UYGktDzj#{b*$8Mbs-V7Xy9`E-w{*-1*yGF3&Q`r?Ec)X z7!~ePp3ySGyDnq2z(L}&z~?f;I$uO8^(OSWKlv3*C{V2Yb>8QisM)9_7Ch!*0LB^= zFBurFvna~5`%RzK`2e{_x9$ROoyr+)Y2DX-@@msJF;%4S2wuq!;ogsazBnD+WY; z#H*yWhwd&4(wnZjduDUM+n4DL4(|9wz}sKr?)qH7gJoq?MRHi2V%(kg1ab%HC{ufV zz=IRYxX=7B;LX-NcAp;bs#Naz-v+#D@^ZO`F9y6h8h7XFfcFZOi}HmvqfQ%^2XY5% z9#P#~U)$9j$kjN#93JovRbEu)!(4q24diNF9$|WBW!@UdEoS?oN9+uE)+Iu{9PacS z*7r!oM)jm1Zk_6&`niCIi3W908cMeo$0tJ)_lz#OX1w zo%i^BNvmCn<>(pFI`cA`m^EIK@1sF|9j*39 z@a)<=$@dOlKH4Fcm3E_gQaWGEFqSEg_JA~TQ2ksiC+?TimC>wkZAyR4%hEGi@=c{T zz1GVatz$$g-!8A0rH+>N-5JYGKiu~tqs3mieneca#D>VYTkx5ZqcpD3rZa58(Lnzrt7;El_R*NKTYoI7>t;ArJApe{cG1-#6=ozoPjyH6@!Bb?OZ z28LX&4cX8d9O)+k6--;fK8QwQCHbG1=7In3MpTA~}U=TYC8aX4K*nQDKAU6kTYw;NudTHhVjb1MV{7oo-Z~{g809e5Z6w^zv*lv3HykF!h zXWEt?{$Bwv=$nq`Xs$t&JD?gp^LEttgDPjV)CZmcFH48k&yJBKap6_i>4BM!7M*_H z#dUFLF)gm8ExK}fSRB!n#2qLUTBUa%ugU^ia!|v;`=cj4>F497nPAU>{RWpx;{V$L zX*bz5T8aS2k(bd@9O3c79PGnN?k8yOv{8Sh%YcvkZ8VLALOE>A`G((NwVjt>Yt~rj z`2Cp$jEFJqI=|v+tlPZ_T?GAebp5f92%ADRRiEjlP*f?zdcU9w@XIiDvNsb=Dphfd zhYSV;4n7V2-a?}%$#@jxcsTWBwTJ$(KeGc3o~LKt0NyWD&glFfpbw$~m(g^ac3zjkbEA*t%O$I-YgEo?cCP9lE6?gX z^ISt7 z7rhOS$A86eM^7RGu;#}@THA^r)xvA*rHzAWt{o zKzU)lbM982)k$y(SzcjWo{i#Va@_Bo2F&m>TJmuH#nKT>x%9|mI@-t@mvv$pw3R)t z8u}32I=z@K1-Bc$TrKn=7X+4z zQT;T&)k`g8wcW6|)nX`5tFI2nzx+gbbUsKQ`2E4bUrW#SbnO{{{Wg^|TAKdb%Ck7N zXJDW08z!f8{h}R_9WAiNaKy`WHS0&f>TjTU%w3vfaHLl6=Smfa_PrQugHvQrID$i&c?$GwUEIsP19y;V@bS;KcOV4Ny z-=}tNj0wB*P@b# zXPnOE|C4=%VJk(g<9&r^up!~=|GXVH^{Q3Yu1$Wz0JZRvMZ-;YTX~uw5`G8T=_JQ< zG@gA=PTm+@xXhotF}nT>SXOXm)#&_>aLDj_P0wh{pIpnY5%FxwZ**ZI8ss>QYc&7c zi7BI*-j1KEoYATc@~FT9iPx$Ir-OuUxL~!b!)vfo@ev-J+h18vjQ1!qJ^$8wPmcBI zRPQ}iscypswraA_tE#*dj4D~R!3k-&SuFSy2Y4yR+I2^FUoUIH3tkQ3z3V(bV?5O1 z=o;VJb2gwjlRXo+^=KQF=lHI|q1L~gT_!+&0?T{bV8 z%Qe5zt)Ion=SEPYEe(n5;DHqs5l=DbMmPpkC7+Ql8OyOyC!sXL3r@^wti> z=~W&R*fU2nkK}-$ONVhA(FJ(fecCgVv+|Q?^`MTZU+K2^&&%3@JZlfrC3&V(%TN24 z#ntj_2Q!}HM0=R>3=`U&lxOX#okw}5OR>wMQ<{}}-t6}yqnVYpe(7|EtJ70{*hxl4 zz-KL>gH`gRi#WOw#_2KVbQvuwdP<99w5UsXcmP<2iOs$=OOZCx*?plma#os$eE%;C zQUow0MF$X#t>8}9^wBvWkAC)S|JXMuSQ$cmnM+$aj8y3 z$$?AYXg0q+UtzSA^sOpqap&HJvYn|sqpP;V%kNR1(R{$Gex>q^ruW|HTEx;8Ex0`F zzE+8Gd)xAPo+E3K<6~QVSJ{tvz;aldU#X1r{Q$FuZ3C;!`i@A zVRw&QO%ngzJsbz)LAFzQuTwLh4)Sbxw{Sg6%(u@94zt*VJ3NSmv}NiL$^rI-NOVZ0 zLgk_ZLRQD{fY2}JWq$qHawF974wq)P~2aJS)%Rb8qH>#<9c8yS6L%bB@SuIMQ3f8UzbnMXjQMq zwe+~pYiA;iR+XpZR%0BxUU@Pz1I_e|XXy!SmaCl60zbzyIi|4?&Bn`Urf0lF4s}WP z{vEANsBuk>=XFefMstQ)q(8vg_R(2B(k!3xEIpY)F3~)UX1dr!jz zo0rj+MsBFR|K2vWE3Yp$YODSDk2RVmXny4eF72(=Y?5QKa%a9t=uI(Uz#QBBs1?dH zn*Uck?0KZQSkUSEsL_@#?C)6@w&`ZwX}*|8q36FH#xp49(asqBz|UMJYCbB7+glK$ z#_=3I1*zDIjL|$1Z_ni!EsOO(aB+dlYS4l`;q`9ayhR3;H)s*L5PnD9JdphRJ zKU6uRS(Zm#{|tFMo>Do>gU50n-=I9Bc`WB~v?MR1%dbFLU>kWE%{JJ1b20A;XDco4 z_$QFwQk65hVjXy|SDw+_M1JgZ$}^gI?0QalrUS0XKm8}=8BM+H?o077wfU19mpSDj zEpkW3d6aF$X7nM-Gg|P~qdcnz$C{^In;T7CJo|vk8O^xQ1GBuWd|b7jcBS!@CeI#W zFq&Ae{i&DZeeMM0VaItHO}WNN%1h!>?jGfd9BAu1rhNV?c6z}JJehCH)5l%q`|&ukO(*bQtm5B}%H zGP52mpV}dPNU@GLx9O-$xZyMqpELg1m!f^h3T6P{KH}FtXDMr8zaOUR-RvYdX4B|c z@AE69ScGInE3Wb^o3E_&EF^DdYJP@gNS>+LiNTB)H)ZC$&k|N1RagO-Y092gDA=#KX^rG@LT{&fp>OnFD4;-JH$1+%22b;U2z9zM%USNmfKrYY zQVGpn6TlmDPK9xDoyTbT?`mW8ai<}T4{KbbEnOTzJYnUzymy8cvJB+W=tyvKt3T+M z#^w@y=tseOJ&YB+*Q3_;wqV1+Sl4=2sgwN__TfywfCitFm*$H9-$Cw69naBK`v5a1 zE6-@2fwIT`jGl?(<4-@Saz=BJ>n9H=&uCeGMK9+S@i0X2vbeSH!4Q6<@{HzVZnkb} zw3wUoVmaYmtGuMlD2KflfDek2CU)!{07lQa$Uir3G>4H!*T1a%+ANxf@KAo?xq4W+ z#0pL#f(8}5oatnB=gx26W4 zLwrQT%H`g`8tX>CQ)Tcu&-?stL>Ks64fuR5fRCdm7X}A^<6vg=?0>+{&qJseE~6VU z3pbw8RM#{2s+^_GnV)SW8ol_<@H9T7az^LB?a$I0&Gfh<%gcBRE0OQJm1i{1-u~=V zB1R-8nF<%WndQQi^7HaW(uCAZ!$X?Eb!o~1ma=@#$4MR^vNV@bs#$8)rnN_iGXi$xwPm*@X;wQ{IM&Q&gaAi*jZJdkjJ zcDLH!`f=Xs`$cc4r!s9-R>efr@%O0jHX`X#j<&2iHe=&|L^=*rJ z96QTVcV0&G9CDRQ&uAL1+TW_2r6am>>Dhf66_c|vi2kH3(4QPRIM3@3NwR&zw;6)P zq{FuvnzHWnV_&06&3VX=kT3$gG(G%>zisa+G`jZBz>71OM$cXD2O*=S>`pHhm-Vi6 z{($jj0#jA{X}(5NZjKu`Esj=5J^QfojFt-Bt~^UeOQk%! zFBKNKfkJ(uz?&Cn?clv8yQ6`nU(DKJ&A!>MnX=E}lC98l@c)0ju{N5o^t59gMsvU% zl(7X#I$D!vYQ6ZJGq)t`rA%+~WtyR*&yL&t=mQo<(;bf#kAfU+cfgA3eI|_PTfplD z&)pLqch+G+?Vc-u_%avzu3?#f-rG&fe9+qwTUVap`vL6XqJJ*hVAxm6qj%t%sD$!l z8~*bs&>OX|QbWg^eijueV*m4nx+T6=iq)`&w?UB zE|%SE2`i8K+l^66Q#Kx|a-XXv{`0bQWbs*9IitDo`q(d&X>|E-z&lTQM)M%2%`lC& zGEvgv*8UlCZ_&6$=f8m&@af7kS{92@c3wtXeaJI8zR_;#bL5bxH2*Ka=x99BvKZ^? zYqT`0@B~ArQvR=s@pF&w?61$|nr|-Z#;%xhXTC{D?h3$rkUbD|RG0FM=KmFsdmia# z*kao!G}_YTOQ;+2b&PP4FXchR7uqy9qCplGda{maui^S3g*OaBA~Hx`)5ey45kj6#b{#` z{VzOspTpL!8$~RM!?lo~Rw&Qt1F@Y_@p0uDy|4yI->f{NEiZB{Z7nJ}1K5}CIO~kQ ztx~d!wceGu!AjnQ(gj>g@{E=R05__IyoMWMInHS;U!xhf`d*cbct2ELSYKNQi+Go3#9f=gL*Bf?@-<$q zJkzE07pGIxrSP0iO-CHyOjp8#j)doQW%`iC2&WhFs1Nc?FIIN}j?;ngPbzVkm z5y`h*{Ttn9&@%avUv5#uq$SjCh)O~B3jx$=xY z@C-QLu8u}eJrHGgpf_5|d#A=VTFNfGu7PdmC+9-8YtiA{d+%y zGl*u92&OU5zs~U-J>?i|C4XCaMoY7ul)*!;yh1s?Jdu~B&9w$Q7H>5BpMAa|H=&iEyiIvV(-Zx*>-xsyBN0Dyaz<0mwyCXrRdBUxPS^B| z=Ga!_x}MQuoByD4#^a+2_H4S*lxuYUkLg+3)al-6!NDz>UdVgi)tC24Yd2Ln^4JdK zS$kM}k!S5D?Esx?Pt~}lBkig_J+ApNuC4u9`DI4u>S1-4amnexbjkEgr`G=3Uo8)` zE9y=j|MOy*iEZYaV0;Pg1G6IMuxr>R&oIuoyRC=1J|jHzDXE9+TZSi&X^Ja8>)y!h zFZEWPh6){c_r|jW z#U%(9b*uz86igENO<%eG1l_U>8!Ac9%?ao(cN(Gu?r-V<-e|0$n*jV8aNKG?RHs|#E^ zclz`J94W=G{qmh-g~P_-DiwaaVx^Wf+(pFt8859n{^NX^wJZU?dzMvC<)~u5G@k0` ze_ouZ>;Pa{CjRFoJ5oEX=*qLSX`r6HPkBbS!V$J}J4Rdnl(e|~j?dFBuF=fjzWosL ztW$=(UBA|RBOa8;%ktn-!*durc^S>+g6A+c^D>&xdD$YO(bUiL52>8hjmFo?Y_y#F zbH>kT*4K9LERUJ@`M5^Q4&`;4htZ~Qa;2 zGTKmkrpj3yG2$++l~s(mE3?D}CbU0kT=Iw=@(e@d5o6>T)~vla0BE~$^GDW0-mZpa z5)zzMldH(}9&s8^+63qWm&!yLwpNg(o`T4o3?kTT@>Ob572)9(0?h^9yh4k^OwcYY zPQ``3I5yd7^%Ey6VX)^6kWg`hD?A3Lx{M_~-2SG=pwUw<@uPszY==RtK=Cp;o(*B& z;$?LHDOiN@$}^fh^w+J*v$$nQ%ifJ|v?%5_m9seFCR$unXAbU*vYeciORLGa?EQHX zSE>SGLXzGe?8i-Xy+7EGGo99ZZJ9y1&$CR;!OI(r6&M5*Rf-h6xsa_02eRV!VjFRY zcOl@&@DdwwG5-ITZy%$jpWNx>-2E!p7V43g(SmiXvhuRH{Dh0?-Dt|&w+4)sws8I2 z;x2fjKPzN()po>n-iFZ<_ioA7=iBdbG1t*e2V)B5I)c&C?v|b_7hmmV$K#A<9u>E1 z9-aq`y84E^-S@e&&^|(MVqcv8EI+}S%U5g;;)u<0aji~*Jy$o=k?@?Z1dk|#HooR- zW!2XAyh@RSnUON1BFM7AM{{fq>WJ> ztV|!NgKN0v40FildH&npkw;63r4QCrnl$-}`@9y8){<7=>L0MgA{Yx%9lT3v4s~E9 z#%RO?%b1Mwq7JHWwN%Kl`|vsOMDpVz=V^YZ=s(^?IW(H1`N5@%zgM2oweLZ11*&-& zO~0t}gUT~G9tK^2{COEoc{@OAG%Z5)4^=LS`y}H2T6r@a%~7%%9sw_lo5%2Ey~}9! zis!$ra$#Is%<*!lo9iJa#}BdEn~jXF*zHd-8Ev`^%R(JgZ`OQGABq{}Sv}cNZ34@M)}D{S>o| z30Y+P|0ME1!|@#5y33EkMvG1y9xRUVuGP3ki_StG;s{UT4m9;|-ttC0v~smp2Chra zDznLNj9bYsFJ1wVdc&bxev>b{WPiEK3jcZ8eY?l)O0l!=@@m9PUAE-!^Zt#Syf^&G z50>bsw5mIA@g01!%L8q|-RtFNN7l%HlJn_>mR@L zE6R=)zI?}qh2ZOyFgffxa{{vor-zqVd(2YBvg5z-q;TN<2YS{?j_2sg3BE@gZD~kc zCC8S6E!(d@-$NsPy(Ok0XInoF6r90qY2O_kfRH7i%y_5OuRMwk5%PuEVjNPsulnWu16UyGgMc;khklX8rRYhD7f^j{Dh3vLuS8- zqiw2jEp3_ox;#v8+Juyg&zKaXUtOaBn}XY1I>V~s^Y8ZkYLOdpul2`A7VG-Z?%#RV z;aZrTCwZ2Q%T=D0*R*QuJit6M1a{O8^HTi;H&0x*ZKjFk*I{={oe;@^=dy7 zEJDLp)1!Ij#{myRG%t;g|L{7k&a6Z2M=Twcqi6KYk1ZYLS)9dh1~C6qc}DX)cuzYp z7;R}#(&F-23R^ign$J>HHEMcBPdUba@6Tu}C-&M`cCK85eSsEP0eP<~h`tFM8>3Oh zPVbu><|BRfngvcCf^jr~uz;g9E~BNONH=YG^HSXR z`Ql=bk&!)kb@6nk^YgrAEMrP0sq078S13&Q+e#`A5({VYPV~ z&G-FT-!|IPm1UA@)qTWw2-_D+AZn4Hw~>653ddX|VF-hF(n%>3+a_ ziAK{#Ro==n`1`YV_?9sGfQS6>ZuEgrrw#8$&wLzk`=X|2wAjJhlxO+QM%fIiM$`V< z@|KlLE3R?vzMMo}VLZ4oNL#B;-aw&F7oI=hp@2p^2)3ni)vAuQ8c+TTuXj~Pm+{6a zp|UPcFL_KfPvV0R+nxD3VsnJN&}n7A`Ufvuj4uTFc{79S;{k-7JJ&y zm1nf3P2NDhuC<=T-)e#Aog9M9v2V9)h3}ta(Mdfmm^;)cZ^wGSi{=Jfjg8wlCT@pU z#V-JUy(Qy#E{@5Ioa4>?@!;UYC##&%bFrJVV?UKyOhw%TJquyci=gO5CUzp{oKw@I3#n zyZm`5oBv(aUZ-iI)3Pv_EMDek!iJ>a1vrlN#B`4&16S~ZKVtL$mFdYfc>B{sguogYbK|WZxLaSJb4||(WROn261G&|mwyIoux{q) zRveo#Xd5j}j*iUBXt7Mf8z|)KTX^dxUmWTavx}Xp*RDD-F)N~EFfR;-XQxONMkLt4 zost-6c7O|Yh~a-;cHi#N-r+s3x*c${2a4t2S8V5k7hb{G^6e0XyQ23;Ox3LTo`=F` zOhS25%svzYZM<`-<2jnsm&ZS=JfrJ>h5q_=vKjk4SQj+#o}ODqk15Y+&Lwt@Q=Y|b`~s%lzf+#k?A*JT zE6;SKEw4Pg&(0sp(fyM4aOJc7w4r@^)Engz{n4d?e#zs1bmvB~`5*J9gy3WIe#Kk1 zInF3t<{j2Dmx)Ls#?KH#<}#k@MXQO`PtUq&(9bU(GbjIa@|s zyHL_}#j{oR4Hcv5kk}hLjkfkNQ3(cHzg-DRWs5ahhC zFfQ=qXu}tI*4D(3wYjwe;cx9BJhX%GTzi<#wVN!HOm#R8)|{*d22Xo%48^69@gHtP^+}HBXr6hr9V(-xMQ)4bX5I%BtyiAWwO@kS z2A`MFQcG83OGkQ~OV93$7DR3!UuY4(?33Qm!tioSwBmGMW2;{9m`~zDQW7z?;6L=l z%V>Tb#8$hEmLlA#az;yWgvSODukRLL9OO+uH9Vhg#VJ0Yu9ArHH&}~yecNcs?u$Xz zpe1YJ4dff^3cUF#&6@Q)91V?uWamkK$iWyvjW%5Dy%tJw+zKYnu#ikSG_}(-V@(e+ z-~rfC52MA)xXQ`7`+R}YV|OUeXja5Jx5b_RI`3f`-HJSq_&bejbRCp(#1+ajnjcg$ z<7hPD(*Wbd%V@2*@mOQ4x$>-BT6OZ`O+s{~T<%uivZmf14>XLEvORg5U#gzOSjdPC z(S!dNV^_lO(Dlre2 z7oLWeFPVya@@cIM+x8NU@_4rI{n03o@t=jOyu+`JR8VOsckr5*{ZuMkXE9drc zoh~o@=SApnjAxDcU&nZj!&fN&;!Wgnj8}T@Iq0`2iSQiVxC7fDo0MlXTcgr-3yZ@| zzba=Djb{F~*KKk0gI>;P{;&Uo=3zARu*q1&!+6Ha$~+IJ-5*6G^D=tg9DJtrOviIH z&l%cl@Qh}cu|<}M=OzMHH+Fs7xHVer*#peOw?p|)umJHs&DZF%L;U)((c;JcN##PG zeI>{0%kRS-{xOv^dPxm7K;ExBqph8zvU~_-alNSA(R>=f9!WD=Cac$JdPYn69EPl| zwIivVwX60du4K2 z3)2kiufJOFaDu^|m*^P&wA97<)zXd|Eg4GrID+^4$#d8TJ$Ebm>j94E=(&yPU#J5w zqouu`ih2A@uYIr3=(#ug?-d$7cah%?HM$A&4|{cj(bCq|Z(JOH+O(!k^EG-VWb94z zM$2a1$&~Z;Eyv=neFM_yvbDhPZ#6xmO^@VS`S?_G-r>z?(=FvpAA(<}7c0MD)z!nw zrH#*+aFLqDMf!{%NTF;w#Ma~e6gYKECp>ON4B}Er{70;YYR7YQ;R*0>SDw-J^Wkng z^JX-UMA=l#Xcpg&RvE2DV0wI$t8|FleX)sPE)G8GS8-vkxe_=3=4d4j%H+jWulesa z3FT=5Na#CA=nThmbk#oI;2O;j_}J^Zjh;8%Kk8&OzvWzWp{8dvSLEzH1x9m4ZvKZ= z&S)zq8mqNMmeoG1m1aFwX$w?W`L<%EQ7x_X22CrMJ65^#o}wxeZkOZMMch{@w`yI) zJx;l^uZ+0e%AM8}aeI_I^~{L7M!EW8-J}fS1K+W6RY#!n&=G-N z^`9zdbi?oc8A78wzlSD2UFD3HW{W?IGmmK)ym%SSJnRkfQCwFKi3^(YjDow{w0Lhu4z6%ZFICxSpikMnJM!>Zw!KnG?a!OUuT)!+7`P7sH?~6+Du^K! z{n1z&2cX^332U8Tf7lcDZd^0iAD2OL6;Brx7~@MRtnw`QmiUC77HK$4j2#x-fVXUr z|Ne7ki;WCZ^sRrccX>dJk<&ouE{~WI2-D`RV~h;E7zuA1a2V0-Z$Ha`iflB#*_r;PvUg``xMrg-QFtj(itxU z&G%;+JALK{->{%amq(F)E3<@&Fzr|C#?HC%-JJ!>#9DW=@bpUoxC+CISL_$Gh%)_( z08yT|btYb2^n#qSV_xuq2|5bPKu4`#aJo4}3+cZqy`48pG`1XK{tn!dG-9@(1x5Ld z9WTTj8afceg+}AsDdnp%j2gr8es%96NzkdC-Mh%e72dljf2F+yvnuWm*pF02iQnRf zMU3(i(*Nm9y1I1{+3!aOwZnr=lax^SK;gtu5~u9nL_&{9h)BHP*qp_<>#%)ds%wvFFO)g*~q z3y*cGCI@JIla{A7y~i9grpFvcV%gt*7JXG(f2B&h zU~bJm@-3xp%p)NWpql86X?r%nlF%8`u8DT+s#pw)YWbd|ge7l$7(MXK9S;R!(9H3E zeH-neECh_hAI#kr{7X{b>3QU8uSmT_$+L8L;Qm?BxClS;pkoou{?w8!b3`*@&q@974ec(HVz;LBrSJgCWkpr8v}&t5L(%jiDCj z$EhD}btfl6d=J0xiB#Hn&TmmCrE4-CI3M--3-K9;SU(ocI7AFuQTI{$e?Qgz64d>3 zyHxk;)8scwQKxn10tMFhu7@7uTEd5&nt z^QXf4l-e>LI2N^aTHz}=vU;~@ZN78Sfxc4s3g#Mu)!mpfjovUZZ0|uBABW*YS_NBn zayq>z+LEs0QE`y#O=qq<|BSFLKS-5WjnHFgoYkjWR9YC8zEkphgpy}*!uut7mpmIU zUXXJjW6ITc3e%R1#EO~}YG}-7f0*JNhRV1a`c~ccX>qE%8*2^4(0)1^1~2%eGv+N= zzFEqBU?OCI7 zB)7Kkv7~?_>7Yezjnel=nKrFCil^_jxyIqNSMQ|1A}2y%^xFHl(lMTcMm^&a(To?r ztuovNhm6n>I^&QrXsb^=?o`|id?0=QZ%X+w%v#WTc6itpn#Z1Q>y6ntl_n=<2#PIK zH%)eqTW@p_CXoK!SQ@+&8cJup=MiX{`-o=DZwk80I)m}hUWoT1@fkZU3=-ai=QNd{ zA7_3bdCW1Y>;9np9KcR`Wmf~(Nl%+YX(<8@R&j&f*`gWq_r({IM$AF0-x4zB0G9Eh z=?s>pbEl+a`|LptjX}Y0&7~lcP)@DtX~)?jEj%~vJq$~5U7I#@5)*NJ_j$Ki_iW%>%|9U>5K;+ z%`;xc13$_$UdB`3feWKBA)zzg{bA5zB95K$f_Y!{^EZpnnC*%((V1`N4-rop@fgqC zgyP&ye8!XeU`M|pnlZZ;eZA#sA<9fdC`n5C#jAnWG?YJp6LA}zUWV) zyZvceHsmt;lNq_x;qrPe`!ZS=ro)~G(<8pY+l!@vpcTxED6KliA=h(-5BVAa4jF?M z^2C_tXDQF9PPp`6oBdmnXSBNfZV$!DvoQT={rjP-_vdEDJQ?K4g)!fI_GrsE%Bh($ zjsi!S1&s$tqI0`jBC>6~p&Y`ghV&qDN2Q))Ayn*ER5zJ)rPO_BjQgUdJjyp_!|}J{ z#$0geKUHDP$4R%RCdQILd=4WKNJCCWR}lO>3wxOsh3dT2r@FGN)O~cP*FhY1=kH*Y ziMeX)&y9`Q%gjDSe8wSG>8*@I#Gn;ZghFaG?v<3g1AYj1*yAwG4yFj&9X&~Rj%^Mr z%3dAqVQa%*J+PiGkrX9MDn~$JwYwd$`0PLYPcTLMiDta=b2#(>6{j;^^a;>jC7N;9 zPxF9*ao4SRz`&RvANkb+W6Q)CP3u~V;zlzJTESf~IewwQILyIi6ZuH<1i}7cA_|}V zRcs7fswE8BFS1(x4zG(~344cX@dUBiSuNE^NUo{tb4WBzVk*kg!T&}yiZrcQ3I5VW z2M_;wSLVRfc>a5GU~0_sjVv}gW1fTb@it?pMLvg}2ixI!r16}4VcBjX7vd{8iu0<8 zG~RE~UN$K>_^ub9!$cL7u=WpH@P*}G&Je%M*1Hm=FowQsby{wh>!sO0vjxG46Eedl zj-VCO8FTq%X&E#ahYXjB&p6}>TF3)~+i0v$dEAp!PnlVs>Is9oC;2E0`=_Cf*C-uh zKCxs~HlF+}WIRuN#v#|IL^BQ=SJdy^?DjQ&bY+L*fg!qx-L>i`tHxB=IkDwq>?uUMkJp=-cDoWiC26*R~w8&&Z8&t zweCV06q+$*@4H`o#>|IljwkXPVR;i@bOgUv?%0*@sod31%z?x(^%HZ8i~U}k15&gc z>P7w5m`T;g>4%7`zSFbx6)cviFCujqDZfo;+=7%Ge$g58wOTJ88B;-h!DdbKSL_pL zHz+=*!Q%18Y i5}Yn)3BXVr@@ zUy0xsnz~!%fvh#=eheyI?O(b;cCvpdRs`9AAV(_6$j;qG4E)mB-+pC@bQ%3NWa2B8 z_~`PSB%uk0#i({w>aGn+#${1=ZN>vA;su{%?AWj@I1JF~q8Te{(xPh{CVDXCSuJ_` zr)O7dd8*3*D|z~1IoQ40h#D_OOZ5}7#vwzoAjTn2(2hT9?GQJZhYs{}VCXvXM|kaO8w=uYsPT!00%Z;zdIWBAWddzXgjM$BSlceoiU|r8xhd z;vAsn-fHCr3`sB%trK>#y9iU$I>G)*hYQLrWP#>|esr`8trmWZAJWDfEqJEwZ2JC( zl4tks%E%vIJlT$d-RFXU1oKHvW7gvCUpNq5Y9;qx!%5G~SQiuBKc9PEtXjQ2bZ zi#;oY)G+3=59@Ch&6wr3;kt=@U2Ab3@d?q4=fG|}a!UzY@Ul;X_7TyHxrjObdC`oI zMi)TY>5QEp(kw&lqK7PTZw|d4&O(Ita=N$q!Yo9PXhS!DCkG9)S*}=@X3cm;+;;<$wAc;xnd|-uxZW%s2Aa)I8&%wP{I>`Plv3V-?nz&1m7JqB(9!FPi-& zK56S#x4%AqMCC9U)N4@LAMKdqxF~*_`G%&l1Kl=`hx?QSK3Y&`QGc6<2{*;q`q7Gw z-6I;uv{NctnML(HTG7g?%*bsO&ExAsDjGUI#@BawMJucH`we0cbs_whLe#HIPGgBL zn)wdC53>G1G-Js>k#G7^$Uj#!W94ZFJ~ZGqU%}+-d2|Op6z9loCBA~mXPV`sff&KC zjm|ju3a!lt`TE{c_zEUp-{qoViKfxSn9ck?L_Gd7{EHuHFMbS-@FtWUKAH$Wc=HmG zM=rLX;u{#nF$C1B{6u5JQF=L)9W_6&jG-`o=^U0Dn_h!3UWR=56EtJT z!LV&U7!ZG0Km$S?P2;EJN*v9Ev?g!9ZcIOZ)rn`UKIXX9N1wFz&2L?GOp`uCuo>u+ zbTsx+HJ4YBxwQO?b3f!%nbBvSm|$obGaL=mGru;6Xkm9Q)~?Ody`s^$5%c%I#*;=& zBlpZ*q8U40>@Hn&>8dkU(D%0~CR-f3lWEmmRr|`6jZ_N~-HKD3xM2%Z4G&0-d;dEI zq%*{4Jg^800#A!(%*(QezgcJn^GLzqr$jTRSsJ-sG-H}5(aJhZ5MHqX-=1ub`Q&q*_v7xkxP?$`UmY=(JWWgRFThN*oqz2VS*N6aWHLA+WB~D z=e|(IG1PhWEdbVM79!Cdj;57H6h8CKQACOeXgKgjXithsOxmFjCXJY{y89@ZvEwa` zC@Sd56w{69%p4*dEJBba)xk zpVcduA1TcPzjQRZ^dFv{E0@N@&*aLbaqHty+0w3!xdO&TUOMAY=aPnL zE39#pPtZaoqjWZAT{F|DrM^$*kp5k$$Rj#bvQ&5YKqbXdl8Oir(f1J1l0qw(*;`OV zGN!mIp_X*U6!%T&Wax~UhE>SH8vW*%j_VQn6AH^v$>VB|DzvC)%75ss{$|6 z{^x|rxa;T~jvBKcn2RPxXUu+Jcz@B1*$hWZbs5uwh!)ila{oT%UMb5kI+)df0Fy7< zRW*bUszDq|o~C6Kt!BwzU}CN-w1RogY3b#n8Se(M58h8SV;23YFNkK$G+YhFPM`C{ zp=Co1@Q2I|g&2c%tmcU%AxEuCa*n~q2`5hcA{kB%gH|w0&z}VtD;jdGi?xNPGTl|B z_V>s^Nr!l`HpNn}7oiV>7pZhnW z8Mht+t+YR5_Fz5;Vj6D@?JfFl%+If9e_8PvGi?963a!MWTqceFq=~O{!zjjDF+&IdpMJAoY#++nbR)LMkTA z*B1+|U~X(bf^i$2@uE+F_6O07dogD73Y9TSjA_w1?!oma?dwG|=9q{NV$vBaN2H+l z&{T7aO5s(YVbH}^S--Mnvso=i6)P@Ig!o@M{4^f?ZqC^*zLy$pJn5)vOkHsI8pK!X(YX66T#x+&#b?|FW9CEU#**@UY{PD>GPS(>AT#Vj@~#x741 zrtNeJjBXM$3h&Pt_r4Qt_%`tw(<*IWE}HoUpv{}UBAW5C_hKpKM$wF!lPya{Gp071 z=C~y)`FM8?`kY4NxzunBy0{inf29KwbvHL*!)o$?fN)E;@4{m`?C3Cb)fSQ8B2}c+mGNCA_o%KbbYl5M~X zgT|@HFnpT3OB~i5rXoya>y>E&o0w1{b5*`asS`ipnT3BAEj3_cGnYF_~H= znlV3b^P;9PuYmMnZ)28d>q>=n+>GO;hciB6=5i~nE}g?jdeQ7J@kzsgdo)U650wIo z8vn=X?`p2?ELX3qgDY;jIXtf@MV~-BTOYxlqJ$M6;{98ApH^rE&xD@)Q4-_ULl~!l zPG=m#uNTenuwC?*X|-wGVsSe(=DkDyl-8JCgOA5L?kJd&hT~Q)m9E1mo22RfD4OhM zmx{0p_$q92?}Ot?f0(dSgC3lRX(XHy3Pmx_z{i^%rwL2iA>3^jx2$ z8I;Ef!|-D3(n?5W=!3~rTI55FEW0l{X3?0xp6eYoX&Dda#xHCXpD`75YAG*cD)NGh z3t#bf`lQ;Q>yC5J6`%1;*tg#EMKcaLPn}4kef1Z+#?B8p+wviPAD`ws*~Gk4ma`o? zW9OSR%SV|PevlM3CSp~eXqGGVBjm$LMvg3--PxAV5mNVip2|)TBnFw*oBIm0U}(`j zwW^E7UPmsBm8!FirAt!{^siuUKxfRC=wCuz(;0IlvVE;+ z4$HEge4A*-T(!w)dVX2Gb;FV-?LVrwZc2Y3Ui&lB&Nawr)KfAE{J&%j@(<_u*)4h? z=k}$u5+_1jg%FG%E;MSOXc2ycR{UwHJnuF(e;Htng1yA$an$x{g^#ueIP6W( z-hSMP2OYcS%{(7Ch{f`Ql@=Dvl`MbgWZVr|JbpIrzB0$p#| zR`1AHO1cG0EYd>bA}@PoUMM&errwZ06LXK{yVAJufmVs5Boz@9E$hkTxgj4K_h8bv zAwOkxYMim-Ek!cI@5zQw5?fPuHvFP;k)eCweJ?Who|1OKlxNgcQ?Q~T zUldWKJ)<-2>Ji?v(64@NS49*)C?au`NQE?nrdI*X_97TjCPG>yz+gU`$j+c#c zWO-EN%#?Bk0%Ptu{*!DG9>PAHgRebGGQo)uSYB=4OIR?MHXnV5_>2e9A8mfEXvQ&s zETeJb7)%BY=T}cUVl59}4@ajmD<$1qQ;yA#rKBJ+=$1*HZI@ARnPh*7aL73j=Niz8 zAE}&(Y(}4Nzeb~oa5g-fdv_-PyBwcfR8DCv-Q_v1{mfAWU}C@1X`rW15iQPf0mnHm zGG5uI_I<3hYe<55|S=A0DM8vnx-6WUHy?Yl77AKUc__4*;a@2E7s;7K2c z@x`haoiU$S@4a3$W2#=?g`ycNInttKgp9o@BL#wD*SAHYw0oy?w2ac=!e_oYN>UL4 zB03NB-xpfJ9Dn(qLE~AV**+R`T(#;3g*E0Ks_xc|oqn{SA=tP^voCXlGFdW)+*IEe zp>pjL&;^I`7(s!DYX7@qNT~Ui|JhT@K!V}^%ruur5(OAimFE6x%0ddg0)wZ@T1awUu8F{E;?jeFmM zfi?K)j2TD&(W04;9i6`tFy@UabH5}$W2aB5`S_8@{{KyU#v{AIIIR@Txb< z0_w{qG=5)BE>WU%Y+>W~*;_Pr`J{10)T0<;cmquinEWi5l_2T=Xk;Pn__+0^UoM zO4Qs39i-5Tf4o}uCDDw{U&c2v%UqE19L}nS8M`4h^jvMs?67~*rD(ZjvjznnzbA{P z2oMo!yL~jY;I5~0EMv^3x~kYX<0*ei8)xja8jUhfMsm%CDf?`eC8pH-=J;{1qNdf} zN4vJki4ZSU6Xb%qI5>QrGGokdF}xpQ95sBY_>7~rgSKutXYJ zm>RkmcfdYQ--tpytpP{ccDj*~Sg-Esu+$+n>SI5AnPsVC>AlB6B#r&|`6af(O5bg4epu=wPB`|c_%gQn zh7{;v4klo{ssq<33*MbL0?jK58oxm+{xhFKYq540 z%zo}AOoZu-9S0;F8jbhNnu96gbPdWjpO=d>AaPc@`G%b@&TPKH{z`|twVRJ&kIyiL z#`O}Emi=&Q;#KgOe)6ejtUc+B)yKW{q?6CUCwR>!zT4-Q&&M1M-{w$?g{q}h=&LRk zn?*y18hqZalqL8GFQjQTrEq1tQ6J8+67u-eC5sw=4wx+ z#l^x`zGDv2LRW^ND|&N<`A|o)}yQ0-8_vy7gn1@MR~-D5O<*uLqX6PcO8m8>_O3tyZ)Tt zei(CoWA63hGv=derWtc=%8e#EV~$fr^SPbn(N7{}KjuiT<(+%hZ=oBG-|A2^>6dHB=R>v$_XcLT2C@g;I9EJ;wvp*x6F$XBV z(XrCkhQ!(*jmBq^U3CE{HZ!5AKwpx`M_M?BoiXNapSm zHGb*%u_48=U(lGT8`F=&kl`WtG!Mz77on8KpmCqcsUbB^jN7U9GRyYw7{`@Is4_IIU&6hVrA>nI3(iD<^=XFDB^Z-PQySEfkwR0<3C zs#mU1h&0-L)ivc+i7iBzc*w`l6fRa`#)D{`K5S*oKA^7*my8uP!=m}1i)}Plr9Akb z8Lzir+>faXsQjU7iw6U}l> zN;3#;8G}Br$TGAvvs33v8Hy7jP*V$DD$?MSpKY^?g!rYiKc95pzA{J+V;~OCuEDjC!)~}{eMF26Q*id}F_kcEj>sK8_ z0@$BV1#F=z!5Q-q#UFnrnla~PTi+#`vE#*@A)XBg*^f%uAtk%It)ELBcss_WGdgzR z_Efy#Gv6GdDFQ@&p7(Opkb=4i&r_Q8wrI!DYHOn#}NFITs?6HZtPq=5i2J3=uP^rsZzuM zE>grVo&7_apz*!ZFjyyN+AE-?FgfG*L>#}Ls%XF=*(}kF9j~N} z4*6}JQda8^Z;=do6tyj7(QU@Yhcmf;*^AzvE~G?b=W>vjC5(?)2|X^h(3p~YTw_dW zd&}g>*l9^}^vsRssVVsp)GEvpt9zJXUn!R!Zf#3mj1FU)^I>yPZbyLMKWe)_Xa)16 zi1!VR2hai+oEbqI#@ti%xX3tib&B|mnJcDGXKb02LzvM<^X;8EtghocM)KHV=9FaD(xlD4A*hBtBz)L(~O+I%DpmnP$vf^}IoR#>^Gdr!!^_MWbbi zj^nhYVfDaR8TiLQ_7a4EzS^7`@AI=9LL0~M z@5d6ySW%M}FQgs_&^$fmp+UU@CMsS%hMkc+9`jDfF!b0?SMGvehGfAr3;=Ev%+L!C zrASyv^zTO{957EbV?L@622x zW0A`+pzU0qAbIESH6fSXl2rU9mrp7+=5qcbhZ0}p68`;DG1e$UQ(+7(??ERqrm(`w zg*pjiGGL%rpwwwvjsA}CyPb`irGms~z7TI7=HGM7P%T!yWFcjl6Y z`3f86b}mnnyz@@pRWA9OHS0w)c%?G$0*9gm=}(QEHCZ%cYNWq@GNwlQODExyGo;nd z<+aM?JPa;KV=g0IM*UuHrn9q5>{vDzTE4TXW*I2n7E+tMa9>ziiOMdtc zhAoT0(7i_Utjzl?4UAgVGsf$Xz5jvTj{mvSjAILE)0fP_h#dib??8r*3{o5O9nHB{ ziDt}qG<#9SbjAbcV=CA(O?dPr%%4IzG4v~#TS1$@EIwmy1#P-nG-GZHQBL&etNA2% z^Oql+sx6c3}TPtTjwU9s(_+#HPN-h=L65{Sl0{y2=CBruK1IJpw`J|u%KCz9(X z%~__(V0&k3;lo10w(H5KUsAcK+;@}W<1fQ1%=YciVS0COjGu5L?`N?Ma@Edgx}4@$ zD;YNN@STX~Fwu+$pN2LdeLCZVi|i9g0`{Chg7Gr@*mOBzfOF{ zi#`F`-l7?Ef!(*r8nY}|wsdXz9$*!Urm);DLVRy0E%8if;Qs$0K4YG{_sMSK!6))l zQDZK|uwLjKw(GnMYdmQsw%*D-#n|=7u(6s9S*3QQ@H5VX@Y_5m?EoxYe46>T>NC!+ zLOW|0pK-p;{)%)Y-n?&~n~}nV$8h+{+*3h;$F4*x&s*)m;O4|H%BwwaE_iPY1fFHH zg)`=%Invs@s*(BkrkohC#yU>*)zUsHu=-p_kyD%qagJ6b7_%`q za=bcWJcMuywvY=$;DT8vKEq+m`VoyMpkwTKUW$kY9H*M=`axtt+e!V1*Zxd;;t{_g zR86D#zKs8kXzW)*_)S?=)7buDiLc8Y7f37z=uFYQbDT z!XW;>G8{G@Se3(OW6t?~W214@AL^6NIO;NJ)f@3qr5C281Jrri@_ME5H7eDOTk=rO z?uuKy2*aM|fw`J7j_zR;DT958;jlIMs z1HF8I?sv9}j+_Vq^Y5<2n6G+mJ6<9h^GM{}&x>XpdzbGQ%~;8i76-%LdEkKuzTr)$ zKqBl8Y)@IKoal(^8$+zGw|1^^hQi#cqTPyLy6I;kIO@}WL5nEUud%BWVwP=iXR@JV zWjWT@(~*Rek=q73WfLp>Hz3Fur2xk9i*3*kg(SqY(qPfZ6+dxZ1o44B=OYd frk%?+{uB5kZR;Gvi??OfPXhAJ}@|_v+OYyv^wlZczM*Vj2tP^~cYNoYL$aq#8!Cq@mUb^`7m8+NL4P)c7^{1^|x7HZHa?zS~ zYnK|sM%5p=c;$xSM%_r$8flKKZ>UGL`2kgI+O(-{^=Zr6PFs2M+P38@S1-$W`Aser zu36P^axMqKlayfV@iXR3p3vIT+BR>(jPWyPgK>gl%x;=)O=_h=1J!6#TXV6sZF*C& zZDPwb7?|G>Dn`q=*-f*Lr+!<}&C}=4v>HY=QvyJyX8eSCEzR`kM4x2y>@z?h z<;~4a2)ua#dA-)oJ`S-ne`JHGSvz~(8O`ffw=P@VHlwYsF0=KKDLLZn)=N^&&{bk{ zCr)o}ZCjG@_Lx)zaNgQw>y|893YSJ034V!?c`uM^%?%lE+r4&KbY!s!fiyob%1~Q9 z`mJYf2?6z5s~QCPxvL~9%&c!)ymV<>oeG3ys#-sFdJsdV1{i`LHv#^cV=O@Z)1uZG zwDcoLR+|lZ^S+=G2Xv=h3ANSdAekQ?!Dvh(@nRW3=<+i|sRn*aTdu9Xp+ToDKix^N z8ggwWokL5%a$_9!j~)g4rEeM*B z3U`Dt0N?81uKB1@0l{ulD?+upv5?tzr>|uqM_w=@KpBg8SVOf45U3u7u9iR4ElWxJ zzf2%-$$Ty-ORyHhsOFYlYbUBvbWsQaMof9A`vs`TkbB9mp|A>3qZ^abpjQTFv~iH! z0RgEHX;^Onzz|k3G~ag>o0L*$hhXkRbx4br z>k|@~7^uaLWkic*8VX@=doq+Fn#+ISsPb5joflmxb7220!pGpClK*4Gfad(4eGvj~ z-j5ho8sjEe^(Kvc+elzg zb%-rAZFn~-vs=9F3aU5HB>mI zM@Z4CXJE`U<{D6kGRwO)=1iJDOtWdKHB7b`&j}6;ll4v$p1;y?k>_vAwAC!9VCU zpVmB+t^eJP>M@u3iB3c{B#)Wu6ap>w3pE$ktX@y06@b#~I7~+=wXE&#wo; z)LEmb}*4w=bzROXmBp9Dem zxv^->>KpN(t)z-;qSHWYic7hbW5$fqBhj(~1&tmfBdLu8)vDKQ^Ik*PaW?LD1sH86 zD~yWA;TA{nEjjD@EeJGdMQ7POYB3c*@D*Ga!4)IieBD*d_#m8@0kpCql2%hm`IOfQ zlz0r7xA+PeRX18rf0aw>nAU1XqH@l!T#c@TVANk-#f{okX+*cOYJCOQNd%-fA-&er zFpZ?nhXCLo^6=*V<|j&rwU-e|Sz~lA@@oJotLl1;m-$8z@o}D^Tl;qy zVVKeqDdfTLH-={65?U^kt>M1H^xYBFNjdFj!$>xlRKrsv^Fpb@8KF0XV4$w8l&Vq8 zW8Xyvne!&Mp!}*TuQW}oJZt?oBp;Q<%yMORw=bg#NgtxruwBiK+{o_+RS8{cq;n>j z;iqvLzC)10t(@+s`NlBCEgzlpwRV~tA6@bbf(ovhTQI5Sqr<%RR^hNPzsOI^qfc8S z(m2oF@(CkwflJ{&tw0!=3>z zWs5W#B@8D8A~IU{MDtQdkg;RqW3kmI!s2n-?ut;ps_L0n1qVwe36T12&)hw4Q4E5HHRX_ zEKZ2Z4Q8G8%^C?dqt?)%&rGy?&$+^hj<5{BBM8o8C4gt z!r`nrta-%v;WWTl7t3nS;p2zHI`YB(RsdCzayYbEH97G5L?xnSb#f$&>>f6r6(U!M zyc9xJ*(JmvGT~|mjL5iQ3f5IVaKX`47&K*?GVE7j%o+hk(+C}pJ+7+N9GE7RU<1Qo z9PMjXB+rV?QEZ*HtNW;l-YybibY-FS)XJG%ZEU9v{pHl`@ z4-wn7p|EA(?S6#_eTFF&!5nySg&IbH2C8_Acrq(Per-TwA7+L2DQnTtw&^}#2`|GZ zwnx>gJux2KuCUS?XJ*^C!V0bI0E}eRcZ`KW1zU9;S}$&nhh0NncC<*jb3qAXvu~JW zDcyjLfd*jJO_}pJ46Jd5lc=F9?6IXJ71)648uP+ftQ=|Gs2%fEk3uhqYRxdfk#^(E zN4#w}I#P?n`TtO4q*KFhb|phb^!YYWnMBlp9`XkRzyMX9oyZvCf>!EO-eP}Mm?QTo zH->VmUX%cs%^ETWQ~`qH79E5h8UqklX6iX zlu;6Q=z+UC$=0Pmm#1*!emlvQZY&dG#yjhSa*Potsmlpx$QMSURy2Nv&B*NhzMEo4 z@lak%X!sP4`Z2O`Xi+0Ln%4KYB-yT{As&Y+V2tZFIr}Qtj*_JVsWYLv%eJv$(j>8l z-9>z@Fw0o!SIJ5*s8k$v!&z0Psx0XF0CTF!9E`1ZD|JS4<&vEc~C9<#f^!ANEmblWZ-ZO?$k z=){0ent031Di}$$Ufsmo>JvL|_V~7y5XpaF$0SeM-Yb(l)B4zrxi~e=tBFDC@*4Bg zGM6Xge}QbInfD3)62v4=v2S)Y$!0$ZHATH2#uOSge{N_VE&43xvB~b3g3kP>v7~B0 z=CS!TiZ^fCOlbVn&%iP~%x&V6seC)gnz3^x%%0vdqiGuAG#Knm4W9kBj&H&9U^HvC zhk(wUJ7aF^1U@mo$f3l%=H|Aw%Qk?%&;Z>_)j$Jz+a+7b=uy^#K?1@BcfGqQ~0LPe3!;EZ&1LF9fEVZ=N<4_Rn-98IVXmZu3HBiyg_pDKvkd z6Ul&#p2v-#1g&N@^#CrP^Aiv)nwXTS=S9@EdxEk||3l<5E9wO5(sCF4h-k|mej z^G|L}^43;gKPKU&HOP%g7-jA1#3X#M_6cJWE?9;UleG9LSCPvWEj_d1PW$0@8AlgW z&sm=cD>07VtwxMN`6M@{uv&o;yb%B*HlcL_l5U>uC~Ew|(fQno!$xCL%U^2%dT}qKUTjDF9P8g*rlfxU@Id&Gj^?Bp zkqi+|ZMTv^b7|6 z*#LA6M^4+4wqmA&D+|U7EY3;)bgm}dVGj(>WtRfiMlr~)CL?c84HYmB>#o>GRquN~5TU6PuqL5C$HD2l8p0A3 zP7B}jV}L7HI3*q8#E=A}!-xSS%R17INwpjZx0s{*8|JS<%~Go%O!Xk5#;*c7r5xo} zg1onxUlvw^d_Vk&R>Y>lYArMTJQ+Z5zo&>VbSTKH$ zCZj$*I6oeE#KHL`^2@^8cvZ7Z3PUxN*esL{q-AZAJP7jn>UyDf~^Afp_894M#> z_i=dWILwGh8qDr8+(`hOq&I?w2jiNCA*q}x?lP1FvYgXOH`p3diC10yv>4-v%nuP# zBEy!|bq&_&sZjBR=0Ha&5rBue1Cvz{?)<(+LV{g2e<%R>FLhME2@(KD)^H;Mu*%>t z2_VR(=SK)n6%Ml#Y;r#~BEaNnmw9@`UpN+CS-ZJ06T!3kL`(#iN0I30&R8Ro)}Ccy zj=v+rxGvhU2AAu?5o=E)=CZ3E6via;{G29HbK5WM$)A1Ebt~j~H;?)Kp7@DUAkQ*=?yzh^5wl>NTDp+hu%4n_5tEt)n4o@-@Nf@&*tLnQ1cL zT$*BywqvNJ4J&>04fk8iqIF|9*T1L%JULTKw&xSDiY+tR#?5VQ89yKA_6u@=me1n4 z=v6+7HO0BJ+gfI{&O!YvNL#bOTIZtJ3oJB0pJlCNM$>d2Ccf-?n22Ay@00uLv~6lNjSP887@Y zf91ylOSn)qe|WiuKJFgr#xjI>gj8Ly-}Jd~Cx4_}!RGPO^eZ49F-IB|5MrEXkBp3? zUbb#kLI_ZPbS17-Po(HE~pqaw{OtpRbjnCF&yY&rU3}gl?H{fsQO% zq7IW+CjsX76*nP4TYeuT0H);^b^_oaxjIY$wBxffkW5PXDb#L8Tq7w^e!|?#=}};` zo+7MWd)5#?2)6csf*v|XJjqyw-J?LXiUqxRu+yVJw1x-*!+RDmwUOq#c8?m&_))iY zLZ~IwInB1)oCGc7#r$?aOuu&0GQN#5zs9Hnkr``{T?MMefhPw<)zOy+aciLw(>x8a z+T55{M`s?)tP`t19to}aex)Q2qt*#_C8&hQY6sRY$= zbE#bkssrF{WpIo>-8j*R1$owFwFNQFv#@P9y9qivkGZvs>2oVcqy^Bj4b=++Qm^R#)*(`U9~fxy;BmU8~06lR;- ze3bW^);b%t?__xocF2|)EpyuDsXL%Y0;}kyJaAiirwZj=AIr9@Q68-(0<6$57BiML z&aFl<|60vPHOiCxqn&D$qoT>JMwMkoHHyj3I;L873|l+au9n3tXC3QQqntmlPsu{G zA*>P|LvtIPYLpHS2Urn?F$~VWVHL_V3+v#NEKIPDaH?d-(6wPkHOk<~t(nB+!dH#V z?}pW~5IroVfKfQWt`g;mxwUt->}bY(ND5^b2B%OuyeHIFgn{ectv$nPl!vHprwZj7 zRjU`k3Js&6*Zi(gh0=r_oNAD9%m&pc)z$#4RLe~Cu9h9eF!Z*oWzm}XRSJb`=2sA{ z)Qgar|8lEQ=I7r*HOesj!>&fzA+N4RsrDnMO0J^L`IMj4wA?P?TRGrOEBl@P00sR zC|mosQzgsBo-wLHqQ3~LQM&e03T1F!G^%A8oS)g%C{6fj3T4oPuv(TOdn$!83{Uvg zvP|YSqZ(y!9&xKswbc0gb~Q>b9uBHedeNCeVQ;?VSIaiAxrf|p7;fZG2vR64&M!4m zFjX%OQ!uQ{uXa-~%*!tZTG1!)!Vuu)Mhd1S%bgUAoa9%gVRV7K zl7jiBRKC@(R>F5=^2Y}$m|iZhQ!u?e-bulGSw9L&p*svPq%a8f7K?+vh z0IgEZ0FFt+2)B7x8iw#FKc#~{j&@Tp?HgmHU?#XO1#^)^-mLxZ1! zl{an*rte1qt@NFbcJjF(1v59Mn}X?1E)ByS^Ug3O4dFpS6{_AS&JVV$VP0_N5AmyE zUJK+8x2s`Z4CIdrQZRi#(oeyR>qwv#zMFg_Jby%xg4qE_xG9+7J`!k^5@leRf*HVr zQqsIA$RFgSq}d-1cT+HuW8P(_Um@V!Luu^z5N7;}xOegnss-^i}aDH%*g6aF-ZVIOF z`=zDnTn7;4oreKcLo5O0D zEq;;`u4jv1riI~+=|M%6eGvXUs7BS9+80g=W}yBKv{DD(7|(xZq+mMJ9i(8I-3_!# z2|Mveb_!;oK66trGx=wy8dm2=e>74s4gAzk!E`5eX=v6l?;k_B(m-``_CT_+ z6wECADNMnP$sdChOy@uJQ!uxMG<^@llr+70 z%TK|K>$`3WW=MV?reHexyEII9eix*q;k#8ds$q4u^0HkG^PTAY%RvfO1_G^2r8#*_)ob4;~P>Q%c^3d$w`NoJIt@z}5ugSA#ml^na!We&hTh+7mh^F0?p zxqEQnscbd3%xshOz4^Ngh-_(@Id1MmXxPFE{SbDV8=@SW%h7pR0OUMAXaLb^2)ktt zSoymhP|L}}_GxqY^nRPI`E2$c5Se{jxFX=TP!-2bhtSUnKi>lM2t!b~HrPk81|3{4 z8MxdbFtHUoRe?R!h^SF`c((|ZQ(focI=4`b~kdo%SJ|itn*Z<|Dq}3a;^XxRvgW%hM#d(Af z(*|_p-!dvNicLyFQKUIij_UzulHc?zR4{1oS3+#)on-B{l^l(~cPc8<(?3>LR7V)M zLQ1`t`XQi%Cp_Z3Z&yGx_>D>_6`Qw%3Nen_{5y6frknzlXhGd$d9zB6ZM{F^i48v07;6R6v~I_XsN>OdF%s zP1XJVN*sY*WoSs=g;;0Dv^tC7s)YQ`fd;lx%a=En;sw)!y^FPvCi#?-?x!DB*KaFDqAB< z)Eft*Vp=ce8e4&|NBuM`*Wr*oI;L5Nv)<)KS%P!UkKHm2JIu@NGEFOPOwg?VOoB#> zR@N=cbBbN6X<57c^Dq-RirGvp!^bu#o#(X7{)XS+g|SY!Q~O3kdOwMRmVrpoCPfMXfV5sb&H- zq!tAgm>MT5!wO6dlT(}uOpTJQuEz8rF)1Z2s{X!=w6aHa_nZ7O87wcMxDtV!X;-0=V0F;I2`X!fDj+Rk9-6vmJq8DSEt73>_W7|!RmWaFkV+Np2qI23o1V-;V)~oY{X1|Pb?^mnYE(7YVMXT8@BiMJf zo_8>;34Q`pFF=krDiFwFsQqF3{T znX_BQ^U6U!Ri9$x7Og#nD|pQ(4Uh*kQ}c~3Ih>q8+~Q~gJ;#)>N){HBa{ZNg zgRS|r<1SZGX1Qab!|>Lpd7od!0T$X-7?#0vivLjnd{8sPI?$(xvXbw~=D)PdG}T_^ zfW5Ri;~m{E!Qt_0CkX1A?3+7;WtyityBcMhE$s+W%hQ$a1kI?tZO42z{B9VNH2F19 zQEgWKjUAJmOa4&iGG?!rNoxMB5evf*D-(bmFisYNUq;q-SRrmc(x2r4T#^o%I~))-P2=ON z0sEd^g&{Za+gcbBACqsHQJgy`U!J1#FB)L%(4;I0P#oMu-=20T;B7 zF2Y_r)(I$49mbu~S3W5*eH*MbRB}~_QlH$WF*&{^Vg4)tIUu)b8GazIA=x{(Y5B6{ zAg$v;Wopb^WMN``sI^eBtca5s{nm*#D_Po%@~dgq@c}vX7bfQ8*DkG-9O7oVO8k0{ zc^g@MVbF3KWL_SC+>;SlXQNc37|UU4A5cP$25J5{(ByI)8uCZG5xHzRg&Q=vXbk3G z^EY6sHkMM@+BE=4&C8ZA0(YAWa#xUx7JaDK9* z$)(V2KIjX%WXTdv6W5X3E4K;F(&l>u;V#Q9XJ%d^7iKJl>(Jca7IMjQm8b`NkgSUz zxWin{T|zTPl8d@amXn*G5@=Gj+hqv3SZOvt0>v({WYH4(`$oitjktWZMg`zf)u<&H zn^v7B7cHTYmqfyg>(o0p1APdi`z*!}+<)32QFrn3#dI(quHP zhL8;n_0;@`4HE6*ts#)s{=RVWB00%=10>>Hj~|3Tc7ip*KeUMZoF8m{ixX=a7+dwH*FbhWZ*Q5$;ey1SfVyj7Ti!rH&)gCsuND4e)*nen% zq*XcfhVrce$bQ3y4r}6;FXp8_xx<=_VdIQp&Bie9jWQHP^|#3wij7W&lA!Fpu9n5# zCqttuN_;4`K0yH+!%*(W2IK~)Ezd~jk99z!4enfqePTo(1v`Le`o;{^4)Lo4;Jr02 zO1o`fR05M=sRFGmFeM0(OH{Ag*ayVOf%9DH;5QF{2Yo#1iO_s)9YmNY_Ll8Czw9`K}8A#1TfZ%}96I`y+$0 zf@&ktQ0#q~N2_}K6}7~ZvS(1G-p2xCdDPTW)GDD{-f7t0#89Q#nY*|K&~90m!+ zaZl4>j@-9KISHwryb-l%QaZ!2MpB+pq&4D>WF;bC^0*)=E4Wlh#6wp`&@4MCuXHCe zqM~)50g+zV8Hh1r_U`-?%$AaQN2^422hoz3IN)?%phGnMc zQ!)7=P-s(i)Yw;HAj|6GE7mY=C{;;(@?Q!oss)py5V2a;K($_4qjE>78^k)j1uu7f z=@|XMimZ@vACC+%2Wm56EK*^S(rx-+N}Fn)p~K&IfJu85a|vy%B~QE-9?W2!`!z0I zBJP=rd0(h2aSmdt%X0yh4omQp)33NVRIBC;qq{RFjsz(qvYdfgexgO)2RPSg4N7%> zU{E0z4cAnZ%ukYXXtq2R()DZnu7wlWIC(lXLCLDrk%$ z&;vt_CN(0;-OGH_FV|6mIu(_H)NPpmHp=o8QL5CS)p6oviV5dryHZe3<}xBxH=FB6 zB9a1?D2@nJH`U1lyI{r8)7;0ka@356i)OwNLanNb%qE;yX8ki!Q_lj7-7FWC*o8%- zvQ`<{;>Qd%Txr}FfJ9j9*MphdM*?vBi0Mp$uGVozH|yca(m}BAaVe`p&6$c&9|+6x zqgf$~EZDrPiV6$kLKq<@XyimYLQZmYtzfrJ{g0zsFK)MHoxDoz751w23i}#pBm}>( zd*~I0IPxN=SJ<)3D;&@*Z#jB}T|o^l;r&g6k_Wh6VgH=Gx#$)87rnv`kX+!Bx3}XJ z_Vhh-aX@N7JNN+>e<*6dz$@%r!VM^gyd5EF*q*se@rD{+VPFyUZ1Q%;zoG4(y1@kP zE_l$g)Fm(L<6jQ-GNg90!LJ47klGpl1{kQPc!R*(1(K^3Z&$}F)IxGyK*`+FV`#VQ3R!UyO+Rkm&Y&gCI=o`UuCe~-d%`Ww`ZP`A+=8@{=tVeA*n;b+ZXj# z`=ko^cL*d`D9OWYuP_plD-Fdfc?EWojY_f}^$vC9^JKumI|h>LmE-2*kmH0mLt0H&y_7=yuuW=&43HWzhmu!6E6&93$ zlw=nX;Eq=~-jE$eyu!o)|B9Y@cF1}~@UW?$d8SXQ5PF62?Xnk$SD4{@g(kFcmXd5N zg6c-SfRdAPsN02lHmSLgZ0^K{SPrT22Kc`0s0AN7y}~#LIu&nTH*7%*=c;Sg3RZty+l6&lgPg&9iPKK`NJ7Ms*6@S1ADGf1t#zY|^A;Lj^84!pt|8&AN4OigdD zj^S;MQJ0*2p;uT`@(Sxw?Fv`1E)B^#X3vu*d4+{&dp&eq?kJ5ATo~YCv7#1(w+OOV zgygLRwFH)2nIW~z@d|C7@+Bj$aB{m>ILVR6Og1bQrc8hFu@9fi*B}V@AGxgwUbhiO_PjYW#EqPIaN4qBfSi!fB{?b%yoU zg0~vH>lKA-@WNWQ5RkVngd}*^h?x@G&7+R$12a&q6yP;Rhk{F8{Hv9{Ne~|&R5#8) z4e}O*h@pW7oJ4}=op9XWprD9=+H%L&E1Z`@&^qOou2;CQ-7B00D{oN^TxNKMGm5g^ z2_(_Lw@SD@?XrO_sCTg|n;vs<`qnV@b~ zS~dq>;Zhs*6m?}cBx_|^5ZZ!td#Bvy_6ipjfrQxfOX?!6I zE{F8lpgL6R=Q}`3XisT5#{iElWT^A<&?{^%%9s1R!WBhW=R>EecV?|uIKK-%_>^q7 z5jRlx1*9(Mgfv=zP*LZ!!=4$|+d zwcy>Wcw4)@!u_4H_{1xCj#qdPS{`y(@6JyAv*qJU&>4D#duwH3idVP`Iv;2UFQDYL zMX&IkZs-h2-G>&g%gL>MP>xslF0|ZdlXt%jEiSaUq_(ue z?=eMP@1Q*wRG=i$-ghbKlDY%D8`?pIq;AB&d%N)|MOE*{5J(BU40%5O-Bgs%8i4}O z2k%EVdAHL}`0yhod3WFy?uO(OA$c9O_}7hkO0vU+G%R~UQTL$U9bNM2Mz8P!r0)Um zrw;4=5WL4wFHn*X1zzDt;60?TKTAx zSLlS!ZGr3=i1r})IJErOrR4Jlq8rK+dem{f!qcet6Q%R{cC?<89cY1r_pmEp5cCR9 zbb5tnLH#PAmWPVqb<39;f!Bg><5QQag-+iqJc9Oq;ZX8X13ox-$JQqGgU~BH2gzS4 z>S5ITe+DR3?@92UrOuF&k2v79gQuvcyWx9D_QCTCPoeeiL(7Y*-uF9!1hTV>R|rt= zQPlf|;ssr3uTwr^<`sSn$se|?+@Qb2+vdSxbV0(oZbF#CIS9sI+3a_}bM-8L` zukc>2JVNpczoeFuJR|Z7FV&(RTTqsL2%WzU<@@~wH{2?RH#GtPmZTeVgt$1$) zhz;s}sC0e^Ew8oX9=xJnhn82mWlc6L?u3?-#}9Cp58%h1wJ#3fua~?+mw|5u*)*jK zN?r(Mt7Dh~-kUkuiO4IwjOJc0%6@!a;Ws}1f%mbh_fHqi)yjslUg49_EBphJe|D(z zzg=G8GfD=e{ttFcbLFd;#bT(!>;YS9mW)<(hsQ32}lH?Wsj(`6L>gx=tf1$m9)`C)!pZQ*6 z4X*t91myj@=oS8gE5AOjq5@D|c;?}g`p8D~GuX-3CiT}Y)N7YdCBhrD{xP)lRg#}V z%O@php=9GAA6WsfzeB1v^cn}Fg#iYs{W`tIopSOKNv|<$c#Zu#*vc!8={i+bSg>X6!@1f4c?s(QP30fCl5 zis~Jpo{M@0B?mxfZAm_^={4?JggrS>K6!m>Q7;7Ls1{tWaUbyZQT291y}r=0Pe|T= zw%53efi(;^seTSL1@etaudz3D9+1HTa-Y0?e8i^HQ#&RjmNuljWPeFS&_D!>_|{>D zl7n*4*)Cr`M66-UUM2bRtJkP?YbtdX1I=y&3sTD|7~46d9tGY+rDcrmHP)ft1fe>;#<7Mh^zj-GHee6xH7nlmF4XOUq|4T=c1X74MIM{f zuv)M2AR7-8LsBDbP@VEgYG{FEz9gSGL|Y};;>(ukknDtyXnnG(cenvfu6!F4HoEXQ zCm%os)s0v~=PcD;eG!^M*@Dk&Y{+?y^?`h|5q?8*6tuJ&v}Ix^_&#*1dgGzfHt@Uf$)S8h7bWnI$;oGTy~YWS*Er3Q)l{ImAl)rn*m{lQie6(= z32#e<)Y*vkCZPpB-}4&h8sI_aJF2|`v`lq9^;Kcm(T-M7PaP;5r$J}2h;{rf>owuu zF}|lhn(Q^UpoMV(7SJo+v9(^~92;-zsTO8~n%;>;=!$nVBxj?A_Z?~}biqfo@L@=* z*~h<}m;X#rliCp*X!%4@#lUMk7WFMA&Pb zSHi!HtPu7ZOVF7Q@j|_7@3_EgJO#X?#9ZH^zdh1K_jbUi1g-%e#fV|^Doro3| zD#@iGOabpCm%J5@*SN@$Etb8;1zq5U*nuQeJW$7XXYi}ZG|N3l61?vyAns}!nO?kA ziEev>TY~}_JM{kdd81h1JxTtp$$;bcAekNVsC6qPc)wChp6K=<*?(bp46pYgxoa$W zg585;zhhrqeuzjO;PNk9Z|g~C-;<9xdb&vVFKWq?deYfv*cXFd5y`!sNYY$v^w4_m z;cvE06UhPXT5^fggJiEm_ntpVB=-xnpL&=`?%-<4CBF8^TpDPd{U`jP^sY!| zeJ#1X+=aSRgM6y1%^9%y`;oiHd&1|eU6a?&;PL_zB7HaH3RU&qJ zps^#mSz^>r4PzTOW^{gPHs=;vl;FL4{-xvwy9dck%{hnPL~{xzB9apWEqQKFlKn=%Jmy)EEIL{egDP!j-=+~~cZy^o)RLRs z9whtZ9_{m%NY3!JHb zA~~;{e<^v6--Be|)lVMtwMe#>wB)&N50ZV3{N+KHiKIGsDV=Bcq_g*u%w7XUa&p}I z`9=>qdo8y|ULcb5T>hnn=j#R7hKUewON9M>0zED@U)@-O8sa9JY86E4AApCw|`1OBDlMIlSX=6CWhu?t<6 zh^en%D$ETP1Z+-`CCY7yvAH>oUC07{e1^ooO3r49*s8Lep&(!@RG|iJ^HMw0mxDaS z(;pvCUoLg=kS0Lk+d+g}hQd{0Z@yp8FS)nfeh&5Y_Byuc=g56=0t(3M|Mx(iDlz?D z|G(mnz#{0q$|3cUfu}sU$8niU>MyoDRRTd?JD)0{h}ddng%u?#6cE)=z@x7s)oM&B zF02Ihk)biAzOc+;6B=_-P>-(A5V2k$&8v(|pK8Z1Wd!K&B}VM;w7Vu{QKygBvB`~| zn`;yMe-58crB7_2|DPQ^lybGdAEU{Wy0pI^m*n}Et0X@TJv{$HG3oE}P7ewN)c&qh zYBeVQt_Z#U9}`j?QT*Lt1B(>mVIz3zAzS~CLlni|Z`+xEk-wL?%&!ACS-8YU#(kX9 zUlHKHXYJVY{HXr>p>|)dh<$F&Mrodz%J>spAiiY(LRS zPw9sDMFDlvPH*@6f9h*Ysp11ksM8o?$VsF<%ofIMAgF&tT@dP-C0Zn|Ty1yL!}L2L zT)oCf4AbkJ*yknB&03Di{k@LWMwQRm{_XMvRQa48Xvh;#WoWh*@mP&+>!Pxk9SF&_ z?Iq<>CP&?~&oElX3*w4D<;j#4CzlDh&o9)-hN4sn|(PP;GKkF7S(PPI(V+)T#J1aGukkBgx)#~{--B>r?)d4@xP#YmxnJc{b{8~S3Y2Y#T<=`crQN#l z*twR*BwTWkkzI(X?uSSq_85d`zcTIyeeL`& zp>apAW4#`ZdS1!yQli<~rG9qOr7YZC+ARjg^9n88r6gb?OMAUH;WBZlpRJkV(y6|e z<%Iq}T)MWZ<9#>$rY!Az<*a{0<4!mzwpV9qH-~0xmoi4ur2*ibY|xlQmT2K_j(`c5 z>@TMrC@y6T%@mgwgkE-ls<8bmIh7sndi$GPn!2fV5t=JQg2p7WL<{#wyR_t-<zRa+VXh)c-%V$t>*&gU%?@n1o9g zwtLxLfq<%-Ob`1#T6chQ2|6@WT)NEgvU?KxA1-BLm$u@Fj4jZ(VaET;(jND2+8-Ks z!O=R5T+;n0+oxOBx~PuV|39GCW3sr(L432jgtGEQnU>wF$dxb90|#-wrp{WpR0b*p zOgNYsnR^hYswEE^HB;#r&{;aW!9t~r_Xm4W^L<0hR(zOcYY%#EEs9ZA}`Q^17N3l5x$>BIqZ*PLd? zPD8K8#A&zI%i?+gzwJ7Gi=RG4xs{o|IZT|Qcy@e>ve&4S4}-#8y^f1JBcFRkr)Ake z@asxfpN0&orI&0yaq6`N$s81c>NEu2$VxgE_J*_sm9VX@)FFufQjCSN-OCK5WXyYIc|8b#{ROiAA60Ld#6+ivo1Di2fT z$yS)~zg;R^GIcC8?&fuD$W*zMtqEnpnDp4)ZRxSfm~0lj_NY7RE?&5@8y1GNkQqTW z{K1LIE}!o*Px|QYwq}Y;-$JOeA+hbcbcb7+rQ3{ebm_rEIGOH_L8xaQbYC@fWP248 zhrIq@cO_lg!{8b?)J$fHiRe`nFyYei&z-VLxda`WDK1@v3VRsDw(HXO>`edY8ct0o zclubgh5?1ma=&SU$$c?&EmZH}b)3>(J;C&KWYwOeYftpK^{$>(clBirpCoTkH`nmd z#>A|8b-S1C>j;?e^k}DTiCT7=-Ba~FW>zMcO*u?DzOEqNyWJSg-Nd%*eMgYK-0R3N zLjhL#Iq|&G^zWLVLC>DJ3dlvS>MQnaZ@6Hg9Ahq+I9Q|Z zUIB`T0fObbakkY^ywi`eeV6@BJ$crGgMS1yd*QUeuO6IxhO%Z-vc0#TJT1r~_m@Z6 ziU;TA@PE&cW>pN%;}#4--Bs{oZ(lPdm*+beoJz}fb9sjm`*w$q6wf=&EyMy%k!2=;O{h*sTKX?$ik8azXa$R#jDBKt42S)Wc z9&XD*Tp7nXr1l!b@G6ICH(XhWE8};?=T;U7lu^dWjoo{wX96d7CYTxX>4vI34@9yE=&3y(OzuQhY{y^FB#uI9OiOPe$ zj)^0C*l%p{?$AR4* z?(tl&mkH`0Q3O$#Gruexr5XH7)Wu)5U>Z#mQ`6SHMmo>;J8<_QH{tF>cAV$4kD2{B zD({E;0bzBX5A|hnw79!JTD#NMdEUpB#nF=IebCb%XxE`I+qpQJHYLs&J;%!)>II-)nz#@g(@oS4-)@-Moa{K|@C9b}se6I_~d3?Gzi2Yr& zYT$#Yv%lAIPN~}8diZ-?E;25AkdeGKHxeFx7v77%2f@Sgjk*Inxx|~MB>cUv%gfgL z0&0IZmOQA{nD~1i;xaP!P5fO8e-Bc=l@oox?PU+_WL@R&eNH;j_l5BH0T`(sCeZN* z5P@hw?|p^!HYy*0Nvt+<9Fv&z>w`^v?Adud-=g7 z0kx}JT`y}9N~CscErz;sp`vr2IcM!~B^mu!_W7=MFT0k$8Lg^6PMzO1ty&uwhrK^)Y(v@jTKLQ70$G2r-$JZ>+ zoQ%qtxi586$%cN8RTNg8~91#D?$^ITH3{w@9&ktwP$^IccG{0{reEy*k`)vN@r1?-g z)ay7mQ=ROC!=%rL6q7#h58i_rWg>h&0KAI=-QA5^zFI+J6UkN)2nE#1W&{o?YD^-) z8E^lxoXf;ADhI@JfPmd%?3m;i<3R>hBIy< zsDI^T-wGuo4B{%;-#0SRd$!ok3$AW6xUClpHvYLNbOKR@haE(MtcODu)T6UZc^Ufs(+;VetzL{#dof|A3Wa*nAg`{dD79mhmp!~B zFU>q1k~g?hB!8x;0}#;beA#>oN$eKtDWzp-mwLTM?V09f59`MCZOcw+(24eLfGv+H zEmKhMUL@&pMHPL%Y?HyS26s!vcwWW80Rd$zD@+o=a<;~vG+>^>tWaZ*#aLZYW6J%) z^$s12u~63?+^Ml21sXd5B^o2U1xg!6x5l1uDR*nTmmS)ru^;(L949r89yy&L{pa6a zQ1WEJ3U|vXz z@?JnPZz}4O_hV}18s#R32Djwoy{0Qr*~>N>e6I;b867fn`(PA01yo89BiuMSv$(@& za`Jvmt!65n1s~3|mUg%!}a>t!1hre=f3%h%qI2XOOFKe|4B0tJO^_xg0f=lK_* z@=zT3x}y*8dtFQAo%ZerWbJ#js9%?7mQDz;_PKS9Nm$}tlcRcd;^Df!d1hwOxaA=&bF>!or zHwHp1=Ypx;namb*lv9rXJWTiN9~*G|XLiEzpOqbVu3!HdDv$6wHtNYL?$?u`|3L&y zS(!Z=?mS(qottRz4NSJ1aPE1-%T6MudZIY@nCqdc#^QcGeb1q1E6M1;ihjLmgZ))C z(*=N+LfgIUM1wr#?oZ0@KI6mgpTbKP@(5}E*0A!dWYPE|rlR8EUdI(W$CzV&4#>;S zfbNG~gvlT^7Syw##PNbHdoaA#FXPoN#Ti3D$ zO{`A_`|0~o$Tw7>l$dhqh3(xH{6+9hcLk3=;-DL$<_NE2MG$pjJ&9)XfxP)DcLm3W z$-9Cx!CQ|R>k3qcAK*Qr>`|GOuJ>%M2NmEe2g`Q_$A%iibdDV2xO>dB>2Dsh!w%=jC4p+qozD(l>g4)^)pVh3X@5;n800{b*a>?G^7Qbjo|iFd6=~_(|_4 zBNoruV8EOBp6H{7mmM8}`kv?uB^*>cMKEzx%DleQ_2PYtubJZg4?-_HIUu%O?_VrG zfqKD3cYe{}M;B1o?t!-HiT(#d<4BxocUC(+qa-gai<_h2G?V;NNT+8Omj4?XkHTb~?&omq$x@W0?9s^W=AyD5PETx4X4=m1-E5kcaQf+P^z+z< zaz8)X7r{gz7L3^SdCBy|cFh#0pDKD;o6z>1eyMx{t)6SVPM3fQmrkxd#Sxd9;uwfaXCf}m zE-P#|kI(gRdi+a+He%?$^eE8)7RmYABTpYzk_R9!*jZx=F-Zr-*`tr?e8;1Ogcr4iN8O~!4Fqs;_q9o zmz{2Cj7)4$(8Y#`DSv<4!#P!#3xB(u#Hqz^GO^<)ZJf?T*P+LDm**xqWnN&*om+AI z)bsqX!{Fl*Lxl7+_KYA4w1FrqbV7t ztI%92(9f7p36hIg=7RT&BF#w5P46Qg)0N${7fR%Kd&GgGI%I*sDppX=+~m-iElBh! zfyS;t0XrceB6A6Ce;~iyL!z%{$9@^!$9KLGYl|BeEZhKv4Y)SaBO2!&lIW9i$#cm0 zNbS?Lx`!{aWwE%6%3ih&yccsQiqDd0o>86@fjZGVqnuwWg8FoM9TY6GH5Mm&>UCr0 z5!AnOqCc?NB5{@I-}G>SbR~V}J?5dIoYR7-cL277Bspqa7 z*%LyIxhSX|MbHp2coAvoc4Diyg1F# zqxSeNZUw^T5~KD$*t)1wKo7F#$!{5Pdiz{9=KoN644yjTK&x(C#&h*5B<=U1c6YTe z`MJhu9btv9K+E)7-Q;G|2x0jvOtuaaO zq71r597Y#REc0u}P%lzWIsQhFPH#`$xpnhchIy>l@vUODzf0inZxJWy&a)laqb2gU zR`zHSe_P>i7-)Y_LS%j#(v*b1zwPp}OCnJF`>O3_XFDROyYufH_*<(n@%P=Fmu;=` zm&dh}e99?*Uw6~~zJXDzhVSo@@#t7Q;JGQEqfXxII4?DPSLdRaRUm-5!Id3`#NQK< z!}l2rm%Q0s$;XbZHg};xrKGxf501q8^?>*D=_HuFDE) ztD9`AO-%Xwrkn2AYWTi`4jOmt#5gYgXyC`Fd^8;IiV}_J$T*(UE*s}aq8EZ{>(t3y zY;YSLwwp-i?~u$n?E-4&mN^*5F@~toAKboLu<1Yw>R;rgFy{pM(=>yBiMsfUy?Sgf zyVyWc-2I)Mc2})>ddE(^;ucn2UnilPNpD zo0#h0AM`MRy-&w^eEKkq2lUj%tM5jg0w%Dqx?dmf$i`0M@4TXH?Bqfmhevq-On_q2 zr`HS|JsbhGPw#cZ{-VaRJ;rw$?#iTUn0k3ma@Uq2&Mpdn53&jzdiRbt^CR-}Are zQom^Ia20A}vVO>qJdbZ_IbHI+L~iOVh38(EKDl1zC$E7|cDQ(gW~d%4y|AMewsi@p zZ|Zyxek~0&7N25|9@luSTo*6%HS-D-)YgI7lO1B)y)F*z_?DKsmvbkaRtr`?w7==@ z&YS_mXF+w7*YRzAc#gea+|Jc5+TZ0a`~~$=2&=Md5g9yvH86c|+<(~aWiO1KiSvAJX7Fv2 z=Z&3GBZ{b698fYeCf>h}NUyVrZP)uh_HY8Ku9-g!67zTBn)%Qz7N3@nvm-iBK4F^8h~tg3T|y6mYX0rl*5QIU!?rc`me zI;hha#)`~%hrGUa6G8nePikEV=7w70YLLI%!@>Gp7n9nb?1axBW#T!!&T2RWmB)J> zTix;)7oSV*vOk{qe1R+b*Q0Zx~n8f!Y(i z4qs2{ocCRoS~&emt?u0C+R3Txf^I%yV#A5sdH-~g#@NlcJJ-B&Xs2}Nb8V>+O$mjq z-H1UqvF&!m4Qht?z)+-%{+9(zp~H&2)yhTg^SNU zOi{|`kNiZQ6FwJC8n7AFCwm$+38?e@rjKchP?gVXx-}O2yvxRhuaso;U+gotz098D5LQ0_$w}w=lK|uIQ#;}F z#~8rTb>q(O%yoae%PV;DjGi+$!6rr9%91?BVSe){}cT{rS7B5}F6&-kfLP&U=;xZQ}- ztMik^42}gH+SN61^&U{tr8kvik5rkq*VM{|r3+PsX*E#Vt^=fJM?AUyzg`4|A z6SZvjF!c8@ox*?Opkp$Hf3xEedRkZSanLi}>+t;Q6uL0B+*?l#W!GR8>Fl~r-l&8+ zmu{U2m%r-N7rtk^+}IXclPP51b(PKK@%m~f=BP+e_uUU6x2{tvN9wt6E}GDoi-Ouc zH+wdVlET0BFdaX_sp%hfVwfhDogVac>-nfW!|S*@H8pMM#=wk+>FJK_%qxy>ZkN3v z*tC~DE606$QB1nJF2sF;A|m!tks_AZyUwcXT2QjCU5}1t zS6$b2qppe#$KEyeu4C^S>)QRl-#PQmoJ`2Q{(pHMxS98~@BP|2b7nGQ;j2!S_Gb=r z6&O+lcBI9a>`G?lbaPyVa7p#6^-%pj5m5aOb`B<-?U&8} zAKK(Z@%(h$olhv~*UpXrIdWM=^(1(dbajW+aFVZ{sf+_0UFM0*w|RWkiBpO_p`<`2 zPHuWcNKz3ew?B!hp)u+?=rHqHfrelV5U}6C_cD(#$@iyNM*7KVFC%69ChtP)9dOoX z2h2%54ly{Ht91m*^=%Dy_A|t z`#Sh5AG?i#2$Qz_Wj(2Qeb~Gu)$+mwbP;+Pmc2X~OU$(Rz_6{;L$FCFQXfm(3e^1fz%K^W9JBi}eJPY%^^Nkl))P;q6Y$AUi9N|3Nvj4b8N2@`e zj-D{-=v*ibN5PH%e?!^Nkmnws$_nU(YCb5BL|Pr)C)-`%s-wH*(K$J!J0G|D%cF}e z(Rhx>H~z0d&7Xa~@&BT-dKCQavd=RddK7#DAMM8f{cHgO3e<1>KhJ0EE)(KquJMTs zV{1d~+|Y=UK0T+t@o!;0Nlmsbgk!ApxId8&`*Rq(z-8I5o)+Z*asf{-|fZ zAkoq}5l&>goik`(v|cQV=hP&>3sdUsNF{@FE&XQrOA0F8sW7@At1DDcy^vK#rKo~Le^nS@jcTNjlyM&3gs&tFc4vqZ-bra zq<+ELk}wnWM8MFb}>E-8zL>&~$m)f9Hs;3NQ z*LW)4APh=0<#CAOh26rRek`&UpQM$hrU3yB&|lyWv!#5ck$WWyMQ*YfE0;;jcK4NXz$j1kt%6 z%B~H)bu4W0r!vW;X@Hmw3P9FCDUF}Hco3M6~T!`=K1BcNZK8X6*hLXI79zSk!%$4^I`0>@`2ZO{Su*= z4CLe0E4|mP@oXs!Sw=R?{K*!L=jR9{3|dpBJZb3Ib+TsgpKQQ(?!DyrF7ZMKfP6Cw zhNd!U=f*#{1U+Hx7O$br9-??1n>S>+k*(k7F*1cULz-iAlufT*q2V+Wu7GJavK7cI z|5e6s=~9e^EH}y@cmsj_sbV>0%rPqe2BlQ!;JbX|OXDb;V964Z5dRT9-gg|N+@6sw zci4Zc3(;mzQM|#41#aU=M`t+>wj`FyiD&upl`=s-+AmGNy5y+pAYUXyh$9`$TCDrau4OP4-R#9!%b~$>@T-gI{_7cU*({ZW= zP`xL`Zad6XyH<+o?vSxNLcu{}k-Wd3YwYAhWqG95*vTiL!UG_WT!;6rTw{Y0W0HR6h=KsI5c45$<{Dps9%JDe8zdQ9>u|kWUB=`Z zJDYT&43DvOuJi-?ac!6T2^8Q@f1@?_6%gPtk1@H%rq?n-7mUd@Hocq)8c`UQnmz2A zm}u#ZsBgxWXG=dTOy$c*HCSl0wUi%DrpOr zk9Nks*}!vzyo638Dy9UR~_Rux2` zOSt5ma%*hdyuKS2Pq<<1K(yHx_rEaJ(8hOy+%XPQU2CiRfE3j`%;3kG4%ztOl6;F- zkOd#I=`CL9RU=M&_sKg$l4>en29j%oicI_#ba#iT8cX8f))Bt&aHtFig|IRDd&s7G zl5d}SHtz4Q-^Np3&-@vUm%_$w+{Wu1`Qov_x&P~HccvyEL$+G&g$X}LFD0XoX5(&o zkzD5}Fwh>of-w1CpRvfskL4JHJ1ZOS{LaYn1o9`cao;i$zHA^lZ(!EgxTUWj#Bnc7 za>0^p)U&zy=xjex#KN%prsL$Ju<@Q{w(+`@x&uVn_)ZX~yYy5X-v^~fGu;DevN(wt z5zk;DgANtQ#Gi(Z*98^X#uT%6`e8kX?1|Ygc^^Si3xI%;-5*F3Ci(VD)GWeP9QQ{Q ztnb8QlczR(7mb(U3S%yA;~Q=H0=dA(Ys=cr^vT;C-NrW;=;d-GMMO2*$-`7+E0C!^ z4s30ivB<`^IgEui9(3xQ3W5BIY;06S^5z2J%Eo>T=a!U>_4fcX;@q;K8yb6;ua};I z#>=reT8MLgJgxm!B6)KV!phhWTPnOAG#1H6OnQYLzG|H5g{jHM1CTjWxZZ54ifmpA z>xV7ILe72No$8!y^~%wR)If3`oZuVUS_Z?5oB!de8`@e1o4DLZ$mu}NaplP~{?i_( zKls$6$kkWi_9m=fjv^f+ohb*t$&xPuRF9lX-UsLY%?W-Tle|9%&0t+4w^5U&inj5e zydCWZ2DG~bozYtblQ&uDUb^emK9rXE!G;Uto5C)!3A-kbWm1kYbPr48lI4t1+kGZC zSTPnCuErPSHAi4X!s>0NwhVA;e4?42kJK_u^ND8d`A8?;w{&ZCxKb1^N<>;Y3lI$I z>OOIMNu_n=6L*5ZAz=b|BBlLoDtV7huTDf4H6G$BQ1_7AON_~mGvpz65+t=J&67F8 z#A+(Vn1e4^{Z|AAB1}1kT}xcIr|U$8jbe{@tR<`r!3$07$gACQa=n- z#Mi+Aq9lK>NpFHADYOJI#DZvL1u|977D>-yOi`tYd|hbcFc^+FefbSkkv~xa=z>n} zH3?UoYfoTWh9cbMVr?jbAxQEkOx&MN6INk6(2CpmnVhygmVB|G?Sm#?_JW5GIOGj) zAlD5|@a*&&ECC_TTII)kl z`vSbu#FIs`l)?`~(P~PD;)KNq&R z8PO4AO5tRfccdc8nLZkxW@zk!mqWT`fs9%YxJ}o_s2G^*bn-|G|OG?tnq z%@q7`N2VuHMgBxK?oXY#giFpFRX=O2WjLDuUoJW3y7wffIz$xDwF4grw?n*=y1q(b01ib@YTuNAIF0PBen;kf%!Wt-!%{NI9=+KIl`;S6p?ZwnN^BG0`sA z4k`Qc{lUR@$crXMN%3~bbB@S->+^QVJGOkcaIhUxPSCrB6Zk~iA@okCq*qd)z8!LJ zfw5>i#D0Wjm3R2XfC{BA=Z4r6LNWB^FMV>5QUPaU^H%VmO;qikx|Bm=pe zl6g;CMRh&>;1t>%3P-5KlfkpDz8&&`N85m$;$QN$AIT(NNz0d02g%@lnEtg2i4r9P zxgGMXtH2;avV9zp{J>*OMaaS6@siJ&Oa|Fr;QLCNF$Z5T02KLto-i30Bi6%reYaWc zc=hHB(B?2~|L_Eh45?O)?}O7-aA$cQpL`Q6&T%-iKVPO-SJQA2CwlZ(@_k={9QCw9 zcvH$nMh7SQQ}BDX?mdGl@`unc#UJSm{U;aDUn+F)7jLNs%je64NtR=xbwoIW6U&yd zo|f{oUofWDE?S1hhl}FhoWQ&x-IsIP&0oo9)7sDWlF!?8{f5TX=;FF(^5vWYnJ(q- zXVZ*@bPsk?HxtO8D!L;cn7RH77a5$&V`yq5>5i|>@Gav#&>d$-bX!I_;nX&2^^uKe zd;~VU*}9yflP{F8LQI9$g$vzmu{Xb(3a;TePgBzC}JbIsVYqe(RQeyP}^Czh0tW#gQ1&-=)0t z5_)u@K<&3~$q!w|!c*U!kDi=Xr@n6oy}(YWgt}$& z*6u@Yel$3jBhD&`y;i0-xrA=+tJ7O$?N`A$Is^P2ez9elB-3Ktfw->)AUigl#J=gP zio9l{h0LoVRp^T%yx>n*y=Wj+ZdL5)N~{W#e{W0Cw6N2dl4ENLeqBoBHbNrju*v$IB~w8l!8eJ z6-4q2S20wk?d+)A3KZXO^4ikGNSKtv(Fh_lU%JU4`AJEE%$K-*;WDQ9{>c_bXNNJ_ zeTJ4W--NoNLi}XcfkT*7Px-W0%eUDL_)auKzSEBE@HX04ro&K_X8{$bI?MI}QgTC#E>^NxkY9CrnerjqHuh9uAI249n4Ut6h z^BhglB%LHJn`c{0EEF6C>J#s$CS&2mdvuRYHj@)C`sG5|vz)y@mp#{=c&A18*-O$> zo%TqN+;izE7zVL>7w0QpZ5SPVk=-K2q`&bs(#h{DI_Zxpq#h+MB36+e=E1vt1?r@~ z39*oL;<~*KRI82eE8IYlCe3{$vAU$Ey0xJ@4H4Un9kG_I7drJ`*N=Dro&QM`AFWAM zKY<+0u5$gC{1~B2$#{)T7X31%Zxel!&|UmX_yybzpO}mPE@al?lR`PRC z{gyf)ZtLr*iY>Au(=@I|?pY5$?kSMT(c0-_n=z16IcviFDc=*wpQ@a7z|i5NxPbmf zfjrI^$%;*w4CJg|yO^Yx>9tI=Bf8Dn%k-ArwD24>J_Q$2y&#VHWqQdk(%7g;^Thfs z$e$A!Ae?A$PZz4u@KRp&r{M28F;BgQA1Vx)PA<<}9hTrr6;t!XIh)1{9RL`+B9h;F zR3@2D^Q%)V@jj-?(VP4gF}Yb7y`(3CvQisS=3c#Ji_|%QwjP_&*;`$FaxQy6p zw#R~E2p{8M)HTSFkqj9d2`gDF8j$2Uqn@w4%ttE>}}hA z-qhAh(e-JfczccQf6mdnotXW1F0CJ#{r8S$`{Yk~T4Ixok?k`VltuDqDR{(wf-92W zxvHY<3Prd^)1!a42ZPM*aG_+M!HOHb6IPe~6t@oh>99`Q?DsuwSzrDq4Xm|u;PqmH=%i*7MTcZ@msf}cF61v({6=Brut zoY%72GvAO`4>}j!oFR&LL^h<&#zONg-F5$eNb{jzE>z~j>eCo1vAX7)Sub(TFxz9l{G9Q7W4tr5=qkjWcL0L5 zI}9rQ&gg5=Z;zRMe;71OTt**gW-C+49VRZ^pkoYh6&Q4qsepZ7i?NXX#w(^kf4k*` z(O=q>VqGP!$t8i_sX<-#mRBcqw?!{)hwidPV}3)|XTiDsIQvF;*)a~YA5_-aryy;_ zeqaS>H)%zR*=PO&rj3L}XyG|utHc}_Ot4--x{*F z&3=d9PROF`)uMQ>8)v_vPmfq*_C2ACgY#_rt_7WaH;-QPN1w>^GtVFcZ0IYHZNEDl zxhFwVBO&|jBgQ&q`>q8pRGxoAUKrgx!s@c0Zq>2<%y!v#dj1d>U7szAkEP=5hv{kC zXw1`t$(Vijw9Y=6q94eTj1ha8wuhw^$n0P7;17AmLiVF(F1bdr?;bW#?0<#2k|}CX zm;DT<4*RXG_H5r|^&gL}&k@CSQ{iR7iwRx|ZAP(&}6v5@oz{qy5h zs_z~aD$-c!8ch~8s7rc#r}hkUwi}#bZiiKCux&DZX8&i=4|4i{O953r(K3dC&a=7T zjLAqk+KHCY=!@(oQUpm(?j~iP^#mHBJ4sHSpV8HJG-Yg!EsF~N-u|ja0{KJQz%rQr z6#Nx)_kz))51|eYvFe3?H2PE`r}ORCa~?g1SS=c?8hvcA46FseRV;D0qS3iRGDxBE7cZ9v%b^})A@fU!|=L< zFpRS9z+K?LTNOwQ&4Gu*fd{4(s5@|Phq2Is=dJDhrgC7T%!SH`!;uL!oDa1+ z=t>wVkM^?hRS{Qa-vh4Kx1_+J%WOXj&RtaYrfMuTNiJOQmmF_BE?WoxX^u@D z`vfb_cC}+~Z@1^zC+yzme6&6vy9epGV-L2F9~^eN^7bDl#3Q9Wtoh3nb-+sT4s?`&y~y@MY*_BP#j zq){%!l*GxJWi@&uc@51o@!l2u#sEGe7;3U1!nB=J6kSM;BP3-wO?8;+sw7E}%M+*?TnaP-xQXn&2 z;RACRlU-%Es0d@S$ru=_#I^0#`;-XePn5VwC1Xs&CDlbbZ~^Rp{@z^HHcoTIz=yZ+Dp;fJiGW)w7ygnZ*$@) zdY}WZaXCe|z-6PgN2{l&=+Pxg<|KxeqPHz!?Gb=_if#!VGfdI5Q~mByDZ15Dz3@%} z<@wRl%ym=rVzZib&TNnLp4|^iVVKKAajhFCowh{QLJxAWZ?xug(qjjeF#x}E)^%e5fbhc^q@#@Rb}b1aQKMyaEND_B#UP01@OX+$_ms; zZK%Ne#TVJx zK9inQ(JehCt&_&j+Mym2O(Q)sg?#EOP$xa9!dOVU{}Vf0tw>Liwxsw~q)Bt*a@3%% zrE%|=em>Fqtks^SM?WxTF?zg06z}FKnJ?NHlM5m{6{`Cu)>dO}JkJ+eaTA<;C_ zvlB?g1qJG)M_Y`Ar1$I5+Dnn1kmAC?($L(<3Ssq0$K3lRXsqpRuc;HQR`iH?exwq& z^f*ss=i5wrc$IrkfZZea-pnTTC~?D>#ukJz&QqXHdU&3(ko4HbPAdb_l3-+M(%fb? zHK}EnD*Xl{afw_^jO5@sG3A(B2s5ocvoN(Q+wZ+v2jUz-1=B${UFZOS-Ps3=f&0)yki+w_TB94j)mDU3}_F1*CX1d=%|EzmDxiuBewU>0F@ zNxu}iH$64B^*Ok=e0=QbZk?ZT_FA_867=|YBr>)%El?c@VN6Yl>@4^S41%Lg3c77K z&0+h|Ljh=V=F4VF)JTCE&AtVDlCt9_1um47GAr`J*fd92T}rPc!ibfW-cGbfY2zN7 z3__3p5XG_;IB!U4Q>3ZsK2w?qSB?_X2pm0GQ38gPc7ky>^%SU4I?(QTtD-b9&4r56 z>t$h#kXT(xZ+O*|UUk}|l=@)GS`2fwC_e7RDW#EwI)ql5=<1Y4I`qIjB_LCx=fD~1 z5=$LM+m!8(dn=&ia-nj(1k5_pA*?>7n3Z1l+M{&Bo6GM+kJpIe!!=gg!d6f5Q;xS; zS*J7#WqSqEhm?LQ2xAMIB&19lQd;@Ymg5wq&B|P;thAqvGgH~1E~Qsvl-}~&qqIkl z<(pubYen%Ho*zTUYc}b3K~grv(&nB{X|6-RQBndjCHm=%(QGPEqqNDJEt3_c%{?wu zR_dJ=#$1Q6`jo6{$9uh9O2=%mpc{JpC$4tXSZRc-e)y!Uv_nd#v~7WYu0_IV>0v+) zq2Ve}qtt!Lm|$+(A;pEtN-NP|TdA13l-@S0DZSAyrDKK$)U-M=vJ~2OLGF#X_WHwce_wgvhu1$ zu)xj;=wOylSY1l5y46}`OTt*}5muMdYca=r%|*{`TIuLVa!;Yhe~aRi`M8y4 zV5*%;J)nXxwy(0%JezJwCSkN#nvQBSQVP^49evrRKL(WYTqr5Y`;_O|gw>_=W{lFC zc6*c-wl=Ork2m1lFA=9?!7dkvjyJQcTWO9}iA(#$d! zDl1(8$D894R+rLScD3WZW41?Wnzbbv;Xl~8NX045xA3B-a22={2u6;#gCjC$7DyPK z609`eQlLhu_4IAkt+K{WJ{KxVCqM@~IE2-u^kFQP-f!1ROKJ?X+ch>w8*6GawTAx#0MiiY*$dAMyY@A%~mN& z3vyg2Dan2EMJ8c&DM8`9r68BBAA0RkI&lAEwnmRPiQ+wW+)7)gMRsfI0TqO?HKHeS zytyen<-kLMZlyUnR7)#RqcmXIk^3u3Tf1DStaLWaIyXgFT}tm-)s#MN*YWncYjP1i z-Ykj_ScFt)Ks!m2gi!js2ep(yQ8;X*}eRYe#} z+NSh@Urp&Fzdb7rEjOKmVg8FXUX7KeWA(6I7)uLnol@4Mt1n8xkkUd>n(ir3v(oP8 zY`I8LT4-~jqI7y$7+I6Bx>kBGW~Fz@ZQ6{b8A~>^(Bmz*2{j$J(hOuZdLW~6ylqOj zun(I_VT`%3*^LfbYL1s#>tJ3AK#kJ;H+RRTO+E(`mQ)K~J=}u^bEW0#Q%claM``|_ zO(_iAv=@i;oW1oZbbhNSKI;TT_=174E%bjtSzanY1nrck2W9egqZuG_n9XOs3(F!) zoBBioi#z1U1$iYhca}NG#Jbc}V9+H!4HMlmw#G)|%#nF0LvkaRJ<|b}odO*!EOR|T zz%nrF>>OboaoGA!%!D6X?U``PsY7=_>)UWcS}JZr3xd$4QDwsIaTJ*_hrBW)O#??6 zUS9sR2&)dXuFvk;S($MAuuwWec7`jAob08p2|qBa1MNezJxW^~yZ;^-XD#;9-8iLr zW%WCMMJea%ly*d3+14TnHA)A=lJi2PqZ#ah{g+keEuXC@_(ibsGU%2g2+IPkH2higkn6xT!EA3cPSK$?@hvN*z*~F=WJZiqg)mYQa{Tn-<12 zo3Q$n64jKxblRgd>Zfi4(c@jB_+TP#rJa!ix_eA%T3NT!9-hd~bxD|r5LbR#q*T(zJ>&_V5U+OX)K|q(rY4ZLPrm@*SgfPkC28FyKn`csD2& z0!los8W~I7rl+j5ZvtY0;FCUbt8p;O{sM(b2Qm&!(K{(gv}m(d-n5so6sQrLfAtA# z)n@I!R3?2?_9-`O54ISSJ!hWD3-nG{UD97hc9c8RpIYthP|wc|qu$qH8;}!7NO}c` zeVJxE9-336Fi0W~jssx8;8?3uA?)K#lZqM<0ZAVw=J^G-we#$4`>p zr@##q>Cb&(?3*X7F6pn_(9)9hmu7pUNB+?L67+ZvZtKd$Exk)wy_Qf}`jEiViuAs| zPI`BgeOglDhNNG0g|SOnfg0(Jj^E@MMfwmbla`i!O49rKj49GTKy$kjRG;)GRyFAg z+)=)frmlM@9@>RAsXS4HSHv!=?g87rV6&x{Rdh=q?&zdfn)Jwj5>0dO7a;E*IR$E@ z59+ZsegH<6URL44i1gtOV~X?_Ibp0c39D=APtB0DjOovv_F}qgW`~o}FxUV#gz%^-X0f5F}*a@k|dpN zL?`?ERIe`SAH0yXbnkBy?OFQB6SwM%9`6&y*K0_xEU4$L zi{f{@YzPzCDp>QK@RZ{)S0}xsqLbb~K@XNy;)XH(xF?KNIpzS(sp+Yq`yMz=BugLW za$!VzNrf>*x)VCtpP>4d{>H8*{XHVG?U+8=Kk;nz_<$(BQIoyxvU(_{vh;3C5*kKBI;WD ze^E?J_x{0ekMxX1gEzu34~pV9W;~|%gl*}ZOp#u0>!f$VQAGLxEK<4z{6b69S=gQ~ za|kWn>5`r&D$>hsE{rU_ONc4bT|xSQG}Wt1`UfktwA{-15teRyp}*mPA)lkiheQ!c zFSg-!prfBr+n{+UoLvfI9E_NL+9F}1^_D!NKG0F1X4?r{EdN%%iqo)dE|k4wUbnH# zDG^qml38;`-TFUEol&>asdeyUh=l_VpiANpi{jg*$a-f1!km}aZ@E1zt>1EcU`3sv zIkM(KAh|Y$ugYa*b9t7zdtQNj4oxQjhe=}~Xq(sA7$!rfZU4LDA~J_t5Q)A@zEiryytS9pp100Frxy+VD2&X^!xNtU^ZMq& z;b0zl>p^AwzKO=wz4cKOnKQ3I&0Ckg+WNcl*26=Z%3EJTgM-S{psu$j6V(CO({GQ` zzBkPof*v1(G1+fJN_)d#t4JxRfY^6+N{4{%gDwhmO5}limlUW`+Q1p`fueLk&>{%q z%xjJ?4v{*jOR1Y*O)2HIM`@>0BW>|KE{bpE<2hxir*9tQO`XzyX_0wL3Zvze6}~W* zdNq^|xn$Zu6{Wn%h001#!D;tP6IPc}54W09FRMLDdmXS~d-V7OCPXhzX>Uv4JlLm- z(lSS6-gZeCjS}UKy)6Z5R!Z)^5EqyC&I@B7lM5B4cPd!wI)v4w)IH{SO^Nm>9sI}+ zx1q-;Me$ubPH9<6-#l1e)~$40MP%+LS#(OYd9W;{K#fx4dk4OuC@n8@p`vs@XdYJ~ ztS+TqX0?@)c6*eL8#3<|^!OAgRpOM+Na>pgCna=BXTgF`xFk$uCAoQUMlGe$dv1Xn z8Ocf~Q3JH#Sb8!gjI%7l>Qd@q)n@n}UXbCF_!4CJjo;htujuD#QGCS;h;ULi{tO2@ z-wEa+!|~`MGH(x`=F?@cVE@)QJFgxP<)ABJoM4IUP6d30$lRIyanqko1@hEJSCk!( zu{Aat(_3wf(|pEchL@LV&(1UE;0x|ZsL()!$r%mmYY2Y*_5dcb)+SRl%P-e@qV)IGxnw7qJBVhEF*Ug@hWIDT#+{*4*SvMovt zYweY2_>3rGe=DH2-4AJ{vD#E1`ypMD_;Z0V<%b8E!Z_7p41P%A zSMcW@JFcE&o4)oe^$ip8y>P|F#4t)KHud?3i0&R4&^-cu) z$a<&PA~PFh%6fltv48B61e*179{7gbB8NQDR25kV^P#X)Y{DYzEdcf>moP=iu8y(3 zb{mwYKfmufG<+U0mWWe2!=a6CrgThBr*uX|WOlHa(up9yutE}OlxTwLmrc3 zOgZH23hK$m5v3h%VVo${At_;(p(<_k_S&Gd@VwdgV1yS$@%@?@JI14pZl-h&JTJ1+ z$&Sb@PBEo3ZIRuvtRxN72JLVkIngQKe>TkC}Y4c|rX$pH8d!d-dj;c_{JcXT55}7kB zrgTbKr*uwEWVZ2{(i%`|_0d+NlsOTaKB1&Qozf{~#uTM_rZCRQ5f=Gk-V(-|G+~m` z24Ti%-N1q84Zu7szpQUoUS@9o8XCSLiXWr{O8E7gN`hyC#Elge`&d_G`gt^peA|Ys zlKD>#VGxQaGh(KH8X9(~q7-L<#TpL8aoP}P|GpCtN{Lq?ju#i_Y@eon7Uwj$$p#e~ zB@#zY=4bl~3@T;@l(DuUNQpDdsTOAlmMV3%Gi+|+WHfwD6hE`$;+$HdX*(1rFERry z8buR_CgM{|3S@BxmLN`^FsYr5+?Y6R8EbN79_{bHE{ZSk3>_NlI7;s>i*q`RHK?FQ z<|^3*2`tJT1+q9Jpq+ByeK6lmzk zSaYGVYfZwWc80}_wV~67I7hvAG&#h($UBv|cFyxf=J6bhb0x%CP@z#Y?YwCU<2+x1 ztepiZVO(hvCdC;P)6PJ@4ROX?zSAyf_?{@fn2(F|S4Rt98e15D zEh~`4nGJFNo+eC+GuV$At1WS+bnf#x8on=z-`2Qtp&~MO7Fe9WK|4DKBeStGH$j|2 zpfVO`n}jg_W=7)J)#3~@+tAK2V^ZXHABZA;xTsbIJeKhfi1S>U#VO{n4#?9ens%OZ z1*$2K#o0A4jAD*3O4! zgeLx(uNG%phj;*4y|cN(wnyeS%fj0JcpF3w+VdfPmUbAc-|yUI~CaeBj8 zf3*pX0zC)qT;LKWwX<=|Si{>AXY2vn9EygYh~j%rT%2=}mFa9xooD_F;>;}2D4IA8 z6=9rfDUgko@rCg(moO>LNVD2^Mzv+EL%M83>$*>IvXzR9b1~LC-4ZO0fH>0~8buSQ zZ&?@@mlVk2Y!8hImoO>Lre3u;Bia&Y^ShdcqTy%QU#Su2GLPQS$>N*`Pnuq#Q8aN3 zXy-Cdfhr^j1Mut})i736VM4WpS>tL}pIRSee!E zlS@e&$jIU>v4nArMVJ!DuGY@RZE0uE`8)PP!>>f~%XC~jMd;(K(3Q{6iOl>wjS^`m z^CxJh=qZrJneRhmIl`nkqhs3HB+-U;hO{0=7d*bk#qd&GoD0$-^N1B{rzA2v`ZS6r z&Mg@Fg0uozoEfB@5@AxDP2%F%ZHP1Yyzc)(!*8&3ubDzG&ErwAp|Q?|INM3mnmCUo zV61$#INNzhjgdGboN8l@ZOd4PFYa;6d^G${6hF$x#km@JXJnd5nFrDIe~2tEF3$BS+?7{h?Oa_JnXIQq4vqCP zeCPU<0$H4$($H9$FeQ#vEzbBv8`|mckx@j$A4IW|i;E-DBD;#yiE$x3$%^?-c4xS) z2tXFcfRvNYeSrkTUOqWmOqN(_caTQ3oG=JW7f{4KBmw>5v(10GqG`D zg@%sO;Qr9gr9NR&JL3|eI9Jj}=QxNn&cv7XZ8v2aCuPy_CupZ8vM#o;XJN89*B0m! z9*q*Ya%Kbg&c&7jSvz~@ah_EmOo}r;GL{r)yxWF2i*D_-0u6r_#n)=Ia|r|(X0tfg z<>*dcH8N`_)7M87$)O|dJPQL}Co3v(B4bH$Cct;JSK{Jaj#%0- zbY&Nw^ny*JXyOcoD_`y?ki~fcBDxk~QXB{yT$pH;#%gX$JBPeCs1Xf+7sapgadG~c z5SebFvD^~fF-oIo;&jd7#D*|{EY5ueh*Kg=iZeEDEUyh?^?tMU4B1!l7c(x-6=jj> z@3OJ3%G14^YUI$B2iRDgmKDh2yl5dS=R%i|lG~JZS7zSy75J*{b%PNp2h3=~v$1DTvca6n{>{#VJ8Mrp4O1!J><+ zF>$(M=#pP8&OxRyZm#If2CXUF}QlXg0b;xDDRIQK(<9yu20mJ;1nrbZ5Z zXCn-KzZ^Pp{Z5-OC9@SU2xa~s6z5xVlf%eeMUgXn?Y z%@M|J0T{@gc^BgRTdGlsV^YPnxwts@I!J>l7UxcA=LSC}PSQe9 zJJsSmYQk8NcDC@UwX>zuhBzyh>`Qs48?;l7i*s{DWDJwV`L9hESYzTeC4_NvrCOYW zf&JGeOd4xTw_2Qub{pc%e0Ji!5T`q|&Lp$s83S?ug z@P%cT)60e{$HbwF&<~iA zI99bdTX}7Wvy0V%e8&)1?VgW|Q%ZQnZKljahFAy z5+_kD&NRObaTcAq>17z8r?~3(L|mNfD{-r^Z-!7er=JIA`5Z!g*F;mr$H}1q@xN7H5AK3ye}I zjuq3+bhi!dbo5pYfH-}`RlnxqzH=+|v4_LP`VWLVJFP|z#aV%%zSXQ2=Xi+tA1R_T zR_HtGA-`uhqIH^$v(QWeH*mVaJ(yD*Acy;Omwm&wdv}6JeMPY$9f-uYO&b4(|9lLQ z&cu*NCpkQ8CB^q(KIDnaQ#Q&RD!T_q|3)0*07o9q@0+EHw7YbEGBMZND2My;T{`Fb z)GcFcP>T0vSx6rqW3v0q)o6Q9h&d?4GrTJ_5YgZ8b z2Ew<1%%dKaJ&feCBrTfP`gBybMdof#G~X_dUM|sNFB154NU-pkW6->mS70Dm<{F=9 zFm{)Tt|WGIim|mJ_8>vhc9MSP^fL0Q8)81UeJ~tjoyXY2X|A`{VeAfkQ~l95HST}Q zjIDF!Pz8U{i@iT35W1<*-;N2qmdnF&)&`-6UB;vyGB=k<7mP`5WEZA{@p4IFu=Q+@ z^G6sVEzK@GX0{bYNQ?Gz+GSt#Ujsq=iy}4_!ru;^g${-BDr|Xejw9shlzQK#Bg-Cz zO)kmNxLOok>ro>Gaugim3ghV%V~7F@kb*yb>4sPpL?0P8PEgqQvHdoPif9PFSIvc3 zkJ?lw<6>L8=8nA9SstAKOi#3K?T2}w%S}DEMmHOXV#18)f%hEvn#(Mo_tZn|Ww;uz z6x6#KR33O8k#E8)9Skpw*K)X2=HsiTf$V```<|n~pi3Fc&wGriJaBGapmWA#_u1j5 zFkVkH=HQFSHo&~El(bAJ) z1KD%tWnZ9o>ZC6FZTy;OXuj7}(a`)Lyd!XhRqmLf5O9zv_TX6&mCi!fa7vSwbsP=l zGIDh2@$b5Hzaxnd#e9~QcdwWV44TQ`oRy`eD00`>WLm`hp8xG~CspJRq0o>joO0~$ zlemEX66)Zukaxtt>*8w=16~cw)~!KK#{6tMWI67MK4{couqbZ8EW^3~1s4x7EilW+ z;NrJ>Joi8Ch-?y^mFb_cg!X#GHxMYhI3!A>fy`Gh?+X}8$t;%>nG&?}Scx%cAR)3t zO2~u`W3v0qWffsOV=+dBBD>rX#v3WZWX#Ws&HXdXXzo{2ehEnXbN|+-ckTlbhlpZN zKS%&PeHyRBvNu5Ca`H2t^VQ6(=Ke=2>PXG~PpGnB?te0;Rz_;>e+Ng=-2bMnj?~=m zo9gIplf3M0Uu5@kG26?d$1Gv^1)lpKH}Qjd1e==sUv$*-B;{;pJX6Bmp$;?y{j>1$ zfsn7e3e@NR=X}PZx&M(0W6|9IL|9MKm+P@7b6ihSlk0|eLTsH!etC^Aj5lqr7tQ^? z$(Wq`vw7J4ZJ)7l?jO5w{AUEhQ7rl!&Ha5+!g$Ak!FEAG7fxW-q^i=}+Ql{MV3^-=ouvHLws3;CgMKhpEdr!m3&rdPkXF>NI^djTdc&V&XfJz8Y!18M= zya;$Mk8~MV#bvPH(-jg_GQ(dyVcUgzbX5SO;D4zc)^n)dZE0aVL6B?<2*hpl_naI= z5?`>Mv!I+y#C?tUTrVWP-?&9I^$!!p0l7HwH!32#M}mpJjnQ@qi9eB7YEZ;qg>;|T zO#B@Wdo?!1(|jPi3j}?mnz+nnZ&N)}N(9pL}yy>WwTtI&Vf~w_+-xfOYLIUt~IG<#oGRbuN zSk9jdz4Q6r|4+`J`^DzBL57V)F_jM#z-iNX%Ee;~3Y_y_tf>5~a{jBnI#N0RWlJ6f zIse-dJphu=_da!0%?Eu_<4?9aQaS&}lsZy5|2tEj(*-&If1WV@m*brODZDTRHOgGq zlyKCu8dc8!$ft)M$1N{GV*bqMZL@iZPY*>GbV8ld&-8ADcT-p4fo9M}<+&PeOoCrSOEQoIfok zpbM_2a{e5I$w$7zkn?wrIm#mI|K=z|Zq0uV1#c{hy$W$h`81_|f+{s-{Dw%ONnSb1 z53V{=j`CeW9tDo_3CfNH8MQe0*-|x?qx|ToBjqSRmDQ1Ql+SQ<5iJKya;dM7{H=_r}M+rs!P#6m|IB(MJ{{?s6Hlsp9Z zMmC5XWjgfqxyALAqs%W0<3m$naFm6$vt>(T0=aV+JIb9cJ!l$Hv*obFai>C)n~36I z2#mt;#VY4oJ8Og#YN_IxW^X(s3*`L z$KJRJ&KDjshS*D#l^R9rLR+r zg>hlLH{eK(=tcq3e5D-*$fQ#bxeF3+DvBFcf&gKEH@=25kZY*b^Y<|EUL{^m{^qHjX0@vN z+EKgE4g^86a}iiMl1W=xlc~Oz!pm5oikbavVSJxg6@!j5wBP)j$C&IsL;KQSJB-m6 zk-0QY0}&=eWl6nN)h_VS^{uJ~kLocH0*(;HzDzt^RlRR(r^`(V%p9u%DOopi)%(6p z!v}Pf@sf*|?M@(n2o00MP;0;_E}*}%r6d0o{M53YZiyE<0I)LmF@dJ2OfucWt2MD) zKkjPPVfyN_YcbeJFv|Z`SX%`){=_b_sb&Vpr!*kFt_DJc5fSB zH4S7AM!~On1qNMa$5>cCq#08hIKss2U1Chdty2-k`(?%)d=c3dHVs6WB)+#>LtO6m zwb~FXj9YEnZ@UY2`VIn)5yd`i>~Kc^u%K`Ce+0YG{4U3B>X*WPaD~Q=%$uRD{tpWZ zWb8|lZJ0JA?(s__%tSI(#V)?nLC#?5#B9ObO!J`-A1a@xf><76UVu+?DSG)Gtlq%t| zF+Rx@sUnNb6LhFRwsY^aK(~x3J0p*ybHU3q-f$Y;*YLo_Ov;!2%m zcP&##j46X+Pp7Gm#~2Js>9Gqd94Qha^Y%x5mJSXHeq$IRxDjlKue1+v)6C&y#^eL znW@8OqByA#ah8)+Q+HF_u59X9!ZucgEk2;2y>PuLQ4yJ!3M5(N?wREUfi4ut?!E#R z?^t3?S)4p$K+qWVoWSC9zg>O+Rpd`(@%PbjqC&Xz@?}n3ZrQNjP^XtBqOY;DJ`;T(2|;N8kongMp5QqWYN^gB!iL^n$ccH z!2nZ%Y_!p3YaNdw=XteZsM;}EM`4bu~OP23s5-vIK=Y-ENlTRVt2O-e* zqgNA`&%Xwuwus_rFCs0&tEm&b@sb?JV`tDj6f`ffiDrMYULK0X(3k@(+G!>+qUg-H zDCksBpcaV-XZk;_BC&JGRQ4&?!2NA*AbX}wX7o;2-RRuMtX)B_?^@!l2af*~0!|dg ziJXYSS*JIA>Oza{o5ax#K3lXij=oPTv3U8F`Ijx4dJ`t&O1cF-xU(r4Vz4OLso*yj z2Cb85@E@U}Y4<+;q!IB#2Y|?YR=^xAi==7yH|xgZ!qrWUkYkc4ZefNt4C1k`OUpfu zM=UQg-@bQWfHE8=CW(H9_%2A7ToGg+WPFC-67akqKG>x)XtUcvqPeTpcW8y zA5S9quLBNS4@_{6DuS8-)$NQb3FDOrCfbPfuv^fAtpvs1v$o#{?S6!9ZO+kkWWL2(&dVAW8NmbG|KvVBL zW3qeN*=g!tV9dc63{awh2$LE-_zx~Ar%%`%OS=wJL~*(u@C}1|1I)3sXjXg&d1^r| zhimFup)C#?E=t!~S`u$iQee`x$ns)Bp@Z{ufk0sW2qRE^cvTEzWRu~ea&O7!>bTd^H$M^xu4s4yS4y~o=!%UQfjk^y&Uc$kD zQbHw5!QXE2=BLC9LvH3mpK0R%K0H>8s+l%Bq{Vjymn=A0Wvz zxPK|2!z+QNzG;#9D9wp$Fk*UXo)cGN8QTb;N}Lbf|Ga1iiW>CqNtz8an|elt;hWa5s(mFzmm!%oG_WFx_)X_ z)pH$#7P#g&pjPmEwS&z#&I3xa&;`Z;>G=E|&hb?))@L7`~N>RKmlXzSBxT8Od>xaPZ0u5E><^E=-KibE!06kEhMNkac$Ui@M1IuRGsMEt8#|>L zButIor_9(N9)0+?N1ubyw-pUn!HW;gaR>V7c?P4=yI4A=MsH+D%?E!ZhI+0z@glJ%lmT*vDot8a-j^m>S&(>-}Nw1Miyl5k{Xa8t%44@$@oxs&P+*B1NO8 zJgyjN-Uu82;n6obwRH|gpCcNsP9uM~+^IHtbZsCSy{pL;!_m9`USjMIk3MI~z9(b! zxuRhma_liF?m!#8qsL%4de>jWis9&u(ZY^LZ>W7+*tx=>CW4N&Ug;t=HTDb}M`CS|E`J&-A_~gp47fr0D z5_cVn)z~YoVM?s7zd9Ng#3;?->I1Q==EH@BI$5-_bo|DUXges%6UD!TgGaf(vA4s$ zl0=w2t3HISv8$kPKGadF=Kv6my;F>{^4gsb2TYzzzg^m1H2kw5ihrVhf=`%5f3q2i z^w!zYF%`=l@{IlA(KkKqaLObLM8oYlQ9PX6<1dfi*uiHs8ojTjV?iDZ>;2);JKZ#G z0!GilXD}PD3_H+9@0im^QZvYJWgSza_cIye(f?R9b(?+MRuEwa(Qu6~imM9Ti{`cs zHiMA@`iH6p7DQ7oSFfkU>Rn+BVpX~Aaj80PyK(t23lc394Of;ht){sH&22lm43b3T zwxY3fO2^jNz`Fi!>DZYL)oZH400G;;!yox!<+ba!6FN>j3{vhW8vcQBKgJE(<4@=~ z{e1=_y$x`6EO4Aqmw#~dvpi$O;-fM8BGFKS+pgk1@i)wY4P{1Y^s9a1**#QdBvIdz zUQbDsOfkk1{V``sRu&D1SUZV^wP{hzyWEQ=)`0bh&^@dOu>xmGR=6>Vs>IsdV=V4W zr>E;UQ_pvf=naV$Ln6w7CU>AY(`bu98c8`*x=Jb1nHo)}sveF+WLuOsD@N<#yr+!-!!isG@JYEJ)$>)ml77)iOAO;zYa7)hyrWIabmR6T-3V` z#HCzQFEE?FSTG)4ED;U=cChC2xdTng5iWy~lp8V>N{P`O23bmARTifTqOrNa_2N=G z^(;QLW#;3Mau?BXZC(_Q&vOTwloMSBBPlmAbxc`&LX|`+eQXj+L~R{35{(;|xNTg@ z)9Oii=)`86z<1ac>!=DMCB+?RQV!2E7)jZ}kfzJg;pnW(uoAvRQVuCF9+Ps|1701! z+-2gH3(&=Gm>n@WoNjRknv_FK1|umaI69_uIo{PVrOSzF9dmFX8V6g9#ie}2uOsC= zYsLsjxw~k%9~M8u<_YqrLqr!S|DW9w-<;?FVeg-M` z5Dj-g$`iDH!x$g#Ga5;`X->zKlp9vpb4YJPtLgy)W~T5*e&SL-W7g5-X2$RVkaADa zaJ`N7P=PzpbU7vjH7Px=NLXO;w2sx+@Cv0#@$JTj-4aNWJBl~j*GbpXXk*DLYeQkSNI|XyeqBh6Pjh zoV11oQ+C#5EbfBO+I3uTFQdnWkZ5nwa3cccz%qBBx!~4SBb|vFqH(Ij6-i3vg4xsPbLFNdU4;eoXE-@Gz|k>0kjb!;^bMB}8e zaZE@3>Mj^2jmZCs(f37|Rz&d#lRMRPG&Ss%MprtTQH7C?^pC9P=m>^DTY?~ESQ3+R z*n3VLOU^AN_Cgm+vHgu?qGy0G<;|?pk&-f7z<}~Yqbp0!w*p8?q%65rUdJ39h{pLP z#^O?bSTE&maNV+-A?1FsBqHFHG(wS-=b*1@ms@UbKjiK6@{;*zxf~}$t|+b!$COFrVcFUC+?O2mL6Zj9stQwT%~%W~ z1l7Z^8@CAANzRP=#S+8v%I68 zIv%&zcGw@=i5{lXa5PP}zum2!5?^IWP zrn;x+dUzg#GvNSD$K;6Bs{G9fQ+a`PC#pOaUt3r>l4T0OR8Fx7YL!QqI8!QTCOH!- zc@upFf~F(0#OVmA=fHHWM0Cb%l$yl_AJ>axMX*W>9`PKMBP7zPwE_E78nViPImctH za$$BbA#oV+iP$;x-QoU;QKzD!1^8CZz>AJT5J5ksI6OsA7jIIMGgZ9l7H8qbn-=t~ zRT=uOdfSva6;&?8djmXJmjsE}5YGyrRyjM%6)Ba+7@VnzIMwIO!3}7dU=XWO**o-f ze$_)?|Dw%e z46ztu4>lOewvmEk{~FtS_bNK|P`nzIox@)djGiT~rIteM0~hj+O#zt7gMETpS{LWe|JKhWxEA1z?x1c8Q=+sV-e-c$}&8_)#urD{%vwj<$)BqIxbR&hgrRF+@Bq zSPrpAa3Y=?>?@OXM2`@EyS29Jx1B(S& zimGSX@djsVmi@!#OdPSiiM|3s)8ZuY8kNT2uytjt)x*T?hy$^Yvyfjc;#69oGMgi$ zRi5H-rd0mj;c*FRVvl!F1IL?P_8D} zDP>|cHR>Gt6J+f_I`(eNehS3i#q-$BK~T0{==(Tbqf-l%Nw7+dQk;d?=(J#OYE*`g z3)@;LtE-ot6b{SH#I85SD0Dn8Ou=R>3FtHLjIB< z08_arMNzfN#SUjmvSao~m1p3*M3rj{O2ky2=@Qf`=Q*4y zl}odn36;<^FUc7qWTylSRn~X5ZG7g)b5Z4)5PKC@>l=eaY=v3q@l0xkIVs2_l&_T8 z7iP$>rbfnSBV@jfYn{Lu-f$Mg-p8W?TnfNy;(_<7pHXSK;`lRL9Oz*Dn&}=3UUipYiL^G6VxhKd&E#>eMd#-xre=k zD$j-3hbg?OvMB&NDo!>CicIRL&~LB=TZsjnJ zTIH$~c?u>}@+SQpPB29<->yp1H#Cyf;_NP8^gYYbtom|gLD-VF)Y<)CnEnEsf-dCG z%TfR~1usn!6nk?vZa~uo7H8@}xgy7zI#4c2apvF#Rx$9aIZ%va-H^k1>F9~Cqsj{* z_E;J6SCl9yQ+cINP^&!0;!LT$h>#o`r81W!DEd0M0Zpqj#A;Q}wnJ2o?6l_yRCy7^ zp7e2H_9y^Tsi9VRZk8McQz|cYI8!RYY@Bo*_KEo;N6fE?1jxa|E@bwi(WpqP8AqqFlU*z5+p0Tztq@tMbIK1Eg=c`$|-K zDGq7|uL%M{T4hs@5=GT22WB}_D*L54Q-iuim7jwS__H?T_NTj!zgr;3ZPHYaomea6Pe^mI{uKynLJ6y z?+bQO_{o!W{LvEklPBr;Q%)80h4MSgoXL}P{NEYQ);q#)oy(XyNyq=~arPK`pkJUR zI7!E!2>gPRbo`MZuVC^d9sjRS@oL7}INuJLkrVo*hGG=~Vozlue|?Z#k9GW!Bt;Fz zI{vWBnH=kQkx($!5P!rWsK@%jEU{XZq3ikV0~TJ4DzAbV{#}avMS&ou^3DKimBk>F zU`plf1y zoXPb({#ccA2OS{(s7-#gDno0z^u!^3P^F7cfJ<0QmjW=A_d5h-jc^0vMV~WO%O^6N z36;F*THYJ@)vCPQ51E%oEStO-RbB(JSFo0alnzYmdHlawf?DPMNzRnYdwkAREgvMr z)}V)jB(*9-Yq{681NTOiYj9rTb;c!`AZl=KjNfJx)GF7PI8!R`bT|vIkQ> zlsQ|88xX(CB34t?@c%i`;r3Z=P~~+HdpZL7%cwto1~c?Ym#D7lT?Ni6Gn5cpIiE@r z6n!1sfVemdsaB&h{P}zTr@CB)D%axejg2aE6o9FGphQrs^eoPl%KOWlg^&Gz4Dzd0 zd5arzv`<)gaywLcJ;dHal~-64fT?^gLr|-HIoKV+l*(7VDnCcm?X4<5M97{lkzb9< z@F&|l>^5~Ms=NW;_u$c`7S5r%4eI#VWXTCi47gYIA zh&}FLEejNYsr(>_s#U&KrAVoK)1uB)ONhVYapvF##Gfh?t5q4gzDJJO`WjSu6V6Lq zInTE!08{x)0JTa#MUH|gmG5LY3$LZ`k{_z9?@D;??Q>V6%A4^mK?(8~*c5{!flGbtU{lnKQN4zF*Z>tU(ZerkeSJm9o6={hna2xty(c1pAPXI36lj!X=-e zV2`=N?`4CSz7l@HVNCsBk@$NyXX;A0M5y*YH+((c=agd;SjB(g+qDc-qC8 zK~Y6@_4bj+nHuX?e9pvJV)9X_%xs=NiyIyt;v_b33Hksta5 zwaT}HOo9oOyh%TY6HI}A0zv%65`9y*$|GOg^>++$E5u&JT3#sPR9bLud^JNzt9(Ai z*(R#Asc(%+<0&U(4H}&sc`2$a;2U%c?{hs0z-swYfuL6THX*j2zn&yWwS@RbReR{5 z1H?ZL_OMpv(_t&+@}=fnRCycL(#NN3J|*HRErMF*>kemXUVgF>mG4$D(FxCuHuXi7 z^}UlB^y{&UQ049TlVAnN=Pe4LAL7TKH3$loYkgS{moxcbKmKl+vz533@iz;^YU>ud zcJI3HVZBh%9T0mKM>k)h0IY6r1W?!QZJ!(kQ+0d2N>TXQ{f9+;YgIn$hs?o4-|n&- zsw|?)66CM7DF9QsA=vjoWuhTVj#}mas`thr5A`Yh1cLY%z9N6VrufkaQQ50?UvYi* zZ+z!fMwLN1n95%~iW;ble`aweYnh1TI18`k=Yd~sEyZtK-RKYKAN}IuLr~>9h`p4> zXMmIkKZ8~0i!4#C^6OxCbS=LiH+hT;l@R|eNl@4FH~dDmT9r3jAu9KMGa5&gcjC{4 zA`K`Y}mFpq)V-jD1 z1-q_QCK@QHs*%VP|Gh+zYDwGTQ|^t!iDCjl{3nCHsZn|22VwumynS*9ELFo@&=|vG z{Duq#&?@6UAmgWaxMQSu{W9xA#AV!zptzn5a-C;ePvqQNJs6@6F5 z)N1`>nfob4p9HLCB%9xNLXL_BS|UfGQjO%- zNzN)q1tB@Q4sJpGYw;mljY=c*UC8bq4ZwNQa393}=RyA8L2{<@ORo}?9TlJ2oC%e@ z$$9B;f+>R4x@^-oH7YxY{#K-3Lx+sO5cfl4BaUvtqX10hS1E!rJ8e`xsg@l7waV{3 z@~wLgPCQ_lsO19?`_hH{gFyg22jjn$DXPe>j*4#zoT)kZL)G5MIhcqB0qa(@&-aPx zsK~<~M8K8#*&q>9R4(!C6-5?jO3{WYrjCm5GvrsdqVek%yn%}TgCkjn{9PUeV2XYT zqUsv`;F6O_MHX!XQ)4Z1}jIa6j80{$0TP;(f@4D zl%ijQzEaWJ@R!b(vGs2#e(@SuhfvtNa}71PT4} zwC>Vu_rZbzsOVvc{gH(H-9aK&nuLwPWeZA^h?O{#rAf36ItxEFp|=cJ-HK*(+N=vI zdIVx$rErSS@I6m`jRrW9>nB38GeF_Bhy`_%9##J<5p>^7eQFhxxP z(~5conFLdck{NQ;HR@g_R=1))J! zYU>fJThRe$9y1sfJr0c#5AshWDF9Q{J4H|{YRYn^6t%1JQ==9S0@kf)wb{ZfayFQ6WzYF<0((j~Wz!scan-Q)WjGNNnkm z5>Bu~VNjt*yPbQ2}c)aW)^#A@mm z{+fLFn$4!5qGurXJJ#*?ECpb7>r^19>lQC_CPo($opYSY%hQD6a3(e&k@SewsBGWK z4jJA4XD;{vRX&S1Z8!&?@+kmQ*(G3FWn-0crLw(2j?&MeE%hmwK#=I-D2c;T0#0Bm%7S_DNVHM$*q&eZ5`7IYSVYIM7LkM-24xc2Ro#pvXKHl2RjG8)0TS(V#)%s{>h-PQ04Ow z`y5pk4GO?icC5}WGj%MJqgL4~=q#90*~8|34sJlAe~DPF%3fhAx9!#TK2-Sv-Xh_# zdry`EFqJ#!2+Hg-(;kH6c|p~32bZ8$xm^%YFb5qVF_7G9ANIHJ;fIWP)7i_GqskYd zv8@OB$L%0O@Te#;C`nMO9OQ7OR1P*c6Sd?`s~lhuuc>ADja;`8!@fh6FX8nYs?_hY zSuOYQDJrR?ZSg6XP|2J0b2w3c0zqQO;2Ts~-|;;5=XQHzh?gPusR8*rg8=M!?jAsq zT^-K@t42~C&qKUOr3t^4XhUM#0)pWI0ocw(~htinb}&uRhiVN4JuPAp;9T@GsT%wq<>_w?iw9w?Di8XdL0^@l90d8 zprB0A;2c3+qirqDl%gGzoGC@y1j_4HwAsu1VVs6HaMW_RN(2FzqU}ANN!4iUEN2x( zL1&>{DcZ>QURv;eJZdE*WBVE81dK z!%S547Boh)ctsf`XNq=6QBre>5@eOSoXhp1aV)pl;5q}GM{<$&*W!ZN&2n72hfFUnRM_~gz@h*w zyICNpvyb*UQ`ska#OltTY+Q0HX8#1=jFlk&bg)Y-`>-TMW!VEq!BqB9Hu=?^ebxcP zUCjO|UV!;{aY6m@lYX6C!t#mg?E98DQ`twl#OlsIb5f55nEf-Hb-3284|bDfKhUD6 zI{U#sXDa(xhgjX&hjeNbZ=pYj*sm6@Ho-2j?E7RWs?L63fisnT|17b(vkyz1jF+bk zUqE9#i|hQxvLBSAs5<+Y3}-6)1cO-J*#}LUz6i5_iMIlH#64hB0JiT#Qv`MPp)O}C z`vFN}b!TrkcY1fs{uRW&a3KG1mIAQs`&k5a_OWHoRQ5@mp1tRf3A4s{~jM6*^qxRkk7J@@hGa^_lX(K)V?1~sQ#PH z6TJy0X8!@-^(Jv$C)Vz6RI+) z${*rVCSCcxZDMt2?_OGXKkobg@Rb+NI(&~3wBTHLNQ#)=_q|J;seM1pBSzWlxfwdg z8@GP;*C=5FG0frTDY9HEb9&}Sl=Tx{ zo96JYASeQpHLEI}8kdC`(xqh`5$uzYuVfvWCBIFRHDYk5ol(}$(AeI>r|3a8CTntu zLhEYbB}b)cSx5SeRb)*i6dXSF45Di_t?Tv>%K8Nwn+uTt+zP_zM@WYSTD7d1WpdQA z7CVepWF2D=+mvdZi=dXZ&||DJw`NqySA#g)C%;XR ze+9Xmr&O4kY9vL z(GO*c%w)~U5Y)03xr|k0O$s^-ze=^pZ4>9#{2%AEMp=L0Us+5-{;gCHM$av~L{Q5* z)L^V4YmUcQMb@-H>ZVoe_;rgGix*2!j60D3F385Jb-2sZsRiO_o3V0(Hjh{4%TkN;~AO#ZI>`9D&)R zQ0$Du^llJ5gG(kG}@PD^s8RL&}JrY;5-RP}Yx0TR>1hir9^Wb^Z#e@2z9 zq1emDS{kam_%}E$&(0DQD%IRtT%}SSb@NN)S9kX1FD}9dV$m2Bn^Rb$U^iKI@d`sV zoqev$naaK(ORVnfLl2y>4zo8xu|pQ}?*su@_8A^U)!DNKXDa(qDPnbJ-)&~^6_~vZ z6#HQIw>%2KvQM`N>g-1toT=|p~EqITPXG@VD=yY%YN2IvSYm}O(;^?&#{PM_NpUuP1upS$IOAlFnc>Z zGJVLu76f2N=4l2+6`9of;dq>_vc(a1y3d(9GSAI&=HLb-mRrPRjn*2We_>sn zG!Dhh49NRA>L(Zb$7HY-K0zVw5kn+!GMp*FrvxR$1zr7xjl?+x@@q-RAz!4LP)Gub zeRGii%B6lx$Wou67P73wnG*8%6frGiMV462xP|}PkYQIGyA>*G#l@K*e)rpxtrmsm?eVpCf$K_MNW*wexZMBVTceD(0f-FInSWA1b=Y*XWVuG$v+!9OlQil4mJvhlBs1uy&5^E_z;wf>t6YU1YtqPdH zr+zHKDwm*6kaLK&l%U7WZKq(c?wG)U{I@yk#}ed{1a*SrY+@}Xn7?w#Ef}l^6x-k+ zZ%9!;mf*M&L7m{tz_FzSogUx&dkoeSimg+Sf6t;=EWwfh>IBCd$ zx+N6bXYe>EQ$Mx`7x@Hrf@=(7EhQM2JX+jH^v2^L3Hg_^)Q=@NzeG?cxE58Z)>49* zP6W@LQ3LnDhy3>z^jT9u9^_x4Zul9jMb~X4K|VvC zEhVrAWLyl^7mBU0L_gTnk0n^+6V!WfX_8n=3AS0?YY7J13a4oq@*fAnSb`g~6ig?$ zh)|2uboZNE4aQ(wLveFF4qhz;9d(J$w+ZS5m$<}Q+Jj??gI~r3e}iJwf&2#!^<#T* zfkjX!xXC5fVuJTZJcGgdK{0`2@L`hru>_X~yQLFA-3fL$eV2DI*fu!GE?%^6EWv7z zvg!mEWr?-42i=yn?t=;XvJ$bD66`W_+y)G`EfkXxd}6t= zJ-E)HU^>Btfs&RI7~>8(2@?#!<=Vp|IS|J7;9~F33H}+dmJ$qTY&!~rZ3o5PnBbK_ z7)x*^#g|u#>Z;;;i(pF$j@c0X3WIHrCCWkm>lF243GyC6U80LK#9B(Ql{c#&2HOE| zAxikbu|WM;f=hy|I>GgUV@nD8UvT`}7;HxP$yVJsKwQ^@BRB47;GRE+m&$^c|k`#1~&&;b%M1ea%^c2 z2HA7*U2Aj~ypPC0zMP?cY!4tsP$#(5A=XlY;fHU5w@J}m@yZUDiXVf1EWxE^3Z@fW z=@a|w1UE)jjP8!E(LqpbGH?%qek{S|76sD@Zpaa9DM5BgpLa3XZg@t+F?hqFek{Qi zK`@=*pBZv&DZ!xk#BB=LZb%t0=31-Z1B?fs9yhp=9e!WcnSc0n@f;xd~5o;+y+%|8+U_iyM%Apg7FKF(^|%wg-0xOegqPiC{|! zPM$yiJPbAziX$w@|7KA?mf%){pib~m-6iU}di)j`Y#0>x%s~F948>vz{^JnT3GS(T z55_;f5XD6Ih2lOA?m^IxCAg#f=LAKYSW6`u_R)le7;HZ%4)k#keCo#%+@B?=_uzpH zv6d2SpN+M`V8fv}$iU+uNBvlWJ2#TxVS^l7O3)`WY&ZtnABx-hutvWnWeExti(Q+p z_XxI>VEKk#t1;LJDDF^#e8QoAEWx8eIdqBc_sOxP1g&=5^9Kwz5{g4S$hUT>A4_mo zil9z#uSKk-1lhyeO~POYKyh~)*8D-;@H1G8ZY~qm32t|ZwUl7$(#7Jr_$VmujEh}U zj{30#584EE0?#GZQi6q-#ka&@2jVov1Fbpe#}YiAq+mM1eFm|X5_E4Dy$^#OgkvD~ zfV$ylP@?;S-O>qeDUfGN36^Ka%)nryq1exXHNR!3A4{;#AgB}E8YIO8{9WL>{`fk3 zqrWVxYx})KrZITL6(Ao=QBd|u;9oXDkx4yaUmr*kY!!My;!&^4&k^i_DuxJ|7bFp7 zsOvAWEWMzonDiMaZePGT8SJM1)s~4u7K6(s6y0r$Ot)33yw?!yj->KZFDceb_6Q+) z$Uk5Uzq?$5BHjbOV2@PgxZe}(u@v`P?+A7`{;L}HRlnLYQ7m!xm@ECt#G>f;Ut7k* zZ&X93ezj$yWOH_xFZ^CDXjV1WM(8i|ns9f+IatN9P#lcshjxJ=HrB6aDXQ3OHP+82 zITK^eoAh%y;je$hKB-naBX@N|X5?}29sLce90$c+bC8c16o9Gxz#*tr>T7$!)Qo&B zSLKJjAn|63GepSV$Pg1Va>#{7q!B-Yzj5-{zoxq1;90+--tkb}7gw98O`)V-HNQTn zs^D5**H0*+%0r;|w=(2A z_!NMxk8ipJg`&G{k?94WGqpZGUgk{AjHjyn9ylQ>) z4aO?#s& z5)}p6rJp0%>s5Y;kiF*-tWg>Mn-#V_alf^w@=#oZP-QC-r_$(Gg(lvy2$4$K7N3G` z+K9gxlmb=OcXSVZuyYJmPKDxj5y&Tla9y=99;c0M;zv-{=`k< z6JN7Bt2o@4w>ehvFevsYpo)nvE#_CL;>U(&)oWzvufANg zdZz=iiicwrJ;?VA0_Ea;SrO=)h7_d z#`-IRqUs~&r!r@1tbZgVk99THU)TioSpRBNF<;E^PqLh;vHrEH5^Ai!CO46zGS=TF z2@0mh`i~SbJ=TA?j8)EuACx&$=fmH8&8o&a{Es7#GkOihD%$wK%7^?GK~Of<-v&@r zLXGv0S;{1sTEl<$I8)a?-#VO$4M=?B62r0Pcd+4Wc)#*im!Qh&_~fww`A&f#rt(9Z zqLND57N4ZDmW5tNHb;`=Ter#%5AHP8kN06 z|A_Koy`~I9l}F;!D+}_yEDFF>mNNuNB_uxeI8!738zEWW&{`%wvdFPUr4jna%Hp$T zxu|jmURxv~-*IEL{4GmSwaU*@oGF!G2A!p!Bj(_TCGLj^+1Ek58kOPqH!E(LD@Ob% zDDL4xeshb0vRZzeBdAq=Lg@ctUUp7W=Ngrr_YeEk*xGwC~giE_sT+kNRs;LziQjurKDlyB-k9!a;C&3JkA{4 zfaV69SWUUsof`H?V!NhZub`s2P#hjXMJ@$kj)pvz~No#;nrdwhAefCetyg(Jk0TjGSU|0k1tbz29#O(E5+$)DMo3^ znAr@`Xr!T`>f$7P;c9;S5PX9YoexC|54K%{{bFO)k;1A43Adm*Ud6;%@%GnKyLI3y z$7-z;`Ujg&C>r;mxMOi8C_{cXgF3RQ-O1IErnWvw2q9`BHL{Y?G1k6JedXxPwyQ^H zuJh;7>Emx#z|p~<2iXMvB2r! zh`HM?$Ndl?i)Dz_s0=@HhTYtEG^$*PZwWof?_*N{rm|~+pjO$#<4maJ?XPRurcAyy zD%V{e_L%F0(S16j%0>9H6c3>RJ_QI=YM?GI#N`ujLeVCwbf`b7{L53<_-+e+MsbUA z@j-E0vue@r#&7PFqF}m&JzdV!KsS{*b8rKi+gik060+69J;gcnIQ-d-6y&$hQ9riO zw0AV5g{Cc2Obbo>B=-}Ypm}$fm{@4mt(IHSCHOGht~$J%@bDfu$;K{bR~Dv?=yVNY zlz2Q8hgPo%tWzgn_=wgJQJpNY5nYO%+^|gTO2S99N~bFwu@OB1iu+~5I&D_l>1x&K zL_Fu`!a8j!eMIm|rpr~Qlc2c25!R_qMsyIZ(&;KoY($q~r$Sh#Znp3dt~l4lh;YO$X4leg(bG4r$BL9=svY|gpX*IP9Qg;|A6A*URb6k zS32oVs~rKNr$TXNGOSbF5BSYnFZU`UID3d2PqGw?t+%S1v9pNKdrPCF* z*odAD#iN|CPMxyCM>Oi>i;d_xP#hIn@-8XiBU)6g5m)+hV~vzn@RSGL|5UA2+d@QxU$hc8DcA%gW|znSf*_( z;UgN!^W?_)P&_&n*2&BYAJHnEu2LHpV5iVbyZ&jPEE(ZKD2~pCW!g5#MAOKZoi2jn zF`=FIDhMCZDxI#C8_|oQIHMevsjn}cbf+6U0iu^c@rXiLr|rwaN3=>IuJPr@rBIw~ zgmpT=5@QH+v$2scDe$Jb3*0qCtPH! zWV+E7ThS|_cwp$@PRYt1!cQGfH~0cXSL0e9n&}W*_=r~NbgeHp09T{XLJaqWk7$)n zYaF?874B2$IAv_%BN}CL<;K-eoEVzP^o5UTl}>A2x#8l%;)a!cwDggFst|cYZd`*i zB2->FBYZ@wWV+sw8*89AJrb5_|CI0%jSAt*jXV@b+F_jzc7=~qxFYgLFF4Y3hji_<6-mT6*H_=r~NwAK?F(d)4gxv);- zv%*KTN~gRnHljB`aZ+ff1BHuhl}^`rVk>$h6sK5WnMV9co-aH76W0hMtkXnC_=r}? zbiLe&-h``BX!SPGnTv@mT8nBd_<#ta>YjUUwE053F|b;5<@}_R#A`M$TI`}NX!R%o$y!R>AaHI`j_O=;Lt=|4R z#8EJ}EHga!q7^+6w*s?gmf`&dANl~|)?jXtV)*#Gm#jh@1G6m;GH?ENw;^r>vy02T z$1dsnDdIL@w(%HV`fcxP5I2F@%u`ODF?(CYZNW4w=6&?k8T}Er1G9aG;r$=q_5j3j zF#F^f&WxCO2jT>J^OVQW@AnAeW-yyl%)95?%LX8BkGqp(xZ#%e6A^a+Ghr~?d*PH4 z;v|?Ico6%UDR}!I*$m7i53+FOoH>X)g4waaf+SWRI2rNgV0O+hoNPBpTuOBUbMu_W z(S3iN_7mdH=*@N~+V$Ew1;kzOHonZfSL8C|5qAZ%JF8%H*aeftyz7SZgvTDRr1$NJ zyMy^R9%Sa3dx)Ly0p^Z8$dG>K35a`wiGvi(!D#HW!D1MCf!WX2xM9$c-ETs?1(B?j@C_rOyc#q{Y7=75aG(GG8S=z-V(b9;y3<(U)l0d}Mh3M?=@@~ipc zX0$JuWBBe&=rK|R*$OcaGWn7@;>vn!Fb^rQAjg?Q1pXVC`(+vKJ!^$Hr22t5*15r!Mi9MBeV8q72oI4ftrjMxIx;<1}n_b4OY2S+}sgEUMi%pHh$ zD42&i_!)@|19P4wt$o2+%UG7=dH=Cp#e4gm9T zTUw*QT%f)^5X?D_WC!85C25TYbE^7w44B7eCCgwuS6X8+Z&_O7FtR1B@nG6HX-xog zt}U&D!CWGZ$VA)^)#DH_k19zx3Cu;xZ!-2!Yzmn3bMo6m@ms~Ff|>OsI}FSjNogI9 zR#{rpz&zTJmJQ}iOIp*xTwIXW5n!HZOY2B5kIzVJ2AHR2rF9gTXE@TD3Fi5Rw2nqr zmewpV&vT@8445YPhQ3Fi)|hwFJzQlyy9q=VT>YicCd00nC##lAQ?VQde3h zf%*56w3dOnN?FUnT9*5ASWhas&~z`Rhge}H*&L9$c9 zyhR$3)4;sWlIH1P{xd19Gr;^;PFiPzd2v}bFhaat(9P2W=QK? z?4hEZ2j&%?WUIi0lC*MQUXzj5`KTZ(tqZ`s(v{YQU|v;_)vAwJ&r0hG%$t$cm0-Gxt;W2bWB}$3>f5Wp%$Fs*8q77Wv|KQ+ElKMd zFmF_B4VdedUmnc+6}uM9$CTf7VBRY`MAm|Nr~3AK?2(l41~Auo(z+4MyHt;V;-34G z-2~lQE{Ro1P@%90hpyxWr2ZD8K6;@yr~Y{~8b^KtcU5zKoG z$^MN|RNr;Ta+2MNnzPbc59S?~wC)1)K2KVAgIQF5_h7t&WcPykA4^*If%%{zt^2`z zNE(p`(DJ3}f%&i}t^a`eh%2oJ!F)#=k%z#1G9%50!F(zutw+Fo(UI1pV7`}>)??Ts zE3L=T&z07H!FmxABjbF@_7FHos3*_U8` zoRQX77_Tg?ufhDEvdUn7Yf1JEm_MeZ^(~m+XQlNWn7=#H`X0LHKte-GPQnH^R-C#)T7cf7wrS&UXC29Qz=9kil{EmJ(Y5oD`7lyDJBKU1q zS`Ans#iEezX-n1$((#nET0^=`L0U0LZ(&HQ5z_5EX|;j$mMTgUq>}}$zyH-oge!oVIK(a(|A=9n!j ztxk|`osw2(^z)_F1=8IW>k8?ZBUv{{cQB;Y9nzb5(&~Zgg%N4!3F*!SY4w71V@XLkNO$w3)fdvc+tS(!(mPwy+8WY*%F_B9q<6?js~`H6 zq_qvC`zotHr28wsZPCw@-wuHEwzjmkgYAYbei>=)0O{?85oy>F(z_+4wG*Vb zNl7aO>75kY8PdB56loX;={*c-?E+~-`RxknR7tWy_-#&FyFq#@OIo|5Rgl(TNDs+M zYY)ufN^1zD|0aw`!=9+#k=9<2-Z3Suy|D(WuZaqL$Ah6s;gCMimTZ4W?^~AE2uSafmDWf|?{7%!0A#+jMnQU% zBdr55p7J{g(wU58qcO58tuc@u>PagD=?Rv!#zOj_g0#j#dYmJz@sJ*)qD+AFu#{v6 zLwdL+t%;D{+mY5GkRGePodoHTo@A3DeSj;iDUd!mC#^$KUs76AAwAlV)?wJ!mDb^y zw=At`kRD%>mJR8N!iY3X$C2@+bp)j62qV&PB&263YX+nzr6fBFEmvAIAwAiV*3poj zrr0b zK7sgcC1J&i5Pu;ltfspl@o!67e?Y>|39IcM_@72H(i#ql4Jm0&g+$qt)?xUA$eI5G DPv{qe literal 0 HcmV?d00001 diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p2t b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p2t new file mode 100644 index 0000000..16daf53 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p2t @@ -0,0 +1,9 @@ +-w +-l 5 +-i 6 +-n 1 +-t 1 +-s 1 +-c 0 +-e 0 +-exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p3t b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p3t new file mode 100644 index 0000000..e625c68 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p3t @@ -0,0 +1,5 @@ +-rem +-distrce +-log "RAM2GS_LCMXO256C_impl1.log" +-o "RAM2GS_LCMXO256C_impl1.csv" +-pr "RAM2GS_LCMXO256C_impl1.prf" diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pad b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pad new file mode 100644 index 0000000..4582186 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pad @@ -0,0 +1,271 @@ +PAD Specification File +*************************** + +PART TYPE: LCMXO256C +Performance Grade: 3 +PACKAGE: TQFP100 +Package Status: Final Version 1.19 + +Tue Aug 15 05:03:28 2023 + +Pinout by Port Name: ++-----------+----------+---------------+------+------------------------------+ +| Port Name | Pin/Bank | Buffer Type | Site | Properties | ++-----------+----------+---------------+------+------------------------------+ +| CROW[0] | 32/1 | LVCMOS33_IN | PB2C | SLEW:FAST PULL:UP | +| CROW[1] | 34/1 | LVCMOS33_IN | PB2D | SLEW:FAST PULL:UP | +| Din[0] | 21/1 | LVCMOS33_IN | PL8A | SLEW:FAST PULL:UP | +| Din[1] | 15/1 | LVCMOS33_IN | PL6A | SLEW:FAST PULL:UP | +| Din[2] | 14/1 | LVCMOS33_IN | PL5D | SLEW:FAST PULL:UP | +| Din[3] | 16/1 | LVCMOS33_IN | PL6B | SLEW:FAST PULL:UP | +| Din[4] | 18/1 | LVCMOS33_IN | PL7B | SLEW:FAST PULL:UP | +| Din[5] | 17/1 | LVCMOS33_IN | PL7A | SLEW:FAST PULL:UP | +| Din[6] | 20/1 | LVCMOS33_IN | PL7D | SLEW:FAST PULL:UP | +| Din[7] | 19/1 | LVCMOS33_IN | PL7C | SLEW:FAST PULL:UP | +| Dout[0] | 1/1 | LVCMOS33_OUT | PL2A | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[1] | 7/1 | LVCMOS33_OUT | PL4A | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[2] | 8/1 | LVCMOS33_OUT | PL4B | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[3] | 6/1 | LVCMOS33_OUT | PL3D | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[4] | 4/1 | LVCMOS33_OUT | PL3B | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[5] | 5/1 | LVCMOS33_OUT | PL3C | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[6] | 2/1 | LVCMOS33_OUT | PL2B | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[7] | 3/1 | LVCMOS33_OUT | PL3A | DRIVE:8mA SLEW:FAST PULL:UP | +| LED | 57/0 | LVCMOS33_OUT | PR7B | DRIVE:8mA SLEW:FAST PULL:UP | +| MAin[0] | 23/1 | LVCMOS33_IN | PL9A | SLEW:FAST PULL:UP | +| MAin[1] | 38/1 | LVCMOS33_IN | PB3C | SLEW:FAST PULL:UP | +| MAin[2] | 37/1 | LVCMOS33_IN | PB3B | SLEW:FAST PULL:UP | +| MAin[3] | 47/1 | LVCMOS33_IN | PB5A | SLEW:FAST PULL:UP | +| MAin[4] | 46/1 | LVCMOS33_IN | PB4D | SLEW:FAST PULL:UP | +| MAin[5] | 45/1 | LVCMOS33_IN | PB4C | SLEW:FAST PULL:UP | +| MAin[6] | 49/1 | LVCMOS33_IN | PB5C | SLEW:FAST PULL:UP | +| MAin[7] | 44/1 | LVCMOS33_IN | PB4B | SLEW:FAST PULL:UP | +| MAin[8] | 50/1 | LVCMOS33_IN | PB5D | SLEW:FAST PULL:UP | +| MAin[9] | 51/0 | LVCMOS33_IN | PR9B | SLEW:FAST PULL:UP | +| PHI2 | 39/1 | LVCMOS33_IN | PB3D | SLEW:FAST PULL:UP | +| RA[0] | 98/0 | LVCMOS33_OUT | PT2C | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[10] | 87/0 | LVCMOS33_OUT | PT3D | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[11] | 79/0 | LVCMOS33_OUT | PT5A | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[1] | 89/0 | LVCMOS33_OUT | PT3C | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[2] | 94/0 | LVCMOS33_OUT | PT3A | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[3] | 97/0 | LVCMOS33_OUT | PT2D | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[4] | 99/0 | LVCMOS33_OUT | PT2B | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[5] | 95/0 | LVCMOS33_OUT | PT2F | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[6] | 91/0 | LVCMOS33_OUT | PT3B | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[7] | 100/0 | LVCMOS33_OUT | PT2A | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[8] | 96/0 | LVCMOS33_OUT | PT2E | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[9] | 85/0 | LVCMOS33_OUT | PT4B | DRIVE:8mA SLEW:FAST PULL:UP | +| RBA[0] | 63/0 | LVCMOS33_OUT | PR5D | DRIVE:8mA SLEW:FAST PULL:UP | +| RBA[1] | 83/0 | LVCMOS33_OUT | PT4C | DRIVE:8mA SLEW:FAST PULL:UP | +| RCKE | 82/0 | LVCMOS33_OUT | PT4D | DRIVE:8mA SLEW:FAST PULL:UP | +| RCLK | 86/0 | LVCMOS33_IN | PT4A | SLEW:FAST PULL:UP | +| RDQMH | 76/0 | LVCMOS33_OUT | PR2A | DRIVE:8mA SLEW:FAST PULL:UP | +| RDQML | 61/0 | LVCMOS33_OUT | PR6A | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[0] | 64/0 | LVCMOS33_BIDI | PR5C | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[1] | 65/0 | LVCMOS33_BIDI | PR5B | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[2] | 66/0 | LVCMOS33_BIDI | PR5A | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[3] | 67/0 | LVCMOS33_BIDI | PR4B | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[4] | 68/0 | LVCMOS33_BIDI | PR4A | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[5] | 69/0 | LVCMOS33_BIDI | PR3D | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[6] | 70/0 | LVCMOS33_BIDI | PR3C | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[7] | 71/0 | LVCMOS33_BIDI | PR3B | DRIVE:8mA SLEW:FAST PULL:UP | +| UFMCLK | 58/0 | LVCMOS33_OUT | PR7A | DRIVE:8mA SLEW:FAST PULL:UP | +| UFMSDI | 56/0 | LVCMOS33_OUT | PR7C | DRIVE:8mA SLEW:FAST PULL:UP | +| UFMSDO | 55/0 | LVCMOS33_IN | PR7D | SLEW:FAST PULL:UP | +| nCCAS | 27/1 | LVCMOS33_IN | PL9B | SLEW:FAST PULL:UP | +| nCRAS | 43/1 | LVCMOS33_IN | PB4A | SLEW:FAST PULL:UP | +| nFWE | 22/1 | LVCMOS33_IN | PL8B | SLEW:FAST PULL:UP | +| nRCAS | 78/0 | LVCMOS33_OUT | PT5B | DRIVE:8mA SLEW:FAST PULL:UP | +| nRCS | 77/0 | LVCMOS33_OUT | PT5C | DRIVE:8mA SLEW:FAST PULL:UP | +| nRRAS | 73/0 | LVCMOS33_OUT | PR2B | DRIVE:8mA SLEW:FAST PULL:UP | +| nRWE | 72/0 | LVCMOS33_OUT | PR3A | DRIVE:8mA SLEW:FAST PULL:UP | +| nUFMCS | 53/0 | LVCMOS33_OUT | PR8B | DRIVE:8mA SLEW:FAST PULL:UP | ++-----------+----------+---------------+------+------------------------------+ + +Vccio by Bank: ++------+-------+ +| Bank | Vccio | ++------+-------+ +| 0 | 3.3V | +| 1 | 3.3V | ++------+-------+ + +Vref by Bank: ++------+-----+-----------------+---------+ +| Vref | Pin | Bank # / Vref # | Load(s) | ++------+-----+-----------------+---------+ ++------+-----+-----------------+---------+ + +Pinout by Pin Number: ++----------+---------------------+------------+---------------+------+---------------+ +| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | ++----------+---------------------+------------+---------------+------+---------------+ +| 1/1 | Dout[0] | LOCATED | LVCMOS33_OUT | PL2A | | +| 2/1 | Dout[6] | LOCATED | LVCMOS33_OUT | PL2B | | +| 3/1 | Dout[7] | LOCATED | LVCMOS33_OUT | PL3A | | +| 4/1 | Dout[4] | LOCATED | LVCMOS33_OUT | PL3B | | +| 5/1 | Dout[5] | LOCATED | LVCMOS33_OUT | PL3C | | +| 6/1 | Dout[3] | LOCATED | LVCMOS33_OUT | PL3D | | +| 7/1 | Dout[1] | LOCATED | LVCMOS33_OUT | PL4A | | +| 8/1 | Dout[2] | LOCATED | LVCMOS33_OUT | PL4B | | +| 9/1 | unused, PULL:UP | | | PL5A | | +| 11/1 | unused, PULL:UP | | | PL5B | | +| 13/1 | unused, PULL:UP | | | PL5C | | +| 14/1 | Din[2] | LOCATED | LVCMOS33_IN | PL5D | GSR_PADN | +| 15/1 | Din[1] | LOCATED | LVCMOS33_IN | PL6A | | +| 16/1 | Din[3] | LOCATED | LVCMOS33_IN | PL6B | TSALLPAD | +| 17/1 | Din[5] | LOCATED | LVCMOS33_IN | PL7A | | +| 18/1 | Din[4] | LOCATED | LVCMOS33_IN | PL7B | | +| 19/1 | Din[7] | LOCATED | LVCMOS33_IN | PL7C | | +| 20/1 | Din[6] | LOCATED | LVCMOS33_IN | PL7D | | +| 21/1 | Din[0] | LOCATED | LVCMOS33_IN | PL8A | | +| 22/1 | nFWE | LOCATED | LVCMOS33_IN | PL8B | | +| 23/1 | MAin[0] | LOCATED | LVCMOS33_IN | PL9A | | +| 27/1 | nCCAS | LOCATED | LVCMOS33_IN | PL9B | | +| 29/1 | unused, PULL:UP | | | PB2A | | +| 30/1 | unused, PULL:UP | | | PB2B | | +| 32/1 | CROW[0] | LOCATED | LVCMOS33_IN | PB2C | | +| 34/1 | CROW[1] | LOCATED | LVCMOS33_IN | PB2D | | +| 36/1 | unused, PULL:UP | | | PB3A | PCLKT1_1 | +| 37/1 | MAin[2] | LOCATED | LVCMOS33_IN | PB3B | | +| 38/1 | MAin[1] | LOCATED | LVCMOS33_IN | PB3C | PCLKT1_0 | +| 39/1 | PHI2 | LOCATED | LVCMOS33_IN | PB3D | | +| 43/1 | nCRAS | LOCATED | LVCMOS33_IN | PB4A | | +| 44/1 | MAin[7] | LOCATED | LVCMOS33_IN | PB4B | | +| 45/1 | MAin[5] | LOCATED | LVCMOS33_IN | PB4C | | +| 46/1 | MAin[4] | LOCATED | LVCMOS33_IN | PB4D | | +| 47/1 | MAin[3] | LOCATED | LVCMOS33_IN | PB5A | | +| 49/1 | MAin[6] | LOCATED | LVCMOS33_IN | PB5C | | +| 50/1 | MAin[8] | LOCATED | LVCMOS33_IN | PB5D | | +| 51/0 | MAin[9] | LOCATED | LVCMOS33_IN | PR9B | | +| 52/0 | unused, PULL:UP | | | PR9A | | +| 53/0 | nUFMCS | LOCATED | LVCMOS33_OUT | PR8B | | +| 54/0 | unused, PULL:UP | | | PR8A | | +| 55/0 | UFMSDO | LOCATED | LVCMOS33_IN | PR7D | | +| 56/0 | UFMSDI | LOCATED | LVCMOS33_OUT | PR7C | | +| 57/0 | LED | LOCATED | LVCMOS33_OUT | PR7B | | +| 58/0 | UFMCLK | LOCATED | LVCMOS33_OUT | PR7A | | +| 59/0 | unused, PULL:UP | | | PR6B | | +| 61/0 | RDQML | LOCATED | LVCMOS33_OUT | PR6A | | +| 63/0 | RBA[0] | LOCATED | LVCMOS33_OUT | PR5D | | +| 64/0 | RD[0] | LOCATED | LVCMOS33_BIDI | PR5C | | +| 65/0 | RD[1] | LOCATED | LVCMOS33_BIDI | PR5B | | +| 66/0 | RD[2] | LOCATED | LVCMOS33_BIDI | PR5A | | +| 67/0 | RD[3] | LOCATED | LVCMOS33_BIDI | PR4B | | +| 68/0 | RD[4] | LOCATED | LVCMOS33_BIDI | PR4A | | +| 69/0 | RD[5] | LOCATED | LVCMOS33_BIDI | PR3D | | +| 70/0 | RD[6] | LOCATED | LVCMOS33_BIDI | PR3C | | +| 71/0 | RD[7] | LOCATED | LVCMOS33_BIDI | PR3B | | +| 72/0 | nRWE | LOCATED | LVCMOS33_OUT | PR3A | | +| 73/0 | nRRAS | LOCATED | LVCMOS33_OUT | PR2B | | +| 76/0 | RDQMH | LOCATED | LVCMOS33_OUT | PR2A | | +| 77/0 | nRCS | LOCATED | LVCMOS33_OUT | PT5C | | +| 78/0 | nRCAS | LOCATED | LVCMOS33_OUT | PT5B | | +| 79/0 | RA[11] | LOCATED | LVCMOS33_OUT | PT5A | | +| 80/0 | unused, PULL:UP | | | PT4F | | +| 81/0 | unused, PULL:UP | | | PT4E | | +| 82/0 | RCKE | LOCATED | LVCMOS33_OUT | PT4D | | +| 83/0 | RBA[1] | LOCATED | LVCMOS33_OUT | PT4C | | +| 85/0 | RA[9] | LOCATED | LVCMOS33_OUT | PT4B | PCLKT0_1 | +| 86/0 | RCLK | LOCATED | LVCMOS33_IN | PT4A | PCLKT0_0 | +| 87/0 | RA[10] | LOCATED | LVCMOS33_OUT | PT3D | | +| 89/0 | RA[1] | LOCATED | LVCMOS33_OUT | PT3C | | +| 91/0 | RA[6] | LOCATED | LVCMOS33_OUT | PT3B | | +| 94/0 | RA[2] | LOCATED | LVCMOS33_OUT | PT3A | | +| 95/0 | RA[5] | LOCATED | LVCMOS33_OUT | PT2F | | +| 96/0 | RA[8] | LOCATED | LVCMOS33_OUT | PT2E | | +| 97/0 | RA[3] | LOCATED | LVCMOS33_OUT | PT2D | | +| 98/0 | RA[0] | LOCATED | LVCMOS33_OUT | PT2C | | +| 99/0 | RA[4] | LOCATED | LVCMOS33_OUT | PT2B | | +| 100/0 | RA[7] | LOCATED | LVCMOS33_OUT | PT2A | | +| PB5B/0 | unused, PULL:UP | | | PB5B | | +| PT5D/0 | unused, PULL:UP | | | PT5D | | +| TCK/1 | | | | TCK | TCK | +| TDI/1 | | | | TDI | TDI | +| TDO/1 | | | | TDO | TDO | +| TMS/1 | | | | TMS | TMS | ++----------+---------------------+------------+---------------+------+---------------+ + + +List of All Pins' Locate Preferences Based on Final Placement After PAR +to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): + +LOCATE COMP "CROW[0]" SITE "32"; +LOCATE COMP "CROW[1]" SITE "34"; +LOCATE COMP "Din[0]" SITE "21"; +LOCATE COMP "Din[1]" SITE "15"; +LOCATE COMP "Din[2]" SITE "14"; +LOCATE COMP "Din[3]" SITE "16"; +LOCATE COMP "Din[4]" SITE "18"; +LOCATE COMP "Din[5]" SITE "17"; +LOCATE COMP "Din[6]" SITE "20"; +LOCATE COMP "Din[7]" SITE "19"; +LOCATE COMP "Dout[0]" SITE "1"; +LOCATE COMP "Dout[1]" SITE "7"; +LOCATE COMP "Dout[2]" SITE "8"; +LOCATE COMP "Dout[3]" SITE "6"; +LOCATE COMP "Dout[4]" SITE "4"; +LOCATE COMP "Dout[5]" SITE "5"; +LOCATE COMP "Dout[6]" SITE "2"; +LOCATE COMP "Dout[7]" SITE "3"; +LOCATE COMP "LED" SITE "57"; +LOCATE COMP "MAin[0]" SITE "23"; +LOCATE COMP "MAin[1]" SITE "38"; +LOCATE COMP "MAin[2]" SITE "37"; +LOCATE COMP "MAin[3]" SITE "47"; +LOCATE COMP "MAin[4]" SITE "46"; +LOCATE COMP "MAin[5]" SITE "45"; +LOCATE COMP "MAin[6]" SITE "49"; +LOCATE COMP "MAin[7]" SITE "44"; +LOCATE COMP "MAin[8]" SITE "50"; +LOCATE COMP "MAin[9]" SITE "51"; +LOCATE COMP "PHI2" SITE "39"; +LOCATE COMP "RA[0]" SITE "98"; +LOCATE COMP "RA[10]" SITE "87"; +LOCATE COMP "RA[11]" SITE "79"; +LOCATE COMP "RA[1]" SITE "89"; +LOCATE COMP "RA[2]" SITE "94"; +LOCATE COMP "RA[3]" SITE "97"; +LOCATE COMP "RA[4]" SITE "99"; +LOCATE COMP "RA[5]" SITE "95"; +LOCATE COMP "RA[6]" SITE "91"; +LOCATE COMP "RA[7]" SITE "100"; +LOCATE COMP "RA[8]" SITE "96"; +LOCATE COMP "RA[9]" SITE "85"; +LOCATE COMP "RBA[0]" SITE "63"; +LOCATE COMP "RBA[1]" SITE "83"; +LOCATE COMP "RCKE" SITE "82"; +LOCATE COMP "RCLK" SITE "86"; +LOCATE COMP "RDQMH" SITE "76"; +LOCATE COMP "RDQML" SITE "61"; +LOCATE COMP "RD[0]" SITE "64"; +LOCATE COMP "RD[1]" SITE "65"; +LOCATE COMP "RD[2]" SITE "66"; +LOCATE COMP "RD[3]" SITE "67"; +LOCATE COMP "RD[4]" SITE "68"; +LOCATE COMP "RD[5]" SITE "69"; +LOCATE COMP "RD[6]" SITE "70"; +LOCATE COMP "RD[7]" SITE "71"; +LOCATE COMP "UFMCLK" SITE "58"; +LOCATE COMP "UFMSDI" SITE "56"; +LOCATE COMP "UFMSDO" SITE "55"; +LOCATE COMP "nCCAS" SITE "27"; +LOCATE COMP "nCRAS" SITE "43"; +LOCATE COMP "nFWE" SITE "22"; +LOCATE COMP "nRCAS" SITE "78"; +LOCATE COMP "nRCS" SITE "77"; +LOCATE COMP "nRRAS" SITE "73"; +LOCATE COMP "nRWE" SITE "72"; +LOCATE COMP "nUFMCS" SITE "53"; + + + + + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:28 2023 + diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.par b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.par new file mode 100644 index 0000000..e40d29a --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.par @@ -0,0 +1,263 @@ +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:23 2023 + +C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO256C_impl1.p2t +RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir +RAM2GS_LCMXO256C_impl1.prf -gui -msgset +D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml + + +Preference file: RAM2GS_LCMXO256C_impl1.prf. + +Level/ Number Worst Timing Worst Timing Run NCD +Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status +---------- -------- ----- ------ ----------- ----------- ---- ------ +5_1 * 0 -10.044 913247 0.273 0 06 Completed + +* : Design saved. + +Total (real) run time for 1-seed: 6 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd" +Tue Aug 15 05:03:23 2023 + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir/5_1.ncd RAM2GS_LCMXO256C_impl1.prf +Preference file: RAM2GS_LCMXO256C_impl1.prf. +Placement level-cost: 5-1. +Routing Iterations: 6 + +Loading design for application par from file RAM2GS_LCMXO256C_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application par from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +License checked out. + + +Ignore Preference Error(s): True +Device utilization summary: + + PIO (prelim) 67/79 84% used + 67/78 85% bonded + SLICE 71/128 55% used + + + +Number of Signals: 262 +Number of Connections: 662 + +Pin Constraint Summary: + 67 out of 67 pins locked (100% locked). + +The following 2 signals are selected to use the primary clock routing resources: + RCLK_c (driver: RCLK, clk load #: 40) + PHI2_c (driver: PHI2, clk load #: 13) + +The following 1 signal is selected to use the secondary clock routing resources: + nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0) + +No signal is selected as Global Set/Reset. +Starting Placer Phase 0. +........ +Finished Placer Phase 0. REAL time: 0 secs + +Starting Placer Phase 1. +.............. +Placer score = 831129. +Finished Placer Phase 1. REAL time: 5 secs + +Starting Placer Phase 2. +. +Placer score = 828350 +Finished Placer Phase 2. REAL time: 5 secs + + +------------------ Clock Report ------------------ + +Global Clock Resources: + CLK_PIN : 1 out of 4 (25%) + General PIO: 1 out of 80 (1%) + +Global Clocks: + PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT4A)", clk load = 40 + PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB3D)", clk load = 13 + SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB4A)", clk load = 7, ce load = 0, sr load = 0 + + PRIMARY : 2 out of 4 (50%) + SECONDARY: 1 out of 4 (25%) + +--------------- End of Clock Report --------------- + + +I/O Usage Summary (final): + 67 out of 79 (84.8%) PIO sites used. + 67 out of 78 (85.9%) bonded PIO sites used. + Number of PIO comps: 67; differential: 0. + Number of Vref pins used: 0. + +I/O Bank Usage Summary: ++----------+----------------+------------+------------+------------+ +| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | ++----------+----------------+------------+------------+------------+ +| 0 | 36 / 41 ( 87%) | 3.3V | - | - | +| 1 | 31 / 37 ( 83%) | 3.3V | - | - | ++----------+----------------+------------+------------+------------+ + +Total placer CPU time: 4 secs + +Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd. + +0 connections routed; 662 unrouted. +Starting router resource preassignment +WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew. +WARNING - par: The driver of secondary clock net nCRAS_c is not placed on one of the PIO sites dedicated for secondary clocks. This secondary clock will be routed through general routing resource and may suffer from excessive delay or skew. + +WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. + Signal=nCCAS_c loads=7 clock_loads=4 + +Completed router resource preassignment. Real time: 5 secs + +Start NBR router at 05:03:28 08/15/23 + +***************************************************************** +Info: NBR allows conflicts(one node used by more than one signal) + in the earlier iterations. In each iteration, it tries to + solve the conflicts while keeping the critical connections + routed as short as possible. The routing process is said to + be completed when no conflicts exist and all connections + are routed. +Note: NBR uses a different method to calculate timing slacks. The + worst slack and total negative slack may not be the same as + that in TRCE report. You should always run TRCE to verify + your design. +***************************************************************** + +Start NBR special constraint process at 05:03:28 08/15/23 + +Start NBR section for initial routing at 05:03:28 08/15/23 +Level 1, iteration 1 +0(0.00%) conflict; 563(85.05%) untouched conns; 712361 (nbr) score; +Estimated worst slack/total negative slack: -9.968ns/-712.361ns; real time: 5 secs +Level 2, iteration 1 +3(0.02%) conflicts; 494(74.62%) untouched conns; 697746 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-697.746ns; real time: 5 secs +Level 3, iteration 1 +6(0.05%) conflicts; 255(38.52%) untouched conns; 756550 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-756.550ns; real time: 5 secs +Level 4, iteration 1 +17(0.14%) conflicts; 0(0.00%) untouched conn; 761255 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-761.256ns; real time: 5 secs + +Info: Initial congestion level at 75% usage is 0 +Info: Initial congestion area at 75% usage is 0 (0.00%) + +Start NBR section for normal routing at 05:03:28 08/15/23 +Level 4, iteration 1 +12(0.10%) conflicts; 0(0.00%) untouched conn; 765605 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-765.606ns; real time: 5 secs +Level 4, iteration 2 +6(0.05%) conflicts; 0(0.00%) untouched conn; 766423 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-766.424ns; real time: 5 secs +Level 4, iteration 3 +3(0.02%) conflicts; 0(0.00%) untouched conn; 769148 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-769.149ns; real time: 5 secs +Level 4, iteration 4 +3(0.02%) conflicts; 0(0.00%) untouched conn; 769148 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-769.149ns; real time: 5 secs +Level 4, iteration 5 +3(0.02%) conflicts; 0(0.00%) untouched conn; 766523 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-766.524ns; real time: 5 secs +Level 4, iteration 6 +1(0.01%) conflict; 0(0.00%) untouched conn; 766523 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-766.524ns; real time: 5 secs +Level 4, iteration 7 +1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs +Level 4, iteration 8 +1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs +Level 4, iteration 9 +1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs +Level 4, iteration 10 +0(0.00%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs + +Start NBR section for performance tuning (iteration 1) at 05:03:29 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs + +Start NBR section for re-routing at 05:03:29 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 768048 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-768.049ns; real time: 6 secs + +Start NBR section for post-routing at 05:03:29 08/15/23 + +End NBR router with 0 unrouted connection + +NBR Summary +----------- + Number of unrouted connections : 0 (0.00%) + Number of connections with timing violations : 256 (38.67%) + Estimated worst slack : -10.044ns + Timing score : 913247 +----------- +Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. + + + +WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. + Signal=nCCAS_c loads=7 clock_loads=4 + +Total CPU time 5 secs +Total REAL time: 6 secs +Completely routed. +End of route. 662 routed (100.00%); 0 unrouted. + +Hold time timing score: 0, hold timing errors: 0 + +Timing score: 913247 + +Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd. + + +All signals are completely routed. + + +PAR_SUMMARY::Run status = Completed +PAR_SUMMARY::Number of unrouted conns = 0 +PAR_SUMMARY::Worst slack> = -10.044 +PAR_SUMMARY::Timing score> = 913.247 +PAR_SUMMARY::Worst slack> = 0.273 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Number of errors = 0 + +Total CPU time to completion: 5 secs +Total REAL time to completion: 6 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.prf b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.prf new file mode 100644 index 0000000..881ee9b --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.prf @@ -0,0 +1,81 @@ +SCHEMATIC START ; +# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:03:20 2023 + +SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ; +LOCATE COMP "RD[7]" SITE "71" ; +LOCATE COMP "RD[6]" SITE "70" ; +LOCATE COMP "RD[5]" SITE "69" ; +LOCATE COMP "RD[4]" SITE "68" ; +LOCATE COMP "RD[3]" SITE "67" ; +LOCATE COMP "RD[2]" SITE "66" ; +LOCATE COMP "RD[1]" SITE "65" ; +LOCATE COMP "RD[0]" SITE "64" ; +LOCATE COMP "Dout[7]" SITE "3" ; +LOCATE COMP "Dout[6]" SITE "2" ; +LOCATE COMP "Dout[5]" SITE "5" ; +LOCATE COMP "Dout[4]" SITE "4" ; +LOCATE COMP "Dout[3]" SITE "6" ; +LOCATE COMP "Dout[2]" SITE "8" ; +LOCATE COMP "Dout[1]" SITE "7" ; +LOCATE COMP "Dout[0]" SITE "1" ; +LOCATE COMP "LED" SITE "57" ; +LOCATE COMP "RBA[1]" SITE "83" ; +LOCATE COMP "RBA[0]" SITE "63" ; +LOCATE COMP "RA[11]" SITE "79" ; +LOCATE COMP "RA[10]" SITE "87" ; +LOCATE COMP "RA[9]" SITE "85" ; +LOCATE COMP "RA[8]" SITE "96" ; +LOCATE COMP "RA[7]" SITE "100" ; +LOCATE COMP "RA[6]" SITE "91" ; +LOCATE COMP "RA[5]" SITE "95" ; +LOCATE COMP "RA[4]" SITE "99" ; +LOCATE COMP "RA[3]" SITE "97" ; +LOCATE COMP "RA[2]" SITE "94" ; +LOCATE COMP "RA[1]" SITE "89" ; +LOCATE COMP "RA[0]" SITE "98" ; +LOCATE COMP "nRCS" SITE "77" ; +LOCATE COMP "RCKE" SITE "82" ; +LOCATE COMP "nRWE" SITE "72" ; +LOCATE COMP "nRRAS" SITE "73" ; +LOCATE COMP "nRCAS" SITE "78" ; +LOCATE COMP "RDQMH" SITE "76" ; +LOCATE COMP "RDQML" SITE "61" ; +LOCATE COMP "nUFMCS" SITE "53" ; +LOCATE COMP "UFMCLK" SITE "58" ; +LOCATE COMP "UFMSDI" SITE "56" ; +LOCATE COMP "PHI2" SITE "39" ; +LOCATE COMP "MAin[9]" SITE "51" ; +LOCATE COMP "MAin[8]" SITE "50" ; +LOCATE COMP "MAin[7]" SITE "44" ; +LOCATE COMP "MAin[6]" SITE "49" ; +LOCATE COMP "MAin[5]" SITE "45" ; +LOCATE COMP "MAin[4]" SITE "46" ; +LOCATE COMP "MAin[3]" SITE "47" ; +LOCATE COMP "MAin[2]" SITE "37" ; +LOCATE COMP "MAin[1]" SITE "38" ; +LOCATE COMP "MAin[0]" SITE "23" ; +LOCATE COMP "CROW[1]" SITE "34" ; +LOCATE COMP "CROW[0]" SITE "32" ; +LOCATE COMP "Din[7]" SITE "19" ; +LOCATE COMP "Din[6]" SITE "20" ; +LOCATE COMP "Din[5]" SITE "17" ; +LOCATE COMP "Din[4]" SITE "18" ; +LOCATE COMP "Din[3]" SITE "16" ; +LOCATE COMP "Din[2]" SITE "14" ; +LOCATE COMP "Din[1]" SITE "15" ; +LOCATE COMP "Din[0]" SITE "21" ; +LOCATE COMP "nCCAS" SITE "27" ; +LOCATE COMP "nCRAS" SITE "43" ; +LOCATE COMP "nFWE" SITE "22" ; +LOCATE COMP "RCLK" SITE "86" ; +LOCATE COMP "UFMSDO" SITE "55" ; +SCHEMATIC END ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +COMMERCIAL ; + +// No timing preferences found. TRCE invokes auto-generation of timing preferences +// Section Autogen +FREQUENCY NET "RCLK_c" 283.768 MHz ; +FREQUENCY NET "PHI2_c" 120.077 MHz ; +// End Section Autogen diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pt b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pt new file mode 100644 index 0000000..916dbc3 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pt @@ -0,0 +1,10 @@ +-v +10 + + + + +-gt +-sethld +-sp 3 +-sphld m diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.t2b b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.t2b new file mode 100644 index 0000000..aa05f83 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.t2b @@ -0,0 +1,2 @@ + +-g ES:No diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.tw1 b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.tw1 new file mode 100644 index 0000000..2cd86e2 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.tw1 @@ -0,0 +1,353 @@ + +Loading design for application trce from file ram2gs_lcmxo256c_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:21 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf +Design file: ram2gs_lcmxo256c_impl1_map.ncd +Preference file: ram2gs_lcmxo256c_impl1.prf +Device,speed: LCMXO256C,3 +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +Report Type: based on TRACE automatically generated preferences +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ; + 383 items scored, 213 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path exceeds requirements by 5.089ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i14 (from RCLK_c +) + Destination: FF Data in n8MEGEN_418 (to RCLK_c +) + + Delay: 8.369ns (24.4% logic, 75.6% route), 5 logic levels. + + Constraint Details: + + 8.369ns physical path delay SLICE_1 to SLICE_56 exceeds + 3.524ns delay constraint less + 0.244ns CE_SET requirement (totaling 3.280ns) by 5.089ns + + Physical Path Details: + + Data path SLICE_1 to SLICE_56: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_1.CLK to SLICE_1.Q0 SLICE_1 (from RCLK_c) +ROUTE 5 e 1.441 SLICE_1.Q0 to SLICE_90.C1 FS_14 +CTOF_DEL --- 0.371 SLICE_90.C1 to SLICE_90.F1 SLICE_90 +ROUTE 1 e 1.441 SLICE_90.F1 to SLICE_75.B0 n2328 +CTOF_DEL --- 0.371 SLICE_75.B0 to SLICE_75.F0 SLICE_75 +ROUTE 2 e 1.441 SLICE_75.F0 to SLICE_87.B1 n2214 +CTOF_DEL --- 0.371 SLICE_87.B1 to SLICE_87.F1 SLICE_87 +ROUTE 1 e 0.561 SLICE_87.F1 to SLICE_87.A0 n7 +CTOF_DEL --- 0.371 SLICE_87.A0 to SLICE_87.F0 SLICE_87 +ROUTE 1 e 1.441 SLICE_87.F0 to SLICE_56.CE RCLK_c_enable_11 (to RCLK_c) + -------- + 8.369 (24.4% logic, 75.6% route), 5 logic levels. + +Warning: 116.104MHz is the maximum frequency for this preference. + + +================================================================================ +Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ; + 106 items scored, 97 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path exceeds requirements by 7.535ns (weighted slack = -15.070ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i0 (from PHI2_c +) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 11.061ns (21.8% logic, 78.2% route), 6 logic levels. + + Constraint Details: + + 11.061ns physical path delay SLICE_88 to SLICE_14 exceeds + 4.164ns delay constraint less + 0.638ns LSR_SET requirement (totaling 3.526ns) by 7.535ns + + Physical Path Details: + + Data path SLICE_88 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_88.CLK to SLICE_88.Q0 SLICE_88 (from PHI2_c) +ROUTE 1 e 1.441 SLICE_88.Q0 to SLICE_97.D0 Bank_0 +CTOF_DEL --- 0.371 SLICE_97.D0 to SLICE_97.F0 SLICE_97 +ROUTE 1 e 1.441 SLICE_97.F0 to SLICE_81.B0 n2314 +CTOF_DEL --- 0.371 SLICE_81.B0 to SLICE_81.F0 SLICE_81 +ROUTE 1 e 1.441 SLICE_81.F0 to SLICE_18.B1 n26 +CTOF_DEL --- 0.371 SLICE_18.B1 to SLICE_18.F1 SLICE_18 +ROUTE 8 e 1.441 SLICE_18.F1 to SLICE_89.B0 n1326 +CTOF_DEL --- 0.371 SLICE_89.B0 to SLICE_89.F0 SLICE_89 +ROUTE 1 e 1.441 SLICE_89.F0 to SLICE_79.C0 n1280 +CTOF_DEL --- 0.371 SLICE_79.C0 to SLICE_79.F0 SLICE_79 +ROUTE 2 e 1.441 SLICE_79.F0 to SLICE_14.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 11.061 (21.8% logic, 78.2% route), 6 logic levels. + +Warning: 42.739MHz is the maximum frequency for this preference. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY NET "RCLK_c" 283.768000 MHz ; | 283.768 MHz| 116.104 MHz| 5 * + | | | +FREQUENCY NET "PHI2_c" 120.077000 MHz ; | 120.077 MHz| 42.739 MHz| 6 * + | | | +---------------------------------------------------------------------------- + + +2 preferences(marked by "*" above) not met. + +---------------------------------------------------------------------------- +Critical Nets | Loads| Errors| % of total +---------------------------------------------------------------------------- +n1326 | 8| 96| 30.97% + | | | +n26 | 1| 72| 23.23% + | | | +---------------------------------------------------------------------------- + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 + Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Setup): +--------------- + +Timing errors: 310 Score: 1346529 +Cumulative negative slack: 874289 + +Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:21 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf +Design file: ram2gs_lcmxo256c_impl1_map.ncd +Preference file: ram2gs_lcmxo256c_impl1.prf +Device,speed: LCMXO256C,M +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ; + 383 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.342ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i4 (from RCLK_c +) + Destination: FF Data in IS_FSM__i5 (to RCLK_c +) + + Delay: 0.325ns (38.8% logic, 61.2% route), 1 logic levels. + + Constraint Details: + + 0.325ns physical path delay SLICE_100 to SLICE_100 meets + -0.017ns M_HLD and + 0.000ns delay constraint requirement (totaling -0.017ns) by 0.342ns + + Physical Path Details: + + Data path SLICE_100 to SLICE_100: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 SLICE_100.CLK to SLICE_100.Q0 SLICE_100 (from RCLK_c) +ROUTE 1 e 0.199 SLICE_100.Q0 to SLICE_100.M1 n736 (to RCLK_c) + -------- + 0.325 (38.8% logic, 61.2% route), 1 logic levels. + + +================================================================================ +Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ; + 106 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.430ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted_406 (from PHI2_c -) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 0.411ns (51.3% logic, 48.7% route), 2 logic levels. + + Constraint Details: + + 0.411ns physical path delay SLICE_14 to SLICE_14 meets + -0.019ns DIN_HLD and + 0.000ns delay constraint requirement (totaling -0.019ns) by 0.430ns + + Physical Path Details: + + Data path SLICE_14 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 SLICE_14.CLK to SLICE_14.Q0 SLICE_14 (from PHI2_c) +ROUTE 2 e 0.199 SLICE_14.Q0 to SLICE_14.C0 C1Submitted +CTOF_DEL --- 0.074 SLICE_14.C0 to SLICE_14.F0 SLICE_14 +ROUTE 1 e 0.001 SLICE_14.F0 to SLICE_14.DI0 n6_adj_3 (to PHI2_c) + -------- + 0.411 (51.3% logic, 48.7% route), 2 logic levels. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference(MIN Delays) | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY NET "RCLK_c" 283.768000 MHz ; | 0.000 ns| 0.342 ns| 1 + | | | +FREQUENCY NET "PHI2_c" 120.077000 MHz ; | 0.000 ns| 0.430 ns| 2 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 + Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 310 (setup), 0 (hold) +Score: 1346529 (setup), 0 (hold) +Cumulative negative slack: 874289 (874289+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.twr b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.twr new file mode 100644 index 0000000..5fca6c6 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.twr @@ -0,0 +1,2170 @@ + +Loading design for application trce from file ram2gs_lcmxo256c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:29 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf +Design file: ram2gs_lcmxo256c_impl1.ncd +Preference file: ram2gs_lcmxo256c_impl1.prf +Device,speed: LCMXO256C,3 +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +Report Type: based on TRACE automatically generated preferences +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ; + 383 items scored, 231 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path exceeds requirements by 4.182ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i17 (from RCLK_c +) + Destination: FF Data in UFMCLK_416 (to RCLK_c +) + + Delay: 7.525ns (27.2% logic, 72.8% route), 5 logic levels. + + Constraint Details: + + 7.525ns physical path delay SLICE_8 to SLICE_43 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.181ns DIN_SET requirement (totaling 3.343ns) by 4.182ns + + Physical Path Details: + + Data path SLICE_8 to SLICE_43: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R5C5A.CLK to R5C5A.Q1 SLICE_8 (from RCLK_c) +ROUTE 4 1.509 R5C5A.Q1 to R6C4C.A1 FS_17 +CTOF_DEL --- 0.371 R6C4C.A1 to R6C4C.F1 SLICE_68 +ROUTE 2 1.503 R6C4C.F1 to R7C5B.A1 n2471 +CTOF_DEL --- 0.371 R7C5B.A1 to R7C5B.F1 SLICE_44 +ROUTE 2 1.972 R7C5B.F1 to R3C2B.C1 n2462 +CTOF_DEL --- 0.371 R3C2B.C1 to R3C2B.F1 SLICE_43 +ROUTE 1 0.497 R3C2B.F1 to R3C2B.C0 n1160 +CTOF_DEL --- 0.371 R3C2B.C0 to R3C2B.F0 SLICE_43 +ROUTE 1 0.000 R3C2B.F0 to R3C2B.DI0 UFMCLK_N_224 (to RCLK_c) + -------- + 7.525 (27.2% logic, 72.8% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_8: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R5C5A.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_43: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R3C2B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 3.947ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i16 (from RCLK_c +) + Destination: FF Data in UFMCLK_416 (to RCLK_c +) + + Delay: 7.290ns (28.0% logic, 72.0% route), 5 logic levels. + + Constraint Details: + + 7.290ns physical path delay SLICE_8 to SLICE_43 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.181ns DIN_SET requirement (totaling 3.343ns) by 3.947ns + + Physical Path Details: + + Data path SLICE_8 to SLICE_43: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R5C5A.CLK to R5C5A.Q0 SLICE_8 (from RCLK_c) +ROUTE 5 1.526 R5C5A.Q0 to R5C2D.A0 FS_16 +CTOF_DEL --- 0.371 R5C2D.A0 to R5C2D.F0 SLICE_90 +ROUTE 1 1.251 R5C2D.F0 to R7C5B.D1 n2470 +CTOF_DEL --- 0.371 R7C5B.D1 to R7C5B.F1 SLICE_44 +ROUTE 2 1.972 R7C5B.F1 to R3C2B.C1 n2462 +CTOF_DEL --- 0.371 R3C2B.C1 to R3C2B.F1 SLICE_43 +ROUTE 1 0.497 R3C2B.F1 to R3C2B.C0 n1160 +CTOF_DEL --- 0.371 R3C2B.C0 to R3C2B.F0 SLICE_43 +ROUTE 1 0.000 R3C2B.F0 to R3C2B.DI0 UFMCLK_N_224 (to RCLK_c) + -------- + 7.290 (28.0% logic, 72.0% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_8: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R5C5A.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_43: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R3C2B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 3.864ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i12 (from RCLK_c +) + Destination: FF Data in n8MEGEN_418 (to RCLK_c +) + + Delay: 7.144ns (28.6% logic, 71.4% route), 5 logic levels. + + Constraint Details: + + 7.144ns physical path delay SLICE_3 to SLICE_56 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.244ns CE_SET requirement (totaling 3.280ns) by 3.864ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_56: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R5C4C.CLK to R5C4C.Q0 SLICE_3 (from RCLK_c) +ROUTE 4 2.038 R5C4C.Q0 to R5C2D.B1 FS_12 +CTOF_DEL --- 0.371 R5C2D.B1 to R5C2D.F1 SLICE_90 +ROUTE 1 0.887 R5C2D.F1 to R4C2D.C0 n2328 +CTOF_DEL --- 0.371 R4C2D.C0 to R4C2D.F0 SLICE_75 +ROUTE 2 0.513 R4C2D.F0 to R4C2C.C1 n2214 +CTOF_DEL --- 0.371 R4C2C.C1 to R4C2C.F1 SLICE_87 +ROUTE 1 0.497 R4C2C.F1 to R4C2C.C0 n7 +CTOF_DEL --- 0.371 R4C2C.C0 to R4C2C.F0 SLICE_87 +ROUTE 1 1.165 R4C2C.F0 to R6C2C.CE RCLK_c_enable_11 (to RCLK_c) + -------- + 7.144 (28.6% logic, 71.4% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R5C4C.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_56: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R6C2C.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 3.702ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i13 (from RCLK_c +) + Destination: FF Data in UFMCLK_416 (to RCLK_c +) + + Delay: 7.045ns (29.0% logic, 71.0% route), 5 logic levels. + + Constraint Details: + + 7.045ns physical path delay SLICE_3 to SLICE_43 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.181ns DIN_SET requirement (totaling 3.343ns) by 3.702ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_43: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R5C4C.CLK to R5C4C.Q1 SLICE_3 (from RCLK_c) +ROUTE 3 1.057 R5C4C.Q1 to R5C2B.A1 FS_13 +CTOF_DEL --- 0.371 R5C2B.A1 to R5C2B.F1 SLICE_94 +ROUTE 3 1.475 R5C2B.F1 to R7C5B.C1 n2272 +CTOF_DEL --- 0.371 R7C5B.C1 to R7C5B.F1 SLICE_44 +ROUTE 2 1.972 R7C5B.F1 to R3C2B.C1 n2462 +CTOF_DEL --- 0.371 R3C2B.C1 to R3C2B.F1 SLICE_43 +ROUTE 1 0.497 R3C2B.F1 to R3C2B.C0 n1160 +CTOF_DEL --- 0.371 R3C2B.C0 to R3C2B.F0 SLICE_43 +ROUTE 1 0.000 R3C2B.F0 to R3C2B.DI0 UFMCLK_N_224 (to RCLK_c) + -------- + 7.045 (29.0% logic, 71.0% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R5C4C.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_43: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R3C2B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 3.669ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i11 (from RCLK_c +) + Destination: FF Data in InitReady_394 (to RCLK_c +) + + Delay: 6.949ns (24.1% logic, 75.9% route), 4 logic levels. + + Constraint Details: + + 6.949ns physical path delay SLICE_5 to SLICE_25 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.244ns CE_SET requirement (totaling 3.280ns) by 3.669ns + + Physical Path Details: + + Data path SLICE_5 to SLICE_25: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R5C4B.CLK to R5C4B.Q1 SLICE_5 (from RCLK_c) +ROUTE 8 1.895 R5C4B.Q1 to R5C2B.C0 FS_11 +CTOF_DEL --- 0.371 R5C2B.C0 to R5C2B.F0 SLICE_94 +ROUTE 1 0.694 R5C2B.F0 to R3C2A.D1 n12 +CTOF_DEL --- 0.371 R3C2A.D1 to R3C2A.F1 SLICE_69 +ROUTE 3 1.057 R3C2A.F1 to R5C2C.A1 n62 +CTOF_DEL --- 0.371 R5C2C.A1 to R5C2C.F1 SLICE_95 +ROUTE 1 1.630 R5C2C.F1 to R6C2A.CE RCLK_c_enable_25 (to RCLK_c) + -------- + 6.949 (24.1% logic, 75.9% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_5: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R5C4B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_25: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R6C2A.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 3.582ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i12 (from RCLK_c +) + Destination: FF Data in UFMCLK_416 (to RCLK_c +) + + Delay: 6.925ns (29.5% logic, 70.5% route), 5 logic levels. + + Constraint Details: + + 6.925ns physical path delay SLICE_3 to SLICE_43 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.181ns DIN_SET requirement (totaling 3.343ns) by 3.582ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_43: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R5C4C.CLK to R5C4C.Q0 SLICE_3 (from RCLK_c) +ROUTE 4 0.909 R5C4C.Q0 to R6C4C.C1 FS_12 +CTOF_DEL --- 0.371 R6C4C.C1 to R6C4C.F1 SLICE_68 +ROUTE 2 1.503 R6C4C.F1 to R7C5B.A1 n2471 +CTOF_DEL --- 0.371 R7C5B.A1 to R7C5B.F1 SLICE_44 +ROUTE 2 1.972 R7C5B.F1 to R3C2B.C1 n2462 +CTOF_DEL --- 0.371 R3C2B.C1 to R3C2B.F1 SLICE_43 +ROUTE 1 0.497 R3C2B.F1 to R3C2B.C0 n1160 +CTOF_DEL --- 0.371 R3C2B.C0 to R3C2B.F0 SLICE_43 +ROUTE 1 0.000 R3C2B.F0 to R3C2B.DI0 UFMCLK_N_224 (to RCLK_c) + -------- + 6.925 (29.5% logic, 70.5% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R5C4C.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_43: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R3C2B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 3.567ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CASr3_384 (from RCLK_c +) + Destination: FF Data in nRCS_396 (to RCLK_c +) + + Delay: 6.910ns (31.5% logic, 68.5% route), 5 logic levels. + + Constraint Details: + + 6.910ns physical path delay SLICE_68 to SLICE_60 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.181ns DIN_SET requirement (totaling 3.343ns) by 3.567ns + + Physical Path Details: + + Data path SLICE_68 to SLICE_60: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R6C4C.CLK to R6C4C.Q1 SLICE_68 (from RCLK_c) +ROUTE 2 1.364 R6C4C.Q1 to R8C5C.C0 CASr3 +CTOF_DEL --- 0.371 R8C5C.C0 to R8C5C.F0 SLICE_74 +ROUTE 2 0.513 R8C5C.F0 to R8C5C.C1 n1 +CTOF_DEL --- 0.371 R8C5C.C1 to R8C5C.F1 SLICE_74 +ROUTE 2 1.276 R8C5C.F1 to R8C4D.M0 n15_adj_1 +MTOOFX_DEL --- 0.501 R8C4D.M0 to R8C4D.OFX0 i2099/SLICE_72 +ROUTE 1 1.583 R8C4D.OFX0 to R2C5B.A0 n2481 +CTOF_DEL --- 0.371 R2C5B.A0 to R2C5B.F0 SLICE_60 +ROUTE 1 0.000 R2C5B.F0 to R2C5B.DI0 nRCS_N_136 (to RCLK_c) + -------- + 6.910 (31.5% logic, 68.5% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_68: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R6C4C.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_60: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R2C5B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 3.552ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i12 (from RCLK_c +) + Destination: FF Data in LEDEN_419 (to RCLK_c +) + + Delay: 6.832ns (24.5% logic, 75.5% route), 4 logic levels. + + Constraint Details: + + 6.832ns physical path delay SLICE_3 to SLICE_26 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.244ns CE_SET requirement (totaling 3.280ns) by 3.552ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_26: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R5C4C.CLK to R5C4C.Q0 SLICE_3 (from RCLK_c) +ROUTE 4 2.038 R5C4C.Q0 to R5C2D.B1 FS_12 +CTOF_DEL --- 0.371 R5C2D.B1 to R5C2D.F1 SLICE_90 +ROUTE 1 0.887 R5C2D.F1 to R4C2D.C0 n2328 +CTOF_DEL --- 0.371 R4C2D.C0 to R4C2D.F0 SLICE_75 +ROUTE 2 0.513 R4C2D.F0 to R4C2D.C1 n2214 +CTOF_DEL --- 0.371 R4C2D.C1 to R4C2D.F1 SLICE_75 +ROUTE 1 1.721 R4C2D.F1 to R7C5A.CE RCLK_c_enable_12 (to RCLK_c) + -------- + 6.832 (24.5% logic, 75.5% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R5C4C.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_26: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R7C5A.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 3.405ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i17 (from RCLK_c +) + Destination: FF Data in UFMCLK_416 (to RCLK_c +) + + Delay: 6.303ns (26.5% logic, 73.5% route), 4 logic levels. + + Constraint Details: + + 6.303ns physical path delay SLICE_8 to SLICE_43 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.626ns LSR_SET requirement (totaling 2.898ns) by 3.405ns + + Physical Path Details: + + Data path SLICE_8 to SLICE_43: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R5C5A.CLK to R5C5A.Q1 SLICE_8 (from RCLK_c) +ROUTE 4 1.509 R5C5A.Q1 to R6C4C.A1 FS_17 +CTOF_DEL --- 0.371 R6C4C.A1 to R6C4C.F1 SLICE_68 +ROUTE 2 1.042 R6C4C.F1 to R6C2D.A1 n2471 +CTOF_DEL --- 0.371 R6C2D.A1 to R6C2D.F1 SLICE_78 +ROUTE 3 0.528 R6C2D.F1 to R6C2D.C0 n2464 +CTOF_DEL --- 0.371 R6C2D.C0 to R6C2D.F0 SLICE_78 +ROUTE 2 1.551 R6C2D.F0 to R3C2B.LSR n1846 (to RCLK_c) + -------- + 6.303 (26.5% logic, 73.5% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_8: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R5C5A.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_43: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R3C2B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 3.361ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i15 (from RCLK_c +) + Destination: FF Data in UFMCLK_416 (to RCLK_c +) + + Delay: 6.704ns (30.5% logic, 69.5% route), 5 logic levels. + + Constraint Details: + + 6.704ns physical path delay SLICE_1 to SLICE_43 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.181ns DIN_SET requirement (totaling 3.343ns) by 3.361ns + + Physical Path Details: + + Data path SLICE_1 to SLICE_43: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R5C4D.CLK to R5C4D.Q1 SLICE_1 (from RCLK_c) +ROUTE 3 0.716 R5C4D.Q1 to R5C2B.D1 FS_15 +CTOF_DEL --- 0.371 R5C2B.D1 to R5C2B.F1 SLICE_94 +ROUTE 3 1.475 R5C2B.F1 to R7C5B.C1 n2272 +CTOF_DEL --- 0.371 R7C5B.C1 to R7C5B.F1 SLICE_44 +ROUTE 2 1.972 R7C5B.F1 to R3C2B.C1 n2462 +CTOF_DEL --- 0.371 R3C2B.C1 to R3C2B.F1 SLICE_43 +ROUTE 1 0.497 R3C2B.F1 to R3C2B.C0 n1160 +CTOF_DEL --- 0.371 R3C2B.C0 to R3C2B.F0 SLICE_43 +ROUTE 1 0.000 R3C2B.F0 to R3C2B.DI0 UFMCLK_N_224 (to RCLK_c) + -------- + 6.704 (30.5% logic, 69.5% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R5C4D.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_43: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R3C2B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + +Warning: 129.769MHz is the maximum frequency for this preference. + + +================================================================================ +Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ; + 106 items scored, 95 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path exceeds requirements by 5.022ns (weighted slack = -10.044ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i0 (from PHI2_c +) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 8.548ns (28.3% logic, 71.7% route), 6 logic levels. + + Constraint Details: + + 8.548ns physical path delay SLICE_88 to SLICE_14 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.638ns LSR_SET requirement (totaling 3.526ns) by 5.022ns + + Physical Path Details: + + Data path SLICE_88 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R4C3D.CLK to R4C3D.Q0 SLICE_88 (from PHI2_c) +ROUTE 1 1.155 R4C3D.Q0 to R2C2A.D0 Bank_0 +CTOF_DEL --- 0.371 R2C2A.D0 to R2C2A.F0 SLICE_97 +ROUTE 1 1.348 R2C2A.F0 to R4C4A.C0 n2314 +CTOF_DEL --- 0.371 R4C4A.C0 to R4C4A.F0 SLICE_81 +ROUTE 1 0.626 R4C4A.F0 to R4C4D.D1 n26 +CTOF_DEL --- 0.371 R4C4D.D1 to R4C4D.F1 SLICE_18 +ROUTE 8 1.225 R4C4D.F1 to R5C5B.D0 n1326 +CTOF_DEL --- 0.371 R5C5B.D0 to R5C5B.F0 SLICE_89 +ROUTE 1 0.700 R5C5B.F0 to R6C5C.D0 n1280 +CTOF_DEL --- 0.371 R6C5C.D0 to R6C5C.F0 SLICE_79 +ROUTE 2 1.079 R6C5C.F0 to R5C5D.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 8.548 (28.3% logic, 71.7% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R4C3D.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R5C5D.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 5.022ns (weighted slack = -10.044ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i0 (from PHI2_c +) + Destination: FF Data in ADSubmitted_407 (to PHI2_c -) + + Delay: 8.548ns (28.3% logic, 71.7% route), 6 logic levels. + + Constraint Details: + + 8.548ns physical path delay SLICE_88 to SLICE_9 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.638ns LSR_SET requirement (totaling 3.526ns) by 5.022ns + + Physical Path Details: + + Data path SLICE_88 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R4C3D.CLK to R4C3D.Q0 SLICE_88 (from PHI2_c) +ROUTE 1 1.155 R4C3D.Q0 to R2C2A.D0 Bank_0 +CTOF_DEL --- 0.371 R2C2A.D0 to R2C2A.F0 SLICE_97 +ROUTE 1 1.348 R2C2A.F0 to R4C4A.C0 n2314 +CTOF_DEL --- 0.371 R4C4A.C0 to R4C4A.F0 SLICE_81 +ROUTE 1 0.626 R4C4A.F0 to R4C4D.D1 n26 +CTOF_DEL --- 0.371 R4C4D.D1 to R4C4D.F1 SLICE_18 +ROUTE 8 1.225 R4C4D.F1 to R5C5B.D0 n1326 +CTOF_DEL --- 0.371 R5C5B.D0 to R5C5B.F0 SLICE_89 +ROUTE 1 0.700 R5C5B.F0 to R6C5C.D0 n1280 +CTOF_DEL --- 0.371 R6C5C.D0 to R6C5C.F0 SLICE_79 +ROUTE 2 1.079 R6C5C.F0 to R4C5D.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 8.548 (28.3% logic, 71.7% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R4C3D.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R4C5D.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.893ns (weighted slack = -9.786ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 8.419ns (28.7% logic, 71.3% route), 6 logic levels. + + Constraint Details: + + 8.419ns physical path delay SLICE_99 to SLICE_14 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.638ns LSR_SET requirement (totaling 3.526ns) by 4.893ns + + Physical Path Details: + + Data path SLICE_99 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C4C.CLK to R2C4C.Q1 SLICE_99 (from PHI2_c) +ROUTE 1 1.026 R2C4C.Q1 to R2C2A.A0 Bank_7 +CTOF_DEL --- 0.371 R2C2A.A0 to R2C2A.F0 SLICE_97 +ROUTE 1 1.348 R2C2A.F0 to R4C4A.C0 n2314 +CTOF_DEL --- 0.371 R4C4A.C0 to R4C4A.F0 SLICE_81 +ROUTE 1 0.626 R4C4A.F0 to R4C4D.D1 n26 +CTOF_DEL --- 0.371 R4C4D.D1 to R4C4D.F1 SLICE_18 +ROUTE 8 1.225 R4C4D.F1 to R5C5B.D0 n1326 +CTOF_DEL --- 0.371 R5C5B.D0 to R5C5B.F0 SLICE_89 +ROUTE 1 0.700 R5C5B.F0 to R6C5C.D0 n1280 +CTOF_DEL --- 0.371 R6C5C.D0 to R6C5C.F0 SLICE_79 +ROUTE 2 1.079 R6C5C.F0 to R5C5D.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 8.419 (28.7% logic, 71.3% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C4C.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R5C5D.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.893ns (weighted slack = -9.786ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in ADSubmitted_407 (to PHI2_c -) + + Delay: 8.419ns (28.7% logic, 71.3% route), 6 logic levels. + + Constraint Details: + + 8.419ns physical path delay SLICE_99 to SLICE_9 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.638ns LSR_SET requirement (totaling 3.526ns) by 4.893ns + + Physical Path Details: + + Data path SLICE_99 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C4C.CLK to R2C4C.Q1 SLICE_99 (from PHI2_c) +ROUTE 1 1.026 R2C4C.Q1 to R2C2A.A0 Bank_7 +CTOF_DEL --- 0.371 R2C2A.A0 to R2C2A.F0 SLICE_97 +ROUTE 1 1.348 R2C2A.F0 to R4C4A.C0 n2314 +CTOF_DEL --- 0.371 R4C4A.C0 to R4C4A.F0 SLICE_81 +ROUTE 1 0.626 R4C4A.F0 to R4C4D.D1 n26 +CTOF_DEL --- 0.371 R4C4D.D1 to R4C4D.F1 SLICE_18 +ROUTE 8 1.225 R4C4D.F1 to R5C5B.D0 n1326 +CTOF_DEL --- 0.371 R5C5B.D0 to R5C5B.F0 SLICE_89 +ROUTE 1 0.700 R5C5B.F0 to R6C5C.D0 n1280 +CTOF_DEL --- 0.371 R6C5C.D0 to R6C5C.F0 SLICE_79 +ROUTE 2 1.079 R6C5C.F0 to R4C5D.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 8.419 (28.7% logic, 71.3% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C4C.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R4C5D.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.392ns (weighted slack = -8.784ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i0 (from PHI2_c +) + Destination: FF Data in CmdUFMCS_412 (to PHI2_c -) + FF CmdUFMCLK_413 + + Delay: 8.291ns (29.1% logic, 70.9% route), 6 logic levels. + + Constraint Details: + + 8.291ns physical path delay SLICE_88 to SLICE_81 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 3.899ns) by 4.392ns + + Physical Path Details: + + Data path SLICE_88 to SLICE_81: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R4C3D.CLK to R4C3D.Q0 SLICE_88 (from PHI2_c) +ROUTE 1 1.155 R4C3D.Q0 to R2C2A.D0 Bank_0 +CTOF_DEL --- 0.371 R2C2A.D0 to R2C2A.F0 SLICE_97 +ROUTE 1 1.348 R2C2A.F0 to R4C4A.C0 n2314 +CTOF_DEL --- 0.371 R4C4A.C0 to R4C4A.F0 SLICE_81 +ROUTE 1 0.626 R4C4A.F0 to R4C4D.D1 n26 +CTOF_DEL --- 0.371 R4C4D.D1 to R4C4D.F1 SLICE_18 +ROUTE 8 0.755 R4C4D.F1 to R4C3A.D0 n1326 +CTOF_DEL --- 0.371 R4C3A.D0 to R4C3A.F0 SLICE_82 +ROUTE 2 0.903 R4C3A.F0 to R4C5C.C1 n2460 +CTOF_DEL --- 0.371 R4C5C.C1 to R4C5C.F1 SLICE_83 +ROUTE 2 1.089 R4C5C.F1 to R4C4A.CE PHI2_N_120_enable_6 (to PHI2_c) + -------- + 8.291 (29.1% logic, 70.9% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R4C3D.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_81: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R4C4A.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.392ns (weighted slack = -8.784ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i0 (from PHI2_c +) + Destination: FF Data in CmdUFMSDI_414 (to PHI2_c -) + + Delay: 8.291ns (29.1% logic, 70.9% route), 6 logic levels. + + Constraint Details: + + 8.291ns physical path delay SLICE_88 to SLICE_93 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 3.899ns) by 4.392ns + + Physical Path Details: + + Data path SLICE_88 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R4C3D.CLK to R4C3D.Q0 SLICE_88 (from PHI2_c) +ROUTE 1 1.155 R4C3D.Q0 to R2C2A.D0 Bank_0 +CTOF_DEL --- 0.371 R2C2A.D0 to R2C2A.F0 SLICE_97 +ROUTE 1 1.348 R2C2A.F0 to R4C4A.C0 n2314 +CTOF_DEL --- 0.371 R4C4A.C0 to R4C4A.F0 SLICE_81 +ROUTE 1 0.626 R4C4A.F0 to R4C4D.D1 n26 +CTOF_DEL --- 0.371 R4C4D.D1 to R4C4D.F1 SLICE_18 +ROUTE 8 0.755 R4C4D.F1 to R4C3A.D0 n1326 +CTOF_DEL --- 0.371 R4C3A.D0 to R4C3A.F0 SLICE_82 +ROUTE 2 0.903 R4C3A.F0 to R4C5C.C1 n2460 +CTOF_DEL --- 0.371 R4C5C.C1 to R4C5C.F1 SLICE_83 +ROUTE 2 1.089 R4C5C.F1 to R3C5A.CE PHI2_N_120_enable_6 (to PHI2_c) + -------- + 8.291 (29.1% logic, 70.9% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R4C3D.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R3C5A.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.263ns (weighted slack = -8.526ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in CmdUFMCS_412 (to PHI2_c -) + FF CmdUFMCLK_413 + + Delay: 8.162ns (29.6% logic, 70.4% route), 6 logic levels. + + Constraint Details: + + 8.162ns physical path delay SLICE_99 to SLICE_81 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 3.899ns) by 4.263ns + + Physical Path Details: + + Data path SLICE_99 to SLICE_81: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C4C.CLK to R2C4C.Q1 SLICE_99 (from PHI2_c) +ROUTE 1 1.026 R2C4C.Q1 to R2C2A.A0 Bank_7 +CTOF_DEL --- 0.371 R2C2A.A0 to R2C2A.F0 SLICE_97 +ROUTE 1 1.348 R2C2A.F0 to R4C4A.C0 n2314 +CTOF_DEL --- 0.371 R4C4A.C0 to R4C4A.F0 SLICE_81 +ROUTE 1 0.626 R4C4A.F0 to R4C4D.D1 n26 +CTOF_DEL --- 0.371 R4C4D.D1 to R4C4D.F1 SLICE_18 +ROUTE 8 0.755 R4C4D.F1 to R4C3A.D0 n1326 +CTOF_DEL --- 0.371 R4C3A.D0 to R4C3A.F0 SLICE_82 +ROUTE 2 0.903 R4C3A.F0 to R4C5C.C1 n2460 +CTOF_DEL --- 0.371 R4C5C.C1 to R4C5C.F1 SLICE_83 +ROUTE 2 1.089 R4C5C.F1 to R4C4A.CE PHI2_N_120_enable_6 (to PHI2_c) + -------- + 8.162 (29.6% logic, 70.4% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C4C.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_81: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R4C4A.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.263ns (weighted slack = -8.526ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in CmdUFMSDI_414 (to PHI2_c -) + + Delay: 8.162ns (29.6% logic, 70.4% route), 6 logic levels. + + Constraint Details: + + 8.162ns physical path delay SLICE_99 to SLICE_93 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 3.899ns) by 4.263ns + + Physical Path Details: + + Data path SLICE_99 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C4C.CLK to R2C4C.Q1 SLICE_99 (from PHI2_c) +ROUTE 1 1.026 R2C4C.Q1 to R2C2A.A0 Bank_7 +CTOF_DEL --- 0.371 R2C2A.A0 to R2C2A.F0 SLICE_97 +ROUTE 1 1.348 R2C2A.F0 to R4C4A.C0 n2314 +CTOF_DEL --- 0.371 R4C4A.C0 to R4C4A.F0 SLICE_81 +ROUTE 1 0.626 R4C4A.F0 to R4C4D.D1 n26 +CTOF_DEL --- 0.371 R4C4D.D1 to R4C4D.F1 SLICE_18 +ROUTE 8 0.755 R4C4D.F1 to R4C3A.D0 n1326 +CTOF_DEL --- 0.371 R4C3A.D0 to R4C3A.F0 SLICE_82 +ROUTE 2 0.903 R4C3A.F0 to R4C5C.C1 n2460 +CTOF_DEL --- 0.371 R4C5C.C1 to R4C5C.F1 SLICE_83 +ROUTE 2 1.089 R4C5C.F1 to R3C5A.CE PHI2_N_120_enable_6 (to PHI2_c) + -------- + 8.162 (29.6% logic, 70.4% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C4C.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R3C5A.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.241ns (weighted slack = -8.482ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i6 (from PHI2_c +) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 7.767ns (31.1% logic, 68.9% route), 6 logic levels. + + Constraint Details: + + 7.767ns physical path delay SLICE_99 to SLICE_14 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.638ns LSR_SET requirement (totaling 3.526ns) by 4.241ns + + Physical Path Details: + + Data path SLICE_99 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C4C.CLK to R2C4C.Q0 SLICE_99 (from PHI2_c) +ROUTE 1 1.026 R2C4C.Q0 to R4C4A.A1 Bank_6 +CTOF_DEL --- 0.371 R4C4A.A1 to R4C4A.F1 SLICE_81 +ROUTE 1 0.696 R4C4A.F1 to R4C4A.B0 n2278 +CTOF_DEL --- 0.371 R4C4A.B0 to R4C4A.F0 SLICE_81 +ROUTE 1 0.626 R4C4A.F0 to R4C4D.D1 n26 +CTOF_DEL --- 0.371 R4C4D.D1 to R4C4D.F1 SLICE_18 +ROUTE 8 1.225 R4C4D.F1 to R5C5B.D0 n1326 +CTOF_DEL --- 0.371 R5C5B.D0 to R5C5B.F0 SLICE_89 +ROUTE 1 0.700 R5C5B.F0 to R6C5C.D0 n1280 +CTOF_DEL --- 0.371 R6C5C.D0 to R6C5C.F0 SLICE_79 +ROUTE 2 1.079 R6C5C.F0 to R5C5D.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 7.767 (31.1% logic, 68.9% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C4C.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R5C5D.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.241ns (weighted slack = -8.482ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i6 (from PHI2_c +) + Destination: FF Data in ADSubmitted_407 (to PHI2_c -) + + Delay: 7.767ns (31.1% logic, 68.9% route), 6 logic levels. + + Constraint Details: + + 7.767ns physical path delay SLICE_99 to SLICE_9 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.638ns LSR_SET requirement (totaling 3.526ns) by 4.241ns + + Physical Path Details: + + Data path SLICE_99 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C4C.CLK to R2C4C.Q0 SLICE_99 (from PHI2_c) +ROUTE 1 1.026 R2C4C.Q0 to R4C4A.A1 Bank_6 +CTOF_DEL --- 0.371 R4C4A.A1 to R4C4A.F1 SLICE_81 +ROUTE 1 0.696 R4C4A.F1 to R4C4A.B0 n2278 +CTOF_DEL --- 0.371 R4C4A.B0 to R4C4A.F0 SLICE_81 +ROUTE 1 0.626 R4C4A.F0 to R4C4D.D1 n26 +CTOF_DEL --- 0.371 R4C4D.D1 to R4C4D.F1 SLICE_18 +ROUTE 8 1.225 R4C4D.F1 to R5C5B.D0 n1326 +CTOF_DEL --- 0.371 R5C5B.D0 to R5C5B.F0 SLICE_89 +ROUTE 1 0.700 R5C5B.F0 to R6C5C.D0 n1280 +CTOF_DEL --- 0.371 R6C5C.D0 to R6C5C.F0 SLICE_79 +ROUTE 2 1.079 R6C5C.F0 to R4C5D.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 7.767 (31.1% logic, 68.9% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C4C.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R4C5D.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + +Warning: 54.431MHz is the maximum frequency for this preference. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY NET "RCLK_c" 283.768000 MHz ; | 283.768 MHz| 129.769 MHz| 5 * + | | | +FREQUENCY NET "PHI2_c" 120.077000 MHz ; | 120.077 MHz| 54.431 MHz| 6 * + | | | +---------------------------------------------------------------------------- + + +2 preferences(marked by "*" above) not met. + +---------------------------------------------------------------------------- +Critical Nets | Loads| Errors| % of total +---------------------------------------------------------------------------- +n1326 | 8| 95| 29.14% + | | | +n26 | 1| 71| 21.78% + | | | +---------------------------------------------------------------------------- + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 + Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Setup): +--------------- + +Timing errors: 326 Score: 913247 +Cumulative negative slack: 638389 + +Constraints cover 489 paths, 2 nets, and 414 connections (62.54% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:29 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf +Design file: ram2gs_lcmxo256c_impl1.ncd +Preference file: ram2gs_lcmxo256c_impl1.prf +Device,speed: LCMXO256C,m +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ; + 383 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.273ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i4 (from RCLK_c +) + Destination: FF Data in IS_FSM__i5 (to RCLK_c +) + + Delay: 0.256ns (49.2% logic, 50.8% route), 1 logic levels. + + Constraint Details: + + 0.256ns physical path delay SLICE_100 to SLICE_100 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.273ns + + Physical Path Details: + + Data path SLICE_100 to SLICE_100: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R6C2B.CLK to R6C2B.Q0 SLICE_100 (from RCLK_c) +ROUTE 1 0.130 R6C2B.Q0 to R6C2B.M1 n736 (to RCLK_c) + -------- + 0.256 (49.2% logic, 50.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_100: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R6C2B.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_100: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R6C2B.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.273ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i8 (from RCLK_c +) + Destination: FF Data in IS_FSM__i9 (to RCLK_c +) + + Delay: 0.256ns (49.2% logic, 50.8% route), 1 logic levels. + + Constraint Details: + + 0.256ns physical path delay SLICE_76 to SLICE_76 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.273ns + + Physical Path Details: + + Data path SLICE_76 to SLICE_76: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R4C4B.CLK to R4C4B.Q0 SLICE_76 (from RCLK_c) +ROUTE 1 0.130 R4C4B.Q0 to R4C4B.M1 n732 (to RCLK_c) + -------- + 0.256 (49.2% logic, 50.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_76: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R4C4B.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_76: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R4C4B.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.273ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i12 (from RCLK_c +) + Destination: FF Data in IS_FSM__i13 (to RCLK_c +) + + Delay: 0.256ns (49.2% logic, 50.8% route), 1 logic levels. + + Constraint Details: + + 0.256ns physical path delay SLICE_77 to SLICE_77 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.273ns + + Physical Path Details: + + Data path SLICE_77 to SLICE_77: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R6C3D.CLK to R6C3D.Q0 SLICE_77 (from RCLK_c) +ROUTE 1 0.130 R6C3D.Q0 to R6C3D.M1 n728 (to RCLK_c) + -------- + 0.256 (49.2% logic, 50.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_77: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R6C3D.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_77: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R6C3D.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.273ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i14 (from RCLK_c +) + Destination: FF Data in IS_FSM__i15 (to RCLK_c +) + + Delay: 0.256ns (49.2% logic, 50.8% route), 1 logic levels. + + Constraint Details: + + 0.256ns physical path delay SLICE_80 to SLICE_80 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.273ns + + Physical Path Details: + + Data path SLICE_80 to SLICE_80: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R8C4A.CLK to R8C4A.Q0 SLICE_80 (from RCLK_c) +ROUTE 1 0.130 R8C4A.Q0 to R8C4A.M1 n726 (to RCLK_c) + -------- + 0.256 (49.2% logic, 50.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_80: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R8C4A.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_80: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R8C4A.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.273ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i10 (from RCLK_c +) + Destination: FF Data in IS_FSM__i11 (to RCLK_c +) + + Delay: 0.256ns (49.2% logic, 50.8% route), 1 logic levels. + + Constraint Details: + + 0.256ns physical path delay SLICE_82 to SLICE_82 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.273ns + + Physical Path Details: + + Data path SLICE_82 to SLICE_82: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R4C3A.CLK to R4C3A.Q0 SLICE_82 (from RCLK_c) +ROUTE 1 0.130 R4C3A.Q0 to R4C3A.M1 n730 (to RCLK_c) + -------- + 0.256 (49.2% logic, 50.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_82: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R4C3A.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_82: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R4C3A.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.273ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i2 (from RCLK_c +) + Destination: FF Data in IS_FSM__i3 (to RCLK_c +) + + Delay: 0.256ns (49.2% logic, 50.8% route), 1 logic levels. + + Constraint Details: + + 0.256ns physical path delay SLICE_84 to SLICE_84 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.273ns + + Physical Path Details: + + Data path SLICE_84 to SLICE_84: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R3C4A.CLK to R3C4A.Q0 SLICE_84 (from RCLK_c) +ROUTE 1 0.130 R3C4A.Q0 to R3C4A.M1 n738 (to RCLK_c) + -------- + 0.256 (49.2% logic, 50.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_84: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R3C4A.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_84: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R3C4A.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.273ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i6 (from RCLK_c +) + Destination: FF Data in IS_FSM__i7 (to RCLK_c +) + + Delay: 0.256ns (49.2% logic, 50.8% route), 1 logic levels. + + Constraint Details: + + 0.256ns physical path delay SLICE_86 to SLICE_86 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.273ns + + Physical Path Details: + + Data path SLICE_86 to SLICE_86: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R4C3C.CLK to R4C3C.Q0 SLICE_86 (from RCLK_c) +ROUTE 1 0.130 R4C3C.Q0 to R4C3C.M1 n734 (to RCLK_c) + -------- + 0.256 (49.2% logic, 50.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_86: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R4C3C.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_86: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R4C3C.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.281ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i0 (from RCLK_c +) + Destination: FF Data in IS_FSM__i1 (to RCLK_c +) + + Delay: 0.264ns (47.7% logic, 52.3% route), 1 logic levels. + + Constraint Details: + + 0.264ns physical path delay SLICE_87 to SLICE_87 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.281ns + + Physical Path Details: + + Data path SLICE_87 to SLICE_87: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R4C2C.CLK to R4C2C.Q0 SLICE_87 (from RCLK_c) +ROUTE 6 0.138 R4C2C.Q0 to R4C2C.M1 nRCS_N_139 (to RCLK_c) + -------- + 0.264 (47.7% logic, 52.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_87: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R4C2C.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_87: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R4C2C.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.288ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RASr2_380 (from RCLK_c +) + Destination: FF Data in RASr3_381 (to RCLK_c +) + + Delay: 0.271ns (46.5% logic, 53.5% route), 1 logic levels. + + Constraint Details: + + 0.271ns physical path delay SLICE_74 to SLICE_74 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.288ns + + Physical Path Details: + + Data path SLICE_74 to SLICE_74: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R8C5C.CLK to R8C5C.Q0 SLICE_74 (from RCLK_c) +ROUTE 14 0.145 R8C5C.Q0 to R8C5C.M1 RASr2 (to RCLK_c) + -------- + 0.271 (46.5% logic, 53.5% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_74: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R8C5C.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_74: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R8C5C.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.301ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i15 (from RCLK_c +) + Destination: FF Data in FS_610_add_4_16 (to RCLK_c +) + FF FS_610__i15 + FF FS_610__i14 + + Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels. + + Constraint Details: + + 0.257ns physical path delay SLICE_1 to SLICE_1 meets + -0.044ns LUT_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.044ns) by 0.301ns + + Physical Path Details: + + Data path SLICE_1 to SLICE_1: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R5C4D.CLK to R5C4D.Q1 SLICE_1 (from RCLK_c) +ROUTE 3 0.131 R5C4D.Q1 to R5C4D.A1 FS_15 (to RCLK_c) + -------- + 0.257 (49.0% logic, 51.0% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R5C4D.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R5C4D.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + +================================================================================ +Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ; + 106 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.361ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted_406 (from PHI2_c -) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 0.342ns (61.7% logic, 38.3% route), 2 logic levels. + + Constraint Details: + + 0.342ns physical path delay SLICE_14 to SLICE_14 meets + -0.019ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.361ns + + Physical Path Details: + + Data path SLICE_14 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R5C5D.CLK to R5C5D.Q0 SLICE_14 (from PHI2_c) +ROUTE 2 0.131 R5C5D.Q0 to R5C5D.A0 C1Submitted +CTOF_DEL --- 0.074 R5C5D.A0 to R5C5D.F0 SLICE_14 +ROUTE 1 0.000 R5C5D.F0 to R5C5D.DI0 n6_adj_3 (to PHI2_c) + -------- + 0.342 (61.7% logic, 38.3% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R5C5D.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R5C5D.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.361ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q ADSubmitted_407 (from PHI2_c -) + Destination: FF Data in ADSubmitted_407 (to PHI2_c -) + + Delay: 0.342ns (61.7% logic, 38.3% route), 2 logic levels. + + Constraint Details: + + 0.342ns physical path delay SLICE_9 to SLICE_9 meets + -0.019ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.361ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R4C5D.CLK to R4C5D.Q0 SLICE_9 (from PHI2_c) +ROUTE 2 0.131 R4C5D.Q0 to R4C5D.A0 ADSubmitted +CTOF_DEL --- 0.074 R4C5D.A0 to R4C5D.F0 SLICE_9 +ROUTE 1 0.000 R4C5D.F0 to R4C5D.DI0 n1413 (to PHI2_c) + -------- + 0.342 (61.7% logic, 38.3% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R4C5D.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R4C5D.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.587ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in XOR8MEG_408 (to PHI2_c -) + + Delay: 0.564ns (37.4% logic, 62.6% route), 2 logic levels. + + Constraint Details: + + 0.564ns physical path delay SLICE_18 to SLICE_49 meets + -0.023ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.023ns) by 0.587ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_49: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R4C4D.CLK to R4C4D.Q0 SLICE_18 (from PHI2_c) +ROUTE 2 0.223 R4C4D.Q0 to R3C4A.B1 CmdEnable +CTOF_DEL --- 0.074 R3C4A.B1 to R3C4A.F1 SLICE_84 +ROUTE 1 0.130 R3C4A.F1 to R3C4C.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 0.564 (37.4% logic, 62.6% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R4C4D.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_49: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R3C4C.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.869ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in CmdUFMCS_412 (to PHI2_c -) + FF CmdUFMCLK_413 + + Delay: 0.846ns (33.7% logic, 66.3% route), 3 logic levels. + + Constraint Details: + + 0.846ns physical path delay SLICE_18 to SLICE_81 meets + -0.023ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.023ns) by 0.869ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_81: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R4C4D.CLK to R4C4D.Q0 SLICE_18 (from PHI2_c) +ROUTE 2 0.145 R4C4D.Q0 to R4C5C.D0 CmdEnable +CTOF_DEL --- 0.074 R4C5C.D0 to R4C5C.F0 SLICE_83 +ROUTE 2 0.196 R4C5C.F0 to R4C5C.A1 n10 +CTOF_DEL --- 0.074 R4C5C.A1 to R4C5C.F1 SLICE_83 +ROUTE 2 0.220 R4C5C.F1 to R4C4A.CE PHI2_N_120_enable_6 (to PHI2_c) + -------- + 0.846 (33.7% logic, 66.3% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R4C4D.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_81: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R4C4A.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.869ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in CmdUFMSDI_414 (to PHI2_c -) + + Delay: 0.846ns (33.7% logic, 66.3% route), 3 logic levels. + + Constraint Details: + + 0.846ns physical path delay SLICE_18 to SLICE_93 meets + -0.023ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.023ns) by 0.869ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R4C4D.CLK to R4C4D.Q0 SLICE_18 (from PHI2_c) +ROUTE 2 0.145 R4C4D.Q0 to R4C5C.D0 CmdEnable +CTOF_DEL --- 0.074 R4C5C.D0 to R4C5C.F0 SLICE_83 +ROUTE 2 0.196 R4C5C.F0 to R4C5C.A1 n10 +CTOF_DEL --- 0.074 R4C5C.A1 to R4C5C.F1 SLICE_83 +ROUTE 2 0.220 R4C5C.F1 to R3C5A.CE PHI2_N_120_enable_6 (to PHI2_c) + -------- + 0.846 (33.7% logic, 66.3% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R4C4D.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R3C5A.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.057ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in Cmdn8MEGEN_410 (to PHI2_c -) + + Delay: 1.034ns (34.7% logic, 65.3% route), 4 logic levels. + + Constraint Details: + + 1.034ns physical path delay SLICE_18 to SLICE_23 meets + -0.023ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.023ns) by 1.057ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_23: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R4C4D.CLK to R4C4D.Q0 SLICE_18 (from PHI2_c) +ROUTE 2 0.145 R4C4D.Q0 to R4C5C.D0 CmdEnable +CTOF_DEL --- 0.074 R4C5C.D0 to R4C5C.F0 SLICE_83 +ROUTE 2 0.211 R4C5C.F0 to R4C4B.A1 n10 +CTOF_DEL --- 0.074 R4C4B.A1 to R4C4B.F1 SLICE_76 +ROUTE 2 0.103 R4C4B.F1 to R4C4B.C0 n2458 +CTOF_DEL --- 0.074 R4C4B.C0 to R4C4B.F0 SLICE_76 +ROUTE 1 0.216 R4C4B.F0 to R3C4B.CE PHI2_N_120_enable_4 (to PHI2_c) + -------- + 1.034 (34.7% logic, 65.3% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R4C4D.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_23: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R3C4B.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.079ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in CmdSubmitted_411 (to PHI2_c -) + + Delay: 1.056ns (34.0% logic, 66.0% route), 4 logic levels. + + Constraint Details: + + 1.056ns physical path delay SLICE_18 to SLICE_19 meets + -0.023ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.023ns) by 1.079ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R4C4D.CLK to R4C4D.Q0 SLICE_18 (from PHI2_c) +ROUTE 2 0.145 R4C4D.Q0 to R4C5C.D0 CmdEnable +CTOF_DEL --- 0.074 R4C5C.D0 to R4C5C.F0 SLICE_83 +ROUTE 2 0.211 R4C5C.F0 to R4C4B.A1 n10 +CTOF_DEL --- 0.074 R4C4B.A1 to R4C4B.F1 SLICE_76 +ROUTE 2 0.211 R4C4B.F1 to R6C4D.A0 n2458 +CTOF_DEL --- 0.074 R6C4D.A0 to R6C4D.F0 SLICE_91 +ROUTE 1 0.130 R6C4D.F0 to R6C4B.CE PHI2_N_120_enable_5 (to PHI2_c) + -------- + 1.056 (34.0% logic, 66.0% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R4C4D.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R6C4B.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.104ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q ADSubmitted_407 (from PHI2_c -) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 1.081ns (37.9% logic, 62.1% route), 4 logic levels. + + Constraint Details: + + 1.081ns physical path delay SLICE_9 to SLICE_18 meets + -0.023ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.023ns) by 1.104ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R4C5D.CLK to R4C5D.Q0 SLICE_9 (from PHI2_c) +ROUTE 2 0.143 R4C5D.Q0 to R3C5C.D0 ADSubmitted +CTOOFX_DEL --- 0.125 R3C5C.D0 to R3C5C.OFX0 i26/SLICE_71 +ROUTE 1 0.207 R3C5C.OFX0 to R4C5A.A0 n13_adj_2 +CTOF_DEL --- 0.074 R4C5A.A0 to R4C5A.F0 SLICE_105 +ROUTE 1 0.179 R4C5A.F0 to R4C3A.C1 n14 +CTOF_DEL --- 0.074 R4C3A.C1 to R4C3A.F1 SLICE_82 +ROUTE 1 0.142 R4C3A.F1 to R4C4D.CE PHI2_N_120_enable_7 (to PHI2_c) + -------- + 1.081 (37.9% logic, 62.1% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R4C5D.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R4C4D.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.368ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted_406 (from PHI2_c -) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 1.345ns (35.7% logic, 64.3% route), 5 logic levels. + + Constraint Details: + + 1.345ns physical path delay SLICE_14 to SLICE_18 meets + -0.023ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.023ns) by 1.368ns + + Physical Path Details: + + Data path SLICE_14 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R5C5D.CLK to R5C5D.Q0 SLICE_14 (from PHI2_c) +ROUTE 2 0.196 R5C5D.Q0 to R5C5D.A1 C1Submitted +CTOF_DEL --- 0.074 R5C5D.A1 to R5C5D.F1 SLICE_14 +ROUTE 1 0.141 R5C5D.F1 to R3C5C.D1 n2284 +CTOOFX_DEL --- 0.121 R3C5C.D1 to R3C5C.OFX0 i26/SLICE_71 +ROUTE 1 0.207 R3C5C.OFX0 to R4C5A.A0 n13_adj_2 +CTOF_DEL --- 0.074 R4C5A.A0 to R4C5A.F0 SLICE_105 +ROUTE 1 0.179 R4C5A.F0 to R4C3A.C1 n14 +CTOF_DEL --- 0.074 R4C3A.C1 to R4C3A.F1 SLICE_82 +ROUTE 1 0.142 R4C3A.F1 to R4C4D.CE PHI2_N_120_enable_7 (to PHI2_c) + -------- + 1.345 (35.7% logic, 64.3% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R5C5D.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R4C4D.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 4.689ns (weighted slack = 9.378ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q XOR8MEG_408 (from PHI2_c -) + Destination: FF Data in RA11_385 (to PHI2_c +) + + Delay: 0.517ns (40.8% logic, 59.2% route), 2 logic levels. + + Constraint Details: + + 0.517ns physical path delay SLICE_49 to SLICE_32 meets + -0.008ns DIN_HLD and + -4.164ns delay constraint less + 0.000ns skew requirement (totaling -4.172ns) by 4.689ns + + Physical Path Details: + + Data path SLICE_49 to SLICE_32: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R3C4C.CLK to R3C4C.Q0 SLICE_49 (from PHI2_c) +ROUTE 1 0.306 R3C4C.Q0 to R2C5A.A0 XOR8MEG +CTOF_DEL --- 0.074 R2C5A.A0 to R2C5A.F0 SLICE_32 +ROUTE 1 0.000 R2C5A.F0 to R2C5A.DI0 RA11_N_184 (to PHI2_c) + -------- + 0.517 (40.8% logic, 59.2% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_49: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R3C4C.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_32: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R2C5A.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference(MIN Delays) | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY NET "RCLK_c" 283.768000 MHz ; | 0.000 ns| 0.273 ns| 1 + | | | +FREQUENCY NET "PHI2_c" 120.077000 MHz ; | 0.000 ns| 0.361 ns| 2 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 + Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 489 paths, 2 nets, and 414 connections (62.54% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 326 (setup), 0 (hold) +Score: 913247 (setup), 0 (hold) +Cumulative negative slack: 638389 (638389+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_bgn.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_bgn.html new file mode 100644 index 0000000..6117b69 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_bgn.html @@ -0,0 +1,111 @@ + +Bitgen Report + + +

    BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 15 05:03:33 2023
+
+
+Command: bitgen -w -g ES:No -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf 
+
+Loading design for application Bitgen from file RAM2GS_LCMXO256C_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 3
+Loading device for application Bitgen from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from RAM2GS_LCMXO256C_impl1.prf.
+
+
+Preference Summary:
+
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                             ES  |                           No**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+Saving bit stream in "RAM2GS_LCMXO256C_impl1.bit".
+Total CPU Time: 0 secs 
+Total REAL Time: 0 secs 
+Peak Memory Usage: 44 MB
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_iotiming.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_iotiming.html new file mode 100644 index 0000000..e3b9e75 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_iotiming.html @@ -0,0 +1,203 @@ + +I/O Timing Report + + +
    I/O Timing Report
+Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 4
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 5
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: M
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+// Design: RAM2GS
+// Package: TQFP100
+// ncd File: ram2gs_lcmxo256c_impl1.ncd
+// Version: Diamond (64-bit) 3.12.1.454
+// Written on Tue Aug 15 05:03:30 2023
+// M: Minimum Performance Grade
+// iotiming RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml
+
+I/O Timing Report (All units are in ns)
+
+Worst Case Results across Performance Grades (M, 5, 4, 3):
+
+// Input Setup and Hold Times
+
+Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
+----------------------------------------------------------------------
+CROW[0] nCRAS F    -0.006      M       1.907     3
+CROW[1] nCRAS F    -0.006      M       1.907     3
+Din[0]  PHI2  F     5.992      3       2.081     3
+Din[0]  nCCAS F     1.591      3      -0.045     M
+Din[1]  PHI2  F     5.388      3       2.863     3
+Din[1]  nCCAS F     0.231      3       0.973     3
+Din[2]  PHI2  F     4.913      3       2.842     3
+Din[2]  nCCAS F     0.265      3       1.112     3
+Din[3]  PHI2  F     6.776      3       2.065     3
+Din[3]  nCCAS F     0.702      3       0.725     3
+Din[4]  PHI2  F     4.191      3       1.807     3
+Din[4]  nCCAS F     1.107      3       0.235     3
+Din[5]  PHI2  F     7.709      3       0.737     3
+Din[5]  nCCAS F     1.192      3       0.184     3
+Din[6]  PHI2  F     6.617      3       1.159     3
+Din[6]  nCCAS F     0.904      3       0.149     3
+Din[7]  PHI2  F     6.864      3       1.300     3
+Din[7]  nCCAS F     0.531      3       0.451     3
+MAin[0] PHI2  F     4.802      3       1.029     3
+MAin[0] nCRAS F     1.511      3       0.599     3
+MAin[1] PHI2  F     4.513      3       1.653     3
+MAin[1] nCRAS F     0.340      3       1.609     3
+MAin[2] PHI2  F     4.241      3       1.193     3
+MAin[2] nCRAS F     1.248      3       0.814     3
+MAin[3] PHI2  F     6.748      3      -0.221     M
+MAin[3] nCRAS F     0.375      3       1.589     3
+MAin[4] PHI2  F     7.111      3      -0.295     M
+MAin[4] nCRAS F    -0.038      M       2.031     3
+MAin[5] PHI2  F     4.083      3       1.319     3
+MAin[5] nCRAS F    -0.126      M       2.320     3
+MAin[6] PHI2  F     8.738      3      -0.639     M
+MAin[6] nCRAS F     0.505      3       1.464     3
+MAin[7] PHI2  F     7.566      3      -0.400     M
+MAin[7] nCRAS F     0.390      3       1.577     3
+MAin[8] nCRAS F    -0.017      M       1.932     3
+MAin[9] nCRAS F     1.390      3       0.679     3
+PHI2    RCLK  R     4.721      3      -0.539     M
+UFMSDO  RCLK  R     2.307      3      -0.173     M
+nCCAS   RCLK  R     3.513      3      -0.441     M
+nCCAS   nCRAS F     1.800      3       0.388     3
+nCRAS   RCLK  R     1.107      3       0.266     3
+nFWE    PHI2  F     4.160      3       1.763     3
+nFWE    nCRAS F     0.864      3       1.164     3
+
+
+// Clock to Output Delay
+
+Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
+------------------------------------------------------------------------
+LED    RCLK  R     7.020         3        1.411          M
+LED    nCRAS F    10.053         3        2.020          M
+RA[0]  RCLK  R     8.511         3        1.707          M
+RA[0]  nCRAS F    10.448         3        2.067          M
+RA[10] RCLK  R     7.422         3        1.486          M
+RA[11] PHI2  R     8.233         3        1.633          M
+RA[1]  RCLK  R     8.292         3        1.649          M
+RA[1]  nCRAS F    10.175         3        2.009          M
+RA[2]  RCLK  R     8.708         3        1.746          M
+RA[2]  nCRAS F    10.512         3        2.079          M
+RA[3]  RCLK  R     6.982         3        1.404          M
+RA[3]  nCRAS F     8.753         3        1.739          M
+RA[4]  RCLK  R     6.982         3        1.404          M
+RA[4]  nCRAS F     9.764         3        1.953          M
+RA[5]  RCLK  R     6.982         3        1.404          M
+RA[5]  nCRAS F    10.635         3        2.140          M
+RA[6]  RCLK  R     9.127         3        1.839          M
+RA[6]  nCRAS F    10.861         3        2.160          M
+RA[7]  RCLK  R     8.287         3        1.659          M
+RA[7]  nCRAS F    10.995         3        2.202          M
+RA[8]  RCLK  R     8.834         3        1.776          M
+RA[8]  nCRAS F    10.930         3        2.181          M
+RA[9]  RCLK  R     6.729         3        1.353          M
+RA[9]  nCRAS F    10.423         3        2.088          M
+RBA[0] nCRAS F     7.746         3        1.538          M
+RBA[1] nCRAS F     9.473         3        1.887          M
+RCKE   RCLK  R     8.348         3        1.695          M
+RDQMH  RCLK  R     7.433         3        1.503          M
+RDQML  RCLK  R     9.061         3        1.821          M
+RD[0]  nCCAS F     6.791         3        1.468          M
+RD[1]  nCCAS F     7.502         3        1.596          M
+RD[2]  nCCAS F     9.015         3        1.924          M
+RD[3]  nCCAS F     8.919         3        1.901          M
+RD[4]  nCCAS F     7.500         3        1.596          M
+RD[5]  nCCAS F     6.791         3        1.468          M
+RD[6]  nCCAS F     7.950         3        1.703          M
+RD[7]  nCCAS F     7.871         3        1.681          M
+UFMCLK RCLK  R     7.767         3        1.567          M
+UFMSDI RCLK  R     5.675         3        1.141          M
+nRCAS  RCLK  R     6.518         3        1.300          M
+nRCS   RCLK  R     5.675         3        1.141          M
+nRRAS  RCLK  R     7.469         3        1.503          M
+nRWE   RCLK  R     5.675         3        1.141          M
+nUFMCS RCLK  R     7.873         3        1.593          M
+WARNING: you must also run trce with hold speed: 3
+WARNING: you must also run trce with setup speed: M
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_lattice.synproj b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_lattice.synproj new file mode 100644 index 0000000..1c77aea --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_lattice.synproj @@ -0,0 +1,41 @@ +-a "MachXO" +-d LCMXO256C +-t TQFP100 +-s 3 +-frequency 200 +-optimization_goal Balanced +-bram_utilization 100 +-ramstyle Auto +-romstyle auto +-dsp_utilization 100 +-use_dsp 1 +-use_carry_chain 1 +-carry_chain_length 0 +-force_gsr Auto +-resource_sharing 1 +-propagate_constants 1 +-remove_duplicate_regs 1 +-mux_style Auto +-max_fanout 1000 +-fsm_encoding_style Auto +-twr_paths 3 +-fix_gated_clocks 1 +-loop_limit 1950 + + + +-use_io_insertion 1 +-resolve_mixed_drivers 0 +-use_io_reg auto + + +-lpf 1 +-p "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C" +-ver "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v" +-top RAM2GS + + +-p "C:/lscc/diamond/3.12/ispfpga/mj5g00/data" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C" + +-ngd "RAM2GS_LCMXO256C_impl1.ngd" + diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.asd b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.asd new file mode 100644 index 0000000..a397419 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.asd @@ -0,0 +1,13 @@ +[ActiveSupport MAP] +Device = LCMXO256C; +Package = TQFP100; +Performance = 3; +LUTS_avail = 256; +LUTS_used = 142; +FF_avail = 256; +FF_used = 102; +INPUT_LVCMOS33 = 26; +OUTPUT_LVCMOS33 = 33; +BIDI_LVCMOS33 = 8; +IO_avail = 78; +IO_used = 67; diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.cam b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.cam new file mode 100644 index 0000000..91ebb0b --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.cam @@ -0,0 +1,99 @@ +[ START MERGED ] +nCRAS_N_9 nCRAS_c +nCCAS_N_3 nCCAS_c +n2477 Ready +nFWE_N_5 nFWE_c +PHI2_N_120 PHI2_c +n1425 nRowColSel_N_34 +nRWE_N_176 nRWE_N_177 +RASr2_N_63 RASr2 +n1426 nRowColSel_N_35 +[ END MERGED ] +[ START CLIPPED ] +GND_net +VCC_net +FS_610_add_4_18/CO1 +FS_610_add_4_18/CO0 +FS_610_add_4_10/CO0 +FS_610_add_4_4/CO0 +FS_610_add_4_12/CO0 +FS_610_add_4_2/CO0 +FS_610_add_4_14/CO0 +FS_610_add_4_6/CO0 +FS_610_add_4_16/CO0 +FS_610_add_4_8/CO0 +[ END CLIPPED ] +[ START DESIGN PREFS ] +SCHEMATIC START ; +# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:03:20 2023 + +SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ; +LOCATE COMP "RD[7]" SITE "71" ; +LOCATE COMP "RD[6]" SITE "70" ; +LOCATE COMP "RD[5]" SITE "69" ; +LOCATE COMP "RD[4]" SITE "68" ; +LOCATE COMP "RD[3]" SITE "67" ; +LOCATE COMP "RD[2]" SITE "66" ; +LOCATE COMP "RD[1]" SITE "65" ; +LOCATE COMP "RD[0]" SITE "64" ; +LOCATE COMP "Dout[7]" SITE "3" ; +LOCATE COMP "Dout[6]" SITE "2" ; +LOCATE COMP "Dout[5]" SITE "5" ; +LOCATE COMP "Dout[4]" SITE "4" ; +LOCATE COMP "Dout[3]" SITE "6" ; +LOCATE COMP "Dout[2]" SITE "8" ; +LOCATE COMP "Dout[1]" SITE "7" ; +LOCATE COMP "Dout[0]" SITE "1" ; +LOCATE COMP "LED" SITE "57" ; +LOCATE COMP "RBA[1]" SITE "83" ; +LOCATE COMP "RBA[0]" SITE "63" ; +LOCATE COMP "RA[11]" SITE "79" ; +LOCATE COMP "RA[10]" SITE "87" ; +LOCATE COMP "RA[9]" SITE "85" ; +LOCATE COMP "RA[8]" SITE "96" ; +LOCATE COMP "RA[7]" SITE "100" ; +LOCATE COMP "RA[6]" SITE "91" ; +LOCATE COMP "RA[5]" SITE "95" ; +LOCATE COMP "RA[4]" SITE "99" ; +LOCATE COMP "RA[3]" SITE "97" ; +LOCATE COMP "RA[2]" SITE "94" ; +LOCATE COMP "RA[1]" SITE "89" ; +LOCATE COMP "RA[0]" SITE "98" ; +LOCATE COMP "nRCS" SITE "77" ; +LOCATE COMP "RCKE" SITE "82" ; +LOCATE COMP "nRWE" SITE "72" ; +LOCATE COMP "nRRAS" SITE "73" ; +LOCATE COMP "nRCAS" SITE "78" ; +LOCATE COMP "RDQMH" SITE "76" ; +LOCATE COMP "RDQML" SITE "61" ; +LOCATE COMP "nUFMCS" SITE "53" ; +LOCATE COMP "UFMCLK" SITE "58" ; +LOCATE COMP "UFMSDI" SITE "56" ; +LOCATE COMP "PHI2" SITE "39" ; +LOCATE COMP "MAin[9]" SITE "51" ; +LOCATE COMP "MAin[8]" SITE "50" ; +LOCATE COMP "MAin[7]" SITE "44" ; +LOCATE COMP "MAin[6]" SITE "49" ; +LOCATE COMP "MAin[5]" SITE "45" ; +LOCATE COMP "MAin[4]" SITE "46" ; +LOCATE COMP "MAin[3]" SITE "47" ; +LOCATE COMP "MAin[2]" SITE "37" ; +LOCATE COMP "MAin[1]" SITE "38" ; +LOCATE COMP "MAin[0]" SITE "23" ; +LOCATE COMP "CROW[1]" SITE "34" ; +LOCATE COMP "CROW[0]" SITE "32" ; +LOCATE COMP "Din[7]" SITE "19" ; +LOCATE COMP "Din[6]" SITE "20" ; +LOCATE COMP "Din[5]" SITE "17" ; +LOCATE COMP "Din[4]" SITE "18" ; +LOCATE COMP "Din[3]" SITE "16" ; +LOCATE COMP "Din[2]" SITE "14" ; +LOCATE COMP "Din[1]" SITE "15" ; +LOCATE COMP "Din[0]" SITE "21" ; +LOCATE COMP "nCCAS" SITE "27" ; +LOCATE COMP "nCRAS" SITE "43" ; +LOCATE COMP "nFWE" SITE "22" ; +LOCATE COMP "RCLK" SITE "86" ; +LOCATE COMP "UFMSDO" SITE "55" ; +SCHEMATIC END ; +[ END DESIGN PREFS ] diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.hrr b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.hrr new file mode 100644 index 0000000..c405991 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.hrr @@ -0,0 +1,10 @@ +--------------------------------------------------- +Report for cell RAM2GS + Instance path: RAM2GS + Cell usage: + cell count Res Usage(%) + SLIC 71.00 100.0 + LUT4 124.00 100.0 + IOBUF 67 100.0 + PFUREG 102 100.0 + RIPPLE 9 100.0 diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.ncd b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.ncd new file mode 100644 index 0000000000000000000000000000000000000000..0a2beec11840943a318528230a92a464a40118f8 GIT binary patch literal 107268 zcmeHw2Yg(|asGi7EF#qxcA=V z-h1!87uj-mY$vwkIIH*8^; z$_)#VQ{sk&>Me0kh$7M4C>YAz6QOp?+!LX8%iI&8cFQbqsNFKx7HYT50*A^ev%sNp z$}Dh*hB6DBYA*{c?S;TmoL5-jP>2c(912lkfkPoG(H^ciJ&Yzeg9?exm_nj6q>z}5 zsJS}&)^`v0CpKibdwgO=XIK6_8p^rcVm2mnnP76>6!%%JQ`~30PH~?VJH>t0>=gIKz+|_dbsLm-v?tBa)SlSI)>=<@6m()Bvu_J( zYE(D|SuvTdnYRTsnYRTsnYRTs-fc&2>6T2n#lU7ZO)PEpZN_BwZ5fJQ(;P^O5za0> zwNk|_XP0KB&ad@F(Jpp6^De8@yX$CFfSjpOvEW`|M`p3)nRi*AnRi*8nRmITy}M4M zWpw$Cc5chy%DgROEAuw1E3oKC4vqHLdpC^Mhr2h_2L^}wP4sotJ@?#G-*v~%`W@pp zPSkH0-?fvy!!aYb?!0~b-tmbW+j{p*>=@rWzGuQ@U)Vb`JltRF9qb?w7;++?BXr3h#4Y;(jr_&z*_;i2_vh zB0p5z5tJ7Hn-V&pC&cwi$erAaq+-tLk z`ul=(0V{dEINHVSEzPHbCel^N&Fwmr|z>#aX-YGOgeBsgqlo0a6d$v_(0qbfhJQD+z%BjUJ&;~{mL|D zVXZGd*u)R&?UeKkQoWrBugYap_UPsW4LM#=2l|RoJ2ut8mm+k|AER1638rbvTL( zHPfC9@tQRb+PrqgfdYO@&k(>3GX2Qx#C$r+x$*i<=GAk^d%-TvPvy#%utQ(uG8i_Ys+_258vWxef zJ+f&`dz4irPB)Uy(nr!+{75>>A4z8gMABIUk#tr;Bt5Q!cpr(QOzA+pWI9=VWJ)zM zGfX!{d}Aa%Lj~drBl$B_Af7LhpH-mgii0>H#lLB81%gcMBIy}gNS4u3+7bU1;gg{S z@mG=jG8B4XX&9H{pJt_!1qMm7svti2#0#Z(i1$e+%XkWF6mOHxEm}|I&X8W5OA318 zTGC1p&k{+`fI!^Jh%-rZ5mypP&wxOChAj{u65*4fgm$l)+IgNW)Kt$DYN}@i7L5+B zd9Z7T)(a}W55FJZ&9Ff_(If3XzqGd!U5uHqQ z3el-VrxBe_)JAj$(V0ZciOwQAn`i~mc|~bOBMGs6bRCGMhwYq6$$vQI)8J zsFSFR=whNvh*lF_O0iS8qM8PUs$UP1IqqE`{U zn&>q|uO)gN(d&ucK=ekUHxa#==q*HVC3+jt+lk&m^iHC85xtw}Jw)#%dLPmIi9SH| zL81>4eVFJYL?0#k7}3XxK0)+JqE8Whn&>k`pC$Sn(dUW2K=ehTFA;s2=zgNF5Pg;C z0iv%FeVynVMBgO(7SXqfzC-j~qQ4;e9?|!Sen9k>M1Mu}L!uuM{g~*liGD)#H$*=r z`dgw0iGD`(bE3Z^`g@{Z5d8zuFNyw<=%0vwMfA@^4-x&E=r=^aCHfble z6P-nLHqkjm=Mt?TI*({2(JG?zi7p_zkmw?!JW+wDNK_&!6IF=XiK;{$M4d!kL>CiX zLbRIbQld3Pml1Un^$_(E^%3sUCE8AO9ntkfJBW4?-9U6B(M?3-L^l)NLbQu$ zH_-&q9->=`ZX>##=nkU2M0XP1MRa$L?C`*7y}gjH*T+dCGThDoPC9AHNneuW-@ao< zy<8{lIrkPRuL7w#euH%H+*s;yD`Yjn=Y}Tx%>1VLyqu;H5}Xz|HwYfiji6~+O(1+Z zh0rv@oRjW1EwcqaGpA`jx1ec0J2W9H-IvpET9%l8N23lJI*yn@!!pIm>>D3z0Xx49 zi^dCuVudic>(0GiBbJO8>P3@UFQx7+?d}`B^Sa&Rd-v`n_~!lUP8cud+ly}52zRQs zv!g>YdDSlMEx4?G5tojagjaq0j+^U6zdIL<7m~Xk!y|fk@93Y{e%-E})KVYm3nu7r zOUG6DJTo$-IOZaon48nHX~3kCjif)a+&Qw6ntIM8UGU%1@uKLbe*4Z_>qWmGkEE&{ zVG4eGkE6R29mD-=``6b8>z%Q-AM5vlNNwt!;yJ7M|-407LIooViGTu#Y6&&Zyt`D zD3+;buOpx8fYww#X+F%~aaLK}51HI)J(9TlX!DIv!FLM=*Ts%V?=0FnQZs{`y45$l zM`P?4%8`PxvG1#Gk>yY>_^jtrW2EC*X47e7M03`5k5SB(8=a&N{#!tc)7_&qaQ*U2 zNlA<|HaLMAjv|bgk_Jbb-D=jmiKE{$v&W^YxK`61iqo_`S4?s;eNcO7A)8A3nm^hs ze9H)^#9Y;}YJ|~hUm|K1aVT~A#>I@B^mtlkb{^}Ui5)0b>*Hid(mrs>L~YOAy?b_z z?%YLv>!ZOaP<$s_Eq@Fyl|f)ony$Qcv_3F8Tptg5nmV*njd;r?zT`%aljg(xSyui~ z51QuRM2e%$Xec|@vlw(oBBk#T**KBE>F|XozfP7m8N+;SvfW8!v+bSaWcuK-#<1cP zlksjMoAItmPNt8A#7`VJ>w=R_?ne^Y-1kg!GJUk#NXH~hnh*0wCa98W+7{5zVcYJz zJWe)R^_AT^UX7@))#Az2HfcW0pYgLYveF7aZrrxWSp7n5crF~2?yisfC_uVDEKO|K z8S{{V1@^fu(po~(j2k}Mk0O+|R}z$_0p?3qjG2o0WCFUwDPNN4n=qr;nDVThV3(O_ z(x`mWe3-vhVrjwbz)=-lu}7Y)&vcpT&> zGXW#Zr1>y^CMH)O?sv-K4J`7GQ3)KAu|}0>GXMa8XgKnOgCpjV5pJe? zlHx(rO;sPsF(2-0&cwGew2Y?+W(XJ{z9x|F>&}?nylZw#zP!iT(d}00w`V>b#GpkC zUmZ!J-v~dFD#l!-AG`;%6A0ml3P|^%O&H6vSn22=OneO>-ItK3$aRh!(|vo22`h_y zQ=B?mx{ioXn%}d1;+FcjUuTl&R|v<={cZ-ur1>y^zGe%t$avnCT3=X?r1{mD9zdIm zzDCVNy=3n@_QJGb(tMb|#G3iGHc9lsZbSl}ZYrueF%|sA9C5-kTD#x3rlLY@UX-pV z=KYe2f&nF7*YEf=zgQfb&J_zS=lAy1XtLnf+Db>>j3f3zpJo`d3+Y_sx>LGO426%+ zB+&;b{0atKm}9zu4O8gj1?fIy(lS&dGNg0SxXzN)uQ-v^uk{!#FX^=247f@2Vg7;v z5mjD*Q!&y$PGMBo9{Vjz3zcn?{kp`u_*E^QC}cRArQ~R6Ex-txwmp6ei#|BnVwEDL zqyfG-lIH7qsW~lMzjgZ#vjA2t_${UrU)!p*o8qcn^S7J)eg!6fdshC6$?sQg@>jC* zmrZ`ZTTT9QR{oO7?+*r(zm%1~X!84x$K)?&$m|<=$sDK} znf);#nFBq~r)6dXa}UgXYS~5i0uu$B!QfXvk54K4eW6+X$~kLLH_gO_X~@-_Z4S96 zSwpUrHQ-7!59S&|vU^*n&(mfMvEIF{Bc9Pm;#@i)9T)-2(MO@l7+}z5^bu$>2KciX zee{`(0rqT0A9*HYfIFMfN1e$SV9sXrJI7=U`o?DTyT)V;dxn=nL$Jw#U>9w&RG-Rc zR;)aj$|7beAD;?#`6a8UVaB<*n$_<-&KmTcX7#&{vj#n(YMxw5Wt8WcynN>AjC4MJX2Z>AwjxLS zMp8NLlM8O%XVCuXJWBBX9(Z7MXt1}xp3m{w&jG%oGh_5On=*d5*1vXmq_4kgV4#iv z@9o`GY@@_N*Yc6|=1ZQxY%FwbY}=TpkF}$#rj^8IIHc;P?R>8viLXoJhQ0L+&sc5DUT}%d&7I~`n7|7{0Pf?xGuitXII{hYd)*J zTu_=Q=+7LbbAi%1O_cJP^ax4|e1tv=rHr~bO69Sz7)sv)R5D86jB7^eCP8UY#?+rV zN?U=_`AwAa(-IMs7N11dSsTXD_&ZWEN2<0$j!ad@Y-^m z;I$IR>z~;?>L{S}$RBGBfdJ^!ttcg#4pFsql1%CZQ20jbHs;O^A1-ub6`X=C!@%ctvGd|A}e0Ik1 z`I!)(LnCVkd)w9(y1FhetX^?%@2VB|cCYF=@4U8kc}mJtQr}8SUfHv%m;UElt0<*+ z<-OgM$%HDh8DRDS1`1sRZ3B7w$k-9+>N5KRtCtV1-yCiZ(Au`$9-y!Fk-h3Y7}`cjO`qib zG^BCg-FM)caVjsB=H-5lACk!vo#W#6ge#{XnHs1Dh%Q8X1(Yiopb0L!x`@YU|JZ6G z*{C{90NQ2&dU_O~XEXuIucVoi!dmhkabtCWE?(9@71suB^s)#=BcrWbtRkJdi=yq_ zQ={$PJ~E4H8UZ{pjVpRqk}aG8V<`5{Y;;buRk}Y`aJdE9nNg6P)dZOXGSBy7uQNp1 zhk+`#X$4%f?_HLlEW`P}Vj7f@hh->P!&W$W|2m_PT45n|ZWL1IH6fJ&Df%4~o^G(= z3LU7tvCN!MP?N>E*W;SO_G|%HF=G?wT~mXLJ>#lg*e)loqfn0ACplEpzJm(qW)yC# zEZkN`;dXu#ZVWe>cers}@;e~0U`^gUN5NW%!cN_k42|CE0EZP^vuk};g3F9$@E1*u zOP))R*)!7#1?K@9zGOBrqwvdH_+1o*U!e)V3~N^u{9)zA#b)vgKq+f?I#9&{+=U6M zGFGjhH#Mqcrs|lx!vawyi>P80QROD07*TUm#wqztpol^1fR!@Nm!%f+f`t-q0;sSlrFZZ&<`&*&(kaPOaBH3Ls>Axf0i0&(g$R zW~|rUH#I1EV(a*0v!vX8Frb{#Q1228!Hc61T-}7A+PZWlXtYo%-;n- z79;ImTr<)xN|2T@q4?a?NV~UZRkuzg?CwPZKeB;lotT#L%nk?fp=}R(n4oWU-kJL9 zV-3@;7Kiq6npHbKuirIXXxpFVyEPV)mnM*;or`Y%%3B+kH6h86Y)#=#ehtguF71+W zK0J-rDlfW3EvEbsL&{>_3EVP{ufjFs_yk-tha(bPXH03HH4Uy^zkXOuXZkHf`=VBJ zpb1fiXnGq%4uQp>*6EyC(CG^U^JIXD!S-|kQ#oTb@V(Q3Np>!H-Osw>d%ay>+3_Vy zN{kLJ8UYeZ#8;gQ-Qxlwy`*p!t(!;6&&{|#$U@_1}aLquw1=nml z&lljeC+{r?kM@0V8sJf6$JnF)jqeR2Kr;>Y7ja?$+~2jEOavY<^k{u%i?xfJqtM&h zgkA>pcloT>u?}@-et(P$pB5_Kf|#H%tveKHp3>4)%@?K(FdM zNPCy{DwLTpcUML+x2=h}EMKhWmP5q3&o_CPYxx2&#+X}&YsTDZxMo9mPGSf%7HOtA z<19x`$<5Nym{om&88iU3QK7S-ec0H-tF0}(DvHZ%nz(du>8-jXzvLU)Qjs6ejho5j z_eaBXHS|k-3SoxqW?VC5FGwJou~PH4sm&yI@!ZEnVlLXeI*MNwwZEQOZRHFuAYN-h zS&xEpdlQrnDBajleqlR~yyQoOBPSr*;Y@=)UAA`pH6L#MBll4njJ+Ey_I5_GcViQKjzRRWCyyS-u!m>o z)0@oY!)}MY;*GHvuc#%<=Jk;5q@o@ZftJreZhBo-@bcWWf%_#}ChxP=-RNgsz z38%pT9k&3zDGJb=n*hxMs67Fe-tsG!v$y;NpfSU_+=nRrG_yk1K(wWp7|x8<#;;5r zNVk;_spCKP?W6~EcxRVI?JWsvX>n+Rzw+Uo-A&Xw zsCDDa0{dhGzx3gqO6Ed%Xgx=LXy*EH&C~KF2~;!o1m8I|R3*Ml_WW#kiHQ&uKA1_k zYfoqDf%sc39QQxL(VfB*IZGL|AUdq zG01AhDtaHk3om#ofkRDan}%jWk|g^$ZPp^TB`b~xw4riG8a=Y#^5^~1WYz(_OD1&^ zu|0m$dX}?Y!Z_Fx;NX$;vz@l{Gghxxr#qjX=QN$&Z9_b|CZl9}|KNK4&StOY=E?iV z<#7yoX^_|JzG>j?2{SX$0Li4x+JkG;?Jeiwnuq@e`rWe5PTTPr&wh-hJKnsDMfYmu z3w1mN`@C!GKJm*pY18(gtiat(JWPuRH>9cPBey;r_M-dQ3Jl_!8Q3Y98&EB~aNq z;wK)=F*WZYYd&3M9uG^BP0&prU8S$)h!ozHOx}mPVjLezWvm@IIXtJGh+!(v9g}Bd?t3?TPGZybJjW{rJ zSA60F%TokklW0#?0(R2|tR&XsEIjUQTB`%HR`UMY*qWxivfj*uJSRp!xuVw$j^yQt z^z*qKAB87>zCE?w^2}BU23oOXM9{ir^x3T$Fjo7080dhk)#EK3Ct}1eImelE2YtL|OENw>+F1!3XGNWZ@8Jc13tV?oDj|*UZcLM8-or!Nu4QsOm ztrl2ct7{IU%=n}(9e^|@XnwK9_=|w?mjdH2X=2LxfDoO0N}4O_EbkdW&Fx)^=K zxMuV%NYIwC)pY;cWY-n&0#+*jr(zjjYr*##SjN}GGQO?}J_g@>KI!5azk(XS z$VzP?SU7Oqd?n)%kw*ZfjN0wEX4Jk8*Ie~$6BK9cI{jp76wAg#h~Wk}_H<0@p7*1> z4OA8cClak1lIGYHJ*dg3!#C|hDY{o9v zG>cV^({J=dY>G&BCh__~i`NeTuO9|pKh(r4<25oR!~3_>VJoa}8BB!5zn+?lcc^^2)(Z}hN&J0YXu$s5OJ=)md}fTl@VBd2B`wHW^hF#d61 z{9{dwXJVX@n6V&RW>`wl8@}SlJ^>pB7#9P?Y_6TfGv@Yb+-Hz~Dgk-MX4n^|2D!Hx zChN9*$kC+#NktW(v;J5hzZYO7Ij+77oXe8WSxYXCyV{||7@Wm<8~ zAl;aNG-Cs7x)ojzr6%U(=LKeXRbdM2JCotWXDv`a1E78$K>b`3s9B~~4kTolT6xz% z+|*VX`P6cGEmb$71zmAvDm?x&deh)PXN>yiqFF}L-Cmj^fI={s*y)pyyIJT zdx5?Bfj!G|zs13q(>P#A%xXS-O=nSOr?#Yu68@#^PRlBEE{Av*C!L$IbM#LK5W+dj zL-H&Dl{I^x{~yg&zH0IK6*$nZ!GS)|v`cK4VrQ#0){89A%X|b5)ZJVy;^C`s8dGGG zmcn@Mi~!@O;+hTG=W)%x^>fJ>$k=>(aOyEY>!k83QeD~i3|=w_{^Y0W->}gCI-vh8 zK>wRf=x4=_c&Stj`i@%;@m)>c{T$AK+JRqo*f-#s@%=?yGrqr&;5%d2s)=uMp}Fr^ ze19AG{tMvyyG?vM_;$~*;P6ZOU26qwW~G;5s|?QcQ?;FdFT;BWt{L7(;+i>pDS>y! zHrG!N)O^FB&w%Zw_$PgGFg<%Z(A_S>wjj@s?azGb`xe~a1GxVZ;Qm1q+)mu$fqRN= zuYz+%J2c(0T^5^%buh;?>em9*jQV?U&8T;N*@;nqOoIB1t+HvJuK~vGP8m{W0QGGT z&zmrQXkqmM~??ZDa%stfXq-Wlsz?mOI4z}8o~gm*fUrH3$Dxg0=dVBd;s z2KHBR&A|S$0K1US*gBi;QAdit&HG(x3M#)`=Dq@|Z&mWpW8-!h_In-dfDSJF#3KE# zf%KmO>3`Eix)YsvNDtqs>EC1oV&dtV{`Mq12{*}Vz$@eV@wjGgufa8Qc(uiI#xB{P zg{6Mb;`eWX-=71&KWpMQ(^4x$BeO^O@qrBd>gq^nsjJDI&{AIsNqnxJM-&r7XN7w|IU7^ror zFf_dr0H6VA%lWuwfPMql4A8GzfM)EPeQj!hA|$p!a-&ds@DsxQ0_;Cp!2S||{S^TF zPffsPSz-M4Pz10g=frNx)-o_-&#PB6p8eSk5VIA&4%f`<6S!uOf82sRV}Gu5y8Suc zw=u?;9`B`K`M`GQ9}x!$^C0?Hl>?y|CXDd)FpZ52`gL>d%0+}+~soNz~I*Y zKB}+#3Q4eIdC~H-iTBwX2GRA&`mXMKmK&i+Gn_WOqGEE0amE4Ec8L0iO$2U7ka8C(aVB{>*d6VUYxj`?TZ&N z4V4g?Kg@ce-(N`dvZ&#DSr*X?Z>2bR@uH%k@*%S?^g7l=FGn<7FDFIx;>6dC7ccS| za%LqDGhUXcUY0goFDIw6WqCv`PM~Yl;-O{i(8VpZ$es+M zlN+vn8xtT=F}M$lQRm9rbJmGdH6aiUw&inpdPcIeii&QYzL+iH#t>>8!-D)Kr zKuoZ5LBq9jK}0KlaO=mm#X~khyim1rQNy)zVMHrVY&%iw9c8B@iwR?uL#7lu%bGx? z&~T+xBT8{Y+un5&%O*-GA2M58RHc*}u9VJ*Qk=+kqPE3VO6|~@T6#Bjf|N?bmC_Ya ziWAsQ)N0-C_^BPbV1*ufPqb2PxK=JsYeinHBY`a$6;CT;l|!~f*`ZqLY`9h~iD<EF8)ynFIYvt02R-C|gV$;B| z=a_39hinL4s%lx&aJ8(7sKtqFjaG)%xoD{#GPKak#1nhl-Eg&B7Ey~6+LBsE`vyI= z9I`O3N7d5XaJ6(t)Z)ap8!jJ|=L;l^>v0yd%hYw#p2FVmbJQ(;Ds+Fth0aBUc4F7z z?(qqKxw_T~(=o$x52)O08!mTCL~bWMWx2ft=^kgRYlh{fNA{DkKiF`&XGP?8B2bpw zTXODkwkKv-Zu;4!MDBGBmpk&#zPxidfaUfUm3y4I>kP|Hui;PR9&WhY^4o3hqbWuC zAxw#_S#EFHxX0P)o?*GytK1_Ems{S|>C5fJi7dCbFx=xz%V${b4J!A>hRdCP`nQ;O zB0-khTl(#B_Nr%CZhCb?g7eXa%bosBf@0nY^;m9iakt0WG@4<#$5if34VOFp?#E)@ ziRD;s?`%SkvwSGlHKe^Q7Z0*dj+*hjH+ZrzSqKMp1yvA~S{oUg%$j`9cSE<}rH(c(;5xJdst&hTU zFI*d{Vy-sBVqc?T*BdVO5oxgtPPk^o_M)|+Di+meSnO+6?ClK~dr3rWXU)%u?FDN? z&Vt1Zi+!DneSO2lUK$bG3D%6*UaU6c98#TOvFYuXNzAgd;bI>d5!;E?jM!eNHq_p* zsW-jTHWB;AhKqevL~JKiGh%y@+EC+W-Z!b(;|&-4=!n=(q-MnS0<|G$>3W7iPH&n@ zdi$1!i+xN)Y$s4NVtamjsH0(V+AbA)cf-X#HX^nYr%m+wds;({TUDdCI3=CEr{Pkc z8j;$G(k6QS{mq_o!}|JGmHM`ZOMO~IY9~gU81S~bhn&5a86MZStI&5eT*8nj5V&O_o~o$HeBeAh|o@a#yck?-p)zG!qU4`?7JH-c27iXCq8@Nfq~I_p=w_I zGLWN3kY!Jy^>OqB~QO4g)qO*+HmFodKt(@E8IlBq2>Q7D@K)=I6W=8J94 zfxN9%`Sob6rcll_nu}kKM$fjzH)?TB>eeJ}G&pJ{y;_Mj8o9LIviUYB_0FTOE$MnS z3H53veOk#XTM(6?UTv@@p>^DpiFQ`NBcvg7C{3#v&?=5gSE0Gkwo7a-bR<_n4!(YU zy=1z*T?VM_uEtU?fb*&V@Wi}f4%{M&_9ASB&qt3EPXtgS3 zSevLCfa+8O;8nD|kfa)bxS9lUdu&07JCIIt#ASdFL)^(k+~mzsYxZ%6LtGU^F#sH? zY-nQMRt}}8Y)C4lb3rz(5wdBL$_8y}5_HbuP87?P4)blj2y0$3r47a)(xg7EM4N&n z=4dvW>+8ujs9ivi*F-bZ~5ZGuE z45sQDNtPk|uQ4=QhcOzhNif~Y5Qem(qNN($X)4=JL4o!;G0r#MFpjwt=f_~mC zZ@z7oN{lhpCc>C%5-Q>1W><-V8RoD>I2=JY9wol*`!DzG;Q}isn5Zj9OEn3(&anmI z7m%cI(4m4@P|*%v3U(wZ*3rl9wnnt;Qkw*{t+7c63s@@?g;KHIeA_B2SwLSG*}U+8 zst*)jXmg>Pv>=+IlA@qWih?Q@l2oi%k}8sANP4zlF0K$UOqlw}T<)YB_wD=Cig?c= zic(3?XDSKwteqW^1l_2823{&0w4%a+y(Xbu=thn;>b5Z}SE`wobHlq~>vqe*>( zst#ttGXaji`-Fi3?5(-n$tO->lMsEYQF0;^wMtH!4oN2s^9k_Nb~^cVy5^)^Xhn3= z)FV4-Y8}w!U6G<{u$-bjk$gHOck(5DAyb$eBE5i7e`PM$elE>w#*D2WvExe^?76#J zy#9?~p{5lq)I(xqOZlDKcaST|7)7NEG=9TY#($_aRB5^`zBIEFzj7NCwK z9T3_IFoVTXFlrKVsS$(UI@z`rxzw(q5og<6kO)cIu2nXdBasI9F!aSpHeKs-ie3`Q zw>pxhed?4|s|ZQ^ZBf`}?q^x+;_z@>dU`&kKS{#FpMB5^B6NU38XZeWDy3`Ekp%Ou zjvq-nkdVYp+*0ckB;O1qYjHqvJ*`#Um&+~uSb8wfZU&q4UBbYuUMlWkD&cVyMVbVy zsX+x8GzlnD8w zQ79MK$xJ}?2(Xl+CWYRhw=jC=b-Ty+?%lbAJWH{}3+{V_mvLC?RN+~amxE{Z3Qiig zue(qAo9kP_S=j&}ngk&=x`lUSzBC)ts0T)pWypd0?ZVJR1X>yh z)Fc4uI9n}-vep3v+B$ena|i0k+0tmVCZUDO5Q@-VJ zC`Ek=+I1r>c78GLl+Cl|+*7X zv_2%UhPlnGoJU343+3F9%T-^OAvReN9!`%22VKI0#F`XJOzYL{yw36%DQ_%?Mgfph z%R5#=)qyTcq}p?L@19+wJ9nAO#|qyi^i`QaGEKsW(Ij+xmqjQ>C6d$}ueP~RP#rju z)Hz{5B1w56$W%j&B+Z4eQ*$9nbM>X$#d?zMVTncWMejYGeC_1EeGlF0#Rn%^CQuYJ z>D|3!qGPy!Z9lna+C>5z4Je>&5c}VV4+Fqa~%R`nI<8Z z+FGdncq)QRBUQ&bJ%%YiGtGX5CTT&9EKws?b+uPDV1$M3w!9)qXlk#` z1?8~H%_12up*|ixrov;`X%Z@t;?m`0?>gD_Jt4+LTMsV5gmR*0M=EhDaeJO9oXk3= zx{65mL(OU|AhcRQ1e@B65aeX58syTBg>P%Kxg5izp%_Z)oB`d4B<*aSGN2V2yCaD; zY)%8PU44=$#6<3MZCjuaO+x>wwqbJ=cgUqd0CFkFAcH1BxzhjS*?E`o$>?~U=m0)i zZ!q9#ZLi8s{V7u1giIG(;ZR%$C~8-ZXd_0D>RC0&;C!l7V%C9GU5IBi34N~h0%fXH zWR6CiXFCZM>Do7P=`E+q|>&cgPuyuWbFgEzrMu4%#Cm|ERGv!R$ z3&Bc_4HTh^8i5|kiSeqyi=jrHqQU}e5{9Be0hm>X1cMPlrKROXIVfD^kU@{ zX?nm*8L*#tDHv#z90v0<85HuJjQE!e17oChZUTL4l4CD4xCw zlC%XXAaWr|b3q!7N4e=d;h>>X?BqfCYV@6!07SKRXi3dU*mcFSxa`*mM>G1gIEGBW zRRlmU8Z8z|99g{<#Z_q|16x%HO?2QS9L!t0#Kpf3LTUC$UjQ@Xvd&ukM0%aokJZ^a zzFydyu2y7$y>1KuMjDt$dJLM?PIL^DhTH&&dMw~udoEOJh5PsoP^mT!J)#;y<5-`v ziq6=6qcB)V=}#~r6U7B>UdW_N=J4ugJ#L?zLjz9Eu}R2Jk8w1S{m|*t)z4NKw}b)3qpFiM9^)3dcgRgU#`qp=^!xz)_1s1==8n|65R8 z^P;ab32;biujIL>-YUh7<5p0hxSAX^UUQ*AIz*9+EAjm!tM6@StulhJ8i57wQIN&Z ze7i6(hdl0;VEmyMdC1ae6Qk(}+bcl3?z{mrNK#}e*pLfJnoD&I_6jx>M3NTNB!KNQ z+f*d6Dn$bvBfLX2VD@hwD;oIqMo$AOE;OLBAxY62X*EU-+M})J_E6wgW%#`l9jcW8 zKY1%ofDE&n#lpM`#Z?>dCTqpYp8dLrmF<)r`gaQh6Fd*t%22;y@Pb@U7>woC?BlZ+ zmrLqd4;i+aI+ z0^lY>aq=9>N-h1@u^0f2_?InOb?5y2TY{Psn1+l6+H+1?9Q%dDPUFR6)XFG(jk zq&e@4@PHe;nfBoy%vk%Tmxh|ARJked2OAym5gU+hh@FssAi@CcxQR4%AL-=gh)#;d zJkJe32o7*?8Zl^6*o0bgn&88c;%LA&I_N>RDtaJ+c4~OuQ7E!1J_1I%6bn^oQmP%y z#`N+>BMi`zV{A_c!!J2C#}44*!ofIzdvdvDZ%Lg{QJ)4wp$qu1QaxH#Xeiihe**1P z-wZ*u3YaG&T#oj|3S9h?D6Vx!iX$}Q;)$5NT>2@9c_%Fm{VrQfL`gaqggw;wAZTgN z_K92M?Cz)0RE;mtBPu)`gG$Pw;%89&Qmax(s>Op2HS2_Ijz5dyniu9!li<6#c5XeZ z>2oNrJqmlQ<%4L#yv4(wul+nYJciDb{xGFzUGxHYxDmCUZp-5f;Gwyp!z*NfFZe@b zfEP+Kr}(09FsN2{2t8;LhfFVUNFraQW z=+~qw4xPS?s_rIJyC7AS@&ywlsZ^ST1_1*M!TX_oU_gzdmXBeGjoMdGUe_XkAuSKx zbNyy1iR0m~N^!F|pi5X70h)vXs6j?B{E1_Qt^EUN5F%_*e+*134nb!@)AE*uOR_tFmW6H{FWl&GF{^rKnY8}X{R^S*(q?xH>TH>awCQA<|^ zzFIrf%u=zXVB~)jT2b_(m$iHhCEU&5LV2Jh-J}2|w2Ru$&sLe%d|Ox;q^JjhnE))5 ztB&YEs)+(O={w-3g@HUQ#42<&SHREgNpZ)2S2&tjz1125v`~}K#R>#CTiq@~E=_`E zy4bQ06m9}_7Va;gZ!HetbfGjHL)fzZ9<-zDxsXLoDll|ZMw74;ZdR3K{rLN6opM6! zG${;(7>=yzAAkYis2#743u-k0%5izNu78R0aNF9^T0ZFL^do=lMgI!SI;;{P&0?Dr z%yK7+1yRNiQT$As7sWLxREE4QT0-?72@5kcG(S44&2oi0b{nUr_iDPN2lzSvIR1AkT?g1btodLP-E?6Q|LQs zY7w0@^-@k6Y#NSMud$kR@)=d-NNI#_nWO$hWHbw$Dh(XS7Sa5#A53eW7Pq_W?85#A zEK~$o+f!{Tpn7gZ;)9sOPldx=x^WxTNC#KG_byYT&Lx!zI!miUtk9)Z>EJ?=ju)<- zW=jQW{okVXS_>3#6$MVC8S^Eh01j+_1{T^XU{AXNHquo9bNIP%Fhk;YdcvigLYndg zgp@C=8bo8Re}{HyW{lOVDg5l4LNxZIe-9RlZ1k;Kvp_V~E|>oW%4=pc;Tl?Gcx=20 z=E)(BaDE96>LS5GlQ05V2@`C1{}E+%^84fu{Iw*Sr*<8tSka6m=1*SBJ7)V37^^`CATAuXq{s&}mRo*+t;oY= z{|{{e9NTG4grdXfCWHy9dC(mV7OO2b&>5N(YXX-) zCQ=?vxGtAl{ML9AOw7YV919M*{|7^&!ybc?;UK?sV^$AJ49ercMO{3&Xj15-6E@eI z?mRxi0%LJcGDo{0V~%Fxx0VyZLRAMAYW8E=KdH8b?LgI)>oj^an#yeNK>O@i-9geZ5guFpd8 zvu$2?J6Rb(F~XqAuN-MP8|5#skP z;GyOkZ8*v{D-&BHasPr8TQE z3{hf!VUbrCTP^|vo!3J_w-~EV@#d4#R-Ia4R?S-SU~rM@NO6W1XrrY4#Y#J?xPanV z`P00b6gnnaYaribmK3Q8Mexu_6y1c7P}y=5goXJ%IAT!(3snPHz(2-V(C-fthcY;z z5vm8Bp@l(cwZx;fg3{2UR;EdjejJj1YzG4s07HfzUo>mifB0ggA1TmauT}*I1R5%U zt}}&$-5y+Fo7o{e%z)9&Ab?ptqjMS)qN%j%2SZ&I3cUZ>(utO8=R#IZ3R)_7F(Hve zxm__X+6d(mB5$I~4-vOqjN%Ygi)&KQW5&C%b6PFM&HPZ&6_Ei;S(+;li=MqV@VgYv z(McZ0v1%FosF1w0%>?XtAtQI=8Zgt6Xxt(@%mb@Q4+8R{8q0SXSSWN{_ot0S{KG9G z^>U!mjq*B`1d^a$)wnIq+USXu)~w1f?3^k;IM~vQ(%n{8)Q!^0(ALch8GW(RnpGL5 z>t@yWqqIhis2in~p{<*(=|HTsW>tnk-O1q;c9?6y;n6fZc}8jvKxZ5Q6FHp1JT3|?i~yy>_}+i|+!yFt#17Jr)dlFWr$aTU0j z&NE!N^OVa*;d1s-8C+POSA&b`K;j}Ds9b6ZmoH^-;eNdaTudht7wJUhGAdloioE%W zC1QNl!NqhWagmNxE@Q&w#CK%0g>il@xR}l)F4CFGWs`7Owl{+dkGJjMV$S~(7dii{ zTs8}r(p%G95(m$V71x1}dUA~031Us*&~M(JX2L&TAtBZE!lN~p%RQNDJ%#pzzheq$ zTl82vru7PKXSZ7ohm)pLG8EO3>10!j0Z?m_lZ{%)(`VjjXxRbT=jb@W(`)mPrjjHK z%6t;KWhWTusDk^~Km^ksDQ+Xd4!Uf)0X#7IR)cYhZ9^E$&=LTTj~h{3r&-PtfU_*% z%izxe`Mm@!H-VQfBSM@dwkcsWBXP*hD6DZQ3acD}F3hW9l2gnq&Tep7ZtHVBnl3Pe z`k+^$a9A(_20E2MGtRU;!{TO^byYr}zo=&u<=#hs;G=@WhH6si4<`~vg%~5<$ps@# V%3@TEF*??Y0Y;h>GJ4>F{|DGXEf@d* literal 0 HcmV?d00001 diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvho.sdf b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvho.sdf new file mode 100644 index 0000000..92c0943 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvho.sdf @@ -0,0 +1,3036 @@ +(DELAYFILE + (SDFVERSION "3.0") + (DESIGN "RAM2GS") + (DATE "Tue Aug 15 05:03:23 2023") + (VENDOR "Lattice") + (PROGRAM "ldbanno") + (VERSION "Diamond (64-bit) 3.12.1.454") + (DIVIDER /) + (VOLTAGE 1.26:1.20:1.14) + (PROCESS "default") + (TEMPERATURE -40:25:85) + (TIMESCALE 1ps) + (CELL + (CELLTYPE "SLICE_0") + (INSTANCE SLICE_0I) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_1") + (INSTANCE SLICE_1I) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_2") + (INSTANCE SLICE_2I) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_3") + (INSTANCE SLICE_3I) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_4") + (INSTANCE SLICE_4I) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + ) + ) + (CELL + (CELLTYPE "SLICE_5") + (INSTANCE SLICE_5I) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_6") + (INSTANCE SLICE_6I) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_7") + (INSTANCE SLICE_7I) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_8") + (INSTANCE SLICE_8I) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_9") + (INSTANCE SLICE_9I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_14") + (INSTANCE SLICE_14I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_18") + (INSTANCE SLICE_18I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_19") + (INSTANCE SLICE_19I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_23") + (INSTANCE SLICE_23I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_25") + (INSTANCE SLICE_25I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_26") + (INSTANCE SLICE_26I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_31") + (INSTANCE SLICE_31I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_32") + (INSTANCE SLICE_32I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_34") + (INSTANCE SLICE_34I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_35") + (INSTANCE SLICE_35I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_36") + (INSTANCE SLICE_36I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_43") + (INSTANCE SLICE_43I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_44") + (INSTANCE SLICE_44I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_49") + (INSTANCE SLICE_49I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_56") + (INSTANCE SLICE_56I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_58") + (INSTANCE SLICE_58I) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_60") + (INSTANCE SLICE_60I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_61") + (INSTANCE SLICE_61I) + (DELAY + (ABSOLUTE + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH D0 OFX0 (508:569:631)(508:569:631)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_63") + (INSTANCE SLICE_63I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_64") + (INSTANCE SLICE_64I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_65") + (INSTANCE SLICE_65I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_66") + (INSTANCE SLICE_66I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_67") + (INSTANCE SLICE_67I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_68") + (INSTANCE SLICE_68I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_69") + (INSTANCE SLICE_69I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "RCKEEN_I_0_445_SLICE_70") + (INSTANCE RCKEEN_I_0_445_SLICE_70I) + (DELAY + (ABSOLUTE + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH D0 OFX0 (508:569:631)(508:569:631)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + ) + ) + ) + (CELL + (CELLTYPE "i26_SLICE_71") + (INSTANCE i26_SLICE_71I) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH D0 OFX0 (508:569:631)(508:569:631)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + ) + ) + ) + (CELL + (CELLTYPE "i2099_SLICE_72") + (INSTANCE i2099_SLICE_72I) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + ) + ) + ) + (CELL + (CELLTYPE "i26_adj_28_SLICE_73") + (INSTANCE i26_adj_28_SLICE_73I) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH D0 OFX0 (508:569:631)(508:569:631)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_74") + (INSTANCE SLICE_74I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_75") + (INSTANCE SLICE_75I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_76") + (INSTANCE SLICE_76I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_77") + (INSTANCE SLICE_77I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_78") + (INSTANCE SLICE_78I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_79") + (INSTANCE SLICE_79I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_80") + (INSTANCE SLICE_80I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_81") + (INSTANCE SLICE_81I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_82") + (INSTANCE SLICE_82I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_83") + (INSTANCE SLICE_83I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_84") + (INSTANCE SLICE_84I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_85") + (INSTANCE SLICE_85I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_86") + (INSTANCE SLICE_86I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_87") + (INSTANCE SLICE_87I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_88") + (INSTANCE SLICE_88I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_89") + (INSTANCE SLICE_89I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "SLICE_90") + (INSTANCE SLICE_90I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_91") + (INSTANCE SLICE_91I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_92") + (INSTANCE SLICE_92I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "SLICE_93") + (INSTANCE SLICE_93I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_94") + (INSTANCE SLICE_94I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_95") + (INSTANCE SLICE_95I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_96") + (INSTANCE SLICE_96I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_97") + (INSTANCE SLICE_97I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_98") + (INSTANCE SLICE_98I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "SLICE_99") + (INSTANCE SLICE_99I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_100") + (INSTANCE SLICE_100I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_101") + (INSTANCE SLICE_101I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_102") + (INSTANCE SLICE_102I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_103") + (INSTANCE SLICE_103I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "SLICE_104") + (INSTANCE SLICE_104I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_105") + (INSTANCE SLICE_105I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "RD_7_B") + (INSTANCE RD_7_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD7 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD7 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD7 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD7) (1250:1250:1250)) + (WIDTH (negedge RD7) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_6_B") + (INSTANCE RD_6_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD6 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD6 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD6 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD6) (1250:1250:1250)) + (WIDTH (negedge RD6) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_5_B") + (INSTANCE RD_5_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD5 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD5 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD5 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD5) (1250:1250:1250)) + (WIDTH (negedge RD5) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_4_B") + (INSTANCE RD_4_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD4 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD4 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD4 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD4) (1250:1250:1250)) + (WIDTH (negedge RD4) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_3_B") + (INSTANCE RD_3_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD3 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD3 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD3 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD3) (1250:1250:1250)) + (WIDTH (negedge RD3) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_2_B") + (INSTANCE RD_2_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD2 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD2 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD2 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD2) (1250:1250:1250)) + (WIDTH (negedge RD2) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_1_B") + (INSTANCE RD_1_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD1 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD1 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD1 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD1) (1250:1250:1250)) + (WIDTH (negedge RD1) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_0_B") + (INSTANCE RD_0_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD0 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD0 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD0 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD0) (1250:1250:1250)) + (WIDTH (negedge RD0) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Dout_7_B") + (INSTANCE Dout_7_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout7 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_6_B") + (INSTANCE Dout_6_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout6 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_5_B") + (INSTANCE Dout_5_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout5 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_4_B") + (INSTANCE Dout_4_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout4 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_3_B") + (INSTANCE Dout_3_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout3 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_2_B") + (INSTANCE Dout_2_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout2 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_1_B") + (INSTANCE Dout_1_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout1 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_0_B") + (INSTANCE Dout_0_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout0 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "LEDB") + (INSTANCE LEDI) + (DELAY + (ABSOLUTE + (IOPATH PADDO LEDS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_1_B") + (INSTANCE RBA_1_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RBA1 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_0_B") + (INSTANCE RBA_0_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RBA0 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_11_B") + (INSTANCE RA_11_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA11 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_10_B") + (INSTANCE RA_10_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA10 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_9_B") + (INSTANCE RA_9_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA9 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_8_B") + (INSTANCE RA_8_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA8 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_7_B") + (INSTANCE RA_7_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA7 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_6_B") + (INSTANCE RA_6_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA6 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_5_B") + (INSTANCE RA_5_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA5 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_4_B") + (INSTANCE RA_4_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA4 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_3_B") + (INSTANCE RA_3_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA3 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_2_B") + (INSTANCE RA_2_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA2 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_1_B") + (INSTANCE RA_1_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA1 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_0_B") + (INSTANCE RA_0_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA0 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nRCSB") + (INSTANCE nRCSI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRCSS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RCKEB") + (INSTANCE RCKEI) + (DELAY + (ABSOLUTE + (IOPATH PADDO RCKES (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nRWEB") + (INSTANCE nRWEI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRWES (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nRRASB") + (INSTANCE nRRASI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRRASS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nRCASB") + (INSTANCE nRCASI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRCASS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RDQMHB") + (INSTANCE RDQMHI) + (DELAY + (ABSOLUTE + (IOPATH PADDO RDQMHS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RDQMLB") + (INSTANCE RDQMLI) + (DELAY + (ABSOLUTE + (IOPATH PADDO RDQMLS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nUFMCSB") + (INSTANCE nUFMCSI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nUFMCSS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "UFMCLKB") + (INSTANCE UFMCLKI) + (DELAY + (ABSOLUTE + (IOPATH PADDO UFMCLKS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "UFMSDIB") + (INSTANCE UFMSDII) + (DELAY + (ABSOLUTE + (IOPATH PADDO UFMSDIS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "PHI2B") + (INSTANCE PHI2I) + (DELAY + (ABSOLUTE + (IOPATH PHI2S PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge PHI2S) (1250:1250:1250)) + (WIDTH (negedge PHI2S) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_9_B") + (INSTANCE MAin_9_I) + (DELAY + (ABSOLUTE + (IOPATH MAin9 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin9) (1250:1250:1250)) + (WIDTH (negedge MAin9) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_8_B") + (INSTANCE MAin_8_I) + (DELAY + (ABSOLUTE + (IOPATH MAin8 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin8) (1250:1250:1250)) + (WIDTH (negedge MAin8) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_7_B") + (INSTANCE MAin_7_I) + (DELAY + (ABSOLUTE + (IOPATH MAin7 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin7) (1250:1250:1250)) + (WIDTH (negedge MAin7) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_6_B") + (INSTANCE MAin_6_I) + (DELAY + (ABSOLUTE + (IOPATH MAin6 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin6) (1250:1250:1250)) + (WIDTH (negedge MAin6) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_5_B") + (INSTANCE MAin_5_I) + (DELAY + (ABSOLUTE + (IOPATH MAin5 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin5) (1250:1250:1250)) + (WIDTH (negedge MAin5) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_4_B") + (INSTANCE MAin_4_I) + (DELAY + (ABSOLUTE + (IOPATH MAin4 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin4) (1250:1250:1250)) + (WIDTH (negedge MAin4) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_3_B") + (INSTANCE MAin_3_I) + (DELAY + (ABSOLUTE + (IOPATH MAin3 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin3) (1250:1250:1250)) + (WIDTH (negedge MAin3) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_2_B") + (INSTANCE MAin_2_I) + (DELAY + (ABSOLUTE + (IOPATH MAin2 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin2) (1250:1250:1250)) + (WIDTH (negedge MAin2) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_1_B") + (INSTANCE MAin_1_I) + (DELAY + (ABSOLUTE + (IOPATH MAin1 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin1) (1250:1250:1250)) + (WIDTH (negedge MAin1) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_0_B") + (INSTANCE MAin_0_I) + (DELAY + (ABSOLUTE + (IOPATH MAin0 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin0) (1250:1250:1250)) + (WIDTH (negedge MAin0) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "CROW_1_B") + (INSTANCE CROW_1_I) + (DELAY + (ABSOLUTE + (IOPATH CROW1 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW1) (1250:1250:1250)) + (WIDTH (negedge CROW1) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "CROW_0_B") + (INSTANCE CROW_0_I) + (DELAY + (ABSOLUTE + (IOPATH CROW0 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW0) (1250:1250:1250)) + (WIDTH (negedge CROW0) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_7_B") + (INSTANCE Din_7_I) + (DELAY + (ABSOLUTE + (IOPATH Din7 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din7) (1250:1250:1250)) + (WIDTH (negedge Din7) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_6_B") + (INSTANCE Din_6_I) + (DELAY + (ABSOLUTE + (IOPATH Din6 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din6) (1250:1250:1250)) + (WIDTH (negedge Din6) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_5_B") + (INSTANCE Din_5_I) + (DELAY + (ABSOLUTE + (IOPATH Din5 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din5) (1250:1250:1250)) + (WIDTH (negedge Din5) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_4_B") + (INSTANCE Din_4_I) + (DELAY + (ABSOLUTE + (IOPATH Din4 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din4) (1250:1250:1250)) + (WIDTH (negedge Din4) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_3_B") + (INSTANCE Din_3_I) + (DELAY + (ABSOLUTE + (IOPATH Din3 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din3) (1250:1250:1250)) + (WIDTH (negedge Din3) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_2_B") + (INSTANCE Din_2_I) + (DELAY + (ABSOLUTE + (IOPATH Din2 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din2) (1250:1250:1250)) + (WIDTH (negedge Din2) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_1_B") + (INSTANCE Din_1_I) + (DELAY + (ABSOLUTE + (IOPATH Din1 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din1) (1250:1250:1250)) + (WIDTH (negedge Din1) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_0_B") + (INSTANCE Din_0_I) + (DELAY + (ABSOLUTE + (IOPATH Din0 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din0) (1250:1250:1250)) + (WIDTH (negedge Din0) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "nCCASB") + (INSTANCE nCCASI) + (DELAY + (ABSOLUTE + (IOPATH nCCASS PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nCCASS) (1250:1250:1250)) + (WIDTH (negedge nCCASS) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "nCRASB") + (INSTANCE nCRASI) + (DELAY + (ABSOLUTE + (IOPATH nCRASS PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nCRASS) (1250:1250:1250)) + (WIDTH (negedge nCRASS) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "nFWEB") + (INSTANCE nFWEI) + (DELAY + (ABSOLUTE + (IOPATH nFWES PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nFWES) (1250:1250:1250)) + (WIDTH (negedge nFWES) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RCLKB") + (INSTANCE RCLKI) + (DELAY + (ABSOLUTE + (IOPATH RCLKS PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RCLKS) (1250:1250:1250)) + (WIDTH (negedge RCLKS) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "UFMSDOB") + (INSTANCE UFMSDOI) + (DELAY + (ABSOLUTE + (IOPATH UFMSDOS PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge UFMSDOS) (1250:1250:1250)) + (WIDTH (negedge UFMSDOS) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RAM2GS") + (INSTANCE ) + (DELAY + (ABSOLUTE + (INTERCONNECT SLICE_0I/Q1 SLICE_0I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q1 SLICE_77I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q1 SLICE_88I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q0 SLICE_0I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q0 SLICE_68I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q0 SLICE_88I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_0I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_1I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_2I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_3I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_4I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_5I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_6I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_7I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_8I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_25I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_26I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_31I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_34I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_35I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_36I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_43I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_44I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_56I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_58I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_60I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_61I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_63I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_64I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_65I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_66I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_67I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_68I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_69I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_74I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_76I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_77I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_79I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_80I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_82I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_83I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_84I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_86I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_87I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_91I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_100I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/FCO SLICE_0I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/FCO SLICE_7I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q1 SLICE_1I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q1 SLICE_94I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q1 SLICE_94I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_1I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_69I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_78I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_90I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_90I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/FCO SLICE_1I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/FCO SLICE_8I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q1 SLICE_2I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q1 SLICE_77I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q1 SLICE_88I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q0 SLICE_2I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q0 SLICE_43I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q0 SLICE_77I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/FCO SLICE_2I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q1 SLICE_3I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q1 SLICE_94I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q1 SLICE_94I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q0 SLICE_3I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q0 SLICE_68I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q0 SLICE_69I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q0 SLICE_90I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/FCO SLICE_3I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q1 SLICE_4I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q1 SLICE_43I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q1 SLICE_68I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q0 SLICE_4I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q0 SLICE_68I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/FCO SLICE_6I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_5I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_44I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_56I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_75I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_75I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_78I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_94I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_95I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q0 SLICE_5I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q0 SLICE_56I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q0 SLICE_75I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q0 SLICE_88I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q0 SLICE_95I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q0 SLICE_95I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/FCO SLICE_5I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q1 SLICE_6I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q1 SLICE_68I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q0 SLICE_6I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q0 SLICE_77I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q1 SLICE_7I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q1 SLICE_77I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q1 SLICE_88I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q0 SLICE_7I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q0 SLICE_87I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q0 SLICE_88I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q1 SLICE_8I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q1 SLICE_68I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q1 SLICE_69I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q1 SLICE_90I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q0 SLICE_8I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q0 SLICE_78I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q0 SLICE_90I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q0 SLICE_90I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q0 SLICE_94I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_9I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_14I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_18I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI i26_SLICE_71I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_82I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_83I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_84I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_89I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_89I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_97I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_99I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F1 SLICE_9I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F1 SLICE_14I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F1 SLICE_18I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F1 SLICE_76I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F1 SLICE_82I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F1 SLICE_84I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F1 SLICE_89I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F1 SLICE_89I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_9I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI i26_SLICE_71I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI i26_SLICE_71I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI i26_adj_28_SLICE_73I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI i26_adj_28_SLICE_73I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_76I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_82I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_83I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_84I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_89I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_97I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_98I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/F1 SLICE_9I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/Q0 SLICE_9I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/Q0 i26_SLICE_71I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/F1 SLICE_9I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89I/F1 SLICE_9I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/F0 SLICE_9I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F0 SLICE_9I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F0 SLICE_14I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_9I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_14I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_18I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_19I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_23I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_32I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_49I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_81I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_88I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_91I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_93I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_99I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_101I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_102I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_14I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_23I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_32I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_32I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI i26_adj_28_SLICE_73I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI i26_adj_28_SLICE_73I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_79I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_92I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_92I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_92I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_99I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_14I/Q0 SLICE_14I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_14I/Q0 SLICE_14I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_14I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_76I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_82I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_85I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_86I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_89I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_98I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_105I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_14I/F0 SLICE_14I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_14I/F1 i26_SLICE_71I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_5_I/PADDI SLICE_18I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_5_I/PADDI SLICE_95I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_5_I/PADDI SLICE_103I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96I/F0 SLICE_18I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/F0 SLICE_18I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_2_I/PADDI SLICE_18I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_2_I/PADDI SLICE_96I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_2_I/PADDI SLICE_101I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT i26_adj_28_SLICE_73I/OFX0 SLICE_18I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/F0 SLICE_18I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/F0 SLICE_79I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F0 SLICE_18I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/F1 SLICE_18I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/Q0 SLICE_83I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/Q0 SLICE_84I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/Q1 SLICE_19I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/Q1 SLICE_91I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/Q1 SLICE_100I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19I/Q0 SLICE_19I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19I/Q0 SLICE_100I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/Q0 SLICE_19I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/Q0 SLICE_100I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19I/F0 SLICE_19I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/F0 SLICE_19I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19I/F1 SLICE_67I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19I/F1 SLICE_87I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_23I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI i26_SLICE_71I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI i26_adj_28_SLICE_73I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_76I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_79I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_85I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_91I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_91I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_101I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_105I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_23I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_32I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_86I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_92I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_99I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23I/F1 SLICE_23I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23I/F1 SLICE_49I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23I/F1 SLICE_84I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_23I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_49I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_76I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_83I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_85I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_86I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_91I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_101I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_105I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_105I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56I/Q0 SLICE_23I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56I/Q0 SLICE_32I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_23I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_49I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_86I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_88I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_89I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_93I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23I/F0 SLICE_23I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/F0 SLICE_23I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23I/Q0 SLICE_56I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_25I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_36I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_58I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_60I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_61I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_63I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_67I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 RCKEEN_I_0_445_SLICE_70I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 i2099_SLICE_72I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 i2099_SLICE_72I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_80I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_104I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_25I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_34I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_35I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_35I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_58I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_60I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_63I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_65I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_65I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_66I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_68I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 RCKEEN_I_0_445_SLICE_70I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_74I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_100I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_25I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_34I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_34I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_43I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_44I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_56I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_60I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_63I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_65I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_69I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_75I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_78I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_87I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_95I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_100I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_100I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_102I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_25I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_31I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_31I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_32I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_34I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_34I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_36I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_58I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_58I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_60I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_61I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_63I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 i2099_SLICE_72I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 i2099_SLICE_72I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_78I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_80I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_85I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_90I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_95I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_96I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_97I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_100I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_104I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F0 SLICE_25I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95I/F1 SLICE_25I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_76I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_77I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_80I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_82I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_84I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_86I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_87I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_100I/CE (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_26I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_78I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_83I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_85I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_90I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_95I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_96I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_97I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_98I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 SLICE_26I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 SLICE_58I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 RCKEEN_I_0_445_SLICE_70I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 RCKEEN_I_0_445_SLICE_70I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 SLICE_74I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 SLICE_74I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 SLICE_103I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_26I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_49I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/F0 SLICE_26I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/F1 SLICE_26I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/F1 LEDI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_31I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_58I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_66I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_66I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 RCKEEN_I_0_445_SLICE_70I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 i2099_SLICE_72I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_80I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q1 SLICE_31I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q1 SLICE_84I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q1 SLICE_102I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q1 SLICE_102I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63I/F1 SLICE_31I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63I/F1 SLICE_63I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_31I/F0 SLICE_31I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/Q1 SLICE_31I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/Q1 SLICE_82I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/Q1 SLICE_102I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_31I/Q0 RA_10_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_31I/F1 SLICE_61I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_49I/Q0 SLICE_32I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32I/F0 SLICE_32I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32I/Q0 RA_11_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32I/F1 SLICE_83I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT RCKEEN_I_0_445_SLICE_70I/OFX0 SLICE_34I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_34I/F0 SLICE_34I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/F1 SLICE_34I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/F1 SLICE_58I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/F1 SLICE_60I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_34I/Q0 SLICE_35I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_34I/F1 SLICE_60I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/Q0 SLICE_35I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/Q0 SLICE_60I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/Q0 RCKEI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q1 SLICE_35I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83I/Q0 SLICE_35I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83I/Q0 SLICE_74I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/F0 SLICE_35I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/Q0 SLICE_35I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/F1 SLICE_104I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/Q1 SLICE_67I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/Q1 SLICE_68I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/Q1 SLICE_74I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/F0 SLICE_36I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F1 SLICE_36I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/F1 SLICE_64I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/F1 SLICE_66I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44I/F1 SLICE_43I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44I/F1 SLICE_44I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/F1 SLICE_43I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/F1 SLICE_69I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/F1 SLICE_95I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43I/F1 SLICE_43I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/Q0 SLICE_43I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43I/F0 SLICE_43I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100I/F0 SLICE_43I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100I/F0 SLICE_44I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/F0 SLICE_43I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/F0 SLICE_44I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43I/Q0 UFMCLKI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90I/F0 SLICE_44I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94I/F1 SLICE_44I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94I/F1 SLICE_75I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94I/F1 SLICE_78I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/F1 SLICE_44I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/F1 SLICE_78I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93I/Q0 SLICE_44I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/F1 SLICE_44I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44I/F0 SLICE_44I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44I/Q0 UFMSDII/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_49I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_81I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_86I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_88I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_89I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_49I/F1 SLICE_49I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_49I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI i26_SLICE_71I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI i26_adj_28_SLICE_73I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI i26_adj_28_SLICE_73I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_79I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_81I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_92I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_102I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_103I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_49I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI i26_adj_28_SLICE_73I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI i26_adj_28_SLICE_73I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_76I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_79I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_91I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_91I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_92I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_92I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_102I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_103I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_49I/F0 SLICE_49I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84I/F1 SLICE_49I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/F1 SLICE_56I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/F1 SLICE_78I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/F1 SLICE_95I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56I/F1 SLICE_56I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT UFMSDOI/PADDI SLICE_56I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56I/F0 SLICE_56I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/F0 SLICE_56I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102I/F0 SLICE_58I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F1 SLICE_58I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F1 i2099_SLICE_72I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_58I/OFX0 SLICE_58I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_58I/Q0 nRCASI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60I/F1 SLICE_60I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60I/F1 SLICE_61I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT i2099_SLICE_72I/OFX0 SLICE_60I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60I/F0 SLICE_60I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60I/Q0 nRCSI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q0 SLICE_61I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q0 SLICE_63I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q0 i2099_SLICE_72I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q0 i2099_SLICE_72I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q0 SLICE_87I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q0 SLICE_102I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_61I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_64I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_65I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_65I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_66I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_66I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_80I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100I/F1 SLICE_61I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61I/Q0 SLICE_61I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61I/Q0 nRRASI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61I/OFX0 SLICE_61I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F0 SLICE_63I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102I/F1 SLICE_63I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63I/F0 SLICE_63I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/F0 SLICE_63I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63I/Q0 nRWEI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_64I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_64I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_93I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_93I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_96I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_97I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_98I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_98I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_99I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_99I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_101I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_101I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_103I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_9_I/PADDI SLICE_64I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_9_I/PADDI SLICE_90I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_9_I/PADDI SLICE_93I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_9_I/PADDI SLICE_93I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90I/Q1 SLICE_64I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103I/F0 SLICE_64I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/F1 SLICE_64I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/F1 SLICE_80I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/F1 SLICE_104I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/F0 SLICE_64I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/F1 RA_9_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/Q1 SLICE_65I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/Q1 SLICE_87I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_65I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_66I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_67I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_74I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_80I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_100I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/F0 SLICE_65I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/F1 SLICE_104I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/F0 SLICE_66I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/F0 SLICE_67I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/Q1 SLICE_67I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_67I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 nUFMCSI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/F0 RCKEEN_I_0_445_SLICE_70I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/F1 SLICE_69I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/F0 SLICE_77I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q1 SLICE_74I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q1 SLICE_103I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94I/F0 SLICE_69I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/F0 SLICE_69I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95I/F0 SLICE_69I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q1 RCKEEN_I_0_445_SLICE_70I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q1 RCKEEN_I_0_445_SLICE_70I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q1 SLICE_74I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q1 SLICE_74I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q1 SLICE_103I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/F1 i26_SLICE_71I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/F1 SLICE_83I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F1 i26_SLICE_71I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT i26_SLICE_71I/OFX0 SLICE_105I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F0 SLICE_74I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F0 SLICE_104I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/F0 SLICE_75I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/F0 SLICE_87I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90I/F1 SLICE_75I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83I/F0 SLICE_76I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83I/F0 SLICE_83I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/F1 SLICE_76I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/F1 SLICE_91I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/Q0 SLICE_76I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/Q1 SLICE_76I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77I/F0 SLICE_77I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77I/Q0 SLICE_77I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/Q1 SLICE_77I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77I/F1 SLICE_87I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77I/Q1 SLICE_80I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_7_I/PADDI SLICE_78I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_7_I/PADDI SLICE_96I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_7_I/PADDI SLICE_99I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_6_I/PADDI SLICE_78I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_6_I/PADDI SLICE_97I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_6_I/PADDI SLICE_101I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/Q0 SLICE_101I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/Q1 SLICE_99I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F1 SLICE_79I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89I/F0 SLICE_79I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/Q1 SLICE_79I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_79I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_89I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_92I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_98I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_103I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_105I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_105I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/Q0 SLICE_80I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102I/Q1 SLICE_81I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99I/Q0 SLICE_81I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101I/Q1 SLICE_81I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/F1 SLICE_81I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97I/F0 SLICE_81I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102I/Q0 SLICE_81I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83I/F1 SLICE_81I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83I/F1 SLICE_93I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F0 SLICE_82I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/F0 SLICE_82I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/F0 SLICE_83I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/Q0 SLICE_82I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84I/F0 SLICE_84I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/F0 SLICE_84I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/F0 SLICE_85I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84I/Q0 SLICE_84I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84I/Q1 SLICE_100I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F0 SLICE_85I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/F1 SLICE_85I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/F1 SLICE_86I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/F1 SLICE_105I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT CROW_1_I/PADDI SLICE_85I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT CROW_0_I/PADDI SLICE_85I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/Q0 RBA_0_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/Q1 RBA_1_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/Q0 SLICE_86I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100I/Q1 SLICE_86I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/F1 SLICE_87I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/F0 SLICE_88I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/Q0 SLICE_97I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/Q1 SLICE_96I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89I/Q0 RD_0_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89I/Q1 RD_1_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT MAin_8_I/PADDI SLICE_90I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_8_I/PADDI SLICE_98I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90I/Q0 SLICE_98I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/Q0 RD_6_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/Q1 RD_7_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93I/F0 RDQMHI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93I/F1 RDQMLI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT MAin_4_I/PADDI SLICE_95I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_4_I/PADDI SLICE_97I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_4_I/PADDI SLICE_97I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95I/Q0 SLICE_97I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95I/Q1 SLICE_103I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_3_I/PADDI SLICE_96I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_3_I/PADDI SLICE_96I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_3_I/PADDI SLICE_96I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96I/Q1 SLICE_96I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101I/Q0 SLICE_96I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96I/Q0 SLICE_101I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96I/F1 RA_3_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99I/Q1 SLICE_97I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97I/Q0 SLICE_98I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97I/F1 RA_4_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97I/Q1 SLICE_99I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/F0 RA_8_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/F1 RA_0_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99I/F0 RA_7_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99I/F1 RA_1_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100I/Q0 SLICE_100I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101I/F0 RA_6_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101I/F1 RA_2_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103I/Q0 RD_2_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103I/F1 RA_5_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103I/Q1 RD_3_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/Q0 RD_4_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 RD_7_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 RD_6_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 RD_5_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 RD_4_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 RD_3_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 RD_2_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 RD_1_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 RD_0_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/Q1 RD_5_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_7_I/PADDI Dout_7_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_6_I/PADDI Dout_6_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_5_I/PADDI Dout_5_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_4_I/PADDI Dout_4_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_3_I/PADDI Dout_3_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_2_I/PADDI Dout_2_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_1_I/PADDI Dout_1_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_0_I/PADDI Dout_0_I/PADDO (0:0:0)(0:0:0)) + ) + ) + ) +) diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvho.vho b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvho.vho new file mode 100644 index 0000000..ab79c11 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvho.vho @@ -0,0 +1,26269 @@ + +-- VHDL netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 + +-- ldbanno -n VHDL -o RAM2GS_LCMXO256C_impl1_mapvho.vho -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd +-- Netlist created on Tue Aug 15 05:03:20 2023 +-- Netlist written on Tue Aug 15 05:03:23 2023 +-- Design is for device LCMXO256C +-- Design is for package TQFP100 +-- Design is for performance grade 3 + +-- entity vmuxregsre + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity vmuxregsre is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre : ENTITY IS TRUE; + + end vmuxregsre; + + architecture Structure of vmuxregsre is + component FL1P3DX + generic (GSR: String); + port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; + CK: in Std_logic; SD: in Std_logic; CD: in Std_logic; + Q: out Std_logic); + end component; + begin + INST01: FL1P3DX + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q); + end Structure; + +-- entity vcc + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity vcc is + port (PWR1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vcc : ENTITY IS TRUE; + + end vcc; + + architecture Structure of vcc is + component VHI + port (Z: out Std_logic); + end component; + begin + INST1: VHI + port map (Z=>PWR1); + end Structure; + +-- entity gnd + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity gnd is + port (PWR0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF gnd : ENTITY IS TRUE; + + end gnd; + + architecture Structure of gnd is + component VLO + port (Z: out Std_logic); + end component; + begin + INST1: VLO + port map (Z=>PWR0); + end Structure; + +-- entity ccu2B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity ccu2B is + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF ccu2B : ENTITY IS TRUE; + + end ccu2B; + + architecture Structure of ccu2B is + component CCU2 + generic (INIT0: String; INIT1: String; INJECT1_0: String; + INJECT1_1: String); + port (CIN: in Std_logic; A0: in Std_logic; B0: in Std_logic; + C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; + B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; + S0: out Std_logic; S1: out Std_logic; COUT0: out Std_logic; + COUT1: out Std_logic); + end component; + begin + inst1: CCU2 + generic map (INIT0 => "0xfaaa", INIT1 => "0xfaaa", INJECT1_0 => "NO", + INJECT1_1 => "NO") + port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, + C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT0=>CO0, COUT1=>CO1); + end Structure; + +-- entity SLICE_0 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_0 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_0"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_FCI_CLK : VitalDelayType := 0 ns; + tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_0 : ENTITY IS TRUE; + + end SLICE_0; + + architecture Structure of SLICE_0 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal FCI_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_0_FS_610_add_4_8_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_0_FS_610_add_4_8_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i7: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_0_FS_610_add_4_8_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i6: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_0_FS_610_add_4_8_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_8: ccu2B + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_0_FS_610_add_4_8_S0, + S1=>SLICE_0_FS_610_add_4_8_S1, CO0=>open, CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, + FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_FCI_CLK : x01 := '0'; + VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => FCI_dly, + TestSignalName => "FCI", + TestDelay => tisd_FCI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_FCI_CLK_noedge_posedge, + SetupLow => tsetup_FCI_CLK_noedge_posedge, + HoldHigh => thold_FCI_CLK_noedge_posedge, + HoldLow => thold_FCI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => FCI_CLK_TimingDatash, + Violation => tviol_FCI_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_dly'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_dly'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_dly'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_1 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_1 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_1"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_FCI_CLK : VitalDelayType := 0 ns; + tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_1 : ENTITY IS TRUE; + + end SLICE_1; + + architecture Structure of SLICE_1 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal FCI_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_1_FS_610_add_4_16_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_1_FS_610_add_4_16_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i15: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_1_FS_610_add_4_16_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i14: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_1_FS_610_add_4_16_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_16: ccu2B + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_dly, + S0=>SLICE_1_FS_610_add_4_16_S0, S1=>SLICE_1_FS_610_add_4_16_S1, + CO0=>open, CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, + FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_FCI_CLK : x01 := '0'; + VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => FCI_dly, + TestSignalName => "FCI", + TestDelay => tisd_FCI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_FCI_CLK_noedge_posedge, + SetupLow => tsetup_FCI_CLK_noedge_posedge, + HoldHigh => thold_FCI_CLK_noedge_posedge, + HoldLow => thold_FCI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => FCI_CLK_TimingDatash, + Violation => tviol_FCI_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_dly'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_dly'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_dly'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_2 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_2 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_2"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_FCI_CLK : VitalDelayType := 0 ns; + tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_2 : ENTITY IS TRUE; + + end SLICE_2; + + architecture Structure of SLICE_2 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal FCI_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_2_FS_610_add_4_6_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_2_FS_610_add_4_6_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i5: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_2_FS_610_add_4_6_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i4: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_2_FS_610_add_4_6_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_6: ccu2B + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_2_FS_610_add_4_6_S0, + S1=>SLICE_2_FS_610_add_4_6_S1, CO0=>open, CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, + FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_FCI_CLK : x01 := '0'; + VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => FCI_dly, + TestSignalName => "FCI", + TestDelay => tisd_FCI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_FCI_CLK_noedge_posedge, + SetupLow => tsetup_FCI_CLK_noedge_posedge, + HoldHigh => thold_FCI_CLK_noedge_posedge, + HoldLow => thold_FCI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => FCI_CLK_TimingDatash, + Violation => tviol_FCI_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_dly'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_dly'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_dly'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_3 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_3 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_3"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_FCI_CLK : VitalDelayType := 0 ns; + tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_3 : ENTITY IS TRUE; + + end SLICE_3; + + architecture Structure of SLICE_3 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal FCI_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_3_FS_610_add_4_14_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_3_FS_610_add_4_14_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i13: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_3_FS_610_add_4_14_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i12: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_3_FS_610_add_4_14_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_14: ccu2B + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_dly, + S0=>SLICE_3_FS_610_add_4_14_S0, S1=>SLICE_3_FS_610_add_4_14_S1, + CO0=>open, CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, + FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_FCI_CLK : x01 := '0'; + VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => FCI_dly, + TestSignalName => "FCI", + TestDelay => tisd_FCI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_FCI_CLK_noedge_posedge, + SetupLow => tsetup_FCI_CLK_noedge_posedge, + HoldHigh => thold_FCI_CLK_noedge_posedge, + HoldLow => thold_FCI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => FCI_CLK_TimingDatash, + Violation => tviol_FCI_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_dly'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_dly'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_dly'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity ccu20001 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity ccu20001 is + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF ccu20001 : ENTITY IS TRUE; + + end ccu20001; + + architecture Structure of ccu20001 is + component CCU2 + generic (INIT0: String; INIT1: String; INJECT1_0: String; + INJECT1_1: String); + port (CIN: in Std_logic; A0: in Std_logic; B0: in Std_logic; + C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; + B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; + S0: out Std_logic; S1: out Std_logic; COUT0: out Std_logic; + COUT1: out Std_logic); + end component; + begin + inst1: CCU2 + generic map (INIT0 => "0x0555", INIT1 => "0xfaaa", INJECT1_0 => "NO", + INJECT1_1 => "NO") + port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, + C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT0=>CO0, COUT1=>CO1); + end Structure; + +-- entity SLICE_4 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_4 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_4"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_4 : ENTITY IS TRUE; + + end SLICE_4; + + architecture Structure of SLICE_4 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_4_FS_610_add_4_2_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_4_FS_610_add_4_2_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu20001 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i1: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_4_FS_610_add_4_2_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i0: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_4_FS_610_add_4_2_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_2: ccu20001 + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>GNDI, S0=>SLICE_4_FS_610_add_4_2_S0, + S1=>SLICE_4_FS_610_add_4_2_S1, CO0=>open, CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, Q0_out, Q1_out, FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_dly'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_dly'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_5 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_5 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_5"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_FCI_CLK : VitalDelayType := 0 ns; + tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_5 : ENTITY IS TRUE; + + end SLICE_5; + + architecture Structure of SLICE_5 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal FCI_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_5_FS_610_add_4_12_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_5_FS_610_add_4_12_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i11: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_5_FS_610_add_4_12_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i10: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_5_FS_610_add_4_12_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_12: ccu2B + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_dly, + S0=>SLICE_5_FS_610_add_4_12_S0, S1=>SLICE_5_FS_610_add_4_12_S1, + CO0=>open, CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, + FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_FCI_CLK : x01 := '0'; + VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => FCI_dly, + TestSignalName => "FCI", + TestDelay => tisd_FCI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_FCI_CLK_noedge_posedge, + SetupLow => tsetup_FCI_CLK_noedge_posedge, + HoldHigh => thold_FCI_CLK_noedge_posedge, + HoldLow => thold_FCI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => FCI_CLK_TimingDatash, + Violation => tviol_FCI_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_dly'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_dly'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_dly'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_6 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_6 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_6"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_FCI_CLK : VitalDelayType := 0 ns; + tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_6 : ENTITY IS TRUE; + + end SLICE_6; + + architecture Structure of SLICE_6 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal FCI_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_6_FS_610_add_4_4_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_6_FS_610_add_4_4_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i3: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_6_FS_610_add_4_4_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i2: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_6_FS_610_add_4_4_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_4: ccu2B + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_6_FS_610_add_4_4_S0, + S1=>SLICE_6_FS_610_add_4_4_S1, CO0=>open, CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, + FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_FCI_CLK : x01 := '0'; + VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => FCI_dly, + TestSignalName => "FCI", + TestDelay => tisd_FCI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_FCI_CLK_noedge_posedge, + SetupLow => tsetup_FCI_CLK_noedge_posedge, + HoldHigh => thold_FCI_CLK_noedge_posedge, + HoldLow => thold_FCI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => FCI_CLK_TimingDatash, + Violation => tviol_FCI_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_dly'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_dly'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_dly'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_7 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_7 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_7"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_FCI_CLK : VitalDelayType := 0 ns; + tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_7 : ENTITY IS TRUE; + + end SLICE_7; + + architecture Structure of SLICE_7 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal FCI_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_7_FS_610_add_4_10_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_7_FS_610_add_4_10_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i9: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_7_FS_610_add_4_10_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i8: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_7_FS_610_add_4_10_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_10: ccu2B + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_dly, + S0=>SLICE_7_FS_610_add_4_10_S0, S1=>SLICE_7_FS_610_add_4_10_S1, + CO0=>open, CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, + FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_FCI_CLK : x01 := '0'; + VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => FCI_dly, + TestSignalName => "FCI", + TestDelay => tisd_FCI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_FCI_CLK_noedge_posedge, + SetupLow => tsetup_FCI_CLK_noedge_posedge, + HoldHigh => thold_FCI_CLK_noedge_posedge, + HoldLow => thold_FCI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => FCI_CLK_TimingDatash, + Violation => tviol_FCI_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_dly'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_dly'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_dly'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_8 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_8 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_8"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_FCI_CLK : VitalDelayType := 0 ns; + tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_8 : ENTITY IS TRUE; + + end SLICE_8; + + architecture Structure of SLICE_8 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal FCI_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_8_FS_610_add_4_18_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_8_FS_610_add_4_18_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i17: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_8_FS_610_add_4_18_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i16: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_8_FS_610_add_4_18_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_18: ccu2B + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_dly, + S0=>SLICE_8_FS_610_add_4_18_S0, S1=>SLICE_8_FS_610_add_4_18_S1, + CO0=>open, CO1=>open); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_FCI_CLK : x01 := '0'; + VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => FCI_dly, + TestSignalName => "FCI", + TestDelay => tisd_FCI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_FCI_CLK_noedge_posedge, + SetupLow => tsetup_FCI_CLK_noedge_posedge, + HoldHigh => thold_FCI_CLK_noedge_posedge, + HoldLow => thold_FCI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => FCI_CLK_TimingDatash, + Violation => tviol_FCI_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut4 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut4 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut4 : ENTITY IS TRUE; + + end lut4; + + architecture Structure of lut4 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xDFDF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40002 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40002 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40002 : ENTITY IS TRUE; + + end lut40002; + + architecture Structure of lut40002 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x50DC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity vmuxregsre0003 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity vmuxregsre0003 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre0003 : ENTITY IS TRUE; + + end vmuxregsre0003; + + architecture Structure of vmuxregsre0003 is + component FL1P3IY + generic (GSR: String); + port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; + CK: in Std_logic; SD: in Std_logic; CD: in Std_logic; + Q: out Std_logic); + end component; + begin + INST01: FL1P3IY + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q); + end Structure; + +-- entity inverter + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity inverter is + port (I: in Std_logic; Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF inverter : ENTITY IS TRUE; + + end inverter; + + architecture Structure of inverter is + component INV + port (A: in Std_logic; Z: out Std_logic); + end component; + begin + INST1: INV + port map (A=>I, Z=>Z); + end Structure; + +-- entity SLICE_9 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_9 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_9"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_9 : ENTITY IS TRUE; + + end SLICE_9; + + architecture Structure of SLICE_9 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40002 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + begin + i1_2_lut_3_lut: lut4 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1125_4_lut: lut40002 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + ADSubmitted_407: vmuxregsre0003 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40004 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40004 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40004 : ENTITY IS TRUE; + + end lut40004; + + architecture Structure of lut40004 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xEEEE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40005 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40005 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40005 : ENTITY IS TRUE; + + end lut40005; + + architecture Structure of lut40005 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xE0F0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity vmuxregsre0006 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity vmuxregsre0006 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre0006 : ENTITY IS TRUE; + + end vmuxregsre0006; + + architecture Structure of vmuxregsre0006 is + component FL1P3JY + generic (GSR: String); + port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; + CK: in Std_logic; SD: in Std_logic; PD: in Std_logic; + Q: out Std_logic); + end component; + begin + INST01: FL1P3JY + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q); + end Structure; + +-- entity SLICE_14 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_14 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_14"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_14 : ENTITY IS TRUE; + + end SLICE_14; + + architecture Structure of SLICE_14 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40005 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0006 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + begin + i1988_2_lut: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2062_2_lut_3_lut_4_lut: lut40005 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + C1Submitted_406: vmuxregsre0006 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40007 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40007 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40007 : ENTITY IS TRUE; + + end lut40007; + + architecture Structure of lut40007 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xDFFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40008 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40008 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40008 : ENTITY IS TRUE; + + end lut40008; + + architecture Structure of lut40008 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0800") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_18 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_18 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_18"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_18 : ENTITY IS TRUE; + + end SLICE_18; + + architecture Structure of SLICE_18 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40007 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40008 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i13_4_lut: lut40007 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i3_4_lut_adj_21: lut40008 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CmdEnable_405: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40009 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40009 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40009 : ENTITY IS TRUE; + + end lut40009; + + architecture Structure of lut40009 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0808") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40010 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40010 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40010 : ENTITY IS TRUE; + + end lut40010; + + architecture Structure of lut40010 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFFFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_19 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_19 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_19"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_19 : ENTITY IS TRUE; + + end SLICE_19; + + architecture Structure of SLICE_19 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40009 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40010 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_rep_29: lut40009 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + n2568_001_BUF1_BUF1: lut40010 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + CmdSubmitted_411: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, DI0_dly, CE_dly, CLK_dly, + F0_out, Q0_out, F1_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0 <= F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40011 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40011 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40011 : ENTITY IS TRUE; + + end lut40011; + + architecture Structure of lut40011 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFEFE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40012 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40012 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40012 : ENTITY IS TRUE; + + end lut40012; + + architecture Structure of lut40012 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xCC5C") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_23 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_23 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_23"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_23 : ENTITY IS TRUE; + + end SLICE_23; + + architecture Structure of SLICE_23 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40011 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40012 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_3_lut_adj_2: lut40011 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + Cmdn8MEGEN_I_93_4_lut: lut40012 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + Cmdn8MEGEN_410: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40013 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40013 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40013 : ENTITY IS TRUE; + + end lut40013; + + architecture Structure of lut40013 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x4000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_25 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_25 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_25"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_25 : ENTITY IS TRUE; + + end SLICE_25; + + architecture Structure of SLICE_25 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40010 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40013 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i3_3_lut_4_lut_4_lut: lut40013 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + n2568_000_BUF1_BUF1: lut40010 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + InitReady_394: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, DI0_dly, CE_dly, + CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0 <= F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40014 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40014 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40014 : ENTITY IS TRUE; + + end lut40014; + + architecture Structure of lut40014 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFDFD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_26 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_26 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_26"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_26 : ENTITY IS TRUE; + + end SLICE_26; + + architecture Structure of SLICE_26 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40010 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40014 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2049_3_lut: lut40014 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + m1_lut: lut40010 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + LEDEN_419: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, DI0_dly, CE_dly, CLK_dly, + F0_out, Q0_out, F1_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0 <= F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40015 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40015 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40015 : ENTITY IS TRUE; + + end lut40015; + + architecture Structure of lut40015 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xDDDD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_31 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_31 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_31"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_31 : ENTITY IS TRUE; + + end SLICE_31; + + architecture Structure of SLICE_31 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component vmuxregsre0006 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40011 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40015 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_2_lut: lut40015 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_3_lut_adj_27: lut40011 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + RA10_400: vmuxregsre0006 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, + LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40016 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40016 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40016 : ENTITY IS TRUE; + + end lut40016; + + architecture Structure of lut40016 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xC6C6") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_32 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_32 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_32"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_32 : ENTITY IS TRUE; + + end SLICE_32; + + architecture Structure of SLICE_32 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40016 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + Din_7_I_0_462_i6_2_lut_rep_35: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RA11_I_54_3_lut: lut40016 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + RA11_385: vmuxregsre0003 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, + LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40017 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40017 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40017 : ENTITY IS TRUE; + + end lut40017; + + architecture Structure of lut40017 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xF8F8") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40018 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40018 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40018 : ENTITY IS TRUE; + + end lut40018; + + architecture Structure of lut40018 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xCACA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_34 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_34 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_34"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_34 : ENTITY IS TRUE; + + end SLICE_34; + + architecture Structure of SLICE_34 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40017 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i78_2_lut_rep_24_3_lut: lut40017 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1259_3_lut: lut40018 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + RCKEEN_401: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40019 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40019 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40019 : ENTITY IS TRUE; + + end lut40019; + + architecture Structure of lut40019 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xBBBB") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40020 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40020 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40020 : ENTITY IS TRUE; + + end lut40020; + + architecture Structure of lut40020 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xCFC8") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_35 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_35 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_35"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_35 : ENTITY IS TRUE; + + end SLICE_35; + + architecture Structure of SLICE_35 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40019 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40020 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut: lut40019 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RCKE_I_0_449_4_lut: lut40020 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CASr2_383: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + RCKE_395: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_36 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_36 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_36"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_36 : ENTITY IS TRUE; + + end SLICE_36; + + architecture Structure of SLICE_36 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40010 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40015 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i771_2_lut_rep_26_2_lut: lut40015 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + n2568_002_BUF1_BUF1: lut40010 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + Ready_404: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, + Q0_out, F1_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0 <= F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40021 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40021 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40021 : ENTITY IS TRUE; + + end lut40021; + + architecture Structure of lut40021 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x3A0A") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40022 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40022 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40022 : ENTITY IS TRUE; + + end lut40022; + + architecture Structure of lut40022 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xACAC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_43 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_43 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_43"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_43 : ENTITY IS TRUE; + + end SLICE_43; + + architecture Structure of SLICE_43 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40022 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i919_4_lut: lut40021 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i886_3_lut: lut40022 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + UFMCLK_416: vmuxregsre0003 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40023 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40023 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40023 : ENTITY IS TRUE; + + end lut40023; + + architecture Structure of lut40023 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFEFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40024 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40024 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40024 : ENTITY IS TRUE; + + end lut40024; + + architecture Structure of lut40024 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xF202") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_44 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_44 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_44"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_44 : ENTITY IS TRUE; + + end SLICE_44; + + architecture Structure of SLICE_44 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40023 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40024 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_19_4_lut: lut40023 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + n2454_bdd_3_lut_4_lut: lut40024 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + UFMSDI_417: vmuxregsre0003 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, + F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40025 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40025 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40025 : ENTITY IS TRUE; + + end lut40025; + + architecture Structure of lut40025 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFEFA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40026 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40026 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40026 : ENTITY IS TRUE; + + end lut40026; + + architecture Structure of lut40026 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0020") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_49 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_49 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_49"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_49 : ENTITY IS TRUE; + + end SLICE_49; + + architecture Structure of SLICE_49 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40025 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40026 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2028_4_lut: lut40025 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i3_4_lut_adj_12: lut40026 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + XOR8MEG_408: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40027 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40027 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40027 : ENTITY IS TRUE; + + end lut40027; + + architecture Structure of lut40027 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xCCC5") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_56 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_56 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_56"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_56 : ENTITY IS TRUE; + + end SLICE_56; + + architecture Structure of SLICE_56 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40027 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_3_lut_adj_4: lut4 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + n8MEGEN_I_14_4_lut: lut40027 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + n8MEGEN_418: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40028 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40028 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40028 : ENTITY IS TRUE; + + end lut40028; + + architecture Structure of lut40028 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x7F2F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40029 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40029 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40029 : ENTITY IS TRUE; + + end lut40029; + + architecture Structure of lut40029 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xBFBF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity vmuxregsre0030 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity vmuxregsre0030 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre0030 : ENTITY IS TRUE; + + end vmuxregsre0030; + + architecture Structure of vmuxregsre0030 is + component FL1P3BX + generic (GSR: String); + port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; + CK: in Std_logic; SD: in Std_logic; PD: in Std_logic; + Q: out Std_logic); + end component; + begin + INST01: FL1P3BX + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q); + end Structure; + +-- entity selmux2 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity selmux2 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF selmux2 : ENTITY IS TRUE; + + end selmux2; + + architecture Structure of selmux2 is + component MUX21 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + begin + INST1: MUX21 + port map (D0=>D0, D1=>D1, SD=>SD, Z=>Z); + end Structure; + +-- entity SLICE_58 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_58 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_58"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; + Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_58 : ENTITY IS TRUE; + + end SLICE_58; + + architecture Structure of SLICE_58 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal SLICE_58_SLICE_58_K1_H1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_58_i2095_GATE_H0: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40028 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40029 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0030 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + begin + SLICE_58_K1: lut40028 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, + Z=>SLICE_58_SLICE_58_K1_H1); + i2095_GATE: lut40029 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, + Z=>SLICE_58_i2095_GATE_H0); + DRIVEGND: gnd + port map (PWR0=>GNDI); + nRCAS_398: vmuxregsre0030 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + SLICE_58_K0K1MUX: selmux2 + port map (D0=>SLICE_58_i2095_GATE_H0, D1=>SLICE_58_SLICE_58_K1_H1, + SD=>M0_ipd, Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, M0_ipd, CE_dly, CLK_dly, OFX0_out, Q0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + OFX0_zd := OFX0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 7 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40031 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40031 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40031 : ENTITY IS TRUE; + + end lut40031; + + architecture Structure of lut40031 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFA88") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40032 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40032 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40032 : ENTITY IS TRUE; + + end lut40032; + + architecture Structure of lut40032 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xCFDD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_60 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_60 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_60"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_60 : ENTITY IS TRUE; + + end SLICE_60; + + architecture Structure of SLICE_60 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0030 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40031 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40032 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1234_4_lut_4_lut: lut40031 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_4_lut_adj_17: lut40032 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nRCS_396: vmuxregsre0030 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40033 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40033 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40033 : ENTITY IS TRUE; + + end lut40033; + + architecture Structure of lut40033 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x7373") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40034 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40034 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40034 : ENTITY IS TRUE; + + end lut40034; + + architecture Structure of lut40034 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFFFE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_61 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_61 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_61"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_61 : ENTITY IS TRUE; + + end SLICE_61; + + architecture Structure of SLICE_61 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal SLICE_61_SLICE_61_K1_H1: Std_logic; + signal SLICE_61_i16_GATE_H0: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0030 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + component lut40033 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + SLICE_61_K1: lut40033 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, + Z=>SLICE_61_SLICE_61_K1_H1); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i16_GATE: lut40034 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, + Z=>SLICE_61_i16_GATE_H0); + nRRAS_397: vmuxregsre0030 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + SLICE_61_K0K1MUX: selmux2 + port map (D0=>SLICE_61_i16_GATE_H0, D1=>SLICE_61_SLICE_61_K1_H1, + SD=>M0_ipd, Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, M0_ipd, CLK_dly, OFX0_out, Q0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + OFX0_zd := OFX0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 7 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40035 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40035 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40035 : ENTITY IS TRUE; + + end lut40035; + + architecture Structure of lut40035 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFF7F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40036 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40036 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40036 : ENTITY IS TRUE; + + end lut40036; + + architecture Structure of lut40036 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xCFC5") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_63 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_63 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_63"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_63 : ENTITY IS TRUE; + + end SLICE_63; + + architecture Structure of SLICE_63 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0030 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40035 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40036 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_4_lut_adj_8: lut40035 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + nRWE_I_0_455_4_lut: lut40036 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nRWE_399: vmuxregsre0030 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40037 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40037 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40037 : ENTITY IS TRUE; + + end lut40037; + + architecture Structure of lut40037 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xCFEE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_64 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_64 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_64"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_64 : ENTITY IS TRUE; + + end SLICE_64; + + architecture Structure of SLICE_64 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40037 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i10_3_lut: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1_4_lut: lut40037 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nRowColSel_402: vmuxregsre0003 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40038 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40038 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40038 : ENTITY IS TRUE; + + end lut40038; + + architecture Structure of lut40038 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x2000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_65 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_65 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_65"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_65 : ENTITY IS TRUE; + + end SLICE_65; + + architecture Structure of SLICE_65 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40038 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + Ready_bdd_4_lut: lut40038 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut_adj_25: lut40004 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + S_FSM_i4: vmuxregsre0003 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40039 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40039 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40039 : ENTITY IS TRUE; + + end lut40039; + + architecture Structure of lut40039 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFFFE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40040 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40040 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40040 : ENTITY IS TRUE; + + end lut40040; + + architecture Structure of lut40040 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x4444") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_66 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_66 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_66"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_66 : ENTITY IS TRUE; + + end SLICE_66; + + architecture Structure of SLICE_66 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40040 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_4_lut: lut40039 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i2057_2_lut: lut40040 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + S_FSM_i3: vmuxregsre0003 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40041 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40041 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40041 : ENTITY IS TRUE; + + end lut40041; + + architecture Structure of lut40041 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x3A3A") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_67 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_67 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_67"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_67 : ENTITY IS TRUE; + + end SLICE_67; + + architecture Structure of SLICE_67 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40019 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40041 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1129_3_lut: lut40041 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1_2_lut_adj_23: lut40019 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + S_FSM_i2: vmuxregsre0003 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, M0_dly, + LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_68 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_68 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_68"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_68 : ENTITY IS TRUE; + + end SLICE_68; + + architecture Structure of SLICE_68 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal M0_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2024_2_lut_rep_28: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2026_4_lut: lut40039 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CASr3_384: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + S_FSM_i1: vmuxregsre + port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + M0_INVERTERIN: inverter + port map (I=>M0_dly, Z=>M0_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40042 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40042 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40042 : ENTITY IS TRUE; + + end lut40042; + + architecture Structure of lut40042 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x8000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_69 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_69 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_69"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_69 : ENTITY IS TRUE; + + end SLICE_69; + + architecture Structure of SLICE_69 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0006 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40042 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i6_4_lut: lut40042 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i11_3_lut: lut40018 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + nUFMCS_415: vmuxregsre0006 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40043 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40043 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40043 : ENTITY IS TRUE; + + end lut40043; + + architecture Structure of lut40043 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x1F1F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40044 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40044 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40044 : ENTITY IS TRUE; + + end lut40044; + + architecture Structure of lut40044 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x5540") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity RCKEEN_I_0_445_SLICE_70 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RCKEEN_I_0_445_SLICE_70 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RCKEEN_I_0_445_SLICE_70"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RCKEEN_I_0_445_SLICE_70 : ENTITY IS TRUE; + + end RCKEEN_I_0_445_SLICE_70; + + architecture Structure of RCKEEN_I_0_445_SLICE_70 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal RCKEEN_I_0_445_SLICE_70_RCKEEN_I_0_445_SLICE_70_K1_H1: Std_logic; + signal RCKEEN_I_0_445_SLICE_70_RCKEEN_I_0_445_GATE_H0: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + component lut40043 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40044 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RCKEEN_I_0_445_SLICE_70_K1: lut40043 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, + Z=>RCKEEN_I_0_445_SLICE_70_RCKEEN_I_0_445_SLICE_70_K1_H1); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RCKEEN_I_0_445_GATE: lut40044 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, + Z=>RCKEEN_I_0_445_SLICE_70_RCKEEN_I_0_445_GATE_H0); + RCKEEN_I_0_445_SLICE_70_K0K1MUX: selmux2 + port map (D0=>RCKEEN_I_0_445_SLICE_70_RCKEEN_I_0_445_GATE_H0, + D1=>RCKEEN_I_0_445_SLICE_70_RCKEEN_I_0_445_SLICE_70_K1_H1, + SD=>M0_ipd, Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M0_ipd, OFX0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + OFX0_zd := OFX0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 7 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40045 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40045 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40045 : ENTITY IS TRUE; + + end lut40045; + + architecture Structure of lut40045 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0080") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40046 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40046 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40046 : ENTITY IS TRUE; + + end lut40046; + + architecture Structure of lut40046 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0004") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity i26_SLICE_71 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity i26_SLICE_71 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "i26_SLICE_71"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + OFX0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF i26_SLICE_71 : ENTITY IS TRUE; + + end i26_SLICE_71; + + architecture Structure of i26_SLICE_71 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + + signal i26_SLICE_71_i26_SLICE_71_K1_H1: Std_logic; + signal i26_SLICE_71_i26_GATE_H0: Std_logic; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + component lut40045 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40046 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i26_SLICE_71_K1: lut40045 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, + Z=>i26_SLICE_71_i26_SLICE_71_K1_H1); + i26_GATE: lut40046 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, + Z=>i26_SLICE_71_i26_GATE_H0); + i26_SLICE_71_K0K1MUX: selmux2 + port map (D0=>i26_SLICE_71_i26_GATE_H0, + D1=>i26_SLICE_71_i26_SLICE_71_K1_H1, SD=>M0_ipd, Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M0_ipd, OFX0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + OFX0_zd := OFX0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 7 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 8 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40047 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40047 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40047 : ENTITY IS TRUE; + + end lut40047; + + architecture Structure of lut40047 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x2F23") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40048 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40048 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40048 : ENTITY IS TRUE; + + end lut40048; + + architecture Structure of lut40048 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x2F2F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity i2099_SLICE_72 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity i2099_SLICE_72 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "i2099_SLICE_72"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF i2099_SLICE_72 : ENTITY IS TRUE; + + end i2099_SLICE_72; + + architecture Structure of i2099_SLICE_72 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + + signal i2099_SLICE_72_i2099_SLICE_72_K1_H1: Std_logic; + signal GNDI: Std_logic; + signal i2099_SLICE_72_i2099_GATE_H0: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + component lut40047 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40048 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2099_SLICE_72_K1: lut40047 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, + Z=>i2099_SLICE_72_i2099_SLICE_72_K1_H1); + i2099_GATE: lut40048 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, + Z=>i2099_SLICE_72_i2099_GATE_H0); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2099_SLICE_72_K0K1MUX: selmux2 + port map (D0=>i2099_SLICE_72_i2099_GATE_H0, + D1=>i2099_SLICE_72_i2099_SLICE_72_K1_H1, SD=>M0_ipd, + Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, M0_ipd, OFX0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + OFX0_zd := OFX0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 7 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40049 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40049 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40049 : ENTITY IS TRUE; + + end lut40049; + + architecture Structure of lut40049 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x4000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40050 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40050 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40050 : ENTITY IS TRUE; + + end lut40050; + + architecture Structure of lut40050 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0002") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity i26_adj_28_SLICE_73 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity i26_adj_28_SLICE_73 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "i26_adj_28_SLICE_73"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + OFX0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF i26_adj_28_SLICE_73 : ENTITY IS TRUE; + + end i26_adj_28_SLICE_73; + + architecture Structure of i26_adj_28_SLICE_73 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + + signal i26_adj_28_SLICE_73_i26_adj_28_SLICE_73_K1_H1: Std_logic; + signal i26_adj_28_SLICE_73_i26_adj_28_GATE_H0: Std_logic; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + component lut40049 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40050 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i26_adj_28_SLICE_73_K1: lut40049 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, + Z=>i26_adj_28_SLICE_73_i26_adj_28_SLICE_73_K1_H1); + i26_adj_28_GATE: lut40050 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, + Z=>i26_adj_28_SLICE_73_i26_adj_28_GATE_H0); + i26_adj_28_SLICE_73_K0K1MUX: selmux2 + port map (D0=>i26_adj_28_SLICE_73_i26_adj_28_GATE_H0, + D1=>i26_adj_28_SLICE_73_i26_adj_28_SLICE_73_K1_H1, SD=>M0_ipd, + Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M0_ipd, OFX0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + OFX0_zd := OFX0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 7 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 8 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40051 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40051 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40051 : ENTITY IS TRUE; + + end lut40051; + + architecture Structure of lut40051 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x1F10") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40052 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40052 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40052 : ENTITY IS TRUE; + + end lut40052; + + architecture Structure of lut40052 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0040") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_74 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_74 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_74"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_74 : ENTITY IS TRUE; + + end SLICE_74; + + architecture Structure of SLICE_74 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40051 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40052 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i35_3_lut_4_lut: lut40051 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i3_4_lut: lut40052 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RASr3_381: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RASr2_380: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40053 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40053 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40053 : ENTITY IS TRUE; + + end lut40053; + + architecture Structure of lut40053 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0200") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_75 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_75 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_75"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_75 : ENTITY IS TRUE; + + end SLICE_75; + + architecture Structure of SLICE_75 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40009 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40053 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut: lut40009 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i7_4_lut: lut40053 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40054 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40054 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40054 : ENTITY IS TRUE; + + end lut40054; + + architecture Structure of lut40054 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x1000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40055 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40055 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40055 : ENTITY IS TRUE; + + end lut40055; + + architecture Structure of lut40055 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xB300") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_76 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_76 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_76"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_76 : ENTITY IS TRUE; + + end SLICE_76; + + architecture Structure of SLICE_76 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40054 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40055 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i5_3_lut_rep_15_4_lut: lut40054 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_4_lut_4_lut: lut40055 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + IS_FSM_i9: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_FSM_i8: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, + Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40056 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40056 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40056 : ENTITY IS TRUE; + + end lut40056; + + architecture Structure of lut40056 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0004") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_77 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_77 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_77"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_77 : ENTITY IS TRUE; + + end SLICE_77; + + architecture Structure of SLICE_77 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40011 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40056 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i3_4_lut_adj_18: lut40056 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1994_3_lut: lut40011 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_FSM_i13: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i12: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40057 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40057 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40057 : ENTITY IS TRUE; + + end lut40057; + + architecture Structure of lut40057 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0101") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_78 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_78 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_78"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_78 : ENTITY IS TRUE; + + end SLICE_78; + + architecture Structure of SLICE_78 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40057 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i5_3_lut_rep_21_4_lut: lut40039 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i2065_2_lut_3_lut: lut40057 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RowA_i7: vmuxregsre0003 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i6: vmuxregsre0003 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40058 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40058 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40058 : ENTITY IS TRUE; + + end lut40058; + + architecture Structure of lut40058 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0202") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40059 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40059 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40059 : ENTITY IS TRUE; + + end lut40059; + + architecture Structure of lut40059 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0400") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_79 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_79 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_79"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_79 : ENTITY IS TRUE; + + end SLICE_79; + + architecture Structure of SLICE_79 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal M0_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40058 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40059 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_25_3_lut: lut40058 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_4_lut: lut40059 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + PHI2r2_377: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CASr_382: vmuxregsre + port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + M0_INVERTERIN: inverter + port map (I=>M0_dly, Z=>M0_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40060 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40060 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40060 : ENTITY IS TRUE; + + end lut40060; + + architecture Structure of lut40060 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFFFD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_80 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_80 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_80"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_80 : ENTITY IS TRUE; + + end SLICE_80; + + architecture Structure of SLICE_80 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40060 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_adj_16: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1_2_lut_3_lut_4_lut_4_lut: lut40060 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + IS_FSM_i15: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i14: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40061 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40061 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40061 : ENTITY IS TRUE; + + end lut40061; + + architecture Structure of lut40061 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x8888") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40062 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40062 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40062 : ENTITY IS TRUE; + + end lut40062; + + architecture Structure of lut40062 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xBFFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_81 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_81 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_81"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_81 : ENTITY IS TRUE; + + end SLICE_81; + + architecture Structure of SLICE_81 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40061 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40062 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1982_2_lut: lut40061 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i12_4_lut: lut40062 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CmdUFMCS_412: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + CmdUFMCLK_413: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40063 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40063 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40063 : ENTITY IS TRUE; + + end lut40063; + + architecture Structure of lut40063 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0302") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_82 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_82 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_82"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_82 : ENTITY IS TRUE; + + end SLICE_82; + + architecture Structure of SLICE_82 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40063 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2052_4_lut: lut40063 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1990_2_lut_rep_17: lut40004 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_FSM_i11: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i10: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_83 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_83 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_83"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_83 : ENTITY IS TRUE; + + end SLICE_83; + + architecture Structure of SLICE_83 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal M0_NOTIN: Std_logic; + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40008 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40026 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_4_lut: lut40008 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i4_4_lut: lut40026 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RASr_379: vmuxregsre + port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + M0_INVERTERIN: inverter + port map (I=>M0_dly, Z=>M0_NOTIN); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_84 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_84 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_84"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_84 : ENTITY IS TRUE; + + end SLICE_84; + + architecture Structure of SLICE_84 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40014 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40056 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_4_lut_adj_11: lut40056 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut_3_lut_adj_5: lut40014 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_FSM_i3: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i2: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_85 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_85 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_85"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_85 : ENTITY IS TRUE; + + end SLICE_85; + + architecture Structure of SLICE_85 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40013 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_4_lut_adj_15: lut40013 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i2004_2_lut_rep_30: lut40004 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RBA_i2: vmuxregsre0003 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RBA_i1: vmuxregsre0003 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40064 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40064 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40064 : ENTITY IS TRUE; + + end lut40064; + + architecture Structure of lut40064 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x1010") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_86 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_86 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_86"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_86 : ENTITY IS TRUE; + + end SLICE_86; + + architecture Structure of SLICE_86 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40009 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40064 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_adj_10: lut40009 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1_2_lut_rep_20_3_lut: lut40064 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + IS_FSM_i7: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i6: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40065 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40065 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40065 : ENTITY IS TRUE; + + end lut40065; + + architecture Structure of lut40065 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xCAC0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_87 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_87 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_87"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_87 : ENTITY IS TRUE; + + end SLICE_87; + + architecture Structure of SLICE_87 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40040 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40065 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_2_lut: lut40040 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i17_4_lut: lut40065 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + IS_FSM_i1: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i0: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40066 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40066 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40066 : ENTITY IS TRUE; + + end lut40066; + + architecture Structure of lut40066 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0062") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_88 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_88 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_88"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_88 : ENTITY IS TRUE; + + end SLICE_88; + + architecture Structure of SLICE_88 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40009 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40066 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + n2452_bdd_2_lut_rep_18_3_lut: lut40009 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_6_bdd_4_lut: lut40066 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + Bank_i1: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + Bank_i0: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_89 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_89 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_89"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_89 : ENTITY IS TRUE; + + end SLICE_89; + + architecture Structure of SLICE_89 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40014 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40064 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_16_3_lut: lut40064 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_3_lut_adj_1: lut40014 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + WRD_i1: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + WRD_i0: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_90 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_90 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_90"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_90 : ENTITY IS TRUE; + + end SLICE_90; + + architecture Structure of SLICE_90 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0006 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2032_2_lut_3_lut_4_lut: lut40039 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i2_2_lut_rep_27: lut40004 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RowA_i9: vmuxregsre0006 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i8: vmuxregsre0003 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40067 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40067 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40067 : ENTITY IS TRUE; + + end lut40067; + + architecture Structure of lut40067 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x8C00") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_91 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_91 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_91"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_91 : ENTITY IS TRUE; + + end SLICE_91; + + architecture Structure of SLICE_91 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40061 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40067 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_33: lut40061 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_4_lut_adj_3: lut40067 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + PHI2r_376: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + PHI2r3_378: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40068 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40068 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40068 : ENTITY IS TRUE; + + end lut40068; + + architecture Structure of lut40068 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x2222") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40069 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40069 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40069 : ENTITY IS TRUE; + + end lut40069; + + architecture Structure of lut40069 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x4040") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_92 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_92 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_92"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_92 : ENTITY IS TRUE; + + end SLICE_92; + + architecture Structure of SLICE_92 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40068 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40069 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_32: lut40068 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_3_lut_rep_31: lut40069 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + WRD_i7: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + WRD_i6: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, + M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40070 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40070 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40070 : ENTITY IS TRUE; + + end lut40070; + + architecture Structure of lut40070 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x7777") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_93 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_93 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_93"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_93 : ENTITY IS TRUE; + + end SLICE_93; + + architecture Structure of SLICE_93 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40019 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40070 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2060_2_lut: lut40070 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1512_2_lut: lut40019 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + CmdUFMSDI_414: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, M0_dly, CE_dly, + CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_94 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_94 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_94"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_94 : ENTITY IS TRUE; + + end SLICE_94; + + architecture Structure of SLICE_94 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40042 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1976_2_lut: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i5_4_lut: lut40042 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40071 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40071 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40071 : ENTITY IS TRUE; + + end lut40071; + + architecture Structure of lut40071 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0001") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_95 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_95 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_95"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_95 : ENTITY IS TRUE; + + end SLICE_95; + + architecture Structure of SLICE_95 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component vmuxregsre0006 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40061 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40071 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_adj_22: lut40061 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2055_3_lut_4_lut: lut40071 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RowA_i5: vmuxregsre0006 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i4: vmuxregsre0003 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_96 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_96 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_96"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_96 : ENTITY IS TRUE; + + end SLICE_96; + + architecture Structure of SLICE_96 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40042 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i4_3_lut: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2020_4_lut: lut40042 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RowA_i3: vmuxregsre0003 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i2: vmuxregsre0003 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_97 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_97 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_97"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_97 : ENTITY IS TRUE; + + end SLICE_97; + + architecture Structure of SLICE_97 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40042 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i5_3_lut: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2018_4_lut: lut40042 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RowA_i1: vmuxregsre0003 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i0: vmuxregsre0003 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_98 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_98 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_98"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_98 : ENTITY IS TRUE; + + end SLICE_98; + + architecture Structure of SLICE_98 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal M1_NOTIN: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal M0_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i1_3_lut: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_9_I_0_427_i9_3_lut: lut40018 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + FWEr_389: vmuxregsre + port map (D0=>M1_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + M1_INVERTERIN: inverter + port map (I=>M1_dly, Z=>M1_NOTIN); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + CBR_390: vmuxregsre + port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + M0_INVERTERIN: inverter + port map (I=>M0_dly, Z=>M0_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_99 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_99 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_99"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_99 : ENTITY IS TRUE; + + end SLICE_99; + + architecture Structure of SLICE_99 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i2_3_lut: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_9_I_0_427_i8_3_lut: lut40018 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + Bank_i7: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + Bank_i6: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40072 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40072 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40072 : ENTITY IS TRUE; + + end lut40072; + + architecture Structure of lut40072 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xF0F7") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40073 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40073 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40073 : ENTITY IS TRUE; + + end lut40073; + + architecture Structure of lut40073 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x08FF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_100 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_100 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_100"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_100 : ENTITY IS TRUE; + + end SLICE_100; + + architecture Structure of SLICE_100 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40072 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40073 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_2_lut_3_lut_4_lut: lut40072 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut_4_lut_adj_7: lut40073 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + IS_FSM_i5: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_FSM_i4: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, + Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_101 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_101 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_101"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_101 : ENTITY IS TRUE; + + end SLICE_101; + + architecture Structure of SLICE_101 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i3_3_lut: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_9_I_0_427_i7_3_lut: lut40018 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + Bank_i5: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + Bank_i4: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_102 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_102 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_102"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_102 : ENTITY IS TRUE; + + end SLICE_102; + + architecture Structure of SLICE_102 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40014 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_adj_26: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + InitReady_bdd_3_lut: lut40014 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + Bank_i3: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + Bank_i2: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, + M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_103 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_103 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_103"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_103 : ENTITY IS TRUE; + + end SLICE_103; + + architecture Structure of SLICE_103 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40014 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i6_3_lut: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_3_lut_adj_14: lut40014 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + WRD_i3: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + WRD_i2: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40074 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40074 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40074 : ENTITY IS TRUE; + + end lut40074; + + architecture Structure of lut40074 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xF0DD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_104 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_104 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_104"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_104 : ENTITY IS TRUE; + + end SLICE_104; + + architecture Structure of SLICE_104 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40074 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + n2414_bdd_2_lut: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + n1_bdd_4_lut: lut40074 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40075 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40075 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40075 : ENTITY IS TRUE; + + end lut40075; + + architecture Structure of lut40075 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x2020") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_105 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_105 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_105"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_105 : ENTITY IS TRUE; + + end SLICE_105; + + architecture Structure of SLICE_105 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40075 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1513_2_lut: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_3_lut_adj_20: lut40075 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + WRD_i5: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + WRD_i4: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, + M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity mjiobuf + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity mjiobuf is + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + + ATTRIBUTE Vital_Level0 OF mjiobuf : ENTITY IS TRUE; + + end mjiobuf; + + architecture Structure of mjiobuf is + component IBPU + port (I: in Std_logic; O: out Std_logic); + end component; + component OBZPU + port (I: in Std_logic; T: in Std_logic; O: out Std_logic); + end component; + begin + INST1: IBPU + port map (I=>PADI, O=>Z); + INST2: OBZPU + port map (I=>I, T=>T, O=>PAD); + end Structure; + +-- entity RD_7_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RD_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_7_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD7 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD7_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD7 : VitalDelayType := 0 ns; + tpw_RD7_posedge : VitalDelayType := 0 ns; + tpw_RD7_negedge : VitalDelayType := 0 ns; + tpd_RD7_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD7: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_7_B : ENTITY IS TRUE; + + end RD_7_B; + + architecture Structure of RD_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD7_ipd : std_logic := 'X'; + signal RD7_out : std_logic := 'Z'; + + component mjiobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_7_713: mjiobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD7_out, + PADI=>RD7_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD7_ipd, RD7, tipd_RD7); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD7_ipd, RD7_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD7_zd : std_logic := 'X'; + VARIABLE RD7_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD7_RD7 : x01 := '0'; + VARIABLE periodcheckinfo_RD7 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD7_ipd, + TestSignalName => "RD7", + Period => tperiod_RD7, + PulseWidthHigh => tpw_RD7_posedge, + PulseWidthLow => tpw_RD7_negedge, + PeriodData => periodcheckinfo_RD7, + Violation => tviol_RD7_RD7, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD7_zd := RD7_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD7_ipd'last_event, + PathDelay => tpd_RD7_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD7, OutSignalName => "RD7", OutTemp => RD7_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD7, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD7, + PathCondition => TRUE)), + GlitchData => RD7_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_6_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RD_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_6_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD6 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD6_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD6 : VitalDelayType := 0 ns; + tpw_RD6_posedge : VitalDelayType := 0 ns; + tpw_RD6_negedge : VitalDelayType := 0 ns; + tpd_RD6_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD6: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_6_B : ENTITY IS TRUE; + + end RD_6_B; + + architecture Structure of RD_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD6_ipd : std_logic := 'X'; + signal RD6_out : std_logic := 'Z'; + + component mjiobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_6_714: mjiobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD6_out, + PADI=>RD6_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD6_ipd, RD6, tipd_RD6); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD6_ipd, RD6_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD6_zd : std_logic := 'X'; + VARIABLE RD6_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD6_RD6 : x01 := '0'; + VARIABLE periodcheckinfo_RD6 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD6_ipd, + TestSignalName => "RD6", + Period => tperiod_RD6, + PulseWidthHigh => tpw_RD6_posedge, + PulseWidthLow => tpw_RD6_negedge, + PeriodData => periodcheckinfo_RD6, + Violation => tviol_RD6_RD6, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD6_zd := RD6_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD6_ipd'last_event, + PathDelay => tpd_RD6_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD6, OutSignalName => "RD6", OutTemp => RD6_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD6, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD6, + PathCondition => TRUE)), + GlitchData => RD6_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_5_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RD_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_5_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD5 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD5_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD5 : VitalDelayType := 0 ns; + tpw_RD5_posedge : VitalDelayType := 0 ns; + tpw_RD5_negedge : VitalDelayType := 0 ns; + tpd_RD5_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD5: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_5_B : ENTITY IS TRUE; + + end RD_5_B; + + architecture Structure of RD_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD5_ipd : std_logic := 'X'; + signal RD5_out : std_logic := 'Z'; + + component mjiobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_5_715: mjiobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD5_out, + PADI=>RD5_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD5_ipd, RD5, tipd_RD5); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD5_ipd, RD5_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD5_zd : std_logic := 'X'; + VARIABLE RD5_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD5_RD5 : x01 := '0'; + VARIABLE periodcheckinfo_RD5 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD5_ipd, + TestSignalName => "RD5", + Period => tperiod_RD5, + PulseWidthHigh => tpw_RD5_posedge, + PulseWidthLow => tpw_RD5_negedge, + PeriodData => periodcheckinfo_RD5, + Violation => tviol_RD5_RD5, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD5_zd := RD5_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD5_ipd'last_event, + PathDelay => tpd_RD5_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD5, OutSignalName => "RD5", OutTemp => RD5_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD5, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD5, + PathCondition => TRUE)), + GlitchData => RD5_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_4_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RD_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_4_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD4 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD4_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD4 : VitalDelayType := 0 ns; + tpw_RD4_posedge : VitalDelayType := 0 ns; + tpw_RD4_negedge : VitalDelayType := 0 ns; + tpd_RD4_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD4: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_4_B : ENTITY IS TRUE; + + end RD_4_B; + + architecture Structure of RD_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD4_ipd : std_logic := 'X'; + signal RD4_out : std_logic := 'Z'; + + component mjiobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_4_716: mjiobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD4_out, + PADI=>RD4_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD4_ipd, RD4, tipd_RD4); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD4_ipd, RD4_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD4_zd : std_logic := 'X'; + VARIABLE RD4_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD4_RD4 : x01 := '0'; + VARIABLE periodcheckinfo_RD4 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD4_ipd, + TestSignalName => "RD4", + Period => tperiod_RD4, + PulseWidthHigh => tpw_RD4_posedge, + PulseWidthLow => tpw_RD4_negedge, + PeriodData => periodcheckinfo_RD4, + Violation => tviol_RD4_RD4, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD4_zd := RD4_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD4_ipd'last_event, + PathDelay => tpd_RD4_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD4, OutSignalName => "RD4", OutTemp => RD4_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD4, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD4, + PathCondition => TRUE)), + GlitchData => RD4_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_3_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RD_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_3_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD3 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD3_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD3 : VitalDelayType := 0 ns; + tpw_RD3_posedge : VitalDelayType := 0 ns; + tpw_RD3_negedge : VitalDelayType := 0 ns; + tpd_RD3_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD3: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_3_B : ENTITY IS TRUE; + + end RD_3_B; + + architecture Structure of RD_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD3_ipd : std_logic := 'X'; + signal RD3_out : std_logic := 'Z'; + + component mjiobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_3_717: mjiobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD3_out, + PADI=>RD3_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD3_ipd, RD3, tipd_RD3); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD3_ipd, RD3_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD3_zd : std_logic := 'X'; + VARIABLE RD3_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD3_RD3 : x01 := '0'; + VARIABLE periodcheckinfo_RD3 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD3_ipd, + TestSignalName => "RD3", + Period => tperiod_RD3, + PulseWidthHigh => tpw_RD3_posedge, + PulseWidthLow => tpw_RD3_negedge, + PeriodData => periodcheckinfo_RD3, + Violation => tviol_RD3_RD3, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD3_zd := RD3_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD3_ipd'last_event, + PathDelay => tpd_RD3_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD3, OutSignalName => "RD3", OutTemp => RD3_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD3, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD3, + PathCondition => TRUE)), + GlitchData => RD3_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_2_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RD_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_2_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD2 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD2_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD2 : VitalDelayType := 0 ns; + tpw_RD2_posedge : VitalDelayType := 0 ns; + tpw_RD2_negedge : VitalDelayType := 0 ns; + tpd_RD2_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD2: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_2_B : ENTITY IS TRUE; + + end RD_2_B; + + architecture Structure of RD_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD2_ipd : std_logic := 'X'; + signal RD2_out : std_logic := 'Z'; + + component mjiobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_2_718: mjiobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD2_out, + PADI=>RD2_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD2_ipd, RD2, tipd_RD2); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD2_ipd, RD2_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD2_zd : std_logic := 'X'; + VARIABLE RD2_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD2_RD2 : x01 := '0'; + VARIABLE periodcheckinfo_RD2 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD2_ipd, + TestSignalName => "RD2", + Period => tperiod_RD2, + PulseWidthHigh => tpw_RD2_posedge, + PulseWidthLow => tpw_RD2_negedge, + PeriodData => periodcheckinfo_RD2, + Violation => tviol_RD2_RD2, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD2_zd := RD2_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD2_ipd'last_event, + PathDelay => tpd_RD2_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD2, OutSignalName => "RD2", OutTemp => RD2_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD2, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD2, + PathCondition => TRUE)), + GlitchData => RD2_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_1_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RD_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_1_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD1 : VitalDelayType := 0 ns; + tpw_RD1_posedge : VitalDelayType := 0 ns; + tpw_RD1_negedge : VitalDelayType := 0 ns; + tpd_RD1_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD1: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_1_B : ENTITY IS TRUE; + + end RD_1_B; + + architecture Structure of RD_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD1_ipd : std_logic := 'X'; + signal RD1_out : std_logic := 'Z'; + + component mjiobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_1_719: mjiobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD1_out, + PADI=>RD1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD1_ipd, RD1, tipd_RD1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD1_ipd, RD1_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD1_zd : std_logic := 'X'; + VARIABLE RD1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD1_RD1 : x01 := '0'; + VARIABLE periodcheckinfo_RD1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD1_ipd, + TestSignalName => "RD1", + Period => tperiod_RD1, + PulseWidthHigh => tpw_RD1_posedge, + PulseWidthLow => tpw_RD1_negedge, + PeriodData => periodcheckinfo_RD1, + Violation => tviol_RD1_RD1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD1_zd := RD1_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD1_ipd'last_event, + PathDelay => tpd_RD1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD1, OutSignalName => "RD1", OutTemp => RD1_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD1, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD1, + PathCondition => TRUE)), + GlitchData => RD1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_0_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RD_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_0_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD0 : VitalDelayType := 0 ns; + tpw_RD0_posedge : VitalDelayType := 0 ns; + tpw_RD0_negedge : VitalDelayType := 0 ns; + tpd_RD0_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD0: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_0_B : ENTITY IS TRUE; + + end RD_0_B; + + architecture Structure of RD_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD0_ipd : std_logic := 'X'; + signal RD0_out : std_logic := 'Z'; + + component mjiobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_0_720: mjiobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD0_out, + PADI=>RD0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD0_ipd, RD0, tipd_RD0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD0_ipd, RD0_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD0_zd : std_logic := 'X'; + VARIABLE RD0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD0_RD0 : x01 := '0'; + VARIABLE periodcheckinfo_RD0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD0_ipd, + TestSignalName => "RD0", + Period => tperiod_RD0, + PulseWidthHigh => tpw_RD0_posedge, + PulseWidthLow => tpw_RD0_negedge, + PeriodData => periodcheckinfo_RD0, + Violation => tviol_RD0_RD0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD0_zd := RD0_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD0_ipd'last_event, + PathDelay => tpd_RD0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD0, OutSignalName => "RD0", OutTemp => RD0_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD0, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD0, + PathCondition => TRUE)), + GlitchData => RD0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity mjiobuf0076 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity mjiobuf0076 is + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + + ATTRIBUTE Vital_Level0 OF mjiobuf0076 : ENTITY IS TRUE; + + end mjiobuf0076; + + architecture Structure of mjiobuf0076 is + component OBZPU + port (I: in Std_logic; T: in Std_logic; O: out Std_logic); + end component; + begin + INST5: OBZPU + port map (I=>I, T=>T, O=>PAD); + end Structure; + +-- entity Dout_7_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Dout_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_7_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; Dout7: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_7_B : ENTITY IS TRUE; + + end Dout_7_B; + + architecture Structure of Dout_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout7_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_7: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout7_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout7_out) + VARIABLE Dout7_zd : std_logic := 'X'; + VARIABLE Dout7_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout7_zd := Dout7_out; + + VitalPathDelay01Z ( + OutSignal => Dout7, OutSignalName => "Dout7", OutTemp => Dout7_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout7, + PathCondition => TRUE)), + GlitchData => Dout7_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_6_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Dout_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_6_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; Dout6: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_6_B : ENTITY IS TRUE; + + end Dout_6_B; + + architecture Structure of Dout_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout6_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_6: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout6_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout6_out) + VARIABLE Dout6_zd : std_logic := 'X'; + VARIABLE Dout6_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout6_zd := Dout6_out; + + VitalPathDelay01Z ( + OutSignal => Dout6, OutSignalName => "Dout6", OutTemp => Dout6_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout6, + PathCondition => TRUE)), + GlitchData => Dout6_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_5_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Dout_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_5_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; Dout5: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_5_B : ENTITY IS TRUE; + + end Dout_5_B; + + architecture Structure of Dout_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout5_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_5: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout5_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout5_out) + VARIABLE Dout5_zd : std_logic := 'X'; + VARIABLE Dout5_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout5_zd := Dout5_out; + + VitalPathDelay01Z ( + OutSignal => Dout5, OutSignalName => "Dout5", OutTemp => Dout5_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout5, + PathCondition => TRUE)), + GlitchData => Dout5_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_4_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Dout_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_4_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; Dout4: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_4_B : ENTITY IS TRUE; + + end Dout_4_B; + + architecture Structure of Dout_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout4_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_4: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout4_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout4_out) + VARIABLE Dout4_zd : std_logic := 'X'; + VARIABLE Dout4_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout4_zd := Dout4_out; + + VitalPathDelay01Z ( + OutSignal => Dout4, OutSignalName => "Dout4", OutTemp => Dout4_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout4, + PathCondition => TRUE)), + GlitchData => Dout4_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_3_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Dout_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_3_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; Dout3: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_3_B : ENTITY IS TRUE; + + end Dout_3_B; + + architecture Structure of Dout_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout3_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_3: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout3_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout3_out) + VARIABLE Dout3_zd : std_logic := 'X'; + VARIABLE Dout3_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout3_zd := Dout3_out; + + VitalPathDelay01Z ( + OutSignal => Dout3, OutSignalName => "Dout3", OutTemp => Dout3_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout3, + PathCondition => TRUE)), + GlitchData => Dout3_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_2_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Dout_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_2_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; Dout2: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_2_B : ENTITY IS TRUE; + + end Dout_2_B; + + architecture Structure of Dout_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout2_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_2: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout2_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout2_out) + VARIABLE Dout2_zd : std_logic := 'X'; + VARIABLE Dout2_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout2_zd := Dout2_out; + + VitalPathDelay01Z ( + OutSignal => Dout2, OutSignalName => "Dout2", OutTemp => Dout2_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout2, + PathCondition => TRUE)), + GlitchData => Dout2_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_1_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Dout_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_1_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; Dout1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_1_B : ENTITY IS TRUE; + + end Dout_1_B; + + architecture Structure of Dout_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_1: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout1_out) + VARIABLE Dout1_zd : std_logic := 'X'; + VARIABLE Dout1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout1_zd := Dout1_out; + + VitalPathDelay01Z ( + OutSignal => Dout1, OutSignalName => "Dout1", OutTemp => Dout1_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout1, + PathCondition => TRUE)), + GlitchData => Dout1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_0_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Dout_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_0_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; Dout0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_0_B : ENTITY IS TRUE; + + end Dout_0_B; + + architecture Structure of Dout_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_0: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout0_out) + VARIABLE Dout0_zd : std_logic := 'X'; + VARIABLE Dout0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout0_zd := Dout0_out; + + VitalPathDelay01Z ( + OutSignal => Dout0, OutSignalName => "Dout0", OutTemp => Dout0_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout0, + PathCondition => TRUE)), + GlitchData => Dout0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity LEDB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity LEDB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "LEDB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_LEDS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; LEDS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF LEDB : ENTITY IS TRUE; + + end LEDB; + + architecture Structure of LEDB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal LEDS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + LED_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>LEDS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, LEDS_out) + VARIABLE LEDS_zd : std_logic := 'X'; + VARIABLE LEDS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + LEDS_zd := LEDS_out; + + VitalPathDelay01Z ( + OutSignal => LEDS, OutSignalName => "LEDS", OutTemp => LEDS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_LEDS, + PathCondition => TRUE)), + GlitchData => LEDS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RBA_1_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RBA_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RBA_1_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RBA1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; RBA1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RBA_1_B : ENTITY IS TRUE; + + end RBA_1_B; + + architecture Structure of RBA_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RBA1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RBA_pad_1: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RBA1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RBA1_out) + VARIABLE RBA1_zd : std_logic := 'X'; + VARIABLE RBA1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RBA1_zd := RBA1_out; + + VitalPathDelay01Z ( + OutSignal => RBA1, OutSignalName => "RBA1", OutTemp => RBA1_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RBA1, + PathCondition => TRUE)), + GlitchData => RBA1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RBA_0_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RBA_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RBA_0_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RBA0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; RBA0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RBA_0_B : ENTITY IS TRUE; + + end RBA_0_B; + + architecture Structure of RBA_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RBA0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RBA_pad_0: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RBA0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RBA0_out) + VARIABLE RBA0_zd : std_logic := 'X'; + VARIABLE RBA0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RBA0_zd := RBA0_out; + + VitalPathDelay01Z ( + OutSignal => RBA0, OutSignalName => "RBA0", OutTemp => RBA0_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RBA0, + PathCondition => TRUE)), + GlitchData => RBA0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_11_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_11_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_11_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA11 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; RA11: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_11_B : ENTITY IS TRUE; + + end RA_11_B; + + architecture Structure of RA_11_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA11_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_11: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA11_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA11_out) + VARIABLE RA11_zd : std_logic := 'X'; + VARIABLE RA11_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA11_zd := RA11_out; + + VitalPathDelay01Z ( + OutSignal => RA11, OutSignalName => "RA11", OutTemp => RA11_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA11, + PathCondition => TRUE)), + GlitchData => RA11_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_10_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_10_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_10_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA10 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; RA10: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_10_B : ENTITY IS TRUE; + + end RA_10_B; + + architecture Structure of RA_10_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA10_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_10: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA10_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA10_out) + VARIABLE RA10_zd : std_logic := 'X'; + VARIABLE RA10_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA10_zd := RA10_out; + + VitalPathDelay01Z ( + OutSignal => RA10, OutSignalName => "RA10", OutTemp => RA10_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA10, + PathCondition => TRUE)), + GlitchData => RA10_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_9_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_9_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_9_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA9 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA9: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_9_B : ENTITY IS TRUE; + + end RA_9_B; + + architecture Structure of RA_9_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA9_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_9: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA9_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA9_out) + VARIABLE RA9_zd : std_logic := 'X'; + VARIABLE RA9_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA9_zd := RA9_out; + + VitalPathDelay01Z ( + OutSignal => RA9, OutSignalName => "RA9", OutTemp => RA9_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA9, + PathCondition => TRUE)), + GlitchData => RA9_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_8_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_8_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_8_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA8 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA8: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_8_B : ENTITY IS TRUE; + + end RA_8_B; + + architecture Structure of RA_8_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA8_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_8: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA8_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA8_out) + VARIABLE RA8_zd : std_logic := 'X'; + VARIABLE RA8_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA8_zd := RA8_out; + + VitalPathDelay01Z ( + OutSignal => RA8, OutSignalName => "RA8", OutTemp => RA8_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA8, + PathCondition => TRUE)), + GlitchData => RA8_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_7_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_7_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA7: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_7_B : ENTITY IS TRUE; + + end RA_7_B; + + architecture Structure of RA_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA7_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_7: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA7_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA7_out) + VARIABLE RA7_zd : std_logic := 'X'; + VARIABLE RA7_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA7_zd := RA7_out; + + VitalPathDelay01Z ( + OutSignal => RA7, OutSignalName => "RA7", OutTemp => RA7_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA7, + PathCondition => TRUE)), + GlitchData => RA7_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_6_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_6_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA6: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_6_B : ENTITY IS TRUE; + + end RA_6_B; + + architecture Structure of RA_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA6_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_6: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA6_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA6_out) + VARIABLE RA6_zd : std_logic := 'X'; + VARIABLE RA6_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA6_zd := RA6_out; + + VitalPathDelay01Z ( + OutSignal => RA6, OutSignalName => "RA6", OutTemp => RA6_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA6, + PathCondition => TRUE)), + GlitchData => RA6_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_5_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_5_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA5: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_5_B : ENTITY IS TRUE; + + end RA_5_B; + + architecture Structure of RA_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA5_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_5: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA5_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA5_out) + VARIABLE RA5_zd : std_logic := 'X'; + VARIABLE RA5_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA5_zd := RA5_out; + + VitalPathDelay01Z ( + OutSignal => RA5, OutSignalName => "RA5", OutTemp => RA5_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA5, + PathCondition => TRUE)), + GlitchData => RA5_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_4_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_4_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA4: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_4_B : ENTITY IS TRUE; + + end RA_4_B; + + architecture Structure of RA_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA4_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_4: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA4_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA4_out) + VARIABLE RA4_zd : std_logic := 'X'; + VARIABLE RA4_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA4_zd := RA4_out; + + VitalPathDelay01Z ( + OutSignal => RA4, OutSignalName => "RA4", OutTemp => RA4_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA4, + PathCondition => TRUE)), + GlitchData => RA4_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_3_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_3_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA3: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_3_B : ENTITY IS TRUE; + + end RA_3_B; + + architecture Structure of RA_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA3_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_3: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA3_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA3_out) + VARIABLE RA3_zd : std_logic := 'X'; + VARIABLE RA3_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA3_zd := RA3_out; + + VitalPathDelay01Z ( + OutSignal => RA3, OutSignalName => "RA3", OutTemp => RA3_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA3, + PathCondition => TRUE)), + GlitchData => RA3_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_2_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_2_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA2: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_2_B : ENTITY IS TRUE; + + end RA_2_B; + + architecture Structure of RA_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA2_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_2: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA2_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA2_out) + VARIABLE RA2_zd : std_logic := 'X'; + VARIABLE RA2_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA2_zd := RA2_out; + + VitalPathDelay01Z ( + OutSignal => RA2, OutSignalName => "RA2", OutTemp => RA2_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA2, + PathCondition => TRUE)), + GlitchData => RA2_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_1_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_1_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_1_B : ENTITY IS TRUE; + + end RA_1_B; + + architecture Structure of RA_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_1: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA1_out) + VARIABLE RA1_zd : std_logic := 'X'; + VARIABLE RA1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA1_zd := RA1_out; + + VitalPathDelay01Z ( + OutSignal => RA1, OutSignalName => "RA1", OutTemp => RA1_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA1, + PathCondition => TRUE)), + GlitchData => RA1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_0_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_0_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_0_B : ENTITY IS TRUE; + + end RA_0_B; + + architecture Structure of RA_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_0: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA0_out) + VARIABLE RA0_zd : std_logic := 'X'; + VARIABLE RA0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA0_zd := RA0_out; + + VitalPathDelay01Z ( + OutSignal => RA0, OutSignalName => "RA0", OutTemp => RA0_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA0, + PathCondition => TRUE)), + GlitchData => RA0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRCSB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity nRCSB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRCSB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nRCSS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; nRCSS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRCSB : ENTITY IS TRUE; + + end nRCSB; + + architecture Structure of nRCSB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nRCSS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nRCS_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRCSS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nRCSS_out) + VARIABLE nRCSS_zd : std_logic := 'X'; + VARIABLE nRCSS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRCSS_zd := nRCSS_out; + + VitalPathDelay01Z ( + OutSignal => nRCSS, OutSignalName => "nRCSS", OutTemp => nRCSS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nRCSS, + PathCondition => TRUE)), + GlitchData => nRCSS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RCKEB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RCKEB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RCKEB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RCKES : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; RCKES: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RCKEB : ENTITY IS TRUE; + + end RCKEB; + + architecture Structure of RCKEB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RCKES_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RCKE_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RCKES_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RCKES_out) + VARIABLE RCKES_zd : std_logic := 'X'; + VARIABLE RCKES_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RCKES_zd := RCKES_out; + + VitalPathDelay01Z ( + OutSignal => RCKES, OutSignalName => "RCKES", OutTemp => RCKES_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RCKES, + PathCondition => TRUE)), + GlitchData => RCKES_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRWEB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity nRWEB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRWEB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nRWES : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; nRWES: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRWEB : ENTITY IS TRUE; + + end nRWEB; + + architecture Structure of nRWEB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nRWES_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nRWE_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRWES_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nRWES_out) + VARIABLE nRWES_zd : std_logic := 'X'; + VARIABLE nRWES_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRWES_zd := nRWES_out; + + VitalPathDelay01Z ( + OutSignal => nRWES, OutSignalName => "nRWES", OutTemp => nRWES_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nRWES, + PathCondition => TRUE)), + GlitchData => nRWES_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRRASB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity nRRASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRRASB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nRRASS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; nRRASS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRRASB : ENTITY IS TRUE; + + end nRRASB; + + architecture Structure of nRRASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nRRASS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nRRAS_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRRASS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nRRASS_out) + VARIABLE nRRASS_zd : std_logic := 'X'; + VARIABLE nRRASS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRRASS_zd := nRRASS_out; + + VitalPathDelay01Z ( + OutSignal => nRRASS, OutSignalName => "nRRASS", OutTemp => nRRASS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nRRASS, + PathCondition => TRUE)), + GlitchData => nRRASS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRCASB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity nRCASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRCASB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nRCASS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; nRCASS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRCASB : ENTITY IS TRUE; + + end nRCASB; + + architecture Structure of nRCASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nRCASS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nRCAS_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRCASS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nRCASS_out) + VARIABLE nRCASS_zd : std_logic := 'X'; + VARIABLE nRCASS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRCASS_zd := nRCASS_out; + + VitalPathDelay01Z ( + OutSignal => nRCASS, OutSignalName => "nRCASS", OutTemp => nRCASS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nRCASS, + PathCondition => TRUE)), + GlitchData => nRCASS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RDQMHB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RDQMHB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RDQMHB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RDQMHS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; RDQMHS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RDQMHB : ENTITY IS TRUE; + + end RDQMHB; + + architecture Structure of RDQMHB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RDQMHS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RDQMH_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RDQMHS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RDQMHS_out) + VARIABLE RDQMHS_zd : std_logic := 'X'; + VARIABLE RDQMHS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RDQMHS_zd := RDQMHS_out; + + VitalPathDelay01Z ( + OutSignal => RDQMHS, OutSignalName => "RDQMHS", OutTemp => RDQMHS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RDQMHS, + PathCondition => TRUE)), + GlitchData => RDQMHS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RDQMLB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RDQMLB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RDQMLB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RDQMLS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; RDQMLS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RDQMLB : ENTITY IS TRUE; + + end RDQMLB; + + architecture Structure of RDQMLB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RDQMLS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RDQML_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RDQMLS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RDQMLS_out) + VARIABLE RDQMLS_zd : std_logic := 'X'; + VARIABLE RDQMLS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RDQMLS_zd := RDQMLS_out; + + VitalPathDelay01Z ( + OutSignal => RDQMLS, OutSignalName => "RDQMLS", OutTemp => RDQMLS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RDQMLS, + PathCondition => TRUE)), + GlitchData => RDQMLS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nUFMCSB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity nUFMCSB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nUFMCSB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + + tpd_PADDO_nUFMCSS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; nUFMCSS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nUFMCSB : ENTITY IS TRUE; + + end nUFMCSB; + + architecture Structure of nUFMCSB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nUFMCSS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nUFMCS_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nUFMCSS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nUFMCSS_out) + VARIABLE nUFMCSS_zd : std_logic := 'X'; + VARIABLE nUFMCSS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nUFMCSS_zd := nUFMCSS_out; + + VitalPathDelay01Z ( + OutSignal => nUFMCSS, OutSignalName => "nUFMCSS", OutTemp => nUFMCSS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nUFMCSS, + PathCondition => TRUE)), + GlitchData => nUFMCSS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity UFMCLKB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity UFMCLKB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "UFMCLKB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + + tpd_PADDO_UFMCLKS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; UFMCLKS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF UFMCLKB : ENTITY IS TRUE; + + end UFMCLKB; + + architecture Structure of UFMCLKB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal UFMCLKS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + UFMCLK_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>UFMCLKS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, UFMCLKS_out) + VARIABLE UFMCLKS_zd : std_logic := 'X'; + VARIABLE UFMCLKS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + UFMCLKS_zd := UFMCLKS_out; + + VitalPathDelay01Z ( + OutSignal => UFMCLKS, OutSignalName => "UFMCLKS", OutTemp => UFMCLKS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_UFMCLKS, + PathCondition => TRUE)), + GlitchData => UFMCLKS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity UFMSDIB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity UFMSDIB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "UFMSDIB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + + tpd_PADDO_UFMSDIS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; UFMSDIS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF UFMSDIB : ENTITY IS TRUE; + + end UFMSDIB; + + architecture Structure of UFMSDIB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal UFMSDIS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + UFMSDI_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>UFMSDIS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, UFMSDIS_out) + VARIABLE UFMSDIS_zd : std_logic := 'X'; + VARIABLE UFMSDIS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + UFMSDIS_zd := UFMSDIS_out; + + VitalPathDelay01Z ( + OutSignal => UFMSDIS, OutSignalName => "UFMSDIS", OutTemp => UFMSDIS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_UFMSDIS, + PathCondition => TRUE)), + GlitchData => UFMSDIS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity mjiobuf0077 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity mjiobuf0077 is + port (Z: out Std_logic; PAD: in Std_logic); + + ATTRIBUTE Vital_Level0 OF mjiobuf0077 : ENTITY IS TRUE; + + end mjiobuf0077; + + architecture Structure of mjiobuf0077 is + component IBPU + port (I: in Std_logic; O: out Std_logic); + end component; + begin + INST1: IBPU + port map (I=>PAD, O=>Z); + end Structure; + +-- entity PHI2B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity PHI2B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "PHI2B"; + + tipd_PHI2S : VitalDelayType01 := (0 ns, 0 ns); + tpd_PHI2S_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_PHI2S : VitalDelayType := 0 ns; + tpw_PHI2S_posedge : VitalDelayType := 0 ns; + tpw_PHI2S_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; PHI2S: in Std_logic); + + ATTRIBUTE Vital_Level0 OF PHI2B : ENTITY IS TRUE; + + end PHI2B; + + architecture Structure of PHI2B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PHI2S_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + PHI2_pad: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>PHI2S_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PHI2S_ipd, PHI2S, tipd_PHI2S); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PHI2S_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_PHI2S_PHI2S : x01 := '0'; + VARIABLE periodcheckinfo_PHI2S : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => PHI2S_ipd, + TestSignalName => "PHI2S", + Period => tperiod_PHI2S, + PulseWidthHigh => tpw_PHI2S_posedge, + PulseWidthLow => tpw_PHI2S_negedge, + PeriodData => periodcheckinfo_PHI2S, + Violation => tviol_PHI2S_PHI2S, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => PHI2S_ipd'last_event, + PathDelay => tpd_PHI2S_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_9_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_9_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_9_B"; + + tipd_MAin9 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin9_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin9 : VitalDelayType := 0 ns; + tpw_MAin9_posedge : VitalDelayType := 0 ns; + tpw_MAin9_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin9: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_9_B : ENTITY IS TRUE; + + end MAin_9_B; + + architecture Structure of MAin_9_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin9_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_9: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin9_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin9_ipd, MAin9, tipd_MAin9); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin9_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin9_MAin9 : x01 := '0'; + VARIABLE periodcheckinfo_MAin9 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin9_ipd, + TestSignalName => "MAin9", + Period => tperiod_MAin9, + PulseWidthHigh => tpw_MAin9_posedge, + PulseWidthLow => tpw_MAin9_negedge, + PeriodData => periodcheckinfo_MAin9, + Violation => tviol_MAin9_MAin9, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin9_ipd'last_event, + PathDelay => tpd_MAin9_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_8_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_8_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_8_B"; + + tipd_MAin8 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin8_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin8 : VitalDelayType := 0 ns; + tpw_MAin8_posedge : VitalDelayType := 0 ns; + tpw_MAin8_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin8: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_8_B : ENTITY IS TRUE; + + end MAin_8_B; + + architecture Structure of MAin_8_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin8_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_8: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin8_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin8_ipd, MAin8, tipd_MAin8); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin8_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin8_MAin8 : x01 := '0'; + VARIABLE periodcheckinfo_MAin8 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin8_ipd, + TestSignalName => "MAin8", + Period => tperiod_MAin8, + PulseWidthHigh => tpw_MAin8_posedge, + PulseWidthLow => tpw_MAin8_negedge, + PeriodData => periodcheckinfo_MAin8, + Violation => tviol_MAin8_MAin8, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin8_ipd'last_event, + PathDelay => tpd_MAin8_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_7_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_7_B"; + + tipd_MAin7 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin7_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin7 : VitalDelayType := 0 ns; + tpw_MAin7_posedge : VitalDelayType := 0 ns; + tpw_MAin7_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin7: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_7_B : ENTITY IS TRUE; + + end MAin_7_B; + + architecture Structure of MAin_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin7_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_7: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin7_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin7_ipd, MAin7, tipd_MAin7); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin7_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin7_MAin7 : x01 := '0'; + VARIABLE periodcheckinfo_MAin7 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin7_ipd, + TestSignalName => "MAin7", + Period => tperiod_MAin7, + PulseWidthHigh => tpw_MAin7_posedge, + PulseWidthLow => tpw_MAin7_negedge, + PeriodData => periodcheckinfo_MAin7, + Violation => tviol_MAin7_MAin7, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin7_ipd'last_event, + PathDelay => tpd_MAin7_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_6_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_6_B"; + + tipd_MAin6 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin6_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin6 : VitalDelayType := 0 ns; + tpw_MAin6_posedge : VitalDelayType := 0 ns; + tpw_MAin6_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin6: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_6_B : ENTITY IS TRUE; + + end MAin_6_B; + + architecture Structure of MAin_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin6_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_6: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin6_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin6_ipd, MAin6, tipd_MAin6); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin6_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin6_MAin6 : x01 := '0'; + VARIABLE periodcheckinfo_MAin6 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin6_ipd, + TestSignalName => "MAin6", + Period => tperiod_MAin6, + PulseWidthHigh => tpw_MAin6_posedge, + PulseWidthLow => tpw_MAin6_negedge, + PeriodData => periodcheckinfo_MAin6, + Violation => tviol_MAin6_MAin6, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin6_ipd'last_event, + PathDelay => tpd_MAin6_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_5_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_5_B"; + + tipd_MAin5 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin5_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin5 : VitalDelayType := 0 ns; + tpw_MAin5_posedge : VitalDelayType := 0 ns; + tpw_MAin5_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin5: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_5_B : ENTITY IS TRUE; + + end MAin_5_B; + + architecture Structure of MAin_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin5_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_5: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin5_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin5_ipd, MAin5, tipd_MAin5); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin5_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin5_MAin5 : x01 := '0'; + VARIABLE periodcheckinfo_MAin5 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin5_ipd, + TestSignalName => "MAin5", + Period => tperiod_MAin5, + PulseWidthHigh => tpw_MAin5_posedge, + PulseWidthLow => tpw_MAin5_negedge, + PeriodData => periodcheckinfo_MAin5, + Violation => tviol_MAin5_MAin5, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin5_ipd'last_event, + PathDelay => tpd_MAin5_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_4_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_4_B"; + + tipd_MAin4 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin4_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin4 : VitalDelayType := 0 ns; + tpw_MAin4_posedge : VitalDelayType := 0 ns; + tpw_MAin4_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin4: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_4_B : ENTITY IS TRUE; + + end MAin_4_B; + + architecture Structure of MAin_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin4_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_4: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin4_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin4_ipd, MAin4, tipd_MAin4); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin4_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin4_MAin4 : x01 := '0'; + VARIABLE periodcheckinfo_MAin4 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin4_ipd, + TestSignalName => "MAin4", + Period => tperiod_MAin4, + PulseWidthHigh => tpw_MAin4_posedge, + PulseWidthLow => tpw_MAin4_negedge, + PeriodData => periodcheckinfo_MAin4, + Violation => tviol_MAin4_MAin4, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin4_ipd'last_event, + PathDelay => tpd_MAin4_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_3_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_3_B"; + + tipd_MAin3 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin3_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin3 : VitalDelayType := 0 ns; + tpw_MAin3_posedge : VitalDelayType := 0 ns; + tpw_MAin3_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin3: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_3_B : ENTITY IS TRUE; + + end MAin_3_B; + + architecture Structure of MAin_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin3_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_3: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin3_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin3_ipd, MAin3, tipd_MAin3); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin3_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin3_MAin3 : x01 := '0'; + VARIABLE periodcheckinfo_MAin3 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin3_ipd, + TestSignalName => "MAin3", + Period => tperiod_MAin3, + PulseWidthHigh => tpw_MAin3_posedge, + PulseWidthLow => tpw_MAin3_negedge, + PeriodData => periodcheckinfo_MAin3, + Violation => tviol_MAin3_MAin3, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin3_ipd'last_event, + PathDelay => tpd_MAin3_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_2_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_2_B"; + + tipd_MAin2 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin2_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin2 : VitalDelayType := 0 ns; + tpw_MAin2_posedge : VitalDelayType := 0 ns; + tpw_MAin2_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin2: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_2_B : ENTITY IS TRUE; + + end MAin_2_B; + + architecture Structure of MAin_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin2_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_2: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin2_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin2_ipd, MAin2, tipd_MAin2); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin2_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin2_MAin2 : x01 := '0'; + VARIABLE periodcheckinfo_MAin2 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin2_ipd, + TestSignalName => "MAin2", + Period => tperiod_MAin2, + PulseWidthHigh => tpw_MAin2_posedge, + PulseWidthLow => tpw_MAin2_negedge, + PeriodData => periodcheckinfo_MAin2, + Violation => tviol_MAin2_MAin2, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin2_ipd'last_event, + PathDelay => tpd_MAin2_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_1_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_1_B"; + + tipd_MAin1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin1 : VitalDelayType := 0 ns; + tpw_MAin1_posedge : VitalDelayType := 0 ns; + tpw_MAin1_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin1: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_1_B : ENTITY IS TRUE; + + end MAin_1_B; + + architecture Structure of MAin_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin1_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_1: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin1_ipd, MAin1, tipd_MAin1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin1_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin1_MAin1 : x01 := '0'; + VARIABLE periodcheckinfo_MAin1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin1_ipd, + TestSignalName => "MAin1", + Period => tperiod_MAin1, + PulseWidthHigh => tpw_MAin1_posedge, + PulseWidthLow => tpw_MAin1_negedge, + PeriodData => periodcheckinfo_MAin1, + Violation => tviol_MAin1_MAin1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin1_ipd'last_event, + PathDelay => tpd_MAin1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_0_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_0_B"; + + tipd_MAin0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin0 : VitalDelayType := 0 ns; + tpw_MAin0_posedge : VitalDelayType := 0 ns; + tpw_MAin0_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin0: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_0_B : ENTITY IS TRUE; + + end MAin_0_B; + + architecture Structure of MAin_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin0_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_0: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin0_ipd, MAin0, tipd_MAin0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin0_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin0_MAin0 : x01 := '0'; + VARIABLE periodcheckinfo_MAin0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin0_ipd, + TestSignalName => "MAin0", + Period => tperiod_MAin0, + PulseWidthHigh => tpw_MAin0_posedge, + PulseWidthLow => tpw_MAin0_negedge, + PeriodData => periodcheckinfo_MAin0, + Violation => tviol_MAin0_MAin0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin0_ipd'last_event, + PathDelay => tpd_MAin0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity CROW_1_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity CROW_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "CROW_1_B"; + + tipd_CROW1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CROW1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CROW1 : VitalDelayType := 0 ns; + tpw_CROW1_posedge : VitalDelayType := 0 ns; + tpw_CROW1_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; CROW1: in Std_logic); + + ATTRIBUTE Vital_Level0 OF CROW_1_B : ENTITY IS TRUE; + + end CROW_1_B; + + architecture Structure of CROW_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal CROW1_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + CROW_pad_1: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>CROW1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(CROW1_ipd, CROW1, tipd_CROW1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, CROW1_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_CROW1_CROW1 : x01 := '0'; + VARIABLE periodcheckinfo_CROW1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => CROW1_ipd, + TestSignalName => "CROW1", + Period => tperiod_CROW1, + PulseWidthHigh => tpw_CROW1_posedge, + PulseWidthLow => tpw_CROW1_negedge, + PeriodData => periodcheckinfo_CROW1, + Violation => tviol_CROW1_CROW1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => CROW1_ipd'last_event, + PathDelay => tpd_CROW1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity CROW_0_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity CROW_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "CROW_0_B"; + + tipd_CROW0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CROW0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CROW0 : VitalDelayType := 0 ns; + tpw_CROW0_posedge : VitalDelayType := 0 ns; + tpw_CROW0_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; CROW0: in Std_logic); + + ATTRIBUTE Vital_Level0 OF CROW_0_B : ENTITY IS TRUE; + + end CROW_0_B; + + architecture Structure of CROW_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal CROW0_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + CROW_pad_0: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>CROW0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(CROW0_ipd, CROW0, tipd_CROW0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, CROW0_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_CROW0_CROW0 : x01 := '0'; + VARIABLE periodcheckinfo_CROW0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => CROW0_ipd, + TestSignalName => "CROW0", + Period => tperiod_CROW0, + PulseWidthHigh => tpw_CROW0_posedge, + PulseWidthLow => tpw_CROW0_negedge, + PeriodData => periodcheckinfo_CROW0, + Violation => tviol_CROW0_CROW0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => CROW0_ipd'last_event, + PathDelay => tpd_CROW0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_7_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Din_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_7_B"; + + tipd_Din7 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din7_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din7 : VitalDelayType := 0 ns; + tpw_Din7_posedge : VitalDelayType := 0 ns; + tpw_Din7_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din7: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_7_B : ENTITY IS TRUE; + + end Din_7_B; + + architecture Structure of Din_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din7_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_7: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>Din7_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din7_ipd, Din7, tipd_Din7); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din7_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din7_Din7 : x01 := '0'; + VARIABLE periodcheckinfo_Din7 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din7_ipd, + TestSignalName => "Din7", + Period => tperiod_Din7, + PulseWidthHigh => tpw_Din7_posedge, + PulseWidthLow => tpw_Din7_negedge, + PeriodData => periodcheckinfo_Din7, + Violation => tviol_Din7_Din7, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din7_ipd'last_event, + PathDelay => tpd_Din7_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_6_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Din_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_6_B"; + + tipd_Din6 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din6_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din6 : VitalDelayType := 0 ns; + tpw_Din6_posedge : VitalDelayType := 0 ns; + tpw_Din6_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din6: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_6_B : ENTITY IS TRUE; + + end Din_6_B; + + architecture Structure of Din_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din6_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_6: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>Din6_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din6_ipd, Din6, tipd_Din6); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din6_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din6_Din6 : x01 := '0'; + VARIABLE periodcheckinfo_Din6 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din6_ipd, + TestSignalName => "Din6", + Period => tperiod_Din6, + PulseWidthHigh => tpw_Din6_posedge, + PulseWidthLow => tpw_Din6_negedge, + PeriodData => periodcheckinfo_Din6, + Violation => tviol_Din6_Din6, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din6_ipd'last_event, + PathDelay => tpd_Din6_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_5_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Din_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_5_B"; + + tipd_Din5 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din5_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din5 : VitalDelayType := 0 ns; + tpw_Din5_posedge : VitalDelayType := 0 ns; + tpw_Din5_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din5: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_5_B : ENTITY IS TRUE; + + end Din_5_B; + + architecture Structure of Din_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din5_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_5: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>Din5_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din5_ipd, Din5, tipd_Din5); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din5_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din5_Din5 : x01 := '0'; + VARIABLE periodcheckinfo_Din5 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din5_ipd, + TestSignalName => "Din5", + Period => tperiod_Din5, + PulseWidthHigh => tpw_Din5_posedge, + PulseWidthLow => tpw_Din5_negedge, + PeriodData => periodcheckinfo_Din5, + Violation => tviol_Din5_Din5, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din5_ipd'last_event, + PathDelay => tpd_Din5_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_4_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Din_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_4_B"; + + tipd_Din4 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din4_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din4 : VitalDelayType := 0 ns; + tpw_Din4_posedge : VitalDelayType := 0 ns; + tpw_Din4_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din4: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_4_B : ENTITY IS TRUE; + + end Din_4_B; + + architecture Structure of Din_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din4_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_4: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>Din4_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din4_ipd, Din4, tipd_Din4); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din4_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din4_Din4 : x01 := '0'; + VARIABLE periodcheckinfo_Din4 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din4_ipd, + TestSignalName => "Din4", + Period => tperiod_Din4, + PulseWidthHigh => tpw_Din4_posedge, + PulseWidthLow => tpw_Din4_negedge, + PeriodData => periodcheckinfo_Din4, + Violation => tviol_Din4_Din4, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din4_ipd'last_event, + PathDelay => tpd_Din4_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_3_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Din_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_3_B"; + + tipd_Din3 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din3_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din3 : VitalDelayType := 0 ns; + tpw_Din3_posedge : VitalDelayType := 0 ns; + tpw_Din3_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din3: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_3_B : ENTITY IS TRUE; + + end Din_3_B; + + architecture Structure of Din_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din3_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_3: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>Din3_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din3_ipd, Din3, tipd_Din3); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din3_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din3_Din3 : x01 := '0'; + VARIABLE periodcheckinfo_Din3 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din3_ipd, + TestSignalName => "Din3", + Period => tperiod_Din3, + PulseWidthHigh => tpw_Din3_posedge, + PulseWidthLow => tpw_Din3_negedge, + PeriodData => periodcheckinfo_Din3, + Violation => tviol_Din3_Din3, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din3_ipd'last_event, + PathDelay => tpd_Din3_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_2_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Din_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_2_B"; + + tipd_Din2 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din2_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din2 : VitalDelayType := 0 ns; + tpw_Din2_posedge : VitalDelayType := 0 ns; + tpw_Din2_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din2: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_2_B : ENTITY IS TRUE; + + end Din_2_B; + + architecture Structure of Din_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din2_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_2: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>Din2_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din2_ipd, Din2, tipd_Din2); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din2_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din2_Din2 : x01 := '0'; + VARIABLE periodcheckinfo_Din2 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din2_ipd, + TestSignalName => "Din2", + Period => tperiod_Din2, + PulseWidthHigh => tpw_Din2_posedge, + PulseWidthLow => tpw_Din2_negedge, + PeriodData => periodcheckinfo_Din2, + Violation => tviol_Din2_Din2, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din2_ipd'last_event, + PathDelay => tpd_Din2_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_1_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Din_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_1_B"; + + tipd_Din1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din1 : VitalDelayType := 0 ns; + tpw_Din1_posedge : VitalDelayType := 0 ns; + tpw_Din1_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din1: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_1_B : ENTITY IS TRUE; + + end Din_1_B; + + architecture Structure of Din_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din1_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_1: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>Din1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din1_ipd, Din1, tipd_Din1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din1_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din1_Din1 : x01 := '0'; + VARIABLE periodcheckinfo_Din1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din1_ipd, + TestSignalName => "Din1", + Period => tperiod_Din1, + PulseWidthHigh => tpw_Din1_posedge, + PulseWidthLow => tpw_Din1_negedge, + PeriodData => periodcheckinfo_Din1, + Violation => tviol_Din1_Din1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din1_ipd'last_event, + PathDelay => tpd_Din1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_0_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Din_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_0_B"; + + tipd_Din0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din0 : VitalDelayType := 0 ns; + tpw_Din0_posedge : VitalDelayType := 0 ns; + tpw_Din0_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din0: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_0_B : ENTITY IS TRUE; + + end Din_0_B; + + architecture Structure of Din_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din0_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_0: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>Din0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din0_ipd, Din0, tipd_Din0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din0_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din0_Din0 : x01 := '0'; + VARIABLE periodcheckinfo_Din0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din0_ipd, + TestSignalName => "Din0", + Period => tperiod_Din0, + PulseWidthHigh => tpw_Din0_posedge, + PulseWidthLow => tpw_Din0_negedge, + PeriodData => periodcheckinfo_Din0, + Violation => tviol_Din0_Din0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din0_ipd'last_event, + PathDelay => tpd_Din0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nCCASB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity nCCASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nCCASB"; + + tipd_nCCASS : VitalDelayType01 := (0 ns, 0 ns); + tpd_nCCASS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nCCASS : VitalDelayType := 0 ns; + tpw_nCCASS_posedge : VitalDelayType := 0 ns; + tpw_nCCASS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; nCCASS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nCCASB : ENTITY IS TRUE; + + end nCCASB; + + architecture Structure of nCCASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal nCCASS_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + nCCAS_pad: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>nCCASS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(nCCASS_ipd, nCCASS, tipd_nCCASS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, nCCASS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_nCCASS_nCCASS : x01 := '0'; + VARIABLE periodcheckinfo_nCCASS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => nCCASS_ipd, + TestSignalName => "nCCASS", + Period => tperiod_nCCASS, + PulseWidthHigh => tpw_nCCASS_posedge, + PulseWidthLow => tpw_nCCASS_negedge, + PeriodData => periodcheckinfo_nCCASS, + Violation => tviol_nCCASS_nCCASS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => nCCASS_ipd'last_event, + PathDelay => tpd_nCCASS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nCRASB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity nCRASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nCRASB"; + + tipd_nCRASS : VitalDelayType01 := (0 ns, 0 ns); + tpd_nCRASS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nCRASS : VitalDelayType := 0 ns; + tpw_nCRASS_posedge : VitalDelayType := 0 ns; + tpw_nCRASS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; nCRASS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nCRASB : ENTITY IS TRUE; + + end nCRASB; + + architecture Structure of nCRASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal nCRASS_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + nCRAS_pad: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>nCRASS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(nCRASS_ipd, nCRASS, tipd_nCRASS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, nCRASS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_nCRASS_nCRASS : x01 := '0'; + VARIABLE periodcheckinfo_nCRASS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => nCRASS_ipd, + TestSignalName => "nCRASS", + Period => tperiod_nCRASS, + PulseWidthHigh => tpw_nCRASS_posedge, + PulseWidthLow => tpw_nCRASS_negedge, + PeriodData => periodcheckinfo_nCRASS, + Violation => tviol_nCRASS_nCRASS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => nCRASS_ipd'last_event, + PathDelay => tpd_nCRASS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nFWEB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity nFWEB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nFWEB"; + + tipd_nFWES : VitalDelayType01 := (0 ns, 0 ns); + tpd_nFWES_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nFWES : VitalDelayType := 0 ns; + tpw_nFWES_posedge : VitalDelayType := 0 ns; + tpw_nFWES_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; nFWES: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nFWEB : ENTITY IS TRUE; + + end nFWEB; + + architecture Structure of nFWEB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal nFWES_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + nFWE_pad: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>nFWES_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(nFWES_ipd, nFWES, tipd_nFWES); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, nFWES_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_nFWES_nFWES : x01 := '0'; + VARIABLE periodcheckinfo_nFWES : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => nFWES_ipd, + TestSignalName => "nFWES", + Period => tperiod_nFWES, + PulseWidthHigh => tpw_nFWES_posedge, + PulseWidthLow => tpw_nFWES_negedge, + PeriodData => periodcheckinfo_nFWES, + Violation => tviol_nFWES_nFWES, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => nFWES_ipd'last_event, + PathDelay => tpd_nFWES_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RCLKB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RCLKB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RCLKB"; + + tipd_RCLKS : VitalDelayType01 := (0 ns, 0 ns); + tpd_RCLKS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RCLKS : VitalDelayType := 0 ns; + tpw_RCLKS_posedge : VitalDelayType := 0 ns; + tpw_RCLKS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; RCLKS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RCLKB : ENTITY IS TRUE; + + end RCLKB; + + architecture Structure of RCLKB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal RCLKS_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + RCLK_pad: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>RCLKS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(RCLKS_ipd, RCLKS, tipd_RCLKS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, RCLKS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RCLKS_RCLKS : x01 := '0'; + VARIABLE periodcheckinfo_RCLKS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RCLKS_ipd, + TestSignalName => "RCLKS", + Period => tperiod_RCLKS, + PulseWidthHigh => tpw_RCLKS_posedge, + PulseWidthLow => tpw_RCLKS_negedge, + PeriodData => periodcheckinfo_RCLKS, + Violation => tviol_RCLKS_RCLKS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RCLKS_ipd'last_event, + PathDelay => tpd_RCLKS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity UFMSDOB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity UFMSDOB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "UFMSDOB"; + + tipd_UFMSDOS : VitalDelayType01 := (0 ns, 0 ns); + tpd_UFMSDOS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_UFMSDOS : VitalDelayType := 0 ns; + tpw_UFMSDOS_posedge : VitalDelayType := 0 ns; + tpw_UFMSDOS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; UFMSDOS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF UFMSDOB : ENTITY IS TRUE; + + end UFMSDOB; + + architecture Structure of UFMSDOB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal UFMSDOS_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + UFMSDO_pad: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>UFMSDOS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(UFMSDOS_ipd, UFMSDOS, tipd_UFMSDOS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, UFMSDOS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_UFMSDOS_UFMSDOS : x01 := '0'; + VARIABLE periodcheckinfo_UFMSDOS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => UFMSDOS_ipd, + TestSignalName => "UFMSDOS", + Period => tperiod_UFMSDOS, + PulseWidthHigh => tpw_UFMSDOS_posedge, + PulseWidthLow => tpw_UFMSDOS_negedge, + PeriodData => periodcheckinfo_UFMSDOS, + Violation => tviol_UFMSDOS_UFMSDOS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => UFMSDOS_ipd'last_event, + PathDelay => tpd_UFMSDOS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RAM2GS + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RAM2GS is + port (PHI2: in Std_logic; MAin: in Std_logic_vector (9 downto 0); + CROW: in Std_logic_vector (1 downto 0); + Din: in Std_logic_vector (7 downto 0); + Dout: out Std_logic_vector (7 downto 0); nCCAS: in Std_logic; + nCRAS: in Std_logic; nFWE: in Std_logic; LED: out Std_logic; + RBA: out Std_logic_vector (1 downto 0); + RA: out Std_logic_vector (11 downto 0); + RD: inout Std_logic_vector (7 downto 0); nRCS: out Std_logic; + RCLK: in Std_logic; RCKE: out Std_logic; nRWE: out Std_logic; + nRRAS: out Std_logic; nRCAS: out Std_logic; RDQMH: out Std_logic; + RDQML: out Std_logic; nUFMCS: out Std_logic; UFMCLK: out Std_logic; + UFMSDI: out Std_logic; UFMSDO: in Std_logic); + + + + end RAM2GS; + + architecture Structure of RAM2GS is + signal FS_7: Std_logic; + signal FS_6: Std_logic; + signal RCLK_c: Std_logic; + signal n2010: Std_logic; + signal n2011: Std_logic; + signal FS_15: Std_logic; + signal FS_14: Std_logic; + signal n2014: Std_logic; + signal n2015: Std_logic; + signal FS_5: Std_logic; + signal FS_4: Std_logic; + signal n2009: Std_logic; + signal FS_13: Std_logic; + signal FS_12: Std_logic; + signal n2013: Std_logic; + signal FS_1: Std_logic; + signal FS_0: Std_logic; + signal n2008: Std_logic; + signal FS_11: Std_logic; + signal FS_10: Std_logic; + signal n2012: Std_logic; + signal FS_3: Std_logic; + signal FS_2: Std_logic; + signal FS_9: Std_logic; + signal FS_8: Std_logic; + signal FS_17: Std_logic; + signal FS_16: Std_logic; + signal MAin_c_1: Std_logic; + signal n1326: Std_logic; + signal MAin_c_0: Std_logic; + signal n2263: Std_logic; + signal ADSubmitted: Std_logic; + signal n2242: Std_logic; + signal n2459: Std_logic; + signal n1413: Std_logic; + signal C1Submitted_N_237: Std_logic; + signal PHI2_c: Std_logic; + signal Din_c_6: Std_logic; + signal C1Submitted: Std_logic; + signal nFWE_c: Std_logic; + signal n6_adj_3: Std_logic; + signal n2284: Std_logic; + signal MAin_c_5: Std_logic; + signal n2316: Std_logic; + signal n26: Std_logic; + signal MAin_c_2: Std_logic; + signal n15: Std_logic; + signal n2463: Std_logic; + signal CmdEnable_N_248: Std_logic; + signal PHI2_N_120_enable_7: Std_logic; + signal CmdEnable: Std_logic; + signal PHI2r2: Std_logic; + signal CmdSubmitted: Std_logic; + signal PHI2r3: Std_logic; + signal n2568_001_BUF1: Std_logic; + signal PHI2_N_120_enable_5: Std_logic; + signal n2472: Std_logic; + signal Din_c_5: Std_logic; + signal Din_c_7: Std_logic; + signal n1314: Std_logic; + signal Din_c_4: Std_logic; + signal n8MEGEN: Std_logic; + signal Din_c_0: Std_logic; + signal Cmdn8MEGEN_N_264: Std_logic; + signal PHI2_N_120_enable_4: Std_logic; + signal Cmdn8MEGEN: Std_logic; + signal nRowColSel_N_35: Std_logic; + signal RASr2: Std_logic; + signal InitReady: Std_logic; + signal Ready: Std_logic; + signal n2568_000_BUF1: Std_logic; + signal RCLK_c_enable_25: Std_logic; + signal RCLK_c_enable_23: Std_logic; + signal nCRAS_c: Std_logic; + signal CBR: Std_logic; + signal LEDEN: Std_logic; + signal n2568: Std_logic; + signal RCLK_c_enable_12: Std_logic; + signal LED_N_84: Std_logic; + signal nRowColSel_N_34: Std_logic; + signal nRCAS_N_165: Std_logic; + signal n2208: Std_logic; + signal n2209: Std_logic; + signal nRWE_N_177: Std_logic; + signal RA_0S: Std_logic; + signal n56: Std_logic; + signal XOR8MEG: Std_logic; + signal RA11_N_184: Std_logic; + signal RA_c: Std_logic; + signal n2478: Std_logic; + signal RCKEEN_N_122: Std_logic; + signal RCKEEN_N_121: Std_logic; + signal RCLK_c_enable_4: Std_logic; + signal RCKEEN: Std_logic; + signal n2467: Std_logic; + signal RCKE_c: Std_logic; + signal RASr3: Std_logic; + signal RASr: Std_logic; + signal RCKE_N_132: Std_logic; + signal CASr: Std_logic; + signal nRWE_N_182: Std_logic; + signal CASr2: Std_logic; + signal n2568_002_BUF1: Std_logic; + signal Ready_N_292: Std_logic; + signal n2469: Std_logic; + signal n2462: Std_logic; + signal n62: Std_logic; + signal n1160: Std_logic; + signal CmdUFMCLK: Std_logic; + signal UFMCLK_N_224: Std_logic; + signal RCLK_c_enable_24: Std_logic; + signal n1846: Std_logic; + signal UFMCLK_c: Std_logic; + signal n2470: Std_logic; + signal n2272: Std_logic; + signal n2471: Std_logic; + signal CmdUFMSDI: Std_logic; + signal n2461: Std_logic; + signal UFMSDI_N_231: Std_logic; + signal UFMSDI_c: Std_logic; + signal Din_c_1: Std_logic; + signal n2324: Std_logic; + signal Din_c_2: Std_logic; + signal Din_c_3: Std_logic; + signal XOR8MEG_N_110: Std_logic; + signal PHI2_N_120_enable_1: Std_logic; + signal n2464: Std_logic; + signal n1325: Std_logic; + signal UFMSDO_c: Std_logic; + signal n8MEGEN_N_91: Std_logic; + signal RCLK_c_enable_11: Std_logic; + signal n2427: Std_logic; + signal n15_adj_1: Std_logic; + signal nRCAS_N_161: Std_logic; + signal nRCAS_c: Std_logic; + signal n13: Std_logic; + signal n2481: Std_logic; + signal nRCS_N_136: Std_logic; + signal nRCS_c: Std_logic; + signal nRCS_N_139: Std_logic; + signal nRowColSel_N_32: Std_logic; + signal n6: Std_logic; + signal nRRAS_c: Std_logic; + signal n2138: Std_logic; + signal nRWE_N_178: Std_logic; + signal n33: Std_logic; + signal nRWE_N_171: Std_logic; + signal RCLK_c_enable_3: Std_logic; + signal nRWE_c: Std_logic; + signal nRowColSel: Std_logic; + signal MAin_c_9: Std_logic; + signal RowA_9: Std_logic; + signal nRowColSel_N_28: Std_logic; + signal n1502: Std_logic; + signal n1410: Std_logic; + signal RA_1_9: Std_logic; + signal Ready_N_296: Std_logic; + signal nRowColSel_N_33: Std_logic; + signal n1503: Std_logic; + signal n2414: Std_logic; + signal n1093: Std_logic; + signal CmdUFMCS: Std_logic; + signal nUFMCS_c: Std_logic; + signal n11: Std_logic; + signal n1417: Std_logic; + signal n2322: Std_logic; + signal CASr3: Std_logic; + signal n12: Std_logic; + signal n2164: Std_logic; + signal LEDEN_N_82: Std_logic; + signal FWEr: Std_logic; + signal n2476: Std_logic; + signal n2475: Std_logic; + signal n13_adj_2: Std_logic; + signal n1: Std_logic; + signal n2214: Std_logic; + signal n2328: Std_logic; + signal n10: Std_logic; + signal n2458: Std_logic; + signal n732: Std_logic; + signal n733: Std_logic; + signal n2290: Std_logic; + signal n728: Std_logic; + signal n729: Std_logic; + signal n8: Std_logic; + signal n727: Std_logic; + signal MAin_c_7: Std_logic; + signal MAin_c_6: Std_logic; + signal RowA_6: Std_logic; + signal RowA_7: Std_logic; + signal n2468: Std_logic; + signal n1280: Std_logic; + signal PHI2r: Std_logic; + signal nCCAS_c: Std_logic; + signal n726: Std_logic; + signal Bank_3: Std_logic; + signal Bank_6: Std_logic; + signal Bank_5: Std_logic; + signal n2278: Std_logic; + signal n2314: Std_logic; + signal Bank_2: Std_logic; + signal PHI2_N_120_enable_6: Std_logic; + signal n14: Std_logic; + signal n2460: Std_logic; + signal n730: Std_logic; + signal n2262: Std_logic; + signal n2473: Std_logic; + signal n738: Std_logic; + signal n737: Std_logic; + signal n2474: Std_logic; + signal n2253: Std_logic; + signal CROW_c_1: Std_logic; + signal CROW_c_0: Std_logic; + signal RBA_c_0: Std_logic; + signal RBA_c_1: Std_logic; + signal n734: Std_logic; + signal n735: Std_logic; + signal n7: Std_logic; + signal n2451: Std_logic; + signal Bank_0: Std_logic; + signal Bank_1: Std_logic; + signal WRD_0: Std_logic; + signal WRD_1: Std_logic; + signal MAin_c_8: Std_logic; + signal RowA_8: Std_logic; + signal WRD_6: Std_logic; + signal WRD_7: Std_logic; + signal RDQMH_c: Std_logic; + signal RDQML_c: Std_logic; + signal MAin_c_4: Std_logic; + signal RowA_4: Std_logic; + signal RowA_5: Std_logic; + signal MAin_c_3: Std_logic; + signal RowA_3: Std_logic; + signal Bank_4: Std_logic; + signal RowA_2: Std_logic; + signal RA_1_3: Std_logic; + signal Bank_7: Std_logic; + signal RowA_0: Std_logic; + signal RA_1_4: Std_logic; + signal RowA_1: Std_logic; + signal RA_1_8: Std_logic; + signal RA_1_0: Std_logic; + signal RA_1_7: Std_logic; + signal RA_1_1: Std_logic; + signal n736: Std_logic; + signal RA_1_6: Std_logic; + signal RA_1_2: Std_logic; + signal WRD_2: Std_logic; + signal RA_1_5: Std_logic; + signal WRD_3: Std_logic; + signal WRD_4: Std_logic; + signal n984: Std_logic; + signal WRD_5: Std_logic; + signal Dout_c: Std_logic; + signal Dout_0S: Std_logic; + signal Dout_1S: Std_logic; + signal Dout_2S: Std_logic; + signal Dout_3S: Std_logic; + signal Dout_4S: Std_logic; + signal Dout_5S: Std_logic; + signal Dout_6S: Std_logic; + signal VCCI: Std_logic; + signal GNDI_TSALL: Std_logic; + component VHI + port (Z: out Std_logic); + end component; + component VLO + port (Z: out Std_logic); + end component; + component PUR + port (PUR: in Std_logic); + end component; + component GSR + port (GSR: in Std_logic); + end component; + component TSALL + port (TSALL: in Std_logic); + end component; + component SLICE_0 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + end component; + component SLICE_1 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + end component; + component SLICE_2 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + end component; + component SLICE_3 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + end component; + component SLICE_4 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_5 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + end component; + component SLICE_6 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + end component; + component SLICE_7 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + end component; + component SLICE_8 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_9 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_14 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_18 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_19 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_23 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_25 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_26 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_31 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_32 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_34 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_35 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_36 + port (B1: in Std_logic; A1: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_43 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_44 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_49 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_56 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_58 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; + Q0: out Std_logic); + end component; + component SLICE_60 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_61 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_63 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_64 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_65 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_66 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_67 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_68 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_69 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component RCKEEN_I_0_445_SLICE_70 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); + end component; + component i26_SLICE_71 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + OFX0: out Std_logic); + end component; + component i2099_SLICE_72 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); + end component; + component i26_adj_28_SLICE_73 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + OFX0: out Std_logic); + end component; + component SLICE_74 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_75 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_76 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_77 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_78 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_79 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_80 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_81 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_82 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_83 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_84 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_85 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_86 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_87 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_88 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_89 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_90 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_91 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_92 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_93 + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_94 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_95 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_96 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_97 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_98 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_99 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_100 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_101 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_102 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_103 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_104 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_105 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component RD_7_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD7: inout Std_logic); + end component; + component RD_6_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD6: inout Std_logic); + end component; + component RD_5_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD5: inout Std_logic); + end component; + component RD_4_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD4: inout Std_logic); + end component; + component RD_3_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD3: inout Std_logic); + end component; + component RD_2_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD2: inout Std_logic); + end component; + component RD_1_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD1: inout Std_logic); + end component; + component RD_0_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD0: inout Std_logic); + end component; + component Dout_7_B + port (PADDO: in Std_logic; Dout7: out Std_logic); + end component; + component Dout_6_B + port (PADDO: in Std_logic; Dout6: out Std_logic); + end component; + component Dout_5_B + port (PADDO: in Std_logic; Dout5: out Std_logic); + end component; + component Dout_4_B + port (PADDO: in Std_logic; Dout4: out Std_logic); + end component; + component Dout_3_B + port (PADDO: in Std_logic; Dout3: out Std_logic); + end component; + component Dout_2_B + port (PADDO: in Std_logic; Dout2: out Std_logic); + end component; + component Dout_1_B + port (PADDO: in Std_logic; Dout1: out Std_logic); + end component; + component Dout_0_B + port (PADDO: in Std_logic; Dout0: out Std_logic); + end component; + component LEDB + port (PADDO: in Std_logic; LEDS: out Std_logic); + end component; + component RBA_1_B + port (PADDO: in Std_logic; RBA1: out Std_logic); + end component; + component RBA_0_B + port (PADDO: in Std_logic; RBA0: out Std_logic); + end component; + component RA_11_B + port (PADDO: in Std_logic; RA11: out Std_logic); + end component; + component RA_10_B + port (PADDO: in Std_logic; RA10: out Std_logic); + end component; + component RA_9_B + port (PADDO: in Std_logic; RA9: out Std_logic); + end component; + component RA_8_B + port (PADDO: in Std_logic; RA8: out Std_logic); + end component; + component RA_7_B + port (PADDO: in Std_logic; RA7: out Std_logic); + end component; + component RA_6_B + port (PADDO: in Std_logic; RA6: out Std_logic); + end component; + component RA_5_B + port (PADDO: in Std_logic; RA5: out Std_logic); + end component; + component RA_4_B + port (PADDO: in Std_logic; RA4: out Std_logic); + end component; + component RA_3_B + port (PADDO: in Std_logic; RA3: out Std_logic); + end component; + component RA_2_B + port (PADDO: in Std_logic; RA2: out Std_logic); + end component; + component RA_1_B + port (PADDO: in Std_logic; RA1: out Std_logic); + end component; + component RA_0_B + port (PADDO: in Std_logic; RA0: out Std_logic); + end component; + component nRCSB + port (PADDO: in Std_logic; nRCSS: out Std_logic); + end component; + component RCKEB + port (PADDO: in Std_logic; RCKES: out Std_logic); + end component; + component nRWEB + port (PADDO: in Std_logic; nRWES: out Std_logic); + end component; + component nRRASB + port (PADDO: in Std_logic; nRRASS: out Std_logic); + end component; + component nRCASB + port (PADDO: in Std_logic; nRCASS: out Std_logic); + end component; + component RDQMHB + port (PADDO: in Std_logic; RDQMHS: out Std_logic); + end component; + component RDQMLB + port (PADDO: in Std_logic; RDQMLS: out Std_logic); + end component; + component nUFMCSB + port (PADDO: in Std_logic; nUFMCSS: out Std_logic); + end component; + component UFMCLKB + port (PADDO: in Std_logic; UFMCLKS: out Std_logic); + end component; + component UFMSDIB + port (PADDO: in Std_logic; UFMSDIS: out Std_logic); + end component; + component PHI2B + port (PADDI: out Std_logic; PHI2S: in Std_logic); + end component; + component MAin_9_B + port (PADDI: out Std_logic; MAin9: in Std_logic); + end component; + component MAin_8_B + port (PADDI: out Std_logic; MAin8: in Std_logic); + end component; + component MAin_7_B + port (PADDI: out Std_logic; MAin7: in Std_logic); + end component; + component MAin_6_B + port (PADDI: out Std_logic; MAin6: in Std_logic); + end component; + component MAin_5_B + port (PADDI: out Std_logic; MAin5: in Std_logic); + end component; + component MAin_4_B + port (PADDI: out Std_logic; MAin4: in Std_logic); + end component; + component MAin_3_B + port (PADDI: out Std_logic; MAin3: in Std_logic); + end component; + component MAin_2_B + port (PADDI: out Std_logic; MAin2: in Std_logic); + end component; + component MAin_1_B + port (PADDI: out Std_logic; MAin1: in Std_logic); + end component; + component MAin_0_B + port (PADDI: out Std_logic; MAin0: in Std_logic); + end component; + component CROW_1_B + port (PADDI: out Std_logic; CROW1: in Std_logic); + end component; + component CROW_0_B + port (PADDI: out Std_logic; CROW0: in Std_logic); + end component; + component Din_7_B + port (PADDI: out Std_logic; Din7: in Std_logic); + end component; + component Din_6_B + port (PADDI: out Std_logic; Din6: in Std_logic); + end component; + component Din_5_B + port (PADDI: out Std_logic; Din5: in Std_logic); + end component; + component Din_4_B + port (PADDI: out Std_logic; Din4: in Std_logic); + end component; + component Din_3_B + port (PADDI: out Std_logic; Din3: in Std_logic); + end component; + component Din_2_B + port (PADDI: out Std_logic; Din2: in Std_logic); + end component; + component Din_1_B + port (PADDI: out Std_logic; Din1: in Std_logic); + end component; + component Din_0_B + port (PADDI: out Std_logic; Din0: in Std_logic); + end component; + component nCCASB + port (PADDI: out Std_logic; nCCASS: in Std_logic); + end component; + component nCRASB + port (PADDI: out Std_logic; nCRASS: in Std_logic); + end component; + component nFWEB + port (PADDI: out Std_logic; nFWES: in Std_logic); + end component; + component RCLKB + port (PADDI: out Std_logic; RCLKS: in Std_logic); + end component; + component UFMSDOB + port (PADDI: out Std_logic; UFMSDOS: in Std_logic); + end component; + begin + SLICE_0I: SLICE_0 + port map (A1=>FS_7, A0=>FS_6, CLK=>RCLK_c, FCI=>n2010, Q0=>FS_6, + Q1=>FS_7, FCO=>n2011); + SLICE_1I: SLICE_1 + port map (A1=>FS_15, A0=>FS_14, CLK=>RCLK_c, FCI=>n2014, Q0=>FS_14, + Q1=>FS_15, FCO=>n2015); + SLICE_2I: SLICE_2 + port map (A1=>FS_5, A0=>FS_4, CLK=>RCLK_c, FCI=>n2009, Q0=>FS_4, + Q1=>FS_5, FCO=>n2010); + SLICE_3I: SLICE_3 + port map (A1=>FS_13, A0=>FS_12, CLK=>RCLK_c, FCI=>n2013, Q0=>FS_12, + Q1=>FS_13, FCO=>n2014); + SLICE_4I: SLICE_4 + port map (A1=>FS_1, A0=>FS_0, CLK=>RCLK_c, Q0=>FS_0, Q1=>FS_1, + FCO=>n2008); + SLICE_5I: SLICE_5 + port map (A1=>FS_11, A0=>FS_10, CLK=>RCLK_c, FCI=>n2012, Q0=>FS_10, + Q1=>FS_11, FCO=>n2013); + SLICE_6I: SLICE_6 + port map (A1=>FS_3, A0=>FS_2, CLK=>RCLK_c, FCI=>n2008, Q0=>FS_2, + Q1=>FS_3, FCO=>n2009); + SLICE_7I: SLICE_7 + port map (A1=>FS_9, A0=>FS_8, CLK=>RCLK_c, FCI=>n2011, Q0=>FS_8, + Q1=>FS_9, FCO=>n2012); + SLICE_8I: SLICE_8 + port map (A1=>FS_17, A0=>FS_16, CLK=>RCLK_c, FCI=>n2015, Q0=>FS_16, + Q1=>FS_17); + SLICE_9I: SLICE_9 + port map (C1=>MAin_c_1, B1=>n1326, A1=>MAin_c_0, D0=>n2263, + C0=>ADSubmitted, B0=>n2242, A0=>n2459, DI0=>n1413, + LSR=>C1Submitted_N_237, CLK=>PHI2_c, F0=>n1413, + Q0=>ADSubmitted, F1=>n2263); + SLICE_14I: SLICE_14 + port map (B1=>Din_c_6, A1=>C1Submitted, D0=>MAin_c_1, C0=>C1Submitted, + B0=>n1326, A0=>nFWE_c, DI0=>n6_adj_3, LSR=>C1Submitted_N_237, + CLK=>PHI2_c, F0=>n6_adj_3, Q0=>C1Submitted, F1=>n2284); + SLICE_18I: SLICE_18 + port map (D1=>MAin_c_5, C1=>n2316, B1=>n26, A1=>MAin_c_2, D0=>n15, + C0=>n1326, B0=>n2463, A0=>MAin_c_1, DI0=>CmdEnable_N_248, + CE=>PHI2_N_120_enable_7, CLK=>PHI2_c, F0=>CmdEnable_N_248, + Q0=>CmdEnable, F1=>n1326); + SLICE_19I: SLICE_19 + port map (C1=>PHI2r2, B1=>CmdSubmitted, A1=>PHI2r3, DI0=>n2568_001_BUF1, + CE=>PHI2_N_120_enable_5, CLK=>PHI2_c, F0=>n2568_001_BUF1, + Q0=>CmdSubmitted, F1=>n2472); + SLICE_23I: SLICE_23 + port map (C1=>Din_c_5, B1=>Din_c_7, A1=>Din_c_6, D0=>n1314, C0=>Din_c_4, + B0=>n8MEGEN, A0=>Din_c_0, DI0=>Cmdn8MEGEN_N_264, + CE=>PHI2_N_120_enable_4, CLK=>PHI2_c, F0=>Cmdn8MEGEN_N_264, + Q0=>Cmdn8MEGEN, F1=>n1314); + SLICE_25I: SLICE_25 + port map (D1=>nRowColSel_N_35, C1=>RASr2, B1=>InitReady, A1=>Ready, + DI0=>n2568_000_BUF1, CE=>RCLK_c_enable_25, CLK=>RCLK_c, + F0=>n2568_000_BUF1, Q0=>InitReady, F1=>RCLK_c_enable_23); + SLICE_26I: SLICE_26 + port map (C1=>nCRAS_c, B1=>CBR, A1=>LEDEN, DI0=>n2568, + CE=>RCLK_c_enable_12, CLK=>RCLK_c, F0=>n2568, Q0=>LEDEN, + F1=>LED_N_84); + SLICE_31I: SLICE_31 + port map (B1=>nRowColSel_N_34, A1=>Ready, C0=>nRCAS_N_165, B0=>Ready, + A0=>n2208, DI0=>n2209, LSR=>nRWE_N_177, CLK=>RCLK_c, F0=>n2209, + Q0=>RA_0S, F1=>n56); + SLICE_32I: SLICE_32 + port map (B1=>Din_c_7, A1=>Din_c_6, C0=>n8MEGEN, B0=>XOR8MEG, + A0=>Din_c_6, DI0=>RA11_N_184, LSR=>Ready, CLK=>PHI2_c, + F0=>RA11_N_184, Q0=>RA_c, F1=>n2478); + SLICE_34I: SLICE_34 + port map (C1=>Ready, B1=>InitReady, A1=>RASr2, C0=>Ready, + B0=>RCKEEN_N_122, A0=>InitReady, DI0=>RCKEEN_N_121, + CE=>RCLK_c_enable_4, CLK=>RCLK_c, F0=>RCKEEN_N_121, Q0=>RCKEEN, + F1=>n2467); + SLICE_35I: SLICE_35 + port map (B1=>RCKE_c, A1=>RASr2, D0=>RASr3, C0=>RASr2, B0=>RCKEEN, + A0=>RASr, DI0=>RCKE_N_132, M1=>CASr, CLK=>RCLK_c, + F0=>RCKE_N_132, Q0=>RCKE_c, F1=>nRWE_N_182, Q1=>CASr2); + SLICE_36I: SLICE_36 + port map (B1=>nRowColSel_N_35, A1=>Ready, DI0=>n2568_002_BUF1, + CE=>Ready_N_292, CLK=>RCLK_c, F0=>n2568_002_BUF1, Q0=>Ready, + F1=>n2469); + SLICE_43I: SLICE_43 + port map (D1=>FS_1, C1=>n2462, B1=>n62, A1=>FS_4, C0=>InitReady, + B0=>n1160, A0=>CmdUFMCLK, DI0=>UFMCLK_N_224, + CE=>RCLK_c_enable_24, LSR=>n1846, CLK=>RCLK_c, + F0=>UFMCLK_N_224, Q0=>UFMCLK_c, F1=>n1160); + SLICE_44I: SLICE_44 + port map (D1=>FS_11, C1=>n2470, B1=>n2272, A1=>n2471, D0=>CmdUFMSDI, + C0=>InitReady, B0=>n2462, A0=>n2461, DI0=>UFMSDI_N_231, + CE=>RCLK_c_enable_24, LSR=>n1846, CLK=>RCLK_c, + F0=>UFMSDI_N_231, Q0=>UFMSDI_c, F1=>n2462); + SLICE_49I: SLICE_49 + port map (D1=>Din_c_1, C1=>n1314, B1=>LEDEN, A1=>Din_c_4, D0=>n2324, + C0=>Din_c_2, B0=>Din_c_3, A0=>Din_c_0, DI0=>XOR8MEG_N_110, + CE=>PHI2_N_120_enable_1, CLK=>PHI2_c, F0=>XOR8MEG_N_110, + Q0=>XOR8MEG, F1=>n2324); + SLICE_56I: SLICE_56 + port map (C1=>FS_10, B1=>n2464, A1=>FS_11, D0=>n1325, C0=>InitReady, + B0=>Cmdn8MEGEN, A0=>UFMSDO_c, DI0=>n8MEGEN_N_91, + CE=>RCLK_c_enable_11, CLK=>RCLK_c, F0=>n8MEGEN_N_91, + Q0=>n8MEGEN, F1=>n1325); + SLICE_58I: SLICE_58 + port map (D1=>n2427, C1=>RASr2, B1=>CBR, A1=>Ready, C0=>Ready, + B0=>n15_adj_1, A0=>nRowColSel_N_34, DI0=>nRCAS_N_161, + M0=>nRowColSel_N_35, CE=>RCLK_c_enable_4, CLK=>RCLK_c, + OFX0=>nRCAS_N_161, Q0=>nRCAS_c); + SLICE_60I: SLICE_60 + port map (D1=>Ready, C1=>RCKE_c, B1=>InitReady, A1=>RASr2, + D0=>nRowColSel_N_35, C0=>n13, B0=>n2481, A0=>n2467, + DI0=>nRCS_N_136, CE=>RCLK_c_enable_4, CLK=>RCLK_c, + F0=>nRCS_N_136, Q0=>nRCS_c, F1=>n13); + SLICE_61I: SLICE_61 + port map (C1=>nRCS_N_139, B1=>n13, A1=>Ready, D0=>nRowColSel_N_32, + C0=>n6, B0=>nRRAS_c, A0=>n56, DI0=>n2138, M0=>nRowColSel_N_35, + CLK=>RCLK_c, OFX0=>n2138, Q0=>nRRAS_c); + SLICE_63I: SLICE_63 + port map (D1=>nRCS_N_139, C1=>InitReady, B1=>RASr2, A1=>nRowColSel_N_35, + D0=>n2208, C0=>Ready, B0=>nRWE_N_178, A0=>n33, DI0=>nRWE_N_171, + CE=>RCLK_c_enable_3, CLK=>RCLK_c, F0=>nRWE_N_171, Q0=>nRWE_c, + F1=>n2208); + SLICE_64I: SLICE_64 + port map (C1=>nRowColSel, B1=>MAin_c_9, A1=>RowA_9, D0=>nRowColSel_N_32, + C0=>nRowColSel_N_28, B0=>n1502, A0=>nRowColSel, DI0=>n1410, + LSR=>n2469, CLK=>RCLK_c, F0=>n1410, Q0=>nRowColSel, F1=>RA_1_9); + SLICE_65I: SLICE_65 + port map (D1=>InitReady, C1=>Ready_N_296, B1=>RASr2, A1=>nRowColSel_N_32, + B0=>nRowColSel_N_33, A0=>nRowColSel_N_32, DI0=>n1503, + LSR=>RASr2, CLK=>RCLK_c, F0=>n1503, Q0=>nRowColSel_N_32, + F1=>n2414); + SLICE_66I: SLICE_66 + port map (D1=>nRowColSel_N_33, C1=>nRowColSel_N_34, B1=>n2469, + A1=>nRowColSel_N_32, B0=>RASr2, A0=>nRowColSel_N_32, + DI0=>n1093, LSR=>nRowColSel_N_34, CLK=>RCLK_c, F0=>n1093, + Q0=>nRowColSel_N_33, F1=>RCLK_c_enable_4); + SLICE_67I: SLICE_67 + port map (C1=>n2472, B1=>CmdUFMCS, A1=>nUFMCS_c, B0=>CASr2, + A0=>nRowColSel_N_33, M0=>n1093, LSR=>nRowColSel_N_35, + CLK=>RCLK_c, F0=>n11, Q0=>nRowColSel_N_34, F1=>n1417); + SLICE_68I: SLICE_68 + port map (B1=>FS_12, A1=>FS_17, D0=>FS_3, C0=>FS_6, B0=>FS_1, A0=>FS_0, + M1=>CASr2, M0=>RASr2, CLK=>RCLK_c, F0=>n2322, + Q0=>nRowColSel_N_35, F1=>n2471, Q1=>CASr3); + SLICE_69I: SLICE_69 + port map (D1=>FS_14, C1=>FS_12, B1=>n12, A1=>FS_17, C0=>InitReady, + B0=>n1417, A0=>n62, DI0=>n2164, LSR=>LEDEN_N_82, CLK=>RCLK_c, + F0=>n2164, Q0=>nUFMCS_c, F1=>n62); + RCKEEN_I_0_445_SLICE_70I: RCKEEN_I_0_445_SLICE_70 + port map (C1=>RASr2, B1=>FWEr, A1=>CBR, D0=>nRowColSel_N_34, C0=>FWEr, + B0=>n11, A0=>CBR, M0=>nRowColSel_N_35, OFX0=>RCKEEN_N_122); + i26_SLICE_71I: i26_SLICE_71 + port map (D1=>n2284, C1=>n2476, B1=>MAin_c_1, A1=>MAin_c_0, + D0=>ADSubmitted, C0=>MAin_c_0, B0=>n2475, A0=>Din_c_5, + M0=>Din_c_2, OFX0=>n13_adj_2); + i2099_SLICE_72I: i2099_SLICE_72 + port map (D1=>nRowColSel_N_34, C1=>nRowColSel_N_35, B1=>Ready, + A1=>nRCS_N_139, C0=>nRowColSel_N_35, B0=>Ready, A0=>nRCS_N_139, + M0=>n15_adj_1, OFX0=>n2481); + i26_adj_28_SLICE_73I: i26_adj_28_SLICE_73 + port map (D1=>MAin_c_0, C1=>Din_c_2, B1=>Din_c_3, A1=>Din_c_6, + D0=>MAin_c_0, C0=>Din_c_2, B0=>Din_c_3, A0=>Din_c_6, + M0=>Din_c_5, OFX0=>n15); + SLICE_74I: SLICE_74 + port map (D1=>n1, C1=>nRowColSel_N_33, B1=>CBR, A1=>FWEr, D0=>CASr3, + C0=>CASr2, B0=>FWEr, A0=>CBR, M1=>RASr2, M0=>RASr, CLK=>RCLK_c, + F0=>n1, Q0=>RASr2, F1=>n15_adj_1, Q1=>RASr3); + SLICE_75I: SLICE_75 + port map (C1=>InitReady, B1=>FS_11, A1=>n2214, D0=>FS_11, C0=>n2272, + B0=>n2328, A0=>FS_10, F0=>n2214, F1=>RCLK_c_enable_12); + SLICE_76I: SLICE_76 + port map (D1=>MAin_c_0, C1=>n10, B1=>n1326, A1=>nFWE_c, D0=>n2458, + C0=>Din_c_4, B0=>Din_c_5, A0=>Din_c_3, M1=>n732, M0=>n733, + CE=>RCLK_c_enable_23, CLK=>RCLK_c, F0=>PHI2_N_120_enable_4, + Q0=>n732, F1=>n2458, Q1=>nRWE_N_177); + SLICE_77I: SLICE_77 + port map (D1=>FS_7, C1=>n2322, B1=>FS_4, A1=>n2290, C0=>FS_9, B0=>FS_5, + A0=>FS_2, M1=>n728, M0=>n729, CE=>RCLK_c_enable_23, + CLK=>RCLK_c, F0=>n2290, Q0=>n728, F1=>n8, Q1=>n727); + SLICE_78I: SLICE_78 + port map (D1=>n2471, C1=>n2272, B1=>FS_14, A1=>FS_16, C0=>InitReady, + B0=>n2464, A0=>FS_11, M1=>MAin_c_7, M0=>MAin_c_6, LSR=>Ready, + CLK=>nCRAS_c, F0=>n1846, Q0=>RowA_6, F1=>n2464, Q1=>RowA_7); + SLICE_79I: SLICE_79 + port map (C1=>Din_c_5, B1=>Din_c_3, A1=>Din_c_6, D0=>n2468, C0=>n1280, + B0=>n2463, A0=>Din_c_2, M1=>PHI2r, M0=>nCCAS_c, CLK=>RCLK_c, + F0=>C1Submitted_N_237, Q0=>CASr, F1=>n2468, Q1=>PHI2r2); + SLICE_80I: SLICE_80 + port map (B1=>nRowColSel_N_33, A1=>nRowColSel_N_34, D0=>nRowColSel_N_35, + C0=>n1502, B0=>nRowColSel_N_32, A0=>Ready, M1=>n726, M0=>n727, + CE=>RCLK_c_enable_23, CLK=>RCLK_c, F0=>RCLK_c_enable_3, + Q0=>n726, F1=>n1502, Q1=>Ready_N_296); + SLICE_81I: SLICE_81 + port map (B1=>Bank_3, A1=>Bank_6, D0=>Bank_5, C0=>n2278, B0=>n2314, + A0=>Bank_2, M1=>Din_c_2, M0=>Din_c_1, CE=>PHI2_N_120_enable_6, + CLK=>PHI2_c, F0=>n26, Q0=>CmdUFMCLK, F1=>n2278, Q1=>CmdUFMCS); + SLICE_82I: SLICE_82 + port map (D1=>MAin_c_1, C1=>n14, B1=>n2460, A1=>MAin_c_0, B0=>n1326, + A0=>nFWE_c, M1=>n730, M0=>nRWE_N_177, CE=>RCLK_c_enable_23, + CLK=>RCLK_c, F0=>n2460, Q0=>n730, F1=>PHI2_N_120_enable_7, + Q1=>n729); + SLICE_83I: SLICE_83 + port map (D1=>n2476, C1=>n2460, B1=>n10, A1=>MAin_c_0, D0=>MAin_c_1, + C0=>CmdEnable, B0=>n2478, A0=>Din_c_4, M0=>nCRAS_c, + CLK=>RCLK_c, F0=>n10, Q0=>RASr, F1=>PHI2_N_120_enable_6); + SLICE_84I: SLICE_84 + port map (D1=>n1314, C1=>n2262, B1=>CmdEnable, A1=>n2473, C0=>MAin_c_1, + B0=>n1326, A0=>MAin_c_0, M1=>n738, M0=>nRCAS_N_165, + CE=>RCLK_c_enable_23, CLK=>RCLK_c, F0=>n2262, Q0=>n738, + F1=>PHI2_N_120_enable_1, Q1=>n737); + SLICE_85I: SLICE_85 + port map (D1=>n2474, C1=>Din_c_5, B1=>n2253, A1=>n2473, B0=>nFWE_c, + A0=>Din_c_4, M1=>CROW_c_1, M0=>CROW_c_0, LSR=>Ready, + CLK=>nCRAS_c, F0=>n2473, Q0=>RBA_c_0, F1=>n2242, Q1=>RBA_c_1); + SLICE_86I: SLICE_86 + port map (C1=>Din_c_1, B1=>Din_c_0, A1=>Din_c_7, C0=>n2253, B0=>nFWE_c, + A0=>Din_c_4, M1=>n734, M0=>n735, CE=>RCLK_c_enable_23, + CLK=>RCLK_c, F0=>n2463, Q0=>n734, F1=>n2253, Q1=>n733); + SLICE_87I: SLICE_87 + port map (B1=>n2214, A1=>FS_8, D0=>n8, C0=>InitReady, B0=>n2472, A0=>n7, + M1=>nRCS_N_139, M0=>Ready_N_296, CE=>RCLK_c_enable_23, + CLK=>RCLK_c, F0=>RCLK_c_enable_11, Q0=>nRCS_N_139, F1=>n7, + Q1=>nRCAS_N_165); + SLICE_88I: SLICE_88 + port map (C1=>FS_10, B1=>FS_6, A1=>n2451, D0=>FS_8, C0=>FS_5, B0=>FS_9, + A0=>FS_7, M1=>Din_c_1, M0=>Din_c_0, CLK=>PHI2_c, F0=>n2451, + Q0=>Bank_0, F1=>n2461, Q1=>Bank_1); + SLICE_89I: SLICE_89 + port map (C1=>MAin_c_1, B1=>n1326, A1=>nFWE_c, C0=>MAin_c_0, B0=>n1326, + A0=>MAin_c_1, M1=>Din_c_1, M0=>Din_c_0, CLK=>nCCAS_c, + F0=>n1280, Q0=>WRD_0, F1=>n2459, Q1=>WRD_1); + SLICE_90I: SLICE_90 + port map (D1=>FS_16, C1=>FS_14, B1=>FS_12, A1=>FS_17, B0=>FS_14, + A0=>FS_16, M1=>MAin_c_9, M0=>MAin_c_8, LSR=>Ready, + CLK=>nCRAS_c, F0=>n2470, Q0=>RowA_8, F1=>n2328, Q1=>RowA_9); + SLICE_91I: SLICE_91 + port map (B1=>Din_c_5, A1=>Din_c_3, D0=>n2458, C0=>Din_c_5, B0=>Din_c_4, + A0=>Din_c_3, M1=>PHI2_c, M0=>PHI2r2, CLK=>RCLK_c, + F0=>PHI2_N_120_enable_5, Q0=>PHI2r3, F1=>n2476, Q1=>PHI2r); + SLICE_92I: SLICE_92 + port map (B1=>Din_c_3, A1=>Din_c_6, C0=>Din_c_3, B0=>Din_c_2, + A0=>Din_c_6, M1=>Din_c_7, M0=>Din_c_6, CLK=>nCCAS_c, F0=>n2474, + Q0=>WRD_6, F1=>n2475, Q1=>WRD_7); + SLICE_93I: SLICE_93 + port map (B1=>nRowColSel, A1=>MAin_c_9, B0=>nRowColSel, A0=>MAin_c_9, + M0=>Din_c_0, CE=>PHI2_N_120_enable_6, CLK=>PHI2_c, F0=>RDQMH_c, + Q0=>CmdUFMSDI, F1=>RDQML_c); + SLICE_94I: SLICE_94 + port map (B1=>FS_15, A1=>FS_13, D0=>FS_11, C0=>FS_16, B0=>FS_13, + A0=>FS_15, F0=>n12, F1=>n2272); + SLICE_95I: SLICE_95 + port map (B1=>FS_10, A1=>n62, D0=>InitReady, C0=>FS_10, B0=>n2464, + A0=>FS_11, M1=>MAin_c_5, M0=>MAin_c_4, LSR=>Ready, + CLK=>nCRAS_c, F0=>LEDEN_N_82, Q0=>RowA_4, F1=>RCLK_c_enable_25, + Q1=>RowA_5); + SLICE_96I: SLICE_96 + port map (C1=>nRowColSel, B1=>MAin_c_3, A1=>RowA_3, D0=>Bank_1, + C0=>Bank_4, B0=>MAin_c_3, A0=>MAin_c_7, M1=>MAin_c_3, + M0=>MAin_c_2, LSR=>Ready, CLK=>nCRAS_c, F0=>n2316, Q0=>RowA_2, + F1=>RA_1_3, Q1=>RowA_3); + SLICE_97I: SLICE_97 + port map (C1=>nRowColSel, B1=>MAin_c_4, A1=>RowA_4, D0=>Bank_0, + C0=>Bank_7, B0=>MAin_c_4, A0=>MAin_c_6, M1=>MAin_c_1, + M0=>MAin_c_0, LSR=>Ready, CLK=>nCRAS_c, F0=>n2314, Q0=>RowA_0, + F1=>RA_1_4, Q1=>RowA_1); + SLICE_98I: SLICE_98 + port map (C1=>nRowColSel, B1=>MAin_c_0, A1=>RowA_0, C0=>nRowColSel, + B0=>MAin_c_8, A0=>RowA_8, M1=>nFWE_c, M0=>nCCAS_c, + CLK=>nCRAS_c, F0=>RA_1_8, Q0=>CBR, F1=>RA_1_0, Q1=>FWEr); + SLICE_99I: SLICE_99 + port map (C1=>nRowColSel, B1=>MAin_c_1, A1=>RowA_1, C0=>nRowColSel, + B0=>MAin_c_7, A0=>RowA_7, M1=>Din_c_7, M0=>Din_c_6, + CLK=>PHI2_c, F0=>RA_1_7, Q0=>Bank_6, F1=>RA_1_1, Q1=>Bank_7); + SLICE_100I: SLICE_100 + port map (D1=>Ready, C1=>nRowColSel_N_33, B1=>InitReady, A1=>RASr2, + D0=>InitReady, C0=>PHI2r2, B0=>CmdSubmitted, A0=>PHI2r3, + M1=>n736, M0=>n737, CE=>RCLK_c_enable_23, CLK=>RCLK_c, + F0=>RCLK_c_enable_24, Q0=>n736, F1=>n6, Q1=>n735); + SLICE_101I: SLICE_101 + port map (C1=>nRowColSel, B1=>MAin_c_2, A1=>RowA_2, C0=>nRowColSel, + B0=>MAin_c_6, A0=>RowA_6, M1=>Din_c_5, M0=>Din_c_4, + CLK=>PHI2_c, F0=>RA_1_6, Q0=>Bank_4, F1=>RA_1_2, Q1=>Bank_5); + SLICE_102I: SLICE_102 + port map (B1=>nRWE_N_177, A1=>nRCAS_N_165, C0=>nRCAS_N_165, + B0=>nRCS_N_139, A0=>InitReady, M1=>Din_c_3, M0=>Din_c_2, + CLK=>PHI2_c, F0=>n2427, Q0=>Bank_2, F1=>n33, Q1=>Bank_3); + SLICE_103I: SLICE_103 + port map (C1=>nRowColSel, B1=>MAin_c_5, A1=>RowA_5, C0=>CBR, B0=>CASr3, + A0=>FWEr, M1=>Din_c_3, M0=>Din_c_2, CLK=>nCCAS_c, + F0=>nRowColSel_N_28, Q0=>WRD_2, F1=>RA_1_5, Q1=>WRD_3); + SLICE_104I: SLICE_104 + port map (B1=>Ready, A1=>n2414, D0=>nRowColSel_N_35, C0=>nRWE_N_182, + B0=>n1502, A0=>n1, F0=>nRWE_N_178, F1=>Ready_N_292); + SLICE_105I: SLICE_105 + port map (B1=>nFWE_c, A1=>nCCAS_c, C0=>n13_adj_2, B0=>Din_c_4, A0=>n2253, + M1=>Din_c_5, M0=>Din_c_4, CLK=>nCCAS_c, F0=>n14, Q0=>WRD_4, + F1=>n984, Q1=>WRD_5); + RD_7_I: RD_7_B + port map (PADDI=>Dout_c, PADDT=>n984, PADDO=>WRD_7, RD7=>RD(7)); + RD_6_I: RD_6_B + port map (PADDI=>Dout_0S, PADDT=>n984, PADDO=>WRD_6, RD6=>RD(6)); + RD_5_I: RD_5_B + port map (PADDI=>Dout_1S, PADDT=>n984, PADDO=>WRD_5, RD5=>RD(5)); + RD_4_I: RD_4_B + port map (PADDI=>Dout_2S, PADDT=>n984, PADDO=>WRD_4, RD4=>RD(4)); + RD_3_I: RD_3_B + port map (PADDI=>Dout_3S, PADDT=>n984, PADDO=>WRD_3, RD3=>RD(3)); + RD_2_I: RD_2_B + port map (PADDI=>Dout_4S, PADDT=>n984, PADDO=>WRD_2, RD2=>RD(2)); + RD_1_I: RD_1_B + port map (PADDI=>Dout_5S, PADDT=>n984, PADDO=>WRD_1, RD1=>RD(1)); + RD_0_I: RD_0_B + port map (PADDI=>Dout_6S, PADDT=>n984, PADDO=>WRD_0, RD0=>RD(0)); + Dout_7_I: Dout_7_B + port map (PADDO=>Dout_c, Dout7=>Dout(7)); + Dout_6_I: Dout_6_B + port map (PADDO=>Dout_0S, Dout6=>Dout(6)); + Dout_5_I: Dout_5_B + port map (PADDO=>Dout_1S, Dout5=>Dout(5)); + Dout_4_I: Dout_4_B + port map (PADDO=>Dout_2S, Dout4=>Dout(4)); + Dout_3_I: Dout_3_B + port map (PADDO=>Dout_3S, Dout3=>Dout(3)); + Dout_2_I: Dout_2_B + port map (PADDO=>Dout_4S, Dout2=>Dout(2)); + Dout_1_I: Dout_1_B + port map (PADDO=>Dout_5S, Dout1=>Dout(1)); + Dout_0_I: Dout_0_B + port map (PADDO=>Dout_6S, Dout0=>Dout(0)); + LEDI: LEDB + port map (PADDO=>LED_N_84, LEDS=>LED); + RBA_1_I: RBA_1_B + port map (PADDO=>RBA_c_1, RBA1=>RBA(1)); + RBA_0_I: RBA_0_B + port map (PADDO=>RBA_c_0, RBA0=>RBA(0)); + RA_11_I: RA_11_B + port map (PADDO=>RA_c, RA11=>RA(11)); + RA_10_I: RA_10_B + port map (PADDO=>RA_0S, RA10=>RA(10)); + RA_9_I: RA_9_B + port map (PADDO=>RA_1_9, RA9=>RA(9)); + RA_8_I: RA_8_B + port map (PADDO=>RA_1_8, RA8=>RA(8)); + RA_7_I: RA_7_B + port map (PADDO=>RA_1_7, RA7=>RA(7)); + RA_6_I: RA_6_B + port map (PADDO=>RA_1_6, RA6=>RA(6)); + RA_5_I: RA_5_B + port map (PADDO=>RA_1_5, RA5=>RA(5)); + RA_4_I: RA_4_B + port map (PADDO=>RA_1_4, RA4=>RA(4)); + RA_3_I: RA_3_B + port map (PADDO=>RA_1_3, RA3=>RA(3)); + RA_2_I: RA_2_B + port map (PADDO=>RA_1_2, RA2=>RA(2)); + RA_1_I: RA_1_B + port map (PADDO=>RA_1_1, RA1=>RA(1)); + RA_0_I: RA_0_B + port map (PADDO=>RA_1_0, RA0=>RA(0)); + nRCSI: nRCSB + port map (PADDO=>nRCS_c, nRCSS=>nRCS); + RCKEI: RCKEB + port map (PADDO=>RCKE_c, RCKES=>RCKE); + nRWEI: nRWEB + port map (PADDO=>nRWE_c, nRWES=>nRWE); + nRRASI: nRRASB + port map (PADDO=>nRRAS_c, nRRASS=>nRRAS); + nRCASI: nRCASB + port map (PADDO=>nRCAS_c, nRCASS=>nRCAS); + RDQMHI: RDQMHB + port map (PADDO=>RDQMH_c, RDQMHS=>RDQMH); + RDQMLI: RDQMLB + port map (PADDO=>RDQML_c, RDQMLS=>RDQML); + nUFMCSI: nUFMCSB + port map (PADDO=>nUFMCS_c, nUFMCSS=>nUFMCS); + UFMCLKI: UFMCLKB + port map (PADDO=>UFMCLK_c, UFMCLKS=>UFMCLK); + UFMSDII: UFMSDIB + port map (PADDO=>UFMSDI_c, UFMSDIS=>UFMSDI); + PHI2I: PHI2B + port map (PADDI=>PHI2_c, PHI2S=>PHI2); + MAin_9_I: MAin_9_B + port map (PADDI=>MAin_c_9, MAin9=>MAin(9)); + MAin_8_I: MAin_8_B + port map (PADDI=>MAin_c_8, MAin8=>MAin(8)); + MAin_7_I: MAin_7_B + port map (PADDI=>MAin_c_7, MAin7=>MAin(7)); + MAin_6_I: MAin_6_B + port map (PADDI=>MAin_c_6, MAin6=>MAin(6)); + MAin_5_I: MAin_5_B + port map (PADDI=>MAin_c_5, MAin5=>MAin(5)); + MAin_4_I: MAin_4_B + port map (PADDI=>MAin_c_4, MAin4=>MAin(4)); + MAin_3_I: MAin_3_B + port map (PADDI=>MAin_c_3, MAin3=>MAin(3)); + MAin_2_I: MAin_2_B + port map (PADDI=>MAin_c_2, MAin2=>MAin(2)); + MAin_1_I: MAin_1_B + port map (PADDI=>MAin_c_1, MAin1=>MAin(1)); + MAin_0_I: MAin_0_B + port map (PADDI=>MAin_c_0, MAin0=>MAin(0)); + CROW_1_I: CROW_1_B + port map (PADDI=>CROW_c_1, CROW1=>CROW(1)); + CROW_0_I: CROW_0_B + port map (PADDI=>CROW_c_0, CROW0=>CROW(0)); + Din_7_I: Din_7_B + port map (PADDI=>Din_c_7, Din7=>Din(7)); + Din_6_I: Din_6_B + port map (PADDI=>Din_c_6, Din6=>Din(6)); + Din_5_I: Din_5_B + port map (PADDI=>Din_c_5, Din5=>Din(5)); + Din_4_I: Din_4_B + port map (PADDI=>Din_c_4, Din4=>Din(4)); + Din_3_I: Din_3_B + port map (PADDI=>Din_c_3, Din3=>Din(3)); + Din_2_I: Din_2_B + port map (PADDI=>Din_c_2, Din2=>Din(2)); + Din_1_I: Din_1_B + port map (PADDI=>Din_c_1, Din1=>Din(1)); + Din_0_I: Din_0_B + port map (PADDI=>Din_c_0, Din0=>Din(0)); + nCCASI: nCCASB + port map (PADDI=>nCCAS_c, nCCASS=>nCCAS); + nCRASI: nCRASB + port map (PADDI=>nCRAS_c, nCRASS=>nCRAS); + nFWEI: nFWEB + port map (PADDI=>nFWE_c, nFWES=>nFWE); + RCLKI: RCLKB + port map (PADDI=>RCLK_c, RCLKS=>RCLK); + UFMSDOI: UFMSDOB + port map (PADDI=>UFMSDO_c, UFMSDOS=>UFMSDO); + VHI_INST: VHI + port map (Z=>VCCI); + PUR_INST: PUR + port map (PUR=>VCCI); + GSR_INST: GSR + port map (GSR=>VCCI); + VLO_INST: VLO + port map (Z=>GNDI_TSALL); + TSALL_INST: TSALL + port map (TSALL=>GNDI_TSALL); + end Structure; + + + + library IEEE, vital2000, MACHXO; + configuration Structure_CON of RAM2GS is + for Structure + end for; + end Structure_CON; + + diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.sdf b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.sdf new file mode 100644 index 0000000..834db9e --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.sdf @@ -0,0 +1,3036 @@ +(DELAYFILE + (SDFVERSION "3.0") + (DESIGN "RAM2GS") + (DATE "Tue Aug 15 05:03:22 2023") + (VENDOR "Lattice") + (PROGRAM "ldbanno") + (VERSION "Diamond (64-bit) 3.12.1.454") + (DIVIDER /) + (VOLTAGE 1.26:1.20:1.14) + (PROCESS "default") + (TEMPERATURE -40:25:85) + (TIMESCALE 1ps) + (CELL + (CELLTYPE "SLICE_0") + (INSTANCE SLICE_0) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_1") + (INSTANCE SLICE_1) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_2") + (INSTANCE SLICE_2) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_3") + (INSTANCE SLICE_3) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_4") + (INSTANCE SLICE_4) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + ) + ) + (CELL + (CELLTYPE "SLICE_5") + (INSTANCE SLICE_5) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_6") + (INSTANCE SLICE_6) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_7") + (INSTANCE SLICE_7) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_8") + (INSTANCE SLICE_8) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_9") + (INSTANCE SLICE_9) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_14") + (INSTANCE SLICE_14) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_18") + (INSTANCE SLICE_18) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_19") + (INSTANCE SLICE_19) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_23") + (INSTANCE SLICE_23) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_25") + (INSTANCE SLICE_25) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_26") + (INSTANCE SLICE_26) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_31") + (INSTANCE SLICE_31) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_32") + (INSTANCE SLICE_32) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_34") + (INSTANCE SLICE_34) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_35") + (INSTANCE SLICE_35) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_36") + (INSTANCE SLICE_36) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_43") + (INSTANCE SLICE_43) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_44") + (INSTANCE SLICE_44) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_49") + (INSTANCE SLICE_49) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_56") + (INSTANCE SLICE_56) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_58") + (INSTANCE SLICE_58) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_60") + (INSTANCE SLICE_60) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_61") + (INSTANCE SLICE_61) + (DELAY + (ABSOLUTE + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH D0 OFX0 (508:569:631)(508:569:631)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_63") + (INSTANCE SLICE_63) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_64") + (INSTANCE SLICE_64) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_65") + (INSTANCE SLICE_65) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_66") + (INSTANCE SLICE_66) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_67") + (INSTANCE SLICE_67) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_68") + (INSTANCE SLICE_68) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_69") + (INSTANCE SLICE_69) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "RCKEEN_I_0_445_SLICE_70") + (INSTANCE RCKEEN_I_0_445\/SLICE_70) + (DELAY + (ABSOLUTE + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH D0 OFX0 (508:569:631)(508:569:631)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + ) + ) + ) + (CELL + (CELLTYPE "i26_SLICE_71") + (INSTANCE i26\/SLICE_71) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH D0 OFX0 (508:569:631)(508:569:631)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + ) + ) + ) + (CELL + (CELLTYPE "i2099_SLICE_72") + (INSTANCE i2099\/SLICE_72) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + ) + ) + ) + (CELL + (CELLTYPE "i26_adj_28_SLICE_73") + (INSTANCE i26_adj_28\/SLICE_73) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH D0 OFX0 (508:569:631)(508:569:631)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_74") + (INSTANCE SLICE_74) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_75") + (INSTANCE SLICE_75) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_76") + (INSTANCE SLICE_76) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_77") + (INSTANCE SLICE_77) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_78") + (INSTANCE SLICE_78) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_79") + (INSTANCE SLICE_79) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_80") + (INSTANCE SLICE_80) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_81") + (INSTANCE SLICE_81) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_82") + (INSTANCE SLICE_82) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_83") + (INSTANCE SLICE_83) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_84") + (INSTANCE SLICE_84) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_85") + (INSTANCE SLICE_85) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_86") + (INSTANCE SLICE_86) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_87") + (INSTANCE SLICE_87) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_88") + (INSTANCE SLICE_88) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_89") + (INSTANCE SLICE_89) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "SLICE_90") + (INSTANCE SLICE_90) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_91") + (INSTANCE SLICE_91) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_92") + (INSTANCE SLICE_92) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "SLICE_93") + (INSTANCE SLICE_93) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_94") + (INSTANCE SLICE_94) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_95") + (INSTANCE SLICE_95) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_96") + (INSTANCE SLICE_96) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_97") + (INSTANCE SLICE_97) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_98") + (INSTANCE SLICE_98) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "SLICE_99") + (INSTANCE SLICE_99) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_100") + (INSTANCE SLICE_100) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_101") + (INSTANCE SLICE_101) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_102") + (INSTANCE SLICE_102) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_103") + (INSTANCE SLICE_103) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "SLICE_104") + (INSTANCE SLICE_104) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_105") + (INSTANCE SLICE_105) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "RD_7_") + (INSTANCE RD\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD7 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD7 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD7 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD7) (1250:1250:1250)) + (WIDTH (negedge RD7) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_6_") + (INSTANCE RD\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD6 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD6 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD6 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD6) (1250:1250:1250)) + (WIDTH (negedge RD6) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_5_") + (INSTANCE RD\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD5 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD5 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD5 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD5) (1250:1250:1250)) + (WIDTH (negedge RD5) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_4_") + (INSTANCE RD\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD4 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD4 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD4 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD4) (1250:1250:1250)) + (WIDTH (negedge RD4) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_3_") + (INSTANCE RD\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD3 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD3 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD3 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD3) (1250:1250:1250)) + (WIDTH (negedge RD3) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_2_") + (INSTANCE RD\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD2 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD2 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD2 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD2) (1250:1250:1250)) + (WIDTH (negedge RD2) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_1_") + (INSTANCE RD\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD1 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD1 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD1 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD1) (1250:1250:1250)) + (WIDTH (negedge RD1) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_0_") + (INSTANCE RD\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD0 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD0 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD0 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD0) (1250:1250:1250)) + (WIDTH (negedge RD0) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Dout_7_") + (INSTANCE Dout\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout7 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_6_") + (INSTANCE Dout\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout6 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_5_") + (INSTANCE Dout\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout5 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_4_") + (INSTANCE Dout\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout4 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_3_") + (INSTANCE Dout\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout3 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_2_") + (INSTANCE Dout\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout2 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_1_") + (INSTANCE Dout\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout1 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_0_") + (INSTANCE Dout\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout0 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "LED") + (INSTANCE LED_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO LED (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_1_") + (INSTANCE RBA\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RBA1 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_0_") + (INSTANCE RBA\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RBA0 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_11_") + (INSTANCE RA\[11\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA11 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_10_") + (INSTANCE RA\[10\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA10 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_9_") + (INSTANCE RA\[9\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA9 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_8_") + (INSTANCE RA\[8\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA8 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_7_") + (INSTANCE RA\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA7 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_6_") + (INSTANCE RA\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA6 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_5_") + (INSTANCE RA\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA5 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_4_") + (INSTANCE RA\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA4 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_3_") + (INSTANCE RA\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA3 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_2_") + (INSTANCE RA\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA2 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_1_") + (INSTANCE RA\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA1 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_0_") + (INSTANCE RA\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA0 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nRCS") + (INSTANCE nRCS_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRCS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RCKE") + (INSTANCE RCKE_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RCKE (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nRWE") + (INSTANCE nRWE_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRWE (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nRRAS") + (INSTANCE nRRAS_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRRAS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nRCAS") + (INSTANCE nRCAS_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRCAS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RDQMH") + (INSTANCE RDQMH_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RDQMH (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RDQML") + (INSTANCE RDQML_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RDQML (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nUFMCS") + (INSTANCE nUFMCS_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nUFMCS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "UFMCLK") + (INSTANCE UFMCLK_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO UFMCLK (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "UFMSDI") + (INSTANCE UFMSDI_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO UFMSDI (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "PHI2") + (INSTANCE PHI2_I) + (DELAY + (ABSOLUTE + (IOPATH PHI2 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge PHI2) (1250:1250:1250)) + (WIDTH (negedge PHI2) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_9_") + (INSTANCE MAin\[9\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin9 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin9) (1250:1250:1250)) + (WIDTH (negedge MAin9) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_8_") + (INSTANCE MAin\[8\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin8 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin8) (1250:1250:1250)) + (WIDTH (negedge MAin8) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_7_") + (INSTANCE MAin\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin7 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin7) (1250:1250:1250)) + (WIDTH (negedge MAin7) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_6_") + (INSTANCE MAin\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin6 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin6) (1250:1250:1250)) + (WIDTH (negedge MAin6) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_5_") + (INSTANCE MAin\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin5 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin5) (1250:1250:1250)) + (WIDTH (negedge MAin5) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_4_") + (INSTANCE MAin\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin4 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin4) (1250:1250:1250)) + (WIDTH (negedge MAin4) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_3_") + (INSTANCE MAin\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin3 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin3) (1250:1250:1250)) + (WIDTH (negedge MAin3) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_2_") + (INSTANCE MAin\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin2 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin2) (1250:1250:1250)) + (WIDTH (negedge MAin2) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_1_") + (INSTANCE MAin\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin1 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin1) (1250:1250:1250)) + (WIDTH (negedge MAin1) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_0_") + (INSTANCE MAin\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin0 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin0) (1250:1250:1250)) + (WIDTH (negedge MAin0) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "CROW_1_") + (INSTANCE CROW\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH CROW1 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW1) (1250:1250:1250)) + (WIDTH (negedge CROW1) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "CROW_0_") + (INSTANCE CROW\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH CROW0 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW0) (1250:1250:1250)) + (WIDTH (negedge CROW0) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_7_") + (INSTANCE Din\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din7 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din7) (1250:1250:1250)) + (WIDTH (negedge Din7) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_6_") + (INSTANCE Din\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din6 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din6) (1250:1250:1250)) + (WIDTH (negedge Din6) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_5_") + (INSTANCE Din\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din5 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din5) (1250:1250:1250)) + (WIDTH (negedge Din5) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_4_") + (INSTANCE Din\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din4 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din4) (1250:1250:1250)) + (WIDTH (negedge Din4) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_3_") + (INSTANCE Din\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din3 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din3) (1250:1250:1250)) + (WIDTH (negedge Din3) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_2_") + (INSTANCE Din\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din2 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din2) (1250:1250:1250)) + (WIDTH (negedge Din2) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_1_") + (INSTANCE Din\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din1 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din1) (1250:1250:1250)) + (WIDTH (negedge Din1) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_0_") + (INSTANCE Din\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din0 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din0) (1250:1250:1250)) + (WIDTH (negedge Din0) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "nCCAS") + (INSTANCE nCCAS_I) + (DELAY + (ABSOLUTE + (IOPATH nCCAS PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nCCAS) (1250:1250:1250)) + (WIDTH (negedge nCCAS) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "nCRAS") + (INSTANCE nCRAS_I) + (DELAY + (ABSOLUTE + (IOPATH nCRAS PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nCRAS) (1250:1250:1250)) + (WIDTH (negedge nCRAS) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "nFWE") + (INSTANCE nFWE_I) + (DELAY + (ABSOLUTE + (IOPATH nFWE PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nFWE) (1250:1250:1250)) + (WIDTH (negedge nFWE) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RCLK") + (INSTANCE RCLK_I) + (DELAY + (ABSOLUTE + (IOPATH RCLK PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RCLK) (1250:1250:1250)) + (WIDTH (negedge RCLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "UFMSDO") + (INSTANCE UFMSDO_I) + (DELAY + (ABSOLUTE + (IOPATH UFMSDO PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge UFMSDO) (1250:1250:1250)) + (WIDTH (negedge UFMSDO) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RAM2GS") + (INSTANCE ) + (DELAY + (ABSOLUTE + (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_77/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_88/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q0 SLICE_0/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q0 SLICE_68/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q0 SLICE_88/B1 (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_0/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_1/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_2/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_3/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_4/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_5/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_6/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_7/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_8/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_25/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_26/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_31/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_34/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_35/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_36/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_43/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_44/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_56/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_58/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_60/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_61/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_63/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_64/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_65/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_66/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_67/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_68/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_69/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_74/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_76/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_77/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_79/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_80/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_82/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_83/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_84/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_86/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_87/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_91/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_100/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/FCO SLICE_0/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/FCO SLICE_7/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_1/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_94/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_94/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_69/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_78/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_90/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_90/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/FCO SLICE_1/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/FCO SLICE_8/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_77/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_88/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_43/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_77/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/FCO SLICE_2/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_94/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_94/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_68/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_69/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_90/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/FCO SLICE_3/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_43/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_68/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q0 SLICE_68/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/FCO SLICE_6/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_44/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_56/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_75/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_75/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_78/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_94/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_95/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_5/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_56/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_75/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_88/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_95/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_95/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/FCO SLICE_5/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_6/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_68/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q0 SLICE_6/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q0 SLICE_77/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q1 SLICE_7/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q1 SLICE_77/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q1 SLICE_88/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q0 SLICE_7/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q0 SLICE_87/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q0 SLICE_88/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q1 SLICE_8/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q1 SLICE_68/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q1 SLICE_69/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q1 SLICE_90/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q0 SLICE_8/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q0 SLICE_78/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q0 SLICE_90/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q0 SLICE_90/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q0 SLICE_94/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_9/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_14/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_18/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI i26\/SLICE_71/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_82/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_83/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_84/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_89/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_89/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_97/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_99/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F1 SLICE_9/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F1 SLICE_14/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F1 SLICE_18/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F1 SLICE_76/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F1 SLICE_82/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F1 SLICE_84/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F1 SLICE_89/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F1 SLICE_89/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_9/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI i26\/SLICE_71/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI i26\/SLICE_71/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI i26_adj_28\/SLICE_73/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI i26_adj_28\/SLICE_73/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_76/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_82/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_83/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_84/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_89/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_97/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_98/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/F1 SLICE_9/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q0 SLICE_9/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q0 i26\/SLICE_71/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F1 SLICE_9/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/F1 SLICE_9/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/F0 SLICE_9/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F0 SLICE_9/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F0 SLICE_14/LSR (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_9/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_14/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_18/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_19/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_23/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_32/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_49/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_81/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_88/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_91/M1 (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_93/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_99/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_101/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_102/CLK (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_14/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_23/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_32/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_32/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI i26_adj_28\/SLICE_73/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI i26_adj_28\/SLICE_73/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_79/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_92/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_92/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_92/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_99/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_14/Q0 SLICE_14/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_14/Q0 SLICE_14/C0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_14/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_76/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_82/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_85/B0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_86/B0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_89/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_98/M1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_105/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_14/F0 SLICE_14/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_14/F1 i26\/SLICE_71/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_18/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_95/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_103/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/F0 SLICE_18/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F0 SLICE_18/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_18/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_96/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_101/B1 (0:0:0)(0:0:0)) + (INTERCONNECT i26_adj_28\/SLICE_73/OFX0 SLICE_18/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/F0 SLICE_18/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/F0 SLICE_79/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F0 SLICE_18/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F1 SLICE_18/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/Q0 SLICE_83/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/Q0 SLICE_84/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/Q1 SLICE_19/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/Q1 SLICE_91/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/Q1 SLICE_100/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/Q0 SLICE_19/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/Q0 SLICE_100/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/Q0 SLICE_19/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/Q0 SLICE_100/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/F0 SLICE_19/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/F0 SLICE_19/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/F1 SLICE_67/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/F1 SLICE_87/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_23/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI i26\/SLICE_71/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI i26_adj_28\/SLICE_73/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_76/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_79/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_85/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_91/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_91/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_101/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_105/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_23/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_32/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_86/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_92/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_99/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23/F1 SLICE_23/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23/F1 SLICE_49/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23/F1 SLICE_84/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_23/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_49/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_76/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_83/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_85/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_86/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_91/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_101/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_105/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_105/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56/Q0 SLICE_23/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56/Q0 SLICE_32/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_23/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_49/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_86/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_88/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_89/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_93/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23/F0 SLICE_23/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/F0 SLICE_23/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23/Q0 SLICE_56/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_25/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_36/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_58/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_60/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_61/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_63/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_67/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 RCKEEN_I_0_445\/SLICE_70/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 i2099\/SLICE_72/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 i2099\/SLICE_72/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_80/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_104/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_25/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_34/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_35/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_35/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_58/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_60/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_63/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_65/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_65/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_66/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_68/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 RCKEEN_I_0_445\/SLICE_70/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_74/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_100/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_25/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_34/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_34/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_43/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_44/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_56/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_60/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_63/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_65/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_69/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_75/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_78/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_87/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_95/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_100/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_100/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_102/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_25/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_31/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_31/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_32/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_34/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_34/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_36/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_58/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_58/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_60/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_61/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_63/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 i2099\/SLICE_72/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 i2099\/SLICE_72/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_78/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_80/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_85/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_90/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_95/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_96/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_97/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_100/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_104/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F0 SLICE_25/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95/F1 SLICE_25/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_76/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_77/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_80/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_82/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_84/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_86/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_87/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_100/CE (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_26/C1 (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_78/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_83/M0 (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_85/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_90/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_95/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_96/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_97/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_98/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_26/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_58/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 RCKEEN_I_0_445\/SLICE_70/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 RCKEEN_I_0_445\/SLICE_70/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_74/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_74/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_103/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_26/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_49/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/F0 SLICE_26/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/F1 SLICE_26/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/F1 LED_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_31/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_58/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_66/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_66/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 RCKEEN_I_0_445\/SLICE_70/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 i2099\/SLICE_72/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_80/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q1 SLICE_31/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q1 SLICE_84/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q1 SLICE_102/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q1 SLICE_102/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63/F1 SLICE_31/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63/F1 SLICE_63/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_31/F0 SLICE_31/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/Q1 SLICE_31/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/Q1 SLICE_82/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/Q1 SLICE_102/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_31/Q0 RA\[10\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_31/F1 SLICE_61/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_49/Q0 SLICE_32/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32/F0 SLICE_32/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32/Q0 RA\[11\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32/F1 SLICE_83/B0 (0:0:0)(0:0:0)) + (INTERCONNECT RCKEEN_I_0_445\/SLICE_70/OFX0 SLICE_34/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_34/F0 SLICE_34/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/F1 SLICE_34/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/F1 SLICE_58/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/F1 SLICE_60/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_34/Q0 SLICE_35/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_34/F1 SLICE_60/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/Q0 SLICE_35/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/Q0 SLICE_60/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/Q0 RCKE_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q1 SLICE_35/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/Q0 SLICE_35/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/Q0 SLICE_74/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/F0 SLICE_35/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/Q0 SLICE_35/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/F1 SLICE_104/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/Q1 SLICE_67/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/Q1 SLICE_68/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/Q1 SLICE_74/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/F0 SLICE_36/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 SLICE_36/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/F1 SLICE_64/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/F1 SLICE_66/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/F1 SLICE_43/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/F1 SLICE_44/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/F1 SLICE_43/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/F1 SLICE_69/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/F1 SLICE_95/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43/F1 SLICE_43/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/Q0 SLICE_43/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43/F0 SLICE_43/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F0 SLICE_43/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F0 SLICE_44/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/F0 SLICE_43/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/F0 SLICE_44/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43/Q0 UFMCLK_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/F0 SLICE_44/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94/F1 SLICE_44/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94/F1 SLICE_75/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94/F1 SLICE_78/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/F1 SLICE_44/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/F1 SLICE_78/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/Q0 SLICE_44/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F1 SLICE_44/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/F0 SLICE_44/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/Q0 UFMSDI_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_49/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_81/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_86/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_88/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_89/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_49/F1 SLICE_49/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_49/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI i26\/SLICE_71/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI i26_adj_28\/SLICE_73/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI i26_adj_28\/SLICE_73/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_79/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_81/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_92/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_102/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_103/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_49/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI i26_adj_28\/SLICE_73/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI i26_adj_28\/SLICE_73/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_76/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_79/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_91/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_91/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_92/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_92/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_102/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_103/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_49/F0 SLICE_49/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/F1 SLICE_49/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/F1 SLICE_56/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/F1 SLICE_78/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/F1 SLICE_95/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56/F1 SLICE_56/D0 (0:0:0)(0:0:0)) + (INTERCONNECT UFMSDO_I/PADDI SLICE_56/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56/F0 SLICE_56/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/F0 SLICE_56/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/F0 SLICE_58/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_58/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 i2099\/SLICE_72/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_58/OFX0 SLICE_58/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_58/Q0 nRCAS_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60/F1 SLICE_60/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60/F1 SLICE_61/B1 (0:0:0)(0:0:0)) + (INTERCONNECT i2099\/SLICE_72/OFX0 SLICE_60/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60/F0 SLICE_60/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60/Q0 nRCS_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q0 SLICE_61/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q0 SLICE_63/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q0 i2099\/SLICE_72/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q0 i2099\/SLICE_72/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q0 SLICE_87/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q0 SLICE_102/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_61/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_64/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_65/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_65/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_66/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_66/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_80/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F1 SLICE_61/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61/Q0 SLICE_61/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61/Q0 nRRAS_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61/OFX0 SLICE_61/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F0 SLICE_63/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/F1 SLICE_63/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63/F0 SLICE_63/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F0 SLICE_63/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63/Q0 nRWE_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_64/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_64/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_93/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_93/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_96/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_97/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_98/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_98/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_99/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_99/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_101/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_101/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_103/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_64/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_90/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_93/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_93/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/Q1 SLICE_64/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/F0 SLICE_64/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F1 SLICE_64/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F1 SLICE_80/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F1 SLICE_104/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/F0 SLICE_64/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/F1 RA\[9\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/Q1 SLICE_65/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/Q1 SLICE_87/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_65/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_66/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_67/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_74/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_80/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_100/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/F0 SLICE_65/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/F1 SLICE_104/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/F0 SLICE_66/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/F0 SLICE_67/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/Q1 SLICE_67/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_67/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 nUFMCS_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/F0 RCKEEN_I_0_445\/SLICE_70/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/F1 SLICE_69/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/F0 SLICE_77/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q1 SLICE_74/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q1 SLICE_103/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94/F0 SLICE_69/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/F0 SLICE_69/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95/F0 SLICE_69/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 RCKEEN_I_0_445\/SLICE_70/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 RCKEEN_I_0_445\/SLICE_70/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 SLICE_74/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 SLICE_74/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 SLICE_103/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/F1 i26\/SLICE_71/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/F1 SLICE_83/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 i26\/SLICE_71/B0 (0:0:0)(0:0:0)) + (INTERCONNECT i26\/SLICE_71/OFX0 SLICE_105/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F0 SLICE_74/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F0 SLICE_104/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/F0 SLICE_75/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/F0 SLICE_87/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/F1 SLICE_75/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/F0 SLICE_76/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/F0 SLICE_83/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/F1 SLICE_76/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/F1 SLICE_91/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/Q0 SLICE_76/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/Q1 SLICE_76/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/F0 SLICE_77/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/Q0 SLICE_77/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/Q1 SLICE_77/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/F1 SLICE_87/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/Q1 SLICE_80/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_78/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_96/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_99/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_78/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_97/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_101/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/Q0 SLICE_101/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/Q1 SLICE_99/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_79/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/F0 SLICE_79/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/Q1 SLICE_79/M1 (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_79/M0 (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_89/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_92/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_98/M0 (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_103/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_105/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_105/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/Q0 SLICE_80/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/Q1 SLICE_81/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/Q0 SLICE_81/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/Q1 SLICE_81/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F1 SLICE_81/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/F0 SLICE_81/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/Q0 SLICE_81/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/F1 SLICE_81/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/F1 SLICE_93/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F0 SLICE_82/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F0 SLICE_82/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F0 SLICE_83/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/Q0 SLICE_82/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/F0 SLICE_84/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F0 SLICE_84/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F0 SLICE_85/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/Q0 SLICE_84/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/Q1 SLICE_100/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F0 SLICE_85/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/F1 SLICE_85/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/F1 SLICE_86/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/F1 SLICE_105/A0 (0:0:0)(0:0:0)) + (INTERCONNECT CROW\[1\]_I/PADDI SLICE_85/M1 (0:0:0)(0:0:0)) + (INTERCONNECT CROW\[0\]_I/PADDI SLICE_85/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/Q0 RBA\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/Q1 RBA\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/Q0 SLICE_86/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/Q1 SLICE_86/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/F1 SLICE_87/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F0 SLICE_88/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/Q0 SLICE_97/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/Q1 SLICE_96/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/Q0 RD\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/Q1 RD\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[8\]_I/PADDI SLICE_90/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[8\]_I/PADDI SLICE_98/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/Q0 SLICE_98/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/Q0 RD\[6\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/Q1 RD\[7\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/F0 RDQMH_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/F1 RDQML_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_95/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_97/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_97/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95/Q0 SLICE_97/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95/Q1 SLICE_103/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_96/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_96/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_96/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/Q1 SLICE_96/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/Q0 SLICE_96/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/Q0 SLICE_101/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/F1 RA\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/Q1 SLICE_97/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/Q0 SLICE_98/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/F1 RA\[4\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/Q1 SLICE_99/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/F0 RA\[8\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/F1 RA\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/F0 RA\[7\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/F1 RA\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/Q0 SLICE_100/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/F0 RA\[6\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/F1 RA\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/Q0 RD\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/F1 RA\[5\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/Q1 RD\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/Q0 RD\[4\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 RD\[7\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 RD\[6\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 RD\[5\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 RD\[4\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 RD\[3\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 RD\[2\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 RD\[1\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 RD\[0\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/Q1 RD\[5\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (0:0:0)(0:0:0)) + ) + ) + ) +) diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.vo b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.vo new file mode 100644 index 0000000..d68e04c --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.vo @@ -0,0 +1,3678 @@ + +// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 + +// ldbanno -n Verilog -o RAM2GS_LCMXO256C_impl1_mapvo.vo -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd +// Netlist created on Tue Aug 15 05:03:20 2023 +// Netlist written on Tue Aug 15 05:03:22 2023 +// Design is for device LCMXO256C +// Design is for package TQFP100 +// Design is for performance grade 3 + +`timescale 1 ns / 1 ps + +module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, + RD, nRCS, RCLK, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, + UFMCLK, UFMSDI, UFMSDO ); + input PHI2; + input [9:0] MAin; + input [1:0] CROW; + input [7:0] Din; + input nCCAS, nCRAS, nFWE, RCLK, UFMSDO; + output [7:0] Dout; + output LED; + output [1:0] RBA; + output [11:0] RA; + output nRCS, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI; + inout [7:0] RD; + wire FS_7, FS_6, RCLK_c, n2010, n2011, FS_15, FS_14, n2014, n2015, FS_5, + FS_4, n2009, FS_13, FS_12, n2013, FS_1, FS_0, n2008, FS_11, FS_10, + n2012, FS_3, FS_2, FS_9, FS_8, FS_17, FS_16, MAin_c_1, n1326, + MAin_c_0, n2263, ADSubmitted, n2242, n2459, n1413, C1Submitted_N_237, + PHI2_c, Din_c_6, C1Submitted, nFWE_c, n6_adj_3, n2284, MAin_c_5, + n2316, n26, MAin_c_2, n15, n2463, CmdEnable_N_248, + PHI2_N_120_enable_7, CmdEnable, PHI2r2, CmdSubmitted, PHI2r3, + \n2568\001/BUF1 , PHI2_N_120_enable_5, n2472, Din_c_5, Din_c_7, n1314, + Din_c_4, n8MEGEN, Din_c_0, Cmdn8MEGEN_N_264, PHI2_N_120_enable_4, + Cmdn8MEGEN, nRowColSel_N_35, RASr2, InitReady, Ready, + \n2568\000/BUF1 , RCLK_c_enable_25, RCLK_c_enable_23, nCRAS_c, CBR, + LEDEN, n2568, RCLK_c_enable_12, LED_N_84, nRowColSel_N_34, + nRCAS_N_165, n2208, n2209, nRWE_N_177, RA_0, n56, XOR8MEG, RA11_N_184, + RA_c, n2478, RCKEEN_N_122, RCKEEN_N_121, RCLK_c_enable_4, RCKEEN, + n2467, RCKE_c, RASr3, RASr, RCKE_N_132, CASr, nRWE_N_182, CASr2, + \n2568\002/BUF1 , Ready_N_292, n2469, n2462, n62, n1160, CmdUFMCLK, + UFMCLK_N_224, RCLK_c_enable_24, n1846, UFMCLK_c, n2470, n2272, n2471, + CmdUFMSDI, n2461, UFMSDI_N_231, UFMSDI_c, Din_c_1, n2324, Din_c_2, + Din_c_3, XOR8MEG_N_110, PHI2_N_120_enable_1, n2464, n1325, UFMSDO_c, + n8MEGEN_N_91, RCLK_c_enable_11, n2427, n15_adj_1, nRCAS_N_161, + nRCAS_c, n13, n2481, nRCS_N_136, nRCS_c, nRCS_N_139, nRowColSel_N_32, + n6, nRRAS_c, n2138, nRWE_N_178, n33, nRWE_N_171, RCLK_c_enable_3, + nRWE_c, nRowColSel, MAin_c_9, RowA_9, nRowColSel_N_28, n1502, n1410, + RA_1_9, Ready_N_296, nRowColSel_N_33, n1503, n2414, n1093, CmdUFMCS, + nUFMCS_c, n11, n1417, n2322, CASr3, n12, n2164, LEDEN_N_82, FWEr, + n2476, n2475, n13_adj_2, n1, n2214, n2328, n10, n2458, n732, n733, + n2290, n728, n729, n8, n727, MAin_c_7, MAin_c_6, RowA_6, RowA_7, + n2468, n1280, PHI2r, nCCAS_c, n726, Bank_3, Bank_6, Bank_5, n2278, + n2314, Bank_2, PHI2_N_120_enable_6, n14, n2460, n730, n2262, n2473, + n738, n737, n2474, n2253, CROW_c_1, CROW_c_0, RBA_c_0, RBA_c_1, n734, + n735, n7, n2451, Bank_0, Bank_1, WRD_0, WRD_1, MAin_c_8, RowA_8, + WRD_6, WRD_7, RDQMH_c, RDQML_c, MAin_c_4, RowA_4, RowA_5, MAin_c_3, + RowA_3, Bank_4, RowA_2, RA_1_3, Bank_7, RowA_0, RA_1_4, RowA_1, + RA_1_8, RA_1_0, RA_1_7, RA_1_1, n736, RA_1_6, RA_1_2, WRD_2, RA_1_5, + WRD_3, WRD_4, n984, WRD_5, Dout_c, Dout_0, Dout_1, Dout_2, Dout_3, + Dout_4, Dout_5, Dout_6, VCCI, GNDI_TSALL; + + SLICE_0 SLICE_0( .A1(FS_7), .A0(FS_6), .CLK(RCLK_c), .FCI(n2010), .Q0(FS_6), + .Q1(FS_7), .FCO(n2011)); + SLICE_1 SLICE_1( .A1(FS_15), .A0(FS_14), .CLK(RCLK_c), .FCI(n2014), + .Q0(FS_14), .Q1(FS_15), .FCO(n2015)); + SLICE_2 SLICE_2( .A1(FS_5), .A0(FS_4), .CLK(RCLK_c), .FCI(n2009), .Q0(FS_4), + .Q1(FS_5), .FCO(n2010)); + SLICE_3 SLICE_3( .A1(FS_13), .A0(FS_12), .CLK(RCLK_c), .FCI(n2013), + .Q0(FS_12), .Q1(FS_13), .FCO(n2014)); + SLICE_4 SLICE_4( .A1(FS_1), .A0(FS_0), .CLK(RCLK_c), .Q0(FS_0), .Q1(FS_1), + .FCO(n2008)); + SLICE_5 SLICE_5( .A1(FS_11), .A0(FS_10), .CLK(RCLK_c), .FCI(n2012), + .Q0(FS_10), .Q1(FS_11), .FCO(n2013)); + SLICE_6 SLICE_6( .A1(FS_3), .A0(FS_2), .CLK(RCLK_c), .FCI(n2008), .Q0(FS_2), + .Q1(FS_3), .FCO(n2009)); + SLICE_7 SLICE_7( .A1(FS_9), .A0(FS_8), .CLK(RCLK_c), .FCI(n2011), .Q0(FS_8), + .Q1(FS_9), .FCO(n2012)); + SLICE_8 SLICE_8( .A1(FS_17), .A0(FS_16), .CLK(RCLK_c), .FCI(n2015), + .Q0(FS_16), .Q1(FS_17)); + SLICE_9 SLICE_9( .C1(MAin_c_1), .B1(n1326), .A1(MAin_c_0), .D0(n2263), + .C0(ADSubmitted), .B0(n2242), .A0(n2459), .DI0(n1413), + .LSR(C1Submitted_N_237), .CLK(PHI2_c), .F0(n1413), .Q0(ADSubmitted), + .F1(n2263)); + SLICE_14 SLICE_14( .B1(Din_c_6), .A1(C1Submitted), .D0(MAin_c_1), + .C0(C1Submitted), .B0(n1326), .A0(nFWE_c), .DI0(n6_adj_3), + .LSR(C1Submitted_N_237), .CLK(PHI2_c), .F0(n6_adj_3), .Q0(C1Submitted), + .F1(n2284)); + SLICE_18 SLICE_18( .D1(MAin_c_5), .C1(n2316), .B1(n26), .A1(MAin_c_2), + .D0(n15), .C0(n1326), .B0(n2463), .A0(MAin_c_1), .DI0(CmdEnable_N_248), + .CE(PHI2_N_120_enable_7), .CLK(PHI2_c), .F0(CmdEnable_N_248), + .Q0(CmdEnable), .F1(n1326)); + SLICE_19 SLICE_19( .C1(PHI2r2), .B1(CmdSubmitted), .A1(PHI2r3), + .DI0(\n2568\001/BUF1 ), .CE(PHI2_N_120_enable_5), .CLK(PHI2_c), + .F0(\n2568\001/BUF1 ), .Q0(CmdSubmitted), .F1(n2472)); + SLICE_23 SLICE_23( .C1(Din_c_5), .B1(Din_c_7), .A1(Din_c_6), .D0(n1314), + .C0(Din_c_4), .B0(n8MEGEN), .A0(Din_c_0), .DI0(Cmdn8MEGEN_N_264), + .CE(PHI2_N_120_enable_4), .CLK(PHI2_c), .F0(Cmdn8MEGEN_N_264), + .Q0(Cmdn8MEGEN), .F1(n1314)); + SLICE_25 SLICE_25( .D1(nRowColSel_N_35), .C1(RASr2), .B1(InitReady), + .A1(Ready), .DI0(\n2568\000/BUF1 ), .CE(RCLK_c_enable_25), .CLK(RCLK_c), + .F0(\n2568\000/BUF1 ), .Q0(InitReady), .F1(RCLK_c_enable_23)); + SLICE_26 SLICE_26( .C1(nCRAS_c), .B1(CBR), .A1(LEDEN), .DI0(n2568), + .CE(RCLK_c_enable_12), .CLK(RCLK_c), .F0(n2568), .Q0(LEDEN), .F1(LED_N_84)); + SLICE_31 SLICE_31( .B1(nRowColSel_N_34), .A1(Ready), .C0(nRCAS_N_165), + .B0(Ready), .A0(n2208), .DI0(n2209), .LSR(nRWE_N_177), .CLK(RCLK_c), + .F0(n2209), .Q0(RA_0), .F1(n56)); + SLICE_32 SLICE_32( .B1(Din_c_7), .A1(Din_c_6), .C0(n8MEGEN), .B0(XOR8MEG), + .A0(Din_c_6), .DI0(RA11_N_184), .LSR(Ready), .CLK(PHI2_c), .F0(RA11_N_184), + .Q0(RA_c), .F1(n2478)); + SLICE_34 SLICE_34( .C1(Ready), .B1(InitReady), .A1(RASr2), .C0(Ready), + .B0(RCKEEN_N_122), .A0(InitReady), .DI0(RCKEEN_N_121), + .CE(RCLK_c_enable_4), .CLK(RCLK_c), .F0(RCKEEN_N_121), .Q0(RCKEEN), + .F1(n2467)); + SLICE_35 SLICE_35( .B1(RCKE_c), .A1(RASr2), .D0(RASr3), .C0(RASr2), + .B0(RCKEEN), .A0(RASr), .DI0(RCKE_N_132), .M1(CASr), .CLK(RCLK_c), + .F0(RCKE_N_132), .Q0(RCKE_c), .F1(nRWE_N_182), .Q1(CASr2)); + SLICE_36 SLICE_36( .B1(nRowColSel_N_35), .A1(Ready), .DI0(\n2568\002/BUF1 ), + .CE(Ready_N_292), .CLK(RCLK_c), .F0(\n2568\002/BUF1 ), .Q0(Ready), + .F1(n2469)); + SLICE_43 SLICE_43( .D1(FS_1), .C1(n2462), .B1(n62), .A1(FS_4), + .C0(InitReady), .B0(n1160), .A0(CmdUFMCLK), .DI0(UFMCLK_N_224), + .CE(RCLK_c_enable_24), .LSR(n1846), .CLK(RCLK_c), .F0(UFMCLK_N_224), + .Q0(UFMCLK_c), .F1(n1160)); + SLICE_44 SLICE_44( .D1(FS_11), .C1(n2470), .B1(n2272), .A1(n2471), + .D0(CmdUFMSDI), .C0(InitReady), .B0(n2462), .A0(n2461), .DI0(UFMSDI_N_231), + .CE(RCLK_c_enable_24), .LSR(n1846), .CLK(RCLK_c), .F0(UFMSDI_N_231), + .Q0(UFMSDI_c), .F1(n2462)); + SLICE_49 SLICE_49( .D1(Din_c_1), .C1(n1314), .B1(LEDEN), .A1(Din_c_4), + .D0(n2324), .C0(Din_c_2), .B0(Din_c_3), .A0(Din_c_0), .DI0(XOR8MEG_N_110), + .CE(PHI2_N_120_enable_1), .CLK(PHI2_c), .F0(XOR8MEG_N_110), .Q0(XOR8MEG), + .F1(n2324)); + SLICE_56 SLICE_56( .C1(FS_10), .B1(n2464), .A1(FS_11), .D0(n1325), + .C0(InitReady), .B0(Cmdn8MEGEN), .A0(UFMSDO_c), .DI0(n8MEGEN_N_91), + .CE(RCLK_c_enable_11), .CLK(RCLK_c), .F0(n8MEGEN_N_91), .Q0(n8MEGEN), + .F1(n1325)); + SLICE_58 SLICE_58( .D1(n2427), .C1(RASr2), .B1(CBR), .A1(Ready), .C0(Ready), + .B0(n15_adj_1), .A0(nRowColSel_N_34), .DI0(nRCAS_N_161), + .M0(nRowColSel_N_35), .CE(RCLK_c_enable_4), .CLK(RCLK_c), + .OFX0(nRCAS_N_161), .Q0(nRCAS_c)); + SLICE_60 SLICE_60( .D1(Ready), .C1(RCKE_c), .B1(InitReady), .A1(RASr2), + .D0(nRowColSel_N_35), .C0(n13), .B0(n2481), .A0(n2467), .DI0(nRCS_N_136), + .CE(RCLK_c_enable_4), .CLK(RCLK_c), .F0(nRCS_N_136), .Q0(nRCS_c), .F1(n13)); + SLICE_61 SLICE_61( .C1(nRCS_N_139), .B1(n13), .A1(Ready), + .D0(nRowColSel_N_32), .C0(n6), .B0(nRRAS_c), .A0(n56), .DI0(n2138), + .M0(nRowColSel_N_35), .CLK(RCLK_c), .OFX0(n2138), .Q0(nRRAS_c)); + SLICE_63 SLICE_63( .D1(nRCS_N_139), .C1(InitReady), .B1(RASr2), + .A1(nRowColSel_N_35), .D0(n2208), .C0(Ready), .B0(nRWE_N_178), .A0(n33), + .DI0(nRWE_N_171), .CE(RCLK_c_enable_3), .CLK(RCLK_c), .F0(nRWE_N_171), + .Q0(nRWE_c), .F1(n2208)); + SLICE_64 SLICE_64( .C1(nRowColSel), .B1(MAin_c_9), .A1(RowA_9), + .D0(nRowColSel_N_32), .C0(nRowColSel_N_28), .B0(n1502), .A0(nRowColSel), + .DI0(n1410), .LSR(n2469), .CLK(RCLK_c), .F0(n1410), .Q0(nRowColSel), + .F1(RA_1_9)); + SLICE_65 SLICE_65( .D1(InitReady), .C1(Ready_N_296), .B1(RASr2), + .A1(nRowColSel_N_32), .B0(nRowColSel_N_33), .A0(nRowColSel_N_32), + .DI0(n1503), .LSR(RASr2), .CLK(RCLK_c), .F0(n1503), .Q0(nRowColSel_N_32), + .F1(n2414)); + SLICE_66 SLICE_66( .D1(nRowColSel_N_33), .C1(nRowColSel_N_34), .B1(n2469), + .A1(nRowColSel_N_32), .B0(RASr2), .A0(nRowColSel_N_32), .DI0(n1093), + .LSR(nRowColSel_N_34), .CLK(RCLK_c), .F0(n1093), .Q0(nRowColSel_N_33), + .F1(RCLK_c_enable_4)); + SLICE_67 SLICE_67( .C1(n2472), .B1(CmdUFMCS), .A1(nUFMCS_c), .B0(CASr2), + .A0(nRowColSel_N_33), .M0(n1093), .LSR(nRowColSel_N_35), .CLK(RCLK_c), + .F0(n11), .Q0(nRowColSel_N_34), .F1(n1417)); + SLICE_68 SLICE_68( .B1(FS_12), .A1(FS_17), .D0(FS_3), .C0(FS_6), .B0(FS_1), + .A0(FS_0), .M1(CASr2), .M0(RASr2), .CLK(RCLK_c), .F0(n2322), + .Q0(nRowColSel_N_35), .F1(n2471), .Q1(CASr3)); + SLICE_69 SLICE_69( .D1(FS_14), .C1(FS_12), .B1(n12), .A1(FS_17), + .C0(InitReady), .B0(n1417), .A0(n62), .DI0(n2164), .LSR(LEDEN_N_82), + .CLK(RCLK_c), .F0(n2164), .Q0(nUFMCS_c), .F1(n62)); + RCKEEN_I_0_445_SLICE_70 \RCKEEN_I_0_445/SLICE_70 ( .C1(RASr2), .B1(FWEr), + .A1(CBR), .D0(nRowColSel_N_34), .C0(FWEr), .B0(n11), .A0(CBR), + .M0(nRowColSel_N_35), .OFX0(RCKEEN_N_122)); + i26_SLICE_71 \i26/SLICE_71 ( .D1(n2284), .C1(n2476), .B1(MAin_c_1), + .A1(MAin_c_0), .D0(ADSubmitted), .C0(MAin_c_0), .B0(n2475), .A0(Din_c_5), + .M0(Din_c_2), .OFX0(n13_adj_2)); + i2099_SLICE_72 \i2099/SLICE_72 ( .D1(nRowColSel_N_34), .C1(nRowColSel_N_35), + .B1(Ready), .A1(nRCS_N_139), .C0(nRowColSel_N_35), .B0(Ready), + .A0(nRCS_N_139), .M0(n15_adj_1), .OFX0(n2481)); + i26_adj_28_SLICE_73 \i26_adj_28/SLICE_73 ( .D1(MAin_c_0), .C1(Din_c_2), + .B1(Din_c_3), .A1(Din_c_6), .D0(MAin_c_0), .C0(Din_c_2), .B0(Din_c_3), + .A0(Din_c_6), .M0(Din_c_5), .OFX0(n15)); + SLICE_74 SLICE_74( .D1(n1), .C1(nRowColSel_N_33), .B1(CBR), .A1(FWEr), + .D0(CASr3), .C0(CASr2), .B0(FWEr), .A0(CBR), .M1(RASr2), .M0(RASr), + .CLK(RCLK_c), .F0(n1), .Q0(RASr2), .F1(n15_adj_1), .Q1(RASr3)); + SLICE_75 SLICE_75( .C1(InitReady), .B1(FS_11), .A1(n2214), .D0(FS_11), + .C0(n2272), .B0(n2328), .A0(FS_10), .F0(n2214), .F1(RCLK_c_enable_12)); + SLICE_76 SLICE_76( .D1(MAin_c_0), .C1(n10), .B1(n1326), .A1(nFWE_c), + .D0(n2458), .C0(Din_c_4), .B0(Din_c_5), .A0(Din_c_3), .M1(n732), .M0(n733), + .CE(RCLK_c_enable_23), .CLK(RCLK_c), .F0(PHI2_N_120_enable_4), .Q0(n732), + .F1(n2458), .Q1(nRWE_N_177)); + SLICE_77 SLICE_77( .D1(FS_7), .C1(n2322), .B1(FS_4), .A1(n2290), .C0(FS_9), + .B0(FS_5), .A0(FS_2), .M1(n728), .M0(n729), .CE(RCLK_c_enable_23), + .CLK(RCLK_c), .F0(n2290), .Q0(n728), .F1(n8), .Q1(n727)); + SLICE_78 SLICE_78( .D1(n2471), .C1(n2272), .B1(FS_14), .A1(FS_16), + .C0(InitReady), .B0(n2464), .A0(FS_11), .M1(MAin_c_7), .M0(MAin_c_6), + .LSR(Ready), .CLK(nCRAS_c), .F0(n1846), .Q0(RowA_6), .F1(n2464), + .Q1(RowA_7)); + SLICE_79 SLICE_79( .C1(Din_c_5), .B1(Din_c_3), .A1(Din_c_6), .D0(n2468), + .C0(n1280), .B0(n2463), .A0(Din_c_2), .M1(PHI2r), .M0(nCCAS_c), + .CLK(RCLK_c), .F0(C1Submitted_N_237), .Q0(CASr), .F1(n2468), .Q1(PHI2r2)); + SLICE_80 SLICE_80( .B1(nRowColSel_N_33), .A1(nRowColSel_N_34), + .D0(nRowColSel_N_35), .C0(n1502), .B0(nRowColSel_N_32), .A0(Ready), + .M1(n726), .M0(n727), .CE(RCLK_c_enable_23), .CLK(RCLK_c), + .F0(RCLK_c_enable_3), .Q0(n726), .F1(n1502), .Q1(Ready_N_296)); + SLICE_81 SLICE_81( .B1(Bank_3), .A1(Bank_6), .D0(Bank_5), .C0(n2278), + .B0(n2314), .A0(Bank_2), .M1(Din_c_2), .M0(Din_c_1), + .CE(PHI2_N_120_enable_6), .CLK(PHI2_c), .F0(n26), .Q0(CmdUFMCLK), + .F1(n2278), .Q1(CmdUFMCS)); + SLICE_82 SLICE_82( .D1(MAin_c_1), .C1(n14), .B1(n2460), .A1(MAin_c_0), + .B0(n1326), .A0(nFWE_c), .M1(n730), .M0(nRWE_N_177), .CE(RCLK_c_enable_23), + .CLK(RCLK_c), .F0(n2460), .Q0(n730), .F1(PHI2_N_120_enable_7), .Q1(n729)); + SLICE_83 SLICE_83( .D1(n2476), .C1(n2460), .B1(n10), .A1(MAin_c_0), + .D0(MAin_c_1), .C0(CmdEnable), .B0(n2478), .A0(Din_c_4), .M0(nCRAS_c), + .CLK(RCLK_c), .F0(n10), .Q0(RASr), .F1(PHI2_N_120_enable_6)); + SLICE_84 SLICE_84( .D1(n1314), .C1(n2262), .B1(CmdEnable), .A1(n2473), + .C0(MAin_c_1), .B0(n1326), .A0(MAin_c_0), .M1(n738), .M0(nRCAS_N_165), + .CE(RCLK_c_enable_23), .CLK(RCLK_c), .F0(n2262), .Q0(n738), + .F1(PHI2_N_120_enable_1), .Q1(n737)); + SLICE_85 SLICE_85( .D1(n2474), .C1(Din_c_5), .B1(n2253), .A1(n2473), + .B0(nFWE_c), .A0(Din_c_4), .M1(CROW_c_1), .M0(CROW_c_0), .LSR(Ready), + .CLK(nCRAS_c), .F0(n2473), .Q0(RBA_c_0), .F1(n2242), .Q1(RBA_c_1)); + SLICE_86 SLICE_86( .C1(Din_c_1), .B1(Din_c_0), .A1(Din_c_7), .C0(n2253), + .B0(nFWE_c), .A0(Din_c_4), .M1(n734), .M0(n735), .CE(RCLK_c_enable_23), + .CLK(RCLK_c), .F0(n2463), .Q0(n734), .F1(n2253), .Q1(n733)); + SLICE_87 SLICE_87( .B1(n2214), .A1(FS_8), .D0(n8), .C0(InitReady), + .B0(n2472), .A0(n7), .M1(nRCS_N_139), .M0(Ready_N_296), + .CE(RCLK_c_enable_23), .CLK(RCLK_c), .F0(RCLK_c_enable_11), + .Q0(nRCS_N_139), .F1(n7), .Q1(nRCAS_N_165)); + SLICE_88 SLICE_88( .C1(FS_10), .B1(FS_6), .A1(n2451), .D0(FS_8), .C0(FS_5), + .B0(FS_9), .A0(FS_7), .M1(Din_c_1), .M0(Din_c_0), .CLK(PHI2_c), .F0(n2451), + .Q0(Bank_0), .F1(n2461), .Q1(Bank_1)); + SLICE_89 SLICE_89( .C1(MAin_c_1), .B1(n1326), .A1(nFWE_c), .C0(MAin_c_0), + .B0(n1326), .A0(MAin_c_1), .M1(Din_c_1), .M0(Din_c_0), .CLK(nCCAS_c), + .F0(n1280), .Q0(WRD_0), .F1(n2459), .Q1(WRD_1)); + SLICE_90 SLICE_90( .D1(FS_16), .C1(FS_14), .B1(FS_12), .A1(FS_17), + .B0(FS_14), .A0(FS_16), .M1(MAin_c_9), .M0(MAin_c_8), .LSR(Ready), + .CLK(nCRAS_c), .F0(n2470), .Q0(RowA_8), .F1(n2328), .Q1(RowA_9)); + SLICE_91 SLICE_91( .B1(Din_c_5), .A1(Din_c_3), .D0(n2458), .C0(Din_c_5), + .B0(Din_c_4), .A0(Din_c_3), .M1(PHI2_c), .M0(PHI2r2), .CLK(RCLK_c), + .F0(PHI2_N_120_enable_5), .Q0(PHI2r3), .F1(n2476), .Q1(PHI2r)); + SLICE_92 SLICE_92( .B1(Din_c_3), .A1(Din_c_6), .C0(Din_c_3), .B0(Din_c_2), + .A0(Din_c_6), .M1(Din_c_7), .M0(Din_c_6), .CLK(nCCAS_c), .F0(n2474), + .Q0(WRD_6), .F1(n2475), .Q1(WRD_7)); + SLICE_93 SLICE_93( .B1(nRowColSel), .A1(MAin_c_9), .B0(nRowColSel), + .A0(MAin_c_9), .M0(Din_c_0), .CE(PHI2_N_120_enable_6), .CLK(PHI2_c), + .F0(RDQMH_c), .Q0(CmdUFMSDI), .F1(RDQML_c)); + SLICE_94 SLICE_94( .B1(FS_15), .A1(FS_13), .D0(FS_11), .C0(FS_16), + .B0(FS_13), .A0(FS_15), .F0(n12), .F1(n2272)); + SLICE_95 SLICE_95( .B1(FS_10), .A1(n62), .D0(InitReady), .C0(FS_10), + .B0(n2464), .A0(FS_11), .M1(MAin_c_5), .M0(MAin_c_4), .LSR(Ready), + .CLK(nCRAS_c), .F0(LEDEN_N_82), .Q0(RowA_4), .F1(RCLK_c_enable_25), + .Q1(RowA_5)); + SLICE_96 SLICE_96( .C1(nRowColSel), .B1(MAin_c_3), .A1(RowA_3), .D0(Bank_1), + .C0(Bank_4), .B0(MAin_c_3), .A0(MAin_c_7), .M1(MAin_c_3), .M0(MAin_c_2), + .LSR(Ready), .CLK(nCRAS_c), .F0(n2316), .Q0(RowA_2), .F1(RA_1_3), + .Q1(RowA_3)); + SLICE_97 SLICE_97( .C1(nRowColSel), .B1(MAin_c_4), .A1(RowA_4), .D0(Bank_0), + .C0(Bank_7), .B0(MAin_c_4), .A0(MAin_c_6), .M1(MAin_c_1), .M0(MAin_c_0), + .LSR(Ready), .CLK(nCRAS_c), .F0(n2314), .Q0(RowA_0), .F1(RA_1_4), + .Q1(RowA_1)); + SLICE_98 SLICE_98( .C1(nRowColSel), .B1(MAin_c_0), .A1(RowA_0), + .C0(nRowColSel), .B0(MAin_c_8), .A0(RowA_8), .M1(nFWE_c), .M0(nCCAS_c), + .CLK(nCRAS_c), .F0(RA_1_8), .Q0(CBR), .F1(RA_1_0), .Q1(FWEr)); + SLICE_99 SLICE_99( .C1(nRowColSel), .B1(MAin_c_1), .A1(RowA_1), + .C0(nRowColSel), .B0(MAin_c_7), .A0(RowA_7), .M1(Din_c_7), .M0(Din_c_6), + .CLK(PHI2_c), .F0(RA_1_7), .Q0(Bank_6), .F1(RA_1_1), .Q1(Bank_7)); + SLICE_100 SLICE_100( .D1(Ready), .C1(nRowColSel_N_33), .B1(InitReady), + .A1(RASr2), .D0(InitReady), .C0(PHI2r2), .B0(CmdSubmitted), .A0(PHI2r3), + .M1(n736), .M0(n737), .CE(RCLK_c_enable_23), .CLK(RCLK_c), + .F0(RCLK_c_enable_24), .Q0(n736), .F1(n6), .Q1(n735)); + SLICE_101 SLICE_101( .C1(nRowColSel), .B1(MAin_c_2), .A1(RowA_2), + .C0(nRowColSel), .B0(MAin_c_6), .A0(RowA_6), .M1(Din_c_5), .M0(Din_c_4), + .CLK(PHI2_c), .F0(RA_1_6), .Q0(Bank_4), .F1(RA_1_2), .Q1(Bank_5)); + SLICE_102 SLICE_102( .B1(nRWE_N_177), .A1(nRCAS_N_165), .C0(nRCAS_N_165), + .B0(nRCS_N_139), .A0(InitReady), .M1(Din_c_3), .M0(Din_c_2), .CLK(PHI2_c), + .F0(n2427), .Q0(Bank_2), .F1(n33), .Q1(Bank_3)); + SLICE_103 SLICE_103( .C1(nRowColSel), .B1(MAin_c_5), .A1(RowA_5), .C0(CBR), + .B0(CASr3), .A0(FWEr), .M1(Din_c_3), .M0(Din_c_2), .CLK(nCCAS_c), + .F0(nRowColSel_N_28), .Q0(WRD_2), .F1(RA_1_5), .Q1(WRD_3)); + SLICE_104 SLICE_104( .B1(Ready), .A1(n2414), .D0(nRowColSel_N_35), + .C0(nRWE_N_182), .B0(n1502), .A0(n1), .F0(nRWE_N_178), .F1(Ready_N_292)); + SLICE_105 SLICE_105( .B1(nFWE_c), .A1(nCCAS_c), .C0(n13_adj_2), .B0(Din_c_4), + .A0(n2253), .M1(Din_c_5), .M0(Din_c_4), .CLK(nCCAS_c), .F0(n14), + .Q0(WRD_4), .F1(n984), .Q1(WRD_5)); + RD_7_ \RD[7]_I ( .PADDI(Dout_c), .PADDT(n984), .PADDO(WRD_7), .RD7(RD[7])); + RD_6_ \RD[6]_I ( .PADDI(Dout_0), .PADDT(n984), .PADDO(WRD_6), .RD6(RD[6])); + RD_5_ \RD[5]_I ( .PADDI(Dout_1), .PADDT(n984), .PADDO(WRD_5), .RD5(RD[5])); + RD_4_ \RD[4]_I ( .PADDI(Dout_2), .PADDT(n984), .PADDO(WRD_4), .RD4(RD[4])); + RD_3_ \RD[3]_I ( .PADDI(Dout_3), .PADDT(n984), .PADDO(WRD_3), .RD3(RD[3])); + RD_2_ \RD[2]_I ( .PADDI(Dout_4), .PADDT(n984), .PADDO(WRD_2), .RD2(RD[2])); + RD_1_ \RD[1]_I ( .PADDI(Dout_5), .PADDT(n984), .PADDO(WRD_1), .RD1(RD[1])); + RD_0_ \RD[0]_I ( .PADDI(Dout_6), .PADDT(n984), .PADDO(WRD_0), .RD0(RD[0])); + Dout_7_ \Dout[7]_I ( .PADDO(Dout_c), .Dout7(Dout[7])); + Dout_6_ \Dout[6]_I ( .PADDO(Dout_0), .Dout6(Dout[6])); + Dout_5_ \Dout[5]_I ( .PADDO(Dout_1), .Dout5(Dout[5])); + Dout_4_ \Dout[4]_I ( .PADDO(Dout_2), .Dout4(Dout[4])); + Dout_3_ \Dout[3]_I ( .PADDO(Dout_3), .Dout3(Dout[3])); + Dout_2_ \Dout[2]_I ( .PADDO(Dout_4), .Dout2(Dout[2])); + Dout_1_ \Dout[1]_I ( .PADDO(Dout_5), .Dout1(Dout[1])); + Dout_0_ \Dout[0]_I ( .PADDO(Dout_6), .Dout0(Dout[0])); + LED LED_I( .PADDO(LED_N_84), .LED(LED)); + RBA_1_ \RBA[1]_I ( .PADDO(RBA_c_1), .RBA1(RBA[1])); + RBA_0_ \RBA[0]_I ( .PADDO(RBA_c_0), .RBA0(RBA[0])); + RA_11_ \RA[11]_I ( .PADDO(RA_c), .RA11(RA[11])); + RA_10_ \RA[10]_I ( .PADDO(RA_0), .RA10(RA[10])); + RA_9_ \RA[9]_I ( .PADDO(RA_1_9), .RA9(RA[9])); + RA_8_ \RA[8]_I ( .PADDO(RA_1_8), .RA8(RA[8])); + RA_7_ \RA[7]_I ( .PADDO(RA_1_7), .RA7(RA[7])); + RA_6_ \RA[6]_I ( .PADDO(RA_1_6), .RA6(RA[6])); + RA_5_ \RA[5]_I ( .PADDO(RA_1_5), .RA5(RA[5])); + RA_4_ \RA[4]_I ( .PADDO(RA_1_4), .RA4(RA[4])); + RA_3_ \RA[3]_I ( .PADDO(RA_1_3), .RA3(RA[3])); + RA_2_ \RA[2]_I ( .PADDO(RA_1_2), .RA2(RA[2])); + RA_1_ \RA[1]_I ( .PADDO(RA_1_1), .RA1(RA[1])); + RA_0_ \RA[0]_I ( .PADDO(RA_1_0), .RA0(RA[0])); + nRCS nRCS_I( .PADDO(nRCS_c), .nRCS(nRCS)); + RCKE RCKE_I( .PADDO(RCKE_c), .RCKE(RCKE)); + nRWE nRWE_I( .PADDO(nRWE_c), .nRWE(nRWE)); + nRRAS nRRAS_I( .PADDO(nRRAS_c), .nRRAS(nRRAS)); + nRCAS nRCAS_I( .PADDO(nRCAS_c), .nRCAS(nRCAS)); + RDQMH RDQMH_I( .PADDO(RDQMH_c), .RDQMH(RDQMH)); + RDQML RDQML_I( .PADDO(RDQML_c), .RDQML(RDQML)); + nUFMCS nUFMCS_I( .PADDO(nUFMCS_c), .nUFMCS(nUFMCS)); + UFMCLK UFMCLK_I( .PADDO(UFMCLK_c), .UFMCLK(UFMCLK)); + UFMSDI UFMSDI_I( .PADDO(UFMSDI_c), .UFMSDI(UFMSDI)); + PHI2 PHI2_I( .PADDI(PHI2_c), .PHI2(PHI2)); + MAin_9_ \MAin[9]_I ( .PADDI(MAin_c_9), .MAin9(MAin[9])); + MAin_8_ \MAin[8]_I ( .PADDI(MAin_c_8), .MAin8(MAin[8])); + MAin_7_ \MAin[7]_I ( .PADDI(MAin_c_7), .MAin7(MAin[7])); + MAin_6_ \MAin[6]_I ( .PADDI(MAin_c_6), .MAin6(MAin[6])); + MAin_5_ \MAin[5]_I ( .PADDI(MAin_c_5), .MAin5(MAin[5])); + MAin_4_ \MAin[4]_I ( .PADDI(MAin_c_4), .MAin4(MAin[4])); + MAin_3_ \MAin[3]_I ( .PADDI(MAin_c_3), .MAin3(MAin[3])); + MAin_2_ \MAin[2]_I ( .PADDI(MAin_c_2), .MAin2(MAin[2])); + MAin_1_ \MAin[1]_I ( .PADDI(MAin_c_1), .MAin1(MAin[1])); + MAin_0_ \MAin[0]_I ( .PADDI(MAin_c_0), .MAin0(MAin[0])); + CROW_1_ \CROW[1]_I ( .PADDI(CROW_c_1), .CROW1(CROW[1])); + CROW_0_ \CROW[0]_I ( .PADDI(CROW_c_0), .CROW0(CROW[0])); + Din_7_ \Din[7]_I ( .PADDI(Din_c_7), .Din7(Din[7])); + Din_6_ \Din[6]_I ( .PADDI(Din_c_6), .Din6(Din[6])); + Din_5_ \Din[5]_I ( .PADDI(Din_c_5), .Din5(Din[5])); + Din_4_ \Din[4]_I ( .PADDI(Din_c_4), .Din4(Din[4])); + Din_3_ \Din[3]_I ( .PADDI(Din_c_3), .Din3(Din[3])); + Din_2_ \Din[2]_I ( .PADDI(Din_c_2), .Din2(Din[2])); + Din_1_ \Din[1]_I ( .PADDI(Din_c_1), .Din1(Din[1])); + Din_0_ \Din[0]_I ( .PADDI(Din_c_0), .Din0(Din[0])); + nCCAS nCCAS_I( .PADDI(nCCAS_c), .nCCAS(nCCAS)); + nCRAS nCRAS_I( .PADDI(nCRAS_c), .nCRAS(nCRAS)); + nFWE nFWE_I( .PADDI(nFWE_c), .nFWE(nFWE)); + RCLK RCLK_I( .PADDI(RCLK_c), .RCLK(RCLK)); + UFMSDO UFMSDO_I( .PADDI(UFMSDO_c), .UFMSDO(UFMSDO)); + VHI VHI_INST( .Z(VCCI)); + PUR PUR_INST( .PUR(VCCI)); + GSR GSR_INST( .GSR(VCCI)); + VLO VLO_INST( .Z(GNDI_TSALL)); + TSALL TSALL_INST( .TSALL(GNDI_TSALL)); +endmodule + +module SLICE_0 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, \SLICE_0/FS_610_add_4_8_S1 , GNDI, \SLICE_0/FS_610_add_4_8_S0 , + A1_dly, CLK_dly, A0_dly, FCI_dly; + + vmuxregsre FS_610__i7( .D0(VCCI), .D1(\SLICE_0/FS_610_add_4_8_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i6( .D0(VCCI), .D1(\SLICE_0/FS_610_add_4_8_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_8( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), + .S0(\SLICE_0/FS_610_add_4_8_S0 ), .S1(\SLICE_0/FS_610_add_4_8_S1 ), .CO0(), + .CO1(FCO)); + + specify + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly); + endspecify + +endmodule + +module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module vcc ( output PWR1 ); + + VHI INST1( .Z(PWR1)); +endmodule + +module gnd ( output PWR0 ); + + VLO INST1( .Z(PWR0)); +endmodule + +module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO0, + CO1 ); + + CCU2 inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT0(CO0), .COUT1(CO1)); + defparam inst1.INIT0 = 16'hfaaa; + defparam inst1.INIT1 = 16'hfaaa; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_1 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, \SLICE_1/FS_610_add_4_16_S1 , GNDI, + \SLICE_1/FS_610_add_4_16_S0 , A1_dly, CLK_dly, A0_dly, FCI_dly; + + vmuxregsre FS_610__i15( .D0(VCCI), .D1(\SLICE_1/FS_610_add_4_16_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i14( .D0(VCCI), .D1(\SLICE_1/FS_610_add_4_16_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_16( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), + .S0(\SLICE_1/FS_610_add_4_16_S0 ), .S1(\SLICE_1/FS_610_add_4_16_S1 ), + .CO0(), .CO1(FCO)); + + specify + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly); + endspecify + +endmodule + +module SLICE_2 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, \SLICE_2/FS_610_add_4_6_S1 , GNDI, \SLICE_2/FS_610_add_4_6_S0 , + A1_dly, CLK_dly, A0_dly, FCI_dly; + + vmuxregsre FS_610__i5( .D0(VCCI), .D1(\SLICE_2/FS_610_add_4_6_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i4( .D0(VCCI), .D1(\SLICE_2/FS_610_add_4_6_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_6( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), + .S0(\SLICE_2/FS_610_add_4_6_S0 ), .S1(\SLICE_2/FS_610_add_4_6_S1 ), .CO0(), + .CO1(FCO)); + + specify + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly); + endspecify + +endmodule + +module SLICE_3 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, \SLICE_3/FS_610_add_4_14_S1 , GNDI, + \SLICE_3/FS_610_add_4_14_S0 , A1_dly, CLK_dly, A0_dly, FCI_dly; + + vmuxregsre FS_610__i13( .D0(VCCI), .D1(\SLICE_3/FS_610_add_4_14_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i12( .D0(VCCI), .D1(\SLICE_3/FS_610_add_4_14_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_14( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), + .S0(\SLICE_3/FS_610_add_4_14_S0 ), .S1(\SLICE_3/FS_610_add_4_14_S1 ), + .CO0(), .CO1(FCO)); + + specify + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly); + endspecify + +endmodule + +module SLICE_4 ( input A1, A0, CLK, output Q0, Q1, FCO ); + wire VCCI, \SLICE_4/FS_610_add_4_2_S1 , GNDI, \SLICE_4/FS_610_add_4_2_S0 , + A1_dly, CLK_dly, A0_dly; + + vmuxregsre FS_610__i1( .D0(VCCI), .D1(\SLICE_4/FS_610_add_4_2_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i0( .D0(VCCI), .D1(\SLICE_4/FS_610_add_4_2_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20001 FS_610_add_4_2( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), + .S0(\SLICE_4/FS_610_add_4_2_S0 ), .S1(\SLICE_4/FS_610_add_4_2_S1 ), .CO0(), + .CO1(FCO)); + + specify + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + endspecify + +endmodule + +module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO0, + CO1 ); + + CCU2 inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT0(CO0), .COUT1(CO1)); + defparam inst1.INIT0 = 16'h0555; + defparam inst1.INIT1 = 16'hfaaa; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_5 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, \SLICE_5/FS_610_add_4_12_S1 , GNDI, + \SLICE_5/FS_610_add_4_12_S0 , A1_dly, CLK_dly, A0_dly, FCI_dly; + + vmuxregsre FS_610__i11( .D0(VCCI), .D1(\SLICE_5/FS_610_add_4_12_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i10( .D0(VCCI), .D1(\SLICE_5/FS_610_add_4_12_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_12( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), + .S0(\SLICE_5/FS_610_add_4_12_S0 ), .S1(\SLICE_5/FS_610_add_4_12_S1 ), + .CO0(), .CO1(FCO)); + + specify + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly); + endspecify + +endmodule + +module SLICE_6 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, \SLICE_6/FS_610_add_4_4_S1 , GNDI, \SLICE_6/FS_610_add_4_4_S0 , + A1_dly, CLK_dly, A0_dly, FCI_dly; + + vmuxregsre FS_610__i3( .D0(VCCI), .D1(\SLICE_6/FS_610_add_4_4_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i2( .D0(VCCI), .D1(\SLICE_6/FS_610_add_4_4_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_4( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), + .S0(\SLICE_6/FS_610_add_4_4_S0 ), .S1(\SLICE_6/FS_610_add_4_4_S1 ), .CO0(), + .CO1(FCO)); + + specify + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly); + endspecify + +endmodule + +module SLICE_7 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, \SLICE_7/FS_610_add_4_10_S1 , GNDI, + \SLICE_7/FS_610_add_4_10_S0 , A1_dly, CLK_dly, A0_dly, FCI_dly; + + vmuxregsre FS_610__i9( .D0(VCCI), .D1(\SLICE_7/FS_610_add_4_10_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i8( .D0(VCCI), .D1(\SLICE_7/FS_610_add_4_10_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_10( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), + .S0(\SLICE_7/FS_610_add_4_10_S0 ), .S1(\SLICE_7/FS_610_add_4_10_S1 ), + .CO0(), .CO1(FCO)); + + specify + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly); + endspecify + +endmodule + +module SLICE_8 ( input A1, A0, CLK, FCI, output Q0, Q1 ); + wire VCCI, \SLICE_8/FS_610_add_4_18_S1 , GNDI, + \SLICE_8/FS_610_add_4_18_S0 , A1_dly, CLK_dly, A0_dly, FCI_dly; + + vmuxregsre FS_610__i17( .D0(VCCI), .D1(\SLICE_8/FS_610_add_4_18_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i16( .D0(VCCI), .D1(\SLICE_8/FS_610_add_4_18_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_18( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), + .S0(\SLICE_8/FS_610_add_4_18_S0 ), .S1(\SLICE_8/FS_610_add_4_18_S1 ), + .CO0(), .CO1()); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly); + endspecify + +endmodule + +module SLICE_9 ( input C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut4 i1_2_lut_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40002 i1125_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 ADSubmitted_407( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut4 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hDFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40002 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h50DC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0003 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module inverter ( input I, output Z ); + + INV INST1( .A(I), .Z(Z)); +endmodule + +module SLICE_14 ( input B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40004 i1988_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40005 i2062_2_lut_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0006 C1Submitted_406( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40004 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40005 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hE0F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0006 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3JY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module SLICE_18 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40007 i13_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40008 i3_4_lut_adj_21( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdEnable_405( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40007 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hDFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40008 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_19 ( input C1, B1, A1, DI0, CE, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; + + lut40009 i2_3_lut_rep_29( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40010 \n2568\001/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), + .Z(F0)); + vmuxregsre CmdSubmitted_411( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40009 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40010 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_23 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; + + lut40011 i1_2_lut_3_lut_adj_2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40012 Cmdn8MEGEN_I_93_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre Cmdn8MEGEN_410( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40011 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40012 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCC5C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_25 ( input D1, C1, B1, A1, DI0, CE, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40013 i3_3_lut_4_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40010 \n2568\000/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre InitReady_394( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40013 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_26 ( input C1, B1, A1, DI0, CE, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40014 i2049_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40010 m1_lut( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre LEDEN_419( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40014 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_31 ( input B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40015 i1_2_lut_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40011 i2_3_lut_adj_27( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0006 RA10_400( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40015 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_32 ( input B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40004 Din_7__I_0_462_i6_2_lut_rep_35( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40016 RA11_I_54_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 RA11_385( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40016 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hC6C6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_34 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40017 i78_2_lut_rep_24_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40018 i1259_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre RCKEEN_401( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40017 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hF8F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40018 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_35 ( input B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; + + lut40019 i1_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40020 RCKE_I_0_449_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CASr2_383( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre RCKE_395( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40019 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40020 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCFC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_36 ( input B1, A1, DI0, CE, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40015 i771_2_lut_rep_26_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40010 \n2568\002/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), + .Z(F0)); + vmuxregsre Ready_404( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_43 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, CLK, output + F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40021 i919_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40022 i886_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 UFMCLK_416( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40021 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h3A0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40022 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_44 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40023 i1_2_lut_rep_19_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40024 n2454_bdd_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 UFMSDI_417( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40023 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFEFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40024 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hF202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_49 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40025 i2028_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40026 i3_4_lut_adj_12( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre XOR8MEG_408( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40025 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40026 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_56 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut4 i1_2_lut_3_lut_adj_4( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40027 n8MEGEN_I_14_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre n8MEGEN_418( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40027 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCCC5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_58 ( input D1, C1, B1, A1, C0, B0, A0, DI0, M0, CE, CLK, output + OFX0, Q0 ); + wire \SLICE_58/SLICE_58_K1_H1 , GNDI, \SLICE_58/i2095/GATE_H0 , VCCI, + DI0_dly, CLK_dly, CE_dly; + + lut40028 SLICE_58_K1( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\SLICE_58/SLICE_58_K1_H1 )); + lut40029 \i2095/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\SLICE_58/i2095/GATE_H0 )); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0030 nRCAS_398( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 SLICE_58_K0K1MUX( .D0(\SLICE_58/i2095/GATE_H0 ), + .D1(\SLICE_58/SLICE_58_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40028 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h7F2F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40029 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hBFBF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0030 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module selmux2 ( input D0, D1, SD, output Z ); + + MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); +endmodule + +module SLICE_60 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40031 i1234_4_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40032 i1_4_lut_adj_17( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0030 nRCS_396( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40031 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFA88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40032 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCFDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_61 ( input C1, B1, A1, D0, C0, B0, A0, DI0, M0, CLK, output OFX0, + Q0 ); + wire GNDI, \SLICE_61/SLICE_61_K1_H1 , \SLICE_61/i16/GATE_H0 , VCCI, + DI0_dly, CLK_dly; + + lut40033 SLICE_61_K1( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(\SLICE_61/SLICE_61_K1_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40034 \i16/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\SLICE_61/i16/GATE_H0 )); + vmuxregsre0030 nRRAS_397( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 SLICE_61_K0K1MUX( .D0(\SLICE_61/i16/GATE_H0 ), + .D1(\SLICE_61/SLICE_61_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40033 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h7373) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40034 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40035 i2_3_lut_4_lut_adj_8( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40036 nRWE_I_0_455_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0030 nRWE_399( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40035 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFF7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40036 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCFC5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_64 ( input C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; + + lut40018 MAin_9__I_0_427_i10_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40037 i1_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 nRowColSel_402( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40037 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCFEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_65 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40038 Ready_bdd_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40004 i1_2_lut_adj_25( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 S_FSM_i4( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40038 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_66 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40039 i2_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40040 i2057_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 S_FSM_i3( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40039 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40040 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_67 ( input C1, B1, A1, B0, A0, M0, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, LSR_dly; + + lut40041 i1129_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40019 i1_2_lut_adj_23( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0003 S_FSM_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40041 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h3A3A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_68 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M0_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40004 i2024_2_lut_rep_28( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40039 i2026_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CASr3_384( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre S_FSM_i1( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_69 ( input D1, C1, B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; + + lut40042 i6_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40018 i11_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0006 nUFMCS_415( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40042 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module RCKEEN_I_0_445_SLICE_70 ( input C1, B1, A1, D0, C0, B0, A0, M0, output + OFX0 ); + wire GNDI, \RCKEEN_I_0_445/SLICE_70/RCKEEN_I_0_445/SLICE_70_K1_H1 , + \RCKEEN_I_0_445/SLICE_70/RCKEEN_I_0_445/GATE_H0 ; + + lut40043 \RCKEEN_I_0_445/SLICE_70_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(\RCKEEN_I_0_445/SLICE_70/RCKEEN_I_0_445/SLICE_70_K1_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40044 \RCKEEN_I_0_445/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\RCKEEN_I_0_445/SLICE_70/RCKEEN_I_0_445/GATE_H0 )); + selmux2 \RCKEEN_I_0_445/SLICE_70_K0K1MUX ( + .D0(\RCKEEN_I_0_445/SLICE_70/RCKEEN_I_0_445/GATE_H0 ), + .D1(\RCKEEN_I_0_445/SLICE_70/RCKEEN_I_0_445/SLICE_70_K1_H1 ), .SD(M0), + .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40043 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h1F1F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40044 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h5540) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module i26_SLICE_71 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output OFX0 ); + wire \i26/SLICE_71/i26/SLICE_71_K1_H1 , \i26/SLICE_71/i26/GATE_H0 ; + + lut40045 \i26/SLICE_71_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\i26/SLICE_71/i26/SLICE_71_K1_H1 )); + lut40046 \i26/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\i26/SLICE_71/i26/GATE_H0 )); + selmux2 \i26/SLICE_71_K0K1MUX ( .D0(\i26/SLICE_71/i26/GATE_H0 ), + .D1(\i26/SLICE_71/i26/SLICE_71_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40045 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40046 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module i2099_SLICE_72 ( input D1, C1, B1, A1, C0, B0, A0, M0, output OFX0 ); + wire \i2099/SLICE_72/i2099/SLICE_72_K1_H1 , GNDI, + \i2099/SLICE_72/i2099/GATE_H0 ; + + lut40047 \i2099/SLICE_72_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\i2099/SLICE_72/i2099/SLICE_72_K1_H1 )); + lut40048 \i2099/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\i2099/SLICE_72/i2099/GATE_H0 )); + gnd DRIVEGND( .PWR0(GNDI)); + selmux2 \i2099/SLICE_72_K0K1MUX ( .D0(\i2099/SLICE_72/i2099/GATE_H0 ), + .D1(\i2099/SLICE_72/i2099/SLICE_72_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40047 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2F23) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40048 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2F2F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module i26_adj_28_SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output + OFX0 ); + wire \i26_adj_28/SLICE_73/i26_adj_28/SLICE_73_K1_H1 , + \i26_adj_28/SLICE_73/i26_adj_28/GATE_H0 ; + + lut40049 \i26_adj_28/SLICE_73_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\i26_adj_28/SLICE_73/i26_adj_28/SLICE_73_K1_H1 )); + lut40050 \i26_adj_28/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\i26_adj_28/SLICE_73/i26_adj_28/GATE_H0 )); + selmux2 \i26_adj_28/SLICE_73_K0K1MUX ( + .D0(\i26_adj_28/SLICE_73/i26_adj_28/GATE_H0 ), + .D1(\i26_adj_28/SLICE_73/i26_adj_28/SLICE_73_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40049 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40050 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_74 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly; + + lut40051 i35_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40052 i3_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre RASr3_381( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre RASr2_380( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40051 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h1F10) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40052 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_75 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40009 i2_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40053 i7_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40053 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_76 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40054 i5_3_lut_rep_15_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40055 i1_4_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre IS_FSM__i9( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre IS_FSM__i8( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40054 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40055 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hB300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_77 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40056 i3_4_lut_adj_18( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40011 i1994_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre IS_FSM__i13( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i12( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40056 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_78 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40039 i5_3_lut_rep_21_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40057 i2065_2_lut_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 RowA_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 RowA_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40057 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_79 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M0_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40058 i1_2_lut_rep_25_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40059 i2_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre PHI2r2_377( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre CASr_382( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40058 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40059 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_80 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40004 i1_2_lut_adj_16( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40060 i1_2_lut_3_lut_4_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre IS_FSM__i15( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i14( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40060 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_81 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40061 i1982_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40062 i12_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdUFMCS_412( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre CmdUFMCLK_413( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40061 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40062 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hBFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_82 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40063 i2052_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40004 i1990_2_lut_rep_17( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre IS_FSM__i11( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i10( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40063 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0302) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_83 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, + F1 ); + wire M0_NOTIN, VCCI, GNDI, M0_dly, CLK_dly; + + lut40008 i1_2_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40026 i4_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre RASr_379( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_84 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40056 i2_4_lut_adj_11( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40014 i1_2_lut_3_lut_adj_5( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre IS_FSM__i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_85 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40013 i2_3_lut_4_lut_adj_15( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40004 i2004_2_lut_rep_30( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 RBA__i2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 RBA__i1( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_86 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40009 i2_3_lut_adj_10( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40064 i1_2_lut_rep_20_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre IS_FSM__i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40064 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_87 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40040 i2_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40065 i17_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre IS_FSM__i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40065 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_88 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40009 n2452_bdd_2_lut_rep_18_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40066 FS_6__bdd_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre Bank_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre Bank_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40066 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0062) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_89 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40064 i1_2_lut_rep_16_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40014 i2_3_lut_adj_1( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre WRD_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre WRD_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module SLICE_90 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40039 i2032_2_lut_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40004 i2_2_lut_rep_27( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0006 RowA_i9( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 RowA_i8( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_91 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40061 i1_2_lut_rep_33( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40067 i2_4_lut_adj_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre PHI2r_376( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre PHI2r3_378( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40067 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h8C00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_92 ( input B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40068 i1_2_lut_rep_32( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40069 i2_3_lut_rep_31( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre WRD_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre WRD_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module lut40068 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40069 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_93 ( input B1, A1, B0, A0, M0, CE, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; + + lut40070 i2060_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40019 i1512_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre CmdUFMSDI_414( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40070 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_94 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40004 i1976_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 i5_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_95 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40061 i1_2_lut_adj_22( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 i2055_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0006 RowA_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 RowA_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40071 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_96 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40018 MAin_9__I_0_427_i4_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 i2020_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 RowA_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 RowA_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_97 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40018 MAin_9__I_0_427_i5_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 i2018_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 RowA_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 RowA_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_98 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, M1_NOTIN, VCCI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40018 MAin_9__I_0_427_i1_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40018 MAin_9__I_0_427_i9_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre FWEr_389( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre CBR_390( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module SLICE_99 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40018 MAin_9__I_0_427_i2_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40018 MAin_9__I_0_427_i8_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre Bank_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre Bank_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_100 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40072 i2_2_lut_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40073 i1_2_lut_4_lut_adj_7( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre IS_FSM__i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre IS_FSM__i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40072 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hF0F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40073 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h08FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_101 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40018 MAin_9__I_0_427_i3_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40018 MAin_9__I_0_427_i7_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre Bank_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre Bank_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_102 ( input B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40004 i1_2_lut_adj_26( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40014 InitReady_bdd_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre Bank_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre Bank_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_103 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40018 MAin_9__I_0_427_i6_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40014 i2_3_lut_adj_14( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre WRD_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre WRD_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module SLICE_104 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40004 n2414_bdd_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40074 n1_bdd_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40074 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hF0DD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_105 ( input B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40004 i1513_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40075 i2_3_lut_adj_20( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre WRD_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre WRD_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module lut40075 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 ); + + mjiobuf Dout_pad_7__713( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), + .PADI(RD7)); + + specify + (PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD7) = (0:0:0,0:0:0); + (RD7 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD7, 0:0:0); + $width (negedge RD7, 0:0:0); + endspecify + +endmodule + +module mjiobuf ( input I, T, output Z, PAD, input PADI ); + + IBPU INST1( .I(PADI), .O(Z)); + OBZPU INST2( .I(I), .T(T), .O(PAD)); +endmodule + +module RD_6_ ( output PADDI, input PADDT, PADDO, inout RD6 ); + + mjiobuf Dout_pad_6__714( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD6), + .PADI(RD6)); + + specify + (PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD6) = (0:0:0,0:0:0); + (RD6 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD6, 0:0:0); + $width (negedge RD6, 0:0:0); + endspecify + +endmodule + +module RD_5_ ( output PADDI, input PADDT, PADDO, inout RD5 ); + + mjiobuf Dout_pad_5__715( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD5), + .PADI(RD5)); + + specify + (PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD5) = (0:0:0,0:0:0); + (RD5 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD5, 0:0:0); + $width (negedge RD5, 0:0:0); + endspecify + +endmodule + +module RD_4_ ( output PADDI, input PADDT, PADDO, inout RD4 ); + + mjiobuf Dout_pad_4__716( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD4), + .PADI(RD4)); + + specify + (PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD4) = (0:0:0,0:0:0); + (RD4 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD4, 0:0:0); + $width (negedge RD4, 0:0:0); + endspecify + +endmodule + +module RD_3_ ( output PADDI, input PADDT, PADDO, inout RD3 ); + + mjiobuf Dout_pad_3__717( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD3), + .PADI(RD3)); + + specify + (PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD3) = (0:0:0,0:0:0); + (RD3 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD3, 0:0:0); + $width (negedge RD3, 0:0:0); + endspecify + +endmodule + +module RD_2_ ( output PADDI, input PADDT, PADDO, inout RD2 ); + + mjiobuf Dout_pad_2__718( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD2), + .PADI(RD2)); + + specify + (PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD2) = (0:0:0,0:0:0); + (RD2 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD2, 0:0:0); + $width (negedge RD2, 0:0:0); + endspecify + +endmodule + +module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 ); + + mjiobuf Dout_pad_1__719( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD1), + .PADI(RD1)); + + specify + (PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD1) = (0:0:0,0:0:0); + (RD1 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD1, 0:0:0); + $width (negedge RD1, 0:0:0); + endspecify + +endmodule + +module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 ); + + mjiobuf Dout_pad_0__720( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), + .PADI(RD0)); + + specify + (PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD0) = (0:0:0,0:0:0); + (RD0 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD0, 0:0:0); + $width (negedge RD0, 0:0:0); + endspecify + +endmodule + +module Dout_7_ ( input PADDO, output Dout7 ); + wire GNDI; + + mjiobuf0076 Dout_pad_7( .I(PADDO), .T(GNDI), .PAD(Dout7)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module mjiobuf0076 ( input I, T, output PAD ); + + OBZPU INST5( .I(I), .T(T), .O(PAD)); +endmodule + +module Dout_6_ ( input PADDO, output Dout6 ); + wire GNDI; + + mjiobuf0076 Dout_pad_6( .I(PADDO), .T(GNDI), .PAD(Dout6)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_5_ ( input PADDO, output Dout5 ); + wire GNDI; + + mjiobuf0076 Dout_pad_5( .I(PADDO), .T(GNDI), .PAD(Dout5)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_4_ ( input PADDO, output Dout4 ); + wire GNDI; + + mjiobuf0076 Dout_pad_4( .I(PADDO), .T(GNDI), .PAD(Dout4)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_3_ ( input PADDO, output Dout3 ); + wire GNDI; + + mjiobuf0076 Dout_pad_3( .I(PADDO), .T(GNDI), .PAD(Dout3)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_2_ ( input PADDO, output Dout2 ); + wire GNDI; + + mjiobuf0076 Dout_pad_2( .I(PADDO), .T(GNDI), .PAD(Dout2)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_1_ ( input PADDO, output Dout1 ); + wire GNDI; + + mjiobuf0076 Dout_pad_1( .I(PADDO), .T(GNDI), .PAD(Dout1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_0_ ( input PADDO, output Dout0 ); + wire GNDI; + + mjiobuf0076 Dout_pad_0( .I(PADDO), .T(GNDI), .PAD(Dout0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module LED ( input PADDO, output LED ); + wire GNDI; + + mjiobuf0076 LED_pad( .I(PADDO), .T(GNDI), .PAD(LED)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => LED) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RBA_1_ ( input PADDO, output RBA1 ); + wire GNDI; + + mjiobuf0076 RBA_pad_1( .I(PADDO), .T(GNDI), .PAD(RBA1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RBA1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RBA_0_ ( input PADDO, output RBA0 ); + wire GNDI; + + mjiobuf0076 RBA_pad_0( .I(PADDO), .T(GNDI), .PAD(RBA0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RBA0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_11_ ( input PADDO, output RA11 ); + wire GNDI; + + mjiobuf0076 RA_pad_11( .I(PADDO), .T(GNDI), .PAD(RA11)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA11) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_10_ ( input PADDO, output RA10 ); + wire GNDI; + + mjiobuf0076 RA_pad_10( .I(PADDO), .T(GNDI), .PAD(RA10)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA10) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_9_ ( input PADDO, output RA9 ); + wire GNDI; + + mjiobuf0076 RA_pad_9( .I(PADDO), .T(GNDI), .PAD(RA9)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA9) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_8_ ( input PADDO, output RA8 ); + wire GNDI; + + mjiobuf0076 RA_pad_8( .I(PADDO), .T(GNDI), .PAD(RA8)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA8) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_7_ ( input PADDO, output RA7 ); + wire GNDI; + + mjiobuf0076 RA_pad_7( .I(PADDO), .T(GNDI), .PAD(RA7)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_6_ ( input PADDO, output RA6 ); + wire GNDI; + + mjiobuf0076 RA_pad_6( .I(PADDO), .T(GNDI), .PAD(RA6)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_5_ ( input PADDO, output RA5 ); + wire GNDI; + + mjiobuf0076 RA_pad_5( .I(PADDO), .T(GNDI), .PAD(RA5)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_4_ ( input PADDO, output RA4 ); + wire GNDI; + + mjiobuf0076 RA_pad_4( .I(PADDO), .T(GNDI), .PAD(RA4)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_3_ ( input PADDO, output RA3 ); + wire GNDI; + + mjiobuf0076 RA_pad_3( .I(PADDO), .T(GNDI), .PAD(RA3)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_2_ ( input PADDO, output RA2 ); + wire GNDI; + + mjiobuf0076 RA_pad_2( .I(PADDO), .T(GNDI), .PAD(RA2)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_1_ ( input PADDO, output RA1 ); + wire GNDI; + + mjiobuf0076 RA_pad_1( .I(PADDO), .T(GNDI), .PAD(RA1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_0_ ( input PADDO, output RA0 ); + wire GNDI; + + mjiobuf0076 RA_pad_0( .I(PADDO), .T(GNDI), .PAD(RA0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRCS ( input PADDO, output nRCS ); + wire GNDI; + + mjiobuf0076 nRCS_pad( .I(PADDO), .T(GNDI), .PAD(nRCS)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nRCS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RCKE ( input PADDO, output RCKE ); + wire GNDI; + + mjiobuf0076 RCKE_pad( .I(PADDO), .T(GNDI), .PAD(RCKE)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RCKE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRWE ( input PADDO, output nRWE ); + wire GNDI; + + mjiobuf0076 nRWE_pad( .I(PADDO), .T(GNDI), .PAD(nRWE)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nRWE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRRAS ( input PADDO, output nRRAS ); + wire GNDI; + + mjiobuf0076 nRRAS_pad( .I(PADDO), .T(GNDI), .PAD(nRRAS)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nRRAS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRCAS ( input PADDO, output nRCAS ); + wire GNDI; + + mjiobuf0076 nRCAS_pad( .I(PADDO), .T(GNDI), .PAD(nRCAS)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nRCAS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RDQMH ( input PADDO, output RDQMH ); + wire GNDI; + + mjiobuf0076 RDQMH_pad( .I(PADDO), .T(GNDI), .PAD(RDQMH)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RDQMH) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RDQML ( input PADDO, output RDQML ); + wire GNDI; + + mjiobuf0076 RDQML_pad( .I(PADDO), .T(GNDI), .PAD(RDQML)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RDQML) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nUFMCS ( input PADDO, output nUFMCS ); + wire GNDI; + + mjiobuf0076 nUFMCS_pad( .I(PADDO), .T(GNDI), .PAD(nUFMCS)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nUFMCS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module UFMCLK ( input PADDO, output UFMCLK ); + wire GNDI; + + mjiobuf0076 UFMCLK_pad( .I(PADDO), .T(GNDI), .PAD(UFMCLK)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => UFMCLK) = (0:0:0,0:0:0); + endspecify + +endmodule + +module UFMSDI ( input PADDO, output UFMSDI ); + wire GNDI; + + mjiobuf0076 UFMSDI_pad( .I(PADDO), .T(GNDI), .PAD(UFMSDI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => UFMSDI) = (0:0:0,0:0:0); + endspecify + +endmodule + +module PHI2 ( output PADDI, input PHI2 ); + + mjiobuf0077 PHI2_pad( .Z(PADDI), .PAD(PHI2)); + + specify + (PHI2 => PADDI) = (0:0:0,0:0:0); + $width (posedge PHI2, 0:0:0); + $width (negedge PHI2, 0:0:0); + endspecify + +endmodule + +module mjiobuf0077 ( output Z, input PAD ); + + IBPU INST1( .I(PAD), .O(Z)); +endmodule + +module MAin_9_ ( output PADDI, input MAin9 ); + + mjiobuf0077 MAin_pad_9( .Z(PADDI), .PAD(MAin9)); + + specify + (MAin9 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin9, 0:0:0); + $width (negedge MAin9, 0:0:0); + endspecify + +endmodule + +module MAin_8_ ( output PADDI, input MAin8 ); + + mjiobuf0077 MAin_pad_8( .Z(PADDI), .PAD(MAin8)); + + specify + (MAin8 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin8, 0:0:0); + $width (negedge MAin8, 0:0:0); + endspecify + +endmodule + +module MAin_7_ ( output PADDI, input MAin7 ); + + mjiobuf0077 MAin_pad_7( .Z(PADDI), .PAD(MAin7)); + + specify + (MAin7 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin7, 0:0:0); + $width (negedge MAin7, 0:0:0); + endspecify + +endmodule + +module MAin_6_ ( output PADDI, input MAin6 ); + + mjiobuf0077 MAin_pad_6( .Z(PADDI), .PAD(MAin6)); + + specify + (MAin6 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin6, 0:0:0); + $width (negedge MAin6, 0:0:0); + endspecify + +endmodule + +module MAin_5_ ( output PADDI, input MAin5 ); + + mjiobuf0077 MAin_pad_5( .Z(PADDI), .PAD(MAin5)); + + specify + (MAin5 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin5, 0:0:0); + $width (negedge MAin5, 0:0:0); + endspecify + +endmodule + +module MAin_4_ ( output PADDI, input MAin4 ); + + mjiobuf0077 MAin_pad_4( .Z(PADDI), .PAD(MAin4)); + + specify + (MAin4 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin4, 0:0:0); + $width (negedge MAin4, 0:0:0); + endspecify + +endmodule + +module MAin_3_ ( output PADDI, input MAin3 ); + + mjiobuf0077 MAin_pad_3( .Z(PADDI), .PAD(MAin3)); + + specify + (MAin3 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin3, 0:0:0); + $width (negedge MAin3, 0:0:0); + endspecify + +endmodule + +module MAin_2_ ( output PADDI, input MAin2 ); + + mjiobuf0077 MAin_pad_2( .Z(PADDI), .PAD(MAin2)); + + specify + (MAin2 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin2, 0:0:0); + $width (negedge MAin2, 0:0:0); + endspecify + +endmodule + +module MAin_1_ ( output PADDI, input MAin1 ); + + mjiobuf0077 MAin_pad_1( .Z(PADDI), .PAD(MAin1)); + + specify + (MAin1 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin1, 0:0:0); + $width (negedge MAin1, 0:0:0); + endspecify + +endmodule + +module MAin_0_ ( output PADDI, input MAin0 ); + + mjiobuf0077 MAin_pad_0( .Z(PADDI), .PAD(MAin0)); + + specify + (MAin0 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin0, 0:0:0); + $width (negedge MAin0, 0:0:0); + endspecify + +endmodule + +module CROW_1_ ( output PADDI, input CROW1 ); + + mjiobuf0077 CROW_pad_1( .Z(PADDI), .PAD(CROW1)); + + specify + (CROW1 => PADDI) = (0:0:0,0:0:0); + $width (posedge CROW1, 0:0:0); + $width (negedge CROW1, 0:0:0); + endspecify + +endmodule + +module CROW_0_ ( output PADDI, input CROW0 ); + + mjiobuf0077 CROW_pad_0( .Z(PADDI), .PAD(CROW0)); + + specify + (CROW0 => PADDI) = (0:0:0,0:0:0); + $width (posedge CROW0, 0:0:0); + $width (negedge CROW0, 0:0:0); + endspecify + +endmodule + +module Din_7_ ( output PADDI, input Din7 ); + + mjiobuf0077 Din_pad_7( .Z(PADDI), .PAD(Din7)); + + specify + (Din7 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din7, 0:0:0); + $width (negedge Din7, 0:0:0); + endspecify + +endmodule + +module Din_6_ ( output PADDI, input Din6 ); + + mjiobuf0077 Din_pad_6( .Z(PADDI), .PAD(Din6)); + + specify + (Din6 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din6, 0:0:0); + $width (negedge Din6, 0:0:0); + endspecify + +endmodule + +module Din_5_ ( output PADDI, input Din5 ); + + mjiobuf0077 Din_pad_5( .Z(PADDI), .PAD(Din5)); + + specify + (Din5 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din5, 0:0:0); + $width (negedge Din5, 0:0:0); + endspecify + +endmodule + +module Din_4_ ( output PADDI, input Din4 ); + + mjiobuf0077 Din_pad_4( .Z(PADDI), .PAD(Din4)); + + specify + (Din4 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din4, 0:0:0); + $width (negedge Din4, 0:0:0); + endspecify + +endmodule + +module Din_3_ ( output PADDI, input Din3 ); + + mjiobuf0077 Din_pad_3( .Z(PADDI), .PAD(Din3)); + + specify + (Din3 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din3, 0:0:0); + $width (negedge Din3, 0:0:0); + endspecify + +endmodule + +module Din_2_ ( output PADDI, input Din2 ); + + mjiobuf0077 Din_pad_2( .Z(PADDI), .PAD(Din2)); + + specify + (Din2 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din2, 0:0:0); + $width (negedge Din2, 0:0:0); + endspecify + +endmodule + +module Din_1_ ( output PADDI, input Din1 ); + + mjiobuf0077 Din_pad_1( .Z(PADDI), .PAD(Din1)); + + specify + (Din1 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din1, 0:0:0); + $width (negedge Din1, 0:0:0); + endspecify + +endmodule + +module Din_0_ ( output PADDI, input Din0 ); + + mjiobuf0077 Din_pad_0( .Z(PADDI), .PAD(Din0)); + + specify + (Din0 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din0, 0:0:0); + $width (negedge Din0, 0:0:0); + endspecify + +endmodule + +module nCCAS ( output PADDI, input nCCAS ); + + mjiobuf0077 nCCAS_pad( .Z(PADDI), .PAD(nCCAS)); + + specify + (nCCAS => PADDI) = (0:0:0,0:0:0); + $width (posedge nCCAS, 0:0:0); + $width (negedge nCCAS, 0:0:0); + endspecify + +endmodule + +module nCRAS ( output PADDI, input nCRAS ); + + mjiobuf0077 nCRAS_pad( .Z(PADDI), .PAD(nCRAS)); + + specify + (nCRAS => PADDI) = (0:0:0,0:0:0); + $width (posedge nCRAS, 0:0:0); + $width (negedge nCRAS, 0:0:0); + endspecify + +endmodule + +module nFWE ( output PADDI, input nFWE ); + + mjiobuf0077 nFWE_pad( .Z(PADDI), .PAD(nFWE)); + + specify + (nFWE => PADDI) = (0:0:0,0:0:0); + $width (posedge nFWE, 0:0:0); + $width (negedge nFWE, 0:0:0); + endspecify + +endmodule + +module RCLK ( output PADDI, input RCLK ); + + mjiobuf0077 RCLK_pad( .Z(PADDI), .PAD(RCLK)); + + specify + (RCLK => PADDI) = (0:0:0,0:0:0); + $width (posedge RCLK, 0:0:0); + $width (negedge RCLK, 0:0:0); + endspecify + +endmodule + +module UFMSDO ( output PADDI, input UFMSDO ); + + mjiobuf0077 UFMSDO_pad( .Z(PADDI), .PAD(UFMSDO)); + + specify + (UFMSDO => PADDI) = (0:0:0,0:0:0); + $width (posedge UFMSDO, 0:0:0); + $width (negedge UFMSDO, 0:0:0); + endspecify + +endmodule diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mrp.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mrp.html new file mode 100644 index 0000000..56f2c31 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mrp.html @@ -0,0 +1,368 @@ + +Project Summary + + +
    
+            Lattice Mapping Report File for Design Module 'RAM2GS'
+
+
+
+Design Information
+
+Command line:   map -a MachXO -p LCMXO256C -t TQFP100 -s 3 -oc Commercial
+     RAM2GS_LCMXO256C_impl1.ngd -o RAM2GS_LCMXO256C_impl1_map.ncd -pr
+     RAM2GS_LCMXO256C_impl1.prf -mp RAM2GS_LCMXO256C_impl1.mrp -lpf D:/OneDrive/
+     Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.lpf
+     -lpf
+     D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.lpf -c
+     0 -gui -msgset
+     D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml 
+Target Vendor:  LATTICE
+Target Device:  LCMXO256CTQFP100
+Target Performance:   3
+Mapper:  mj5g00,  version:  Diamond (64-bit) 3.12.1.454
+Mapped on:  08/15/23  05:03:20
+
+
+Design Summary
+   Number of PFU registers:   102 out of   256 (40%)
+   Number of SLICEs:        71 out of   128 (55%)
+      SLICEs as Logic/ROM:     71 out of   128 (55%)
+      SLICEs as RAM:            0 out of    64 (0%)
+      SLICEs as Carry:          9 out of   128 (7%)
+   Number of LUT4s:        142 out of   256 (55%)
+      Number used as logic LUTs:        124
+      Number used as distributed RAM:     0
+      Number used as ripple logic:       18
+      Number used as shift registers:     0
+   Number of external PIOs: 67 out of 78 (86%)
+   Number of GSRs:  0 out of 1 (0%)
+   JTAG used :      No
+   Readback used :  No
+   Oscillator used :  No
+   Startup used :   No
+   Number of TSALL: 0 out of 1 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
+     distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and
+     ripple logic.
+   Number of clocks:  4
+     Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK )
+     Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
+     Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
+     Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
+   Number of Clock Enables:  13
+     Net PHI2_N_120_enable_4: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_4: 3 loads, 3 LSLICEs
+     Net RCLK_c_enable_23: 8 loads, 8 LSLICEs
+     Net RCLK_c_enable_12: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_3: 1 loads, 1 LSLICEs
+     Net PHI2_N_120_enable_5: 1 loads, 1 LSLICEs
+     Net PHI2_N_120_enable_6: 2 loads, 2 LSLICEs
+     Net RCLK_c_enable_24: 2 loads, 2 LSLICEs
+     Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs
+     Net Ready_N_292: 1 loads, 1 LSLICEs
+
+     Net RCLK_c_enable_11: 1 loads, 1 LSLICEs
+     Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_25: 1 loads, 1 LSLICEs
+   Number of LSRs:  9
+     Net RASr2: 1 loads, 1 LSLICEs
+     Net Ready: 7 loads, 7 LSLICEs
+     Net C1Submitted_N_237: 2 loads, 2 LSLICEs
+     Net n2469: 1 loads, 1 LSLICEs
+     Net nRowColSel_N_35: 1 loads, 1 LSLICEs
+     Net n1846: 2 loads, 2 LSLICEs
+     Net LEDEN_N_82: 1 loads, 1 LSLICEs
+     Net nRowColSel_N_34: 1 loads, 1 LSLICEs
+     Net nRWE_N_177: 1 loads, 1 LSLICEs
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+     Net Ready: 23 loads
+     Net InitReady: 17 loads
+     Net RASr2: 14 loads
+     Net nRowColSel: 13 loads
+     Net MAin_c_0: 12 loads
+     Net nRowColSel_N_35: 12 loads
+     Net Din_c_3: 11 loads
+     Net Din_c_6: 11 loads
+     Net MAin_c_1: 11 loads
+     Net Din_c_4: 10 loads
+
+
+
+
+   Number of warnings:  0
+   Number of errors:    0
+     
+
+
+
+
+Design Errors/Warnings
+
+   No errors or warnings present.
+
+
+
+IO (PIO) Attributes
+
++---------------------+-----------+-----------+------------+------------+
+| IO Name             | Direction | Levelmode | IO         | FIXEDDELAY |
+|                     |           |  IO_TYPE  | Register   |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[7]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[6]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[5]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[4]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[3]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[2]               | BIDIR     | LVCMOS33  |            |            |
+
++---------------------+-----------+-----------+------------+------------+
+| RD[1]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[0]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[7]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[6]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[5]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[4]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[3]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[2]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[1]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[0]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| LED                 | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RBA[1]              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RBA[0]              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[11]              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[10]              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[9]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[8]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[7]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[6]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[5]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[4]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[3]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[2]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[1]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[0]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRCS                | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RCKE                | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRWE                | OUTPUT    | LVCMOS33  |            |            |
+
++---------------------+-----------+-----------+------------+------------+
+| nRRAS               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRCAS               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RDQMH               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RDQML               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nUFMCS              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMCLK              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMSDI              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| PHI2                | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[9]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[8]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[7]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[6]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[5]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[4]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[3]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[2]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[1]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[0]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| CROW[1]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| CROW[0]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[7]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[6]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[5]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[4]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[3]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[2]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[1]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[0]              | INPUT     | LVCMOS33  |            |            |
+
++---------------------+-----------+-----------+------------+------------+
+| nCCAS               | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nCRAS               | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nFWE                | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RCLK                | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMSDO              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+
+
+Removed logic
+
+Block i2 undriven or does not drive anything - clipped.
+Block GSR_INST undriven or does not drive anything - clipped.
+Signal nCRAS_N_9 was merged into signal nCRAS_c
+Signal nCCAS_N_3 was merged into signal nCCAS_c
+Signal PHI2_N_120 was merged into signal PHI2_c
+Signal RASr2_N_63 was merged into signal RASr2
+Signal n1426 was merged into signal nRowColSel_N_35
+Signal nRWE_N_176 was merged into signal nRWE_N_177
+Signal n1425 was merged into signal nRowColSel_N_34
+Signal nFWE_N_5 was merged into signal nFWE_c
+Signal n2477 was merged into signal Ready
+Signal GND_net undriven or does not drive anything - clipped.
+Signal VCC_net undriven or does not drive anything - clipped.
+Signal FS_610_add_4_18/CO1 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_18/CO0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_10/CO0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_4/CO0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_12/CO0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_2/CO0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_14/CO0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_6/CO0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_16/CO0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_8/CO0 undriven or does not drive anything - clipped.
+Block i2135 was optimized away.
+Block i2134 was optimized away.
+Block i2136 was optimized away.
+Block RASr2_I_0_1_lut was optimized away.
+Block i1137_1_lut was optimized away.
+Block nRWE_I_50_1_lut was optimized away.
+Block i1136_1_lut was optimized away.
+Block i1_1_lut was optimized away.
+Block i637_1_lut_rep_34 was optimized away.
+Block i1 was optimized away.
+
+
+
+Run Time and Memory Usage
+-------------------------
+
+   Total CPU Time: 0 secs  
+   Total REAL Time: 0 secs  
+   Peak Memory Usage: 29 MB
+        
+
+
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+     Copyright (c) 1995 AT&T Corp.   All rights reserved.
+     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+     Copyright (c) 2001 Agere Systems   All rights reserved.
+     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
+     reserved.
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_pad.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_pad.html new file mode 100644 index 0000000..e31d039 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_pad.html @@ -0,0 +1,336 @@ + +PAD Specification File + + +
    PAD Specification File
+***************************
+
+PART TYPE:        LCMXO256C
+Performance Grade:      3
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.19
+
+Tue Aug 15 05:03:28 2023
+
+Pinout by Port Name:
++-----------+----------+---------------+------+------------------------------+
+| Port Name | Pin/Bank | Buffer Type   | Site | Properties                   |
++-----------+----------+---------------+------+------------------------------+
+| CROW[0]   | 32/1     | LVCMOS33_IN   | PB2C | SLEW:FAST PULL:UP            |
+| CROW[1]   | 34/1     | LVCMOS33_IN   | PB2D | SLEW:FAST PULL:UP            |
+| Din[0]    | 21/1     | LVCMOS33_IN   | PL8A | SLEW:FAST PULL:UP            |
+| Din[1]    | 15/1     | LVCMOS33_IN   | PL6A | SLEW:FAST PULL:UP            |
+| Din[2]    | 14/1     | LVCMOS33_IN   | PL5D | SLEW:FAST PULL:UP            |
+| Din[3]    | 16/1     | LVCMOS33_IN   | PL6B | SLEW:FAST PULL:UP            |
+| Din[4]    | 18/1     | LVCMOS33_IN   | PL7B | SLEW:FAST PULL:UP            |
+| Din[5]    | 17/1     | LVCMOS33_IN   | PL7A | SLEW:FAST PULL:UP            |
+| Din[6]    | 20/1     | LVCMOS33_IN   | PL7D | SLEW:FAST PULL:UP            |
+| Din[7]    | 19/1     | LVCMOS33_IN   | PL7C | SLEW:FAST PULL:UP            |
+| Dout[0]   | 1/1      | LVCMOS33_OUT  | PL2A | DRIVE:8mA SLEW:FAST PULL:UP  |
+| Dout[1]   | 7/1      | LVCMOS33_OUT  | PL4A | DRIVE:8mA SLEW:FAST PULL:UP  |
+| Dout[2]   | 8/1      | LVCMOS33_OUT  | PL4B | DRIVE:8mA SLEW:FAST PULL:UP  |
+| Dout[3]   | 6/1      | LVCMOS33_OUT  | PL3D | DRIVE:8mA SLEW:FAST PULL:UP  |
+| Dout[4]   | 4/1      | LVCMOS33_OUT  | PL3B | DRIVE:8mA SLEW:FAST PULL:UP  |
+| Dout[5]   | 5/1      | LVCMOS33_OUT  | PL3C | DRIVE:8mA SLEW:FAST PULL:UP  |
+| Dout[6]   | 2/1      | LVCMOS33_OUT  | PL2B | DRIVE:8mA SLEW:FAST PULL:UP  |
+| Dout[7]   | 3/1      | LVCMOS33_OUT  | PL3A | DRIVE:8mA SLEW:FAST PULL:UP  |
+| LED       | 57/0     | LVCMOS33_OUT  | PR7B | DRIVE:8mA SLEW:FAST PULL:UP  |
+| MAin[0]   | 23/1     | LVCMOS33_IN   | PL9A | SLEW:FAST PULL:UP            |
+| MAin[1]   | 38/1     | LVCMOS33_IN   | PB3C | SLEW:FAST PULL:UP            |
+| MAin[2]   | 37/1     | LVCMOS33_IN   | PB3B | SLEW:FAST PULL:UP            |
+| MAin[3]   | 47/1     | LVCMOS33_IN   | PB5A | SLEW:FAST PULL:UP            |
+| MAin[4]   | 46/1     | LVCMOS33_IN   | PB4D | SLEW:FAST PULL:UP            |
+| MAin[5]   | 45/1     | LVCMOS33_IN   | PB4C | SLEW:FAST PULL:UP            |
+| MAin[6]   | 49/1     | LVCMOS33_IN   | PB5C | SLEW:FAST PULL:UP            |
+| MAin[7]   | 44/1     | LVCMOS33_IN   | PB4B | SLEW:FAST PULL:UP            |
+| MAin[8]   | 50/1     | LVCMOS33_IN   | PB5D | SLEW:FAST PULL:UP            |
+| MAin[9]   | 51/0     | LVCMOS33_IN   | PR9B | SLEW:FAST PULL:UP            |
+| PHI2      | 39/1     | LVCMOS33_IN   | PB3D | SLEW:FAST PULL:UP            |
+| RA[0]     | 98/0     | LVCMOS33_OUT  | PT2C | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[10]    | 87/0     | LVCMOS33_OUT  | PT3D | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[11]    | 79/0     | LVCMOS33_OUT  | PT5A | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[1]     | 89/0     | LVCMOS33_OUT  | PT3C | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[2]     | 94/0     | LVCMOS33_OUT  | PT3A | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[3]     | 97/0     | LVCMOS33_OUT  | PT2D | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[4]     | 99/0     | LVCMOS33_OUT  | PT2B | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[5]     | 95/0     | LVCMOS33_OUT  | PT2F | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[6]     | 91/0     | LVCMOS33_OUT  | PT3B | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[7]     | 100/0    | LVCMOS33_OUT  | PT2A | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[8]     | 96/0     | LVCMOS33_OUT  | PT2E | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[9]     | 85/0     | LVCMOS33_OUT  | PT4B | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RBA[0]    | 63/0     | LVCMOS33_OUT  | PR5D | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RBA[1]    | 83/0     | LVCMOS33_OUT  | PT4C | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RCKE      | 82/0     | LVCMOS33_OUT  | PT4D | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RCLK      | 86/0     | LVCMOS33_IN   | PT4A | SLEW:FAST PULL:UP            |
+| RDQMH     | 76/0     | LVCMOS33_OUT  | PR2A | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RDQML     | 61/0     | LVCMOS33_OUT  | PR6A | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RD[0]     | 64/0     | LVCMOS33_BIDI | PR5C | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RD[1]     | 65/0     | LVCMOS33_BIDI | PR5B | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RD[2]     | 66/0     | LVCMOS33_BIDI | PR5A | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RD[3]     | 67/0     | LVCMOS33_BIDI | PR4B | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RD[4]     | 68/0     | LVCMOS33_BIDI | PR4A | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RD[5]     | 69/0     | LVCMOS33_BIDI | PR3D | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RD[6]     | 70/0     | LVCMOS33_BIDI | PR3C | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RD[7]     | 71/0     | LVCMOS33_BIDI | PR3B | DRIVE:8mA SLEW:FAST PULL:UP  |
+| UFMCLK    | 58/0     | LVCMOS33_OUT  | PR7A | DRIVE:8mA SLEW:FAST PULL:UP  |
+| UFMSDI    | 56/0     | LVCMOS33_OUT  | PR7C | DRIVE:8mA SLEW:FAST PULL:UP  |
+| UFMSDO    | 55/0     | LVCMOS33_IN   | PR7D | SLEW:FAST PULL:UP            |
+| nCCAS     | 27/1     | LVCMOS33_IN   | PL9B | SLEW:FAST PULL:UP            |
+| nCRAS     | 43/1     | LVCMOS33_IN   | PB4A | SLEW:FAST PULL:UP            |
+| nFWE      | 22/1     | LVCMOS33_IN   | PL8B | SLEW:FAST PULL:UP            |
+| nRCAS     | 78/0     | LVCMOS33_OUT  | PT5B | DRIVE:8mA SLEW:FAST PULL:UP  |
+| nRCS      | 77/0     | LVCMOS33_OUT  | PT5C | DRIVE:8mA SLEW:FAST PULL:UP  |
+| nRRAS     | 73/0     | LVCMOS33_OUT  | PR2B | DRIVE:8mA SLEW:FAST PULL:UP  |
+| nRWE      | 72/0     | LVCMOS33_OUT  | PR3A | DRIVE:8mA SLEW:FAST PULL:UP  |
+| nUFMCS    | 53/0     | LVCMOS33_OUT  | PR8B | DRIVE:8mA SLEW:FAST PULL:UP  |
++-----------+----------+---------------+------+------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 3.3V  |
+| 1    | 3.3V  |
++------+-------+
+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+---------------------+------------+---------------+------+---------------+
+| Pin/Bank | Pin Info            | Preference | Buffer Type   | Site | Dual Function |
++----------+---------------------+------------+---------------+------+---------------+
+| 1/1      | Dout[0]             | LOCATED    | LVCMOS33_OUT  | PL2A |               |
+| 2/1      | Dout[6]             | LOCATED    | LVCMOS33_OUT  | PL2B |               |
+| 3/1      | Dout[7]             | LOCATED    | LVCMOS33_OUT  | PL3A |               |
+| 4/1      | Dout[4]             | LOCATED    | LVCMOS33_OUT  | PL3B |               |
+| 5/1      | Dout[5]             | LOCATED    | LVCMOS33_OUT  | PL3C |               |
+| 6/1      | Dout[3]             | LOCATED    | LVCMOS33_OUT  | PL3D |               |
+| 7/1      | Dout[1]             | LOCATED    | LVCMOS33_OUT  | PL4A |               |
+| 8/1      | Dout[2]             | LOCATED    | LVCMOS33_OUT  | PL4B |               |
+| 9/1      |     unused, PULL:UP |            |               | PL5A |               |
+| 11/1     |     unused, PULL:UP |            |               | PL5B |               |
+| 13/1     |     unused, PULL:UP |            |               | PL5C |               |
+| 14/1     | Din[2]              | LOCATED    | LVCMOS33_IN   | PL5D | GSR_PADN      |
+| 15/1     | Din[1]              | LOCATED    | LVCMOS33_IN   | PL6A |               |
+| 16/1     | Din[3]              | LOCATED    | LVCMOS33_IN   | PL6B | TSALLPAD      |
+| 17/1     | Din[5]              | LOCATED    | LVCMOS33_IN   | PL7A |               |
+| 18/1     | Din[4]              | LOCATED    | LVCMOS33_IN   | PL7B |               |
+| 19/1     | Din[7]              | LOCATED    | LVCMOS33_IN   | PL7C |               |
+| 20/1     | Din[6]              | LOCATED    | LVCMOS33_IN   | PL7D |               |
+| 21/1     | Din[0]              | LOCATED    | LVCMOS33_IN   | PL8A |               |
+| 22/1     | nFWE                | LOCATED    | LVCMOS33_IN   | PL8B |               |
+| 23/1     | MAin[0]             | LOCATED    | LVCMOS33_IN   | PL9A |               |
+| 27/1     | nCCAS               | LOCATED    | LVCMOS33_IN   | PL9B |               |
+| 29/1     |     unused, PULL:UP |            |               | PB2A |               |
+| 30/1     |     unused, PULL:UP |            |               | PB2B |               |
+| 32/1     | CROW[0]             | LOCATED    | LVCMOS33_IN   | PB2C |               |
+| 34/1     | CROW[1]             | LOCATED    | LVCMOS33_IN   | PB2D |               |
+| 36/1     |     unused, PULL:UP |            |               | PB3A | PCLKT1_1      |
+| 37/1     | MAin[2]             | LOCATED    | LVCMOS33_IN   | PB3B |               |
+| 38/1     | MAin[1]             | LOCATED    | LVCMOS33_IN   | PB3C | PCLKT1_0      |
+| 39/1     | PHI2                | LOCATED    | LVCMOS33_IN   | PB3D |               |
+| 43/1     | nCRAS               | LOCATED    | LVCMOS33_IN   | PB4A |               |
+| 44/1     | MAin[7]             | LOCATED    | LVCMOS33_IN   | PB4B |               |
+| 45/1     | MAin[5]             | LOCATED    | LVCMOS33_IN   | PB4C |               |
+| 46/1     | MAin[4]             | LOCATED    | LVCMOS33_IN   | PB4D |               |
+| 47/1     | MAin[3]             | LOCATED    | LVCMOS33_IN   | PB5A |               |
+| 49/1     | MAin[6]             | LOCATED    | LVCMOS33_IN   | PB5C |               |
+| 50/1     | MAin[8]             | LOCATED    | LVCMOS33_IN   | PB5D |               |
+| 51/0     | MAin[9]             | LOCATED    | LVCMOS33_IN   | PR9B |               |
+| 52/0     |     unused, PULL:UP |            |               | PR9A |               |
+| 53/0     | nUFMCS              | LOCATED    | LVCMOS33_OUT  | PR8B |               |
+| 54/0     |     unused, PULL:UP |            |               | PR8A |               |
+| 55/0     | UFMSDO              | LOCATED    | LVCMOS33_IN   | PR7D |               |
+| 56/0     | UFMSDI              | LOCATED    | LVCMOS33_OUT  | PR7C |               |
+| 57/0     | LED                 | LOCATED    | LVCMOS33_OUT  | PR7B |               |
+| 58/0     | UFMCLK              | LOCATED    | LVCMOS33_OUT  | PR7A |               |
+| 59/0     |     unused, PULL:UP |            |               | PR6B |               |
+| 61/0     | RDQML               | LOCATED    | LVCMOS33_OUT  | PR6A |               |
+| 63/0     | RBA[0]              | LOCATED    | LVCMOS33_OUT  | PR5D |               |
+| 64/0     | RD[0]               | LOCATED    | LVCMOS33_BIDI | PR5C |               |
+| 65/0     | RD[1]               | LOCATED    | LVCMOS33_BIDI | PR5B |               |
+| 66/0     | RD[2]               | LOCATED    | LVCMOS33_BIDI | PR5A |               |
+| 67/0     | RD[3]               | LOCATED    | LVCMOS33_BIDI | PR4B |               |
+| 68/0     | RD[4]               | LOCATED    | LVCMOS33_BIDI | PR4A |               |
+| 69/0     | RD[5]               | LOCATED    | LVCMOS33_BIDI | PR3D |               |
+| 70/0     | RD[6]               | LOCATED    | LVCMOS33_BIDI | PR3C |               |
+| 71/0     | RD[7]               | LOCATED    | LVCMOS33_BIDI | PR3B |               |
+| 72/0     | nRWE                | LOCATED    | LVCMOS33_OUT  | PR3A |               |
+| 73/0     | nRRAS               | LOCATED    | LVCMOS33_OUT  | PR2B |               |
+| 76/0     | RDQMH               | LOCATED    | LVCMOS33_OUT  | PR2A |               |
+| 77/0     | nRCS                | LOCATED    | LVCMOS33_OUT  | PT5C |               |
+| 78/0     | nRCAS               | LOCATED    | LVCMOS33_OUT  | PT5B |               |
+| 79/0     | RA[11]              | LOCATED    | LVCMOS33_OUT  | PT5A |               |
+| 80/0     |     unused, PULL:UP |            |               | PT4F |               |
+| 81/0     |     unused, PULL:UP |            |               | PT4E |               |
+| 82/0     | RCKE                | LOCATED    | LVCMOS33_OUT  | PT4D |               |
+| 83/0     | RBA[1]              | LOCATED    | LVCMOS33_OUT  | PT4C |               |
+| 85/0     | RA[9]               | LOCATED    | LVCMOS33_OUT  | PT4B | PCLKT0_1      |
+| 86/0     | RCLK                | LOCATED    | LVCMOS33_IN   | PT4A | PCLKT0_0      |
+| 87/0     | RA[10]              | LOCATED    | LVCMOS33_OUT  | PT3D |               |
+| 89/0     | RA[1]               | LOCATED    | LVCMOS33_OUT  | PT3C |               |
+| 91/0     | RA[6]               | LOCATED    | LVCMOS33_OUT  | PT3B |               |
+| 94/0     | RA[2]               | LOCATED    | LVCMOS33_OUT  | PT3A |               |
+| 95/0     | RA[5]               | LOCATED    | LVCMOS33_OUT  | PT2F |               |
+| 96/0     | RA[8]               | LOCATED    | LVCMOS33_OUT  | PT2E |               |
+| 97/0     | RA[3]               | LOCATED    | LVCMOS33_OUT  | PT2D |               |
+| 98/0     | RA[0]               | LOCATED    | LVCMOS33_OUT  | PT2C |               |
+| 99/0     | RA[4]               | LOCATED    | LVCMOS33_OUT  | PT2B |               |
+| 100/0    | RA[7]               | LOCATED    | LVCMOS33_OUT  | PT2A |               |
+| PB5B/0   |     unused, PULL:UP |            |               | PB5B |               |
+| PT5D/0   |     unused, PULL:UP |            |               | PT5D |               |
+| TCK/1    |                     |            |               | TCK  | TCK           |
+| TDI/1    |                     |            |               | TDI  | TDI           |
+| TDO/1    |                     |            |               | TDO  | TDO           |
+| TMS/1    |                     |            |               | TMS  | TMS           |
++----------+---------------------+------------+---------------+------+---------------+
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "CROW[0]"  SITE  "32";
+LOCATE  COMP  "CROW[1]"  SITE  "34";
+LOCATE  COMP  "Din[0]"  SITE  "21";
+LOCATE  COMP  "Din[1]"  SITE  "15";
+LOCATE  COMP  "Din[2]"  SITE  "14";
+LOCATE  COMP  "Din[3]"  SITE  "16";
+LOCATE  COMP  "Din[4]"  SITE  "18";
+LOCATE  COMP  "Din[5]"  SITE  "17";
+LOCATE  COMP  "Din[6]"  SITE  "20";
+LOCATE  COMP  "Din[7]"  SITE  "19";
+LOCATE  COMP  "Dout[0]"  SITE  "1";
+LOCATE  COMP  "Dout[1]"  SITE  "7";
+LOCATE  COMP  "Dout[2]"  SITE  "8";
+LOCATE  COMP  "Dout[3]"  SITE  "6";
+LOCATE  COMP  "Dout[4]"  SITE  "4";
+LOCATE  COMP  "Dout[5]"  SITE  "5";
+LOCATE  COMP  "Dout[6]"  SITE  "2";
+LOCATE  COMP  "Dout[7]"  SITE  "3";
+LOCATE  COMP  "LED"  SITE  "57";
+LOCATE  COMP  "MAin[0]"  SITE  "23";
+LOCATE  COMP  "MAin[1]"  SITE  "38";
+LOCATE  COMP  "MAin[2]"  SITE  "37";
+LOCATE  COMP  "MAin[3]"  SITE  "47";
+LOCATE  COMP  "MAin[4]"  SITE  "46";
+LOCATE  COMP  "MAin[5]"  SITE  "45";
+LOCATE  COMP  "MAin[6]"  SITE  "49";
+LOCATE  COMP  "MAin[7]"  SITE  "44";
+LOCATE  COMP  "MAin[8]"  SITE  "50";
+LOCATE  COMP  "MAin[9]"  SITE  "51";
+LOCATE  COMP  "PHI2"  SITE  "39";
+LOCATE  COMP  "RA[0]"  SITE  "98";
+LOCATE  COMP  "RA[10]"  SITE  "87";
+LOCATE  COMP  "RA[11]"  SITE  "79";
+LOCATE  COMP  "RA[1]"  SITE  "89";
+LOCATE  COMP  "RA[2]"  SITE  "94";
+LOCATE  COMP  "RA[3]"  SITE  "97";
+LOCATE  COMP  "RA[4]"  SITE  "99";
+LOCATE  COMP  "RA[5]"  SITE  "95";
+LOCATE  COMP  "RA[6]"  SITE  "91";
+LOCATE  COMP  "RA[7]"  SITE  "100";
+LOCATE  COMP  "RA[8]"  SITE  "96";
+LOCATE  COMP  "RA[9]"  SITE  "85";
+LOCATE  COMP  "RBA[0]"  SITE  "63";
+LOCATE  COMP  "RBA[1]"  SITE  "83";
+LOCATE  COMP  "RCKE"  SITE  "82";
+LOCATE  COMP  "RCLK"  SITE  "86";
+LOCATE  COMP  "RDQMH"  SITE  "76";
+LOCATE  COMP  "RDQML"  SITE  "61";
+LOCATE  COMP  "RD[0]"  SITE  "64";
+LOCATE  COMP  "RD[1]"  SITE  "65";
+LOCATE  COMP  "RD[2]"  SITE  "66";
+LOCATE  COMP  "RD[3]"  SITE  "67";
+LOCATE  COMP  "RD[4]"  SITE  "68";
+LOCATE  COMP  "RD[5]"  SITE  "69";
+LOCATE  COMP  "RD[6]"  SITE  "70";
+LOCATE  COMP  "RD[7]"  SITE  "71";
+LOCATE  COMP  "UFMCLK"  SITE  "58";
+LOCATE  COMP  "UFMSDI"  SITE  "56";
+LOCATE  COMP  "UFMSDO"  SITE  "55";
+LOCATE  COMP  "nCCAS"  SITE  "27";
+LOCATE  COMP  "nCRAS"  SITE  "43";
+LOCATE  COMP  "nFWE"  SITE  "22";
+LOCATE  COMP  "nRCAS"  SITE  "78";
+LOCATE  COMP  "nRCS"  SITE  "77";
+LOCATE  COMP  "nRRAS"  SITE  "73";
+LOCATE  COMP  "nRWE"  SITE  "72";
+LOCATE  COMP  "nUFMCS"  SITE  "53";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 15 05:03:28 2023
+
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_par.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_par.html new file mode 100644 index 0000000..f78605b --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_par.html @@ -0,0 +1,331 @@ + +Place & Route Report + + +
    PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 15 05:03:23 2023
+
+C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO256C_impl1.p2t
+RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir
+RAM2GS_LCMXO256C_impl1.prf -gui -msgset
+D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml
+
+
+Preference file: RAM2GS_LCMXO256C_impl1.prf.
+
+Cost Table Summary
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            -10.044      913247       0.273        0            06           Completed
+* : Design saved.
+
+Total (real) run time for 1-seed: 6 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd"
+Tue Aug 15 05:03:23 2023
+
+
+Best Par Run
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir/5_1.ncd RAM2GS_LCMXO256C_impl1.prf
+Preference file: RAM2GS_LCMXO256C_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file RAM2GS_LCMXO256C_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 3
+Loading device for application par from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+
+Device utilization summary:
+
+   PIO (prelim)      67/79           84% used
+                     67/78           85% bonded
+   SLICE             71/128          55% used
+
+
+
+Number of Signals: 262
+Number of Connections: 662
+
+Pin Constraint Summary:
+   67 out of 67 pins locked (100% locked).
+
+The following 2 signals are selected to use the primary clock routing resources:
+    RCLK_c (driver: RCLK, clk load #: 40)
+    PHI2_c (driver: PHI2, clk load #: 13)
+
+The following 1 signal is selected to use the secondary clock routing resources:
+    nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0)
+
+No signal is selected as Global Set/Reset.
+Starting Placer Phase 0.
+........
+Finished Placer Phase 0.  REAL time: 0 secs 
+
+Starting Placer Phase 1.
+..............
+Placer score = 831129.
+Finished Placer Phase 1.  REAL time: 5 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  828350
+Finished Placer Phase 2.  REAL time: 5 secs 
+
+
+
+Clock Report
+
+Global Clock Resources:
+  CLK_PIN    : 1 out of 4 (25%)
+  General PIO: 1 out of 80 (1%)
+
+Global Clocks:
+  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT4A)", clk load = 40
+  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB3D)", clk load = 13
+  SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB4A)", clk load = 7, ce load = 0, sr load = 0
+
+  PRIMARY  : 2 out of 4 (50%)
+  SECONDARY: 1 out of 4 (25%)
+
+
+
+
+I/O Usage Summary (final):
+   67 out of 79 (84.8%) PIO sites used.
+   67 out of 78 (85.9%) bonded PIO sites used.
+   Number of PIO comps: 67; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+------------+------------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
++----------+----------------+------------+------------+------------+
+| 0        | 36 / 41 ( 87%) | 3.3V       | -          | -          |
+| 1        | 31 / 37 ( 83%) | 3.3V       | -          | -          |
++----------+----------------+------------+------------+------------+
+
+Total placer CPU time: 4 secs 
+
+Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
+
+0 connections routed; 662 unrouted.
+Starting router resource preassignment
+WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
+WARNING - par: The driver of secondary clock net nCRAS_c is not placed on one of the PIO sites dedicated for secondary clocks.  This secondary clock will be routed through general routing resource and may suffer from excessive delay or skew.
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=nCCAS_c loads=7 clock_loads=4
+
+Completed router resource preassignment. Real time: 5 secs 
+
+Start NBR router at 05:03:28 08/15/23
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 05:03:28 08/15/23
+
+Start NBR section for initial routing at 05:03:28 08/15/23
+Level 1, iteration 1
+0(0.00%) conflict; 563(85.05%) untouched conns; 712361 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -9.968ns/-712.361ns; real time: 5 secs 
+Level 2, iteration 1
+3(0.02%) conflicts; 494(74.62%) untouched conns; 697746 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-697.746ns; real time: 5 secs 
+Level 3, iteration 1
+6(0.05%) conflicts; 255(38.52%) untouched conns; 756550 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-756.550ns; real time: 5 secs 
+Level 4, iteration 1
+17(0.14%) conflicts; 0(0.00%) untouched conn; 761255 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-761.256ns; real time: 5 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 05:03:28 08/15/23
+Level 4, iteration 1
+12(0.10%) conflicts; 0(0.00%) untouched conn; 765605 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-765.606ns; real time: 5 secs 
+Level 4, iteration 2
+6(0.05%) conflicts; 0(0.00%) untouched conn; 766423 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-766.424ns; real time: 5 secs 
+Level 4, iteration 3
+3(0.02%) conflicts; 0(0.00%) untouched conn; 769148 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-769.149ns; real time: 5 secs 
+Level 4, iteration 4
+3(0.02%) conflicts; 0(0.00%) untouched conn; 769148 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-769.149ns; real time: 5 secs 
+Level 4, iteration 5
+3(0.02%) conflicts; 0(0.00%) untouched conn; 766523 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-766.524ns; real time: 5 secs 
+Level 4, iteration 6
+1(0.01%) conflict; 0(0.00%) untouched conn; 766523 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-766.524ns; real time: 5 secs 
+Level 4, iteration 7
+1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-772.930ns; real time: 6 secs 
+Level 4, iteration 8
+1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-772.930ns; real time: 6 secs 
+Level 4, iteration 9
+1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-772.930ns; real time: 6 secs 
+Level 4, iteration 10
+0(0.00%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-772.930ns; real time: 6 secs 
+
+Start NBR section for performance tuning (iteration 1) at 05:03:29 08/15/23
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-772.930ns; real time: 6 secs 
+
+Start NBR section for re-routing at 05:03:29 08/15/23
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 768048 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-768.049ns; real time: 6 secs 
+
+Start NBR section for post-routing at 05:03:29 08/15/23
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 256 (38.67%)
+  Estimated worst slack<setup> : -10.044ns
+  Timing score<setup> : 913247
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=nCCAS_c loads=7 clock_loads=4
+
+Total CPU time 5 secs 
+Total REAL time: 6 secs 
+Completely routed.
+End of route.  662 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 913247 
+
+Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack<setup/<ns>> = -10.044
+PAR_SUMMARY::Timing score<setup/<ns>> = 913.247
+PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.273
+PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 5 secs 
+Total REAL time to completion: 6 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_summary.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_summary.html new file mode 100644 index 0000000..3f88aa1 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_summary.html @@ -0,0 +1,83 @@ + +Project Summary + + +
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    RAM2GS_LCMXO256C project summary
    Module Name:RAM2GS_LCMXO256CSynthesis:Lattice LSE
    Implementation Name:impl1Strategy Name:Strategy1
    Last Process:JEDEC FileState:Passed
    Target Device:LCMXO256C-3T100CDevice Family:MachXO
    Device Type:LCMXO256CPackage Type:TQFP100
    Performance grade:3Operating conditions:COM
    Logic preference file:RAM2GS_LCMXO256C.lpf
    Physical Preference file:impl1/RAM2GS_LCMXO256C_impl1.prf
    Product Version:3.12.1.454Patch Version:
    Updated:2023/08/15 05:03:37
    Implementation Location:D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1
    Project File:D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ldf
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_tw1.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_tw1.html new file mode 100644 index 0000000..40eaf8f --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_tw1.html @@ -0,0 +1,434 @@ + +Lattice Map TRACE Report + + +
    Map TRACE Report
+
+Loading design for application trce from file ram2gs_lcmxo256c_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 3
+Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
+Tue Aug 15 05:03:21 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf 
+Design file:     ram2gs_lcmxo256c_impl1_map.ncd
+Preference file: ram2gs_lcmxo256c_impl1.prf
+Device,speed:    LCMXO256C,3
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "RCLK_c" 283.768000 MHz (213 errors)
    • 
+                383 items scored, 213 timing errors detected.
+Warning: 116.104MHz is the maximum frequency for this preference.
+
+
  • FREQUENCY NET "PHI2_c" 120.077000 MHz (97 errors)
    • 
+                106 items scored, 97 timing errors detected.
+Warning:  42.739MHz is the maximum frequency for this preference.
+
+Report Type:     based on TRACE automatically generated preferences
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
+            383 items scored, 213 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 5.089ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i14  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_418  (to RCLK_c +)
+
+   Delay:               8.369ns  (24.4% logic, 75.6% route), 5 logic levels.
+
+ Constraint Details:
+
+      8.369ns physical path delay SLICE_1 to SLICE_56 exceeds
+      3.524ns delay constraint less
+      0.244ns CE_SET requirement (totaling 3.280ns) by 5.089ns
+
+ Physical Path Details:
+
+      Data path SLICE_1 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560    SLICE_1.CLK to     SLICE_1.Q0 SLICE_1 (from RCLK_c)
+ROUTE         5   e 1.441     SLICE_1.Q0 to    SLICE_90.C1 FS_14
+CTOF_DEL    ---     0.371    SLICE_90.C1 to    SLICE_90.F1 SLICE_90
+ROUTE         1   e 1.441    SLICE_90.F1 to    SLICE_75.B0 n2328
+CTOF_DEL    ---     0.371    SLICE_75.B0 to    SLICE_75.F0 SLICE_75
+ROUTE         2   e 1.441    SLICE_75.F0 to    SLICE_87.B1 n2214
+CTOF_DEL    ---     0.371    SLICE_87.B1 to    SLICE_87.F1 SLICE_87
+ROUTE         1   e 0.561    SLICE_87.F1 to    SLICE_87.A0 n7
+CTOF_DEL    ---     0.371    SLICE_87.A0 to    SLICE_87.F0 SLICE_87
+ROUTE         1   e 1.441    SLICE_87.F0 to    SLICE_56.CE RCLK_c_enable_11 (to RCLK_c)
+                  --------
+                    8.369   (24.4% logic, 75.6% route), 5 logic levels.
+
+Warning: 116.104MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
+            106 items scored, 97 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 7.535ns (weighted slack = -15.070ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:              11.061ns  (21.8% logic, 78.2% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.061ns physical path delay SLICE_88 to SLICE_14 exceeds
+      4.164ns delay constraint less
+      0.638ns LSR_SET requirement (totaling 3.526ns) by 7.535ns
+
+ Physical Path Details:
+
+      Data path SLICE_88 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_88.CLK to    SLICE_88.Q0 SLICE_88 (from PHI2_c)
+ROUTE         1   e 1.441    SLICE_88.Q0 to    SLICE_97.D0 Bank_0
+CTOF_DEL    ---     0.371    SLICE_97.D0 to    SLICE_97.F0 SLICE_97
+ROUTE         1   e 1.441    SLICE_97.F0 to    SLICE_81.B0 n2314
+CTOF_DEL    ---     0.371    SLICE_81.B0 to    SLICE_81.F0 SLICE_81
+ROUTE         1   e 1.441    SLICE_81.F0 to    SLICE_18.B1 n26
+CTOF_DEL    ---     0.371    SLICE_18.B1 to    SLICE_18.F1 SLICE_18
+ROUTE         8   e 1.441    SLICE_18.F1 to    SLICE_89.B0 n1326
+CTOF_DEL    ---     0.371    SLICE_89.B0 to    SLICE_89.F0 SLICE_89
+ROUTE         1   e 1.441    SLICE_89.F0 to    SLICE_79.C0 n1280
+CTOF_DEL    ---     0.371    SLICE_79.C0 to    SLICE_79.F0 SLICE_79
+ROUTE         2   e 1.441    SLICE_79.F0 to   SLICE_14.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                   11.061   (21.8% logic, 78.2% route), 6 logic levels.
+
+Warning:  42.739MHz is the maximum frequency for this preference.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "RCLK_c" 283.768000 MHz ; |  283.768 MHz|  116.104 MHz|   5 *
+                                        |             |             |
+FREQUENCY NET "PHI2_c" 120.077000 MHz ; |  120.077 MHz|   42.739 MHz|   6 *
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+2 preferences(marked by "*" above) not met.
+
+----------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+----------------------------------------------------------------------------
+n1326                                   |       8|      96|     30.97%
+                                        |        |        |
+n26                                     |       1|      72|     23.23%
+                                        |        |        |
+----------------------------------------------------------------------------
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
+   Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 310  Score: 1346529
+Cumulative negative slack: 874289
+
+Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
+Tue Aug 15 05:03:21 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf 
+Design file:     ram2gs_lcmxo256c_impl1_map.ncd
+Preference file: ram2gs_lcmxo256c_impl1.prf
+Device,speed:    LCMXO256C,M
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "RCLK_c" 283.768000 MHz (0 errors)
    •             383 items scored, 0 timing errors detected.
+
+
  • FREQUENCY NET "PHI2_c" 120.077000 MHz (0 errors)
    •             106 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
+            383 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.342ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i4  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i5  (to RCLK_c +)
+
+   Delay:               0.325ns  (38.8% logic, 61.2% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.325ns physical path delay SLICE_100 to SLICE_100 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint requirement (totaling -0.017ns) by 0.342ns
+
+ Physical Path Details:
+
+      Data path SLICE_100 to SLICE_100:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126  SLICE_100.CLK to   SLICE_100.Q0 SLICE_100 (from RCLK_c)
+ROUTE         1   e 0.199   SLICE_100.Q0 to   SLICE_100.M1 n736 (to RCLK_c)
+                  --------
+                    0.325   (38.8% logic, 61.2% route), 1 logic levels.
+
+
+================================================================================
+Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
+            106 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.430ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_406  (from PHI2_c -)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               0.411ns  (51.3% logic, 48.7% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.411ns physical path delay SLICE_14 to SLICE_14 meets
+     -0.019ns DIN_HLD and
+      0.000ns delay constraint requirement (totaling -0.019ns) by 0.430ns
+
+ Physical Path Details:
+
+      Data path SLICE_14 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137   SLICE_14.CLK to    SLICE_14.Q0 SLICE_14 (from PHI2_c)
+ROUTE         2   e 0.199    SLICE_14.Q0 to    SLICE_14.C0 C1Submitted
+CTOF_DEL    ---     0.074    SLICE_14.C0 to    SLICE_14.F0 SLICE_14
+ROUTE         1   e 0.001    SLICE_14.F0 to   SLICE_14.DI0 n6_adj_3 (to PHI2_c)
+                  --------
+                    0.411   (51.3% logic, 48.7% route), 2 logic levels.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "RCLK_c" 283.768000 MHz ; |     0.000 ns|     0.342 ns|   1  
+                                        |             |             |
+FREQUENCY NET "PHI2_c" 120.077000 MHz ; |     0.000 ns|     0.430 ns|   2  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
+   Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 310 (setup), 0 (hold)
+Score: 1346529 (setup), 0 (hold)
+Cumulative negative slack: 874289 (874289+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_twr.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_twr.html new file mode 100644 index 0000000..d7e5a9f --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_twr.html @@ -0,0 +1,2251 @@ + +Lattice TRACE Report + + +
    Place & Route TRACE Report
+
+Loading design for application trce from file ram2gs_lcmxo256c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 3
+Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
+Tue Aug 15 05:03:29 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf 
+Design file:     ram2gs_lcmxo256c_impl1.ncd
+Preference file: ram2gs_lcmxo256c_impl1.prf
+Device,speed:    LCMXO256C,3
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "RCLK_c" 283.768000 MHz (231 errors)
    • 
+                383 items scored, 231 timing errors detected.
+Warning: 129.769MHz is the maximum frequency for this preference.
+
+
  • FREQUENCY NET "PHI2_c" 120.077000 MHz (95 errors)
    • 
+                106 items scored, 95 timing errors detected.
+Warning:  54.431MHz is the maximum frequency for this preference.
+
+Report Type:     based on TRACE automatically generated preferences
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
+            383 items scored, 231 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 4.182ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i17  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
+
+   Delay:               7.525ns  (27.2% logic, 72.8% route), 5 logic levels.
+
+ Constraint Details:
+
+      7.525ns physical path delay SLICE_8 to SLICE_43 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 3.343ns) by 4.182ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C5A.CLK to       R5C5A.Q1 SLICE_8 (from RCLK_c)
+ROUTE         4     1.509       R5C5A.Q1 to       R6C4C.A1 FS_17
+CTOF_DEL    ---     0.371       R6C4C.A1 to       R6C4C.F1 SLICE_68
+ROUTE         2     1.503       R6C4C.F1 to       R7C5B.A1 n2471
+CTOF_DEL    ---     0.371       R7C5B.A1 to       R7C5B.F1 SLICE_44
+ROUTE         2     1.972       R7C5B.F1 to       R3C2B.C1 n2462
+CTOF_DEL    ---     0.371       R3C2B.C1 to       R3C2B.F1 SLICE_43
+ROUTE         1     0.497       R3C2B.F1 to       R3C2B.C0 n1160
+CTOF_DEL    ---     0.371       R3C2B.C0 to       R3C2B.F0 SLICE_43
+ROUTE         1     0.000       R3C2B.F0 to      R3C2B.DI0 UFMCLK_N_224 (to RCLK_c)
+                  --------
+                    7.525   (27.2% logic, 72.8% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R5C5A.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R3C2B.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 3.947ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i16  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
+
+   Delay:               7.290ns  (28.0% logic, 72.0% route), 5 logic levels.
+
+ Constraint Details:
+
+      7.290ns physical path delay SLICE_8 to SLICE_43 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 3.343ns) by 3.947ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C5A.CLK to       R5C5A.Q0 SLICE_8 (from RCLK_c)
+ROUTE         5     1.526       R5C5A.Q0 to       R5C2D.A0 FS_16
+CTOF_DEL    ---     0.371       R5C2D.A0 to       R5C2D.F0 SLICE_90
+ROUTE         1     1.251       R5C2D.F0 to       R7C5B.D1 n2470
+CTOF_DEL    ---     0.371       R7C5B.D1 to       R7C5B.F1 SLICE_44
+ROUTE         2     1.972       R7C5B.F1 to       R3C2B.C1 n2462
+CTOF_DEL    ---     0.371       R3C2B.C1 to       R3C2B.F1 SLICE_43
+ROUTE         1     0.497       R3C2B.F1 to       R3C2B.C0 n1160
+CTOF_DEL    ---     0.371       R3C2B.C0 to       R3C2B.F0 SLICE_43
+ROUTE         1     0.000       R3C2B.F0 to      R3C2B.DI0 UFMCLK_N_224 (to RCLK_c)
+                  --------
+                    7.290   (28.0% logic, 72.0% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R5C5A.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R3C2B.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 3.864ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i12  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_418  (to RCLK_c +)
+
+   Delay:               7.144ns  (28.6% logic, 71.4% route), 5 logic levels.
+
+ Constraint Details:
+
+      7.144ns physical path delay SLICE_3 to SLICE_56 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 3.280ns) by 3.864ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C4C.CLK to       R5C4C.Q0 SLICE_3 (from RCLK_c)
+ROUTE         4     2.038       R5C4C.Q0 to       R5C2D.B1 FS_12
+CTOF_DEL    ---     0.371       R5C2D.B1 to       R5C2D.F1 SLICE_90
+ROUTE         1     0.887       R5C2D.F1 to       R4C2D.C0 n2328
+CTOF_DEL    ---     0.371       R4C2D.C0 to       R4C2D.F0 SLICE_75
+ROUTE         2     0.513       R4C2D.F0 to       R4C2C.C1 n2214
+CTOF_DEL    ---     0.371       R4C2C.C1 to       R4C2C.F1 SLICE_87
+ROUTE         1     0.497       R4C2C.F1 to       R4C2C.C0 n7
+CTOF_DEL    ---     0.371       R4C2C.C0 to       R4C2C.F0 SLICE_87
+ROUTE         1     1.165       R4C2C.F0 to       R6C2C.CE RCLK_c_enable_11 (to RCLK_c)
+                  --------
+                    7.144   (28.6% logic, 71.4% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R5C4C.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R6C2C.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 3.702ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i13  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
+
+   Delay:               7.045ns  (29.0% logic, 71.0% route), 5 logic levels.
+
+ Constraint Details:
+
+      7.045ns physical path delay SLICE_3 to SLICE_43 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 3.343ns) by 3.702ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C4C.CLK to       R5C4C.Q1 SLICE_3 (from RCLK_c)
+ROUTE         3     1.057       R5C4C.Q1 to       R5C2B.A1 FS_13
+CTOF_DEL    ---     0.371       R5C2B.A1 to       R5C2B.F1 SLICE_94
+ROUTE         3     1.475       R5C2B.F1 to       R7C5B.C1 n2272
+CTOF_DEL    ---     0.371       R7C5B.C1 to       R7C5B.F1 SLICE_44
+ROUTE         2     1.972       R7C5B.F1 to       R3C2B.C1 n2462
+CTOF_DEL    ---     0.371       R3C2B.C1 to       R3C2B.F1 SLICE_43
+ROUTE         1     0.497       R3C2B.F1 to       R3C2B.C0 n1160
+CTOF_DEL    ---     0.371       R3C2B.C0 to       R3C2B.F0 SLICE_43
+ROUTE         1     0.000       R3C2B.F0 to      R3C2B.DI0 UFMCLK_N_224 (to RCLK_c)
+                  --------
+                    7.045   (29.0% logic, 71.0% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R5C4C.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R3C2B.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 3.669ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i11  (from RCLK_c +)
+   Destination:    FF         Data in        InitReady_394  (to RCLK_c +)
+
+   Delay:               6.949ns  (24.1% logic, 75.9% route), 4 logic levels.
+
+ Constraint Details:
+
+      6.949ns physical path delay SLICE_5 to SLICE_25 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 3.280ns) by 3.669ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to SLICE_25:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C4B.CLK to       R5C4B.Q1 SLICE_5 (from RCLK_c)
+ROUTE         8     1.895       R5C4B.Q1 to       R5C2B.C0 FS_11
+CTOF_DEL    ---     0.371       R5C2B.C0 to       R5C2B.F0 SLICE_94
+ROUTE         1     0.694       R5C2B.F0 to       R3C2A.D1 n12
+CTOF_DEL    ---     0.371       R3C2A.D1 to       R3C2A.F1 SLICE_69
+ROUTE         3     1.057       R3C2A.F1 to       R5C2C.A1 n62
+CTOF_DEL    ---     0.371       R5C2C.A1 to       R5C2C.F1 SLICE_95
+ROUTE         1     1.630       R5C2C.F1 to       R6C2A.CE RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    6.949   (24.1% logic, 75.9% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R5C4B.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_25:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R6C2A.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 3.582ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i12  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
+
+   Delay:               6.925ns  (29.5% logic, 70.5% route), 5 logic levels.
+
+ Constraint Details:
+
+      6.925ns physical path delay SLICE_3 to SLICE_43 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 3.343ns) by 3.582ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C4C.CLK to       R5C4C.Q0 SLICE_3 (from RCLK_c)
+ROUTE         4     0.909       R5C4C.Q0 to       R6C4C.C1 FS_12
+CTOF_DEL    ---     0.371       R6C4C.C1 to       R6C4C.F1 SLICE_68
+ROUTE         2     1.503       R6C4C.F1 to       R7C5B.A1 n2471
+CTOF_DEL    ---     0.371       R7C5B.A1 to       R7C5B.F1 SLICE_44
+ROUTE         2     1.972       R7C5B.F1 to       R3C2B.C1 n2462
+CTOF_DEL    ---     0.371       R3C2B.C1 to       R3C2B.F1 SLICE_43
+ROUTE         1     0.497       R3C2B.F1 to       R3C2B.C0 n1160
+CTOF_DEL    ---     0.371       R3C2B.C0 to       R3C2B.F0 SLICE_43
+ROUTE         1     0.000       R3C2B.F0 to      R3C2B.DI0 UFMCLK_N_224 (to RCLK_c)
+                  --------
+                    6.925   (29.5% logic, 70.5% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R5C4C.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R3C2B.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 3.567ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CASr3_384  (from RCLK_c +)
+   Destination:    FF         Data in        nRCS_396  (to RCLK_c +)
+
+   Delay:               6.910ns  (31.5% logic, 68.5% route), 5 logic levels.
+
+ Constraint Details:
+
+      6.910ns physical path delay SLICE_68 to SLICE_60 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 3.343ns) by 3.567ns
+
+ Physical Path Details:
+
+      Data path SLICE_68 to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R6C4C.CLK to       R6C4C.Q1 SLICE_68 (from RCLK_c)
+ROUTE         2     1.364       R6C4C.Q1 to       R8C5C.C0 CASr3
+CTOF_DEL    ---     0.371       R8C5C.C0 to       R8C5C.F0 SLICE_74
+ROUTE         2     0.513       R8C5C.F0 to       R8C5C.C1 n1
+CTOF_DEL    ---     0.371       R8C5C.C1 to       R8C5C.F1 SLICE_74
+ROUTE         2     1.276       R8C5C.F1 to       R8C4D.M0 n15_adj_1
+MTOOFX_DEL  ---     0.501       R8C4D.M0 to     R8C4D.OFX0 i2099/SLICE_72
+ROUTE         1     1.583     R8C4D.OFX0 to       R2C5B.A0 n2481
+CTOF_DEL    ---     0.371       R2C5B.A0 to       R2C5B.F0 SLICE_60
+ROUTE         1     0.000       R2C5B.F0 to      R2C5B.DI0 nRCS_N_136 (to RCLK_c)
+                  --------
+                    6.910   (31.5% logic, 68.5% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_68:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R6C4C.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R2C5B.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 3.552ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i12  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_419  (to RCLK_c +)
+
+   Delay:               6.832ns  (24.5% logic, 75.5% route), 4 logic levels.
+
+ Constraint Details:
+
+      6.832ns physical path delay SLICE_3 to SLICE_26 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 3.280ns) by 3.552ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C4C.CLK to       R5C4C.Q0 SLICE_3 (from RCLK_c)
+ROUTE         4     2.038       R5C4C.Q0 to       R5C2D.B1 FS_12
+CTOF_DEL    ---     0.371       R5C2D.B1 to       R5C2D.F1 SLICE_90
+ROUTE         1     0.887       R5C2D.F1 to       R4C2D.C0 n2328
+CTOF_DEL    ---     0.371       R4C2D.C0 to       R4C2D.F0 SLICE_75
+ROUTE         2     0.513       R4C2D.F0 to       R4C2D.C1 n2214
+CTOF_DEL    ---     0.371       R4C2D.C1 to       R4C2D.F1 SLICE_75
+ROUTE         1     1.721       R4C2D.F1 to       R7C5A.CE RCLK_c_enable_12 (to RCLK_c)
+                  --------
+                    6.832   (24.5% logic, 75.5% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R5C4C.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R7C5A.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 3.405ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i17  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
+
+   Delay:               6.303ns  (26.5% logic, 73.5% route), 4 logic levels.
+
+ Constraint Details:
+
+      6.303ns physical path delay SLICE_8 to SLICE_43 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.626ns LSR_SET requirement (totaling 2.898ns) by 3.405ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C5A.CLK to       R5C5A.Q1 SLICE_8 (from RCLK_c)
+ROUTE         4     1.509       R5C5A.Q1 to       R6C4C.A1 FS_17
+CTOF_DEL    ---     0.371       R6C4C.A1 to       R6C4C.F1 SLICE_68
+ROUTE         2     1.042       R6C4C.F1 to       R6C2D.A1 n2471
+CTOF_DEL    ---     0.371       R6C2D.A1 to       R6C2D.F1 SLICE_78
+ROUTE         3     0.528       R6C2D.F1 to       R6C2D.C0 n2464
+CTOF_DEL    ---     0.371       R6C2D.C0 to       R6C2D.F0 SLICE_78
+ROUTE         2     1.551       R6C2D.F0 to      R3C2B.LSR n1846 (to RCLK_c)
+                  --------
+                    6.303   (26.5% logic, 73.5% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R5C5A.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R3C2B.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 3.361ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i15  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
+
+   Delay:               6.704ns  (30.5% logic, 69.5% route), 5 logic levels.
+
+ Constraint Details:
+
+      6.704ns physical path delay SLICE_1 to SLICE_43 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 3.343ns) by 3.361ns
+
+ Physical Path Details:
+
+      Data path SLICE_1 to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C4D.CLK to       R5C4D.Q1 SLICE_1 (from RCLK_c)
+ROUTE         3     0.716       R5C4D.Q1 to       R5C2B.D1 FS_15
+CTOF_DEL    ---     0.371       R5C2B.D1 to       R5C2B.F1 SLICE_94
+ROUTE         3     1.475       R5C2B.F1 to       R7C5B.C1 n2272
+CTOF_DEL    ---     0.371       R7C5B.C1 to       R7C5B.F1 SLICE_44
+ROUTE         2     1.972       R7C5B.F1 to       R3C2B.C1 n2462
+CTOF_DEL    ---     0.371       R3C2B.C1 to       R3C2B.F1 SLICE_43
+ROUTE         1     0.497       R3C2B.F1 to       R3C2B.C0 n1160
+CTOF_DEL    ---     0.371       R3C2B.C0 to       R3C2B.F0 SLICE_43
+ROUTE         1     0.000       R3C2B.F0 to      R3C2B.DI0 UFMCLK_N_224 (to RCLK_c)
+                  --------
+                    6.704   (30.5% logic, 69.5% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R5C4D.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R3C2B.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+Warning: 129.769MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
+            106 items scored, 95 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 5.022ns (weighted slack = -10.044ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               8.548ns  (28.3% logic, 71.7% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.548ns physical path delay SLICE_88 to SLICE_14 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.638ns LSR_SET requirement (totaling 3.526ns) by 5.022ns
+
+ Physical Path Details:
+
+      Data path SLICE_88 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R4C3D.CLK to       R4C3D.Q0 SLICE_88 (from PHI2_c)
+ROUTE         1     1.155       R4C3D.Q0 to       R2C2A.D0 Bank_0
+CTOF_DEL    ---     0.371       R2C2A.D0 to       R2C2A.F0 SLICE_97
+ROUTE         1     1.348       R2C2A.F0 to       R4C4A.C0 n2314
+CTOF_DEL    ---     0.371       R4C4A.C0 to       R4C4A.F0 SLICE_81
+ROUTE         1     0.626       R4C4A.F0 to       R4C4D.D1 n26
+CTOF_DEL    ---     0.371       R4C4D.D1 to       R4C4D.F1 SLICE_18
+ROUTE         8     1.225       R4C4D.F1 to       R5C5B.D0 n1326
+CTOF_DEL    ---     0.371       R5C5B.D0 to       R5C5B.F0 SLICE_89
+ROUTE         1     0.700       R5C5B.F0 to       R6C5C.D0 n1280
+CTOF_DEL    ---     0.371       R6C5C.D0 to       R6C5C.F0 SLICE_79
+ROUTE         2     1.079       R6C5C.F0 to      R5C5D.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    8.548   (28.3% logic, 71.7% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R4C3D.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R5C5D.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 5.022ns (weighted slack = -10.044ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        ADSubmitted_407  (to PHI2_c -)
+
+   Delay:               8.548ns  (28.3% logic, 71.7% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.548ns physical path delay SLICE_88 to SLICE_9 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.638ns LSR_SET requirement (totaling 3.526ns) by 5.022ns
+
+ Physical Path Details:
+
+      Data path SLICE_88 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R4C3D.CLK to       R4C3D.Q0 SLICE_88 (from PHI2_c)
+ROUTE         1     1.155       R4C3D.Q0 to       R2C2A.D0 Bank_0
+CTOF_DEL    ---     0.371       R2C2A.D0 to       R2C2A.F0 SLICE_97
+ROUTE         1     1.348       R2C2A.F0 to       R4C4A.C0 n2314
+CTOF_DEL    ---     0.371       R4C4A.C0 to       R4C4A.F0 SLICE_81
+ROUTE         1     0.626       R4C4A.F0 to       R4C4D.D1 n26
+CTOF_DEL    ---     0.371       R4C4D.D1 to       R4C4D.F1 SLICE_18
+ROUTE         8     1.225       R4C4D.F1 to       R5C5B.D0 n1326
+CTOF_DEL    ---     0.371       R5C5B.D0 to       R5C5B.F0 SLICE_89
+ROUTE         1     0.700       R5C5B.F0 to       R6C5C.D0 n1280
+CTOF_DEL    ---     0.371       R6C5C.D0 to       R6C5C.F0 SLICE_79
+ROUTE         2     1.079       R6C5C.F0 to      R4C5D.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    8.548   (28.3% logic, 71.7% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R4C3D.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R4C5D.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.893ns (weighted slack = -9.786ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               8.419ns  (28.7% logic, 71.3% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.419ns physical path delay SLICE_99 to SLICE_14 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.638ns LSR_SET requirement (totaling 3.526ns) by 4.893ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C4C.CLK to       R2C4C.Q1 SLICE_99 (from PHI2_c)
+ROUTE         1     1.026       R2C4C.Q1 to       R2C2A.A0 Bank_7
+CTOF_DEL    ---     0.371       R2C2A.A0 to       R2C2A.F0 SLICE_97
+ROUTE         1     1.348       R2C2A.F0 to       R4C4A.C0 n2314
+CTOF_DEL    ---     0.371       R4C4A.C0 to       R4C4A.F0 SLICE_81
+ROUTE         1     0.626       R4C4A.F0 to       R4C4D.D1 n26
+CTOF_DEL    ---     0.371       R4C4D.D1 to       R4C4D.F1 SLICE_18
+ROUTE         8     1.225       R4C4D.F1 to       R5C5B.D0 n1326
+CTOF_DEL    ---     0.371       R5C5B.D0 to       R5C5B.F0 SLICE_89
+ROUTE         1     0.700       R5C5B.F0 to       R6C5C.D0 n1280
+CTOF_DEL    ---     0.371       R6C5C.D0 to       R6C5C.F0 SLICE_79
+ROUTE         2     1.079       R6C5C.F0 to      R5C5D.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    8.419   (28.7% logic, 71.3% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C4C.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R5C5D.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.893ns (weighted slack = -9.786ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        ADSubmitted_407  (to PHI2_c -)
+
+   Delay:               8.419ns  (28.7% logic, 71.3% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.419ns physical path delay SLICE_99 to SLICE_9 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.638ns LSR_SET requirement (totaling 3.526ns) by 4.893ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C4C.CLK to       R2C4C.Q1 SLICE_99 (from PHI2_c)
+ROUTE         1     1.026       R2C4C.Q1 to       R2C2A.A0 Bank_7
+CTOF_DEL    ---     0.371       R2C2A.A0 to       R2C2A.F0 SLICE_97
+ROUTE         1     1.348       R2C2A.F0 to       R4C4A.C0 n2314
+CTOF_DEL    ---     0.371       R4C4A.C0 to       R4C4A.F0 SLICE_81
+ROUTE         1     0.626       R4C4A.F0 to       R4C4D.D1 n26
+CTOF_DEL    ---     0.371       R4C4D.D1 to       R4C4D.F1 SLICE_18
+ROUTE         8     1.225       R4C4D.F1 to       R5C5B.D0 n1326
+CTOF_DEL    ---     0.371       R5C5B.D0 to       R5C5B.F0 SLICE_89
+ROUTE         1     0.700       R5C5B.F0 to       R6C5C.D0 n1280
+CTOF_DEL    ---     0.371       R6C5C.D0 to       R6C5C.F0 SLICE_79
+ROUTE         2     1.079       R6C5C.F0 to      R4C5D.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    8.419   (28.7% logic, 71.3% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C4C.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R4C5D.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.392ns (weighted slack = -8.784ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_412  (to PHI2_c -)
+                   FF                        CmdUFMCLK_413
+
+   Delay:               8.291ns  (29.1% logic, 70.9% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.291ns physical path delay SLICE_88 to SLICE_81 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 3.899ns) by 4.392ns
+
+ Physical Path Details:
+
+      Data path SLICE_88 to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R4C3D.CLK to       R4C3D.Q0 SLICE_88 (from PHI2_c)
+ROUTE         1     1.155       R4C3D.Q0 to       R2C2A.D0 Bank_0
+CTOF_DEL    ---     0.371       R2C2A.D0 to       R2C2A.F0 SLICE_97
+ROUTE         1     1.348       R2C2A.F0 to       R4C4A.C0 n2314
+CTOF_DEL    ---     0.371       R4C4A.C0 to       R4C4A.F0 SLICE_81
+ROUTE         1     0.626       R4C4A.F0 to       R4C4D.D1 n26
+CTOF_DEL    ---     0.371       R4C4D.D1 to       R4C4D.F1 SLICE_18
+ROUTE         8     0.755       R4C4D.F1 to       R4C3A.D0 n1326
+CTOF_DEL    ---     0.371       R4C3A.D0 to       R4C3A.F0 SLICE_82
+ROUTE         2     0.903       R4C3A.F0 to       R4C5C.C1 n2460
+CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_83
+ROUTE         2     1.089       R4C5C.F1 to       R4C4A.CE PHI2_N_120_enable_6 (to PHI2_c)
+                  --------
+                    8.291   (29.1% logic, 70.9% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R4C3D.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R4C4A.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.392ns (weighted slack = -8.784ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI_414  (to PHI2_c -)
+
+   Delay:               8.291ns  (29.1% logic, 70.9% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.291ns physical path delay SLICE_88 to SLICE_93 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 3.899ns) by 4.392ns
+
+ Physical Path Details:
+
+      Data path SLICE_88 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R4C3D.CLK to       R4C3D.Q0 SLICE_88 (from PHI2_c)
+ROUTE         1     1.155       R4C3D.Q0 to       R2C2A.D0 Bank_0
+CTOF_DEL    ---     0.371       R2C2A.D0 to       R2C2A.F0 SLICE_97
+ROUTE         1     1.348       R2C2A.F0 to       R4C4A.C0 n2314
+CTOF_DEL    ---     0.371       R4C4A.C0 to       R4C4A.F0 SLICE_81
+ROUTE         1     0.626       R4C4A.F0 to       R4C4D.D1 n26
+CTOF_DEL    ---     0.371       R4C4D.D1 to       R4C4D.F1 SLICE_18
+ROUTE         8     0.755       R4C4D.F1 to       R4C3A.D0 n1326
+CTOF_DEL    ---     0.371       R4C3A.D0 to       R4C3A.F0 SLICE_82
+ROUTE         2     0.903       R4C3A.F0 to       R4C5C.C1 n2460
+CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_83
+ROUTE         2     1.089       R4C5C.F1 to       R3C5A.CE PHI2_N_120_enable_6 (to PHI2_c)
+                  --------
+                    8.291   (29.1% logic, 70.9% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R4C3D.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R3C5A.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.263ns (weighted slack = -8.526ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_412  (to PHI2_c -)
+                   FF                        CmdUFMCLK_413
+
+   Delay:               8.162ns  (29.6% logic, 70.4% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.162ns physical path delay SLICE_99 to SLICE_81 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 3.899ns) by 4.263ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C4C.CLK to       R2C4C.Q1 SLICE_99 (from PHI2_c)
+ROUTE         1     1.026       R2C4C.Q1 to       R2C2A.A0 Bank_7
+CTOF_DEL    ---     0.371       R2C2A.A0 to       R2C2A.F0 SLICE_97
+ROUTE         1     1.348       R2C2A.F0 to       R4C4A.C0 n2314
+CTOF_DEL    ---     0.371       R4C4A.C0 to       R4C4A.F0 SLICE_81
+ROUTE         1     0.626       R4C4A.F0 to       R4C4D.D1 n26
+CTOF_DEL    ---     0.371       R4C4D.D1 to       R4C4D.F1 SLICE_18
+ROUTE         8     0.755       R4C4D.F1 to       R4C3A.D0 n1326
+CTOF_DEL    ---     0.371       R4C3A.D0 to       R4C3A.F0 SLICE_82
+ROUTE         2     0.903       R4C3A.F0 to       R4C5C.C1 n2460
+CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_83
+ROUTE         2     1.089       R4C5C.F1 to       R4C4A.CE PHI2_N_120_enable_6 (to PHI2_c)
+                  --------
+                    8.162   (29.6% logic, 70.4% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C4C.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R4C4A.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.263ns (weighted slack = -8.526ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI_414  (to PHI2_c -)
+
+   Delay:               8.162ns  (29.6% logic, 70.4% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.162ns physical path delay SLICE_99 to SLICE_93 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 3.899ns) by 4.263ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C4C.CLK to       R2C4C.Q1 SLICE_99 (from PHI2_c)
+ROUTE         1     1.026       R2C4C.Q1 to       R2C2A.A0 Bank_7
+CTOF_DEL    ---     0.371       R2C2A.A0 to       R2C2A.F0 SLICE_97
+ROUTE         1     1.348       R2C2A.F0 to       R4C4A.C0 n2314
+CTOF_DEL    ---     0.371       R4C4A.C0 to       R4C4A.F0 SLICE_81
+ROUTE         1     0.626       R4C4A.F0 to       R4C4D.D1 n26
+CTOF_DEL    ---     0.371       R4C4D.D1 to       R4C4D.F1 SLICE_18
+ROUTE         8     0.755       R4C4D.F1 to       R4C3A.D0 n1326
+CTOF_DEL    ---     0.371       R4C3A.D0 to       R4C3A.F0 SLICE_82
+ROUTE         2     0.903       R4C3A.F0 to       R4C5C.C1 n2460
+CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_83
+ROUTE         2     1.089       R4C5C.F1 to       R3C5A.CE PHI2_N_120_enable_6 (to PHI2_c)
+                  --------
+                    8.162   (29.6% logic, 70.4% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C4C.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R3C5A.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.241ns (weighted slack = -8.482ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               7.767ns  (31.1% logic, 68.9% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.767ns physical path delay SLICE_99 to SLICE_14 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.638ns LSR_SET requirement (totaling 3.526ns) by 4.241ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C4C.CLK to       R2C4C.Q0 SLICE_99 (from PHI2_c)
+ROUTE         1     1.026       R2C4C.Q0 to       R4C4A.A1 Bank_6
+CTOF_DEL    ---     0.371       R4C4A.A1 to       R4C4A.F1 SLICE_81
+ROUTE         1     0.696       R4C4A.F1 to       R4C4A.B0 n2278
+CTOF_DEL    ---     0.371       R4C4A.B0 to       R4C4A.F0 SLICE_81
+ROUTE         1     0.626       R4C4A.F0 to       R4C4D.D1 n26
+CTOF_DEL    ---     0.371       R4C4D.D1 to       R4C4D.F1 SLICE_18
+ROUTE         8     1.225       R4C4D.F1 to       R5C5B.D0 n1326
+CTOF_DEL    ---     0.371       R5C5B.D0 to       R5C5B.F0 SLICE_89
+ROUTE         1     0.700       R5C5B.F0 to       R6C5C.D0 n1280
+CTOF_DEL    ---     0.371       R6C5C.D0 to       R6C5C.F0 SLICE_79
+ROUTE         2     1.079       R6C5C.F0 to      R5C5D.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    7.767   (31.1% logic, 68.9% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C4C.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R5C5D.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.241ns (weighted slack = -8.482ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        ADSubmitted_407  (to PHI2_c -)
+
+   Delay:               7.767ns  (31.1% logic, 68.9% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.767ns physical path delay SLICE_99 to SLICE_9 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.638ns LSR_SET requirement (totaling 3.526ns) by 4.241ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C4C.CLK to       R2C4C.Q0 SLICE_99 (from PHI2_c)
+ROUTE         1     1.026       R2C4C.Q0 to       R4C4A.A1 Bank_6
+CTOF_DEL    ---     0.371       R4C4A.A1 to       R4C4A.F1 SLICE_81
+ROUTE         1     0.696       R4C4A.F1 to       R4C4A.B0 n2278
+CTOF_DEL    ---     0.371       R4C4A.B0 to       R4C4A.F0 SLICE_81
+ROUTE         1     0.626       R4C4A.F0 to       R4C4D.D1 n26
+CTOF_DEL    ---     0.371       R4C4D.D1 to       R4C4D.F1 SLICE_18
+ROUTE         8     1.225       R4C4D.F1 to       R5C5B.D0 n1326
+CTOF_DEL    ---     0.371       R5C5B.D0 to       R5C5B.F0 SLICE_89
+ROUTE         1     0.700       R5C5B.F0 to       R6C5C.D0 n1280
+CTOF_DEL    ---     0.371       R6C5C.D0 to       R6C5C.F0 SLICE_79
+ROUTE         2     1.079       R6C5C.F0 to      R4C5D.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    7.767   (31.1% logic, 68.9% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C4C.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R4C5D.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+Warning:  54.431MHz is the maximum frequency for this preference.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "RCLK_c" 283.768000 MHz ; |  283.768 MHz|  129.769 MHz|   5 *
+                                        |             |             |
+FREQUENCY NET "PHI2_c" 120.077000 MHz ; |  120.077 MHz|   54.431 MHz|   6 *
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+2 preferences(marked by "*" above) not met.
+
+----------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+----------------------------------------------------------------------------
+n1326                                   |       8|      95|     29.14%
+                                        |        |        |
+n26                                     |       1|      71|     21.78%
+                                        |        |        |
+----------------------------------------------------------------------------
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
+   Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 326  Score: 913247
+Cumulative negative slack: 638389
+
+Constraints cover 489 paths, 2 nets, and 414 connections (62.54% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
+Tue Aug 15 05:03:29 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf 
+Design file:     ram2gs_lcmxo256c_impl1.ncd
+Preference file: ram2gs_lcmxo256c_impl1.prf
+Device,speed:    LCMXO256C,m
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "RCLK_c" 283.768000 MHz (0 errors)
    •             383 items scored, 0 timing errors detected.
+
+
  • FREQUENCY NET "PHI2_c" 120.077000 MHz (0 errors)
    •             106 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
+            383 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.273ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i4  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i5  (to RCLK_c +)
+
+   Delay:               0.256ns  (49.2% logic, 50.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.256ns physical path delay SLICE_100 to SLICE_100 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.273ns
+
+ Physical Path Details:
+
+      Data path SLICE_100 to SLICE_100:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R6C2B.CLK to       R6C2B.Q0 SLICE_100 (from RCLK_c)
+ROUTE         1     0.130       R6C2B.Q0 to       R6C2B.M1 n736 (to RCLK_c)
+                  --------
+                    0.256   (49.2% logic, 50.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_100:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R6C2B.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_100:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R6C2B.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.273ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i8  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i9  (to RCLK_c +)
+
+   Delay:               0.256ns  (49.2% logic, 50.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.256ns physical path delay SLICE_76 to SLICE_76 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.273ns
+
+ Physical Path Details:
+
+      Data path SLICE_76 to SLICE_76:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R4C4B.CLK to       R4C4B.Q0 SLICE_76 (from RCLK_c)
+ROUTE         1     0.130       R4C4B.Q0 to       R4C4B.M1 n732 (to RCLK_c)
+                  --------
+                    0.256   (49.2% logic, 50.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_76:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R4C4B.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_76:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R4C4B.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.273ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i12  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i13  (to RCLK_c +)
+
+   Delay:               0.256ns  (49.2% logic, 50.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.256ns physical path delay SLICE_77 to SLICE_77 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.273ns
+
+ Physical Path Details:
+
+      Data path SLICE_77 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R6C3D.CLK to       R6C3D.Q0 SLICE_77 (from RCLK_c)
+ROUTE         1     0.130       R6C3D.Q0 to       R6C3D.M1 n728 (to RCLK_c)
+                  --------
+                    0.256   (49.2% logic, 50.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R6C3D.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R6C3D.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.273ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i14  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i15  (to RCLK_c +)
+
+   Delay:               0.256ns  (49.2% logic, 50.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.256ns physical path delay SLICE_80 to SLICE_80 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.273ns
+
+ Physical Path Details:
+
+      Data path SLICE_80 to SLICE_80:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R8C4A.CLK to       R8C4A.Q0 SLICE_80 (from RCLK_c)
+ROUTE         1     0.130       R8C4A.Q0 to       R8C4A.M1 n726 (to RCLK_c)
+                  --------
+                    0.256   (49.2% logic, 50.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_80:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R8C4A.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_80:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R8C4A.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.273ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i10  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i11  (to RCLK_c +)
+
+   Delay:               0.256ns  (49.2% logic, 50.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.256ns physical path delay SLICE_82 to SLICE_82 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.273ns
+
+ Physical Path Details:
+
+      Data path SLICE_82 to SLICE_82:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R4C3A.CLK to       R4C3A.Q0 SLICE_82 (from RCLK_c)
+ROUTE         1     0.130       R4C3A.Q0 to       R4C3A.M1 n730 (to RCLK_c)
+                  --------
+                    0.256   (49.2% logic, 50.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_82:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R4C3A.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_82:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R4C3A.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.273ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i2  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i3  (to RCLK_c +)
+
+   Delay:               0.256ns  (49.2% logic, 50.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.256ns physical path delay SLICE_84 to SLICE_84 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.273ns
+
+ Physical Path Details:
+
+      Data path SLICE_84 to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R3C4A.CLK to       R3C4A.Q0 SLICE_84 (from RCLK_c)
+ROUTE         1     0.130       R3C4A.Q0 to       R3C4A.M1 n738 (to RCLK_c)
+                  --------
+                    0.256   (49.2% logic, 50.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R3C4A.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R3C4A.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.273ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i6  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i7  (to RCLK_c +)
+
+   Delay:               0.256ns  (49.2% logic, 50.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.256ns physical path delay SLICE_86 to SLICE_86 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.273ns
+
+ Physical Path Details:
+
+      Data path SLICE_86 to SLICE_86:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R4C3C.CLK to       R4C3C.Q0 SLICE_86 (from RCLK_c)
+ROUTE         1     0.130       R4C3C.Q0 to       R4C3C.M1 n734 (to RCLK_c)
+                  --------
+                    0.256   (49.2% logic, 50.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_86:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R4C3C.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_86:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R4C3C.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.281ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i0  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i1  (to RCLK_c +)
+
+   Delay:               0.264ns  (47.7% logic, 52.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.264ns physical path delay SLICE_87 to SLICE_87 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.281ns
+
+ Physical Path Details:
+
+      Data path SLICE_87 to SLICE_87:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R4C2C.CLK to       R4C2C.Q0 SLICE_87 (from RCLK_c)
+ROUTE         6     0.138       R4C2C.Q0 to       R4C2C.M1 nRCS_N_139 (to RCLK_c)
+                  --------
+                    0.264   (47.7% logic, 52.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_87:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R4C2C.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_87:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R4C2C.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.288ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RASr2_380  (from RCLK_c +)
+   Destination:    FF         Data in        RASr3_381  (to RCLK_c +)
+
+   Delay:               0.271ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.271ns physical path delay SLICE_74 to SLICE_74 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.288ns
+
+ Physical Path Details:
+
+      Data path SLICE_74 to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R8C5C.CLK to       R8C5C.Q0 SLICE_74 (from RCLK_c)
+ROUTE        14     0.145       R8C5C.Q0 to       R8C5C.M1 RASr2 (to RCLK_c)
+                  --------
+                    0.271   (46.5% logic, 53.5% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R8C5C.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R8C5C.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.301ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i15  (from RCLK_c +)
+   Destination:    FF         Data in        FS_610_add_4_16  (to RCLK_c +)
+                   FF                        FS_610__i15
+                   FF                        FS_610__i14
+
+   Delay:               0.257ns  (49.0% logic, 51.0% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.257ns physical path delay SLICE_1 to SLICE_1 meets
+     -0.044ns LUT_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.044ns) by 0.301ns
+
+ Physical Path Details:
+
+      Data path SLICE_1 to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R5C4D.CLK to       R5C4D.Q1 SLICE_1 (from RCLK_c)
+ROUTE         3     0.131       R5C4D.Q1 to       R5C4D.A1 FS_15 (to RCLK_c)
+                  --------
+                    0.257   (49.0% logic, 51.0% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R5C4D.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R5C4D.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
+            106 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.361ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_406  (from PHI2_c -)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               0.342ns  (61.7% logic, 38.3% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.342ns physical path delay SLICE_14 to SLICE_14 meets
+     -0.019ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.361ns
+
+ Physical Path Details:
+
+      Data path SLICE_14 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R5C5D.CLK to       R5C5D.Q0 SLICE_14 (from PHI2_c)
+ROUTE         2     0.131       R5C5D.Q0 to       R5C5D.A0 C1Submitted
+CTOF_DEL    ---     0.074       R5C5D.A0 to       R5C5D.F0 SLICE_14
+ROUTE         1     0.000       R5C5D.F0 to      R5C5D.DI0 n6_adj_3 (to PHI2_c)
+                  --------
+                    0.342   (61.7% logic, 38.3% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R5C5D.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R5C5D.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.361ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_407  (from PHI2_c -)
+   Destination:    FF         Data in        ADSubmitted_407  (to PHI2_c -)
+
+   Delay:               0.342ns  (61.7% logic, 38.3% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.342ns physical path delay SLICE_9 to SLICE_9 meets
+     -0.019ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.361ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R4C5D.CLK to       R4C5D.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2     0.131       R4C5D.Q0 to       R4C5D.A0 ADSubmitted
+CTOF_DEL    ---     0.074       R4C5D.A0 to       R4C5D.F0 SLICE_9
+ROUTE         1     0.000       R4C5D.F0 to      R4C5D.DI0 n1413 (to PHI2_c)
+                  --------
+                    0.342   (61.7% logic, 38.3% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R4C5D.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R4C5D.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.587ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        XOR8MEG_408  (to PHI2_c -)
+
+   Delay:               0.564ns  (37.4% logic, 62.6% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.564ns physical path delay SLICE_18 to SLICE_49 meets
+     -0.023ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 0.587ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_49:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R4C4D.CLK to       R4C4D.Q0 SLICE_18 (from PHI2_c)
+ROUTE         2     0.223       R4C4D.Q0 to       R3C4A.B1 CmdEnable
+CTOF_DEL    ---     0.074       R3C4A.B1 to       R3C4A.F1 SLICE_84
+ROUTE         1     0.130       R3C4A.F1 to       R3C4C.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    0.564   (37.4% logic, 62.6% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R4C4D.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_49:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R3C4C.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.869ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMCS_412  (to PHI2_c -)
+                   FF                        CmdUFMCLK_413
+
+   Delay:               0.846ns  (33.7% logic, 66.3% route), 3 logic levels.
+
+ Constraint Details:
+
+      0.846ns physical path delay SLICE_18 to SLICE_81 meets
+     -0.023ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 0.869ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R4C4D.CLK to       R4C4D.Q0 SLICE_18 (from PHI2_c)
+ROUTE         2     0.145       R4C4D.Q0 to       R4C5C.D0 CmdEnable
+CTOF_DEL    ---     0.074       R4C5C.D0 to       R4C5C.F0 SLICE_83
+ROUTE         2     0.196       R4C5C.F0 to       R4C5C.A1 n10
+CTOF_DEL    ---     0.074       R4C5C.A1 to       R4C5C.F1 SLICE_83
+ROUTE         2     0.220       R4C5C.F1 to       R4C4A.CE PHI2_N_120_enable_6 (to PHI2_c)
+                  --------
+                    0.846   (33.7% logic, 66.3% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R4C4D.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R4C4A.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.869ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMSDI_414  (to PHI2_c -)
+
+   Delay:               0.846ns  (33.7% logic, 66.3% route), 3 logic levels.
+
+ Constraint Details:
+
+      0.846ns physical path delay SLICE_18 to SLICE_93 meets
+     -0.023ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 0.869ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R4C4D.CLK to       R4C4D.Q0 SLICE_18 (from PHI2_c)
+ROUTE         2     0.145       R4C4D.Q0 to       R4C5C.D0 CmdEnable
+CTOF_DEL    ---     0.074       R4C5C.D0 to       R4C5C.F0 SLICE_83
+ROUTE         2     0.196       R4C5C.F0 to       R4C5C.A1 n10
+CTOF_DEL    ---     0.074       R4C5C.A1 to       R4C5C.F1 SLICE_83
+ROUTE         2     0.220       R4C5C.F1 to       R3C5A.CE PHI2_N_120_enable_6 (to PHI2_c)
+                  --------
+                    0.846   (33.7% logic, 66.3% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R4C4D.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R3C5A.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.057ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        Cmdn8MEGEN_410  (to PHI2_c -)
+
+   Delay:               1.034ns  (34.7% logic, 65.3% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.034ns physical path delay SLICE_18 to SLICE_23 meets
+     -0.023ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 1.057ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R4C4D.CLK to       R4C4D.Q0 SLICE_18 (from PHI2_c)
+ROUTE         2     0.145       R4C4D.Q0 to       R4C5C.D0 CmdEnable
+CTOF_DEL    ---     0.074       R4C5C.D0 to       R4C5C.F0 SLICE_83
+ROUTE         2     0.211       R4C5C.F0 to       R4C4B.A1 n10
+CTOF_DEL    ---     0.074       R4C4B.A1 to       R4C4B.F1 SLICE_76
+ROUTE         2     0.103       R4C4B.F1 to       R4C4B.C0 n2458
+CTOF_DEL    ---     0.074       R4C4B.C0 to       R4C4B.F0 SLICE_76
+ROUTE         1     0.216       R4C4B.F0 to       R3C4B.CE PHI2_N_120_enable_4 (to PHI2_c)
+                  --------
+                    1.034   (34.7% logic, 65.3% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R4C4D.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R3C4B.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.079ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        CmdSubmitted_411  (to PHI2_c -)
+
+   Delay:               1.056ns  (34.0% logic, 66.0% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.056ns physical path delay SLICE_18 to SLICE_19 meets
+     -0.023ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 1.079ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R4C4D.CLK to       R4C4D.Q0 SLICE_18 (from PHI2_c)
+ROUTE         2     0.145       R4C4D.Q0 to       R4C5C.D0 CmdEnable
+CTOF_DEL    ---     0.074       R4C5C.D0 to       R4C5C.F0 SLICE_83
+ROUTE         2     0.211       R4C5C.F0 to       R4C4B.A1 n10
+CTOF_DEL    ---     0.074       R4C4B.A1 to       R4C4B.F1 SLICE_76
+ROUTE         2     0.211       R4C4B.F1 to       R6C4D.A0 n2458
+CTOF_DEL    ---     0.074       R6C4D.A0 to       R6C4D.F0 SLICE_91
+ROUTE         1     0.130       R6C4D.F0 to       R6C4B.CE PHI2_N_120_enable_5 (to PHI2_c)
+                  --------
+                    1.056   (34.0% logic, 66.0% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R4C4D.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R6C4B.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.104ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_407  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               1.081ns  (37.9% logic, 62.1% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.081ns physical path delay SLICE_9 to SLICE_18 meets
+     -0.023ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 1.104ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R4C5D.CLK to       R4C5D.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2     0.143       R4C5D.Q0 to       R3C5C.D0 ADSubmitted
+CTOOFX_DEL  ---     0.125       R3C5C.D0 to     R3C5C.OFX0 i26/SLICE_71
+ROUTE         1     0.207     R3C5C.OFX0 to       R4C5A.A0 n13_adj_2
+CTOF_DEL    ---     0.074       R4C5A.A0 to       R4C5A.F0 SLICE_105
+ROUTE         1     0.179       R4C5A.F0 to       R4C3A.C1 n14
+CTOF_DEL    ---     0.074       R4C3A.C1 to       R4C3A.F1 SLICE_82
+ROUTE         1     0.142       R4C3A.F1 to       R4C4D.CE PHI2_N_120_enable_7 (to PHI2_c)
+                  --------
+                    1.081   (37.9% logic, 62.1% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R4C5D.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R4C4D.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.368ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_406  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               1.345ns  (35.7% logic, 64.3% route), 5 logic levels.
+
+ Constraint Details:
+
+      1.345ns physical path delay SLICE_14 to SLICE_18 meets
+     -0.023ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 1.368ns
+
+ Physical Path Details:
+
+      Data path SLICE_14 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R5C5D.CLK to       R5C5D.Q0 SLICE_14 (from PHI2_c)
+ROUTE         2     0.196       R5C5D.Q0 to       R5C5D.A1 C1Submitted
+CTOF_DEL    ---     0.074       R5C5D.A1 to       R5C5D.F1 SLICE_14
+ROUTE         1     0.141       R5C5D.F1 to       R3C5C.D1 n2284
+CTOOFX_DEL  ---     0.121       R3C5C.D1 to     R3C5C.OFX0 i26/SLICE_71
+ROUTE         1     0.207     R3C5C.OFX0 to       R4C5A.A0 n13_adj_2
+CTOF_DEL    ---     0.074       R4C5A.A0 to       R4C5A.F0 SLICE_105
+ROUTE         1     0.179       R4C5A.F0 to       R4C3A.C1 n14
+CTOF_DEL    ---     0.074       R4C3A.C1 to       R4C3A.F1 SLICE_82
+ROUTE         1     0.142       R4C3A.F1 to       R4C4D.CE PHI2_N_120_enable_7 (to PHI2_c)
+                  --------
+                    1.345   (35.7% logic, 64.3% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R5C5D.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R4C4D.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.689ns (weighted slack = 9.378ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              XOR8MEG_408  (from PHI2_c -)
+   Destination:    FF         Data in        RA11_385  (to PHI2_c +)
+
+   Delay:               0.517ns  (40.8% logic, 59.2% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.517ns physical path delay SLICE_49 to SLICE_32 meets
+     -0.008ns DIN_HLD and
+     -4.164ns delay constraint less
+      0.000ns skew requirement (totaling -4.172ns) by 4.689ns
+
+ Physical Path Details:
+
+      Data path SLICE_49 to SLICE_32:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R3C4C.CLK to       R3C4C.Q0 SLICE_49 (from PHI2_c)
+ROUTE         1     0.306       R3C4C.Q0 to       R2C5A.A0 XOR8MEG
+CTOF_DEL    ---     0.074       R2C5A.A0 to       R2C5A.F0 SLICE_32
+ROUTE         1     0.000       R2C5A.F0 to      R2C5A.DI0 RA11_N_184 (to PHI2_c)
+                  --------
+                    0.517   (40.8% logic, 59.2% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_49:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R3C4C.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_32:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R2C5A.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "RCLK_c" 283.768000 MHz ; |     0.000 ns|     0.273 ns|   1  
+                                        |             |             |
+FREQUENCY NET "PHI2_c" 120.077000 MHz ; |     0.000 ns|     0.361 ns|   2  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
+   Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 489 paths, 2 nets, and 414 connections (62.54% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 326 (setup), 0 (hold)
+Score: 913247 (setup), 0 (hold)
+Cumulative negative slack: 638389 (638389+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_drc.log b/CPLD/LCMXO256C/impl1/RAM2GS_drc.log new file mode 100644 index 0000000..7293e09 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_drc.log @@ -0,0 +1,15 @@ +Results of NGD DRC are available in RAM2GS_drc.log. +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... + + +Running DRC... + +DRC complete with no errors or warnings + +Design Results: + 318 blocks expanded +completed the first expansion +All blocks are expanded and NGD expansion is successful. +Writing NGD file RAM2GS_LCMXO256C_impl1.ngd. diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_lse.twr b/CPLD/LCMXO256C/impl1/RAM2GS_lse.twr new file mode 100644 index 0000000..02e97ea --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_lse.twr @@ -0,0 +1,291 @@ +-------------------------------------------------------------------------------- +Lattice Synthesis Timing Report, Version +Tue Aug 15 05:03:20 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Design: RAM2GS +Constraint file: +Report level: verbose report, limited to 3 items per constraint +-------------------------------------------------------------------------------- + + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c] + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c] + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c] + 115 items scored, 112 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path violates requirements by 8.575ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK Bank_i3 (from PHI2_c +) + Destination: FD1P3AX SP CmdUFMCS_412 (to PHI2_c -) + + Delay: 10.811ns (23.7% logic, 76.3% route), 6 logic levels. + + Constraint Details: + + 10.811ns data_path Bank_i3 to CmdUFMCS_412 violates + 2.500ns delay constraint less + 0.264ns LCE_S requirement (totaling 2.236ns) by 8.575ns + + Path Details: Bank_i3 to CmdUFMCS_412 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q Bank_i3 (from PHI2_c) +Route 1 e 1.220 Bank[3] +LUT4 --- 0.390 B to Z i1982_2_lut +Route 1 e 1.220 n2278 +LUT4 --- 0.390 C to Z i12_4_lut +Route 1 e 1.220 n26 +LUT4 --- 0.390 B to Z i13_4_lut +Route 8 e 1.719 n1326 +LUT4 --- 0.390 B to Z i1990_2_lut_rep_17 +Route 2 e 1.386 n2460 +LUT4 --- 0.390 C to Z i1_2_lut_4_lut +Route 3 e 1.483 PHI2_N_120_enable_6 + -------- + 10.811 (23.7% logic, 76.3% route), 6 logic levels. + + +Error: The following path violates requirements by 8.575ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK Bank_i3 (from PHI2_c +) + Destination: FD1P3AX SP CmdUFMSDI_414 (to PHI2_c -) + + Delay: 10.811ns (23.7% logic, 76.3% route), 6 logic levels. + + Constraint Details: + + 10.811ns data_path Bank_i3 to CmdUFMSDI_414 violates + 2.500ns delay constraint less + 0.264ns LCE_S requirement (totaling 2.236ns) by 8.575ns + + Path Details: Bank_i3 to CmdUFMSDI_414 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q Bank_i3 (from PHI2_c) +Route 1 e 1.220 Bank[3] +LUT4 --- 0.390 B to Z i1982_2_lut +Route 1 e 1.220 n2278 +LUT4 --- 0.390 C to Z i12_4_lut +Route 1 e 1.220 n26 +LUT4 --- 0.390 B to Z i13_4_lut +Route 8 e 1.719 n1326 +LUT4 --- 0.390 B to Z i1990_2_lut_rep_17 +Route 2 e 1.386 n2460 +LUT4 --- 0.390 C to Z i1_2_lut_4_lut +Route 3 e 1.483 PHI2_N_120_enable_6 + -------- + 10.811 (23.7% logic, 76.3% route), 6 logic levels. + + +Error: The following path violates requirements by 8.575ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK Bank_i3 (from PHI2_c +) + Destination: FD1P3AX SP CmdUFMCLK_413 (to PHI2_c -) + + Delay: 10.811ns (23.7% logic, 76.3% route), 6 logic levels. + + Constraint Details: + + 10.811ns data_path Bank_i3 to CmdUFMCLK_413 violates + 2.500ns delay constraint less + 0.264ns LCE_S requirement (totaling 2.236ns) by 8.575ns + + Path Details: Bank_i3 to CmdUFMCLK_413 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q Bank_i3 (from PHI2_c) +Route 1 e 1.220 Bank[3] +LUT4 --- 0.390 B to Z i1982_2_lut +Route 1 e 1.220 n2278 +LUT4 --- 0.390 C to Z i12_4_lut +Route 1 e 1.220 n26 +LUT4 --- 0.390 B to Z i13_4_lut +Route 8 e 1.719 n1326 +LUT4 --- 0.390 B to Z i1990_2_lut_rep_17 +Route 2 e 1.386 n2460 +LUT4 --- 0.390 C to Z i1_2_lut_4_lut +Route 3 e 1.483 PHI2_N_120_enable_6 + -------- + 10.811 (23.7% logic, 76.3% route), 6 logic levels. + +Warning: 11.075 ns is the maximum delay for this constraint. + + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c] + 357 items scored, 234 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path violates requirements by 4.364ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK FS_610__i13 (from RCLK_c +) + Destination: FD1P3AX D n8MEGEN_418 (to RCLK_c +) + + Delay: 9.182ns (23.7% logic, 76.3% route), 5 logic levels. + + Constraint Details: + + 9.182ns data_path FS_610__i13 to n8MEGEN_418 violates + 5.000ns delay constraint less + 0.182ns L_S requirement (totaling 4.818ns) by 4.364ns + + Path Details: FS_610__i13 to n8MEGEN_418 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q FS_610__i13 (from RCLK_c) +Route 3 e 1.603 FS[13] +LUT4 --- 0.390 A to Z i1976_2_lut +Route 3 e 1.483 n2272 +LUT4 --- 0.390 C to Z i5_3_lut_rep_21_4_lut +Route 3 e 1.483 n2464 +LUT4 --- 0.390 B to Z i1_2_lut_3_lut_adj_4 +Route 1 e 1.220 n1325 +LUT4 --- 0.390 D to Z n8MEGEN_I_14_4_lut +Route 1 e 1.220 n8MEGEN_N_91 + -------- + 9.182 (23.7% logic, 76.3% route), 5 logic levels. + + +Error: The following path violates requirements by 4.364ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK FS_610__i15 (from RCLK_c +) + Destination: FD1P3AX D n8MEGEN_418 (to RCLK_c +) + + Delay: 9.182ns (23.7% logic, 76.3% route), 5 logic levels. + + Constraint Details: + + 9.182ns data_path FS_610__i15 to n8MEGEN_418 violates + 5.000ns delay constraint less + 0.182ns L_S requirement (totaling 4.818ns) by 4.364ns + + Path Details: FS_610__i15 to n8MEGEN_418 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q FS_610__i15 (from RCLK_c) +Route 3 e 1.603 FS[15] +LUT4 --- 0.390 B to Z i1976_2_lut +Route 3 e 1.483 n2272 +LUT4 --- 0.390 C to Z i5_3_lut_rep_21_4_lut +Route 3 e 1.483 n2464 +LUT4 --- 0.390 B to Z i1_2_lut_3_lut_adj_4 +Route 1 e 1.220 n1325 +LUT4 --- 0.390 D to Z n8MEGEN_I_14_4_lut +Route 1 e 1.220 n8MEGEN_N_91 + -------- + 9.182 (23.7% logic, 76.3% route), 5 logic levels. + + +Error: The following path violates requirements by 4.349ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK FS_610__i13 (from RCLK_c +) + Destination: FD1P3AX SP n8MEGEN_418 (to RCLK_c +) + + Delay: 9.085ns (23.9% logic, 76.1% route), 5 logic levels. + + Constraint Details: + + 9.085ns data_path FS_610__i13 to n8MEGEN_418 violates + 5.000ns delay constraint less + 0.264ns LCE_S requirement (totaling 4.736ns) by 4.349ns + + Path Details: FS_610__i13 to n8MEGEN_418 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q FS_610__i13 (from RCLK_c) +Route 3 e 1.603 FS[13] +LUT4 --- 0.390 A to Z i1976_2_lut +Route 3 e 1.483 n2272 +LUT4 --- 0.390 C to Z i7_4_lut +Route 2 e 1.386 n2214 +LUT4 --- 0.390 B to Z i2_2_lut +Route 1 e 1.220 n7 +LUT4 --- 0.390 A to Z i17_4_lut +Route 1 e 1.220 RCLK_c_enable_11 + -------- + 9.085 (23.9% logic, 76.1% route), 5 logic levels. + +Warning: 9.364 ns is the maximum delay for this constraint. + + +Timing Report Summary +-------------- +-------------------------------------------------------------------------------- +Constraint | Constraint| Actual|Levels +-------------------------------------------------------------------------------- + | | | +create_clock -period 5.000000 -name | | | +clk3 [get_nets nCCAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk2 [get_nets nCRAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk1 [get_nets PHI2_c] | 5.000 ns| 22.150 ns| 6 * + | | | +create_clock -period 5.000000 -name | | | +clk0 [get_nets RCLK_c] | 5.000 ns| 9.364 ns| 5 * + | | | +-------------------------------------------------------------------------------- + + +2 constraints not met. + +-------------------------------------------------------------------------------- +Critical Nets | Loads| Errors| % of total +-------------------------------------------------------------------------------- +n1326 | 8| 104| 30.06% + | | | +n26 | 1| 78| 22.54% + | | | +RCLK_c_enable_23 | 16| 64| 18.50% + | | | +-------------------------------------------------------------------------------- + + +Timing summary: +--------------- + +Timing errors: 346 Score: 1874657 + +Constraints cover 476 paths, 187 nets, and 480 connections (64.3% coverage) + + +Peak memory: 52895744 bytes, TRCE: 1204224 bytes, DLYMAN: 163840 bytes +CPU_TIME_REPORT: 0 secs diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_lse_lsetwr.html b/CPLD/LCMXO256C/impl1/RAM2GS_lse_lsetwr.html new file mode 100644 index 0000000..2c994f7 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_lse_lsetwr.html @@ -0,0 +1,356 @@ + +Lattice Synthesis Timing Report + + +
    Lattice Synthesis Timing Report
+--------------------------------------------------------------------------------
+Lattice Synthesis Timing Report, Version  
+Tue Aug 15 05:03:20 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design:     RAM2GS
+Constraint file:  
+Report level:    verbose report, limited to 3 items per constraint
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c]
+            115 items scored, 112 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 8.575ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i3  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdUFMCS_412  (to PHI2_c -)
+
+   Delay:                  10.811ns  (23.7% logic, 76.3% route), 6 logic levels.
+
+ Constraint Details:
+
+     10.811ns data_path Bank_i3 to CmdUFMCS_412 violates
+      2.500ns delay constraint less
+      0.264ns LCE_S requirement (totaling 2.236ns) by 8.575ns
+
+ Path Details: Bank_i3 to CmdUFMCS_412
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              Bank_i3 (from PHI2_c)
+Route         1   e 1.220                                  Bank[3]
+LUT4        ---     0.390              B to Z              i1982_2_lut
+Route         1   e 1.220                                  n2278
+LUT4        ---     0.390              C to Z              i12_4_lut
+Route         1   e 1.220                                  n26
+LUT4        ---     0.390              B to Z              i13_4_lut
+Route         8   e 1.719                                  n1326
+LUT4        ---     0.390              B to Z              i1990_2_lut_rep_17
+Route         2   e 1.386                                  n2460
+LUT4        ---     0.390              C to Z              i1_2_lut_4_lut
+Route         3   e 1.483                                  PHI2_N_120_enable_6
+                  --------
+                   10.811  (23.7% logic, 76.3% route), 6 logic levels.
+
+
+Error:  The following path violates requirements by 8.575ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i3  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdUFMSDI_414  (to PHI2_c -)
+
+   Delay:                  10.811ns  (23.7% logic, 76.3% route), 6 logic levels.
+
+ Constraint Details:
+
+     10.811ns data_path Bank_i3 to CmdUFMSDI_414 violates
+      2.500ns delay constraint less
+      0.264ns LCE_S requirement (totaling 2.236ns) by 8.575ns
+
+ Path Details: Bank_i3 to CmdUFMSDI_414
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              Bank_i3 (from PHI2_c)
+Route         1   e 1.220                                  Bank[3]
+LUT4        ---     0.390              B to Z              i1982_2_lut
+Route         1   e 1.220                                  n2278
+LUT4        ---     0.390              C to Z              i12_4_lut
+Route         1   e 1.220                                  n26
+LUT4        ---     0.390              B to Z              i13_4_lut
+Route         8   e 1.719                                  n1326
+LUT4        ---     0.390              B to Z              i1990_2_lut_rep_17
+Route         2   e 1.386                                  n2460
+LUT4        ---     0.390              C to Z              i1_2_lut_4_lut
+Route         3   e 1.483                                  PHI2_N_120_enable_6
+                  --------
+                   10.811  (23.7% logic, 76.3% route), 6 logic levels.
+
+
+Error:  The following path violates requirements by 8.575ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i3  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdUFMCLK_413  (to PHI2_c -)
+
+   Delay:                  10.811ns  (23.7% logic, 76.3% route), 6 logic levels.
+
+ Constraint Details:
+
+     10.811ns data_path Bank_i3 to CmdUFMCLK_413 violates
+      2.500ns delay constraint less
+      0.264ns LCE_S requirement (totaling 2.236ns) by 8.575ns
+
+ Path Details: Bank_i3 to CmdUFMCLK_413
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              Bank_i3 (from PHI2_c)
+Route         1   e 1.220                                  Bank[3]
+LUT4        ---     0.390              B to Z              i1982_2_lut
+Route         1   e 1.220                                  n2278
+LUT4        ---     0.390              C to Z              i12_4_lut
+Route         1   e 1.220                                  n26
+LUT4        ---     0.390              B to Z              i13_4_lut
+Route         8   e 1.719                                  n1326
+LUT4        ---     0.390              B to Z              i1990_2_lut_rep_17
+Route         2   e 1.386                                  n2460
+LUT4        ---     0.390              C to Z              i1_2_lut_4_lut
+Route         3   e 1.483                                  PHI2_N_120_enable_6
+                  --------
+                   10.811  (23.7% logic, 76.3% route), 6 logic levels.
+
+Warning: 11.075 ns is the maximum delay for this constraint.
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
+            357 items scored, 234 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 4.364ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_610__i13  (from RCLK_c +)
+   Destination:    FD1P3AX    D              n8MEGEN_418  (to RCLK_c +)
+
+   Delay:                   9.182ns  (23.7% logic, 76.3% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.182ns data_path FS_610__i13 to n8MEGEN_418 violates
+      5.000ns delay constraint less
+      0.182ns L_S requirement (totaling 4.818ns) by 4.364ns
+
+ Path Details: FS_610__i13 to n8MEGEN_418
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              FS_610__i13 (from RCLK_c)
+Route         3   e 1.603                                  FS[13]
+LUT4        ---     0.390              A to Z              i1976_2_lut
+Route         3   e 1.483                                  n2272
+LUT4        ---     0.390              C to Z              i5_3_lut_rep_21_4_lut
+Route         3   e 1.483                                  n2464
+LUT4        ---     0.390              B to Z              i1_2_lut_3_lut_adj_4
+Route         1   e 1.220                                  n1325
+LUT4        ---     0.390              D to Z              n8MEGEN_I_14_4_lut
+Route         1   e 1.220                                  n8MEGEN_N_91
+                  --------
+                    9.182  (23.7% logic, 76.3% route), 5 logic levels.
+
+
+Error:  The following path violates requirements by 4.364ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_610__i15  (from RCLK_c +)
+   Destination:    FD1P3AX    D              n8MEGEN_418  (to RCLK_c +)
+
+   Delay:                   9.182ns  (23.7% logic, 76.3% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.182ns data_path FS_610__i15 to n8MEGEN_418 violates
+      5.000ns delay constraint less
+      0.182ns L_S requirement (totaling 4.818ns) by 4.364ns
+
+ Path Details: FS_610__i15 to n8MEGEN_418
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              FS_610__i15 (from RCLK_c)
+Route         3   e 1.603                                  FS[15]
+LUT4        ---     0.390              B to Z              i1976_2_lut
+Route         3   e 1.483                                  n2272
+LUT4        ---     0.390              C to Z              i5_3_lut_rep_21_4_lut
+Route         3   e 1.483                                  n2464
+LUT4        ---     0.390              B to Z              i1_2_lut_3_lut_adj_4
+Route         1   e 1.220                                  n1325
+LUT4        ---     0.390              D to Z              n8MEGEN_I_14_4_lut
+Route         1   e 1.220                                  n8MEGEN_N_91
+                  --------
+                    9.182  (23.7% logic, 76.3% route), 5 logic levels.
+
+
+Error:  The following path violates requirements by 4.349ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_610__i13  (from RCLK_c +)
+   Destination:    FD1P3AX    SP             n8MEGEN_418  (to RCLK_c +)
+
+   Delay:                   9.085ns  (23.9% logic, 76.1% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.085ns data_path FS_610__i13 to n8MEGEN_418 violates
+      5.000ns delay constraint less
+      0.264ns LCE_S requirement (totaling 4.736ns) by 4.349ns
+
+ Path Details: FS_610__i13 to n8MEGEN_418
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              FS_610__i13 (from RCLK_c)
+Route         3   e 1.603                                  FS[13]
+LUT4        ---     0.390              A to Z              i1976_2_lut
+Route         3   e 1.483                                  n2272
+LUT4        ---     0.390              C to Z              i7_4_lut
+Route         2   e 1.386                                  n2214
+LUT4        ---     0.390              B to Z              i2_2_lut
+Route         1   e 1.220                                  n7
+LUT4        ---     0.390              A to Z              i17_4_lut
+Route         1   e 1.220                                  RCLK_c_enable_11
+                  --------
+                    9.085  (23.9% logic, 76.1% route), 5 logic levels.
+
+Warning: 9.364 ns is the maximum delay for this constraint.
+
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets PHI2_c]                  |     5.000 ns|    22.150 ns|     6 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |     5.000 ns|     9.364 ns|     5 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+--------------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+--------------------------------------------------------------------------------
+n1326                                   |       8|     104|     30.06%
+                                        |        |        |
+n26                                     |       1|      78|     22.54%
+                                        |        |        |
+RCLK_c_enable_23                        |      16|      64|     18.50%
+                                        |        |        |
+--------------------------------------------------------------------------------
+
+
+Timing summary:
+---------------
+
+Timing errors: 346  Score: 1874657
+
+Constraints cover  476 paths, 187 nets, and 480 connections (64.3% coverage)
+
+
+Peak memory: 52895744 bytes, TRCE: 1204224 bytes, DLYMAN: 163840 bytes
+CPU_TIME_REPORT: 0 secs 
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_prim.v b/CPLD/LCMXO256C/impl1/RAM2GS_prim.v new file mode 100644 index 0000000..ef9726d --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_prim.v @@ -0,0 +1,819 @@ +// Verilog netlist produced by program LSE : version Diamond (64-bit) 3.12.1.454 +// Netlist written on Tue Aug 15 05:03:20 2023 +// +// Verilog Description of module RAM2GS +// + +module RAM2GS (PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, + LED, RBA, RA, RD, nRCS, RCLK, RCKE, nRWE, nRRAS, + nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI, UFMSDO) /* synthesis syn_module_defined=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1[8:14]) + input PHI2; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) + input [9:0]MAin; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + input [1:0]CROW; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18]) + input [7:0]Din; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + output [7:0]Dout; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + input nCCAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) + input nCRAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + input nFWE; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(36[8:12]) + output LED; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(22[9:12]) + output [1:0]RBA; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22]) + output [11:0]RA; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + inout [7:0]RD; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + output nRCS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[13:17]) + input RCLK; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12]) + output RCKE; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(45[13:17]) + output nRWE; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[45:49]) + output nRRAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[23:28]) + output nRCAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[34:39]) + output RDQMH; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[16:21]) + output RDQML; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[9:14]) + output nUFMCS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(63[13:19]) + output UFMCLK; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(64[13:19]) + output UFMSDI; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(65[13:19]) + input UFMSDO; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(66[8:14]) + + wire PHI2_c /* synthesis is_clock=1, SET_AS_NETWORK=PHI2_c */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) + wire nCCAS_c /* synthesis is_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) + wire nCRAS_c /* synthesis is_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + wire RCLK_c /* synthesis SET_AS_NETWORK=RCLK_c, is_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12]) + wire nCCAS_N_3 /* synthesis is_inv_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + wire nCRAS_N_9 /* synthesis is_inv_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22]) + wire PHI2_N_120 /* synthesis is_inv_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(38[6:13]) + + wire GND_net, VCC_net, PHI2r, PHI2r2, PHI2r3, RASr, RASr2, + RASr3, CASr, CASr2, CASr3, FWEr, CBR, LEDEN, Din_c_7, + Din_c_6, Din_c_5, Din_c_4, Din_c_3, Din_c_2, Din_c_1, Din_c_0; + wire [7:0]Bank; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(31[12:16]) + + wire CROW_c_1, CROW_c_0, MAin_c_9, MAin_c_8, MAin_c_7, MAin_c_6, + MAin_c_5, MAin_c_4, MAin_c_3, MAin_c_2, MAin_c_1, MAin_c_0, + nFWE_c, n8MEGEN, XOR8MEG, RCKEEN, RCKE_c, nRCS_c, nRRAS_c, + nRCAS_c, nRWE_c, RBA_c_1, RBA_c_0, nRowColSel, RA_c, RA_0; + wire [9:0]RowA; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(51[12:16]) + + wire RA_1_9, RA_1_8, RA_1_7, RA_1_6, RA_1_5, RA_1_4, RA_1_3, + RA_1_2, RA_1_1, RA_1_0, RDQML_c, RDQMH_c; + wire [7:0]WRD; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(59[12:15]) + + wire nUFMCS_c, UFMCLK_c, UFMSDI_c, UFMSDO_c, C1Submitted, ADSubmitted, + CmdEnable, CmdSubmitted, Cmdn8MEGEN, CmdUFMCLK, CmdUFMSDI, + CmdUFMCS, InitReady, Ready; + wire [17:0]FS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(86[13:15]) + + wire LED_N_84, nFWE_N_5, n2414, RA11_N_184, n15, n2262, PHI2_N_120_enable_6, + n2257, n7, RASr2_N_63, RCKE_N_132, nRowColSel_N_35, n2011, + nRWE_N_182, RCKEEN_N_130, nRowColSel_N_34, nRowColSel_N_33, + n2015, nRowColSel_N_32, nRowColSel_N_28, n1426, n6, n2328, + n2457, n1425, RCKEEN_N_123, nRWE_N_178, RCKEEN_N_122, n2324, + nRCS_N_139, nRCAS_N_165, nRWE_N_177, nRWE_N_176, n2322, Ready_N_296, + n2316, n2314, Ready_N_292, nRCS_N_136, nRCAS_N_161, nRWE_N_171, + RCKEEN_N_121, n2336, PHI2_N_120_enable_5, n2209, CmdEnable_N_248, + C1Submitted_N_237, n2478, n2477, n2138, n1410, n2290, Cmdn8MEGEN_N_264, + XOR8MEG_N_110, n2208, LEDEN_N_82, n2243, RCLK_c_enable_24, + n2476, n2475, n8MEGEN_N_91, UFMCLK_N_224, UFMSDI_N_231, n2460, + n2227, n2253, n726, n727, n728, n729, n730, n1502, n732, + n733, n734, n735, n736, n737, n738, n2284, n2463, n2164, + PHI2_N_120_enable_4, n1325, n2278, n1503, n2214, n1417, + n2010, n2474, n2009, n1280, n33, n2473, n2263, n56, + PHI2_N_120_enable_1, n12, n10, n13, n2272, Dout_c, n78, + n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, + n89, n90, n91, n92, n93, n94, n95, n15_adj_1, n1, + n2462, n2472, n2471, n1093, RCLK_c_enable_11, n62, RCLK_c_enable_25, + n2470, n2242, n2461, RCLK_c_enable_23, RCLK_c_enable_12, n2451, + n2014, n14, n13_adj_2, n2568, n2245, PHI2_N_120_enable_7, + RCLK_c_enable_4, n2469, n1413, n1846, Dout_0, Dout_1, n984, + Dout_2, Dout_3, Dout_4, n1314, Dout_5, Dout_6, n2468, + n1160, n2337, n2008, n2013, n6_adj_3, RCLK_c_enable_3, n2467, + n2012, n2479, n1326, n2464, n8, n2481, n2430, n2459, + n2458, n2427, n2480, n11, n26; + + VHI i2 (.Z(VCC_net)); + INV i2136 (.A(PHI2_c), .Z(PHI2_N_120)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) + ORCALUT4 i6_4_lut (.A(FS[17]), .B(n12), .C(FS[12]), .D(FS[14]), + .Z(n62)) /* synthesis lut_function=(A (B (C (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i6_4_lut.init = 16'h8000; + ORCALUT4 i1_4_lut_4_lut (.A(Din_c_3), .B(Din_c_5), .C(Din_c_4), .D(n2458), + .Z(PHI2_N_120_enable_4)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A !(B+!(D))) */ ; + defparam i1_4_lut_4_lut.init = 16'hb300; + FD1S3AX PHI2r2_377 (.D(PHI2r), .CK(RCLK_c), .Q(PHI2r2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam PHI2r2_377.GSR = "ENABLED"; + ORCALUT4 i1994_3_lut (.A(FS[2]), .B(FS[5]), .C(FS[9]), .Z(n2290)) /* synthesis lut_function=(A+(B+(C))) */ ; + defparam i1994_3_lut.init = 16'hfefe; + ORCALUT4 i1_2_lut_3_lut (.A(MAin_c_0), .B(n1326), .C(MAin_c_1), .Z(n2263)) /* synthesis lut_function=((B+!(C))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(80[15:31]) + defparam i1_2_lut_3_lut.init = 16'hdfdf; + FD1S3AX PHI2r3_378 (.D(PHI2r2), .CK(RCLK_c), .Q(PHI2r3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam PHI2r3_378.GSR = "ENABLED"; + FD1S3AX RASr_379 (.D(nCRAS_N_9), .CK(RCLK_c), .Q(RASr)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam RASr_379.GSR = "ENABLED"; + FD1S3AX RASr2_380 (.D(RASr), .CK(RCLK_c), .Q(RASr2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam RASr2_380.GSR = "ENABLED"; + FD1S3AX RASr3_381 (.D(RASr2), .CK(RCLK_c), .Q(RASr3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam RASr3_381.GSR = "ENABLED"; + FD1S3AX CASr_382 (.D(nCCAS_N_3), .CK(RCLK_c), .Q(CASr)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam CASr_382.GSR = "ENABLED"; + FD1S3AX CASr2_383 (.D(CASr), .CK(RCLK_c), .Q(CASr2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam CASr2_383.GSR = "ENABLED"; + FD1S3AX CASr3_384 (.D(CASr2), .CK(RCLK_c), .Q(CASr3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam CASr3_384.GSR = "ENABLED"; + FD1S3IX RA11_385 (.D(RA11_N_184), .CK(PHI2_c), .CD(n2477), .Q(RA_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam RA11_385.GSR = "ENABLED"; + FD1S3IX RowA_i0 (.D(MAin_c_0), .CK(nCRAS_N_9), .CD(n2477), .Q(RowA[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i0.GSR = "ENABLED"; + ORCALUT4 i637_1_lut_rep_34 (.A(Ready), .Z(n2477)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i637_1_lut_rep_34.init = 16'h5555; + FD1S3AX WRD_i0 (.D(Din_c_0), .CK(nCCAS_N_3), .Q(WRD[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i0.GSR = "ENABLED"; + FD1S3AX FWEr_389 (.D(nFWE_N_5), .CK(nCRAS_N_9), .Q(FWEr)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam FWEr_389.GSR = "ENABLED"; + FD1S3AX CBR_390 (.D(nCCAS_N_3), .CK(nCRAS_N_9), .Q(CBR)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam CBR_390.GSR = "ENABLED"; + FD1S3IX ADSubmitted_407 (.D(n1413), .CK(PHI2_N_120), .CD(C1Submitted_N_237), + .Q(ADSubmitted)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam ADSubmitted_407.GSR = "ENABLED"; + ORCALUT4 i2026_4_lut (.A(FS[0]), .B(FS[1]), .C(FS[6]), .D(FS[3]), + .Z(n2322)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; + defparam i2026_4_lut.init = 16'hfffe; + FD1S3AX RCKE_395 (.D(RCKE_N_132), .CK(RCLK_c), .Q(RCKE_c)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(141[9] 144[5]) + defparam RCKE_395.GSR = "ENABLED"; + FD1P3AY nRCS_396 (.D(nRCS_N_136), .SP(RCLK_c_enable_4), .CK(RCLK_c), + .Q(nRCS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRCS_396.GSR = "ENABLED"; + FD1S3IX nRowColSel_402 (.D(n1410), .CK(RCLK_c), .CD(n2469), .Q(nRowColSel)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRowColSel_402.GSR = "ENABLED"; + ORCALUT4 n8MEGEN_I_14_4_lut (.A(UFMSDO_c), .B(Cmdn8MEGEN), .C(InitReady), + .D(n1325), .Z(n8MEGEN_N_91)) /* synthesis lut_function=(A (B (C+(D)))+!A (B+!(C+(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(394[12] 409[6]) + defparam n8MEGEN_I_14_4_lut.init = 16'hccc5; + ORCALUT4 i771_2_lut_rep_26_2_lut (.A(Ready), .B(nRowColSel_N_35), .Z(n2469)) /* synthesis lut_function=((B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i771_2_lut_rep_26_2_lut.init = 16'hdddd; + ORCALUT4 i7_4_lut (.A(FS[10]), .B(n2328), .C(n2272), .D(FS[11]), + .Z(n2214)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i7_4_lut.init = 16'h0200; + ORCALUT4 i2062_2_lut_3_lut_4_lut (.A(nFWE_c), .B(n1326), .C(C1Submitted), + .D(MAin_c_1), .Z(n6_adj_3)) /* synthesis lut_function=(A (C)+!A (B (C)+!B !((D)+!C))) */ ; + defparam i2062_2_lut_3_lut_4_lut.init = 16'he0f0; + ORCALUT4 i2046_1_lut_2_lut_3_lut_3_lut (.A(Ready), .B(n13), .C(nRCS_N_139), + .Z(n2337)) /* synthesis lut_function=(!(A (B)+!A !((C)+!B))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i2046_1_lut_2_lut_3_lut_3_lut.init = 16'h7373; + ORCALUT4 i3_3_lut_4_lut_4_lut (.A(Ready), .B(InitReady), .C(RASr2), + .D(nRowColSel_N_35), .Z(RCLK_c_enable_23)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i3_3_lut_4_lut_4_lut.init = 16'h4000; + ORCALUT4 i2065_2_lut_3_lut (.A(FS[11]), .B(n2464), .C(InitReady), + .Z(n1846)) /* synthesis lut_function=(!(A+(B+(C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i2065_2_lut_3_lut.init = 16'h0101; + ORCALUT4 i2055_3_lut_4_lut (.A(FS[11]), .B(n2464), .C(FS[10]), .D(InitReady), + .Z(LEDEN_N_82)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i2055_3_lut_4_lut.init = 16'h0001; + ORCALUT4 i2_3_lut (.A(n2214), .B(FS[11]), .C(InitReady), .Z(RCLK_c_enable_12)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam i2_3_lut.init = 16'h0808; + CCU2 FS_610_add_4_8 (.A0(FS[6]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[7]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2010), + .COUT1(n2011), .S0(n89), .S1(n88)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_8.INIT0 = 16'hfaaa; + defparam FS_610_add_4_8.INIT1 = 16'hfaaa; + defparam FS_610_add_4_8.INJECT1_0 = "NO"; + defparam FS_610_add_4_8.INJECT1_1 = "NO"; + FD1S3IX S_FSM_i3 (.D(n1093), .CK(RCLK_c), .CD(n1425), .Q(nRowColSel_N_33)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam S_FSM_i3.GSR = "ENABLED"; + ORCALUT4 Ready_bdd_4_lut (.A(nRowColSel_N_32), .B(RASr2), .C(Ready_N_296), + .D(InitReady), .Z(n2414)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ; + defparam Ready_bdd_4_lut.init = 16'h2000; + FD1S3AY nRRAS_397 (.D(n2138), .CK(RCLK_c), .Q(nRRAS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRRAS_397.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_2_lut (.A(Ready), .B(nRowColSel_N_34), .Z(n56)) /* synthesis lut_function=((B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i1_2_lut_2_lut.init = 16'hdddd; + ORCALUT4 i2_4_lut (.A(Din_c_2), .B(n2463), .C(n1280), .D(n2468), + .Z(C1Submitted_N_237)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ; + defparam i2_4_lut.init = 16'h0400; + ORCALUT4 i1_2_lut_3_lut_4_lut_4_lut (.A(Ready), .B(nRowColSel_N_32), + .C(n1502), .D(nRowColSel_N_35), .Z(RCLK_c_enable_3)) /* synthesis lut_function=((B+(C+(D)))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i1_2_lut_3_lut_4_lut_4_lut.init = 16'hfffd; + ORCALUT4 Din_7__I_0_462_i6_2_lut_rep_35 (.A(Din_c_6), .B(Din_c_7), .Z(n2478)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(315[17:31]) + defparam Din_7__I_0_462_i6_2_lut_rep_35.init = 16'heeee; + BB Dout_pad_7__713 (.I(WRD[7]), .T(n984), .B(RD[7]), .O(Dout_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + FD1P3AY nRCAS_398 (.D(nRCAS_N_161), .SP(RCLK_c_enable_4), .CK(RCLK_c), + .Q(nRCAS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRCAS_398.GSR = "ENABLED"; + FD1P3AY nRWE_399 (.D(nRWE_N_171), .SP(RCLK_c_enable_3), .CK(RCLK_c), + .Q(nRWE_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRWE_399.GSR = "ENABLED"; + FD1S3JX RA10_400 (.D(n2209), .CK(RCLK_c), .PD(nRWE_N_176), .Q(RA_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam RA10_400.GSR = "ENABLED"; + FD1P3AX RCKEEN_401 (.D(RCKEEN_N_121), .SP(RCLK_c_enable_4), .CK(RCLK_c), + .Q(RCKEEN)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam RCKEEN_401.GSR = "ENABLED"; + FD1S3AX FS_610__i0 (.D(n95), .CK(RCLK_c), .Q(FS[0])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i0.GSR = "ENABLED"; + ORCALUT4 i13_4_lut (.A(MAin_c_2), .B(n26), .C(n2316), .D(MAin_c_5), + .Z(n1326)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ; + defparam i13_4_lut.init = 16'hdfff; + ORCALUT4 i12_4_lut (.A(Bank[2]), .B(n2314), .C(n2278), .D(Bank[5]), + .Z(n26)) /* synthesis lut_function=(A+!(B (C (D)))) */ ; + defparam i12_4_lut.init = 16'hbfff; + ORCALUT4 i2_3_lut_adj_1 (.A(MAin_c_1), .B(n1326), .C(MAin_c_0), .Z(n1280)) /* synthesis lut_function=((B+(C))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(80[15:31]) + defparam i2_3_lut_adj_1.init = 16'hfdfd; + FD1S3IX RBA__i1 (.D(CROW_c_0), .CK(nCRAS_N_9), .CD(n2477), .Q(RBA_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RBA__i1.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_3_lut_adj_2 (.A(Din_c_6), .B(Din_c_7), .C(Din_c_5), + .Z(n1314)) /* synthesis lut_function=(A+(B+(C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(315[17:31]) + defparam i1_2_lut_3_lut_adj_2.init = 16'hfefe; + ORCALUT4 i2020_4_lut (.A(MAin_c_7), .B(MAin_c_3), .C(Bank[4]), .D(Bank[1]), + .Z(n2316)) /* synthesis lut_function=(A (B (C (D)))) */ ; + defparam i2020_4_lut.init = 16'h8000; + ORCALUT4 i1990_2_lut_rep_17 (.A(nFWE_c), .B(n1326), .Z(n2460)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1990_2_lut_rep_17.init = 16'heeee; + ORCALUT4 i1125_4_lut (.A(n2459), .B(n2242), .C(ADSubmitted), .D(n2263), + .Z(n1413)) /* synthesis lut_function=(!(A ((D)+!B)+!A !(B (C+!(D))+!B (C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam i1125_4_lut.init = 16'h50dc; + ORCALUT4 i2018_4_lut (.A(MAin_c_6), .B(MAin_c_4), .C(Bank[7]), .D(Bank[0]), + .Z(n2314)) /* synthesis lut_function=(A (B (C (D)))) */ ; + defparam i2018_4_lut.init = 16'h8000; + ORCALUT4 i4_4_lut (.A(Din_c_4), .B(n2478), .C(CmdEnable), .D(MAin_c_1), + .Z(n10)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ; + defparam i4_4_lut.init = 16'h0020; + ORCALUT4 i2_2_lut_rep_27 (.A(FS[16]), .B(FS[14]), .Z(n2470)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i2_2_lut_rep_27.init = 16'heeee; + ORCALUT4 i2_3_lut_4_lut (.A(nRowColSel_N_32), .B(n2469), .C(nRowColSel_N_34), + .D(nRowColSel_N_33), .Z(RCLK_c_enable_4)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i2_3_lut_4_lut.init = 16'hfffe; + ORCALUT4 Cmdn8MEGEN_I_93_4_lut (.A(Din_c_0), .B(n8MEGEN), .C(Din_c_4), + .D(n1314), .Z(Cmdn8MEGEN_N_264)) /* synthesis lut_function=(A (B ((D)+!C))+!A (B+!((D)+!C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(321[13] 335[7]) + defparam Cmdn8MEGEN_I_93_4_lut.init = 16'hcc5c; + ORCALUT4 i1982_2_lut (.A(Bank[6]), .B(Bank[3]), .Z(n2278)) /* synthesis lut_function=(A (B)) */ ; + defparam i1982_2_lut.init = 16'h8888; + ORCALUT4 i2_4_lut_adj_3 (.A(Din_c_3), .B(Din_c_4), .C(Din_c_5), .D(n2458), + .Z(PHI2_N_120_enable_5)) /* synthesis lut_function=(A (B (D))+!A !((C+!(D))+!B)) */ ; + defparam i2_4_lut_adj_3.init = 16'h8c00; + FD1P3AX IS_FSM__i0 (.D(Ready_N_296), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(nRCS_N_139)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i0.GSR = "ENABLED"; + FD1S3JX C1Submitted_406 (.D(n6_adj_3), .CK(PHI2_N_120), .PD(C1Submitted_N_237), + .Q(C1Submitted)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam C1Submitted_406.GSR = "ENABLED"; + FD1S3JX nUFMCS_415 (.D(n2164), .CK(RCLK_c), .PD(LEDEN_N_82), .Q(nUFMCS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam nUFMCS_415.GSR = "ENABLED"; + ORCALUT4 i2049_3_lut (.A(LEDEN), .B(CBR), .C(nCRAS_c), .Z(LED_N_84)) /* synthesis lut_function=((B+(C))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(23[15:41]) + defparam i2049_3_lut.init = 16'hfdfd; + ORCALUT4 MAin_9__I_0_427_i10_3_lut (.A(RowA[9]), .B(MAin_c_9), .C(nRowColSel), + .Z(RA_1_9)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i10_3_lut.init = 16'hcaca; + FD1S3AX S_FSM_i1 (.D(RASr2_N_63), .CK(RCLK_c), .Q(nRowColSel_N_35)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam S_FSM_i1.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_3_lut_adj_4 (.A(FS[11]), .B(n2464), .C(FS[10]), + .Z(n1325)) /* synthesis lut_function=((B+!(C))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i1_2_lut_3_lut_adj_4.init = 16'hdfdf; + ORCALUT4 MAin_9__I_0_427_i9_3_lut (.A(RowA[8]), .B(MAin_c_8), .C(nRowColSel), + .Z(RA_1_8)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i9_3_lut.init = 16'hcaca; + ORCALUT4 MAin_9__I_0_427_i8_3_lut (.A(RowA[7]), .B(MAin_c_7), .C(nRowColSel), + .Z(RA_1_7)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i8_3_lut.init = 16'hcaca; + ORCALUT4 i1209_4_lut_else_4_lut (.A(nRCS_N_139), .B(Ready), .C(nRowColSel_N_35), + .Z(n2479)) /* synthesis lut_function=(!(A (B (C))+!A (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(48[6:16]) + defparam i1209_4_lut_else_4_lut.init = 16'h2f2f; + ORCALUT4 i1_2_lut_3_lut_adj_5 (.A(MAin_c_0), .B(n1326), .C(MAin_c_1), + .Z(n2262)) /* synthesis lut_function=((B+(C))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(80[15:31]) + defparam i1_2_lut_3_lut_adj_5.init = 16'hfdfd; + ORCALUT4 i2045_1_lut_4_lut (.A(n56), .B(nRRAS_c), .C(n6), .D(nRowColSel_N_32), + .Z(n2336)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; + defparam i2045_1_lut_4_lut.init = 16'hfffe; + FD1S3AX Bank_i0 (.D(Din_c_0), .CK(PHI2_c), .Q(Bank[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i0.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_4_lut (.A(MAin_c_0), .B(n10), .C(n2460), .D(n2476), + .Z(PHI2_N_120_enable_6)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ; + defparam i1_2_lut_4_lut.init = 16'h0800; + ORCALUT4 i2_3_lut_rep_29 (.A(PHI2r3), .B(CmdSubmitted), .C(PHI2r2), + .Z(n2472)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(402[16:47]) + defparam i2_3_lut_rep_29.init = 16'h0808; + ORCALUT4 nRowColSel_N_34_bdd_3_lut_2115 (.A(nRowColSel_N_34), .B(n15_adj_1), + .C(Ready), .Z(n2430)) /* synthesis lut_function=(A+!(B (C))) */ ; + defparam nRowColSel_N_34_bdd_3_lut_2115.init = 16'hbfbf; + ORCALUT4 i4_4_lut_adj_6 (.A(MAin_c_1), .B(n2476), .C(MAin_c_0), .D(n2284), + .Z(n2257)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ; + defparam i4_4_lut_adj_6.init = 16'h0080; + FD1S3AX PHI2r_376 (.D(PHI2_c), .CK(RCLK_c), .Q(PHI2r)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam PHI2r_376.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_4_lut_adj_7 (.A(PHI2r3), .B(CmdSubmitted), .C(PHI2r2), + .D(InitReady), .Z(RCLK_c_enable_24)) /* synthesis lut_function=(!(A (B (C (D))+!B (D))+!A (D))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(402[16:47]) + defparam i1_2_lut_4_lut_adj_7.init = 16'h08ff; + ORCALUT4 i2024_2_lut_rep_28 (.A(FS[17]), .B(FS[12]), .Z(n2471)) /* synthesis lut_function=(A+(B)) */ ; + defparam i2024_2_lut_rep_28.init = 16'heeee; + FD1S3IX S_FSM_i4 (.D(n1503), .CK(RCLK_c), .CD(RASr2_N_63), .Q(nRowColSel_N_32)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam S_FSM_i4.GSR = "ENABLED"; + CCU2 FS_610_add_4_16 (.A0(FS[14]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[15]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2014), + .COUT1(n2015), .S0(n81), .S1(n80)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_16.INIT0 = 16'hfaaa; + defparam FS_610_add_4_16.INIT1 = 16'hfaaa; + defparam FS_610_add_4_16.INJECT1_0 = "NO"; + defparam FS_610_add_4_16.INJECT1_1 = "NO"; + ORCALUT4 i2_3_lut_4_lut_adj_8 (.A(nRowColSel_N_35), .B(RASr2), .C(InitReady), + .D(nRCS_N_139), .Z(n2208)) /* synthesis lut_function=((((D)+!C)+!B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i2_3_lut_4_lut_adj_8.init = 16'hff7f; + ORCALUT4 i1_4_lut_4_lut_adj_9 (.A(CBR), .B(n11), .C(FWEr), .D(nRowColSel_N_34), + .Z(RCKEEN_N_123)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(23[27:31]) + defparam i1_4_lut_4_lut_adj_9.init = 16'h5540; + ORCALUT4 i3_4_lut (.A(CBR), .B(FWEr), .C(CASr2), .D(CASr3), .Z(n1)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ; + defparam i3_4_lut.init = 16'h0040; + PFUMX i2095 (.BLUT(n2430), .ALUT(n2457), .C0(nRowColSel_N_35), .Z(nRCAS_N_161)); + ORCALUT4 MAin_9__I_0_427_i7_3_lut (.A(RowA[6]), .B(MAin_c_6), .C(nRowColSel), + .Z(RA_1_6)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i7_3_lut.init = 16'hcaca; + ORCALUT4 i1_4_lut (.A(nRowColSel), .B(n1502), .C(nRowColSel_N_28), + .D(nRowColSel_N_32), .Z(n1410)) /* synthesis lut_function=(A (B+!(C (D)))+!A (B+!(C+!(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i1_4_lut.init = 16'hcfee; + ORCALUT4 i1_2_lut (.A(RASr2), .B(RCKE_c), .Z(nRWE_N_182)) /* synthesis lut_function=(A+!(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam i1_2_lut.init = 16'hbbbb; + ORCALUT4 i2004_2_lut_rep_30 (.A(Din_c_4), .B(nFWE_c), .Z(n2473)) /* synthesis lut_function=(A+(B)) */ ; + defparam i2004_2_lut_rep_30.init = 16'heeee; + ORCALUT4 i1_2_lut_rep_20_3_lut (.A(Din_c_4), .B(nFWE_c), .C(n2253), + .Z(n2463)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ; + defparam i1_2_lut_rep_20_3_lut.init = 16'h1010; + ORCALUT4 i2_3_lut_adj_10 (.A(Din_c_7), .B(Din_c_0), .C(Din_c_1), .Z(n2253)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ; + defparam i2_3_lut_adj_10.init = 16'h0808; + CCU2 FS_610_add_4_6 (.A0(FS[4]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[5]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2009), + .COUT1(n2010), .S0(n91), .S1(n90)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_6.INIT0 = 16'hfaaa; + defparam FS_610_add_4_6.INIT1 = 16'hfaaa; + defparam FS_610_add_4_6.INJECT1_0 = "NO"; + defparam FS_610_add_4_6.INJECT1_1 = "NO"; + ORCALUT4 i2_4_lut_adj_11 (.A(n2473), .B(CmdEnable), .C(n2262), .D(n1314), + .Z(PHI2_N_120_enable_1)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ; + defparam i2_4_lut_adj_11.init = 16'h0004; + ORCALUT4 MAin_9__I_0_427_i6_3_lut (.A(RowA[5]), .B(MAin_c_5), .C(nRowColSel), + .Z(RA_1_5)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i6_3_lut.init = 16'hcaca; + ORCALUT4 i3_4_lut_adj_12 (.A(Din_c_0), .B(Din_c_3), .C(Din_c_2), .D(n2324), + .Z(XOR8MEG_N_110)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ; + defparam i3_4_lut_adj_12.init = 16'h0020; + ORCALUT4 MAin_9__I_0_427_i5_3_lut (.A(RowA[4]), .B(MAin_c_4), .C(nRowColSel), + .Z(RA_1_4)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i5_3_lut.init = 16'hcaca; + ORCALUT4 i2028_4_lut (.A(Din_c_4), .B(LEDEN), .C(n1314), .D(Din_c_1), + .Z(n2324)) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ; + defparam i2028_4_lut.init = 16'hfefa; + ORCALUT4 MAin_9__I_0_427_i4_3_lut (.A(RowA[3]), .B(MAin_c_3), .C(nRowColSel), + .Z(RA_1_3)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i4_3_lut.init = 16'hcaca; + ORCALUT4 i2_3_lut_rep_31 (.A(Din_c_6), .B(Din_c_2), .C(Din_c_3), .Z(n2474)) /* synthesis lut_function=(!(A+!(B (C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) + defparam i2_3_lut_rep_31.init = 16'h4040; + FD1P3IX UFMSDI_417 (.D(UFMSDI_N_231), .SP(RCLK_c_enable_24), .CD(n1846), + .CK(RCLK_c), .Q(UFMSDI_c)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam UFMSDI_417.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_4_lut_adj_13 (.A(Din_c_6), .B(Din_c_2), .C(Din_c_3), + .D(MAin_c_0), .Z(n2243)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) + defparam i1_2_lut_4_lut_adj_13.init = 16'h4000; + ORCALUT4 MAin_9__I_0_427_i3_3_lut (.A(RowA[2]), .B(MAin_c_2), .C(nRowColSel), + .Z(RA_1_2)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i3_3_lut.init = 16'hcaca; + ORCALUT4 n2427_bdd_4_lut_4_lut (.A(CBR), .B(RASr2), .C(Ready), .D(n2427), + .Z(n2457)) /* synthesis lut_function=(!(A (B (C+!(D)))+!A !((C+(D))+!B))) */ ; + defparam n2427_bdd_4_lut_4_lut.init = 16'h7f73; + GSR GSR_INST (.GSR(VCC_net)); + ORCALUT4 i2_3_lut_adj_14 (.A(FWEr), .B(CASr3), .C(CBR), .Z(nRowColSel_N_28)) /* synthesis lut_function=((B+(C))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(230[16:37]) + defparam i2_3_lut_adj_14.init = 16'hfdfd; + ORCALUT4 InitReady_bdd_3_lut (.A(InitReady), .B(nRCS_N_139), .C(nRCAS_N_165), + .Z(n2427)) /* synthesis lut_function=((B+(C))+!A) */ ; + defparam InitReady_bdd_3_lut.init = 16'hfdfd; + ORCALUT4 i35_3_lut_4_lut (.A(FWEr), .B(CBR), .C(nRowColSel_N_33), + .D(n1), .Z(n15_adj_1)) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C+(D))))) */ ; + defparam i35_3_lut_4_lut.init = 16'h1f10; + ORCALUT4 MAin_9__I_0_427_i2_3_lut (.A(RowA[1]), .B(MAin_c_1), .C(nRowColSel), + .Z(RA_1_1)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i2_3_lut.init = 16'hcaca; + CCU2 FS_610_add_4_14 (.A0(FS[12]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[13]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2013), + .COUT1(n2014), .S0(n83), .S1(n82)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_14.INIT0 = 16'hfaaa; + defparam FS_610_add_4_14.INIT1 = 16'hfaaa; + defparam FS_610_add_4_14.INJECT1_0 = "NO"; + defparam FS_610_add_4_14.INJECT1_1 = "NO"; + ORCALUT4 i2_3_lut_4_lut_adj_15 (.A(n2473), .B(n2253), .C(Din_c_5), + .D(n2474), .Z(n2242)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ; + defparam i2_3_lut_4_lut_adj_15.init = 16'h4000; + ORCALUT4 n2414_bdd_2_lut (.A(n2414), .B(Ready), .Z(Ready_N_292)) /* synthesis lut_function=(A+(B)) */ ; + defparam n2414_bdd_2_lut.init = 16'heeee; + ORCALUT4 i1_2_lut_adj_16 (.A(nRowColSel_N_34), .B(nRowColSel_N_33), + .Z(n1502)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i1_2_lut_adj_16.init = 16'heeee; + ORCALUT4 RCKE_I_0_449_4_lut (.A(RASr), .B(RCKEEN), .C(RASr2), .D(RASr3), + .Z(RCKE_N_132)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B (C+(D))+!B !(C+!(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(143[11:55]) + defparam RCKE_I_0_449_4_lut.init = 16'hcfc8; + ORCALUT4 i1_4_lut_adj_17 (.A(n2467), .B(n2481), .C(n13), .D(nRowColSel_N_35), + .Z(nRCS_N_136)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B+!(C (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(48[6:16]) + defparam i1_4_lut_adj_17.init = 16'hcfdd; + FD1P3AX IS_FSM__i15 (.D(n726), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(Ready_N_296)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i15.GSR = "ENABLED"; + ORCALUT4 MAin_9__I_0_427_i1_3_lut (.A(RowA[0]), .B(MAin_c_0), .C(nRowColSel), + .Z(RA_1_0)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i1_3_lut.init = 16'hcaca; + ORCALUT4 i1558_2_lut_3_lut (.A(FWEr), .B(CBR), .C(RASr2), .Z(RCKEEN_N_130)) /* synthesis lut_function=(!(A (C)+!A (B (C)))) */ ; + defparam i1558_2_lut_3_lut.init = 16'h1f1f; + ORCALUT4 RA11_I_54_3_lut (.A(Din_c_6), .B(XOR8MEG), .C(n8MEGEN), .Z(RA11_N_184)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A (B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(99[22:51]) + defparam RA11_I_54_3_lut.init = 16'hc6c6; + ORCALUT4 i17_4_lut (.A(n7), .B(n2472), .C(InitReady), .D(n8), .Z(RCLK_c_enable_11)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ; + defparam i17_4_lut.init = 16'hcac0; + ORCALUT4 i1234_4_lut_4_lut (.A(RASr2), .B(InitReady), .C(RCKE_c), + .D(Ready), .Z(n13)) /* synthesis lut_function=(A (B+(D))+!A (C (D))) */ ; + defparam i1234_4_lut_4_lut.init = 16'hfa88; + ORCALUT4 i2_2_lut (.A(FS[8]), .B(n2214), .Z(n7)) /* synthesis lut_function=(!(A+!(B))) */ ; + defparam i2_2_lut.init = 16'h4444; + ORCALUT4 i78_2_lut_rep_24_3_lut (.A(RASr2), .B(InitReady), .C(Ready), + .Z(n2467)) /* synthesis lut_function=(A (B+(C))+!A (C)) */ ; + defparam i78_2_lut_rep_24_3_lut.init = 16'hf8f8; + FD1P3AX IS_FSM__i14 (.D(n727), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n726)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i14.GSR = "ENABLED"; + FD1P3AX IS_FSM__i13 (.D(n728), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n727)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i13.GSR = "ENABLED"; + ORCALUT4 i2_2_lut_3_lut_4_lut (.A(RASr2), .B(InitReady), .C(nRowColSel_N_33), + .D(Ready), .Z(n6)) /* synthesis lut_function=(A (B (C)+!B (C+!(D)))+!A (C+!(D))) */ ; + defparam i2_2_lut_3_lut_4_lut.init = 16'hf0f7; + ORCALUT4 i1512_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQMH_c)) /* synthesis lut_function=(A+!(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(58[17:46]) + defparam i1512_2_lut.init = 16'hbbbb; + ORCALUT4 i1_1_lut (.A(nFWE_c), .Z(nFWE_N_5)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam i1_1_lut.init = 16'h5555; + FD1P3AX IS_FSM__i12 (.D(n729), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n728)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i12.GSR = "ENABLED"; + FD1P3AX XOR8MEG_408 (.D(XOR8MEG_N_110), .SP(PHI2_N_120_enable_1), .CK(PHI2_N_120), + .Q(XOR8MEG)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam XOR8MEG_408.GSR = "ENABLED"; + FD1P3AX n8MEGEN_418 (.D(n8MEGEN_N_91), .SP(RCLK_c_enable_11), .CK(RCLK_c), + .Q(n8MEGEN)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam n8MEGEN_418.GSR = "ENABLED"; + FD1P3AX LEDEN_419 (.D(n2568), .SP(RCLK_c_enable_12), .CK(RCLK_c), + .Q(LEDEN)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam LEDEN_419.GSR = "ENABLED"; + PFUMX i16 (.BLUT(n2336), .ALUT(n2337), .C0(nRowColSel_N_35), .Z(n2138)); + FD1P3AX Ready_404 (.D(n2568), .SP(Ready_N_292), .CK(RCLK_c), .Q(Ready)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam Ready_404.GSR = "ENABLED"; + FD1P3AX CmdUFMCLK_413 (.D(Din_c_1), .SP(PHI2_N_120_enable_6), .CK(PHI2_N_120), + .Q(CmdUFMCLK)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdUFMCLK_413.GSR = "ENABLED"; + FD1P3AX CmdUFMSDI_414 (.D(Din_c_0), .SP(PHI2_N_120_enable_6), .CK(PHI2_N_120), + .Q(CmdUFMSDI)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdUFMSDI_414.GSR = "ENABLED"; + FD1P3AX Cmdn8MEGEN_410 (.D(Cmdn8MEGEN_N_264), .SP(PHI2_N_120_enable_4), + .CK(PHI2_N_120), .Q(Cmdn8MEGEN)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam Cmdn8MEGEN_410.GSR = "ENABLED"; + FD1P3AX CmdSubmitted_411 (.D(n2568), .SP(PHI2_N_120_enable_5), .CK(PHI2_N_120), + .Q(CmdSubmitted)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdSubmitted_411.GSR = "ENABLED"; + FD1P3AX CmdUFMCS_412 (.D(Din_c_2), .SP(PHI2_N_120_enable_6), .CK(PHI2_N_120), + .Q(CmdUFMCS)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdUFMCS_412.GSR = "ENABLED"; + FD1P3AX IS_FSM__i11 (.D(n730), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n729)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i11.GSR = "ENABLED"; + ORCALUT4 i2060_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQML_c)) /* synthesis lut_function=(!(A (B))) */ ; + defparam i2060_2_lut.init = 16'h7777; + ORCALUT4 i1_2_lut_rep_32 (.A(Din_c_6), .B(Din_c_3), .Z(n2475)) /* synthesis lut_function=(!((B)+!A)) */ ; + defparam i1_2_lut_rep_32.init = 16'h2222; + FD1P3AX IS_FSM__i10 (.D(nRWE_N_177), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n730)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i10.GSR = "ENABLED"; + ORCALUT4 i3_4_lut_adj_18 (.A(n2290), .B(FS[4]), .C(n2322), .D(FS[7]), + .Z(n8)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ; + defparam i3_4_lut_adj_18.init = 16'h0004; + ORCALUT4 i886_3_lut (.A(CmdUFMCLK), .B(n1160), .C(InitReady), .Z(UFMCLK_N_224)) /* synthesis lut_function=(A (B+(C))+!A !((C)+!B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(386[12] 409[6]) + defparam i886_3_lut.init = 16'hacac; + FD1P3AX IS_FSM__i9 (.D(n732), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(nRWE_N_177)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i9.GSR = "ENABLED"; + ORCALUT4 i2_3_lut_4_lut_adj_19 (.A(Din_c_6), .B(Din_c_3), .C(Din_c_2), + .D(MAin_c_0), .Z(n2245)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ; + defparam i2_3_lut_4_lut_adj_19.init = 16'h0002; + ORCALUT4 i919_4_lut (.A(FS[4]), .B(n62), .C(n2462), .D(FS[1]), .Z(n1160)) /* synthesis lut_function=(!(A (B (C)+!B !((D)+!C))+!A (B+!(C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(386[12] 409[6]) + defparam i919_4_lut.init = 16'h3a0a; + ORCALUT4 i2052_4_lut (.A(MAin_c_0), .B(n2460), .C(n14), .D(MAin_c_1), + .Z(PHI2_N_120_enable_7)) /* synthesis lut_function=(!(A (B+(C))+!A (B+(C+!(D))))) */ ; + defparam i2052_4_lut.init = 16'h0302; + ORCALUT4 i2_3_lut_adj_20 (.A(n2253), .B(Din_c_4), .C(n13_adj_2), .Z(n14)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ; + defparam i2_3_lut_adj_20.init = 16'h2020; + ORCALUT4 i1136_1_lut (.A(nRowColSel_N_34), .Z(n1425)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i1136_1_lut.init = 16'h5555; + FD1P3AX IS_FSM__i8 (.D(n733), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n732)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i8.GSR = "ENABLED"; + FD1P3AX IS_FSM__i7 (.D(n734), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n733)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i7.GSR = "ENABLED"; + FD1P3AX IS_FSM__i6 (.D(n735), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n734)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i6.GSR = "ENABLED"; + FD1P3AX IS_FSM__i5 (.D(n736), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n735)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i5.GSR = "ENABLED"; + FD1P3AX IS_FSM__i4 (.D(n737), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n736)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i4.GSR = "ENABLED"; + FD1P3AX IS_FSM__i3 (.D(n738), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n737)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i3.GSR = "ENABLED"; + FD1P3AX IS_FSM__i2 (.D(nRCAS_N_165), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n738)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i2.GSR = "ENABLED"; + FD1P3AX IS_FSM__i1 (.D(nRCS_N_139), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(nRCAS_N_165)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i1.GSR = "ENABLED"; + FD1S3IX RBA__i2 (.D(CROW_c_1), .CK(nCRAS_N_9), .CD(n2477), .Q(RBA_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RBA__i2.GSR = "ENABLED"; + FD1S3AX FS_610__i17 (.D(n78), .CK(RCLK_c), .Q(FS[17])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i17.GSR = "ENABLED"; + FD1S3AX FS_610__i16 (.D(n79), .CK(RCLK_c), .Q(FS[16])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i16.GSR = "ENABLED"; + FD1S3AX FS_610__i15 (.D(n80), .CK(RCLK_c), .Q(FS[15])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i15.GSR = "ENABLED"; + FD1S3AX FS_610__i14 (.D(n81), .CK(RCLK_c), .Q(FS[14])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i14.GSR = "ENABLED"; + FD1S3AX FS_610__i13 (.D(n82), .CK(RCLK_c), .Q(FS[13])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i13.GSR = "ENABLED"; + FD1S3AX FS_610__i12 (.D(n83), .CK(RCLK_c), .Q(FS[12])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i12.GSR = "ENABLED"; + FD1S3AX FS_610__i11 (.D(n84), .CK(RCLK_c), .Q(FS[11])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i11.GSR = "ENABLED"; + FD1S3AX FS_610__i10 (.D(n85), .CK(RCLK_c), .Q(FS[10])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i10.GSR = "ENABLED"; + FD1S3AX FS_610__i9 (.D(n86), .CK(RCLK_c), .Q(FS[9])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i9.GSR = "ENABLED"; + FD1S3AX FS_610__i8 (.D(n87), .CK(RCLK_c), .Q(FS[8])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i8.GSR = "ENABLED"; + FD1S3AX FS_610__i7 (.D(n88), .CK(RCLK_c), .Q(FS[7])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i7.GSR = "ENABLED"; + FD1S3AX FS_610__i6 (.D(n89), .CK(RCLK_c), .Q(FS[6])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i6.GSR = "ENABLED"; + FD1S3AX FS_610__i5 (.D(n90), .CK(RCLK_c), .Q(FS[5])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i5.GSR = "ENABLED"; + FD1S3AX FS_610__i4 (.D(n91), .CK(RCLK_c), .Q(FS[4])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i4.GSR = "ENABLED"; + FD1S3AX FS_610__i3 (.D(n92), .CK(RCLK_c), .Q(FS[3])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i3.GSR = "ENABLED"; + FD1S3AX FS_610__i2 (.D(n93), .CK(RCLK_c), .Q(FS[2])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i2.GSR = "ENABLED"; + FD1S3AX FS_610__i1 (.D(n94), .CK(RCLK_c), .Q(FS[1])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i1.GSR = "ENABLED"; + FD1S3AX WRD_i7 (.D(Din_c_7), .CK(nCCAS_N_3), .Q(WRD[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i7.GSR = "ENABLED"; + ORCALUT4 i3_4_lut_adj_21 (.A(MAin_c_1), .B(n2463), .C(n1326), .D(n15), + .Z(CmdEnable_N_248)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ; + defparam i3_4_lut_adj_21.init = 16'h0800; + FD1S3AX WRD_i6 (.D(Din_c_6), .CK(nCCAS_N_3), .Q(WRD[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i6.GSR = "ENABLED"; + FD1S3AX WRD_i5 (.D(Din_c_5), .CK(nCCAS_N_3), .Q(WRD[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i5.GSR = "ENABLED"; + FD1S3AX WRD_i4 (.D(Din_c_4), .CK(nCCAS_N_3), .Q(WRD[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i4.GSR = "ENABLED"; + FD1S3AX WRD_i3 (.D(Din_c_3), .CK(nCCAS_N_3), .Q(WRD[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i3.GSR = "ENABLED"; + FD1S3AX WRD_i2 (.D(Din_c_2), .CK(nCCAS_N_3), .Q(WRD[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i2.GSR = "ENABLED"; + FD1S3AX WRD_i1 (.D(Din_c_1), .CK(nCCAS_N_3), .Q(WRD[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i1.GSR = "ENABLED"; + FD1S3JX RowA_i9 (.D(MAin_c_9), .CK(nCRAS_N_9), .PD(n2477), .Q(RowA[9])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i9.GSR = "ENABLED"; + FD1S3IX RowA_i8 (.D(MAin_c_8), .CK(nCRAS_N_9), .CD(n2477), .Q(RowA[8])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i8.GSR = "ENABLED"; + FD1S3IX RowA_i7 (.D(MAin_c_7), .CK(nCRAS_N_9), .CD(n2477), .Q(RowA[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i7.GSR = "ENABLED"; + FD1S3IX RowA_i6 (.D(MAin_c_6), .CK(nCRAS_N_9), .CD(n2477), .Q(RowA[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i6.GSR = "ENABLED"; + FD1S3JX RowA_i5 (.D(MAin_c_5), .CK(nCRAS_N_9), .PD(n2477), .Q(RowA[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i5.GSR = "ENABLED"; + FD1S3IX RowA_i4 (.D(MAin_c_4), .CK(nCRAS_N_9), .CD(n2477), .Q(RowA[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i4.GSR = "ENABLED"; + FD1S3IX RowA_i3 (.D(MAin_c_3), .CK(nCRAS_N_9), .CD(n2477), .Q(RowA[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i3.GSR = "ENABLED"; + FD1S3IX RowA_i2 (.D(MAin_c_2), .CK(nCRAS_N_9), .CD(n2477), .Q(RowA[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i2.GSR = "ENABLED"; + FD1S3IX RowA_i1 (.D(MAin_c_1), .CK(nCRAS_N_9), .CD(n2477), .Q(RowA[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i1.GSR = "ENABLED"; + FD1S3AX Bank_i7 (.D(Din_c_7), .CK(PHI2_c), .Q(Bank[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i7.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_rep_25_3_lut (.A(Din_c_6), .B(Din_c_3), .C(Din_c_5), + .Z(n2468)) /* synthesis lut_function=(!((B+(C))+!A)) */ ; + defparam i1_2_lut_rep_25_3_lut.init = 16'h0202; + ORCALUT4 i5_3_lut_rep_15_4_lut (.A(nFWE_c), .B(n1326), .C(n10), .D(MAin_c_0), + .Z(n2458)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ; + defparam i5_3_lut_rep_15_4_lut.init = 16'h1000; + FD1S3AX Bank_i6 (.D(Din_c_6), .CK(PHI2_c), .Q(Bank[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i6.GSR = "ENABLED"; + FD1S3AX Bank_i5 (.D(Din_c_5), .CK(PHI2_c), .Q(Bank[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i5.GSR = "ENABLED"; + FD1S3AX Bank_i4 (.D(Din_c_4), .CK(PHI2_c), .Q(Bank[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i4.GSR = "ENABLED"; + FD1S3AX Bank_i3 (.D(Din_c_3), .CK(PHI2_c), .Q(Bank[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i3.GSR = "ENABLED"; + FD1S3AX Bank_i2 (.D(Din_c_2), .CK(PHI2_c), .Q(Bank[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i2.GSR = "ENABLED"; + FD1S3AX Bank_i1 (.D(Din_c_1), .CK(PHI2_c), .Q(Bank[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i1.GSR = "ENABLED"; + ORCALUT4 FS_6__bdd_4_lut (.A(FS[7]), .B(FS[9]), .C(FS[5]), .D(FS[8]), + .Z(n2451)) /* synthesis lut_function=(!(A (B+(D))+!A (((D)+!C)+!B))) */ ; + defparam FS_6__bdd_4_lut.init = 16'h0062; + BB Dout_pad_6__714 (.I(WRD[6]), .T(n984), .B(RD[6]), .O(Dout_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + BB Dout_pad_5__715 (.I(WRD[5]), .T(n984), .B(RD[5]), .O(Dout_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + ORCALUT4 i1_2_lut_rep_16_3_lut (.A(nFWE_c), .B(n1326), .C(MAin_c_1), + .Z(n2459)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ; + defparam i1_2_lut_rep_16_3_lut.init = 16'h1010; + BB Dout_pad_4__716 (.I(WRD[4]), .T(n984), .B(RD[4]), .O(Dout_2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + BB Dout_pad_3__717 (.I(WRD[3]), .T(n984), .B(RD[3]), .O(Dout_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + BB Dout_pad_2__718 (.I(WRD[2]), .T(n984), .B(RD[2]), .O(Dout_4)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + ORCALUT4 i1_2_lut_rep_33 (.A(Din_c_3), .B(Din_c_5), .Z(n2476)) /* synthesis lut_function=(A (B)) */ ; + defparam i1_2_lut_rep_33.init = 16'h8888; + BB Dout_pad_1__719 (.I(WRD[1]), .T(n984), .B(RD[1]), .O(Dout_5)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + BB Dout_pad_0__720 (.I(WRD[0]), .T(n984), .B(RD[0]), .O(Dout_6)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + OB Dout_pad_7 (.I(Dout_c), .O(Dout[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_6 (.I(Dout_0), .O(Dout[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_5 (.I(Dout_1), .O(Dout[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_4 (.I(Dout_2), .O(Dout[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_3 (.I(Dout_3), .O(Dout[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_2 (.I(Dout_4), .O(Dout[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_1 (.I(Dout_5), .O(Dout[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_0 (.I(Dout_6), .O(Dout[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB LED_pad (.I(LED_N_84), .O(LED)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(22[9:12]) + OB RBA_pad_1 (.I(RBA_c_1), .O(RBA[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22]) + OB RBA_pad_0 (.I(RBA_c_0), .O(RBA[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22]) + OB RA_pad_11 (.I(RA_c), .O(RA[11])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_10 (.I(RA_0), .O(RA[10])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_9 (.I(RA_1_9), .O(RA[9])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_8 (.I(RA_1_8), .O(RA[8])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_7 (.I(RA_1_7), .O(RA[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_6 (.I(RA_1_6), .O(RA[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_5 (.I(RA_1_5), .O(RA[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_4 (.I(RA_1_4), .O(RA[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_3 (.I(RA_1_3), .O(RA[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_2 (.I(RA_1_2), .O(RA[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_1 (.I(RA_1_1), .O(RA[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_0 (.I(RA_1_0), .O(RA[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB nRCS_pad (.I(nRCS_c), .O(nRCS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[13:17]) + OB RCKE_pad (.I(RCKE_c), .O(RCKE)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(45[13:17]) + OB nRWE_pad (.I(nRWE_c), .O(nRWE)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[45:49]) + OB nRRAS_pad (.I(nRRAS_c), .O(nRRAS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[23:28]) + OB nRCAS_pad (.I(nRCAS_c), .O(nRCAS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[34:39]) + OB RDQMH_pad (.I(RDQMH_c), .O(RDQMH)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[16:21]) + OB RDQML_pad (.I(RDQML_c), .O(RDQML)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[9:14]) + OB nUFMCS_pad (.I(nUFMCS_c), .O(nUFMCS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(63[13:19]) + OB UFMCLK_pad (.I(UFMCLK_c), .O(UFMCLK)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(64[13:19]) + OB UFMSDI_pad (.I(UFMSDI_c), .O(UFMSDI)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(65[13:19]) + IB PHI2_pad (.I(PHI2), .O(PHI2_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) + IB MAin_pad_9 (.I(MAin[9]), .O(MAin_c_9)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_8 (.I(MAin[8]), .O(MAin_c_8)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_7 (.I(MAin[7]), .O(MAin_c_7)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_6 (.I(MAin[6]), .O(MAin_c_6)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_5 (.I(MAin[5]), .O(MAin_c_5)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_4 (.I(MAin[4]), .O(MAin_c_4)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_3 (.I(MAin[3]), .O(MAin_c_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_2 (.I(MAin[2]), .O(MAin_c_2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_1 (.I(MAin[1]), .O(MAin_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_0 (.I(MAin[0]), .O(MAin_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB CROW_pad_1 (.I(CROW[1]), .O(CROW_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18]) + IB CROW_pad_0 (.I(CROW[0]), .O(CROW_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18]) + IB Din_pad_7 (.I(Din[7]), .O(Din_c_7)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_6 (.I(Din[6]), .O(Din_c_6)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_5 (.I(Din[5]), .O(Din_c_5)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_4 (.I(Din[4]), .O(Din_c_4)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_3 (.I(Din[3]), .O(Din_c_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_2 (.I(Din[2]), .O(Din_c_2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_1 (.I(Din[1]), .O(Din_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_0 (.I(Din[0]), .O(Din_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB nCCAS_pad (.I(nCCAS), .O(nCCAS_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) + IB nCRAS_pad (.I(nCRAS), .O(nCRAS_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + IB nFWE_pad (.I(nFWE), .O(nFWE_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(36[8:12]) + IB RCLK_pad (.I(RCLK), .O(RCLK_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12]) + IB UFMSDO_pad (.I(UFMSDO), .O(UFMSDO_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(66[8:14]) + ORCALUT4 i1_2_lut_rep_19_4_lut (.A(n2471), .B(n2272), .C(n2470), .D(FS[11]), + .Z(n2462)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i1_2_lut_rep_19_4_lut.init = 16'hfeff; + CCU2 FS_610_add_4_2 (.A0(FS[0]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[1]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(GND_net), + .COUT1(n2008), .S0(n95), .S1(n94)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_2.INIT0 = 16'h0555; + defparam FS_610_add_4_2.INIT1 = 16'hfaaa; + defparam FS_610_add_4_2.INJECT1_0 = "NO"; + defparam FS_610_add_4_2.INJECT1_1 = "NO"; + ORCALUT4 i2057_2_lut (.A(nRowColSel_N_32), .B(RASr2), .Z(n1093)) /* synthesis lut_function=(!(A+!(B))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i2057_2_lut.init = 16'h4444; + ORCALUT4 n2454_bdd_3_lut_4_lut (.A(n2461), .B(n2462), .C(InitReady), + .D(CmdUFMSDI), .Z(UFMSDI_N_231)) /* synthesis lut_function=(A (B (C (D))+!B ((D)+!C))+!A (C (D))) */ ; + defparam n2454_bdd_3_lut_4_lut.init = 16'hf202; + FD1P3IX UFMCLK_416 (.D(UFMCLK_N_224), .SP(RCLK_c_enable_24), .CD(n1846), + .CK(RCLK_c), .Q(UFMCLK_c)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam UFMCLK_416.GSR = "ENABLED"; + FD1P3AX CmdEnable_405 (.D(CmdEnable_N_248), .SP(PHI2_N_120_enable_7), + .CK(PHI2_N_120), .Q(CmdEnable)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdEnable_405.GSR = "ENABLED"; + ORCALUT4 i1513_2_lut (.A(nCCAS_c), .B(nFWE_c), .Z(n984)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1513_2_lut.init = 16'heeee; + ORCALUT4 n1_bdd_4_lut (.A(n1), .B(n1502), .C(nRWE_N_182), .D(nRowColSel_N_35), + .Z(nRWE_N_178)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))+!A (C+!(D))) */ ; + defparam n1_bdd_4_lut.init = 16'hf0dd; + CCU2 FS_610_add_4_12 (.A0(FS[10]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[11]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2012), + .COUT1(n2013), .S0(n85), .S1(n84)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_12.INIT0 = 16'hfaaa; + defparam FS_610_add_4_12.INIT1 = 16'hfaaa; + defparam FS_610_add_4_12.INJECT1_0 = "NO"; + defparam FS_610_add_4_12.INJECT1_1 = "NO"; + ORCALUT4 i1_2_lut_adj_22 (.A(n62), .B(FS[10]), .Z(RCLK_c_enable_25)) /* synthesis lut_function=(A (B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i1_2_lut_adj_22.init = 16'h8888; + ORCALUT4 i1209_4_lut_then_4_lut (.A(nRCS_N_139), .B(Ready), .C(nRowColSel_N_35), + .D(nRowColSel_N_34), .Z(n2480)) /* synthesis lut_function=(!(A (B (C+!(D)))+!A (B (C+!(D))+!B (C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(48[6:16]) + defparam i1209_4_lut_then_4_lut.init = 16'h2f23; + ORCALUT4 nRWE_I_0_455_4_lut (.A(n33), .B(nRWE_N_178), .C(Ready), .D(n2208), + .Z(nRWE_N_171)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B+!(C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6]) + defparam nRWE_I_0_455_4_lut.init = 16'hcfc5; + ORCALUT4 nRWE_I_50_1_lut (.A(nRWE_N_177), .Z(nRWE_N_176)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(255[14] 262[8]) + defparam nRWE_I_50_1_lut.init = 16'h5555; + CCU2 FS_610_add_4_4 (.A0(FS[2]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[3]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2008), + .COUT1(n2009), .S0(n93), .S1(n92)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_4.INIT0 = 16'hfaaa; + defparam FS_610_add_4_4.INIT1 = 16'hfaaa; + defparam FS_610_add_4_4.INJECT1_0 = "NO"; + defparam FS_610_add_4_4.INJECT1_1 = "NO"; + CCU2 FS_610_add_4_10 (.A0(FS[8]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[9]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2011), + .COUT1(n2012), .S0(n87), .S1(n86)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_10.INIT0 = 16'hfaaa; + defparam FS_610_add_4_10.INIT1 = 16'hfaaa; + defparam FS_610_add_4_10.INJECT1_0 = "NO"; + defparam FS_610_add_4_10.INJECT1_1 = "NO"; + ORCALUT4 i1_2_lut_adj_23 (.A(nRowColSel_N_33), .B(CASr2), .Z(n11)) /* synthesis lut_function=(A+!(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(48[6:16]) + defparam i1_2_lut_adj_23.init = 16'hbbbb; + CCU2 FS_610_add_4_18 (.A0(FS[16]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[17]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2015), + .S0(n79), .S1(n78)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_18.INIT0 = 16'hfaaa; + defparam FS_610_add_4_18.INIT1 = 16'hfaaa; + defparam FS_610_add_4_18.INJECT1_0 = "NO"; + defparam FS_610_add_4_18.INJECT1_1 = "NO"; + ORCALUT4 i5_3_lut_rep_21_4_lut (.A(FS[16]), .B(FS[14]), .C(n2272), + .D(n2471), .Z(n2464)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i5_3_lut_rep_21_4_lut.init = 16'hfffe; + ORCALUT4 i1137_1_lut (.A(nRowColSel_N_35), .Z(n1426)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i1137_1_lut.init = 16'h5555; + ORCALUT4 RASr2_I_0_1_lut (.A(RASr2), .Z(RASr2_N_63)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(143[40:46]) + defparam RASr2_I_0_1_lut.init = 16'h5555; + ORCALUT4 n2452_bdd_2_lut_rep_18_3_lut (.A(n2451), .B(FS[6]), .C(FS[10]), + .Z(n2461)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ; + defparam n2452_bdd_2_lut_rep_18_3_lut.init = 16'h0808; + ORCALUT4 i2_3_lut_4_lut_adj_24 (.A(Din_c_5), .B(n2475), .C(MAin_c_0), + .D(ADSubmitted), .Z(n2227)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) + defparam i2_3_lut_4_lut_adj_24.init = 16'h0004; + ORCALUT4 i1_2_lut_adj_25 (.A(nRowColSel_N_32), .B(nRowColSel_N_33), + .Z(n1503)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i1_2_lut_adj_25.init = 16'heeee; + ORCALUT4 i5_4_lut (.A(FS[15]), .B(FS[13]), .C(FS[16]), .D(FS[11]), + .Z(n12)) /* synthesis lut_function=(A (B (C (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i5_4_lut.init = 16'h8000; + ORCALUT4 i1_2_lut_adj_26 (.A(nRCAS_N_165), .B(nRWE_N_177), .Z(n33)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1_2_lut_adj_26.init = 16'heeee; + ORCALUT4 i1259_3_lut (.A(InitReady), .B(RCKEEN_N_122), .C(Ready), + .Z(RCKEEN_N_121)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(84[6:11]) + defparam i1259_3_lut.init = 16'hcaca; + FD1P3AX InitReady_394 (.D(n2568), .SP(RCLK_c_enable_25), .CK(RCLK_c), + .Q(InitReady)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(134[9] 138[5]) + defparam InitReady_394.GSR = "ENABLED"; + ORCALUT4 i11_3_lut (.A(n62), .B(n1417), .C(InitReady), .Z(n2164)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(21[6:11]) + defparam i11_3_lut.init = 16'hcaca; + PFUMX RCKEEN_I_0_445 (.BLUT(RCKEEN_N_123), .ALUT(RCKEEN_N_130), .C0(nRowColSel_N_35), + .Z(RCKEEN_N_122)); + ORCALUT4 i1129_3_lut (.A(nUFMCS_c), .B(CmdUFMCS), .C(n2472), .Z(n1417)) /* synthesis lut_function=(!(A (B (C))+!A (B+!(C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam i1129_3_lut.init = 16'h3a3a; + FD1S3IX S_FSM_i2 (.D(n1093), .CK(RCLK_c), .CD(n1426), .Q(nRowColSel_N_34)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam S_FSM_i2.GSR = "ENABLED"; + INV i2134 (.A(nCCAS_c), .Z(nCCAS_N_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) + ORCALUT4 i1988_2_lut (.A(C1Submitted), .B(Din_c_6), .Z(n2284)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1988_2_lut.init = 16'heeee; + PFUMX i26 (.BLUT(n2227), .ALUT(n2257), .C0(Din_c_2), .Z(n13_adj_2)); + INV i2135 (.A(nCRAS_c), .Z(nCRAS_N_9)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + VLO i1 (.Z(GND_net)); + TSALL TSALL_INST (.TSALL(GND_net)); + ORCALUT4 i2_3_lut_adj_27 (.A(n2208), .B(Ready), .C(nRCAS_N_165), .Z(n2209)) /* synthesis lut_function=(A+(B+(C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i2_3_lut_adj_27.init = 16'hfefe; + PUR PUR_INST (.PUR(VCC_net)); + defparam PUR_INST.RST_PULSE = 1; + ORCALUT4 i2032_2_lut_3_lut_4_lut (.A(FS[17]), .B(FS[12]), .C(FS[14]), + .D(FS[16]), .Z(n2328)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; + defparam i2032_2_lut_3_lut_4_lut.init = 16'hfffe; + ORCALUT4 i1976_2_lut (.A(FS[13]), .B(FS[15]), .Z(n2272)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1976_2_lut.init = 16'heeee; + ORCALUT4 m1_lut (.Z(n2568)) /* synthesis lut_function=1, syn_instantiated=1 */ ; + defparam m1_lut.init = 16'hffff; + PFUMX i2099 (.BLUT(n2479), .ALUT(n2480), .C0(n15_adj_1), .Z(n2481)); + PFUMX i26_adj_28 (.BLUT(n2245), .ALUT(n2243), .C0(Din_c_5), .Z(n15)); + +endmodule +// +// Verilog Description of module TSALL +// module not written out since it is a black-box. +// + +// +// Verilog Description of module PUR +// module not written out since it is a black-box. +// + diff --git a/CPLD/LCMXO256C/impl1/automake.log b/CPLD/LCMXO256C/impl1/automake.log new file mode 100644 index 0000000..0229264 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/automake.log @@ -0,0 +1,1026 @@ + +synthesis -f "RAM2GS_LCMXO256C_impl1_lattice.synproj" +synthesis: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:20 2023 + + +Command Line: synthesis -f RAM2GS_LCMXO256C_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml + + +Synthesis options: +The -a option is MachXO. +The -s option is 3. +The -t option is TQFP100. +The -d option is LCMXO256C. +Using package TQFP100. +Using performance grade 3. + + +########################################################## + +### Lattice Family : MachXO + +### Device : LCMXO256C + +### Package : TQFP100 + +### Speed : 3 + +########################################################## + + + + +Optimization goal = Balanced +Top-level module name = RAM2GS. +Target frequency = 200.000000 MHz. +Maximum fanout = 1000. +Timing path count = 3 +BRAM utilization = 100.000000 % +DSP usage = true +DSP utilization = 100.000000 % +fsm_encoding_style = auto +resolve_mixed_drivers = 0 +fix_gated_clocks = 1 + +Mux style = Auto +Use Carry Chain = true +carry_chain_length = 0 +Loop Limit = 1950. +Use IO Insertion = TRUE +Use IO Reg = AUTO + +Resource Sharing = TRUE +Propagate Constants = TRUE +Remove Duplicate Registers = TRUE +force_gsr = auto +ROM style = auto +RAM style = auto +The -comp option is FALSE. +The -syn option is FALSE. +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C (searchpath added) +-p C:/lscc/diamond/3.12/ispfpga/mj5g00/data (searchpath added) +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1 (searchpath added) +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C (searchpath added) +Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v +NGD file = RAM2GS_LCMXO256C_impl1.ngd +-sdc option: SDC file input not used. +-lpf option: Output file option is ON. +Hardtimer checking is enabled (default). The -dt option is not used. +The -r option is OFF. [ Remove LOC Properties is OFF. ] +Technology check ok... + +Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482 +Compile design. +Compile Design Begin +Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482 +Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482 +Top module name (Verilog): RAM2GS + + + + +Last elaborated design is RAM2GS() +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... +Loading device for application map from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Top-level module name = RAM2GS. + +original encoding -> new encoding (one-hot encoding) + + 0000 -> 0000000000000001 + + 0001 -> 0000000000000010 + + 0010 -> 0000000000000100 + + 0011 -> 0000000000001000 + + 0100 -> 0000000000010000 + + 0101 -> 0000000000100000 + + 0110 -> 0000000001000000 + + 0111 -> 0000000010000000 + + 1000 -> 0000000100000000 + + 1001 -> 0000001000000000 + + 1010 -> 0000010000000000 + + 1011 -> 0000100000000000 + + 1100 -> 0001000000000000 + + 1101 -> 0010000000000000 + + 1110 -> 0100000000000000 + + 1111 -> 1000000000000000 + + +original encoding -> new encoding (one-hot encoding) + + 00 -> 0001 + + 01 -> 0010 + + 10 -> 0100 + + 11 -> 1000 + + + + +GSR will not be inferred because no asynchronous signal was found in the netlist. + +Applying 200.000000 MHz constraint to all clocks + + +Results of NGD DRC are available in RAM2GS_drc.log. +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... + + +Running DRC... + +DRC complete with no errors or warnings + +Design Results: + 318 blocks expanded +completed the first expansion +All blocks are expanded and NGD expansion is successful. +Writing NGD file RAM2GS_LCMXO256C_impl1.ngd. + +################### Begin Area Report (RAM2GS)###################### +Number of register bits => 102 of 490 (20 % ) +BB => 8 +CCU2 => 9 +FD1P3AX => 28 +FD1P3AY => 3 +FD1P3IX => 2 +FD1S3AX => 47 +FD1S3AY => 1 +FD1S3IX => 16 +FD1S3JX => 5 +GSR => 1 +IB => 26 +INV => 3 +OB => 33 +ORCALUT4 => 127 +PFUMX => 6 +################### End Area Report ################## + +################### Begin BlackBox Report ###################### +TSALL => 1 +################### End BlackBox Report ################## + +################### Begin Clock Report ###################### +Clock Nets +Number of Clocks: 4 + Net : RCLK_c, loads : 62 + Net : PHI2_c, loads : 11 + Net : nCCAS_c, loads : 2 + Net : nCRAS_c, loads : 2 +Clock Enable Nets +Number of Clock Enables: 13 +Top 10 highest fanout Clock Enables: + Net : RCLK_c_enable_23, loads : 16 + Net : RCLK_c_enable_4, loads : 3 + Net : PHI2_N_120_enable_6, loads : 3 + Net : RCLK_c_enable_24, loads : 2 + Net : RCLK_c_enable_12, loads : 1 + Net : PHI2_N_120_enable_1, loads : 1 + Net : PHI2_N_120_enable_4, loads : 1 + Net : RCLK_c_enable_3, loads : 1 + Net : PHI2_N_120_enable_5, loads : 1 + Net : RCLK_c_enable_11, loads : 1 +Highest fanout non-clock nets +Top 10 highest fanout non-clock nets: + Net : InitReady, loads : 17 + Net : Ready, loads : 17 + Net : RCLK_c_enable_23, loads : 16 + Net : nCRAS_N_9, loads : 15 + Net : RASr2, loads : 13 + Net : nRowColSel, loads : 13 + Net : n2477, loads : 13 + Net : MAin_c_0, loads : 12 + Net : nRowColSel_N_35, loads : 12 + Net : Din_c_6, loads : 11 +################### End Clock Report ################## + +Timing Report Summary +-------------- +-------------------------------------------------------------------------------- +Constraint | Constraint| Actual|Levels +-------------------------------------------------------------------------------- + | | | +create_clock -period 5.000000 -name | | | +clk3 [get_nets nCCAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk2 [get_nets nCRAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk1 [get_nets PHI2_c] | 200.000 MHz| 45.147 MHz| 6 * + | | | +create_clock -period 5.000000 -name | | | +clk0 [get_nets RCLK_c] | 200.000 MHz| 106.792 MHz| 5 * + | | | +-------------------------------------------------------------------------------- + + +2 constraints not met. + + +Peak Memory Usage: 50.672 MB + +-------------------------------------------------------------- +Elapsed CPU time for LSE flow : 0.516 secs +-------------------------------------------------------------- + +map -a "MachXO" -p LCMXO256C -t TQFP100 -s 3 -oc Commercial "RAM2GS_LCMXO256C_impl1.ngd" -o "RAM2GS_LCMXO256C_impl1_map.ncd" -pr "RAM2GS_LCMXO256C_impl1.prf" -mp "RAM2GS_LCMXO256C_impl1.mrp" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.lpf" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.lpf" -c 0 +map: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + Process the file: RAM2GS_LCMXO256C_impl1.ngd + Picdevice="LCMXO256C" + + Pictype="TQFP100" + + Picspeed=3 + + Remove unused logic + + Do not produce over sized NCDs. + +Part used: LCMXO256CTQFP100, Performance used: 3. + +Loading device for application map from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Running general design DRC... + +Removing unused logic... + +Optimizing... + + + + +Design Summary: + Number of PFU registers: 102 out of 256 (40%) + Number of SLICEs: 71 out of 128 (55%) + SLICEs as Logic/ROM: 71 out of 128 (55%) + SLICEs as RAM: 0 out of 64 (0%) + SLICEs as Carry: 9 out of 128 (7%) + Number of LUT4s: 142 out of 256 (55%) + Number used as logic LUTs: 124 + Number used as distributed RAM: 0 + Number used as ripple logic: 18 + Number used as shift registers: 0 + Number of external PIOs: 67 out of 78 (86%) + Number of GSRs: 0 out of 1 (0%) + JTAG used : No + Readback used : No + Oscillator used : No + Startup used : No + Number of TSALL: 0 out of 1 (0%) + Notes:- + 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) + 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. + Number of clocks: 4 + Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK ) + Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 ) + Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS ) + Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) + Number of Clock Enables: 13 + Net PHI2_N_120_enable_4: 1 loads, 1 LSLICEs + Net RCLK_c_enable_4: 3 loads, 3 LSLICEs + Net RCLK_c_enable_23: 8 loads, 8 LSLICEs + Net RCLK_c_enable_12: 1 loads, 1 LSLICEs + Net RCLK_c_enable_3: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_5: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_6: 2 loads, 2 LSLICEs + Net RCLK_c_enable_24: 2 loads, 2 LSLICEs + Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs + Net Ready_N_292: 1 loads, 1 LSLICEs + Net RCLK_c_enable_11: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs + Net RCLK_c_enable_25: 1 loads, 1 LSLICEs + Number of LSRs: 9 + Net RASr2: 1 loads, 1 LSLICEs + Net Ready: 7 loads, 7 LSLICEs + Net C1Submitted_N_237: 2 loads, 2 LSLICEs + Net n2469: 1 loads, 1 LSLICEs + Net nRowColSel_N_35: 1 loads, 1 LSLICEs + Net n1846: 2 loads, 2 LSLICEs + Net LEDEN_N_82: 1 loads, 1 LSLICEs + Net nRowColSel_N_34: 1 loads, 1 LSLICEs + Net nRWE_N_177: 1 loads, 1 LSLICEs + Number of nets driven by tri-state buffers: 0 + Top 10 highest fanout non-clock nets: + Net Ready: 23 loads + Net InitReady: 17 loads + Net RASr2: 14 loads + Net nRowColSel: 13 loads + Net MAin_c_0: 12 loads + Net nRowColSel_N_35: 12 loads + Net Din_c_3: 11 loads + Net Din_c_6: 11 loads + Net MAin_c_1: 11 loads + Net Din_c_4: 10 loads + + + Number of warnings: 0 + Number of errors: 0 + + + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 29 MB + +Dumping design to file RAM2GS_LCMXO256C_impl1_map.ncd. + +ncd2vdb "RAM2GS_LCMXO256C_impl1_map.ncd" ".vdbs/RAM2GS_LCMXO256C_impl1_map.vdb" + +Loading device for application ncd2vdb from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. + +ncd2eqn "RAM2GS_LCMXO256C_impl1_map.ncd" +ncd2eqn: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Start loading RAM2GS_LCMXO256C_impl1_map.ncd. + +Loading design for application ncd2eqn from file RAM2GS_LCMXO256C_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application ncd2eqn from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +Finish loading RAM2GS_LCMXO256C_impl1_map.ncd. +ncd2eqn runs successfully. + +trce -f "RAM2GS_LCMXO256C_impl1.mt" -o "RAM2GS_LCMXO256C_impl1.tw1" "RAM2GS_LCMXO256C_impl1_map.ncd" "RAM2GS_LCMXO256C_impl1.prf" +trce: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Loading design for application trce from file ram2gs_lcmxo256c_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:21 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf +Design file: ram2gs_lcmxo256c_impl1_map.ncd +Preference file: ram2gs_lcmxo256c_impl1.prf +Device,speed: LCMXO256C,3 +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +Report Type: based on TRACE automatically generated preferences +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Setup): +--------------- + +Timing errors: 310 Score: 1346529 +Cumulative negative slack: 874289 + +Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:21 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf +Design file: ram2gs_lcmxo256c_impl1_map.ncd +Preference file: ram2gs_lcmxo256c_impl1.prf +Device,speed: LCMXO256C,M +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 310 (setup), 0 (hold) +Score: 1346529 (setup), 0 (hold) +Cumulative negative slack: 874289 (874289+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 32 MB + + +ldbanno "RAM2GS_LCMXO256C_impl1_map.ncd" -n Verilog -o "RAM2GS_LCMXO256C_impl1_mapvo.vo" -w -neg +ldbanno: version Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Writing a Verilog netlist using the orca library type based on the RAM2GS_LCMXO256C_impl1_map design file. + + +Loading design for application ldbanno from file RAM2GS_LCMXO256C_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application ldbanno from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +Converting design RAM2GS_LCMXO256C_impl1_map.ncd into .ldb format. +Writing Verilog netlist to file RAM2GS_LCMXO256C_impl1_mapvo.vo +Writing SDF timing to file RAM2GS_LCMXO256C_impl1_mapvo.sdf + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 29 MB + +ldbanno "RAM2GS_LCMXO256C_impl1_map.ncd" -n VHDL -o "RAM2GS_LCMXO256C_impl1_mapvho.vho" -w -neg +ldbanno: version Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Writing a VHDL netlist using the orca library type based on the RAM2GS_LCMXO256C_impl1_map design file. + + +Loading design for application ldbanno from file RAM2GS_LCMXO256C_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application ldbanno from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +Converting design RAM2GS_LCMXO256C_impl1_map.ncd into .ldb format. +Writing VHDL netlist to file RAM2GS_LCMXO256C_impl1_mapvho.vho +Writing SDF timing to file RAM2GS_LCMXO256C_impl1_mapvho.sdf + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 29 MB + +mpartrce -p "RAM2GS_LCMXO256C_impl1.p2t" -f "RAM2GS_LCMXO256C_impl1.p3t" -tf "RAM2GS_LCMXO256C_impl1.pt" "RAM2GS_LCMXO256C_impl1_map.ncd" "RAM2GS_LCMXO256C_impl1.ncd" + +---- MParTrce Tool ---- +Removing old design directory at request of -rem command line option to this program. +Running par. Please wait . . . + +Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd" +Tue Aug 15 05:03:23 2023 + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir/5_1.ncd RAM2GS_LCMXO256C_impl1.prf +Preference file: RAM2GS_LCMXO256C_impl1.prf. +Placement level-cost: 5-1. +Routing Iterations: 6 + +Loading design for application par from file RAM2GS_LCMXO256C_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application par from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +License checked out. + + +Ignore Preference Error(s): True +Device utilization summary: + + PIO (prelim) 67/79 84% used + 67/78 85% bonded + SLICE 71/128 55% used + + + +Number of Signals: 262 +Number of Connections: 662 + +Pin Constraint Summary: + 67 out of 67 pins locked (100% locked). + +The following 2 signals are selected to use the primary clock routing resources: + RCLK_c (driver: RCLK, clk load #: 40) + PHI2_c (driver: PHI2, clk load #: 13) + +The following 1 signal is selected to use the secondary clock routing resources: + nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0) + +No signal is selected as Global Set/Reset. +Starting Placer Phase 0. +........ +Finished Placer Phase 0. REAL time: 0 secs + +Starting Placer Phase 1. +.............. +Placer score = 831129. +Finished Placer Phase 1. REAL time: 5 secs + +Starting Placer Phase 2. +. +Placer score = 828350 +Finished Placer Phase 2. REAL time: 5 secs + + +------------------ Clock Report ------------------ + +Global Clock Resources: + CLK_PIN : 1 out of 4 (25%) + General PIO: 1 out of 80 (1%) + +Global Clocks: + PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT4A)", clk load = 40 + PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB3D)", clk load = 13 + SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB4A)", clk load = 7, ce load = 0, sr load = 0 + + PRIMARY : 2 out of 4 (50%) + SECONDARY: 1 out of 4 (25%) + +--------------- End of Clock Report --------------- + + +I/O Usage Summary (final): + 67 out of 79 (84.8%) PIO sites used. + 67 out of 78 (85.9%) bonded PIO sites used. + Number of PIO comps: 67; differential: 0. + Number of Vref pins used: 0. + +I/O Bank Usage Summary: ++----------+----------------+------------+------------+------------+ +| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | ++----------+----------------+------------+------------+------------+ +| 0 | 36 / 41 ( 87%) | 3.3V | - | - | +| 1 | 31 / 37 ( 83%) | 3.3V | - | - | ++----------+----------------+------------+------------+------------+ + +Total placer CPU time: 4 secs + +Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd. + +0 connections routed; 662 unrouted. +Starting router resource preassignment + + + + + +Completed router resource preassignment. Real time: 5 secs + +Start NBR router at 05:03:28 08/15/23 + +***************************************************************** +Info: NBR allows conflicts(one node used by more than one signal) + in the earlier iterations. In each iteration, it tries to + solve the conflicts while keeping the critical connections + routed as short as possible. The routing process is said to + be completed when no conflicts exist and all connections + are routed. +Note: NBR uses a different method to calculate timing slacks. The + worst slack and total negative slack may not be the same as + that in TRCE report. You should always run TRCE to verify + your design. +***************************************************************** + +Start NBR special constraint process at 05:03:28 08/15/23 + +Start NBR section for initial routing at 05:03:28 08/15/23 +Level 1, iteration 1 +0(0.00%) conflict; 563(85.05%) untouched conns; 712361 (nbr) score; +Estimated worst slack/total negative slack: -9.968ns/-712.361ns; real time: 5 secs +Level 2, iteration 1 +3(0.02%) conflicts; 494(74.62%) untouched conns; 697746 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-697.746ns; real time: 5 secs +Level 3, iteration 1 +6(0.05%) conflicts; 255(38.52%) untouched conns; 756550 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-756.550ns; real time: 5 secs +Level 4, iteration 1 +17(0.14%) conflicts; 0(0.00%) untouched conn; 761255 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-761.256ns; real time: 5 secs + +Info: Initial congestion level at 75% usage is 0 +Info: Initial congestion area at 75% usage is 0 (0.00%) + +Start NBR section for normal routing at 05:03:28 08/15/23 +Level 4, iteration 1 +12(0.10%) conflicts; 0(0.00%) untouched conn; 765605 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-765.606ns; real time: 5 secs +Level 4, iteration 2 +6(0.05%) conflicts; 0(0.00%) untouched conn; 766423 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-766.424ns; real time: 5 secs +Level 4, iteration 3 +3(0.02%) conflicts; 0(0.00%) untouched conn; 769148 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-769.149ns; real time: 5 secs +Level 4, iteration 4 +3(0.02%) conflicts; 0(0.00%) untouched conn; 769148 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-769.149ns; real time: 5 secs +Level 4, iteration 5 +3(0.02%) conflicts; 0(0.00%) untouched conn; 766523 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-766.524ns; real time: 5 secs +Level 4, iteration 6 +1(0.01%) conflict; 0(0.00%) untouched conn; 766523 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-766.524ns; real time: 5 secs +Level 4, iteration 7 +1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs +Level 4, iteration 8 +1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs +Level 4, iteration 9 +1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs +Level 4, iteration 10 +0(0.00%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs + +Start NBR section for performance tuning (iteration 1) at 05:03:29 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs + +Start NBR section for re-routing at 05:03:29 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 768048 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-768.049ns; real time: 6 secs + +Start NBR section for post-routing at 05:03:29 08/15/23 + +End NBR router with 0 unrouted connection + +NBR Summary +----------- + Number of unrouted connections : 0 (0.00%) + Number of connections with timing violations : 256 (38.67%) + Estimated worst slack : -10.044ns + Timing score : 913247 +----------- +Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. + + + + + +Total CPU time 5 secs +Total REAL time: 6 secs +Completely routed. +End of route. 662 routed (100.00%); 0 unrouted. + +Hold time timing score: 0, hold timing errors: 0 + +Timing score: 913247 + +Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd. + + +PAR_SUMMARY::Run status = Completed +PAR_SUMMARY::Number of unrouted conns = 0 +PAR_SUMMARY::Worst slack> = -10.044 +PAR_SUMMARY::Timing score> = 913.247 +PAR_SUMMARY::Worst slack> = 0.273 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Number of errors = 0 + +Total CPU time to completion: 5 secs +Total REAL time to completion: 6 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Exiting par with exit code 0 +Exiting mpartrce with exit code 0 + +trce -f "RAM2GS_LCMXO256C_impl1.pt" -o "RAM2GS_LCMXO256C_impl1.twr" "RAM2GS_LCMXO256C_impl1.ncd" "RAM2GS_LCMXO256C_impl1.prf" +trce: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Loading design for application trce from file ram2gs_lcmxo256c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:29 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf +Design file: ram2gs_lcmxo256c_impl1.ncd +Preference file: ram2gs_lcmxo256c_impl1.prf +Device,speed: LCMXO256C,3 +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +Report Type: based on TRACE automatically generated preferences +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Setup): +--------------- + +Timing errors: 326 Score: 913247 +Cumulative negative slack: 638389 + +Constraints cover 489 paths, 2 nets, and 414 connections (62.54% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:29 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf +Design file: ram2gs_lcmxo256c_impl1.ncd +Preference file: ram2gs_lcmxo256c_impl1.prf +Device,speed: LCMXO256C,m +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 489 paths, 2 nets, and 414 connections (62.54% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 326 (setup), 0 (hold) +Score: 913247 (setup), 0 (hold) +Cumulative negative slack: 638389 (638389+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 31 MB + + +iotiming "RAM2GS_LCMXO256C_impl1.ncd" "RAM2GS_LCMXO256C_impl1.prf" +I/O Timing Report: +: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application iotiming from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +Running Performance Grade: 3 +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... + +Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 4 +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +Running Performance Grade: 4 +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... + +Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 5 +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +Running Performance Grade: 5 +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... + +Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: M +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +Running Performance Grade: M +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... +Done. + +tmcheck -par "RAM2GS_LCMXO256C_impl1.par" + +bitgen -w "RAM2GS_LCMXO256C_impl1.ncd" -f "RAM2GS_LCMXO256C_impl1.t2b" "RAM2GS_LCMXO256C_impl1.prf" + + +BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + + +Loading design for application Bitgen from file RAM2GS_LCMXO256C_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application Bitgen from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. + +Running DRC. +DRC detected 0 errors and 0 warnings. +Reading Preference File from RAM2GS_LCMXO256C_impl1.prf. + +Preference Summary: ++---------------------------------+---------------------------------+ +| Preference | Current Setting | ++---------------------------------+---------------------------------+ +| CONFIG_SECURE | OFF** | ++---------------------------------+---------------------------------+ +| INBUF | ON** | ++---------------------------------+---------------------------------+ +| ES | No** | ++---------------------------------+---------------------------------+ + * Default setting. + ** The specified setting matches the default setting. + + +Creating bit map... +Saving bit stream in "RAM2GS_LCMXO256C_impl1.bit". +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 44 MB + +ddtcmd -dev LCMXO256C-XXT100 -if "RAM2GS_LCMXO256C_impl1.bit" -oft -jed -of "RAM2GS_LCMXO256C_impl1.jed" -comment "RAM2GS_LCMXO256C_impl1.alt" +Lattice Diamond Deployment Tool 3.12 Command Line + +Loading Programmer Device Database... + +Generating JED..... +Device Name: LCMXO256C-XXT100 +Reading Input File: RAM2GS_LCMXO256C_impl1.bit +Output File: RAM2GS_LCMXO256C_impl1.jed +Comment file RAM2GS_LCMXO256C_impl1.alt. +Generating JEDEC..... +File RAM2GS_LCMXO256C_impl1.jed generated successfully. +Lattice Diamond Deployment Tool has exited successfully. + diff --git a/CPLD/LCMXO256C/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO256C/impl1/hdla_gen_hierarchy.html new file mode 100644 index 0000000..df264d3 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/hdla_gen_hierarchy.html @@ -0,0 +1,9 @@ + 
    Setting log file to 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1/hdla_gen_hierarchy.html'.
+Starting: parse design source files
+(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v'
+(VERI-1482) Analyzing Verilog file 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v'
+INFO - D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
+INFO - D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v(1,1-411,10) (VERI-9000) elaborating module 'RAM2GS'
+Done: design load finished with (0) errors, and (0) warnings
+
+
    \ No newline at end of file diff --git a/CPLD/LCMXO256C/impl1/impl1.xcf b/CPLD/LCMXO256C/impl1/impl1.xcf new file mode 100644 index 0000000..19089d7 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/impl1.xcf @@ -0,0 +1,50 @@ + + + + + + JTAG + + + 1 + Lattice + MachXO + LCMXO256C + 0x01281043 + All + LCMXO256C + + 8 + 11111111 + 1 + 0 + + D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.jed + 08/15/23 04:29:43 + 0xF26B + FLASH Erase,Program,Verify + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB + EzUSB-0 + \\?\usb#vid_1134&amp;pid_8001#5&amp;887acb0&amp;0&amp;13# + + diff --git a/CPLD/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1.ior b/CPLD/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1.ior new file mode 100644 index 0000000..83e2eca --- /dev/null +++ b/CPLD/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1.ior @@ -0,0 +1,138 @@ +Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 4 +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 5 +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: M +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +// Design: RAM2GS +// Package: TQFP100 +// ncd File: ram2gs_lcmxo256c_impl1.ncd +// Version: Diamond (64-bit) 3.12.1.454 +// Written on Tue Aug 15 05:03:30 2023 +// M: Minimum Performance Grade +// iotiming RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml + +I/O Timing Report (All units are in ns) + +Worst Case Results across Performance Grades (M, 5, 4, 3): + +// Input Setup and Hold Times + +Port Clock Edge Setup Performance_Grade Hold Performance_Grade +---------------------------------------------------------------------- +CROW[0] nCRAS F -0.006 M 1.907 3 +CROW[1] nCRAS F -0.006 M 1.907 3 +Din[0] PHI2 F 5.992 3 2.081 3 +Din[0] nCCAS F 1.591 3 -0.045 M +Din[1] PHI2 F 5.388 3 2.863 3 +Din[1] nCCAS F 0.231 3 0.973 3 +Din[2] PHI2 F 4.913 3 2.842 3 +Din[2] nCCAS F 0.265 3 1.112 3 +Din[3] PHI2 F 6.776 3 2.065 3 +Din[3] nCCAS F 0.702 3 0.725 3 +Din[4] PHI2 F 4.191 3 1.807 3 +Din[4] nCCAS F 1.107 3 0.235 3 +Din[5] PHI2 F 7.709 3 0.737 3 +Din[5] nCCAS F 1.192 3 0.184 3 +Din[6] PHI2 F 6.617 3 1.159 3 +Din[6] nCCAS F 0.904 3 0.149 3 +Din[7] PHI2 F 6.864 3 1.300 3 +Din[7] nCCAS F 0.531 3 0.451 3 +MAin[0] PHI2 F 4.802 3 1.029 3 +MAin[0] nCRAS F 1.511 3 0.599 3 +MAin[1] PHI2 F 4.513 3 1.653 3 +MAin[1] nCRAS F 0.340 3 1.609 3 +MAin[2] PHI2 F 4.241 3 1.193 3 +MAin[2] nCRAS F 1.248 3 0.814 3 +MAin[3] PHI2 F 6.748 3 -0.221 M +MAin[3] nCRAS F 0.375 3 1.589 3 +MAin[4] PHI2 F 7.111 3 -0.295 M +MAin[4] nCRAS F -0.038 M 2.031 3 +MAin[5] PHI2 F 4.083 3 1.319 3 +MAin[5] nCRAS F -0.126 M 2.320 3 +MAin[6] PHI2 F 8.738 3 -0.639 M +MAin[6] nCRAS F 0.505 3 1.464 3 +MAin[7] PHI2 F 7.566 3 -0.400 M +MAin[7] nCRAS F 0.390 3 1.577 3 +MAin[8] nCRAS F -0.017 M 1.932 3 +MAin[9] nCRAS F 1.390 3 0.679 3 +PHI2 RCLK R 4.721 3 -0.539 M +UFMSDO RCLK R 2.307 3 -0.173 M +nCCAS RCLK R 3.513 3 -0.441 M +nCCAS nCRAS F 1.800 3 0.388 3 +nCRAS RCLK R 1.107 3 0.266 3 +nFWE PHI2 F 4.160 3 1.763 3 +nFWE nCRAS F 0.864 3 1.164 3 + + +// Clock to Output Delay + +Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade +------------------------------------------------------------------------ +LED RCLK R 7.020 3 1.411 M +LED nCRAS F 10.053 3 2.020 M +RA[0] RCLK R 8.511 3 1.707 M +RA[0] nCRAS F 10.448 3 2.067 M +RA[10] RCLK R 7.422 3 1.486 M +RA[11] PHI2 R 8.233 3 1.633 M +RA[1] RCLK R 8.292 3 1.649 M +RA[1] nCRAS F 10.175 3 2.009 M +RA[2] RCLK R 8.708 3 1.746 M +RA[2] nCRAS F 10.512 3 2.079 M +RA[3] RCLK R 6.982 3 1.404 M +RA[3] nCRAS F 8.753 3 1.739 M +RA[4] RCLK R 6.982 3 1.404 M +RA[4] nCRAS F 9.764 3 1.953 M +RA[5] RCLK R 6.982 3 1.404 M +RA[5] nCRAS F 10.635 3 2.140 M +RA[6] RCLK R 9.127 3 1.839 M +RA[6] nCRAS F 10.861 3 2.160 M +RA[7] RCLK R 8.287 3 1.659 M +RA[7] nCRAS F 10.995 3 2.202 M +RA[8] RCLK R 8.834 3 1.776 M +RA[8] nCRAS F 10.930 3 2.181 M +RA[9] RCLK R 6.729 3 1.353 M +RA[9] nCRAS F 10.423 3 2.088 M +RBA[0] nCRAS F 7.746 3 1.538 M +RBA[1] nCRAS F 9.473 3 1.887 M +RCKE RCLK R 8.348 3 1.695 M +RDQMH RCLK R 7.433 3 1.503 M +RDQML RCLK R 9.061 3 1.821 M +RD[0] nCCAS F 6.791 3 1.468 M +RD[1] nCCAS F 7.502 3 1.596 M +RD[2] nCCAS F 9.015 3 1.924 M +RD[3] nCCAS F 8.919 3 1.901 M +RD[4] nCCAS F 7.500 3 1.596 M +RD[5] nCCAS F 6.791 3 1.468 M +RD[6] nCCAS F 7.950 3 1.703 M +RD[7] nCCAS F 7.871 3 1.681 M +UFMCLK RCLK R 7.767 3 1.567 M +UFMSDI RCLK R 5.675 3 1.141 M +nRCAS RCLK R 6.518 3 1.300 M +nRCS RCLK R 5.675 3 1.141 M +nRRAS RCLK R 7.469 3 1.503 M +nRWE RCLK R 5.675 3 1.141 M +nUFMCS RCLK R 7.873 3 1.593 M +WARNING: you must also run trce with hold speed: 3 +WARNING: you must also run trce with setup speed: M diff --git a/CPLD/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1_trce.asd b/CPLD/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1_trce.asd new file mode 100644 index 0000000..e83757e --- /dev/null +++ b/CPLD/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1_trce.asd @@ -0,0 +1,13 @@ +[ActiveSupport TRCE] +; Setup Analysis +Fmax_0 = 129.769 MHz (283.768 MHz); +Fmax_1 = 54.431 MHz (120.077 MHz); +Failed = 2 (Total 2); +Clock_ports = 4; +Clock_nets = 4; +; Hold Analysis +Fmax_0 = 0.273 ns (0.000 ns); +Fmax_1 = 0.361 ns (0.000 ns); +Failed = 0 (Total 2); +Clock_ports = 4; +Clock_nets = 4; diff --git a/CPLD/LCMXO256C/impl1/synthesis.log b/CPLD/LCMXO256C/impl1/synthesis.log new file mode 100644 index 0000000..0788bf8 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/synthesis.log @@ -0,0 +1,238 @@ +synthesis: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:20 2023 + + +Command Line: synthesis -f RAM2GS_LCMXO256C_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml + +Synthesis options: +The -a option is MachXO. +The -s option is 3. +The -t option is TQFP100. +The -d option is LCMXO256C. +Using package TQFP100. +Using performance grade 3. + + +########################################################## + +### Lattice Family : MachXO + +### Device : LCMXO256C + +### Package : TQFP100 + +### Speed : 3 + +########################################################## + + + +INFO - synthesis: User-Selected Strategy Settings +Optimization goal = Balanced +Top-level module name = RAM2GS. +Target frequency = 200.000000 MHz. +Maximum fanout = 1000. +Timing path count = 3 +BRAM utilization = 100.000000 % +DSP usage = true +DSP utilization = 100.000000 % +fsm_encoding_style = auto +resolve_mixed_drivers = 0 +fix_gated_clocks = 1 + +Mux style = Auto +Use Carry Chain = true +carry_chain_length = 0 +Loop Limit = 1950. +Use IO Insertion = TRUE +Use IO Reg = AUTO + +Resource Sharing = TRUE +Propagate Constants = TRUE +Remove Duplicate Registers = TRUE +force_gsr = auto +ROM style = auto +RAM style = auto +The -comp option is FALSE. +The -syn option is FALSE. +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C (searchpath added) +-p C:/lscc/diamond/3.12/ispfpga/mj5g00/data (searchpath added) +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1 (searchpath added) +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C (searchpath added) +Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v +NGD file = RAM2GS_LCMXO256C_impl1.ngd +-sdc option: SDC file input not used. +-lpf option: Output file option is ON. +Hardtimer checking is enabled (default). The -dt option is not used. +The -r option is OFF. [ Remove LOC Properties is OFF. ] +Technology check ok... + +Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482 +Compile design. +Compile Design Begin +Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482 +Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482 +Top module name (Verilog): RAM2GS +INFO - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1): compiling module RAM2GS. VERI-1018 +WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131): expression size 32 truncated to fit in target size 2. VERI-1209 +WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136): expression size 32 truncated to fit in target size 18. VERI-1209 +WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263): expression size 32 truncated to fit in target size 4. VERI-1209 +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... +Loading device for application map from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Top-level module name = RAM2GS. +INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding +original encoding -> new encoding (one-hot encoding) + + 0000 -> 0000000000000001 + + 0001 -> 0000000000000010 + + 0010 -> 0000000000000100 + + 0011 -> 0000000000001000 + + 0100 -> 0000000000010000 + + 0101 -> 0000000000100000 + + 0110 -> 0000000001000000 + + 0111 -> 0000000010000000 + + 1000 -> 0000000100000000 + + 1001 -> 0000001000000000 + + 1010 -> 0000010000000000 + + 1011 -> 0000100000000000 + + 1100 -> 0001000000000000 + + 1101 -> 0010000000000000 + + 1110 -> 0100000000000000 + + 1111 -> 1000000000000000 + +INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding +original encoding -> new encoding (one-hot encoding) + + 00 -> 0001 + + 01 -> 0010 + + 10 -> 0100 + + 11 -> 1000 + + + + +GSR will not be inferred because no asynchronous signal was found in the netlist. +WARNING - synthesis: Initial value found on instance C1Submitted_406 will be ignored. +Applying 200.000000 MHz constraint to all clocks + +WARNING - synthesis: No user .sdc file. +Results of NGD DRC are available in RAM2GS_drc.log. +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... +All blocks are expanded and NGD expansion is successful. +Writing NGD file RAM2GS_LCMXO256C_impl1.ngd. + +################### Begin Area Report (RAM2GS)###################### +Number of register bits => 102 of 490 (20 % ) +BB => 8 +CCU2 => 9 +FD1P3AX => 28 +FD1P3AY => 3 +FD1P3IX => 2 +FD1S3AX => 47 +FD1S3AY => 1 +FD1S3IX => 16 +FD1S3JX => 5 +GSR => 1 +IB => 26 +INV => 3 +OB => 33 +ORCALUT4 => 127 +PFUMX => 6 +################### End Area Report ################## + +################### Begin BlackBox Report ###################### +TSALL => 1 +################### End BlackBox Report ################## + +################### Begin Clock Report ###################### +Clock Nets +Number of Clocks: 4 + Net : RCLK_c, loads : 62 + Net : PHI2_c, loads : 11 + Net : nCCAS_c, loads : 2 + Net : nCRAS_c, loads : 2 +Clock Enable Nets +Number of Clock Enables: 13 +Top 10 highest fanout Clock Enables: + Net : RCLK_c_enable_23, loads : 16 + Net : RCLK_c_enable_4, loads : 3 + Net : PHI2_N_120_enable_6, loads : 3 + Net : RCLK_c_enable_24, loads : 2 + Net : RCLK_c_enable_12, loads : 1 + Net : PHI2_N_120_enable_1, loads : 1 + Net : PHI2_N_120_enable_4, loads : 1 + Net : RCLK_c_enable_3, loads : 1 + Net : PHI2_N_120_enable_5, loads : 1 + Net : RCLK_c_enable_11, loads : 1 +Highest fanout non-clock nets +Top 10 highest fanout non-clock nets: + Net : InitReady, loads : 17 + Net : Ready, loads : 17 + Net : RCLK_c_enable_23, loads : 16 + Net : nCRAS_N_9, loads : 15 + Net : RASr2, loads : 13 + Net : nRowColSel, loads : 13 + Net : n2477, loads : 13 + Net : MAin_c_0, loads : 12 + Net : nRowColSel_N_35, loads : 12 + Net : Din_c_6, loads : 11 +################### End Clock Report ################## + +Timing Report Summary +-------------- +-------------------------------------------------------------------------------- +Constraint | Constraint| Actual|Levels +-------------------------------------------------------------------------------- + | | | +create_clock -period 5.000000 -name | | | +clk3 [get_nets nCCAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk2 [get_nets nCRAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk1 [get_nets PHI2_c] | 200.000 MHz| 45.147 MHz| 6 * + | | | +create_clock -period 5.000000 -name | | | +clk0 [get_nets RCLK_c] | 200.000 MHz| 106.792 MHz| 5 * + | | | +-------------------------------------------------------------------------------- + + +2 constraints not met. + + +Peak Memory Usage: 50.672 MB + +-------------------------------------------------------------- +Elapsed CPU time for LSE flow : 0.516 secs +-------------------------------------------------------------- diff --git a/CPLD/LCMXO256C/impl1/synthesis_lse.html b/CPLD/LCMXO256C/impl1/synthesis_lse.html new file mode 100644 index 0000000..110b727 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/synthesis_lse.html @@ -0,0 +1,303 @@ + +Synthesis and Ngdbuild Report + + +
    Synthesis and Ngdbuild  Report
+synthesis:  version Diamond (64-bit) 3.12.1.454
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 15 05:03:20 2023
+
+
+Command Line:  synthesis -f RAM2GS_LCMXO256C_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml 
+
+Synthesis options:
+The -a option is MachXO.
+The -s option is 3.
+The -t option is TQFP100.
+The -d option is LCMXO256C.
+Using package TQFP100.
+Using performance grade 3.
+                                                          
+
+##########################################################
+
+### Lattice Family : MachXO
+
+### Device  : LCMXO256C
+
+### Package : TQFP100
+
+### Speed   : 3
+
+##########################################################
+
+                                                          
+
+INFO - synthesis: User-Selected Strategy Settings
+Optimization goal = Balanced
+Top-level module name = RAM2GS.
+Target frequency = 200.000000 MHz.
+Maximum fanout = 1000.
+Timing path count = 3
+BRAM utilization = 100.000000 %
+DSP usage = true
+DSP utilization = 100.000000 %
+fsm_encoding_style = auto
+resolve_mixed_drivers = 0
+fix_gated_clocks = 1
+
+Mux style = Auto
+Use Carry Chain = true
+carry_chain_length = 0
+Loop Limit = 1950.
+Use IO Insertion = TRUE
+Use IO Reg = AUTO
+
+Resource Sharing = TRUE
+Propagate Constants = TRUE
+Remove Duplicate Registers = TRUE
+force_gsr = auto
+ROM style = auto
+RAM style = auto
+The -comp option is FALSE.
+The -syn option is FALSE.
+-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C (searchpath added)
+-p C:/lscc/diamond/3.12/ispfpga/mj5g00/data (searchpath added)
+-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1 (searchpath added)
+-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C (searchpath added)
+Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v
+NGD file = RAM2GS_LCMXO256C_impl1.ngd
+-sdc option: SDC file input not used.
+-lpf option: Output file option is ON.
+Hardtimer checking is enabled (default). The -dt option is not used.
+The -r option is OFF. [ Remove LOC Properties is OFF. ]
+Technology check ok...
+
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
+Compile design.
+Compile Design Begin
+Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
+Top module name (Verilog): RAM2GS
+INFO - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1): compiling module RAM2GS. VERI-1018
+WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131): expression size 32 truncated to fit in target size 2. VERI-1209
+WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136): expression size 32 truncated to fit in target size 18. VERI-1209
+WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263): expression size 32 truncated to fit in target size 4. VERI-1209
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+Loading device for application map from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.19.
+Top-level module name = RAM2GS.
+INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 0000 -> 0000000000000001
+
+ 0001 -> 0000000000000010
+
+ 0010 -> 0000000000000100
+
+ 0011 -> 0000000000001000
+
+ 0100 -> 0000000000010000
+
+ 0101 -> 0000000000100000
+
+ 0110 -> 0000000001000000
+
+ 0111 -> 0000000010000000
+
+ 1000 -> 0000000100000000
+
+ 1001 -> 0000001000000000
+
+ 1010 -> 0000010000000000
+
+ 1011 -> 0000100000000000
+
+ 1100 -> 0001000000000000
+
+ 1101 -> 0010000000000000
+
+ 1110 -> 0100000000000000
+
+ 1111 -> 1000000000000000
+
+INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 00 -> 0001
+
+ 01 -> 0010
+
+ 10 -> 0100
+
+ 11 -> 1000
+
+
+
+
+GSR will not be inferred because no asynchronous signal was found in the netlist.
+WARNING - synthesis: Initial value found on instance C1Submitted_406 will be ignored.
+Applying 200.000000 MHz constraint to all clocks
+
+WARNING - synthesis: No user .sdc file.
+Results of NGD DRC are available in RAM2GS_drc.log.
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+All blocks are expanded and NGD expansion is successful.
+Writing NGD file RAM2GS_LCMXO256C_impl1.ngd.
+
+################### Begin Area Report (RAM2GS)######################
+Number of register bits => 102 of 490 (20 % )
+BB => 8
+CCU2 => 9
+FD1P3AX => 28
+FD1P3AY => 3
+FD1P3IX => 2
+FD1S3AX => 47
+FD1S3AY => 1
+FD1S3IX => 16
+FD1S3JX => 5
+GSR => 1
+IB => 26
+INV => 3
+OB => 33
+ORCALUT4 => 127
+PFUMX => 6
+################### End Area Report ##################
+
+################### Begin BlackBox Report ######################
+TSALL => 1
+################### End BlackBox Report ##################
+
+################### Begin Clock Report ######################
+Clock Nets
+Number of Clocks: 4
+  Net : RCLK_c, loads : 62
+  Net : PHI2_c, loads : 11
+  Net : nCCAS_c, loads : 2
+  Net : nCRAS_c, loads : 2
+Clock Enable Nets
+Number of Clock Enables: 13
+Top 10 highest fanout Clock Enables:
+  Net : RCLK_c_enable_23, loads : 16
+  Net : RCLK_c_enable_4, loads : 3
+  Net : PHI2_N_120_enable_6, loads : 3
+  Net : RCLK_c_enable_24, loads : 2
+  Net : RCLK_c_enable_12, loads : 1
+  Net : PHI2_N_120_enable_1, loads : 1
+  Net : PHI2_N_120_enable_4, loads : 1
+  Net : RCLK_c_enable_3, loads : 1
+  Net : PHI2_N_120_enable_5, loads : 1
+  Net : RCLK_c_enable_11, loads : 1
+Highest fanout non-clock nets
+Top 10 highest fanout non-clock nets:
+  Net : InitReady, loads : 17
+  Net : Ready, loads : 17
+  Net : RCLK_c_enable_23, loads : 16
+  Net : nCRAS_N_9, loads : 15
+  Net : RASr2, loads : 13
+  Net : nRowColSel, loads : 13
+  Net : n2477, loads : 13
+  Net : MAin_c_0, loads : 12
+  Net : nRowColSel_N_35, loads : 12
+  Net : Din_c_6, loads : 11
+################### End Clock Report ##################
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets PHI2_c]                  |  200.000 MHz|   45.147 MHz|     6 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |  200.000 MHz|  106.792 MHz|     5 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+
+Peak Memory Usage: 50.672  MB
+
+--------------------------------------------------------------
+Elapsed CPU time for LSE flow : 0.516  secs
+--------------------------------------------------------------
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO256C/impl1/xxx_lse_cp_file_list b/CPLD/LCMXO256C/impl1/xxx_lse_cp_file_list new file mode 100644 index 0000000..1c1a02c --- /dev/null +++ b/CPLD/LCMXO256C/impl1/xxx_lse_cp_file_list @@ -0,0 +1,250 @@ +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v diff --git a/CPLD/LCMXO256C/impl1/xxx_lse_sign_file b/CPLD/LCMXO256C/impl1/xxx_lse_sign_file new file mode 100644 index 0000000..15202f1 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/xxx_lse_sign_file @@ -0,0 +1,250 @@ +LSE_CPS_ID_1 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:8[8:12]" +LSE_CPS_ID_2 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_3 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_4 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:80[15:31]" +LSE_CPS_ID_5 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_6 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_7 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_8 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_9 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_10 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_11 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_12 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_13 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_14 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_15 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_16 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_17 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_18 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_19 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:141[9] 144[5]" +LSE_CPS_ID_20 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_21 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_22 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:394[12] 409[6]" +LSE_CPS_ID_23 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_24 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_25 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_26 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_27 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_28 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_29 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_30 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_31 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_32 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_33 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_34 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_35 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:315[17:31]" +LSE_CPS_ID_36 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_37 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_38 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_39 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_40 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_41 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_42 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:80[15:31]" +LSE_CPS_ID_43 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_44 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:315[17:31]" +LSE_CPS_ID_45 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_46 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_47 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_48 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:321[13] 335[7]" +LSE_CPS_ID_49 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_50 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_51 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_52 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:23[15:41]" +LSE_CPS_ID_53 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_54 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_55 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_56 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_57 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_58 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:48[6:16]" +LSE_CPS_ID_59 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:80[15:31]" +LSE_CPS_ID_60 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_61 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:402[16:47]" +LSE_CPS_ID_62 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_63 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:402[16:47]" +LSE_CPS_ID_64 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_65 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_66 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_67 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:23[27:31]" +LSE_CPS_ID_68 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_69 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_70 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_71 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_72 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_73 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_74 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_75 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" +LSE_CPS_ID_76 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_77 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" +LSE_CPS_ID_78 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_79 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:230[16:37]" +LSE_CPS_ID_80 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_81 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_82 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_83 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:143[11:55]" +LSE_CPS_ID_84 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:48[6:16]" +LSE_CPS_ID_85 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_86 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_87 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:99[22:51]" +LSE_CPS_ID_88 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_89 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_90 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:58[17:46]" +LSE_CPS_ID_91 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_92 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_93 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_94 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_95 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_96 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_97 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_98 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_99 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_100 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_101 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_102 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_103 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_104 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:386[12] 409[6]" +LSE_CPS_ID_105 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_106 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:386[12] 409[6]" +LSE_CPS_ID_107 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_108 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_109 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_110 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_111 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_112 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_113 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_114 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_115 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_116 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_117 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_118 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_119 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_120 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_121 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_122 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_123 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_124 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_125 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_126 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_127 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_128 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_129 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_130 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_131 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_132 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_133 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_134 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_135 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_136 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_137 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_138 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_139 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_140 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_141 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_142 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_143 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_144 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_145 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_146 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_147 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_148 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_149 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_150 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_151 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_152 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_153 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_154 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_155 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_156 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_157 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_158 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_159 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_160 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_161 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_162 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_163 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_164 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_165 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_166 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_167 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_168 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_169 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_170 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_171 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_172 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:22[9:12]" +LSE_CPS_ID_173 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:47[19:22]" +LSE_CPS_ID_174 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:47[19:22]" +LSE_CPS_ID_175 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_176 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_177 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_178 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_179 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_180 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_181 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_182 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_183 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_184 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_185 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_186 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_187 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[13:17]" +LSE_CPS_ID_188 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:45[13:17]" +LSE_CPS_ID_189 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[45:49]" +LSE_CPS_ID_190 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[23:28]" +LSE_CPS_ID_191 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[34:39]" +LSE_CPS_ID_192 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:56[16:21]" +LSE_CPS_ID_193 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:56[9:14]" +LSE_CPS_ID_194 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:63[13:19]" +LSE_CPS_ID_195 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:64[13:19]" +LSE_CPS_ID_196 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:65[13:19]" +LSE_CPS_ID_197 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:8[8:12]" +LSE_CPS_ID_198 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_199 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_200 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_201 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_202 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_203 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_204 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_205 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_206 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_207 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_208 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:34[14:18]" +LSE_CPS_ID_209 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:34[14:18]" +LSE_CPS_ID_210 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_211 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_212 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_213 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_214 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_215 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_216 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_217 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_218 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[8:13]" +LSE_CPS_ID_219 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[15:20]" +LSE_CPS_ID_220 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:36[8:12]" +LSE_CPS_ID_221 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:41[8:12]" +LSE_CPS_ID_222 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:66[8:14]" +LSE_CPS_ID_223 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_224 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_225 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_226 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_227 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_228 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_229 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_230 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:48[6:16]" +LSE_CPS_ID_231 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]" +LSE_CPS_ID_232 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:255[14] 262[8]" +LSE_CPS_ID_233 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_234 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_235 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:48[6:16]" +LSE_CPS_ID_236 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_237 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_238 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_239 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:143[40:46]" +LSE_CPS_ID_240 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" +LSE_CPS_ID_241 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_242 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_243 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:84[6:11]" +LSE_CPS_ID_244 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:134[9] 138[5]" +LSE_CPS_ID_245 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:21[6:11]" +LSE_CPS_ID_246 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_247 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_248 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[8:13]" +LSE_CPS_ID_249 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[15:20]" +LSE_CPS_ID_250 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" diff --git a/CPLD/LCMXO640C/.run_manager.ini b/CPLD/LCMXO640C/.run_manager.ini new file mode 100644 index 0000000..8c0aa7b --- /dev/null +++ b/CPLD/LCMXO640C/.run_manager.ini @@ -0,0 +1,9 @@ +[Runmanager] +Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0) +windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) +headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0) + +[impl1%3CStrategy1%3E] +isChecked=false +isHidden=false +isExpanded=false diff --git a/CPLD/LCMXO640C/.setting.ini b/CPLD/LCMXO640C/.setting.ini new file mode 100644 index 0000000..22632d4 --- /dev/null +++ b/CPLD/LCMXO640C/.setting.ini @@ -0,0 +1,4 @@ +[General] +Export.auto_tasks=Bitgen +Map.auto_tasks=MapEqu, MapTrace, MapVerilogSimFile, MapVHDLSimFile +PAR.auto_tasks=PARTrace, IOTiming diff --git a/CPLD/LCMXO640C/RAM2GS_LCMXO256C1.sty b/CPLD/LCMXO640C/RAM2GS_LCMXO256C1.sty new file mode 100644 index 0000000..7292d5f --- /dev/null +++ b/CPLD/LCMXO640C/RAM2GS_LCMXO256C1.sty @@ -0,0 +1,205 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf b/CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf new file mode 100644 index 0000000..20835a0 --- /dev/null +++ b/CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO640C/RAM2GS_LCMXO640C.lpf b/CPLD/LCMXO640C/RAM2GS_LCMXO640C.lpf new file mode 100644 index 0000000..64fb54f --- /dev/null +++ b/CPLD/LCMXO640C/RAM2GS_LCMXO640C.lpf @@ -0,0 +1,137 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +IOBUF ALLPORTS PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "CROW[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "CROW[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "PHI2" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RCLK" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "nCCAS" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "nCRAS" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Din[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Din[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Din[2]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Din[3]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Din[4]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Din[5]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Din[6]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Din[7]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[2]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[3]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[4]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[5]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[6]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[7]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[8]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[9]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "UFMSDO" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "nFWE" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dout[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dout[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dout[2]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dout[3]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dout[4]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dout[5]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dout[6]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dout[7]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "LED" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[2]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[3]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[4]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[5]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[6]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[7]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[8]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[9]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[10]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[11]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RBA[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RBA[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RCKE" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RDQMH" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RDQML" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "UFMCLK" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "UFMSDI" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "nRCAS" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "nRCS" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "nRRAS" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "nRWE" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "nUFMCS" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RD[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RD[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RD[2]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RD[3]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RD[4]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RD[5]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RD[6]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RD[7]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +LOCATE COMP "Dout[0]" SITE "1" ; +LOCATE COMP "Dout[6]" SITE "2" ; +LOCATE COMP "Dout[7]" SITE "3" ; +LOCATE COMP "Dout[4]" SITE "4" ; +LOCATE COMP "Dout[5]" SITE "5" ; +LOCATE COMP "Dout[1]" SITE "7" ; +LOCATE COMP "Dout[2]" SITE "8" ; +LOCATE COMP "Dout[3]" SITE "6" ; +LOCATE COMP "LED" SITE "57" ; +LOCATE COMP "RA[0]" SITE "98" ; +LOCATE COMP "RA[1]" SITE "89" ; +LOCATE COMP "RA[2]" SITE "94" ; +LOCATE COMP "RA[3]" SITE "97" ; +LOCATE COMP "RA[4]" SITE "99" ; +LOCATE COMP "RA[5]" SITE "95" ; +LOCATE COMP "RA[6]" SITE "91" ; +LOCATE COMP "RA[7]" SITE "100" ; +LOCATE COMP "RA[8]" SITE "96" ; +LOCATE COMP "RA[9]" SITE "85" ; +LOCATE COMP "RA[10]" SITE "87" ; +LOCATE COMP "RA[11]" SITE "79" ; +LOCATE COMP "RBA[0]" SITE "63" ; +LOCATE COMP "RBA[1]" SITE "83" ; +LOCATE COMP "RCKE" SITE "82" ; +LOCATE COMP "RDQMH" SITE "76" ; +LOCATE COMP "RDQML" SITE "61" ; +LOCATE COMP "UFMCLK" SITE "58" ; +LOCATE COMP "nUFMCS" SITE "53" ; +LOCATE COMP "nRWE" SITE "72" ; +LOCATE COMP "UFMSDI" SITE "56" ; +LOCATE COMP "nRCS" SITE "77" ; +LOCATE COMP "nRRAS" SITE "73" ; +LOCATE COMP "nRCAS" SITE "78" ; +LOCATE COMP "CROW[0]" SITE "32" ; +LOCATE COMP "CROW[1]" SITE "34" ; +LOCATE COMP "PHI2" SITE "39" ; +LOCATE COMP "nCRAS" SITE "43" ; +LOCATE COMP "RCLK" SITE "86" ; +LOCATE COMP "nCCAS" SITE "27" ; +LOCATE COMP "Din[0]" SITE "21" ; +LOCATE COMP "Din[1]" SITE "15" ; +LOCATE COMP "Din[2]" SITE "14" ; +LOCATE COMP "Din[3]" SITE "16" ; +LOCATE COMP "Din[4]" SITE "18" ; +LOCATE COMP "Din[5]" SITE "17" ; +LOCATE COMP "Din[6]" SITE "20" ; +LOCATE COMP "Din[7]" SITE "19" ; +LOCATE COMP "MAin[0]" SITE "23" ; +LOCATE COMP "MAin[1]" SITE "38" ; +LOCATE COMP "MAin[2]" SITE "37" ; +LOCATE COMP "MAin[3]" SITE "47" ; +LOCATE COMP "MAin[4]" SITE "46" ; +LOCATE COMP "MAin[5]" SITE "45" ; +LOCATE COMP "MAin[6]" SITE "49" ; +LOCATE COMP "MAin[7]" SITE "44" ; +LOCATE COMP "MAin[8]" SITE "50" ; +LOCATE COMP "MAin[9]" SITE "51" ; +LOCATE COMP "UFMSDO" SITE "55" ; +LOCATE COMP "nFWE" SITE "22" ; +LOCATE COMP "RD[0]" SITE "64" ; +LOCATE COMP "RD[1]" SITE "65" ; +LOCATE COMP "RD[2]" SITE "66" ; +LOCATE COMP "RD[3]" SITE "67" ; +LOCATE COMP "RD[4]" SITE "68" ; +LOCATE COMP "RD[5]" SITE "69" ; +LOCATE COMP "RD[6]" SITE "70" ; +LOCATE COMP "RD[7]" SITE "71" ; diff --git a/CPLD/LCMXO640C/impl1/.build_status b/CPLD/LCMXO640C/impl1/.build_status new file mode 100644 index 0000000..a3a7abe --- /dev/null +++ b/CPLD/LCMXO640C/impl1/.build_status @@ -0,0 +1,60 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO640C/impl1/.vdbs/RAM2GS_LCMXO640C_impl1_map.vdb b/CPLD/LCMXO640C/impl1/.vdbs/RAM2GS_LCMXO640C_impl1_map.vdb new file mode 100644 index 0000000000000000000000000000000000000000..085d429eac00e43d373fed4d0f5e9df9fee0e707 GIT binary patch literal 62815 zcmd6Qd3apMapzz#gNvLQfPhSh;V}n3eS^Us0%&HXHOG3g%|ujeYwsg_X(eaZmc5%j zlilnQ9kfLsqJmJgK~f|&GXOM44vLUth#_;|iL-Y$=jOieJJ}rG->=W=_a6N12MqSx z`D41Py56hq>guZMe*OC0_kk0m6Pe5_8T_K3`LYwExi5U^N8U3s@}?70xpzMK_s=WV5Cc_$hMqh6JM<$}J?U$l!Ymr8bWCBF|rlTv%_wIDhY=))kHY1tw zElRqYadrqz#JJCG(z=`8?&6&9)b1ULsYtc4O2XOp{e zdwa(gj$~AEf(6Z4C`5@#uu$ew__=gHG!@<6TD={!s{ty061I!RX8#jFLeXe z0C3em_=xS-u7tWP5OFS}%lFUjqyiI}$-~D^pwm}ot&z&z#Jv=wY-arA{OqBlD^|60 zYrZIV$>w3qj17eX<*uw=-cnbigW<_Nk*)k>vwn2uL@0fUiB~_@yS8>~r~1DsGX@pA zbZy(R+GAE!hm9^#B?K zP%nV`0n`nkP5`w6s2xBXQ7fp6gw}(yK>+mvs2@Px0O|x#D}dS(8ec3oOS8>sBbf0< z2-ZWe7J`)!tcGAY1WN(P{l@-^oM}Z9|A&u2nhWlAoPcaD1&k+ z0|`O~5`+vS2pLEaGLRr-AVJ7LfRI7U*8(~zA?Sf9gB}P7dLSU^fqDGx;M&JTP8<^YR0>b+BMm`uiQJQhEVW=>-I(7Z8+QKu~%CLFokqr56yCUO-TK4=JVhRig~b z0;JLlkV-E=D!l-y^a7;P3y@0hK`Onk1(jYvP-I(7Z8+QKu~%CLFokqr56yC z-b0LaqKn(EN0bp%{^wA_|42;2|6KgP^gkB^|KlL#e;lOzkAsx|agg#q4pRQdLCXI) zNckTJDgWaj<$oN6E?A8mr2LPAl>c#%@;?qz{>MSe|2Rnb9|tM_;~?dKEM)x8q0s+0 zQ2QSTYX9Rv?SCAo{f`5+|8b!9KNi&f$JT;F@rsmzgp~hrl*<1&NckTJDgWaj<$oNc z{Evf_|FMwqKelRWD9$z=sQr%vwf}LT_CF5P{>OpZ|2R3{6K zl>f1S@IMaa{f|Y_|LA&a|6}vY|7arPe=K19j{~*;aUg@P`%R7DowWaPrP}{EQ2QST zYX9Rv?SCAo{f`B;|FPB8{>MSe|2Rnb9|tM_;~?dK9Hjh@gOvYqkn%qcQvSz6#{bx= z8UN!z?SCAo{f`5+|8b!9KMvIX$AQ}aSWx>PTMO-f9Hjh@gOvYqkn%qcQvSz5%Ktb> z`5y-<|KlL#e=KDEkA=PesV~1dwpbuB3IEgE{^a(K^Pex~B!049Q8Uk@c8PJa7DrU# zh-w^Bjw4EO#6mU3WhstWj3XLxL_LnE#SxV_q8dk(%w|BN}l;J&vfw z5tTTi8b_4lh*AtOv9Wr4^~&ql^olPQXf|W;dJG=K;9d;w$KY-Z?!@3$3~tBZ^%fT} zeEkM7xEF)_F}NFpJ2AKwgWDlIzJPV4X{XoYOCh)zf{hTYhhQxPDKE2iR_sy`oJ#^#O` z7q_r*E-#T7DH<97ei_<8AEDs8bfNY z8$)XE97Ad^9z$wxA0jdC-+XdzW%@)6T}?-q)6u0=^Z`81y?DBpzX65|1!3iAR{2#3M{h z;t?h$@dy)>c!Y^bJi^2z9${hwuki`+rfH{?V7LW*dA1KY!9kAwg=T5+kJ*ei`4s>B5 z=BYL;%w}9z7-DT$7-DT$7-DT$7-DT$7-DT$7-DT$7-DT$7-DT$7-DT$7-DT$7-DT$ z7-DT$7-DT$7-DT$7-DT$7-DT$7-DT$7-DT$7-DT$7-DT$7+`H!h?NvO>&j+qSQsKr zSQsKrSQsKrSQsKrSQsKrSQsKrSQsKrSQsKrSQsD=wxgHcxOf?lo3LoBVvKC&U@HaJ zNx^kfaQzfqF9kP9!L6s@HdAmLNn8Qz>i0fyXdX|hY%GSJ!P$P8hzBt9aKJ(CLVa!PQnYn>`wb(mu~oky18J!c zUKoP$>G_iaoWSx;JL+7yWv(XNjn*AJxqPy@)U20h?dHNM5Ww`cx{kz8+JZp~%`kJh z5bY*yA=*va0yNfyQGpY)qQ+PgPN1p@)HtVl-uxZFC5KNQpAjh4V6}5$mirHb*BvA# z@#N?Vw?OQ$%{1pXS>i$G*7o(wMy^nW<8yB!5Ki7m^9e;G_l<5{-3s@O3Pija!J}t@&)-XB$4d=(9^cyWp}pIHfCwT@G%`<>A;|9m0z~S-;Nn9R5i_0Udad`wj zE|1X2<*}yb@>q3q`HskUMZPccJ&|umudh0}iF`-oyCUBg`JTuRM1Ec5H${HK=kst% z58BO)Ic%*JmGF7kNQZ}Yba~iCmxo1kdDudiUl;jJk>BunR$|3gVjL?q$ERnOjWEWK z&j;ZAvIIvTyk~}l;jkKANyR?smMHLAgSrgc>Bi0aiD5TEn|fn)%?29Tt9A^JVzZng z!W$-6?b{@y*feL57-#p}Y}se4K3nnGn$OmKw&AmjKD*?z3ogrX_L^bGapv+EXD*L% z=JFV4E{}2M@)&0>k8$Sm7-uezapv+EXD*L%=JFV4E{}2M@)&0>k8$Sm7-uezapv+E zXD*L%=JFV4E{}2M@)&0>k8$Sm7-uezapv;vXze8@H<9m%d{^ZABHt7Ffyl3m{HDln z_&im7M!&U&tu6@q9H1(rJkh<=C*Kr$B8iDx{@hEew?DCy=`X<(&74%X#?Jrcqb@r) zYqRpt7? z*+rjS^4SHKg}bW)SxmJi+s#w#g;OMr;;7{zwuozyJ)65cb9l~4CpY96be9>9vH2e8`d0jzX- z0IQrHzzU}au)67h+{Wr9tAx2tkzW`2fynnnzAy4!k?)9nOXS-=kM2VB~X??NdUQxi=urZzb^6vk?)CoU*x+Y-x2wi$hUny5Ao01m=F$A01&?`f%vbu zQNAhi>mol8`JTx4MZPQY9g%N|eB0+yy+f`NsGa~IJy!zhiRy{`y2uYiz9;g1k?)Fp zN90=~-}d>@X=i|teb9`xTxWILn!#L4Tw{atda z#_EMZdhTK>dVCu5@s(q0zesq&_@SLja_x&Z^%z9J(h~WO$ah7)FY-N+ABg5)3;JU_g2RL)8Nq#2&!#c0jJZD%vOV9g**fd|%{yB0muM zb&=l``3;{(`=(tbI0ij{(dhx0O%K4JdH|-@12DoKfO&R6_Oc$roLSlFR`#mL+1Zwo zv9s4N(-(+%H;yjP%43H$~*wJGv z!61p_;!MVF+`M*kYsY~Cb$R*YYamcf;L!kz+_ccP%O5WT42blhGb|mMzI^@C)#%ph zwP^d+T6B5)`po&~&wZqM;lt-z&GW72n}fk1Y~zSKNG5ta?~p&ecxrZqxeQePbVCAl z3DhJ|kw8@fWeJo#Fb+PQ?hDqkkAqVH)}1ZonfNT4c#vII&V$ZfA}J!a~iyZrK+t!M7? z>kgk^o?cnGV2A+Bc;Iu6-tW8kumHxk*REZC!`_*v<^Z(vxpZaQL%GhSk6R@jhdeHv zo3`6e$4@VX;9>|iLa-i!wGga?U^N8GAy^8*@~H=pt!RS{*KoQd!LhsRcOE-qJ+mvs2@Px0O|x#D}dSpVh7CV-hhii*Ej%uc2!Fphekl+x-T)RZ+dx;WTKC-8}J62 zIvR)hvEn+{`!Csn{?O@4`M!ly4gB|u=U!|bY<;-;v8UUG=bnG@nS#kb+x=+g+=mOT z&V}pt_sbA|K$bM5EOUwEN#-*cr!JQ1CpYgU&}%rxhh4^OS1iK2FE5N%&AZVs2z zQjF8UaVp?Z7wTZDu-7JW*98RBF{ZG%8TF$_AAQ)g>d#P$8NA~sM7qJpDZ>-#0u~{K zNDtJ@=bFt@xzSucQfv=brlnA(2Wp;Gp^k@3!xL(6Acb1OGw)jSx#ylX?J`oW22vev zQy0RfPW7Dnpu>mSeDb4Q*GBOGxqC&NQbLEm6-OFz4kz+Lmm9J7^{+CwK?4GTME06wmd~u z8&a;V;i_smrm9`nsm0E4IaOnvI-XOPn+JwBC@R?dBnL%57!*cX7o|{p!_}aAs6kU3 zzNv%Za%#jlZF)}q;R>}D3bll1t|_XzB&E7O+@NYP7E~?DaXDO8OEFdr!D=vExi(^Q z#RkC?xh@E~7C_>yx|+S8uAf@0R6c|G*wRvUchi6(H~;vUxwKe9HO_ZB=RWpqcX@XD zptAiYpnm9dxpH50!>S1;eSwWE z)KQi5&p-S0h56?`W-EfNDXt>9Vw=0qoRJ<{MQBKbv7T&FVU zKq*x%THROITX%X$c2|pjppkQ(=<_i}jg5t+fbBa}cSl^=u zLuH|f-C^_h&L3U603|3aVCUiRhrq^$lzp*{?!IyPrOVegA46xG5rDl+PV~8ApW6u& zinmlL)85r~z3frLi^)Rq3blnwbN#ue&#!dOU6?E2-R5ND>q}MgT&(SKsinvbklx15 zv9tTC%k_UZ>Ygzo0Hqf}p(?ErtZ$9hx3XJH-wCXcGKH1qLakIiSE#4;d8u4uvrDzg z?#z9$7xek$0;VO$=dm7Z+KMe_uB~ImHg}Br?p8x>(0Y~n-fit}sFg~1FJ1ICtY7m( zSh=txzEF{?Pu8^UxwpAB)%Uh?a~<#Ipl* z7QKzer3b6pdiL(doz0EiiMpucTf6i&(c8pvM5sWa9yE6-29#TTy?l=YeB$hrM!;BF z>Zyf=U8?kYxW=G0saA&t#iQI6BW~=IbmGnxyMY~h z>)lrC)xn+q=I-QNs)Xjtj$%YK=L+!U`=DA-B_Zyq7T_C~`4Gai7V>wko!|>Oq7Dy3 zxe%n*7idVzyA`^QK&);}R+iwd+gM;P-~}4NjL);ctX5MVqP%Ns%`Na=zb1MZTWoHj zB$oiAAvG;n2%K=ia7Aiuq=rqe_bQ%Ib^E(ChQ)56x`(tA+CVhI!6N!|Ao?>`(9;xa zER2ZvZXyGRc$mYe+Jx`5@mRH4UR*p^Xr#HNJu@GKZmEW0qXGb<&)vS)=dofx41ZN9 zHn_9V?mv6C)4DU*++`?Ms)h0Ilnwv~o115fgMDJzNMYHJHd-5CnL69pYXDGcgtLvQ z0ir(rkkML7A!}I5pcZ?58dR!;+)cO(n<2CeIu?v-qu_gOd2tYo>#21#Tt81W4c`zA z&lV7ZC+*mtXZGDd&krm?&l%*e9D9qY#GofMy`ZIKM|w=r`y0DdbUaRw*3_6COu8@G z_`gsOqujkc)-3jdD0i-(HodB)$$QUz-jB&!g}Z86W#qjn1_v$GQABHVfYt0g7I?aV9xBnCthA;JvK(%6aM zhjXzN%&T;ayvJUL3kVksU^1*(K}dS8P#b=ep*}*V zSsy%{IkbKTXg%;`4Zf$MmItsdGi>$k2gY#%J3M4tVZNM!8apVR?_MV}g}^Qu!#Fro z>;)Za7MEJPb?o)9D<`$>hvF2N0y&8Z${NqR@Bwtk1P;-WU|;n|>eJ;&$g z@0n3saS=aDTdW>UE>?HHI1WP~?9wb=x4k#URoCetwr;6Der3=(lff@rYzKYt(CJ$B zzQt1urCqL?mr7wLn26Gb8^w<0zp>FaH7G2}-r1wsDq@x*Br&A|TE$BXV76jA1*gT* zIX0^2lpG3+awff3F%;K>8FWc?i05eBW8Vma704Y_SD0tj!&#pzs3zGb){`Z(^0;zP z%|3?9O3jWOtFp0Tc1^h_TUyX6V$A4XZ3{M1$sRYxW&KP64@iam9M+)62?RpF6t`|< z)q4U9C(eZCioI|tEJ8Qm?X}c8=wR1IF18HDT{_B$Un*|y1G}XdJ8sp{?2HaW(S3^x z3v!Zd7Jm2E;NnIwRn~hwk1ii+F3%OJ!9vI|#9Qoys~~E-r{-qbyD8c`fu|#B+Y7KG zj!z8grCmO8#bc6Sd%^hPx#o25g%vzh-WPUw=D?w1NAGyUuv-rT%DoQM(qb46&8&TwNozWqIUa+q>Fi9}Ix*>WscTffS!!?g;Dq;mZwT^YJ z&Xas8<)G5H;qp?W!t$EvVAqMazOp%7QsKgVE{4&pxje#d}?y zFO@^TaIj;8Uv7R{4D9ldSQgg<(_E-vff{eP9zF7a-}{BW_s$6GOo6o=hJPqk!*(A~ zJG!;_i`{+TSBddc+q#49#)DDU=IlW=4;ZdFQ4ep9J&POvXd#<}7k zY_yGQ_Zo6E!gh~W@$T33p_M`?8B&92uGEAdC=%o zI~4Cwj7BMx?G)c241?&P#l3x~LOoUmzT9KgI_TkHG`NW8!y*7s@7x6Kg%6V&%~Kxz z-nqABhOwoq)WDgyGN^@)eelB5hYBUR@G`9ZV|Xwr8a!UoylikOT8o{6sWCiuKyk`| z7lwBC+ym<_L378@!B@6kFK8jy6-zUG_sXoOJItP{V;elbQWcNH7!&a<7krvGCsIx!psxfv;nq8q0N_UU@46w^kC@i;@+DTZ| zZzgXE@#YRHe>L3DLOE0$T1;&swCJi?QK1?P(%~$$cY-lG*}x8lc6IJ^PMA@OnZL71 z*frx?sb&b!q>^h@YXs;PO-N?-0CrI@H@&T40WXwOM6n2@X*a_l6);e2p1bS zGyM5vdBOoeZo&Z+MczeCDBpKOG-0R$@xEU}k)G!g5o5g2?#6$#} zX`C`;VakU2Fr`$DEwStQb2YbA9jrxyP9FQ5j;}f z>uOPHA$*!#0vIeFU4^8vOEhedzl7>)fAFy0OcoLt2S zcyoW)EydVjw!sC?LM>*R_O=%U&sT(i=k+F4Y*AQ8Y@znpZ(xu8>NO*0tS`7RJ66!9 zGZr}QHI~2xS=NYgqFUG8*dHk`#H5T6SV5;Yv!9rd z3k|v8h^Lr)8$g(eC%Ix~5#wqG5MGk=U5huO0>?9?SzReMtHYBK&g$?iem}S&hzP7A z9*n3tgL2HG zOlKe1VMmedTXkBFSrMrOvk$c*ve%b)v9(o5dv4v$X7!#fzCvy!&6Ra0>4{=zUlh9< zQ*4B9Y8Z9*gp>DJ$m%vCvZ%_<5%?Hmq!q1i@o78 zug91V63qR9$635=6zbj{Ti%EM~+&X>{STO9Wd>lW~R=ybKpcjOjpy9+K#m5}kIHmuly zVOhJg#bMTl%eoe0t!=7c?G7@BQH!x&D&N;ApQ`TiIZ>$|V~zPgB|hz2ZBI>yNgFQf zMvOJWWXake(GGhyT+WLj=ZOua+pAkPg0#oM!=Da$l{od(P!l&fsP^yAOZBaK$*6s|*DiyA1`ZDV!BI!`Xdh1ePn{{MNfT zz-r^pptsAjCn_n76*J9Pe9;7^E8zUlX@uAqP?cS-D3xj<>nS~;_yHBe+kZa=)+?2F zZMVGZDZDj1!`pwY1qLjYcYU|K8!5asJI&jD8wMsU;M_co&6rE4c6nNGX))wGL3#6y zAI(*Mg$6b(VEoW&L?T!`tnc<6+@+B9ln(m1)xk3N-@Jh#8!q#O7;_!?N#_0wJ1}PY zxE*iI_SW)}J`>0qGqY+Unfvegz@814c{#>h2Y`~f|9TKi+HjdyW6X6BD4F|j6~U?v zmw6?|TnB=Zx&JZ}4BK#-;|SPb?LY^ElDYp56D-?snPZ<;z+4A}lDYrt6HME1nd1e< zfVmC|C3F9cDOk7RGGB}_*MXsA?!RaS3zy1#w`cQ~mSW6x%U{2_wPr1x|9%!M+;EvM z#F*=rd*K1m;Pj;W*wa!;S+tVT`nI{5BC9Zum1D7Oy+)(zGC2(Nxu$hX0%$?A8W*U zJ`v#CK>m58B+BG*V7k92U!{2#=r@~`WW48}LrQYO>YjOQ`*4?y@v^7QWlaC9AnyY{ zX)fb!OqCk8O1ZZQ;+M=#Z2i9;aAv&Hd0bc+Ehha|q?z%0!0-SW{wWGr{f{9fgAURMkdh&rM}{mXL#D4G zB_lFq#h8-OH=Fd^k!HqgNk*SR0WTyY)|f3MOa^59wI(G4!ncsJ0%X7nkpW>cAgmbW zmvH)(mG~$n&f6`El$U2_&G%ByH%m~9<4wN*1T=ry2!FijEl63nOkTYng$#dLYNKr< zWsn(rgr^~Iu@JvS%5WT=)JGAXs5bT63nf=ORA z>8eS;(xewnO6}rxmrVKzldhTcvPrL)^r}f;Ht98!UN`9tlfGh7YAx@-X;O-daL=Ta z3*oOa>DQQ)T}u2-ld?+*Z<&;GCHzfDGh_N>5ajsFQSMgfK8kX7Iq9h~iayuDM^6Fp zH_CxZX;N`)%GzaeJx`_X$v&a_F{L_@iuZh7QE$Yk*)ybON-9$GDn*^=i!)aFvXLn! zxne!hjvi4jS^&XcfvWO{=7#6Z4LRI+1yic+22xrXn^M#)r%0LFQ9_ZjLZ3uR(cDGK z;rIG1;>IA4bZ{EuL(MCmW``JyYJEw`H1{XoU?@2I~({Lc72_ zvjMy_d%@nB4P%3NXO^=8$yaa~xsxy(V%adwjOo`Vk>gJ( z0ab)@qRR00T2***14-~xR91={NR%EG8y*Aa53*|fm8elfvu+%ZyeY>Y33wS{rYz?; zBg}C|X>oip<+wU+Qc9EKi|jbAcwHMQ+e|*ZUR5^FV-RgMl=)#XMMrj-91pcY%3qe1 zqr*DLn(zuQn+M8>?>3 z#Ty1s6(QX>o0PsTlY1m`eXZofyFQA7A7bfPJ6gr*yU6jU%BgS^z8*R1n*ypZlbNS@ zX=7PT9iTv7G%!>4EpJbGQa9MAOi9n{h_|}Il;eOp!gAVTmQz=F-*u$a8K%5%A1M`> zHkI&eCS{mGm=OfiJ0@i_cz@~;@AGX)`6+4{VT`j^M&Yb@V@jPVrOgX&A*FIs+Dthh znNr%Be5pCR@*pz&DY3DbV*NCWb9~Q;MfiuY&nmT zlw*lPB`H&CZ03OYvK~PGlo25j*)rvjp{2{@+TMdGs^@@ZWo^m#6RUuU0GGvPK3? z1@3_?GsW+T-cTPH0mNT6!XJ$ZMX78JMm(Po0_0CsjCfXrDepyPr;_{}(##b1Mc+_Q zGXe3Jjqpbr-jiv@e%S6j^cJTav2pyVSen-JEdV&em{Kj6stZvWJ|+dopVCmv{AYRN zJWh!Y)q=qf`7+Jq7jOXY1!VYBaU{ntRe;5861iul{Q2F0_$#tMNW=bM%4RcV@4bPP z*D@vkj!8LI*)%FT@k|NRpb=(Dn1+q8O}`azX5x`Zd~_ad<)EH0gZdMsnDXCf1H_+_ z2M0WBrD!IVq2t%n6hS6)hz+5UV}+TrK@>G%rmPUvlIbOr@>VRTs98}OGpa8gAL&{K z|Ehs$)QD#QNL8c}WBN@rs1i2}o_2_> zp~+_JnesZCY^KTtL-G8Ca-3|>p_q+i%F9?!!W0r=j$+=H!l6)@X7WpNyiyo+1nf>; zhS&w)h_sDUqs2~!ZCBa5vkNkLYyxw$+({a2R)%e4N}2F7!mJ$I!pm71rmQS)Lp<3K z)|JH4ovX!Y1T@Kc8+$oBK10KSH4o(Yo234Z8U3ZfC4JZ2*2bgser)V5Q%>*0kbonH z)%td%!ccpwPJ#2L6sWy9)67Iyy^A)m)yPJMf~un^MtuyeECSVmw_!@2REx|MU$zO1 zn(AY=lYL1Vij%5CF|8wI`m@0y&lG55yGE93W zrLqyGq?q0`DJ4ai9GG%wW%4y)=9HSSAK4i8Gb=)vsqW84ZOIu;)t@Zp5TGGoN;QGA z*i<9&%H`{T_{&E4<1I)-BaoTyv{Kuq#x=Erb)>`3tgW|Uuaw>YPn0I0Ehmc}^u}}&dNHb3jV9K%2v7Ra6lY=QnMD;WYDKMHm z){Zc1#|x%4<&qOB;|%G`r(Z@vZy*tt#cusVqi)JWJK6jfDAGR8aV#< zxc)L0K>kz=V7c>RHcO2|taW*(r#iy&_%_}vkJrn*XdeQGRibc|=8r$4_san0PX#+H zpfH%y@BaetgHKWJ*jP%5(qS~sM$z8P3fpP+z!LE}fo`WRA5gEJh$ObJs;gl)=-5>F`+Z>43^Zv;Lwz8EkZ zV|V;93doR*m|8}ZBaI_(z*OBJzqIJZtpr7KO5$sgX7YF+&`(h4(Rej=@H<$X>u+v6 zhLk^LPQM-4vjAAi^gB)ZT_*i*lYWm$zt^PSXVOn2r6c2;Dai4s0x{l?T)&^?2lzhG zas4SLQs9^6I9fv?#}U(v8b@ZY842jISirmdA_=Cr?;o+a*@8!!2!HHH-bD4Ma;ahX zOFZxK^SnnM4{!Zgj)37{;pI#@YY8XK#PZ@FX6eBej5k9q5$c#&6mGu*3R)3TP_e!qDQ~F8^H?W(=VK3F1jwK2299@XHW|Zr#u?rPn$6S2OCkbO z`bjiLs45=o1$U={vW*<*s(gZrg?yF{1b<4I{sJX98iEL!l0Eo)hQjt7Q{I7TW~?8y znmWN&vkkhu6_isd^y;j$D$nz~D7KSFBcK`Pu*;aTNqX=vh^GKb_O!9A|9PYcj%z~s z89P&MY?dmF@^(;8 zL0Lhl@=5o(ca-p_+%5H(x1bQnO7-h#ETUl{CDk=VT4FFvZUUelb3Kn@N{lH-q-{8- z8Ppl3u+mr_yXvvunk)1Lr+3dHn|A0;z{$s+QJfN25Ex-jJo zTz~KcdHz)USi;)eK*}NcE2PY;FJ~jepCV(3OERXc9EYTK0eJX~EPpCi$s<;wKuO3& zPWA^ClHEs`D$JDq!jx*ql;ege)rRReAk9ql8KH~#oP&UOW=(&96k{8aTo|SNcxP7i zWp#&*Q04Qq-oJqoHi8r!^SpvO^afI1$&`0)3GYJAq$lSeQRSNfXR5xvkFNV>$a$2U ze-l?y8l>c4Q~QGr}cmn+i101**6SQSyNt5Jg@&TUZ1bZrx7gXfMX}A zftU4jNj8#!J{4U>qxpsyFlshQh2y1+K{>wEu$*n|sHN&65>ZR3(oB_r4?cSKsi)4o z>+SE`_5(=i8g-f7!<0hOQ^0DxCM;%6sJSFlbAw5J`hgEV6@N} z?9RlgiR9Bj^Da!OrZi=gk2Yzw_)PIx6mzCXa^5XAktCYMG?MGD=@*-0D zGs2nCvUAYc2(T4-n}yldWBBJ!iH5RfTbc4kD!_*sl*5#R#j3FKOel}5F!5C3|3w~{ zjHJ!QvJuJ{1yNzuc*mSR9&}Qv8Of1GRVH7N{S*OBqeKaFJTN7Ue!|!4E+E67n!_-_ zr{G!4yAfs+8I)(n%gLES7RHdW_&5ltchrBXEH9+tp|526Nu-GN#R38)^bD}PJyX_- z%0~7*QX?{sb?gU$X2+5|Gh5zqM5;i8Eu{jpW*G!|vUg};XqL&7!ezPa9SW3q_Rf#9 zJYS11^6|FR9(8+srk&FX^EqH(`O8N5V=)z9*PHgPV;|HUK`> zzZ?Oi3U^sTHorzTh}WgC*-Tr_Z#L!eW)jcqe~RUKd>PZJWi|qa0RyW^>y|md!vMm$ zo7$N~>qwpDxTY#n0SNPAiil}u44lPdMv9OkW;s0y%j0z;o^|_amgg&R+x0Bayqqa5 zFl`oLZM!OQ<8%(i)M1im4pbA1LP~czh^f05Nt9m{p|&bs1)9T#>z$c=c}Yl%lh}2j zSrb*98+6vK^-^8+RVd|%WXh+m@#fNDv$;RR^6{8TvoER2y!}^@AnR|=LBl>^&6KCg zZaT&+ep$rb@`|b@d;Ia|^=*KCIUs5;U5SR1jUt?~rF3&GD>Y>^)j^nstnwfOp z1_8jI>J8dU3XGO7GwDw4WjTI|gjHbs^ypLZtq&*EHU!>;W|K|}D+XQPCu}1t$u=@& zK&`~^3|oAqLkONl-DxV8;RnJ9sk=gi@#eH<76yf%&V=l{~lG0ExEp!SKH$6RmC_N#254GPXbNe z-=~Y^l1Bve>p;^`F{QZgpO=9_fR^^>UIorhY|DwwIwU%(@lZ|5e ze^uo?-!Uv_t62WuRCzB^&StUvzpL^=qWsgQ{C}_<;Q=0y;Vn+&`BNs0gOGRlRZ{3> zRX3-e;H)u+Fp?@d00HO5lqgenI`MQ$gxL`kCA*U_Q-=7lK=C=C>102sip#<_D1*n2 zpwU$}0jK=OELt`~8C@_o^A-p@=o$ z08=&5bgeYHj~Y6r=6;XTpuJ(jCkiONDsxhA=wTH2R^dU>C#($F3o|^{J$dW2skR-K7 zoPqRVOUeG@%N__H%gLmRK32B(XnJ3dCnEv9eA{ zVt)n{h#$4Y%2XwZ{h3W5{sK#^?AB~t&N%qU$oQR>@CT5|yy>YYAAcfx+`o_<$*stic~h9&)pbW(c`3`qZ`CH={CQhRa>NdJ~4{i$?Pd)5j_|F$Ll>2y+i zItoa?(2}YN*IZn?{NA~dzhfzXmN!jM`e%S6f7ep}TsozDU^(*lEalIWG9iC=$_Fa? z_bur!>_F-sm5%%aOZtncq+*se^0+1arBqTeSsD3y2)Qhou5ew~y_TeNWM!nx_AD8g^#A6eqxNGJBk zBY^lHTjJkLC-%n~fcU+Z__xxD{qX}JexD`&?Q~*)TmXolvc$iWPV8Ur2l4wY@$aS+ z``7V7`~ge+d+Egf^?4Bg6HEO2>BRnZcM$(mOZ*4v#Qybk5Pz{H{=;-)|2jE{|CuG` zY$>I?{p;T#{^yqXk4T)*n#q|>?=qEUx`WoiF3 zoz}g<4BCHfX+M)r>s~nq?Uz{E3}X6}wz+qNLHnhamivEFXx&S_p#3+NmP^hlwC*ij z(EeLX%PsY3Rt;~mq5!{KEPjffJ+u2e;eW5nIUsh!{puQ88h{EdTfSt#9qUcJ*n7J9lQD`~06<&-0!4to42? zek<*@SFN+hOV-vpvTRGHzs3*Vw6@mz4+nkog?YZ?+OF28z2KM^;-57Jvc+uKmG7Ot z=$y-ItM*x+<@+x5tz5fz&)z!?@6x}%cg3o;1HJzJq`94^PuZz=a{8=|XUv^==8E2p z3#Ux2*m%~iy?d<4`lr&rvlk{?M-M*!;3Kw7O+9J;DMxNO_({)y>hq61bj$SQ*>hWt zIQp0)4?gsWEr%U;>`_}juxb6KsfESMK7P@ri??jP_@kS)gxqX7WY6Sj!)Kf@)qC=(XP?;X-%px**Yqi;6@@<83Vrg%v(D_@aO#8Yr=5A~DN`F4x(+|`;G-Ky9d-C&CwU^vk2w73L!Wy15skx-I_`*Lj%*zL zFURJCS)NhlHJRZ*9!YAzJn!#ZJI3q|;Zk@Q$#i5L*+ABM^~_a=dIGIi zFDBpTlkW@3_qpWzbn<;N`94*AFLF;p$5=uwN^~*#KA(JFNWRY{-=~xBlgam~_`Rj5 zul9~ECDSeGk@QOXBy~x@WI&R~ifr##At#pDL9(M{m1MPKC&?N~N7gbKs;5n^ENhvr zxaKOZg^Fvw;##b@W-6}P)Rmef%PC5}Odsn=y);mkQ$S-z0u#-Z48+Mk{tc-C3#pa*oG&*CfJgSq<$*D7^Png{gti9t1;Zr3~lhCw|k{m60y5t#>fnu0@f?VY==Pn=S+~vcZyL^~) zmk)F9@?p+hKFqmmYZ&wnu=Hy6!BgyuI|r-I;i_|}>Kv&$N2|_pcRns8G*)pA+58t8 zLzYva`9b>lCv?kZlI2vhG5;elvC(8Xm2b>H1|~M4ET??N{6k=3gUWIYWz63PCN{4u z$9%^8U0`Bk%W{lr%yR=1n_iZismb+o0uvizmSgq2p^u_Gp;=}*ZNZqLJdvS=7*mud zGPE0GitR6^@t= zEV#J}NBV^OXGzwwP~pfm;Q}{b;V3KNj*(<7ixrLrD za9ay*gZwBL;r^E-Q?ED+)L#oE86;pJ2dgBWgnWS{s|{DlW8??b`XahM? zCGms|(T-M0Jol5lP?FWgOLBkrg!~sH$0C_OQ|=rEBPz3B_r!)%Png@Xal`bPXXOo= z;=`CHy0R{<_L!|{Ac|YxV_)NY>|K11{fY0f2l4$sb6{?5+o)WeCOKX5F3A~^VlZxP zV;aV;XG`8KIY-jumQzY& zHU%cub(T|hW8NQ_So2vNTdwL1d_OV~QL^22&VgIao6G;72FgELl4C5EI=baMiJg^a*#NWa-#LuHh~)t~&Nm zR^kj?IrcCVkPhK4lB8n~9QuR{>6K#-9DZ;iTy^Zhj}CjWBpG}1_sD4-)`%=?E0?S7 zqoKp*`#w}h&3hk;O%|)I&6kuXk|Fi$xCk<5bpiYM{dQTh?pvF!&GyKascRo~_^}?r zGBw@QHC=H{R$NnwtK;fPwR!E9csw0fPc3n8Rm)HL*(L6oCGN!~?)fF|g(dE}CGP1Z z?#U(YsU_~M>VK8|Epg8*aW5`$&o6N=EOE~*aZfLCPcCs!Rov|duG{y7=@U-&>TN%8 zqUs#0I>)Qd(W-N#>Kv*%hpW!Psb%ow{+-v)0=7Nqzg2Kv{*hpNtzs&lmJ9IraZs?Le3b6wS0AFAf6;%qz#yQO1Tmec<7Pw3;pz?CCfmeVd< z;C?9q|0YrRa-7R@+HEV`k0jtP93OD}t59Le(J;$t=N;&NUjp9ic%S3X9e?fkJI6md z{za%b%P}>}={Nnv^*srAkK+#ufr!WjW)qg{1{5Y&yqfIU}`&bvB*xvYav8!qSQr zHl6>noYCFF8e5qSv;2-2l#Y;9=Ef{%KCqBZCNpK0Gf`NgbR~sM=FKesdJO4gGK*$8 zQ;UV9Gb&^T9M3L2sO@Ux5 zdOOhuaw6^+1QJg|J|M|z>#8JU4CL>OtPh_B>d%@0gBQ^TaLnw?Yb(7 zCuAr}eW+4HctV=VeA%1j-;qy_(ac-VeS_tLU)OQdbB*KX8!tNUqKCav!wbjGWc%RZ zZqEFl?v&SB56!hZE_sUNFiEi)Q)@k3&LbpGl{`&SzVLg3O0E{UBJMt`j5u@ig)6%YSWS$uq&6v(mEDQ6Dz?3^GR@j52_VmES zs?@GAVH#qJbPn;@s10L^bRt6?8B?Sa8EVcLOD7qg5B9VlFMPI?(%~77m<}wsa(IR# zeZoCQm=4cyJ=emO!!sQEgbQ3bJj3C)pYZQ2TpXVBBjvR15A&Bz z%3jbu;@cmMXDZx7ZF1x*ABs)3K-#kWWW}WFyjJo$Nt?)xv3hH*ub0;wByW_wNs@2zJk(m>BIjErZtw%5sWk%sT=TjhE#V*qBpbQd4F* zWzS!t4@-#$#AxO$r%sHsw0ICKIqJ$dON|G*lA{idv-GM>Aj_%F{H6M^6srv)%c*E% zEloX?CCw$vF@dp`sus@`){H~UmTuB?vi!~RZGEv*AQ6Bh1A0Zr#*^ikGk=*rEHYjg zJP(V?6Js0W6&)L5meUlBapT11n&mVUV=SG@(9yHdIQ9ikeX0%|9dYOj^Ttt1;$e&s zbmQKv?ZBaZ>v5E5(-J#z45p5H>KNL0Fb$J922-Y9I$CuO?66RJYp2K9caHDG(-eG< zXD;|Yb(QPXTBhRQQfu9;YPdjhq2wY-%Vf!2EcYdnEs{w|+;q!otWtGHY&C)7Ol;u+jWIH=BpO6NDLE;B33#E~=oLaRN zUWltOWtLOt##jbQgJ(GwF~)Mu@O6x$)?bdjjIneot-Wnz!{Xc-4|}E9Xb_=)9?bW) z0|)h($u~`mZ3os<$2vV@7R*HI7)u@Fsbe&CjHHgC)G?eo22)2pb*$5aY?*`9F_t>U zQ^#oP7)c#Nsbe^G45p5H>1e%r>s3}ws+`uVXOr(U$@l;KQ!i$flZukdDy2hKDIKy( z>5x@QhpbXMWR=n(tCS8|rF6(Dr9)OJ9kNR4kX1^@MCy=LN=8;G9kNR4kX1^DtWr8; zmC_-rlnz-XI$7E zlA9&BNN$yUPV#xl7bLeyZkK#f@+HZaC0~(zRdR>qYmz%9Uzgk^`G(|f$u}j%6W7|o zZ^`*>$#*3GCi$-9dy;!3-1i@(al?CHG5yCHb}F zH<@$LW5Q3aMd|fb&gb>qgCg4)j3vmPE?)is?PdoHCI*VaMd|fb&gb>qgCg4)j3vm zPE?)is?Pd&HCI*VaMd|fb&j|*Y?d@mpwg4oK$bJK+3v?~Ek+e<1HEI4)UJUlRtkF2 z6RBMSRjeEImM2m>2dY>_=oL?-)�pQ)D@#sbyoQKou(tz1)e^>Od9ijVx#EwNR@9 zRjfYrS|?IF2C7(#WH}?Xh1wxd#mXeh8NiKN8K`2NlI4u+My&``v1-w)oJcJXlx9n- zXa!&vuuubmDpoXE&g5WJf1rx>jo#oysvf9fwWHTJk?IRnvG&PwW*CdGH&De&D9f36 zjOqzgu`bGT<|CuJ168b&^vWhuU4bgrOnP4vsZOYJ1*La2k?9CbTuEyp1Y*Riv2HjVgOpq?qcBDtlF= zSOFMS_Nqv+Ffgj@Rgq%7U{u+wBE>SosIpf@iq(ZtWv_}9iw>j8UKJ_UB1V{XFsonutlt0Kkn$EdPbMT%9CQDv`+6pJOJ%3c*I)=);3 zy(&^Ht&A#rRis#P8CCYGNU;zzs_0dR(46GS^30f`S4Ds7Ps>rZJG^XfPkzwIzOwp?%!*bG?qE|(RMW!*e4G}JI z^-8!A3l}%Tvlck4LAbz`?<(Q2A>sBQT>7pO64MhfkjcABNLmabA7LSr1I&=LG(rY4 zc~=QZ3nk>3g-qU6LejDc8OY>aB_ut9kmD9IIlv4_PalXsPn^gu%HX(5w$m5}sY zLIyHOl97UtflS_2LNdY-a&HTnysLy{WFllBlXsPnjA(>hZy}R+ zm5_{tgbZZzt`d?Fl#u&c$mCrmBqJ{&1DU+5gk;1ftAu1`A!Hy2%NLoD%t(aX-$D*oNoF!a26Ct*dHF-1Bjk{U9I29YEJ6lyv`XSh z$lWdEc$K7UL9R1$tV+^15431U zt0Wx=@^MCvS4sK^(FSs?O5#b#$6LsWDoG!KJiy3xRg!K%w1KRTS851P$Pn#dmBbS= z6lJ(d;t3f{HdH0?*uecT}uK(D(=1#AJjZ<#tPOpW;Bh*9U5o#jw z2z8NogxW|vLVYA2p+*Xij!-AXJ8Ye4q;!ef>Lqbo%_MHCo5XFklen#Z68HbXJ9X3(5ER zQZ>ANEaQwXXv5n__b<-?3@pD^L(O%P>m@fxZj^jha+Bm{$t{vwC7+XgUh)OWZIat1 zUzB`F@?}YKc3@!nSLE?k$sLlfN$!+P?8g?B>yJ)uH<`?dnDhN zRL&d>EdPPLeki$D@*~NQB|nkeC;6%5XOf>wej)j#j`jp2wM(Fi87RwXr554Nfhy)B z?FmL|O`wX|Nqd5k+9^=QT%|q1NUaW3F>`58FjA|a%6Uv%f|1!VFmYDXj$mYV2uz&g zv>_Oom4S&fp7sMHvm!8Y{?m3~WR?de&W73zjLbk_;@qgsz{vCmCZ1%{USMSEfr;~` zwgMy57nnGUY9}x>sDr1?FUBE?Av}|GT&-TFp_3rouMvgQ0)pv z(rny*U@{l$+;$|*$~r@xhGdwr44IwV4@~CiENA>N(k!hr)M-ctCL_((=^UPS~#cJ%jR^!a})q_h6xW<|Fs|S}Dh>bJ*FIi7yIfJsDKC%|DWOb3{jMqk6 z8|d^l;LCz6XDBz?T0y6`f`Vq0H`>}kr?-QGW&$wUT0*C{go0*nFxuKer?-WIX4){? zT0^I|hJt2BG1}Tgb^Vg%%r(YZi>R(-=+Q-sEX3U+&S_@fv z$joNdmueWWHc~lc_J9H|f3Z^_5r8BEk{OUJgA@#;_#l-8Qk5VT4q_G%>wy>mwd8m!K-xwcA7lYdI}0BIAR6T=8W&YYq$J6GL1VX1ck{8J|qz>QRq!k?{#At}(Nm)r`ev zjaKJ`;!-rrS?m~PtzB;rONzCSQ9eHwOWQ1GsbrMTs>KpG%UMYo<#TbdRL*i1T1NQ{ zUM#7zoOPH{KJV*^ZHrkc%UPxwWg|(lM9*?oaYmVK)r89Dv9*v?<2`{|lB0Y*$@lm|lJD^qB;VspN503`jC_wT z7Wp1uCGtJKJmhWn{J#TUSmltyLjQdSyv!=GgPK)JhpbXM zbf}?p=omxk(7}b$p`!|=Lx&SehmIqZ4jn)!9XfJQI&{dObm&+?>Ci!f(xJ_&(xHK` zbZCGq9U4eWhX&lzp@F${XaFxA>MPNKRgN*MgguAyd%S@S|9DRu-{Wm=e2;g&@jV`G z<@>*T;yE2DYsG-NcJLLNtX?U3mE_fu*GOI~d7b3-k~c`+D0!3Q&62lB-YR*UI?45t8zeVM zJ}bFNaCW92HhGu-9d8Se6b*>IO{XSmC^Gu-9d z8Se7!40ri|O zHf&9ktS0o&GqP}gygq(|scpPG0h`O0j%n1d1C<;QqrV#Ut3V|O#OTIG-5;prfEc~o zs9y#uIUq)-H|iIGN)CuI78v#OKqUvn7$S`NS)h^wVvHO{{WMU?0Wk&?qwWh-azKo6 z#;BhJDmfs=@MF}E1C<;QV^lKgM}bNXh%s0hb#I`O17eI}M*T2Q8uL%Eiq}8dMCu2D z(hLwOMm!7k{Xl6xh!g{%QTGH&vqPj9AC3B6pfp!Rieb~J?*>XUN2C}{jrzAh6>F|6 zXOK1OJ5c2cEXx^sjrn$9;(9F08IXk@F@vR6flxzVVyS4D~`)2OmnMT(i!sIpf@iV4=JvR6fldDp12S4E2H z*r>8sMT%M4sIpf@ipkrkvR6flIo+tTS4Cm!xrs!3Xxim6GuZqkEBUALM z$b2X=MX!p?ha+RXs(1+2KY&6Urw=1|5Ie@|M*G?@FNsWYZtSJ*M<`Dy{zIPj$zv#E zl4~ysg&(0j<8gtjefJp3nB>w+Lg7a!uZXxr);@j=WlVCr1)=aGlviwAWb3^^3}sAu zUW{OP63i_X*XerE5Q7<0OAd<>3{Qf&>ElvgZ!TgmV`|AsF@oVqFmFroX+f_-VlZRU zD=i3yC&9dN&K5SiIR-PPmYfkI7@h?4)*hc(^tL7jGp3dt5F;3#1hejAdj#RRM=yY4 zIHPLG@i4;SNjUG3#lw@{DaCL`r59Nc4o|{)Coi7B^qMM$Gb+8tf^c{e&c}`7F-~v3 zVmPB}$-ywf;Ym0jii&4Jy-bVYjH)Ha!U%^a;e2!}9w_yGE`~FzmK+Kr9G-;p0ke22 z)xQD6a7O7rNs0q9gu|0?J_Z+$w))S47|y6#av+RwcoNQs_2T(h|Ev(h8C6S;gAoo- z!ud>5JY;A2RWY1Vwd61u;qWA!Pd>$yx-J5X;f$&!N5Ke(C*gh~Vd9TZ__}0FJ~k8? zRZ9+n5e`qn`4m~~8R+7&7|y6#atw@ccoNQM-D2ZG|4|yl8C6RTfe{W*!udpA>|W@O zv>48)T5<%8aCj2#=Mt5#*aFeN-O9(xXH+dY07f`G3Fpg=Vjo5S{~N;@RZEV45e`qn z`3k1kjLGsVVmPB}$>A@;;Ym1O6csxWzG|Br9eT0O39tGk)_A7T?~@Q>f)zC?MsdfxK7R&CEnitUrUV3$Gb!5$L__5xR)I_D@Uew^1k!NSE;=lPrDwBvf_ zuNceM5$(ep>%HFk=9 zb3w8wxm5B&$%iB#mRu(Jh~%S^^6Kw!#3&9Y?)vXOS(WxhZ9yo5b{6SceUVXO&(sz~ zWUdKJ?5Em-h|FgK6ML<;AR=>hU}7KE7DQyO3QX+L+JcD8rvnrFw{{>R^QpkZ-mVRZ z$b2#|vF~R&ZNkcPWnkh+kma-#V?F_sjtf~%qp=erRtweBF*GLQtRAYTV`yZ?Sxr<= z$I$qUv%09Bj-gQ+XSGp19YbR^&g!FjI)+AUoYhG6bPSE#IIEND=@=TlaaJqU(=l`g zQ`VT}XM$PnGwdNyChQmEU|K4?a{+}M0jT}aW*)A!~-E1w8 z7FB1RsK()?s#T;jT(EWoj##S|rn6s> zwXjL`>A;w%7KSV+u*mT9tOBx}qFaZy!0FIM#Ta8@Ds81_x^jcs!)!8KLOP_{ipv$6 zOkAMwJuXT39v2~ekIN3e$At#px7YN_L$Wlz@>ndc@*pg(^5`qB|JXmlRHs&&b9&?w z_kZI*mz2Xh%lQAoM}YQ@)oLC)N!Cbqmh2+gRkE98tt46cw|5N6V@NVA8Ii1$>@L|u z@(4+#o3?k1%4dG2h+AwA%N;_DVV`Jm2Olfz^ za%^v$l`8FgSx%cU&dQZ`#Vn_-7-uD`uB>T8##z~_!!2#gI4fOsxTVb*XXUGQ;Vh^5 z*>Gzmtaj)ur(qgvWvq7ZET_pDYo%PeI;JrjYvo+JI;NQ$Yb9N}I;H~{Yh_(JMbI^j zwbCw~BCOLefmnGfQ^Z~h*um5Q1rh;BG9Z}&$uda6K#C7~!!B3DbUT|kEU|P-p;H>; z4KD6EWI0{d7%N=58m2=VW0jJwhUxCcSY@WGVFm+Z%n0Q`nB@!=#+dQS;WEn^NQ|-a zs7}hIQO|5;x_g?s#KSmm+pizJ{r~5$U;eAA>R8EflH(;Wmb^srQpw9C#l~%W$IIn> zh2)izS4mzid5z??lGjQ4i$(TBZRk4Z8@lfD!(i_6!(i^3Inz9KX`^zIK)S&G@pQtZl$|EV%t1%}8raY2DZ5#9Uz?4T)utC_(4orC@1N00WM~q`6y=Ew z4aJzZ>5FQoygHrcV@y$=7=}h=Oi`Z5(A116$`ctHpfOgSCHwaHv2TBpaOu81F|ltS zxN_hAVEK_g;ZC-2ao;{`fg{(13taWK7|KexcUZXUZ86jk;R08^Erxm}+&e8?^|lzS zLAbz`x5e;&fxHv$6vCx%{~^gB0Rx%b76XYVAvapc*coBAx2b2?RNh~%ZGi#Gp|F|>e+o=x)U*xI>u7R zcC?V1@7T$P3@&_5|PKv72<~rn75NR=!m7 zLCJ?CAC_Du`H1ABlFKDmNXng^&aRKi{c*`BBv(p4DfyJ-(~_$sS4%!4DRzE3yRMb< zI?45t8zeVMJ}bFNaazt+=+PuHpo9 zh^EqJwXN5tLh&;ucj}AmTC`y81xD&?fhyXwHV`9qN1%$& zQ5(e;8?D2rqBaVOMq^Y_8wEvMGODPJf})8TRn$g7(ejKcYNMcNkVX}?QBbr~ql(%n zD4MTPMQs$6wQ7oNwUKTeUZX%=Y#G9U1O|y8Bnu$91StqeSwX4;q{cw2)Uwy=n3o9K zU<_#&eLKtPJjPgt%Mn2T2p<_MWjRjhJXU0^YRb_>C$1u6^;wQNI#U%HGXhJiW0X<- z<#cJwfmyB`zjQ7tGG^{_l*@940}Eqqgq`qXEHa&Kij37kWhZ>u)TDl$=g7SMVLT-e zTPC)mg7P2lw57*YyJ-Ys14KYjyMM30Y&8n6J1NDz3STYr5i^thlBU7xghccjgLGt*_X5XEh~N5PXWcqf zYAaT+!rj@kFf(W%dXsX(FLCjxmj`0L1r7} zMt)RA?}|o4#kUWm&f9!tNiohf_%Q0Sg6imNJQ0cym8QM*=tIxB$h&`MSEed$k<=uu zk~YaQNxP&&(kbbZv|e%9<(s@`<}Kaw>6Pff_X_Wg?Hzsc=$8ygmP=MhR!Vk|>?q;9 z+~(NwJ66eOC&?Pg&XQduyGnMGtd-RIm#_C0o41V0V_ecwG}7*#3ArC7*;Ddp$zGDZ zCF>>oNFF2ESMpfN<0LJcFZcG--m#zD2S^?-IZ(1e@&w62k_Ixt;2Pgo{zX%hT+@dF z*`LhSS>Ld7L(w}2R;^l9%N}QZJIwm!Hni=$w)F4Cf8B=Nl2FDzVDWWKPBzYKY(D>D z4BbCQus~RJ-pA|aACl>tlKxSLUwPCqn_hTKXpJj&d)(t6+0B;k?G>S8P7V291hJh^lL` zsEf)G&O#Mv%yD9ZTZ6NLWAPW&rUZkNmET!J=IxHb#jwsY=4W$V+$&={O>sH zgyrbe*EXI`ihRTrqfRvB@cM0atUXk7RIjLca_e-gK<#t?6}wmqtsjs^<++}jnQKhH zATB35+Zz9a9Q`lLQF!gsH7k`lQ#nWd#qZAQ*ec%_TzSsriC<@ZVrawgl)6glIVjJe zC7vDAvle<&syO7K2U5=w51o2;%q#TdWSH2L<>!;-7bRJ?O5APrPOEpBu#tLjwDAIT z_=v5v3$r#B8@}$?aV%8{mD4#gs`?uo?6>)8$9+=|J?5lihsFy@g^$=vTAz0G z!RKzK+E!WfWvIjS%Jp&RzQJ_=rkCQn5ZHR#;D)$Z>RHx!DLSt;o%>9uK2hzn!Vh=#GJu4#n)4 z!8ntRD_y~&58;DC%as>EsT$u&)Tdk2*R&9I-`45SXB#t$AgJ{=HloHy%t7De+)}mn zof@a1#z*Xr1NEUWF3p^L!p8N}r<}EtbZd`FHN#-pJEFQRv_6R;LZx@iZ=Gwzb%k=w zd6~w$Ee%(oDbkmSx@S$}Y!vvYWnrtmb7EKxarF)Z)^@trr5fH;X*<^Sh+}lmR3n*0 z<`y-IO~<4j@wikiMAWl&AyiAuaCb#1u6kt z!j)E{kekl2A!T@PUpGl(uG9$C*+Ud+Wg2zQ-Sib|Gx&$WZ+=n)SxlJjF=}bI)znks z-7_ECgSV%F9U7k^H9l(DrZr zN_@oJ+l0+PY?Hyjs>YpY@Da0b8Z;u)=&WdXGaFCM*1206hii;hGBSURMbL?92g%79lc_|f!!MSk}e-H z-R|+Sonevw-J9r)R(0wXon)O9dr@z@8LPpsZO6&Omson-_;cC*$7Pcc4-pyjCQrFZo?qbr9sX!n)r4O z$Bd?)>+mF_iD%z*C8G(`Jyd2i@$OWss$|qgpfsbsb)VVo`Eq%ZSItwN*TlDTFy=M& zoQQc%Jp1N-L=Tot8CKF|btjCqonrp&Y5asfz(*WRRxsbFtM9hq)Qx+edgj3Vnc)ez zV`ZuvhJ@b1xMmsJu(wU0oqdh_h>?#NWADgPt>vp4ze0xt~c71NBfA&l+OB+hSPyY-HPIEd9ujPqtnD<4pPtY zn1jT#eVuZk-?=oe^A)ik=WR97#JW2)`bnOTIQQ6iv>{q!^=_#~m|MH+gFJ`W(uiVq zRCIjWAjLwXb;uSGfRK$j)BF1Ayq@JU(A`;K`!MYvf zHLp++y<^_oENh8w&#ZTjErAlEXWplL+Fa^C zfgq}%dZHJ^z9V| zAKPfRm8`V3H%5qNcZ zIu&s8#_8!(&Nyjq@4uc1u%hmoNfBOACbD8=DZQdUp>6Cd_E*|hH}<9C_=uxp-`t{G zelE7NHDitaP~#&$Ef3g$t6_4t4QyJh-}Uh}P*yaPfpWLizDv0CBO3=07auXno@o{* z?>+yb*~>5cIMJ-BD24g2Z^}2ew7cayApI4!kXqk#%zn{u2i7(oPm+ApvM1?NkKB{n zv~Q_xK#h;67CKy!;EFYkgHYik_Q}5aW(gjQ8Xwh|iYgr$ZybUOA2FuoJY_9TvTbKO z?P|7E#y~~YOS#Z2(Wek2A2HG1!7-bGc3HEZ4?6>6rr=s08R=efKJ|aJr>S+RMRv4B z7KViWMNczk?%idpvq61_RRbZRrNqh=dv8P7BW2M~lxz~HKDtiX_T4aLJfV8)X^9e| zUbn5oW_hTO8r3Wp19eg=dQvs5`bae!7(*3fc1tU!cO4G~dwbz8C~Ku}>sHllctxTT zCQN;#nx%vqSU0gGO9@#YYMLc$ZE2PUCYDArS!SzuBF%3?^vzcCn=tjEYJL;S_5hP1 zKs99DD9uiNxSH(`l$jYATbk2^>>W#UnhNo6R_(w0&E**{|JU_r`Nj<0G!2cARy!g&B?f|8m5^hhKjDp+}#`XwzO% z_tAQBn^`m1r=f_u&dm8I1AuWx<{yHwE*Rf;cR3hS|mYr(p zg&d7|j@FEBtI;#XDB&#&BXm@hLSnWqDBoi5dte$*Sg+K_{edZYtJAt6)$^71ls}i1 zoBy)s>13RbTJ~7WxGfI0Z6UH{qMBr`jBR~*!=9*x7<;y|nUWN=e;dUR-@u3uM#WPb z)zZJFaTb~6Bd%bqTFQ5G{i_=9L4}W~(lfg>)xlILq}ZcPjB3^%-9(9HOYF+|m`2YA3DG^gO%`lGsAOTN%tB|9g^4l? ziFc27G>XC|{+(g2SMrHx_uw|k+rU;yez;7&o+Lk3CZBj~)+v)u{5!FXJsBmQeN*YA zY?F(u{SP$kGzWb%t`?f-4rM0#W}OL5G-2vv{$|iSLqhdV_=yb5PC|4oYMu*ee3n)c zrnasb`G)ut-|h)bmL7NF-MP-ZRm+K|buDc!Y`**oJNVKWhUam;Wt$pax%1lOje6r! z6+TNYcx!M4*kAQ_`WWr_yiRzM@HN7X!q*B<7xG&|?{<8T!jk;?;S#sAEaW7>0af6(zmj+Z%d zej1*`(jX_J!7Cik^K`j8g?v3i{+9~(aNON-o#Tk(u;Y*;|1h|yaNvTF`iqD^600j<0llmE)@&U*q^%$JaT&-ti5N zZ*+W<iGu@dU>c9ZzyR+3^&|cR0S&@l?l+j;A@E?)WapGaS!!e7EB{ zj_+|i*YUlM=Q+O5@%@gQ9M5;$?0A9Wg^m|FUhH^@;}*wB$0^5Y#~H`1jbiCB@gN`3^Ev?0BH{(?E$1cfV2mY_5flJ5PN{w1H>L6_5iU5h&@2;0b&mjdw|#j#2z5_0I>&% zJwWUMVh<2|fY<}X9w7Dru?L7fK>-ZW+!aqadz^6MN?Rb>qk&aJuyv@_S&hc6y<4Z*RaijNfjkjMGUM2UP z!mAxW<9LnZwT{<0UhjB=i9FqpF94-@t2PGJO0Y?*N(q&{H^2f93OD}z2hGo|LFK9N9=r;+Zn{pAa(|^Gl-o* z>F6#Lggg2C*}Uok8pjVrLLLgV-6w&LDOM zu``IBLF^1-XAnDs*crsmAa(|^Gl-o*>F6 z#Lggg2C*}Uok8pjVrLLLgV-6w&LDOM|LlmJ?~$AS3}R;xJA>F6#Lggg2C*}Uok8pj zVrLLLgV-6w&LDOMu``IBLF^1-XAnDs*crsmAa(|^Gl-o*>F6#Lggg2C*}Uok8pjVrLLLgV-6w&LDOMu``IBLF^1-XAnDs*crsm zAa(|^Gl-o*>F6#Lggg2C*}Uok8pjVrLLLgV-6w&LDOMu``IBLF^1-XAnDs*crsm zAa(|^Gl-o*>F6#Lggg2C*}Uok8pjVrLLL zgV-6w&LDOM8Mi_DHHf`;6=H7?dxO{;#NHtG2C+AYy+P~^Vs8+8gV-Cy-XQh{u{Vgl zLF^4;ZxDNf*c-&&Aod2aH;BDK>=u`7sOLF@`*R}i~` z*cHUCAa(_@D~Me|>=u`7sOLF@@)PmuX{cOlQyj}-De4e~q<@;nXlJPq9-*L7Np;T^jnaA z3({{v`YlMm1?jgS{T8I(g7jOEehboXLHaF7zXj>HApI7k--7g8kbVo&Z$bJkNWTT? zw;=r%q~C({TabPW(r-cfEl9rw>9-*L7Np;T^jnaA3({{v`YlMm1?jgS`^iTLUn2L@ z9N90y&Hf3yj1vU$7ee}ONd@X{9md4*1s3N%JJ2X?33fqJ~{Xb z;Xk_`h(E}9@*>A$9glN7-tlFQuM)mN`+Khy9?I>+lBZ*aU(_;Qu^CL#3zQg0yj22yVz^#)Qu zAnzSO!hcRkc#!ZQ;X%TKga-)^67F^(;XuNHgaZi&5)LFi@G~m^SA^F%Uh8^S;w0kZ+5)J@m5Fvr-%5z;CP$k?T%k`{F39B9r-sP!hO~84oCi>2miYqzu|bd z<2N0@<;efmpilkWA*6ml>IbBLKQW;lXDJ z?-A0@{^a;)$GWG*>M-gT^-j7>F*JFpM{(E zSs?GTK;CD8yw3u8p9S(h3*6+$`z+q~@E(izKOpaeK;935ye|TIe+2SA2^@7Ca~yY^ zaD1fWqa62ie6-_cjSsw^;(mOPyYNBoy$3ILyu@*fBlpw8a}zx{?a1x&xVc9joOR@G zc--Wd_f_NG&-as#dmO*- z_yfluI^OH}BgY>*{>1S<$Dca>%<<=rzi|Ae0TuyU66D^ z(gjHuBwdhvgQO2Kuzf~I{eRWncewj&LLU5i@xp@z8@S*-?hg|FFOCm7*3=O2Z*yGc z*zVZr*zMTk*z4HmSa;k}NIrN_f~0eRka!Mse1hXajtwF9hzlu@dIkyqPtLQT!cHLe0kIE=K8XJF9bfAB zN+Ionh1JuPuM>qVm{=HrEQs)r3#0eSO*~UV;*ARq77m}2KNIVnj$e1AeK3KdA16{K z!Xv~p5kA$Cn{aU->3Edm(T-1dB;36o4kR2%IFN84;XuNHOuQiZ|D$8O1`ymU8A$93 zsRxxy9VYmjp!LNnIaAtRaxg{hC+4{ddA$6YGP7`J(U2$w85HEGybgD`yl5m)!;yNv zQFZ`@V^+($`})+HvX+;5jKs_&oGqI!ZlLI05tM4g{WB$xGD;{jQ)kPW^QXpNgSZ%}yRW2Ps*_Yz-Q@o)1z13|ZwyEM@y4>t=xA>=J8 zNGAvB%dEcM?)(VHVW!r$-QJmhU03YfO*F?Kg?pMMYWOCoj8gpC!n@ zDiKB!kP+fgMfP?_MgrW71Rx{8YU$Ar6lZxAS(f+9tCI|0q%T}VPu#}}i5n#DCwtr= zaf8GS5;x&I?($-@EFVx*9cw(!<2+7~IG^Hig2V|DCrF%x^Ek`v(XxCwaqjGK9`A92 z#Ce#<2@)qroFH)$&f_dES zT+4P9M?JnoNIinY^?HwsQR^JJ(epUUi`}w(2jbYx<9MmZ0TKu4)3}J^Jwo(6j`BLV zEZ>nbtrbT;UM3_TAaP*tw+boK$wJ~fSBSpF6)%%pt-u=LRtff# ziUREkg~yc&^@;+G1%>@eg>ds>k33aL-2(gFA`UF7K_pioW_d3pi&H1Vb&h!mnF(51 z>Ap-~XoIg1(gt56{Fwabgo-h_?~$M9QO#cJfj(X;CAUCkc}+@fA9N+`^cH!5Cpogl z{zMr#xieC~o~Autp&ErBX^gNn${ca3z?yLUd`H*|Fv4yyT=}+(%KMliBcio43uF}qvSb2T27xSX+EgDO5KE6!j(2q(GSxpvYK&wfC#!4>Am9t??eVWnFvk zt)Te?@uSXDP1ef21Qv7G`t{I{lCM=0kKL$YXAPpd5mmRDpxM*E&pza#g&~$+$4~gp z6B$D-T5ps|QDAsQfnWb~1zn$-C@_Sgzz+wyg056e6c{E^xU^KzHLHmNLm>(uEERP1 zYNEh!hr)+S1zpFQC@`dg$)9&|-(qQJ0)0>7{53c9v6QDA67fuCk{1zqKuC@}n> zz^^)*LUO@umhUOXE`LTvSGyM1&1U(dp|11LqKeCBvwSb8>r1M*idH{719d}56&KU$ z*J_|{EUDs}+AQA(id(Qf8^xuyS^gNPn@Xyehm?TQ;9AKlvUFb)~-1inBJmGWMuI9T_QW*gVtdA3Ll?)*t_PYmqFaSg3X>sI4z~ zNRiUJy+N{)g6}T*`IKiN1>aNh3n|Y!3ck1G=Te?!6ntOFPp3SqDENBGPo_MJDER)8 zpGtYwQ1AlD7h5xL1HadId&x$&~cOAy%Y+3j}o970d z=R}=9xDI1>wk-TF;@_i_<$ouz+4DQ3(VhG+u8k%GjYH*aAIxzz#v?YK7_WH4$H>B) zwIt+L%Lh@0BWQ&WC$9u@D2-#V=?qgZK@f5=GLAW;bW4M^|ixiIOaFrwmvs5*%1y;5ZvaK7Uuj`NO}3DNt6kRe@xwwA__(`Se~`d6!mP9SzhaBO-e5z`K8U}Qa6IG@|N9*;a-4Bo zbo{6g{ZG0(wv+4S&N_>KQ}%S&cx&)cq{9Os>1=Ym*m0}lrH+>iN#|4Uj%|&7|EweZ zpUY)^4fgfyqezD5UXppA5Np7gF+g`r!}C`pb+Nit^< zrgJ8}SW}JrS@N_GYM_e}vA<6E0~HQ@f+PFJxEsPLmGoeDKT$}y!-dqueL`!YmPbp^ zjN09JHlg_-tvYc{N{63`=3`DcXoLoRmJX-{wCIdawii)Myhvc^3 zgSqk(jAn|3Z4_cT+hh5r#{v=yNGu?+uqd-wH1$kg74A^&tv8-a*7&ft$q}VbDG*PK zS2^CKz_>r>$WA%#JA_YEzFG#!~@q)w)67L}% zFG#$9DC3<^<2}LS<=K*WLE;687bISgc%S6)g2emBGTwzWUXEmuUmiP&7bISgctPR? ziT6;C7bM<4mGRD{@p8nAczGfvUXXY};suEpB;F@`ydd%Zxr}!@jh7>1#LL4f@q)w) z5-&)+An`uM;{}QLFJ-*?b%D}u96=*qo@0p@BwmnsLE;68mq~~A021$C%Xp{KcsbHW zygcF(FG#!~@q)w)5-$@D@q)zrw-_&L(Y@DrGi&999MOJKYG0AsM&Vt;2TS#dM4f|l zsB>>4>ZiH7`hxxAovm5R*g0>9`lns}bXU(y_3SwrmtyCW=)!R7ahdM>PTX|rJC|+w@CK%HU3Vleb|U}mxixhr3EHM+!H~e;@aMth<>rE|x#z@>_(@6v~z=;L6)nH5xrTzaej;1&J0US_)3I7sySt z_!BK|qP;{&v~Lx9w5pIIT846>1&J0US}KZYFO-{T@h4i`M7u>uv~Lr7w5qrwTE=jq z1&J0US}K%iFOr*R@h4i`L^~-Y+P4cWTCVuE%a_B8maKh$RmTfu5*B?ga{RI5w}dpS zuL_yszw7RP#hB^7cEzOIMm(k#CVyf;^H^clq5I&r(STw4J|2zw;Be)#(MRH`hX6A5 z5`AZ`ei?qf6YID}&3_9aJZlBDSBNH$_Po`}?UwcC>b4w)A42d*tWF5LT#?xmUDx7l z{LO(6(h^nJ*DHdzctmd#W?c*0=uo$C6vGnhnsuGYO&?C;ImzQW#p0RSMu&Ldh=)-1Dt0ro-UA2s9an4{1~Q!45=^qMH%;)?Gn74?gHO%!i+#dD)#>%zh$CpGwMd6Rru zmGii9g)nQKnJL-ZHD0sg=Z1^G&L->^o#oyOV|%piI>qh&4c&5Y>wa%Qu*C6kQs~hJ z>^54oAGCF+uYSWrjd5&H7e(3fOIiDj z3c&n+ZCq~E4;*i*c#SJwS1OJ+RlL>}uP+rxnkruBiZ_&sLroR0cf}h^#o?xkH@M)l%F%{0@y z#q~Z{>Mb_YyVdnRU+T>_)BBw3eWBD_Xr}jh*SoFMn`@@`1=qX1)SGUmcbn^dvDBMv zrbjQM8GfnMn`)*M@zXGXq?UUf05$T{W(s zw0JUZb&(DFxIy2UHFzzgNogA$CO0^?Vm=>qil6xKQJ|Gs>1L1TRw3gJeUwS_F|5zJ z=9|WgE?X2K-sx?0$R8YKxK5bWms|+{>QE`2e~|*)3RKE~;|j->jypK+=(x&pwU7$n zc$G3bA1mpJB&eMT3dfr;_Gmbw1>OPIHD|h9yd8C^baa^I$p=V2^vgRMn`}AgufJ6L zD6^VHiA-i))3ziiUVym{iJ?OQvYsicrSNX=cyANL^flL_SXo`afRSFD@AcF{J>4lq z>ZwzTV7FtBW3OYMW8Kjf+V!FBM|_t@+~NUhj;)Suj>{Z5Y)S??gc(0y5PsCe^Jep2|3kcy*fvYu(PR;ajWFKipN$Tr$!H|yCt zO*^PoGjV^{OS5esHE) zgaQFyehUv$kitpo~>4kM4sXHDCF2_UTm3Xc-QQr11uyb>rp zN{m@q*HqI=pz!E0o@rcfS_u>$9mYCMF59mJ3XdX#AwT8Ryb>rpS~gU6O*gFs3Xcxc zgUZ*u5-2=MVeS}fUI`Q)r7(AF)v7K0kjP<4YoYMy*xb>z(6kaLJUUE_nmM*#2^1bh zX3R{#2-Un2C_Gv=5p_*At%Nu?@{S|x9&26+6rO&?3y`dPym=*1c$A)ul72|AStU?- zba->3S-WW^PLq`|fH!mAyLW_4US$$~xRYet{cm#@FQ%fsh8B+-h4o3bx9rtqF z+i|^+7drb0GyNPASxN@^HYRiS;fQ0@aoll2NczN`>8jJEi;q?Uvw270-5nnx#BxNI zb?H%YNrNKHkT{0K5z{Guy~Z1zt(M@3C&owo>VezD$G8E9E*aMXsHtsYJQOO^)v8Mi zVxilzsY8<*`#$cVQ+JmJ=wrc zCoE3^gk@_ruyYCfMQ7O|4c4ArYHcec)+GPDrp&sBnpXrBfD-R8)!Lg@1QmeJL8dd+ zv?8bgbQS-r6K}5m$0+WQW3^>kJ|R$3~z8h z=Cc=lht&}am;Fe-dwg3Z+A5pRtdfG#$hJzv1W6}2z+xKOR*6;$NnJbIv(eEJVEP&+fU;~QedzlU{(*y<)(Fm z0*WCs>ujC0ZDwprBXLx%fCFRIx>?bGNmAqF4^`?!50$3cGojq2eSiRL$H2 z6AzVBa)>G|B&$zsKY5a+GlYgZ_E2#W7piuAZ(#JHa!L+SrQ7HgWco`^-pkr) u z1G>WT|t=^A7%>m6>Q)^VgN_U)o6!>o{{ zMJ&^t`_DTrI4(L~D%9^&O{c#DwHTW1GU7ea^|m-pIZivyIBpec-)WI}8dLmc)>d!) zl=Wn>6oOc?zNzh|_70D2v*U%17dc++c!^M{O=<0i-Rg;`(qx3WB*8g=w8@znX5jv?Lo?WT(!>7MO)j^leA&vksS zFzcVOIxWwQ#(HJdMhx_7N|5y}G)vLODN;a>5^B4|HlT`wq8~^`DYAefRiFvPwzP_q zp7V(!c|?&q%9c-A9@FEq(}^zSK-cO~KkS9onwN)ipo#snzPas|hjO4t`_RtE_RB*# zP^1BA2HJjkCrn zCN;V3mz^@B$k3$;eEVgm%qZH});ri_$h1zuP>Gt2to?HjQEZBfCKE%peDNWRO>xm> z^3YJX-C|Q*^q5@KGPhrBii;w%j}{K5*tAPhTol9fRNr2)DK29%b8OZ>{Sd{bxM(s9 zXUpdwve*7lgO>t2SYk_rk&cOe< z&X*RJFvVpBay9Ykx5&0X2vJ-#uR(M9!b29D;-Y&kx_z_TEjGnPkH-SF-R&2f;-YxH zDUNNw*c2DV8&K4792--0hU`EeczKezNgNa5EvBO%1ZCVUb!;CGj>(8iFF44icoAOHp|T& zo|`)@H`7aXEH`kZ*5avhtQ0qQc!A3t+l5-lTI2OIT>pZXLcT{IcPScH7~dkP-iht0 z-7Ok>2et8LYOH&pN&LIS)-ylF^MCl4o|qI znc6eO+#@xz_5;%F<>xcEiH)p5Q_vrq8o#c%jT*7t>#>kyrj(-u7*_dgJjhiM2(&Rz9m|m7} z9B$Zddx`Z&HUG?&et}ZY;fhdR?P(e`f^PO{Ai`nhN=j_aU=j``fc7EHP-x-aRni{QtzT`(LjiXF0HSi@r zQibudQfuH#ex%YEOf32Th#Bq(jfB$V<8!TncX^gd(L^(v^}WlpREjl9xRC13v0itV zJWHiWM21QO@A52_;uJp;*7YvW(u5dR>1p6yo}~)QOfeBz-@80ZrFg8onfl)4St>s!YO?p94S*7q*Y zQcckNk&IH`yF5!3o++*LHSjLaQfZX{e$cM#U7n@U3Idbeo~`4XHK?VgG?R+-UXWBl z+z$LK;AR6m2Sjs$@y|Tnc`#&})9F5H(s>}cAH)v;{~&Plfn5Nihk)@5I@%9}C0gk8 zFg58ykSqf6V&Inm_Xx0$g6J_|{D&V5y;qUF$k?T-UKXl5=61awsX8;|<+6L0?AlU)poxtw`Za1)Rg6J(^-1zA;_UQ%Z zW-r^c3ncqNd;s{jf$IkL9T2?>j6FCsBfoGan)Z=uIGn?3J`$RXw9ZyD?qkZWpMaK6 zLGx!|?B`(2QBXMsnvR3=7a;o*lum&3BuGwy_%!fmfIAE9S0FkEh)UhxXzPssnyvd5 z*zZ7eUe&fQpHR(cy60}K{;DH1?yiX=uggW2F$+0_W{%;4`hTzfmGEV&+FRA73C&!Z zi?n1vfYOg3y#$iWApQyXE5Q8>>@Oht6_5#CD>9+E>pe3TBd$Dol6e7Jo}8$>&}Qsa z^}eRwS#yy~KP@=G;BRXCJ+w_xQW$ymBW-`E?Yi1L4-e$K<6WCZB`t^Dw3%@?P__OE zT5f{oTVU*8V9ej3@(*ab4a(e)CW}DHg4BV;gE$600WJl$1fmQW&k&!#HBY?zT7NN} z+h%-+)C;9vB=zE;?j4?<<}xmoV3`EVC0HRrc_3V*{_2tL;2qhMlC6_$y<|@X*`OX} zsg9OCE7?ZLHc7TwGFH|Y$jvbm?rVLA@`5fvPj6Asb?P53(8&+>4E`rOR4WRS^$izv RsDlGV3%k}|b<&15_b<8_WT*fD literal 0 HcmV?d00001 diff --git a/CPLD/LCMXO640C/impl1/.vdbs/RAM2GS_tech.vdb b/CPLD/LCMXO640C/impl1/.vdbs/RAM2GS_tech.vdb new file mode 100644 index 0000000000000000000000000000000000000000..f29938d5dfd514646ce1ea07f0978e6a1e082650 GIT binary patch literal 72003 zcmdUY2b>(mvHr}4%XfRH6G#Y!**gIj2$BF3#K9hLSkf8EWU#Rxk0^w*$xcEUP_Qfn zCxMV|_jJBM5R$+`#?QuJqI1AFfS>)G6VBn;SpV;@h|YOGx`v?SZO zV)dljLmQp?to>Uv)SGDOT+lgZOE!D@;G56f(s}x&-Ivbq+LG&CGq7dOyi3mP?3%M> z)~xw+w|uf^Mo)HVc-teJdhXq_@!st{TU2qjoObn{3%c&uGJnCm*=Jro>ynLIW?$2F z*~Z!Pwr%<3#^ZbEUV3KNmeD6HU$Zi|>ekiEk9AyK?SJjT50zfBrnjc|)~1yUv$czt zueqgGKQ9`%J-6gmztW4P(u-HDUR8VO;)*)gjmIlj+`4e!*3}D_?0C z&+MF+nLBs(tVKGLF>_|m>*}68Co_BQ)pIU6Gc)gs`L5@tR?MeIEnTZOKhSp;U4 z;~VNH%ou<4#Crt&sZ|t z>r~B$QWkWb*>&0WilN<)-n+JE$2QlA^?p`uwCyH0$@@l!N^32a8hmBJ%AZe0EJ zqetSRux{qVASh8D5QAM;Cse3O<4#nn}vcE`zE6ogqa6_Tkpo)!C zl*1~fT3IEy&J(!fHX(Em!0m7XVmSkEX3WFwFkB2T4|B$)v7O|-dLZl>}pHd$59Ye z_NllmWgpKN1>S*+_)c7wvQI!P?%{S4E`}%LB7Fu|pmg^{#%L6$;G&W;xNOB!x#U3{ z^KxQ=;;BHwXcVe^VZ}2~8WVXtu|V-OCc>CbmD?!ZiIHap7mY%2@szh3&-}$`5d;z` z8OA+>bY}u4CL@SqCKI*}Z88J7?pz5bQ|Z)>)@0arL+xC91nnQR$!H_d9znJGm^K+r zsXc;@X_L|E`a`~Bt8GrTmN~I~i8)=22g{t^${5Y)0$d)h3vpTIbQWT954Ur1F+5L) z7a_FF>1@VmPUqud_%>Ym=0qM;J@c~7DUB%k(qx$4_9HYI!l-$bE-)ur1!3f=>J^w1 zd9p4v{kP+CY;z)#6<~%^(7>FW7;_|$hObgK8Cz3UN+63PS;o@_>7E0a7@{DG8DiMx zv?0!!lkG0S5MMXnr46d&u4!c7#Sxtt+x2*`jO|?pex1Pm4(i>A#;K_Hl~L--ibp8Rnzz}RRr%!fQx zxdLM&Pr_&wlFl|ZS}B1|HVWr)RT9HgVNZo|d6q6?2~NJC|-G6WqQl}-LMLZ-Jp5|vFD)2T8BMnVH(KGe0s z1x7+UAdEQ4FEA2!IbdQ3f+%JOVU=q;=R@*>fS@Rhugil@*6y1)VE3#=#u&(jJPeh@^wiV zajI-am+mHjT&5LxF_na+?`G(xN}r$59FUXa(ne7@xre53v32WT52o9U6B)(?y~rGO z|Bsoqqlg>;=|N8907$1Bam@S>WGAlUF_EM{LE28a(pBuj<>7i1m*rY^Am$SPDS`Xu zwv$vIZjaz%xEoi#*%3$8skDLF(G?Iz9P_o!jyS^TLR49e*{R7G%g6G38kZ9bTu2&G zmVrD47q}2LZXu8cB}}b;=3&6ZzX+n3G3P?opiKlzIK3s9NOJVE=Hv+eMVmpSiD)y> zCZb~YJo#Bx*2C?~xGZn;9Ad7A+gET|>VF*4l4xPp#fwH(rt*N+7kRvGCjUWE&{ zRKkc;WiTT`_lE$9=mlO(^yrr@DVuf!XbJ5m?v#yI^jM*b?3Z=h2(=rI<&3a@%L-9I zf5v4A`xU}H-2RBm687&9lQ!@tft$9WgiTuVQn*0av{k|=P?e7nw)+QwM4$pMCQ!)J zlAUkM1D2G*3u^|}wuGzustTuOv;yUDrAruU>x~@nYVk%6cy+oGChKD)pBhUouL2@H zS0$=ospVgcdAtG6uuSm&Kxq$AgvT|$T<}Is7*%NXB?KO*D9wa`QGH3l85Jqjk{@v@ zooNrMlOc?%Rq4Vmj4<|UsvgFLDV{7lc~&4Sn2xjHWU7$<>W<2hKz3`wHSSNxT^Dfa z)&x<^nsQm&aI`gbW{a=R?|*BGYMy5Lr0qv{YibZ3i?k+XKQX=ZQ)o@&D3${tuVy@0 z)-)bbv6hK=AihcPzBL_$s7$dY;lTqQdn*#A5eA;toq(t;_K=Q4XHW29>tY_%_GG~Y z)6BaAqyQ(z(Pv4BgTB#2^q&T%i(pDJlR&+44j834gQx=-4VumNz4fA zLRNvM`%XMq;=YJ*51@Al+=y9;kuZu;r7BwQsBkJfr?u-*W&2IuLR4CLl~pn z-ydoCseMjpS%_0SBb>{P5Uv&>_%rk?419sW!@?mg?eiMJ8R00wk)F1xaK^v5^8uE{ z8-W)STv$d%aNQ*>#qUSgtsAixT-bGMT#4(dA7Itl+&?Vh@i^KO%^t`VXmE>%YIdzm)aV*ytNh;77Dp^)y4d zZM&(gU=^sx)p)S{$gPA^Ppbs(>+v>3W0WD`l$T0p^ryD2h@-p|&TlR&0TyuyyqLJc zlF{NC!mk8B^SZj-^{j%2s%^xBC9XROr)#}i;6_}^>_|&jt#C$E?gplz+ZA{*afEAb ztf#-T6zhqPe!(ShyLt$qttad~3Wor_tPpK!K!o7?ge>8-rB4dn2*=G4PQmmG+!stA zqB8I&oVKRY89P#wHR5Q0Dz9+2PkP#)!WkdnZUtEEPvFG_-XD^!7I+qeffDR*pWJm= z;NgBw2MLbYaqzkmFyccmyt8jrv*)bBvbc(OhsQWy?B4B|R6L46TTEN}C-KFgV zjC!B3w0!{Gv~)w$jW9GWvUeR{U}Y)%AK<|f{X@J7AvuMPecJaEMDN5O|x%(UeFJHZ7iP6NhtRKLOnDyBCij5wApe}GFE zO+(cu@RVu5SVnqZDNEofRZmMGnMy_D)~XhBB#=fWT&-2D-vBOFC5U2H6*eGkRsE%% zu-uPUrF+-VoYJhBYX7TUz`j^j92@UqRVnVk2fI)SM8#8AlqKKF2xNh!;`vraAafM1mX(zQE>waA~kXL{S7XlsN~yDDASo(LmPRj;r;v8?1NWy!ZE0?AYo z2KMBp0T+`IL@|>ITZfyu5!^~Xa1);~onk{?PW*sz4f2Sb#*$`tO-Rm`3;T}ZKd zsKh&1m%u77BAgn0r@(z{d>i4kG6gqQs7BW0!8HFNX#xwBHFdz4PT`CNx)+ll@d7WV z)@(?2TA-b!9mU+I#h-A`rF*B4v#|Gnu40AQEZ!qR@E3pP6VB%UZh`v(y&6$z-tWQ# zjZfi?VBG~w$JRo;y#UOnOBfrAN@IkoMj(VSohpZE*6uar$Fu@3Ch)LqwZMl$dvag{ zKM-*wWSDrnqZZL{9Ms(UE$hw)(9`i+FsZWjvNSItd^{v!hSRdTa|e^lUs zozp9lH+kJ6xIiVukq>bn6P!_rYCGh`_Mvcrr)Aq9j5t-kz|#^(7;%zc;A!0t0WJ+o z5XJNyR;lq+y(OJN+>hI=TC=)gg%|l$%x-3@SUnH*{sbN@U9L9pbprQwxrT7c=?;M# zT`Jj=2lcXEaAAFt4{<78pij!4F!EICj6U790E_4aUQG1akd(FPPs6W-_0|2jzOOu- zy{&pLt3WT-hX+f%n+f*-$_d|BDfNMA9UF0BWr$*7hwzAq((fpS5tR<%Av{n84-4Li+P#l>5AX-^z;L_Z zeR1DUJgst@#_te(*s7V9R!y4xDKBAEBlEYXC{!U~?4(qg120AI#&WQ{J0)Gk z@6K%4y>`Qno~mp=w)h8zv%|gCCj*i*CmugxN>qObmN?~*zj#9hVgHZ7eRcgeqB8L$ zoK8Wd3#*NJP;Ebvw1L{_Oqh;MTcr!s#vK*Hs2Y{dsLlN$z@i#~7gvp~1+ALyzV1@? zir=8otL`BpkDw}?eMs;XR^5Y0{)7ihZND?{KMUMf+wTqhF9P?~_6Nf0ZvQIqu)4^b zs{Xs+0(G&Kkw0;N6I`G!;+O|lKK`39rHf!)hJY3SHO=NW%uL@(f!6(-Eig4O;>8q!rW&&%g?3A6jl)?m~1Gf@z82|{PsELHE!FcI@+jWC~w2ACTFC89MMon;RFFlFX zqvt#X50>I58~9X#`--1p;LQT}74H%5fkl(R!-^)1URI?E6wS_&Fyd4`fue~cj5t*` zqi8n`uy|*I7gI?#Bz@CrPwOsa;`6%AIki959jA)fbIzk!J=*tic(7D5jc^a3V+8K2 zWV(SLD{!L{HCZApdA&(+VYQH+ZAIY%wXoA9j5t*WqZapQfW=`7yqM^_LsB-a0Sb9z z$1J034H;ICtzi}(EYWuw_?rdpi~dx?J&<+@+=$*ijc{7-83GTBowUqD;R3PK;t69q zm5&j-8e$SgoGP2&8cqjTT7$rgsU#bczG)4meJLe5`nSwWJN==1tx#()UrJHEmhG<2 zW@Xt=y&Vshg3ck_1L#75`wBW2(HP+u;DO;qf;Wm%ZG<@XHHv3gS>(s|^EOErD2sg! zd9jTsT%atrAHvw3D4xEu&Ied}6M+{~R(D7*T3L80p_H>w`{cTGi-{a?gk6_XkL|jy zVD+e;cjLiQ&y|SExwi#)pg7+pcwbFd5l`DD-a~ke-~%L6 z6@*b0DxFc2do{qK3V|0>MOf;-E1T6{f-BpPbLZD~W#M*Xzde0DD@(sVhHqoN6; zqE%T<+fh!C`B0e(XU2E#%>aus1zt><*{rQMt;~M>N>C;?mq+_f1;1mc-au9A<6&R( z-o$MzGzGK<50+AHC!9i6a9CLg4Vn_EV%WE%9`fgc%WeK6}&INJBcTJBOW}2_Xys%>br<1d;=cnPBsZXY}Le3 zIpmRV)r2t}^S7;u-eIkdF&Ki(8ExDq^F7$Khwh~hea51DqWy7UDOHZbq&&iguFt{IApLEOC$_pex7)?pr`P_Rz^DOpxzV2djNd_4-B6Xd|1WAvGtON-Llzw31dT3 zd;=A85s@(FsmdIvn5MyesA5%Kqhe(mgpsGD3tG1OB;e9`1yM}@vqGxY`k&K1rBVORe1R9o|7HD^ONec%1u|b8sp^imPk+kS_gHkcOLH&ePr?_4barxVS zKPB7){FegvMgKDc|CPXv=-rLMTFej~V`;V>O}QC$ib zG#sjmFya)?py3cl7;#c3tKs|taM80Mis?D5(m>C1O6c|ePwM#}thxu8I0;zOd( zBtJ{fdss*sf*@W)&z4F@bx1D}c}Q;)zQ3B91yhg_H&GF+>R=v=1%Fy0uM}2 zmt%qNL%Q&0bmUG2*&}auN|Mjf=0Ww;fUz%weaSuVdv@z|Gn$QG3C(DqCR57M*^?;` zwjzdp2p+5kkS3f)q~Lx7m`XTpNZ`e6C|n=ElPzhBZ$GZ<`GByk`!i5clFyd6% zjDffp0xU)#@Zv^bOW(~b1hW!5D0~4u8ytCBhlI!!upa+uqj~D}>3V&-UZ1Yl(8VW@ zRj-V=PBL}$@sm^pAA<0#NG!Wc*z#i!=81p=l8l`^*8fWsB(kHGsSfYxhVchZ9-E9! zAAd}&(hJA!WBiHSqdh&^oArk_Yb58W6Jh&t78hln_AKsNDwoFcAv{8B{vvL&Ykb={i)mLKtzvGZ^bDB!NUqVXS4&<$#Mx z2%?xtgthORL~m&$hS%xM_wdACt6iVpQ89Z+cQ-5RK?+;&V5$8c1Md~Mul7v_o)x%J zyHW*tP)&V;3#*=dh|38sta|dICKN7EJ=-N=#3`Oe_3mbXMM(lLt|VI@{;;m3mzn;* z_0tcqdLF910}qy39weM%d|2SVTDBSZPJtV>xDOFd@hNy%CFD(Bk4Tz8B@{d9nNH;s zRtaImsdT}8fxdxK-ksd1ZD`##^fq*O@)K@1YHn(8Lw}Cd z<0|qqc(7FRIHEBRpfBKo;nRZmRr7g7WwP^>z>R8Di(#7aNTYCpdN`pWj4Qw@zd${7 zh|Gf%YK1fEai0WO7I_6;Oa)Lh5Jo_T@UaV@L<2EMo|++YbOtT0iUgeFsex9Yt*35 z{t-r;%FAyh-vU@vB=BM?%7(OIR22GnG}!;2o{#~i#*Y)kFzp@G*a{ebCES3C?aIT-cDsZC`<)%nWH>GgC zTK>T_bX5W`CXR5;wK#BeU{(p@c-;oidTdm}7Ko-C@$5i62|>^?)#1SsY64N&L9E6D z?XXtxM!0U0cn|OjJW#+jg7*bnX7H7GpmG#GZ2wG4-c^z|Z2wG0J65=`{S!u>EL;AE zW(cG6QuQ(Rug(sz4CEclnhB=~D0pC2 zY}14hr+5WsMI2$osr-#uxl_rHc!3vFa#*Iu9}L>By?{-$ps_5o_Xno*D9<`DHI0S# zkk_$zu!MOG;p|@oUaT@G_F&-0_S#~7JB|4tZ76va5}#^Ndor>LiM{$#`kDPWl-6P` zvX5Zf@5x5wr-em+3gNWtE`j^@n=$mK3*6YR>YK=eY0eN_V8c`$>1n5mU)Y8TBTl9B zZTM7x#fAl5OzmMQYa5l=B>;RoE9`v6g=9w?8l89J!sHvB0Sj8 zGabDwqhj{yvr8ym4k)h1gQdd%L{tV0SKxv8`GWUVc`2eY;J!-WMwRYmh{`v`uEYa7 zZ{pd(tMo>#szs4E2Na~upYagJbgEpY)u=%;d9v?UJc9u>k24WQoJwZ~6z=5!%dkM; z#mp$1we_c48x|7!OHk@QbwrocD;e$ByeA0 zHxN!mDR`hD&Rhs1PVoxd8gYaXr}8%na&II*;sst@(6&t7%=?k3#7z|Zhju-vkyEk% zJjZ`%yP1!a&b27Bu?L^%xbolgnHMX-Gn1;~{WRR1L~i|^+yAv^&z_2!iVFA=r~IU; z$F5#dKasGyG0k{OjIefr-3|dsv^5-U3rAbR(dKY89ga4Iqh2_g3P-(TPna~LK^3hD zFSoI1DS_RoidOcSzQ^WuZ4`=z2@^)YYGK zQXFDWLI;gAo?rnPX|W^Cb|h^_n(T;YM^Zr~v8!i?NVK-$$RjC@#69=+h`m>H00ok(^RGE4>F!5WX&O&CMRbGG07hZdHfA!YzT5=0e&enH)kzd@g4*VzD(W()62%*8Q=XXD zwRV$k{*_g?L8L2jt-`e$*BV?O$F&yMCvdI9bqB7*&TTt-bjx&O>jAk7SA6x7M%^0A zD|!Ifi0f`#_u$%u>t0-&ac#ksSa9_v8%-ms=mjK)s}I*!T>ZE{iE9AYAg*}*m>Jq) z-Pm>jcH)ZpMp|9-Fyf!WwF}pyxOU_EG_J>ReFoQm;rcAD&*6F;S8U@BZ9nA|pGW*j zTwlQT6t1UnJ%j66T+iXkoZ>=SG2IC+0|ZvrmiC&K+{)+00;pJU_1w%*X1Gh5Uu}ke znJc$=tY+RNT?=N-ySh6Anp6V6#_Bx{)qBQN@2Rg&<(8~o(y?-3cHx>_@A8g4-1Y81 zW65yu2f;Szss!ZJsZ7+pw~GY{b8i;rPI64Ov!@=1`Iyrf9Tv$EqYLEtA9jukKwY+L?T&mzWvV^h(Ue7NFTi-fq@yquxqe~RQ;;OBnKcw(nl-ZmOvNCW_4X?F z4b@yqxm-!PIL8O7DNilws2^M<9u!1Zljz2LqK4*l$C?${4yw`XXic{*5j#$1){%S? z8bF?`%a$%(yX=-_1?DU30TA+0fshTzDa&?cHtyJ|Ie&sf>^3+hC znwsvIF{U9Oo@z}scPw6!%Pm>CXkdC{z2@$r$eFWPZntJ`=QWuHUGus!v**usQ;>R;!z8vWVs4&>ZSIC8(>c?EvId3~n9Bn63h1=Ra0wKF-?am&a;F6~jox z9ti(*>EzLQ69Sdi<+4MWxwCi8y`<;zOBA)O@iEFl4E1K#XEtxRW5cF?=|pPEGW_?G z4F9(yPn%PeS3*_Ubd>9W??8M6FC`0=sAnvwx&b-kXhcnrs&7$E9bRke5>_hgt}2$U zy=CRnb;}CPNY>23|1Vr+Pf&Rk2IOd0+t>9QWFBTX7FG$4OP6k3cFW41Wh=ot!bWjU zEla)qC}3_ts_@Oy4$^XO>S$_%2RuK=}eqLrzd-z$lGSaW$gL|U0jRAiHQv8k1T3RCck0F1U zg|do~^1#bqsKX*V4+T<2hptfd@5#)$Y)KmnTT;EUz;&>~o@J5NCugaU%Ljv849KbL z#~5PHoX$+PcQ~`_Zi*=}Hk;|)-Lv7Y&FeE~c3#$b>4N!lGmB!|HjnL%hSz6zuMg2y zbavvOc93Iz??{*{P!@CS&QR-PcP1JfyF=c=nL9+Bih-`ord@YucG36N)@K&e*YOs2 ztC!!ls$*sEZ5^xodR@scnRS!sj&R@zFX8@v7q0U1K{A>8f0Za&g8*?%%!t0)AAYa%H)QJGFfyknZAsk zls8Pt%w&t;Ew67Who_1j`0=#{WH}|sQr-+;?NVv4wFA@d#S7QK5w2>K!TJOcVm+o^ zw2BE;lvb@?vSKT{U`)ULZDaU@tDHdJBc2jMYfp#??y} z-hN9*UpBk&mW~y@1Ipg5uDw#(dpc@(+@Qv-%EgW_cJ0Ql1_blJnE&ej5Ib`May09v zDAsUCv@tZGMeERp))w}(^5Paa|2V{1CIn7hZ|2Q#MyhMbb^WoRzpYVrrFz;3o5FjO zVEwItwY&~U1($nEIyx|`li{4@7slqSER8{X1^wS%&nWbeFI9BNw|BF%F@3#OGs$k< z8Z|@PtJa_k-O}WFOUeplaTvR24nEXG&rzc`H31|H0~Aa&Bl>K4*%iw8Y@i zS&XnWf-j9Auj_)mLz%7FoLc-UtDiP4 zPqzms-RhMu)$k*Hy?p%&nmsGftN}S=2P0IrKRbJw0ICU^*U=&~+L5{x_<<4E2}fRS z;TqS{)eFb`6C)IR?ap%BGB7U471E>RtgaJosIXnghu$DPEW(@NmjOAcsX>o}^+0Lv z^+#nsLHEO3p1$^Nf;f4ww^vP61~5-NEi*Kb*=(-_6;!YW+*td$IOjKuW$xe4W(X!(wBf)TDkO$txQj?gy8P(ioX7$kK=!-$g9^$!CF~p5Mj-i{!_jX^~^M z=4CUa_XG}}Qqa3j&=VhR5t#Ps2~gB};1JHRA%pJ+d1f`pEH+|Yte|OOuqtzSJy;!S z4$n`GgZVQyb8Y^~mZ^Gp?K}ZA&T^@)t?!NMYV=UNH)24`;iVp!1;fi=iW)T*ln?f! zs)IpQ4M@q6K9~(XJejC~7^CN=^1l*bxG7+0K+c$~y(j@8@3*!pqw#b{DsbyqzaD84 zq{dPstcmhpLQwpbLGiJQDIh16@;a6+UMQ=)>@^C_Yu`Ewc<+D1mBf@6NToSaDqM`# zy)~x{(SnCHNSnJp5WE4ICWck4H)iyhYO<@8j!^WzPkOc67<{AZWEKaa7f}w>Lk_jP zsXTAg%2Owgi=ug48EDCXjF!-AzCl{@g8ff3h$|nTIhKPs-tq=@7Fy3hws)m^OGxLJ0~B71ia9eVT-PyR>{l0GgFz5zKEyLVx8WXG;Mn3;17 zDDe6E=0MCw`SpinehQS_@|3^#6Zb|narZYpaQ1`eLi75=z2~ntRa7o5QNE^~y*hev z_)fKHsk?ZYH(Kk5k?V!>hoX?{#6YeFWEyPljj|x>jN3>5W+UYTS^`ruJC;$M|30^9 zF@+}CUu*Uv+tyyqV>m%E!xs9Y!iCViVyjOqY#mbTIp*9%^>LXsY=pe!HNqp59dq5# zH)K5fb{rbI7Eb8p@04N6vA~oK2usL89h*_d(+m8q9vfquAT%_V!pQlF!VKkK!ja+6 z(V6%M8t?~c06Eny+zgpGeL~0dvBx8`yu~$Zy;A#Wti-)Bemb;s-`;|97P>1gKv}Dc z&_Sg0=;nV_qqg4)1Ykgp7%NVXwO}RF^XlcO(t$^3E~D;w%hNsPc69w5UtnWcCjBzK zLvK*92Q@rvScLpkkgWlkjkDIMS{)Xuls^+Pn=HoE3KgB@7v)jUZ9#?xWFJ&$?r2U& z?$~kkq&DpIq6Rj;qbk#E)N)6_6A%G8vMM={ z8M0SM`uifL#W-mJZD{R`RQT?G8Tu^`GV0eLr@Fb+)=-Vz)Y96Gb<)KwN=FID9G|2O zvorKNM?|!5DO7l0cUJ21{-7=fh+S!W|T&q zAEDpOJLzX-P@6^u_#g9$6OPBu+G`ZN7CmOi*v9E45!Yogn%Af7=A7B{8m#MkK|N>o zf(2b?o_6)F*QT$@nH{Isrme>AaEVG(Qwi*TMU6eGIOrZ>Xx)b&z1wA$v1^c%Y6|91 z(JLl!KC;>#xlWA#ZIoj>7X+*g2rKfXRxQC#)9#YYDROttH-W&u$Oh6IdzLqEo|(h*x8 z*khM9lxabU49F1)U|XtpYu8-`gCjG=2#t=+MzwuVGAh^3Z07*waA1(D0V!vSRUsbm zD;$PQhSi$mRMP9H;eqOaA{Kpf*#W8FKfy{5$P5UJb4~szx9H*=#~;Wc@{lQZ4_K4m z1pIMGK|rb|UI*SGh#EofjRUX3?qo?eQiZkU(g?9aRvICeok}CbYEEf{ScfQ$5Yx@l z2r*(ViLks0E;Qm;QZ)vN9oDAIYajTkMo%@$6fzA6HhxOTLxxJDN+Cn0QKgWf!KhM5 zKQyWo;@(G-LVRLyNcOcwB@JX$3D{6Zm4FRqR0-H{MwNgKXjBQ$h$_qShb4OISZS6MeVR>Y?Wwzy`cIwNZp@_W8pob_hq#Xr@OryY% zTof4ci2#>R)$io+yn=OXsJz{RTl>Q0ts}tOMu4|iaGQU#1-JR9M}Wf}%DY1>r%eyv z770f=qt0RIEwz>sw$x-~Qe;%3UfuY9(5s?Tm5$uei^^DGGjB4bJ6a+}3f9^hmv5q{ z!WjL?a>X-2Mh4`RL+VkrEQi!1;gEVH98!;jL+X)mNIeQ}ou$W{vD5iwio7LdzN^Ar zGjmSEyd0<&tD;7K!)o-mEvSA@gScFdv)OG?XR}i+M72brvaB~bY>SSbUDs%KAb4)b>m5M@DTL;ZUs+eAmH5m-1W>(QkVmP^IuED>nFmy2%mXSR z<^h!m^MFc#c|aw;5U_$Z=R1L445TM8E|PyWABMLbz8=6TS!;O#=9>jTyg%_m9#Gy% ze=!dzucd!C09L8;@C@wt^PuYG^q2FXYNzwR1E`dqZxqYx(?i;ZmEL%WRbEFoV5PYN zu+m)tSZS{Stn^m^RvIh-D;*Yql@<%YN{K<#`@hC{UT`8350Ha0-*=R_1~&dhZ3B+-0N|G z2Jb@4V5PKI@eFn8uj0wcjHZrOu8|b(&0+m*?-u{H$b;?c=9b7k#Y1HYhQ}|}`oB8n zS8yz|V3!7CI9Wqq6ez-goT_0gfhyM$wK!}Ym#A&QYVeBXix#dP|JsYZT2g5)&C>;i z&!p|uE@q87xXp99>Mu#dJh`Q$-gNMH7vx1FYui2glMr*}s2zp{fpiQAi?08c`{1dj zV7|w3U}5Xst8tY+IzMmr84K*A^MyOOZCotmrlC5dL?0o?Nf^cUn;(x_*&E;=Nn>Si zZlDeWa`Z;_;Go{f)}MyK8u8CTotcPb&Ak1e7AXi<5mlSfxvOnWb?!wSbSY>wgR|8B z@tcBj7?9dg^*U1AQ5}DR`u0p+MP?5RQC3)py;*Xs!>RCpzju{+?(*O8+(;@NZZCxv zy?6VF+%EYy6o>AQuxMn40G#RruYCL496KzoU;r>2m=_QhZ^WgT}DY%ex_J z=gw@)j(C=|b3koK@*k}96v2R;3at6cE2j}}L|Tib$!2~lOy)$3Ig2r;LfVVGYKuk5 zg8tro93kp^3Gp_yC#vh8Y+;r%<5F41)Vt_TiupTLatQX`d)MyTE%92p^VMl%wcPcL zo<9_MKTpk^qQ2v$Pu)JcT{5bcyL=|dcnx(Rp(!1?wY%?L9A6`99r?ZH(F(haKDPHv z)*@b@C45gorZSLr{vVUH-f70N*cex zFs#liY5iv2i!q#2o?EfHqjB;s=0 zKEN3thwv(dhiUpl5ii{$F`ljH*C)ATASIuVV9;t`isHj zOe8!J;XiP_1J|>N-v?f=B4qq)I{c~*zoNr0>+nlD{GtxujBp9k{R)>;ehU^K^>UDF zl?at!9%E2=(w>CSLv1G^RB7;;Q~IvFG^9NRG)&uwkbi1E6Zttwd4p71L3Ldntv~io z(6Vl<<14tFvfv|zwT+4>K_Vi{kz}qW{uAQYqcF3{xJ-Q!kem-VSS5-lH8B&D_*z4p z;5P!L5LKxZ3lWb)GuMI-N&k$Ch4~9EC+Uy=Y8n)6-HT|@H-YwEq`3%TFXA6TI1TiN zqq5||wA+x~7{KoY{vg1~^RKwh1AGGDCm{XR2$MSR-yu93@ehE05yBM+KZejr%J&Ib z-p28&46!nuhIx^v!z%TtD%IEfa{U`n%=Ygjk*dh2Dry=OO@g@p#q~VcorkQ*j@iyh;=QqNe2^*k7a5kOzvuZvoQ5RW&rQ2xVj!2gwhRa!W+QoDBy2|2;PMFQ;5$( z{C32@gZK}0ft>Q@!i?xsuF|r+RA)%Wj{(k%Yr*I~Fq($=D~R8N@CKdHod}Ocd==8a z9U&$3HiS-jI+T%!kWP#Y>%j0LEs_~pM9lCrz`qPUMR%Jn`Sm)ZOLV~~0gCQz$dIDD zANWfUI^|8F46DeH-jm^fA!NoWWPG&F@FXyr1UN-?GT;q}e;jfC+Z{8wNN4bXpMe+3 zK&*;xnvCngU;z@)9O=bqUCj8i2+4RQLZ>_xVo*-RDj>+90SqW(R^<+al<9RABNuTp zq@TyfuUn7hel#0bP5qQ9pjV!kMt(i0j#5-@LiJv-HUuVq&{9A^qx(4sS`&U@(F}jqP!gl$@^aj4}@wyhtR3$ z52uWivQty;LC8`(E|h&?%EYz0isb3&(tIA2-E6I+Nl8giPt`lut;C!Mqgz z0_9b9gVp zHPGj`5N3e?1FlJczXfsjL|q7#jaWI>vNq+&;U=V{XC>!Xc>&IxzKHO7gv{Yage=)C zgyhH)ovd>@M!TDbP@<~h;y8>6ya*%>3~VE9I*bNmGr>1ha3`Tm$@Ff(zUS5T!HXel#U&eQ?6evP}GMW zO6u4%8cXWsq(WKEPGPKYcuQ1hw0R0gvK*^12Oeo13LU9Lgv3!hkZKC=`gFqUL9`H;btA)tHT~0-l0R92l+13;Vn8` zsKXl&QZ6%5e}>}`r<~QOU#$#@HPsw`IIPZzB_M2$%4tnh3a!aMOEJw!aF}`#;2dXC z`452PPY83cLXOBu@1Mt*?!+d8jz&PbKN2s~9{dBqH-T`bJMlEaGk`c78B(hx{EJU$ z&S7XyG#?WDl?2iz^@$FRr&$sIXJNphfcZ2&s&*1`>emE65dwDgc?9ff$l<3Xs0zL! zeLCY96kP==v5#R$k3yz2ZpJ%xNMFYId>zuiGEPs;kiLBga=cK-FVG?TlPe%c_GOgw zVuVg&R>n-6rcXy=RS(WcS%Nb+-%@c&KBXU=Qtk3L$cuE3pj zA+_|A{Kpeg^}t&2i;;kpVkI9}Z1ArZc?2vq2|lj~@J|{mhLlx@xQLgtU~8FIQ>3zFjg1sRm}7vL#J;(salz5+bONc^t^KU{#P6p8<};0Fuv z6e97z5j?*AlUF{->Ks=m4aB>O)B;xNt%-7aWg5bOr2(r34knnGk1CIaT=&%f~Q!{6ZJ<})c0`g$k zQd$uWljuQh&cyH5_-`ouU_SoS8vjj&AIisbx<&pkDEvS^{xcf?ZH3R}<2lJ;`WF?x zHy{65jsLE~XY=u{#($6a3i?|AtQnjsTM@f9is^q5HX%HbwFjj-B=Ry%7NdsqAy9U% zr2L2GWt~OS6jy3q|I`%LX(K2l4qi3Du!B92xm5fAG~lTF(n3Ok3T85-^b&@p*Ik}sS(5VXEVU&dRnb}Opn+(F3$7&EJ zv`Cyv|8+`T#%|K{CiHKHq2H-9TFDG5{WmH#{aZ-So6s-A!vxfU`K%&+g(x1cJqmeU zhU@Ke6Y^%nsCSZoT-b*;s>)KCb4bq{>BlU^1KEEN#aaY874VONei_n@MR)0R)TRr;Ep7`Uem{5yiV2;W^-Q8bSwuxYhgEE?If2O=Zpp zL~fL2asd)?iJG=P55)939R6`8`DtVEZhAF}8rKhhD;{F}MjQMd6&vK)@16KM3 z^LZcWSiWI|oRczt)?4S7v*?qoAL&_s@?$y|8{u4RzwDlvAp5-Ke=Jx>L zoQ*PnE|++KJN(nH=@Yct5?ti_JuZ?z2r_QseH|f-$sH1qw_D`oPB6*0fowfY?V|{H z>SQ2qwaCe39MB|x2;oDTjJ|L^;vnZc4W=-Z1?xca?Lbqf5uXCt1f40laYu`0L+;?33dkk%Ljh*1F%lrTQ!&(!kAiO8aPLFF;3s2` zAA|C{(Ck*88|MDaMs{dPL=9m7m5EFR#?4y7K@oNWOX=iR8; zr$IYhQ^J-?TT|0&et#Fg7?suqFc*N>*E@}E>Wu3Oe4)@oMfvsAC; zR-aBFmi*bm$m}dc*gw7p;beqdEk8kr=L64vt{w4TqqNr}egrB!8R5Ao8v8RYdyPTJ zbhjaV1>xBU{{}ewNhj&yOZTgJf(*ad`v9gl;bybAxT>6(9sf;2-md@+2kcxYcsCNT zNKQ>w>Zz6-ZX*O#-$j9L0u@Ef0^{we$eLE1gsi!S@!udk2MK8LA4JHSZ9;f9(ozC+ zcry@Z$vGmxpE^pN98PO7~r$`+(0 zTmyppbV4WD*3|5+K8R@`Y1$u6fObbg+W+2ry{o6 z==1I5a}qM-;D|b;u|YEV8B;^dn1Xg{268m`up#^qiK*8o5sD$;FXyCLSSIyeB&I1H zkC3A~rzRJ{i4KDtu7u_}R)ov6D{~Fdmm(vsRbRs5RBaWz^w+G=U2qtA9B`jU*nn^z z$Y@**h;K!l+prwP{sFw$OwLA}%?O{W!V7%Tcj(uLkUN<%(OIZJ$D&+%W@1|K49&EU ziScKGc{NTjZ4Yp?@~NPu@tHJtNSfjNG@@wIjtA{j(j=Sg`cs+g59u(a&#rF67rG~_ zgKRS1hO=V6H-Ly0rXbEoNMnUfd6r?^2wsN+{3@z+n4p{U(MJLNQ=nUju5K#GDmE3Y zKL8|sFo*7Vp&?%%vERTx>9!6=epSNAE0A-H$R;4Ee=)WZ zxSB)DVeJngRTVxkPv?%8ve=arc9~UNf?W<$hMa1$i{v2>c6lcN&Mq#g@vC*XMu+Tq zn2tRXL-t4zblMU$mBxn2)_bijB}j9upe>e!f^uQ95*oJID#R^6~sTO z<6qF>Q#$0hgmfIIpmb@^&p!56Bs&;j8juJ%ner?L`T)Rm$Q(yiOKN=DK1fZma`ehQ zerZ?rL&G_7bMg;^n5aLY<=R8@0t3pGw&2wAyS|gnXQT9BCAJM@bWkLtX`!@KqZU^D zkI09<=R^Q#(i}Zgtq%HP$rdAAIf4PXQy?dTb~!@MjBv!H8LY10BhcFcz6#HD;2df> z_4th0?763P&YO)5KC_hsc)Sv2nhVNvKzXGOxrhXFwG1vnAhD(7i_(>&Vl|+m99ED?%}|blwU)C$)eT;E0(&-iNr`HD z2S{ZtX@P1vl5?4ZR4l)fOtl3D7^i(60r0M8Ow`eS>oJ4;f zcA3VK%1La^!>-j>QaOq2KsaA^A!uF4o93s zE|1y0fRY*eD$SWp)BhC)oim^nl>f2A^VD9-S;(9=jB-pE-^C z6}*V)N$hf1I*$?2af@TXKq~F|qwZ6I%79myZV+^?R)N{*js^N>2&K18rY(g^eK^jf z`;vJFW|Beb_|K3h$96n8_fdq`B7Oium_D80fqaCu9*P^+6*;()`oKr#O$^=vQjUVh zN$O@cc;jd;hR`kt_#vR#BG@zKrRKz+smTScv%Sd+P4!v6MI2XxN#((jZk()MhUBIdz^Cs4g3iH^6m$p7f!G4>Cn<&=UW^)rZU z^hWN4=_8l{bt&FEj+&VH6UR-ma)nS<*5WCD!W*aGXXp4la(EsgEsRbSJEZ~9R;cMC z0R9T$^#~tFHVq_7Hd!_yt(Z%3KLMKBr7{OwsQjn#CjiGUHW_qj&^>_2 z_sK5a-s+e713+?W!&&Jk1vxc9zTZL)2r|_kN_iH5Ovx2VC+-DErZmVQK{f?Q=J`II za#)b*0LhdFd7mJg10+*&6_0t|FUXbv$&?29fFRofBvW!$%ajiavNb?5r9o~JWP5;Q zN}4@WJ|xJg0g@>Va=Rc?Q$rG>$us2+L3#m_DGhR`Ae#at^JJr8%7+D+4vkW6WihZ2eZG+lmwI|b4t%gQVI38pSIV0wh4rksDzCsx}{E0oR^BaQ|zZ=!^3^C%OxEFK01z932}1{$hW?je|A50?eVGQ>ote34E@sL~^+IJ57rI zx2?t3L$V6sGk|W;g=2U-I5AwKL#17m*-sWb7Ur@6XbvW2@ZH!ta<9UQb1LQ{k(AQB z(Z2!*S+L)88Li8hu_xWi#q(S4!?&GFHsZ}i0N3D9}u6!r3^%F z=^*LTCMijrvY~>cEFF{nP$g{&l0IXSl7#Ieu|n%7zP)Qe;f}KPqV|Ncx;fDpKV!YW~M@7EoADFOd)8 zNyaDTFb@lvGf1(Wa_n_k$UcJ<>nMjZEaX;$6it=mOIQ}N-ylU7<=DNlke@V2k#;#` zU?B$#QUp|v9V!bsXpka;xcLN><8CvEAB*hpF(~sPD97Dya6eJFtcBZYa6i@QkWimd zavwIhpXqcK?o$T$bK*VKdaJC-+f<`lUkQWSBwiHmF}I6wZVh z)Ta&V*9wKxUUvj+7$g~F*XgZi97 z{a&GP-pimKH>f`ll?WDw-RBMFkAexdY}~IH%%2p-U$u6>W-x!2jDpWiIqo+M>Mt5) z4m&#Tw+!m9g0hZ6x!*RZzX{4ZM&*9Tp#Dx&nRPVCaldD9|0_6q^~8P2;Qk>vd(FiC zfx-QgxCGZg5#r~rAZ8d(uM)!phWwrrQGnlOkpEK1b{o0UAonO_tBqV`kPdt@*tXfo z)duM*WQ&blV~{b0Y_^dfH%K0n2ivrbTx*aCg>15spD@UzLV7lGok5ln7H*@#@jWM`8?J%<#;qEoKl*08|xXlK~*KWWwYvHySTmx}Qc@Gi~__;#{ z#TOun!bY`V9QQthY9uPbjdG27z+iY7-$`)IQe(bkFgyY7l&J%38uvqklf!Em&INOg z*bhPT9L)0+^!}4*rdTTUyw!K{5ksMaF#_9&=UE8v6m)Bv3-%iQBvLitnM74ya!<;$z%P#oVX0L929QE z{mv)nFT~M{rAi3b({A+~SYo7Tb-R`)S;q1eb?o=!Hbr0aAVgZe=&&mi#boiI3tIUx-_5 zF>dZs+?>Q)=5?-nFUkcMUhy7;ZNtrd2sbBgj`xG<8bUu# zXkzW!paS}Rcyqq{BGRJ?!hg&3Ae<(xWzZ)7TbcG+l!kM)1#_tr)nM8 zRo;PH#d_Sz@5HU_F5HqmxFt5=7T<_l>~7rLdvJ5&jWbSokX#^}2N0HT!>#Ng+>+aI zOYFccz7x0D!??MR;O4|O?vU9N0n>j?2n;r+kH|GRW4;7X!&h*t|0-^&ui;krb=+#d zfm_WtajX6oZdEVfR{3q*Dqh5`{5!aneHXXn_i#&mAGi2RxW!(^&HVvx$VC1yzNRj7 z0b+8CJ1{6LubR1UB~rC&vqKUr*%%CBRXi2Lv*7ELLq@r4vfNC~Y|T&!U`i!m;l5X| z8i68#{Z`e4i5VKu5wJ@P59!DhBulkn+pNRum@Zt9u(FMZJZwl}us`5i-7aYSftC6S zumdIu>?Wza&@m@^2L@Dxn61M)g8EhsNks-SyVgr)1P$}FR>lS;@c$($J@AR%{y`OC z!LwU+g!LOR5!P=wtNl93277gcWc?<>q74se3|VLUEV3aJA=%JYn=GqOEHTZXiIDXW zHj1PoDW~R8m}T8zxYf4cR?~`GbsKI~hvQap1a9R=;#PJPZpmr5C8pyRpMhH}ksIV2R=jKM!nHX;87or`4P&dAaK|CtL5uw>p#2&<^0*CJE({*;O`MzCM=UIn; z?)uStuf5h+Yp=cbqjv48gABWD#)1WNX3lD!Hf!#jnJstRym01%mU+z=waoiL%e)y2 z=Cs_=eBqo0^B2sUHDm6u@6DPwACig9FCs?hn2{X5<|+Zyt8R zyqUMoSuktnf`#({oO|22*`r4fn>u6Of{D!~_=vGre)n5b$3SuMj0Helxo}qV10{STo3mhXB%`R*=;n*AxM*VY=(|QwxbU1|BC>WB5=*ZP z3+Y2-7yR%ur#0oJEow8}|4c~Mi9q74`e&&v(OY};lrv7HxX zM-|*+c70rBClT|@NfAafPo}QJDThCxyrk$X-L9f>Pp}wb$R%OkzMvYzQZ2o;g%a4& z)&vU(Pc_~2S(eLnRcRyim5g-&4Umd1wYM;0P`edW+Lt7V{R6|SMKsoZ2g%mgN zhar=!%p0i0Xcj;w%tU*lw45`f>W)nd${b z{MTMdwnM3C#Yv)meq%C*i%fuCLwr{3otun-+F9oWp6800`%(jp$h}&YDfa)D8jK(1 z8g!`Z>3%Uk>TGCdttbQr$ZY5yQEaQl$sg%dR%(Tu9WX6$o$Uv8K($`}&gb2=>47$sI zrSbg&i&>{9zVVk|m}rMWR}L&pGu!b|BF2H#$N|Jq{9xMai5QWqfyvpiV*c|#k}-a( z^aa~RiYJLPx`CYoEg0=Zj8`q@=tgr{Ne_D!w;gBEocg*nML7rVI+Ak5e{=!`)p5p% z7wOd^L*0QwgsyGiGY1!dLe)RKJxeq%3@3x3lX`}iz5>$9&|DpR*?!c6=>*HcomQ&xjh@^j_G zr)epS;ERHZ0oeYyvyt`(kF6_nDagN+eUpfb$rt zE%7rNRq(Qs95G5Gpg%m3(y~8ja3zgmuiP+#qB14|=r9Mu5qWh#OHq8%}h$FMdlaGB?R#8qk;xWIPnMRmQbx&w?1?d-+^DART6-g)gV8ae(ab3}c6j=%f z$Th7jL>Q+Uufe|O5V8czMDGKMuuErr&=apmtd70K<& zh#Vj20p~{h%$STpcMcDOW0w1YuyMoC)a!RH%bd;!K^hi#pI&m#>m6q7vJHgzSL z1b=)5dEsi+Co-}ZY!U|32q;8f*0ud(B?j{wtF$F(jjU(^Z=PwRB(4jXcpAEtJBYB6 z>10b7QMMQ*zOBkNfA}W~VmmMbQ)NQ)LEFB}G{%s(zB0om6BnS)@$a)(jiH33*ed)@ zuU~({3M>l#q59i)vyf~DdvJ^S(z;5FVj-kuXgM1mq~vo;D2nV96bm8cxH^gN1X|`U zrzpaNOA-aPJs~6V)P3Y4jHhC8nDg#{7WCc3VztkjBDT(Nv-ymr6jWmv78^<8@VBS& z^9A(#6g_XRTzh$WCE0naAOS?q=&Z?VWF@cJq zY||6Wn{-&JN$oSW$d#4-UIRg|+pf!fkBS6;LcGOHJNEwr;~$MYz+(-k)!wjG^8`r#<1hgt8mom4D?Gzx>ZGlPrHrU3rH zs=bs&QaApJzCtRWy_zX72chtOdPF_KuI=J0XjWMh33eEn!Ek%jp7`7pXxnP^R|?QY zA0TPuPduJKuEaPjlqk*d1A1UR(}eK@sUEa34IXbHCia;@sh}u6Fa4Ra7^5oyjA=;u z^4_>g&)x#9QApnZA4p1e$j7A67ot-rZn>GVxGwS)G$ct2*7&zekHy>g-96y?DB@JR)qF+yWg2G1r z_zFsOG*@~v5R5zTXscu zx|r8dijw^+n8xjjI+3E73L-xpU?IjJsFlQa0kiLS6vh}|u~ecch9@qfB*v7qA(J?M zoHEFfJ^Qs$fcaP2cGa)XN}ImE!GBfTfO+IzUK-a`vHo<+=DzKsHbJ|!YK&=KU`b1` zHb{k-6YRUB*iMW3)lEY?GXx`v+bBqsK` z93Nad31d~|apj%wlrT8z(JVw1OhAYgPka}ClcMDPVMctO=$bD)XE6@b8rs!UEO^|C zUs|=+l~D+@3!hurUxzfhS7HRN!Ttwz$!U$&F{RS31gq6rk&nJc`}N~zP_?(XgG*AW ztrEQQ3u5B(1GF|<@m%}n|p11J1E-8iu~nMiW2M~fKaqjyXbMIiI|OO zyG!jrJeOIhrpM&v~CceLivM>!Mp)Sm1k#F3=^e`s1bQ;GG zghBIfs7k6U96u>&H`v>D5+*o_;|CD=vBlVg#Y&nW8mEV#pPt7w$qqX44X*O&i>-|? z<{ZJEEd}+*I~!rd!O^m!_V-hD~~ zjC8CvQGY!$y#XeWr~9J*`pkc8fbnIm6pf;GM{|VH%;UC`4^r}8;7CEsr|}r8R1+dW z6Z#^}89%-8dCS7!ML>N=?pM4fZhK`6B}ENs4zVQ+c@p|dN$P3KJ2L-wWMVs32+xi9 zN)CJf9&zvpChHT|I$w&)+yI|F?)ty6me*F>aUk)Ooa3}nC-TyvOsg?=|BS}NseOK- zC@0@XOzr(EYTuyaZ8Ih~?&u^t2psI_;xZ=<=7E1eQdd_PbS2)ic`Uzk?5(2KA6{pd zjFpc$A}`*>QUeUmE`E^KGWFQT7zEIpr*X7!NJ9+w&t6_@`RFxbtW#tnLVt0p4JwT# z-v4@v;@bNc+Rmm8I`;k7VjGGCpBctt&O&Ezpq*NbonKT~%mTXyNW6am5%49nnSKJ% zOG1Rd0?ktuYVEi{-D9v+c5EI9zVgmJY{K%T1Ao9iK#KiHb zz>xKpNU&IfN5f|s+N>r>bW!XJx%sKj)! z077_e*4={52@c~}i0y!dE0zFr$Ye#1Tt}t?V@Dokn5Xz#mlN6hE=v^{7A-03cgJv% z?|hqr3QXh*?j~VhXpyhoSA$`Zg!M<$cbsoLbshyZ>oa^%>kWK{bNIe4@!jzzT;|bd zU*VI|;K84vTQK10LRlxE5lDbu+KQ?3W!fJ9yn>Ek<6p z&)rp+K=Ns`hTj%yi!s-BGOxmfZ*@}m>e50)4*gsuhMOMH&VugG1z4OB#)8P3+bE3V zg9ej!V!!GI7!|{t3>@s-ict9-_xE4@|HF6b{b zE_X{3hB}qf0*67LWSG|2L4UzY3f2_uv^Tn+#=(JwyRWLW6SZBQmx67}kfKYM&mty{ zPZY!8T6{Pq8#M#9i>?@XTyNGG*v%^A2DH(_tm(!1=D8__pR)DRc zXw7zE&Af(bHHH$AnIcPhlNY&l2h%D{06%Os4ppGnPG(w#p&%k)L8Ht27B~^cM^UjS zFWPP>L=Nnupe8;P;ouOY@Gm&@S+ezY;gLZcssc$Z`8pYkDN89@+=2w|gFd;KX|kOl zi<_LQWn_bWoo!JDorM~wjYzg*lybR-1seN}amg5TxnZmDO|cY@t;C?cX$A$0;;QZ- zlO0mx7X7PWuN)t+nwWwpQ#e1Zi)xcs@ZZ~3X$QQ+GRR+;(g@%tM1PzOaol#-s+l-h zd}!>5@`1U(%AW{=(Dgb`k8;G9ZTP@@&Ha?ecFLHpoHs(FxJQf}Yv0+`V9+>Mc_(l@ zBhu!VH}Kk8478~nB8T-uT(jWMB@Dc?;{k2QgN0c%q>+D!Z`|}bV8Zc(xneOkyh~-~ zKPwTn)7u^V>U3h_x?C2}D%@^VcaKA6Blf*p$yf{k4hxpnbif&SgJ(UNu#TeGj#V?+ zBLgS0UnGyh_=hN}!$5`(*CFQf3lcF#1?YQ_?h|=sRU*doTOiMbcCx6pTvyn3N;X8S zK}4qQsl-I<4@8%?h}}VO4gc);N(^~R?svHH0RYZn-BX{-qoDXMLI zL8jzXu-v6iB(!-y)nq%KD%+WVToPsyw_)Md2>H8M&FlOrYT21` z-{_$Vv?P2M4hyAJOIxe=wvNjG_iZvY?K0c2{D^U&Ax)pf)M5;|kT3>wkL|fqR!9nh zLpmruiU}GV6PB>qy?xo1Zly3hK3-0FO1nECMbhO{hHXyU31 zD5>=sQ)`qPtgulMIlqe-I}mV1+}Zu|fS1~@Wx2xdo8;ENBjzwB1#TEaD#(Mq{u^m= z_|bN7Sa}_b^kJ4&xt>g9x2=P+dVkiZq=+{K_JZA57wXS9491VztE2Zj+gA`%YsZ(@ zTU+}wu6Pc#&vaT$mT4v3?x`NFc|?fya1%APcF@A{-rv#^xYWM#N2Z96Vve2^2Cg4Z z$-Sv5d|obSS-gun8y_+%OpGj6`%;+$2v9)>8xcp;#pw+SQ*!98lpK)F$bHNmfEE(1j%DEV0s2W;A6MEeG;WH z=7ks{+4d=TUjVNRdSq%PrUX$-MLp#dJx$ELcK;JEB;oks#SeZIbi0FDv>m@!wELep zKE074jGsF@mdfA+j;i3kEp>I-AZ=`u7j@BgseE)@CB}*DxbjI$kaCOmODg%`QHtaE zgb;-++v%)Zicj^)FK9(lYCHL`L$b%qPqL=7KLx?G@Vt(?Dw^zVKIz#0v>gabAEPRc zVHxJS{upgM*MaEL`frWUX+_E9^QZRHXY|(|8Blaf_@{ z5M6mQ<<%Ir&J{;xI;a!5ZWz-TLv2Vwx7?ix5NFJ0OnWR03(@~r>uZ!)t zp%J88723p0e37xwQ5<6&7A$3OyGr5iL|SnM(-=cOBwU`BfjzeH%CpSsF{}AbQ}zu} zd+zs>F?bXLM%t;p|D|M%uW;Mt=?>_cJ4zT6eoV=-$RBs9k%d9n!MeLE>@SLe$uYN- zX`O%C_9AwNz`XFkDT;kA$55-@ll*%`ct72IcnO1sc3K-uoV{|MDt6oQZ!tft9c7DA z(hqmL`Fk`;LGp5JM@4Fz6~tG|?46LsXBdT&KjcGdlm66hyU!4rYh7p(8_*bl+^B5n z7Bg@+6|68%YYrF{nB98I0W4lcx!reP^pE%or1t)`DcGXO<4mmMa`|@KLOi^xR_#6Q z|Mtt2Gd?~(ey}5^Q`+B>Y#U-#%;WnXU+!BJWA+5v!MMT+iKrENS^7A>nh$*TvwMRT`Ke$;bt z#8ZCX(=XLQ#KO2MCA+={$x*WP~o4jPU0 z&FVX2Ot0vla2gM`xJbKX(Wqd#4DB4Hd>DxSVmA&AbX5{es8-Bty$-__!-QWKM`XGtnA1d zyO#K4#mJiDZ^S|_^Du0G{3J1~5WV*;#JM1;Vj6E-&U<#YZ0VKbfO+m+V(5=AGDWeF zSM!bU)Mx=EQW#&^hR+P z=10LrcR#L~Ub5q5)zWPEl?VJUfhH+6^f{n1%>u6Y{I z<_3{}gkr{LrxZhsH?UXw*4)^!)@=NxoaW_tR=rdyl9AMEf?|TGpjSzKx7?{;GDfc;M}`^;P)pK;gaTAruoMfuql7E`2H! z;HSAG_WZ9Q$!jO!owz67km&U|<~Gu{4DbE@8-K?ukJ9V{X;I)k>AgbBlveyk3WaxM zxBuV`;KI7_aT0mZJHut$gkVA%qyHTgZ#$F1CXGaiuaIFsqqOsI%8b}1&rivv@&A*| zhuGRdT~|98bn+c{TVFcs^q;&!@0GXl$Tk1YwP7f8EA)P?ZNH4({YJx7Wwo^IC%C|6GB|Di%DGAMQD#abSS|Pex;}^=pcc(1;)wFEj}Y$hl*2 zR@Ld8?`dc8xp=X6$r4DV36BBj?=0IT&+GGVkiX3KC-vwTaC0_t+oKeR{`gatI=G(2OMFLK_nA{&&-YA=IL>`BCg{;}cPs4p z-B`C*FAhe?P`4N0uK3b1F^0V}&?V_2Z_I8mR?cvPwieWtd8mXjC*q0C!;4eG4&7528?M*q$`a}DSKsA2f>W3C|E-KM!uovAbu;oXevP&LF81Gg z`L|2T7#E#|-iKhbWIMp_P|H|050x=%Y|9IHQPqQC?DY6(l!zlQ?JQyFPH&*)MwR~* zOKh*d6u}B`5V?y%V+>WWO?-@1Eiar4`&x45Vd&N=BY(Iq!q8t&Ns#Gp_0oNq68+M@ z1(J=JZKFbrFJ?HNS-n6>ZvhK*7GJIg9pVMrmvc%nB(|D#RGfMO8Tf;$96L`V1wD)C z&^O2sBfvzIL(V_kUYLHND7+M>|<)(;zH%YN^!GA5Pk$J=20pPaAn621L|h;! zh^P$WGL8#^0wUr%iW@GtEAIMJXGRne&{4-h$5BTe=>PYebHDH2`|4G9BPn41_WOKp z)v5E&-Ol~qbI)DgtHTca?Qh2vKJud6xZJqj@~Xn}zTDOyo%WnDxiLF0EM3sllv~-k z>a3oYVpC^s-P&bq^58V*a2+ZiBffrvH-8~)a`?|Z%T9hAypHq}M%`=;Xn@e+5 zc1)UE$dqjs?xeJAQMeP++>&r7q`57^9iQg53Ktr}XHecY;f_sn+l6c8^%d6QPELsy zGAmrr3a2Yk&=k^@C}@S#l_+S1)0HS_h0~QNXob_2C}@S#N-t=It$}>iGIidp+;jrX zTCj8rH*3MBrIgdG1)G}YYQfUTY1V?J)!VEsVT$y{%>+YHTOzI9qP9d@yG3n@w04VH z;k0&(np;}CMXhjJIYq5-S~*3na2gFot#CzowZc|jU*Sxgm$bs^N|dz1=}MHe!s$ws zGF!M5w6HHi(5XB#=u@5aO~2>kd_mruvLy zn^jZAS-q?3&5TwYJ5ak>uPI%-_U_5li`lUu?yFjdxUYI0;=U?&i2JJ9A?}-jsa}57 zZ7P1CJu7}y?U`Mi+}lyk1f3bk>bDIwy@;FzSu>fFtKK%$RK0Dese0Q`6WtE#ZOu}( z-ezE{7R@Ye_1lWc>bI>cMnwxCX-2qu?4gxvX1RK7RqCYPu1vI>ovwOURT|w5G-^Pu zs!_AxQRJY`X34AGRee^ytLm(JS6e!|8x-1lS6t}ewso$mx2S@Z)|_ATx2 zT+`RTs=TIuS@+7N;(Z0Yg-&<4phr*{`(z78GJrJNfv^lWNux6x-R zrW4R+^7mWP_Z43L zekpxlThiYzrtfQ0`uol4``VWNej$Bd8`Ix+3P@CM_4g`nOU1Wg$j49X$Ht-QV#l); zWCKwkkk*j-)`37;MdoG)0%;wY#~lcym1NF$AduFQ`Qd>;8YkwG2Lcs(P(4o==tl6Z)-%mr$rXT)(8fi8L`ul01*_6cJPb=6)L4QB3Uz?^(?d{6$Y&H%iw<~I| zAWd$&$|uTIQxzyTtsEN)ljv#P*jSj{POHYIH_7d^W^A65+)gXTCOpaQv|dVD_VEL~ zo!0x3u2NF_I=;7a<%+nkloYABu_D#EN@`J&RJzxdTo>7D#Z|IZX_ahMSS4GvRmoN*RkBq#WG5QQF18KB6i(`Hqwlz$_3M%r zRaM!bo59!GXYjT98GNmO245AB!B-7r@KpsF{A?X$w~-B$6*{m{vXX6MWQA&MW>{Gi z8yhqDRa9U@VTODa71+p^A+IV(_z4cO0cqn~BAo!iCUzP8Dq3*MXcgMA@hc;pDq67d zDns77LWj3Bic1@x##XQm29BMmAiML~C{&S#jXsrZ>rd$%ZM3PBHmz4kSE;=XE)~$T zp`}tOHnL>!t3V*z%Gh91nTic18T={`XsKcgYz)arr-~9Vwa2&$%2=fpc5l%#ykFWsYB!q!c_<_MR*y))d<%hyd2?L zgjXP3hww^-S0TI_;d+FBK)3fFXM_(S zd>G+wgpVM66yakCA4m8E!aWF|MEDfKrx8Aba4*7V5k80Td4w+@d=cSG2wz6{3c^BK!>DA%uq!9zpmy!Y>g19pRSu4n;T&;c$dG2z3Z^5spAO65%L>qY>&6jzKsU;W&ij z5#}MBfY5-@h;Smpe1ruECm}3EcoxFR2u%oigaSe{LJ^^a(1Os4(1y^Cun6H4gl8ix zMmQDWG=wDxWrPldPJ}Lmr3lLqmLr^w(2Z~g!U}|y2&)iQBlIAwL0F5>i_nL#4q-jQ z281&a&O$gF;W-E!5uS^%3E>=seuQ%oHY037I1gbf!Zw8S5iUS@9>R8n3lT0t*nzMU zVE|zl!fu3%5iUWv6k!j-UWDf(T$Y0!Ue?#&l5gto-wusfcbD&g4=n}!nNEK5)~)@; zerPYaH!Vpk4>f1sfbN4Ev!c}U)rt_O=8GIB78fl}D<~R}5R@Re0eA#AQbns)1mG)( zZRZ9>j78ET`EmgEQIbVco{J5TR(W+H5ZfKtex=v8dRKcoNr)t~8SW6`r zmtorWe7;Zu26yb;6BT0S_I!Uqxc$u)_hyy5`u1+wxqZ)`ZGdl6oZVsD3r#JBFm6Wb z$hN($&4i+CXLaVoq~j{i+TLtw^>5yKVSgcR&MDjT?rxOejLw}~mkw;+vSS-c8Y6wm zK%vyq_S~i>O-N#?&jp*98{e^hnQ&nvalvxuU?mgo3H$IvuUXp*rl0;xw(agO#O-(h zvJNVfkIQ=q?hdrATDpAc>i+Kj_N=lW9JhhhTJqhend4(-kVr8fBPFSxvNeWO1SUPH z2uwUK;lju#+-L2>54{eC!nOIG+ACo)qkCZcp5ASnw_e`g+#bVz;?8^pa;58-Qb6d;>stcv8+8w&R)q&k`l9l~bS@#na7##O$f$?#W z@U2kLTxAPPCP*a0KKYPqvc_s|j|(^jt9_RMv2C&ON|2(qPU8zEFi1oJ*)14T1JFw5`{YBeL#QlmhpMS#Jrb$MXp4)|qxzPp@=xG;3^l z5AuCKU(AS@)%RnyO=Akhe4O+I6vi4}>nx474q^QA@;dljxxRh)&}#}7r^|ilxN-bh zP?F+I4Ngi82Lj{GuD}_^o-FI#NHK1iaoeq_G*>AP{IsMzXYW%sK2RPkWFvO0`GaKP z+j>ALYp6OnF~Yvoag9(aq|n?R8yD$0mHlas>^%0jJ3CNl?cWYVQaJ|B9O&J3S?8`D zecN`RZDTZu0&VP6s}=XbS=I>zrInda?(1LHx2k`8s-@AOrPhqma%Nm}(c?b(kc&yh zT|HH__@+7oS@w%*#nn{Mw`A1fAn6UozxqU6m%W6?eUPO zY|(10?8)0(Gt@Vkc#_=q$%kAr&RWl^RQMs=St7Ce`K<0awcDDze|wAq&yTyM_=fFS zBV@_~$Ei(Aa!H$JeX{Xrq&qASz~ytIq`3;YspBFnj!cO5^KWqW8I0_Z3@k9b6np;*t^3lT?NmNp$&{xvsjhhzfUCAfak|G)G2bmdXANCdxW@^ z1-)s5x>~xnj4^3a$L4{H`nShh%rHc?#<@&UBL{X2 z5RWQND_!BxqBh5nH4Vk788220>{bZ|trAvZVp^OD66NfZ54oH{vuQ(YG$&(#ti+U< z#@4JUk_<|4a;r6mSEPEDas6Dg#Q8gB+|AW$89Sa<+J8R zl^JD?elDX_hq6&OZurXdvi#UesVvuWQfEgmCJS+{lX2ut2I3g>l?i6qg-R(5-4(ib zh9btNW5xjWxCtDr%48l2ul!x=oJrGV2m&HGLpoWuTdbfd*>1q1qGq7LkuL5c!sB@+Fav zGZ*<%HTj~*$IUA8#cJ}+A|H1Kk#DXhUl93t;1T&kHTk^A$3{Tp^VQ_BC)Ap1Es<}E z<)D&v)a53SO!o6_ZLrgfOZ7&=f zc@s{l+6%{h!h}7=0p`!X5=<C5lpoW1>>d>!F0>$QfL}%b|5%Jn=RE> z$jORT1XEkYtdP@F!C`uC6*Vn5K^Iq}6y5r7hNPSdj?&cQz!g0QmP}3wS4ghRmc*`p zFotlgE}cD(5l6Caxu8PU_;I@6i6@>VD+i6kbSKLkqe61LKKB#KO;x`bDfY+xY?3{u z5_cdk9QQR7PW3h~9QQX9PW3o19QQdBPW3u39QQjDPW3!59QQpFPW3)79QQvHPW3=9 z9QQ#JPW3`B9QQ*LPW41D9QQ>NPW8sA@<5febjqktvInhFEtm+WQdZ$q%2QVxZzYZ)ozJs+-xeEYPCc(ZZs85 zwOJw>D^^9*detYFDmtfopegK~Q}jutEJ=ATB9xpgPcBsm+Vf12oIIUTDW}hDgmSVK z+1J%mA;~8fLfKbh|8yc4(RJT_eJi^=m-aX1^z7#{{gvx&?ksjGXB?zI(z|r|s-CW; zi{-;=gRgF3;;X)^J1=Bk9#oT3P4!Zk zMT`2H7B{`%{LPy;pVXIkl$KbdpDk+uGlU6jXkkZ<(iKYc7rh0HUtg`lFe9yA8TzgpSR}&O=%M#65rHA&89}VIU|T^&n#H-lJcEa}BD^ zX{eU|ZlOBOLv`vXRQ1`OET|gd)N87A02Er;R<*4vRPXfARGD}A-O0* zRqsW4o`kQe{u}(#{p7Q1a>IG8*l#O6d9QV*2knee(CR~I8KAXCU9(+*f_r(LI=*T9 zYEP3IpkuGK$%9lu`(giEKs)9T18pe{+EPaX+P||2)`1?X2aG~hpOMUfs=Wjz8>)E+ z)x;GDXI}+-GfS2)aF@rXV)fnrw_^1O!)i+!tHr-ttRC#KI(rnW`V4OdR^4lPvVDQ( zlrIor)fr^9xv^dSkjJKC^`HH3#p*GJ)z&mtOWqmyJF}~Yd8{5fidB8aJOiutYOHE@ zRiE6qVLt8D;;{ocFr8&r-|MldSbdNGtyn$Qu-cZ!YKzC}`=6ZS`Xn6Ir*?I<&VzK$ zC`k3?2N@vE>$@VVfHa?4U5yQ@AvnXJ-tIxEAid51R*)WVAZ?F9+S1w1g#fgdMj3-w zK#bQl;mKIXn2HxbOvlR~X2Rz_055$w2rqm%7z4$jc+tb*xzD6wy|QO{cW3>I{Gvst z=NC6#QC`q^MdyO96HlyP(F9f#Se^61p5L*cjPI@m9Vec+0G#stD?~^f9@}e>ZH8s} zMa$}!HQ}SmhQp#ovhA?=xbD>((t8hBI_K^K$o`%UOMCk}msadS47-T{i*RIa>U?6ou4rKy;S**kEc@z`Hz^S>3|_Tp;Y zO;88K&BJh3EZXU6>1?GDo`c33i)ReS0o#J`33$!PaQOb{(D*Jd=nRnEF~7W^L$KVa zkauuivd^)aKk*0<#dP~t5v_lk2dRvwhP&v2ywEg;2v zED{haNXuq}aUd`PX{ocFdtBZKPjE0D9;ELZ8l+crzz8RX*yB|VFt9owHh4dnUbC*U zYdg%o??`O!am41anbVatNe@kbm+{zk|j#Yla46BfL?VP#Dl>5)hjS z#6l(zi=#kPAWo<-h3+4mGR$YY&f^WC(HM`H_a(n|jPLZn)kt1zxNJ@x1T1tWOaC(F z%RGK8$}>sF{o(!4iUruzN|nHpm~6xZzC%GO&I?wV@b$!I@EOZdNCqoWwpiuP#Xi}U zsTRVvlnL9`QP>8fel$yRuT;($+-=87Jk#{BZ~xSgh3NF!R6`2U&eGy}@o3s#=xh(y zrUcJpbmest@*W=1?;hIH3WO6tW5uE=N5zU~VUv+cLqt zXcWu=n8WctuU0eL7qI^~$wG6Ry{@`qo%MwtyK0^1``?<+EN7il>#WV83u{QmUYc6x zkzo0shQ=}$sk%-~;kgr72EzX~Ebmu0_Sr=4DVfM!Jc``Fdx*@iy_8?JSJKATUi+VA zY!`Y!DnPIBzZIY-JAkI@kEvV-O8sV+ z;1!!=c%r3iaZ>=^kImZPkZH7Ol$Hk7U{PG$Q#_hh#WfWhHe3Y{@8+70Ht; z;A;QNCUC9v8~pPLl`wDBRj*9@Y<~$-VW0PUxGVgh>whc!5A(k@g&D3pq-J@|;R>4V ziiy1*>8kFlhv^O-&$JodQX;!6(?%~FMYbZlaX!I=FWm&X&9@^UQfjT{lG97bO#Oee1SW0poa{SlL+vI_m2;;9}gRxPMj{!#A){^ zP6IDE^d<65?nr?d+4zPCA!_UBfU?iYc5Wms?7DGGca0lv?BaG!U?`QY} zHL~(Negu=cj|~HA?B(j|0<2cVv%4#B@&Nl3I7K7QhLLi*Ch##vbf%_aop(Qidj-LL zMkcsdj)J?Iqg>qzw^p;l_~VWU!1z;-I#3Td6*sFlG?tJE*NmxzvuF6Dj&nSAUxDf5?h-TT?^E@Qg#%}Y! z6{6P|L`x~>wb+?F6YjTv#lDX0NWyKyK@{g@WD7XJrT7wE*!;EGoE({X(sp&2dD}>) zYio(fHJOO)9Yti|EQCvD_HU6{>kjs}s&o~?IPG>k9N08$X7{v@Vak)3)m}F};2i(}9l=;QW#IYAp6U-1ZR*H~O! z^?a+~cBG4ERe}425sO*tnY6+iG7)>$C}OK1*8bwx{DSoQZ(A~(OPp3+T6n(4s$%)Y z{5tP9}VK1u6Z?LA8S!?->t6RI0W zp<2yhNS;ba12ug7F@oxt&wFSpR9E=l3e}_hZ#BCoIJ28tB?EN5o4^Hyk(=FNo?x(( z;av;hCBz$SVsr)9IPECsb)J!ycM~n|b2H(5&M2G%I7iD~?k~hMHs0)CyR(h5`{U#E z$uj%}Xo7r2`Ud}7k-pF&JGE3+=xnK6X^>OABRl_a=g>wO3u1C$H{6!PEKW8i3POso)-HD?uzZTjUKw1ZkPY9 zP<9VVw4`>Ii{b9F9Zj>>>Is;K_b-My$|GxLfUJNySd)>d3%{Hb#CTOm8o|5nJZbJjPth=v{DC-Yp-FpzDu zhbUld%YGS6AD?(;LiT(@c3UQ7FBpYvV16UW+6x!5AnRWnQhD&9=#HPI9st5Wj>ljQ z4ht)o-Bau>74HQJj#A22vOVT&+ZMyy-{Ceb?8#p29&?6gkFIlqXNP%)I!sx84Xwte zcsp_Zyi8nQIEw3PxaQHx%KhX*vHE_p;X2Dq9~UDV|977tU64Jd;LLPtmAJXH#jjlW zb8F@%50C7x4DBS#YFdKnMqPLl2idkaQs>loXwAO|y2^4J!Hx*4n%vtN{??a7KcVAm zI|%lR9N1w929(s}Ydc559)Lacq4S9kU3q-1RCV7YZL9lYMCX?J-@3pt(;+;y;f!NI z9^rB-Q&2wg4d?d^jd0shmPL%fb;e#EUeN#^EjZG6(hqp-ulJ4YCW?1un(T{5Q5>K+ ze5Z&y2;91he3W9<<-1aX{PeEL$sWBbGtU3kj5^}~{B_5UTT`1RI2Z3%?`Xb9zRB06 zFFQ>=s)R>5v8Q)MM`E~f5I))F!+HnpZ@pV7enQ)BmsWz#cIE!Q-;}R9uoJTJ%RpMP zpQ9KXY^o`I&P>7Qa{OU4F_YS?z#A9*x){$z+P3gWj*u;`#0*w)%kyy%oru8!8(B@j zOP8J;SoV&BB{$LjtHK`bvbV=YV2KTpJMWz`He+{rbO>6;oale6u~~yZx@>PJUQ*AI z6+7Gf0BR35;Gb17go=|myog-h0(Au z3f;9*@@j%)3L&@}yT_wOZBDoUty7Gn{GY@VN~z7JQuvT9*D-B}exy=Cb!+3_SV$i4Hmrp7{#{&$??099drJ-p`CVl zT$LM;cAy!r3UnqYbmJkW{=Mv8sxSX!r>uYbo8h0(MD;~<@n7grj5*Isl+=mpi$`7j zDlUF-#z{8fL+?L%Yi6*pqND9u9?@zQgRxe})~Wu!PE)5j#8+(bB!8LVU(z=6C#Fu# z7-bFS;XzXay=?X9eAO?o4C})~8&?ulSB%=mCuAG#b?aG6*!G7lGN+72TKx4`@>?EK5DfP=*7J!GY%|Im+5S%<{2C(sYLD=1 zJ;Gl;itqs8;k>6UdGT81GIhIRHDluiv)~xtuk*h(&ei_6;(MRNcWNUB51n{hPLFrw zFKK;fXnbexmn-P?aOwWWH@0Smcysm>JQDJR%=>i&|0_KBU**C7%2Dtu`0W(~kp;Jx zWmGZm=@-IBkD8P``@}Al|EB)ufMN-<}-{Q4V->(_W(zs}?OwWGKW41Z{&?SE;qW~Xh6(JZ^(mYNEL>9tjz2?VwdD|$a z71Off9dFlEdu>f_kq4!Mc9s9Fpq=7Cn%a=WUqZwnmFeclA13?qFvd7Fv84YY52o8Q z4*!Sj@GZpb&E5{b!`tDvk78CaD;{eu7n$08Vrny1*z>_b+4NJwr7Dk`o#DZ)VBhS2 zE7;%ee{0saIPj4+z^DtQ~b#I3$dywi7y+ef=ZHPzQ&89DAhH#F|e2MJ%a=eAbelf(NF`4w;78|Lj$PYB%aBDnAH;C{CU_no8Q zt_JR=WZ^K&-s?)axq9*Z@*Iy|MR&jdt?0hV|5kLr)uB7Jqlz6TZ`HYaK601lzM;{r zZ-(NjJeg(UFacZ{fw=uW>;Ey7zlSKl%cJ~#9_8;HMR_%p=Z9D&c}5GGl+5^A8Z{@Ap9eXAkrbjsm?J&`U%3DlJv5`L{ff1?XdfJtGDBN`GI0 z{!It;%Dqqzbo0>10O)4Vhd&E8%xa-*g}RdhbkJo{ycWAeLwM=?6XqW#%s=E|{t*xJ zyGLQJFwdB!`v1Z;f$~|E(S1lhy&+D>g}6d+vhr!qdBmZeH z=oF8A9UOwyOHJ+5{=W8&Pr1HPv1Jy{UdAUe7SE z*}~ZuJp7TsA3tqTUS8@w^3BrVskcg}X2eHcMzUS{1p@r@4&d>2=@&-!lu|3gOrI-wNSZImo7VQt>{P%0s(it4HRiw`M%(rhYhWGnRQssSU>F&SsAZIRYYf zY~*A3uZH$d#SaZ^m|LK;f&BlE^S7@O#$WNn{MY<2f8VGTR4bVE3`F9{W^BmV9L*2& z;nsb@KgpS%+7;A*R&QrE~C9?azOMJ?87a$9&88m~W2um}-u(e<5L3 zj|qH-bhl`A|G})`#!^U3%u+I zn>)dqYOvg)hgfQ`;_>u#i|?>oeA{=6@A+==-O+9lbc^t8xIf5M`FhX1-}9_oKW|k` zSH2LS-J@Q6#a91Yd&L3%x2Et#*DF%Hp;#;NYvep?EB^;2tK`G4kv}l(U}68~kPH?W zK7`{}$)C)63Hm|h`#y*093xygk!16>kUo+r=J(kr{-5s?KlFX#2cvx=aIT_0F~sg@ zK6sWQJy6)LYSz@WO;fDwEX#do(9ZG#|64mt@K2T6S!TP=lG;%%#0!gdbYSG~$s6XW zI~*OrYD(x?f#d#BV*k2TwLC2Fuj~!~;(No7d~f)-(cTdBhH%1=FC_;8G90JywV@UL zLHkN(e{hR9X_xABkALkCyZvwN4`21awLg5x`a`}cwZn=R0s7HHj--iSHS(8@4)?e< zTqrqHfY+ew1E}&Rm|WA**K=Xo;r^ncCjDc?3z1J~FZIXlAou$Y@__FkKN;;HfeRIN zkn~HVMJKL^O_3&~<_+R_hr+zPJ8oaBEiuD{`b zE3UszT&H$d3!Tj#*L=U;$X{3cwV`pHoP!U*EgP)Cp|U44T^@4RwI(?KC2{`m9_PRI zIRDis&a2sc|F4J{IByQl$X8f)#dFpxI$End61dZ2Uv2&t|69|#$N$#8@d@^g)HW_A z1AfcS=EhItxMh3BHf~pF=;dfV&Kt;NK(_Cm*hcPeh{XSJNDR&ajBez*(c2D*V^w_h z^6oB~I*ys^+g`D8Dce4^U5o#W4eg>$1;qg#*|MVvDcitracGM(R8~U45%Z1VOuj-%C=iU@UcubxDt>*3H{9_jIgZ2H14>^shU6&C1%F2sjIhp z!_viV^nLvH_>aL|LMY4M}(g&!p zEv*^at9~bFw(yH`|CJjDzEHo%je%tTAd|3LEgV=_~>pHr80pS83L`IXN$22H@U z<=|pS;j_BNmuF;os}Y; z6}g1)4Aa>k6P^93<~qx8cI>|=5}g%eojpTw_CJZv{#gpvrYmRi5yjAuY zhO@sUI{RzQb=F*|GkYE{(ODtZ*)tSp|C{LSv6}0wn4vRu3KN~>Bb_A=Up>Qc_IRSR z!J6x=l%X^AIue~V#X93Fg`QbDg9qSTjWJ_tuCta5ovCMLI_uiCcTen~txS$EZ!Xvvy#A)fF4!R%deI|OfnFjnY-RE{mruD~@QQz@7c7p|STBcW z=tUO-1HD9^*2-iJ? zIU++ZfuFo`sm&$a;!?iJPy3%@u;4WcPARi%u9W%=rG$=fM|oq^ht{<|ZCJr!K&O^N zYOa=JGSm|Iy1h_K)P;ImpEk4{nyBTlnycm547CKVZZE(Rqb1pWc*-ry;fY%2)Lbpc zWvC_abVV%@TGo}GwoZgqcGrpK)?6*eXQ(A`bfK2^aFV?)SeSTnE_Y`a8s6;DA*IX+nWN0ODa-o%I?`Pf9=d#o%S~;fXT4~78 zO5ox`E78Kjy5^@1E5{~UIj-hfX{^*rTj1bAE77vTx~Feh;rK)=^J=b@6En0DxVO+s zw5YJ|>05+4A<;@h&9yQ=Lo1j? z%Cj=G68N?Qy`6n(NNhD>UHj8!R&e6hK_y>vrL<-!C3I~&SC|@{Qd*xjr4$mSG}l}y z?HNi5JllcZGef2HK7DKbc-6i`N~z{bS(Kraz_A_Z?JbA>r}ybIDtOC*(@Ja2wQ@?O zR_t|8wsH%j5@}^!@^4H}`P8s2(Mo&Gwesu?t%Qzk*V_jVzYp#`3Gqe&owgc;zt%?Tb-hBRP+Y>r9(aUKy*UM=c zdI?-xQOn8|AzboJPumjZl0+}%n(JjrhF${a7JBLH>W=mDwBe;A(MxB|^-|8zOW@wF zIlbE+O)yWcqs1$wh|zM`lh`9ZOFgD5sr1sCS6W^>lzObq{yNl#-&N)91M!MAtcO2; zxSuP&EUEbNnpa%@ejr`(z(v)HM~l)O?S72i&-KPD5S+i&UGsX&pI4^q9eANy?`YY% zBl&B=Ty8(t8-D=j>b;`o^_Dj_#`P{V1q-NJ?`UDUqrGN0$Dd}ndatT^z2&+8biD&l zQtKTp9d{&8&h7X1UY*ptr{?vxx5$Ri}C`?mWT=WCLBudR8#E1y#? zGzH$E);n7M?FeR6`?=nDr-j3LU(M@X`Bxx?roh|NdPfVq9i^J}?{!JN*Vnw>mG22H zGzH$A);l_%&=G7o@8|a3kktFkn%8?uhFuH1HLZ8FNV_te_Uz}1pOsYn?3!16YDUF_ z1;@_bo-^a)OC3eO=D45h{hXxU8*5(gX&Lnn95$_Y)ZiV(ntABYP3pa==JlSQQSZQE z>w<$G`D-g{XV1?`s@-4nYR{;wc0Taeq}q|YwlbW(?`N2wo78)A&FeigquznPCiRZo zwUxDV*YNTMH+-L0^J>q^sCMA4Nwp(yZDsAeHN3slReM{_t9?L5wF7TWsvS9ND{D6y z!>f#4wJ)f7wGYgwcHpc@wIg3`W$>Kne(u}PORBxS=G8tZquPP5Ce@BywUxmM+x=W^ zyiCir_C+IY+bGhzMqG$Kvzlq!>tQUfHLpfm`W31AvIuq8h zx!kOdT&{GbmqOYSu{5J2k(yy?S{Atd4y1dq<2m}YdAVHv4aOtgeV!zfA$MIM2U_J` z70U^)ctgx9{d+FA@K)oIp7UJrE;SzMSqr2_F0M<*bm4g=cT5tu|A@+c!torf1qcfRS_`8*X>`r{ zbl>Pm^ps~I>(;eN)?h9A53nvMCoDF4(84U>ja^9#v(YDc989~3z=A;asYY?Wh==)O6IK8Gf=5mU4uu0Fk4S8%dInt`D8;!?wtlq}cG9W)~ zIF~Qus7_s6mR04n%%bO_B+_kqo(K}JLQo~V-|HDH&F=xPXDam?-)$C{RKuTrf1{qq zbR`W$)*Rm&2U#^NSLFUq4;Ru)4~JTInjC4Z&YTP$iYpi6s>&XSd5trXo@)-$Q@4PJ zCXtJ@s?jw$(<}ZLDmvffNEaT-PUI2tAQ5nSZ7#+k4F~Ll+vdcFH8EzA+9q9jl>4O zv@>bSXXkQ9qDz$iuDc`A1X-JXZ#XfR+j~4Be#1lmBxB9I$3wp@mpcnOo7?P@Cu@b*YP;2_ zVV6&ftZRK*oi4}xs-zvetcA)~dRBu}j8z>Re0(Wrm{qy=$KJ13W$z1Dc7&qw-osD)gV zYk4c=w5iaU9NqqtT<)OzO^&p5h&tD55pT1}F}*$*m)TIBT%>n@&htpCF1``VtwtxG zKE-&Xx4?W(Jlc4qCGJeu$yv8Ee9OY1o%M_nq<>6AJWYd~Eo4?0qw>dLG^Ns?J< z)?gaQE3J$C=Jk;^K*MUqzUTWU$|ZT$t@nMC)?mS^#6Zv*+~fN>t-+l>Em&qLSKUtE zsc8*P^JbTG@ZFrW z!s~mn+?f--9BF|=-TF9>@}+)^CSCrJAEQZ^V5(-n$l{WweuT^N?cU(aOnT1|zAU5_ z*3KL-y*X&a*{Z)>j`YkWJ}zm2Yu!#O3w6~C|6}%ECw-}{vDNE3&`W&2w%Glbwd{yWvzqG)s#5hvs`LQT=}S9>vlf9xzMGg zC*N|ZexXa{sZPyosPnwan~i?=jG?2)a6LL?8wGA^rOC5Bc6t8xhzW z3@f6Kxu5bTh&H0#=SUmzRd1DOBhK?uWG(el+C;3EnT>}~3c0jtzG{X10ltj~m@GBb z%QsDg#F_uf!NH$wQL%(x{Q#hGk?~0P%mS?3NJe_|ZGioDlOwHg_-xGEhS8NH9%+?x z-H36uTe`T+cS{jw?7fyAX&E)gL%nj5mU=%9(;*kj*Y#$U&yC!q8?Nv?(o?1TqRHeU ztuS=vDlGF{*Av>r(mTeWYjqos^o8F-*K#@~&Gr*X<{{toHb{%k z>R)E*kydly>Pz0GKZhTGfXR_oImLnNzRbIyvgxI)vpxy=nJ# z`jhlTZ`LJDj(XGX>-5L+>rkfk7$_7==s3CDYU|MBK%NL7pATDdqn{iJ3&UUCmwl&X zcU$Uv;3Ui0A|uAT5CcQLT%@&@Uyga3fwtLa8jtjbZ+k?O)*3mjG94?G#pQjivC7F& zI3U+}P>zvIRH@YqQ1z0{9*q?v9mCk4Jl5?B4Wac@I3F5t#VuvVp8Wl7szW6TMQcxW7zTM)xkj0JaHroc(j-`Rz z!3L|Se218C9Ptjdd>?KN;vR1KM&+Ah`If&C$kiDy%6G2u8V?NQ;Lu5Z8{QP~jx@bQ zbvw%H5yd^)>Jinq-qMS7dW>7N3ET2mt8di44VFj4F+o{qjjjxM^Idu&uGme&_5iM> zcSm`gEak)K_E3;sljB_!@X-I%GW;pv(Gl4d@L*&F2T_@wxvUH0mMy(V&%M?sPFaQb zlP(5kmrGwU9%<`8v79*Tlq0Qu#l?-%gM%%XrU%;kneiy6X*fC3nx5lPPSPlzVsS}p zKXW|FNg74xJ&>04$fKO5;p9kLzpX4E^VRf_pQe|}R~7>)N80*#oZepa=f-u$BW-;? zEr&k;O3E2+b|99MGL_dGkF=DJJl0oiDBF#+OBQKGg;`80>Xl=IxQ~9EO8@9T99W8PVZ;IsvBWxqmf*10b@0q{x`I46QXiViR zZNRo9t@bC?FQtyeDQPJmdCXVJRC0Zgv@Ud~`lYlfZssYe6svs{#u zK2ZlRL@v@&zB=bmP)^I_>PA}2m##0;n^~{PX?j9SdNW<0VS1`FS2xmTzb!81_RfO+ zejn2_+H87C4tP%F9IbK}#d7Dr2p-oWMopOU*OkaM)i&D|BtE&7hvGim7`X+29D zFkjNr9(8|;(>ot|vE4{ZzQnV6Uf9{X1AqQ;s>LNuonhMxo>FesnsRS{=gOYW75Lkd z)#a6Az#EfSPqZKrd(EXA5Aq~55@rT7cY0TJx{c3szwcM(I5U{*=hJ03(tY2r1x}N+ znI67>mCMc8VLUN#bLYB*@hunc@4~>$g>ceamig%=X-xx0ST6E5?ZhJKGWYgL=-3V7If;*_ACsyUn#v?rkYgYGPYCO_Meq4%WJm#mKk+X12TlM1dU>vKG#D%VOuD#yt zY7(p{cALVJ8(^uk5}e$iu72%j*wob+j{~PGOAqN{*1%&Lq}3a`!RkR?*H-B2PUDf* z`usYUD*~i5|Jit?8?Jz^ob@KH^%gsUi}_iFjK{Q9S1u36QC(@=fkL4jy*ZcLV9El5 za-xP$qOpU+7EUuQivZANJ|k~DCcM?j`8HF7VL*=?q^!=()2I1 zCBHArAwRz#ItA88K(yEw06*0#2m7I91^b~VSTkpBq;B*(ASYV#br1ODPZk#b!LHjI zRnAAg=(k(Z^>nBS7Cc)ltr;Kk-3!KF(t7M>Z;em0c~--3d?C~-vi2Avu|@iopPEKx z5$ds@N4*m|)MY%}tz!Y`*TH}!x*JmcC zJ#tZQ^W(7YD~v~a0}LB2G-o8!1$KlAC477%kAHsWoxxGc*K7=zNG#v{Gs zQ$XT(9naA_0PtoRI&hKRf%cl?rZ%LdzID!+PzSP5`4^N&F4EElgWbks+#PweO9OdE z>w@7I$+P@q?n4`{#BQR-kPaA$?a%_L=Z^mQ0T89gGXjkRA_GKH2A!1u94{fMC*Ot_|y01?6 z)UWkAmIXM6F4aABI;D=R-%-wVBAlx@id&>(ZD%~jvBvXqQZ8#f z&#OZ{g(u%~QE!Szr$5$HvFGZmbwU{=?u?);Gf+?E;X9Xeqa7MQmpj|w2e&cf1WH#m6DzZj2nM=$(A)Lbsovh_UC znGw>vVd5sbCL*nHP<8vbvV}g;L5;LR1WJ;Nad*HuoCDWSF4B_T+z%R$aeKx=?j^<} zt)_CP@fddty4LK|j7M6b)NDNFt59-7Ld5%c9QVZ6=W>TQy^uZ*G8`63&)EmFdzHl{ zEoQNNPn_N+3_ILyAieu-*pqbmlGZNKYH`Wib13B27>~5bJ?^?fB6mO_=V*~54%lAO zWoEi|W7}x=b#26U5IMF7b#B`PdHHrCocl9klzp_D~-5p**J- z>QaUn(<%Jv7ER%G1>X z&3mKeEh)-6z!^}~I6vFvYQa~%7h85q0}uM*V6>CVBIElu7{;?5&(Ryc5bO^+T3TZ6 zS7W*7BKgCi1i46y!^7QP($W$Q51Jg)krrioye}wZrfwDK`Yi4P1AUjOF-%-L}G5f=KvY!1WuB=jfgAIvajsJkqk(QNPM~q&NI` zpe#o-FOg(i@viH)SzOYq{{&C=dgGCnxE+p1TFPuZQA|N1oMW1q1ybq^C^Rhenwe?% zX?)Z>EC(5@Wr}A}f3Ne-4_UW+?_`ce>^R1c4Rwz7CePxw)}T-RC{uRhMIMi29k#Ns z*QyQW8AeONip((>H87nl_4sMkah7HHSOwcUIFUxY2c=kO`Iv@KqWRF&MB|Bi8xM1( z#J5~JyY6BB#?$6pVRAgM#B^4D2nU+$0MzMaM0vJUg?oI?uJk2a-Hup9%-pZ$L%S(ZwGRY zR=L-i9P8GDRxBQAJkpz=i!y)9c%*l9L+)hbkruPr_-G}s1ioCMT#K_)OixaeupXo( zy^c3o+=vG}%EdBY^w(VOn5&IP`jXY)?KU3iUB5z?e~a-*Uy2D-a-zl2l5d04J?kXq zpLG+SlwWwP2X(2Y!ReIkpgh+eS|^lW;&!-tC=c~io~y6$qzuAiStLEdqNGPm3QhzQ zVylS_iCaRDxbiI*@uW6g>n5hFS#I_F5mdUcn6CDu_@+ZYN? zz#4^Iqtnj~WU z1mpRRAQyCO%?00b@%}Ct9?r~2??nCS+L7Ko0Pug+;*vfSKly|RX|0jwAvMu4VT)Bo z)FtJHVmmf@#nxK`6|eKw9(YhYyWZDMT0{oW;0T{e6VLZ}3KwFEmzNA+_;Fm2(OXV8Qv$*6fg#s5|U_8>NqY2rYNVA+G$+&Woo{#&G z7StB6v-C&{g2`hUOdTR8idF=lXNnd-OjIaqs=;DCRk+C`xXV58@J2r|bN0w0W0@5* z39ihO?t3XpeYus8^lE74gw4hyttH)LJjR_1EuVa<@kk$x7FyD8JkomB{*A_CI$C3w z9`Eb(8YV{UlRWV*>k zJd{}sT3vWJhII@N!W`!0CIxvs%kqd0sbDH9OZL%0C+_ea<2xm0w=%Q&!NMRps7Yrh zVYZm9sNC&=9MmRFP!|^E1W~Npf0p~e;>>zwCA7qu@nhrZo+jjE&vb@sN790o>EO#n zIoZSJJ}YTSFWR@2^nUNUjq^+%EIZY!O=aDvO zYyXrS%Fg;qorKnUxccVq!>07lef!xa1lsz&NXOli6sJE2t1Lf|4GMP;ycTp5Spc_t zB85@s#aP|Jgn;*irz<~S^7n*i9oF9yp4gzdFsh0Je9J|A%HkkTPLtmJI94A%V{)Wr zDmDEy<#;SLaw@KJdaTUt2*@DRx zXF8svg?GlUJx}P}@VVA5F&=5Ai+p!oR<_Nx3w$wQ>18te*tOnuK_PU7{P%wPHPPjx zl8CVkG0t^7M=!&s)Bk+ec%%=-?}k4bkF-3{TK^K`kru2rpij$1+KM2Y-ff$=>R|Rf zEB4{w9Sl2(rNMB|ekRHVThaKCFZKcOe*Ob03`S3~-tVPohc^au%Y!VjQm{!*)?+@V zltSFu;F0|~7O`WBAH&I7=%>bYPU>c#7W_~xelY3f)Hqm#nP)jR_IZDRtRN!PDfMo+ zIjGS>SJvPW^@25Y-Hbr2)%>*L#{=H8%?T;p8SoZMabdky1w6r$tm9r4@XD5L_$)Sz zfM~7p$9@rDg|su++N8PM1yF49TxFR(mSG%iE5o^5vVqiaGb?F4!A%|dgy2TLNcGYlDiH>zHD4^3Av%3mp&N2@m~I z(qq5WGGAmowukVfy+n@fruGLmM9s3ZCCWow<>6Z{Egx*0me1Kb;fb9R9_^LJ{jrOS zZ@%e3;k4aGae?L4cDCjJ9U1L)ItA1Pk0>8zY1Q@k1^Z@Wg-0AqZc_A+U;S;diq5#s zvla;pKJQx3nj=MIS;S2RwEiMIB!~lO4*`zqmOEIA3TIr$lub@u>a|Q-cs`x^uNfTt z&QT^udd;hGA7)xE(p%1gOX}cDdedg?-+#~KNQ-*qnNqpPlWmm4AS)MXmFubG+384M zzNu>l2fyXI1L=c*I5_yT2Q4mX>O#1z#};hdeapdv^d8}jwYa3IAK_9?y57(BnjC5A zqK~yZo}y+l>1;+MY-civ42E2SlXgx-OK4stw4U%mc+C_(wi$Y%b+}0 z7N)JsahgY`Jc^HPMgtI5PZ9v#?vX!Ba>Jy2w)fRxEOm@&@X#R4{_3GYn9cT+o(2cA z?OuwktGpCpcB@})KGIa8FoVZ6>)rrnj-J?K$Ld6q^yC5x?##H+gM)t^7##fZe3A0> z!EXU?i|{b7badBNoUgsxc%;Q_-G7boNQ+r}*fk@|C2%|Te3K)+=}y1RKzcW3tcyNx za-{d5OVQgSEzRBmP01C;C8Q*-&r9TcLS}mg?<(WXy4Q4m z_)ie`WyT|Y@DEWpm{qw*E8K219(80uBG2k%NbO?Pku%UVNU3_OSb|-00qNFhj~J z_vEr9@$K%x;N|=FZrQng&z@~tu?SvhZWXazR*rEXPqIiegGF#xju{UH^J&bWq>j^n zAMm8_;*vaPZp1fc(cD;)GR=4hJk&?N45_S-IdLibHHsrW6bXtZ(oRH#E6iTHii= zzZ`XQQ$EsK&KsPZyI=Z&A6rRl*)NUd4u?O&cUY2^DL9QI(^eh0Ja}K0lqkovRWF(c z^wJ`EUF!9MUs8`!@a95cq0z$yMJnNPKhl+KqVe!Ne;CFY6iW|v!0KlaMnx{tQg%)& z$!mEf?(Z}?(pq+h1Iir>z4O(Nqz~NzL-KlyOM2WR82qj_9_bmFH{Abe~}4g_f}!k1*s+)QEwi)U2D^WUjW}{oE=v;M?w%_E z%uz0PneRf(e66>e%sek9>nuXTaVD43eo$mKl<~yMv+HB#fs8T8jeRW`z|l z=?(Y!!#U7XGT0j*=cCKqXWMNe{2$k8&4@W2!EmGoBZvbd!6dtAT+y#Yh> z+9k##t@S{CHz<>?}!qyL-~w@>Y`Q%`cbxW2Ck#mpR5NKj2v`>zST4 zO$xyDu&J=YTTUrr>24-$a>6S=z?40&<4ohpw_HqT_s?MrHXD!h9`wj$cIs&6C6bi8 z=us@FpJH)I%gV;7D3e^IRh2H^kSFDIZK)mSg_Z3XbR0D6r6*K$i3yT~y8{TBgz>c1 z&?O{$LX)(9J7|)=6sCjFB(3QoT@({ux4K0y@}BkyrtmqDs-diiymXlJKO?1+7^n!Cmdn=WwL4jyex^q*?D^gOsdbgLIK}0IZnq^%HlpuJ;r7#U}O8 z9iDZnu^xNSyE8z9?(7D8nq&p9YhGef;l?dlLAjtBE!Qvnz)senU!3T2>sG<*Ezud| zQn;W8cfS=-LXDK?XnB`9dn0Mp`x{Lz;=MnP+kv*7`*q`y-ueN&lkzLZBfX;=Ys=0G zkk)llXHX;F^%gheJp^MbSCZZWteqZWyd92~^d5WAcq~iZf8t@0bBss&U|6IE=^eO8 zPX)f~-(Wn_;uANx^djD$O^)du@;z8sj97A!mhFCS=aH85%1);d&*?O*?+<=q=|#Lj z4mf|1l(zIY(wp*E??y#Kjpc6*$xJLi>o}egYsN^2v6EUcx(^qTzJ$y z^=9C=^ppp^DbMMT`Vb!VqCAvKd13jW4=sz+i#mC+sssB62RpBFg}2Dp zVFmkRcro9zqrDi+He@5K@r!=0I?)Pm!nxebuwwRo07@>>>$|Yw;p9jk|1-bgL0aAr zP~UHHNz0yE;}?xb+KM2&&YfEa+Ey)HzI3(xy3!XPBbAutx>tFBk!AmyHxH8}7A0Yz zF%+yp?!6p%c8xmOLf^+P`! zMfX?#?k;b>k1$sFkor+@moYFlZu3jT$6Ai1U}oFsfD}lf=Zhj5e&KU0I#zH3_St5> zOFV}JEqj7NI>kHAA0 zl8bZ$IyLJ?TJ^limfGX|d}imq*A8_j?2r*6l4{X$Q$qr$kQoY#ZURjU;VJ z$9g{FTAi%x8;?3tljL+I=}CK8=Vx5QlkkWuwzYMClVhDEU)D|Y046jKhYf8*;La?7 zFG~a3Re7#`sb3ktsApnUd|vi9;$3;a@nx32B4xHdBhUMnIyWkk)E`$9SZ*%F1)Y7UtgVd69W(WeINZ3oR_c$14|Fv~37ogFLUp&8_2T-ohd2wAyE%kz0BTw^@a zl3wH2GI$qf@Xj_K>mkn`7N9e^NN+g{`EE8IY1M_(3-jImLKw-5OpY{lD_qt?1{*$m zLR#cHUT1L=9v1yheZ+Wr-Ve0MvE7)S3^+& z9{83^<wFQ zPu`Wj@QubJtwYjdG4F_P`g}>NoUx2M5vt7P(|~ zrT9gB!w|9QNVfoUJc&a({~Le8hO}0x&(b5U)l(i`to}2tMhNTY1j|I-}2%Z3+W*J+0x!eI`QISs=k97M{IJR_>@kr-^OFn5wS_;pn zV?!Q$FyqS03Ayz~diT$PkDZnWX?0I;G9GEGr14Z)XFGi0TP~JC6li6U-k+CS*O~&S zfMo9v_S9VO508vdr#Je3O@k0Te?c|(`>sybWxg?}`5*bosI;Oukinz4tZBppl;Xa?c~JZtEj1J(tcVjJ(fUV?5IRh&%HZ@Oh>p9DjfQ z)p*h1S;E61VMnj|DPA-PA4V?HJ;&e_(x;3^S|*e;O2(ty=C9znhE2vJEq+nmzs7Ml z@5A9~=U33Nkq@~O=K4UzlH*qmWiZ>dM^pqw3nF!L01` zM}0_7r(Rf3gO|l+Jq=$zJ*ktV$GWi$1}BjVPQJ;{SNeV|&_4sJ`mO@vLx+=#wCXJ6A&&Ai?m$cb=B*dnVU$-{ zWyT`16!Q#}6k(IM}6UF@oMEMuZ-LglwvpB}%eJvX9$#!b9e7)MMQD)oc zW7cq{U%?O-8YO(g(OhFS1|u)ZCYMFV_m?nTy2J4tEzQ|+eazdj*T0~F^p3l+_T-v{ zv`o$TUP;oDUZWcnn6{PF<>BrN&*YL53+*Cty;XY>NZ5BV&e1xvb83xv{jr=Jqpx>zq_xNX-sH%WgA7Oi(Rie_ z>D-9NJj5^JlWnBskOQAYBQ0_HH+W1(o7kntGFVetzFH@gUuUbX9;~PG0vJi!64&yG z&zKanzuaKJnS!*@2D$|htoWg`YxLmnh2~@Gf;Ecp+{r>KOlh${Wa7r<$N%72d6Swu z#j{WXwVPLY7U9+GS+Fi5)o_<*9b>An;-ZWXg?hB0q9*dLay)#?r7%T>)Y(zhTHJ=aOisS#Vp-*Fom>qk zy$ucmU0l+Ve>$$b{gdz_y>}{}bV9u~4@WD!$a6Z<#h7219O+G$`W+S0`m_{aEEj3j zg{yDGb9!Oj2WfeDl}iSs!-!0K&Q4Yph?52f4u6!Mpr8 zgejUj%E1aUq!c>A2@uZhf~W1BqSdYfP^at$IF?C%p4N&ySjlVrWz3T~PyNNlBYp7K zupRS3q=;U &X0>R<8%~(&XuO@zUg5E&;~F=;S(YbDf=WK$NVgw^o&QUWM|#tZ*k1dT@ksC9fcf!F#v{E4 zf8CnQnH|mg;4g8Pb}e0veTz0sdvdwgnsUd21bB`*2&OG~IsLJwlu|xWopv`;MLZ8W{=b?jh%&?j=LWQrCEZIWwLw}9@ zeo4X7gT{~dEk;@oT>r`PA+P0qklk!N(qgyx0zAqc{};d1MtTl(bw9=-xk$?r>O=5k z%P^tC8^-N1qzjxC4bITWJ4B4+Wt2Bowst`emIx7EeEwcgwQQZt}($VX`jH zEy9yTRnKqqiGnSHEz^TUC&6ev3hlK8iH?^9D2wmqhyx%h&(Tfr81mbUM_LSH5sf7m zX-iu;1No+QbqU^V1(KocXt)KK;Dr5CSV+6{yD zRfW9O6oQsW6cRigf>mUh^fd-E66z@EHubJShrc|v~rDK@F^RsA(#Ul zVrAEsc|UZ5bxxW?(&8X-r;M~XL&v|!;*u8K^6fp0D^3Y_21%=aoPl9_eIJ9tT4m{x zmZ`3+rpXoZ8qv0LF^_Gp@a;!h+xePUPEKqsyv2B=<;2#)R~nD>7R-70m=tME&lwmg zmz2R;%Hs0A!r95Oo(gAIU)D+DvTiJ^#&u;Dp6F6|rqdWpI-1;MSVB@c0S>xF}~kyHW3%>)sYoUo{x4|3LG=Cg1tH-E_lEOexF=cHhkZP>Htp4bM%H! z`{pC9D!w?DQ=Wqe(-G*+!?-9HX?bZhA44UrD&A>wV2?&J%O9k5y5aI=I;uxa4-XpHHpR`R1@TO!%F;OlR}b+;f8qPJ(cE&GB);Dr zbQMQSmADE-TAG9J`6X>hOKJm!d~=%+xA@|SVZfZO@xY#C^7dQ1Xf4XYP(03VnJ^-K z*q2Dbhteqc@GTeb^PY@N2=_WkHx8x9xp{)^MTLaxB!xZT&VN3b^7HN48NBLHZOIqH;A^FQinq?9m^HcR` zzOnh%8S^_#C1Sqo5e3B$pAN<#BnU4Dk1Nc96gqpyA%2JGXv0zHK|5CTmbT+8W@$`U z(%|zP0)vCN3yoEJl|MRlsMH2*fJ|PNrhOjYa#?}#y$l7fS5`vHP*3|vT69tx6U)i_ zi5J4{kc+hD^{SXBr&Kx9BF!?1WXPj`&vMEC5b{Y#(o&WV=lU?;P4@sdjz?NM)V8=R z@()TpP(?cbBmcAkX|WS!rz_IdqLv=ZU`=W~$xq5JdQR%$^d@rDAIqg3-IY)E0ljG( zss08^YL9RAT_2#5sbu*AKk1a-C?iO4aATqs#v~ErK*UhQdRiuxr+nJvNXwh(_y#r7 z^5!_cCxWzgjy|u1M$lFS;dSYMzo~z7n-zR2xG$9rNUQXUwX0;91;ZYSa#&rw) z^x*{SNud;3!N1|0WQCY{qn~&}Q&O(E!Haa;ZFQg_IGEmPQelo=?op%5eIbsKy0H?n zONxo*&xL2ZO?6m$uyPwubR=&vwfsF#=?=`Eq6_9G~|5SK^VIV}*wuSVzmd zt7oGUa*-C`*m^nRVo~6^c>HIPNO^kh!$|K^;h}7f?)@gxyUKW^Wl&`Kn6C_|vztwh zv~&u~7ytF+?kjJn$uaI~I3D~fI@0oR?Zj4-BP}|c31>|%)=l2R&jFk?bt`hr(?o#IV^tEk3H-$ z!9#k-!mR**%Un34K<`MSq+|ePq;{nyF7cZ@kncHe$;rB zlNU2hcXFg1dC0>G8g5P~`^lg*F{R-|3AijI4}>GcNMlqH2P7 zWQ}v#s3c;%6)_HSJV$GGH#r_aH50UEtvqQcb>;5xSxY`haAsi7nRW2qr13uMnXuck zX_34a#?kWEY@N%aLx%85BpP0OwNh z(hpce9m;}-j?mO{>GWYS;Df4j20&UzJlAQ-+w^OU>}V0WNS|{eR)<|Pla>X5`hPPy z(y{_QB02a<&5^iYm7%) z{*aRA$w`abcf6}SX{O6jUfb#2R`BUa5`Sj71($;G%*pNSill_M>A%yfBBe{%AR`XenTwYYakTHES8 zOE2QRDCW(CY2@UEG}~Duna6Qwd;O7?bonX((lh?Y`wXNdJ;R1Oy@YlZf0FIX_Of1M zp?=l3aC%lA^s79lXX;YoQm53B^&QJsdC-yaR9EKnx619i%o>Ps zdWl(s2U{a+fCke_1b@iPejdCM047nS=6>Fv6=UBF&had9o$5+|0P-*?1T(h2`4HMb zE-m*8S8jZhS4LmZzKL)4O^G9T`pK(RETPx@6m9YW;-^zrC398yUi|0X}Al0N)h=p%2i^hi@@ z!lm4CFTqFyzd$b1BF{f9A}w)6w{o%W*7U|>ofNCCZmg3vzR1CCYE`%CJ$`@`z?_f7 z1GfoIogRX@!%zPNgSbo*-`$8&bUa7zL^V$Tvhhgo+~n7gNy|&Gr$1-bVe>O zl3tGZ$2vciwETH#^LC3%`bvzM+%zFAt7ZH%B+{~4CS{U~w5*&NZ=k(RHT*uS^b`m! zvleJ*_CBRl`aVR_O0UzT@Nv3v^Jj=E5-t=kvh&^^anCUB@l6pIeOhD>zc%8oH11)C zMqJoek)5_P;$qGsTzf%qQil0fM6Kp6CQ-P@^YSMfFMo#T&3n1==DpqXjz7eB$Lj?UTZwklAg4ITv2+^gIt;(XidZEp0uQKJp3)WNK1OsesVEA`3D-V zO_08F4g4GQbGb-Mx}4|#e}#Psl$}+X?Y#slWFkNUNvhB!2&o7}Qd1^|RHZTy0trcE zPzWK60vX^z6rmkx1fI>pXwzuhIG{)?PKZ22h&&Ml1Vlt2pvYumw}>`~jnG0;Z|`rP zUEg2au-;iKxx4n6zB7Gi{Le9FxMMGnJ7dPd`am{j%QBxGdKm zgns<{;*41?yjPdTnBk7-5ogSBhyFmEG2>vJqZ#10OI-K`ru$)Mi8H2O)?v&X)~!EZ zTM9R(W<+hc?1$C}sJ=2w(2ry6HT!?qMvKt38kGu++?QI_Oa`uz;%+H?}i?eaR_r{f$rowal-iaU>4&SCv2I>;Q%yt zQ*cAyG(=IWeJ_(g4wVX(spp~Ujt)tT#Co=Fe@Cb1A=rNw_L$GnL~pv)ehOFYZD$!y zq4iCT@&7t^pHY72{`&3i8Vj4*c2VMD0^oyjEs6*dlRNyi;;!Ixf1h`a89Q9ciSKTZ zRnsG@zMrCUB8-??D@X7=H@<&68HLDN?^mYqmxe1hJc3A}`nd=)?TP@AjGG%HuUxGC z0o24_;)~@|2h`D>6%}j!p-0<=xRCyOMDpPTF%6ub`u z*A1@N1s6f49qLti!RiN%QCF@tJ02sk*0-yKVS`F27mTLJzDkiVI#wJ7A?EMlFD6IK zmD8o&;*1?GS7{c_i?fPt?NJSHO<{LO0iw=S4?~ecdmV5XYLJ4KQ`kR=0oCn=L-p%= z)P4$A>{&HwXAy{g*cf@`;L#{e7w24_M~X@h5pmy$c%G@mUGO@LY&>f>zVH!bW9c=F zc|pxVsLM3Q%P~5cb*ngIu1L(eT%0jyvEq*G$*rN=l^SUG+68#aytCoqM${taX3N95 zs&fb_oZ&k=cV)1mLh6ZO`4#F&MXw-P>V171`?H+B9g5u9zT>}e;1-&M#&~WwI?FSH zsu?dqeH{0KIAcC3>`fG77GcZ7a+l%ZRN_w@p71K3R4klvoXmurG;_O)yFcOgGvZbi zym}lKpbBS9zfU0ZXe@&=(wyv-ZRFOrPvg(VtY2uYtToMBb3xq2@pxu*rEWK~-$5of zzmFj$4gt{Yf@6jNhcLn6%k;L0`bQZx%NUQ-Z9cLw>dI2UP9?~22_L=i(O$TM*G|Hq z<}Pu@tJ^SVdPtmchm|9`VZ^ao;`vSPqe2m9^JUL^hk-p9GPI})KVmxjw zn)Bs~!#MWZAR~>_6vbE4W_#wJddE4d)}GBT@@uvKo7JwD)eiM{R1SdH2&jPO<&le$ z*K!H#`H&YqBaJav%Ey#68;4x;iaS;@Utrur2us9vLzR@oZ zUBU-y{#GP{#&|UnHoRyd;}EB#xT840Ax?0-i(v*W?@V!uK4=+|Q+SIrJGT=Dl^`Jk zKR@C}h|Sgq1xM8AvT2MX>foYeqN)8PIxhibTx6j6HkUQg$D~3fyM&OV!xZY(;j>WCVQ|affl=2_2q4a8lLO?C!x?=TY z!C*xu$2_f#rjE>^;c^+bq2)!K?I+yO*Y|_##k~vbsvDoeQr&jAeNVz9By=jKzXfwS zj;ld5#*PaEj5&DnROz`p(?iKWF|a+LC@=dZzF>M|z(9AX!oBQEut8Ih3vmhn0iBx7 z#CYsyv&S?Z{c5hU8MmTy{~LH3;}vK0^}V)5obe?mgZsHSV_sspHMBSf#KM<;8FIcZ zcgB_-O|h*s#h)rC*uc<0xP{sLnXLPyAb<0HS@*{jYE`O!RM%L_@IMzw;8_0zo`Jy=EaEE~|P1SG93ULlcf>t>A39k5!^;Y4M%n5*uQ!M!69re=#M{{t+QK|x_WGRcLwhu5k0%S(hfLI=cNP+Snh1U63_l@ zDRs_x#$Nbr30X;F+}4LWcaJ#Z_&m3?17pWUmk#edbgNI7wLjytcLE2kOk=$2XBd%{ zVlj@9+b8ADvNRo?vKSBU$*$IT@Wt8H8aJVsdZH-Mtrr~2>Lp&sryN(jwvR21a94^n z^!vS8q#wcreq%$Cy8Jd|?KbtDtjea&&4JA@MXw;KJF`eb%yUb{z%PyM*FXi{I#-8;9I{?5cg7)i za6AYT9q9cMdk`ERh)h8@zwLz_@sNTd>FdoIAbgS9_Fz(#o`2g5uznJX{_iE`f+@ka z2OGJ*-jtA7u_Z@8ijEwl?usG61DV#qA}X0scCkxTrdKkh#{ zR4~7V9vX!T`+_+T*#!zV{1&XB$zYt;iC(%^doaauuRX3&objoR%Mc{G=W)=?7_Isw zqcMjIW04XX;|15^^xzRe)r?o8YWeOL;}9RJg~m9NGQMz33UDMPxT2n7*z$9whFNw# z&W){ZP*2E^=os$EMF5VLQ7g9In(d9P64a*WliF3$D@a&VJz>&96TQG44p^M+SC8uJ z``KyYjMw}M6)FbFSZptt6QK#4j%AH7?gG2Lx?zHr5laxyvED=W#Bq6#JWP!`n(aU`#& zp{Ncn)7JYMi|UT7jxN2YvQ3Xv^a`>he~Y-7D`I>U^Wid1itK?swY`^cjOYI=1_yKH z*O+hHjr)o?I&iL$?uv{}roH2i2 zT96!Zgoo-#V;sd&B}zhdlm*9m|z80 zFg3vJW5pR$104Ks;*8gh#>}rYDdW}SQ9b`6cgB&X`^6bYT7rwTMECG;rp3M5gW1bE zEqCWQrSt{StD!l*b8)3tD|o@Rd8WgdPu0F$w3Bhj<>tbs0UR<0huiDttzC8U>d*_n zl$e8%pkZ)?{-EWe6w_VSZJFihvSYZtG$#wC6yzC!JcF6RWhI9S<~^mui%vGCl-q6_ z=q_dm4~a95QU226uJ~bU?AP`Zi|+6NFn=D&v@s#f3n-p|zo(s=g$* zo5WMB2;>WhYC_=(=H)?c8^js&9ID^7t8#pVlg8n6{S=FDH;Oanfp>omW6T+Z-=VW# z#^E;#&GmdJ4;C5s+>!^2jHeAppZ5{PYaIRCU&T3WWvw{dM`vGkhcqd3(=XFb&Us+@ zmA!PwLqt)bA5ERYBKZ*#bz4^GJyj*PT#>bx6#+&r@%svVoD@_)o&!C(%eCT+m%V~f zF|vZj_#7;f_}y7!*77Y^$el53rMSuy8INU49E-UlRCM)C3DozP)jyP426c&5zNhj% zOwk_lj6nV!6YXmiw=us3n(!%c#w$LC{u2EXjd83mlvdpD?!$SkXhp&2d8yok8%yTHo<6*15< zLX6TvY#$;97hO|miA@=Kcj-JU+m?-&;64o5@BUi@fkiltLlucqs`m#&> zVp1^fxuE)SbUa8Wjd94ZNStxV6WmdUEo|q8fBRHFDThA4R(mpqgQDWMwbflI=oM}+ zwp6a;D#FPntWp2G3VrNf=+s^$i0%2|y3g_$+db7sn=0L}Q=Gk3?$wtbNl~L8-&pBF zB^_^j#XS;rmM8XYN0zg)xWcB`A#S|$gQxzWervVgDEdKwj=pls{{&UL&dQUmYqTVL z@3R9IZBg-QxbS)JFYQ8H#1G9l@)^lS)_CSv%+rsNJL9;A;lITh$2|=2Ph-q)y!_RH zF)KkQDmab9TX_O>>A#6HUU5Zka~hv>VPD@}E9B0Yi@f(E#Wcp3V!@Ybq%n57$yo+g zM9C8O6Vd9a%txKaWQu6$P$GRE}-ikkdgfSfIf)53V>v<%|CP<_dRk znebg#;SN!7n-^5LL&a^qsKU)w9IaJR#!IGyj>I4j6=oK)zx7mc#xd^r{6KdjTOlh{ z5RI|q7w7O|Jae-+W2I@JyO>~JC(bw~wuN(e>xZD){FB@nv-mbI7#JSywnCB77}MR> zi^Ms+kyA3g#!N?RNpJ0eTCM&i3=m5G_)z?o!3d|=F~s3mDt!7A7)s*8xNJ6yUn$FmkM6?ewbtS~mGF^(oiuFl)oYa@^9S+=tG zh$X#?mM>hexaWvEZQ7x4(C_Kk^wVl;JJ2zLp~`tA*Yb{)s($P{1C%*KhM`h>3}wb0 zxW~RDP60?6J~vDp6(cc!pM5+zVk*eTpi*dz9WI8k>ps-8k^__4GbtupD+ke)Tjt-P z2HaCQ;7~ecxx^_f{M~sHLrUDe9vl7-iZf>0@sT!Twj*(6Eh;2>RuVBU&P5*J{kwbj zW-cvMfKVSrsLB^%6di$eKAl?_7?H8eHm%F$DN~o{WPNu9s#uhhKYL7EwDzYRusG&4 z?JvQpox9H|T)`)t3+^~^#ylIs|yjbJ3-7gbg|ZxhNt<07~|v))bSN;vSCC zB8~ApDAA?eLDh^MZfP7dX#2Yq(~aZDxf}!`Leo~>NT|**Sq!gd<1lVPxCeefaT||* z1c#Z>*V7pD6@&?B05rxNT~=@ECzc3wRT@!9zFCqF0{y@6b^O;GI(oO5$^%YLPvz}D z49aQbU&?Uf7sN#sdje@>yTdOHi=6gcNcU+bV=kmOeO2y^xscxUDRIW#OEKozO`LHz zM*6-+%GmMKrQPvllCKRi9{2I&j3XcaQ*jtaJ_Z-nG;(oEmOnG+6UhC_S>+WN#BFY< zre&BIHt-}DC8`Jj0U_DGIMsLv>^x~PZu(+s3gade`NCf*JYycJI`YGXE11bz(v?Xh zrYx@Z#+I{GdsK^B?f02%gu*3;)|+w`*{wR)Q~8R#RC~FEj}K=0jN6d4{y5H<7r*+0 zN@KpwH*3A*HfCCMJReaP%;FLk#T9b@N6Jkhk)zeK&nKcCeWandidG356qj5mdIg{; z7fmc2q9>*pK7edI^plyr#txVB&h}~T4CD_fWgEsdPY#?0lltty^#(R#7`fEP;hqNb zLvUga`n^72tYGMK?KJ-XLdM&p&{`{(0z(yX-c-Hqa4>z@rH-b!*7BGNF{gyAsKOf%kjC) z;rYrVdFr9GQ+bAuZz?AlkMS`Nq=d#?NN7HuuF~C6zv%0GrA)+)PsTCm7tmYN7@z$H zHc&1VXH1p3?GbSfThfcOJ$q5PYg}E4Jo!`R2~&&l=C+UIcoSt5>ob-6&u5WBS3f&% zxGj0YoR4FF$VvXvL~o7;A}@uDNWk4&*#;TH3`L(^0Nsi4aG}3=H=GMhobtbUT(Z^q%qvlTN=szL4b-6@c zZB7>>x6t7GbE{xV?>7jHxyv)DC>moHYv*UwrNP2O$ zm-ysxcS<}R0>xXay_7l8s-mxc>x!le7qGr*s((wz<L(TgB%*4_Nhua7tC_BU%O+2@QvZdO#PgZ3eQ;5lS6N$Y3g5;;vK*Z zmC(ccvh0!CP)3zyupJd7lQ+Ci$s7Lj!Xc@|OVF9Ptr~}JJ45b_6*Relcc`?Ze${G! z&9ZQRRT+Hkfj)Q+>d8H+z4m1BVBonhsnUi|e-dTzWo;9<3uCX%r|=XCBZPM-<1Gsv zj5ux`(9g=t`ucBHH|EP?4__m9#@uz@ypuR%hfCJs@krs`sKGSGd~e8uB;z67xk+ej z+0}-l=Kgo));4GtC*q7F2R|pyI10OPj!#LVJKl*D zs`S;Y;qO!ppImvPj1*ez_BJ&0TJ3L& zn{B49k#zMIc2JbJt8$(6L8_2lm4`SBRlQcSC|i!VyEY=+@1vkFr=T&O49z~}cyY!Y zPn$DlRr2kIRjvyOrEz%7;I7xi8B2I^42OQ$ob1l=2MgZ%7?6cw-*T z+vj>R;0mV7_dDEnci}HEGT%?`j5+O|h7nDb$$7ggdt8jSM=zIO z<2~=iyDHehVoQ4_0g6T}O@D9HY@oXcb21J^R%0abP(sLFwm zGUSj;ERsW`^>h~@3T{QKnuTUUV?6hl;4n0zF{VcIp$=n3M_2xwKOTLl4@x;lp|&56 zL1*R3JGYg4^6YMrQ!e4-n~3Y{3^(y&w3UvF#2KFqZ8-r|fyOx6!ad@Qqg@2Y=?w<} z^&KVRAYgQgT-9kFk=3hB&AFv=D1xp~5t}Ou2+#pE@{HeA7~#HBxPpg#G$(_`GvQ?C zGBh$?aSQyuAiu_xzGczC@Ys8LrNQ=0UBA0xFHz|igZi#W@lHxHwI=@N=(nXZp>y&o zA2`t!gRa~t3Ox{dyE4ZcCIJ;5MzY7`9M71V*Qd>m=c9=Ch+ZEfqk_4j?Uy`_Bf-c_ z8iyANzg3*WTaAQI!mx+NIJ%m3;v7z7ObO57D3x+&KT0M!-F=1{QL8s83!8v1!I9Fv zpbo|l*oDHtkbzYz35H_~tEDA(#htO0?})p&0ggGs3%OS{O&&*VNNP0Yal}~5!M5zy zqPHk_ON-;8JA}vwaZsrgvN*aMvB5!;%W(F?7a^~&mOJB8Mq*1y?p;JI4}sso;*1CV9{t<|amFK#0$1vvG4DY1gYm{}dtFXPkyV+Y@NCbv zX?K>3U5wLo?Ls!&9Dv z)$v!SjC0w<(PLJwS1j_duHV276=&g*Y{1j!b%P6lbiU$;IF-DH?Leu6%~dQifi*VIT0<@RW4zD1gs~>wK21FGa5gQv4SBJ*&A_>YK;4R znY|}t9D%m~mPS5=K@=NguUv==k=}GPw+8LwOm|KAg5%r#M;lQ8C* zs1FtyGn<#ZOMZ<<%*ZS^4*4J_6-4Lss8pjf)iX7=Z>>!IJxp#~`{pd5wN{Cav-$JjiXB-6iQi&Zs}&J2KB(3AY>d7)&%CVDskBE2UgKBhbUa`7=pXH( z2tfIJb+YQY1>)k|8gQIjdn&nSfiK0mwMU;3XY6oGYeB)(>SI$(x0dB8<{ah16FcR4 zcabrw=5koiN5&kWc#QcG;HHVbOT(qi?aa_tsfshlMZp~JO z+~y|9_FGlhptj0I5i`I^7-zY9A~TbmUIFb241Q8ou1+8S}oI z)imu=L~@#YbF6QwGQHki5-AEqH5#2L2J|%SxH*|qz~XGr+b+DVXUqZqp*P5#ajd;w zH_$IXUg01^a3M zvu_X=x+K!_j!a88T%rf6o|rrpH=LugyhWFk)73YT{wI@z~oT=G}5< zJmJzDnj3R2>UB=z{r;Ld!r1X^UyQA@{!XQ4N8mwfdevtML9y7oK9*yhgH%{uFZNEA zVDKes+Mv|&Wk|wy)`fa<(7&Jzu9SP@)<0s>dY(Arp{N~Gt`ld>vX}-zXsTS-i{cy} z>uDF-FpaT<7sqhuCnmhbufry%IJkus88beM8G0%9x~dai<_s#<_9nb?YkNkXPeDd+ zw08zQ5Bdfp*U8spZv>S@6;$0%r(%SWOD)N@UK>XM-d)+6K0s$fq2fXp<#9W*m$4&}VZjs;AG^M5* zuecOKmKtr$s{y@&ZybVMToDpDgbZ%&^tdLnzHiDnMKV^Gu}GmtbRC_Gl5DRql&}j0 zb_VK|+ZRi->u7tCJKJ;V!&j3U+dZl&PldBp*C(YsP**X^uAERj4O2Ko`W7AMNgi$B zNiGz<0zg3bA|vM)uHYeup~<6*r!gK3|E?*XS2#W0aHCiwbvBF;%yOE489|6ny*;eJPY9jq!;X;QNaLV}3d6y&hxM3h&n% zvsQ>(i!7|w-<|SxN;6kaK!KuiYpuMzQ*>mEZJ@&VKw)c0mza976-|!DSiz84I|KjK z_se+qD@RZ&P2cgJnd-mfOB_}~(?5JxHhtsXA7mjL^IQ1|S2JGZS-~Mw8QU0#e8CMo zo75Jqd;gTyxm1}sj#VyAzNTT(Fmegm!;6(Yb7YK@p&J<^e`##b5#Bzf9UI$ybf=Mb z2S^&W&cX1D-mm(2DJTYAz30H$d2x1~UD`X?GB|S>GSVnK{O*E4CIr=wDT{9suzfpg zz#ejE9JyN3VRxgh$C5I17mYFZ%6!ee@z~GiaUf$Z@%t+^%b-LmJjWNMSmL!GZjs0@ z^kCHaDOsAXdmD3{Xg#2#T>+UAw{WX_T+^#fBNG`yJFcH|<(**Fb;&)cc$uz^~X3&pPh5D@M?_48ZCysl^4QF3R@S%g0b zG3H~1{tCjFTFzfV7&Bh0YGcb3IX)9{)u(0x4^#rTy^(doIbOLAsdPk4$u>x`9*5X` zd0FJ(eI>{7OJn=_Kgg9u1N!GmS!Dq+=KqW-+~x-AB&v9KN@4l&yiMFyjxgr z%jAtz@;2X-|L^W`FmI5)5&@r_d)Qh_#+m-FZ3O zD@`=2KB^oSp*CUEOJls67hu0zoN=t=ohQy%L6a-Fxg4uO@rOY!@ z$g{o?4FgcQg!MDo$e0&>h*e%n%*Fovz4K!PW4o7HJ3?x0S_bMTRX?WoZUbi2*HB>_yh;%UE1#&48#^9oixV0+0h>m z8?Q#I@tr`%Y_mS&VXUlVXgJ0hw|>@VW)0gzHLUZVY%ip!uPb+FmDvJoSRB5`bgc6v z1_`GHhn_7p$5_G8mHGr3_iqke(u64qO)y&av}OA(~lpZyZnL7+=$jAP&feMe)=I>a#8o;%_jsHoQ6 zDJJCMInCz5)wise*|2C`kwcjxsNBL2tjE31fDi%jrmk>JlaD3(aw zMUeieOdaQvEoj2>B57=Y+P|bU#&#dlbWxh#lm@xMII3TRTbipfuS;!^OGq;TK2T|B zBJ`_@H29^lJs*c3w?Uk7R8^=&8e@kM5>A6feQu+Km2>YD8u?Yd*M7$cP-(dy5}^=iZ({q>z{f;6H zerasaqmq-Bh%;s#-DjORV}}tE&VXHgexrnySr&z6{hGM_`ZWj=Ku=U9Y?){;irMz3 z9g%I`I7$!hF;&s?8;Gt}Uyu@^{_Z!Y;kpXM$WEcTErn`QWO9syetdr88{*iHG$UYn z5odcorQw@}jro)YujHpO=HEW1ZR~I{XNadZLiWQ_c1rmPL|wUa?>JnG)Z4HWGDLBO z&1}06rvMPpS&09+!WBFdf9`RfIOAn-GYXkTW4r|2o43o27r&O<<;EO@FTP2BjVaU8 zZgIwz6ICd_w5l)5G*8kB;lMt^o!Pe<`UtKjHlw>g2pZXagz;QN>zfaa*)NP*Dshad zFZ`zzF>HCDRx$_*C9`YP=S;qUGmuXUtT&l^ZivUKucEs>VW_(imGNr4Z`2 zRzI#Wg_Y}DQ8y^R9*o{z3dcYf$wfq@1I|$W?|20%#2OHd@t*&gsWE0st&)vDdM8p? zYMODR3T=$Wn5h~wN}MrMNSTzv=wRNLDTGF0LW6V@Bei~z@P#hMjct2{b{{BoM zG)3I`URjL>6?-=0bGHhE5E{9}?_rpyt}a}`vE4IXoUwu-7cUpHIo6NQxT%bPXk`q2 zB!e$a;tk??16KWp$Wrc=;Ep%R!8I~r_6qxwJ7x&&&v_jx^>}f{GbUrEj3FqEanlI& z)+IBA`}+P4dA06ijCtWaRMQ*j(-;@dq1w)lDU`8gqPs|W^nh^) zE4A8sG*)UmLfsfE|SpFdk z>W{ccdGrS-X3DAjk#Z^j{**6Q8rlcmGCYJK+r3hzFC&!l_Sfu7?wB*Q=iA()W{WfC z+uVDg+-Z!PP#-6qCr%it{VB@)W8{oWIe$_dQ{MSWrMw+uTe@S)Ll&f5T%T`cr;%DZTyQF6G14 zC}q0n1+JOD*qfqWY~P=;r9I1;DWNfDIS+nWoN*Jn27gU046QaCWgeZRaY^mf^lMzo z8S|9>GN&vd6S+uvjJ;Q7$`>o;LvLdm`%`|5($Ia^fRtlGK*O9GdRs}^?PL^7_iyZr zT-vjoc@-ax@e1UeZ!KyI2px9pa%Z!pfDNq8&pY zd`>yk{TsPs-3XbHL*mLJ`YEulpPYHLhvp}pl{+riA{(&f_4o$|WY7=>3>$2DJ&xj% z3vryEbp99t-HG3m3Rm#XP`ho$REe?W#Pqedw@3G{*H2NpcZT;%(IS4`u;g$6hDiHB;1B1@7KdM;Mx0i;lNvJ+ zE;F=FtZ-0y!BrM{=5i2&zWV5jGYtP@X|r++$5b`67Nv0gNW?tV5{Mg#o|U&izz#bGv@X0 zJ2P8hjL*3XO=G+`W6qTwhq?2f%N0pur<=YV2RjKrgKRwNB6Q=|D-L7JPS$a7&DKrQ zm|HAf*)v{W@{E25#BmcDsCUK(>@px{cU&;?>2G7cjp`G5#(VuM*1<6LrZIN;k?WTQ zdDU9f1M`hoRfn$lx$F%5)=$m0j6&fju$^D4d@kEmxbJQMbJ@ZfI( zU1i8!xyTxQV(iRZIu}(_2GP*O;QSH%qGRnJoEJP6t=^m8#tZ%(S92UDzs9^J@pntb z8OMeYnk z)%E+7i&#OE!)9k25>uNawn+{75$2+wT7>Tl@B88!Z)9edUT2>)Cb=I8cZ2-~ulkbUozmOXp_$k!-fN L-P_9czytpe!`;4g literal 0 HcmV?d00001 diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.pad b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.pad new file mode 100644 index 0000000..124dd5c --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.pad @@ -0,0 +1,353 @@ +PAD Specification File +*************************** + +PART TYPE: LCMXO640C +Performance Grade: 3 +PACKAGE: TQFP100 +Package Status: Final Version 1.17 + +Tue Aug 15 05:03:28 2023 + +Pinout by Port Name: ++-----------+----------+---------------+-------+------------------------------+ +| Port Name | Pin/Bank | Buffer Type | Site | Properties | ++-----------+----------+---------------+-------+------------------------------+ +| CROW[0] | 32/2 | LVCMOS33_IN | PB4C | SLEW:FAST PULL:UP | +| CROW[1] | 34/2 | LVCMOS33_IN | PB4E | SLEW:FAST PULL:UP | +| Din[0] | 21/3 | LVCMOS33_IN | PL10C | SLEW:FAST PULL:UP | +| Din[1] | 15/3 | LVCMOS33_IN | PL7B | SLEW:FAST PULL:UP | +| Din[2] | 14/3 | LVCMOS33_IN | PL5B | SLEW:FAST PULL:UP | +| Din[3] | 16/3 | LVCMOS33_IN | PL8C | SLEW:FAST PULL:UP | +| Din[4] | 18/3 | LVCMOS33_IN | PL9A | SLEW:FAST PULL:UP | +| Din[5] | 17/3 | LVCMOS33_IN | PL8D | SLEW:FAST PULL:UP | +| Din[6] | 20/3 | LVCMOS33_IN | PL10A | SLEW:FAST PULL:UP | +| Din[7] | 19/3 | LVCMOS33_IN | PL9C | SLEW:FAST PULL:UP | +| Dout[0] | 1/3 | LVCMOS33_OUT | PL2A | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[1] | 7/3 | LVCMOS33_OUT | PL3C | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[2] | 8/3 | LVCMOS33_OUT | PL3D | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[3] | 6/3 | LVCMOS33_OUT | PL3B | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[4] | 4/3 | LVCMOS33_OUT | PL2D | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[5] | 5/3 | LVCMOS33_OUT | PL3A | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[6] | 2/3 | LVCMOS33_OUT | PL2C | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[7] | 3/3 | LVCMOS33_OUT | PL2B | DRIVE:8mA SLEW:FAST PULL:UP | +| LED | 57/1 | LVCMOS33_OUT | PR10B | DRIVE:8mA SLEW:FAST PULL:UP | +| MAin[0] | 23/3 | LVCMOS33_IN | PL11C | SLEW:FAST PULL:UP | +| MAin[1] | 38/2 | LVCMOS33_IN | PB6B | SLEW:FAST PULL:UP | +| MAin[2] | 37/2 | LVCMOS33_IN | PB5D | SLEW:FAST PULL:UP | +| MAin[3] | 47/2 | LVCMOS33_IN | PB9C | SLEW:FAST PULL:UP | +| MAin[4] | 46/2 | LVCMOS33_IN | PB9A | SLEW:FAST PULL:UP | +| MAin[5] | 45/2 | LVCMOS33_IN | PB8D | SLEW:FAST PULL:UP | +| MAin[6] | 49/2 | LVCMOS33_IN | PB9D | SLEW:FAST PULL:UP | +| MAin[7] | 44/2 | LVCMOS33_IN | PB8C | SLEW:FAST PULL:UP | +| MAin[8] | 50/2 | LVCMOS33_IN | PB9F | SLEW:FAST PULL:UP | +| MAin[9] | 51/1 | LVCMOS33_IN | PR11D | SLEW:FAST PULL:UP | +| PHI2 | 39/2 | LVCMOS33_IN | PB6C | SLEW:FAST PULL:UP | +| RA[0] | 98/0 | LVCMOS33_OUT | PT2B | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[10] | 87/0 | LVCMOS33_OUT | PT5A | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[11] | 79/0 | LVCMOS33_OUT | PT9A | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[1] | 89/0 | LVCMOS33_OUT | PT4F | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[2] | 94/0 | LVCMOS33_OUT | PT3B | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[3] | 97/0 | LVCMOS33_OUT | PT2E | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[4] | 99/0 | LVCMOS33_OUT | PT2C | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[5] | 95/0 | LVCMOS33_OUT | PT3A | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[6] | 91/0 | LVCMOS33_OUT | PT3F | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[7] | 100/0 | LVCMOS33_OUT | PT2A | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[8] | 96/0 | LVCMOS33_OUT | PT2F | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[9] | 85/0 | LVCMOS33_OUT | PT6B | DRIVE:8mA SLEW:FAST PULL:UP | +| RBA[0] | 63/1 | LVCMOS33_OUT | PR7B | DRIVE:8mA SLEW:FAST PULL:UP | +| RBA[1] | 83/0 | LVCMOS33_OUT | PT7A | DRIVE:8mA SLEW:FAST PULL:UP | +| RCKE | 82/0 | LVCMOS33_OUT | PT7E | DRIVE:8mA SLEW:FAST PULL:UP | +| RCLK | 86/0 | LVCMOS33_IN | PT5B | SLEW:FAST PULL:UP | +| RDQMH | 76/0 | LVCMOS33_OUT | PT9F | DRIVE:8mA SLEW:FAST PULL:UP | +| RDQML | 61/1 | LVCMOS33_OUT | PR9B | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[0] | 64/1 | LVCMOS33_BIDI | PR6C | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[1] | 65/1 | LVCMOS33_BIDI | PR6B | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[2] | 66/1 | LVCMOS33_BIDI | PR5D | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[3] | 67/1 | LVCMOS33_BIDI | PR5B | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[4] | 68/1 | LVCMOS33_BIDI | PR4D | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[5] | 69/1 | LVCMOS33_BIDI | PR4B | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[6] | 70/1 | LVCMOS33_BIDI | PR3D | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[7] | 71/1 | LVCMOS33_BIDI | PR3B | DRIVE:8mA SLEW:FAST PULL:UP | +| UFMCLK | 58/1 | LVCMOS33_OUT | PR10A | DRIVE:8mA SLEW:FAST PULL:UP | +| UFMSDI | 56/1 | LVCMOS33_OUT | PR10C | DRIVE:8mA SLEW:FAST PULL:UP | +| UFMSDO | 55/1 | LVCMOS33_IN | PR10D | SLEW:FAST PULL:UP | +| nCCAS | 27/2 | LVCMOS33_IN | PB2C | SLEW:FAST PULL:UP | +| nCRAS | 43/2 | LVCMOS33_IN | PB8B | SLEW:FAST PULL:UP | +| nFWE | 22/3 | LVCMOS33_IN | PL11A | SLEW:FAST PULL:UP | +| nRCAS | 78/0 | LVCMOS33_OUT | PT9C | DRIVE:8mA SLEW:FAST PULL:UP | +| nRCS | 77/0 | LVCMOS33_OUT | PT9E | DRIVE:8mA SLEW:FAST PULL:UP | +| nRRAS | 73/1 | LVCMOS33_OUT | PR2B | DRIVE:8mA SLEW:FAST PULL:UP | +| nRWE | 72/1 | LVCMOS33_OUT | PR2D | DRIVE:8mA SLEW:FAST PULL:UP | +| nUFMCS | 53/1 | LVCMOS33_OUT | PR11C | DRIVE:8mA SLEW:FAST PULL:UP | ++-----------+----------+---------------+-------+------------------------------+ + +Vccio by Bank: ++------+-------+ +| Bank | Vccio | ++------+-------+ +| 0 | 3.3V | +| 1 | 3.3V | +| 2 | | +| 3 | 3.3V | ++------+-------+ + +Vref by Bank: ++------+-----+-----------------+---------+ +| Vref | Pin | Bank # / Vref # | Load(s) | ++------+-----+-----------------+---------+ ++------+-----+-----------------+---------+ + +Pinout by Pin Number: ++----------+---------------------+------------+---------------+-------+---------------+ +| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | ++----------+---------------------+------------+---------------+-------+---------------+ +| 1/3 | Dout[0] | LOCATED | LVCMOS33_OUT | PL2A | | +| 2/3 | Dout[6] | LOCATED | LVCMOS33_OUT | PL2C | | +| 3/3 | Dout[7] | LOCATED | LVCMOS33_OUT | PL2B | | +| 4/3 | Dout[4] | LOCATED | LVCMOS33_OUT | PL2D | | +| 5/3 | Dout[5] | LOCATED | LVCMOS33_OUT | PL3A | | +| 6/3 | Dout[3] | LOCATED | LVCMOS33_OUT | PL3B | | +| 7/3 | Dout[1] | LOCATED | LVCMOS33_OUT | PL3C | | +| 8/3 | Dout[2] | LOCATED | LVCMOS33_OUT | PL3D | | +| 9/3 | unused, PULL:UP | | | PL4A | | +| 11/3 | unused, PULL:UP | | | PL4C | | +| 13/3 | unused, PULL:UP | | | PL4D | | +| 14/3 | Din[2] | LOCATED | LVCMOS33_IN | PL5B | GSR_PADN | +| 15/3 | Din[1] | LOCATED | LVCMOS33_IN | PL7B | | +| 16/3 | Din[3] | LOCATED | LVCMOS33_IN | PL8C | TSALLPAD | +| 17/3 | Din[5] | LOCATED | LVCMOS33_IN | PL8D | | +| 18/3 | Din[4] | LOCATED | LVCMOS33_IN | PL9A | | +| 19/3 | Din[7] | LOCATED | LVCMOS33_IN | PL9C | | +| 20/3 | Din[6] | LOCATED | LVCMOS33_IN | PL10A | | +| 21/3 | Din[0] | LOCATED | LVCMOS33_IN | PL10C | | +| 22/3 | nFWE | LOCATED | LVCMOS33_IN | PL11A | | +| 23/3 | MAin[0] | LOCATED | LVCMOS33_IN | PL11C | | +| 27/2 | nCCAS | LOCATED | LVCMOS33_IN | PB2C | | +| 32/2 | CROW[0] | LOCATED | LVCMOS33_IN | PB4C | | +| 34/2 | CROW[1] | LOCATED | LVCMOS33_IN | PB4E | | +| 36/2 | unused, PULL:UP | | | PB5B | PCLKT2_1 | +| 37/2 | MAin[2] | LOCATED | LVCMOS33_IN | PB5D | | +| 38/2 | MAin[1] | LOCATED | LVCMOS33_IN | PB6B | PCLKT2_0 | +| 39/2 | PHI2 | LOCATED | LVCMOS33_IN | PB6C | | +| 43/2 | nCRAS | LOCATED | LVCMOS33_IN | PB8B | | +| 44/2 | MAin[7] | LOCATED | LVCMOS33_IN | PB8C | | +| 45/2 | MAin[5] | LOCATED | LVCMOS33_IN | PB8D | | +| 46/2 | MAin[4] | LOCATED | LVCMOS33_IN | PB9A | | +| 47/2 | MAin[3] | LOCATED | LVCMOS33_IN | PB9C | | +| 49/2 | MAin[6] | LOCATED | LVCMOS33_IN | PB9D | | +| 50/2 | MAin[8] | LOCATED | LVCMOS33_IN | PB9F | | +| 51/1 | MAin[9] | LOCATED | LVCMOS33_IN | PR11D | | +| 52/1 | unused, PULL:UP | | | PR11B | | +| 53/1 | nUFMCS | LOCATED | LVCMOS33_OUT | PR11C | | +| 54/1 | unused, PULL:UP | | | PR11A | | +| 55/1 | UFMSDO | LOCATED | LVCMOS33_IN | PR10D | | +| 56/1 | UFMSDI | LOCATED | LVCMOS33_OUT | PR10C | | +| 57/1 | LED | LOCATED | LVCMOS33_OUT | PR10B | | +| 58/1 | UFMCLK | LOCATED | LVCMOS33_OUT | PR10A | | +| 59/1 | unused, PULL:UP | | | PR9D | | +| 61/1 | RDQML | LOCATED | LVCMOS33_OUT | PR9B | | +| 63/1 | RBA[0] | LOCATED | LVCMOS33_OUT | PR7B | | +| 64/1 | RD[0] | LOCATED | LVCMOS33_BIDI | PR6C | | +| 65/1 | RD[1] | LOCATED | LVCMOS33_BIDI | PR6B | | +| 66/1 | RD[2] | LOCATED | LVCMOS33_BIDI | PR5D | | +| 67/1 | RD[3] | LOCATED | LVCMOS33_BIDI | PR5B | | +| 68/1 | RD[4] | LOCATED | LVCMOS33_BIDI | PR4D | | +| 69/1 | RD[5] | LOCATED | LVCMOS33_BIDI | PR4B | | +| 70/1 | RD[6] | LOCATED | LVCMOS33_BIDI | PR3D | | +| 71/1 | RD[7] | LOCATED | LVCMOS33_BIDI | PR3B | | +| 72/1 | nRWE | LOCATED | LVCMOS33_OUT | PR2D | | +| 73/1 | nRRAS | LOCATED | LVCMOS33_OUT | PR2B | | +| 76/0 | RDQMH | LOCATED | LVCMOS33_OUT | PT9F | | +| 77/0 | nRCS | LOCATED | LVCMOS33_OUT | PT9E | | +| 78/0 | nRCAS | LOCATED | LVCMOS33_OUT | PT9C | | +| 79/0 | RA[11] | LOCATED | LVCMOS33_OUT | PT9A | | +| 82/0 | RCKE | LOCATED | LVCMOS33_OUT | PT7E | D7 | +| 83/0 | RBA[1] | LOCATED | LVCMOS33_OUT | PT7A | D6 | +| 85/0 | RA[9] | LOCATED | LVCMOS33_OUT | PT6B | PCLKT0_1 | +| 86/0 | RCLK | LOCATED | LVCMOS33_IN | PT5B | PCLKT0_0 | +| 87/0 | RA[10] | LOCATED | LVCMOS33_OUT | PT5A | | +| 89/0 | RA[1] | LOCATED | LVCMOS33_OUT | PT4F | | +| 91/0 | RA[6] | LOCATED | LVCMOS33_OUT | PT3F | D3 | +| 94/0 | RA[2] | LOCATED | LVCMOS33_OUT | PT3B | | +| 95/0 | RA[5] | LOCATED | LVCMOS33_OUT | PT3A | | +| 96/0 | RA[8] | LOCATED | LVCMOS33_OUT | PT2F | D2 | +| 97/0 | RA[3] | LOCATED | LVCMOS33_OUT | PT2E | | +| 98/0 | RA[0] | LOCATED | LVCMOS33_OUT | PT2B | D1 | +| 99/0 | RA[4] | LOCATED | LVCMOS33_OUT | PT2C | | +| 100/0 | RA[7] | LOCATED | LVCMOS33_OUT | PT2A | | +| PB2A/2 | unused, PULL:UP | | | PB2A | | +| PB2B/2 | unused, PULL:UP | | | PB2B | | +| PB2D/2 | unused, PULL:UP | | | PB2D | | +| PB3A/2 | unused, PULL:UP | | | PB3A | | +| PB3B/2 | unused, PULL:UP | | | PB3B | | +| PB3C/2 | unused, PULL:UP | | | PB3C | | +| PB3D/2 | unused, PULL:UP | | | PB3D | | +| PB4A/2 | unused, PULL:UP | | | PB4A | | +| PB4B/2 | unused, PULL:UP | | | PB4B | | +| PB4D/2 | unused, PULL:UP | | | PB4D | | +| PB4F/2 | unused, PULL:UP | | | PB4F | | +| PB5A/2 | unused, PULL:UP | | | PB5A | | +| PB5C/2 | unused, PULL:UP | | | PB5C | | +| PB6A/2 | unused, PULL:UP | | | PB6A | | +| PB6D/2 | unused, PULL:UP | | | PB6D | | +| PB7A/2 | unused, PULL:UP | | | PB7A | | +| PB7B/2 | unused, PULL:UP | | | PB7B | | +| PB7C/2 | unused, PULL:UP | | | PB7C | | +| PB7D/2 | unused, PULL:UP | | | PB7D | | +| PB7E/2 | unused, PULL:UP | | | PB7E | | +| PB7F/2 | unused, PULL:UP | | | PB7F | | +| PB8A/2 | unused, PULL:UP | | | PB8A | | +| PB9B/2 | unused, PULL:UP | | | PB9B | | +| PB9E/0 | unused, PULL:UP | | | PB9E | | +| PL4B/3 | unused, PULL:UP | | | PL4B | | +| PL5A/3 | unused, PULL:UP | | | PL5A | | +| PL5C/3 | unused, PULL:UP | | | PL5C | | +| PL5D/3 | unused, PULL:UP | | | PL5D | | +| PL6A/3 | unused, PULL:UP | | | PL6A | | +| PL6B/3 | unused, PULL:UP | | | PL6B | | +| PL6C/3 | unused, PULL:UP | | | PL6C | | +| PL6D/3 | unused, PULL:UP | | | PL6D | | +| PL7A/3 | unused, PULL:UP | | | PL7A | | +| PL7C/3 | unused, PULL:UP | | | PL7C | | +| PL7D/3 | unused, PULL:UP | | | PL7D | | +| PL8A/3 | unused, PULL:UP | | | PL8A | | +| PL8B/3 | unused, PULL:UP | | | PL8B | | +| PL9B/3 | unused, PULL:UP | | | PL9B | | +| PL9D/3 | unused, PULL:UP | | | PL9D | | +| PL10B/3 | unused, PULL:UP | | | PL10B | | +| PL10D/3 | unused, PULL:UP | | | PL10D | | +| PL11B/3 | unused, PULL:UP | | | PL11B | | +| PL11D/3 | unused, PULL:UP | | | PL11D | | +| PR2A/1 | unused, PULL:UP | | | PR2A | | +| PR2C/1 | unused, PULL:UP | | | PR2C | | +| PR3A/1 | unused, PULL:UP | | | PR3A | | +| PR3C/1 | unused, PULL:UP | | | PR3C | | +| PR4A/1 | unused, PULL:UP | | | PR4A | | +| PR4C/1 | unused, PULL:UP | | | PR4C | | +| PR5A/1 | unused, PULL:UP | | | PR5A | | +| PR5C/1 | unused, PULL:UP | | | PR5C | | +| PR6A/1 | unused, PULL:UP | | | PR6A | | +| PR6D/1 | unused, PULL:UP | | | PR6D | | +| PR7A/1 | unused, PULL:UP | | | PR7A | | +| PR7C/1 | unused, PULL:UP | | | PR7C | | +| PR7D/1 | unused, PULL:UP | | | PR7D | | +| PR8A/1 | unused, PULL:UP | | | PR8A | | +| PR8B/1 | unused, PULL:UP | | | PR8B | | +| PR8C/1 | unused, PULL:UP | | | PR8C | | +| PR8D/1 | unused, PULL:UP | | | PR8D | | +| PR9A/1 | unused, PULL:UP | | | PR9A | | +| PR9C/1 | unused, PULL:UP | | | PR9C | | +| PT2D/0 | unused, PULL:UP | | | PT2D | | +| PT3C/0 | unused, PULL:UP | | | PT3C | | +| PT3D/0 | unused, PULL:UP | | | PT3D | | +| PT3E/0 | unused, PULL:UP | | | PT3E | | +| PT4A/0 | unused, PULL:UP | | | PT4A | | +| PT4B/0 | unused, PULL:UP | | | PT4B | | +| PT4C/0 | unused, PULL:UP | | | PT4C | | +| PT4D/0 | unused, PULL:UP | | | PT4D | | +| PT4E/0 | unused, PULL:UP | | | PT4E | | +| PT5C/0 | unused, PULL:UP | | | PT5C | | +| PT5D/0 | unused, PULL:UP | | | PT5D | | +| PT6A/0 | unused, PULL:UP | | | PT6A | | +| PT6C/0 | unused, PULL:UP | | | PT6C | | +| PT6D/0 | unused, PULL:UP | | | PT6D | | +| PT7B/0 | unused, PULL:UP | | | PT7B | | +| PT7C/0 | unused, PULL:UP | | | PT7C | | +| PT7D/0 | unused, PULL:UP | | | PT7D | | +| PT7F/0 | unused, PULL:UP | | | PT7F | | +| PT8A/0 | unused, PULL:UP | | | PT8A | | +| PT8B/0 | unused, PULL:UP | | | PT8B | | +| PT8C/0 | unused, PULL:UP | | | PT8C | | +| PT8D/0 | unused, PULL:UP | | | PT8D | | +| PT9B/0 | unused, PULL:UP | | | PT9B | | +| PT9D/0 | unused, PULL:UP | | | PT9D | | +| TCK/2 | | | | TCK | TCK | +| TDI/2 | | | | TDI | TDID0 | +| TDO/2 | | | | TDO | TDO | +| TMS/2 | | | | TMS | TMS | ++----------+---------------------+------------+---------------+-------+---------------+ + + +List of All Pins' Locate Preferences Based on Final Placement After PAR +to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): + +LOCATE COMP "CROW[0]" SITE "32"; +LOCATE COMP "CROW[1]" SITE "34"; +LOCATE COMP "Din[0]" SITE "21"; +LOCATE COMP "Din[1]" SITE "15"; +LOCATE COMP "Din[2]" SITE "14"; +LOCATE COMP "Din[3]" SITE "16"; +LOCATE COMP "Din[4]" SITE "18"; +LOCATE COMP "Din[5]" SITE "17"; +LOCATE COMP "Din[6]" SITE "20"; +LOCATE COMP "Din[7]" SITE "19"; +LOCATE COMP "Dout[0]" SITE "1"; +LOCATE COMP "Dout[1]" SITE "7"; +LOCATE COMP "Dout[2]" SITE "8"; +LOCATE COMP "Dout[3]" SITE "6"; +LOCATE COMP "Dout[4]" SITE "4"; +LOCATE COMP "Dout[5]" SITE "5"; +LOCATE COMP "Dout[6]" SITE "2"; +LOCATE COMP "Dout[7]" SITE "3"; +LOCATE COMP "LED" SITE "57"; +LOCATE COMP "MAin[0]" SITE "23"; +LOCATE COMP "MAin[1]" SITE "38"; +LOCATE COMP "MAin[2]" SITE "37"; +LOCATE COMP "MAin[3]" SITE "47"; +LOCATE COMP "MAin[4]" SITE "46"; +LOCATE COMP "MAin[5]" SITE "45"; +LOCATE COMP "MAin[6]" SITE "49"; +LOCATE COMP "MAin[7]" SITE "44"; +LOCATE COMP "MAin[8]" SITE "50"; +LOCATE COMP "MAin[9]" SITE "51"; +LOCATE COMP "PHI2" SITE "39"; +LOCATE COMP "RA[0]" SITE "98"; +LOCATE COMP "RA[10]" SITE "87"; +LOCATE COMP "RA[11]" SITE "79"; +LOCATE COMP "RA[1]" SITE "89"; +LOCATE COMP "RA[2]" SITE "94"; +LOCATE COMP "RA[3]" SITE "97"; +LOCATE COMP "RA[4]" SITE "99"; +LOCATE COMP "RA[5]" SITE "95"; +LOCATE COMP "RA[6]" SITE "91"; +LOCATE COMP "RA[7]" SITE "100"; +LOCATE COMP "RA[8]" SITE "96"; +LOCATE COMP "RA[9]" SITE "85"; +LOCATE COMP "RBA[0]" SITE "63"; +LOCATE COMP "RBA[1]" SITE "83"; +LOCATE COMP "RCKE" SITE "82"; +LOCATE COMP "RCLK" SITE "86"; +LOCATE COMP "RDQMH" SITE "76"; +LOCATE COMP "RDQML" SITE "61"; +LOCATE COMP "RD[0]" SITE "64"; +LOCATE COMP "RD[1]" SITE "65"; +LOCATE COMP "RD[2]" SITE "66"; +LOCATE COMP "RD[3]" SITE "67"; +LOCATE COMP "RD[4]" SITE "68"; +LOCATE COMP "RD[5]" SITE "69"; +LOCATE COMP "RD[6]" SITE "70"; +LOCATE COMP "RD[7]" SITE "71"; +LOCATE COMP "UFMCLK" SITE "58"; +LOCATE COMP "UFMSDI" SITE "56"; +LOCATE COMP "UFMSDO" SITE "55"; +LOCATE COMP "nCCAS" SITE "27"; +LOCATE COMP "nCRAS" SITE "43"; +LOCATE COMP "nFWE" SITE "22"; +LOCATE COMP "nRCAS" SITE "78"; +LOCATE COMP "nRCS" SITE "77"; +LOCATE COMP "nRRAS" SITE "73"; +LOCATE COMP "nRWE" SITE "72"; +LOCATE COMP "nUFMCS" SITE "53"; + + + + + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:28 2023 + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.par b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.par new file mode 100644 index 0000000..ac4e203 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.par @@ -0,0 +1,225 @@ + +Lattice Place and Route Report for Design "RAM2GS_LCMXO640C_impl1_map.ncd" +Tue Aug 15 05:03:25 2023 + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir/5_1.ncd RAM2GS_LCMXO640C_impl1.prf +Preference file: RAM2GS_LCMXO640C_impl1.prf. +Placement level-cost: 5-1. +Routing Iterations: 6 + +Loading design for application par from file RAM2GS_LCMXO640C_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 3 +Loading device for application par from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +License checked out. + + +Ignore Preference Error(s): True +Device utilization summary: + + PIO (prelim) 67/159 42% used + 67/74 90% bonded + SLICE 71/320 22% used + + + +Number of Signals: 262 +Number of Connections: 662 + +Pin Constraint Summary: + 67 out of 67 pins locked (100% locked). + +The following 2 signals are selected to use the primary clock routing resources: + RCLK_c (driver: RCLK, clk load #: 40) + PHI2_c (driver: PHI2, clk load #: 13) + +The following 1 signal is selected to use the secondary clock routing resources: + nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0) + +No signal is selected as Global Set/Reset. +Starting Placer Phase 0. +......... +Finished Placer Phase 0. REAL time: 0 secs + +Starting Placer Phase 1. +......... +Placer score = 1223575. +Finished Placer Phase 1. REAL time: 3 secs + +Starting Placer Phase 2. +. +Placer score = 1220793 +Finished Placer Phase 2. REAL time: 3 secs + + +------------------ Clock Report ------------------ + +Global Clock Resources: + CLK_PIN : 1 out of 4 (25%) + General PIO: 1 out of 160 (0%) + +Global Clocks: + PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT5B)", clk load = 40 + PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB6C)", clk load = 13 + SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB8B)", clk load = 7, ce load = 0, sr load = 0 + + PRIMARY : 2 out of 4 (50%) + SECONDARY: 1 out of 4 (25%) + +--------------- End of Clock Report --------------- + + +I/O Usage Summary (final): + 67 out of 159 (42.1%) PIO sites used. + 67 out of 74 (90.5%) bonded PIO sites used. + Number of PIO comps: 67; differential: 0. + Number of Vref pins used: 0. + +I/O Bank Usage Summary: ++----------+----------------+------------+------------+------------+ +| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | ++----------+----------------+------------+------------+------------+ +| 0 | 18 / 18 (100%) | 3.3V | - | - | +| 1 | 18 / 21 ( 85%) | 3.3V | - | - | +| 2 | 13 / 14 ( 92%) | - | - | - | +| 3 | 18 / 21 ( 85%) | 3.3V | - | - | ++----------+----------------+------------+------------+------------+ + +Total placer CPU time: 3 secs + +Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd. + +0 connections routed; 662 unrouted. +Starting router resource preassignment +WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew. +WARNING - par: The driver of secondary clock net nCRAS_c is not placed on one of the PIO sites dedicated for secondary clocks. This secondary clock will be routed through general routing resource and may suffer from excessive delay or skew. + +WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. + Signal=nCCAS_c loads=7 clock_loads=4 + +Completed router resource preassignment. Real time: 3 secs + +Start NBR router at 05:03:28 08/15/23 + +***************************************************************** +Info: NBR allows conflicts(one node used by more than one signal) + in the earlier iterations. In each iteration, it tries to + solve the conflicts while keeping the critical connections + routed as short as possible. The routing process is said to + be completed when no conflicts exist and all connections + are routed. +Note: NBR uses a different method to calculate timing slacks. The + worst slack and total negative slack may not be the same as + that in TRCE report. You should always run TRCE to verify + your design. +***************************************************************** + +Start NBR special constraint process at 05:03:28 08/15/23 + +Start NBR section for initial routing at 05:03:28 08/15/23 +Level 1, iteration 1 +0(0.00%) conflict; 559(84.44%) untouched conns; 717961 (nbr) score; +Estimated worst slack/total negative slack: -9.776ns/-717.961ns; real time: 3 secs +Level 2, iteration 1 +7(0.03%) conflicts; 496(74.92%) untouched conns; 699022 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-699.022ns; real time: 3 secs +Level 3, iteration 1 +9(0.03%) conflicts; 252(38.07%) untouched conns; 765745 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-765.746ns; real time: 3 secs +Level 4, iteration 1 +9(0.03%) conflicts; 0(0.00%) untouched conn; 781820 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-781.821ns; real time: 4 secs + +Info: Initial congestion level at 75% usage is 0 +Info: Initial congestion area at 75% usage is 0 (0.00%) + +Start NBR section for normal routing at 05:03:29 08/15/23 +Level 4, iteration 1 +5(0.02%) conflicts; 0(0.00%) untouched conn; 781048 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-781.049ns; real time: 4 secs +Level 4, iteration 2 +4(0.01%) conflicts; 0(0.00%) untouched conn; 780690 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-780.691ns; real time: 4 secs +Level 4, iteration 3 +4(0.01%) conflicts; 0(0.00%) untouched conn; 780715 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-780.716ns; real time: 4 secs +Level 4, iteration 4 +2(0.01%) conflicts; 0(0.00%) untouched conn; 780715 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-780.716ns; real time: 4 secs +Level 4, iteration 5 +2(0.01%) conflicts; 0(0.00%) untouched conn; 783401 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 4 secs +Level 4, iteration 6 +0(0.00%) conflict; 0(0.00%) untouched conn; 783401 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 4 secs + +Start NBR section for performance tuning (iteration 1) at 05:03:29 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 783401 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 4 secs + +Start NBR section for re-routing at 05:03:29 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 776978 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-776.979ns; real time: 4 secs + +Start NBR section for post-routing at 05:03:29 08/15/23 + +End NBR router with 0 unrouted connection + +NBR Summary +----------- + Number of unrouted connections : 0 (0.00%) + Number of connections with timing violations : 260 (39.27%) + Estimated worst slack : -9.822ns + Timing score : 909228 +----------- +Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. + + + +WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. + Signal=nCCAS_c loads=7 clock_loads=4 + +Total CPU time 4 secs +Total REAL time: 4 secs +Completely routed. +End of route. 662 routed (100.00%); 0 unrouted. + +Hold time timing score: 0, hold timing errors: 0 + +Timing score: 909228 + +Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd. + + +All signals are completely routed. + + +PAR_SUMMARY::Run status = Completed +PAR_SUMMARY::Number of unrouted conns = 0 +PAR_SUMMARY::Worst slack> = -9.822 +PAR_SUMMARY::Timing score> = 909.228 +PAR_SUMMARY::Worst slack> = 0.273 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Number of errors = 0 + +Total CPU time to completion: 4 secs +Total REAL time to completion: 4 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1_par.asd b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1_par.asd new file mode 100644 index 0000000..676f553 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1_par.asd @@ -0,0 +1,42 @@ +[ActiveSupport PAR] +; Global primary clocks +GLOBAL_PRIMARY_USED = 2; +; Global primary clock #0 +GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c; +GLOBAL_PRIMARY_0_DRIVERTYPE = CLK_PIN; +GLOBAL_PRIMARY_0_LOADNUM = 40; +; Global primary clock #1 +GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c; +GLOBAL_PRIMARY_1_DRIVERTYPE = PIO; +GLOBAL_PRIMARY_1_LOADNUM = 13; +; # of global secondary clocks +GLOBAL_SECONDARY_USED = 1; +; Global secondary clock #0 +GLOBAL_SECONDARY_0_SIGNALNAME = nCRAS_c; +GLOBAL_SECONDARY_0_DRIVERTYPE = PIO; +GLOBAL_SECONDARY_0_LOADNUM = 9; +GLOBAL_SECONDARY_0_SIGTYPE = CLK; +; I/O Bank 0 Usage +BANK_0_USED = 18; +BANK_0_AVAIL = 18; +BANK_0_VCCIO = 3.3V; +BANK_0_VREF1 = NA; +BANK_0_VREF2 = NA; +; I/O Bank 1 Usage +BANK_1_USED = 18; +BANK_1_AVAIL = 21; +BANK_1_VCCIO = 3.3V; +BANK_1_VREF1 = NA; +BANK_1_VREF2 = NA; +; I/O Bank 2 Usage +BANK_2_USED = 13; +BANK_2_AVAIL = 14; +BANK_2_VCCIO = NA; +BANK_2_VREF1 = NA; +BANK_2_VREF2 = NA; +; I/O Bank 3 Usage +BANK_3_USED = 18; +BANK_3_AVAIL = 21; +BANK_3_VCCIO = 3.3V; +BANK_3_VREF1 = NA; +BANK_3_VREF2 = NA; diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/RAM2GS_LCMXO640C_impl1.par b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/RAM2GS_LCMXO640C_impl1.par new file mode 100644 index 0000000..cce2773 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/RAM2GS_LCMXO640C_impl1.par @@ -0,0 +1,28 @@ +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:25 2023 + +C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO640C_impl1.p2t +RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir +RAM2GS_LCMXO640C_impl1.prf -gui -msgset +D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml + + +Preference file: RAM2GS_LCMXO640C_impl1.prf. + +Level/ Number Worst Timing Worst Timing Run NCD +Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status +---------- -------- ----- ------ ----------- ----------- ---- ------ +5_1 * 0 -9.822 909228 0.273 0 04 Completed + +* : Design saved. + +Total (real) run time for 1-seed: 4 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.drc b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.drc new file mode 100644 index 0000000..ec074a2 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.drc @@ -0,0 +1 @@ +DRC detected 0 errors and 0 warnings. diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.jed b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.jed new file mode 100644 index 0000000..b2ff5f6 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.jed @@ -0,0 +1,1745 @@ + +* +NOTE JEDEC CREATED BY: Lattice Semiconductor Diamond Deployment Tool 3.12* +NOTE Version: Diamond (64-bit) 3.12.1.454* +NOTE Readback: Off* +NOTE Security: Off* +NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * +NOTE All Rights Reserved * +NOTE DATE CREATED: Tue Aug 15 05:03:33 2023 * +NOTE DESIGN NAME: RAM2GS * +NOTE DEVICE NAME: LCMXO640C-3TQFP100 * +NOTE PIN ASSIGNMENTS * +NOTE PINS RD[7] : 71 : inout * +NOTE PINS RD[6] : 70 : inout * +NOTE PINS RD[5] : 69 : inout * +NOTE PINS RD[4] : 68 : inout * +NOTE PINS RD[3] : 67 : inout * +NOTE PINS RD[2] : 66 : inout * +NOTE PINS RD[1] : 65 : inout * +NOTE PINS RD[0] : 64 : inout * +NOTE PINS Dout[7] : 3 : out * +NOTE PINS Dout[6] : 2 : out * +NOTE PINS Dout[5] : 5 : out * +NOTE PINS Dout[4] : 4 : out * +NOTE PINS Dout[3] : 6 : out * +NOTE PINS Dout[2] : 8 : out * +NOTE PINS Dout[1] : 7 : out * +NOTE PINS Dout[0] : 1 : out * +NOTE PINS LED : 57 : out * +NOTE PINS RBA[1] : 83 : out * +NOTE PINS RBA[0] : 63 : out * +NOTE PINS RA[11] : 79 : out * +NOTE PINS RA[10] : 87 : out * +NOTE PINS RA[9] : 85 : out * +NOTE PINS RA[8] : 96 : out * +NOTE PINS RA[7] : 100 : out * +NOTE PINS RA[6] : 91 : out * +NOTE PINS RA[5] : 95 : out * +NOTE PINS RA[4] : 99 : out * +NOTE PINS RA[3] : 97 : out * +NOTE PINS RA[2] : 94 : out * +NOTE PINS RA[1] : 89 : out * +NOTE PINS RA[0] : 98 : out * +NOTE PINS nRCS : 77 : out * +NOTE PINS RCKE : 82 : out * +NOTE PINS nRWE : 72 : out * +NOTE PINS nRRAS : 73 : out * +NOTE PINS nRCAS : 78 : out * +NOTE PINS RDQMH : 76 : out * +NOTE PINS RDQML : 61 : out * +NOTE PINS nUFMCS : 53 : out * +NOTE PINS UFMCLK : 58 : out * +NOTE PINS UFMSDI : 56 : out * +NOTE PINS PHI2 : 39 : in * +NOTE PINS MAin[9] : 51 : in * +NOTE PINS MAin[8] : 50 : in * +NOTE PINS MAin[7] : 44 : in * +NOTE PINS MAin[6] : 49 : in * +NOTE PINS MAin[5] : 45 : in * +NOTE PINS MAin[4] : 46 : in * +NOTE PINS MAin[3] : 47 : in * +NOTE PINS MAin[2] : 37 : in * +NOTE PINS MAin[1] : 38 : in * +NOTE PINS MAin[0] : 23 : in * +NOTE PINS CROW[1] : 34 : in * +NOTE PINS CROW[0] : 32 : in * +NOTE PINS Din[7] : 19 : in * +NOTE PINS Din[6] : 20 : in * +NOTE PINS Din[5] : 17 : in * +NOTE PINS Din[4] : 18 : in * +NOTE PINS Din[3] : 16 : in * +NOTE PINS Din[2] : 14 : in * +NOTE PINS Din[1] : 15 : in * +NOTE PINS Din[0] : 21 : in * +NOTE PINS nCCAS : 27 : in * +NOTE PINS nCRAS : 43 : in * +NOTE PINS nFWE : 22 : in * +NOTE PINS RCLK : 86 : in * +NOTE PINS UFMSDO : 55 : in * +NOTE CONFIGURATION MODE: NONE * +NOTE COMPRESSION: off * + + +QF130036* +G0* +F0* +L000000 +11111111001111111111011110111100111111111101111011110011111111110111101111111111 +11111111111011111111111111111111101111111111111111111110111111111111111111111011 +1111111111111111111011110011111111110101111011001111111111010111011111111111 +11111111111111111111111110111111111111111111111011111111111111111111101111111111 +11111111111011110011111111110111101111111111111111111110111100111111111101111011 +1111111111111111111011110011111111110101110111001111111111010111011111111111 +11111111001111111111011110111100111111111101111011110011111111110111101111001111 +11111101111011111111111111111111101111111111111111111110111111111111111111111011 +1111111111111111111011110011111111110101110111001111111111010111011111111111 +11111111111111111111111110111111111111111111111011111111111111111111101111001111 +11111101111011111111111111111111101111111111111111111110111111111111111111111011 +1111111111111111111011110011111111110101110111001111111111010111011111111111 +11111111111111111111110111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111100111111111100111111111111111110 +11111111111111111111111111111111111011111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111110 +11111111111111111111111111111111111011111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111110111111111111111101111111111111111111111111111111111111111 +11111111111111111111111110111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111011111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111110111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111110001111111111110111111111110111111111011111111111111 +11111111111111111111111111111111111111101111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111100011111110111111111110011111111011111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111001111111111111111111100111111111111 +11111111111111111111111111111111111111111111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111011111111111111111111111111111 +1111111111111111111111111111110111111111011111111111011111111101111111111111 +11111111111111111111111111111111111111111111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111110111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111101111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111001111111111111111111111111111111111111111111111111111111011111111111011111 +1111111111111111111111111111111111111111111111111111101111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111111111011111 +1111111111111111111111111111111111111110111111111111111111111011111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111110101111111111111111111010111111111111 +11111111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111011111111111110111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111101111111111111111 +1111111111111011111111111111111100111111101111111111111111111111111111111011 +11011111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111101101111111111111111 +1101111111111101101111111111100111011111111111011111111111111111111111111011 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111101111111111111111 +1111111111111110110111111111111101111111110101111011111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110101111111111111111 +1110111111111110111111111111111111111111101111101011111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111001111111101110111 +1111111011101010100011111111111111111110111100110111111111111111111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111000001111111110111 +1110011011011101100111101111111111111111111101100100100111111101111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111001111011011111111 +1111011011011101110101011111111111111111011011110011010111111111111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110001011011111110111 +1110111100010101110111111111111111111111111111110001110111111111111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110101111111111101111 +1110111111111111011011111111111111111111111111100011111111111101111110111011 +11011111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1110111111111111111101111111111001111111111111100011111111111111111111111011 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111011111011111111111111111111011111111111111111101111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111111111111111 +1110111111111111111011111111111101111111111111101011111111111111111110011110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111101111111 +1111101111111011111010111111111111101111011111110111111011111111111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111100000011101111111111111100101110111111111110111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111101111111111011111111 +1101100111011111111111011111111011111111011111011111111101011111111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111101111011111111101111111011101111111111111111111111111011111111111111111 +01111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111101111111111111111111111111111 +1101101111011111110110001111111110111011111111111111111010011111111111111011 +01011111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111011111111111 +1101101001111111101111010110111111011011111111111111111100011111111111111011 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111101101111111111110111111111111 +1111111111011111110111110110111111110111011111111111111111111111111111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111110111111111111111111111111111 +1110111111111111110111111100111111110101111111111111111111111111111111111111 +10111111111111111111111111111111111111111111010111111111111111111001011111111111 +11111111111111111111111111111111111111111111111101111111111111111111111011111111 +0011101111011101011111110111111111101101011111111111111111111111110111111101 +11111111111111111111111111111111111111111111110111111111111111111111011111111111 +11111111111111111111111111111111111111111111111111011111111111111111111101111111 +0110101001111111110111111110111101110111011111111111111111111110110111111111 +11111111111111111111111111111111111111111111111111111111111111111111011111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111001111011011111111111110111011111111111111111111111111111111111111111101 +11111111111111111111111111111111111111111111101111111111111111111100011111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111110 +1110001111111111111111111100111111111110111111111111111111111111101111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1110111111111111111001111010111110111111111111111111111011111111111111111111 +11011111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1110001111111111111111001011001111011111111111111111111101111111111101111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111101111111111111111111111110101110111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1110101111111111111111111110111111110111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111110111111111111111111011100111 +1111111111111011111111011110111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111101111111111111111101110111 +1111001111111101111011011100101001111111111111111111111111111111111111011111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111101111 +1101101111111111111111110111110111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1101101111111111111110111110111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111101111111111111111111111111 +1111111110111111111111111111101110111001111111111111111111011111110111111011 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111011111111111110111101001111111011111111111111110111111110111111011 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111011111111111111110100011101010101111111111111111111111110111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111011111111111111111111111111 +1111111111011111111111110100110101110111111111111111111111111111101111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111010101111111 +1111111111011111111111010111111111110111111111111111111111111111111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111011011101111111 +1111111011011111111011011100111111111111111111111100000111011111111110111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111110100011011111111 +1111111100011111111111111100111111101111111111111101110111111111111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111011111111111 +1111110111011111111110111111111111111111111111111111110011111111111110111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111101111111111111111111111111111111111111110101111011 +1111111111111111111111111011101111111111111100111111111011111111111111111011 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111011111111111111111111111111111111111111001111101 +1111111111111111111111111010101101111111111001111111111101111111111111111011 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +0111111111111111111111111111111001111111111111111111111111111111111111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111011 +1111111111111111111111111111010101111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111100101111111111111111111101110101111111111111111111111111111111101 +11111100111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111110001111111111111001101110111011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111101101111111110111010001111111111111111111111111111111111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111101111111110111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111011111011 +1111111111111111111111111111011111111111110111111111111110011111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111101111111 +0111111111111111111111110111111101111111100111111111111110011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111011 +1111111111111111111111111111111001111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110101111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111110 +1111111111111111111111111111011101111111101111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111011111111111111111111111111111 +1111111111101100111111111111010111111111111111111111111111101011111110111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111110110111 +1111110010011100111111111111101101110111111111111111111111101101111101111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111110111111111111111111111110100111 +1111110101011011011111111010111001111111101111111111111111110111111110011111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111011111 +1111111111000110111111111111011100111111111101111111111111101111111101111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111110111111100111111110111011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111100111111100001101110111110111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100010001111110011101111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111110111111111100111100101111011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111110111001111111111111111011110111 +1111111111110101101111111100111111111111111111111110111111110111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111011101111111111111011101101111 +1111111111111101110111111100111111111111111111111110100111111101111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111011111111110111111111111111 +1111111111111011111111110111111111111111111111111101110111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111110011111111111 +1111111111111111111111111111111111111111111111111111010111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111011111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111101111111111111111101110111111111111110011111011111111111111111011 +11011111111111111111111111111111111111111111111111111111111111111011011111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111101101111111111111010011111111111111111111111011 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111110111111111111111101000010111111111111011111101111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111000111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111110101111111111111101011111111111111111101111110 +11111111111111111111111111111111111111111001111111111111111111111101111111111111 +11111111111111111111111110111111111111111111111110111111111111111111111111111111 +1111111111111101111111111111111111111111111111110001111111111101111111111101 +11111111111111111111111111111111111111111001111111111111111111111111111111111111 +11111111111111111111111111011111111111111111111111011111111111111111111111111111 +1111111111111011111111111111111111111111111111100010100111111101111110111111 +11111111111111111111111111111111111111111111111111111111111111111111011111111111 +11111111111111111111111111110111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111110010110111111011111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111110111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111100011010111111101111101011111 +11111111111111111111111111111111111111111111111111111111111111101111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111101111111111 +1111111111101111111111111111111110111111111111101011111111111111111111111011 +11011111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111100111111111111111111111011111111111100011111111111111111111111011 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111101111111 +1111111111111101111111111111111110110111111111110011111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111110101111111 +1111111111111111111111111111111111111101111111101011111111111111111111111110 +11111111111111111111111111111111111111111011111111111111101111111111111111111111 +11111101111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111101111111111111111110111111111111111011111110111111111111111101 +11111111111111111111111111111111111111111101111111111111100101111111111111111111 +11111001111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111011111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111001111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111011111111111111111111010111111111011111111111111111111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11101111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111110010111111111011111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111101111111111111111111111111 +1111111111111111111111111111111110111111111111111111101111111111111111111111 +11011111111111111111111111111111111111111111111111110101111111111111111111111111 +11111111111111111111111111111111111111111111111111111001111111111111111111111111 +1111111111111111111111111111111111111111111111111111110111111111111111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111110111111111111110111111111111111111111111 +11111111111111111111111111111111111111111111111111111011111111111111111111111111 +11111111111111111111111111111111111111111111111111101111111111111111111111111111 +1111111111111111111111111111111111010111111111111111110111111111111111111111 +11111111111111111111111111111111111111111111111111111110111111111101111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111110111 +1111111111111111111111111111111111110011111111111111111111111101111111111111 +11111111111111111111111111111111111111111111111111111001000101111111011111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111100111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111011001111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111101111 +1111111111111111111111111111111111111101011111111111111111111011111111111111 +11111111111111111111111111111111111111111111111111111111111101111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111110111111011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111001111111111111100111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111101111111111111111101111111111111111111111111111111111111111111 +11011111111111111111111111111111111111111111111111111001111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111101001111111111111111111111111111111111111111110 +11111111111111111111111111111111111111111111111111111111111111111111111101111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111110101111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111011111111111111111101111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111011111111111111011101111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111110111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111100111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111101111111111 +1111111111111111111111111111111111111111111111111111111111111111110011111111 +11111111111111111111111101111111111111111111110111111111001111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111110111111111 +1111111111111111111111111111111111111111111111111111111111111111100111111110 +11111111111111111111111111111111111111111111101111111111110101111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111101101111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111101111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111101111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111101111111111111111110010111011111111110101111111110111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111001111111111111111111110001011111111110110111111111011010111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111100001111111111110110111111111110111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111101111111111111111111111010010111111111111010111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111110111111 +1111111111101111111111111111111110111011111011111111111011111111111111111011 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111101111111111111011011 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111110110111 +1111111111111111111111111111111110010101011101111111111011011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111011111 +1111111111110111111111111111111111111111011111111111111111111111111110111110 +11111111111111111111111111111111111111111111111111111111111111111011111111111111 +11111111100111111111111111111111111111111111111111111111111111111111111101111111 +1111111111111111110111111111100111100110111111111111111111111111111111111101 +11111111111111111111111111111111111111111111111111111111111111111011111111111111 +11111111110111111111111111111111111111111111111111111111111111111111111011111111 +1111111111111111111111111111101111110111011111111111111111111111110111111111 +11111111111111111111111111111111111111111111111111111111111111111111011111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111101111111111111101111111111111111111111111111110111111111101 +11111111111111111111111111111111111111111111111111111111111111111101111111111111 +11111111101111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111101111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111110111111111111111111111111111111111111111111111111111 +1111111111101111111111111101111110111111111111111111111011111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111110111111111110111111111111111111111111111111101111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111101111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111110111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111011111111010111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111101111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111100101111111 +1111111111111011111111111111111111111111110111111111111111100011111111111111 +11111111111111111111111111111111111111111111111111111111100101111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111110101111111 +1111111111111101111111111111111111111111101110111111111111101101111111111111 +11111111111111111111111111111111111111111111111111111111111001111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111011111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111011101111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111011111111111111101111111111111111101111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111101111111111111111111111111111111111111111111101111 +1111111111111111111111111011011110111111111111111111111111101111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111011111111111111111111111111111111111111111110111 +1111111111111111111111111110111111111111111111111111111111101111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111110111100010111111111111111111111111101111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111110011111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111100111 +1111111111111111111111111111111111110111111111111110011111011101111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111110111 +1111111111111111111111111110111111101111111111111110111111111011111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111110110111111111111111111111111110111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111101111 +1111111111111111111111111111111111111111111111111111111110111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111101111111111 +1111111111111111111111111000111111101111111111111111111011111111111111111111 +11011111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111011100001110111111111111111111111111111111111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111100101111111 +1111111111111111111111111111111111111111111111111111111001011111111111111111 +11111110111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100111111111111111111111111111111111111111111111111 +11111101111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100111111111110111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111011111111111111011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111101111111111 +1111111111101111111111111000111110101111111111111111111011111111111111111111 +11011111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111101111111111 +1111111111101111111111111000111111110111111111111111111101111111111111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111101111111 +1111111111111101111111111100111111111111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111110111111111 +1111111111110111111111111111111111011111111111111111111111011111111111111111 +11111100111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111110111111111111111111111111111011111111111111111111111111111111111 +11111010111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111101111111111100111111111111011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111000111111111111011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111011111111111110111111111111111111111111111111111111 +01111111111111111111110101111111111111111111010111111111111111111101011111111111 +11111111111111111111111111111111111111111111111111111111111111111111101111111111 +1111111111101111111111111111111110111111111111111111111111111111111111111111 +01011111111111111111111101111111111111111111110111111111111111111111011111111111 +11111111111111111111111111111111111111111111111111111111111111111111110111111111 +1111111111110111111111111000100001011111111111111111111111111111111111111110 +11111111111111111111111011111111111111111111101111111111111111111110111111111111 +11111111111111111111111111111111111111111111111111111111111111111111101101111111 +1111111111111111111111111100111110110111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +10111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111001111111 +1111111111111111111111111111111111111111101101111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111101111111 +1111111111111111111111111000111111111111110000111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111101101111111111111111011111111 +1111111111111111111111111100111111111111111100111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111110101111111111000111110101111111111111111111111111111111111111111 +11011111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111101111111111000111111010111111111111111111111111111111111111110 +11111111111111111111111111111111111111111111111111111111111110110111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100111110110111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111011111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111101111 +1111111111111111111111111111111111111011101101111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111110111 +1111111111111111111111111100111111111101111100111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111000111111111111110100111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111011111111111111111011111111111111111111111111111111 +01111111111111111111111111111111111111111111111111111111111110111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111101111111111111111111110101111111111111111111011111111111111111111 +01011111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111000100001110111111111111111111111111111111111111110 +11111111111111111111111111111111111111111111111111111111111110110111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111100101111111111100111110010111111111111111111101011111111111111111 +11111111111111111111111111111111111111111111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111011111111111111111 +10111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111000111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111011111111111111110111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111000111111101011111111111111111111111111111111111011 +11011111111111111111111111111111111111111111110111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111000111111110101111111111111111111111111111110111011 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100111110110111111111111111111111111111111101111111 +11111111111111111111111111111111111111111111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111110011110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111110111111111111111111111111111111111111111111111111111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111011111111100111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111110110111111000111111111111111111111111111111111111111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111011111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111011111111111111111111101111111111 +1111111111101111111111111111111111111111111111111111111011111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111011111111111111111111101111111111 +1111111111111111111111111000100001111111111111111111111101111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111011111111111111111111101111111 +1111111111101101111111111100111111111111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111101111111111111111111110111111111 +1111111111110111111111111111111111111111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111101111111111000111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111101111111111111100111111111111111111111111111111111111111111111111 +11111111111111111111111101111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111000111111101111111111111111111111111111111111111111 +11111111111111111111111101111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111000111111110111011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100111111110111111111111111111111111111111111111111 +11111111111111111111101011111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111110011111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111011111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111110011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111101111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100111111111111111111111111111110011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111011011111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111000111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111011111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111101111111111 +1111111010111111001011011111111111010111111111111011111111111111111111111011 +11011111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111101111111110111111111 +1101111011011110110111111000100001100111111111011011111111111111111111111011 +11111111111111111111111111111111111111111111111111111111111110110111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111101101111111 +1111110101011110110111011100111111110111111111010011111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111011111111111111111 +1110101111011111111000111111111111110111111111010011111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111011111111111 +1111111111011110101001101111111110111110111111010011111011111111110111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111000011101111111 +1110001010011111110111011000111111111111011111110010111111111101110111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111011111111111 +1111001101011111110111011100111111110111011111110011111101111111111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111001111111111 +1111101111111111110101111100111111010111011111110011011111111101100111111101 +11111111111111111111111111111111111111111101111111111111111110111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1110111111111111011111111000111111111111111111100111111011111111111111111011 +11011111111111111111111111111111111111111101111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1110110011111111111111111000111111110111111111110011111101111111111111111010 +11111111111111111111111111111111111111111111111111111111111110110111111111111111 +11111111111111111111111111111111111111111111111111111111111111101111111111111111 +1111001111011111111111111100111111110111111111110011111111011111111111111111 +11111111111111111111111111111111111111101011111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1110001101111111111111111111111110110111111111110111111111011111111111111111 +11111101111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111001111111111111111110111111011111110111111111111111111111111101 +11111011111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111001011101110111111100111110011111011111110011111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111101111111111111111111 +1101111011111111111111111000111111110111011111010011111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111110011011101111111011111111111110111111110111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111011111110111 +1111010111111110111111111111111111101011100101111111101111011111111111111111 +11011111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111000011111110111 +1101011011111110111111111000100001110011111100111111110110011111111111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111011111101111 +1111111101011111110111111100111111111111011001111110111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111011110111111 +1110111111111111011111111111111111111101111110111111110011111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111110111111111111111111111111110111011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111110011011111111111111000111111111110111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111110101011111111111111100111111101111111111111111111111101101111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1110111111011111111111111100111111111111111111111111111111111111111111111111 +01111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1110001111011111111111111000111111111111100111111111111111111111111111111111 +01011111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111001001111111111111111000111111110111111111111111111111111111111111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111001111011111111111111100111111110111111100111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1110000111011111111111111111111110110111111111111111111111111111111111111111 +10111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111001101111111111111011111111110111111101111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111000011011111111111001100111111111111110111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1101001110011111111111111000111111010111111100111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111101111111111111110111011111111110111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111101111111111111111101111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1101111111011111110111111000100001110111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111110110111 +1111110110111111111111111100111111110111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111011111111111111111111111110111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111111111111111 +1111111111111111111111111111111111111111111111111111110111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111011001111111111111111000111111111111111111111110000111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111011111111111 +1110111111111111111111111100111111111111111111111111110111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111011011111111111 +1111111111111111111111111100111111111111111111111101110111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111001111011111111111111000111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111100111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111000111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111011111111111111100111111110111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111110111011111111111111111111111110111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111011 +1111111111111111011011011111111111111111011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111010011111110101001100111111111111011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1101111101111111111111011000111111111110111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111101 +1111111111111111111110011011111111111011111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111100111111111111111 +11111111111111111111111111111111111111111111111101011111111111111111110111111111 +1111001111011111111111111111111111111111111111111111111111111110111111111111 +11111111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111011111111111111111111101111111 +1101111111011111111111101000100001111111111111111111111111111111110111111111 +11111111111111111111111111111111111111111111111111111111111111101111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1101101110011111111111111100111111111111111111111111111111111110101111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111110111111111111111111111111111111 +1111101011011111111011111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111110111111 +1101101111011111101111111111111110111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111110111 +1110101110011111110111111000111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111101111 +1111100111011110110111111100111111110111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111110111111 +1111101111011111111111111100111111010111111111111111111111111111111111111111 +11111111111111111111110111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1110001111111111111111011000111111101011111111111111111110011101111111111111 +11111111111111111111111101111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1110000011111111111111011000111111110101111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111011101011111111010111100111111111111111111111111111110111011111111111111 +11111111111111111111111111111111111111111111111111111111111111101111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111001111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111101011111111111111111011111111111 +1111001111111001110111111111111111111111111111111111111111111011111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111011111111111111111011111111111111011011111111111 +1111000001011101101001111100111111111011111111111100111111111101111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111110111111111111111100011111111111 +1101010111011111111111011000111111111111011111111111010111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111011111111111111111111111111111111110111011111111111 +1111001110011011111101111011111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111011111111111111111111111111111111 +1111111111101111111111111111011111111111000111111011111110011111110011111111 +11011111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111011111111111111111111111111111111 +1111111111111111111111111000101111111111011111011011111111011111110111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111011111111111111111111111111111 +1111111111101101111111111100100101111011111101011111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111101111111111111111111111111111111 +1111111111110111111111111111111101111010010111110011111110111111101111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111101111111111111111111111010110110010011101111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111101111111111000111111111111011101110000010111111101111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111011111111111100111111111111011101110010110111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111101111111111111100111111111111011111110011110111111101111111111111 +01111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111101011111111111111111111001111111 +1111111111111111111111111000011111111101111111100011111111111111111111111011 +01011111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111011111111111111111111101111111 +1111111111111111111111111000101111111111111111100011111111111111111111111011 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111011111111 +1111111111111111111111111100110101111111111111110111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111110111111111111111111111111111111 +1111111111111111111111111111111111111111111111110111111111111111111111111111 +10111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111100111011111111011111111111111111111111101 +11111100111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100101101110111011111111011111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111000111111111111011111011111111111111111111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111011110011101110111111111111111111111111111111111101 +01111111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111001111111 +1111111111101111111111111111111111111011101111111110111110011111111111111111 +01011111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111101111111 +1111111111111111111111110111100001111111111111111110011110011111111111111110 +11111110111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111011111111 +1111111111111101111111111100111111111111110101111111110111111111111111111111 +11111110111111111111111111111111111111111111111111111111111110101111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111110101111111111000111111111101111101111111111111111111111111111111 +10111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111101111111111100101111111111111111111111111111111101111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111101111111111100100001111011111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100101101111111011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111101011111111111000111101111111111111111111111111111011111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111101001111111111000011111101111011111111111111111111111111111111111 +11011111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111100101111111111100100101110101011111111111111111111111111111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111101111111111100101001111011111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111011111111110000111101111010111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111010111111111111111111111111111111111111111111111110111 +1111111111111111111111111100011110111011111101111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111110111111111111111111111111111111111111111111111100111 +1111111111111111111111111100101101111111111000111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111101111111111111111111111111111111111111111111111111111 +1111111111111111111111110100110101111111011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111110111111 +1111111111111111111111111110111011011101011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111101001111111 +1111111111101111111111110110111110111001111111111111111011111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111101111111 +1111111111110111111111110100111001111101011111111111111011111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111110001111111 +1111111111111101111111111100101111110111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111101111111 +1111111111111101111111111000111101010111111111111111111101111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111110111111111111111111111111111111 +1111111111111111111111111100111111111011101111111111111111111110011111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111011111111111111111111111111111 +1111111111111111111111111000111111111101011111111110110111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100111111111011111111111111111011011111110111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100111111111010110111111111001111111111011111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111101111111111111000011111101111101111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111101111111111000100111110111111100111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111101111111111100111101111111101101111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111100101111111111011111111111111110111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100101111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100101101111111111101111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111110100110001111111101111111111111111101101111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111101101111111 +1111111111111111111111111110101111111111111111111111111111111111110111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111110100101001111111101111111111111111111111110111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111101101111111 +1111111111101101111111111100100101110111110101111111111111111110101111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111110011111111 +1111111111111111111111111000111101110111101111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111110111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111000111101111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100111111111111111111111111111111111111111101111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100111011111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110110111111111111111 +11111111111111111111111111111111111111111111111101011111111111111111111001111111 +1111111111101111111111111011111111111101011111111111111011101111111111111111 +11111111111111111111111111111111111111111111111111111111111111010111111111111111 +11111111111111111111111111111111111111111111111111011111111111111111111101111111 +1111111111111111111111111011111101111111011111111111111101101101111111111111 +11111111111111111111111111111111111111111111111111111111111110110111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111011111111 +1111111111100101111111111111111011110111111111111111111111011101111111111111 +11111111111111111111111111111111111111111111111111111111111110101111111111111111 +11111111111111111111111111111111111111111111111110111111111111111111111111111111 +1111111111111111111111111011101101110110111111111111111111000111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111010111111111111111111111111111111111111111111111111111111111111110111111 +1111111111111011111111111111111111111111111111111111110011111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111110111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111101111111111111111111111111111110111110110101111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111110111 +1111111111111111111111110111111111111111111101111110000111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111101111111111111111111111111111111111111111111111111111111111111111010111 +1111111111111111111111111110111111111111111111111111110111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111101001111111 +1111111111101101111111111111111110111111111111111111111011111111111111111011 +11011111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111010111111111111111111101111111110001111111 +1101111111111011111111111111111111011111111111111111111101111111111111111011 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111010011111111111111111111111111111101111111 +1111111111111101111111111111111110110111111111111111111011011111111111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111011111111111111111111111011111111101111111 +1110111111110101111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111110111111111011111110111111111111111110110111101111111 +1111101101111111111111101111111111111111111111111111111111111111111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111110111111111110010111111111101111011111111011001111111 +1110110010011111110111001111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111101111111111110011010111111111110110111011011111111111 +1111110111011111111111011111111111111111111111111111111111111111111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111110111111111111101111111111111111111111111111001111111111 +1111111111011111110111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111100111111111111111 +11111111111111111111111111111111111111100011111110011101111111110101110101111111 +1110111110111001111111111111111111111111111111111110111110011111111111111111 +11011111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111100011111111011111111111111011111101111111 +1110111111011101111111111111111111111111111111111110011110011111111111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111110011111110111111111111101111011111111111 +1111011111111111111111111111111111111111111111111111110111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111101111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111011111111 +1110011111111011111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111110011111111011111111111111111111111110111 +1111111111110111110111111111111110111111111111111111111111111101111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111110011111110111111111111111111111111110111 +1111001111111101111111111111111110011111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111010011111111111111111101111111111111110111 +1101001111111111110111111111111111110111111111111111111111111101111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111011111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111101101011111111111111001101101111111 +1111111111111111111111111111111110100111111111111111111110111111111111111111 +11011111111111111111111111111111111111111111111111111111111111100111111111111111 +11111111111111111111111111111111111111111110010110011111111111111011111001111111 +1111110011011101111111111111111111010111111111111111111111011111111111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111011000101111111 +1111111110011111111111111111111110110111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111001111111111 +1111111101101111111111111111111111101111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111110111111111111111111111011111111111111111111111100111 +0111111111111101111111011111111111110111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111110110 +0011111111111111111110001111111111100111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111101111111111111111111110111111111111111111111111101111 +1111111111111011111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111110111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111101111111111111111111110111111111111111 +11111111111111111111111111110111111111111111111111111111111111111111111010111111 +0011111111111101111111111111111111100111111111111111111111111111111111111111 +11011111111111111111111111111111111111111111111111111111111111100111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111100111111 +0111111111111111111111111111111111110111111111111111111111110111111111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111011111110111111 +1111111111111011111111111111111111111111111111111111111111101111111100111111 +11111111111111111111111111111111111111111011111111111111111110111111111111111111 +11111111111111111111111111101111111111111111111111111111111111111111011110010110 +1111111111111111111111111111111111101111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111011111110111111 +1111111111111111111011001111111110111111111111111101111011111101111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111011111111111111 +1111111111111111111110011111111111011111111111111110111111111011111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111101011111110111 +1111111011111111111111001111111111111111111111111110110111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111010111 +1111111111011111111101111111111111111111111111111111010101111111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111111111111111 +11110101111111111111111111100111111111111111111101011111111111111111101100111011 +0111111111101001111111001111111110100111111111111111111011111111110011111011 +11011111111111111111111111111111111111111111111111111111111111111111111111111111 +11111101111111111111111111100111111111111111111110011111111101111111111111011111 +1001001111100101111111011111111111000111111111010011111101111111100111111011 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111011111111111111111111111111111111111111111111111111111111111111111110110111 +0101001111111101111111111111111111110111111111010011111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111101111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111110011111100 +1111111111111011111110111111111111110111111111111011111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111110111111111111111111100111101111111001 +1101001011111011111111111111111110111111111111011011111111111111111011111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111110111111111111111110101111110101111111 +0111001011011101111111111111111111111111111111101011111111111111110111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111010111111111111111101111011111111111 +0111000110011111111111111111111110110111111111111011111111111111110111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111011001111111101 +0111001101011111111111111111111111011111111111111011111111111110111111111101 +11111111111111111111111111111111111111111101111111111111111111110111111111111111 +11111111111111111111111111100111111111111111111111111111111110111011111111010111 +0110111110101101111111111111111111111111111111100010111011111111110111111111 +11011111111111111111111111111111111111111001111111111111111111110111111111111111 +11111111111111111111111111110111111111111111111111111111111110001111111111110110 +0011010001010111111111111111111111110111111111100011111101111110100111111110 +11111111111111111111111111111111111111111111111111111111111111101111111111111111 +11111111111111111111111111101111111111111111111111111111111111001111011111111011 +0111110111011011111111111111111111111111111111111111110011011111111111111111 +11111111111111111111111111111111111111101111111111111111111110111111111111111111 +11111111111111111111111111111111111111111111111111111111111110111011011111101111 +1111111111011111111111111111111110111111111111100011111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111110101111111111111101100001 +1011111111111111111111011111111111111111111111110011111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111110101 +0111111111111111111111011111111111111111111111110011111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111110101111111111111101111 +0101111111111111111111111111111111111111111111011111111011011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111011111111011011011111111 +1111111111111111111110011111111111111111111111110011111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111111111111111001011111101111111 +1111111111111111111111111111111111111111111111111101111110011111111111111111 +11111111111111111111111111111111111111111111111111111111111111100111111111111111 +11111111111111111111111111111111111111111111111111111111111101001000011011111111 +1111111001011111111111111111111111111111111111111110111110011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111110111101001011011111111111 +1111111010111111111111111111111111111111111111111110110111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111111111111111 +11111111111111111111111111111111111111111111111111111111110111001111011111111111 +1111111111011111111111111111111111111111111111111111010111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111110011111111101001111110101110111 +1111111111101001101111101111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111110011111111110001111111001110111 +1111111111100101110111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111001111111111101111 +1111111111111100110011111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110001111111110111111 +1111111111111011111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111110111111111111111111111011111111110111111100101111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110111110000001111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111101111111111111111111110111111111111111111111101111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111011111111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111001111011111111111101110111111111111 +1111111111111001011111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111100110111111111111111100011001111111110 +1111110011001101110111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111110111111111111101111011011101111111 +0111110100011101111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111101110110111111111111111101011111111111 +1111111111011011111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111101111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111101011111111111111111110101111001 +0011111010110101010011111111100111101111111100111111111111111111111111111111 +11011111111111111111111111111111111111111011111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111011111111101111111011001111110 +0111111011011100111101101111101101110111111101111111111111111111111111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111110111111111101111011111111111101 +0111110101011010111111011111101001111111111011111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111110011111111111 +1111111111011110110111111111111101111111111111111111111111111111111111111111 +11111111111111111101011111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111101011111111101111011111101011111 +0011111111101101101011111111111110111110100111111111111011111111111111111111 +11111111111111111111011111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111110011111111110111001111101110111 +0111111111111101111111111111111111111111111111111111111111111111111111111111 +11111111111111111110111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111011011111110111 +1111111111110101110101011111111111110111010101111111111101011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110011111001011111110 +1111111111101001111011111111111111010111111111111111111111011111111111111111 +01111111111111111111111111111111111111110101111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111101011111111110001001111101110011 +1111111100101101111111111111100110110111111111111111111010011111111111111111 +01011111111111111111111111111111111111111001111111111111111111101111111111111111 +11111111111111111111111111111111111111111111111110011111111110001011111001111111 +1011110011000101111111111111101111111111111111111111111100011111111111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111001111011111111101 +0111110111011001111111111111111101111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111000111001111111111 +1111111111001111111111111111101101001111111111111111111111111111111111111111 +10111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111011111111111101110111111110111 +1111111011101101111111111111111111110111011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111110111111111111001001011101110111 +0111111011011001111111101111111111111111011110111111111111111111111111111111 +11111100111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111101101011111101110111 +1111110111011101111111011111111111111111011101111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111101111001101101111 +0111111100000101111111111111111111101110111111111111111111111111111111111111 +01111111111111111111011111111111111111111111111111111111111111111110011111111111 +11111111111111111111111111010111111111111111111101011111111111100111111111111110 +0111001111110100111111111100111111111011101111111111111110011101111111111111 +01011111111111111111111111111111111111111111111111111111111111111111011111111111 +11111111111111111111111111110111111111111111111111011111111101111001011111111111 +0001001111111001111111110100111111111011111111111111111110011101111111111110 +11111100111111111110111111111111111111111111111111111111111111111110111111111111 +11111111111111111111111111111111111111111111111111111111111101111111011111111111 +1111001111111111111111110100111111111101010111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111101111111111111111111110111111111111111010011111111111 +1110001111111111011111111100111111111111111111111111111111101011111111111111 +10111111111111111111111111111111111111111111111111111111111111111101011111111111 +11111111111111111111111111111111111111111111111111101111111101001101111110111011 +0011110111110101101111110100111110111011111001111111111011111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111011111111111 +11111111111111111111111111111111111111111111111111111111111110010011111111111111 +0110111111011101110111111000111000011111111100111111111101111111111111111111 +11111111111111111111111111111111111111111111111111111111111110110110111111111111 +11111111111111111111111111111111111111111111111111111111111111001111011111010100 +1111111111011111111111111100011111110111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111110111111110001111111111110111 +1111100110011011111111111100111101111101111111111111111111011111111111111111 +01111111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111110111111111111111111111011111111110001011111001001111 +1110101101111110111111111000110011111011111111111111111110011111111111111111 +01011111111111111111111111111111111111111111111111111111111111100111111111111111 +11111111111111111111111111111111111111111111111110011111111110001011011100010111 +1110100011111111111111111000001101111111111111111111111110011111111111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111101111111111111111111111111111111111001101011110111111 +1111101111001101111111111100111101111011111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111111111111111 +11111111111111111111111111111111111111111111111011111111111111101010011011111111 +1110001111111110111111111100111111111011011111111111111111111111111111111111 +10111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111110111111111111111111111111111111111001111101001111011 +1111101111101000111111111101111111111110001101111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111101111111111111111111111111111111111001111000101111111 +1111100011011100111111111101101001111111010100111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111101001110111101111101 +0101000111010001010111110101010111111111111001111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111101111111011111111 +1011001100011101111111111101111101111110111110111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111010111111111111111111111001111111111010111111100111111 +0011001001101111010111111100111111111011011111111111111011111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111110111111111111111111111110111111101001011111101011111 +0101001011000111110111110110111111111101011111111111111101111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111101111111111111111111111101101111111001111011010110111 +1111111110011101111111111100111111111010011111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111110111111111110011001001111111110 +1111111011011111101111111000111111111011111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111011111111111001110110101110011 +1111001111101101111111011100111110111111111110111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110001001011001011111 +0111001111111101111111011000111111111111111101111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111110111111111111001111111110111111 +1110011111101001111010111100111111110111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111001111111110111101 +0111011111100111111111111100111111010111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111110101111011 +1111010111111111111011001000111111111111101101111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111111111111110110011011001111011 +0011011011011111111111011000000111111111110100111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111100011111111111 +0111001100011111111110011110111101111111101101111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110101111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111111111111101 +1111011011011111111001111010111111111111111011111111111111111111111111111111 +11111001111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111110011111111111111111111111001111111111111111111111011 +1111111011101101111011111100111111111001111111111111111111111111111111111111 +11110011111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111101111111111111111111111111101111111111011111111111111 +0111111001110111111111101100111001111101011100111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111101011111111111111111111011111101111101111110110001 +0101001111011100110111010110111111111011001101111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111011111111111111111111111111111101111111111111011 +1111011111111001111101111110111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111111111111111111110101101111111 +1111011110101001111111111110111111110111111111111111111110011111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111111111111101110011011101111111 +1101001111011101111111110111101111110111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111101111111111111111 +11111111111111111111111111111111111111111111111111111111111111011001011111111111 +1111100111111111111111110111111111111111111111111111111110111111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111111111111111 +11111111111111111111111111111111111111111111111111111111111110011111000011111111 +1111111111010011111111111110110110101111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111011111111111111 +1111010111111111111111110110111010111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110111001111111111111 +1111001111011111111111111111111100011111101011111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111011111111111 +1110001111011111111111111111111111110111110111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111011011111111111 +1111011110111111111111111110111111111111101111111111111111111111111111111111 +11111111111111111111111111111111111111111101111111111111111110110111111111111111 +11111111111111111111111111111111111111111111111111111111111110111010111001010111 +1111001011101111100111111000111111110111110111111111111010011111111111111111 +11111111111111111111111111111111111111111101111111111111111111010111111111111111 +11111111111111111111111111111111111111111111111111111111111110011111011101110111 +0011001001111101110011111100111111101111100111111111111010011111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111111111111111011111011111111110 +0111000111011111101101111100111111111111111101111111111101011111111111111111 +11111111111111111111111111111111111111101011111111111111111110100111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111111011101111 +1111001111000111111111111100101101111111111111111111111111111111111111111111 +11111111111111111111011111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111101011111111111111110111111111011 +0111111111111111110111111100111111111111111100111111111111111111111111111111 +11111111111111111111011111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111110011111111111111011011111111001 +0111001111111111111111111100111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111101111011111111111111 +0101001111111110100111110100111111111111111111111111111111111111111111111111 +11111111111111111010111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111101011111111100 +1111111111111111111111111110111111111111111111111111111111111111111111111111 +01111111111111111111111111111111001111111111000011111111111111111111101111111111 +11111111111111111111011111111111111011111101111010011101111111010110111101001001 +0011111111111111111111111100111111110110101111111011111011111011110011111011 +01011111111111111111111111111101001111111110110101100111111111111111111111111111 +11111111111111110111111101111111111101111110010011011111111101001001011110110111 +0101111111111111111111110100011111110111011111011111111101111001110111111011 +11111111111111111111111111111111101111111110111111011111111111111111111101111111 +11111111111111111111101001111111111101111101110100001111111111001111011110111111 +0111111111111111111111111100111100110111111111010011111111111111101111111111 +11111111111111111111111111111110101111111110110111111011111111111111100111111111 +11111111111111111011111101111111111101111111100111101101111110010111011011110100 +1110111011011111111111111000111110101111110111110111111111101111111111111111 +10111111111111111111111111111111001111111111011111001111011111111110011101111111 +11101001111111111111100111111111001111111111111011000110101111001011111101101111 +0111111010100111100011111110011011110111111111011011111111111011110111111101 +11111111111111111111111111111110001111111111110110011111101101111111011001111111 +11111101111111111111101100111111011111111111111100110111111110001011111101110111 +0110011011011101100101001110100100101111011110111111111111111101110111111111 +11111111111111111111111111111111101111111111110111111110110101111111001111111111 +11100001111111111110101101110111111101111111111011011101110111001101011111110011 +1111011011000101110011011110101101110111111101110011111111111100111111111101 +11111111111111111111111111111110101111111111111111111011011001111111011111111111 +11111111111111111011111001111111000111111111111111111111011111001111101011111110 +1110111101011111110111111110111101111111011111110111111111111111101111111101 +11111111111111111111111111111110011111111111110111111000110111111110111111111111 +11111111111111111000011011111110111111111111111111111111111110101111111111110111 +0110001011111111111010011011111111111111101011100011001011111101111111111111 +11011111111111111111111111111110011111111111111111111100001111111111111111111111 +11111111111111111100111101111111111111111110111111111111111110000011111111111111 +0010001001011111111011011101111111111111110111110010110111111111111011111110 +11111111111111111111111111111111001111111111111111111100111101111111111111111111 +11111111111111111111011101111111111111111111111111111111110111001111011111111010 +0111000111011111111110011101111111111111111101111010111101011111110111111111 +11111111111111111111111111111111001111111111111111111011101101111111111111111111 +11111111111111111011111101111111111111111111011111111100111110101101111111110111 +1110001110011111111101111111111111111111111111111011110111011111111111111111 +11110011111111111111111111111111011111111101111011011111111111111111011111111111 +11111111111111111110111111111111001101111111110011111110111111101111101001111111 +1111001101111101110001001110101110111111111111110011111011111100111111111111 +11111111111111111111111111111111011111011111111111001111111111111111111110111111 +11111101111111111110111111111111011101111111111111111101110011001001010001110111 +1011000011001101110101011100101101111111011111110001110011111111010011111111 +11111111111111111111111111111101001111111111111101010100111111111111011101111111 +11111111111111110110111111111111000001111111110001011101110101000111111111110111 +0101111111011101110111010100100001010111111111011010110101011100110111111111 +11111111111111111111111111111111001110111011111110011111111111111111111111111111 +11101111111111111110111111111110101111111101110111111011010111101110011111011111 +1111111110101011101110111110111101110110111111111011100111111111111111111111 +01111111111111111111111111111111111111111111110111101100111111111101011111111111 +11111111110111111111111111111111101100110011111111111111110111111111101110110001 +0111010111101111111111001111111110111111111101110010111110011111111111111011 +01011111111111111111111111111101101111111111101111010100011001111111011111111111 +11111111100111111111001111111111110001011111111111111111110001111011001111001010 +0101011001111111111111010110111001111111111100010110111110011111111111111011 +11111111111111111111111111111111101111111111111111110100111101111111111111111111 +11111111111111111111111100110111111101110011111111011111101111110111111100110111 +0101001111010101111110111111111111110111111011100011010111111111111111111111 +11111111111111111111111111111110111111111111111111111100111111111110111111111111 +11111110111111111111110111111111111101100011111111011111111110001100010111111111 +1001111111111101111111111111101101010111111111010011111111111111111111111111 +10111111111111111111111111111111010111111111111111110100111110111111101111111111 +11111111111111111111111110010111111111110011111011011111111111111011111110111011 +1101001101111001101111001100111110110111011111010011111111101111111111111101 +11111111111111111111111111111110001011011111111111111000111101011111111111111111 +11111111111111111111111111010111111111100000111100111111111110111001101111111101 +1110001011111101110111011100101111000111111111100111110111111111111111111111 +11111111111111111111111111111111000101011111111111111100111111110111111101111111 +11111111111111111111111111101111111111110011110011011111111111101111011101011111 +0011001011111111111111111011111111111110111111110010111111111111111111111101 +11111111111111111111111111111111011110011111111111111100011001110111110101111111 +11111111111111111111111111111111111111100011011111111111111111001011011111111111 +1111111111011011111110111111110110111111111111110011100111110111111111111101 +01111111111111111111111111111110001111111111111110011000111111111111111111111111 +11111111111111111111111011111111011101101110111111111110110110111010101111111011 +1110001110111111110110011101111111110111111111100011111111011111111111111111 +01011111111111111111111111111110001111111111111111001000111111111111111111111111 +11111111111111111111111101111111011011101110111111111110110110111011010111100111 +1110101111011111110111001101101001101111111100100111111110111111111111111110 +11111111111111111111111111111111101111111111111111111100111111111111111111111111 +11111111111111111111011111111110111111110111010111111111000111111011011110111101 +0111001111111111101111011101101111111111111111110011111111111111111111111111 +11111111111111111111111111111110101111111111111111111100111111111111111111111111 +11111111111111111111111101111011111111101111111111111110111110111101011110100111 +0111001111111110111111011100110101111111111111110011111111111111111111111111 +10111111111111111111111111111111011111111001110111111101111111110110011111111111 +11111111111111111111101111111101001111111111111111011110000111111111101111110011 +1111001011101111110011001101111111110111111111110011111111111001111111111111 +11111111111111111111111111111111011111111001110111111100101001100111011111111111 +11111111111111111111111001111111011111111110110010111111110011011010010111110111 +1111001011110111110111011101111111110111111111110110111111111101111111111111 +11111111111111111111111111111101111111111111111111110100100111111111111111111111 +11111111111111111111111101111111111101010101011111011111110101111001111101101101 +0001001101001101111101010101111111111111111111011110011111111111111111111111 +11111111111111111111111111111111111111111110101111111101111100111110111111111111 +11111111111111111111111111111110110101111111100111111111111011111111011100111111 +1111001011011110101110011100111110101111111111110011110111111011111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111110111111111111111011111111010111111111101111111000111111111111111 +1111101111101111110111111111011110111001011111110111111111111111110111111011 +11011101111111111111111111111111111011111111111111110110111101111111111111111111 +11111111111111110111111111111110011101010010110111111111111101001111011101111111 +1101001011111111111111111111111111111111011111010010111111111110100111111011 +11111111111111111111111111111111111111111111111111110110111011111111111111111111 +11111111111111111111111111111111111111010010000111111111111111011011001101111111 +1110001101110101111111111111111101110111111111010010111111111111111111111111 +11111101111111111111111111111111111101111111111111111111101101111111111111111111 +11111111111111111011111111111011111101111111110111111011111110001110001111111111 +1101001011011101101111111111101101010100111111010111010111111111111111111111 +11111111111111111111111111111111111011111111111111110101011110111111111111111111 +11111001111111111111010010111110111111011011111011010101111111001111101111111111 +0101000111101001111011011111111011101111111111010001111111011111110111111101 +11111111111111111111111111111111111000011111111111111100101111011111111111111111 +11111001111111111011101101011100011111111011111110101101111110000010011101111110 +0110001001111101111101001111011101110111111111100010110110011110100111111111 +11111111111111111111111111111111111011011111111111111110110101110111111111111111 +11111111111111111111101101111011111111111111111001001011111111001011011101111011 +1111001111011101111111011111111101110111111111110010000011011111111111111101 +11111111111111111111111111111111111111011111111111111111111111110111111111111111 +11111111111111111101111101111011111111101111111111101101111110001101000101111111 +1111001111110001111110011111101101110111111111111111110011111111111111111101 +01111111111111111111111111111111111111111111111111111000100111111111111111111111 +11111111111111111011110001111111101101100011111011111110101110111101111111111010 +1010010110111111111101001111111111111110011110101010001111111111111111111011 +01011111111111111111111111111111111111111111111111111000101101111111111110111111 +11111111111111111011101101111111101100100010110001111111111110001011111111111111 +0110011111011111111111011111111111111111011101100010110111111111111111111011 +11111111111111111111111111111111111111111111111111111100101001111111111101111111 +11111111111111111110101101111111111001110001111111011111110111111111111111111111 +0111111011011111111111011111111111111111111111110011110111111111111111111110 +11111111111111111111111111111111111111111111111111111100111101111111111111111111 +11111111111111111111111101111111110111110011000111111111011110111111111111111101 +1111111111011111111110111111111111111110111111111110110111111111111111111111 +10111101111111111111011111111111111111111111111111011100111110110111101111111111 +11111111111111111111110100110011101100110011111111011111111111111011101001111011 +1111001111101111011111011111101111110111100100111011111111111110110111111101 +11111000111111111111011111111111111111111111111011011100111111110111111111111111 +11111111111111111111101101011101111100111110010111011111111111001010011001111111 +1011001111011101110111011111101101101111111101111011111111111111110111111111 +11111111111111111111111111111111111111111111111110110100111110000111110101111111 +11111111111111110111111000110111110001010011101111111111111101111101011111111101 +0101000111111111111010111111101101111111111101011011111111111110010111111101 +11111111111111111010111111111111111111111111111111111101111110111111101111111111 +11111111111111111111111111101111111111110010110010111111111111111011010111111111 +1111001110000111111111111111110001111111110011111111111111111110101111111111 +11111111111111111111111111111111111111111111111111111111100111111111101011111111 +11111111111111111111110101111111111110011111111111111111111111110100110101111111 +1111001111111011111111111111111111111111111101111110111011111110111111111111 +11111111111111111111111111111111111111111111111111111111101101110111111101111111 +11111111111111110100101111111111111111011110010111111111111101111011011101111111 +1101001001111101111111110110111111111111111101111110011111111111111111111111 +11111011111111111111111111111111111111111111111111111111101001111111101111111111 +11111111111111111100101101111111101111111110101111111111111101101111011011111111 +1101001111111111111111110110111111110111101111111110110101011110111111111111 +11111101111111111111111111111111111111111111111111111111111100111111111111111111 +11111111111111111000111101111111111111101111110111111111111111111111111111111111 +1111001111111111111111111100111111110111111011111111110111011111111111111111 +11111111111111111111111111111111111111011001101111111111111010111111111111111111 +11101111111111111111111111110100011111111011101111111111111101110111111100011111 +1101001001101110111111110111111110111111011111111101011011111111111110111111 +11111111111111111111111111111111111011011101110111111111111101111010011101111111 +11111111111111111000111110111011011111101111110011111111111110111001011110011111 +1110001011011111111111111010101101111111011111111110111101111111111101111111 +11111111111111111111111111111111111111011111111111111111111111110110101011111111 +11110101111111111100111111110111111111111110111111011110111111111110001100111111 +1111001010011110111111111110011110110110111111111111110111011111111110011111 +11111111111111111111111111111111110100011011111111111111111111010001111101111111 +11111101111111111100111111101011111111111111110111111111110110111011011010111111 +1111001111010110110111111100110001011011111111111110110111011111111111111111 +11111111111111111111111111111111111111111111110111011111111111111111011111111111 +11111111111111111011111011111111011111101101111011111111111110000111111111110111 +1110111110111011100101111000111011111011111111111111111111111001011111111111 +11111111111111111111111111111111111111111111111111011111111111111111110111111111 +11111111111111111011111101111110111111101111100111111111111110001110011111111111 +1110011111011101110001111000111101111111111111111111111111111100011111111111 +11111111111111111111111111111111111111111111111011111111111111111111111101111111 +11111111111111111101111111111111111111111111110101011111111111001111011111101111 +0111111111111111111111011110011111111001011111111111111111111111110111111111 +11111111111111111111111111111111111111111111101110111111111111111110111111111111 +11111111111111111001111111111111111111101110110111011111111111001111111111111011 +1111110111011111101111111110111101111111111111111111111111111011111111111111 +11111111111111111111111111111111111111011101111111111111111101111111111001111111 +11101101111111111111010111100111111111110011111011001111111111001111111101111110 +0111111110111000111111111110111111111111111111111110111111111100110111111111 +11111111111111111111011111111111111011011011111111111111101101111111111101111111 +11111101111111111111101101100011101111111111111111011111111111011111111111111101 +0111111111011000111011111110111111111111111110111110011111111111110111111111 +11111111111111111111111111111111111111011111111111111111011101111111111111111111 +11101001111111110101011101111111011101011111111011011111111101001111111111111111 +0101111111111111010111010110111111111111011101111111110011011011111111111111 +11111111111111111011111111111111110100011111111111111111110001111111111101111111 +11100111111111111111111001111111100111111111111000110111111111001111111011111111 +0111111111111111111001111110111111111111011111111110110111111111101111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111101111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111101111111111111101111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111101111111 +1111110111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111101111111111111111111111111111111111 +11111111111111111111111111111111111111010111111111111111111111111111110101111111 +1111111111111111111111111111111111010111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111101011111111111111111111111111111 +1111110111110111111111111111111111010111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111101111111111111111011111111111111011111111 +1111111111110011111111111111111111101111111111111111111111111111111111111111 +11111111111111111111111111111110111111111111111111111111111111001111111111111111 +11111111111111111111111111111111111111111111111110111111101111111111110011111111 +1111111111111011111111111111111111101111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111011111111111111111111111111111110111111101 +1111111111110111111101111111111111011111111111111111111111111111111111111111 +11111111111111111111111111111101011111111111111111111111111111011111111111111111 +11111111111111111111111111010111111111111111111101110011111111111111110111001111 +1111111111110101101111111111111111011100101111111111111111111011111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111110111111111111111111111111111111101101 +1111111111111111101101111111111111111110111111111111111111111010111111111111 +11111111111111111111111111111111111111111111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111110110111111111111111111010111 +1111111111111111100011111111111111111101011111111111111111111001111111111111 +11111111111110011111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111110001111111111111111111111111111110111 +1111111111111111100011111111111111111111111111111111111111111101111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111101011 +1111111111111111111111111111111111111110111111111111111111111111111111111111 +11111111111011111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111101011 +1111111111111111111111111111111111111111100111111111111111111011111111111111 +11111111110111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111110111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111110111111111111111111111111111111111 +11111111111111111111111110111100111111111101011110111111111111111111101111111111 +11111111111011111111111111111111101111111111111111111110111111111111111111111011 +1111111111111111111011111111111111111111101111111111111111111110111111111111 +11111111111111111111111110111100111111111101001111110011111111110101111011111111 +11111111111011110011111111110101111011001111111111010110011100111111111101011010 +1100111111111101011010110011111111110101100111001111111111010111011111111111 +11111111001111111111010111011100111111111101001111111111111111111111101111111111 +11111111111011111111111111111111101111001111111111010110011111111111111111111011 +1111111111111111111011111111111111111111101111111111111111111110111111111111 +11111111001111111111011110111100111111111101111011111111111111111111101111111111 +11111111111011111111111111111111101111111111111111111110111100111111111101011010 +1100111111111101011010110011111111110101100111001111111111010111011111111111 +* +C2594* +N User Electronic Signature Data* +U00000000000000000000000000000000* +451D diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.log b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.log new file mode 100644 index 0000000..d0353b8 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.log @@ -0,0 +1,4 @@ +---- MParTrce Tool Log File ---- + +==== Par Standard Out ==== +==== End of Par Standard Out ==== diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lpf b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lpf new file mode 100644 index 0000000..2743d95 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lpf @@ -0,0 +1,4 @@ +#BLOCK ASYNCPATHS; +#BLOCK RESETPATHS; + +#FREQUENCY 200.000000 MHz; diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lsedata b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lsedata new file mode 100644 index 0000000..0f0f220 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lsedata @@ -0,0 +1,6331 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mrp b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mrp new file mode 100644 index 0000000..e44642b --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mrp @@ -0,0 +1,336 @@ + + Lattice Mapping Report File for Design Module 'RAM2GS' + + +Design Information +------------------ + +Command line: map -a MachXO -p LCMXO640C -t TQFP100 -s 3 -oc Commercial + RAM2GS_LCMXO640C_impl1.ngd -o RAM2GS_LCMXO640C_impl1_map.ncd -pr + RAM2GS_LCMXO640C_impl1.prf -mp RAM2GS_LCMXO640C_impl1.mrp -lpf D:/OneDrive/ + Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lpf + -lpf + D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/RAM2GS_LCMXO640C.lpf -c + 0 -gui -msgset + D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml +Target Vendor: LATTICE +Target Device: LCMXO640CTQFP100 +Target Performance: 3 +Mapper: mj5g00, version: Diamond (64-bit) 3.12.1.454 +Mapped on: 08/15/23 05:03:22 + +Design Summary +-------------- + + Number of PFU registers: 102 out of 640 (16%) + Number of SLICEs: 71 out of 320 (22%) + SLICEs as Logic/ROM: 71 out of 320 (22%) + SLICEs as RAM: 0 out of 192 (0%) + SLICEs as Carry: 9 out of 320 (3%) + Number of LUT4s: 142 out of 640 (22%) + Number used as logic LUTs: 124 + Number used as distributed RAM: 0 + Number used as ripple logic: 18 + Number used as shift registers: 0 + Number of external PIOs: 67 out of 74 (91%) + Number of GSRs: 0 out of 1 (0%) + JTAG used : No + Readback used : No + Oscillator used : No + Startup used : No + Number of TSALL: 0 out of 1 (0%) + Notes:- + 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of + distributed RAMs) + 2*(Number of ripple logic) + 2. Number of logic LUT4s does not include count of distributed RAM and + ripple logic. + Number of clocks: 4 + Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK ) + Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 ) + Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS ) + Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) + Number of Clock Enables: 13 + Net PHI2_N_120_enable_4: 1 loads, 1 LSLICEs + Net RCLK_c_enable_4: 3 loads, 3 LSLICEs + Net RCLK_c_enable_23: 8 loads, 8 LSLICEs + Net RCLK_c_enable_12: 1 loads, 1 LSLICEs + Net RCLK_c_enable_3: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_5: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_6: 2 loads, 2 LSLICEs + Net RCLK_c_enable_24: 2 loads, 2 LSLICEs + Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs + Net Ready_N_292: 1 loads, 1 LSLICEs + + Page 1 + + + + +Design: RAM2GS Date: 08/15/23 05:03:22 + +Design Summary (cont) +--------------------- + Net RCLK_c_enable_11: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs + Net RCLK_c_enable_25: 1 loads, 1 LSLICEs + Number of LSRs: 9 + Net RASr2: 1 loads, 1 LSLICEs + Net Ready: 7 loads, 7 LSLICEs + Net C1Submitted_N_237: 2 loads, 2 LSLICEs + Net n2469: 1 loads, 1 LSLICEs + Net nRowColSel_N_35: 1 loads, 1 LSLICEs + Net n1846: 2 loads, 2 LSLICEs + Net LEDEN_N_82: 1 loads, 1 LSLICEs + Net nRowColSel_N_34: 1 loads, 1 LSLICEs + Net nRWE_N_177: 1 loads, 1 LSLICEs + Number of nets driven by tri-state buffers: 0 + Top 10 highest fanout non-clock nets: + Net Ready: 23 loads + Net InitReady: 17 loads + Net RASr2: 14 loads + Net nRowColSel: 13 loads + Net MAin_c_0: 12 loads + Net nRowColSel_N_35: 12 loads + Net Din_c_3: 11 loads + Net Din_c_6: 11 loads + Net MAin_c_1: 11 loads + Net Din_c_4: 10 loads + + + + + Number of warnings: 0 + Number of errors: 0 + + +Design Errors/Warnings +---------------------- + + No errors or warnings present. + +IO (PIO) Attributes +------------------- + ++---------------------+-----------+-----------+------------+------------+ +| IO Name | Direction | Levelmode | IO | FIXEDDELAY | +| | | IO_TYPE | Register | | ++---------------------+-----------+-----------+------------+------------+ +| RD[7] | BIDIR | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[6] | BIDIR | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[5] | BIDIR | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[4] | BIDIR | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[3] | BIDIR | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[2] | BIDIR | LVCMOS33 | | | + + Page 2 + + + + +Design: RAM2GS Date: 08/15/23 05:03:22 + +IO (PIO) Attributes (cont) +-------------------------- ++---------------------+-----------+-----------+------------+------------+ +| RD[1] | BIDIR | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[0] | BIDIR | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[7] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[6] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[5] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[4] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[3] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[2] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[1] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[0] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| LED | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RBA[1] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RBA[0] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[11] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[10] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[9] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[8] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[7] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[6] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[5] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[4] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[3] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[2] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[1] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[0] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nRCS | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RCKE | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nRWE | OUTPUT | LVCMOS33 | | | + + Page 3 + + + + +Design: RAM2GS Date: 08/15/23 05:03:22 + +IO (PIO) Attributes (cont) +-------------------------- ++---------------------+-----------+-----------+------------+------------+ +| nRRAS | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nRCAS | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RDQMH | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RDQML | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nUFMCS | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| UFMCLK | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| UFMSDI | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| PHI2 | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[9] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[8] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[7] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[6] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[5] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[4] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[3] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[2] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[1] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[0] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| CROW[1] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| CROW[0] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[7] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[6] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[5] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[4] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[3] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[2] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[1] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[0] | INPUT | LVCMOS33 | | | + + Page 4 + + + + +Design: RAM2GS Date: 08/15/23 05:03:22 + +IO (PIO) Attributes (cont) +-------------------------- ++---------------------+-----------+-----------+------------+------------+ +| nCCAS | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nCRAS | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nFWE | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RCLK | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| UFMSDO | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ + +Removed logic +------------- + +Block i2 undriven or does not drive anything - clipped. +Block GSR_INST undriven or does not drive anything - clipped. +Signal nCRAS_N_9 was merged into signal nCRAS_c +Signal nCCAS_N_3 was merged into signal nCCAS_c +Signal PHI2_N_120 was merged into signal PHI2_c +Signal RASr2_N_63 was merged into signal RASr2 +Signal n1426 was merged into signal nRowColSel_N_35 +Signal nRWE_N_176 was merged into signal nRWE_N_177 +Signal n1425 was merged into signal nRowColSel_N_34 +Signal nFWE_N_5 was merged into signal nFWE_c +Signal n2477 was merged into signal Ready +Signal GND_net undriven or does not drive anything - clipped. +Signal VCC_net undriven or does not drive anything - clipped. +Signal FS_610_add_4_18/CO1 undriven or does not drive anything - clipped. +Signal FS_610_add_4_18/CO0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_10/CO0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_4/CO0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_12/CO0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_2/CO0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_14/CO0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_6/CO0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_16/CO0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_8/CO0 undriven or does not drive anything - clipped. +Block i2135 was optimized away. +Block i2134 was optimized away. +Block i2136 was optimized away. +Block RASr2_I_0_1_lut was optimized away. +Block i1137_1_lut was optimized away. +Block nRWE_I_50_1_lut was optimized away. +Block i1136_1_lut was optimized away. +Block i1_1_lut was optimized away. +Block i637_1_lut_rep_34 was optimized away. +Block i1 was optimized away. + +Run Time and Memory Usage +------------------------- + + Total CPU Time: 0 secs + Total REAL Time: 0 secs + Peak Memory Usage: 30 MB + + + Page 5 + + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. + Copyright (c) 1995 AT&T Corp. All rights reserved. + Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. + Copyright (c) 2001 Agere Systems All rights reserved. + Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights + reserved. diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mt b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mt new file mode 100644 index 0000000..2d70ad1 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mt @@ -0,0 +1,9 @@ +-v +1 + + +-gt + + +-mapchkpnt 0 +-sethld diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.n2e b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.n2e new file mode 100644 index 0000000..737af10 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.n2e @@ -0,0 +1,596 @@ + +comp 0: SLICE_0 (FSLICE) + +comp 1: SLICE_1 (FSLICE) + +comp 2: SLICE_2 (FSLICE) + +comp 3: SLICE_3 (FSLICE) + +comp 4: SLICE_4 (FSLICE) + +comp 5: SLICE_5 (FSLICE) + +comp 6: SLICE_6 (FSLICE) + +comp 7: SLICE_7 (FSLICE) + +comp 8: SLICE_8 (FSLICE) + +comp 9: SLICE_9 (FSLICE) +n1413 = (~n2263*(~ADSubmitted*n2242+ADSubmitted*(~n2459+n2242))+n2263*(ADSubmitted*~n2459)) +ADSubmitted.D = n1413 +ADSubmitted.CLK = ~PHI2_c +ADSubmitted.SP = VCC +ADSubmitted.LSR = C1Submitted_N_237 +n2263 = (~MAin_c_1+(~MAin_c_0+n1326)) + +comp 10: SLICE_14 (FSLICE) +n6_adj_3 = (~MAin_c_1*C1Submitted+MAin_c_1*(C1Submitted*(nFWE_c+n1326))) +C1Submitted.D = n6_adj_3 +C1Submitted.CLK = ~PHI2_c +C1Submitted.SP = VCC +C1Submitted.LSR = C1Submitted_N_237 +n2284 = (C1Submitted+Din_c_6) + +comp 11: SLICE_18 (FSLICE) +CmdEnable_N_248 = (n15*(~n1326*(n2463*MAin_c_1))) +CmdEnable.D = CmdEnable_N_248 +CmdEnable.CLK = ~PHI2_c +CmdEnable.SP = PHI2_N_120_enable_7 +CmdEnable.LSR = GND +n1326 = (~MAin_c_5+(~n2316+(~MAin_c_2+n26))) + +comp 12: SLICE_19 (FSLICE) +n2568\001/BUF1 = VCC +CmdSubmitted.D = n2568\001/BUF1 +CmdSubmitted.CLK = ~PHI2_c +CmdSubmitted.SP = PHI2_N_120_enable_5 +CmdSubmitted.LSR = GND +n2472 = (~PHI2r2*(CmdSubmitted*PHI2r3)) + +comp 13: SLICE_23 (FSLICE) +Cmdn8MEGEN_N_264 = (~n1314*(~Din_c_4*n8MEGEN+Din_c_4*~Din_c_0)+n1314*n8MEGEN) +Cmdn8MEGEN.D = Cmdn8MEGEN_N_264 +Cmdn8MEGEN.CLK = ~PHI2_c +Cmdn8MEGEN.SP = PHI2_N_120_enable_4 +Cmdn8MEGEN.LSR = GND +n1314 = ((Din_c_6+Din_c_7)+Din_c_5) + +comp 14: SLICE_25 (FSLICE) +n2568\000/BUF1 = VCC +InitReady.D = n2568\000/BUF1 +InitReady.CLK = RCLK_c +InitReady.SP = RCLK_c_enable_25 +InitReady.LSR = GND +RCLK_c_enable_23 = (nRowColSel_N_35*(RASr2*(InitReady*~Ready))) + +comp 15: SLICE_26 (FSLICE) +n2568 = VCC +LEDEN.D = n2568 +LEDEN.CLK = RCLK_c +LEDEN.SP = RCLK_c_enable_12 +LEDEN.LSR = GND +LED_N_84 = ((~LEDEN+CBR)+nCRAS_c) + +comp 16: SLICE_31 (FSLICE) +n2209 = ((n2208+Ready)+nRCAS_N_165) +RA_0.D = n2209 +RA_0.CLK = RCLK_c +RA_0.SP = VCC +RA_0.LSR = ~nRWE_N_177 +n56 = (~Ready+nRowColSel_N_34) + +comp 17: SLICE_32 (FSLICE) +RA11_N_184 = (~n8MEGEN*(XOR8MEG@Din_c_6)+n8MEGEN*XOR8MEG) +RA_c.D = RA11_N_184 +RA_c.CLK = PHI2_c +RA_c.SP = VCC +RA_c.LSR = ~Ready +n2478 = (Din_c_6+Din_c_7) + +comp 18: SLICE_34 (FSLICE) +RCKEEN_N_121 = (~Ready*InitReady+Ready*RCKEEN_N_122) +RCKEEN.D = RCKEEN_N_121 +RCKEEN.CLK = RCLK_c +RCKEEN.SP = RCLK_c_enable_4 +RCKEEN.LSR = GND +n2467 = ((InitReady*RASr2)+Ready) + +comp 19: SLICE_35 (FSLICE) +RCKE_N_132 = (~RASr3*(~RASr2*(RCKEEN*RASr)+RASr2*RCKEEN)+RASr3*(~RASr2+RCKEEN)) +RCKE_c.D = RCKE_N_132 +RCKE_c.CLK = RCLK_c +RCKE_c.SP = VCC +RCKE_c.LSR = GND +nRWE_N_182 = (~RCKE_c+RASr2) +CASr2.D = CASr +CASr2.CLK = RCLK_c +CASr2.SP = VCC +CASr2.LSR = GND + +comp 20: SLICE_36 (FSLICE) +n2568\002/BUF1 = VCC +Ready.D = n2568\002/BUF1 +Ready.CLK = RCLK_c +Ready.SP = Ready_N_292 +Ready.LSR = GND +n2469 = (~Ready+nRowColSel_N_35) + +comp 21: SLICE_43 (FSLICE) +UFMCLK_N_224 = (~InitReady*n1160+InitReady*CmdUFMCLK) +UFMCLK_c.D = UFMCLK_N_224 +UFMCLK_c.CLK = RCLK_c +UFMCLK_c.SP = RCLK_c_enable_24 +UFMCLK_c.LSR = n1846 +n1160 = (~FS_1*(~n2462*FS_4)+FS_1*(~n2462*FS_4+n2462*~n62)) + +comp 22: SLICE_44 (FSLICE) +UFMSDI_N_231 = (~CmdUFMSDI*(~InitReady*(~n2462*n2461))+CmdUFMSDI*((~n2462*n2461)+InitReady)) +UFMSDI_c.D = UFMSDI_N_231 +UFMSDI_c.CLK = RCLK_c +UFMSDI_c.SP = RCLK_c_enable_24 +UFMSDI_c.LSR = n1846 +n2462 = (~FS_11+((n2471+n2272)+n2470)) + +comp 23: SLICE_49 (FSLICE) +XOR8MEG_N_110 = (~n2324*(Din_c_2*(~Din_c_3*Din_c_0))) +XOR8MEG.D = XOR8MEG_N_110 +XOR8MEG.CLK = ~PHI2_c +XOR8MEG.SP = PHI2_N_120_enable_1 +XOR8MEG.LSR = GND +n2324 = (~Din_c_1*(Din_c_4+n1314)+Din_c_1*((Din_c_4+LEDEN)+n1314)) + +comp 24: SLICE_56 (FSLICE) +n8MEGEN_N_91 = (~n1325*(~InitReady*~UFMSDO_c+InitReady*Cmdn8MEGEN)+n1325*Cmdn8MEGEN) +n8MEGEN.D = n8MEGEN_N_91 +n8MEGEN.CLK = RCLK_c +n8MEGEN.SP = RCLK_c_enable_11 +n8MEGEN.LSR = GND +n1325 = (~FS_10+(~FS_11+n2464)) + +comp 25: SLICE_58 (FSLICE) +nRCAS_N_161 = (((~CBR*Ready)+(n2427*~Ready)+(n2427*~CBR)+~RASr2)*nRowColSel_N_35)+((nRowColSel_N_34+~n15_adj_1+~Ready)*~nRowColSel_N_35) +nRCAS_c.D = nRCAS_N_161 +nRCAS_c.CLK = RCLK_c +nRCAS_c.SP = RCLK_c_enable_4 +nRCAS_c.LSR = GND + +comp 26: SLICE_60 (FSLICE) +nRCS_N_136 = (~nRowColSel_N_35*(~n2467+n2481)+nRowColSel_N_35*(~n13+n2481)) +nRCS_c.D = nRCS_N_136 +nRCS_c.CLK = RCLK_c +nRCS_c.SP = RCLK_c_enable_4 +nRCS_c.LSR = GND +n13 = (~Ready*(InitReady*RASr2)+Ready*(RASr2+RCKE_c)) + +comp 27: SLICE_61 (FSLICE) +n2138 = (((nRCS_N_139*~Ready)+~n13)*nRowColSel_N_35)+((n56+nRRAS_c+n6+nRowColSel_N_32)*~nRowColSel_N_35) +nRRAS_c.D = n2138 +nRRAS_c.CLK = RCLK_c +nRRAS_c.SP = VCC +nRRAS_c.LSR = GND + +comp 28: SLICE_63 (FSLICE) +nRWE_N_171 = (~n2208*(~Ready*~n33+Ready*nRWE_N_178)+n2208*(~Ready+nRWE_N_178)) +nRWE_c.D = nRWE_N_171 +nRWE_c.CLK = RCLK_c +nRWE_c.SP = RCLK_c_enable_3 +nRWE_c.LSR = GND +n2208 = ((~InitReady+(~RASr2+~nRowColSel_N_35))+nRCS_N_139) + +comp 29: SLICE_64 (FSLICE) +n1410 = (~nRowColSel_N_32*(nRowColSel+n1502)+nRowColSel_N_32*(~nRowColSel_N_28+n1502)) +nRowColSel.D = n1410 +nRowColSel.CLK = RCLK_c +nRowColSel.SP = VCC +nRowColSel.LSR = n2469 +RA_1_9 = (~nRowColSel*RowA_9+nRowColSel*MAin_c_9) + +comp 30: SLICE_65 (FSLICE) +n1503 = (nRowColSel_N_32+nRowColSel_N_33) +nRowColSel_N_32.D = n1503 +nRowColSel_N_32.CLK = RCLK_c +nRowColSel_N_32.SP = VCC +nRowColSel_N_32.LSR = ~RASr2 +n2414 = (InitReady*(Ready_N_296*(~RASr2*nRowColSel_N_32))) + +comp 31: SLICE_66 (FSLICE) +n1093 = (RASr2*~nRowColSel_N_32) +nRowColSel_N_33.D = n1093 +nRowColSel_N_33.CLK = RCLK_c +nRowColSel_N_33.SP = VCC +nRowColSel_N_33.LSR = ~nRowColSel_N_34 +RCLK_c_enable_4 = (((nRowColSel_N_32+n2469)+nRowColSel_N_34)+nRowColSel_N_33) + +comp 32: SLICE_67 (FSLICE) +n11 = (~CASr2+nRowColSel_N_33) +nRowColSel_N_34.D = n1093 +nRowColSel_N_34.CLK = RCLK_c +nRowColSel_N_34.SP = VCC +nRowColSel_N_34.LSR = ~nRowColSel_N_35 +n1417 = (~n2472*nUFMCS_c+n2472*~CmdUFMCS) + +comp 33: SLICE_68 (FSLICE) +n2322 = (((FS_0+FS_1)+FS_6)+FS_3) +nRowColSel_N_35.D = ~RASr2 +nRowColSel_N_35.CLK = RCLK_c +nRowColSel_N_35.SP = VCC +nRowColSel_N_35.LSR = GND +n2471 = (FS_17+FS_12) +CASr3.D = CASr2 +CASr3.CLK = RCLK_c +CASr3.SP = VCC +CASr3.LSR = GND + +comp 34: SLICE_69 (FSLICE) +n2164 = (~InitReady*n62+InitReady*n1417) +nUFMCS_c.D = n2164 +nUFMCS_c.CLK = RCLK_c +nUFMCS_c.SP = VCC +nUFMCS_c.LSR = LEDEN_N_82 +n62 = (FS_14*(FS_12*(n12*FS_17))) + +comp 35: RCKEEN_I_0_445/SLICE_70 (FSLICE) +RCKEEN_N_122 = (((~FWEr*~CBR)+~RASr2)*nRowColSel_N_35)+(((FWEr*n11*~CBR)+(nRowColSel_N_34*~CBR))*~nRowColSel_N_35) + +comp 36: i26/SLICE_71 (FSLICE) +n13_adj_2 = ((~n2284*n2476*MAin_c_1*MAin_c_0)*Din_c_2)+((~ADSubmitted*~MAin_c_0*n2475*~Din_c_5)*~Din_c_2) + +comp 37: i2099/SLICE_72 (FSLICE) +n2481 = (((nRowColSel_N_35*~Ready*nRCS_N_139)+(nRowColSel_N_34*~Ready*nRCS_N_139)+(~nRowColSel_N_35*~Ready)+(nRowColSel_N_34*~nRowColSel_N_35))*n15_adj_1)+(((~Ready*nRCS_N_139)+~nRowColSel_N_35)*~n15_adj_1) + +comp 38: i26_adj_28/SLICE_73 (FSLICE) +n15 = ((MAin_c_0*Din_c_2*Din_c_3*~Din_c_6)*Din_c_5)+((~MAin_c_0*~Din_c_2*~Din_c_3*Din_c_6)*~Din_c_5) + +comp 39: SLICE_74 (FSLICE) +n1 = (~CASr3*(CASr2*(FWEr*~CBR))) +RASr2.D = RASr +RASr2.CLK = RCLK_c +RASr2.SP = VCC +RASr2.LSR = GND +n15_adj_1 = (~n1*(nRowColSel_N_33*(~CBR*~FWEr))+n1*(~nRowColSel_N_33+(~CBR*~FWEr))) +RASr3.D = RASr2 +RASr3.CLK = RCLK_c +RASr3.SP = VCC +RASr3.LSR = GND + +comp 40: SLICE_75 (FSLICE) +n2214 = (FS_11*(~n2272*(~n2328*FS_10))) +RCLK_c_enable_12 = (~InitReady*(FS_11*n2214)) + +comp 41: SLICE_76 (FSLICE) +PHI2_N_120_enable_4 = (n2458*(~Din_c_4*~Din_c_5+Din_c_4*(~Din_c_5+Din_c_3))) +n732.D = n733 +n732.CLK = RCLK_c +n732.SP = RCLK_c_enable_23 +n732.LSR = GND +n2458 = (MAin_c_0*(n10*(~n1326*~nFWE_c))) +nRWE_N_177.D = n732 +nRWE_N_177.CLK = RCLK_c +nRWE_N_177.SP = RCLK_c_enable_23 +nRWE_N_177.LSR = GND + +comp 42: SLICE_77 (FSLICE) +n2290 = ((FS_2+FS_5)+FS_9) +n728.D = n729 +n728.CLK = RCLK_c +n728.SP = RCLK_c_enable_23 +n728.LSR = GND +n8 = (~FS_7*(~n2322*(FS_4*~n2290))) +n727.D = n728 +n727.CLK = RCLK_c +n727.SP = RCLK_c_enable_23 +n727.LSR = GND + +comp 43: SLICE_78 (FSLICE) +n1846 = (~InitReady*(~n2464*~FS_11)) +RowA_6.D = MAin_c_6 +RowA_6.CLK = ~nCRAS_c +RowA_6.SP = VCC +RowA_6.LSR = ~Ready +n2464 = (((FS_16+FS_14)+n2272)+n2471) +RowA_7.D = MAin_c_7 +RowA_7.CLK = ~nCRAS_c +RowA_7.SP = VCC +RowA_7.LSR = ~Ready + +comp 44: SLICE_79 (FSLICE) +C1Submitted_N_237 = (n2468*(~n1280*(n2463*~Din_c_2))) +CASr.D = ~nCCAS_c +CASr.CLK = RCLK_c +CASr.SP = VCC +CASr.LSR = GND +n2468 = (~Din_c_5*(~Din_c_3*Din_c_6)) +PHI2r2.D = PHI2r +PHI2r2.CLK = RCLK_c +PHI2r2.SP = VCC +PHI2r2.LSR = GND + +comp 45: SLICE_80 (FSLICE) +RCLK_c_enable_3 = (((~Ready+nRowColSel_N_32)+n1502)+nRowColSel_N_35) +n726.D = n727 +n726.CLK = RCLK_c +n726.SP = RCLK_c_enable_23 +n726.LSR = GND +n1502 = (nRowColSel_N_34+nRowColSel_N_33) +Ready_N_296.D = n726 +Ready_N_296.CLK = RCLK_c +Ready_N_296.SP = RCLK_c_enable_23 +Ready_N_296.LSR = GND + +comp 46: SLICE_81 (FSLICE) +n26 = (~Bank_5+(~n2278+(~n2314+Bank_2))) +CmdUFMCLK.D = Din_c_1 +CmdUFMCLK.CLK = ~PHI2_c +CmdUFMCLK.SP = PHI2_N_120_enable_6 +CmdUFMCLK.LSR = GND +n2278 = (Bank_3*Bank_6) +CmdUFMCS.D = Din_c_2 +CmdUFMCS.CLK = ~PHI2_c +CmdUFMCS.SP = PHI2_N_120_enable_6 +CmdUFMCS.LSR = GND + +comp 47: SLICE_82 (FSLICE) +n2460 = (nFWE_c+n1326) +n730.D = nRWE_N_177 +n730.CLK = RCLK_c +n730.SP = RCLK_c_enable_23 +n730.LSR = GND +PHI2_N_120_enable_7 = (~MAin_c_1*(~n14*(~n2460*MAin_c_0))+MAin_c_1*(~n14*~n2460)) +n729.D = n730 +n729.CLK = RCLK_c +n729.SP = RCLK_c_enable_23 +n729.LSR = GND + +comp 48: SLICE_83 (FSLICE) +n10 = (~MAin_c_1*(CmdEnable*(~n2478*Din_c_4))) +RASr.D = ~nCRAS_c +RASr.CLK = RCLK_c +RASr.SP = VCC +RASr.LSR = GND +PHI2_N_120_enable_6 = (n2476*(~n2460*(n10*MAin_c_0))) + +comp 49: SLICE_84 (FSLICE) +n2262 = ((~MAin_c_0+n1326)+MAin_c_1) +n738.D = nRCAS_N_165 +n738.CLK = RCLK_c +n738.SP = RCLK_c_enable_23 +n738.LSR = GND +PHI2_N_120_enable_1 = (~n1314*(~n2262*(CmdEnable*~n2473))) +n737.D = n738 +n737.CLK = RCLK_c +n737.SP = RCLK_c_enable_23 +n737.LSR = GND + +comp 50: SLICE_85 (FSLICE) +n2473 = (Din_c_4+nFWE_c) +RBA_c_0.D = CROW_c_0 +RBA_c_0.CLK = ~nCRAS_c +RBA_c_0.SP = VCC +RBA_c_0.LSR = ~Ready +n2242 = (n2474*(Din_c_5*(n2253*~n2473))) +RBA_c_1.D = CROW_c_1 +RBA_c_1.CLK = ~nCRAS_c +RBA_c_1.SP = VCC +RBA_c_1.LSR = ~Ready + +comp 51: SLICE_86 (FSLICE) +n2463 = (n2253*(~nFWE_c*~Din_c_4)) +n734.D = n735 +n734.CLK = RCLK_c +n734.SP = RCLK_c_enable_23 +n734.LSR = GND +n2253 = (~Din_c_1*(Din_c_0*Din_c_7)) +n733.D = n734 +n733.CLK = RCLK_c +n733.SP = RCLK_c_enable_23 +n733.LSR = GND + +comp 52: SLICE_87 (FSLICE) +RCLK_c_enable_11 = (~n8*(InitReady*n2472)+n8*(~InitReady*n7+InitReady*n2472)) +nRCS_N_139.D = Ready_N_296 +nRCS_N_139.CLK = RCLK_c +nRCS_N_139.SP = RCLK_c_enable_23 +nRCS_N_139.LSR = GND +n7 = (n2214*~FS_8) +nRCAS_N_165.D = nRCS_N_139 +nRCAS_N_165.CLK = RCLK_c +nRCAS_N_165.SP = RCLK_c_enable_23 +nRCAS_N_165.LSR = GND + +comp 53: SLICE_88 (FSLICE) +n2451 = (~FS_8*(~FS_5*(~FS_9*FS_7)+FS_5*(FS_9@FS_7))) +Bank_0.D = Din_c_0 +Bank_0.CLK = PHI2_c +Bank_0.SP = VCC +Bank_0.LSR = GND +n2461 = (~FS_10*(FS_6*n2451)) +Bank_1.D = Din_c_1 +Bank_1.CLK = PHI2_c +Bank_1.SP = VCC +Bank_1.LSR = GND + +comp 54: SLICE_89 (FSLICE) +n1280 = ((~MAin_c_1+n1326)+MAin_c_0) +WRD_0.D = Din_c_0 +WRD_0.CLK = ~nCCAS_c +WRD_0.SP = VCC +WRD_0.LSR = GND +n2459 = (MAin_c_1*(~n1326*~nFWE_c)) +WRD_1.D = Din_c_1 +WRD_1.CLK = ~nCCAS_c +WRD_1.SP = VCC +WRD_1.LSR = GND + +comp 55: SLICE_90 (FSLICE) +n2470 = (FS_16+FS_14) +RowA_8.D = MAin_c_8 +RowA_8.CLK = ~nCRAS_c +RowA_8.SP = VCC +RowA_8.LSR = ~Ready +n2328 = (((FS_17+FS_12)+FS_14)+FS_16) +RowA_9.D = MAin_c_9 +RowA_9.CLK = ~nCRAS_c +RowA_9.SP = VCC +RowA_9.LSR = ~Ready + +comp 56: SLICE_91 (FSLICE) +PHI2_N_120_enable_5 = (n2458*(~Din_c_5*Din_c_4+Din_c_5*(Din_c_4*Din_c_3))) +PHI2r3.D = PHI2r2 +PHI2r3.CLK = RCLK_c +PHI2r3.SP = VCC +PHI2r3.LSR = GND +n2476 = (Din_c_5*Din_c_3) +PHI2r.D = PHI2_c +PHI2r.CLK = RCLK_c +PHI2r.SP = VCC +PHI2r.LSR = GND + +comp 57: SLICE_92 (FSLICE) +n2474 = (Din_c_3*(Din_c_2*~Din_c_6)) +WRD_6.D = Din_c_6 +WRD_6.CLK = ~nCCAS_c +WRD_6.SP = VCC +WRD_6.LSR = GND +n2475 = (~Din_c_3*Din_c_6) +WRD_7.D = Din_c_7 +WRD_7.CLK = ~nCCAS_c +WRD_7.SP = VCC +WRD_7.LSR = GND + +comp 58: SLICE_93 (FSLICE) +RDQMH_c = (~nRowColSel+MAin_c_9) +CmdUFMSDI.D = Din_c_0 +CmdUFMSDI.CLK = ~PHI2_c +CmdUFMSDI.SP = PHI2_N_120_enable_6 +CmdUFMSDI.LSR = GND +RDQML_c = (~nRowColSel+~MAin_c_9) + +comp 59: SLICE_94 (FSLICE) +n12 = (FS_11*(FS_16*(FS_13*FS_15))) +n2272 = (FS_13+FS_15) + +comp 60: SLICE_95 (FSLICE) +LEDEN_N_82 = (~InitReady*(~FS_10*(~n2464*~FS_11))) +RowA_4.D = MAin_c_4 +RowA_4.CLK = ~nCRAS_c +RowA_4.SP = VCC +RowA_4.LSR = ~Ready +RCLK_c_enable_25 = (FS_10*n62) +RowA_5.D = MAin_c_5 +RowA_5.CLK = ~nCRAS_c +RowA_5.SP = VCC +RowA_5.LSR = ~Ready + +comp 61: SLICE_96 (FSLICE) +n2316 = (Bank_1*(Bank_4*(MAin_c_3*MAin_c_7))) +RowA_2.D = MAin_c_2 +RowA_2.CLK = ~nCRAS_c +RowA_2.SP = VCC +RowA_2.LSR = ~Ready +RA_1_3 = (~nRowColSel*RowA_3+nRowColSel*MAin_c_3) +RowA_3.D = MAin_c_3 +RowA_3.CLK = ~nCRAS_c +RowA_3.SP = VCC +RowA_3.LSR = ~Ready + +comp 62: SLICE_97 (FSLICE) +n2314 = (Bank_0*(Bank_7*(MAin_c_4*MAin_c_6))) +RowA_0.D = MAin_c_0 +RowA_0.CLK = ~nCRAS_c +RowA_0.SP = VCC +RowA_0.LSR = ~Ready +RA_1_4 = (~nRowColSel*RowA_4+nRowColSel*MAin_c_4) +RowA_1.D = MAin_c_1 +RowA_1.CLK = ~nCRAS_c +RowA_1.SP = VCC +RowA_1.LSR = ~Ready + +comp 63: SLICE_98 (FSLICE) +RA_1_8 = (~nRowColSel*RowA_8+nRowColSel*MAin_c_8) +CBR.D = ~nCCAS_c +CBR.CLK = ~nCRAS_c +CBR.SP = VCC +CBR.LSR = GND +RA_1_0 = (~nRowColSel*RowA_0+nRowColSel*MAin_c_0) +FWEr.D = ~nFWE_c +FWEr.CLK = ~nCRAS_c +FWEr.SP = VCC +FWEr.LSR = GND + +comp 64: SLICE_99 (FSLICE) +RA_1_7 = (~nRowColSel*RowA_7+nRowColSel*MAin_c_7) +Bank_6.D = Din_c_6 +Bank_6.CLK = PHI2_c +Bank_6.SP = VCC +Bank_6.LSR = GND +RA_1_1 = (~nRowColSel*RowA_1+nRowColSel*MAin_c_1) +Bank_7.D = Din_c_7 +Bank_7.CLK = PHI2_c +Bank_7.SP = VCC +Bank_7.LSR = GND + +comp 65: SLICE_100 (FSLICE) +RCLK_c_enable_24 = (~InitReady+(~PHI2r2*(CmdSubmitted*PHI2r3))) +n736.D = n737 +n736.CLK = RCLK_c +n736.SP = RCLK_c_enable_23 +n736.LSR = GND +n6 = (~Ready*((~InitReady+~RASr2)+nRowColSel_N_33)+Ready*nRowColSel_N_33) +n735.D = n736 +n735.CLK = RCLK_c +n735.SP = RCLK_c_enable_23 +n735.LSR = GND + +comp 66: SLICE_101 (FSLICE) +RA_1_6 = (~nRowColSel*RowA_6+nRowColSel*MAin_c_6) +Bank_4.D = Din_c_4 +Bank_4.CLK = PHI2_c +Bank_4.SP = VCC +Bank_4.LSR = GND +RA_1_2 = (~nRowColSel*RowA_2+nRowColSel*MAin_c_2) +Bank_5.D = Din_c_5 +Bank_5.CLK = PHI2_c +Bank_5.SP = VCC +Bank_5.LSR = GND + +comp 67: SLICE_102 (FSLICE) +n2427 = ((~InitReady+nRCS_N_139)+nRCAS_N_165) +Bank_2.D = Din_c_2 +Bank_2.CLK = PHI2_c +Bank_2.SP = VCC +Bank_2.LSR = GND +n33 = (nRCAS_N_165+nRWE_N_177) +Bank_3.D = Din_c_3 +Bank_3.CLK = PHI2_c +Bank_3.SP = VCC +Bank_3.LSR = GND + +comp 68: SLICE_103 (FSLICE) +nRowColSel_N_28 = ((~FWEr+CASr3)+CBR) +WRD_2.D = Din_c_2 +WRD_2.CLK = ~nCCAS_c +WRD_2.SP = VCC +WRD_2.LSR = GND +RA_1_5 = (~nRowColSel*RowA_5+nRowColSel*MAin_c_5) +WRD_3.D = Din_c_3 +WRD_3.CLK = ~nCCAS_c +WRD_3.SP = VCC +WRD_3.LSR = GND + +comp 69: SLICE_104 (FSLICE) +nRWE_N_178 = (~nRowColSel_N_35*(~n1+n1502)+nRowColSel_N_35*nRWE_N_182) +Ready_N_292 = (n2414+Ready) + +comp 70: SLICE_105 (FSLICE) +n14 = (n13_adj_2*(~Din_c_4*n2253)) +WRD_4.D = Din_c_4 +WRD_4.CLK = ~nCCAS_c +WRD_4.SP = VCC +WRD_4.LSR = GND +n984 = (nCCAS_c+nFWE_c) +WRD_5.D = Din_c_5 +WRD_5.CLK = ~nCCAS_c +WRD_5.SP = VCC +WRD_5.LSR = GND diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.ncd b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.ncd new file mode 100644 index 0000000000000000000000000000000000000000..405a3aa5b24a3654c262d61b46b40f69d2d492db GIT binary patch literal 163428 zcmeFa37lM2l|NqD_XG%AIxNi+x=Dz1Raf;A45Yd{2~Czxx|0CL&?F>aAn621L|h;! zh^P$WGL8#^0wUr%iW@GtEAIMJXGRne&{4-h$5BTe=>PYebHDH2`|4G9BPn41_WOKp z)v5E&-Ol~qbI)DgtHTca?Qh2vKJud6xZJqj@~Xn}zTDOyo%WnDxiLF0EM3sllv~-k z>a3oYVpC^s-P&bq^58V*a2+ZiBffrvH-8~)a`?|Z%T9hAypHq}M%`=;Xn@e+5 zc1)UE$dqjs?xeJAQMeP++>&r7q`57^9iQg53Ktr}XHecY;f_sn+l6c8^%d6QPELsy zGAmrr3a2Yk&=k^@C}@S#l_+S1)0HS_h0~QNXob_2C}@S#N-t=It$}>iGIidp+;jrX zTCj8rH*3MBrIgdG1)G}YYQfUTY1V?J)!VEsVT$y{%>+YHTOzI9qP9d@yG3n@w04VH z;k0&(np;}CMXhjJIYq5-S~*3na2gFot#CzowZc|jU*Sxgm$bs^N|dz1=}MHe!s$ws zGF!M5w6HHi(5XB#=u@5aO~2>kd_mruvLy zn^jZAS-q?3&5TwYJ5ak>uPI%-_U_5li`lUu?yFjdxUYI0;=U?&i2JJ9A?}-jsa}57 zZ7P1CJu7}y?U`Mi+}lyk1f3bk>bDIwy@;FzSu>fFtKK%$RK0Dese0Q`6WtE#ZOu}( z-ezE{7R@Ye_1lWc>bI>cMnwxCX-2qu?4gxvX1RK7RqCYPu1vI>ovwOURT|w5G-^Pu zs!_AxQRJY`X34AGRee^ytLm(JS6e!|8x-1lS6t}ewso$mx2S@Z)|_ATx2 zT+`RTs=TIuS@+7N;(Z0Yg-&<4phr*{`(z78GJrJNfv^lWNux6x-R zrW4R+^7mWP_Z43L zekpxlThiYzrtfQ0`uol4``VWNej$Bd8`Ix+3P@CM_4g`nOU1Wg$j49X$Ht-QV#l); zWCKwkkk*j-)`37;MdoG)0%;wY#~lcym1NF$AduFQ`Qd>;8YkwG2Lcs(P(4o==tl6Z)-%mr$rXT)(8fi8L`ul01*_6cJPb=6)L4QB3Uz?^(?d{6$Y&H%iw<~I| zAWd$&$|uTIQxzyTtsEN)ljv#P*jSj{POHYIH_7d^W^A65+)gXTCOpaQv|dVD_VEL~ zo!0x3u2NF_I=;7a<%+nkloYABu_D#EN@`J&RJzxdTo>7D#Z|IZX_ahMSS4GvRmoN*RkBq#WG5QQF18KB6i(`Hqwlz$_3M%r zRaM!bo59!GXYjT98GNmO245AB!B-7r@KpsF{A?X$w~-B$6*{m{vXX6MWQA&MW>{Gi z8yhqDRa9U@VTODa71+p^A+IV(_z4cO0cqn~BAo!iCUzP8Dq3*MXcgMA@hc;pDq67d zDns77LWj3Bic1@x##XQm29BMmAiML~C{&S#jXsrZ>rd$%ZM3PBHmz4kSE;=XE)~$T zp`}tOHnL>!t3V*z%Gh91nTic18T={`XsKcgYz)arr-~9Vwa2&$%2=fpc5l%#ykFWsYB!q!c_<_MR*y))d<%hyd2?L zgjXP3hww^-S0TI_;d+FBK)3fFXM_(S zd>G+wgpVM66yakCA4m8E!aWF|MEDfKrx8Aba4*7V5k80Td4w+@d=cSG2wz6{3c^BK!>DA%uq!9zpmy!Y>g19pRSu4n;T&;c$dG2z3Z^5spAO65%L>qY>&6jzKsU;W&ij z5#}MBfY5-@h;Smpe1ruECm}3EcoxFR2u%oigaSe{LJ^^a(1Os4(1y^Cun6H4gl8ix zMmQDWG=wDxWrPldPJ}Lmr3lLqmLr^w(2Z~g!U}|y2&)iQBlIAwL0F5>i_nL#4q-jQ z281&a&O$gF;W-E!5uS^%3E>=seuQ%oHY037I1gbf!Zw8S5iUS@9>R8n3lT0t*nzMU zVE|zl!fu3%5iUWv6k!j-UWDf(T$Y0!Ue?#&l5gto-wusfcbD&g4=n}!nNEK5)~)@; zerPYaH!Vpk4>f1sfbN4Ev!c}U)rt_O=8GIB78fl}D<~R}5R@Re0eA#AQbns)1mG)( zZRZ9>j78ET`EmgEQIbVco{J5TR(W+H5ZfKtex=v8dRKcoNr)t~8SW6`r zmtorWe7;Zu26yb;6BT0S_I!Uqxc$u)_hyy5`u1+wxqZ)`ZGdl6oZVsD3r#JBFm6Wb z$hN($&4i+CXLaVoq~j{i+TLtw^>5yKVSgcR&MDjT?rxOejLw}~mkw;+vSS-c8Y6wm zK%vyq_S~i>O-N#?&jp*98{e^hnQ&nvalvxuU?mgo3H$IvuUXp*rl0;xw(agO#O-(h zvJNVfkIQ=q?hdrATDpAc>i+Kj_N=lW9JhhhTJqhend4(-kVr8fBPFSxvNeWO1SUPH z2uwUK;lju#+-L2>54{eC!nOIG+ACo)qkCZcp5ASnw_e`g+#bVz;?8^pa;58-Qb6d;>stcv8+8w&R)q&k`l9l~bS@#na7##O$f$?#W z@U2kLTxAPPCP*a0KKYPqvc_s|j|(^jt9_RMv2C&ON|2(qPU8zEFi1oJ*)14T1JFw5`{YBeL#QlmhpMS#Jrb$MXp4)|qxzPp@=xG;3^l z5AuCKU(AS@)%RnyO=Akhe4O+I6vi4}>nx474q^QA@;dljxxRh)&}#}7r^|ilxN-bh zP?F+I4Ngi82Lj{GuD}_^o-FI#NHK1iaoeq_G*>AP{IsMzXYW%sK2RPkWFvO0`GaKP z+j>ALYp6OnF~Yvoag9(aq|n?R8yD$0mHlas>^%0jJ3CNl?cWYVQaJ|B9O&J3S?8`D zecN`RZDTZu0&VP6s}=XbS=I>zrInda?(1LHx2k`8s-@AOrPhqma%Nm}(c?b(kc&yh zT|HH__@+7oS@w%*#nn{Mw`A1fAn6UozxqU6m%W6?eUPO zY|(10?8)0(Gt@Vkc#_=q$%kAr&RWl^RQMs=St7Ce`K<0awcDDze|wAq&yTyM_=fFS zBV@_~$Ei(Aa!H$JeX{Xrq&qASz~ytIq`3;YspBFnj!cO5^KWqW8I0_Z3@k9b6np;*t^3lT?NmNp$&{xvsjhhzfUCAfak|G)G2bmdXANCdxW@^ z1-)s5x>~xnj4^3a$L4{H`nShh%rHc?#<@&UBL{X2 z5RWQND_!BxqBh5nH4Vk788220>{bZ|trAvZVp^OD66NfZ54oH{vuQ(YG$&(#ti+U< z#@4JUk_<|4a;r6mSEPEDas6Dg#Q8gB+|AW$89Sa<+J8R zl^JD?elDX_hq6&OZurXdvi#UesVvuWQfEgmCJS+{lX2ut2I3g>l?i6qg-R(5-4(ib zh9btNW5xjWxCtDr%48l2ul!x=oJrGV2m&HGLpoWuTdbfd*>1q1qGq7LkuL5c!sB@+Fav zGZ*<%HTj~*$IUA8#cJ}+A|H1Kk#DXhUl93t;1T&kHTk^A$3{Tp^VQ_BC)Ap1Es<}E z<)D&v)a53SO!o6_ZLrgfOZ7&=f zc@s{l+6%{h!h}7=0p`!X5=<C5lpoW1>>d>!F0>$QfL}%b|5%Jn=RE> z$jORT1XEkYtdP@F!C`uC6*Vn5K^Iq}6y5r7hNPSdj?&cQz!g0QmP}3wS4ghRmc*`p zFotlgE}cD(5l6Caxu8PU_;I@6i6@>VD+i6kbSKLkqe61LKKB#KO;x`bDfY+xY?3{u z5_cdk9QQR7PW3h~9QQX9PW3o19QQdBPW3u39QQjDPW3!59QQpFPW3)79QQvHPW3=9 z9QQ#JPW3`B9QQ*LPW41D9QQ>NPW8sA@<5febjqktvInhFEtm+WQdZ$q%2QVxZzYZ)ozJs+-xeEYPCc(ZZs85 zwOJw>D^^9*detYFDmtfopegK~Q}jutEJ=ATB9xpgPcBsm+Vf12oIIUTDW}hDgmSVK z+1J%mA;~8fLfKbh|8yc4(RJT_eJi^=m-aX1^z7#{{gvx&?ksjGXB?zI(z|r|s-CW; zi{-;=gRgF3;;X)^J1=Bk9#oT3P4!Zk zMT`2H7B{`%{LPy;pVXIkl$KbdpDk+uGlU6jXkkZ<(iKYc7rh0HUtg`lFe9yA8TzgpSR}&O=%M#65rHA&89}VIU|T^&n#H-lJcEa}BD^ zX{eU|ZlOBOLv`vXRQ1`OET|gd)N87A02Er;R<*4vRPXfARGD}A-O0* zRqsW4o`kQe{u}(#{p7Q1a>IG8*l#O6d9QV*2knee(CR~I8KAXCU9(+*f_r(LI=*T9 zYEP3IpkuGK$%9lu`(giEKs)9T18pe{+EPaX+P||2)`1?X2aG~hpOMUfs=Wjz8>)E+ z)x;GDXI}+-GfS2)aF@rXV)fnrw_^1O!)i+!tHr-ttRC#KI(rnW`V4OdR^4lPvVDQ( zlrIor)fr^9xv^dSkjJKC^`HH3#p*GJ)z&mtOWqmyJF}~Yd8{5fidB8aJOiutYOHE@ zRiE6qVLt8D;;{ocFr8&r-|MldSbdNGtyn$Qu-cZ!YKzC}`=6ZS`Xn6Ir*?I<&VzK$ zC`k3?2N@vE>$@VVfHa?4U5yQ@AvnXJ-tIxEAid51R*)WVAZ?F9+S1w1g#fgdMj3-w zK#bQl;mKIXn2HxbOvlR~X2Rz_055$w2rqm%7z4$jc+tb*xzD6wy|QO{cW3>I{Gvst z=NC6#QC`q^MdyO96HlyP(F9f#Se^61p5L*cjPI@m9Vec+0G#stD?~^f9@}e>ZH8s} zMa$}!HQ}SmhQp#ovhA?=xbD>((t8hBI_K^K$o`%UOMCk}msadS47-T{i*RIa>U?6ou4rKy;S**kEc@z`Hz^S>3|_Tp;Y zO;88K&BJh3EZXU6>1?GDo`c33i)ReS0o#J`33$!PaQOb{(D*Jd=nRnEF~7W^L$KVa zkauuivd^)aKk*0<#dP~t5v_lk2dRvwhP&v2ywEg;2v zED{haNXuq}aUd`PX{ocFdtBZKPjE0D9;ELZ8l+crzz8RX*yB|VFt9owHh4dnUbC*U zYdg%o??`O!am41anbVatNe@kbm+{zk|j#Yla46BfL?VP#Dl>5)hjS z#6l(zi=#kPAWo<-h3+4mGR$YY&f^WC(HM`H_a(n|jPLZn)kt1zxNJ@x1T1tWOaC(F z%RGK8$}>sF{o(!4iUruzN|nHpm~6xZzC%GO&I?wV@b$!I@EOZdNCqoWwpiuP#Xi}U zsTRVvlnL9`QP>8fel$yRuT;($+-=87Jk#{BZ~xSgh3NF!R6`2U&eGy}@o3s#=xh(y zrUcJpbmest@*W=1?;hIH3WO6tW5uE=N5zU~VUv+cLqt zXcWu=n8WctuU0eL7qI^~$wG6Ry{@`qo%MwtyK0^1``?<+EN7il>#WV83u{QmUYc6x zkzo0shQ=}$sk%-~;kgr72EzX~Ebmu0_Sr=4DVfM!Jc``Fdx*@iy_8?JSJKATUi+VA zY!`Y!DnPIBzZIY-JAkI@kEvV-O8sV+ z;1!!=c%r3iaZ>=^kImZPkZH7Ol$Hk7U{PG$Q#_hh#WfWhHe3Y{@8+70Ht; z;A;QNCUC9v8~pPLl`wDBRj*9@Y<~$-VW0PUxGVgh>whc!5A(k@g&D3pq-J@|;R>4V ziiy1*>8kFlhv^O-&$JodQX;!6(?%~FMYbZlaX!I=FWm&X&9@^UQfjT{lG97bO#Oee1SW0poa{SlL+vI_m2;;9}gRxPMj{!#A){^ zP6IDE^d<65?nr?d+4zPCA!_UBfU?iYc5Wms?7DGGca0lv?BaG!U?`QY} zHL~(Negu=cj|~HA?B(j|0<2cVv%4#B@&Nl3I7K7QhLLi*Ch##vbf%_aop(Qidj-LL zMkcsdj)J?Iqg>qzw^p;l_~VWU!1z;-I#3Td6*sFlG?tJE*NmxzvuF6Dj&nSAUxDf5?h-TT?^E@Qg#%}Y! z6{6P|L`x~>wb+?F6YjTv#lDX0NWyKyK@{g@WD7XJrT7wE*!;EGoE({X(sp&2dD}>) zYio(fHJOO)9Yti|EQCvD_HU6{>kjs}s&o~?IPG>k9N08$X7{v@Vak)3)m}F};2i(}9l=;QW#IYAp6U-1ZR*H~O! z^?a+~cBG4ERe}425sO*tnY6+iG7)>$C}OK1*8bwx{DSoQZ(A~(OPp3+T6n(4s$%)Y z{5tP9}VK1u6Z?LA8S!?->t6RI0W zp<2yhNS;ba12ug7F@oxt&wFSpR9E=l3e}_hZ#BCoIJ28tB?EN5o4^Hyk(=FNo?x(( z;av;hCBz$SVsr)9IPECsb)J!ycM~n|b2H(5&M2G%I7iD~?k~hMHs0)CyR(h5`{U#E z$uj%}Xo7r2`Ud}7k-pF&JGE3+=xnK6X^>OABRl_a=g>wO3u1C$H{6!PEKW8i3POso)-HD?uzZTjUKw1ZkPY9 zP<9VVw4`>Ii{b9F9Zj>>>Is;K_b-My$|GxLfUJNySd)>d3%{Hb#CTOm8o|5nJZbJjPth=v{DC-Yp-FpzDu zhbUld%YGS6AD?(;LiT(@c3UQ7FBpYvV16UW+6x!5AnRWnQhD&9=#HPI9st5Wj>ljQ z4ht)o-Bau>74HQJj#A22vOVT&+ZMyy-{Ceb?8#p29&?6gkFIlqXNP%)I!sx84Xwte zcsp_Zyi8nQIEw3PxaQHx%KhX*vHE_p;X2Dq9~UDV|977tU64Jd;LLPtmAJXH#jjlW zb8F@%50C7x4DBS#YFdKnMqPLl2idkaQs>loXwAO|y2^4J!Hx*4n%vtN{??a7KcVAm zI|%lR9N1w929(s}Ydc559)Lacq4S9kU3q-1RCV7YZL9lYMCX?J-@3pt(;+;y;f!NI z9^rB-Q&2wg4d?d^jd0shmPL%fb;e#EUeN#^EjZG6(hqp-ulJ4YCW?1un(T{5Q5>K+ ze5Z&y2;91he3W9<<-1aX{PeEL$sWBbGtU3kj5^}~{B_5UTT`1RI2Z3%?`Xb9zRB06 zFFQ>=s)R>5v8Q)MM`E~f5I))F!+HnpZ@pV7enQ)BmsWz#cIE!Q-;}R9uoJTJ%RpMP zpQ9KXY^o`I&P>7Qa{OU4F_YS?z#A9*x){$z+P3gWj*u;`#0*w)%kyy%oru8!8(B@j zOP8J;SoV&BB{$LjtHK`bvbV=YV2KTpJMWz`He+{rbO>6;oale6u~~yZx@>PJUQ*AI z6+7Gf0BR35;Gb17go=|myog-h0(Au z3f;9*@@j%)3L&@}yT_wOZBDoUty7Gn{GY@VN~z7JQuvT9*D-B}exy=Cb!+3_SV$i4Hmrp7{#{&$??099drJ-p`CVl zT$LM;cAy!r3UnqYbmJkW{=Mv8sxSX!r>uYbo8h0(MD;~<@n7grj5*Isl+=mpi$`7j zDlUF-#z{8fL+?L%Yi6*pqND9u9?@zQgRxe})~Wu!PE)5j#8+(bB!8LVU(z=6C#Fu# z7-bFS;XzXay=?X9eAO?o4C})~8&?ulSB%=mCuAG#b?aG6*!G7lGN+72TKx4`@>?EK5DfP=*7J!GY%|Im+5S%<{2C(sYLD=1 zJ;Gl;itqs8;k>6UdGT81GIhIRHDluiv)~xtuk*h(&ei_6;(MRNcWNUB51n{hPLFrw zFKK;fXnbexmn-P?aOwWWH@0Smcysm>JQDJR%=>i&|0_KBU**C7%2Dtu`0W(~kp;Jx zWmGZm=@-IBkD8P``@}Al|EB)ufMN-<}-{Q4V->(_W(zs}?OwWGKW41Z{&?SE;qW~Xh6(JZ^(mYNEL>9tjz2?VwdD|$a z71Off9dFlEdu>f_kq4!Mc9s9Fpq=7Cn%a=WUqZwnmFeclA13?qFvd7Fv84YY52o8Q z4*!Sj@GZpb&E5{b!`tDvk78CaD;{eu7n$08Vrny1*z>_b+4NJwr7Dk`o#DZ)VBhS2 zE7;%ee{0saIPj4+z^DtQ~b#I3$dywi7y+ef=ZHPzQ&89DAhH#F|e2MJ%a=eAbelf(NF`4w;78|Lj$PYB%aBDnAH;C{CU_no8Q zt_JR=WZ^K&-s?)axq9*Z@*Iy|MR&jdt?0hV|5kLr)uB7Jqlz6TZ`HYaK601lzM;{r zZ-(NjJeg(UFacZ{fw=uW>;Ey7zlSKl%cJ~#9_8;HMR_%p=Z9D&c}5GGl+5^A8Z{@Ap9eXAkrbjsm?J&`U%3DlJv5`L{ff1?XdfJtGDBN`GI0 z{!It;%Dqqzbo0>10O)4Vhd&E8%xa-*g}RdhbkJo{ycWAeLwM=?6XqW#%s=E|{t*xJ zyGLQJFwdB!`v1Z;f$~|E(S1lhy&+D>g}6d+vhr!qdBmZeH z=oF8A9UOwyOHJ+5{=W8&Pr1HPv1Jy{UdAUe7SE z*}~ZuJp7TsA3tqTUS8@w^3BrVskcg}X2eHcMzUS{1p@r@4&d>2=@&-!lu|3gOrI-wNSZImo7VQt>{P%0s(it4HRiw`M%(rhYhWGnRQssSU>F&SsAZIRYYf zY~*A3uZH$d#SaZ^m|LK;f&BlE^S7@O#$WNn{MY<2f8VGTR4bVE3`F9{W^BmV9L*2& z;nsb@KgpS%+7;A*R&QrE~C9?azOMJ?87a$9&88m~W2um}-u(e<5L3 zj|qH-bhl`A|G})`#!^U3%u+I zn>)dqYOvg)hgfQ`;_>u#i|?>oeA{=6@A+==-O+9lbc^t8xIf5M`FhX1-}9_oKW|k` zSH2LS-J@Q6#a91Yd&L3%x2Et#*DF%Hp;#;NYvep?EB^;2tK`G4kv}l(U}68~kPH?W zK7`{}$)C)63Hm|h`#y*093xygk!16>kUo+r=J(kr{-5s?KlFX#2cvx=aIT_0F~sg@ zK6sWQJy6)LYSz@WO;fDwEX#do(9ZG#|64mt@K2T6S!TP=lG;%%#0!gdbYSG~$s6XW zI~*OrYD(x?f#d#BV*k2TwLC2Fuj~!~;(No7d~f)-(cTdBhH%1=FC_;8G90JywV@UL zLHkN(e{hR9X_xABkALkCyZvwN4`21awLg5x`a`}cwZn=R0s7HHj--iSHS(8@4)?e< zTqrqHfY+ew1E}&Rm|WA**K=Xo;r^ncCjDc?3z1J~FZIXlAou$Y@__FkKN;;HfeRIN zkn~HVMJKL^O_3&~<_+R_hr+zPJ8oaBEiuD{`b zE3UszT&H$d3!Tj#*L=U;$X{3cwV`pHoP!U*EgP)Cp|U44T^@4RwI(?KC2{`m9_PRI zIRDis&a2sc|F4J{IByQl$X8f)#dFpxI$End61dZ2Uv2&t|69|#$N$#8@d@^g)HW_A z1AfcS=EhItxMh3BHf~pF=;dfV&Kt;NK(_Cm*hcPeh{XSJNDR&ajBez*(c2D*V^w_h z^6oB~I*ys^+g`D8Dce4^U5o#W4eg>$1;qg#*|MVvDcitracGM(R8~U45%Z1VOuj-%C=iU@UcubxDt>*3H{9_jIgZ2H14>^shU6&C1%F2sjIhp z!_viV^nLvH_>aL|LMY4M}(g&!p zEv*^at9~bFw(yH`|CJjDzEHo%je%tTAd|3LEgV=_~>pHr80pS83L`IXN$22H@U z<=|pS;j_BNmuF;os}Y; z6}g1)4Aa>k6P^93<~qx8cI>|=5}g%eojpTw_CJZv{#gpvrYmRi5yjAuY zhO@sUI{RzQb=F*|GkYE{(ODtZ*)tSp|C{LSv6}0wn4vRu3KN~>Bb_A=Up>Qc_IRSR z!J6x=l%X^AIue~V#X93Fg`QbDg9qSTjWJ_tuCta5ovCMLI_uiCcTen~txS$EZ!Xvvy#A)fF4!R%deI|OfnFjnY-RE{mruD~@QQz@7c7p|STBcW z=tUO-1HD9^*2-iJ? zIU++ZfuFo`sm&$a;!?iJPy3%@u;4WcPARi%u9W%=rG$=fM|oq^ht{<|ZCJr!K&O^N zYOa=JGSm|Iy1h_K)P;ImpEk4{nyBTlnycm547CKVZZE(Rqb1pWc*-ry;fY%2)Lbpc zWvC_abVV%@TGo}GwoZgqcGrpK)?6*eXQ(A`bfK2^aFV?)SeSTnE_Y`a8s6;DA*IX+nWN0ODa-o%I?`Pf9=d#o%S~;fXT4~78 zO5ox`E78Kjy5^@1E5{~UIj-hfX{^*rTj1bAE77vTx~Feh;rK)=^J=b@6En0DxVO+s zw5YJ|>05+4A<;@h&9yQ=Lo1j? z%Cj=G68N?Qy`6n(NNhD>UHj8!R&e6hK_y>vrL<-!C3I~&SC|@{Qd*xjr4$mSG}l}y z?HNi5JllcZGef2HK7DKbc-6i`N~z{bS(Kraz_A_Z?JbA>r}ybIDtOC*(@Ja2wQ@?O zR_t|8wsH%j5@}^!@^4H}`P8s2(Mo&Gwesu?t%Qzk*V_jVzYp#`3Gqe&owgc;zt%?Tb-hBRP+Y>r9(aUKy*UM=c zdI?-xQOn8|AzboJPumjZl0+}%n(JjrhF${a7JBLH>W=mDwBe;A(MxB|^-|8zOW@wF zIlbE+O)yWcqs1$wh|zM`lh`9ZOFgD5sr1sCS6W^>lzObq{yNl#-&N)91M!MAtcO2; zxSuP&EUEbNnpa%@ejr`(z(v)HM~l)O?S72i&-KPD5S+i&UGsX&pI4^q9eANy?`YY% zBl&B=Ty8(t8-D=j>b;`o^_Dj_#`P{V1q-NJ?`UDUqrGN0$Dd}ndatT^z2&+8biD&l zQtKTp9d{&8&h7X1UY*ptr{?vxx5$Ri}C`?mWT=WCLBudR8#E1y#? zGzH$E);n7M?FeR6`?=nDr-j3LU(M@X`Bxx?roh|NdPfVq9i^J}?{!JN*Vnw>mG22H zGzH$A);l_%&=G7o@8|a3kktFkn%8?uhFuH1HLZ8FNV_te_Uz}1pOsYn?3!16YDUF_ z1;@_bo-^a)OC3eO=D45h{hXxU8*5(gX&Lnn95$_Y)ZiV(ntABYP3pa==JlSQQSZQE z>w<$G`D-g{XV1?`s@-4nYR{;wc0Taeq}q|YwlbW(?`N2wo78)A&FeigquznPCiRZo zwUxDV*YNTMH+-L0^J>q^sCMA4Nwp(yZDsAeHN3slReM{_t9?L5wF7TWsvS9ND{D6y z!>f#4wJ)f7wGYgwcHpc@wIg3`W$>Kne(u}PORBxS=G8tZquPP5Ce@BywUxmM+x=W^ zyiCir_C+IY+bGhzMqG$Kvzlq!>tQUfHLpfm`W31AvIuq8h zx!kOdT&{GbmqOYSu{5J2k(yy?S{Atd4y1dq<2m}YdAVHv4aOtgeV!zfA$MIM2U_J` z70U^)ctgx9{d+FA@K)oIp7UJrE;SzMSqr2_F0M<*bm4g=cT5tu|A@+c!torf1qcfRS_`8*X>`r{ zbl>Pm^ps~I>(;eN)?h9A53nvMCoDF4(84U>ja^9#v(YDc989~3z=A;asYY?Wh==)O6IK8Gf=5mU4uu0Fk4S8%dInt`D8;!?wtlq}cG9W)~ zIF~Qus7_s6mR04n%%bO_B+_kqo(K}JLQo~V-|HDH&F=xPXDam?-)$C{RKuTrf1{qq zbR`W$)*Rm&2U#^NSLFUq4;Ru)4~JTInjC4Z&YTP$iYpi6s>&XSd5trXo@)-$Q@4PJ zCXtJ@s?jw$(<}ZLDmvffNEaT-PUI2tAQ5nSZ7#+k4F~Ll+vdcFH8EzA+9q9jl>4O zv@>bSXXkQ9qDz$iuDc`A1X-JXZ#XfR+j~4Be#1lmBxB9I$3wp@mpcnOo7?P@Cu@b*YP;2_ zVV6&ftZRK*oi4}xs-zvetcA)~dRBu}j8z>Re0(Wrm{qy=$KJ13W$z1Dc7&qw-osD)gV zYk4c=w5iaU9NqqtT<)OzO^&p5h&tD55pT1}F}*$*m)TIBT%>n@&htpCF1``VtwtxG zKE-&Xx4?W(Jlc4qCGJeu$yv8Ee9OY1o%M_nq<>6AJWYd~Eo4?0qw>dLG^Ns?J< z)?gaQE3J$C=Jk;^K*MUqzUTWU$|ZT$t@nMC)?mS^#6Zv*+~fN>t-+l>Em&qLSKUtE zsc8*P^JbTG@ZFrW z!s~mn+?f--9BF|=-TF9>@}+)^CSCrJAEQZ^V5(-n$l{WweuT^N?cU(aOnT1|zAU5_ z*3KL-y*X&a*{Z)>j`YkWJ}zm2Yu!#O3w6~C|6}%ECw-}{vDNE3&`W&2w%Glbwd{yWvzqG)s#5hvs`LQT=}S9>vlf9xzMGg zC*N|ZexXa{sZPyosPnwan~i?=jG?2)a6LL?8wGA^rOC5Bc6t8xhzW z3@f6Kxu5bTh&H0#=SUmzRd1DOBhK?uWG(el+C;3EnT>}~3c0jtzG{X10ltj~m@GBb z%QsDg#F_uf!NH$wQL%(x{Q#hGk?~0P%mS?3NJe_|ZGioDlOwHg_-xGEhS8NH9%+?x z-H36uTe`T+cS{jw?7fyAX&E)gL%nj5mU=%9(;*kj*Y#$U&yC!q8?Nv?(o?1TqRHeU ztuS=vDlGF{*Av>r(mTeWYjqos^o8F-*K#@~&Gr*X<{{toHb{%k z>R)E*kydly>Pz0GKZhTGfXR_oImLnNzRbIyvgxI)vpxy=nJ# z`jhlTZ`LJDj(XGX>-5L+>rkfk7$_7==s3CDYU|MBK%NL7pATDdqn{iJ3&UUCmwl&X zcU$Uv;3Ui0A|uAT5CcQLT%@&@Uyga3fwtLa8jtjbZ+k?O)*3mjG94?G#pQjivC7F& zI3U+}P>zvIRH@YqQ1z0{9*q?v9mCk4Jl5?B4Wac@I3F5t#VuvVp8Wl7szW6TMQcxW7zTM)xkj0JaHroc(j-`Rz z!3L|Se218C9Ptjdd>?KN;vR1KM&+Ah`If&C$kiDy%6G2u8V?NQ;Lu5Z8{QP~jx@bQ zbvw%H5yd^)>Jinq-qMS7dW>7N3ET2mt8di44VFj4F+o{qjjjxM^Idu&uGme&_5iM> zcSm`gEak)K_E3;sljB_!@X-I%GW;pv(Gl4d@L*&F2T_@wxvUH0mMy(V&%M?sPFaQb zlP(5kmrGwU9%<`8v79*Tlq0Qu#l?-%gM%%XrU%;kneiy6X*fC3nx5lPPSPlzVsS}p zKXW|FNg74xJ&>04$fKO5;p9kLzpX4E^VRf_pQe|}R~7>)N80*#oZepa=f-u$BW-;? zEr&k;O3E2+b|99MGL_dGkF=DJJl0oiDBF#+OBQKGg;`80>Xl=IxQ~9EO8@9T99W8PVZ;IsvBWxqmf*10b@0q{x`I46QXiViR zZNRo9t@bC?FQtyeDQPJmdCXVJRC0Zgv@Ud~`lYlfZssYe6svs{#u zK2ZlRL@v@&zB=bmP)^I_>PA}2m##0;n^~{PX?j9SdNW<0VS1`FS2xmTzb!81_RfO+ zejn2_+H87C4tP%F9IbK}#d7Dr2p-oWMopOU*OkaM)i&D|BtE&7hvGim7`X+29D zFkjNr9(8|;(>ot|vE4{ZzQnV6Uf9{X1AqQ;s>LNuonhMxo>FesnsRS{=gOYW75Lkd z)#a6Az#EfSPqZKrd(EXA5Aq~55@rT7cY0TJx{c3szwcM(I5U{*=hJ03(tY2r1x}N+ znI67>mCMc8VLUN#bLYB*@hunc@4~>$g>ceamig%=X-xx0ST6E5?ZhJKGWYgL=-3V7If;*_ACsyUn#v?rkYgYGPYCO_Meq4%WJm#mKk+X12TlM1dU>vKG#D%VOuD#yt zY7(p{cALVJ8(^uk5}e$iu72%j*wob+j{~PGOAqN{*1%&Lq}3a`!RkR?*H-B2PUDf* z`usYUD*~i5|Jit?8?Jz^ob@KH^%gsUi}_iFjK{Q9S1u36QC(@=fkL4jy*ZcLV9El5 za-xP$qOpU+7EUuQivZANJ|k~DCcM?j`8HF7VL*=?q^!=()2I1 zCBHArAwRz#ItA88K(yEw06*0#2m7I91^b~VSTkpBq;B*(ASYV#br1ODPZk#b!LHjI zRnAAg=(k(Z^>nBS7Cc)ltr;Kk-3!KF(t7M>Z;em0c~--3d?C~-vi2Avu|@iopPEKx z5$ds@N4*m|)MY%}tz!Y`*TH}!x*JmcC zJ#tZQ^W(7YD~v~a0}LB2G-o8!1$KlAC477%kAHsWoxxGc*K7=zNG#v{Gs zQ$XT(9naA_0PtoRI&hKRf%cl?rZ%LdzID!+PzSP5`4^N&F4EElgWbks+#PweO9OdE z>w@7I$+P@q?n4`{#BQR-kPaA$?a%_L=Z^mQ0T89gGXjkRA_GKH2A!1u94{fMC*Ot_|y01?6 z)UWkAmIXM6F4aABI;D=R-%-wVBAlx@id&>(ZD%~jvBvXqQZ8#f z&#OZ{g(u%~QE!Szr$5$HvFGZmbwU{=?u?);Gf+?E;X9Xeqa7MQmpj|w2e&cf1WH#m6DzZj2nM=$(A)Lbsovh_UC znGw>vVd5sbCL*nHP<8vbvV}g;L5;LR1WJ;Nad*HuoCDWSF4B_T+z%R$aeKx=?j^<} zt)_CP@fddty4LK|j7M6b)NDNFt59-7Ld5%c9QVZ6=W>TQy^uZ*G8`63&)EmFdzHl{ zEoQNNPn_N+3_ILyAieu-*pqbmlGZNKYH`Wib13B27>~5bJ?^?fB6mO_=V*~54%lAO zWoEi|W7}x=b#26U5IMF7b#B`PdHHrCocl9klzp_D~-5p**J- z>QaUn(<%Jv7ER%G1>X z&3mKeEh)-6z!^}~I6vFvYQa~%7h85q0}uM*V6>CVBIElu7{;?5&(Ryc5bO^+T3TZ6 zS7W*7BKgCi1i46y!^7QP($W$Q51Jg)krrioye}wZrfwDK`Yi4P1AUjOF-%-L}G5f=KvY!1WuB=jfgAIvajsJkqk(QNPM~q&NI` zpe#o-FOg(i@viH)SzOYq{{&C=dgGCnxE+p1TFPuZQA|N1oMW1q1ybq^C^Rhenwe?% zX?)Z>EC(5@Wr}A}f3Ne-4_UW+?_`ce>^R1c4Rwz7CePxw)}T-RC{uRhMIMi29k#Ns z*QyQW8AeONip((>H87nl_4sMkah7HHSOwcUIFUxY2c=kO`Iv@KqWRF&MB|Bi8xM1( z#J5~JyY6BB#?$6pVRAgM#B^4D2nU+$0MzMaM0vJUg?oI?uJk2a-Hup9%-pZ$L%S(ZwGRY zR=L-i9P8GDRxBQAJkpz=i!y)9c%*l9L+)hbkruPr_-G}s1ioCMT#K_)OixaeupXo( zy^c3o+=vG}%EdBY^w(VOn5&IP`jXY)?KU3iUB5z?e~a-*Uy2D-a-zl2l5d04J?kXq zpLG+SlwWwP2X(2Y!ReIkpgh+eS|^lW;&!-tC=c~io~y6$qzuAiStLEdqNGPm3QhzQ zVylS_iCaRDxbiI*@uW6g>n5hFS#I_F5mdUcn6CDu_@+ZYN? zz#4^Iqtnj~WU z1mpRRAQyCO%?00b@%}Ct9?r~2??nCS+L7Ko0Pug+;*vfSKly|RX|0jwAvMu4VT)Bo z)FtJHVmmf@#nxK`6|eKw9(YhYyWZDMT0{oW;0T{e6VLZ}3KwFEmzNA+_;Fm2(OXV8Qv$*6fg#s5|U_8>NqY2rYNVA+G$+&Woo{#&G z7StB6v-C&{g2`hUOdTR8idF=lXNnd-OjIaqs=;DCRk+C`xXV58@J2r|bN0w0W0@5* z39ihO?t3XpeYus8^lE74gw4hyttH)LJjR_1EuVa<@kk$x7FyD8JkomB{*A_CI$C3w z9`Eb(8YV{UlRWV*>k zJd{}sT3vWJhII@N!W`!0CIxvs%kqd0sbDH9OZL%0C+_ea<2xm0w=%Q&!NMRps7Yrh zVYZm9sNC&=9MmRFP!|^E1W~Npf0p~e;>>zwCA7qu@nhrZo+jjE&vb@sN790o>EO#n zIoZSJJ}YTSFWR@2^nUNUjq^+%EIZY!O=aDvO zYyXrS%Fg;qorKnUxccVq!>07lef!xa1lsz&NXOli6sJE2t1Lf|4GMP;ycTp5Spc_t zB85@s#aP|Jgn;*irz<~S^7n*i9oF9yp4gzdFsh0Je9J|A%HkkTPLtmJI94A%V{)Wr zDmDEy<#;SLaw@KJdaTUt2*@DRx zXF8svg?GlUJx}P}@VVA5F&=5Ai+p!oR<_Nx3w$wQ>18te*tOnuK_PU7{P%wPHPPjx zl8CVkG0t^7M=!&s)Bk+ec%%=-?}k4bkF-3{TK^K`kru2rpij$1+KM2Y-ff$=>R|Rf zEB4{w9Sl2(rNMB|ekRHVThaKCFZKcOe*Ob03`S3~-tVPohc^au%Y!VjQm{!*)?+@V zltSFu;F0|~7O`WBAH&I7=%>bYPU>c#7W_~xelY3f)Hqm#nP)jR_IZDRtRN!PDfMo+ zIjGS>SJvPW^@25Y-Hbr2)%>*L#{=H8%?T;p8SoZMabdky1w6r$tm9r4@XD5L_$)Sz zfM~7p$9@rDg|su++N8PM1yF49TxFR(mSG%iE5o^5vVqiaGb?F4!A%|dgy2TLNcGYlDiH>zHD4^3Av%3mp&N2@m~I z(qq5WGGAmowukVfy+n@fruGLmM9s3ZCCWow<>6Z{Egx*0me1Kb;fb9R9_^LJ{jrOS zZ@%e3;k4aGae?L4cDCjJ9U1L)ItA1Pk0>8zY1Q@k1^Z@Wg-0AqZc_A+U;S;diq5#s zvla;pKJQx3nj=MIS;S2RwEiMIB!~lO4*`zqmOEIA3TIr$lub@u>a|Q-cs`x^uNfTt z&QT^udd;hGA7)xE(p%1gOX}cDdedg?-+#~KNQ-*qnNqpPlWmm4AS)MXmFubG+384M zzNu>l2fyXI1L=c*I5_yT2Q4mX>O#1z#};hdeapdv^d8}jwYa3IAK_9?y57(BnjC5A zqK~yZo}y+l>1;+MY-civ42E2SlXgx-OK4stw4U%mc+C_(wi$Y%b+}0 z7N)JsahgY`Jc^HPMgtI5PZ9v#?vX!Ba>Jy2w)fRxEOm@&@X#R4{_3GYn9cT+o(2cA z?OuwktGpCpcB@})KGIa8FoVZ6>)rrnj-J?K$Ld6q^yC5x?##H+gM)t^7##fZe3A0> z!EXU?i|{b7badBNoUgsxc%;Q_-G7boNQ+r}*fk@|C2%|Te3K)+=}y1RKzcW3tcyNx za-{d5OVQgSEzRBmP01C;C8Q*-&r9TcLS}mg?<(WXy4Q4m z_)ie`WyT|Y@DEWpm{qw*E8K219(80uBG2k%NbO?Pku%UVNU3_OSb|-00qNFhj~J z_vEr9@$K%x;N|=FZrQng&z@~tu?SvhZWXazR*rEXPqIiegGF#xju{UH^J&bWq>j^n zAMm8_;*vaPZp1fc(cD;)GR=4hJk&?N45_S-IdLibHHsrW6bXtZ(oRH#E6iTHii= zzZ`XQQ$EsK&KsPZyI=Z&A6rRl*)NUd4u?O&cUY2^DL9QI(^eh0Ja}K0lqkovRWF(c z^wJ`EUF!9MUs8`!@a95cq0z$yMJnNPKhl+KqVe!Ne;CFY6iW|v!0KlaMnx{tQg%)& z$!mEf?(Z}?(pq+h1Iir>z4O(Nqz~NzL-KlyOM2WR82qj_9_bmFH{Abe~}4g_f}!k1*s+)QEwi)U2D^WUjW}{oE=v;M?w%_E z%uz0PneRf(e66>e%sek9>nuXTaVD43eo$mKl<~yMv+HB#fs8T8jeRW`z|l z=?(Y!!#U7XGT0j*=cCKqXWMNe{2$k8&4@W2!EmGoBZvbd!6dtAT+y#Yh> z+9k##t@S{CHz<>?}!qyL-~w@>Y`Q%`cbxW2Ck#mpR5NKj2v`>zST4 zO$xyDu&J=YTTUrr>24-$a>6S=z?40&<4ohpw_HqT_s?MrHXD!h9`wj$cIs&6C6bi8 z=us@FpJH)I%gV;7D3e^IRh2H^kSFDIZK)mSg_Z3XbR0D6r6*K$i3yT~y8{TBgz>c1 z&?O{$LX)(9J7|)=6sCjFB(3QoT@({ux4K0y@}BkyrtmqDs-diiymXlJKO?1+7^n!Cmdn=WwL4jyex^q*?D^gOsdbgLIK}0IZnq^%HlpuJ;r7#U}O8 z9iDZnu^xNSyE8z9?(7D8nq&p9YhGef;l?dlLAjtBE!Qvnz)senU!3T2>sG<*Ezud| zQn;W8cfS=-LXDK?XnB`9dn0Mp`x{Lz;=MnP+kv*7`*q`y-ueN&lkzLZBfX;=Ys=0G zkk)llXHX;F^%gheJp^MbSCZZWteqZWyd92~^d5WAcq~iZf8t@0bBss&U|6IE=^eO8 zPX)f~-(Wn_;uANx^djD$O^)du@;z8sj97A!mhFCS=aH85%1);d&*?O*?+<=q=|#Lj z4mf|1l(zIY(wp*E??y#Kjpc6*$xJLi>o}egYsN^2v6EUcx(^qTzJ$y z^=9C=^ppp^DbMMT`Vb!VqCAvKd13jW4=sz+i#mC+sssB62RpBFg}2Dp zVFmkRcro9zqrDi+He@5K@r!=0I?)Pm!nxebuwwRo07@>>>$|Yw;p9jk|1-bgL0aAr zP~UHHNz0yE;}?xb+KM2&&YfEa+Ey)HzI3(xy3!XPBbAutx>tFBk!AmyHxH8}7A0Yz zF%+yp?!6p%c8xmOLf^+P`! zMfX?#?k;b>k1$sFkor+@moYFlZu3jT$6Ai1U}oFsfD}lf=Zhj5e&KU0I#zH3_St5> zOFV}JEqj7NI>kHAA0 zl8bZ$IyLJ?TJ^limfGX|d}imq*A8_j?2r*6l4{X$Q$qr$kQoY#ZURjU;VJ z$9g{FTAi%x8;?3tljL+I=}CK8=Vx5QlkkWuwzYMClVhDEU)D|Y046jKhYf8*;La?7 zFG~a3Re7#`sb3ktsApnUd|vi9;$3;a@nx32B4xHdBhUMnIyWkk)E`$9SZ*%F1)Y7UtgVd69W(WeINZ3oR_c$14|Fv~37ogFLUp&8_2T-ohd2wAyE%kz0BTw^@a zl3wH2GI$qf@Xj_K>mkn`7N9e^NN+g{`EE8IY1M_(3-jImLKw-5OpY{lD_qt?1{*$m zLR#cHUT1L=9v1yheZ+Wr-Ve0MvE7)S3^+& z9{83^<wFQ zPu`Wj@QubJtwYjdG4F_P`g}>NoUx2M5vt7P(|~ zrT9gB!w|9QNVfoUJc&a({~Le8hO}0x&(b5U)l(i`to}2tMhNTY1j|I-}2%Z3+W*J+0x!eI`QISs=k97M{IJR_>@kr-^OFn5wS_;pn zV?!Q$FyqS03Ayz~diT$PkDZnWX?0I;G9GEGr14Z)XFGi0TP~JC6li6U-k+CS*O~&S zfMo9v_S9VO508vdr#Je3O@k0Te?c|(`>sybWxg?}`5*bosI;Oukinz4tZBppl;Xa?c~JZtEj1J(tcVjJ(fUV?5IRh&%HZ@Oh>p9DjfQ z)p*h1S;E61VMnj|DPA-PA4V?HJ;&e_(x;3^S|*e;O2(ty=C9znhE2vJEq+nmzs7Ml z@5A9~=U33Nkq@~O=K4UzlH*qmWiZ>dM^pqw3nF!L01` zM}0_7r(Rf3gO|l+Jq=$zJ*ktV$GWi$1}BjVPQJ;{SNeV|&_4sJ`mO@vLx+=#wCXJ6A&&Ai?m$cb=B*dnVU$-{ zWyT`16!Q#}6k(IM}6UF@oMEMuZ-LglwvpB}%eJvX9$#!b9e7)MMQD)oc zW7cq{U%?O-8YO(g(OhFS1|u)ZCYMFV_m?nTy2J4tEzQ|+eazdj*T0~F^p3l+_T-v{ zv`o$TUP;oDUZWcnn6{PF<>BrN&*YL53+*Cty;XY>NZ5BV&e1xvb83xv{jr=Jqpx>zq_xNX-sH%WgA7Oi(Rie_ z>D-9NJj5^JlWnBskOQAYBQ0_HH+W1(o7kntGFVetzFH@gUuUbX9;~PG0vJi!64&yG z&zKanzuaKJnS!*@2D$|htoWg`YxLmnh2~@Gf;Ecp+{r>KOlh${Wa7r<$N%72d6Swu z#j{WXwVPLY7U9+GS+Fi5)o_<*9b>An;-ZWXg?hB0q9*dLay)#?r7%T>)Y(zhTHJ=aOisS#Vp-*Fom>qk zy$ucmU0l+Ve>$$b{gdz_y>}{}bV9u~4@WD!$a6Z<#h7219O+G$`W+S0`m_{aEEj3j zg{yDGb9!Oj2WfeDl}iSs!-!0K&Q4Yph?52f4u6!Mpr8 zgejUj%E1aUq!c>A2@uZhf~W1BqSdYfP^at$IF?C%p4N&ySjlVrWz3T~PyNNlBYp7K zupRS3q=;U &X0>R<8%~(&XuO@zUg5E&;~F=;S(YbDf=WK$NVgw^o&QUWM|#tZ*k1dT@ksC9fcf!F#v{E4 zf8CnQnH|mg;4g8Pb}e0veTz0sdvdwgnsUd21bB`*2&OG~IsLJwlu|xWopv`;MLZ8W{=b?jh%&?j=LWQrCEZIWwLw}9@ zeo4X7gT{~dEk;@oT>r`PA+P0qklk!N(qgyx0zAqc{};d1MtTl(bw9=-xk$?r>O=5k z%P^tC8^-N1qzjxC4bITWJ4B4+Wt2Bowst`emIx7EeEwcgwQQZt}($VX`jH zEy9yTRnKqqiGnSHEz^TUC&6ev3hlK8iH?^9D2wmqhyx%h&(Tfr81mbUM_LSH5sf7m zX-iu;1No+QbqU^V1(KocXt)KK;Dr5CSV+6{yD zRfW9O6oQsW6cRigf>mUh^fd-E66z@EHubJShrc|v~rDK@F^RsA(#Ul zVrAEsc|UZ5bxxW?(&8X-r;M~XL&v|!;*u8K^6fp0D^3Y_21%=aoPl9_eIJ9tT4m{x zmZ`3+rpXoZ8qv0LF^_Gp@a;!h+xePUPEKqsyv2B=<;2#)R~nD>7R-70m=tME&lwmg zmz2R;%Hs0A!r95Oo(gAIU)D+DvTiJ^#&u;Dp6F6|rqdWpI-1;MSVB@c0S>xF}~kyHW3%>)sYoUo{x4|3LG=Cg1tH-E_lEOexF=cHhkZP>Htp4bM%H! z`{pC9D!w?DQ=Wqe(-G*+!?-9HX?bZhA44UrD&A>wV2?&J%O9k5y5aI=I;uxa4-XpHHpR`R1@TO!%F;OlR}b+;f8qPJ(cE&GB);Dr zbQMQSmADE-TAG9J`6X>hOKJm!d~=%+xA@|SVZfZO@xY#C^7dQ1Xf4XYP(03VnJ^-K z*q2Dbhteqc@GTeb^PY@N2=_WkHx8x9xp{)^MTLaxB!xZT&VN3b^7HN48NBLHZOIqH;A^FQinq?9m^HcR` zzOnh%8S^_#C1Sqo5e3B$pAN<#BnU4Dk1Nc96gqpyA%2JGXv0zHK|5CTmbT+8W@$`U z(%|zP0)vCN3yoEJl|MRlsMH2*fJ|PNrhOjYa#?}#y$l7fS5`vHP*3|vT69tx6U)i_ zi5J4{kc+hD^{SXBr&Kx9BF!?1WXPj`&vMEC5b{Y#(o&WV=lU?;P4@sdjz?NM)V8=R z@()TpP(?cbBmcAkX|WS!rz_IdqLv=ZU`=W~$xq5JdQR%$^d@rDAIqg3-IY)E0ljG( zss08^YL9RAT_2#5sbu*AKk1a-C?iO4aATqs#v~ErK*UhQdRiuxr+nJvNXwh(_y#r7 z^5!_cCxWzgjy|u1M$lFS;dSYMzo~z7n-zR2xG$9rNUQXUwX0;91;ZYSa#&rw) z^x*{SNud;3!N1|0WQCY{qn~&}Q&O(E!Haa;ZFQg_IGEmPQelo=?op%5eIbsKy0H?n zONxo*&xL2ZO?6m$uyPwubR=&vwfsF#=?=`Eq6_9G~|5SK^VIV}*wuSVzmd zt7oGUa*-C`*m^nRVo~6^c>HIPNO^kh!$|K^;h}7f?)@gxyUKW^Wl&`Kn6C_|vztwh zv~&u~7ytF+?kjJn$uaI~I3D~fI@0oR?Zj4-BP}|c31>|%)=l2R&jFk?bt`hr(?o#IV^tEk3H-$ z!9#k-!mR**%Un34K<`MSq+|ePq;{nyF7cZ@kncHe$;rB zlNU2hcXFg1dC0>G8g5P~`^lg*F{R-|3AijI4}>GcNMlqH2P7 zWQ}v#s3c;%6)_HSJV$GGH#r_aH50UEtvqQcb>;5xSxY`haAsi7nRW2qr13uMnXuck zX_34a#?kWEY@N%aLx%85BpP0OwNh z(hpce9m;}-j?mO{>GWYS;Df4j20&UzJlAQ-+w^OU>}V0WNS|{eR)<|Pla>X5`hPPy z(y{_QB02a<&5^iYm7%) z{*aRA$w`abcf6}SX{O6jUfb#2R`BUa5`Sj71($;G%*pNSill_M>A%yfBBe{%AR`XenTwYYakTHES8 zOE2QRDCW(CY2@UEG}~Duna6Qwd;O7?bonX((lh?Y`wXNdJ;R1Oy@YlZf0FIX_Of1M zp?=l3aC%lA^s79lXX;YoQm53B^&QJsdC-yaR9EKnx619i%o>Ps zdWl(s2U{a+fCke_1b@iPejdCM047nS=6>Fv6=UBF&had9o$5+|0P-*?1T(h2`4HMb zE-m*8S8jZhS4LmZzKL)4O^G9T`pK(RETPx@6m9YW;-^zrC398yUi|0X}Al0N)h=p%2i^hi@@ z!lm4CFTqFyzd$b1BF{f9A}w)6w{o%W*7U|>ofNCCZmg3vzR1CCYE`%CJ$`@`z?_f7 z1GfoIogRX@!%zPNgSbo*-`$8&bUa7zL^V$Tvhhgo+~n7gNy|&Gr$1-bVe>O zl3tGZ$2vciwETH#^LC3%`bvzM+%zFAt7ZH%B+{~4CS{U~w5*&NZ=k(RHT*uS^b`m! zvleJ*_CBRl`aVR_O0UzT@Nv3v^Jj=E5-t=kvh&^^anCUB@l6pIeOhD>zc%8oH11)C zMqJoek)5_P;$qGsTzf%qQil0fM6Kp6CQ-P@^YSMfFMo#T&3n1==DpqXjz7eB$Lj?UTZwklAg4ITv2+^gIt;(XidZEp0uQKJp3)WNK1OsesVEA`3D-V zO_08F4g4GQbGb-Mx}4|#e}#Psl$}+X?Y#slWFkNUNvhB!2&o7}Qd1^|RHZTy0trcE zPzWK60vX^z6rmkx1fI>pXwzuhIG{)?PKZ22h&&Ml1Vlt2pvYumw}>`~jnG0;Z|`rP zUEg2au-;iKxx4n6zB7Gi{Le9FxMMGnJ7dPd`am{j%QBxGdKm zgns<{;*41?yjPdTnBk7-5ogSBhyFmEG2>vJqZ#10OI-K`ru$)Mi8H2O)?v&X)~!EZ zTM9R(W<+hc?1$C}sJ=2w(2ry6HT!?qMvKt38kGu++?QI_Oa`uz;%+H?}i?eaR_r{f$rowal-iaU>4&SCv2I>;Q%yt zQ*cAyG(=IWeJ_(g4wVX(spp~Ujt)tT#Co=Fe@Cb1A=rNw_L$GnL~pv)ehOFYZD$!y zq4iCT@&7t^pHY72{`&3i8Vj4*c2VMD0^oyjEs6*dlRNyi;;!Ixf1h`a89Q9ciSKTZ zRnsG@zMrCUB8-??D@X7=H@<&68HLDN?^mYqmxe1hJc3A}`nd=)?TP@AjGG%HuUxGC z0o24_;)~@|2h`D>6%}j!p-0<=xRCyOMDpPTF%6ub`u z*A1@N1s6f49qLti!RiN%QCF@tJ02sk*0-yKVS`F27mTLJzDkiVI#wJ7A?EMlFD6IK zmD8o&;*1?GS7{c_i?fPt?NJSHO<{LO0iw=S4?~ecdmV5XYLJ4KQ`kR=0oCn=L-p%= z)P4$A>{&HwXAy{g*cf@`;L#{e7w24_M~X@h5pmy$c%G@mUGO@LY&>f>zVH!bW9c=F zc|pxVsLM3Q%P~5cb*ngIu1L(eT%0jyvEq*G$*rN=l^SUG+68#aytCoqM${taX3N95 zs&fb_oZ&k=cV)1mLh6ZO`4#F&MXw-P>V171`?H+B9g5u9zT>}e;1-&M#&~WwI?FSH zsu?dqeH{0KIAcC3>`fG77GcZ7a+l%ZRN_w@p71K3R4klvoXmurG;_O)yFcOgGvZbi zym}lKpbBS9zfU0ZXe@&=(wyv-ZRFOrPvg(VtY2uYtToMBb3xq2@pxu*rEWK~-$5of zzmFj$4gt{Yf@6jNhcLn6%k;L0`bQZx%NUQ-Z9cLw>dI2UP9?~22_L=i(O$TM*G|Hq z<}Pu@tJ^SVdPtmchm|9`VZ^ao;`vSPqe2m9^JUL^hk-p9GPI})KVmxjw zn)Bs~!#MWZAR~>_6vbE4W_#wJddE4d)}GBT@@uvKo7JwD)eiM{R1SdH2&jPO<&le$ z*K!H#`H&YqBaJav%Ey#68;4x;iaS;@Utrur2us9vLzR@oZ zUBU-y{#GP{#&|UnHoRyd;}EB#xT840Ax?0-i(v*W?@V!uK4=+|Q+SIrJGT=Dl^`Jk zKR@C}h|Sgq1xM8AvT2MX>foYeqN)8PIxhibTx6j6HkUQg$D~3fyM&OV!xZY(;j>WCVQ|affl=2_2q4a8lLO?C!x?=TY z!C*xu$2_f#rjE>^;c^+bq2)!K?I+yO*Y|_##k~vbsvDoeQr&jAeNVz9By=jKzXfwS zj;ld5#*PaEj5&DnROz`p(?iKWF|a+LC@=dZzF>M|z(9AX!oBQEut8Ih3vmhn0iBx7 z#CYsyv&S?Z{c5hU8MmTy{~LH3;}vK0^}V)5obe?mgZsHSV_sspHMBSf#KM<;8FIcZ zcgB_-O|h*s#h)rC*uc<0xP{sLnXLPyAb<0HS@*{jYE`O!RM%L_@IMzw;8_0zo`Jy=EaEE~|P1SG93ULlcf>t>A39k5!^;Y4M%n5*uQ!M!69re=#M{{t+QK|x_WGRcLwhu5k0%S(hfLI=cNP+Snh1U63_l@ zDRs_x#$Nbr30X;F+}4LWcaJ#Z_&m3?17pWUmk#edbgNI7wLjytcLE2kOk=$2XBd%{ zVlj@9+b8ADvNRo?vKSBU$*$IT@Wt8H8aJVsdZH-Mtrr~2>Lp&sryN(jwvR21a94^n z^!vS8q#wcreq%$Cy8Jd|?KbtDtjea&&4JA@MXw;KJF`eb%yUb{z%PyM*FXi{I#-8;9I{?5cg7)i za6AYT9q9cMdk`ERh)h8@zwLz_@sNTd>FdoIAbgS9_Fz(#o`2g5uznJX{_iE`f+@ka z2OGJ*-jtA7u_Z@8ijEwl?usG61DV#qA}X0scCkxTrdKkh#{ zR4~7V9vX!T`+_+T*#!zV{1&XB$zYt;iC(%^doaauuRX3&objoR%Mc{G=W)=?7_Isw zqcMjIW04XX;|15^^xzRe)r?o8YWeOL;}9RJg~m9NGQMz33UDMPxT2n7*z$9whFNw# z&W){ZP*2E^=os$EMF5VLQ7g9In(d9P64a*WliF3$D@a&VJz>&96TQG44p^M+SC8uJ z``KyYjMw}M6)FbFSZptt6QK#4j%AH7?gG2Lx?zHr5laxyvED=W#Bq6#JWP!`n(aU`#& zp{Ncn)7JYMi|UT7jxN2YvQ3Xv^a`>he~Y-7D`I>U^Wid1itK?swY`^cjOYI=1_yKH z*O+hHjr)o?I&iL$?uv{}roH2i2 zT96!Zgoo-#V;sd&B}zhdlm*9m|z80 zFg3vJW5pR$104Ks;*8gh#>}rYDdW}SQ9b`6cgB&X`^6bYT7rwTMECG;rp3M5gW1bE zEqCWQrSt{StD!l*b8)3tD|o@Rd8WgdPu0F$w3Bhj<>tbs0UR<0huiDttzC8U>d*_n zl$e8%pkZ)?{-EWe6w_VSZJFihvSYZtG$#wC6yzC!JcF6RWhI9S<~^mui%vGCl-q6_ z=q_dm4~a95QU226uJ~bU?AP`Zi|+6NFn=D&v@s#f3n-p|zo(s=g$* zo5WMB2;>WhYC_=(=H)?c8^js&9ID^7t8#pVlg8n6{S=FDH;Oanfp>omW6T+Z-=VW# z#^E;#&GmdJ4;C5s+>!^2jHeAppZ5{PYaIRCU&T3WWvw{dM`vGkhcqd3(=XFb&Us+@ zmA!PwLqt)bA5ERYBKZ*#bz4^GJyj*PT#>bx6#+&r@%svVoD@_)o&!C(%eCT+m%V~f zF|vZj_#7;f_}y7!*77Y^$el53rMSuy8INU49E-UlRCM)C3DozP)jyP426c&5zNhj% zOwk_lj6nV!6YXmiw=us3n(!%c#w$LC{u2EXjd83mlvdpD?!$SkXhp&2d8yok8%yTHo<6*15< zLX6TvY#$;97hO|miA@=Kcj-JU+m?-&;64o5@BUi@fkiltLlucqs`m#&> zVp1^fxuE)SbUa8Wjd94ZNStxV6WmdUEo|q8fBRHFDThA4R(mpqgQDWMwbflI=oM}+ zwp6a;D#FPntWp2G3VrNf=+s^$i0%2|y3g_$+db7sn=0L}Q=Gk3?$wtbNl~L8-&pBF zB^_^j#XS;rmM8XYN0zg)xWcB`A#S|$gQxzWervVgDEdKwj=pls{{&UL&dQUmYqTVL z@3R9IZBg-QxbS)JFYQ8H#1G9l@)^lS)_CSv%+rsNJL9;A;lITh$2|=2Ph-q)y!_RH zF)KkQDmab9TX_O>>A#6HUU5Zka~hv>VPD@}E9B0Yi@f(E#Wcp3V!@Ybq%n57$yo+g zM9C8O6Vd9a%txKaWQu6$P$GRE}-ikkdgfSfIf)53V>v<%|CP<_dRk znebg#;SN!7n-^5LL&a^qsKU)w9IaJR#!IGyj>I4j6=oK)zx7mc#xd^r{6KdjTOlh{ z5RI|q7w7O|Jae-+W2I@JyO>~JC(bw~wuN(e>xZD){FB@nv-mbI7#JSywnCB77}MR> zi^Ms+kyA3g#!N?RNpJ0eTCM&i3=m5G_)z?o!3d|=F~s3mDt!7A7)s*8xNJ6yUn$FmkM6?ewbtS~mGF^(oiuFl)oYa@^9S+=tG zh$X#?mM>hexaWvEZQ7x4(C_Kk^wVl;JJ2zLp~`tA*Yb{)s($P{1C%*KhM`h>3}wb0 zxW~RDP60?6J~vDp6(cc!pM5+zVk*eTpi*dz9WI8k>ps-8k^__4GbtupD+ke)Tjt-P z2HaCQ;7~ecxx^_f{M~sHLrUDe9vl7-iZf>0@sT!Twj*(6Eh;2>RuVBU&P5*J{kwbj zW-cvMfKVSrsLB^%6di$eKAl?_7?H8eHm%F$DN~o{WPNu9s#uhhKYL7EwDzYRusG&4 z?JvQpox9H|T)`)t3+^~^#ylIs|yjbJ3-7gbg|ZxhNt<07~|v))bSN;vSCC zB8~ApDAA?eLDh^MZfP7dX#2Yq(~aZDxf}!`Leo~>NT|**Sq!gd<1lVPxCeefaT||* z1c#Z>*V7pD6@&?B05rxNT~=@ECzc3wRT@!9zFCqF0{y@6b^O;GI(oO5$^%YLPvz}D z49aQbU&?Uf7sN#sdje@>yTdOHi=6gcNcU+bV=kmOeO2y^xscxUDRIW#OEKozO`LHz zM*6-+%GmMKrQPvllCKRi9{2I&j3XcaQ*jtaJ_Z-nG;(oEmOnG+6UhC_S>+WN#BFY< zre&BIHt-}DC8`Jj0U_DGIMsLv>^x~PZu(+s3gade`NCf*JYycJI`YGXE11bz(v?Xh zrYx@Z#+I{GdsK^B?f02%gu*3;)|+w`*{wR)Q~8R#RC~FEj}K=0jN6d4{y5H<7r*+0 zN@KpwH*3A*HfCCMJReaP%;FLk#T9b@N6Jkhk)zeK&nKcCeWandidG356qj5mdIg{; z7fmc2q9>*pK7edI^plyr#txVB&h}~T4CD_fWgEsdPY#?0lltty^#(R#7`fEP;hqNb zLvUga`n^72tYGMK?KJ-XLdM&p&{`{(0z(yX-c-Hqa4>z@rH-b!*7BGNF{gyAsKOf%kjC) z;rYrVdFr9GQ+bAuZz?AlkMS`Nq=d#?NN7HuuF~C6zv%0GrA)+)PsTCm7tmYN7@z$H zHc&1VXH1p3?GbSfThfcOJ$q5PYg}E4Jo!`R2~&&l=C+UIcoSt5>ob-6&u5WBS3f&% zxGj0YoR4FF$VvXvL~o7;A}@uDNWk4&*#;TH3`L(^0Nsi4aG}3=H=GMhobtbUT(Z^q%qvlTN=szL4b-6@c zZB7>>x6t7GbE{xV?>7jHxyv)DC>moHYv*UwrNP2O$ zm-ysxcS<}R0>xXay_7l8s-mxc>x!le7qGr*s((wz<L(TgB%*4_Nhua7tC_BU%O+2@QvZdO#PgZ3eQ;5lS6N$Y3g5;;vK*Z zmC(ccvh0!CP)3zyupJd7lQ+Ci$s7Lj!Xc@|OVF9Ptr~}JJ45b_6*Relcc`?Ze${G! z&9ZQRRT+Hkfj)Q+>d8H+z4m1BVBonhsnUi|e-dTzWo;9<3uCX%r|=XCBZPM-<1Gsv zj5ux`(9g=t`ucBHH|EP?4__m9#@uz@ypuR%hfCJs@krs`sKGSGd~e8uB;z67xk+ej z+0}-l=Kgo));4GtC*q7F2R|pyI10OPj!#LVJKl*D zs`S;Y;qO!ppImvPj1*ez_BJ&0TJ3L& zn{B49k#zMIc2JbJt8$(6L8_2lm4`SBRlQcSC|i!VyEY=+@1vkFr=T&O49z~}cyY!Y zPn$DlRr2kIRjvyOrEz%7;I7xi8B2I^42OQ$ob1l=2MgZ%7?6cw-*T z+vj>R;0mV7_dDEnci}HEGT%?`j5+O|h7nDb$$7ggdt8jSM=zIO z<2~=iyDHehVoQ4_0g6T}O@D9HY@oXcb21J^R%0abP(sLFwm zGUSj;ERsW`^>h~@3T{QKnuTUUV?6hl;4n0zF{VcIp$=n3M_2xwKOTLl4@x;lp|&56 zL1*R3JGYg4^6YMrQ!e4-n~3Y{3^(y&w3UvF#2KFqZ8-r|fyOx6!ad@Qqg@2Y=?w<} z^&KVRAYgQgT-9kFk=3hB&AFv=D1xp~5t}Ou2+#pE@{HeA7~#HBxPpg#G$(_`GvQ?C zGBh$?aSQyuAiu_xzGczC@Ys8LrNQ=0UBA0xFHz|igZi#W@lHxHwI=@N=(nXZp>y&o zA2`t!gRa~t3Ox{dyE4ZcCIJ;5MzY7`9M71V*Qd>m=c9=Ch+ZEfqk_4j?Uy`_Bf-c_ z8iyANzg3*WTaAQI!mx+NIJ%m3;v7z7ObO57D3x+&KT0M!-F=1{QL8s83!8v1!I9Fv zpbo|l*oDHtkbzYz35H_~tEDA(#htO0?})p&0ggGs3%OS{O&&*VNNP0Yal}~5!M5zy zqPHk_ON-;8JA}vwaZsrgvN*aMvB5!;%W(F?7a^~&mOJB8Mq*1y?p;JI4}sso;*1CV9{t<|amFK#0$1vvG4DY1gYm{}dtFXPkyV+Y@NCbv zX?K>3U5wLo?Ls!&9Dv z)$v!SjC0w<(PLJwS1j_duHV276=&g*Y{1j!b%P6lbiU$;IF-DH?Leu6%~dQifi*VIT0<@RW4zD1gs~>wK21FGa5gQv4SBJ*&A_>YK;4R znY|}t9D%m~mPS5=K@=NguUv==k=}GPw+8LwOm|KAg5%r#M;lQ8C* zs1FtyGn<#ZOMZ<<%*ZS^4*4J_6-4Lss8pjf)iX7=Z>>!IJxp#~`{pd5wN{Cav-$JjiXB-6iQi&Zs}&J2KB(3AY>d7)&%CVDskBE2UgKBhbUa`7=pXH( z2tfIJb+YQY1>)k|8gQIjdn&nSfiK0mwMU;3XY6oGYeB)(>SI$(x0dB8<{ah16FcR4 zcabrw=5koiN5&kWc#QcG;HHVbOT(qi?aa_tsfshlMZp~JO z+~y|9_FGlhptj0I5i`I^7-zY9A~TbmUIFb241Q8ou1+8S}oI z)imu=L~@#YbF6QwGQHki5-AEqH5#2L2J|%SxH*|qz~XGr+b+DVXUqZqp*P5#ajd;w zH_$IXUg01^a3M zvu_X=x+K!_j!a88T%rf6o|rrpH=LugyhWFk)73YT{wI@z~oT=G}5< zJmJzDnj3R2>UB=z{r;Ld!r1X^UyQA@{!XQ4N8mwfdevtML9y7oK9*yhgH%{uFZNEA zVDKes+Mv|&Wk|wy)`fa<(7&Jzu9SP@)<0s>dY(Arp{N~Gt`ld>vX}-zXsTS-i{cy} z>uDF-FpaT<7sqhuCnmhbufry%IJkus88beM8G0%9x~dai<_s#<_9nb?YkNkXPeDd+ zw08zQ5Bdfp*U8spZv>S@6;$0%r(%SWOD)N@UK>XM-d)+6K0s$fq2fXp<#9W*m$4&}VZjs;AG^M5* zuecOKmKtr$s{y@&ZybVMToDpDgbZ%&^tdLnzHiDnMKV^Gu}GmtbRC_Gl5DRql&}j0 zb_VK|+ZRi->u7tCJKJ;V!&j3U+dZl&PldBp*C(YsP**X^uAERj4O2Ko`W7AMNgi$B zNiGz<0zg3bA|vM)uHYeup~<6*r!gK3|E?*XS2#W0aHCiwbvBF;%yOE489|6ny*;eJPY9jq!;X;QNaLV}3d6y&hxM3h&n% zvsQ>(i!7|w-<|SxN;6kaK!KuiYpuMzQ*>mEZJ@&VKw)c0mza976-|!DSiz84I|KjK z_se+qD@RZ&P2cgJnd-mfOB_}~(?5JxHhtsXA7mjL^IQ1|S2JGZS-~Mw8QU0#e8CMo zo75Jqd;gTyxm1}sj#VyAzNTT(Fmegm!;6(Yb7YK@p&J<^e`##b5#Bzf9UI$ybf=Mb z2S^&W&cX1D-mm(2DJTYAz30H$d2x1~UD`X?GB|S>GSVnK{O*E4CIr=wDT{9suzfpg zz#ejE9JyN3VRxgh$C5I17mYFZ%6!ee@z~GiaUf$Z@%t+^%b-LmJjWNMSmL!GZjs0@ z^kCHaDOsAXdmD3{Xg#2#T>+UAw{WX_T+^#fBNG`yJFcH|<(**Fb;&)cc$uz^~X3&pPh5D@M?_48ZCysl^4QF3R@S%g0b zG3H~1{tCjFTFzfV7&Bh0YGcb3IX)9{)u(0x4^#rTy^(doIbOLAsdPk4$u>x`9*5X` zd0FJ(eI>{7OJn=_Kgg9u1N!GmS!Dq+=KqW-+~x-AB&v9KN@4l&yiMFyjxgr z%jAtz@;2X-|L^W`FmI5)5&@r_d)Qh_#+m-FZ3O zD@`=2KB^oSp*CUEOJls67hu0zoN=t=ohQy%L6a-Fxg4uO@rOY!@ z$g{o?4FgcQg!MDo$e0&>h*e%n%*Fovz4K!PW4o7HJ3?x0S_bMTRX?WoZUbi2*HB>_yh;%UE1#&48#^9oixV0+0h>m z8?Q#I@tr`%Y_mS&VXUlVXgJ0hw|>@VW)0gzHLUZVY%ip!uPb+FmDvJoSRB5`bgc6v z1_`GHhn_7p$5_G8mHGr3_iqke(u64qO)y&av}OA(~lpZyZnL7+=$jAP&feMe)=I>a#8o;%_jsHoQ6 zDJJCMInCz5)wise*|2C`kwcjxsNBL2tjE31fDi%jrmk>JlaD3(aw zMUeieOdaQvEoj2>B57=Y+P|bU#&#dlbWxh#lm@xMII3TRTbipfuS;!^OGq;TK2T|B zBJ`_@H29^lJs*c3w?Uk7R8^=&8e@kM5>A6feQu+Km2>YD8u?Yd*M7$cP-(dy5}^=iZ({q>z{f;6H zerasaqmq-Bh%;s#-DjORV}}tE&VXHgexrnySr&z6{hGM_`ZWj=Ku=U9Y?){;irMz3 z9g%I`I7$!hF;&s?8;Gt}Uyu@^{_Z!Y;kpXM$WEcTErn`QWO9syetdr88{*iHG$UYn z5odcorQw@}jro)YujHpO=HEW1ZR~I{XNadZLiWQ_c1rmPL|wUa?>JnG)Z4HWGDLBO z&1}06rvMPpS&09+!WBFdf9`RfIOAn-GYXkTW4r|2o43o27r&O<<;EO@FTP2BjVaU8 zZgIwz6ICd_w5l)5G*8kB;lMt^o!Pe<`UtKjHlw>g2pZXagz;QN>zfaa*)NP*Dshad zFZ`zzF>HCDRx$_*C9`YP=S;qUGmuXUtT&l^ZivUKucEs>VW_(imGNr4Z`2 zRzI#Wg_Y}DQ8y^R9*o{z3dcYf$wfq@1I|$W?|20%#2OHd@t*&gsWE0st&)vDdM8p? zYMODR3T=$Wn5h~wN}MrMNSTzv=wRNLDTGF0LW6V@Bei~z@P#hMjct2{b{{BoM zG)3I`URjL>6?-=0bGHhE5E{9}?_rpyt}a}`vE4IXoUwu-7cUpHIo6NQxT%bPXk`q2 zB!e$a;tk??16KWp$Wrc=;Ep%R!8I~r_6qxwJ7x&&&v_jx^>}f{GbUrEj3FqEanlI& z)+IBA`}+P4dA06ijCtWaRMQ*j(-;@dq1w)lDU`8gqPs|W^nh^) zE4A8sG*)UmLfsfE|SpFdk z>W{ccdGrS-X3DAjk#Z^j{**6Q8rlcmGCYJK+r3hzFC&!l_Sfu7?wB*Q=iA()W{WfC z+uVDg+-Z!PP#-6qCr%it{VB@)W8{oWIe$_dQ{MSWrMw+uTe@S)Ll&f5T%T`cr;%DZTyQF6G14 zC}q0n1+JOD*qfqWY~P=;r9I1;DWNfDIS+nWoN*Jn27gU046QaCWgeZRaY^mf^lMzo z8S|9>GN&vd6S+uvjJ;Q7$`>o;LvLdm`%`|5($Ia^fRtlGK*O9GdRs}^?PL^7_iyZr zT-vjoc@-ax@e1UeZ!KyI2px9pa%Z!pfDNq8&pY zd`>yk{TsPs-3XbHL*mLJ`YEulpPYHLhvp}pl{+riA{(&f_4o$|WY7=>3>$2DJ&xj% z3vryEbp99t-HG3m3Rm#XP`ho$REe?W#Pqedw@3G{*H2NpcZT;%(IS4`u;g$6hDiHB;1B1@7KdM;Mx0i;lNvJ+ zE;F=FtZ-0y!BrM{=5i2&zWV5jGYtP@X|r++$5b`67Nv0gNW?tV5{Mg#o|U&izz#bGv@X0 zJ2P8hjL*3XO=G+`W6qTwhq?2f%N0pur<=YV2RjKrgKRwNB6Q=|D-L7JPS$a7&DKrQ zm|HAf*)v{W@{E25#BmcDsCUK(>@px{cU&;?>2G7cjp`G5#(VuM*1<6LrZIN;k?WTQ zdDU9f1M`hoRfn$lx$F%5)=$m0j6&fju$^D4d@kEmxbJQMbJ@ZfI( zU1i8!xyTxQV(iRZIu}(_2GP*O;QSH%qGRnJoEJP6t=^m8#tZ%(S92UDzs9^J@pntb z8OMeYnk z)%E+7i&#OE!)9k25>uNawn+{75$2+wT7>Tl@B88!Z)9edUT2>)Cb=I8cZ2-~ulkbUozmOXp_$k!-fN L-P_9czytpe!`;4g literal 0 HcmV?d00001 diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.ngd b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.ngd new file mode 100644 index 0000000000000000000000000000000000000000..05461893d7778ff80bb96d3a958d0e278910e24f GIT binary patch literal 160693 zcmbTf2bdhi@jiTaD+vSw1`&2iVg(o!2y;mR6ZV1x2MVK8Kp?@bA_x@b$Wg3`B6`Tt zumppRvAxC^u(7!zIAg92<_892mSAIWU@%}~lE3%unx2{6Ihp_S-SdE^-m0#y>Z%Si z)6?s#YS7Zq+}@!7wi+B*((yMkDJuC&(c*VkI%R6+uX8m^S*8EZ76n(R&o02r}wQsX+_^jtBzgUw{q3$ z6%ESzN`VU39N&JdZ9}k6v97sC&YE}Vw7ETV`xZ=_)jhkH8Z@J~V`j@Cb3qmz%E6|- zE@y7v%nqk-de4k$)CU}lp3dHm-XlSuRn~OZ%!RWjwb@-nN<_M+E$Hc@N5@zsyLzW} z%$wFXuV?18x$`<^I+XLt=$zj(qdS2Q4je^Gngm}kt#@wE>{*aLr;w2D=sjfGypGw<2hOuucW=j{=H{bOvXUo zKT$E%*M_`>M>e1)QP?o(Z|0_zwe>AszPzthH$+RbF7=Y=uBj8r>yMQR;4=Jcp3(wn z_Yg`r-ZBLhKQ}~8kRSM|Q)>aBC%syzugz{jTTChnjLM`X-VTcbK+{=A`dM;Yd<6Cq){ z&j3IfSgo}jUX5wd@~|Bv7#N^sJ1;`SG9M!?wJ_VB7v>aHXZ@$D;i>F9f2zneJNDa_ zTu*6((C2v}pxOGoDA$~9el9{&W==a~+AP|S7WZw@uCMoTMVJ%LQ*s>&_w+TlMZ@4> zwiXLnZOt_DQzwBz?ZKANwBduYTr({`sLC~S{P{qxrvU$VNv_!mKdj0%$CzD0Jv8-T zTW}6EJB8OY^+`wLllqn{Kc3BLRf`&!+{%IDFMdc+^*iN|V4Xox2wuNel4~~d-^+5{ z%I^PqH6+-wZ~7rYSN>cKiB{OqSrMXzj?ET>CbzId%@s>0x6;&3D->h5=?pn7=!*Vf zfp8%7lHl#^q2F{hJc&MAmR#eqOQc)crm)xiO=$-7DC=lnUt_v~9iHIrlUSW)%1ow{ zOGFMDXxD4DNVe(m?Kc%oHBV`y3EvZ{rDZB5zu|?F?F{=rqjKQ+Z4t%LZEYlFWG$H* zkgvYw8j6nX;TQ^5``c9vMc;mHh14Xb@GC}=9u54=Gdwi3-{l&LG59blXT#e+77dR* z=jBKXvt?eyV}1WL<=Pp%-x;0F^k|1ls0Fb^IX|S@lXIqCLO^y$Ww^{Dw``~uJ-@c- z`SrvVF6K>{Y#}tJWQ3UQQ%%)ODZkyQYniMS)T~teLyatYDW`9(9_IhT7LBcX68^2B zkl2I%R$-Y|Jrn%Z3MHEv@<)wi3&Ydw87&OKKO7@T>WNUYMK{nMN_Z{pOuwI6AvKwe z{%%Au8Fz3(9!4yrilLb21NXZjZxYjC2Sc^f>ZxAHYh&nM%NvS=;6III8~goQKji5y z`G0{>b~A(gsx4G=D{a|Tg_1Ut>h+4Dm;j%+p(NAK-^LTl*52+M7>X%funk4adO=|P zZn2wb%bY?;u?Bx!#Zau_d1WM-RP#l$ISw+wmx~lxHMMzaGzQ=8>Qc}?I8X`Xx>XMV ztMWp%aab96)e)*4i>N_=^GZnRp^{mawGE$Ef0_>|l>AXB+t$ojKI;mnt%XD1>4lJL zW^%t(3@OO{Jk;0LOmE&U38z)pM_Zq9LIl@O1>rSx4h{q=q}a9tuUbO2V0h9C_=d)V zqMM-)Ls5=7d0PaVA@))}yq?67>cvonJ(X!R#t|OG&hdG(}9Lt zL%61g4}2tL%p|O=EQDcodnm1kl6c9xt`u^^;b`FDiUuaNPL}1bcBz$f+VW~BDrGiWx3U6Wh?dT+NG{Q@P23n$~{Y)f6 zK-a`@9vB*6{5QkyL@!xh3}b4%T?ldUl5O6?^qHh;aC+ZL`Stl4T+4I(85z{zy0tj@ z>~HFg_3JTWFQ-Oc$C~vXTwAXMTXWgJRu^hY#oQK-Lc7`<;j*P)t!{+b%)w?_CFIHk zB*vN?d8WoDNdL!8>jM0dsXv~@FvjBMyCCAS5aX2NA8u62jHIlS{7?pZ{_DxL-8MDq zTE7UZv?sNMU8%-Kf2`q8WjmFi0G*)4<}H_XI!RE?IRcJwEWaFj!lA*a=O`D<{;@HYwyJqr8q~X!o2(b&d-^GHy-0q?2*yo;`-VY(FFPgQVuyLEtXW_p*OKFXG&?J6 z=R%rmW*005^EF&Ows7fw+z>ct<<)*#o-2+nmBO)lQ`Vwt3gG?{DpsAA%v6QmOtw${!Y%pKLO5;4W7RO`RIe#r|$J zwLtUtLZO;&jynghra~QTNO##GY*quOfo5Q*P6;P}2)*Nk*wk=1(6gsr`)YN62q)H!G8HY#8{H66tV8 zM)M61^|Q=$z*EuhT9C;cb>O&;iQ_sa zc8wq3F!=uITIQ$&*N^L%&^d8^$AtCcx+bpg)V#x8$d3T8167`#mkLnklz^AIOr+=o z8Qlb2Kdy5E)vNQ5E<>~_L_3LGS2cxM9ZfjH1_HBS!bFxF*EOMgJPr6@7a9;&B%F!e z<6#~7U{4`CR1SyM>nbnU4xlMSG*&0KlA+z>x>>-ux;{}83ZV@`6ZG9P3wF`ZU7c8+sYuHhqEkmr zEPnrSm5_#$ovZ)?Y}nAqFgWYVv80a8w~8?U``A3Jhs{Al5xxs1B+7t8pCOWLOm+UZ zOG!0s0UD^=+h~lV^8R`Y(!&@PR->&&MHl}(s8JG{AO_WWGWh=6?#6_*)+jO;e_W{% zj6Br2Gx)(4b`4vn4y_kAyP2(*L{-84&<$9{)c%fdN|U8^v&56EQ>Q7LGHM2vco!VW zA+VwX$FT|&pcbaa2b)A@C0aVH^d>){0<9D$)PIzyK@&*p#jU%+@}v~*9p1l_)gh5n z-ETxF6f*RH@xgu-NXsCCV4?U;7JyN@xTb$YTB~E)$Nn;rOct=*o31IRIVKc3HwWK8 z)rqtqE2Kvx^N1Rbp@!jRJQLrUI(HBkhuGpKc?Ul@%uX7gOiIze-_oL}B_#)?mqZDD{w>9XOxR;} zT^zzO{#KK0Q6U2&m`jH!ivdTSzqp(z74~0=j~*u0`6+hT9@=YZ8q7EMRv?F-jj1I$ ztiQj?PL|hAlo%IeXE>V2N+XztdVlxbB2^lX1~rKMD^NAC@Q%b_tzU$%z!bRhz$lTrqdq@4a2xbDUV9XlH2YL26fO+-rm2}X8?uryXq$eB_Xx@~ zG#=60-G`tl>*IVx^3LJ2YD99SwFRh9m=8q$8*_P&xuqX*xftKP6p?&RV1WwDa)~_< z7?RbFtQtz|EgFgs=H6gQZ6Ph%41`dua_hXI_)KN9h+_R)6bz5mm&&9T%$SYV$+*16 zTiOo3nX+#5K~0@Et#@Y6td1GrPj<-1%jUV=J$N6CTeyL56FOu5tod`N@s07VTEl{_ zuD-P^P6mBP1?(nWVm36+u0{%Ghwt=$79=3Nr`#}JtB@k$tE`q-rboXK`*J=i)FXQQ zDM^`GeJywfgTUL6WA$A#4oCGbn_?gl{1!e78MxgFW#AO5-_wazhwtM$lEwG}PFV*+ zNVfzv@$KroLIP;xP1J@jv2wN+WWljVTAO|KY5VIVy8zJ#JAGoI;N|5!~Cob=1y~& z_RqTV<};x!$}!Ds8&!>I=G*r9m}aJq25Iy$19R1wW)5caG0i|d zpkkV)-ChCR)XT694qWGGX7{2=+-mW#8;L^FpD0Y`EN>ZytB9)~ws{fBhe`P$BKZt* z?@C0n(I>`SG`ZhqMO-%XfhrmJwT;d-Z7tz~+@Q68l@-gt2NK)^DXx1+xc6Chg5M-OpbZfy@PU>#8 z7Q~}9JbLyMpj1f1|6b8>X9t48vis!?4Wso-pRZ8@L*?O|Q{MD68^knho!c-bA|=Ny zyObq+u1P=LFGuXbEGuvT&OmJbl`QWUuM{ z`BD)VG!v@{fYV${DFJXEn~;=1sw!)0F(JZ0wU!eA=d#wM1dB8m5)#dv&K~qagiD21 zTu1(M3d@KeY%tEyS2)67G!^5Zzn>LKz~!MZ=N~wrLg^{YkX`JE zk|f-)vlSwfjkYUIdCc$#evXetM%sT_{W8gvfr zY2m=r!els)%0~4f+jY8!8*rPV4Y=PWAN^zQiG8iuXoCV?RF@v~^qhOST?6Xb`l_%b zHl4Rg-h*POn2(*YX$Xquw#Tp=>Wb#|~70f(YvA z!%iRb!2O}HAVgcIaIF7xB^1P)Gn*zK$&xKj&#b=A`Ez@^7h-MyE}@lkxG(xlTs1U0 z^LzVxX3gay@h%&5%N(%I%7fJe7SJUgu8ope9WyyieBIGSk(DRX==&(r$RtJEU}aer z^2oV8UHZOnJ2&DZCAoUNFNhGdpWgEI%}NBJ$@Tu`+Z_X8af8V{E`(YR@*}36fBnWt zfpitK_~1x3QboeL8yOx4@jrtl*4LKf)bfpu=;TmpZ-mFu?|Je@&%#adz*{aZH*;`z z>+cfaa)dK|{>+77EGE^&R>PQ+^+4z*3=?n(i(SNh)XKW8gzK@h=QBum*tmXbHnybB zm_H9@47@?XU-IsFuL7<*XLsVc$K48-=gyio8$zf!Qvun?p`~wXpU%!U?BZHwHhy7C zl@$pr<3?4hqZ|Qd-Yw*7AkL8YQ)H)N;Oif z{U9I-U7R)#td-)7GcxvSnXa$fuPMe}*0oV6qt^{C({q z1@wRB%nB zHf)=u!~SxQ#>{6YJ>7k5^X~>!od6LTe_yW-)SCmByT*z|n8fjkht{WOV=O}k2bRXP zo}Kk%c9d2XPuY4VTpVlCl6o3lR99Tjx5qhAomx`QYRj!!P|uL7yjoCCuPf_7J#Q`v zY9;jqxP2u8rWlmb(Y$&eJm5*gfENr=o|0jtf-v6_1-!z z6Ry70hHackCc6DzVMmz00hdWbw{5uULf};-6Rxcg7%#%~N?~ab(Q=0o>y1`lqbre2 zv?5qSxy@MLI0S=BntMDT=VAoyn?8S5*F5=}=>7u0t{DruX3n0=orq_C>V#4lZN5{) zb#}&F&YO=D-;TN0GplD_-vT`o9^wK_CZwLYXIXWqe(G~L6(nWxF$A79r(`)|%}>d4 z;WxWduYq&gVO~AT@#?Uk9_5l^j$4m%ushVQL-Az*c9yF;bSg*NE~g&l`1ymN9!1BT zZPkHOXzrn2J<2C>ohez~&S0Td+hkl>_#Krxlv~#QLsKZ{l<6tG95SZ4^&0eu?$o2K zECq6`Kd>I}D;!-z_~EW7Y0PCZJ`K2`N7bN92L9%W~JuU;?qu@4S>VAaX$k1{?W?^nU8zUu#c%9-l*|2d0oKf6E$yuC7gjyY2YYMsDU>V!Q~VT6 z)h7Y1Ro%v0l9S6Rn71OQrD5KCoLEXp(~{Ht6wKR_*<^kF})~%m=1R z3iU8Q%(afqr(hbmvYLYF<=V6~yB(zA;xn3l||reNB=u$+R~CX4eam~GNqO2M>bW;F$~spb?@Fuk0a zh8eWOAzT}IJjz$rw0u2`Ev(AwET>>v(o;>r>`+gtdYFdH^6OE2{D|gG!}O-BkdkHt z9-2?V97di@bz$vHH6={=kU|QkeLeXU%m8;*>tSq?P}X!m1v6w{uBKq7!}MYbrZ>}p z)&{|*?*~>>FzxOrq+rITkcR2bm(wuEuO9^|B@q5nz7B1k#2WW5)x)^q#Jht+J&bz+ zJl#*hxEa99!BV|6KaI8yPD`_056-8g*{%lzt!b%deCds6GKCb(=H5S_f@$E?Y6@lp zP6k@5TYoM*DJ{)>m{O{j=I6fyKdGc(2)Cz%abtj%%GV1|q3=_G))~TMGP-(m`85cbZeU^Yo}TAIG^ zmxgKf#57DN_boKkHQ*#JX?(XHW{vv+tZnVdY`+PG6ig?ZQ_{FCP}V*vY1|hmYqxy8 z68&BOm(tR7a<6Jin%<1hr(pU%uAG7yvIp&Ym^!vA)T3C%C~L=33g#N^@stjl_oZUJ zFmAt;l~3zni;OAMOXFi;W$l`V8H9WqrjNVkQ%aaS+xRJ%BTPOmP2WeSVfNGqQn}3< zw@eAQvBqqnp)N_-(@AAoiyvObw?Fb z(lmREdnvfzewLPIfIlv#r0M+UCL~=Fx&N?X(eouf0Y~RnnW+u{#{7Hbmw2i6wCE&PZDVR+aq+v$q&uN%mzEw&oVTXSt6?kUJ zAIkN@dhPXAAqCUy*QzO)zW4=8rJRDfrkxX{V2<+>59IG;`Qr}JkADx*x^PYw_hk01(x0$@B8sMUV{^^m zz%OG8FCKAt5s#CC&Y#3bWbNYJNE3?SJ;|=F4O$4#Tp0?XZ&fE z8c3fd)g9DgwDnmF*vOt)hfV96*WAZm@V9cU6oh)kA!BPZdqr2BGFtm;p|&Vf=ysMJ zhIW%S!Y>F`Cti9SI_J|y}wskkC48oXLjfO>CkYi0yP57j_co1TVyWn_$Jkz z%NGqGUa*DTGmrh{!91vyWa0R{_M)FiyTTY^(S+HhzObPecYI3)=?QuJNHLuCk# zIz-HQp~6y!%<9&AzOnYHl7`MneaW4%124KE&eiBWrYdI9!+CH<@+D2*5k1}W4h8?m zN(-Y(@PAka@rdT@wjK0mnc^IO4l8O|R2Z4fG2&NF3g&a#-K`YN&QkPKFkJVuK?>H> zz|vwGr!D^|C2$NI%=Ld)YcPr}EF_??rI~w+i)oxe{uf|rQ@GfNjodf~sTN{IACzjO z*c(5rh4d6#tdU~Zd$(2!$$;fXtr*AX&kHprY4AIBC0W6HwPNVCSOwI{(W(E`VXWe# zI*fIEm~TiruRHGBUJV9yTQ^i|Aa<*}O!W9f);9zvrvViTbC}uP4hbgv*Nqr+=uQiq zW2SdE&u#5k2>Nl-y1!7eVhD)(qg_L>vVVDoVr}=@hGI^AIWQC-K>s|VIMDnwqG zC6pxVEephE+Lpr>qFEj;f?heDgUf?1F7ukzLo=%sZ4$GOM2(Y34+HJAYW|x6=qZ}k zZat*x>sz9VZD#E}qS@)bTm1=ONdEaUc#9W?G zu7Nnf?+GN~5&HLJ{ZMtkLM@JlUFRA|zJ*w8N3>qWU{`{&#sUlVQT-mph@?$>RwI%P zGTx6!-45l5c755$;LUJ1j0p2olsA zA5L=P(ggL2%&n8uyEe{tY9;j!iwjgOsCNKdQl}FeG_ZNWiX_bjQ|pkD#<0JN`NwwZ zt|k#qSr^92^bV6#;u`hF2{)$o#))l`v~CV;myUHr8z;`L=$g>kusxN#W2^)nmfO~e zuxR7N#X*GWjT0Be<@Cmh?J5yJ+BmVD9bwVNiQ|cF%FZs|5a4OAucgA)V48FnlL#|q z8USQjD8qsCZqFdgbPM+QhGv^G6}xH>X4I>$k>OS@)C@A#%2DqQWe{#`Lx}{Z}l8$OPa!2zy`qdm|b8@Bf1Qemba zYef*#S8otnYS&;o`IpsVI-?(PDTnhO^=?$U@nl6KYnHE-LlOb4wu~~JeoGxg>g_*k zb%E%9Mt7+bq7r&^(EVg>R7_*Ko2&_pDvjx0GTJj(v{UGKWgwmJ%OXuW-Lnxl+9tHU z9Tx~&X|-n{o$I-%P_##Ad&fvbnZA;GHid8IBbRl7k3I)5OcE_Dv3pXwd+zUoi6TfkMKd2Mw>6;oInlW&MQ^%Ea z%>Gf;aPRCR@F52(^0zV-%{^u5npG#Cyka?2J9b!DfBwjCELrt@Bg$_H=K`4F)`$U_ z=fnt3XKmA`x;b6~)L+ugv1<^>ak@UzsEbSigN^ZFB@~~gzav8b{Iptwuyyofyxwvx z-liWTbmuinr=uYN2+xELA-4W9%RtdbJ=m$HV$jSbe{~F|KZY3`ST6QK89zoD99S6_ z(j($=fhi!Gk?a^=-3W|w;aFl#v`RifK}xXb$S&;JrHRjzuPF{={|AB;*Ra3y<(hN* zv*9&mUd#)Q!gr!@V+-!IasO2TdK|xMRMszX*)Y1Rhw3dYtncBTE8}`)*R&Zk8q`_2 z07O&QwAsBq-MsVr0n6{v#VmY`Wg5FWd+~)6O?=wZtgiVSR)6G#Ok6)Cg8Fj;p0GS{ z3?(<|iH@w6Sx^+7t9J`+FDUm@aC5prVyQ0g1p6%$$d8Lt#TH-mu`o zOvGnZ1CHi5$BBi6;n|S`Pgr#vv`&LthhZB$hxiv1@X=jt)}8Vc(N^L+Sv*y)#x&L5 z3(>~q{O)yhA?9$t+NK!OoYC?ijV3O2b}7a*Yud38({RP#!j5US%12g2qhh}yX4B+% zRm5dGyccuXp+AmEw%G?UNzLzAQCSWYy9OXfb?S}a1NV9``r1xN{hcnPo>)AXm zH|^xT{_|B_j_jn?=WSf>)Jb2S#T8Im@*=hE)XCI+u|O2t&{0WV;d&Ieq(jE{Ks0uA zM^OXzc%=?QY}nvOS;VL8-!sdZKX3ndh`ywYjFBC*8QMcRB zabX9p`W#V*ey8JXhZZLHhaOEmjV&Q3+53+QIiVTRr)f~9IrJC2{o~Ir7u&j;mi@dt8LCFHJLN(Vo4g`Bbs!Z`S|DkQ39MUCX5>=gV#_}M_X zEt01nhGpCB<@_4vK?Uvz`}B7Fft*hgQJ9QBsG4MlkYa$E2R zvacXql;!CACs4E*c|A*}Sru+{3JhWNz$95=J)L;3{j| za>$jYd)27Y-$nVGDG|0Y0tSTt&FLXh8q5_Gazypr?&v+4+ORI;; z9Wid~xDFoZHSi6a+;JWGah>^bUHNf50c9*M^}ikYu{h{tED6f~%r&w&`($ibM2nBb zAxXHv0WOsLV+C@f^pR&g5yzTUmU29~42Q~yJ_5^zjwyhYkiGl#yF*G979edyTKa5OzA3H#+ zcB;hHMxMl;CBpMmY`;+_?n#@3;X>#1BaKFmjUHDUYnKH1EU7rkG}Fw+{lmTgC$*?j zw01g4dA1_0k!+Kwgaq1tVKpf$xD=4c*2?1x1C^B5y5XLQh)$s=U5GT{WFWQ?v-o8x zBT26tD`ebRf#k57J_ilTTHq%u3Hufr zS$;Ut1o#?78$;2kEhzpSOhwuqjZd_JX9S0JY;I$mKc*7tlflEV#XnlJqgW%( zg-sWgpBY4T>T!miJ>y38iOx_Lm9?t6`oh-usU6~y5>aOArczNMba%D{`VZm~8F83n zlrrIUDug2etNgN;;F{QkBeWrPi{Wpx-Qn5~A?K@4lLZA!VjZq~JcYE@Kk<2w12T4kFHDm$eB-4*b& z9j?kAXvv41D%@rTWPE8LK_c`TvEqC=aM46KnzG7S5(Xblbprm3t8-tj1RmBn&rqTK25{R&4@zRI4B za#tu)YiyNWUyu_3YigT|lmRpZ<=a+C+mgb$FSJ`ul;5p=-fd9^DkmICau>&4zxWyxHwGW;v z$DhIXvdXS13=VuvYdIJ7otu}RiBs7Nim(TgcW9j@lwE6Kr<0aE&xZft-D2zdT$Me^ z!RcO#)Y<_5mE?Eafcwy-r?Ox5Q3|5>XiF}xs_caoyf)Gr zZ?359^(gjrUE4)@D01b!xys&VtE>k--_(*D9F@HR)ZHE}@yg(rYq<asrCV-d@6gkbGEt6(yP8Bd4frxd>JuPkdGO;XDu}k90wKDto6V4}ewnep_X~ z4ax7jwCg@sWxsEOXOnuQsYYX6)O9^s>LO)T1`3 zZUqBZYFW$1LVHCpq2438cK?@>j`@8Q3%mr>3m^=Ju}LCeo|xjQN< z`{Sbg9u<5mLQ7SC+YtWwC<~oG(>lLyqXi4{f)F-B%RQ*!=UV4C^YB>7&*G@;W1h-> z(*w_9eZS#<(D`$R)Z=B9^&L=J=d%TsRnYPao4lV@RrdeN^5aV?`*a?ZEgMrHRZ`h! zQ0@sWIRNP=Q0|v5%l+I(4X!-e2M)azYOp*9h&!ZM`fQX z;K`?^Ua(a5cMW(D?Nah-Pi3F2-~qWJ^+E~tRq=zH0jZznp~V8v(-b6MM19X|-gDp$ z+R$Q=_f$n?pY!mL&n5NC5^8YeXFG9Kg}12hInDbuB!681D-NkwK>ecvo~B+cs_Y*eIWrLYES3FxQQokt>^~v-rVYwvx!3Zr z2fWv8Qvb9ejT+vtNWG5Qe~%j8*3>(W%KpWZEkw9Nx%Vx6PwP?gZ>&LKCzC_!9|e_t z#|JMU^=F0uP{Z4r_xp;<1`Xg<$a~j=AGZA5CU6&;O5nL#X8;ST_>|Zt^-^ACUk3H2 zN9t|-_nt4mbBJ5%#qN&ZiJ(9!>e*ejmmBAsqB9s`JT;k4P}+v1k^hgsm-AC-wpChbtvbn+@>Y@{W)kr zo&PDzPnw|&%54?M$v7wnt3N5qp*JeGg|D(7Ir2tJW&exXE$}{Iec69`DmN@IZ-Swr zq_UqkfKufB7xfMEWUCu$w&1aa`lMVQ2IdAw7^sH zP7HSV&=TNDx|aMzsoW^k_le7LpH@J*g9D!jq&|05_QL{rq;gw0;8jtdo0!0le`)M{ zDwlz?pH~O{VN{uG4Deq`jyhJkCRET=l#__yHmI#EIgbzJ3aFrhFZgYi8;k#j!|0J7 zslAITmn#hVn_8sud6nA*MsFIB+TK#RT~Thh(mYS)wgxrQA+>cu<#x!+4=JkLPQJ>G zcjUM0RBmE`|19~9MwQ#fRk@wZ@*8_9HxATT7m^;e>;Rp6LCZ*8!}cZcs5-jt%mwZNPn$^W;YeRc>@%<#xB_cl2Nfc-x}f4!Ydl3jS5_2;ZWX-OG?h zx$P>X_9)>$OMdrF<-Sw|70B*Kw1R~?VaqliCAYzU6H9o;6p-2umW?UO?{R`xMOh`k z!U-E)v>UYSswg?33l*`V zCr3_9RJo}rw`)OuURdQ?Ky^aPSY2OxUget0@*|QecVJcJ_N#)@yaFWmb7k9*%I)i+ ztR)*pRqo3bl{+MmU*kg!mdbTE$j_mw+yT(p0^U9@tv<+6IopvV$559INz^dWA#ZA+ za?^Y{yHVw)fH%D?znF+CPzQtBr$WgBBnzm0VnFK9qRLH%&iyP>t)OgZ*;`BQQ$P)_ z9Px<_@ZT@bCN43CgZ9Kol4G^RJkq>R>RIO>-r9amP0K0cDtDA4$Fi#2JX__KmgU!CRBmyga)(3mFs)@d>T?R!40gezOslfj8F&PfH#L-eOCB3|Hk=6jbhXP;dII?=)NG)|cgXc2(}A zipuquVxFJOVoLWQn_`I{6N=mCTuy@l^;!pl%;ZK zH^{FetK2D&J{6XIUSzowiz>Iqli$Boxs`cn0gv0IP#-NTZk?x=v%x#1ijN%&q*hnZHqbeyq>(dqO2Ks;27Qik9c#-7gX+syvm*D;UICv{C( z<-S_L0S{W`#YL67z`rQwwG?rphL*h6 zQn^d3N*}STau?b#9MtIrYPr0ua@Up`@YmST6&~LRg3lcV#3N3tp$Yyh@$jGB7#_em za`d5-DFDe1^hXv)X?F<8O;3Mwq9>A_j*&dd8$xoEIs2Y;j7TnzbS|n4Avt2d*AKW< zBkBfE2k`0R%p3*Op^F1TE)Q)Oj8O42*W5)FEDw4}0$z$W%W62S%EnT7H z5x&v6Y$%<>&-4~wB0BrZM)LT|5Va56{co-4Ud+0g6(f1VP_<`96^7?UvRE>bYlqU= zH0PjZKl9Jaz;uvjGL z*!-80XFEekX3ns;{fkKUMUoc`ReRI)h4yzv@))20Qs*T@)!t|=A3j_pj}46E1!{=e z8y0WB*NGz8YZ=K4bs2hjoFc{^b76&7#1>TfFR}9@jO&3=&gK>6j&S%dZM-n9c|#EO zp=rk~xLPDnD;UX(g2={LvSCT*p+6AGQvxG-o)<};7xl}{Pd+>Ugh;vtBYCMkgyd$2 z_jZP@er9CnrIjHhNAB6+>?S(T^o`D|+#w`49rm3OUlYkSx)tcVH2**Rj1&DuSYJhf;fuNunE;a|$n`9vgF#~uYk*g5Q^e>S}-lBKHAd6_qaWM=h2 zv#%1#^U6l@YBhvp(~`T73v=_V$oH$AAtW0&Sv~4{(RqqxbY4G{WW#QIF8HBHo>(=K zH^g?{XqjBvCEdO#%I3jZC3mcPl0YL6vHtn?20ib(3T*OJ#(hL9Y7>O!lBeg5&Krl4Y&_t^ zv9m<-1pcEvx+WMxXTv#nFPtZmUvZ4&E!sEs*VR5T=Irg-Hezea#Msxr7GdY=5|q0& zDtkeZa>VX%c*U|M{V%cGqO#}N1c}|EuPAqdYp|P?E&^>GEG~ONCd&uE_J>#s*Y;bERQ87F~S3ds%DhsQ%MR;d|uaXd~F5GEI2eb0Nyz>yg@C$y=p+6{)R?;aeqGp)w;O$+t?k zY2J1vzEu*NjI!*-RVoxPRGGcGLbVab!r6=RR32d{p@Kk2oP!O1+Zx7x3~wqg@_dVwlltEn|6Zc zkElcs?<_OJ9pc*6@44x2`YpQpT_lz6xJ=vcSdq`i%sTaI6y8MjUtaHXW|NY<0TrLO zfnR(Bs(o(y3_f3`Ormb?@(n1hNcentML~st#^=k5Dzi-}7^>pSRH%#OjL)4jj{Yw} z^B4PkLm44=iEE$l3u-g=JMI@{Z0>JIvlnct`p@(0Gj?P_ULH%vZVorEgFeaF&GLM; z%Zd{j%LE)*5HOLkTddvf>yojXR}E7#_L_pqY?dds(Tx4BTkF#O-WR!a)RwF6g~pMp ze@(I8rD2H9jh42p0lmvhy0m-1m(VmO;nK~paF}jjHhRRxMT&jGLOJ{r2CPCw7s{iCly-TAUd3P>RYPOOt?FZhiRT`6Ui589uLzi&r z%P;Qqkhs)rNeSc9*L;=PPZ!vzOZQo|F5TyRkxS0{?f!~tHdp;$&DXoME0T*F0K}zz zyrfIbC2j|(bBPx2nm1NQQJQ?gip#{MeLTaI#JjzuGR-Ao8+GZSI+uPBe347zzcc1S zXdI>b@sOu(^q*LitqNh3f}~4h5v8)CF^MRZiz+j*C}1K=Q`}K6g;5F&Q(SsDuQFpD zVjFkKu8q?7zc5PEe|6MSXxu{emrC_6?TILrm5I_=Kj~77;_eGEFq+V4;huQ`6E3a1 za`RinrLn$YhAw$3)1n(@qb@z-*1Gh_7rL~^iF3I+*%EWK8RnxodQ3q!jYyR2a*azx zZXpo^W0zpzn1Zo7O1vdc4EwjZWS0$7T)N+eOGRQEb?G55a_K=Aru_ge>5Dr(wAxV1 z4(qY~cZbHURR4tyVU&!8nf(x#@7pFyJ0jIK`0`;U#;KC*e9@+5S_|CyLeuojb#H~U z@O>`&zAs=RW>zq6Gre~zv!i2}KhOmpsZy`O#OVhd1?|K(>huGu*69af^8a>v^gCzp ze$i6>XM6Qd+qO*C635nx4Eox@%+6NQ>Am6fcVT#q)10ntTfl_V$1dFOExmIo(;Ait z8!}6$ceYFcaT;5PGJ6+@ZPe+9hq#k?m`jug5b0=%@}P>AC}+)D{Cg$$ zU5c_fNtRyY%k+}9Czc@(mQ-e!qJVlCB1@`m_uS(T1kE4Odld?Dy|v%vr{S(A{?kme zFma}LeiXAe&op`F}d?f z!n+fKeS2UQCKC|eZ-n77oq$`lGI<)KEsVP9L8p%YwcbUR*(r*)1n-dsm6@Oey3ybb zSW(7mPagk5mkz&wJ)b9Tqxw%W-833`@~&(c3td9=xJ=Q;WG0ljeN3#6T)Gby=G~M_ zTi-TyjpXP~Wy2Jg?n6ZMnJ*j9$H(ei^4%|rQp@Emu`cNM(OcN!zO5C-mL541OjkhB4cze%u$zbZ%Nd)0UTAdlIgRN;Znh0JEDdd-x=Hdsn!JPn^Py>%A3@ zs`r-_RHQs@`?&at-gcUqs0>p^)q9I7vs!w#V(B38T5m&g|*QwnMq~`4ZgWw!?d2pvvsv%C=^cI9 zzAA3+ToN~>`|fVZW>#%lW)H>9tYU7|eebBK%#OZ*x~;^)?T?y&g*do#$uOn+ey4~< zk!3J(`dhw&c48Y1`BOtY!g$I?q`8eWS|9u@ULOp9U~4`{-cj{mln;H5`tfdM*@!Fs zc!#QN#Jv|5p!*eMBksKwQhO9-Bd+x0aXvTV(#}Lb{<@9vs4SrA$M=+w*VPE4;_Nr` zR32ee&wakA!eG*me}ihr`NVWTe#%QfyLr-O(kC5%GKdyNVQicPG8-jQcle|6vcJONi zaeQh~_NYss4^gs5T|(Oq$$@%TndJx2GM$%NNfsO3GgFHZrd|C-8BKz#P|hUx7JKjY z073H?C->tR8{`qK_W9``?ejB?@o(&e&%d#vU^^EabU3u`s`^hf19z0%T{S)*S_p?N z8k*_J%Tpr>_N-#EpF80FHgv)$%d!P{kCAKv4p@g4B22dcpDy*}Bdo#%;CL{rXfO#j zHveZFEvFqHw9=0MDuClE8SG!h!QSMZ+2f!Q1K2s0`e65X(pM$e-M)NSAiB4E2qJHXZy5=7(WNIPG0aVN{zMwq9z?Gq5|AN6}1bk6JUzL~+^6%m&EmaF{M)#+$As!mp z=>6%`$K2DPW>3|>t{gT26o_LpZ287aqCLq^-jN>Y@QX8Aka&vp6Sz6U7BCUt9rvGp zgT!}|ZjFE!=NVaM-D5@{SOrGh5W6?9?80Ge}pk! zw;c{2_??`L=LeVgog8gRjOSdZ?2j;nLGl=ock@_mYNPdZroyf}@y!!vQPBKprWx4x zIB3oP83zB22lltnW(Svu=}^8Dq*M15j^0e&SL4Zh<)(YRi!$R>|0#v~)LmATZ~P>6 zmnr$iPZlgEpatG4mK*Sx zopE@N^ur!Z`!b6x`G8SU`Y#7~}cg8*JK4 zM?pRzecd8;Tv5|v$@PkrXpob`3oL`_qg@E`jluEMiI8%)e6@0XV3+g|a$h!FBS zW0`>#!m`-=IaPl5%fE#8e^x59v?QSMo*l2~7%cLB#P6Jw#ruWiu}ucV``;t>bE?EP z>iwT9(X#3-3+eo}%^zLB#YQLE?2P>8(73Paze&|Qz0j49mc`AZ%Hrl*E)$^Fmrt0r zX_-|>fY-HY38(SRb7mog>%u#)ykMa?cvRUiwa#qdQm?_p>AwZ&uNJY5I{k(dIsIk; zU;m6e*B2Xgddq)h4}!-1RR8x;q*)Bj7Ql5 znn?5McVD_8R(xmkbEF{_7fk_i`fU`LtCeij>9^yj-}=4AUpxf)e@1%FALl=XYA|v= zVA30nb#H~yTpGxSn zIlgExnQAX9s?24ExPC%vZnhaLL+PCUcT+k3k=pr}RlKbTrmtz=at&W%Q8F*VoWiNm&5%zEGtc7 z*3C24pSp`i!~ezWi@%mpK(~YT`E3=AP5LF(KY}m1&mD91C_Y7PQ~lpXSH051wdr-4 zzN(zSfc}Q2UEw7+u@wE}CYB}mZm_|ob&0X*(*nk!s(^|6plR#(fTo+lT*2D3r*fbB zNL6KuzQJ@y&TVO9p{zA;v?KprrPq*pOL2hQjMk9%#69}NJx*ev+g1N{)!1hV^r|4a zhCJ4hHKYW3MP4?GOQ4TM3w)LrYonazigHz8T#%f8Ew3`iIuWKA=qo(99~MSJm_YZx zxaJ}Xn!hN}Jnq=x^foVAC^Kod-peRsTJH=r4M_g!Tx8?>BB} zT;>Q*`mp$PZjncUhzX{Fcs@_&h`fNwUVDTWVM?d(x1F7HyZ@M=`D5UssBSUiq&*CS z|He@rff~*&64PFO=%h3GKOCa}trD61VI1Cl+s?cfg{P?gyG!-q-2ex9o{5C_ysDgM zBH=yXk#n6SyyqbyuXjv%FDi0p32jP*cX)%!Y>3^)l|CXRb6!;hQH=t|1EVtMI}uhP zc0*ZZ7?gzLdjH8qMPlN3@c)+1qjzlM(}k(3|NE7Cf6ql)@{AVo_kyyV(IWny=gJu^ z;_s;#t$0R@g#H{zz6OVC{N1dAz`!H1S*zr+FPRI<5eBY4{3Uaq8(|e<|3ccIY8y<_ zne*B?x~%s1qanKQM_xD=f9OS1(&R~pE{CH1RsYwmdVfoW@M9GZm1Zuk$O%K@@99N3 zcSijE3Nj)7K41;nVi?LK{na0+lnMfdO_=?sO|=oGPz?{X$(&w{FmN&VRaNFIp~A3H zdDKm2jY~Q4*G?z4?!F(O`$j`_q912|x8;Q>{AH{jz50IqmAo9BBZ0m!P>HXSHspDX zj@W1VF;Cjbd?hcSaqc!acVQ@~lb4thbVnV9!9*dD5B0`9x5Bb|-OO zgJAF!Ey?RORo+WLYoZ_PN3iQH0ZmhUr>HV#6e3J9rhK}0VvJRY@saZyiX|N9y~dg< zG3_|kc&RVbKIWS1lVqGf4Wb0!civf-pzwhhukHE-$3p?V$x`Bc5oRkMi6oAn?6}gq(l3S@qm5Am3w^-MF*+=Ys&R`z1ER~oy6ah^7>$>Fqn8Ojf1kp z1d|y&2`aPJF?Q)HhMcj4Ce7zY21^ZE@(W!9C6>F|Cw z#4P+7=O@m>pT%B|8a4V)D08stzcoEa-yF{oN^O zol&$T8C9>WG9?I$&C&uF7SIA-gi*0xZk^&s7}fLpJ5*sXiRvfFl2aUF+TZ_L(Q;bf z;eV{Y=vIHn)u&h}T~PgH(~+a)^t_V1FL{*JXD+bipuRg@Qm2-a_rR{j%@Z^uv7CM$ zv6xp9(A?@j5m1rApbDYGBdx{>XMA7oi%%^Z=3NleM+atHi`d4N(|&^+J<`(8a-t2Z zp9Np^bZ1Y09`92+RR3*GnB9^07sC6Wx#l6(#Rb{0Do=OT`pFHe>mfNQ2>vLn`)XGkYWNPi{y)+v+cJw}5$Nct(ZCw9&?d_n%f&=4?m6g!fC1pYnjj`DF4K z{Q>d*R|>;Z(O}~J=Pt(i3bBoP|6eaXe(QVYPgP>#O58IaIQrm+ps-8zUsa4FF6-?J zEjeON#1`z>H6Y8N!7faNk3 zl{ph!aUVkmS$Ky$VL_Ro`6H@3d9E=~88;xVhwes|^4Z@65%-&5ty!D+P4Vcq@29Jn z<=v|P-b9v*&u3!&(Nqj4n9RwpJ|8cfvrevZC#RX7PeUL7Fmxpv(VG-}$_Jh4Dcugf%A8z{Fyr&izsOxr(EP5lp5QPLxr1L44&k4V2JgsDy zlDd48bhb}yW2x(JT1kZwzaIhLHicy-jLENUcfBZg0~AijP~A|Uy64!*jXy3t;wh^4 zvh6eL1KIealPPnB!nFC%CIoxjL!`_kLFX>=r8g)x4oq@ zw>xC$)Xk*h9Qy1H?ekW5XHP}pLskFHsUhkbOCL5F`usI?-r-f_^KCFT?yi^FJcyE3 zBz(?$Dszn`pz)axLcSIXhN^fVappFPp>V?IHP1|#snPI%vCmrO(MujXZErVPtBm%^9Din)D7G5JFHM#Oo%Zu!_} z9zLA;YM!QPUp&SXZ!a@9mm-X+^!~&viVNRpv%roA!B>mCEe_ zPDTFa$jYccC#Is^o}T|Qv>vAVzg0;2>?OaR_h4T9`1YDo^6uDkd8jC@OZd#kvR{R# zNuT-nRzuPbiazsB_?l8AXM7%c!S??oX#QfKCk9aB64yR&;ic~)hWc7&)0KzBUTTsIIYu8RgTUWkl8tS&z9)i*{ zaHHH1dX8BOqeug06!;T=ly{>qADZe3By*|HM?S1Lo`&R}uqt3;8e09YrlaN4(i?rl z)LQhDol7;g(P?Pw^phR@2#VYy`J1Vzhc=%%F%RW4Re!}SBBBsp6C|_sCX778Ft$ku zFSq!h(ztwcpbxeULwIF@2irnxGK9?CYXSjH2>Ep8COg6q5PcYO=5i~-D#Uj15dOem z62k3EDsyFlm`>S|LAslA+o``5Opdx~V%zEQ%l9||g=b+nHVX;dBgpFMrm`H@FGJH+ zjy{<;bo@F@L6^dD$<}L&Jg1j`iEO>50Jq8lhOXvzwpHdTC&Cmn^SY|aTn7iEY-NYU zv!5$n?zf2k;%+*wL1nHjlA(RxY={_JUKrz1l_R@pmFq{O+uZQUjR%V| z*D8I`aOmn)NL_B=5m&FadF(JNPq@nGGqEj%h!)cm!l)|WA{5So{%6;DTo?*&}bd`nGhQ>BJBIVLO)ZaQl58cj+dnkT;GK%H8!=~JX zT6(caG#*7m(=Ekh552Wg(?bi=L+`E7+e@m+{h*hkFOLpwH_G_y9GP2+#vz>^y1(8E z1!3P*P$m7f5MflWw~k*@HJHS5_p-`d>JZbh+&)Opruw0C-8-Y*4m!|6nYpU}mQox+ zJt8&Uh^nH~u^R73%=jxSy1K@@;r$*gnat0Ns|tk#4D&O4QC^{Fgek~#yxDu$sNZYJ z@P97$mbb^b!5VQQVc z6NFxaY0X?XKs&LG=5#iw+4%48;QjyG_`g{&rW^Il$C^=vO=0%V|9_l)3Ahv0`F<`J z5d~osAz>epO+XANtDwUsI|f8HK_j3b3MN-URD`%Mb&1v%tEefqZY?&oR;^kYZEMx4 zb6i@jTjSoU)l`MtT9^O(oo~LGley+z|GzwsUh>Y&Iq&;zbLPy+Ox;ghzOnFv7XQN} zE!pRnFsr(sBM|7@B#R95+9=oQ~Hta`gPLS)240y!vDH!GyLtZB|7e=GJkst z6ja?-n;!n|FZ{2&wWR8{TmHiTy4zuTJPMu{{?}cPGTBf03;*l3m+4XPXabH9@^ReW zfB*)Kh5vOwObYh*3_7JB13-*m!NPw?5=_fa^u&I*DZ&1l434!0dl_4~y=yaqJs)5< zl?Bra|LIBh5G>g9Wk2c{4M zjA1Ucce2Uw1aELen)E`%$nXR&k`9XBw66}J78j`OFVlWRNWH4N72b1Gepc7r1@F-_ zg7k^3ZhMZ)oz8>0YfF5M#f9R=Bt4#=I2k80OlhD&2BlCSAJJ@pDYEEYHU#AYtVkHH z!O(?ZTowiayD>?aE(-^wnhNh#gzz3kQ@9F*pR=ty6`X}CdwsHraP+C??(*cC+e`ZW z0>1FuvF#oNBMZMfZ7e3Q`z1oUKNwdD#~fbWt%PZxbJg$fP_qH1NaWomU4~uaIcf zU59P7(vS6Chi&v)CwBCmaP*)gQ864%dhbXvD2^s=cenvY4aXnIQ{w?vB@AfW}jJp-T%)(am?H5J; zB8Z*3DAe6#8M6R&Hx_6mF7-zP6+WEag@Gm*#2X{15qg^h8uBr2ie>@OoM2i2t<6QF zglPf2GEE~@&%buJj7T-+Uq==Xr=q>P+p3d+)ea7=dGhK2+VJ`Q)(3eoKRg|AD~t@~-xU*S(g>u!c)@!k$U zTJOpkSNwGam!3gDoI(p|WxsG3lxY1&TA|qhqlW2)AZR?m@GpJEUw2ndFn0D&VZDM& zm=@lr*woqm@(|uXWeD#VmZjkr4WnL`Vz44*3DM4jvpWlZ18A-(-rRfzV z)UP3q>g%08DB>O}(4oAeb}x^=W?ZrU9|X#$YH&7S<;Htu1N{yCJi=CWKS~p(L-~(X zfXNVapNV)YgYl_SdAfTnr|ot7&Vn}a@1UaN#d?f z)-NMaK7m8y|AN#XJA|{;re~L(`d7AeO<~M(j9<`y5so2qC)Uhb+h1ml27SpNV|%;5%<(rGV|%+lO7b@vV|%+lgn1`p z&%fz!pW5E;GTw{vf=k;PU4E|}jV-<1|8e!}i1d$Zz1{!J)9Z+E5F8=o>1{?3z@Rb4 zh77^<=~VyV_VB!5!5ABo1k>{4H|0r~U?h#k(5^RdAkwR^bRR~-iA8MU%sY@<`+u8=S!c%yxs3%8@>9CGQ``B zu|#5WiKv7bf)`RzgADo^f`x0;Y=GflG+L&{1FT3`hXQpWm`=mQuq1Uvm`;qL$)@Kp zJzyD{H_lNye<^l{`X~06w1(?*mW%n)`MWB4bVlWz-KhpkmdhfrWu@x%2-SMRcKHhEnl`c=>K6L$cK;Vb23jU8Zi}dZ^Y5f*2 z-^cIcn`05hP&nr9z1_QQ27MpL^95=)z|b(g>5&=_Ff>mu38O9qV;?(ZZ} zIE^3IW)+PKPQp(H+^CP=SK(OwH~G5P&1eXREJV5^3Y2W7t7$9;1v#-hcO zRrWbKlliwUkc0@*$vBQu(A$k)4#xkRWXE{Bv5L;{@jq>Pxg0YKe0(sZ{?7-w5qgm& zHN-n|Q|#k+QUNAD9{N(U2Z8bleSCzAT5S`qHIMv`xIPp^HFuO{Xg(|zID2++)m=Dv zmC8OQ&JHwxSq^_Ife_94DXho>Z^PNQ6r@aJ6opsl5evh;pA}G&%MALOb-I3@3otZ= zNjU8HHbLTEQnw?uN%h&PQU8CT=0laY`(Gu3wdPSNS<>Z>v=Gj+pv@hH7u0E_<}dfU zjO}n7npq9?$uQJ8fd8%ZivabHOA*{qxL=;9N^us2$N!*s;veKQ;lw}6aDiSKNbKrj zZJ@hIA$*vFk_5G^@nMY}2;G&EV80~{ukfYD1>2q>lVHK$st$t>qzP8)OE%t?q=rYM zk#`G()tpQnnQD>;JD>3R9DyoS^mhL@DHs=k@flme9Q6FYEn7MfJp%uy?RuQWfg~@{|}0EfKG-Hs>zAm9h3Bn z{K#aG_iYyR*p6dPRoUN`!^meJf0_@c$B=1YCG(*81|QSCOZM?ch;_W?(m#>E zQ89e{ixdW;zBNSn%`P>|I|9?f?}IV^l?gB?!W%tdw2umcv5(`x-f;=jdWVNaetRD3 zZY!vBUZZ)k8{F#2vZZ^Ec^wCxrm`yS3#LXu6%RPxp2uHhZ7&?y5dQ|RFVTE?E2SU0 zqKc$baa5n|QTjmte{~1|cWk~%r14^w@n(t{i&^$tdc>Y+V6Do&Y)2xk(!S)+M}md7 z`)fF32N_)9TLp`y^vtDBstSIsf!QDCDUpVGRS!)tC&w1#PaBcaqnI@5@HS5LVhScngcJvI7bt?NzCMva6+MiViH?Ptm>91S@ zKYXLu%J{KW!EZbeY4kB->n_`?v`RB5QlBhPLji`S=>4nIT!4wxvzHDbX2BVf+x9H*ln2fIBTRGrO;3kZIw$#?o(`$(m#6m!`_mzn zy0W+X8<`HN?CsF)NWSIhRWJ#jz`KQcI;64>TsFx@^KgVrhu|(Z31Bds4j~zW$#e*b z5lp5-NRnWBIwUb3R&vJ$LqPOxA)1X2a#>5wUie_4WHOot5kX65;` zBM6k~Z!jH#dz8@a2=)RINDQ^f7J~6~$bvMIBgGhM{gF-2uzEP9>z*-+8nZlg1`cXa zS+7Ykh!u?KkV6cUc#lTYZD^H?gWC*51DzO5CeuiMK&qK2T zrpS<2A>iBP1FT4TF_cCZf^jj}vw#ADBmBge_8oQpyOvp;I%i>99CHRvX+=NqQ6cq+ zqSCfZj|=l_!0vBAhQ<(l603v46Kv`()D(XOyxNu-l&q%_!Z!qAN1gTbXGdzUJ5w_> z>iH8!%!SqPW99KkyMC#j}qa8l_`LB7g_fcZ=0%zlT`)cToluZqe| zIN{jdOTvemvgc)iL#9P{P+BMy|}6rLQA z3%pyR=a^^*#SmQZydFIkDFy3cid#|0*z=tW^we|WWSHWHGBwDcnBrfkmfw^DOi?sr z42i}AtVr0cIqE_%7QWr~DxC|2Y2lNb`q@2-gdYW3;%9eqD16e}HeDiaP}v8psPIn6 zpyM51c%>DR6Yp8~M{4o3|F~Q*^LBp=6VcKFEqwR4EZgKm(cUv@4rF3Ul~|G@W}$!McRC2pK(qEQ zUBp(}*}NkMj=ln{>97rV__sH6h2$WBd+KDu*9McDAM^7j>9jwks`GeINMqs}> zc@H#pw#q(~iAvoA=GBWn@)W#ZL#q6=3u7j@moi$1a%HcyN-QrBDMKm^PpNHR0vgem z8)zuN6k(LZdt?Gkq)wc6UOxim6H1+*^w1;WTI%%gsA5Me1ozRVd#9^lfR2S==iuOT zRQ4%JW|{4(^tFtcjmqG%O3Z{xc5l+bdEdQrLic8@Q|`wx=c?@U zxoF+Ot;0mhVU}K{Pm0!Bi`0YMaG{e|=?C}D$cwXk;afUGR6^m2m1*$HGbq9b#;Dl< zBjH%+rv&dxX0J1Z%Ai-BubKeXjhG_*-&|5A$T z?Fxrc$WqdIl|z-U5VX9?!45Agpuz-i<; zFM8t!H6CDS9!=+{3&FHrUC)Qcs;S=DWnb^Ce4uyay(8$C66fKBocHx&C$3c8 zGAc2@AbPu@)i~%DE&PG#8|Jjk6_U`a6H0u9P zZcSDkowPD47;85omJ_)qCsD*VrQ$?KkD7c9onTOhg^isk^_OR2=1oSb+M zfosDPFIG1hC*DI41dB^VLyM-vRpM9+1ynI;o_G%-NPBpDhW_BhyJpGW_vkt2O0VF6 z+mh4>oxOS4Lah_;&Z+r`=wwTx4_y+Q4hpDMzjvadhv!sc8GQRNG7Z92)@yU1gY{W-BV_W54Y&2UrbrjT8H?7NzuV+ zO=WmsDZrozGX^C%G{n$6hkf^y?8iymDFZ`VgmGkl$LOkG9+5o}z6!?D#$vCY_qR*n z;0sjt(X=l-s96J$qa7`X%agbvX>&Yva8V^zD&`{M5|;8R18fHQFdjP%Ne7tJtb=-- ztmgn|1AVG$){G%1bzzwQA13k=7ZtonsFph^*<>)eQ@>1aQYw_Y(|DQQ$QcuM;@}G* zx9rRHU#90(4lIQ0yu3>9BE6iAdNK;spV9q+1qQW1Vzwi7=#oR|N-X$jF{1ROwxb>k zw%{Lnqm-<eo5){@o4&DmHk5|s=h~(RyT!R^=Qluq&wmV%=lXs|+g$7N|expY`~8{WXZ1!>}74!0Krn+TS6prurGl z8tQ5E*Szl&ub%fHn!ZG3pOA7ETqh1MBg~ zT{ym#jQNhrKzRE14wDX+m=DZQ6TTAHR&>&NEJ+RdSg^#LniGuc72dXoM(Lv~^W0jg zJ2Tai`-UxO*AvZLuCh;J=y7!({|?-D7!opc-yk^i1Y6v9P|9@Q2%FBu#3$mu!yE=B zcxl#gP(iT3eZ!Z;-eLD0l#-1)c=Z*-2%E5)?weaHb&oE#q<;B>M;(u*uTa^SN>TNr zle~b3Q+I5detRtHXTrT<;TmV-Qa48&4fR-{QyHCPP}FzHd6ltg!2KTz3c^HKFjD_+dT>ZiD-`lAY_`Z*|E zC;DEKAtx!*Fjb>$AKPN& z*B#%s4ozRFvM&^(>Lx8(ct{&?!mX!k$$ak5ysHYWP zm7|gjnvp-XELfnv^F1fHtbQbIGt|#6Ao6pB)%5+m$Q9$Q?rsjOGsKxO;YC(@PBwJMACczo^-RYKRhNx7VyjhMcrAX8vd zbI9)kb*EjZRmN%lc0#BqPs0(cOst5n(UhpH>t!vbqvcbja^s-R2g(Ne8>(DndzGm< z!k|)F|8UGH5@o#sb2Oi|6YW#!7Ql5X`%m#|Fjkoe&mD^t-~gUpGy`~sZ3ggIMWIeK zi~wGU*qi7uXa?}~qF_M)pZvv;A94WCuw^3$FlE75ZNeG>43X)mYw`PnBnPlNI1J$U z{SzKS<3Ci{50&p)KOQkifM>SBSUgkUpg>K9aCisZkIc|Jq45p8y~-Gi-_b@7;MNMMKL=l-=4lo>y`;<9qJiv;CJ(H&{1mjSq8SOb`!nBj$j78@R z;CLGm{05@YpCVD#o24M8S9Cf2H#qoum3`f)%oL*NzeM9K5k3WlXigwJ?`l1;eQ z{A#W`uwRGN<^#Lk4F~)MNB>A=-%Ca-^C(v(RzNfd_DuLUoba3u(cv}J>;k0#(J%sg zF2sy-88icXW=60eun)4={E-8Dx+5Douqiuc7YM5v*#9U+16x^d#r&F8iUs~XV%uVx zHvX~7{?CpE_NTi3Ir(*dT) z+jPDjlMApSVOJJ0?9L0ufxQseREsd}eT0i)d0qy~zAwa53(=VNXo6Q+^eQ=-&o(D`kH2I{FEn_g%6=L1 zH3t*Ci(%eZgGgQIV3s|@y-PvHL%6}0F!3B0+Udp9U(~4oKb^la_Gs5;c*iCiMd{E- zthv#R+NtrUV8VqCZPQBMD^!>0w-9j6m*}3KG@OH@Z&KO!C4Gaj$M_7+OO}-AQ`2UN zKG8Kx^g;ypiX7Tu_fk%)#A*cGc;7Z=i9R*WI~vzZTb5@&;}R{`9dfNqb$%h5Yo`IaxzYr zRAO^MJbes&8;V{4zlWkvM5)>s6@6CHtE5Y4TnGHaMJhpbnRJXRSa33KzkTfr7QG-X z8(B12?!**fHBZJL#HvMq(4wbT4xD&6TD(PN-!4Zzy~I_CELtGGa9Wk8=O<0k^ND2FE0s!|hZb1$Vgz*P>608&^l?ct4^cBjXTW!*V$c+g85_N$A$sOBn{H*% zCpof_MU&-@(}t)i`lEEUr^|LrqQ^d+eIDHuFaT?k(@QOtI6Ez(SCmcB^9!cvc}Rrw zT&5f3^jQV3B8hH_ma&;3dLOm^2fn8Z+=>)3vfR89VKqg6>Q;;XDAtnbIV<-bgcg5_ z`G9=X)2G7IBXM$OPp>MOqF2H1Kf*ThhgVsXBl8e7!_yOyj;DTyr&pDDM?-Y_##26L z(W`ltBL5cN~|kshs3hnPPpuPHQ}m~~Kr|lB2+{CU^Ur8p zc+c|oXz^z%`}edj8dkdlBrr(K<3v;rL|dkBk1x{G|CpdZno)^!phO1QhRn{Z=e)&! zJl5hP{EUrX3Yk1C1V3gC)+Bq0U?1HgTOWLW0<3- zLDH8#!9da~Fg)27)S|2WlN`p|AkQnz0Yqaoz& zD*GC$ufEk5NLrqxhun#zWyr@+(#i0ktXK&ob<22_3NSd{B-OpLlvb1buNj)Ly zDxA4>G|(QYUyRO&BVT zwgmp*4oUoqPN(~Umy?ZJ5*`AG{IUtFDe1paNrjfYG;i#fchKUU80e>>l2*I)yCCt> zDM?e(DFynC5|Ig?cbZs`Mz*^Q8j||vx;)F0q{ztGkA4(%N`VfjDXB3csp7OGsqgLG zr=i8WRQ98CRMK4J68-Rry|hf3lIG^==UPO@kVL-_nrky?NE&=)dXyh{N;a~WE};YR zgw>R^%dXC)#umNQ?yF7Dp~bsZ_SIZe(sFp>q@qYV%`qiq%k<&{CKv?XnP9lQz@Qz(r~mUNmU8(EUdd6jILu$q!Sk9g@b7cE=J_nK#}etpiRiuVhZ{ai&Qt%aAeL3ud4 z%1f6Zvy{aI14*l0ud>!=(2%rg^n#07(%DKjvZNOruX0I_u$q!~$Ev;bx!sbav4y4g zqs3oh1d@zOx)>Gj^q`1enl`<3o{Jgo43RMc?`-8&E>1FNNSgoIp%1d8OVhHEC0$YW zDm+H5DXCJbmbAM?NsIa%Xrr4QDB@OB()mS|Se4P-Vh9lUB`o4wa&L89mTVgiQq1mb5D(>9ZES)U!>S3|jn^ z%6{CWJe=>S_$z6Vv^i-?I@8A8{4$X-B>f2t&vzI!B&FR}Shw&Kv(wZSjpDUb+c3INhZKYD)SdRxRn90$Ogi;*H!u4aR5TQ`-eCDBcmbDEW8eQ8%q`nE+$ zZQmc%72W(+W&dSIC9RL~0~tA&)*;kxEpuXfm0ViI|L!nBkraQ+_A2WMs}8(LD^Gr2 z#S758E+ZS+OK)eWCBkZX$@)4My>En9-6#x*?y@}d#UbNV$J5Zx{kTt-@`d;}4A6xN z-?RV{ko6{n+@a_)@Epf~=?yH4p$u~EbOa{N{zFR!m-7Xpr{^$kP14ml-TTR5GmE?< zPuRbJts_Var-spCni>zVBCy2CHgzEwb)phy=BXpX^eu+3BT@Nntfi>zxJ8C?;@B&*laye{3Jvlu^SWOpx zTP@%1Dogx3f0lG!%9L~&s{gq*kqK*u{{8;?5`#vfjeG83 z+#aB)JWtc7TFH{uCR9OXwYOW6wEUSfW~0U5;aYNtcvmBYWvI*x*8f zYD=;rUh3Fl;B~quelc2nSY_X8a?-j~@lpbobRohpl(e~^5)xy9muQK=rHU9QS(~+FBeltswHLX9vFKK4WP6UVnxZ>|e#FGIvO2mg%}}>JY+4Vr z_^8V6wxXiXLiqK>DUC&+oi=Bve}u3NMc)9ACmf;{PRrwcgcuVR7&LOP)1#Y)vFNkY zvN4>Y{*e-lMGr}Pl^aTg)fBx?=xHt5%C#hV(Wc{WLyJ3A_R~^S^iSaFJxU__N(5jy zEq_(n6nzUqdEX*YGeoyZd6l1}7&Js5dBj@0BbcV;uT09uQ1n%0!C17N_bRvK39BjE zDh1)KMYm74BznZqz5Ad=7t```_6x%Ma+@FB&z`=yXo|kN%F{QM>5>0THwf>&i(ch& zn?XbLvdP0vV9_@hWn(D%Y9$zp?uGEasZ3Z+(d|RgI;T6>E#>sY(Nnvj#m7|k-%Y}M zYn~tf%c8gW;mtX{txELG4m~!QsD+-6ziD}ut$79w(Ib}3KuhH5ZE4vU=Jd9R=rLul zaP3q0MJlJLH!%F|b5%<%p(M2|`lwNNxY z3Ab{K&7dKA&t5C>b1xEoO;I+6p1vX@7<+nJ+N=E7A*`n8MCfT9-U+v*@Lt(#BCX!} z16GIFQPEcx_yMu(>04uFcwbR6MPHSp2g?#QLv*`5(zd{$A$mos>pxiZt+WkC`0sAg zx7w~K3C5xihHHFX!!(InC_4Um&a2#*WY7@Zeb5>EvgqqlvN81ZR$DL@Jpnm=t2Sp% z(eX%l$DNi$kNRZjP3Y!ND!VHe6@4wd`2(f-#!yZyQ}hpDf>3k;b$+a3x>CsWRoJy9 z(E!Wwd3wxev!<}MPI(etKY?{X zt}i;cU3V))e~}i^SEs{Qal!-$Xe-U6WxN%C%Z6J@3>v;2_w=UM=~bLw?*wIvmzSJcYtlGaz$%IX@f#2nw@v?SX3Gj53&LhsQ-9E0cM7ln zqb>MQKI@C=_#0^Cr%A%}#dJK@RBAluOWnVKao73yMZx(_@6l5`;Fu>>!@hFz2__G& z0FP%g%o2?k!gu5%?F#-oNQ-2Ys}RIj`&2Nta8>-;GEp&v|Jn5_R}iK-vv8Uy_-P@) zAXmk|#eO%27@FtR#aCIfAM3p~M;#HS_3q~cbxB9-es)XIx+T5*WE}mJ%6=_%DTvk^ z&}le%aE)U|Yu?7sjzN`#1kp-vy@4>TE=bDyy~qBKqxBj`HgW>iSzaY?6IL@?JEf~7 zb#hyhWIwt-ffk>JBpE&hlD3!4$%AVl@G`VVWW36?8OSXV8AB39;Px_uMgn$!?)b$l z=~~*R^=e7+FX54EGlbQYWXGx{*)4i$)+^Q-Xz?$qp)M7zDc8B?*sq>|%RuFnxxQ&P`JE_KVb&vF39~bdM zSmI(x(vt^2D>7(E>eg+|%`EBqvTWqQ+Z&R8tPiLusaL6Kh3{qi6~2cZRQOTbhM$GT zJ@`iXLV^naYvjxeMXB(=aOftooXmEV_>DSufQDBoTKs@0KDFJ0fr;EK_Z#CMH~l&- zI=I5q9pzs*0j8*$)19#$r2s?oc!o!sx)4lP_{64?SGgxen6B_$OTk+E*Nafs+wpel zf83W-)-N5L&9;SS@Yegyy%Ps2)zDFjJ5uHy^o3A?lr@&O^KJC!Req1~{AXTFa34f( zDr3(KZF``s5?ipB?@KydC1~3BdLQIQRQ$sfHN-n|Q!3to2JR~n)*6{f4PpT(_IsdA zn3mMdu9jpYDr-tQ>g}En;K1iqL#vGM$3W6=;g54|k@TQ4CH>r1@ih?0k{&LpL{1R{ zopCH_P0p+QHpQSR=|O)-k(7n!es0r#p`acY_v7~Z29?)wM>XnN0e1Y;Xq2v6OaBrNpaDoFa3#bkZ z?SPlomjX$7Q_`cBik}BtagO2HO^GczVqkb_6TC#%!BH36`nyeXZ09$0N1AR7*3q0QkL^d?JsS><{Y^FOA(bCHagN=s{0kR!kEDj0%L{Vz z?{+91VB<(Lt7xEcw_;H00SysR22Iel?5ZzCHTTJnzGJ(?qo9T!Qj0i|Xn9W-?EBpmpP zYOr!qNp~UM?ktL=`;(@m`wNIgC6XS_Uo=|##j=WjZVBxN zP$P~jQqTHr8~QXA|EG;?FEhwHs`yEu_&|;@O{b4o*k{qFIXVX(-)jaAd==Neat;dU z{Gv#wexb7yVKU#LUP3zhWc~}EqtICf%kE6mj+)MZLbY}JIn7w7b*%FW9QYb8bxKj| z++L#7w$S;tQt^~ay%==pM0|URL7_9h=v98L2-9>9ia2X%b9DB6b@*O5@O9NtAB)nt z*P-)}(0KsSc#=!K7m2W55LqCMtrLlzLCw*b{pEz4ao|5xL;EJq`i)IhP3YX0 zQSrID7lRJfso&UW033zRDp0&HLzt#>h*NEyLz;6|$Ke}K$AKlpPCja#-ywF^WrWVd zF%@4_pk53*RAYYUFer59S*SY%F`a|mYC1!5&BRXM4OUki_?Bwe&yCXAsZ^paaMm5J ziqoC_Dmrzr#7@Pa&{>#5Jh_Cib?j<7gVW8>nLe^D{k-^Xj0Kw{`Y-eJI~uXh?}{qE zI7hu0);Twiu+1|lbk1^MF&$5uPBK?b=aA;;B=29e6|KFa8hYDN>)csTiC93#1)Z}? z+_PUP@vgljhLr^dh0c0d%nj)bDpk`N+8mv!M;!DjT6-6x7AH#QuCj{%HVEZEgU%Y8 zdlowJd*PV7%GGo-u+E=DI>Vf5I>VZyvtO$&KSpcssfIS?D4iV{Ol_3JS&!q}#(ad% z$FRhXOf{WzK=E;naqJYT=?t-(iJcj5k4vGo_dzEerSm+3cUMv9ybkMZ%2m@z)WZ_b zy9|o6&T+lU>qWveok6i`I)j>{v*q!V`{2M2R70W(oj)Vddk1u$$*K5ehk7wWxr+tI z_@K~PoAfHr+d3>l{{UhR$9WblQaj|D_uC&qST|Vwv7HFLa(xsrZ>m>cyZl zCWo%e42pF&q`k`1DZ(_J;kjx$qno2M=9bo-aNvikA+Dlyp0Vg%vO?!IrQ+wi)Qdp} z@4%}(qb(7hBu-0tmDd#Q$aD(TbPmfkW1UX>Z+sgEexw?@Sy4JqW$3l1Lg(cYtW%&~ z3_6Fx5>I6q6zk+lUghNyVVcgN5jvyoX6TF<+WICO__1o(I~Aq#$0WU>Q|RF7ck!%E zy%=?+X+<&mqyz z)x8*W4v8U@OK1Qbh0eKf;B!U7*g6q9!<}ZVbJEaOzsG@};3QFuTIU&r@~FUBua;4F zEb7IeGbxYQDKjW^)>~fXRgE#7ShaOV$C{xt{eo^UptVm`!=AY)oj>B7wIn6hc`}dL zhA5phtn=dg&g4z-)1v-ItQ-ot_a0i8nBI)6p9+?EmR{0UWg zi%q?R&Wb-&@G5^TGAMMmz=40t5vJ*kjL;d?oU?k|xb_ho_!$zt37x+nm&$&GqO!qO z4N>d-z35f`QlPHGP`)TlI}@hqjBu-+HL}!F@YS_z-TIY$hia%5PiR&gkZ1r`-_;U5(bhK;0=t={#v;-YbY558rZ8 z>wMxMZ0%|~7bLxkr!h@uj9qP=L!D-mgW>BniY6g{>Aa>T+ST&t7%{go7-E~88;BM8>E)%8m2bZ2bD0Kd0!C5)# zC3IGTo)h>7mqDSku8dIDUe(q)qEJm|TyxeLcTw*r&{_r7X%ahsNn-fr2%Q&mDt?jT zp2a%xZ(xbPB&+G10gJtuBTUno5OLO6yBTL4mCk&K0~>LYXc9Zm!dd4B)_GQ`_$fu| z#jwr~QeNfRG=pND)6>8-Z%ya$D4kq0bOwBJ%8O|2zpCM_Cb9D;oFvAk#X2v*R;Nd- zLvJRo{Ha_`=W1B&g(P9@EH`l0gLI4Q$Qb@B;2-ya*DoD>Gj0NPSU33;9QdVb_#hpP z9fjZ>9XRW+4&B0|UP9}{hdEwFQv@j1xip5-=+KUAoiKKoj?)aCqaW@5HV*tB=#-;$ zyu6B!x5PS6m1rd|^}Kf9bOs!T1HV!YZ#Ypp z&%quONT)Qdr9C9I=-Q0UM)*XL8TBhx8W$IkdtGjxu9uon%#zEKVT%tfuE zGAh2p7CNuPR{u*=F9w}sVF{ICQ0UMK)Yl!tG@S{#YC2AH))~0yoW(fsTh;JRlQQ@O zQhRY(=)8n)ue;QXL1!uGJfRr$>FBkgFKLYFM4UCDIXVYiaP&9Sfoga+7PZdHF%@4P z)SXvSw3ahMXI>7&bi&YtScg_^zM^;3bjC-lb9i&k>OX(}`)I39HT=tp(s?Y838ti2 z=kG~cWf`G!a?-0jmanEm>nZ=Pchq!_h*dl5s8}AFK1Nz#I(?P z)uQ!}5jw{sY+ue)(a|d%U$qF+bSAqII_YNU^z3u+G|;J64WBwuI)8(8R^^1wV>aDf zjnG-0MpEai>Ci919$nlPqgSJRo;TE z%d5O=Gw9PvY(#j!?-Hiz;4aP{xbLlK1gDo zJtK7ROA)N#K#lTKwSNucL$ZaF!dT^JYfHm*$1e zI}WW_qmM!7MCDc9%rGc)Xr8rSl&I?;Km`{Ig6; zsUmb1Td=ZfZ~*Q( zaMs#_SNSYoP3I?Y;9EJuG@YX(u`@T_44wV&N#MA;PAc0c7PU?ztaDRfosU57R}S@J zIO{6JNuv*nb$*^iEz%Sk_B5u2&q&AG z>Y^qOwx7`1ECPf4Pi*ykL1d|60U9Udq!yUYzLjG+Pjtr6c|ig}k$wrJbOCH^)^e|s;ZzwLabOxxbWHhR$a zUz2)I2zm*f(k!u8!AMho`)i55ec|#qnv?P>AL<^Ig;OWKeF9Ja8zZ$BT>AEgtr8cO zz(u$DIr@78`d-xE-pJEqFK`g-?~})iF-jzWK?o|7U0=2kPyzP$j9?#^WWSe^g1v{W z)F8{}$BVxg>_^hLy^m=(z2D19uyR_k=L75uSFpcYvfqbA!JaScCU&HTc9@kUko42v zRv_@#3=T+aQ)C6f$PSpVg~-pbmG>iSU{!1y`{fyf+2^{^4DnpNlNK2QYs!PM-B}bv zoFV&u+50O9>VgbO`VoQH;k9a?S}Oh*M=}HtnTu~jD-@vcCBD6=`wg=o{+A*KRu+*V zOY&N#n_UdbQvoJx)fUC3A4Q;i^Z~L~ZScU}%VY!nrHwi-;(tUBU+C6!Ud(T@B2QTh zTnNBIEo)&eP}w@&=Pfi7M`_CYDuX((tDq9sxuWtt*mNe5SETYySp5!#Z$SV@k*h+XPJS_D|L1a9vr5#v+Gze!C{Fbozb1rIt zBiQx~SqHy+KXcsvH|YoLpfA~YTaxTUv!-9+Ulji8oKMU2ukfSoGp``_;Rh-Q_L-M! z>A|}TuRQQl(CezQUFGbBb$i-AjksTdr?QBB{)caiU>{J1)UOKWYo@-1wJ<}2k4_6Z zTt9CGO)%&`gEnyt#QZP70`*56fA$yrqNT42asaFEnDZ*%I)v3!zoYh{*E!#~XP(wOGOZxuX?TYrBR*ly z|JkKO159#$a9%GZBV2#<0h03r-X6SNHqc+%$T^Qi{^*)8?c-ye=qg-gEh_mrznDe? zT-gpD=in-?uDi-w;!w%?#{F_CF(@f2_bX%SE`@K39Qw6|_jbbB?E1Zv=Iar^L26v% z5S6g%B{~;8G{_(~sp9`g11kp@8pfStSn6vlz>1UvkKx$8lY(*1|FGayzQGZ`-bGIJ zxqlJ3`R9KBl>hzC{gdYn-vQn|PykB4*MoEaw?%p~qkryi+#lbHW?9vShu|LZcJ-}Sk_u@3TRB%sgzjhz&K)93!icCi0NINR%Ue`Cjz*NBzU zeC}`TVB@_$j(_fNY@g=mN$PWd;~w~S5)4Q756=BBILHhiG|v5y!8`JsF8TcZWk#^@ z-2Y!&FdF*k@fd^&7M}aRE(;c%`yo=W;M@Ho zxqk`*zJo28KKCb9yB=&I7@zykv|%?NgQ1U;!Fn({_Go#!vM>uBp8Jh;>MQO);bK^_ zCrX~26_G~z+}~ISuWt=A#Nzm%07Vd!_gvxy<)PZGRPFO*p ze5&d|&&_i%)f9e$I*_>Brmks=t^+5gqeC5KEu&NZ387qk2`>iv-Ez)aQ0}F&F%_Nx zS#B)PPZ`%`ukv4fyRR$-;hQv<04@lf@a@&SKL}{t-%$zq)vT06dggdzEKfwWGW?5Q z(*55MQ-1PSzDWoB6$$$kKJ64>ToA4)dgzGu)54e7O@*J}LiplR;AaRg1(k5cLz8X< zm)k^AzEU3qZcE zL_`DO394pahL{$9Uk)RQRIneKM>#G~7lLWw@%I%@l6pTaJl#aN|JIi!=|DIh5D=c| z;x7#91TMD9+EVgx^~)Y_UFO%YX*rE;iYoqbj(ZQ}EOfla)@7lD&>&SiQd5r__FDqw zqqRzG58v4H9N9pB^+q|z&6>Q|iP4R$w4Cw4fwr+yx4Pz^2%r34YW|uhmp%gy2dHel z6{-1+^+|f_q160+99`G>darR$o4-x6$n&i&{mrlWt#kAMNdJ1Tv5h{?zus$X8{;a^ zHNT_(&9C_|_=TmQ=0kA%pyu~V;n5l}uD;%D9DqGHxc>ECV`rNlMoAx|=3kfgAb>%$ z=I`SO7F_Q^j9@{{ha|zc=Kl`Wt94GWpyorKU}4Q~OOSSKSo1pu7}tDUzBRTh2m6)% z&{_V3eGh@C`5F2f*8DM+*Vrp17}xyu*l&Ptg!bc_pT&NiZQc(xe`#c5U@6S@e+iU! z+tXv9sgKI;DT5^$95fEK_$R1jDX+1wcB(%y&^Rb>21?(I87P>t(?4s~gM-FIl0$p?=r3*51vJs$L9XNo z(*<;SBrjH#{%?6PY{QwW&`n>J?VXGk(4<2zaF7DpU&puP#UW{(372yL9mwDO0y;QD z@3N2rI>0jXqHoE}i$S)T7jai5dZi^Vy1~Ca@{$*WVc;&v1TLUGOZ?gi&Wl47y;p-w zW8_6!%WF(J44Qe-KPgz47l)(;3-e-NfN@@23Ic;OvR_z02UvoIdC|8dSeO@sY{7J1 zBswRNXRctupn1;6Cq7P~*Vs+bUq3G>4tAuLJ~Cl8Zya2bjhrBGe`C)8<4Sst<24@Q zH-ZFNS&ELTyq%Ahkszz=FhO=ck_tvu^>dcp0F(B^^<_Rfsv45w(BK5=<V?o^ELse>zRv!{kYjtA?Z)l;pVu=IP}I7-Z=A=Ei;@hUU?9j=GTj zc&zb79(6k;-6>s!rInAI+5X$6b)3FFY7kAxq+JN@_tL2NRio z?=q^=m%P1`LJ1aP=gm2D*=GdGhfoYddE@c(`(Gv-=&#;b^fxB0hFo+b7lj|VUSl7J zwrQoOI5m{6GhJ+qAICp&EUrcB2B>UjE2^|}-k1(;JgA7ZQ5otfbX*)$pN*aK3~I-* znA9_KI}<3MDy8i|>^)aD(BCSh%eS?@JGzmT9uPydhsS-TnL>1q#M}9l@@Imcv4R+G zd;Es0(Z@jCDptNgOnUJExjUS<7KY&%?uUrJy{uh=u7)6nX}*A?wuenKsML8Vo}MDn z*xg}}8^Mz+GhSoARDdapTDnFY;s%&F^|)F4+)ki;$PO$OQ>=|WY{IouPiyK_dQY*k z*5$(RHD6df{gN$o$Mql#b(-YuK*hhuX3ax$^!91doGkLQmiRKT557HwoMsDjhx@N6 z5vR}s^eCyufzU{xZ-K-j8)xcVfN2X{2|>wXfZ<;%em|_zC%{rurKXPV)Jk#r2G#j+B{Skj0qlZ|q$N zNau+(o#hWs2ACx8`Y-0rAy7V5A-$q~e;VfnpU}_!(x}-Q*K$w)jxx2K)TJc*X+OtrglP}J5t7Sx(_H?pS=}v< zocug^4S{>5EC&O&Nfy63j^la~)E|pnX7>)y&OL);?DnXaSlX3wj z?p?kheJX+SsdDekb?fu$As*EEf0cTWXpu7R7xy>6?}y#v2l{YS_> zSY=VDf=5PhG><}Z>f1Kp?KO^9Dse42ThTWM4yCyr7C$Vn;;)s6TVx?9oqORFB7hpKFk zbf}(7lMQDdhtl*gBzTQS6ltuoJhpR-ogwVAZl)Dv}dP75k zZO>3eqkA>iuUWwNY7R}w#@mu)8ZzNT{EL*=PN2UWziLAp4 z0VW==>)RJo>)|K#_*cl~(Kc<-9^dH3>XDSoQl8thj6tVyYyRj>%W(NymsHuk!gzLj zm&u32;gf(#CdeOy;%O*a@Zz^e?TtQ$sqFr_ zFi_cP!%O_b4X#RuC2@BZt+3M$burrrW}K!|OXN^uVWcU3)X_M+#Gp8BHY6OD3@}9j zJrFiK)D19kTKxSsM-nKXz-bBc{L~WRTJzb3;7N1(d9!B~T6zlUk{hQz3#!9a)=q_@ zIXg#KbmLs|akAokq+6os6l}Mp{ig#q&cwD?^F$-ePPzf!IKpC3H^P}{C#GM-nK&7m z=?MRMvk4jlPbElWoSihuJX7yiJ3C|F@2ulobVPqNeHezw1z&1#))`U8E16&{_V1B4 zKiiQ#iY0@I{ZmXUNW;f-5LXti`m7VjI?=`>?Eq6+#*Wm$y-)lvf$|~2FfjeukvjOw z&Anv<{Uwyc`5;(hnoF2=?HRT6aelIM9!HMAQkk&Y`1v?e(Qr@laZCmeI4?>*&VcB* z{r8Xup_rc*~RJNDpOQd7bV4Xf9rs9|6HKIWreBO6lF5%jrZ=4&K z{6n8ycpTapi;$bU=aV z7^Usf5;e%6nDP=EqY@{;6igYXX@JpM3t0>C5A)J=!5G@ju;3GDZ-zyfw&0fZ_e<_x zlQVHNb2w(d+-PzinfC|H=-z7_i*%*|HESA?qbUxi5QGN}iI2q2%u6S?9y*V815A>8 zpKSv>5GWsC9R1mmI{f|R(`5twB~<4IEx2nOkt0m2JkM>avcMO?$dB;$*sAsm|A}VC zsqEg8>2;#yaD@GFRZ5sdr}hi}LmkOSGt6r)J5p9`^)<4A{_2gQZQ1L6Ha6KPg=^x| zlT*=+ocA;;J6sdd+H$d)1Btok>@^mBj#t@sxgf*+!ZoI(5(i=M!2^j2DY|(nh3oJF zo<5cr;bXCFmP=fW!qweHXq6b0!bLYHCuq_n^Y0l7!9LjU@PfaeUwMzsAxiXqTEMwZ zO#w&!GrkA9Jwj!tIZ**e*($N3ECP-~3?7V}qh7tnaj3kPLk`E_EQj8!#2kW=&_a+s z%Jzx*m3MpwSl-82fWCAeR~C#taI)<+&Tp4o!eA(!_H?z$5H=k>!VVLE}fNtxp$J z_N<&V5ewG6*0(AO=x0Do)pt=<7{00cj_E24N2&U~s*cr0uJ4?a{U}OImOHE(ERT4) z?~lOJQCsgXtL)`L0|v{4Ev<$u_fJ+~nq__Ue#ElX*Rq>VV`jNuNkARTx1rEzgE2$v zHWzmMT|rq7&^Y)$8&^@8^*6SC4lF0At&icPbYai{@)%2X!9~^YYfG!d5*Jy(_Ai*& zZF;|U0_iem+UQrcY&1Wy^fdH7QEhzyH6fb{S_nMZ>Kj+U&_?z7Dohch)}<<}DBt)m z9m_V_Bj_aR$$L{ZJh^1=Wp9DyB(?P~uF75+G+=mg&z$rZvg{P>s4=CzR;t>sDBt*R z$g*8VwtR0-F8OMo2f=c(+WLEB_XVyrV0dybM?mU{J=v~gV(iJiZNa{G@26fuZyT?h zqPG4irm}0((ty!>>p)Z3`@VVEkudK4z_MW9yZ0eqo_Z*HKT2(V93DEeC=D3Bw@(Qe z_CCxqG4B14V88F(d#5i>dK9UsO&YiG-~wTI{?Gp56;Vuq4r@p!M=CztH<_v z1iep#--{~y16LX_dLNt?FzkI;*~D1;0ssHnGf(Wf3cXKPTknPTTuvG_dhc%w81{aE zYhv8{a3$FH*1rE|<8ZZAH$!cGzKrS>&^LPT+uWwCB8_~4EO7tljo!9oh%0wCV#Sjx(J**Iu93A2aMzq3O?|nWqQ=^KWyZi9& zU^H88Eh0xRHW)z=%TSyMdzrk zFXU8qv(a5}KD4D#-8)y&?nwcO5xZ`XCD`}weR8X@CG>u@+WKNaWzUe~@i*)}BPjLc z_g*kDzxSMA-@Eq>kHjBF?cCA}G8dzdX?NMW!FF$vo~$q*Bl3@Hjmw9K$QzE;>ycxmMpFq((_hD)*~ zX}~!7_sjMn>q-KC&)y5F|Azy1qxbo0>vMUP%{$V7;kBUwM!i3*wI3Gf z3>gj0$c}_Dqh8pXKf>ty1=DHww4%}Fv1;p+X_dVyXxX6E&6TD@3O#ZmCc$)|6=FiG zuM#X8Os6Dk)W8FW48vlAx&>c@}!n;#$pYY z*^LvQ1j{9A>r*+Ey{s$^7%ayHSjcirT0o6ymQ(S6{%8y=%@1MBazp?}S)N_X<9lB) z8I9K+2am&+4Vj>Y;A*jcQhhKaV2v`Xf`<=26|8V9Sm@=)l{w}Gq=cJ@J%lSYjYoRJYQ48du|Dol~_##Qf!JyiWz$J~z-WkyLbFn)W(aE>~NB6I0pK3(|lw{+pE)Ftpo9*Ti_VH9jR+)J8Q24DHvf*n!?xp!Yny zR+0t`8;ylp{)9G~8T6zvC3_hA1xJM#+vv!g>>XwKqhyU@az*W!F2> zfWdM_TELLyih!4}RQ0C@yflVys(z(o9?L9GEC?25d3~`4OS{e5)?j%OGQd^Yjg~ZE zusk8aLY9kN0YjF@1qX*LkGIYJnB{Rf!J;gGQmZhZe%X?>V0p6I`cMfh3(|nWazeF@ z@?@ilw(KY@{7Q%ZFO@hdv;Qe z(?#SR&{Fji9094*w=Kd}7fg)L%JZ>>KdrIfI~m$@c1huWj^lVcc@fR>!t+qa# zQQ33RjC_LGnA2>5h!I~Ptt^@tm%8PaiE+xFmKW@MGm4F#giErzQ&e_K8uLSPJpKlZ zmgfWw8KqMu#*7vTq#ekN=9UB$M&GCY7u3R|&ZcU+MrAL8p?;#I6@%8IjDSRoDJ&_3 znAHDyZiq?!KgAMEXtm(Fhcipw-E<-to$BpsW2x+~gU$^`OOn!RXs8o{9YdB&)8>9` zsAGa-zc-_UXDnF(MyGkZ4n*$VD{bO0N(v7dmX`$$dq25kV%+;uB^dQ?&WGHfYSgD= z)XHbk`&w^Tm$J&<8OSs;e^FIWoJhy#r6*!^2l`d@%ZgPPzNz{(X%pkjKQ_RkEVpNB zusrv{`A34~I&asWuFBr$NTUYJlLJgM0zXxMTv@=7<>FKordghxF)?Pj09*JIWqCuY z2FnRwoirXSPxp4UvsL!CvNT|@T;>QEvRqJ&DPlfXc59)E&JCDLynUa-yjlky=ZiJ5joOcL|NpuuY6sn#{`9WHKvz%5{u^>*!p zK>Sfj8a0e}N?E|rc&k!Xm?GnyWLIHD`Nn_gSa$I$SGGi1*1T6er~d}3{0-i&15iHl z=uSSt)!>={3|Ssikli$Sw2>)^qkpc_H?j3)7#ZIqq0BCNdpGU z%c>dSo2tK{Bs+$-yf9UTfhG16NT(39yd*7PHOppJC#*Sak7L1dy|*i#Q`z63Y54>m z-=YKxZFy0l3d0^?l&Qkdl&as5G%;p*UT|zROYieP6l;{8jIw;zs^RgKR$p2)cQ#HoMdWx=8Zc~mZbrb6xkK{;(j88Z6hP1Poc8VOL>6 zzl=8T@$hOn%JTVq4Oi`nx-Muv{8g~rgfk@0*@e6`U<_U7=L95{eARJL(!}^YzM)`ZJb27l zf(fJVGn6Q(9&1K^16t>KyE>pi-jb453|bfG1SDEa;Zi5WWGJ!D4KW!?Y|aVx|3|C) zpp#w$tWPfKHfYp{vWqQgm3rc#c0lUv3I1T0fXf^wtykaGc#3~B9>>Cs<5JbGb#3)|(B_JXqVnhWO)QG#NH&?xG_i7z+Uw?5|^lB7( zX58OXRdcGUqfO%Ty!{8MeEOX8{dQG%b*DQMM(&yWGrC-bM*u)_y-`}Z+?1!P+T{%i zA46TJca2KkyUSbRlv}pTCS9j~k1j99xflC#gG&XBzPv6%P`kW2>SMwsetxK1_U`h^ z7{wL4{3aG~R1EyA|6FwW4;*nkL##+ znqrrMGt9Jk3m-w3moU%9WA`413Yad_1hq?rRP`CumKv%fRca zp-oqALzkB_uQl$MTk}-FaJeBu&~T{&1rsiBpfL3@8S35Oi<5nM6GqF0yDaN$d(KsZ z??acDF|V_WSAmp|uegiI+cL}ZM7bk5!>rGlOwKS@C|2A@KS99$);-pZ-xRu>d5z+b z%*Lsx(MQ)62vAC+fXo>?4xTOV#O|3Mgm+eiqHKDU0%Vw=IBxv zHC*19p{m;D>bQ>qcXU1al8cB_?=+Jx*Sd9KMc+zhdm5wzT#o70=5cg+CG*-R@Uu~d z3K%XoB?xMlYtffn1jBbwZ*|Vc0$r|&QCv}9?r9h_!yNKt-&@h;Rm`g_;FWTO3K%Ze zWC&`PSNfT7xi0F9LzlQ0q)aCJa-&16?4x4F^u|lj<<)p+0Z07qC>1b{imM6)xl4Ie ztV^3r9u+q$R@_JX1@+N>O_tzozR)$y+XqK-y`iqoXg9g0lDvZ2h&><|J(AZuK86uc z@AACKWFK7-CsyP#`0mTFcIOX5m)A1yfHWj;N>Kqlk|Dfysaw=YhPJ8xAeR)wUj*kb;HaW(T=V&~lhRG>mVd=K52Bgh@SQ^27MT^BRiyXXZ% zcce`wrtHwVtjTubI|$tdCKC_eLw7_?CLX?rRwqpM8fHQ0rh;a558p#K7`b&1-$S?L zDNa3n4{cHP_|FUNjPZJFQ#!8hx7b3Pl}6DnxTjqqV9Gl)JZ>fS;u_}FPeF2RWv3TR|{?T$Z!DU4q)>wkWY;m+c_HWqfvnap-a_p5*fAGDigrms{fm zMIQ;5TUDT7!sQx&T$a0BEvH(h3*Co>poM4?m=m}XmdA3Ojb9j8Dd4<75u3q@mSkd=x81D zTHqXgqeBIZ?po_p5_5FuEMYm5SQzul~SkxM*~Qf8cVnaL3=cG)i*unv^r?@_Ltek;~xoUFE3W?a<|o%>k}2U2eb=O9f7e1u|r~ydh0cyIi05G1P_7 zjd35#(mVOeb7fzyb7)PG%iV!j)Lq4V=|%ug>H(Pb7#+~@%Mwd~NQC{^Vy#Ywtei-gIs%2m@ zev)R@y9*}cCuvr_$2A#0NweyoQzqjlX;%FWM$3g?uHbQxY**Z5Z{#@pK1z&E(yY1` z*T{uV(yaOiAA23Ev+A$XI?ng#eb2CU;2Cxrn$dXP^7x_#Vlszg4Vwj|{wvG%~-mnhn@)mrul!N4EN0+YqWWcJcqXczd z?#lU?aQS1#$IvCK{-0|y>GBK3id_cw<+~>YV_sq2tn=gSI5VM zOV7{HrMc+7^wgRnmwS$i1)Oyzb{+j9y1W(7jTQLafSfL@`tl3(AQ$bjI_+Z^!K!Nr zsn0LC4;Bb&mmjO#BA3C}8B0#@wG&-#W?uIwBwx)^QKK(^aS3Xd-#I=eTz(q&F{2dc z+T~YKiYs!tXEX%#<*Z#+BP?+n-t$M7|H@GT!{yHfg4*Tol#dCQpAb@gsQ@;#%dhjq zxl4YptATm(X#CZ91uVA;P>Onz`=)t@9x#y=$DtdJpA)T_G#|8ii38!e#AJMdc=8A!g2WoS`*=&xBq zx>vt+d<=y1gpXkstNtlwGI_Lrhil|g>@x6Zci%d261v=iU+jwGmzIDE7-RoQo}hO5 zdCJEy4d?QLk0~#b>aqV)ttoc-bQkP=~@=q0aqf0!--*Kpb;j&qQpmy0zDe1nnz!#V0&LghL#E94I zmm^l>GI)M(*k|4+=<*)s^-V+a@i-MQTsBZpyKJSDw96JzN)`-VnhR&rW&J#HbXne& z@bV{?4@Z~Vm^U7eo@Z16b-RjH7pSN>QuviHUP1bt^DALi(^4gKM`Et62}LNGGjSzc z(>!Z3aV1>SFk>=tC0x@eWioLkT+=$HS>2UzO^dY2#FcPOs6b3z3D@lFXjb6_KWK{-<5Fie7@wr7hqE8UgixiK$0mTW2`GOR8@>&nk!XCeGE8jjBDf~ z;mxOB~&Tk7YTl=a@|PW$O&FVwV%^ zZmj+3+e-(W7muLJ2bgyV_T{74rbW4INksNhnyZI_pm2`wSdHcSSQc6JA90fjm(_pd zh;f%?J*hlv%hY$#<#z1LEM5(%0_r9{tFci}F5Hp0W~*sJNI2h|;4YiszdBA_pVc(T z)uG}iZozZ+i1b_#b2_gll5kEtw4d7K>G3Kds8 zy5my;`{426&;WG#5Y9R-B%er-km0hvV!~0HkJ@ihg4$($l`L46BIK)fxsOY0ie1ji z1h{lpEI9{VKFqw45lFrip#p}>ZVD=wHN6WIs9nZ#J{IV*ZfN4QmokJiTMDRO&atViY^~T zmjKEC$mi2ccB(1;&=O+TCvLys}9Kkk=1 z(p123*)Bm)yTp62bql$q_xx2bbZIV}Nta!7#EV^?;s*3(rw@AX!m^Juyb}S*C!0Qe zk8)W&l4s=tMzY(^mN%oLCz;nLkB(FUVI+Br>4Gk-t{C>u5G0rMp1=Nmmz{ks%Q`9+Y(6r9QvbvmrU1!Y zL>o{?MJ!H`JCa95x0K1`J~+@dncN54=ZKYkRGjo&1^*&Kj(PZV)X8Vj9WBaHhZrI4 zsDH*}($S!-$)uz14zaQwojq^%Tj=Ot%o~O?$MZl1%;U5`P&;ayHkowPg^(Cs>8N9b zVA+nkY-#llI(mkAL-7cB!KDI*qYfE@+EK@p$)uz1S(8ae-PG0yM~?(QbnbZBi8dN} z7N`C+8c})bp);%LXh8YUnbmYjn4(*OPYzx3CX_+bX8rdQHbz;JX7j)`2fqa$-Bla9t@OeP&o ziV!Q?QDs$lBRYD4c?TsRxlW8dfmlq@$zMCYJ5UO0@b89lglB zLD)z9eg-XS8gkTjYDa^Wl6EwjGL3`&2o+bhqxlaFZH10r!kZ3xbd*z7^`1RO+0>54 z7AR0V8bZi$G$}=}Y)4DeV+W(7mzg&p1<5xPRKOUuaV|ma$Vr(@j@oFI%;V&!9UP}P z?nwU)Gpsr*=z{sA9{u>kzyC1rFx-!RpnQB)C*8wcqFhN{z>EVQQ|}}daaoGcOwLgw z99mQC^7?$hW!8X;XD>pR|7G4$IDPA( z(d8@5!~g#y`4#2kt2zQkIYhZ5d1)|SdEiWr?om-QPLA$y<=@|LEch|`QhPFf-!Swl z_FEK^yHo+A-;O3BdHIy)XBMYGkot|)3`zJ{md6c?m`slDB$exT39D`j`Z%=oi80@z zONJNGaY%lUqoRh(A$fwrQJSkC8TT>ZEbjPNmfp!%o-17*5v4U{k8Ype&wdGA0-lv3 zko-JG1&q->I7g5x$rZses{f z1nS8}yF4WCW56998uu~GLY6a`bU8t>Vwd*>?Soan_T}e_*O_;41tdRBQBlL?A&P02 zhs6jACR~m}Uvd#lxI8RlGU;+goLI5T`+`RN)KPuLqRTh%BRN2Fk4ps%moqa2wae*I z9}_N5$orV`EGf^GE@wLw=Xbf6pSP{|^vQS=AoM2AgDxb0rhI%==adr^B$o&L?y{`w-ZL8=vKyt|!t0e7B)`a00poZ+Btej?%j5Y>*JSc|J~?MHc|0Gl zyq4{#U%1a}=;&?S2l05$s{)3jQ&XmrbTmI=GU>?mIhT&+Qds$)4UX$@ZUc1m4)c!8 zK(Z#LD(EwsneabjinQL@9L7tztX%p0A8Nbpmua>!DMxPlrdRdALWUa?Woc4$xG4E2h1BA z$E(aV6)+r~2?VvHxp|XGM{^S zxD=>IZJN)ybTlO#gal>m$5#0+9SHLRCy#1%lebaR#gV4pGfXX){jR zninTVwo3lB@PSR5<5Sqs|KZSKN4@J(0rgi)tY*4TNeq6c3tT9V%+5DXV}cwfc!*GO0c} zO{{EnXTYc=s(;SBaj5=YiV7I&r(_6f^#zW}q8GC&m~RFx3B{px*XNT?*9d=jVu(t=_aY z`X5yPig`Wx5f`BXhWdqBf?7S9GMVi83lu9`z24KyQ8Dy2K6{T~&pTAqP+z7jY4wF^ z3e?-af>8MvTSG@r=!ELK@aa|zlHaCOg$n#+^+t?;*tyUlsMS~E8o6loB~fB!Z~HN` zPuq&>-!N|`9`Ek}6)?8F$|b1PFDRHy_WW5nVr8o@oHb-6s(;J8Q}TH0Buxbj^~DZB zt-dT}GO7NL46(A+hhKCI-}e78@60&ffKVN3s9zAFs#<-i3e-KnB0+IwtM{F-xDBd* z$Gl@5yh-Cw0Ym+=EJ3ZF$e2uS`(hPWwtDlYLw!;Gd*&rvNdBk_80r_LO(i+otjL>8 zs-LHl%T_-jUhiU5FEDRm8j@c}si>iTwqknQ7bOVlo=>^NxVpai$#w_+Qox8&W6nYK zA8@b3asMz*1&j}>DImy|wx;<}xQLMYpvr2_a|nvKERVY+Vlw%0`s@U;vioS_7-to_ z{E>NcafJR4EzqLog(@JV`{<&m$?A^GII*(ToBVjlCRE?eyyGKy%b`F8%n`~H)avIe zCC;S!We&xatsa>@_ytto!@Se+*!Vn01q}6N%92(;=P%S(B`CRU^>I)4zZca#=A9hF zV@8P{XJWKGnLKI*6+-llg2xfQL19tx++6Z+q#7io+y>AJV72OCy1+4 z#QvVG7Pb5H3E~f&AhLKf(4{Jdtqn1P+SZ!5W@PJzsAgpA7S)4)&(eJ;xuSA@p5z&!o9tK_i=M1WK8C_>`uc`J&YH)I0bx`p#sKb)|EMeTwPvfW&8~I zCDm>CuUtf2mfmS5FSBlq(V8Nc7q<>_S^xRYBhY0%9JMr5HIGmM!{rrYEkR>Z?_pR$rYUShjl8%19NeH(=grQK$;Vseqxr zCPz@K-{zW3Zu{*Hv9i^V=+rWc>J6FaMxaXn{fwc$IYL#n`sHbpN%i#!Vr8q(`K)R= zsyAX@JPuV&9V%d`Ul${&)vwE#OscO<5i480N4)YpRNser6H`#tRuwSRZ_iRyt-iKk zGO4~!#c_3G{>Qpjn&+n_c8Rs zYO)cN$s_Z=I5E*jkEH_thmE#P$32VY8sk+uKvgrB^2B8SsSsG}6Ziz*v6`o16sQe9 zlqW|2!v?E)v_Pzsk)^3FccGCccmoILuW*9$3?mQ6335?sRV$7%|;l_bXP)$oS8O?}J8~;k8u- z?mz{qWf*x7W#pobJP|dS?73`;m^Sioj#w!pE8iKzhbw{;93EyBD$g*2pN8ue!-&tE zH1c$W;G&{ANXu{;4fg$f4=!>bkv-AC*Y)4AE>CY1Kq8l9*;Zxj#Pw97jao# zinlnEJJ1%jqEvUadS=>GG}i*pMp>w86IF@))2Tf0@6Qm_-L)lQGTB{^xx|d_N)an% zWXAShFQJi^*h_h+il{te-0q4{F>U0Ln8~D(M>52;ksZqL-i>TZ4O`cEHyUZhyklZ` zyemy))Fasf32-ByVriV>Qp8FL%z1K542!kKr-22$M9WZ~A#hKYpceS2ORSVYlQsjc z#bRxkcbtn?70^1eT0#9Wqu#`ae z_`FlGSUWu1N1&<+rQxgUq6ecywZKDaQ%eaPIlbpBEY_ZRQ=>QrX{u!iJnj(G0y_xF zCpv+b1e;Qwr<}wEIxue*3be?nM7;(71cF*%s|qZ&1t;G*;|CPzh+B}wb61{f8C$ST zZI%{zJWGM41g0N);QLst6Z58}psI6}@(h7HGX%9ju55v}caD4xi*;t+JQS$!P%T5? zt^z?V@Iu)FGuEE44U0wbwsi)o8mL-^z`cn-3p}G(sV*A#Ym57_SQi{*9D@cf)iMNL z%MsLD@Il#I&}Q0zHdw4H^G>_|F z3n(y@VraKw7~m{l@jQ= z;5a^2^kd%AC>{rSs$~eg7$v9$m|~>_5^o%N8WxK&?+V<4_A#nu2)yAE)B<>6UAL4H zsC37?hQ<0bZ>nyf!Fjz-+!u=tV&0Y5MIS4(hQPlIR7?x( zRDpXJ*zQcIJ+u~!4QAdN+>5?cW(@&l);OcR>5ynCfy2kx{MvK~^DaxHfHG?curw9Z zTkukzSSf+ZZcSQYv4fen8U;RdD9;dhRY5KAR+Iuu2`rs`XnQO+lzA(0kUz;&o*@7V zYJu0{6j(}NhBK`{78}OA%W(|8N>QFEkRYf9K5&SY5}5GSv`$!TIPMi(01(p&R6Yg*W7IW~F znSrW5s1&}cLH;aCR118OBUVbFazmT#SnP1-Ey+XGZ*j^q1Zsew7TBF9R!X4lV<$e2 z#YQnNg=6q@it-GBZxaNyz?T_fr35axJHjWsBXBp(K(bMk@(h75V+6H;{z614fpbUp z-;BjZ;~?X+tTw8aA@F_b&jO#QZYw3Q|IXQ0V6h`{F3Li(i|P$SAg@&Q7U)TUW)?b@%x3?MctG!V+;N-PQ~;V{7*S4 zwFRN=^Kp(2ABE=w+)dkMsg@z|gMwNhpP|4~0_T5pB<6>Y#xVd$TFR^;@L8IQX@QR; z#7YUAe)oJV8lJ$sYx9t79;G}(;0K4G7Wk?_tdzj=R}bfp?RhOcTit#ycMfp3&37toIc;L=-zescBPb<3{As>k3p zB<@a?IVx&A5~xlQbw}YQ@lHc|UDA>f$l{N;l5D zORzses(}7!%NqWKKrYqb6*o|PmTiBkG$9H!m4uN?2R1H{SK?jMgO$rhf&Swr!99UO!hivv6>Il zn)$|h)rmpReFslDX$JPZ+9f`Iwv^e@>Wja{v7)YBDiD z);7wUOwNzL6-*}P$J!7faa@Y|v9=`;RP$qPyWQ^la!K#`t6=ETT*zfHlYQABOB`L6cXS`$ zu30~HISX%Mq04#^Dxi<<+Ilg9TwNaB`#B~PM|W+*sL909U0bON@?3dzSEkH3adg)< za7-qT?nZ=+qq~{G>VDX}wsC==y85YYmLR5&?oM&d=;%IB<*Fa{u5BIFab@=6lI^1= zVlSS^yd=(%4JjXA>;9u4R@*m1RQF;xLShSLFZN0k;AU^|&kgp;x`)4MPm;+O^rtBkT)`Xd7q05u-#&s5w zonutM80(lrP>*$Y708(!>wc~oC&#*nkIAv_oiO9%SRWWMnH=kGd6UVp?iJOH#@fo6 zOr8(h0Wm$+z4MyUSac|PoCXci?}HJm9$%mtZftcrPP{*FI?yGRC@3oS+y( z3}LmMaz2K-to8su%W~GmHRI%1w^Izq+V}*!mpQyaEXl8ZPG;Vvcs^{7rD;*;L%jo# zOA6tyf}u-u5zHvX*KsCYc6IoBzLf2hxlI|Rukj&9t?Fpbsr$@!S_BB}1n4pE9LavA(9 zY)AjNA0P2K_|yo`hYizIz;M|EJ;+77?3?m2;WDOti8y@6YPoj-F{wJZ! z({aRec(*UAD(L+(nj)xOMhiZME?I3`e_WQcHhD8ny6mF1$?tM6pB2wID#Guo&c(jW zV_#xvTGY{VM1+ubc|^*`l&++E@5=!R$}M&o_@6ADf6=_((d9gRf)ItIK2VGiKUi7U zE)P+@1jBc%*2$Cl-d*-jQyh0$*6(y3c4yn?(d8NV+}nX<2bT&McLJgjf?Rz^mODBW z|CI}8;!Z&Az_`i8oq*a=F=A!++o0!X-Hnds<6VCjuPIzAVD#JJIf9};(%jJy6(|^R zHYnqZ%hEgf%H!ldI5bLYM87?f3H)DeXRfgEBW(Cg=G~Hkqi5FwRjer$4=J4Hx*tpPX@kQf2p33n{ z85;qT*QBW`ALF|JrP#h9YS6k}2CR%rG+YrvU;6g?UM8+1Zf~$1D=%W+9eA*{&QJ+s ztOged>ajX3>SJm%B^7a5iqK5%QR8y7rqr%Iw#TH`(cD@16`KOyRd*@R*tLf!X>D#; zLI>jYJw~wFqY5UIM)*@6xrotO;`&EtN#@U^GylDoU2t^p`yhAcgGQ&GD$8#z$pad! z4NjdFUXq1ExHGJXsy{JGW&HaiI53q4NGn zz{zy(fZ40DLlex~jD_0+l`uy8Naa&^=-31W3WjN{c6`jovh+^A@;KSa<1@6zKYy^` z%lbw0=HZRiaFThCWFgr}6);?mQc$}**dZnDa%kGe&?T$I3&^@fyF4mFtk`AX<&)K? z(+TLZ3XdGXk8n9EV7NTYua56n?Qj)HE_I^3gx`uT%|*K$oFeXb3718JZgWi@+I=Rv zT+F;JE+qGLsep2+L7lqtEZ6*fmm^|Sle^s8f5<*Af9_9cZVB@q#G|Qkit>!(dstpW z`mBC<+{b`->xhiW9OgZYYQ_}bh#%f3C$QJ7{wgI@(U2##%JLfFrOeBwf|3r$ zRJqh8wUJ57n71A~_^*{l#fy?!h$`W8@${VzN}BU0r2?-KJ`X3xcu>-D(ITbhGHE&U zZi)sa%_>f68Ru2PE0}kCVA7NnkKs#QN3<4x!{;+E6AMy0Jtk9BQY+vfypnl$<${uC z3pYHjPN}V^625?W_XgUV=kf%;)FrjZ@;BiW^R@>nO)2mgzR=(Te-pkCw<$2mjqn)0 z)Frh_@HgR$a8C~$+~d+bhA(wV%>@XrV&1L!ppH1TIH`q9x|n%47lM+G&j}f=WB~`^ ze=zU*R8Z1M86LwI>WCPB6TXCb>mor(6SF*qFLg<_RJxRT4<&+<+?2@BNp0dBgfGL{ zG;o_v7KM2nDJ4YG<+w*=gOnzvc?@6blG;k8D{ziT2PMsPM21eXMV0WC%-ax{bebs4 z6T@<1X&Di3u43MOPLR@xJVY#%1pHn2YUbVV1|=Pvl_^T8Z9*hngNJ)yM@)_tCAEr( zq-)V01Sy^Lr=++@N;7X$;BGWKSESTBE0R{@XMs$R(%eFEl8_Fs!9yb+lr$w$oRk(y z*WuwF3rd;?lvKAzSaFfGmU&wPw`p3wD5*nCBwdf=R0vW!AySmoIU$nPG4Ia6jyPVp z5pi-iYFiL*ZorSBkszg|4v*nW-EP!DCauT0JR6jBwumv3+DF8j8}X_k9+Z@Dcnn|a zl-k9`n+^L+c{!fImpY}6G4W<2^KOU**;^=LjHC_`@#bdi z@<>q9(kzeR3-z7=;Z1mc3RF7B6&X6I6L1i|1uw3nK}rkaMM)h62xoAcazRO{d{I(o znRF}j9(96}F3J=ob&^S&aSE#lN?IN(N{S{p2;YWE5R`Owq$sJg0O8x2_m~@$RFyAE zYM169dwedYAfyCi%I#Qqy;%jsym+ACpZY-$Gjc6prnNvN~)WdJ4vPc znfF3EDCq(bBZ|vCqPNnLMm-%-qRI9Nf*T^ zizXHjN)Iyc*-TKb1qNMI|k@P4Y8o8jPYZ66CJp~9qhV}xLu8vX?-y`tej{FE$5$gNSire@qu!cGY zKK7GV!;yx-IwWFXtNUTUAP$3dc;3J*-LXl;^}rgHGqAmFPzS`7V4WH@@FKhKP{j4Y zI-y|TUeEM+A8`Y)PRSa$RlClQA#MoP^q7HX{Ji2A#Erl@*)?#R?FZl^j*5N2nwv6k z>)|a{Bin}IdW#6xx-GY4@5Ynx8aSvz$s;^tuCT0J_}x`v-1ZUNS;w1HUA38 zmSDLB1GjFKJP>g!ERxqaJba{>w_AfXGi%`Z&TgEy0qa;}qLu}ws zuVqtyL);O2utG;;;^C>g>)gD7_gORLd&K*LHQ%g#SamnvRo%c^W{gg_{m{l2B0d1D z6=v33!xqe~kGL;bs|;M( zr0c}Si2H$c4(QsIjh_*psA5>8VBn@Rmi>y+{jmqr1|B%C`SpkgfOTfxz-{N9_YUHL zD48;F<6o_N5f1|EeAmF!_Z)$=VlWO`g@Jp`8PWvt5R5hqhR>NW`BlURV{}4Cho)~^ zcsk;tV4dM;9B#48jv*cf)&)@mS4Pg>iFi0zRYsBUSo`R8h)006C}KoUo-QOuf|W9( zm+k7`45JSLYjNC&K6*}zRfrG8A}IrRUb6pvhz|qnVlc3~Z~vnaJLo%W;4vd-3`Bf5 zSZ5j0q0Sw;@*`~&ST{xSwW8t(u-3}fXs|BJaa3_6vb1Q80qY-G(HaZZx}0c@1MAX+ zXpILe9TTmiz`8-Ujs|N}Mz9HBT`pS_!Me&3Y!Xau=p;3%VcaNL~9CI zSENL1Dp)tVqIE1-H^)WmIIuR#xM|oDsN#6Au92>K$_6Rhny!4`mZABfgM%!r8ABCsBj zac6;bdt9&tSWm=6D+$(ZqES(WmD8fR7_2P?(OLr54%s>ztjBYLorCTpqO}xr6QZ>Y z<0Ly5tUEG-orh{U(OM4Hldfp3z>K_Toe$OnGIu3zr6bq{s4J_az~T?LaJdkyyV9a{ z5m>L}MQasUxwvRu3>L_Ye}MH?MzBk;6%(yX!FpB3T?W=OGVXG$k`QaJ0E@|tE5UkR zva7&)F(%et4c2R}Xk7!=KjqqMk%3@ouwIsHSA+GeWNW~BsUX%~2i9|rXsre74biB$ z9;}^N(Oif1@}hMEW<*45Jy`F!qIDy>iiy?+uwGA#)=gL?AzB;Jsc2N(4Ay@f(cFYj z%nG7)3s`UFL@NW~^sDr2;N@fc25AvIVR!9l^GO z^<7r9?gZ#MYA-4E98h-hW8 z3W(MNVC~9@)^@PIa7F7uuw;>nhrs$KCfLJZeVY=kN6>R#v>pZPec5^ptRHfMJr34~ zGUEwkalv+=t}OT@W+ViA3b#mRJdInP66~K~eVi7p99W;qwg1Ac%n0@jSii}&&w^bM z6YM!;QPKK0*!AD>uaz(WJGHh z*j*B$^$pkuMn&seWO>p0AJ|=G?ss6f6R6^Qj7y7V0qp%_qV)sVtz_Jf=r1eSZm?U( zxIJKZiwNdns~}p{VE4$2Rt>sJiB>Jxom|oS3G4$vw0;J=jm-E39pnZ371eU0^&8mT zv!eAo*u7$+^#|CN%Uk#r2fKY-v_jZJj%bC!9wjnD^}z0*5v&sIetFTVkFA7gH2`}+ zM6?=$J+>fPjldqw8x^5_aIIwff*p$s))?33MXL$eN9IIpKd{GSM5`&-hsjnmupL=B z0`|c&w>ehHiMSS6B_UcZ!9Ls-tyY*D6Rp-@k4%eJ8?cAVwHDY1Wd*ar9wb|B!5%E* z+JQZUudE2Q$5ukLI$$n{R!4M@6Rl3Tl@ZbE4E6{|w4%sTqSXcLBch_!73`B_Yk#n3 zJA!osdqPgM4gmXvyl8a?dq!Ne4g~v@jA-=$`{=xA^#nWah*mGKk4lSHZ?N5jX!Qa6 z*oWwv33x)a-uaD>qSIs z2)fUT*1?#Y5v`$MA6F2qVHhV{!@(Xe<3@meYD%mfi7mPI5Zoe;Dnf^XJtZ$%hk-pk zEm{uPQ*)wqIJ%06)+n%-$<`5IugnNG8ti0Bw2lP({G4cw0sCB6w8nzHC@)&$z&;}; zTH~=wL9~tn`<%FF9S!zrS<#w+_2k-#V4o$|P6B&wLaaRo>=nFG5sG7OPP8V2y)Z3W zQ!qoasi>9_>{zhpM?~v5u$M zlM}7e!M@fJt+`-d92c#5*vg648DMY7h}L|}m6gu~d!sAZ0hi`GK0SIgESu-B$I z3onLxBci-jc^ZT^M?~u@R$UNP>OaJ)e;2JrkF%Qp#rfJsf3Vv6z+3waW3^3WYYcw1 Tl%tA$X0h51Y0)|nS>pcz?%_?1 literal 0 HcmV?d00001 diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.p2t b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.p2t new file mode 100644 index 0000000..16daf53 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.p2t @@ -0,0 +1,9 @@ +-w +-l 5 +-i 6 +-n 1 +-t 1 +-s 1 +-c 0 +-e 0 +-exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.p3t b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.p3t new file mode 100644 index 0000000..221332e --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.p3t @@ -0,0 +1,5 @@ +-rem +-distrce +-log "RAM2GS_LCMXO640C_impl1.log" +-o "RAM2GS_LCMXO640C_impl1.csv" +-pr "RAM2GS_LCMXO640C_impl1.prf" diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pad b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pad new file mode 100644 index 0000000..124dd5c --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pad @@ -0,0 +1,353 @@ +PAD Specification File +*************************** + +PART TYPE: LCMXO640C +Performance Grade: 3 +PACKAGE: TQFP100 +Package Status: Final Version 1.17 + +Tue Aug 15 05:03:28 2023 + +Pinout by Port Name: ++-----------+----------+---------------+-------+------------------------------+ +| Port Name | Pin/Bank | Buffer Type | Site | Properties | ++-----------+----------+---------------+-------+------------------------------+ +| CROW[0] | 32/2 | LVCMOS33_IN | PB4C | SLEW:FAST PULL:UP | +| CROW[1] | 34/2 | LVCMOS33_IN | PB4E | SLEW:FAST PULL:UP | +| Din[0] | 21/3 | LVCMOS33_IN | PL10C | SLEW:FAST PULL:UP | +| Din[1] | 15/3 | LVCMOS33_IN | PL7B | SLEW:FAST PULL:UP | +| Din[2] | 14/3 | LVCMOS33_IN | PL5B | SLEW:FAST PULL:UP | +| Din[3] | 16/3 | LVCMOS33_IN | PL8C | SLEW:FAST PULL:UP | +| Din[4] | 18/3 | LVCMOS33_IN | PL9A | SLEW:FAST PULL:UP | +| Din[5] | 17/3 | LVCMOS33_IN | PL8D | SLEW:FAST PULL:UP | +| Din[6] | 20/3 | LVCMOS33_IN | PL10A | SLEW:FAST PULL:UP | +| Din[7] | 19/3 | LVCMOS33_IN | PL9C | SLEW:FAST PULL:UP | +| Dout[0] | 1/3 | LVCMOS33_OUT | PL2A | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[1] | 7/3 | LVCMOS33_OUT | PL3C | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[2] | 8/3 | LVCMOS33_OUT | PL3D | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[3] | 6/3 | LVCMOS33_OUT | PL3B | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[4] | 4/3 | LVCMOS33_OUT | PL2D | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[5] | 5/3 | LVCMOS33_OUT | PL3A | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[6] | 2/3 | LVCMOS33_OUT | PL2C | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[7] | 3/3 | LVCMOS33_OUT | PL2B | DRIVE:8mA SLEW:FAST PULL:UP | +| LED | 57/1 | LVCMOS33_OUT | PR10B | DRIVE:8mA SLEW:FAST PULL:UP | +| MAin[0] | 23/3 | LVCMOS33_IN | PL11C | SLEW:FAST PULL:UP | +| MAin[1] | 38/2 | LVCMOS33_IN | PB6B | SLEW:FAST PULL:UP | +| MAin[2] | 37/2 | LVCMOS33_IN | PB5D | SLEW:FAST PULL:UP | +| MAin[3] | 47/2 | LVCMOS33_IN | PB9C | SLEW:FAST PULL:UP | +| MAin[4] | 46/2 | LVCMOS33_IN | PB9A | SLEW:FAST PULL:UP | +| MAin[5] | 45/2 | LVCMOS33_IN | PB8D | SLEW:FAST PULL:UP | +| MAin[6] | 49/2 | LVCMOS33_IN | PB9D | SLEW:FAST PULL:UP | +| MAin[7] | 44/2 | LVCMOS33_IN | PB8C | SLEW:FAST PULL:UP | +| MAin[8] | 50/2 | LVCMOS33_IN | PB9F | SLEW:FAST PULL:UP | +| MAin[9] | 51/1 | LVCMOS33_IN | PR11D | SLEW:FAST PULL:UP | +| PHI2 | 39/2 | LVCMOS33_IN | PB6C | SLEW:FAST PULL:UP | +| RA[0] | 98/0 | LVCMOS33_OUT | PT2B | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[10] | 87/0 | LVCMOS33_OUT | PT5A | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[11] | 79/0 | LVCMOS33_OUT | PT9A | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[1] | 89/0 | LVCMOS33_OUT | PT4F | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[2] | 94/0 | LVCMOS33_OUT | PT3B | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[3] | 97/0 | LVCMOS33_OUT | PT2E | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[4] | 99/0 | LVCMOS33_OUT | PT2C | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[5] | 95/0 | LVCMOS33_OUT | PT3A | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[6] | 91/0 | LVCMOS33_OUT | PT3F | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[7] | 100/0 | LVCMOS33_OUT | PT2A | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[8] | 96/0 | LVCMOS33_OUT | PT2F | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[9] | 85/0 | LVCMOS33_OUT | PT6B | DRIVE:8mA SLEW:FAST PULL:UP | +| RBA[0] | 63/1 | LVCMOS33_OUT | PR7B | DRIVE:8mA SLEW:FAST PULL:UP | +| RBA[1] | 83/0 | LVCMOS33_OUT | PT7A | DRIVE:8mA SLEW:FAST PULL:UP | +| RCKE | 82/0 | LVCMOS33_OUT | PT7E | DRIVE:8mA SLEW:FAST PULL:UP | +| RCLK | 86/0 | LVCMOS33_IN | PT5B | SLEW:FAST PULL:UP | +| RDQMH | 76/0 | LVCMOS33_OUT | PT9F | DRIVE:8mA SLEW:FAST PULL:UP | +| RDQML | 61/1 | LVCMOS33_OUT | PR9B | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[0] | 64/1 | LVCMOS33_BIDI | PR6C | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[1] | 65/1 | LVCMOS33_BIDI | PR6B | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[2] | 66/1 | LVCMOS33_BIDI | PR5D | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[3] | 67/1 | LVCMOS33_BIDI | PR5B | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[4] | 68/1 | LVCMOS33_BIDI | PR4D | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[5] | 69/1 | LVCMOS33_BIDI | PR4B | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[6] | 70/1 | LVCMOS33_BIDI | PR3D | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[7] | 71/1 | LVCMOS33_BIDI | PR3B | DRIVE:8mA SLEW:FAST PULL:UP | +| UFMCLK | 58/1 | LVCMOS33_OUT | PR10A | DRIVE:8mA SLEW:FAST PULL:UP | +| UFMSDI | 56/1 | LVCMOS33_OUT | PR10C | DRIVE:8mA SLEW:FAST PULL:UP | +| UFMSDO | 55/1 | LVCMOS33_IN | PR10D | SLEW:FAST PULL:UP | +| nCCAS | 27/2 | LVCMOS33_IN | PB2C | SLEW:FAST PULL:UP | +| nCRAS | 43/2 | LVCMOS33_IN | PB8B | SLEW:FAST PULL:UP | +| nFWE | 22/3 | LVCMOS33_IN | PL11A | SLEW:FAST PULL:UP | +| nRCAS | 78/0 | LVCMOS33_OUT | PT9C | DRIVE:8mA SLEW:FAST PULL:UP | +| nRCS | 77/0 | LVCMOS33_OUT | PT9E | DRIVE:8mA SLEW:FAST PULL:UP | +| nRRAS | 73/1 | LVCMOS33_OUT | PR2B | DRIVE:8mA SLEW:FAST PULL:UP | +| nRWE | 72/1 | LVCMOS33_OUT | PR2D | DRIVE:8mA SLEW:FAST PULL:UP | +| nUFMCS | 53/1 | LVCMOS33_OUT | PR11C | DRIVE:8mA SLEW:FAST PULL:UP | ++-----------+----------+---------------+-------+------------------------------+ + +Vccio by Bank: ++------+-------+ +| Bank | Vccio | ++------+-------+ +| 0 | 3.3V | +| 1 | 3.3V | +| 2 | | +| 3 | 3.3V | ++------+-------+ + +Vref by Bank: ++------+-----+-----------------+---------+ +| Vref | Pin | Bank # / Vref # | Load(s) | ++------+-----+-----------------+---------+ ++------+-----+-----------------+---------+ + +Pinout by Pin Number: ++----------+---------------------+------------+---------------+-------+---------------+ +| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | ++----------+---------------------+------------+---------------+-------+---------------+ +| 1/3 | Dout[0] | LOCATED | LVCMOS33_OUT | PL2A | | +| 2/3 | Dout[6] | LOCATED | LVCMOS33_OUT | PL2C | | +| 3/3 | Dout[7] | LOCATED | LVCMOS33_OUT | PL2B | | +| 4/3 | Dout[4] | LOCATED | LVCMOS33_OUT | PL2D | | +| 5/3 | Dout[5] | LOCATED | LVCMOS33_OUT | PL3A | | +| 6/3 | Dout[3] | LOCATED | LVCMOS33_OUT | PL3B | | +| 7/3 | Dout[1] | LOCATED | LVCMOS33_OUT | PL3C | | +| 8/3 | Dout[2] | LOCATED | LVCMOS33_OUT | PL3D | | +| 9/3 | unused, PULL:UP | | | PL4A | | +| 11/3 | unused, PULL:UP | | | PL4C | | +| 13/3 | unused, PULL:UP | | | PL4D | | +| 14/3 | Din[2] | LOCATED | LVCMOS33_IN | PL5B | GSR_PADN | +| 15/3 | Din[1] | LOCATED | LVCMOS33_IN | PL7B | | +| 16/3 | Din[3] | LOCATED | LVCMOS33_IN | PL8C | TSALLPAD | +| 17/3 | Din[5] | LOCATED | LVCMOS33_IN | PL8D | | +| 18/3 | Din[4] | LOCATED | LVCMOS33_IN | PL9A | | +| 19/3 | Din[7] | LOCATED | LVCMOS33_IN | PL9C | | +| 20/3 | Din[6] | LOCATED | LVCMOS33_IN | PL10A | | +| 21/3 | Din[0] | LOCATED | LVCMOS33_IN | PL10C | | +| 22/3 | nFWE | LOCATED | LVCMOS33_IN | PL11A | | +| 23/3 | MAin[0] | LOCATED | LVCMOS33_IN | PL11C | | +| 27/2 | nCCAS | LOCATED | LVCMOS33_IN | PB2C | | +| 32/2 | CROW[0] | LOCATED | LVCMOS33_IN | PB4C | | +| 34/2 | CROW[1] | LOCATED | LVCMOS33_IN | PB4E | | +| 36/2 | unused, PULL:UP | | | PB5B | PCLKT2_1 | +| 37/2 | MAin[2] | LOCATED | LVCMOS33_IN | PB5D | | +| 38/2 | MAin[1] | LOCATED | LVCMOS33_IN | PB6B | PCLKT2_0 | +| 39/2 | PHI2 | LOCATED | LVCMOS33_IN | PB6C | | +| 43/2 | nCRAS | LOCATED | LVCMOS33_IN | PB8B | | +| 44/2 | MAin[7] | LOCATED | LVCMOS33_IN | PB8C | | +| 45/2 | MAin[5] | LOCATED | LVCMOS33_IN | PB8D | | +| 46/2 | MAin[4] | LOCATED | LVCMOS33_IN | PB9A | | +| 47/2 | MAin[3] | LOCATED | LVCMOS33_IN | PB9C | | +| 49/2 | MAin[6] | LOCATED | LVCMOS33_IN | PB9D | | +| 50/2 | MAin[8] | LOCATED | LVCMOS33_IN | PB9F | | +| 51/1 | MAin[9] | LOCATED | LVCMOS33_IN | PR11D | | +| 52/1 | unused, PULL:UP | | | PR11B | | +| 53/1 | nUFMCS | LOCATED | LVCMOS33_OUT | PR11C | | +| 54/1 | unused, PULL:UP | | | PR11A | | +| 55/1 | UFMSDO | LOCATED | LVCMOS33_IN | PR10D | | +| 56/1 | UFMSDI | LOCATED | LVCMOS33_OUT | PR10C | | +| 57/1 | LED | LOCATED | LVCMOS33_OUT | PR10B | | +| 58/1 | UFMCLK | LOCATED | LVCMOS33_OUT | PR10A | | +| 59/1 | unused, PULL:UP | | | PR9D | | +| 61/1 | RDQML | LOCATED | LVCMOS33_OUT | PR9B | | +| 63/1 | RBA[0] | LOCATED | LVCMOS33_OUT | PR7B | | +| 64/1 | RD[0] | LOCATED | LVCMOS33_BIDI | PR6C | | +| 65/1 | RD[1] | LOCATED | LVCMOS33_BIDI | PR6B | | +| 66/1 | RD[2] | LOCATED | LVCMOS33_BIDI | PR5D | | +| 67/1 | RD[3] | LOCATED | LVCMOS33_BIDI | PR5B | | +| 68/1 | RD[4] | LOCATED | LVCMOS33_BIDI | PR4D | | +| 69/1 | RD[5] | LOCATED | LVCMOS33_BIDI | PR4B | | +| 70/1 | RD[6] | LOCATED | LVCMOS33_BIDI | PR3D | | +| 71/1 | RD[7] | LOCATED | LVCMOS33_BIDI | PR3B | | +| 72/1 | nRWE | LOCATED | LVCMOS33_OUT | PR2D | | +| 73/1 | nRRAS | LOCATED | LVCMOS33_OUT | PR2B | | +| 76/0 | RDQMH | LOCATED | LVCMOS33_OUT | PT9F | | +| 77/0 | nRCS | LOCATED | LVCMOS33_OUT | PT9E | | +| 78/0 | nRCAS | LOCATED | LVCMOS33_OUT | PT9C | | +| 79/0 | RA[11] | LOCATED | LVCMOS33_OUT | PT9A | | +| 82/0 | RCKE | LOCATED | LVCMOS33_OUT | PT7E | D7 | +| 83/0 | RBA[1] | LOCATED | LVCMOS33_OUT | PT7A | D6 | +| 85/0 | RA[9] | LOCATED | LVCMOS33_OUT | PT6B | PCLKT0_1 | +| 86/0 | RCLK | LOCATED | LVCMOS33_IN | PT5B | PCLKT0_0 | +| 87/0 | RA[10] | LOCATED | LVCMOS33_OUT | PT5A | | +| 89/0 | RA[1] | LOCATED | LVCMOS33_OUT | PT4F | | +| 91/0 | RA[6] | LOCATED | LVCMOS33_OUT | PT3F | D3 | +| 94/0 | RA[2] | LOCATED | LVCMOS33_OUT | PT3B | | +| 95/0 | RA[5] | LOCATED | LVCMOS33_OUT | PT3A | | +| 96/0 | RA[8] | LOCATED | LVCMOS33_OUT | PT2F | D2 | +| 97/0 | RA[3] | LOCATED | LVCMOS33_OUT | PT2E | | +| 98/0 | RA[0] | LOCATED | LVCMOS33_OUT | PT2B | D1 | +| 99/0 | RA[4] | LOCATED | LVCMOS33_OUT | PT2C | | +| 100/0 | RA[7] | LOCATED | LVCMOS33_OUT | PT2A | | +| PB2A/2 | unused, PULL:UP | | | PB2A | | +| PB2B/2 | unused, PULL:UP | | | PB2B | | +| PB2D/2 | unused, PULL:UP | | | PB2D | | +| PB3A/2 | unused, PULL:UP | | | PB3A | | +| PB3B/2 | unused, PULL:UP | | | PB3B | | +| PB3C/2 | unused, PULL:UP | | | PB3C | | +| PB3D/2 | unused, PULL:UP | | | PB3D | | +| PB4A/2 | unused, PULL:UP | | | PB4A | | +| PB4B/2 | unused, PULL:UP | | | PB4B | | +| PB4D/2 | unused, PULL:UP | | | PB4D | | +| PB4F/2 | unused, PULL:UP | | | PB4F | | +| PB5A/2 | unused, PULL:UP | | | PB5A | | +| PB5C/2 | unused, PULL:UP | | | PB5C | | +| PB6A/2 | unused, PULL:UP | | | PB6A | | +| PB6D/2 | unused, PULL:UP | | | PB6D | | +| PB7A/2 | unused, PULL:UP | | | PB7A | | +| PB7B/2 | unused, PULL:UP | | | PB7B | | +| PB7C/2 | unused, PULL:UP | | | PB7C | | +| PB7D/2 | unused, PULL:UP | | | PB7D | | +| PB7E/2 | unused, PULL:UP | | | PB7E | | +| PB7F/2 | unused, PULL:UP | | | PB7F | | +| PB8A/2 | unused, PULL:UP | | | PB8A | | +| PB9B/2 | unused, PULL:UP | | | PB9B | | +| PB9E/0 | unused, PULL:UP | | | PB9E | | +| PL4B/3 | unused, PULL:UP | | | PL4B | | +| PL5A/3 | unused, PULL:UP | | | PL5A | | +| PL5C/3 | unused, PULL:UP | | | PL5C | | +| PL5D/3 | unused, PULL:UP | | | PL5D | | +| PL6A/3 | unused, PULL:UP | | | PL6A | | +| PL6B/3 | unused, PULL:UP | | | PL6B | | +| PL6C/3 | unused, PULL:UP | | | PL6C | | +| PL6D/3 | unused, PULL:UP | | | PL6D | | +| PL7A/3 | unused, PULL:UP | | | PL7A | | +| PL7C/3 | unused, PULL:UP | | | PL7C | | +| PL7D/3 | unused, PULL:UP | | | PL7D | | +| PL8A/3 | unused, PULL:UP | | | PL8A | | +| PL8B/3 | unused, PULL:UP | | | PL8B | | +| PL9B/3 | unused, PULL:UP | | | PL9B | | +| PL9D/3 | unused, PULL:UP | | | PL9D | | +| PL10B/3 | unused, PULL:UP | | | PL10B | | +| PL10D/3 | unused, PULL:UP | | | PL10D | | +| PL11B/3 | unused, PULL:UP | | | PL11B | | +| PL11D/3 | unused, PULL:UP | | | PL11D | | +| PR2A/1 | unused, PULL:UP | | | PR2A | | +| PR2C/1 | unused, PULL:UP | | | PR2C | | +| PR3A/1 | unused, PULL:UP | | | PR3A | | +| PR3C/1 | unused, PULL:UP | | | PR3C | | +| PR4A/1 | unused, PULL:UP | | | PR4A | | +| PR4C/1 | unused, PULL:UP | | | PR4C | | +| PR5A/1 | unused, PULL:UP | | | PR5A | | +| PR5C/1 | unused, PULL:UP | | | PR5C | | +| PR6A/1 | unused, PULL:UP | | | PR6A | | +| PR6D/1 | unused, PULL:UP | | | PR6D | | +| PR7A/1 | unused, PULL:UP | | | PR7A | | +| PR7C/1 | unused, PULL:UP | | | PR7C | | +| PR7D/1 | unused, PULL:UP | | | PR7D | | +| PR8A/1 | unused, PULL:UP | | | PR8A | | +| PR8B/1 | unused, PULL:UP | | | PR8B | | +| PR8C/1 | unused, PULL:UP | | | PR8C | | +| PR8D/1 | unused, PULL:UP | | | PR8D | | +| PR9A/1 | unused, PULL:UP | | | PR9A | | +| PR9C/1 | unused, PULL:UP | | | PR9C | | +| PT2D/0 | unused, PULL:UP | | | PT2D | | +| PT3C/0 | unused, PULL:UP | | | PT3C | | +| PT3D/0 | unused, PULL:UP | | | PT3D | | +| PT3E/0 | unused, PULL:UP | | | PT3E | | +| PT4A/0 | unused, PULL:UP | | | PT4A | | +| PT4B/0 | unused, PULL:UP | | | PT4B | | +| PT4C/0 | unused, PULL:UP | | | PT4C | | +| PT4D/0 | unused, PULL:UP | | | PT4D | | +| PT4E/0 | unused, PULL:UP | | | PT4E | | +| PT5C/0 | unused, PULL:UP | | | PT5C | | +| PT5D/0 | unused, PULL:UP | | | PT5D | | +| PT6A/0 | unused, PULL:UP | | | PT6A | | +| PT6C/0 | unused, PULL:UP | | | PT6C | | +| PT6D/0 | unused, PULL:UP | | | PT6D | | +| PT7B/0 | unused, PULL:UP | | | PT7B | | +| PT7C/0 | unused, PULL:UP | | | PT7C | | +| PT7D/0 | unused, PULL:UP | | | PT7D | | +| PT7F/0 | unused, PULL:UP | | | PT7F | | +| PT8A/0 | unused, PULL:UP | | | PT8A | | +| PT8B/0 | unused, PULL:UP | | | PT8B | | +| PT8C/0 | unused, PULL:UP | | | PT8C | | +| PT8D/0 | unused, PULL:UP | | | PT8D | | +| PT9B/0 | unused, PULL:UP | | | PT9B | | +| PT9D/0 | unused, PULL:UP | | | PT9D | | +| TCK/2 | | | | TCK | TCK | +| TDI/2 | | | | TDI | TDID0 | +| TDO/2 | | | | TDO | TDO | +| TMS/2 | | | | TMS | TMS | ++----------+---------------------+------------+---------------+-------+---------------+ + + +List of All Pins' Locate Preferences Based on Final Placement After PAR +to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): + +LOCATE COMP "CROW[0]" SITE "32"; +LOCATE COMP "CROW[1]" SITE "34"; +LOCATE COMP "Din[0]" SITE "21"; +LOCATE COMP "Din[1]" SITE "15"; +LOCATE COMP "Din[2]" SITE "14"; +LOCATE COMP "Din[3]" SITE "16"; +LOCATE COMP "Din[4]" SITE "18"; +LOCATE COMP "Din[5]" SITE "17"; +LOCATE COMP "Din[6]" SITE "20"; +LOCATE COMP "Din[7]" SITE "19"; +LOCATE COMP "Dout[0]" SITE "1"; +LOCATE COMP "Dout[1]" SITE "7"; +LOCATE COMP "Dout[2]" SITE "8"; +LOCATE COMP "Dout[3]" SITE "6"; +LOCATE COMP "Dout[4]" SITE "4"; +LOCATE COMP "Dout[5]" SITE "5"; +LOCATE COMP "Dout[6]" SITE "2"; +LOCATE COMP "Dout[7]" SITE "3"; +LOCATE COMP "LED" SITE "57"; +LOCATE COMP "MAin[0]" SITE "23"; +LOCATE COMP "MAin[1]" SITE "38"; +LOCATE COMP "MAin[2]" SITE "37"; +LOCATE COMP "MAin[3]" SITE "47"; +LOCATE COMP "MAin[4]" SITE "46"; +LOCATE COMP "MAin[5]" SITE "45"; +LOCATE COMP "MAin[6]" SITE "49"; +LOCATE COMP "MAin[7]" SITE "44"; +LOCATE COMP "MAin[8]" SITE "50"; +LOCATE COMP "MAin[9]" SITE "51"; +LOCATE COMP "PHI2" SITE "39"; +LOCATE COMP "RA[0]" SITE "98"; +LOCATE COMP "RA[10]" SITE "87"; +LOCATE COMP "RA[11]" SITE "79"; +LOCATE COMP "RA[1]" SITE "89"; +LOCATE COMP "RA[2]" SITE "94"; +LOCATE COMP "RA[3]" SITE "97"; +LOCATE COMP "RA[4]" SITE "99"; +LOCATE COMP "RA[5]" SITE "95"; +LOCATE COMP "RA[6]" SITE "91"; +LOCATE COMP "RA[7]" SITE "100"; +LOCATE COMP "RA[8]" SITE "96"; +LOCATE COMP "RA[9]" SITE "85"; +LOCATE COMP "RBA[0]" SITE "63"; +LOCATE COMP "RBA[1]" SITE "83"; +LOCATE COMP "RCKE" SITE "82"; +LOCATE COMP "RCLK" SITE "86"; +LOCATE COMP "RDQMH" SITE "76"; +LOCATE COMP "RDQML" SITE "61"; +LOCATE COMP "RD[0]" SITE "64"; +LOCATE COMP "RD[1]" SITE "65"; +LOCATE COMP "RD[2]" SITE "66"; +LOCATE COMP "RD[3]" SITE "67"; +LOCATE COMP "RD[4]" SITE "68"; +LOCATE COMP "RD[5]" SITE "69"; +LOCATE COMP "RD[6]" SITE "70"; +LOCATE COMP "RD[7]" SITE "71"; +LOCATE COMP "UFMCLK" SITE "58"; +LOCATE COMP "UFMSDI" SITE "56"; +LOCATE COMP "UFMSDO" SITE "55"; +LOCATE COMP "nCCAS" SITE "27"; +LOCATE COMP "nCRAS" SITE "43"; +LOCATE COMP "nFWE" SITE "22"; +LOCATE COMP "nRCAS" SITE "78"; +LOCATE COMP "nRCS" SITE "77"; +LOCATE COMP "nRRAS" SITE "73"; +LOCATE COMP "nRWE" SITE "72"; +LOCATE COMP "nUFMCS" SITE "53"; + + + + + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:28 2023 + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.par b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.par new file mode 100644 index 0000000..ca08894 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.par @@ -0,0 +1,253 @@ +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:25 2023 + +C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO640C_impl1.p2t +RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir +RAM2GS_LCMXO640C_impl1.prf -gui -msgset +D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml + + +Preference file: RAM2GS_LCMXO640C_impl1.prf. + +Level/ Number Worst Timing Worst Timing Run NCD +Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status +---------- -------- ----- ------ ----------- ----------- ---- ------ +5_1 * 0 -9.822 909228 0.273 0 04 Completed + +* : Design saved. + +Total (real) run time for 1-seed: 4 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Lattice Place and Route Report for Design "RAM2GS_LCMXO640C_impl1_map.ncd" +Tue Aug 15 05:03:25 2023 + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir/5_1.ncd RAM2GS_LCMXO640C_impl1.prf +Preference file: RAM2GS_LCMXO640C_impl1.prf. +Placement level-cost: 5-1. +Routing Iterations: 6 + +Loading design for application par from file RAM2GS_LCMXO640C_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 3 +Loading device for application par from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +License checked out. + + +Ignore Preference Error(s): True +Device utilization summary: + + PIO (prelim) 67/159 42% used + 67/74 90% bonded + SLICE 71/320 22% used + + + +Number of Signals: 262 +Number of Connections: 662 + +Pin Constraint Summary: + 67 out of 67 pins locked (100% locked). + +The following 2 signals are selected to use the primary clock routing resources: + RCLK_c (driver: RCLK, clk load #: 40) + PHI2_c (driver: PHI2, clk load #: 13) + +The following 1 signal is selected to use the secondary clock routing resources: + nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0) + +No signal is selected as Global Set/Reset. +Starting Placer Phase 0. +......... +Finished Placer Phase 0. REAL time: 0 secs + +Starting Placer Phase 1. +......... +Placer score = 1223575. +Finished Placer Phase 1. REAL time: 3 secs + +Starting Placer Phase 2. +. +Placer score = 1220793 +Finished Placer Phase 2. REAL time: 3 secs + + +------------------ Clock Report ------------------ + +Global Clock Resources: + CLK_PIN : 1 out of 4 (25%) + General PIO: 1 out of 160 (0%) + +Global Clocks: + PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT5B)", clk load = 40 + PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB6C)", clk load = 13 + SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB8B)", clk load = 7, ce load = 0, sr load = 0 + + PRIMARY : 2 out of 4 (50%) + SECONDARY: 1 out of 4 (25%) + +--------------- End of Clock Report --------------- + + +I/O Usage Summary (final): + 67 out of 159 (42.1%) PIO sites used. + 67 out of 74 (90.5%) bonded PIO sites used. + Number of PIO comps: 67; differential: 0. + Number of Vref pins used: 0. + +I/O Bank Usage Summary: ++----------+----------------+------------+------------+------------+ +| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | ++----------+----------------+------------+------------+------------+ +| 0 | 18 / 18 (100%) | 3.3V | - | - | +| 1 | 18 / 21 ( 85%) | 3.3V | - | - | +| 2 | 13 / 14 ( 92%) | - | - | - | +| 3 | 18 / 21 ( 85%) | 3.3V | - | - | ++----------+----------------+------------+------------+------------+ + +Total placer CPU time: 3 secs + +Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd. + +0 connections routed; 662 unrouted. +Starting router resource preassignment +WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew. +WARNING - par: The driver of secondary clock net nCRAS_c is not placed on one of the PIO sites dedicated for secondary clocks. This secondary clock will be routed through general routing resource and may suffer from excessive delay or skew. + +WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. + Signal=nCCAS_c loads=7 clock_loads=4 + +Completed router resource preassignment. Real time: 3 secs + +Start NBR router at 05:03:28 08/15/23 + +***************************************************************** +Info: NBR allows conflicts(one node used by more than one signal) + in the earlier iterations. In each iteration, it tries to + solve the conflicts while keeping the critical connections + routed as short as possible. The routing process is said to + be completed when no conflicts exist and all connections + are routed. +Note: NBR uses a different method to calculate timing slacks. The + worst slack and total negative slack may not be the same as + that in TRCE report. You should always run TRCE to verify + your design. +***************************************************************** + +Start NBR special constraint process at 05:03:28 08/15/23 + +Start NBR section for initial routing at 05:03:28 08/15/23 +Level 1, iteration 1 +0(0.00%) conflict; 559(84.44%) untouched conns; 717961 (nbr) score; +Estimated worst slack/total negative slack: -9.776ns/-717.961ns; real time: 3 secs +Level 2, iteration 1 +7(0.03%) conflicts; 496(74.92%) untouched conns; 699022 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-699.022ns; real time: 3 secs +Level 3, iteration 1 +9(0.03%) conflicts; 252(38.07%) untouched conns; 765745 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-765.746ns; real time: 3 secs +Level 4, iteration 1 +9(0.03%) conflicts; 0(0.00%) untouched conn; 781820 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-781.821ns; real time: 4 secs + +Info: Initial congestion level at 75% usage is 0 +Info: Initial congestion area at 75% usage is 0 (0.00%) + +Start NBR section for normal routing at 05:03:29 08/15/23 +Level 4, iteration 1 +5(0.02%) conflicts; 0(0.00%) untouched conn; 781048 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-781.049ns; real time: 4 secs +Level 4, iteration 2 +4(0.01%) conflicts; 0(0.00%) untouched conn; 780690 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-780.691ns; real time: 4 secs +Level 4, iteration 3 +4(0.01%) conflicts; 0(0.00%) untouched conn; 780715 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-780.716ns; real time: 4 secs +Level 4, iteration 4 +2(0.01%) conflicts; 0(0.00%) untouched conn; 780715 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-780.716ns; real time: 4 secs +Level 4, iteration 5 +2(0.01%) conflicts; 0(0.00%) untouched conn; 783401 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 4 secs +Level 4, iteration 6 +0(0.00%) conflict; 0(0.00%) untouched conn; 783401 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 4 secs + +Start NBR section for performance tuning (iteration 1) at 05:03:29 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 783401 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 4 secs + +Start NBR section for re-routing at 05:03:29 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 776978 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-776.979ns; real time: 4 secs + +Start NBR section for post-routing at 05:03:29 08/15/23 + +End NBR router with 0 unrouted connection + +NBR Summary +----------- + Number of unrouted connections : 0 (0.00%) + Number of connections with timing violations : 260 (39.27%) + Estimated worst slack : -9.822ns + Timing score : 909228 +----------- +Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. + + + +WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. + Signal=nCCAS_c loads=7 clock_loads=4 + +Total CPU time 4 secs +Total REAL time: 4 secs +Completely routed. +End of route. 662 routed (100.00%); 0 unrouted. + +Hold time timing score: 0, hold timing errors: 0 + +Timing score: 909228 + +Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd. + + +All signals are completely routed. + + +PAR_SUMMARY::Run status = Completed +PAR_SUMMARY::Number of unrouted conns = 0 +PAR_SUMMARY::Worst slack> = -9.822 +PAR_SUMMARY::Timing score> = 909.228 +PAR_SUMMARY::Worst slack> = 0.273 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Number of errors = 0 + +Total CPU time to completion: 4 secs +Total REAL time to completion: 4 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.prf b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.prf new file mode 100644 index 0000000..5fdb83b --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.prf @@ -0,0 +1,81 @@ +SCHEMATIC START ; +# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:03:22 2023 + +SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ; +LOCATE COMP "RD[7]" SITE "71" ; +LOCATE COMP "RD[6]" SITE "70" ; +LOCATE COMP "RD[5]" SITE "69" ; +LOCATE COMP "RD[4]" SITE "68" ; +LOCATE COMP "RD[3]" SITE "67" ; +LOCATE COMP "RD[2]" SITE "66" ; +LOCATE COMP "RD[1]" SITE "65" ; +LOCATE COMP "RD[0]" SITE "64" ; +LOCATE COMP "Dout[7]" SITE "3" ; +LOCATE COMP "Dout[6]" SITE "2" ; +LOCATE COMP "Dout[5]" SITE "5" ; +LOCATE COMP "Dout[4]" SITE "4" ; +LOCATE COMP "Dout[3]" SITE "6" ; +LOCATE COMP "Dout[2]" SITE "8" ; +LOCATE COMP "Dout[1]" SITE "7" ; +LOCATE COMP "Dout[0]" SITE "1" ; +LOCATE COMP "LED" SITE "57" ; +LOCATE COMP "RBA[1]" SITE "83" ; +LOCATE COMP "RBA[0]" SITE "63" ; +LOCATE COMP "RA[11]" SITE "79" ; +LOCATE COMP "RA[10]" SITE "87" ; +LOCATE COMP "RA[9]" SITE "85" ; +LOCATE COMP "RA[8]" SITE "96" ; +LOCATE COMP "RA[7]" SITE "100" ; +LOCATE COMP "RA[6]" SITE "91" ; +LOCATE COMP "RA[5]" SITE "95" ; +LOCATE COMP "RA[4]" SITE "99" ; +LOCATE COMP "RA[3]" SITE "97" ; +LOCATE COMP "RA[2]" SITE "94" ; +LOCATE COMP "RA[1]" SITE "89" ; +LOCATE COMP "RA[0]" SITE "98" ; +LOCATE COMP "nRCS" SITE "77" ; +LOCATE COMP "RCKE" SITE "82" ; +LOCATE COMP "nRWE" SITE "72" ; +LOCATE COMP "nRRAS" SITE "73" ; +LOCATE COMP "nRCAS" SITE "78" ; +LOCATE COMP "RDQMH" SITE "76" ; +LOCATE COMP "RDQML" SITE "61" ; +LOCATE COMP "nUFMCS" SITE "53" ; +LOCATE COMP "UFMCLK" SITE "58" ; +LOCATE COMP "UFMSDI" SITE "56" ; +LOCATE COMP "PHI2" SITE "39" ; +LOCATE COMP "MAin[9]" SITE "51" ; +LOCATE COMP "MAin[8]" SITE "50" ; +LOCATE COMP "MAin[7]" SITE "44" ; +LOCATE COMP "MAin[6]" SITE "49" ; +LOCATE COMP "MAin[5]" SITE "45" ; +LOCATE COMP "MAin[4]" SITE "46" ; +LOCATE COMP "MAin[3]" SITE "47" ; +LOCATE COMP "MAin[2]" SITE "37" ; +LOCATE COMP "MAin[1]" SITE "38" ; +LOCATE COMP "MAin[0]" SITE "23" ; +LOCATE COMP "CROW[1]" SITE "34" ; +LOCATE COMP "CROW[0]" SITE "32" ; +LOCATE COMP "Din[7]" SITE "19" ; +LOCATE COMP "Din[6]" SITE "20" ; +LOCATE COMP "Din[5]" SITE "17" ; +LOCATE COMP "Din[4]" SITE "18" ; +LOCATE COMP "Din[3]" SITE "16" ; +LOCATE COMP "Din[2]" SITE "14" ; +LOCATE COMP "Din[1]" SITE "15" ; +LOCATE COMP "Din[0]" SITE "21" ; +LOCATE COMP "nCCAS" SITE "27" ; +LOCATE COMP "nCRAS" SITE "43" ; +LOCATE COMP "nFWE" SITE "22" ; +LOCATE COMP "RCLK" SITE "86" ; +LOCATE COMP "UFMSDO" SITE "55" ; +SCHEMATIC END ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +COMMERCIAL ; + +// No timing preferences found. TRCE invokes auto-generation of timing preferences +// Section Autogen +FREQUENCY NET "RCLK_c" 283.768 MHz ; +FREQUENCY NET "PHI2_c" 120.077 MHz ; +// End Section Autogen diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pt b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pt new file mode 100644 index 0000000..916dbc3 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pt @@ -0,0 +1,10 @@ +-v +10 + + + + +-gt +-sethld +-sp 3 +-sphld m diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.t2b b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.t2b new file mode 100644 index 0000000..aa05f83 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.t2b @@ -0,0 +1,2 @@ + +-g ES:No diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.tw1 b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.tw1 new file mode 100644 index 0000000..f6f527e --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.tw1 @@ -0,0 +1,353 @@ + +Loading design for application trce from file ram2gs_lcmxo640c_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 3 +Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:23 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf +Design file: ram2gs_lcmxo640c_impl1_map.ncd +Preference file: ram2gs_lcmxo640c_impl1.prf +Device,speed: LCMXO640C,3 +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +Report Type: based on TRACE automatically generated preferences +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ; + 383 items scored, 213 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path exceeds requirements by 5.089ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i14 (from RCLK_c +) + Destination: FF Data in n8MEGEN_418 (to RCLK_c +) + + Delay: 8.369ns (24.4% logic, 75.6% route), 5 logic levels. + + Constraint Details: + + 8.369ns physical path delay SLICE_1 to SLICE_56 exceeds + 3.524ns delay constraint less + 0.244ns CE_SET requirement (totaling 3.280ns) by 5.089ns + + Physical Path Details: + + Data path SLICE_1 to SLICE_56: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_1.CLK to SLICE_1.Q0 SLICE_1 (from RCLK_c) +ROUTE 5 e 1.441 SLICE_1.Q0 to SLICE_90.C1 FS_14 +CTOF_DEL --- 0.371 SLICE_90.C1 to SLICE_90.F1 SLICE_90 +ROUTE 1 e 1.441 SLICE_90.F1 to SLICE_75.B0 n2328 +CTOF_DEL --- 0.371 SLICE_75.B0 to SLICE_75.F0 SLICE_75 +ROUTE 2 e 1.441 SLICE_75.F0 to SLICE_87.B1 n2214 +CTOF_DEL --- 0.371 SLICE_87.B1 to SLICE_87.F1 SLICE_87 +ROUTE 1 e 0.561 SLICE_87.F1 to SLICE_87.A0 n7 +CTOF_DEL --- 0.371 SLICE_87.A0 to SLICE_87.F0 SLICE_87 +ROUTE 1 e 1.441 SLICE_87.F0 to SLICE_56.CE RCLK_c_enable_11 (to RCLK_c) + -------- + 8.369 (24.4% logic, 75.6% route), 5 logic levels. + +Warning: 116.104MHz is the maximum frequency for this preference. + + +================================================================================ +Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ; + 106 items scored, 97 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path exceeds requirements by 7.535ns (weighted slack = -15.070ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i0 (from PHI2_c +) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 11.061ns (21.8% logic, 78.2% route), 6 logic levels. + + Constraint Details: + + 11.061ns physical path delay SLICE_88 to SLICE_14 exceeds + 4.164ns delay constraint less + 0.638ns LSR_SET requirement (totaling 3.526ns) by 7.535ns + + Physical Path Details: + + Data path SLICE_88 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_88.CLK to SLICE_88.Q0 SLICE_88 (from PHI2_c) +ROUTE 1 e 1.441 SLICE_88.Q0 to SLICE_97.D0 Bank_0 +CTOF_DEL --- 0.371 SLICE_97.D0 to SLICE_97.F0 SLICE_97 +ROUTE 1 e 1.441 SLICE_97.F0 to SLICE_81.B0 n2314 +CTOF_DEL --- 0.371 SLICE_81.B0 to SLICE_81.F0 SLICE_81 +ROUTE 1 e 1.441 SLICE_81.F0 to SLICE_18.B1 n26 +CTOF_DEL --- 0.371 SLICE_18.B1 to SLICE_18.F1 SLICE_18 +ROUTE 8 e 1.441 SLICE_18.F1 to SLICE_89.B0 n1326 +CTOF_DEL --- 0.371 SLICE_89.B0 to SLICE_89.F0 SLICE_89 +ROUTE 1 e 1.441 SLICE_89.F0 to SLICE_79.C0 n1280 +CTOF_DEL --- 0.371 SLICE_79.C0 to SLICE_79.F0 SLICE_79 +ROUTE 2 e 1.441 SLICE_79.F0 to SLICE_14.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 11.061 (21.8% logic, 78.2% route), 6 logic levels. + +Warning: 42.739MHz is the maximum frequency for this preference. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY NET "RCLK_c" 283.768000 MHz ; | 283.768 MHz| 116.104 MHz| 5 * + | | | +FREQUENCY NET "PHI2_c" 120.077000 MHz ; | 120.077 MHz| 42.739 MHz| 6 * + | | | +---------------------------------------------------------------------------- + + +2 preferences(marked by "*" above) not met. + +---------------------------------------------------------------------------- +Critical Nets | Loads| Errors| % of total +---------------------------------------------------------------------------- +n1326 | 8| 96| 30.97% + | | | +n26 | 1| 72| 23.23% + | | | +---------------------------------------------------------------------------- + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 + Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Setup): +--------------- + +Timing errors: 310 Score: 1346529 +Cumulative negative slack: 874289 + +Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:23 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf +Design file: ram2gs_lcmxo640c_impl1_map.ncd +Preference file: ram2gs_lcmxo640c_impl1.prf +Device,speed: LCMXO640C,M +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ; + 383 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.342ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i4 (from RCLK_c +) + Destination: FF Data in IS_FSM__i5 (to RCLK_c +) + + Delay: 0.325ns (38.8% logic, 61.2% route), 1 logic levels. + + Constraint Details: + + 0.325ns physical path delay SLICE_100 to SLICE_100 meets + -0.017ns M_HLD and + 0.000ns delay constraint requirement (totaling -0.017ns) by 0.342ns + + Physical Path Details: + + Data path SLICE_100 to SLICE_100: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 SLICE_100.CLK to SLICE_100.Q0 SLICE_100 (from RCLK_c) +ROUTE 1 e 0.199 SLICE_100.Q0 to SLICE_100.M1 n736 (to RCLK_c) + -------- + 0.325 (38.8% logic, 61.2% route), 1 logic levels. + + +================================================================================ +Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ; + 106 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.430ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted_406 (from PHI2_c -) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 0.411ns (51.3% logic, 48.7% route), 2 logic levels. + + Constraint Details: + + 0.411ns physical path delay SLICE_14 to SLICE_14 meets + -0.019ns DIN_HLD and + 0.000ns delay constraint requirement (totaling -0.019ns) by 0.430ns + + Physical Path Details: + + Data path SLICE_14 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 SLICE_14.CLK to SLICE_14.Q0 SLICE_14 (from PHI2_c) +ROUTE 2 e 0.199 SLICE_14.Q0 to SLICE_14.C0 C1Submitted +CTOF_DEL --- 0.074 SLICE_14.C0 to SLICE_14.F0 SLICE_14 +ROUTE 1 e 0.001 SLICE_14.F0 to SLICE_14.DI0 n6_adj_3 (to PHI2_c) + -------- + 0.411 (51.3% logic, 48.7% route), 2 logic levels. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference(MIN Delays) | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY NET "RCLK_c" 283.768000 MHz ; | 0.000 ns| 0.342 ns| 1 + | | | +FREQUENCY NET "PHI2_c" 120.077000 MHz ; | 0.000 ns| 0.430 ns| 2 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 + Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 310 (setup), 0 (hold) +Score: 1346529 (setup), 0 (hold) +Cumulative negative slack: 874289 (874289+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.twr b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.twr new file mode 100644 index 0000000..5ebed7c --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.twr @@ -0,0 +1,2161 @@ + +Loading design for application trce from file ram2gs_lcmxo640c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 3 +Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:29 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf +Design file: ram2gs_lcmxo640c_impl1.ncd +Preference file: ram2gs_lcmxo640c_impl1.prf +Device,speed: LCMXO640C,3 +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +Report Type: based on TRACE automatically generated preferences +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ; + 383 items scored, 233 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path exceeds requirements by 5.082ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i13 (from RCLK_c +) + Destination: FF Data in UFMSDI_417 (to RCLK_c +) + + Delay: 7.980ns (21.0% logic, 79.0% route), 4 logic levels. + + Constraint Details: + + 7.980ns physical path delay SLICE_3 to SLICE_44 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.626ns LSR_SET requirement (totaling 2.898ns) by 5.082ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_44: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R3C5C.CLK to R3C5C.Q1 SLICE_3 (from RCLK_c) +ROUTE 3 1.372 R3C5C.Q1 to R3C2D.C1 FS_13 +CTOF_DEL --- 0.371 R3C2D.C1 to R3C2D.F1 SLICE_94 +ROUTE 3 1.278 R3C2D.F1 to R4C5B.D1 n2272 +CTOF_DEL --- 0.371 R4C5B.D1 to R4C5B.F1 SLICE_78 +ROUTE 3 0.528 R4C5B.F1 to R4C5B.C0 n2464 +CTOF_DEL --- 0.371 R4C5B.C0 to R4C5B.F0 SLICE_78 +ROUTE 2 3.129 R4C5B.F0 to R9C9C.LSR n1846 (to RCLK_c) + -------- + 7.980 (21.0% logic, 79.0% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R3C5C.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_44: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R9C9C.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.998ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i12 (from RCLK_c +) + Destination: FF Data in UFMSDI_417 (to RCLK_c +) + + Delay: 7.896ns (21.2% logic, 78.8% route), 4 logic levels. + + Constraint Details: + + 7.896ns physical path delay SLICE_3 to SLICE_44 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.626ns LSR_SET requirement (totaling 2.898ns) by 4.998ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_44: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R3C5C.CLK to R3C5C.Q0 SLICE_3 (from RCLK_c) +ROUTE 4 1.063 R3C5C.Q0 to R3C6C.A1 FS_12 +CTOF_DEL --- 0.371 R3C6C.A1 to R3C6C.F1 SLICE_68 +ROUTE 2 1.503 R3C6C.F1 to R4C5B.A1 n2471 +CTOF_DEL --- 0.371 R4C5B.A1 to R4C5B.F1 SLICE_78 +ROUTE 3 0.528 R4C5B.F1 to R4C5B.C0 n2464 +CTOF_DEL --- 0.371 R4C5B.C0 to R4C5B.F0 SLICE_78 +ROUTE 2 3.129 R4C5B.F0 to R9C9C.LSR n1846 (to RCLK_c) + -------- + 7.896 (21.2% logic, 78.8% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R3C5C.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_44: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R9C9C.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.889ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i15 (from RCLK_c +) + Destination: FF Data in UFMSDI_417 (to RCLK_c +) + + Delay: 7.787ns (21.5% logic, 78.5% route), 4 logic levels. + + Constraint Details: + + 7.787ns physical path delay SLICE_1 to SLICE_44 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.626ns LSR_SET requirement (totaling 2.898ns) by 4.889ns + + Physical Path Details: + + Data path SLICE_1 to SLICE_44: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R3C5D.CLK to R3C5D.Q1 SLICE_1 (from RCLK_c) +ROUTE 3 1.179 R3C5D.Q1 to R3C2D.D1 FS_15 +CTOF_DEL --- 0.371 R3C2D.D1 to R3C2D.F1 SLICE_94 +ROUTE 3 1.278 R3C2D.F1 to R4C5B.D1 n2272 +CTOF_DEL --- 0.371 R4C5B.D1 to R4C5B.F1 SLICE_78 +ROUTE 3 0.528 R4C5B.F1 to R4C5B.C0 n2464 +CTOF_DEL --- 0.371 R4C5B.C0 to R4C5B.F0 SLICE_78 +ROUTE 2 3.129 R4C5B.F0 to R9C9C.LSR n1846 (to RCLK_c) + -------- + 7.787 (21.5% logic, 78.5% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R3C5D.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_44: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R9C9C.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.800ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i17 (from RCLK_c +) + Destination: FF Data in UFMSDI_417 (to RCLK_c +) + + Delay: 7.698ns (21.7% logic, 78.3% route), 4 logic levels. + + Constraint Details: + + 7.698ns physical path delay SLICE_8 to SLICE_44 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.626ns LSR_SET requirement (totaling 2.898ns) by 4.800ns + + Physical Path Details: + + Data path SLICE_8 to SLICE_44: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R3C6A.CLK to R3C6A.Q1 SLICE_8 (from RCLK_c) +ROUTE 4 0.865 R3C6A.Q1 to R3C6C.C1 FS_17 +CTOF_DEL --- 0.371 R3C6C.C1 to R3C6C.F1 SLICE_68 +ROUTE 2 1.503 R3C6C.F1 to R4C5B.A1 n2471 +CTOF_DEL --- 0.371 R4C5B.A1 to R4C5B.F1 SLICE_78 +ROUTE 3 0.528 R4C5B.F1 to R4C5B.C0 n2464 +CTOF_DEL --- 0.371 R4C5B.C0 to R4C5B.F0 SLICE_78 +ROUTE 2 3.129 R4C5B.F0 to R9C9C.LSR n1846 (to RCLK_c) + -------- + 7.698 (21.7% logic, 78.3% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_8: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R3C6A.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_44: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R9C9C.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.458ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i13 (from RCLK_c +) + Destination: FF Data in UFMCLK_416 (to RCLK_c +) + + Delay: 7.801ns (26.2% logic, 73.8% route), 5 logic levels. + + Constraint Details: + + 7.801ns physical path delay SLICE_3 to SLICE_43 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.181ns DIN_SET requirement (totaling 3.343ns) by 4.458ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_43: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R3C5C.CLK to R3C5C.Q1 SLICE_3 (from RCLK_c) +ROUTE 3 1.372 R3C5C.Q1 to R3C2D.C1 FS_13 +CTOF_DEL --- 0.371 R3C2D.C1 to R3C2D.F1 SLICE_94 +ROUTE 3 1.777 R3C2D.F1 to R9C9C.D1 n2272 +CTOF_DEL --- 0.371 R9C9C.D1 to R9C9C.F1 SLICE_44 +ROUTE 2 2.111 R9C9C.F1 to R3C2B.A1 n2462 +CTOF_DEL --- 0.371 R3C2B.A1 to R3C2B.F1 SLICE_43 +ROUTE 1 0.497 R3C2B.F1 to R3C2B.C0 n1160 +CTOF_DEL --- 0.371 R3C2B.C0 to R3C2B.F0 SLICE_43 +ROUTE 1 0.000 R3C2B.F0 to R3C2B.DI0 UFMCLK_N_224 (to RCLK_c) + -------- + 7.801 (26.2% logic, 73.8% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R3C5C.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_43: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R3C2B.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.352ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i13 (from RCLK_c +) + Destination: FF Data in LEDEN_419 (to RCLK_c +) + + Delay: 7.632ns (21.9% logic, 78.1% route), 4 logic levels. + + Constraint Details: + + 7.632ns physical path delay SLICE_3 to SLICE_26 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.244ns CE_SET requirement (totaling 3.280ns) by 4.352ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_26: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R3C5C.CLK to R3C5C.Q1 SLICE_3 (from RCLK_c) +ROUTE 3 1.372 R3C5C.Q1 to R3C2D.C1 FS_13 +CTOF_DEL --- 0.371 R3C2D.C1 to R3C2D.F1 SLICE_94 +ROUTE 3 1.471 R3C2D.F1 to R4C5C.C0 n2272 +CTOF_DEL --- 0.371 R4C5C.C0 to R4C5C.F0 SLICE_75 +ROUTE 2 0.513 R4C5C.F0 to R4C5C.C1 n2214 +CTOF_DEL --- 0.371 R4C5C.C1 to R4C5C.F1 SLICE_75 +ROUTE 1 2.603 R4C5C.F1 to R9C9B.CE RCLK_c_enable_12 (to RCLK_c) + -------- + 7.632 (21.9% logic, 78.1% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R3C5C.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_26: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R9C9B.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.293ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i12 (from RCLK_c +) + Destination: FF Data in UFMCLK_416 (to RCLK_c +) + + Delay: 7.636ns (26.8% logic, 73.2% route), 5 logic levels. + + Constraint Details: + + 7.636ns physical path delay SLICE_3 to SLICE_43 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.181ns DIN_SET requirement (totaling 3.343ns) by 4.293ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_43: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R3C5C.CLK to R3C5C.Q0 SLICE_3 (from RCLK_c) +ROUTE 4 1.063 R3C5C.Q0 to R3C6C.A1 FS_12 +CTOF_DEL --- 0.371 R3C6C.A1 to R3C6C.F1 SLICE_68 +ROUTE 2 1.921 R3C6C.F1 to R9C9C.C1 n2471 +CTOF_DEL --- 0.371 R9C9C.C1 to R9C9C.F1 SLICE_44 +ROUTE 2 2.111 R9C9C.F1 to R3C2B.A1 n2462 +CTOF_DEL --- 0.371 R3C2B.A1 to R3C2B.F1 SLICE_43 +ROUTE 1 0.497 R3C2B.F1 to R3C2B.C0 n1160 +CTOF_DEL --- 0.371 R3C2B.C0 to R3C2B.F0 SLICE_43 +ROUTE 1 0.000 R3C2B.F0 to R3C2B.DI0 UFMCLK_N_224 (to RCLK_c) + -------- + 7.636 (26.8% logic, 73.2% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R3C5C.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_43: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R3C2B.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.265ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i15 (from RCLK_c +) + Destination: FF Data in UFMCLK_416 (to RCLK_c +) + + Delay: 7.608ns (26.9% logic, 73.1% route), 5 logic levels. + + Constraint Details: + + 7.608ns physical path delay SLICE_1 to SLICE_43 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.181ns DIN_SET requirement (totaling 3.343ns) by 4.265ns + + Physical Path Details: + + Data path SLICE_1 to SLICE_43: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R3C5D.CLK to R3C5D.Q1 SLICE_1 (from RCLK_c) +ROUTE 3 1.179 R3C5D.Q1 to R3C2D.D1 FS_15 +CTOF_DEL --- 0.371 R3C2D.D1 to R3C2D.F1 SLICE_94 +ROUTE 3 1.777 R3C2D.F1 to R9C9C.D1 n2272 +CTOF_DEL --- 0.371 R9C9C.D1 to R9C9C.F1 SLICE_44 +ROUTE 2 2.111 R9C9C.F1 to R3C2B.A1 n2462 +CTOF_DEL --- 0.371 R3C2B.A1 to R3C2B.F1 SLICE_43 +ROUTE 1 0.497 R3C2B.F1 to R3C2B.C0 n1160 +CTOF_DEL --- 0.371 R3C2B.C0 to R3C2B.F0 SLICE_43 +ROUTE 1 0.000 R3C2B.F0 to R3C2B.DI0 UFMCLK_N_224 (to RCLK_c) + -------- + 7.608 (26.9% logic, 73.1% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R3C5D.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_43: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R3C2B.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.226ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i16 (from RCLK_c +) + Destination: FF Data in UFMCLK_416 (to RCLK_c +) + + Delay: 7.569ns (27.0% logic, 73.0% route), 5 logic levels. + + Constraint Details: + + 7.569ns physical path delay SLICE_8 to SLICE_43 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.181ns DIN_SET requirement (totaling 3.343ns) by 4.226ns + + Physical Path Details: + + Data path SLICE_8 to SLICE_43: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R3C6A.CLK to R3C6A.Q0 SLICE_8 (from RCLK_c) +ROUTE 5 0.873 R3C6A.Q0 to R3C6B.C0 FS_16 +CTOF_DEL --- 0.371 R3C6B.C0 to R3C6B.F0 SLICE_90 +ROUTE 1 2.044 R3C6B.F0 to R9C9C.A1 n2470 +CTOF_DEL --- 0.371 R9C9C.A1 to R9C9C.F1 SLICE_44 +ROUTE 2 2.111 R9C9C.F1 to R3C2B.A1 n2462 +CTOF_DEL --- 0.371 R3C2B.A1 to R3C2B.F1 SLICE_43 +ROUTE 1 0.497 R3C2B.F1 to R3C2B.C0 n1160 +CTOF_DEL --- 0.371 R3C2B.C0 to R3C2B.F0 SLICE_43 +ROUTE 1 0.000 R3C2B.F0 to R3C2B.DI0 UFMCLK_N_224 (to RCLK_c) + -------- + 7.569 (27.0% logic, 73.0% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_8: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R3C6A.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_43: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R3C2B.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.159ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i15 (from RCLK_c +) + Destination: FF Data in LEDEN_419 (to RCLK_c +) + + Delay: 7.439ns (22.5% logic, 77.5% route), 4 logic levels. + + Constraint Details: + + 7.439ns physical path delay SLICE_1 to SLICE_26 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.244ns CE_SET requirement (totaling 3.280ns) by 4.159ns + + Physical Path Details: + + Data path SLICE_1 to SLICE_26: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R3C5D.CLK to R3C5D.Q1 SLICE_1 (from RCLK_c) +ROUTE 3 1.179 R3C5D.Q1 to R3C2D.D1 FS_15 +CTOF_DEL --- 0.371 R3C2D.D1 to R3C2D.F1 SLICE_94 +ROUTE 3 1.471 R3C2D.F1 to R4C5C.C0 n2272 +CTOF_DEL --- 0.371 R4C5C.C0 to R4C5C.F0 SLICE_75 +ROUTE 2 0.513 R4C5C.F0 to R4C5C.C1 n2214 +CTOF_DEL --- 0.371 R4C5C.C1 to R4C5C.F1 SLICE_75 +ROUTE 1 2.603 R4C5C.F1 to R9C9B.CE RCLK_c_enable_12 (to RCLK_c) + -------- + 7.439 (22.5% logic, 77.5% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R3C5D.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_26: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R9C9B.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + +Warning: 116.198MHz is the maximum frequency for this preference. + + +================================================================================ +Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ; + 106 items scored, 95 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path exceeds requirements by 4.911ns (weighted slack = -9.822ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 8.437ns (28.6% logic, 71.4% route), 6 logic levels. + + Constraint Details: + + 8.437ns physical path delay SLICE_99 to SLICE_14 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.638ns LSR_SET requirement (totaling 3.526ns) by 4.911ns + + Physical Path Details: + + Data path SLICE_99 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q1 SLICE_99 (from PHI2_c) +ROUTE 1 2.159 R2C2A.Q1 to R7C9A.D0 Bank_7 +CTOF_DEL --- 0.371 R7C9A.D0 to R7C9A.F0 SLICE_97 +ROUTE 1 1.026 R7C9A.F0 to R5C9C.A0 n2314 +CTOF_DEL --- 0.371 R5C9C.A0 to R5C9C.F0 SLICE_81 +ROUTE 1 0.304 R5C9C.F0 to R5C9D.D1 n26 +CTOF_DEL --- 0.371 R5C9D.D1 to R5C9D.F1 SLICE_18 +ROUTE 8 0.947 R5C9D.F1 to R6C9B.C0 n1326 +CTOF_DEL --- 0.371 R6C9B.C0 to R6C9B.F0 SLICE_89 +ROUTE 1 0.497 R6C9B.F0 to R6C9D.C0 n1280 +CTOF_DEL --- 0.371 R6C9D.C0 to R6C9D.F0 SLICE_79 +ROUTE 2 1.089 R6C9D.F0 to R6C7A.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 8.437 (28.6% logic, 71.4% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R2C2A.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R6C7A.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.644ns (weighted slack = -9.288ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in CmdUFMCS_412 (to PHI2_c -) + FF CmdUFMCLK_413 + + Delay: 8.543ns (28.3% logic, 71.7% route), 6 logic levels. + + Constraint Details: + + 8.543ns physical path delay SLICE_99 to SLICE_81 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 3.899ns) by 4.644ns + + Physical Path Details: + + Data path SLICE_99 to SLICE_81: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q1 SLICE_99 (from PHI2_c) +ROUTE 1 2.159 R2C2A.Q1 to R7C9A.D0 Bank_7 +CTOF_DEL --- 0.371 R7C9A.D0 to R7C9A.F0 SLICE_97 +ROUTE 1 1.026 R7C9A.F0 to R5C9C.A0 n2314 +CTOF_DEL --- 0.371 R5C9C.A0 to R5C9C.F0 SLICE_81 +ROUTE 1 0.304 R5C9C.F0 to R5C9D.D1 n26 +CTOF_DEL --- 0.371 R5C9D.D1 to R5C9D.F1 SLICE_18 +ROUTE 8 0.945 R5C9D.F1 to R7C9D.C0 n1326 +CTOF_DEL --- 0.371 R7C9D.C0 to R7C9D.F0 SLICE_82 +ROUTE 2 0.513 R7C9D.F0 to R7C9C.C1 n2460 +CTOF_DEL --- 0.371 R7C9C.C1 to R7C9C.F1 SLICE_83 +ROUTE 2 1.181 R7C9C.F1 to R5C9C.CE PHI2_N_120_enable_6 (to PHI2_c) + -------- + 8.543 (28.3% logic, 71.7% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R2C2A.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_81: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R5C9C.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.644ns (weighted slack = -9.288ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in CmdUFMSDI_414 (to PHI2_c -) + + Delay: 8.543ns (28.3% logic, 71.7% route), 6 logic levels. + + Constraint Details: + + 8.543ns physical path delay SLICE_99 to SLICE_93 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 3.899ns) by 4.644ns + + Physical Path Details: + + Data path SLICE_99 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q1 SLICE_99 (from PHI2_c) +ROUTE 1 2.159 R2C2A.Q1 to R7C9A.D0 Bank_7 +CTOF_DEL --- 0.371 R7C9A.D0 to R7C9A.F0 SLICE_97 +ROUTE 1 1.026 R7C9A.F0 to R5C9C.A0 n2314 +CTOF_DEL --- 0.371 R5C9C.A0 to R5C9C.F0 SLICE_81 +ROUTE 1 0.304 R5C9C.F0 to R5C9D.D1 n26 +CTOF_DEL --- 0.371 R5C9D.D1 to R5C9D.F1 SLICE_18 +ROUTE 8 0.945 R5C9D.F1 to R7C9D.C0 n1326 +CTOF_DEL --- 0.371 R7C9D.C0 to R7C9D.F0 SLICE_82 +ROUTE 2 0.513 R7C9D.F0 to R7C9C.C1 n2460 +CTOF_DEL --- 0.371 R7C9C.C1 to R7C9C.F1 SLICE_83 +ROUTE 2 1.181 R7C9C.F1 to R10C9A.CE PHI2_N_120_enable_6 (to PHI2_c) + -------- + 8.543 (28.3% logic, 71.7% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R2C2A.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R10C9A.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.536ns (weighted slack = -9.072ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 8.435ns (28.6% logic, 71.4% route), 6 logic levels. + + Constraint Details: + + 8.435ns physical path delay SLICE_99 to SLICE_18 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 3.899ns) by 4.536ns + + Physical Path Details: + + Data path SLICE_99 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q1 SLICE_99 (from PHI2_c) +ROUTE 1 2.159 R2C2A.Q1 to R7C9A.D0 Bank_7 +CTOF_DEL --- 0.371 R7C9A.D0 to R7C9A.F0 SLICE_97 +ROUTE 1 1.026 R7C9A.F0 to R5C9C.A0 n2314 +CTOF_DEL --- 0.371 R5C9C.A0 to R5C9C.F0 SLICE_81 +ROUTE 1 0.304 R5C9C.F0 to R5C9D.D1 n26 +CTOF_DEL --- 0.371 R5C9D.D1 to R5C9D.F1 SLICE_18 +ROUTE 8 0.945 R5C9D.F1 to R7C9D.C0 n1326 +CTOF_DEL --- 0.371 R7C9D.C0 to R7C9D.F0 SLICE_82 +ROUTE 2 0.513 R7C9D.F0 to R7C9D.C1 n2460 +CTOF_DEL --- 0.371 R7C9D.C1 to R7C9D.F1 SLICE_82 +ROUTE 1 1.073 R7C9D.F1 to R5C9D.CE PHI2_N_120_enable_7 (to PHI2_c) + -------- + 8.435 (28.6% logic, 71.4% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R2C2A.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R5C9D.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.485ns (weighted slack = -8.970ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in ADSubmitted_407 (to PHI2_c -) + + Delay: 8.011ns (30.1% logic, 69.9% route), 6 logic levels. + + Constraint Details: + + 8.011ns physical path delay SLICE_99 to SLICE_9 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.638ns LSR_SET requirement (totaling 3.526ns) by 4.485ns + + Physical Path Details: + + Data path SLICE_99 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q1 SLICE_99 (from PHI2_c) +ROUTE 1 2.159 R2C2A.Q1 to R7C9A.D0 Bank_7 +CTOF_DEL --- 0.371 R7C9A.D0 to R7C9A.F0 SLICE_97 +ROUTE 1 1.026 R7C9A.F0 to R5C9C.A0 n2314 +CTOF_DEL --- 0.371 R5C9C.A0 to R5C9C.F0 SLICE_81 +ROUTE 1 0.304 R5C9C.F0 to R5C9D.D1 n26 +CTOF_DEL --- 0.371 R5C9D.D1 to R5C9D.F1 SLICE_18 +ROUTE 8 0.947 R5C9D.F1 to R6C9B.C0 n1326 +CTOF_DEL --- 0.371 R6C9B.C0 to R6C9B.F0 SLICE_89 +ROUTE 1 0.497 R6C9B.F0 to R6C9D.C0 n1280 +CTOF_DEL --- 0.371 R6C9D.C0 to R6C9D.F0 SLICE_79 +ROUTE 2 0.663 R6C9D.F0 to R6C9C.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 8.011 (30.1% logic, 69.9% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R2C2A.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R6C9C.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.400ns (weighted slack = -8.800ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in CmdSubmitted_411 (to PHI2_c -) + + Delay: 8.299ns (29.1% logic, 70.9% route), 6 logic levels. + + Constraint Details: + + 8.299ns physical path delay SLICE_99 to SLICE_19 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 3.899ns) by 4.400ns + + Physical Path Details: + + Data path SLICE_99 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q1 SLICE_99 (from PHI2_c) +ROUTE 1 2.159 R2C2A.Q1 to R7C9A.D0 Bank_7 +CTOF_DEL --- 0.371 R7C9A.D0 to R7C9A.F0 SLICE_97 +ROUTE 1 1.026 R7C9A.F0 to R5C9C.A0 n2314 +CTOF_DEL --- 0.371 R5C9C.A0 to R5C9C.F0 SLICE_81 +ROUTE 1 0.304 R5C9C.F0 to R5C9D.D1 n26 +CTOF_DEL --- 0.371 R5C9D.D1 to R5C9D.F1 SLICE_18 +ROUTE 8 0.680 R5C9D.F1 to R5C9B.D1 n1326 +CTOF_DEL --- 0.371 R5C9B.D1 to R5C9B.F1 SLICE_76 +ROUTE 2 1.068 R5C9B.F1 to R5C7C.D0 n2458 +CTOF_DEL --- 0.371 R5C7C.D0 to R5C7C.F0 SLICE_91 +ROUTE 1 0.647 R5C7C.F0 to R5C7D.CE PHI2_N_120_enable_5 (to PHI2_c) + -------- + 8.299 (29.1% logic, 70.9% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R2C2A.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R5C7D.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.271ns (weighted slack = -8.542ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in Cmdn8MEGEN_410 (to PHI2_c -) + + Delay: 8.170ns (29.6% logic, 70.4% route), 6 logic levels. + + Constraint Details: + + 8.170ns physical path delay SLICE_99 to SLICE_23 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 3.899ns) by 4.271ns + + Physical Path Details: + + Data path SLICE_99 to SLICE_23: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q1 SLICE_99 (from PHI2_c) +ROUTE 1 2.159 R2C2A.Q1 to R7C9A.D0 Bank_7 +CTOF_DEL --- 0.371 R7C9A.D0 to R7C9A.F0 SLICE_97 +ROUTE 1 1.026 R7C9A.F0 to R5C9C.A0 n2314 +CTOF_DEL --- 0.371 R5C9C.A0 to R5C9C.F0 SLICE_81 +ROUTE 1 0.304 R5C9C.F0 to R5C9D.D1 n26 +CTOF_DEL --- 0.371 R5C9D.D1 to R5C9D.F1 SLICE_18 +ROUTE 8 0.680 R5C9D.F1 to R5C9B.D1 n1326 +CTOF_DEL --- 0.371 R5C9B.D1 to R5C9B.F1 SLICE_76 +ROUTE 2 0.513 R5C9B.F1 to R5C9B.C0 n2458 +CTOF_DEL --- 0.371 R5C9B.C0 to R5C9B.F0 SLICE_76 +ROUTE 1 1.073 R5C9B.F0 to R5C8B.CE PHI2_N_120_enable_4 (to PHI2_c) + -------- + 8.170 (29.6% logic, 70.4% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R2C2A.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_23: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R5C8B.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.250ns (weighted slack = -8.500ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i1 (from PHI2_c +) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 7.776ns (26.3% logic, 73.7% route), 5 logic levels. + + Constraint Details: + + 7.776ns physical path delay SLICE_88 to SLICE_14 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.638ns LSR_SET requirement (totaling 3.526ns) by 4.250ns + + Physical Path Details: + + Data path SLICE_88 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R9C3B.CLK to R9C3B.Q1 SLICE_88 (from PHI2_c) +ROUTE 1 1.616 R9C3B.Q1 to R9C9A.D0 Bank_1 +CTOF_DEL --- 0.371 R9C9A.D0 to R9C9A.F0 SLICE_96 +ROUTE 1 1.583 R9C9A.F0 to R5C9D.A1 n2316 +CTOF_DEL --- 0.371 R5C9D.A1 to R5C9D.F1 SLICE_18 +ROUTE 8 0.947 R5C9D.F1 to R6C9B.C0 n1326 +CTOF_DEL --- 0.371 R6C9B.C0 to R6C9B.F0 SLICE_89 +ROUTE 1 0.497 R6C9B.F0 to R6C9D.C0 n1280 +CTOF_DEL --- 0.371 R6C9D.C0 to R6C9D.F0 SLICE_79 +ROUTE 2 1.089 R6C9D.F0 to R6C7A.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 7.776 (26.3% logic, 73.7% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R9C3B.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R6C7A.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.196ns (weighted slack = -8.392ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i0 (from PHI2_c +) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 7.722ns (31.3% logic, 68.7% route), 6 logic levels. + + Constraint Details: + + 7.722ns physical path delay SLICE_88 to SLICE_14 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.638ns LSR_SET requirement (totaling 3.526ns) by 4.196ns + + Physical Path Details: + + Data path SLICE_88 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R9C3B.CLK to R9C3B.Q0 SLICE_88 (from PHI2_c) +ROUTE 1 1.444 R9C3B.Q0 to R7C9A.C0 Bank_0 +CTOF_DEL --- 0.371 R7C9A.C0 to R7C9A.F0 SLICE_97 +ROUTE 1 1.026 R7C9A.F0 to R5C9C.A0 n2314 +CTOF_DEL --- 0.371 R5C9C.A0 to R5C9C.F0 SLICE_81 +ROUTE 1 0.304 R5C9C.F0 to R5C9D.D1 n26 +CTOF_DEL --- 0.371 R5C9D.D1 to R5C9D.F1 SLICE_18 +ROUTE 8 0.947 R5C9D.F1 to R6C9B.C0 n1326 +CTOF_DEL --- 0.371 R6C9B.C0 to R6C9B.F0 SLICE_89 +ROUTE 1 0.497 R6C9B.F0 to R6C9D.C0 n1280 +CTOF_DEL --- 0.371 R6C9D.C0 to R6C9D.F0 SLICE_79 +ROUTE 2 1.089 R6C9D.F0 to R6C7A.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 7.722 (31.3% logic, 68.7% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R9C3B.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R6C7A.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.179ns (weighted slack = -8.358ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i6 (from PHI2_c +) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 7.705ns (31.3% logic, 68.7% route), 6 logic levels. + + Constraint Details: + + 7.705ns physical path delay SLICE_99 to SLICE_14 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.638ns LSR_SET requirement (totaling 3.526ns) by 4.179ns + + Physical Path Details: + + Data path SLICE_99 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_99 (from PHI2_c) +ROUTE 1 1.956 R2C2A.Q0 to R5C9C.C1 Bank_6 +CTOF_DEL --- 0.371 R5C9C.C1 to R5C9C.F1 SLICE_81 +ROUTE 1 0.497 R5C9C.F1 to R5C9C.C0 n2278 +CTOF_DEL --- 0.371 R5C9C.C0 to R5C9C.F0 SLICE_81 +ROUTE 1 0.304 R5C9C.F0 to R5C9D.D1 n26 +CTOF_DEL --- 0.371 R5C9D.D1 to R5C9D.F1 SLICE_18 +ROUTE 8 0.947 R5C9D.F1 to R6C9B.C0 n1326 +CTOF_DEL --- 0.371 R6C9B.C0 to R6C9B.F0 SLICE_89 +ROUTE 1 0.497 R6C9B.F0 to R6C9D.C0 n1280 +CTOF_DEL --- 0.371 R6C9D.C0 to R6C9D.F0 SLICE_79 +ROUTE 2 1.089 R6C9D.F0 to R6C7A.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 7.705 (31.3% logic, 68.7% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R2C2A.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R6C7A.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + +Warning: 55.096MHz is the maximum frequency for this preference. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY NET "RCLK_c" 283.768000 MHz ; | 283.768 MHz| 116.198 MHz| 4 * + | | | +FREQUENCY NET "PHI2_c" 120.077000 MHz ; | 120.077 MHz| 55.096 MHz| 6 * + | | | +---------------------------------------------------------------------------- + + +2 preferences(marked by "*" above) not met. + +---------------------------------------------------------------------------- +Critical Nets | Loads| Errors| % of total +---------------------------------------------------------------------------- +n1326 | 8| 94| 28.66% + | | | +n26 | 1| 70| 21.34% + | | | +---------------------------------------------------------------------------- + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 + Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Setup): +--------------- + +Timing errors: 328 Score: 909228 +Cumulative negative slack: 648187 + +Constraints cover 489 paths, 2 nets, and 415 connections (62.69% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:30 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf +Design file: ram2gs_lcmxo640c_impl1.ncd +Preference file: ram2gs_lcmxo640c_impl1.prf +Device,speed: LCMXO640C,m +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ; + 383 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.273ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i4 (from RCLK_c +) + Destination: FF Data in IS_FSM__i5 (to RCLK_c +) + + Delay: 0.256ns (49.2% logic, 50.8% route), 1 logic levels. + + Constraint Details: + + 0.256ns physical path delay SLICE_100 to SLICE_100 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.273ns + + Physical Path Details: + + Data path SLICE_100 to SLICE_100: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R4C8B.CLK to R4C8B.Q0 SLICE_100 (from RCLK_c) +ROUTE 1 0.130 R4C8B.Q0 to R4C8B.M1 n736 (to RCLK_c) + -------- + 0.256 (49.2% logic, 50.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_100: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R4C8B.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_100: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R4C8B.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.273ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i8 (from RCLK_c +) + Destination: FF Data in IS_FSM__i9 (to RCLK_c +) + + Delay: 0.256ns (49.2% logic, 50.8% route), 1 logic levels. + + Constraint Details: + + 0.256ns physical path delay SLICE_76 to SLICE_76 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.273ns + + Physical Path Details: + + Data path SLICE_76 to SLICE_76: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R5C9B.CLK to R5C9B.Q0 SLICE_76 (from RCLK_c) +ROUTE 1 0.130 R5C9B.Q0 to R5C9B.M1 n732 (to RCLK_c) + -------- + 0.256 (49.2% logic, 50.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_76: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R5C9B.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_76: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R5C9B.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.273ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i12 (from RCLK_c +) + Destination: FF Data in IS_FSM__i13 (to RCLK_c +) + + Delay: 0.256ns (49.2% logic, 50.8% route), 1 logic levels. + + Constraint Details: + + 0.256ns physical path delay SLICE_77 to SLICE_77 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.273ns + + Physical Path Details: + + Data path SLICE_77 to SLICE_77: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R3C6D.CLK to R3C6D.Q0 SLICE_77 (from RCLK_c) +ROUTE 1 0.130 R3C6D.Q0 to R3C6D.M1 n728 (to RCLK_c) + -------- + 0.256 (49.2% logic, 50.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_77: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R3C6D.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_77: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R3C6D.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.273ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i14 (from RCLK_c +) + Destination: FF Data in IS_FSM__i15 (to RCLK_c +) + + Delay: 0.256ns (49.2% logic, 50.8% route), 1 logic levels. + + Constraint Details: + + 0.256ns physical path delay SLICE_80 to SLICE_80 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.273ns + + Physical Path Details: + + Data path SLICE_80 to SLICE_80: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R3C8C.CLK to R3C8C.Q0 SLICE_80 (from RCLK_c) +ROUTE 1 0.130 R3C8C.Q0 to R3C8C.M1 n726 (to RCLK_c) + -------- + 0.256 (49.2% logic, 50.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_80: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R3C8C.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_80: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R3C8C.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.273ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i10 (from RCLK_c +) + Destination: FF Data in IS_FSM__i11 (to RCLK_c +) + + Delay: 0.256ns (49.2% logic, 50.8% route), 1 logic levels. + + Constraint Details: + + 0.256ns physical path delay SLICE_82 to SLICE_82 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.273ns + + Physical Path Details: + + Data path SLICE_82 to SLICE_82: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R7C9D.CLK to R7C9D.Q0 SLICE_82 (from RCLK_c) +ROUTE 1 0.130 R7C9D.Q0 to R7C9D.M1 n730 (to RCLK_c) + -------- + 0.256 (49.2% logic, 50.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_82: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R7C9D.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_82: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R7C9D.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.273ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i2 (from RCLK_c +) + Destination: FF Data in IS_FSM__i3 (to RCLK_c +) + + Delay: 0.256ns (49.2% logic, 50.8% route), 1 logic levels. + + Constraint Details: + + 0.256ns physical path delay SLICE_84 to SLICE_84 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.273ns + + Physical Path Details: + + Data path SLICE_84 to SLICE_84: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R5C8C.CLK to R5C8C.Q0 SLICE_84 (from RCLK_c) +ROUTE 1 0.130 R5C8C.Q0 to R5C8C.M1 n738 (to RCLK_c) + -------- + 0.256 (49.2% logic, 50.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_84: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R5C8C.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_84: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R5C8C.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.273ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i6 (from RCLK_c +) + Destination: FF Data in IS_FSM__i7 (to RCLK_c +) + + Delay: 0.256ns (49.2% logic, 50.8% route), 1 logic levels. + + Constraint Details: + + 0.256ns physical path delay SLICE_86 to SLICE_86 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.273ns + + Physical Path Details: + + Data path SLICE_86 to SLICE_86: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R5C8D.CLK to R5C8D.Q0 SLICE_86 (from RCLK_c) +ROUTE 1 0.130 R5C8D.Q0 to R5C8D.M1 n734 (to RCLK_c) + -------- + 0.256 (49.2% logic, 50.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_86: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R5C8D.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_86: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R5C8D.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.277ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i0 (from RCLK_c +) + Destination: FF Data in IS_FSM__i1 (to RCLK_c +) + + Delay: 0.260ns (48.5% logic, 51.5% route), 1 logic levels. + + Constraint Details: + + 0.260ns physical path delay SLICE_87 to SLICE_87 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.277ns + + Physical Path Details: + + Data path SLICE_87 to SLICE_87: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R4C5A.CLK to R4C5A.Q0 SLICE_87 (from RCLK_c) +ROUTE 6 0.134 R4C5A.Q0 to R4C5A.M1 nRCS_N_139 (to RCLK_c) + -------- + 0.260 (48.5% logic, 51.5% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_87: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R4C5A.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_87: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R4C5A.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.290ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RASr2_380 (from RCLK_c +) + Destination: FF Data in RASr3_381 (to RCLK_c +) + + Delay: 0.273ns (46.2% logic, 53.8% route), 1 logic levels. + + Constraint Details: + + 0.273ns physical path delay SLICE_74 to SLICE_74 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.290ns + + Physical Path Details: + + Data path SLICE_74 to SLICE_74: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R4C7A.CLK to R4C7A.Q0 SLICE_74 (from RCLK_c) +ROUTE 14 0.147 R4C7A.Q0 to R4C7A.M1 RASr2 (to RCLK_c) + -------- + 0.273 (46.2% logic, 53.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_74: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R4C7A.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_74: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R4C7A.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.301ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i15 (from RCLK_c +) + Destination: FF Data in FS_610_add_4_16 (to RCLK_c +) + FF FS_610__i15 + FF FS_610__i14 + + Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels. + + Constraint Details: + + 0.257ns physical path delay SLICE_1 to SLICE_1 meets + -0.044ns LUT_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.044ns) by 0.301ns + + Physical Path Details: + + Data path SLICE_1 to SLICE_1: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R3C5D.CLK to R3C5D.Q1 SLICE_1 (from RCLK_c) +ROUTE 3 0.131 R3C5D.Q1 to R3C5D.A1 FS_15 (to RCLK_c) + -------- + 0.257 (49.0% logic, 51.0% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R3C5D.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R3C5D.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + +================================================================================ +Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ; + 106 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.361ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted_406 (from PHI2_c -) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 0.342ns (61.7% logic, 38.3% route), 2 logic levels. + + Constraint Details: + + 0.342ns physical path delay SLICE_14 to SLICE_14 meets + -0.019ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.361ns + + Physical Path Details: + + Data path SLICE_14 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R6C7A.CLK to R6C7A.Q0 SLICE_14 (from PHI2_c) +ROUTE 2 0.131 R6C7A.Q0 to R6C7A.A0 C1Submitted +CTOF_DEL --- 0.074 R6C7A.A0 to R6C7A.F0 SLICE_14 +ROUTE 1 0.000 R6C7A.F0 to R6C7A.DI0 n6_adj_3 (to PHI2_c) + -------- + 0.342 (61.7% logic, 38.3% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R6C7A.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R6C7A.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.361ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q ADSubmitted_407 (from PHI2_c -) + Destination: FF Data in ADSubmitted_407 (to PHI2_c -) + + Delay: 0.342ns (61.7% logic, 38.3% route), 2 logic levels. + + Constraint Details: + + 0.342ns physical path delay SLICE_9 to SLICE_9 meets + -0.019ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.361ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R6C9C.CLK to R6C9C.Q0 SLICE_9 (from PHI2_c) +ROUTE 2 0.131 R6C9C.Q0 to R6C9C.A0 ADSubmitted +CTOF_DEL --- 0.074 R6C9C.A0 to R6C9C.F0 SLICE_9 +ROUTE 1 0.000 R6C9C.F0 to R6C9C.DI0 n1413 (to PHI2_c) + -------- + 0.342 (61.7% logic, 38.3% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R6C9C.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R6C9C.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.585ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in XOR8MEG_408 (to PHI2_c -) + + Delay: 0.562ns (37.5% logic, 62.5% route), 2 logic levels. + + Constraint Details: + + 0.562ns physical path delay SLICE_18 to SLICE_49 meets + -0.023ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.023ns) by 0.585ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_49: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R5C9D.CLK to R5C9D.Q0 SLICE_18 (from PHI2_c) +ROUTE 2 0.221 R5C9D.Q0 to R5C8C.B1 CmdEnable +CTOF_DEL --- 0.074 R5C8C.B1 to R5C8C.F1 SLICE_84 +ROUTE 1 0.130 R5C8C.F1 to R5C8A.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 0.562 (37.5% logic, 62.5% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R5C9D.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_49: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R5C8A.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.885ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in CmdUFMCS_412 (to PHI2_c -) + FF CmdUFMCLK_413 + + Delay: 0.862ns (33.1% logic, 66.9% route), 3 logic levels. + + Constraint Details: + + 0.862ns physical path delay SLICE_18 to SLICE_81 meets + -0.023ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.023ns) by 0.885ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_81: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R5C9D.CLK to R5C9D.Q0 SLICE_18 (from PHI2_c) +ROUTE 2 0.145 R5C9D.Q0 to R7C9C.D0 CmdEnable +CTOF_DEL --- 0.074 R7C9C.D0 to R7C9C.F0 SLICE_83 +ROUTE 2 0.196 R7C9C.F0 to R7C9C.A1 n10 +CTOF_DEL --- 0.074 R7C9C.A1 to R7C9C.F1 SLICE_83 +ROUTE 2 0.236 R7C9C.F1 to R5C9C.CE PHI2_N_120_enable_6 (to PHI2_c) + -------- + 0.862 (33.1% logic, 66.9% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R5C9D.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_81: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R5C9C.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.885ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in CmdUFMSDI_414 (to PHI2_c -) + + Delay: 0.862ns (33.1% logic, 66.9% route), 3 logic levels. + + Constraint Details: + + 0.862ns physical path delay SLICE_18 to SLICE_93 meets + -0.023ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.023ns) by 0.885ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R5C9D.CLK to R5C9D.Q0 SLICE_18 (from PHI2_c) +ROUTE 2 0.145 R5C9D.Q0 to R7C9C.D0 CmdEnable +CTOF_DEL --- 0.074 R7C9C.D0 to R7C9C.F0 SLICE_83 +ROUTE 2 0.196 R7C9C.F0 to R7C9C.A1 n10 +CTOF_DEL --- 0.074 R7C9C.A1 to R7C9C.F1 SLICE_83 +ROUTE 2 0.236 R7C9C.F1 to R10C9A.CE PHI2_N_120_enable_6 (to PHI2_c) + -------- + 0.862 (33.1% logic, 66.9% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R5C9D.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R10C9A.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.146ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in Cmdn8MEGEN_410 (to PHI2_c -) + + Delay: 1.123ns (32.0% logic, 68.0% route), 4 logic levels. + + Constraint Details: + + 1.123ns physical path delay SLICE_18 to SLICE_23 meets + -0.023ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.023ns) by 1.146ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_23: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R5C9D.CLK to R5C9D.Q0 SLICE_18 (from PHI2_c) +ROUTE 2 0.145 R5C9D.Q0 to R7C9C.D0 CmdEnable +CTOF_DEL --- 0.074 R7C9C.D0 to R7C9C.F0 SLICE_83 +ROUTE 2 0.300 R7C9C.F0 to R5C9B.A1 n10 +CTOF_DEL --- 0.074 R5C9B.A1 to R5C9B.F1 SLICE_76 +ROUTE 2 0.103 R5C9B.F1 to R5C9B.C0 n2458 +CTOF_DEL --- 0.074 R5C9B.C0 to R5C9B.F0 SLICE_76 +ROUTE 1 0.216 R5C9B.F0 to R5C8B.CE PHI2_N_120_enable_4 (to PHI2_c) + -------- + 1.123 (32.0% logic, 68.0% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R5C9D.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_23: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R5C8B.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.173ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in CmdSubmitted_411 (to PHI2_c -) + + Delay: 1.150ns (31.2% logic, 68.8% route), 4 logic levels. + + Constraint Details: + + 1.150ns physical path delay SLICE_18 to SLICE_19 meets + -0.023ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.023ns) by 1.173ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R5C9D.CLK to R5C9D.Q0 SLICE_18 (from PHI2_c) +ROUTE 2 0.145 R5C9D.Q0 to R7C9C.D0 CmdEnable +CTOF_DEL --- 0.074 R7C9C.D0 to R7C9C.F0 SLICE_83 +ROUTE 2 0.300 R7C9C.F0 to R5C9B.A1 n10 +CTOF_DEL --- 0.074 R5C9B.A1 to R5C9B.F1 SLICE_76 +ROUTE 2 0.216 R5C9B.F1 to R5C7C.D0 n2458 +CTOF_DEL --- 0.074 R5C7C.D0 to R5C7C.F0 SLICE_91 +ROUTE 1 0.130 R5C7C.F0 to R5C7D.CE PHI2_N_120_enable_5 (to PHI2_c) + -------- + 1.150 (31.2% logic, 68.8% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R5C9D.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R5C7D.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.573ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q ADSubmitted_407 (from PHI2_c -) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 1.550ns (26.5% logic, 73.5% route), 4 logic levels. + + Constraint Details: + + 1.550ns physical path delay SLICE_9 to SLICE_18 meets + -0.023ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.023ns) by 1.573ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R6C9C.CLK to R6C9C.Q0 SLICE_9 (from PHI2_c) +ROUTE 2 0.310 R6C9C.Q0 to R5C7A.A0 ADSubmitted +CTOOFX_DEL --- 0.125 R5C7A.A0 to R5C7A.OFX0 i26/SLICE_71 +ROUTE 1 0.296 R5C7A.OFX0 to R4C9A.A0 n13_adj_2 +CTOF_DEL --- 0.074 R4C9A.A0 to R4C9A.F0 SLICE_105 +ROUTE 1 0.318 R4C9A.F0 to R7C9D.B1 n14 +CTOF_DEL --- 0.074 R7C9D.B1 to R7C9D.F1 SLICE_82 +ROUTE 1 0.216 R7C9D.F1 to R5C9D.CE PHI2_N_120_enable_7 (to PHI2_c) + -------- + 1.550 (26.5% logic, 73.5% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R6C9C.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R5C9D.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.708ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted_406 (from PHI2_c -) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 1.685ns (28.5% logic, 71.5% route), 5 logic levels. + + Constraint Details: + + 1.685ns physical path delay SLICE_14 to SLICE_18 meets + -0.023ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.023ns) by 1.708ns + + Physical Path Details: + + Data path SLICE_14 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R6C7A.CLK to R6C7A.Q0 SLICE_14 (from PHI2_c) +ROUTE 2 0.196 R6C7A.Q0 to R6C7A.A1 C1Submitted +CTOF_DEL --- 0.074 R6C7A.A1 to R6C7A.F1 SLICE_14 +ROUTE 1 0.179 R6C7A.F1 to R5C7A.C1 n2284 +CTOOFX_DEL --- 0.121 R5C7A.C1 to R5C7A.OFX0 i26/SLICE_71 +ROUTE 1 0.296 R5C7A.OFX0 to R4C9A.A0 n13_adj_2 +CTOF_DEL --- 0.074 R4C9A.A0 to R4C9A.F0 SLICE_105 +ROUTE 1 0.318 R4C9A.F0 to R7C9D.B1 n14 +CTOF_DEL --- 0.074 R7C9D.B1 to R7C9D.F1 SLICE_82 +ROUTE 1 0.216 R7C9D.F1 to R5C9D.CE PHI2_N_120_enable_7 (to PHI2_c) + -------- + 1.685 (28.5% logic, 71.5% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R6C7A.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R5C9D.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 4.684ns (weighted slack = 9.368ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q XOR8MEG_408 (from PHI2_c -) + Destination: FF Data in RA11_385 (to PHI2_c +) + + Delay: 0.512ns (41.2% logic, 58.8% route), 2 logic levels. + + Constraint Details: + + 0.512ns physical path delay SLICE_49 to SLICE_32 meets + -0.008ns DIN_HLD and + -4.164ns delay constraint less + 0.000ns skew requirement (totaling -4.172ns) by 4.684ns + + Physical Path Details: + + Data path SLICE_49 to SLICE_32: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R5C8A.CLK to R5C8A.Q0 SLICE_49 (from PHI2_c) +ROUTE 1 0.301 R5C8A.Q0 to R2C9A.C0 XOR8MEG +CTOF_DEL --- 0.074 R2C9A.C0 to R2C9A.F0 SLICE_32 +ROUTE 1 0.000 R2C9A.F0 to R2C9A.DI0 RA11_N_184 (to PHI2_c) + -------- + 0.512 (41.2% logic, 58.8% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_49: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R5C8A.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_32: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R2C9A.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference(MIN Delays) | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY NET "RCLK_c" 283.768000 MHz ; | 0.000 ns| 0.273 ns| 1 + | | | +FREQUENCY NET "PHI2_c" 120.077000 MHz ; | 0.000 ns| 0.361 ns| 2 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 + Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 489 paths, 2 nets, and 415 connections (62.69% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 328 (setup), 0 (hold) +Score: 909228 (setup), 0 (hold) +Cumulative negative slack: 648187 (648187+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_bgn.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_bgn.html new file mode 100644 index 0000000..c5459ef --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_bgn.html @@ -0,0 +1,111 @@ + +Bitgen Report + + + + + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_iotiming.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_iotiming.html new file mode 100644 index 0000000..3bd2593 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_iotiming.html @@ -0,0 +1,203 @@ + +I/O Timing Report + + +
    I/O Timing Report
+Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 4
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 5
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: M
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+// Design: RAM2GS
+// Package: TQFP100
+// ncd File: ram2gs_lcmxo640c_impl1.ncd
+// Version: Diamond (64-bit) 3.12.1.454
+// Written on Tue Aug 15 05:03:31 2023
+// M: Minimum Performance Grade
+// iotiming RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml
+
+I/O Timing Report (All units are in ns)
+
+Worst Case Results across Performance Grades (M, 5, 4, 3):
+
+// Input Setup and Hold Times
+
+Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
+----------------------------------------------------------------------
+CROW[0] nCRAS F    -0.236      M       3.076     3
+CROW[1] nCRAS F    -0.216      M       2.985     3
+Din[0]  PHI2  F     6.373      3       2.684     3
+Din[0]  nCCAS F     1.094      3       0.245     3
+Din[1]  PHI2  F     5.890      3       2.684     3
+Din[1]  nCCAS F     1.106      3       0.247     3
+Din[2]  PHI2  F     4.774      3       2.292     3
+Din[2]  nCCAS F     1.207      3       0.231     3
+Din[3]  PHI2  F     8.665      3       1.537     3
+Din[3]  nCCAS F     0.786      3       0.612     3
+Din[4]  PHI2  F     5.483      3       1.881     3
+Din[4]  nCCAS F     1.180      3       0.282     3
+Din[5]  PHI2  F     7.162      3       1.124     3
+Din[5]  nCCAS F     0.802      3       0.635     3
+Din[6]  PHI2  F     8.125      3       1.435     3
+Din[6]  nCCAS F     1.142      3       0.086     3
+Din[7]  PHI2  F     8.015      3       1.300     3
+Din[7]  nCCAS F     1.259      3      -0.010     M
+MAin[0] PHI2  F     6.577      3       0.639     3
+MAin[0] nCRAS F    -0.004      M       2.291     3
+MAin[1] PHI2  F     6.880      3       1.958     3
+MAin[1] nCRAS F     1.424      3       1.006     3
+MAin[2] PHI2  F     4.559      3       0.456     3
+MAin[2] nCRAS F    -0.209      M       2.966     3
+MAin[3] PHI2  F     5.604      3      -0.096     M
+MAin[3] nCRAS F    -0.323      M       3.369     3
+MAin[4] PHI2  F     6.263      3      -0.211     M
+MAin[4] nCRAS F    -0.086      M       2.536     3
+MAin[5] PHI2  F     4.291      3       0.703     3
+MAin[5] nCRAS F     1.052      3       1.326     3
+MAin[6] PHI2  F     5.837      3      -0.133     M
+MAin[6] nCRAS F    -0.017      M       2.334     3
+MAin[7] PHI2  F     6.302      3      -0.241     M
+MAin[7] nCRAS F    -0.106      M       2.631     3
+MAin[8] nCRAS F    -0.086      M       2.542     3
+MAin[9] nCRAS F     0.549      3       1.796     3
+PHI2    RCLK  R     4.937      3      -0.562     M
+UFMSDO  RCLK  R     2.296      3      -0.152     M
+nCCAS   RCLK  R     1.639      3      -0.029     M
+nCCAS   nCRAS F    -0.229      M       3.059     3
+nCRAS   RCLK  R     1.104      3       0.341     3
+nFWE    PHI2  F     5.086      3       1.672     3
+nFWE    nCRAS F     0.037      3       2.231     3
+
+
+// Clock to Output Delay
+
+Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
+------------------------------------------------------------------------
+LED    RCLK  R     7.152         3        1.423          M
+LED    nCRAS F    12.128         3        2.429          M
+RA[0]  RCLK  R     9.839         3        1.974          M
+RA[0]  nCRAS F    12.557         3        2.494          M
+RA[10] RCLK  R     5.747         3        1.141          M
+RA[11] PHI2  R     7.990         3        1.574          M
+RA[1]  RCLK  R    10.012         3        2.010          M
+RA[1]  nCRAS F    12.750         3        2.545          M
+RA[2]  RCLK  R    10.522         3        2.116          M
+RA[2]  nCRAS F    12.564         3        2.494          M
+RA[3]  RCLK  R    10.341         3        2.077          M
+RA[3]  nCRAS F    11.973         3        2.372          M
+RA[4]  RCLK  R     9.672         3        1.940          M
+RA[4]  nCRAS F    13.443         3        2.679          M
+RA[5]  RCLK  R     9.440         3        1.890          M
+RA[5]  nCRAS F    10.958         3        2.155          M
+RA[6]  RCLK  R    10.605         3        2.138          M
+RA[6]  nCRAS F    13.114         3        2.628          M
+RA[7]  RCLK  R     8.842         3        1.782          M
+RA[7]  nCRAS F    10.779         3        2.148          M
+RA[8]  RCLK  R    10.258         3        2.067          M
+RA[8]  nCRAS F    12.925         3        2.579          M
+RA[9]  RCLK  R     7.160         3        1.425          M
+RA[9]  nCRAS F     9.857         3        1.950          M
+RBA[0] nCRAS F    10.935         3        2.169          M
+RBA[1] nCRAS F    10.976         3        2.184          M
+RCKE   RCLK  R     5.747         3        1.141          M
+RDQMH  RCLK  R     9.890         3        1.991          M
+RDQML  RCLK  R     9.338         3        1.859          M
+RD[0]  nCCAS F     7.488         3        1.591          M
+RD[1]  nCCAS F     8.012         3        1.701          M
+RD[2]  nCCAS F     8.965         3        1.912          M
+RD[3]  nCCAS F     8.965         3        1.912          M
+RD[4]  nCCAS F     7.951         3        1.691          M
+RD[5]  nCCAS F     7.951         3        1.691          M
+RD[6]  nCCAS F     8.012         3        1.701          M
+RD[7]  nCCAS F     8.384         3        1.785          M
+UFMCLK RCLK  R     7.986         3        1.598          M
+UFMSDI RCLK  R     5.747         3        1.141          M
+nRCAS  RCLK  R     5.747         3        1.141          M
+nRCS   RCLK  R     5.747         3        1.141          M
+nRRAS  RCLK  R     6.929         3        1.373          M
+nRWE   RCLK  R     7.375         3        1.459          M
+nUFMCS RCLK  R     7.996         3        1.601          M
+WARNING: you must also run trce with hold speed: 3
+WARNING: you must also run trce with setup speed: M
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_lattice.synproj b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_lattice.synproj new file mode 100644 index 0000000..b97508a --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_lattice.synproj @@ -0,0 +1,41 @@ +-a "MachXO" +-d LCMXO640C +-t TQFP100 +-s 3 +-frequency 200 +-optimization_goal Balanced +-bram_utilization 100 +-ramstyle Auto +-romstyle auto +-dsp_utilization 100 +-use_dsp 1 +-use_carry_chain 1 +-carry_chain_length 0 +-force_gsr Auto +-resource_sharing 1 +-propagate_constants 1 +-remove_duplicate_regs 1 +-mux_style Auto +-max_fanout 1000 +-fsm_encoding_style Auto +-twr_paths 3 +-fix_gated_clocks 1 +-loop_limit 1950 + + + +-use_io_insertion 1 +-resolve_mixed_drivers 0 +-use_io_reg auto + + +-lpf 1 +-p "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C" +-ver "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v" +-top RAM2GS + + +-p "C:/lscc/diamond/3.12/ispfpga/mj5g00/data" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C" + +-ngd "RAM2GS_LCMXO640C_impl1.ngd" + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.asd b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.asd new file mode 100644 index 0000000..a2decba --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.asd @@ -0,0 +1,13 @@ +[ActiveSupport MAP] +Device = LCMXO640C; +Package = TQFP100; +Performance = 3; +LUTS_avail = 640; +LUTS_used = 142; +FF_avail = 640; +FF_used = 102; +INPUT_LVCMOS33 = 26; +OUTPUT_LVCMOS33 = 33; +BIDI_LVCMOS33 = 8; +IO_avail = 74; +IO_used = 67; diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.cam b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.cam new file mode 100644 index 0000000..99dec6c --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.cam @@ -0,0 +1,99 @@ +[ START MERGED ] +nCRAS_N_9 nCRAS_c +nCCAS_N_3 nCCAS_c +n2477 Ready +nFWE_N_5 nFWE_c +PHI2_N_120 PHI2_c +n1425 nRowColSel_N_34 +nRWE_N_176 nRWE_N_177 +RASr2_N_63 RASr2 +n1426 nRowColSel_N_35 +[ END MERGED ] +[ START CLIPPED ] +GND_net +VCC_net +FS_610_add_4_18/CO1 +FS_610_add_4_18/CO0 +FS_610_add_4_10/CO0 +FS_610_add_4_4/CO0 +FS_610_add_4_12/CO0 +FS_610_add_4_2/CO0 +FS_610_add_4_14/CO0 +FS_610_add_4_6/CO0 +FS_610_add_4_16/CO0 +FS_610_add_4_8/CO0 +[ END CLIPPED ] +[ START DESIGN PREFS ] +SCHEMATIC START ; +# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:03:22 2023 + +SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ; +LOCATE COMP "RD[7]" SITE "71" ; +LOCATE COMP "RD[6]" SITE "70" ; +LOCATE COMP "RD[5]" SITE "69" ; +LOCATE COMP "RD[4]" SITE "68" ; +LOCATE COMP "RD[3]" SITE "67" ; +LOCATE COMP "RD[2]" SITE "66" ; +LOCATE COMP "RD[1]" SITE "65" ; +LOCATE COMP "RD[0]" SITE "64" ; +LOCATE COMP "Dout[7]" SITE "3" ; +LOCATE COMP "Dout[6]" SITE "2" ; +LOCATE COMP "Dout[5]" SITE "5" ; +LOCATE COMP "Dout[4]" SITE "4" ; +LOCATE COMP "Dout[3]" SITE "6" ; +LOCATE COMP "Dout[2]" SITE "8" ; +LOCATE COMP "Dout[1]" SITE "7" ; +LOCATE COMP "Dout[0]" SITE "1" ; +LOCATE COMP "LED" SITE "57" ; +LOCATE COMP "RBA[1]" SITE "83" ; +LOCATE COMP "RBA[0]" SITE "63" ; +LOCATE COMP "RA[11]" SITE "79" ; +LOCATE COMP "RA[10]" SITE "87" ; +LOCATE COMP "RA[9]" SITE "85" ; +LOCATE COMP "RA[8]" SITE "96" ; +LOCATE COMP "RA[7]" SITE "100" ; +LOCATE COMP "RA[6]" SITE "91" ; +LOCATE COMP "RA[5]" SITE "95" ; +LOCATE COMP "RA[4]" SITE "99" ; +LOCATE COMP "RA[3]" SITE "97" ; +LOCATE COMP "RA[2]" SITE "94" ; +LOCATE COMP "RA[1]" SITE "89" ; +LOCATE COMP "RA[0]" SITE "98" ; +LOCATE COMP "nRCS" SITE "77" ; +LOCATE COMP "RCKE" SITE "82" ; +LOCATE COMP "nRWE" SITE "72" ; +LOCATE COMP "nRRAS" SITE "73" ; +LOCATE COMP "nRCAS" SITE "78" ; +LOCATE COMP "RDQMH" SITE "76" ; +LOCATE COMP "RDQML" SITE "61" ; +LOCATE COMP "nUFMCS" SITE "53" ; +LOCATE COMP "UFMCLK" SITE "58" ; +LOCATE COMP "UFMSDI" SITE "56" ; +LOCATE COMP "PHI2" SITE "39" ; +LOCATE COMP "MAin[9]" SITE "51" ; +LOCATE COMP "MAin[8]" SITE "50" ; +LOCATE COMP "MAin[7]" SITE "44" ; +LOCATE COMP "MAin[6]" SITE "49" ; +LOCATE COMP "MAin[5]" SITE "45" ; +LOCATE COMP "MAin[4]" SITE "46" ; +LOCATE COMP "MAin[3]" SITE "47" ; +LOCATE COMP "MAin[2]" SITE "37" ; +LOCATE COMP "MAin[1]" SITE "38" ; +LOCATE COMP "MAin[0]" SITE "23" ; +LOCATE COMP "CROW[1]" SITE "34" ; +LOCATE COMP "CROW[0]" SITE "32" ; +LOCATE COMP "Din[7]" SITE "19" ; +LOCATE COMP "Din[6]" SITE "20" ; +LOCATE COMP "Din[5]" SITE "17" ; +LOCATE COMP "Din[4]" SITE "18" ; +LOCATE COMP "Din[3]" SITE "16" ; +LOCATE COMP "Din[2]" SITE "14" ; +LOCATE COMP "Din[1]" SITE "15" ; +LOCATE COMP "Din[0]" SITE "21" ; +LOCATE COMP "nCCAS" SITE "27" ; +LOCATE COMP "nCRAS" SITE "43" ; +LOCATE COMP "nFWE" SITE "22" ; +LOCATE COMP "RCLK" SITE "86" ; +LOCATE COMP "UFMSDO" SITE "55" ; +SCHEMATIC END ; +[ END DESIGN PREFS ] diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.hrr b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.hrr new file mode 100644 index 0000000..c405991 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.hrr @@ -0,0 +1,10 @@ +--------------------------------------------------- +Report for cell RAM2GS + Instance path: RAM2GS + Cell usage: + cell count Res Usage(%) + SLIC 71.00 100.0 + LUT4 124.00 100.0 + IOBUF 67 100.0 + PFUREG 102 100.0 + RIPPLE 9 100.0 diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.ncd b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.ncd new file mode 100644 index 0000000000000000000000000000000000000000..43f5ab2073024f83d3e89b144bd43421e8eea0f6 GIT binary patch literal 107278 zcmeHw2Yg(|asGi7EF#r=fkYLGRJn=+AX5}@04Rt6K_0*&Q4&Oolmv+cRjA@7!@c(! z_uhMzE%zeXa#P$A+p!(niBs)3#c>il;eU4K?R>lY_5q}c6Y0MXKhE*qzTMfK*>7iN z%X@di3BUezOYx(R&CSluu6GX=*No(L{BZSEExDH6H&<@V=W~O#p)JGh<$NtSx}kr4 zfl^92`a9ly?DyX)LfX#d0WENVl;2bq|OiX zmQCusFtuV*=Z2~6CUs7jS~aPpA^LRM+hI~?g{hq;RoV-Ixw)-D)?!rPA`2V}QDhFG z5JeU^6r#uihe8xt;82Jn3mghjWPwAa7g=EGAcz*#d5Kd)1|@D-*uy1m*rGr=C2rWl zFqIn?BB#U+3)NfVo)AT%xlu5bxhF#HmboWF?UuPGLhY7W;843|t}WDVnFS7&Q)Yof z<&;_A5DjG(IMrSjSlSDLqd2dyz@ZQo7C025!UBgvRH8jxae5d{a0V3;oiT+(XGkG2 z8Bud}^sVb2>Pu|MQ1|%6^3JaO`81Ssxy5Wu6aF(#)=cUGxa7$%P;MyU98uF-aU8j zjp{}0*cA6!tyA1*y-snT6+6X!*6bAb#lU2@pLH9QceE$X&(xmS#nyUHcNBDDAhT}^ zYU)%t23awgt(mt4HJP^sHJP^sHQsGUZt0dxxy8U{Hcc#T_HD*w_H7x8Ueg>%iV@B( zJ+)HBEN7QyrOvPSM$s;II`b~8)Vu3wRDhhRQL*4&VMk`M@(5VQTN<)&)BXzc8=XK ze&fX04dc6ZvUfOU_|~1bZ`(UQabsI;&%}=Lz2kc(O!kGf;h~|vdTpS4kn=5AKd_EX zp*YF)mk$*Ebaow!O*^-e>$zrmr+A-*wp@V=IvEo8gbc#LIG?RFlCN1_2sv;MEk=eE z2kxXrWaGDz`?+R$HDtiug!}E`eTEnASHk<;lek|F?{in;ekr`qeTnP)QPeI~hVP zNgVEE2yr4IxsxHK2iEi4iCV3D#0N10$iZlcpb~?aO4gH-irx~Vcg{rr=00YL8{BKN z2m5-1bO9@Qy*S#%?Jd&#p%5}dSX`&#GFn14i05-Mq&Ns%l|wjUWd^ZG?}u=cxdiSf z%2K%UXmgYqf=T=z%BSwLN^w8LnoK%yKZKf0KX5-pn)pE64}m6A65J0JEM5@zL;cD$ zWnsNHKG?($>g|;D3{t(F2(QXzQ{^Z(RF1epEgtGde4*YBRU^|Iy&Y;s<~e#hRE$h` z^meG13b%dEM7<`XPlrl{?dzO+ZE&qWRw|5Cy0JDGTotyc#3~$hm1Kz5?LbwZSHe$uOYpH=4EPrB9IAH8yYUl%K8*1$Tgl~Y+M zHr2>2sa|FzXXIx6rJ1nu(#fp2bTTU~oy-bLC$qNF$*iPwGV8`Bt489@7B_4&tL)-^ zXAf^2)gEP4iPMdwv-FX47C(~C@<-BH0g-gpKqQ@25J`{gAl^sfC{sERFPTmjADL2( z%nZ{_5#Ja|&rpH5!btuM6^Q4H>!d(|%ObG}1*K!Xrm_0hYejoiAUM;tn529H_X6s=N zky+)OM>Lj*YhUi$LCg}i3&tTBC|i zh&qY7h%O;|6wxZ8ONmw!T}ISR)I-!q)K9dA=yIX~qAQ5j5)Bd!5v?N{CR$Ilfv8S2 zLbQ=+6VYa(EksumZ6&&z=o+GHiN=VoBicr^o#=X^9Yi~cZXmjm=q93ZqMM0KU+f~< zO*BEYhv-(K+lX!_+Dmj7k?F+85IvUYaYTq| zuO)gN(d&ucK=ekUHxa#==q*HVC3+jt+lk&m^iHC85xtw}Jw)#%dLPmIi9SH|L81>4 zeVFJYL?0#k7}0%1A1C?*(fvf9B>EK5r-?p8^jV_M5q+NM3q)Te`V!FtL=O^undmD- z4-tKp=xan@C;A4_H;Eo5`g5Xh5q+EJJ4D|l`X13=5d9_5_lbT$^h2V*BKi^0kBNRl z^w&f`CHfiB&x!tq=x>RBLG*V-e^2xeME^+iPelJr^h=^&5&a9%uZjMZ=--I`o#;P^ zena%1M875aFQWe@`X8d-5&fR%e~JE&XrBz_mKOSd7SU{?IYe`b<`K;&Y9(4gw2){K z(PE+_h?Wp7B|4JmD59f@jv+dh=s2R|iB2Fok?16%lZj3tI+f@&qSJ}aAZjBzljtm> zWkhEaokMgk(RoD6iOwflL9~+S0-_6vE+V>^C{I)%DiW25%0v~ScA_d#2T>0PMEyi-h%P4@Ai9EREzuy+5YalKVWRa!8;I&eBSfP_ z8;Ld%Z6?}6bS2SML|cijCc1{`TB0$c>xi}yZ6~^(Xa~_wq8o^AB)W-coaknvTZncM z?IxNa+Cy|J(QQPx6Wu|ym*`HSyNK@2ksanx!$E}dn1fLt4>@)M5=JRrzMo4g4;M^d1I5&c(Wi^5D zoGi{wtGk4#J26bc2Y}yq%W8# zR@ytR&gYqtDaA1t*~HwOo{jw`m24#ak>$>jmDJR8C+UL!mW~%iKV!G=ymhST_v4XN zwIfWyZ|`w*ccNpcZ%yC2v4OG9Slf^F`#_{N^-gl-^s&TYQZD#NQSmsLOBg}Oq^lrg z;_1(%l9AWcizexU|BfYvbN44|Ps8Mhfr;_G^_|;xJbJ9u>BD~B?m`MViwGR$&IqIy z(8@6>qFnG*2>o)8`$z*s8K|bkliY0jpj|sM$7MRRM1Pa!!~89!)Bhv49fL8l%C&YI6#!HdHwvNjiOpv2iOpxQIKa<)^ zWQRv>k}mk~gz;+C8Vnu^iSo?NNzOqZ3j`?TybqLx;~gFCkq%in-dTuAyigVs2`s*O zIBud?rk>qSKGgxOseICWn7`w!vbY~IxzlY8=r#j77VV79g*Hyv}L$%203-B zZ+MT!*e{eL1!H61SKA`XpTfEK5_M`+;s z<(HC@7-wv70yP{(7%wFajx@W~talSfzh`ETOILBNracs=X?w1mhz6^89C|kbduS59P3Q%K(RVDPKG4y1D8zH_uO6E zvukAMF6vt!4Mu_DJK1XaV{oYq0)x_Y<*g%Q{UbwT<3UeThgPZ)Z@I*m+~{%Ae3(DW z${*@M)BKwp48-i0<>iaXpl^>zakLo?Wyg9JgYHPA^c^A_C-OHPzVPJN$ zwEh;#76c7mU+GH{9jepW_STH(iy+ZGwCUx*FQg#*&vW8*#wknRsl z6B~BMJY-;jeQt}ime4fghL8562&L_n1f^+!`H~f5reZ#sfbMY0mn8Zo%qTXdJZmS| zWhR<5DxWkT=C9RwZ0bFKNX5Pt2;8WnNq;0dH~i5>Lo_BH z2l>fNz{oObKFptq$<>GZow7K&H9|w!m-%P|i@al00>@;mQ6<_80Kgv_jy&Puh%c;4oEZ&;6{`PG;n zK%0xcM$JUMWbZrn!n9%1e3-w)n)$XiN%X;PL;{q3WWwGU-Ie^CV$8@zRsC8Pu#ux= zA0R*#^9luaEo#Y!tZ2yRCTYH6$Zl20prv7DOiX)Xf{bz|&4>9*44Orr*LvzSS@3IZr6X^~5&NJ|GmP1VbS`q;DcvWA z!pCQl=mQjf1p_Y3G2Ot1DfIDzbRRNl8LAN((z$3{XG!W;oJi`|dJLAAbXso)+@$$1 zf5Cu=DlfpP7-=7;Fe+@1{g$PL%C^aVU1DAQsuoWaG91lPax}CSU<6Iu9>0Y}ADnEl zN|9310ACzQ^Yy&coR%HCb=wZJ09GydEv6G+TdTC2;;LQqx10Qa1tx!cR{n~~?^kZ} zSF-Y#O@6;yP5yFL{*uY>4+fLJl$F0|^81d*>GK> z9H<(Z{V^e#13k~DWo83&56paO*+usP69t>W;8#D7PbvF-p;`UPIcrci&BTRi$km)} z4!I^-L#~uH;7T(O<{Cn>duyl9(`F2@-o3RWp3z6*Tsj~f7y--CN1@3WV9;jt5oj_7 z__G;(^qGtS_H0HUc_w3kJDbr*oyizr&SvyG$7Brp#%A=p#$*h8hL=J^u*rd77j3ds zpUP)etUQ>?B4#Qdp9*&QC99}m#<{$>>TyigeN`HfuGNLr+hfFD-ekETl~>YzzLaJn@mOAS(AeeMYUUWJoOAfOA2;7Zj*E%om_N?u z%VR43077PetV!lzv>~%U-XwD{;*i-NbCNk2b;#_GJINf3JY@FAo@5S2A2R#nPcjE1 z5SjfkD4By%h|K;tl+3|ML}q_1O6FiRE;J8RnVt@e`h0oND(FGY9B}5$0p|r~-_S7j zJ8&L9pyl(`tbX@#)}Z$^tKWH?HRwCd>USMy4SG(q`W?qvgMQPjez$Sfpw~33-)WpR z=rhggE0(i{dgUjVQiC&jpvfJb3;0Q;SWfd?gqyR~Jh_z0D93samhMUi9 zMUM0ir*hgS7u>whqW#l(l;Hh6^w7xQK&@{qpX0Ni{d`4d#^`T0W&CKpZ_UtfZ(mn` ze;fZ_t8FZ{QDUKM+3-5^CC^_r6uLIFZOGHdnvr@}@4!fR4@Ej{B*f6hEnW0qTdmK0 zE3^%c)XkTC8~tw>caL1Tu4Yn)*O_#=-PT_l?y3#be*-3w{%h+UD44G!1^SlfZ}~RU zn69po{HpvtH*DLs?Shd)^35D5ou4#a1e;?jldrSZ7VMWq>N!Rrqn24Y^Od2|lAE=` z=G&0un?+|bSWUC~la$#ct|ZMJGOd#D^VjCrn%2tIJkdgujrEY+5MkwF&T#*hg!|n7 zEhsE%LY}1JR;#gu?GWl)&^@@ZI5xC#a8&NiCS}UEd7{tcLNuxuX#O0dSECMtfO&lG zcZq%0b)a{wAdd!$(&kbY|0bVj7B!liM>r+raRp&-c+Xw8W}ufJVR;|d#n=4o%6oCm zXSJ6JN)rYBiKBEbP&%iHQa+O&L1}@H&}X5PQ5Q$4JQfy1>Dz!xM(JB|%_!X{C@spE z`V&WKD^NPWiBf)AB7)N5R47gCCA*~1mR1>oF_eA)sN_8F$2Ft$IzefviBfVwi-6LF zO_cI;JTa6C*f>l|dwfP!+?IA^qVyd=CFglNu9@F$g3@vvrJtpy97J5ou^PpoGZddP zyXhiS+E%L^e1y6Lcs-(tSANzkf>(K>HSYV1$vf&e$PKNkJTxj;_9N6h@X2`nFs=<= zTaFXFR^oX56PrgJ1(Y7yL@7T789}MM<|U5OLV{BD{q7{IDDPg0IsbP7mJHK(;+kQ4 zs=&0p2~%?Z#{#CuG-1jQ=tf|gymKe+{7ZrJ_h6csVYalsHT@7^$uRvOt{J9h3QVg_ zm=a7+08Ec>!jzvKkHA!3d6i{N`H6h->tO&(j}w@K&@pTJ9>9`e`fgk^OwSUScEn-& zzJm)=4YGskZ^Vqg1$bn9z8Tky&$9)e zopF4ACdB99@S1^I+uA}`*X4y(%kQnNTz+r&%AWJjZ(EzEq&y|{uAt-o)5*$3z^boICO=jkJ3N1&_A>Z^~{ z`cj(&)2{NYb~$mpUNOj7Ldgd(CyRz)bYyO8FrQ5U8@ffx!769msi5jHcD#x zB=4sojr;Dt1J{gGd8srn_jCM^OrGc*7q=%|IsMqwKs7*gAzBkqE@yxyxa{g89wU9D ztB7Qy>M#Lln+50@QGlM=1Sr3fW=;xg$$P|&)d9MAS^qR#8?@2OA{32`wr;VCbm}gO zw)akrwtIWYEUIY)@WeDO?^!{%a0ZN_*gLb)In7q-{#e0f7G!5dL3VZ%WDdwY-;2G@ z5M>_)s@SF#aLvB=qy%Ld&i7T*po}~$L&+Mp!omC38HLnx3#s#>kUGB!sSHTb@0jp( zgAG^cK;?~P=7fTpEY7_S*9^Aj3b=|Hn>g>88eHrdSJq&=oVbocIdY%mP)+*|Dx8~9 zxUIBsTM>oZ1x>gy++^P2#&OB-fW(3|dGj0vYat3dbyG4ldaD8)R&dR(^*ISHGnT<$ zGBqxFEHZ%UB7Z8zdKWxvBjZ=pw(m-xq^87_^S7eF(yee@`Cbh7%+scoN!Oj@~H-g6nn zceH|c!13K9gUU{e%8n>1yPBwUQ0cnT0^6~;o0Z?Nh{3W$UP+u={ORgSuI756z#vqdjK+ zE(Ed|Y4_rqk#=!{w2TSG=cY#5y*(?tbs}MRFB15X4K(Y-w3KIdIEW8zd(guKy{q!h z)K?#Cn0B=|w2#xQ+VOe)uAxHP{w&|EwvfCufh6r*bn{o<+PJI(Isjz<%bwj7V}QvmT`PFt{KNC;F>uck>EOGO7om)aP9i_!(uwqXCc}f zwVM4+h%!Xe+Zb{PEC#hs=gfjmUl^FD089+FX9}3g8LNTsp9V~_bHVF=))n9D?fS}& zFIiGzbRcVjsg;-++}OR`0&Yzda05-iIgz64rVIIG`&P`Je@lM2BALLrw~De>6LI16 zTL6kqM&rwIZA@Rwi3vJ0g2nr$L+8rnc1oRg<@fR)iSgsh`71@0hZRcKT9jT9Md@G@ zrCGsbwq2}d*+u##0uPDwD+PMZPWYw-i5XjRADIq`D+q`+jvC{LG^b(?%l+SV7KTGn z7!EgKnBko}IarHXz3YK3wt72p%~*S?V6Bo7;JtYotmy#*yZ>uvFLdn6EZ_V=dvqy( zJk2C!f956|EVR}~p;d1}%kjhRijDjrU2L{2zuXuN3FV}!3Bv$44hc`jHN&wV*9^y} zC2-6*^YX!I;ApJc%H_RgXO90P0NzU{1?5;^_ez>))1_$^O`+*O@1T`;{!gB~8j3u6 zmAQyR55}8ggcLh^uLzhHoV;F|ocxdmXb0Y$9fR_5xMol$Q;_zI{k=C$4MINOOg0Yojt)St z>^(?(m-Q-?nJ{-(MKQOviMcFatml?P#JSHmd6;YY0x-syTZ?PP-08SxLwIgt2s0LG zra9v*M^4Gj($Scey@44t0JTw}v!H$0*urb9ExbC4%WIpsba3gdx+K5k8`)BkAJ2`O z$>jG(!*ezCOMD7phU_L>Gh{DJAeymK^Ny*_BzE!K$3^_>3@#vE zXF)j@1?9FTC>>C`v7!9Jb{u)hj|fLjK(xy*+NL&6wgQ8U$zEJDCX-{-?HL<@)0}^x zu+dqRvAE>j69V%eu$Jv2u>q%YuD77v9tGu&CMcb#(X*8D=7!jGT7JD*@T&IDgpKrT zqk7HQI|tW{z0t%TW~|{%gFRigcKtOUZv6xIQ5uZB8!YyAMzMEe6MK$9^spz79>=hU zXXn$K%;n_pO>owqepA;+rE_?ZQJFl{*`D!m{B*0>a@K}6`0R9s)~wAb3ATs!1jJO{ zIeQ7G!2lh%0KF*+(3_h8%>t-B0hZqKE0(jj`~;ve!@10dDE&0ELe@aErI;AbjMc_3 zPaR0QhZ~lAR+P#Gr*sss)1B0@sHFl!`Q)kNKlJUS2XuI6mqqO@32JF^XoA1;;ho)0 z)Hfcq)NIO=p{iWMWP1PLdi~C3ujl5; z`^V*R40&mg*XzD%;Oz-BGtdCZq|DlbYt!v5=i{1(|9bk}vd&K1@fpv4jHWx@yo*Km zYUK-cJO%r_YwJGo%QtD$_Moi5-Az19iw8HPspuoOJ{kB5}{TzR^@*%b%bgj?UyA` z**fAU9?UT{?;&eGU1S~)OOj2{O*19uaR_^XUwX(`yjO$r2fx4UfTmZEwejp@5;)TI z>hb)Qr&o__#IpjBB=7ufjE3td}MhD`Ro}fvG`joUIrz-@Dr5 z;%1S3=KX48p!!q`)u#ZePX|<=)`Y49RX51*(6{HL*DX64bde=>`V|`=s4vDfmw5`V z8K{#9P&1a;e?B!(y;XH*-O>hzGYnL+$5XuPlkU>Fj{SbS#Q_=IXId0L11NqrQ2eYW ziW$Z7=&WZ`-6Jx;Kk*c-StLxbKTT+XXwpuJX+_kt+cRLM3Dl45KGSn8(w_sQKOabcUK8n#y>@3ij40sTy``2s z3@erckR0nih-r=zp zEJ3RU*4OHq!zeR8sY?eSjR~4xYBBy2VEpC4_{*9YcZ{$bG!*g-IGAAJTjXrK(Rep`o}WK`!kEzR{*cC z0$yL)#A_yA8DGGw4`z)i!oZ;lKr&!ofoo>?B3v_%=O=*8*zTF;wE0HuuDZMbICz5&-<_3IN9XY4xtXlfM8#zTnV1~~R~OzNKZ zqq_}T6nnG9_M3q1w*uR5X<|Fe>lf6trq_0{U=}+4YXDFN@a?!}0GDyi0De;f;EbKK z&rc2D^bV@*o|-L*8D7^t&=-mv(9-SOElS@8l)e)veMb|eSt!lxx>d{q^TbJ_D1S0_ zEnvtn9m6%l^fkCYD!TwRf_1zY(?*d%k3%I_g z3D+#R7N%IMDl3#jqxx8&k;HCod~)mscO#}Uk{wHsw& zH8PmyjZFt+VBc>M`#vD{gFx&DnuyIpY-Nftpgq&ReiMi^h;4B;5g4(9xX+0FMuOOk zU9M>ss~o4_=!w`Ak?c(3^}`mg9|B%K3cP-#iC4yJWJ-qjZ>PgnSl`Gas*KC@er*Xz zW!w8LTyu$|am`5nq#(I7WBcnDQ`_F?VFhSJ#8wMDc0K{yroy9Ze_G#Q_kbf!xdB$eg7p4Ze zw;3kuwtUFZr2kPx6`!;Sz8?twG!Xo$CW4))!d;phxaKmg zxMq-UNI;sg0XE$VuZL0-^YZfoGrX!Wh4r1uaN@HTsGk8)KM$aOt_jpEQ!57&GEA+! zYaniFtBmnzYq4MCQuou>7R=0;!rlTV&P9BQ4(X zExWzIUj4wHWqHuz;DIy_7!tFZ4`0(+)Y+*msiK5`DZA6M5}nH--X%%rX6zjO;{k+l z&hn5v3qWPf-sk^EbCs`HJboDt^s8{74>j!)+ojmqYK`?G3-mG{fdh3nSBrS~DxAg? z*`%c~o;x$Z_-VLigZ6n`vv2)eG6pg>pME;^7@&1hc@?Ry?0W_;83cdy)AX-f=zk5+ z|0baSjVAQ7Vn@7GDh7SWEr#M z+avQPjPF}m|0Q7kL%{k6O;|gyc7y7I{GxZpdY1bRw-m7Tl`i3(j%4W}j8-lOkQvyw z;+lc|6>})(YJZOD@{S=m&@E&K=rOn9(rut4#R%0gB{Spg&$d@ z{}qt_6CnM^O{6=~iHG#?otpklMj$4huIX=2!jo{5tPZ>~o}Y+o=Jq;VGl$n&JZJ2Z z{YhBrpIZF>HSqg$;P+=u{AOBeg=l2RjvNN{U?w>mH_7;g7{KUk8#@B886IK7M1@+$m)PDz1|Dp+M2KBtu>U04wGme2; zmkLAEI{^S1fVNzKYX<1oam@hzngwXauGv?o1}H*e8zeUhr3XJD+%LfXg9Ys01F-)D z!2V+suvu0ZzdaNIY{@yXo3gbG%-Hkl)r@COEa85&O<8yViEN#7^#1Sk@|JhNM(7|Qm|O%O?5JV-!%7UJ{DV?AJ%1q^Ksl~ zgL7ZKcWd<;e#K$S`hnrx`g*B{ugtSGx3BN+?H%ai&$fZ#o{jzF+XjZmMz37ow`y=x zZD@F;RJx$IKCr28RYzNI_h|Rf#x0zExNWpPU@u0gl;JVDYT3xZ8gpl0-KH+d&^EBH zw{Oto99T#E$@9^EBUdP|U7X9+Qd@HWmYYrK=G(vL<|lPYo_WFw7sOsJS}k|ET-ZOb zrLULj>%LMF>{wp3>>T2K&ia9M1HCk&a~G#xfG*u3ts#}Q`zq^Yc88tH{zFyvn}(|_ zvR_c)a6VR>@daIf2q#?yWu)3MkXK}e5uY# zp3W+VDbD^!b@sc4>#UU4nLOsBIxG4*J4|u*d)3+hHe6@rh|V~=Q=Jt&owXmPIQu`< z*}jJBtP;@~M;)rOysxv`Vd*z10!TuQmX?O=tUaPLj?6@7y?gH5>j!9qMIdc-CW5kj z5RqkuU@bK9kr1q9cEj~@TtqK?gvQZ}7ljQLfu=`TFZ7n?L@#q2u9xE@df_!TM=xHa zHCXD_QT7PygRW)FFb{E^x{QRgGG3`M_4cPR7;|l1r68Bi4naxaXH%; zFJc;WCV-EyUg-B161^;HxL!_*=!LgZ9K3i@(O~J2;e}qun&{<-hU?|zh+drdn(^XA zK7*x0W_OpUUY0goFQ=sSQsqMu4qm+IX0Uk3>@FRuOYm}3!}W4%L@!R9JlH3rCRto6 z~`Xta9ButG=C615!HaJ8HnQHvAn)=4ei5UN)X z8Cs54wVcp!wVV}EixcYB2`oNZIu99IPE@s=)Nr*di>Sqkbd6d(w2W2`nObO-JsCu& zG+ZrbN7Uj3x}=s)calBoEKEGY;T-*nK#^w2FUoUK|pr{P*TKcW>Uyd|x8iwdKMZV~ES)yjDd*UE~BR^0fud#ksk zFk0+8RMwVWQkM9j^Bb;}l@YDD;cfR;Z$V-7&@HsAP_3+NxK=KRXeEelJ)r17sUJF{LQlOXTB$Z%E0?6TB5&4_z?O`PrWDY(xZB*HC!*<5xqF!?fT0H*ElT%v!pF|A-1OXjGWrJ^F88d6+)fnA za(m0pJsk}LI{o%iBKO*c%N==fU*0((z;b&F%RQY9!#TZ+KaqQ=;d09lxVg`#6y?`2 zCBA04y`|%xj)uv-PURkMxZLu>PG4>(R%E%o#o-=j-*$$__j;9kL&N1xKLT9LJJBG^ z?JfWII5VmlmYd$+kl=iz;c};cn4p+vh}=%V#&UZd-cxQ^;BvLfeNDsVUL29z3D|lmK=PN-(Y z_8d2v@`ictT`KqPhRc0yL~bWio2dC)TRqO{q#5pQdYeMgdZ>S7tWY(tfa%ZC!^pC; z(E0>=HI*Uy^_bQ4A0=y2w(I#Pe+~wC4hw1jTgNB;-Pp^6Ip? zYT5`*0yrbkx~439VM83~3Wp15ll6 z0KAHp7m`#15Lc5RZjUVpar@Irj<^i)A&5IE;{NQz8RDuSiUHtAWkVD5wsI&%WkXUa zoeQ#QjgU=~R5oZ+lb~}JccNIXbeM1JL|F5(DQz$YktX$OCE64uF-NoAJhqN(Q+{mc z#J26bc8;+!hlRf}a>@)w4#4TNqe+?FZoaKYajh7ZS+Rot<>JPVk6mxRZjkcl)7NL@ za_v9OXgx4Ms78$n*FupE*D)e>7?Y%<1c8kv!Cd>S}9dHj?2dZT`Cg_LG^5)wnsl*slZ6b`R zCZQ58Znl;vm|+f^g~Jha<1ymf9yBv;1Tzb)oM57^94*x(HdzmU-lUM~bHrhE%zY1eR`z+FpXdM@4%f{umN_k^- z)MmlzsAU5p)r>(DW=YFM9J*WshN>GdRG*8|>RJF^Wypr{TH&~qQZ+9)A}UY~sk29` zwO;gzCLtHRwenJDja=%N0StA)k)*+qdT#YTjGJ5tald*CW!Cg*nI~?Kgt$>yV0cH0aXVx;h6wO-@U@X z0QOc|xj1SHn}q0Fjgk|Ys8w>(bVxdBm`{M8w$sU{(={jUA}gYkrXJZzQ|o{(?}`*v zgXI+MiR9BMxsxyH3z@>)5a|Vs`m0E_V>GLoFt&c!jxS-b=k9Lt`Zt1wnpUt-4~da2 z<#%q|L9Qg1yGe?lNMChYfZ}R*Q2aHhls7c7B zMht%I6x&whQoDvmoMUrAA|z?MR@z*SL>l13&=(`wbgj!Ns*6)j+Nwxd?NcY8T180O zXN$r%b3e;k7l()A($n)P{V5V2e&;kVh|mEBX>=?hsg$lsM-t4tI({VSKtd8XadW*_ zkbE8q(@DL~GUQJZe=qBT3taDv+e8MB9|TCV`hW7og|nP87-ob}|!CJpwG{ zs7awWs1-);+`fB!@7|p|$g>nnyx_h^co~PKP8FU-c{zAiui&I{`?`CTzq!5@oRtj# zqDc@^qg!}K=1a3t9ul{K;T#KVFw`XUfO=pgS%w^_-!2SIM4+XCKurRWj+hBo+y@z94p-^9L@Ar z^8ytstRRR6xjl7yV%fwjCFXG#cxb!@9-0)Ql$mhMayL|`xuH5uf>P9{pj|i8RDEIG zDVvARxwYI+_n@`P2CdbkbZgD}rnk=eXf#`cYfOLOLv@{1%}Gs@v_2%UhPlnGoX14k z3+3F9%iVEqhS+39csM;49CQf}5^GW@F|Aj(^E%7pq`a{l8U;X3E$>(fRR_8(k!sJ~ zwLQB=cJ4Blj~Bj6=&Le;WSWE#qe7=kYn(k--3Kp7#KGz|DmT3}lsjY?DkGCQrNn3~{ z9XsHKFj94_(_@(Ov(oIBYmye!$PzVTRabje14dZbZp$l@gr?SPE+~gpZWhUS3H6ES zF%=%ePLoiH6qhb1d)LXX?@2K(+InyaCX^F(J5q^LiQDsJ;bhh^)m22gA8J-(0io3b zBG}YkgdnF_)gYI4EPPv=&E*aHDW=M3mZBxz^slmV^K*d0l%VRIUQ?dnrRAtrL4 zYuf^aXcGEYwGEr2xI-=t0+35V1{pL7%9Z{n&(6DyPesS;LK^YkO68>Q9s6 zCSn=JRL`nG2IteI60;7h>OwrDN$7K}7bsJuB9}G=J*P=%u(l4W zS4mM&^^9DJo{I%uv3Z8bV7#MN0`ICxXq_4nG(|Yld`V3HGohBJ%ariTlb*@f$Q+G2 z-*yrz(zS2o(rGZdy<`g_NvC<>rH&9QF#TH4?_Fp1VdQ!i^rOwjDA6RKMw3vx=%;;b z+m4&%fXK6jsR>&(JCv?TsgOpdRnI|_)cOG1nuI2uk|C-_mK-NNSJ)bRpnVKUl?R5k z8a1H#99t9m3`weIWslxacYnlYV2o)lC`iXPlB5z^jODq)3jq`@ z4wz}+;y55RP)-{2q}OQots`IB!PfOf!r0(f8v(`|pM*^O&XhB0F9s_$Hc*5vY6N;D zC&sG+FNGR)iV6#?Nf?R>1z=Vk7BDMnq^F44QN9dKoMi#gU&G2N()56rGGIUPaxl;) zISl4!GAQIb8S$?a2F6J1+ywg8B*$K8bb&}h+T;aB%>32D+>CqWgmJI&CqSmTphK+= zI@ARt7z`bBfHek+T8BtG8Fa6acADicZ4}yhid7veyq;c@r}aXbhRQ2>~&)R zFw($0(qqu9cA{gLG~@Tr8prySRdmMon}q?b0Og)! zLZ)2q#CLfilP;OVtDpUZeR2*BI62oQAs3PqxVnCd_FQBO!XtOuBy^%WY1F7o07w$7 zkfUSk@)jUPT_;S}qI4zNI@Bv13&jpL$8UwQHPQn|Ee;iEgBbpALvhWEzS1PXA*sER z=bn1I6gQ4rL4o3Ga?p6qg$C&mMJ}$y_m8Z;cc8V(2*PRv7Pv=27DMx$!oVEzxL1Pl z@4nJQmPVTxO-I;X0orxv4VXcaB1^%BTu9Pfs$;NMu%RH5w4f#dY?s-lB8gQg8sHe= zU7`WAfAe_Jz)!2522@;VKxIRcqBqiNj2g5@Tg~mEz^}^idp9~%D*=A;R-6DCW;ct4 zc@K)KHsDRxh?OngAF;BXvP1t~VPJyiep?ypHw+%i<%Gd#ZuLGsdvUp>7OpUCHFZEz z&v}EFdWEE(o%d4LO6rME_fiKX^@QWS)FDY-wA)KH8+Ft&*{IVtNMF-W)QMYqAGBj6 zxz9?XaoI2dfQIhs|2Di4!5KFE8b)&4g?5hF-VatMSv|R4QWMi&l1_3+b3PE^0XKGY zE_d7aGuFQ8?V+YARc^`$!A1vs#0I1rVkhJuiZDPsZX!)RoXcIhBchXHG0$_u4}$|7 zoJI_q6gHuroF@2aq&OO|m5y1T7gvPYWZ`*7p~$NE7#QhNEL5RMsdg|M)64fo7@#G` z*q#oCUvg@W9l$4qgK+@&(7~^A>V%5=G#Cn9z=xIU(W*j2!Djn@v{QXE1l1~Fo{Vrg z+7~Nu@lT?-)*UI1(1?pCV)An7ry%B?x!mdjrTH3R1;ubl(`)M>) z;|uhN3J=Gil5(i{85FXQ4y2kW zaFhNV{IoEThlN;$j^+yZnLR1)_-_eE6RWpcLx2`)61rG{0B5V)MaZQ|uuPX&_JP7p zpw7a58~WDb5Kb3L!!d*{>+e82x}FPJ)T9DKIv)s{gq?7+swC^j-$m<`6I!Q9VIahC zWKDk$3;;*%cy(M*s{v4s%d>U;3zUc3){fTlK}V+_`C~8omtfXm`vuZ0wn@P(ccNGj zWqcpS&$4+@T$4g&$ZMk|RR4jnFhfK0qqEv9SEysRIMoM!l6I=RR&KQQLon5aY%tX% zFjc1-sEyw!Ar1X2;kl65KP{KrzB^^Flr4~{gTy&7tV0n|g&J!on?m17Q;X=Nsh4un zVAF84dbQQ0lh3FsM@l1f%N+GbBBNR0RB7NqHjC!J^PaTkX>q%Ij9u7|!9qoVwLQ(Y z0;=amBtD2a{6sj+r5m?VjrZ-__rO`EMx9G46LgkVg;=3WtJ1-RBpokYJI$5~()zzf z>$Mgr;A(nUXHUj_$tZvW+n<4jwhGwOZh(z+6~G*RE*#8|xSft^y)A__NkWL}Tr8`Cp*CW=0dPrA3Cv$D3fD9O4M) z@4-P`BsgdiMj$I;f(`FKpsa3wpl?sHa0z^XaZ6nMpQO0y6_`rJk**1&Y8~kCecYO~ zDQ5ov4E|aY%~QJ$Q>GgGsd$V9BV0d*N3Rj%cddY^Xwa zRzi-23h&KxH2yE(s#{p#s>?oLq1y!*2GZTdqL{OP6^{OHf4a+p{_z)siyW-}JKCn& z0q%4|7d?S6MUQMIZ7a*#(tm*CnHGAGR*S<<>WB-PJ5i|QIWYJQq&;0Zs_oOH&>5Q$ zkYj=Wl=3F_Z?WYux-|(cy2R$ffY&6TDG@s_)7{^qk+W@aXGd0R>947|R|ee5{{jOi zv#uy=q?%?>%(ET*oiH%t_*89yg5pS<1er8f5aCZ07`DGhgB1CI#xlzfuoZc@?Ej%H zfV_5@CZWf50|U)tcIEZ56IY>InB!dGXoiXIOrSwp90Ndep^dr$5OjlVo)~Df%#&)&gzU+(dGh-+yeQ}d zi!7i+odgUbDp!c>Bo?ufE;b;E>g5+08S~dNA2QFf)dEzS1ZmVFLW_C;1e)PGCW?7p z>TYS3N(^%6*-9MKptXb}JMB+dfs4RSyBYnY+JnjF*6=_whNfjP%4^&WbEtTRfKuKJ zBrbmh%4=rSe_bwj61}7+I*{ljCTo2OIB0XhL6ZWrv}L$%rov_yqhRLKElXo;)X0EM zaFUlb!Rbl77sG92UwZ_MgJi9vZBxTuQ<7flL%bi(F()1Ajh zSYRyD^u#PVe><|z#@aOTTg!=Hp{fH5HTyAba`}@`UNb|R)XI~-l&Q_4nF+L<3=X=8 z0X=A}7ibeZg*?Je5hiA$r~xKGp`ILOSM31oqt=dGniR@!rg+?or=s-=XjH6Io3Okw z4P5>-l-JDA-wt|X2))`UW*SVa#&|wmI2b21J3SsW2`#w9=0Y5zNytU)jHk;>C1;?S zb8T_QAZsn5LB=^OM$1`XqwX5g9&0%VhL{FkJ40m|iXUzBqWH-+3BD&0qTIo{J{!f) zv3cF?WMu%w2!krWa-`)Pl)uoH$5_#%z;W`Nm#y!)D358k`r@5r{7A}JUnh2)8q=~I zJk(sH4M*8#r6e$A&qrAuBv79wh3Ye*a?1*oRqq`s8#o|;{#4*zSP4#ACC0n1(gqkH zxN|!$kkSV2^R2LuUy~q%)&Xd1)DyIJqAC{YLbOn2#h6AvtKXx>&{(NTqW?;)<#dPv}RR?Vdqr&!NHaqN_SgXQ8!8}Lt8g5Wc0>LYgT2LuA5cg zhte7~qHdH{hPH0Drv0(fnpGJFbti{Y*kP^#hsRPp*pu1=&>2U-L=LAgkITVBb3=wL zx!g!C9(vG{B8k&dNBMKD{$1=S00Wmw7G1W!%^)wcLPo$!OJP`OQaH%X=}Yd+QIuDs z2)|&CNj{v*$uUV?3gjL!99Wo*;Gmd?GR%=m;vh#V(;OJgn_?WaQ_b;9;vmN_(;Rp( zZ3YKj5W$NcsOr~anLrHW1Yl7j&-IvFet7Bhj!bkXoEQdN*v?}sLz2+ zW`#Li1r8O<0ez`S2)(!?dd*qUyn)qLls6rBpY1qZ@Livr741uVN#??>xEfqc=Mfj_ zJms=MxRlLCi5OpF z;9@$GxJXATmr>zTh`c|FxiHSJ0~gbo#6>z&xok|@vNA&=9&g*g#hm{oE^_`?xoi?H zmwi6XC2{b)Sg{>^)RSY}P7rGfhrWAPnhF1ag@jbs3y)U9&QnR6@25Oun^%Zf%6Y3@rih__z_pb(-ZY0XWM7z6|~xkl#ztauayz zG9tuTV$~5wGZKf~jKUh1qOi&l=)yV0%;M|@mu0p-*Q4nIL#PjWB?^ZH6JVfI2{hv@ z%QGx)W?5I~^ZAQ=Hd5|=^anmFIBcjUh5m3NVN{4Q(w$r|(xfa##TcVwtr%dWNg<<$ G9{PVWbU+#a literal 0 HcmV?d00001 diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvho.sdf b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvho.sdf new file mode 100644 index 0000000..1cdd848 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvho.sdf @@ -0,0 +1,3036 @@ +(DELAYFILE + (SDFVERSION "3.0") + (DESIGN "RAM2GS") + (DATE "Tue Aug 15 05:03:24 2023") + (VENDOR "Lattice") + (PROGRAM "ldbanno") + (VERSION "Diamond (64-bit) 3.12.1.454") + (DIVIDER /) + (VOLTAGE 1.26:1.20:1.14) + (PROCESS "default") + (TEMPERATURE -40:25:85) + (TIMESCALE 1ps) + (CELL + (CELLTYPE "SLICE_0") + (INSTANCE SLICE_0I) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_1") + (INSTANCE SLICE_1I) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_2") + (INSTANCE SLICE_2I) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_3") + (INSTANCE SLICE_3I) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_4") + (INSTANCE SLICE_4I) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + ) + ) + (CELL + (CELLTYPE "SLICE_5") + (INSTANCE SLICE_5I) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_6") + (INSTANCE SLICE_6I) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_7") + (INSTANCE SLICE_7I) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_8") + (INSTANCE SLICE_8I) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_9") + (INSTANCE SLICE_9I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_14") + (INSTANCE SLICE_14I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_18") + (INSTANCE SLICE_18I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_19") + (INSTANCE SLICE_19I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_23") + (INSTANCE SLICE_23I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_25") + (INSTANCE SLICE_25I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_26") + (INSTANCE SLICE_26I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_31") + (INSTANCE SLICE_31I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_32") + (INSTANCE SLICE_32I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_34") + (INSTANCE SLICE_34I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_35") + (INSTANCE SLICE_35I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_36") + (INSTANCE SLICE_36I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_43") + (INSTANCE SLICE_43I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_44") + (INSTANCE SLICE_44I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_49") + (INSTANCE SLICE_49I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_56") + (INSTANCE SLICE_56I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_58") + (INSTANCE SLICE_58I) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_60") + (INSTANCE SLICE_60I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_61") + (INSTANCE SLICE_61I) + (DELAY + (ABSOLUTE + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH D0 OFX0 (508:569:631)(508:569:631)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_63") + (INSTANCE SLICE_63I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_64") + (INSTANCE SLICE_64I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_65") + (INSTANCE SLICE_65I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_66") + (INSTANCE SLICE_66I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_67") + (INSTANCE SLICE_67I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_68") + (INSTANCE SLICE_68I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_69") + (INSTANCE SLICE_69I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "RCKEEN_I_0_445_SLICE_70") + (INSTANCE RCKEEN_I_0_445_SLICE_70I) + (DELAY + (ABSOLUTE + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH D0 OFX0 (508:569:631)(508:569:631)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + ) + ) + ) + (CELL + (CELLTYPE "i26_SLICE_71") + (INSTANCE i26_SLICE_71I) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH D0 OFX0 (508:569:631)(508:569:631)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + ) + ) + ) + (CELL + (CELLTYPE "i2099_SLICE_72") + (INSTANCE i2099_SLICE_72I) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + ) + ) + ) + (CELL + (CELLTYPE "i26_adj_28_SLICE_73") + (INSTANCE i26_adj_28_SLICE_73I) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH D0 OFX0 (508:569:631)(508:569:631)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_74") + (INSTANCE SLICE_74I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_75") + (INSTANCE SLICE_75I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_76") + (INSTANCE SLICE_76I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_77") + (INSTANCE SLICE_77I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_78") + (INSTANCE SLICE_78I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_79") + (INSTANCE SLICE_79I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_80") + (INSTANCE SLICE_80I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_81") + (INSTANCE SLICE_81I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_82") + (INSTANCE SLICE_82I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_83") + (INSTANCE SLICE_83I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_84") + (INSTANCE SLICE_84I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_85") + (INSTANCE SLICE_85I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_86") + (INSTANCE SLICE_86I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_87") + (INSTANCE SLICE_87I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_88") + (INSTANCE SLICE_88I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_89") + (INSTANCE SLICE_89I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "SLICE_90") + (INSTANCE SLICE_90I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_91") + (INSTANCE SLICE_91I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_92") + (INSTANCE SLICE_92I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "SLICE_93") + (INSTANCE SLICE_93I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_94") + (INSTANCE SLICE_94I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_95") + (INSTANCE SLICE_95I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_96") + (INSTANCE SLICE_96I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_97") + (INSTANCE SLICE_97I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_98") + (INSTANCE SLICE_98I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "SLICE_99") + (INSTANCE SLICE_99I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_100") + (INSTANCE SLICE_100I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_101") + (INSTANCE SLICE_101I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_102") + (INSTANCE SLICE_102I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_103") + (INSTANCE SLICE_103I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "SLICE_104") + (INSTANCE SLICE_104I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_105") + (INSTANCE SLICE_105I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "RD_7_B") + (INSTANCE RD_7_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD7 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD7 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD7 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD7) (1250:1250:1250)) + (WIDTH (negedge RD7) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_6_B") + (INSTANCE RD_6_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD6 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD6 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD6 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD6) (1250:1250:1250)) + (WIDTH (negedge RD6) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_5_B") + (INSTANCE RD_5_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD5 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD5 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD5 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD5) (1250:1250:1250)) + (WIDTH (negedge RD5) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_4_B") + (INSTANCE RD_4_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD4 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD4 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD4 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD4) (1250:1250:1250)) + (WIDTH (negedge RD4) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_3_B") + (INSTANCE RD_3_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD3 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD3 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD3 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD3) (1250:1250:1250)) + (WIDTH (negedge RD3) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_2_B") + (INSTANCE RD_2_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD2 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD2 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD2 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD2) (1250:1250:1250)) + (WIDTH (negedge RD2) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_1_B") + (INSTANCE RD_1_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD1 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD1 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD1 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD1) (1250:1250:1250)) + (WIDTH (negedge RD1) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_0_B") + (INSTANCE RD_0_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD0 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD0 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD0 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD0) (1250:1250:1250)) + (WIDTH (negedge RD0) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Dout_7_B") + (INSTANCE Dout_7_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout7 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_6_B") + (INSTANCE Dout_6_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout6 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_5_B") + (INSTANCE Dout_5_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout5 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_4_B") + (INSTANCE Dout_4_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout4 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_3_B") + (INSTANCE Dout_3_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout3 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_2_B") + (INSTANCE Dout_2_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout2 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_1_B") + (INSTANCE Dout_1_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout1 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_0_B") + (INSTANCE Dout_0_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout0 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "LEDB") + (INSTANCE LEDI) + (DELAY + (ABSOLUTE + (IOPATH PADDO LEDS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_1_B") + (INSTANCE RBA_1_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RBA1 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_0_B") + (INSTANCE RBA_0_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RBA0 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_11_B") + (INSTANCE RA_11_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA11 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_10_B") + (INSTANCE RA_10_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA10 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_9_B") + (INSTANCE RA_9_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA9 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_8_B") + (INSTANCE RA_8_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA8 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_7_B") + (INSTANCE RA_7_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA7 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_6_B") + (INSTANCE RA_6_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA6 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_5_B") + (INSTANCE RA_5_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA5 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_4_B") + (INSTANCE RA_4_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA4 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_3_B") + (INSTANCE RA_3_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA3 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_2_B") + (INSTANCE RA_2_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA2 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_1_B") + (INSTANCE RA_1_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA1 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_0_B") + (INSTANCE RA_0_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA0 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nRCSB") + (INSTANCE nRCSI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRCSS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RCKEB") + (INSTANCE RCKEI) + (DELAY + (ABSOLUTE + (IOPATH PADDO RCKES (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nRWEB") + (INSTANCE nRWEI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRWES (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nRRASB") + (INSTANCE nRRASI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRRASS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nRCASB") + (INSTANCE nRCASI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRCASS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RDQMHB") + (INSTANCE RDQMHI) + (DELAY + (ABSOLUTE + (IOPATH PADDO RDQMHS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RDQMLB") + (INSTANCE RDQMLI) + (DELAY + (ABSOLUTE + (IOPATH PADDO RDQMLS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nUFMCSB") + (INSTANCE nUFMCSI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nUFMCSS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "UFMCLKB") + (INSTANCE UFMCLKI) + (DELAY + (ABSOLUTE + (IOPATH PADDO UFMCLKS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "UFMSDIB") + (INSTANCE UFMSDII) + (DELAY + (ABSOLUTE + (IOPATH PADDO UFMSDIS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "PHI2B") + (INSTANCE PHI2I) + (DELAY + (ABSOLUTE + (IOPATH PHI2S PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge PHI2S) (1250:1250:1250)) + (WIDTH (negedge PHI2S) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_9_B") + (INSTANCE MAin_9_I) + (DELAY + (ABSOLUTE + (IOPATH MAin9 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin9) (1250:1250:1250)) + (WIDTH (negedge MAin9) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_8_B") + (INSTANCE MAin_8_I) + (DELAY + (ABSOLUTE + (IOPATH MAin8 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin8) (1250:1250:1250)) + (WIDTH (negedge MAin8) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_7_B") + (INSTANCE MAin_7_I) + (DELAY + (ABSOLUTE + (IOPATH MAin7 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin7) (1250:1250:1250)) + (WIDTH (negedge MAin7) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_6_B") + (INSTANCE MAin_6_I) + (DELAY + (ABSOLUTE + (IOPATH MAin6 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin6) (1250:1250:1250)) + (WIDTH (negedge MAin6) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_5_B") + (INSTANCE MAin_5_I) + (DELAY + (ABSOLUTE + (IOPATH MAin5 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin5) (1250:1250:1250)) + (WIDTH (negedge MAin5) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_4_B") + (INSTANCE MAin_4_I) + (DELAY + (ABSOLUTE + (IOPATH MAin4 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin4) (1250:1250:1250)) + (WIDTH (negedge MAin4) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_3_B") + (INSTANCE MAin_3_I) + (DELAY + (ABSOLUTE + (IOPATH MAin3 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin3) (1250:1250:1250)) + (WIDTH (negedge MAin3) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_2_B") + (INSTANCE MAin_2_I) + (DELAY + (ABSOLUTE + (IOPATH MAin2 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin2) (1250:1250:1250)) + (WIDTH (negedge MAin2) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_1_B") + (INSTANCE MAin_1_I) + (DELAY + (ABSOLUTE + (IOPATH MAin1 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin1) (1250:1250:1250)) + (WIDTH (negedge MAin1) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_0_B") + (INSTANCE MAin_0_I) + (DELAY + (ABSOLUTE + (IOPATH MAin0 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin0) (1250:1250:1250)) + (WIDTH (negedge MAin0) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "CROW_1_B") + (INSTANCE CROW_1_I) + (DELAY + (ABSOLUTE + (IOPATH CROW1 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW1) (1250:1250:1250)) + (WIDTH (negedge CROW1) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "CROW_0_B") + (INSTANCE CROW_0_I) + (DELAY + (ABSOLUTE + (IOPATH CROW0 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW0) (1250:1250:1250)) + (WIDTH (negedge CROW0) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_7_B") + (INSTANCE Din_7_I) + (DELAY + (ABSOLUTE + (IOPATH Din7 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din7) (1250:1250:1250)) + (WIDTH (negedge Din7) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_6_B") + (INSTANCE Din_6_I) + (DELAY + (ABSOLUTE + (IOPATH Din6 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din6) (1250:1250:1250)) + (WIDTH (negedge Din6) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_5_B") + (INSTANCE Din_5_I) + (DELAY + (ABSOLUTE + (IOPATH Din5 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din5) (1250:1250:1250)) + (WIDTH (negedge Din5) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_4_B") + (INSTANCE Din_4_I) + (DELAY + (ABSOLUTE + (IOPATH Din4 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din4) (1250:1250:1250)) + (WIDTH (negedge Din4) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_3_B") + (INSTANCE Din_3_I) + (DELAY + (ABSOLUTE + (IOPATH Din3 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din3) (1250:1250:1250)) + (WIDTH (negedge Din3) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_2_B") + (INSTANCE Din_2_I) + (DELAY + (ABSOLUTE + (IOPATH Din2 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din2) (1250:1250:1250)) + (WIDTH (negedge Din2) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_1_B") + (INSTANCE Din_1_I) + (DELAY + (ABSOLUTE + (IOPATH Din1 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din1) (1250:1250:1250)) + (WIDTH (negedge Din1) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_0_B") + (INSTANCE Din_0_I) + (DELAY + (ABSOLUTE + (IOPATH Din0 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din0) (1250:1250:1250)) + (WIDTH (negedge Din0) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "nCCASB") + (INSTANCE nCCASI) + (DELAY + (ABSOLUTE + (IOPATH nCCASS PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nCCASS) (1250:1250:1250)) + (WIDTH (negedge nCCASS) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "nCRASB") + (INSTANCE nCRASI) + (DELAY + (ABSOLUTE + (IOPATH nCRASS PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nCRASS) (1250:1250:1250)) + (WIDTH (negedge nCRASS) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "nFWEB") + (INSTANCE nFWEI) + (DELAY + (ABSOLUTE + (IOPATH nFWES PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nFWES) (1250:1250:1250)) + (WIDTH (negedge nFWES) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RCLKB") + (INSTANCE RCLKI) + (DELAY + (ABSOLUTE + (IOPATH RCLKS PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RCLKS) (1250:1250:1250)) + (WIDTH (negedge RCLKS) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "UFMSDOB") + (INSTANCE UFMSDOI) + (DELAY + (ABSOLUTE + (IOPATH UFMSDOS PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge UFMSDOS) (1250:1250:1250)) + (WIDTH (negedge UFMSDOS) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RAM2GS") + (INSTANCE ) + (DELAY + (ABSOLUTE + (INTERCONNECT SLICE_0I/Q1 SLICE_0I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q1 SLICE_77I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q1 SLICE_88I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q0 SLICE_0I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q0 SLICE_68I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q0 SLICE_88I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_0I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_1I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_2I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_3I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_4I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_5I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_6I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_7I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_8I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_25I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_26I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_31I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_34I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_35I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_36I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_43I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_44I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_56I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_58I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_60I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_61I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_63I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_64I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_65I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_66I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_67I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_68I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_69I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_74I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_76I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_77I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_79I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_80I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_82I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_83I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_84I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_86I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_87I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_91I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_100I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/FCO SLICE_0I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/FCO SLICE_7I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q1 SLICE_1I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q1 SLICE_94I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q1 SLICE_94I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_1I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_69I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_78I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_90I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_90I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/FCO SLICE_1I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/FCO SLICE_8I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q1 SLICE_2I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q1 SLICE_77I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q1 SLICE_88I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q0 SLICE_2I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q0 SLICE_43I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q0 SLICE_77I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/FCO SLICE_2I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q1 SLICE_3I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q1 SLICE_94I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q1 SLICE_94I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q0 SLICE_3I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q0 SLICE_68I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q0 SLICE_69I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q0 SLICE_90I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/FCO SLICE_3I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q1 SLICE_4I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q1 SLICE_43I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q1 SLICE_68I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q0 SLICE_4I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q0 SLICE_68I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/FCO SLICE_6I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_5I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_44I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_56I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_75I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_75I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_78I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_94I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_95I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q0 SLICE_5I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q0 SLICE_56I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q0 SLICE_75I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q0 SLICE_88I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q0 SLICE_95I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q0 SLICE_95I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/FCO SLICE_5I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q1 SLICE_6I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q1 SLICE_68I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q0 SLICE_6I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q0 SLICE_77I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q1 SLICE_7I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q1 SLICE_77I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q1 SLICE_88I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q0 SLICE_7I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q0 SLICE_87I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q0 SLICE_88I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q1 SLICE_8I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q1 SLICE_68I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q1 SLICE_69I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q1 SLICE_90I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q0 SLICE_8I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q0 SLICE_78I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q0 SLICE_90I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q0 SLICE_90I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q0 SLICE_94I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_9I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_14I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_18I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI i26_SLICE_71I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_82I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_83I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_84I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_89I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_89I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_97I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_99I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F1 SLICE_9I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F1 SLICE_14I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F1 SLICE_18I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F1 SLICE_76I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F1 SLICE_82I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F1 SLICE_84I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F1 SLICE_89I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F1 SLICE_89I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_9I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI i26_SLICE_71I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI i26_SLICE_71I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI i26_adj_28_SLICE_73I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI i26_adj_28_SLICE_73I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_76I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_82I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_83I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_84I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_89I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_97I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_98I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/F1 SLICE_9I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/Q0 SLICE_9I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/Q0 i26_SLICE_71I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/F1 SLICE_9I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89I/F1 SLICE_9I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/F0 SLICE_9I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F0 SLICE_9I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F0 SLICE_14I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_9I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_14I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_18I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_19I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_23I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_32I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_49I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_81I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_88I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_91I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_93I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_99I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_101I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_102I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_14I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_23I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_32I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_32I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI i26_adj_28_SLICE_73I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI i26_adj_28_SLICE_73I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_79I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_92I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_92I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_92I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_99I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_14I/Q0 SLICE_14I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_14I/Q0 SLICE_14I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_14I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_76I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_82I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_85I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_86I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_89I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_98I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_105I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_14I/F0 SLICE_14I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_14I/F1 i26_SLICE_71I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_5_I/PADDI SLICE_18I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_5_I/PADDI SLICE_95I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_5_I/PADDI SLICE_103I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96I/F0 SLICE_18I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/F0 SLICE_18I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_2_I/PADDI SLICE_18I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_2_I/PADDI SLICE_96I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_2_I/PADDI SLICE_101I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT i26_adj_28_SLICE_73I/OFX0 SLICE_18I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/F0 SLICE_18I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/F0 SLICE_79I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F0 SLICE_18I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/F1 SLICE_18I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/Q0 SLICE_83I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/Q0 SLICE_84I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/Q1 SLICE_19I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/Q1 SLICE_91I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/Q1 SLICE_100I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19I/Q0 SLICE_19I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19I/Q0 SLICE_100I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/Q0 SLICE_19I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/Q0 SLICE_100I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19I/F0 SLICE_19I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/F0 SLICE_19I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19I/F1 SLICE_67I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19I/F1 SLICE_87I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_23I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI i26_SLICE_71I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI i26_adj_28_SLICE_73I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_76I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_79I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_85I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_91I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_91I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_101I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_105I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_23I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_32I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_86I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_92I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_99I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23I/F1 SLICE_23I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23I/F1 SLICE_49I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23I/F1 SLICE_84I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_23I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_49I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_76I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_83I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_85I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_86I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_91I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_101I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_105I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_105I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56I/Q0 SLICE_23I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56I/Q0 SLICE_32I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_23I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_49I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_86I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_88I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_89I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_93I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23I/F0 SLICE_23I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/F0 SLICE_23I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23I/Q0 SLICE_56I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_25I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_36I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_58I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_60I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_61I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_63I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_67I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 RCKEEN_I_0_445_SLICE_70I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 i2099_SLICE_72I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 i2099_SLICE_72I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_80I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_104I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_25I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_34I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_35I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_35I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_58I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_60I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_63I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_65I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_65I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_66I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_68I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 RCKEEN_I_0_445_SLICE_70I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_74I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_100I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_25I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_34I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_34I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_43I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_44I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_56I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_60I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_63I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_65I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_69I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_75I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_78I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_87I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_95I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_100I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_100I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_102I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_25I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_31I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_31I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_32I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_34I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_34I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_36I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_58I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_58I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_60I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_61I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_63I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 i2099_SLICE_72I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 i2099_SLICE_72I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_78I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_80I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_85I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_90I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_95I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_96I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_97I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_100I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_104I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F0 SLICE_25I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95I/F1 SLICE_25I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_76I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_77I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_80I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_82I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_84I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_86I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_87I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_100I/CE (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_26I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_78I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_83I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_85I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_90I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_95I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_96I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_97I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_98I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 SLICE_26I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 SLICE_58I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 RCKEEN_I_0_445_SLICE_70I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 RCKEEN_I_0_445_SLICE_70I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 SLICE_74I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 SLICE_74I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 SLICE_103I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_26I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_49I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/F0 SLICE_26I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/F1 SLICE_26I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/F1 LEDI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_31I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_58I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_66I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_66I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 RCKEEN_I_0_445_SLICE_70I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 i2099_SLICE_72I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_80I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q1 SLICE_31I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q1 SLICE_84I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q1 SLICE_102I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q1 SLICE_102I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63I/F1 SLICE_31I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63I/F1 SLICE_63I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_31I/F0 SLICE_31I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/Q1 SLICE_31I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/Q1 SLICE_82I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/Q1 SLICE_102I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_31I/Q0 RA_10_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_31I/F1 SLICE_61I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_49I/Q0 SLICE_32I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32I/F0 SLICE_32I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32I/Q0 RA_11_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32I/F1 SLICE_83I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT RCKEEN_I_0_445_SLICE_70I/OFX0 SLICE_34I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_34I/F0 SLICE_34I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/F1 SLICE_34I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/F1 SLICE_58I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/F1 SLICE_60I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_34I/Q0 SLICE_35I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_34I/F1 SLICE_60I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/Q0 SLICE_35I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/Q0 SLICE_60I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/Q0 RCKEI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q1 SLICE_35I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83I/Q0 SLICE_35I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83I/Q0 SLICE_74I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/F0 SLICE_35I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/Q0 SLICE_35I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/F1 SLICE_104I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/Q1 SLICE_67I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/Q1 SLICE_68I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/Q1 SLICE_74I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/F0 SLICE_36I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F1 SLICE_36I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/F1 SLICE_64I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/F1 SLICE_66I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44I/F1 SLICE_43I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44I/F1 SLICE_44I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/F1 SLICE_43I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/F1 SLICE_69I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/F1 SLICE_95I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43I/F1 SLICE_43I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/Q0 SLICE_43I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43I/F0 SLICE_43I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100I/F0 SLICE_43I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100I/F0 SLICE_44I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/F0 SLICE_43I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/F0 SLICE_44I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43I/Q0 UFMCLKI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90I/F0 SLICE_44I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94I/F1 SLICE_44I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94I/F1 SLICE_75I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94I/F1 SLICE_78I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/F1 SLICE_44I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/F1 SLICE_78I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93I/Q0 SLICE_44I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/F1 SLICE_44I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44I/F0 SLICE_44I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44I/Q0 UFMSDII/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_49I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_81I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_86I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_88I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_89I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_49I/F1 SLICE_49I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_49I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI i26_SLICE_71I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI i26_adj_28_SLICE_73I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI i26_adj_28_SLICE_73I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_79I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_81I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_92I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_102I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_103I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_49I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI i26_adj_28_SLICE_73I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI i26_adj_28_SLICE_73I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_76I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_79I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_91I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_91I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_92I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_92I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_102I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_103I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_49I/F0 SLICE_49I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84I/F1 SLICE_49I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/F1 SLICE_56I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/F1 SLICE_78I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/F1 SLICE_95I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56I/F1 SLICE_56I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT UFMSDOI/PADDI SLICE_56I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56I/F0 SLICE_56I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/F0 SLICE_56I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102I/F0 SLICE_58I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F1 SLICE_58I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F1 i2099_SLICE_72I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_58I/OFX0 SLICE_58I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_58I/Q0 nRCASI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60I/F1 SLICE_60I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60I/F1 SLICE_61I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT i2099_SLICE_72I/OFX0 SLICE_60I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60I/F0 SLICE_60I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60I/Q0 nRCSI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q0 SLICE_61I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q0 SLICE_63I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q0 i2099_SLICE_72I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q0 i2099_SLICE_72I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q0 SLICE_87I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q0 SLICE_102I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_61I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_64I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_65I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_65I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_66I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_66I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_80I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100I/F1 SLICE_61I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61I/Q0 SLICE_61I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61I/Q0 nRRASI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61I/OFX0 SLICE_61I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F0 SLICE_63I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102I/F1 SLICE_63I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63I/F0 SLICE_63I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/F0 SLICE_63I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63I/Q0 nRWEI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_64I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_64I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_93I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_93I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_96I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_97I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_98I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_98I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_99I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_99I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_101I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_101I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_103I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_9_I/PADDI SLICE_64I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_9_I/PADDI SLICE_90I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_9_I/PADDI SLICE_93I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_9_I/PADDI SLICE_93I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90I/Q1 SLICE_64I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103I/F0 SLICE_64I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/F1 SLICE_64I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/F1 SLICE_80I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/F1 SLICE_104I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/F0 SLICE_64I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/F1 RA_9_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/Q1 SLICE_65I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/Q1 SLICE_87I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_65I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_66I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_67I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_74I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_80I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_100I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/F0 SLICE_65I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/F1 SLICE_104I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/F0 SLICE_66I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/F0 SLICE_67I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/Q1 SLICE_67I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_67I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 nUFMCSI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/F0 RCKEEN_I_0_445_SLICE_70I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/F1 SLICE_69I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/F0 SLICE_77I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q1 SLICE_74I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q1 SLICE_103I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94I/F0 SLICE_69I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/F0 SLICE_69I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95I/F0 SLICE_69I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q1 RCKEEN_I_0_445_SLICE_70I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q1 RCKEEN_I_0_445_SLICE_70I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q1 SLICE_74I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q1 SLICE_74I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q1 SLICE_103I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/F1 i26_SLICE_71I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/F1 SLICE_83I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F1 i26_SLICE_71I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT i26_SLICE_71I/OFX0 SLICE_105I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F0 SLICE_74I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F0 SLICE_104I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/F0 SLICE_75I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/F0 SLICE_87I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90I/F1 SLICE_75I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83I/F0 SLICE_76I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83I/F0 SLICE_83I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/F1 SLICE_76I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/F1 SLICE_91I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/Q0 SLICE_76I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/Q1 SLICE_76I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77I/F0 SLICE_77I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77I/Q0 SLICE_77I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/Q1 SLICE_77I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77I/F1 SLICE_87I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77I/Q1 SLICE_80I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_7_I/PADDI SLICE_78I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_7_I/PADDI SLICE_96I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_7_I/PADDI SLICE_99I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_6_I/PADDI SLICE_78I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_6_I/PADDI SLICE_97I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_6_I/PADDI SLICE_101I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/Q0 SLICE_101I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/Q1 SLICE_99I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F1 SLICE_79I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89I/F0 SLICE_79I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/Q1 SLICE_79I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_79I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_89I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_92I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_98I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_103I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_105I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_105I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/Q0 SLICE_80I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102I/Q1 SLICE_81I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99I/Q0 SLICE_81I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101I/Q1 SLICE_81I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/F1 SLICE_81I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97I/F0 SLICE_81I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102I/Q0 SLICE_81I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83I/F1 SLICE_81I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83I/F1 SLICE_93I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F0 SLICE_82I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/F0 SLICE_82I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/F0 SLICE_83I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/Q0 SLICE_82I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84I/F0 SLICE_84I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/F0 SLICE_84I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/F0 SLICE_85I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84I/Q0 SLICE_84I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84I/Q1 SLICE_100I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F0 SLICE_85I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/F1 SLICE_85I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/F1 SLICE_86I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/F1 SLICE_105I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT CROW_1_I/PADDI SLICE_85I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT CROW_0_I/PADDI SLICE_85I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/Q0 RBA_0_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/Q1 RBA_1_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/Q0 SLICE_86I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100I/Q1 SLICE_86I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/F1 SLICE_87I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/F0 SLICE_88I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/Q0 SLICE_97I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/Q1 SLICE_96I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89I/Q0 RD_0_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89I/Q1 RD_1_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT MAin_8_I/PADDI SLICE_90I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_8_I/PADDI SLICE_98I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90I/Q0 SLICE_98I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/Q0 RD_6_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/Q1 RD_7_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93I/F0 RDQMHI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93I/F1 RDQMLI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT MAin_4_I/PADDI SLICE_95I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_4_I/PADDI SLICE_97I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_4_I/PADDI SLICE_97I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95I/Q0 SLICE_97I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95I/Q1 SLICE_103I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_3_I/PADDI SLICE_96I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_3_I/PADDI SLICE_96I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_3_I/PADDI SLICE_96I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96I/Q1 SLICE_96I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101I/Q0 SLICE_96I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96I/Q0 SLICE_101I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96I/F1 RA_3_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99I/Q1 SLICE_97I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97I/Q0 SLICE_98I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97I/F1 RA_4_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97I/Q1 SLICE_99I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/F0 RA_8_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/F1 RA_0_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99I/F0 RA_7_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99I/F1 RA_1_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100I/Q0 SLICE_100I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101I/F0 RA_6_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101I/F1 RA_2_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103I/Q0 RD_2_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103I/F1 RA_5_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103I/Q1 RD_3_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/Q0 RD_4_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 RD_7_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 RD_6_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 RD_5_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 RD_4_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 RD_3_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 RD_2_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 RD_1_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 RD_0_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/Q1 RD_5_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_7_I/PADDI Dout_7_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_6_I/PADDI Dout_6_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_5_I/PADDI Dout_5_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_4_I/PADDI Dout_4_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_3_I/PADDI Dout_3_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_2_I/PADDI Dout_2_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_1_I/PADDI Dout_1_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_0_I/PADDI Dout_0_I/PADDO (0:0:0)(0:0:0)) + ) + ) + ) +) diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvho.vho b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvho.vho new file mode 100644 index 0000000..3bd68d2 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvho.vho @@ -0,0 +1,26269 @@ + +-- VHDL netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 + +-- ldbanno -n VHDL -o RAM2GS_LCMXO640C_impl1_mapvho.vho -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd +-- Netlist created on Tue Aug 15 05:03:22 2023 +-- Netlist written on Tue Aug 15 05:03:24 2023 +-- Design is for device LCMXO640C +-- Design is for package TQFP100 +-- Design is for performance grade 3 + +-- entity vmuxregsre + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity vmuxregsre is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre : ENTITY IS TRUE; + + end vmuxregsre; + + architecture Structure of vmuxregsre is + component FL1P3DX + generic (GSR: String); + port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; + CK: in Std_logic; SD: in Std_logic; CD: in Std_logic; + Q: out Std_logic); + end component; + begin + INST01: FL1P3DX + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q); + end Structure; + +-- entity vcc + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity vcc is + port (PWR1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vcc : ENTITY IS TRUE; + + end vcc; + + architecture Structure of vcc is + component VHI + port (Z: out Std_logic); + end component; + begin + INST1: VHI + port map (Z=>PWR1); + end Structure; + +-- entity gnd + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity gnd is + port (PWR0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF gnd : ENTITY IS TRUE; + + end gnd; + + architecture Structure of gnd is + component VLO + port (Z: out Std_logic); + end component; + begin + INST1: VLO + port map (Z=>PWR0); + end Structure; + +-- entity ccu2B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity ccu2B is + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF ccu2B : ENTITY IS TRUE; + + end ccu2B; + + architecture Structure of ccu2B is + component CCU2 + generic (INIT0: String; INIT1: String; INJECT1_0: String; + INJECT1_1: String); + port (CIN: in Std_logic; A0: in Std_logic; B0: in Std_logic; + C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; + B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; + S0: out Std_logic; S1: out Std_logic; COUT0: out Std_logic; + COUT1: out Std_logic); + end component; + begin + inst1: CCU2 + generic map (INIT0 => "0xfaaa", INIT1 => "0xfaaa", INJECT1_0 => "NO", + INJECT1_1 => "NO") + port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, + C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT0=>CO0, COUT1=>CO1); + end Structure; + +-- entity SLICE_0 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_0 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_0"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_FCI_CLK : VitalDelayType := 0 ns; + tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_0 : ENTITY IS TRUE; + + end SLICE_0; + + architecture Structure of SLICE_0 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal FCI_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_0_FS_610_add_4_8_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_0_FS_610_add_4_8_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i7: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_0_FS_610_add_4_8_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i6: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_0_FS_610_add_4_8_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_8: ccu2B + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_0_FS_610_add_4_8_S0, + S1=>SLICE_0_FS_610_add_4_8_S1, CO0=>open, CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, + FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_FCI_CLK : x01 := '0'; + VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => FCI_dly, + TestSignalName => "FCI", + TestDelay => tisd_FCI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_FCI_CLK_noedge_posedge, + SetupLow => tsetup_FCI_CLK_noedge_posedge, + HoldHigh => thold_FCI_CLK_noedge_posedge, + HoldLow => thold_FCI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => FCI_CLK_TimingDatash, + Violation => tviol_FCI_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_dly'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_dly'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_dly'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_1 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_1 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_1"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_FCI_CLK : VitalDelayType := 0 ns; + tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_1 : ENTITY IS TRUE; + + end SLICE_1; + + architecture Structure of SLICE_1 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal FCI_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_1_FS_610_add_4_16_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_1_FS_610_add_4_16_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i15: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_1_FS_610_add_4_16_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i14: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_1_FS_610_add_4_16_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_16: ccu2B + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_dly, + S0=>SLICE_1_FS_610_add_4_16_S0, S1=>SLICE_1_FS_610_add_4_16_S1, + CO0=>open, CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, + FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_FCI_CLK : x01 := '0'; + VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => FCI_dly, + TestSignalName => "FCI", + TestDelay => tisd_FCI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_FCI_CLK_noedge_posedge, + SetupLow => tsetup_FCI_CLK_noedge_posedge, + HoldHigh => thold_FCI_CLK_noedge_posedge, + HoldLow => thold_FCI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => FCI_CLK_TimingDatash, + Violation => tviol_FCI_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_dly'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_dly'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_dly'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_2 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_2 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_2"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_FCI_CLK : VitalDelayType := 0 ns; + tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_2 : ENTITY IS TRUE; + + end SLICE_2; + + architecture Structure of SLICE_2 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal FCI_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_2_FS_610_add_4_6_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_2_FS_610_add_4_6_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i5: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_2_FS_610_add_4_6_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i4: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_2_FS_610_add_4_6_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_6: ccu2B + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_2_FS_610_add_4_6_S0, + S1=>SLICE_2_FS_610_add_4_6_S1, CO0=>open, CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, + FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_FCI_CLK : x01 := '0'; + VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => FCI_dly, + TestSignalName => "FCI", + TestDelay => tisd_FCI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_FCI_CLK_noedge_posedge, + SetupLow => tsetup_FCI_CLK_noedge_posedge, + HoldHigh => thold_FCI_CLK_noedge_posedge, + HoldLow => thold_FCI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => FCI_CLK_TimingDatash, + Violation => tviol_FCI_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_dly'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_dly'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_dly'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_3 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_3 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_3"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_FCI_CLK : VitalDelayType := 0 ns; + tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_3 : ENTITY IS TRUE; + + end SLICE_3; + + architecture Structure of SLICE_3 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal FCI_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_3_FS_610_add_4_14_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_3_FS_610_add_4_14_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i13: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_3_FS_610_add_4_14_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i12: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_3_FS_610_add_4_14_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_14: ccu2B + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_dly, + S0=>SLICE_3_FS_610_add_4_14_S0, S1=>SLICE_3_FS_610_add_4_14_S1, + CO0=>open, CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, + FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_FCI_CLK : x01 := '0'; + VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => FCI_dly, + TestSignalName => "FCI", + TestDelay => tisd_FCI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_FCI_CLK_noedge_posedge, + SetupLow => tsetup_FCI_CLK_noedge_posedge, + HoldHigh => thold_FCI_CLK_noedge_posedge, + HoldLow => thold_FCI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => FCI_CLK_TimingDatash, + Violation => tviol_FCI_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_dly'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_dly'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_dly'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity ccu20001 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity ccu20001 is + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF ccu20001 : ENTITY IS TRUE; + + end ccu20001; + + architecture Structure of ccu20001 is + component CCU2 + generic (INIT0: String; INIT1: String; INJECT1_0: String; + INJECT1_1: String); + port (CIN: in Std_logic; A0: in Std_logic; B0: in Std_logic; + C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; + B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; + S0: out Std_logic; S1: out Std_logic; COUT0: out Std_logic; + COUT1: out Std_logic); + end component; + begin + inst1: CCU2 + generic map (INIT0 => "0x0555", INIT1 => "0xfaaa", INJECT1_0 => "NO", + INJECT1_1 => "NO") + port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, + C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT0=>CO0, COUT1=>CO1); + end Structure; + +-- entity SLICE_4 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_4 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_4"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_4 : ENTITY IS TRUE; + + end SLICE_4; + + architecture Structure of SLICE_4 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_4_FS_610_add_4_2_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_4_FS_610_add_4_2_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu20001 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i1: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_4_FS_610_add_4_2_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i0: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_4_FS_610_add_4_2_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_2: ccu20001 + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>GNDI, S0=>SLICE_4_FS_610_add_4_2_S0, + S1=>SLICE_4_FS_610_add_4_2_S1, CO0=>open, CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, Q0_out, Q1_out, FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_dly'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_dly'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_5 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_5 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_5"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_FCI_CLK : VitalDelayType := 0 ns; + tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_5 : ENTITY IS TRUE; + + end SLICE_5; + + architecture Structure of SLICE_5 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal FCI_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_5_FS_610_add_4_12_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_5_FS_610_add_4_12_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i11: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_5_FS_610_add_4_12_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i10: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_5_FS_610_add_4_12_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_12: ccu2B + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_dly, + S0=>SLICE_5_FS_610_add_4_12_S0, S1=>SLICE_5_FS_610_add_4_12_S1, + CO0=>open, CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, + FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_FCI_CLK : x01 := '0'; + VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => FCI_dly, + TestSignalName => "FCI", + TestDelay => tisd_FCI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_FCI_CLK_noedge_posedge, + SetupLow => tsetup_FCI_CLK_noedge_posedge, + HoldHigh => thold_FCI_CLK_noedge_posedge, + HoldLow => thold_FCI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => FCI_CLK_TimingDatash, + Violation => tviol_FCI_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_dly'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_dly'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_dly'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_6 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_6 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_6"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_FCI_CLK : VitalDelayType := 0 ns; + tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_6 : ENTITY IS TRUE; + + end SLICE_6; + + architecture Structure of SLICE_6 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal FCI_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_6_FS_610_add_4_4_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_6_FS_610_add_4_4_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i3: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_6_FS_610_add_4_4_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i2: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_6_FS_610_add_4_4_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_4: ccu2B + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_6_FS_610_add_4_4_S0, + S1=>SLICE_6_FS_610_add_4_4_S1, CO0=>open, CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, + FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_FCI_CLK : x01 := '0'; + VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => FCI_dly, + TestSignalName => "FCI", + TestDelay => tisd_FCI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_FCI_CLK_noedge_posedge, + SetupLow => tsetup_FCI_CLK_noedge_posedge, + HoldHigh => thold_FCI_CLK_noedge_posedge, + HoldLow => thold_FCI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => FCI_CLK_TimingDatash, + Violation => tviol_FCI_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_dly'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_dly'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_dly'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_7 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_7 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_7"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_FCI_CLK : VitalDelayType := 0 ns; + tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_7 : ENTITY IS TRUE; + + end SLICE_7; + + architecture Structure of SLICE_7 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal FCI_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_7_FS_610_add_4_10_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_7_FS_610_add_4_10_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i9: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_7_FS_610_add_4_10_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i8: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_7_FS_610_add_4_10_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_10: ccu2B + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_dly, + S0=>SLICE_7_FS_610_add_4_10_S0, S1=>SLICE_7_FS_610_add_4_10_S1, + CO0=>open, CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, + FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_FCI_CLK : x01 := '0'; + VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => FCI_dly, + TestSignalName => "FCI", + TestDelay => tisd_FCI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_FCI_CLK_noedge_posedge, + SetupLow => tsetup_FCI_CLK_noedge_posedge, + HoldHigh => thold_FCI_CLK_noedge_posedge, + HoldLow => thold_FCI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => FCI_CLK_TimingDatash, + Violation => tviol_FCI_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_dly'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_dly'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_dly'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_8 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_8 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_8"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_FCI_CLK : VitalDelayType := 0 ns; + tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_8 : ENTITY IS TRUE; + + end SLICE_8; + + architecture Structure of SLICE_8 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal FCI_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_8_FS_610_add_4_18_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_8_FS_610_add_4_18_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i17: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_8_FS_610_add_4_18_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i16: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_8_FS_610_add_4_18_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_18: ccu2B + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_dly, + S0=>SLICE_8_FS_610_add_4_18_S0, S1=>SLICE_8_FS_610_add_4_18_S1, + CO0=>open, CO1=>open); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_FCI_CLK : x01 := '0'; + VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => FCI_dly, + TestSignalName => "FCI", + TestDelay => tisd_FCI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_FCI_CLK_noedge_posedge, + SetupLow => tsetup_FCI_CLK_noedge_posedge, + HoldHigh => thold_FCI_CLK_noedge_posedge, + HoldLow => thold_FCI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => FCI_CLK_TimingDatash, + Violation => tviol_FCI_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut4 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut4 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut4 : ENTITY IS TRUE; + + end lut4; + + architecture Structure of lut4 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xDFDF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40002 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40002 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40002 : ENTITY IS TRUE; + + end lut40002; + + architecture Structure of lut40002 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x50DC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity vmuxregsre0003 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity vmuxregsre0003 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre0003 : ENTITY IS TRUE; + + end vmuxregsre0003; + + architecture Structure of vmuxregsre0003 is + component FL1P3IY + generic (GSR: String); + port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; + CK: in Std_logic; SD: in Std_logic; CD: in Std_logic; + Q: out Std_logic); + end component; + begin + INST01: FL1P3IY + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q); + end Structure; + +-- entity inverter + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity inverter is + port (I: in Std_logic; Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF inverter : ENTITY IS TRUE; + + end inverter; + + architecture Structure of inverter is + component INV + port (A: in Std_logic; Z: out Std_logic); + end component; + begin + INST1: INV + port map (A=>I, Z=>Z); + end Structure; + +-- entity SLICE_9 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_9 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_9"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_9 : ENTITY IS TRUE; + + end SLICE_9; + + architecture Structure of SLICE_9 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40002 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + begin + i1_2_lut_3_lut: lut4 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1125_4_lut: lut40002 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + ADSubmitted_407: vmuxregsre0003 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40004 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40004 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40004 : ENTITY IS TRUE; + + end lut40004; + + architecture Structure of lut40004 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xEEEE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40005 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40005 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40005 : ENTITY IS TRUE; + + end lut40005; + + architecture Structure of lut40005 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xE0F0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity vmuxregsre0006 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity vmuxregsre0006 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre0006 : ENTITY IS TRUE; + + end vmuxregsre0006; + + architecture Structure of vmuxregsre0006 is + component FL1P3JY + generic (GSR: String); + port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; + CK: in Std_logic; SD: in Std_logic; PD: in Std_logic; + Q: out Std_logic); + end component; + begin + INST01: FL1P3JY + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q); + end Structure; + +-- entity SLICE_14 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_14 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_14"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_14 : ENTITY IS TRUE; + + end SLICE_14; + + architecture Structure of SLICE_14 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40005 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0006 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + begin + i1988_2_lut: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2062_2_lut_3_lut_4_lut: lut40005 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + C1Submitted_406: vmuxregsre0006 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40007 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40007 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40007 : ENTITY IS TRUE; + + end lut40007; + + architecture Structure of lut40007 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xDFFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40008 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40008 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40008 : ENTITY IS TRUE; + + end lut40008; + + architecture Structure of lut40008 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0800") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_18 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_18 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_18"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_18 : ENTITY IS TRUE; + + end SLICE_18; + + architecture Structure of SLICE_18 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40007 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40008 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i13_4_lut: lut40007 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i3_4_lut_adj_21: lut40008 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CmdEnable_405: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40009 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40009 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40009 : ENTITY IS TRUE; + + end lut40009; + + architecture Structure of lut40009 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0808") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40010 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40010 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40010 : ENTITY IS TRUE; + + end lut40010; + + architecture Structure of lut40010 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFFFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_19 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_19 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_19"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_19 : ENTITY IS TRUE; + + end SLICE_19; + + architecture Structure of SLICE_19 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40009 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40010 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_rep_29: lut40009 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + n2568_001_BUF1_BUF1: lut40010 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + CmdSubmitted_411: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, DI0_dly, CE_dly, CLK_dly, + F0_out, Q0_out, F1_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0 <= F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40011 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40011 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40011 : ENTITY IS TRUE; + + end lut40011; + + architecture Structure of lut40011 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFEFE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40012 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40012 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40012 : ENTITY IS TRUE; + + end lut40012; + + architecture Structure of lut40012 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xCC5C") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_23 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_23 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_23"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_23 : ENTITY IS TRUE; + + end SLICE_23; + + architecture Structure of SLICE_23 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40011 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40012 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_3_lut_adj_2: lut40011 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + Cmdn8MEGEN_I_93_4_lut: lut40012 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + Cmdn8MEGEN_410: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40013 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40013 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40013 : ENTITY IS TRUE; + + end lut40013; + + architecture Structure of lut40013 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x4000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_25 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_25 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_25"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_25 : ENTITY IS TRUE; + + end SLICE_25; + + architecture Structure of SLICE_25 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40010 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40013 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i3_3_lut_4_lut_4_lut: lut40013 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + n2568_000_BUF1_BUF1: lut40010 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + InitReady_394: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, DI0_dly, CE_dly, + CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0 <= F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40014 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40014 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40014 : ENTITY IS TRUE; + + end lut40014; + + architecture Structure of lut40014 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFDFD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_26 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_26 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_26"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_26 : ENTITY IS TRUE; + + end SLICE_26; + + architecture Structure of SLICE_26 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40010 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40014 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2049_3_lut: lut40014 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + m1_lut: lut40010 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + LEDEN_419: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, DI0_dly, CE_dly, CLK_dly, + F0_out, Q0_out, F1_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0 <= F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40015 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40015 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40015 : ENTITY IS TRUE; + + end lut40015; + + architecture Structure of lut40015 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xDDDD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_31 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_31 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_31"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_31 : ENTITY IS TRUE; + + end SLICE_31; + + architecture Structure of SLICE_31 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component vmuxregsre0006 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40011 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40015 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_2_lut: lut40015 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_3_lut_adj_27: lut40011 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + RA10_400: vmuxregsre0006 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, + LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40016 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40016 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40016 : ENTITY IS TRUE; + + end lut40016; + + architecture Structure of lut40016 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xC6C6") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_32 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_32 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_32"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_32 : ENTITY IS TRUE; + + end SLICE_32; + + architecture Structure of SLICE_32 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40016 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + Din_7_I_0_462_i6_2_lut_rep_35: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RA11_I_54_3_lut: lut40016 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + RA11_385: vmuxregsre0003 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, + LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40017 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40017 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40017 : ENTITY IS TRUE; + + end lut40017; + + architecture Structure of lut40017 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xF8F8") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40018 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40018 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40018 : ENTITY IS TRUE; + + end lut40018; + + architecture Structure of lut40018 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xCACA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_34 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_34 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_34"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_34 : ENTITY IS TRUE; + + end SLICE_34; + + architecture Structure of SLICE_34 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40017 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i78_2_lut_rep_24_3_lut: lut40017 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1259_3_lut: lut40018 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + RCKEEN_401: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40019 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40019 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40019 : ENTITY IS TRUE; + + end lut40019; + + architecture Structure of lut40019 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xBBBB") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40020 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40020 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40020 : ENTITY IS TRUE; + + end lut40020; + + architecture Structure of lut40020 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xCFC8") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_35 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_35 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_35"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_35 : ENTITY IS TRUE; + + end SLICE_35; + + architecture Structure of SLICE_35 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40019 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40020 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut: lut40019 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RCKE_I_0_449_4_lut: lut40020 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CASr2_383: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + RCKE_395: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_36 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_36 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_36"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_36 : ENTITY IS TRUE; + + end SLICE_36; + + architecture Structure of SLICE_36 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40010 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40015 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i771_2_lut_rep_26_2_lut: lut40015 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + n2568_002_BUF1_BUF1: lut40010 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + Ready_404: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, + Q0_out, F1_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0 <= F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40021 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40021 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40021 : ENTITY IS TRUE; + + end lut40021; + + architecture Structure of lut40021 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x3A0A") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40022 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40022 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40022 : ENTITY IS TRUE; + + end lut40022; + + architecture Structure of lut40022 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xACAC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_43 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_43 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_43"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_43 : ENTITY IS TRUE; + + end SLICE_43; + + architecture Structure of SLICE_43 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40022 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i919_4_lut: lut40021 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i886_3_lut: lut40022 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + UFMCLK_416: vmuxregsre0003 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40023 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40023 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40023 : ENTITY IS TRUE; + + end lut40023; + + architecture Structure of lut40023 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFEFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40024 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40024 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40024 : ENTITY IS TRUE; + + end lut40024; + + architecture Structure of lut40024 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xF202") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_44 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_44 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_44"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_44 : ENTITY IS TRUE; + + end SLICE_44; + + architecture Structure of SLICE_44 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40023 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40024 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_19_4_lut: lut40023 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + n2454_bdd_3_lut_4_lut: lut40024 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + UFMSDI_417: vmuxregsre0003 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, + F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40025 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40025 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40025 : ENTITY IS TRUE; + + end lut40025; + + architecture Structure of lut40025 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFEFA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40026 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40026 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40026 : ENTITY IS TRUE; + + end lut40026; + + architecture Structure of lut40026 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0020") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_49 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_49 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_49"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_49 : ENTITY IS TRUE; + + end SLICE_49; + + architecture Structure of SLICE_49 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40025 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40026 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2028_4_lut: lut40025 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i3_4_lut_adj_12: lut40026 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + XOR8MEG_408: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40027 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40027 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40027 : ENTITY IS TRUE; + + end lut40027; + + architecture Structure of lut40027 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xCCC5") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_56 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_56 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_56"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_56 : ENTITY IS TRUE; + + end SLICE_56; + + architecture Structure of SLICE_56 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40027 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_3_lut_adj_4: lut4 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + n8MEGEN_I_14_4_lut: lut40027 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + n8MEGEN_418: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40028 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40028 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40028 : ENTITY IS TRUE; + + end lut40028; + + architecture Structure of lut40028 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x7F2F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40029 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40029 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40029 : ENTITY IS TRUE; + + end lut40029; + + architecture Structure of lut40029 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xBFBF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity vmuxregsre0030 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity vmuxregsre0030 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre0030 : ENTITY IS TRUE; + + end vmuxregsre0030; + + architecture Structure of vmuxregsre0030 is + component FL1P3BX + generic (GSR: String); + port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; + CK: in Std_logic; SD: in Std_logic; PD: in Std_logic; + Q: out Std_logic); + end component; + begin + INST01: FL1P3BX + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q); + end Structure; + +-- entity selmux2 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity selmux2 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF selmux2 : ENTITY IS TRUE; + + end selmux2; + + architecture Structure of selmux2 is + component MUX21 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + begin + INST1: MUX21 + port map (D0=>D0, D1=>D1, SD=>SD, Z=>Z); + end Structure; + +-- entity SLICE_58 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_58 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_58"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; + Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_58 : ENTITY IS TRUE; + + end SLICE_58; + + architecture Structure of SLICE_58 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal SLICE_58_SLICE_58_K1_H1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_58_i2095_GATE_H0: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40028 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40029 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0030 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + begin + SLICE_58_K1: lut40028 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, + Z=>SLICE_58_SLICE_58_K1_H1); + i2095_GATE: lut40029 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, + Z=>SLICE_58_i2095_GATE_H0); + DRIVEGND: gnd + port map (PWR0=>GNDI); + nRCAS_398: vmuxregsre0030 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + SLICE_58_K0K1MUX: selmux2 + port map (D0=>SLICE_58_i2095_GATE_H0, D1=>SLICE_58_SLICE_58_K1_H1, + SD=>M0_ipd, Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, M0_ipd, CE_dly, CLK_dly, OFX0_out, Q0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + OFX0_zd := OFX0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 7 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40031 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40031 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40031 : ENTITY IS TRUE; + + end lut40031; + + architecture Structure of lut40031 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFA88") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40032 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40032 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40032 : ENTITY IS TRUE; + + end lut40032; + + architecture Structure of lut40032 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xCFDD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_60 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_60 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_60"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_60 : ENTITY IS TRUE; + + end SLICE_60; + + architecture Structure of SLICE_60 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0030 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40031 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40032 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1234_4_lut_4_lut: lut40031 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_4_lut_adj_17: lut40032 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nRCS_396: vmuxregsre0030 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40033 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40033 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40033 : ENTITY IS TRUE; + + end lut40033; + + architecture Structure of lut40033 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x7373") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40034 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40034 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40034 : ENTITY IS TRUE; + + end lut40034; + + architecture Structure of lut40034 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFFFE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_61 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_61 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_61"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_61 : ENTITY IS TRUE; + + end SLICE_61; + + architecture Structure of SLICE_61 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal SLICE_61_SLICE_61_K1_H1: Std_logic; + signal SLICE_61_i16_GATE_H0: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0030 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + component lut40033 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + SLICE_61_K1: lut40033 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, + Z=>SLICE_61_SLICE_61_K1_H1); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i16_GATE: lut40034 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, + Z=>SLICE_61_i16_GATE_H0); + nRRAS_397: vmuxregsre0030 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + SLICE_61_K0K1MUX: selmux2 + port map (D0=>SLICE_61_i16_GATE_H0, D1=>SLICE_61_SLICE_61_K1_H1, + SD=>M0_ipd, Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, M0_ipd, CLK_dly, OFX0_out, Q0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + OFX0_zd := OFX0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 7 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40035 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40035 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40035 : ENTITY IS TRUE; + + end lut40035; + + architecture Structure of lut40035 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFF7F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40036 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40036 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40036 : ENTITY IS TRUE; + + end lut40036; + + architecture Structure of lut40036 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xCFC5") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_63 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_63 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_63"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_63 : ENTITY IS TRUE; + + end SLICE_63; + + architecture Structure of SLICE_63 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0030 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40035 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40036 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_4_lut_adj_8: lut40035 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + nRWE_I_0_455_4_lut: lut40036 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nRWE_399: vmuxregsre0030 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40037 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40037 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40037 : ENTITY IS TRUE; + + end lut40037; + + architecture Structure of lut40037 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xCFEE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_64 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_64 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_64"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_64 : ENTITY IS TRUE; + + end SLICE_64; + + architecture Structure of SLICE_64 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40037 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i10_3_lut: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1_4_lut: lut40037 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nRowColSel_402: vmuxregsre0003 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40038 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40038 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40038 : ENTITY IS TRUE; + + end lut40038; + + architecture Structure of lut40038 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x2000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_65 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_65 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_65"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_65 : ENTITY IS TRUE; + + end SLICE_65; + + architecture Structure of SLICE_65 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40038 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + Ready_bdd_4_lut: lut40038 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut_adj_25: lut40004 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + S_FSM_i4: vmuxregsre0003 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40039 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40039 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40039 : ENTITY IS TRUE; + + end lut40039; + + architecture Structure of lut40039 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFFFE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40040 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40040 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40040 : ENTITY IS TRUE; + + end lut40040; + + architecture Structure of lut40040 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x4444") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_66 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_66 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_66"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_66 : ENTITY IS TRUE; + + end SLICE_66; + + architecture Structure of SLICE_66 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40040 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_4_lut: lut40039 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i2057_2_lut: lut40040 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + S_FSM_i3: vmuxregsre0003 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40041 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40041 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40041 : ENTITY IS TRUE; + + end lut40041; + + architecture Structure of lut40041 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x3A3A") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_67 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_67 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_67"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_67 : ENTITY IS TRUE; + + end SLICE_67; + + architecture Structure of SLICE_67 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40019 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40041 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1129_3_lut: lut40041 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1_2_lut_adj_23: lut40019 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + S_FSM_i2: vmuxregsre0003 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, M0_dly, + LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_68 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_68 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_68"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_68 : ENTITY IS TRUE; + + end SLICE_68; + + architecture Structure of SLICE_68 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal M0_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2024_2_lut_rep_28: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2026_4_lut: lut40039 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CASr3_384: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + S_FSM_i1: vmuxregsre + port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + M0_INVERTERIN: inverter + port map (I=>M0_dly, Z=>M0_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40042 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40042 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40042 : ENTITY IS TRUE; + + end lut40042; + + architecture Structure of lut40042 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x8000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_69 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_69 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_69"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_69 : ENTITY IS TRUE; + + end SLICE_69; + + architecture Structure of SLICE_69 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0006 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40042 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i6_4_lut: lut40042 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i11_3_lut: lut40018 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + nUFMCS_415: vmuxregsre0006 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40043 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40043 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40043 : ENTITY IS TRUE; + + end lut40043; + + architecture Structure of lut40043 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x1F1F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40044 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40044 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40044 : ENTITY IS TRUE; + + end lut40044; + + architecture Structure of lut40044 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x5540") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity RCKEEN_I_0_445_SLICE_70 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RCKEEN_I_0_445_SLICE_70 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RCKEEN_I_0_445_SLICE_70"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RCKEEN_I_0_445_SLICE_70 : ENTITY IS TRUE; + + end RCKEEN_I_0_445_SLICE_70; + + architecture Structure of RCKEEN_I_0_445_SLICE_70 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal RCKEEN_I_0_445_SLICE_70_RCKEEN_I_0_445_SLICE_70_K1_H1: Std_logic; + signal RCKEEN_I_0_445_SLICE_70_RCKEEN_I_0_445_GATE_H0: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + component lut40043 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40044 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RCKEEN_I_0_445_SLICE_70_K1: lut40043 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, + Z=>RCKEEN_I_0_445_SLICE_70_RCKEEN_I_0_445_SLICE_70_K1_H1); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RCKEEN_I_0_445_GATE: lut40044 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, + Z=>RCKEEN_I_0_445_SLICE_70_RCKEEN_I_0_445_GATE_H0); + RCKEEN_I_0_445_SLICE_70_K0K1MUX: selmux2 + port map (D0=>RCKEEN_I_0_445_SLICE_70_RCKEEN_I_0_445_GATE_H0, + D1=>RCKEEN_I_0_445_SLICE_70_RCKEEN_I_0_445_SLICE_70_K1_H1, + SD=>M0_ipd, Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M0_ipd, OFX0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + OFX0_zd := OFX0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 7 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40045 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40045 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40045 : ENTITY IS TRUE; + + end lut40045; + + architecture Structure of lut40045 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0080") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40046 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40046 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40046 : ENTITY IS TRUE; + + end lut40046; + + architecture Structure of lut40046 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0004") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity i26_SLICE_71 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity i26_SLICE_71 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "i26_SLICE_71"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + OFX0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF i26_SLICE_71 : ENTITY IS TRUE; + + end i26_SLICE_71; + + architecture Structure of i26_SLICE_71 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + + signal i26_SLICE_71_i26_SLICE_71_K1_H1: Std_logic; + signal i26_SLICE_71_i26_GATE_H0: Std_logic; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + component lut40045 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40046 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i26_SLICE_71_K1: lut40045 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, + Z=>i26_SLICE_71_i26_SLICE_71_K1_H1); + i26_GATE: lut40046 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, + Z=>i26_SLICE_71_i26_GATE_H0); + i26_SLICE_71_K0K1MUX: selmux2 + port map (D0=>i26_SLICE_71_i26_GATE_H0, + D1=>i26_SLICE_71_i26_SLICE_71_K1_H1, SD=>M0_ipd, Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M0_ipd, OFX0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + OFX0_zd := OFX0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 7 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 8 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40047 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40047 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40047 : ENTITY IS TRUE; + + end lut40047; + + architecture Structure of lut40047 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x2F23") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40048 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40048 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40048 : ENTITY IS TRUE; + + end lut40048; + + architecture Structure of lut40048 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x2F2F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity i2099_SLICE_72 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity i2099_SLICE_72 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "i2099_SLICE_72"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF i2099_SLICE_72 : ENTITY IS TRUE; + + end i2099_SLICE_72; + + architecture Structure of i2099_SLICE_72 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + + signal i2099_SLICE_72_i2099_SLICE_72_K1_H1: Std_logic; + signal GNDI: Std_logic; + signal i2099_SLICE_72_i2099_GATE_H0: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + component lut40047 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40048 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2099_SLICE_72_K1: lut40047 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, + Z=>i2099_SLICE_72_i2099_SLICE_72_K1_H1); + i2099_GATE: lut40048 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, + Z=>i2099_SLICE_72_i2099_GATE_H0); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2099_SLICE_72_K0K1MUX: selmux2 + port map (D0=>i2099_SLICE_72_i2099_GATE_H0, + D1=>i2099_SLICE_72_i2099_SLICE_72_K1_H1, SD=>M0_ipd, + Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, M0_ipd, OFX0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + OFX0_zd := OFX0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 7 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40049 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40049 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40049 : ENTITY IS TRUE; + + end lut40049; + + architecture Structure of lut40049 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x4000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40050 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40050 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40050 : ENTITY IS TRUE; + + end lut40050; + + architecture Structure of lut40050 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0002") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity i26_adj_28_SLICE_73 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity i26_adj_28_SLICE_73 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "i26_adj_28_SLICE_73"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + OFX0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF i26_adj_28_SLICE_73 : ENTITY IS TRUE; + + end i26_adj_28_SLICE_73; + + architecture Structure of i26_adj_28_SLICE_73 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + + signal i26_adj_28_SLICE_73_i26_adj_28_SLICE_73_K1_H1: Std_logic; + signal i26_adj_28_SLICE_73_i26_adj_28_GATE_H0: Std_logic; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + component lut40049 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40050 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i26_adj_28_SLICE_73_K1: lut40049 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, + Z=>i26_adj_28_SLICE_73_i26_adj_28_SLICE_73_K1_H1); + i26_adj_28_GATE: lut40050 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, + Z=>i26_adj_28_SLICE_73_i26_adj_28_GATE_H0); + i26_adj_28_SLICE_73_K0K1MUX: selmux2 + port map (D0=>i26_adj_28_SLICE_73_i26_adj_28_GATE_H0, + D1=>i26_adj_28_SLICE_73_i26_adj_28_SLICE_73_K1_H1, SD=>M0_ipd, + Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M0_ipd, OFX0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + OFX0_zd := OFX0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 7 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 8 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40051 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40051 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40051 : ENTITY IS TRUE; + + end lut40051; + + architecture Structure of lut40051 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x1F10") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40052 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40052 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40052 : ENTITY IS TRUE; + + end lut40052; + + architecture Structure of lut40052 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0040") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_74 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_74 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_74"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_74 : ENTITY IS TRUE; + + end SLICE_74; + + architecture Structure of SLICE_74 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40051 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40052 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i35_3_lut_4_lut: lut40051 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i3_4_lut: lut40052 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RASr3_381: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RASr2_380: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40053 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40053 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40053 : ENTITY IS TRUE; + + end lut40053; + + architecture Structure of lut40053 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0200") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_75 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_75 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_75"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_75 : ENTITY IS TRUE; + + end SLICE_75; + + architecture Structure of SLICE_75 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40009 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40053 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut: lut40009 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i7_4_lut: lut40053 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40054 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40054 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40054 : ENTITY IS TRUE; + + end lut40054; + + architecture Structure of lut40054 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x1000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40055 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40055 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40055 : ENTITY IS TRUE; + + end lut40055; + + architecture Structure of lut40055 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xB300") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_76 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_76 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_76"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_76 : ENTITY IS TRUE; + + end SLICE_76; + + architecture Structure of SLICE_76 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40054 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40055 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i5_3_lut_rep_15_4_lut: lut40054 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_4_lut_4_lut: lut40055 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + IS_FSM_i9: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_FSM_i8: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, + Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40056 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40056 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40056 : ENTITY IS TRUE; + + end lut40056; + + architecture Structure of lut40056 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0004") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_77 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_77 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_77"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_77 : ENTITY IS TRUE; + + end SLICE_77; + + architecture Structure of SLICE_77 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40011 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40056 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i3_4_lut_adj_18: lut40056 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1994_3_lut: lut40011 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_FSM_i13: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i12: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40057 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40057 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40057 : ENTITY IS TRUE; + + end lut40057; + + architecture Structure of lut40057 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0101") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_78 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_78 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_78"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_78 : ENTITY IS TRUE; + + end SLICE_78; + + architecture Structure of SLICE_78 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40057 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i5_3_lut_rep_21_4_lut: lut40039 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i2065_2_lut_3_lut: lut40057 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RowA_i7: vmuxregsre0003 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i6: vmuxregsre0003 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40058 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40058 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40058 : ENTITY IS TRUE; + + end lut40058; + + architecture Structure of lut40058 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0202") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40059 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40059 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40059 : ENTITY IS TRUE; + + end lut40059; + + architecture Structure of lut40059 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0400") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_79 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_79 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_79"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_79 : ENTITY IS TRUE; + + end SLICE_79; + + architecture Structure of SLICE_79 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal M0_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40058 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40059 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_25_3_lut: lut40058 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_4_lut: lut40059 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + PHI2r2_377: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CASr_382: vmuxregsre + port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + M0_INVERTERIN: inverter + port map (I=>M0_dly, Z=>M0_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40060 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40060 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40060 : ENTITY IS TRUE; + + end lut40060; + + architecture Structure of lut40060 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFFFD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_80 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_80 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_80"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_80 : ENTITY IS TRUE; + + end SLICE_80; + + architecture Structure of SLICE_80 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40060 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_adj_16: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1_2_lut_3_lut_4_lut_4_lut: lut40060 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + IS_FSM_i15: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i14: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40061 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40061 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40061 : ENTITY IS TRUE; + + end lut40061; + + architecture Structure of lut40061 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x8888") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40062 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40062 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40062 : ENTITY IS TRUE; + + end lut40062; + + architecture Structure of lut40062 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xBFFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_81 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_81 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_81"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_81 : ENTITY IS TRUE; + + end SLICE_81; + + architecture Structure of SLICE_81 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40061 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40062 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1982_2_lut: lut40061 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i12_4_lut: lut40062 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CmdUFMCS_412: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + CmdUFMCLK_413: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40063 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40063 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40063 : ENTITY IS TRUE; + + end lut40063; + + architecture Structure of lut40063 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0302") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_82 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_82 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_82"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_82 : ENTITY IS TRUE; + + end SLICE_82; + + architecture Structure of SLICE_82 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40063 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2052_4_lut: lut40063 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1990_2_lut_rep_17: lut40004 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_FSM_i11: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i10: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_83 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_83 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_83"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_83 : ENTITY IS TRUE; + + end SLICE_83; + + architecture Structure of SLICE_83 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal M0_NOTIN: Std_logic; + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40008 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40026 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_4_lut: lut40008 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i4_4_lut: lut40026 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RASr_379: vmuxregsre + port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + M0_INVERTERIN: inverter + port map (I=>M0_dly, Z=>M0_NOTIN); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_84 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_84 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_84"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_84 : ENTITY IS TRUE; + + end SLICE_84; + + architecture Structure of SLICE_84 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40014 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40056 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_4_lut_adj_11: lut40056 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut_3_lut_adj_5: lut40014 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_FSM_i3: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i2: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_85 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_85 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_85"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_85 : ENTITY IS TRUE; + + end SLICE_85; + + architecture Structure of SLICE_85 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40013 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_4_lut_adj_15: lut40013 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i2004_2_lut_rep_30: lut40004 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RBA_i2: vmuxregsre0003 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RBA_i1: vmuxregsre0003 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40064 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40064 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40064 : ENTITY IS TRUE; + + end lut40064; + + architecture Structure of lut40064 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x1010") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_86 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_86 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_86"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_86 : ENTITY IS TRUE; + + end SLICE_86; + + architecture Structure of SLICE_86 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40009 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40064 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_adj_10: lut40009 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1_2_lut_rep_20_3_lut: lut40064 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + IS_FSM_i7: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i6: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40065 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40065 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40065 : ENTITY IS TRUE; + + end lut40065; + + architecture Structure of lut40065 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xCAC0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_87 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_87 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_87"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_87 : ENTITY IS TRUE; + + end SLICE_87; + + architecture Structure of SLICE_87 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40040 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40065 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_2_lut: lut40040 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i17_4_lut: lut40065 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + IS_FSM_i1: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i0: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40066 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40066 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40066 : ENTITY IS TRUE; + + end lut40066; + + architecture Structure of lut40066 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0062") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_88 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_88 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_88"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_88 : ENTITY IS TRUE; + + end SLICE_88; + + architecture Structure of SLICE_88 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40009 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40066 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + n2452_bdd_2_lut_rep_18_3_lut: lut40009 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_6_bdd_4_lut: lut40066 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + Bank_i1: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + Bank_i0: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_89 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_89 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_89"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_89 : ENTITY IS TRUE; + + end SLICE_89; + + architecture Structure of SLICE_89 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40014 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40064 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_16_3_lut: lut40064 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_3_lut_adj_1: lut40014 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + WRD_i1: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + WRD_i0: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_90 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_90 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_90"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_90 : ENTITY IS TRUE; + + end SLICE_90; + + architecture Structure of SLICE_90 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0006 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2032_2_lut_3_lut_4_lut: lut40039 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i2_2_lut_rep_27: lut40004 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RowA_i9: vmuxregsre0006 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i8: vmuxregsre0003 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40067 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40067 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40067 : ENTITY IS TRUE; + + end lut40067; + + architecture Structure of lut40067 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x8C00") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_91 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_91 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_91"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_91 : ENTITY IS TRUE; + + end SLICE_91; + + architecture Structure of SLICE_91 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40061 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40067 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_33: lut40061 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_4_lut_adj_3: lut40067 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + PHI2r_376: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + PHI2r3_378: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40068 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40068 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40068 : ENTITY IS TRUE; + + end lut40068; + + architecture Structure of lut40068 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x2222") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40069 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40069 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40069 : ENTITY IS TRUE; + + end lut40069; + + architecture Structure of lut40069 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x4040") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_92 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_92 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_92"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_92 : ENTITY IS TRUE; + + end SLICE_92; + + architecture Structure of SLICE_92 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40068 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40069 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_32: lut40068 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_3_lut_rep_31: lut40069 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + WRD_i7: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + WRD_i6: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, + M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40070 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40070 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40070 : ENTITY IS TRUE; + + end lut40070; + + architecture Structure of lut40070 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x7777") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_93 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_93 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_93"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_93 : ENTITY IS TRUE; + + end SLICE_93; + + architecture Structure of SLICE_93 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40019 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40070 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2060_2_lut: lut40070 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1512_2_lut: lut40019 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + CmdUFMSDI_414: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, M0_dly, CE_dly, + CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_94 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_94 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_94"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_94 : ENTITY IS TRUE; + + end SLICE_94; + + architecture Structure of SLICE_94 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40042 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1976_2_lut: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i5_4_lut: lut40042 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40071 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40071 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40071 : ENTITY IS TRUE; + + end lut40071; + + architecture Structure of lut40071 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0001") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_95 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_95 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_95"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_95 : ENTITY IS TRUE; + + end SLICE_95; + + architecture Structure of SLICE_95 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component vmuxregsre0006 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40061 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40071 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_adj_22: lut40061 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2055_3_lut_4_lut: lut40071 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RowA_i5: vmuxregsre0006 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i4: vmuxregsre0003 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_96 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_96 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_96"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_96 : ENTITY IS TRUE; + + end SLICE_96; + + architecture Structure of SLICE_96 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40042 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i4_3_lut: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2020_4_lut: lut40042 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RowA_i3: vmuxregsre0003 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i2: vmuxregsre0003 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_97 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_97 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_97"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_97 : ENTITY IS TRUE; + + end SLICE_97; + + architecture Structure of SLICE_97 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40042 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i5_3_lut: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2018_4_lut: lut40042 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RowA_i1: vmuxregsre0003 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i0: vmuxregsre0003 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_98 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_98 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_98"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_98 : ENTITY IS TRUE; + + end SLICE_98; + + architecture Structure of SLICE_98 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal M1_NOTIN: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal M0_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i1_3_lut: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_9_I_0_427_i9_3_lut: lut40018 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + FWEr_389: vmuxregsre + port map (D0=>M1_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + M1_INVERTERIN: inverter + port map (I=>M1_dly, Z=>M1_NOTIN); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + CBR_390: vmuxregsre + port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + M0_INVERTERIN: inverter + port map (I=>M0_dly, Z=>M0_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_99 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_99 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_99"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_99 : ENTITY IS TRUE; + + end SLICE_99; + + architecture Structure of SLICE_99 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i2_3_lut: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_9_I_0_427_i8_3_lut: lut40018 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + Bank_i7: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + Bank_i6: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40072 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40072 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40072 : ENTITY IS TRUE; + + end lut40072; + + architecture Structure of lut40072 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xF0F7") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40073 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40073 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40073 : ENTITY IS TRUE; + + end lut40073; + + architecture Structure of lut40073 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x08FF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_100 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_100 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_100"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_100 : ENTITY IS TRUE; + + end SLICE_100; + + architecture Structure of SLICE_100 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40072 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40073 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_2_lut_3_lut_4_lut: lut40072 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut_4_lut_adj_7: lut40073 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + IS_FSM_i5: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_FSM_i4: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, + Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_101 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_101 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_101"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_101 : ENTITY IS TRUE; + + end SLICE_101; + + architecture Structure of SLICE_101 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i3_3_lut: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_9_I_0_427_i7_3_lut: lut40018 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + Bank_i5: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + Bank_i4: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_102 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_102 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_102"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_102 : ENTITY IS TRUE; + + end SLICE_102; + + architecture Structure of SLICE_102 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40014 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_adj_26: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + InitReady_bdd_3_lut: lut40014 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + Bank_i3: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + Bank_i2: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, + M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_103 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_103 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_103"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_103 : ENTITY IS TRUE; + + end SLICE_103; + + architecture Structure of SLICE_103 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40014 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i6_3_lut: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_3_lut_adj_14: lut40014 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + WRD_i3: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + WRD_i2: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40074 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40074 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40074 : ENTITY IS TRUE; + + end lut40074; + + architecture Structure of lut40074 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xF0DD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_104 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_104 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_104"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_104 : ENTITY IS TRUE; + + end SLICE_104; + + architecture Structure of SLICE_104 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40074 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + n2414_bdd_2_lut: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + n1_bdd_4_lut: lut40074 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40075 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40075 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40075 : ENTITY IS TRUE; + + end lut40075; + + architecture Structure of lut40075 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x2020") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_105 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_105 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_105"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_105 : ENTITY IS TRUE; + + end SLICE_105; + + architecture Structure of SLICE_105 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40075 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1513_2_lut: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_3_lut_adj_20: lut40075 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + WRD_i5: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + WRD_i4: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, + M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity mjiobuf + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity mjiobuf is + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + + ATTRIBUTE Vital_Level0 OF mjiobuf : ENTITY IS TRUE; + + end mjiobuf; + + architecture Structure of mjiobuf is + component IBPU + port (I: in Std_logic; O: out Std_logic); + end component; + component OBZPU + port (I: in Std_logic; T: in Std_logic; O: out Std_logic); + end component; + begin + INST1: IBPU + port map (I=>PADI, O=>Z); + INST2: OBZPU + port map (I=>I, T=>T, O=>PAD); + end Structure; + +-- entity RD_7_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RD_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_7_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD7 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD7_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD7 : VitalDelayType := 0 ns; + tpw_RD7_posedge : VitalDelayType := 0 ns; + tpw_RD7_negedge : VitalDelayType := 0 ns; + tpd_RD7_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD7: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_7_B : ENTITY IS TRUE; + + end RD_7_B; + + architecture Structure of RD_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD7_ipd : std_logic := 'X'; + signal RD7_out : std_logic := 'Z'; + + component mjiobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_7_713: mjiobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD7_out, + PADI=>RD7_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD7_ipd, RD7, tipd_RD7); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD7_ipd, RD7_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD7_zd : std_logic := 'X'; + VARIABLE RD7_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD7_RD7 : x01 := '0'; + VARIABLE periodcheckinfo_RD7 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD7_ipd, + TestSignalName => "RD7", + Period => tperiod_RD7, + PulseWidthHigh => tpw_RD7_posedge, + PulseWidthLow => tpw_RD7_negedge, + PeriodData => periodcheckinfo_RD7, + Violation => tviol_RD7_RD7, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD7_zd := RD7_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD7_ipd'last_event, + PathDelay => tpd_RD7_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD7, OutSignalName => "RD7", OutTemp => RD7_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD7, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD7, + PathCondition => TRUE)), + GlitchData => RD7_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_6_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RD_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_6_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD6 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD6_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD6 : VitalDelayType := 0 ns; + tpw_RD6_posedge : VitalDelayType := 0 ns; + tpw_RD6_negedge : VitalDelayType := 0 ns; + tpd_RD6_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD6: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_6_B : ENTITY IS TRUE; + + end RD_6_B; + + architecture Structure of RD_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD6_ipd : std_logic := 'X'; + signal RD6_out : std_logic := 'Z'; + + component mjiobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_6_714: mjiobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD6_out, + PADI=>RD6_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD6_ipd, RD6, tipd_RD6); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD6_ipd, RD6_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD6_zd : std_logic := 'X'; + VARIABLE RD6_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD6_RD6 : x01 := '0'; + VARIABLE periodcheckinfo_RD6 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD6_ipd, + TestSignalName => "RD6", + Period => tperiod_RD6, + PulseWidthHigh => tpw_RD6_posedge, + PulseWidthLow => tpw_RD6_negedge, + PeriodData => periodcheckinfo_RD6, + Violation => tviol_RD6_RD6, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD6_zd := RD6_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD6_ipd'last_event, + PathDelay => tpd_RD6_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD6, OutSignalName => "RD6", OutTemp => RD6_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD6, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD6, + PathCondition => TRUE)), + GlitchData => RD6_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_5_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RD_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_5_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD5 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD5_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD5 : VitalDelayType := 0 ns; + tpw_RD5_posedge : VitalDelayType := 0 ns; + tpw_RD5_negedge : VitalDelayType := 0 ns; + tpd_RD5_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD5: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_5_B : ENTITY IS TRUE; + + end RD_5_B; + + architecture Structure of RD_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD5_ipd : std_logic := 'X'; + signal RD5_out : std_logic := 'Z'; + + component mjiobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_5_715: mjiobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD5_out, + PADI=>RD5_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD5_ipd, RD5, tipd_RD5); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD5_ipd, RD5_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD5_zd : std_logic := 'X'; + VARIABLE RD5_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD5_RD5 : x01 := '0'; + VARIABLE periodcheckinfo_RD5 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD5_ipd, + TestSignalName => "RD5", + Period => tperiod_RD5, + PulseWidthHigh => tpw_RD5_posedge, + PulseWidthLow => tpw_RD5_negedge, + PeriodData => periodcheckinfo_RD5, + Violation => tviol_RD5_RD5, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD5_zd := RD5_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD5_ipd'last_event, + PathDelay => tpd_RD5_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD5, OutSignalName => "RD5", OutTemp => RD5_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD5, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD5, + PathCondition => TRUE)), + GlitchData => RD5_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_4_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RD_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_4_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD4 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD4_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD4 : VitalDelayType := 0 ns; + tpw_RD4_posedge : VitalDelayType := 0 ns; + tpw_RD4_negedge : VitalDelayType := 0 ns; + tpd_RD4_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD4: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_4_B : ENTITY IS TRUE; + + end RD_4_B; + + architecture Structure of RD_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD4_ipd : std_logic := 'X'; + signal RD4_out : std_logic := 'Z'; + + component mjiobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_4_716: mjiobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD4_out, + PADI=>RD4_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD4_ipd, RD4, tipd_RD4); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD4_ipd, RD4_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD4_zd : std_logic := 'X'; + VARIABLE RD4_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD4_RD4 : x01 := '0'; + VARIABLE periodcheckinfo_RD4 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD4_ipd, + TestSignalName => "RD4", + Period => tperiod_RD4, + PulseWidthHigh => tpw_RD4_posedge, + PulseWidthLow => tpw_RD4_negedge, + PeriodData => periodcheckinfo_RD4, + Violation => tviol_RD4_RD4, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD4_zd := RD4_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD4_ipd'last_event, + PathDelay => tpd_RD4_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD4, OutSignalName => "RD4", OutTemp => RD4_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD4, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD4, + PathCondition => TRUE)), + GlitchData => RD4_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_3_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RD_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_3_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD3 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD3_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD3 : VitalDelayType := 0 ns; + tpw_RD3_posedge : VitalDelayType := 0 ns; + tpw_RD3_negedge : VitalDelayType := 0 ns; + tpd_RD3_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD3: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_3_B : ENTITY IS TRUE; + + end RD_3_B; + + architecture Structure of RD_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD3_ipd : std_logic := 'X'; + signal RD3_out : std_logic := 'Z'; + + component mjiobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_3_717: mjiobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD3_out, + PADI=>RD3_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD3_ipd, RD3, tipd_RD3); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD3_ipd, RD3_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD3_zd : std_logic := 'X'; + VARIABLE RD3_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD3_RD3 : x01 := '0'; + VARIABLE periodcheckinfo_RD3 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD3_ipd, + TestSignalName => "RD3", + Period => tperiod_RD3, + PulseWidthHigh => tpw_RD3_posedge, + PulseWidthLow => tpw_RD3_negedge, + PeriodData => periodcheckinfo_RD3, + Violation => tviol_RD3_RD3, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD3_zd := RD3_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD3_ipd'last_event, + PathDelay => tpd_RD3_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD3, OutSignalName => "RD3", OutTemp => RD3_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD3, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD3, + PathCondition => TRUE)), + GlitchData => RD3_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_2_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RD_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_2_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD2 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD2_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD2 : VitalDelayType := 0 ns; + tpw_RD2_posedge : VitalDelayType := 0 ns; + tpw_RD2_negedge : VitalDelayType := 0 ns; + tpd_RD2_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD2: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_2_B : ENTITY IS TRUE; + + end RD_2_B; + + architecture Structure of RD_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD2_ipd : std_logic := 'X'; + signal RD2_out : std_logic := 'Z'; + + component mjiobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_2_718: mjiobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD2_out, + PADI=>RD2_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD2_ipd, RD2, tipd_RD2); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD2_ipd, RD2_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD2_zd : std_logic := 'X'; + VARIABLE RD2_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD2_RD2 : x01 := '0'; + VARIABLE periodcheckinfo_RD2 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD2_ipd, + TestSignalName => "RD2", + Period => tperiod_RD2, + PulseWidthHigh => tpw_RD2_posedge, + PulseWidthLow => tpw_RD2_negedge, + PeriodData => periodcheckinfo_RD2, + Violation => tviol_RD2_RD2, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD2_zd := RD2_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD2_ipd'last_event, + PathDelay => tpd_RD2_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD2, OutSignalName => "RD2", OutTemp => RD2_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD2, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD2, + PathCondition => TRUE)), + GlitchData => RD2_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_1_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RD_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_1_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD1 : VitalDelayType := 0 ns; + tpw_RD1_posedge : VitalDelayType := 0 ns; + tpw_RD1_negedge : VitalDelayType := 0 ns; + tpd_RD1_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD1: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_1_B : ENTITY IS TRUE; + + end RD_1_B; + + architecture Structure of RD_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD1_ipd : std_logic := 'X'; + signal RD1_out : std_logic := 'Z'; + + component mjiobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_1_719: mjiobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD1_out, + PADI=>RD1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD1_ipd, RD1, tipd_RD1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD1_ipd, RD1_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD1_zd : std_logic := 'X'; + VARIABLE RD1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD1_RD1 : x01 := '0'; + VARIABLE periodcheckinfo_RD1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD1_ipd, + TestSignalName => "RD1", + Period => tperiod_RD1, + PulseWidthHigh => tpw_RD1_posedge, + PulseWidthLow => tpw_RD1_negedge, + PeriodData => periodcheckinfo_RD1, + Violation => tviol_RD1_RD1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD1_zd := RD1_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD1_ipd'last_event, + PathDelay => tpd_RD1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD1, OutSignalName => "RD1", OutTemp => RD1_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD1, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD1, + PathCondition => TRUE)), + GlitchData => RD1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_0_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RD_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_0_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD0 : VitalDelayType := 0 ns; + tpw_RD0_posedge : VitalDelayType := 0 ns; + tpw_RD0_negedge : VitalDelayType := 0 ns; + tpd_RD0_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD0: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_0_B : ENTITY IS TRUE; + + end RD_0_B; + + architecture Structure of RD_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD0_ipd : std_logic := 'X'; + signal RD0_out : std_logic := 'Z'; + + component mjiobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_0_720: mjiobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD0_out, + PADI=>RD0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD0_ipd, RD0, tipd_RD0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD0_ipd, RD0_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD0_zd : std_logic := 'X'; + VARIABLE RD0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD0_RD0 : x01 := '0'; + VARIABLE periodcheckinfo_RD0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD0_ipd, + TestSignalName => "RD0", + Period => tperiod_RD0, + PulseWidthHigh => tpw_RD0_posedge, + PulseWidthLow => tpw_RD0_negedge, + PeriodData => periodcheckinfo_RD0, + Violation => tviol_RD0_RD0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD0_zd := RD0_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD0_ipd'last_event, + PathDelay => tpd_RD0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD0, OutSignalName => "RD0", OutTemp => RD0_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD0, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD0, + PathCondition => TRUE)), + GlitchData => RD0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity mjiobuf0076 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity mjiobuf0076 is + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + + ATTRIBUTE Vital_Level0 OF mjiobuf0076 : ENTITY IS TRUE; + + end mjiobuf0076; + + architecture Structure of mjiobuf0076 is + component OBZPU + port (I: in Std_logic; T: in Std_logic; O: out Std_logic); + end component; + begin + INST5: OBZPU + port map (I=>I, T=>T, O=>PAD); + end Structure; + +-- entity Dout_7_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Dout_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_7_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; Dout7: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_7_B : ENTITY IS TRUE; + + end Dout_7_B; + + architecture Structure of Dout_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout7_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_7: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout7_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout7_out) + VARIABLE Dout7_zd : std_logic := 'X'; + VARIABLE Dout7_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout7_zd := Dout7_out; + + VitalPathDelay01Z ( + OutSignal => Dout7, OutSignalName => "Dout7", OutTemp => Dout7_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout7, + PathCondition => TRUE)), + GlitchData => Dout7_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_6_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Dout_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_6_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; Dout6: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_6_B : ENTITY IS TRUE; + + end Dout_6_B; + + architecture Structure of Dout_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout6_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_6: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout6_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout6_out) + VARIABLE Dout6_zd : std_logic := 'X'; + VARIABLE Dout6_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout6_zd := Dout6_out; + + VitalPathDelay01Z ( + OutSignal => Dout6, OutSignalName => "Dout6", OutTemp => Dout6_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout6, + PathCondition => TRUE)), + GlitchData => Dout6_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_5_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Dout_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_5_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; Dout5: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_5_B : ENTITY IS TRUE; + + end Dout_5_B; + + architecture Structure of Dout_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout5_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_5: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout5_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout5_out) + VARIABLE Dout5_zd : std_logic := 'X'; + VARIABLE Dout5_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout5_zd := Dout5_out; + + VitalPathDelay01Z ( + OutSignal => Dout5, OutSignalName => "Dout5", OutTemp => Dout5_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout5, + PathCondition => TRUE)), + GlitchData => Dout5_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_4_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Dout_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_4_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; Dout4: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_4_B : ENTITY IS TRUE; + + end Dout_4_B; + + architecture Structure of Dout_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout4_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_4: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout4_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout4_out) + VARIABLE Dout4_zd : std_logic := 'X'; + VARIABLE Dout4_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout4_zd := Dout4_out; + + VitalPathDelay01Z ( + OutSignal => Dout4, OutSignalName => "Dout4", OutTemp => Dout4_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout4, + PathCondition => TRUE)), + GlitchData => Dout4_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_3_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Dout_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_3_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; Dout3: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_3_B : ENTITY IS TRUE; + + end Dout_3_B; + + architecture Structure of Dout_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout3_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_3: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout3_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout3_out) + VARIABLE Dout3_zd : std_logic := 'X'; + VARIABLE Dout3_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout3_zd := Dout3_out; + + VitalPathDelay01Z ( + OutSignal => Dout3, OutSignalName => "Dout3", OutTemp => Dout3_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout3, + PathCondition => TRUE)), + GlitchData => Dout3_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_2_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Dout_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_2_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; Dout2: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_2_B : ENTITY IS TRUE; + + end Dout_2_B; + + architecture Structure of Dout_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout2_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_2: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout2_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout2_out) + VARIABLE Dout2_zd : std_logic := 'X'; + VARIABLE Dout2_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout2_zd := Dout2_out; + + VitalPathDelay01Z ( + OutSignal => Dout2, OutSignalName => "Dout2", OutTemp => Dout2_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout2, + PathCondition => TRUE)), + GlitchData => Dout2_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_1_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Dout_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_1_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; Dout1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_1_B : ENTITY IS TRUE; + + end Dout_1_B; + + architecture Structure of Dout_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_1: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout1_out) + VARIABLE Dout1_zd : std_logic := 'X'; + VARIABLE Dout1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout1_zd := Dout1_out; + + VitalPathDelay01Z ( + OutSignal => Dout1, OutSignalName => "Dout1", OutTemp => Dout1_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout1, + PathCondition => TRUE)), + GlitchData => Dout1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_0_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Dout_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_0_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; Dout0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_0_B : ENTITY IS TRUE; + + end Dout_0_B; + + architecture Structure of Dout_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_0: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout0_out) + VARIABLE Dout0_zd : std_logic := 'X'; + VARIABLE Dout0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout0_zd := Dout0_out; + + VitalPathDelay01Z ( + OutSignal => Dout0, OutSignalName => "Dout0", OutTemp => Dout0_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout0, + PathCondition => TRUE)), + GlitchData => Dout0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity LEDB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity LEDB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "LEDB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_LEDS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; LEDS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF LEDB : ENTITY IS TRUE; + + end LEDB; + + architecture Structure of LEDB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal LEDS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + LED_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>LEDS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, LEDS_out) + VARIABLE LEDS_zd : std_logic := 'X'; + VARIABLE LEDS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + LEDS_zd := LEDS_out; + + VitalPathDelay01Z ( + OutSignal => LEDS, OutSignalName => "LEDS", OutTemp => LEDS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_LEDS, + PathCondition => TRUE)), + GlitchData => LEDS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RBA_1_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RBA_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RBA_1_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RBA1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; RBA1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RBA_1_B : ENTITY IS TRUE; + + end RBA_1_B; + + architecture Structure of RBA_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RBA1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RBA_pad_1: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RBA1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RBA1_out) + VARIABLE RBA1_zd : std_logic := 'X'; + VARIABLE RBA1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RBA1_zd := RBA1_out; + + VitalPathDelay01Z ( + OutSignal => RBA1, OutSignalName => "RBA1", OutTemp => RBA1_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RBA1, + PathCondition => TRUE)), + GlitchData => RBA1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RBA_0_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RBA_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RBA_0_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RBA0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; RBA0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RBA_0_B : ENTITY IS TRUE; + + end RBA_0_B; + + architecture Structure of RBA_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RBA0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RBA_pad_0: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RBA0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RBA0_out) + VARIABLE RBA0_zd : std_logic := 'X'; + VARIABLE RBA0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RBA0_zd := RBA0_out; + + VitalPathDelay01Z ( + OutSignal => RBA0, OutSignalName => "RBA0", OutTemp => RBA0_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RBA0, + PathCondition => TRUE)), + GlitchData => RBA0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_11_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_11_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_11_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA11 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; RA11: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_11_B : ENTITY IS TRUE; + + end RA_11_B; + + architecture Structure of RA_11_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA11_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_11: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA11_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA11_out) + VARIABLE RA11_zd : std_logic := 'X'; + VARIABLE RA11_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA11_zd := RA11_out; + + VitalPathDelay01Z ( + OutSignal => RA11, OutSignalName => "RA11", OutTemp => RA11_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA11, + PathCondition => TRUE)), + GlitchData => RA11_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_10_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_10_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_10_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA10 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; RA10: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_10_B : ENTITY IS TRUE; + + end RA_10_B; + + architecture Structure of RA_10_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA10_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_10: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA10_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA10_out) + VARIABLE RA10_zd : std_logic := 'X'; + VARIABLE RA10_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA10_zd := RA10_out; + + VitalPathDelay01Z ( + OutSignal => RA10, OutSignalName => "RA10", OutTemp => RA10_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA10, + PathCondition => TRUE)), + GlitchData => RA10_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_9_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_9_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_9_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA9 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA9: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_9_B : ENTITY IS TRUE; + + end RA_9_B; + + architecture Structure of RA_9_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA9_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_9: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA9_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA9_out) + VARIABLE RA9_zd : std_logic := 'X'; + VARIABLE RA9_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA9_zd := RA9_out; + + VitalPathDelay01Z ( + OutSignal => RA9, OutSignalName => "RA9", OutTemp => RA9_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA9, + PathCondition => TRUE)), + GlitchData => RA9_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_8_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_8_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_8_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA8 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA8: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_8_B : ENTITY IS TRUE; + + end RA_8_B; + + architecture Structure of RA_8_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA8_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_8: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA8_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA8_out) + VARIABLE RA8_zd : std_logic := 'X'; + VARIABLE RA8_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA8_zd := RA8_out; + + VitalPathDelay01Z ( + OutSignal => RA8, OutSignalName => "RA8", OutTemp => RA8_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA8, + PathCondition => TRUE)), + GlitchData => RA8_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_7_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_7_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA7: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_7_B : ENTITY IS TRUE; + + end RA_7_B; + + architecture Structure of RA_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA7_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_7: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA7_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA7_out) + VARIABLE RA7_zd : std_logic := 'X'; + VARIABLE RA7_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA7_zd := RA7_out; + + VitalPathDelay01Z ( + OutSignal => RA7, OutSignalName => "RA7", OutTemp => RA7_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA7, + PathCondition => TRUE)), + GlitchData => RA7_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_6_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_6_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA6: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_6_B : ENTITY IS TRUE; + + end RA_6_B; + + architecture Structure of RA_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA6_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_6: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA6_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA6_out) + VARIABLE RA6_zd : std_logic := 'X'; + VARIABLE RA6_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA6_zd := RA6_out; + + VitalPathDelay01Z ( + OutSignal => RA6, OutSignalName => "RA6", OutTemp => RA6_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA6, + PathCondition => TRUE)), + GlitchData => RA6_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_5_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_5_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA5: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_5_B : ENTITY IS TRUE; + + end RA_5_B; + + architecture Structure of RA_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA5_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_5: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA5_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA5_out) + VARIABLE RA5_zd : std_logic := 'X'; + VARIABLE RA5_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA5_zd := RA5_out; + + VitalPathDelay01Z ( + OutSignal => RA5, OutSignalName => "RA5", OutTemp => RA5_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA5, + PathCondition => TRUE)), + GlitchData => RA5_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_4_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_4_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA4: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_4_B : ENTITY IS TRUE; + + end RA_4_B; + + architecture Structure of RA_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA4_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_4: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA4_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA4_out) + VARIABLE RA4_zd : std_logic := 'X'; + VARIABLE RA4_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA4_zd := RA4_out; + + VitalPathDelay01Z ( + OutSignal => RA4, OutSignalName => "RA4", OutTemp => RA4_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA4, + PathCondition => TRUE)), + GlitchData => RA4_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_3_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_3_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA3: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_3_B : ENTITY IS TRUE; + + end RA_3_B; + + architecture Structure of RA_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA3_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_3: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA3_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA3_out) + VARIABLE RA3_zd : std_logic := 'X'; + VARIABLE RA3_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA3_zd := RA3_out; + + VitalPathDelay01Z ( + OutSignal => RA3, OutSignalName => "RA3", OutTemp => RA3_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA3, + PathCondition => TRUE)), + GlitchData => RA3_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_2_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_2_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA2: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_2_B : ENTITY IS TRUE; + + end RA_2_B; + + architecture Structure of RA_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA2_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_2: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA2_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA2_out) + VARIABLE RA2_zd : std_logic := 'X'; + VARIABLE RA2_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA2_zd := RA2_out; + + VitalPathDelay01Z ( + OutSignal => RA2, OutSignalName => "RA2", OutTemp => RA2_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA2, + PathCondition => TRUE)), + GlitchData => RA2_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_1_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_1_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_1_B : ENTITY IS TRUE; + + end RA_1_B; + + architecture Structure of RA_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_1: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA1_out) + VARIABLE RA1_zd : std_logic := 'X'; + VARIABLE RA1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA1_zd := RA1_out; + + VitalPathDelay01Z ( + OutSignal => RA1, OutSignalName => "RA1", OutTemp => RA1_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA1, + PathCondition => TRUE)), + GlitchData => RA1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_0_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_0_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_0_B : ENTITY IS TRUE; + + end RA_0_B; + + architecture Structure of RA_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_0: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA0_out) + VARIABLE RA0_zd : std_logic := 'X'; + VARIABLE RA0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA0_zd := RA0_out; + + VitalPathDelay01Z ( + OutSignal => RA0, OutSignalName => "RA0", OutTemp => RA0_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA0, + PathCondition => TRUE)), + GlitchData => RA0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRCSB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity nRCSB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRCSB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nRCSS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; nRCSS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRCSB : ENTITY IS TRUE; + + end nRCSB; + + architecture Structure of nRCSB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nRCSS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nRCS_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRCSS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nRCSS_out) + VARIABLE nRCSS_zd : std_logic := 'X'; + VARIABLE nRCSS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRCSS_zd := nRCSS_out; + + VitalPathDelay01Z ( + OutSignal => nRCSS, OutSignalName => "nRCSS", OutTemp => nRCSS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nRCSS, + PathCondition => TRUE)), + GlitchData => nRCSS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RCKEB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RCKEB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RCKEB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RCKES : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; RCKES: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RCKEB : ENTITY IS TRUE; + + end RCKEB; + + architecture Structure of RCKEB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RCKES_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RCKE_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RCKES_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RCKES_out) + VARIABLE RCKES_zd : std_logic := 'X'; + VARIABLE RCKES_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RCKES_zd := RCKES_out; + + VitalPathDelay01Z ( + OutSignal => RCKES, OutSignalName => "RCKES", OutTemp => RCKES_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RCKES, + PathCondition => TRUE)), + GlitchData => RCKES_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRWEB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity nRWEB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRWEB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nRWES : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; nRWES: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRWEB : ENTITY IS TRUE; + + end nRWEB; + + architecture Structure of nRWEB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nRWES_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nRWE_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRWES_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nRWES_out) + VARIABLE nRWES_zd : std_logic := 'X'; + VARIABLE nRWES_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRWES_zd := nRWES_out; + + VitalPathDelay01Z ( + OutSignal => nRWES, OutSignalName => "nRWES", OutTemp => nRWES_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nRWES, + PathCondition => TRUE)), + GlitchData => nRWES_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRRASB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity nRRASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRRASB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nRRASS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; nRRASS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRRASB : ENTITY IS TRUE; + + end nRRASB; + + architecture Structure of nRRASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nRRASS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nRRAS_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRRASS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nRRASS_out) + VARIABLE nRRASS_zd : std_logic := 'X'; + VARIABLE nRRASS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRRASS_zd := nRRASS_out; + + VitalPathDelay01Z ( + OutSignal => nRRASS, OutSignalName => "nRRASS", OutTemp => nRRASS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nRRASS, + PathCondition => TRUE)), + GlitchData => nRRASS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRCASB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity nRCASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRCASB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nRCASS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; nRCASS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRCASB : ENTITY IS TRUE; + + end nRCASB; + + architecture Structure of nRCASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nRCASS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nRCAS_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRCASS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nRCASS_out) + VARIABLE nRCASS_zd : std_logic := 'X'; + VARIABLE nRCASS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRCASS_zd := nRCASS_out; + + VitalPathDelay01Z ( + OutSignal => nRCASS, OutSignalName => "nRCASS", OutTemp => nRCASS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nRCASS, + PathCondition => TRUE)), + GlitchData => nRCASS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RDQMHB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RDQMHB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RDQMHB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RDQMHS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; RDQMHS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RDQMHB : ENTITY IS TRUE; + + end RDQMHB; + + architecture Structure of RDQMHB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RDQMHS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RDQMH_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RDQMHS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RDQMHS_out) + VARIABLE RDQMHS_zd : std_logic := 'X'; + VARIABLE RDQMHS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RDQMHS_zd := RDQMHS_out; + + VitalPathDelay01Z ( + OutSignal => RDQMHS, OutSignalName => "RDQMHS", OutTemp => RDQMHS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RDQMHS, + PathCondition => TRUE)), + GlitchData => RDQMHS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RDQMLB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RDQMLB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RDQMLB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RDQMLS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; RDQMLS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RDQMLB : ENTITY IS TRUE; + + end RDQMLB; + + architecture Structure of RDQMLB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RDQMLS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RDQML_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RDQMLS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RDQMLS_out) + VARIABLE RDQMLS_zd : std_logic := 'X'; + VARIABLE RDQMLS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RDQMLS_zd := RDQMLS_out; + + VitalPathDelay01Z ( + OutSignal => RDQMLS, OutSignalName => "RDQMLS", OutTemp => RDQMLS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RDQMLS, + PathCondition => TRUE)), + GlitchData => RDQMLS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nUFMCSB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity nUFMCSB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nUFMCSB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + + tpd_PADDO_nUFMCSS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; nUFMCSS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nUFMCSB : ENTITY IS TRUE; + + end nUFMCSB; + + architecture Structure of nUFMCSB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nUFMCSS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nUFMCS_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nUFMCSS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nUFMCSS_out) + VARIABLE nUFMCSS_zd : std_logic := 'X'; + VARIABLE nUFMCSS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nUFMCSS_zd := nUFMCSS_out; + + VitalPathDelay01Z ( + OutSignal => nUFMCSS, OutSignalName => "nUFMCSS", OutTemp => nUFMCSS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nUFMCSS, + PathCondition => TRUE)), + GlitchData => nUFMCSS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity UFMCLKB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity UFMCLKB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "UFMCLKB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + + tpd_PADDO_UFMCLKS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; UFMCLKS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF UFMCLKB : ENTITY IS TRUE; + + end UFMCLKB; + + architecture Structure of UFMCLKB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal UFMCLKS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + UFMCLK_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>UFMCLKS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, UFMCLKS_out) + VARIABLE UFMCLKS_zd : std_logic := 'X'; + VARIABLE UFMCLKS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + UFMCLKS_zd := UFMCLKS_out; + + VitalPathDelay01Z ( + OutSignal => UFMCLKS, OutSignalName => "UFMCLKS", OutTemp => UFMCLKS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_UFMCLKS, + PathCondition => TRUE)), + GlitchData => UFMCLKS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity UFMSDIB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity UFMSDIB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "UFMSDIB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + + tpd_PADDO_UFMSDIS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; UFMSDIS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF UFMSDIB : ENTITY IS TRUE; + + end UFMSDIB; + + architecture Structure of UFMSDIB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal UFMSDIS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + UFMSDI_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>UFMSDIS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, UFMSDIS_out) + VARIABLE UFMSDIS_zd : std_logic := 'X'; + VARIABLE UFMSDIS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + UFMSDIS_zd := UFMSDIS_out; + + VitalPathDelay01Z ( + OutSignal => UFMSDIS, OutSignalName => "UFMSDIS", OutTemp => UFMSDIS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_UFMSDIS, + PathCondition => TRUE)), + GlitchData => UFMSDIS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity mjiobuf0077 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity mjiobuf0077 is + port (Z: out Std_logic; PAD: in Std_logic); + + ATTRIBUTE Vital_Level0 OF mjiobuf0077 : ENTITY IS TRUE; + + end mjiobuf0077; + + architecture Structure of mjiobuf0077 is + component IBPU + port (I: in Std_logic; O: out Std_logic); + end component; + begin + INST1: IBPU + port map (I=>PAD, O=>Z); + end Structure; + +-- entity PHI2B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity PHI2B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "PHI2B"; + + tipd_PHI2S : VitalDelayType01 := (0 ns, 0 ns); + tpd_PHI2S_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_PHI2S : VitalDelayType := 0 ns; + tpw_PHI2S_posedge : VitalDelayType := 0 ns; + tpw_PHI2S_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; PHI2S: in Std_logic); + + ATTRIBUTE Vital_Level0 OF PHI2B : ENTITY IS TRUE; + + end PHI2B; + + architecture Structure of PHI2B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PHI2S_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + PHI2_pad: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>PHI2S_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PHI2S_ipd, PHI2S, tipd_PHI2S); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PHI2S_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_PHI2S_PHI2S : x01 := '0'; + VARIABLE periodcheckinfo_PHI2S : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => PHI2S_ipd, + TestSignalName => "PHI2S", + Period => tperiod_PHI2S, + PulseWidthHigh => tpw_PHI2S_posedge, + PulseWidthLow => tpw_PHI2S_negedge, + PeriodData => periodcheckinfo_PHI2S, + Violation => tviol_PHI2S_PHI2S, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => PHI2S_ipd'last_event, + PathDelay => tpd_PHI2S_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_9_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_9_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_9_B"; + + tipd_MAin9 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin9_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin9 : VitalDelayType := 0 ns; + tpw_MAin9_posedge : VitalDelayType := 0 ns; + tpw_MAin9_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin9: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_9_B : ENTITY IS TRUE; + + end MAin_9_B; + + architecture Structure of MAin_9_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin9_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_9: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin9_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin9_ipd, MAin9, tipd_MAin9); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin9_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin9_MAin9 : x01 := '0'; + VARIABLE periodcheckinfo_MAin9 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin9_ipd, + TestSignalName => "MAin9", + Period => tperiod_MAin9, + PulseWidthHigh => tpw_MAin9_posedge, + PulseWidthLow => tpw_MAin9_negedge, + PeriodData => periodcheckinfo_MAin9, + Violation => tviol_MAin9_MAin9, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin9_ipd'last_event, + PathDelay => tpd_MAin9_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_8_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_8_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_8_B"; + + tipd_MAin8 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin8_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin8 : VitalDelayType := 0 ns; + tpw_MAin8_posedge : VitalDelayType := 0 ns; + tpw_MAin8_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin8: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_8_B : ENTITY IS TRUE; + + end MAin_8_B; + + architecture Structure of MAin_8_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin8_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_8: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin8_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin8_ipd, MAin8, tipd_MAin8); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin8_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin8_MAin8 : x01 := '0'; + VARIABLE periodcheckinfo_MAin8 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin8_ipd, + TestSignalName => "MAin8", + Period => tperiod_MAin8, + PulseWidthHigh => tpw_MAin8_posedge, + PulseWidthLow => tpw_MAin8_negedge, + PeriodData => periodcheckinfo_MAin8, + Violation => tviol_MAin8_MAin8, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin8_ipd'last_event, + PathDelay => tpd_MAin8_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_7_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_7_B"; + + tipd_MAin7 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin7_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin7 : VitalDelayType := 0 ns; + tpw_MAin7_posedge : VitalDelayType := 0 ns; + tpw_MAin7_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin7: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_7_B : ENTITY IS TRUE; + + end MAin_7_B; + + architecture Structure of MAin_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin7_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_7: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin7_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin7_ipd, MAin7, tipd_MAin7); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin7_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin7_MAin7 : x01 := '0'; + VARIABLE periodcheckinfo_MAin7 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin7_ipd, + TestSignalName => "MAin7", + Period => tperiod_MAin7, + PulseWidthHigh => tpw_MAin7_posedge, + PulseWidthLow => tpw_MAin7_negedge, + PeriodData => periodcheckinfo_MAin7, + Violation => tviol_MAin7_MAin7, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin7_ipd'last_event, + PathDelay => tpd_MAin7_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_6_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_6_B"; + + tipd_MAin6 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin6_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin6 : VitalDelayType := 0 ns; + tpw_MAin6_posedge : VitalDelayType := 0 ns; + tpw_MAin6_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin6: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_6_B : ENTITY IS TRUE; + + end MAin_6_B; + + architecture Structure of MAin_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin6_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_6: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin6_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin6_ipd, MAin6, tipd_MAin6); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin6_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin6_MAin6 : x01 := '0'; + VARIABLE periodcheckinfo_MAin6 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin6_ipd, + TestSignalName => "MAin6", + Period => tperiod_MAin6, + PulseWidthHigh => tpw_MAin6_posedge, + PulseWidthLow => tpw_MAin6_negedge, + PeriodData => periodcheckinfo_MAin6, + Violation => tviol_MAin6_MAin6, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin6_ipd'last_event, + PathDelay => tpd_MAin6_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_5_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_5_B"; + + tipd_MAin5 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin5_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin5 : VitalDelayType := 0 ns; + tpw_MAin5_posedge : VitalDelayType := 0 ns; + tpw_MAin5_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin5: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_5_B : ENTITY IS TRUE; + + end MAin_5_B; + + architecture Structure of MAin_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin5_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_5: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin5_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin5_ipd, MAin5, tipd_MAin5); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin5_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin5_MAin5 : x01 := '0'; + VARIABLE periodcheckinfo_MAin5 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin5_ipd, + TestSignalName => "MAin5", + Period => tperiod_MAin5, + PulseWidthHigh => tpw_MAin5_posedge, + PulseWidthLow => tpw_MAin5_negedge, + PeriodData => periodcheckinfo_MAin5, + Violation => tviol_MAin5_MAin5, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin5_ipd'last_event, + PathDelay => tpd_MAin5_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_4_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_4_B"; + + tipd_MAin4 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin4_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin4 : VitalDelayType := 0 ns; + tpw_MAin4_posedge : VitalDelayType := 0 ns; + tpw_MAin4_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin4: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_4_B : ENTITY IS TRUE; + + end MAin_4_B; + + architecture Structure of MAin_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin4_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_4: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin4_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin4_ipd, MAin4, tipd_MAin4); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin4_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin4_MAin4 : x01 := '0'; + VARIABLE periodcheckinfo_MAin4 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin4_ipd, + TestSignalName => "MAin4", + Period => tperiod_MAin4, + PulseWidthHigh => tpw_MAin4_posedge, + PulseWidthLow => tpw_MAin4_negedge, + PeriodData => periodcheckinfo_MAin4, + Violation => tviol_MAin4_MAin4, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin4_ipd'last_event, + PathDelay => tpd_MAin4_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_3_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_3_B"; + + tipd_MAin3 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin3_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin3 : VitalDelayType := 0 ns; + tpw_MAin3_posedge : VitalDelayType := 0 ns; + tpw_MAin3_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin3: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_3_B : ENTITY IS TRUE; + + end MAin_3_B; + + architecture Structure of MAin_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin3_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_3: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin3_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin3_ipd, MAin3, tipd_MAin3); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin3_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin3_MAin3 : x01 := '0'; + VARIABLE periodcheckinfo_MAin3 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin3_ipd, + TestSignalName => "MAin3", + Period => tperiod_MAin3, + PulseWidthHigh => tpw_MAin3_posedge, + PulseWidthLow => tpw_MAin3_negedge, + PeriodData => periodcheckinfo_MAin3, + Violation => tviol_MAin3_MAin3, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin3_ipd'last_event, + PathDelay => tpd_MAin3_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_2_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_2_B"; + + tipd_MAin2 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin2_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin2 : VitalDelayType := 0 ns; + tpw_MAin2_posedge : VitalDelayType := 0 ns; + tpw_MAin2_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin2: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_2_B : ENTITY IS TRUE; + + end MAin_2_B; + + architecture Structure of MAin_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin2_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_2: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin2_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin2_ipd, MAin2, tipd_MAin2); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin2_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin2_MAin2 : x01 := '0'; + VARIABLE periodcheckinfo_MAin2 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin2_ipd, + TestSignalName => "MAin2", + Period => tperiod_MAin2, + PulseWidthHigh => tpw_MAin2_posedge, + PulseWidthLow => tpw_MAin2_negedge, + PeriodData => periodcheckinfo_MAin2, + Violation => tviol_MAin2_MAin2, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin2_ipd'last_event, + PathDelay => tpd_MAin2_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_1_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_1_B"; + + tipd_MAin1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin1 : VitalDelayType := 0 ns; + tpw_MAin1_posedge : VitalDelayType := 0 ns; + tpw_MAin1_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin1: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_1_B : ENTITY IS TRUE; + + end MAin_1_B; + + architecture Structure of MAin_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin1_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_1: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin1_ipd, MAin1, tipd_MAin1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin1_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin1_MAin1 : x01 := '0'; + VARIABLE periodcheckinfo_MAin1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin1_ipd, + TestSignalName => "MAin1", + Period => tperiod_MAin1, + PulseWidthHigh => tpw_MAin1_posedge, + PulseWidthLow => tpw_MAin1_negedge, + PeriodData => periodcheckinfo_MAin1, + Violation => tviol_MAin1_MAin1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin1_ipd'last_event, + PathDelay => tpd_MAin1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_0_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_0_B"; + + tipd_MAin0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin0 : VitalDelayType := 0 ns; + tpw_MAin0_posedge : VitalDelayType := 0 ns; + tpw_MAin0_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin0: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_0_B : ENTITY IS TRUE; + + end MAin_0_B; + + architecture Structure of MAin_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin0_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_0: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin0_ipd, MAin0, tipd_MAin0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin0_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin0_MAin0 : x01 := '0'; + VARIABLE periodcheckinfo_MAin0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin0_ipd, + TestSignalName => "MAin0", + Period => tperiod_MAin0, + PulseWidthHigh => tpw_MAin0_posedge, + PulseWidthLow => tpw_MAin0_negedge, + PeriodData => periodcheckinfo_MAin0, + Violation => tviol_MAin0_MAin0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin0_ipd'last_event, + PathDelay => tpd_MAin0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity CROW_1_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity CROW_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "CROW_1_B"; + + tipd_CROW1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CROW1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CROW1 : VitalDelayType := 0 ns; + tpw_CROW1_posedge : VitalDelayType := 0 ns; + tpw_CROW1_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; CROW1: in Std_logic); + + ATTRIBUTE Vital_Level0 OF CROW_1_B : ENTITY IS TRUE; + + end CROW_1_B; + + architecture Structure of CROW_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal CROW1_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + CROW_pad_1: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>CROW1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(CROW1_ipd, CROW1, tipd_CROW1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, CROW1_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_CROW1_CROW1 : x01 := '0'; + VARIABLE periodcheckinfo_CROW1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => CROW1_ipd, + TestSignalName => "CROW1", + Period => tperiod_CROW1, + PulseWidthHigh => tpw_CROW1_posedge, + PulseWidthLow => tpw_CROW1_negedge, + PeriodData => periodcheckinfo_CROW1, + Violation => tviol_CROW1_CROW1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => CROW1_ipd'last_event, + PathDelay => tpd_CROW1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity CROW_0_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity CROW_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "CROW_0_B"; + + tipd_CROW0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CROW0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CROW0 : VitalDelayType := 0 ns; + tpw_CROW0_posedge : VitalDelayType := 0 ns; + tpw_CROW0_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; CROW0: in Std_logic); + + ATTRIBUTE Vital_Level0 OF CROW_0_B : ENTITY IS TRUE; + + end CROW_0_B; + + architecture Structure of CROW_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal CROW0_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + CROW_pad_0: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>CROW0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(CROW0_ipd, CROW0, tipd_CROW0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, CROW0_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_CROW0_CROW0 : x01 := '0'; + VARIABLE periodcheckinfo_CROW0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => CROW0_ipd, + TestSignalName => "CROW0", + Period => tperiod_CROW0, + PulseWidthHigh => tpw_CROW0_posedge, + PulseWidthLow => tpw_CROW0_negedge, + PeriodData => periodcheckinfo_CROW0, + Violation => tviol_CROW0_CROW0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => CROW0_ipd'last_event, + PathDelay => tpd_CROW0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_7_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Din_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_7_B"; + + tipd_Din7 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din7_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din7 : VitalDelayType := 0 ns; + tpw_Din7_posedge : VitalDelayType := 0 ns; + tpw_Din7_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din7: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_7_B : ENTITY IS TRUE; + + end Din_7_B; + + architecture Structure of Din_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din7_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_7: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>Din7_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din7_ipd, Din7, tipd_Din7); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din7_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din7_Din7 : x01 := '0'; + VARIABLE periodcheckinfo_Din7 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din7_ipd, + TestSignalName => "Din7", + Period => tperiod_Din7, + PulseWidthHigh => tpw_Din7_posedge, + PulseWidthLow => tpw_Din7_negedge, + PeriodData => periodcheckinfo_Din7, + Violation => tviol_Din7_Din7, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din7_ipd'last_event, + PathDelay => tpd_Din7_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_6_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Din_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_6_B"; + + tipd_Din6 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din6_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din6 : VitalDelayType := 0 ns; + tpw_Din6_posedge : VitalDelayType := 0 ns; + tpw_Din6_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din6: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_6_B : ENTITY IS TRUE; + + end Din_6_B; + + architecture Structure of Din_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din6_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_6: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>Din6_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din6_ipd, Din6, tipd_Din6); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din6_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din6_Din6 : x01 := '0'; + VARIABLE periodcheckinfo_Din6 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din6_ipd, + TestSignalName => "Din6", + Period => tperiod_Din6, + PulseWidthHigh => tpw_Din6_posedge, + PulseWidthLow => tpw_Din6_negedge, + PeriodData => periodcheckinfo_Din6, + Violation => tviol_Din6_Din6, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din6_ipd'last_event, + PathDelay => tpd_Din6_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_5_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Din_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_5_B"; + + tipd_Din5 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din5_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din5 : VitalDelayType := 0 ns; + tpw_Din5_posedge : VitalDelayType := 0 ns; + tpw_Din5_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din5: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_5_B : ENTITY IS TRUE; + + end Din_5_B; + + architecture Structure of Din_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din5_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_5: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>Din5_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din5_ipd, Din5, tipd_Din5); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din5_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din5_Din5 : x01 := '0'; + VARIABLE periodcheckinfo_Din5 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din5_ipd, + TestSignalName => "Din5", + Period => tperiod_Din5, + PulseWidthHigh => tpw_Din5_posedge, + PulseWidthLow => tpw_Din5_negedge, + PeriodData => periodcheckinfo_Din5, + Violation => tviol_Din5_Din5, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din5_ipd'last_event, + PathDelay => tpd_Din5_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_4_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Din_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_4_B"; + + tipd_Din4 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din4_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din4 : VitalDelayType := 0 ns; + tpw_Din4_posedge : VitalDelayType := 0 ns; + tpw_Din4_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din4: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_4_B : ENTITY IS TRUE; + + end Din_4_B; + + architecture Structure of Din_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din4_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_4: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>Din4_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din4_ipd, Din4, tipd_Din4); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din4_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din4_Din4 : x01 := '0'; + VARIABLE periodcheckinfo_Din4 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din4_ipd, + TestSignalName => "Din4", + Period => tperiod_Din4, + PulseWidthHigh => tpw_Din4_posedge, + PulseWidthLow => tpw_Din4_negedge, + PeriodData => periodcheckinfo_Din4, + Violation => tviol_Din4_Din4, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din4_ipd'last_event, + PathDelay => tpd_Din4_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_3_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Din_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_3_B"; + + tipd_Din3 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din3_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din3 : VitalDelayType := 0 ns; + tpw_Din3_posedge : VitalDelayType := 0 ns; + tpw_Din3_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din3: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_3_B : ENTITY IS TRUE; + + end Din_3_B; + + architecture Structure of Din_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din3_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_3: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>Din3_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din3_ipd, Din3, tipd_Din3); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din3_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din3_Din3 : x01 := '0'; + VARIABLE periodcheckinfo_Din3 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din3_ipd, + TestSignalName => "Din3", + Period => tperiod_Din3, + PulseWidthHigh => tpw_Din3_posedge, + PulseWidthLow => tpw_Din3_negedge, + PeriodData => periodcheckinfo_Din3, + Violation => tviol_Din3_Din3, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din3_ipd'last_event, + PathDelay => tpd_Din3_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_2_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Din_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_2_B"; + + tipd_Din2 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din2_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din2 : VitalDelayType := 0 ns; + tpw_Din2_posedge : VitalDelayType := 0 ns; + tpw_Din2_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din2: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_2_B : ENTITY IS TRUE; + + end Din_2_B; + + architecture Structure of Din_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din2_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_2: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>Din2_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din2_ipd, Din2, tipd_Din2); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din2_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din2_Din2 : x01 := '0'; + VARIABLE periodcheckinfo_Din2 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din2_ipd, + TestSignalName => "Din2", + Period => tperiod_Din2, + PulseWidthHigh => tpw_Din2_posedge, + PulseWidthLow => tpw_Din2_negedge, + PeriodData => periodcheckinfo_Din2, + Violation => tviol_Din2_Din2, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din2_ipd'last_event, + PathDelay => tpd_Din2_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_1_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Din_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_1_B"; + + tipd_Din1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din1 : VitalDelayType := 0 ns; + tpw_Din1_posedge : VitalDelayType := 0 ns; + tpw_Din1_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din1: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_1_B : ENTITY IS TRUE; + + end Din_1_B; + + architecture Structure of Din_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din1_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_1: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>Din1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din1_ipd, Din1, tipd_Din1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din1_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din1_Din1 : x01 := '0'; + VARIABLE periodcheckinfo_Din1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din1_ipd, + TestSignalName => "Din1", + Period => tperiod_Din1, + PulseWidthHigh => tpw_Din1_posedge, + PulseWidthLow => tpw_Din1_negedge, + PeriodData => periodcheckinfo_Din1, + Violation => tviol_Din1_Din1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din1_ipd'last_event, + PathDelay => tpd_Din1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_0_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Din_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_0_B"; + + tipd_Din0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din0 : VitalDelayType := 0 ns; + tpw_Din0_posedge : VitalDelayType := 0 ns; + tpw_Din0_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din0: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_0_B : ENTITY IS TRUE; + + end Din_0_B; + + architecture Structure of Din_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din0_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_0: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>Din0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din0_ipd, Din0, tipd_Din0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din0_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din0_Din0 : x01 := '0'; + VARIABLE periodcheckinfo_Din0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din0_ipd, + TestSignalName => "Din0", + Period => tperiod_Din0, + PulseWidthHigh => tpw_Din0_posedge, + PulseWidthLow => tpw_Din0_negedge, + PeriodData => periodcheckinfo_Din0, + Violation => tviol_Din0_Din0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din0_ipd'last_event, + PathDelay => tpd_Din0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nCCASB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity nCCASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nCCASB"; + + tipd_nCCASS : VitalDelayType01 := (0 ns, 0 ns); + tpd_nCCASS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nCCASS : VitalDelayType := 0 ns; + tpw_nCCASS_posedge : VitalDelayType := 0 ns; + tpw_nCCASS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; nCCASS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nCCASB : ENTITY IS TRUE; + + end nCCASB; + + architecture Structure of nCCASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal nCCASS_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + nCCAS_pad: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>nCCASS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(nCCASS_ipd, nCCASS, tipd_nCCASS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, nCCASS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_nCCASS_nCCASS : x01 := '0'; + VARIABLE periodcheckinfo_nCCASS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => nCCASS_ipd, + TestSignalName => "nCCASS", + Period => tperiod_nCCASS, + PulseWidthHigh => tpw_nCCASS_posedge, + PulseWidthLow => tpw_nCCASS_negedge, + PeriodData => periodcheckinfo_nCCASS, + Violation => tviol_nCCASS_nCCASS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => nCCASS_ipd'last_event, + PathDelay => tpd_nCCASS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nCRASB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity nCRASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nCRASB"; + + tipd_nCRASS : VitalDelayType01 := (0 ns, 0 ns); + tpd_nCRASS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nCRASS : VitalDelayType := 0 ns; + tpw_nCRASS_posedge : VitalDelayType := 0 ns; + tpw_nCRASS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; nCRASS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nCRASB : ENTITY IS TRUE; + + end nCRASB; + + architecture Structure of nCRASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal nCRASS_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + nCRAS_pad: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>nCRASS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(nCRASS_ipd, nCRASS, tipd_nCRASS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, nCRASS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_nCRASS_nCRASS : x01 := '0'; + VARIABLE periodcheckinfo_nCRASS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => nCRASS_ipd, + TestSignalName => "nCRASS", + Period => tperiod_nCRASS, + PulseWidthHigh => tpw_nCRASS_posedge, + PulseWidthLow => tpw_nCRASS_negedge, + PeriodData => periodcheckinfo_nCRASS, + Violation => tviol_nCRASS_nCRASS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => nCRASS_ipd'last_event, + PathDelay => tpd_nCRASS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nFWEB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity nFWEB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nFWEB"; + + tipd_nFWES : VitalDelayType01 := (0 ns, 0 ns); + tpd_nFWES_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nFWES : VitalDelayType := 0 ns; + tpw_nFWES_posedge : VitalDelayType := 0 ns; + tpw_nFWES_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; nFWES: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nFWEB : ENTITY IS TRUE; + + end nFWEB; + + architecture Structure of nFWEB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal nFWES_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + nFWE_pad: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>nFWES_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(nFWES_ipd, nFWES, tipd_nFWES); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, nFWES_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_nFWES_nFWES : x01 := '0'; + VARIABLE periodcheckinfo_nFWES : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => nFWES_ipd, + TestSignalName => "nFWES", + Period => tperiod_nFWES, + PulseWidthHigh => tpw_nFWES_posedge, + PulseWidthLow => tpw_nFWES_negedge, + PeriodData => periodcheckinfo_nFWES, + Violation => tviol_nFWES_nFWES, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => nFWES_ipd'last_event, + PathDelay => tpd_nFWES_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RCLKB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RCLKB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RCLKB"; + + tipd_RCLKS : VitalDelayType01 := (0 ns, 0 ns); + tpd_RCLKS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RCLKS : VitalDelayType := 0 ns; + tpw_RCLKS_posedge : VitalDelayType := 0 ns; + tpw_RCLKS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; RCLKS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RCLKB : ENTITY IS TRUE; + + end RCLKB; + + architecture Structure of RCLKB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal RCLKS_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + RCLK_pad: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>RCLKS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(RCLKS_ipd, RCLKS, tipd_RCLKS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, RCLKS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RCLKS_RCLKS : x01 := '0'; + VARIABLE periodcheckinfo_RCLKS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RCLKS_ipd, + TestSignalName => "RCLKS", + Period => tperiod_RCLKS, + PulseWidthHigh => tpw_RCLKS_posedge, + PulseWidthLow => tpw_RCLKS_negedge, + PeriodData => periodcheckinfo_RCLKS, + Violation => tviol_RCLKS_RCLKS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RCLKS_ipd'last_event, + PathDelay => tpd_RCLKS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity UFMSDOB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity UFMSDOB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "UFMSDOB"; + + tipd_UFMSDOS : VitalDelayType01 := (0 ns, 0 ns); + tpd_UFMSDOS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_UFMSDOS : VitalDelayType := 0 ns; + tpw_UFMSDOS_posedge : VitalDelayType := 0 ns; + tpw_UFMSDOS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; UFMSDOS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF UFMSDOB : ENTITY IS TRUE; + + end UFMSDOB; + + architecture Structure of UFMSDOB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal UFMSDOS_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + UFMSDO_pad: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>UFMSDOS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(UFMSDOS_ipd, UFMSDOS, tipd_UFMSDOS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, UFMSDOS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_UFMSDOS_UFMSDOS : x01 := '0'; + VARIABLE periodcheckinfo_UFMSDOS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => UFMSDOS_ipd, + TestSignalName => "UFMSDOS", + Period => tperiod_UFMSDOS, + PulseWidthHigh => tpw_UFMSDOS_posedge, + PulseWidthLow => tpw_UFMSDOS_negedge, + PeriodData => periodcheckinfo_UFMSDOS, + Violation => tviol_UFMSDOS_UFMSDOS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => UFMSDOS_ipd'last_event, + PathDelay => tpd_UFMSDOS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RAM2GS + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RAM2GS is + port (PHI2: in Std_logic; MAin: in Std_logic_vector (9 downto 0); + CROW: in Std_logic_vector (1 downto 0); + Din: in Std_logic_vector (7 downto 0); + Dout: out Std_logic_vector (7 downto 0); nCCAS: in Std_logic; + nCRAS: in Std_logic; nFWE: in Std_logic; LED: out Std_logic; + RBA: out Std_logic_vector (1 downto 0); + RA: out Std_logic_vector (11 downto 0); + RD: inout Std_logic_vector (7 downto 0); nRCS: out Std_logic; + RCLK: in Std_logic; RCKE: out Std_logic; nRWE: out Std_logic; + nRRAS: out Std_logic; nRCAS: out Std_logic; RDQMH: out Std_logic; + RDQML: out Std_logic; nUFMCS: out Std_logic; UFMCLK: out Std_logic; + UFMSDI: out Std_logic; UFMSDO: in Std_logic); + + + + end RAM2GS; + + architecture Structure of RAM2GS is + signal FS_7: Std_logic; + signal FS_6: Std_logic; + signal RCLK_c: Std_logic; + signal n2010: Std_logic; + signal n2011: Std_logic; + signal FS_15: Std_logic; + signal FS_14: Std_logic; + signal n2014: Std_logic; + signal n2015: Std_logic; + signal FS_5: Std_logic; + signal FS_4: Std_logic; + signal n2009: Std_logic; + signal FS_13: Std_logic; + signal FS_12: Std_logic; + signal n2013: Std_logic; + signal FS_1: Std_logic; + signal FS_0: Std_logic; + signal n2008: Std_logic; + signal FS_11: Std_logic; + signal FS_10: Std_logic; + signal n2012: Std_logic; + signal FS_3: Std_logic; + signal FS_2: Std_logic; + signal FS_9: Std_logic; + signal FS_8: Std_logic; + signal FS_17: Std_logic; + signal FS_16: Std_logic; + signal MAin_c_1: Std_logic; + signal n1326: Std_logic; + signal MAin_c_0: Std_logic; + signal n2263: Std_logic; + signal ADSubmitted: Std_logic; + signal n2242: Std_logic; + signal n2459: Std_logic; + signal n1413: Std_logic; + signal C1Submitted_N_237: Std_logic; + signal PHI2_c: Std_logic; + signal Din_c_6: Std_logic; + signal C1Submitted: Std_logic; + signal nFWE_c: Std_logic; + signal n6_adj_3: Std_logic; + signal n2284: Std_logic; + signal MAin_c_5: Std_logic; + signal n2316: Std_logic; + signal n26: Std_logic; + signal MAin_c_2: Std_logic; + signal n15: Std_logic; + signal n2463: Std_logic; + signal CmdEnable_N_248: Std_logic; + signal PHI2_N_120_enable_7: Std_logic; + signal CmdEnable: Std_logic; + signal PHI2r2: Std_logic; + signal CmdSubmitted: Std_logic; + signal PHI2r3: Std_logic; + signal n2568_001_BUF1: Std_logic; + signal PHI2_N_120_enable_5: Std_logic; + signal n2472: Std_logic; + signal Din_c_5: Std_logic; + signal Din_c_7: Std_logic; + signal n1314: Std_logic; + signal Din_c_4: Std_logic; + signal n8MEGEN: Std_logic; + signal Din_c_0: Std_logic; + signal Cmdn8MEGEN_N_264: Std_logic; + signal PHI2_N_120_enable_4: Std_logic; + signal Cmdn8MEGEN: Std_logic; + signal nRowColSel_N_35: Std_logic; + signal RASr2: Std_logic; + signal InitReady: Std_logic; + signal Ready: Std_logic; + signal n2568_000_BUF1: Std_logic; + signal RCLK_c_enable_25: Std_logic; + signal RCLK_c_enable_23: Std_logic; + signal nCRAS_c: Std_logic; + signal CBR: Std_logic; + signal LEDEN: Std_logic; + signal n2568: Std_logic; + signal RCLK_c_enable_12: Std_logic; + signal LED_N_84: Std_logic; + signal nRowColSel_N_34: Std_logic; + signal nRCAS_N_165: Std_logic; + signal n2208: Std_logic; + signal n2209: Std_logic; + signal nRWE_N_177: Std_logic; + signal RA_0S: Std_logic; + signal n56: Std_logic; + signal XOR8MEG: Std_logic; + signal RA11_N_184: Std_logic; + signal RA_c: Std_logic; + signal n2478: Std_logic; + signal RCKEEN_N_122: Std_logic; + signal RCKEEN_N_121: Std_logic; + signal RCLK_c_enable_4: Std_logic; + signal RCKEEN: Std_logic; + signal n2467: Std_logic; + signal RCKE_c: Std_logic; + signal RASr3: Std_logic; + signal RASr: Std_logic; + signal RCKE_N_132: Std_logic; + signal CASr: Std_logic; + signal nRWE_N_182: Std_logic; + signal CASr2: Std_logic; + signal n2568_002_BUF1: Std_logic; + signal Ready_N_292: Std_logic; + signal n2469: Std_logic; + signal n2462: Std_logic; + signal n62: Std_logic; + signal n1160: Std_logic; + signal CmdUFMCLK: Std_logic; + signal UFMCLK_N_224: Std_logic; + signal RCLK_c_enable_24: Std_logic; + signal n1846: Std_logic; + signal UFMCLK_c: Std_logic; + signal n2470: Std_logic; + signal n2272: Std_logic; + signal n2471: Std_logic; + signal CmdUFMSDI: Std_logic; + signal n2461: Std_logic; + signal UFMSDI_N_231: Std_logic; + signal UFMSDI_c: Std_logic; + signal Din_c_1: Std_logic; + signal n2324: Std_logic; + signal Din_c_2: Std_logic; + signal Din_c_3: Std_logic; + signal XOR8MEG_N_110: Std_logic; + signal PHI2_N_120_enable_1: Std_logic; + signal n2464: Std_logic; + signal n1325: Std_logic; + signal UFMSDO_c: Std_logic; + signal n8MEGEN_N_91: Std_logic; + signal RCLK_c_enable_11: Std_logic; + signal n2427: Std_logic; + signal n15_adj_1: Std_logic; + signal nRCAS_N_161: Std_logic; + signal nRCAS_c: Std_logic; + signal n13: Std_logic; + signal n2481: Std_logic; + signal nRCS_N_136: Std_logic; + signal nRCS_c: Std_logic; + signal nRCS_N_139: Std_logic; + signal nRowColSel_N_32: Std_logic; + signal n6: Std_logic; + signal nRRAS_c: Std_logic; + signal n2138: Std_logic; + signal nRWE_N_178: Std_logic; + signal n33: Std_logic; + signal nRWE_N_171: Std_logic; + signal RCLK_c_enable_3: Std_logic; + signal nRWE_c: Std_logic; + signal nRowColSel: Std_logic; + signal MAin_c_9: Std_logic; + signal RowA_9: Std_logic; + signal nRowColSel_N_28: Std_logic; + signal n1502: Std_logic; + signal n1410: Std_logic; + signal RA_1_9: Std_logic; + signal Ready_N_296: Std_logic; + signal nRowColSel_N_33: Std_logic; + signal n1503: Std_logic; + signal n2414: Std_logic; + signal n1093: Std_logic; + signal CmdUFMCS: Std_logic; + signal nUFMCS_c: Std_logic; + signal n11: Std_logic; + signal n1417: Std_logic; + signal n2322: Std_logic; + signal CASr3: Std_logic; + signal n12: Std_logic; + signal n2164: Std_logic; + signal LEDEN_N_82: Std_logic; + signal FWEr: Std_logic; + signal n2476: Std_logic; + signal n2475: Std_logic; + signal n13_adj_2: Std_logic; + signal n1: Std_logic; + signal n2214: Std_logic; + signal n2328: Std_logic; + signal n10: Std_logic; + signal n2458: Std_logic; + signal n732: Std_logic; + signal n733: Std_logic; + signal n2290: Std_logic; + signal n728: Std_logic; + signal n729: Std_logic; + signal n8: Std_logic; + signal n727: Std_logic; + signal MAin_c_7: Std_logic; + signal MAin_c_6: Std_logic; + signal RowA_6: Std_logic; + signal RowA_7: Std_logic; + signal n2468: Std_logic; + signal n1280: Std_logic; + signal PHI2r: Std_logic; + signal nCCAS_c: Std_logic; + signal n726: Std_logic; + signal Bank_3: Std_logic; + signal Bank_6: Std_logic; + signal Bank_5: Std_logic; + signal n2278: Std_logic; + signal n2314: Std_logic; + signal Bank_2: Std_logic; + signal PHI2_N_120_enable_6: Std_logic; + signal n14: Std_logic; + signal n2460: Std_logic; + signal n730: Std_logic; + signal n2262: Std_logic; + signal n2473: Std_logic; + signal n738: Std_logic; + signal n737: Std_logic; + signal n2474: Std_logic; + signal n2253: Std_logic; + signal CROW_c_1: Std_logic; + signal CROW_c_0: Std_logic; + signal RBA_c_0: Std_logic; + signal RBA_c_1: Std_logic; + signal n734: Std_logic; + signal n735: Std_logic; + signal n7: Std_logic; + signal n2451: Std_logic; + signal Bank_0: Std_logic; + signal Bank_1: Std_logic; + signal WRD_0: Std_logic; + signal WRD_1: Std_logic; + signal MAin_c_8: Std_logic; + signal RowA_8: Std_logic; + signal WRD_6: Std_logic; + signal WRD_7: Std_logic; + signal RDQMH_c: Std_logic; + signal RDQML_c: Std_logic; + signal MAin_c_4: Std_logic; + signal RowA_4: Std_logic; + signal RowA_5: Std_logic; + signal MAin_c_3: Std_logic; + signal RowA_3: Std_logic; + signal Bank_4: Std_logic; + signal RowA_2: Std_logic; + signal RA_1_3: Std_logic; + signal Bank_7: Std_logic; + signal RowA_0: Std_logic; + signal RA_1_4: Std_logic; + signal RowA_1: Std_logic; + signal RA_1_8: Std_logic; + signal RA_1_0: Std_logic; + signal RA_1_7: Std_logic; + signal RA_1_1: Std_logic; + signal n736: Std_logic; + signal RA_1_6: Std_logic; + signal RA_1_2: Std_logic; + signal WRD_2: Std_logic; + signal RA_1_5: Std_logic; + signal WRD_3: Std_logic; + signal WRD_4: Std_logic; + signal n984: Std_logic; + signal WRD_5: Std_logic; + signal Dout_c: Std_logic; + signal Dout_0S: Std_logic; + signal Dout_1S: Std_logic; + signal Dout_2S: Std_logic; + signal Dout_3S: Std_logic; + signal Dout_4S: Std_logic; + signal Dout_5S: Std_logic; + signal Dout_6S: Std_logic; + signal VCCI: Std_logic; + signal GNDI_TSALL: Std_logic; + component VHI + port (Z: out Std_logic); + end component; + component VLO + port (Z: out Std_logic); + end component; + component PUR + port (PUR: in Std_logic); + end component; + component GSR + port (GSR: in Std_logic); + end component; + component TSALL + port (TSALL: in Std_logic); + end component; + component SLICE_0 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + end component; + component SLICE_1 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + end component; + component SLICE_2 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + end component; + component SLICE_3 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + end component; + component SLICE_4 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_5 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + end component; + component SLICE_6 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + end component; + component SLICE_7 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + end component; + component SLICE_8 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_9 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_14 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_18 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_19 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_23 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_25 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_26 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_31 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_32 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_34 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_35 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_36 + port (B1: in Std_logic; A1: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_43 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_44 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_49 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_56 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_58 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; + Q0: out Std_logic); + end component; + component SLICE_60 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_61 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_63 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_64 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_65 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_66 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_67 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_68 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_69 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component RCKEEN_I_0_445_SLICE_70 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); + end component; + component i26_SLICE_71 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + OFX0: out Std_logic); + end component; + component i2099_SLICE_72 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); + end component; + component i26_adj_28_SLICE_73 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + OFX0: out Std_logic); + end component; + component SLICE_74 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_75 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_76 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_77 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_78 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_79 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_80 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_81 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_82 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_83 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_84 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_85 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_86 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_87 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_88 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_89 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_90 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_91 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_92 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_93 + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_94 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_95 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_96 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_97 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_98 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_99 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_100 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_101 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_102 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_103 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_104 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_105 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component RD_7_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD7: inout Std_logic); + end component; + component RD_6_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD6: inout Std_logic); + end component; + component RD_5_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD5: inout Std_logic); + end component; + component RD_4_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD4: inout Std_logic); + end component; + component RD_3_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD3: inout Std_logic); + end component; + component RD_2_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD2: inout Std_logic); + end component; + component RD_1_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD1: inout Std_logic); + end component; + component RD_0_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD0: inout Std_logic); + end component; + component Dout_7_B + port (PADDO: in Std_logic; Dout7: out Std_logic); + end component; + component Dout_6_B + port (PADDO: in Std_logic; Dout6: out Std_logic); + end component; + component Dout_5_B + port (PADDO: in Std_logic; Dout5: out Std_logic); + end component; + component Dout_4_B + port (PADDO: in Std_logic; Dout4: out Std_logic); + end component; + component Dout_3_B + port (PADDO: in Std_logic; Dout3: out Std_logic); + end component; + component Dout_2_B + port (PADDO: in Std_logic; Dout2: out Std_logic); + end component; + component Dout_1_B + port (PADDO: in Std_logic; Dout1: out Std_logic); + end component; + component Dout_0_B + port (PADDO: in Std_logic; Dout0: out Std_logic); + end component; + component LEDB + port (PADDO: in Std_logic; LEDS: out Std_logic); + end component; + component RBA_1_B + port (PADDO: in Std_logic; RBA1: out Std_logic); + end component; + component RBA_0_B + port (PADDO: in Std_logic; RBA0: out Std_logic); + end component; + component RA_11_B + port (PADDO: in Std_logic; RA11: out Std_logic); + end component; + component RA_10_B + port (PADDO: in Std_logic; RA10: out Std_logic); + end component; + component RA_9_B + port (PADDO: in Std_logic; RA9: out Std_logic); + end component; + component RA_8_B + port (PADDO: in Std_logic; RA8: out Std_logic); + end component; + component RA_7_B + port (PADDO: in Std_logic; RA7: out Std_logic); + end component; + component RA_6_B + port (PADDO: in Std_logic; RA6: out Std_logic); + end component; + component RA_5_B + port (PADDO: in Std_logic; RA5: out Std_logic); + end component; + component RA_4_B + port (PADDO: in Std_logic; RA4: out Std_logic); + end component; + component RA_3_B + port (PADDO: in Std_logic; RA3: out Std_logic); + end component; + component RA_2_B + port (PADDO: in Std_logic; RA2: out Std_logic); + end component; + component RA_1_B + port (PADDO: in Std_logic; RA1: out Std_logic); + end component; + component RA_0_B + port (PADDO: in Std_logic; RA0: out Std_logic); + end component; + component nRCSB + port (PADDO: in Std_logic; nRCSS: out Std_logic); + end component; + component RCKEB + port (PADDO: in Std_logic; RCKES: out Std_logic); + end component; + component nRWEB + port (PADDO: in Std_logic; nRWES: out Std_logic); + end component; + component nRRASB + port (PADDO: in Std_logic; nRRASS: out Std_logic); + end component; + component nRCASB + port (PADDO: in Std_logic; nRCASS: out Std_logic); + end component; + component RDQMHB + port (PADDO: in Std_logic; RDQMHS: out Std_logic); + end component; + component RDQMLB + port (PADDO: in Std_logic; RDQMLS: out Std_logic); + end component; + component nUFMCSB + port (PADDO: in Std_logic; nUFMCSS: out Std_logic); + end component; + component UFMCLKB + port (PADDO: in Std_logic; UFMCLKS: out Std_logic); + end component; + component UFMSDIB + port (PADDO: in Std_logic; UFMSDIS: out Std_logic); + end component; + component PHI2B + port (PADDI: out Std_logic; PHI2S: in Std_logic); + end component; + component MAin_9_B + port (PADDI: out Std_logic; MAin9: in Std_logic); + end component; + component MAin_8_B + port (PADDI: out Std_logic; MAin8: in Std_logic); + end component; + component MAin_7_B + port (PADDI: out Std_logic; MAin7: in Std_logic); + end component; + component MAin_6_B + port (PADDI: out Std_logic; MAin6: in Std_logic); + end component; + component MAin_5_B + port (PADDI: out Std_logic; MAin5: in Std_logic); + end component; + component MAin_4_B + port (PADDI: out Std_logic; MAin4: in Std_logic); + end component; + component MAin_3_B + port (PADDI: out Std_logic; MAin3: in Std_logic); + end component; + component MAin_2_B + port (PADDI: out Std_logic; MAin2: in Std_logic); + end component; + component MAin_1_B + port (PADDI: out Std_logic; MAin1: in Std_logic); + end component; + component MAin_0_B + port (PADDI: out Std_logic; MAin0: in Std_logic); + end component; + component CROW_1_B + port (PADDI: out Std_logic; CROW1: in Std_logic); + end component; + component CROW_0_B + port (PADDI: out Std_logic; CROW0: in Std_logic); + end component; + component Din_7_B + port (PADDI: out Std_logic; Din7: in Std_logic); + end component; + component Din_6_B + port (PADDI: out Std_logic; Din6: in Std_logic); + end component; + component Din_5_B + port (PADDI: out Std_logic; Din5: in Std_logic); + end component; + component Din_4_B + port (PADDI: out Std_logic; Din4: in Std_logic); + end component; + component Din_3_B + port (PADDI: out Std_logic; Din3: in Std_logic); + end component; + component Din_2_B + port (PADDI: out Std_logic; Din2: in Std_logic); + end component; + component Din_1_B + port (PADDI: out Std_logic; Din1: in Std_logic); + end component; + component Din_0_B + port (PADDI: out Std_logic; Din0: in Std_logic); + end component; + component nCCASB + port (PADDI: out Std_logic; nCCASS: in Std_logic); + end component; + component nCRASB + port (PADDI: out Std_logic; nCRASS: in Std_logic); + end component; + component nFWEB + port (PADDI: out Std_logic; nFWES: in Std_logic); + end component; + component RCLKB + port (PADDI: out Std_logic; RCLKS: in Std_logic); + end component; + component UFMSDOB + port (PADDI: out Std_logic; UFMSDOS: in Std_logic); + end component; + begin + SLICE_0I: SLICE_0 + port map (A1=>FS_7, A0=>FS_6, CLK=>RCLK_c, FCI=>n2010, Q0=>FS_6, + Q1=>FS_7, FCO=>n2011); + SLICE_1I: SLICE_1 + port map (A1=>FS_15, A0=>FS_14, CLK=>RCLK_c, FCI=>n2014, Q0=>FS_14, + Q1=>FS_15, FCO=>n2015); + SLICE_2I: SLICE_2 + port map (A1=>FS_5, A0=>FS_4, CLK=>RCLK_c, FCI=>n2009, Q0=>FS_4, + Q1=>FS_5, FCO=>n2010); + SLICE_3I: SLICE_3 + port map (A1=>FS_13, A0=>FS_12, CLK=>RCLK_c, FCI=>n2013, Q0=>FS_12, + Q1=>FS_13, FCO=>n2014); + SLICE_4I: SLICE_4 + port map (A1=>FS_1, A0=>FS_0, CLK=>RCLK_c, Q0=>FS_0, Q1=>FS_1, + FCO=>n2008); + SLICE_5I: SLICE_5 + port map (A1=>FS_11, A0=>FS_10, CLK=>RCLK_c, FCI=>n2012, Q0=>FS_10, + Q1=>FS_11, FCO=>n2013); + SLICE_6I: SLICE_6 + port map (A1=>FS_3, A0=>FS_2, CLK=>RCLK_c, FCI=>n2008, Q0=>FS_2, + Q1=>FS_3, FCO=>n2009); + SLICE_7I: SLICE_7 + port map (A1=>FS_9, A0=>FS_8, CLK=>RCLK_c, FCI=>n2011, Q0=>FS_8, + Q1=>FS_9, FCO=>n2012); + SLICE_8I: SLICE_8 + port map (A1=>FS_17, A0=>FS_16, CLK=>RCLK_c, FCI=>n2015, Q0=>FS_16, + Q1=>FS_17); + SLICE_9I: SLICE_9 + port map (C1=>MAin_c_1, B1=>n1326, A1=>MAin_c_0, D0=>n2263, + C0=>ADSubmitted, B0=>n2242, A0=>n2459, DI0=>n1413, + LSR=>C1Submitted_N_237, CLK=>PHI2_c, F0=>n1413, + Q0=>ADSubmitted, F1=>n2263); + SLICE_14I: SLICE_14 + port map (B1=>Din_c_6, A1=>C1Submitted, D0=>MAin_c_1, C0=>C1Submitted, + B0=>n1326, A0=>nFWE_c, DI0=>n6_adj_3, LSR=>C1Submitted_N_237, + CLK=>PHI2_c, F0=>n6_adj_3, Q0=>C1Submitted, F1=>n2284); + SLICE_18I: SLICE_18 + port map (D1=>MAin_c_5, C1=>n2316, B1=>n26, A1=>MAin_c_2, D0=>n15, + C0=>n1326, B0=>n2463, A0=>MAin_c_1, DI0=>CmdEnable_N_248, + CE=>PHI2_N_120_enable_7, CLK=>PHI2_c, F0=>CmdEnable_N_248, + Q0=>CmdEnable, F1=>n1326); + SLICE_19I: SLICE_19 + port map (C1=>PHI2r2, B1=>CmdSubmitted, A1=>PHI2r3, DI0=>n2568_001_BUF1, + CE=>PHI2_N_120_enable_5, CLK=>PHI2_c, F0=>n2568_001_BUF1, + Q0=>CmdSubmitted, F1=>n2472); + SLICE_23I: SLICE_23 + port map (C1=>Din_c_5, B1=>Din_c_7, A1=>Din_c_6, D0=>n1314, C0=>Din_c_4, + B0=>n8MEGEN, A0=>Din_c_0, DI0=>Cmdn8MEGEN_N_264, + CE=>PHI2_N_120_enable_4, CLK=>PHI2_c, F0=>Cmdn8MEGEN_N_264, + Q0=>Cmdn8MEGEN, F1=>n1314); + SLICE_25I: SLICE_25 + port map (D1=>nRowColSel_N_35, C1=>RASr2, B1=>InitReady, A1=>Ready, + DI0=>n2568_000_BUF1, CE=>RCLK_c_enable_25, CLK=>RCLK_c, + F0=>n2568_000_BUF1, Q0=>InitReady, F1=>RCLK_c_enable_23); + SLICE_26I: SLICE_26 + port map (C1=>nCRAS_c, B1=>CBR, A1=>LEDEN, DI0=>n2568, + CE=>RCLK_c_enable_12, CLK=>RCLK_c, F0=>n2568, Q0=>LEDEN, + F1=>LED_N_84); + SLICE_31I: SLICE_31 + port map (B1=>nRowColSel_N_34, A1=>Ready, C0=>nRCAS_N_165, B0=>Ready, + A0=>n2208, DI0=>n2209, LSR=>nRWE_N_177, CLK=>RCLK_c, F0=>n2209, + Q0=>RA_0S, F1=>n56); + SLICE_32I: SLICE_32 + port map (B1=>Din_c_7, A1=>Din_c_6, C0=>n8MEGEN, B0=>XOR8MEG, + A0=>Din_c_6, DI0=>RA11_N_184, LSR=>Ready, CLK=>PHI2_c, + F0=>RA11_N_184, Q0=>RA_c, F1=>n2478); + SLICE_34I: SLICE_34 + port map (C1=>Ready, B1=>InitReady, A1=>RASr2, C0=>Ready, + B0=>RCKEEN_N_122, A0=>InitReady, DI0=>RCKEEN_N_121, + CE=>RCLK_c_enable_4, CLK=>RCLK_c, F0=>RCKEEN_N_121, Q0=>RCKEEN, + F1=>n2467); + SLICE_35I: SLICE_35 + port map (B1=>RCKE_c, A1=>RASr2, D0=>RASr3, C0=>RASr2, B0=>RCKEEN, + A0=>RASr, DI0=>RCKE_N_132, M1=>CASr, CLK=>RCLK_c, + F0=>RCKE_N_132, Q0=>RCKE_c, F1=>nRWE_N_182, Q1=>CASr2); + SLICE_36I: SLICE_36 + port map (B1=>nRowColSel_N_35, A1=>Ready, DI0=>n2568_002_BUF1, + CE=>Ready_N_292, CLK=>RCLK_c, F0=>n2568_002_BUF1, Q0=>Ready, + F1=>n2469); + SLICE_43I: SLICE_43 + port map (D1=>FS_1, C1=>n2462, B1=>n62, A1=>FS_4, C0=>InitReady, + B0=>n1160, A0=>CmdUFMCLK, DI0=>UFMCLK_N_224, + CE=>RCLK_c_enable_24, LSR=>n1846, CLK=>RCLK_c, + F0=>UFMCLK_N_224, Q0=>UFMCLK_c, F1=>n1160); + SLICE_44I: SLICE_44 + port map (D1=>FS_11, C1=>n2470, B1=>n2272, A1=>n2471, D0=>CmdUFMSDI, + C0=>InitReady, B0=>n2462, A0=>n2461, DI0=>UFMSDI_N_231, + CE=>RCLK_c_enable_24, LSR=>n1846, CLK=>RCLK_c, + F0=>UFMSDI_N_231, Q0=>UFMSDI_c, F1=>n2462); + SLICE_49I: SLICE_49 + port map (D1=>Din_c_1, C1=>n1314, B1=>LEDEN, A1=>Din_c_4, D0=>n2324, + C0=>Din_c_2, B0=>Din_c_3, A0=>Din_c_0, DI0=>XOR8MEG_N_110, + CE=>PHI2_N_120_enable_1, CLK=>PHI2_c, F0=>XOR8MEG_N_110, + Q0=>XOR8MEG, F1=>n2324); + SLICE_56I: SLICE_56 + port map (C1=>FS_10, B1=>n2464, A1=>FS_11, D0=>n1325, C0=>InitReady, + B0=>Cmdn8MEGEN, A0=>UFMSDO_c, DI0=>n8MEGEN_N_91, + CE=>RCLK_c_enable_11, CLK=>RCLK_c, F0=>n8MEGEN_N_91, + Q0=>n8MEGEN, F1=>n1325); + SLICE_58I: SLICE_58 + port map (D1=>n2427, C1=>RASr2, B1=>CBR, A1=>Ready, C0=>Ready, + B0=>n15_adj_1, A0=>nRowColSel_N_34, DI0=>nRCAS_N_161, + M0=>nRowColSel_N_35, CE=>RCLK_c_enable_4, CLK=>RCLK_c, + OFX0=>nRCAS_N_161, Q0=>nRCAS_c); + SLICE_60I: SLICE_60 + port map (D1=>Ready, C1=>RCKE_c, B1=>InitReady, A1=>RASr2, + D0=>nRowColSel_N_35, C0=>n13, B0=>n2481, A0=>n2467, + DI0=>nRCS_N_136, CE=>RCLK_c_enable_4, CLK=>RCLK_c, + F0=>nRCS_N_136, Q0=>nRCS_c, F1=>n13); + SLICE_61I: SLICE_61 + port map (C1=>nRCS_N_139, B1=>n13, A1=>Ready, D0=>nRowColSel_N_32, + C0=>n6, B0=>nRRAS_c, A0=>n56, DI0=>n2138, M0=>nRowColSel_N_35, + CLK=>RCLK_c, OFX0=>n2138, Q0=>nRRAS_c); + SLICE_63I: SLICE_63 + port map (D1=>nRCS_N_139, C1=>InitReady, B1=>RASr2, A1=>nRowColSel_N_35, + D0=>n2208, C0=>Ready, B0=>nRWE_N_178, A0=>n33, DI0=>nRWE_N_171, + CE=>RCLK_c_enable_3, CLK=>RCLK_c, F0=>nRWE_N_171, Q0=>nRWE_c, + F1=>n2208); + SLICE_64I: SLICE_64 + port map (C1=>nRowColSel, B1=>MAin_c_9, A1=>RowA_9, D0=>nRowColSel_N_32, + C0=>nRowColSel_N_28, B0=>n1502, A0=>nRowColSel, DI0=>n1410, + LSR=>n2469, CLK=>RCLK_c, F0=>n1410, Q0=>nRowColSel, F1=>RA_1_9); + SLICE_65I: SLICE_65 + port map (D1=>InitReady, C1=>Ready_N_296, B1=>RASr2, A1=>nRowColSel_N_32, + B0=>nRowColSel_N_33, A0=>nRowColSel_N_32, DI0=>n1503, + LSR=>RASr2, CLK=>RCLK_c, F0=>n1503, Q0=>nRowColSel_N_32, + F1=>n2414); + SLICE_66I: SLICE_66 + port map (D1=>nRowColSel_N_33, C1=>nRowColSel_N_34, B1=>n2469, + A1=>nRowColSel_N_32, B0=>RASr2, A0=>nRowColSel_N_32, + DI0=>n1093, LSR=>nRowColSel_N_34, CLK=>RCLK_c, F0=>n1093, + Q0=>nRowColSel_N_33, F1=>RCLK_c_enable_4); + SLICE_67I: SLICE_67 + port map (C1=>n2472, B1=>CmdUFMCS, A1=>nUFMCS_c, B0=>CASr2, + A0=>nRowColSel_N_33, M0=>n1093, LSR=>nRowColSel_N_35, + CLK=>RCLK_c, F0=>n11, Q0=>nRowColSel_N_34, F1=>n1417); + SLICE_68I: SLICE_68 + port map (B1=>FS_12, A1=>FS_17, D0=>FS_3, C0=>FS_6, B0=>FS_1, A0=>FS_0, + M1=>CASr2, M0=>RASr2, CLK=>RCLK_c, F0=>n2322, + Q0=>nRowColSel_N_35, F1=>n2471, Q1=>CASr3); + SLICE_69I: SLICE_69 + port map (D1=>FS_14, C1=>FS_12, B1=>n12, A1=>FS_17, C0=>InitReady, + B0=>n1417, A0=>n62, DI0=>n2164, LSR=>LEDEN_N_82, CLK=>RCLK_c, + F0=>n2164, Q0=>nUFMCS_c, F1=>n62); + RCKEEN_I_0_445_SLICE_70I: RCKEEN_I_0_445_SLICE_70 + port map (C1=>RASr2, B1=>FWEr, A1=>CBR, D0=>nRowColSel_N_34, C0=>FWEr, + B0=>n11, A0=>CBR, M0=>nRowColSel_N_35, OFX0=>RCKEEN_N_122); + i26_SLICE_71I: i26_SLICE_71 + port map (D1=>n2284, C1=>n2476, B1=>MAin_c_1, A1=>MAin_c_0, + D0=>ADSubmitted, C0=>MAin_c_0, B0=>n2475, A0=>Din_c_5, + M0=>Din_c_2, OFX0=>n13_adj_2); + i2099_SLICE_72I: i2099_SLICE_72 + port map (D1=>nRowColSel_N_34, C1=>nRowColSel_N_35, B1=>Ready, + A1=>nRCS_N_139, C0=>nRowColSel_N_35, B0=>Ready, A0=>nRCS_N_139, + M0=>n15_adj_1, OFX0=>n2481); + i26_adj_28_SLICE_73I: i26_adj_28_SLICE_73 + port map (D1=>MAin_c_0, C1=>Din_c_2, B1=>Din_c_3, A1=>Din_c_6, + D0=>MAin_c_0, C0=>Din_c_2, B0=>Din_c_3, A0=>Din_c_6, + M0=>Din_c_5, OFX0=>n15); + SLICE_74I: SLICE_74 + port map (D1=>n1, C1=>nRowColSel_N_33, B1=>CBR, A1=>FWEr, D0=>CASr3, + C0=>CASr2, B0=>FWEr, A0=>CBR, M1=>RASr2, M0=>RASr, CLK=>RCLK_c, + F0=>n1, Q0=>RASr2, F1=>n15_adj_1, Q1=>RASr3); + SLICE_75I: SLICE_75 + port map (C1=>InitReady, B1=>FS_11, A1=>n2214, D0=>FS_11, C0=>n2272, + B0=>n2328, A0=>FS_10, F0=>n2214, F1=>RCLK_c_enable_12); + SLICE_76I: SLICE_76 + port map (D1=>MAin_c_0, C1=>n10, B1=>n1326, A1=>nFWE_c, D0=>n2458, + C0=>Din_c_4, B0=>Din_c_5, A0=>Din_c_3, M1=>n732, M0=>n733, + CE=>RCLK_c_enable_23, CLK=>RCLK_c, F0=>PHI2_N_120_enable_4, + Q0=>n732, F1=>n2458, Q1=>nRWE_N_177); + SLICE_77I: SLICE_77 + port map (D1=>FS_7, C1=>n2322, B1=>FS_4, A1=>n2290, C0=>FS_9, B0=>FS_5, + A0=>FS_2, M1=>n728, M0=>n729, CE=>RCLK_c_enable_23, + CLK=>RCLK_c, F0=>n2290, Q0=>n728, F1=>n8, Q1=>n727); + SLICE_78I: SLICE_78 + port map (D1=>n2471, C1=>n2272, B1=>FS_14, A1=>FS_16, C0=>InitReady, + B0=>n2464, A0=>FS_11, M1=>MAin_c_7, M0=>MAin_c_6, LSR=>Ready, + CLK=>nCRAS_c, F0=>n1846, Q0=>RowA_6, F1=>n2464, Q1=>RowA_7); + SLICE_79I: SLICE_79 + port map (C1=>Din_c_5, B1=>Din_c_3, A1=>Din_c_6, D0=>n2468, C0=>n1280, + B0=>n2463, A0=>Din_c_2, M1=>PHI2r, M0=>nCCAS_c, CLK=>RCLK_c, + F0=>C1Submitted_N_237, Q0=>CASr, F1=>n2468, Q1=>PHI2r2); + SLICE_80I: SLICE_80 + port map (B1=>nRowColSel_N_33, A1=>nRowColSel_N_34, D0=>nRowColSel_N_35, + C0=>n1502, B0=>nRowColSel_N_32, A0=>Ready, M1=>n726, M0=>n727, + CE=>RCLK_c_enable_23, CLK=>RCLK_c, F0=>RCLK_c_enable_3, + Q0=>n726, F1=>n1502, Q1=>Ready_N_296); + SLICE_81I: SLICE_81 + port map (B1=>Bank_3, A1=>Bank_6, D0=>Bank_5, C0=>n2278, B0=>n2314, + A0=>Bank_2, M1=>Din_c_2, M0=>Din_c_1, CE=>PHI2_N_120_enable_6, + CLK=>PHI2_c, F0=>n26, Q0=>CmdUFMCLK, F1=>n2278, Q1=>CmdUFMCS); + SLICE_82I: SLICE_82 + port map (D1=>MAin_c_1, C1=>n14, B1=>n2460, A1=>MAin_c_0, B0=>n1326, + A0=>nFWE_c, M1=>n730, M0=>nRWE_N_177, CE=>RCLK_c_enable_23, + CLK=>RCLK_c, F0=>n2460, Q0=>n730, F1=>PHI2_N_120_enable_7, + Q1=>n729); + SLICE_83I: SLICE_83 + port map (D1=>n2476, C1=>n2460, B1=>n10, A1=>MAin_c_0, D0=>MAin_c_1, + C0=>CmdEnable, B0=>n2478, A0=>Din_c_4, M0=>nCRAS_c, + CLK=>RCLK_c, F0=>n10, Q0=>RASr, F1=>PHI2_N_120_enable_6); + SLICE_84I: SLICE_84 + port map (D1=>n1314, C1=>n2262, B1=>CmdEnable, A1=>n2473, C0=>MAin_c_1, + B0=>n1326, A0=>MAin_c_0, M1=>n738, M0=>nRCAS_N_165, + CE=>RCLK_c_enable_23, CLK=>RCLK_c, F0=>n2262, Q0=>n738, + F1=>PHI2_N_120_enable_1, Q1=>n737); + SLICE_85I: SLICE_85 + port map (D1=>n2474, C1=>Din_c_5, B1=>n2253, A1=>n2473, B0=>nFWE_c, + A0=>Din_c_4, M1=>CROW_c_1, M0=>CROW_c_0, LSR=>Ready, + CLK=>nCRAS_c, F0=>n2473, Q0=>RBA_c_0, F1=>n2242, Q1=>RBA_c_1); + SLICE_86I: SLICE_86 + port map (C1=>Din_c_1, B1=>Din_c_0, A1=>Din_c_7, C0=>n2253, B0=>nFWE_c, + A0=>Din_c_4, M1=>n734, M0=>n735, CE=>RCLK_c_enable_23, + CLK=>RCLK_c, F0=>n2463, Q0=>n734, F1=>n2253, Q1=>n733); + SLICE_87I: SLICE_87 + port map (B1=>n2214, A1=>FS_8, D0=>n8, C0=>InitReady, B0=>n2472, A0=>n7, + M1=>nRCS_N_139, M0=>Ready_N_296, CE=>RCLK_c_enable_23, + CLK=>RCLK_c, F0=>RCLK_c_enable_11, Q0=>nRCS_N_139, F1=>n7, + Q1=>nRCAS_N_165); + SLICE_88I: SLICE_88 + port map (C1=>FS_10, B1=>FS_6, A1=>n2451, D0=>FS_8, C0=>FS_5, B0=>FS_9, + A0=>FS_7, M1=>Din_c_1, M0=>Din_c_0, CLK=>PHI2_c, F0=>n2451, + Q0=>Bank_0, F1=>n2461, Q1=>Bank_1); + SLICE_89I: SLICE_89 + port map (C1=>MAin_c_1, B1=>n1326, A1=>nFWE_c, C0=>MAin_c_0, B0=>n1326, + A0=>MAin_c_1, M1=>Din_c_1, M0=>Din_c_0, CLK=>nCCAS_c, + F0=>n1280, Q0=>WRD_0, F1=>n2459, Q1=>WRD_1); + SLICE_90I: SLICE_90 + port map (D1=>FS_16, C1=>FS_14, B1=>FS_12, A1=>FS_17, B0=>FS_14, + A0=>FS_16, M1=>MAin_c_9, M0=>MAin_c_8, LSR=>Ready, + CLK=>nCRAS_c, F0=>n2470, Q0=>RowA_8, F1=>n2328, Q1=>RowA_9); + SLICE_91I: SLICE_91 + port map (B1=>Din_c_5, A1=>Din_c_3, D0=>n2458, C0=>Din_c_5, B0=>Din_c_4, + A0=>Din_c_3, M1=>PHI2_c, M0=>PHI2r2, CLK=>RCLK_c, + F0=>PHI2_N_120_enable_5, Q0=>PHI2r3, F1=>n2476, Q1=>PHI2r); + SLICE_92I: SLICE_92 + port map (B1=>Din_c_3, A1=>Din_c_6, C0=>Din_c_3, B0=>Din_c_2, + A0=>Din_c_6, M1=>Din_c_7, M0=>Din_c_6, CLK=>nCCAS_c, F0=>n2474, + Q0=>WRD_6, F1=>n2475, Q1=>WRD_7); + SLICE_93I: SLICE_93 + port map (B1=>nRowColSel, A1=>MAin_c_9, B0=>nRowColSel, A0=>MAin_c_9, + M0=>Din_c_0, CE=>PHI2_N_120_enable_6, CLK=>PHI2_c, F0=>RDQMH_c, + Q0=>CmdUFMSDI, F1=>RDQML_c); + SLICE_94I: SLICE_94 + port map (B1=>FS_15, A1=>FS_13, D0=>FS_11, C0=>FS_16, B0=>FS_13, + A0=>FS_15, F0=>n12, F1=>n2272); + SLICE_95I: SLICE_95 + port map (B1=>FS_10, A1=>n62, D0=>InitReady, C0=>FS_10, B0=>n2464, + A0=>FS_11, M1=>MAin_c_5, M0=>MAin_c_4, LSR=>Ready, + CLK=>nCRAS_c, F0=>LEDEN_N_82, Q0=>RowA_4, F1=>RCLK_c_enable_25, + Q1=>RowA_5); + SLICE_96I: SLICE_96 + port map (C1=>nRowColSel, B1=>MAin_c_3, A1=>RowA_3, D0=>Bank_1, + C0=>Bank_4, B0=>MAin_c_3, A0=>MAin_c_7, M1=>MAin_c_3, + M0=>MAin_c_2, LSR=>Ready, CLK=>nCRAS_c, F0=>n2316, Q0=>RowA_2, + F1=>RA_1_3, Q1=>RowA_3); + SLICE_97I: SLICE_97 + port map (C1=>nRowColSel, B1=>MAin_c_4, A1=>RowA_4, D0=>Bank_0, + C0=>Bank_7, B0=>MAin_c_4, A0=>MAin_c_6, M1=>MAin_c_1, + M0=>MAin_c_0, LSR=>Ready, CLK=>nCRAS_c, F0=>n2314, Q0=>RowA_0, + F1=>RA_1_4, Q1=>RowA_1); + SLICE_98I: SLICE_98 + port map (C1=>nRowColSel, B1=>MAin_c_0, A1=>RowA_0, C0=>nRowColSel, + B0=>MAin_c_8, A0=>RowA_8, M1=>nFWE_c, M0=>nCCAS_c, + CLK=>nCRAS_c, F0=>RA_1_8, Q0=>CBR, F1=>RA_1_0, Q1=>FWEr); + SLICE_99I: SLICE_99 + port map (C1=>nRowColSel, B1=>MAin_c_1, A1=>RowA_1, C0=>nRowColSel, + B0=>MAin_c_7, A0=>RowA_7, M1=>Din_c_7, M0=>Din_c_6, + CLK=>PHI2_c, F0=>RA_1_7, Q0=>Bank_6, F1=>RA_1_1, Q1=>Bank_7); + SLICE_100I: SLICE_100 + port map (D1=>Ready, C1=>nRowColSel_N_33, B1=>InitReady, A1=>RASr2, + D0=>InitReady, C0=>PHI2r2, B0=>CmdSubmitted, A0=>PHI2r3, + M1=>n736, M0=>n737, CE=>RCLK_c_enable_23, CLK=>RCLK_c, + F0=>RCLK_c_enable_24, Q0=>n736, F1=>n6, Q1=>n735); + SLICE_101I: SLICE_101 + port map (C1=>nRowColSel, B1=>MAin_c_2, A1=>RowA_2, C0=>nRowColSel, + B0=>MAin_c_6, A0=>RowA_6, M1=>Din_c_5, M0=>Din_c_4, + CLK=>PHI2_c, F0=>RA_1_6, Q0=>Bank_4, F1=>RA_1_2, Q1=>Bank_5); + SLICE_102I: SLICE_102 + port map (B1=>nRWE_N_177, A1=>nRCAS_N_165, C0=>nRCAS_N_165, + B0=>nRCS_N_139, A0=>InitReady, M1=>Din_c_3, M0=>Din_c_2, + CLK=>PHI2_c, F0=>n2427, Q0=>Bank_2, F1=>n33, Q1=>Bank_3); + SLICE_103I: SLICE_103 + port map (C1=>nRowColSel, B1=>MAin_c_5, A1=>RowA_5, C0=>CBR, B0=>CASr3, + A0=>FWEr, M1=>Din_c_3, M0=>Din_c_2, CLK=>nCCAS_c, + F0=>nRowColSel_N_28, Q0=>WRD_2, F1=>RA_1_5, Q1=>WRD_3); + SLICE_104I: SLICE_104 + port map (B1=>Ready, A1=>n2414, D0=>nRowColSel_N_35, C0=>nRWE_N_182, + B0=>n1502, A0=>n1, F0=>nRWE_N_178, F1=>Ready_N_292); + SLICE_105I: SLICE_105 + port map (B1=>nFWE_c, A1=>nCCAS_c, C0=>n13_adj_2, B0=>Din_c_4, A0=>n2253, + M1=>Din_c_5, M0=>Din_c_4, CLK=>nCCAS_c, F0=>n14, Q0=>WRD_4, + F1=>n984, Q1=>WRD_5); + RD_7_I: RD_7_B + port map (PADDI=>Dout_c, PADDT=>n984, PADDO=>WRD_7, RD7=>RD(7)); + RD_6_I: RD_6_B + port map (PADDI=>Dout_0S, PADDT=>n984, PADDO=>WRD_6, RD6=>RD(6)); + RD_5_I: RD_5_B + port map (PADDI=>Dout_1S, PADDT=>n984, PADDO=>WRD_5, RD5=>RD(5)); + RD_4_I: RD_4_B + port map (PADDI=>Dout_2S, PADDT=>n984, PADDO=>WRD_4, RD4=>RD(4)); + RD_3_I: RD_3_B + port map (PADDI=>Dout_3S, PADDT=>n984, PADDO=>WRD_3, RD3=>RD(3)); + RD_2_I: RD_2_B + port map (PADDI=>Dout_4S, PADDT=>n984, PADDO=>WRD_2, RD2=>RD(2)); + RD_1_I: RD_1_B + port map (PADDI=>Dout_5S, PADDT=>n984, PADDO=>WRD_1, RD1=>RD(1)); + RD_0_I: RD_0_B + port map (PADDI=>Dout_6S, PADDT=>n984, PADDO=>WRD_0, RD0=>RD(0)); + Dout_7_I: Dout_7_B + port map (PADDO=>Dout_c, Dout7=>Dout(7)); + Dout_6_I: Dout_6_B + port map (PADDO=>Dout_0S, Dout6=>Dout(6)); + Dout_5_I: Dout_5_B + port map (PADDO=>Dout_1S, Dout5=>Dout(5)); + Dout_4_I: Dout_4_B + port map (PADDO=>Dout_2S, Dout4=>Dout(4)); + Dout_3_I: Dout_3_B + port map (PADDO=>Dout_3S, Dout3=>Dout(3)); + Dout_2_I: Dout_2_B + port map (PADDO=>Dout_4S, Dout2=>Dout(2)); + Dout_1_I: Dout_1_B + port map (PADDO=>Dout_5S, Dout1=>Dout(1)); + Dout_0_I: Dout_0_B + port map (PADDO=>Dout_6S, Dout0=>Dout(0)); + LEDI: LEDB + port map (PADDO=>LED_N_84, LEDS=>LED); + RBA_1_I: RBA_1_B + port map (PADDO=>RBA_c_1, RBA1=>RBA(1)); + RBA_0_I: RBA_0_B + port map (PADDO=>RBA_c_0, RBA0=>RBA(0)); + RA_11_I: RA_11_B + port map (PADDO=>RA_c, RA11=>RA(11)); + RA_10_I: RA_10_B + port map (PADDO=>RA_0S, RA10=>RA(10)); + RA_9_I: RA_9_B + port map (PADDO=>RA_1_9, RA9=>RA(9)); + RA_8_I: RA_8_B + port map (PADDO=>RA_1_8, RA8=>RA(8)); + RA_7_I: RA_7_B + port map (PADDO=>RA_1_7, RA7=>RA(7)); + RA_6_I: RA_6_B + port map (PADDO=>RA_1_6, RA6=>RA(6)); + RA_5_I: RA_5_B + port map (PADDO=>RA_1_5, RA5=>RA(5)); + RA_4_I: RA_4_B + port map (PADDO=>RA_1_4, RA4=>RA(4)); + RA_3_I: RA_3_B + port map (PADDO=>RA_1_3, RA3=>RA(3)); + RA_2_I: RA_2_B + port map (PADDO=>RA_1_2, RA2=>RA(2)); + RA_1_I: RA_1_B + port map (PADDO=>RA_1_1, RA1=>RA(1)); + RA_0_I: RA_0_B + port map (PADDO=>RA_1_0, RA0=>RA(0)); + nRCSI: nRCSB + port map (PADDO=>nRCS_c, nRCSS=>nRCS); + RCKEI: RCKEB + port map (PADDO=>RCKE_c, RCKES=>RCKE); + nRWEI: nRWEB + port map (PADDO=>nRWE_c, nRWES=>nRWE); + nRRASI: nRRASB + port map (PADDO=>nRRAS_c, nRRASS=>nRRAS); + nRCASI: nRCASB + port map (PADDO=>nRCAS_c, nRCASS=>nRCAS); + RDQMHI: RDQMHB + port map (PADDO=>RDQMH_c, RDQMHS=>RDQMH); + RDQMLI: RDQMLB + port map (PADDO=>RDQML_c, RDQMLS=>RDQML); + nUFMCSI: nUFMCSB + port map (PADDO=>nUFMCS_c, nUFMCSS=>nUFMCS); + UFMCLKI: UFMCLKB + port map (PADDO=>UFMCLK_c, UFMCLKS=>UFMCLK); + UFMSDII: UFMSDIB + port map (PADDO=>UFMSDI_c, UFMSDIS=>UFMSDI); + PHI2I: PHI2B + port map (PADDI=>PHI2_c, PHI2S=>PHI2); + MAin_9_I: MAin_9_B + port map (PADDI=>MAin_c_9, MAin9=>MAin(9)); + MAin_8_I: MAin_8_B + port map (PADDI=>MAin_c_8, MAin8=>MAin(8)); + MAin_7_I: MAin_7_B + port map (PADDI=>MAin_c_7, MAin7=>MAin(7)); + MAin_6_I: MAin_6_B + port map (PADDI=>MAin_c_6, MAin6=>MAin(6)); + MAin_5_I: MAin_5_B + port map (PADDI=>MAin_c_5, MAin5=>MAin(5)); + MAin_4_I: MAin_4_B + port map (PADDI=>MAin_c_4, MAin4=>MAin(4)); + MAin_3_I: MAin_3_B + port map (PADDI=>MAin_c_3, MAin3=>MAin(3)); + MAin_2_I: MAin_2_B + port map (PADDI=>MAin_c_2, MAin2=>MAin(2)); + MAin_1_I: MAin_1_B + port map (PADDI=>MAin_c_1, MAin1=>MAin(1)); + MAin_0_I: MAin_0_B + port map (PADDI=>MAin_c_0, MAin0=>MAin(0)); + CROW_1_I: CROW_1_B + port map (PADDI=>CROW_c_1, CROW1=>CROW(1)); + CROW_0_I: CROW_0_B + port map (PADDI=>CROW_c_0, CROW0=>CROW(0)); + Din_7_I: Din_7_B + port map (PADDI=>Din_c_7, Din7=>Din(7)); + Din_6_I: Din_6_B + port map (PADDI=>Din_c_6, Din6=>Din(6)); + Din_5_I: Din_5_B + port map (PADDI=>Din_c_5, Din5=>Din(5)); + Din_4_I: Din_4_B + port map (PADDI=>Din_c_4, Din4=>Din(4)); + Din_3_I: Din_3_B + port map (PADDI=>Din_c_3, Din3=>Din(3)); + Din_2_I: Din_2_B + port map (PADDI=>Din_c_2, Din2=>Din(2)); + Din_1_I: Din_1_B + port map (PADDI=>Din_c_1, Din1=>Din(1)); + Din_0_I: Din_0_B + port map (PADDI=>Din_c_0, Din0=>Din(0)); + nCCASI: nCCASB + port map (PADDI=>nCCAS_c, nCCASS=>nCCAS); + nCRASI: nCRASB + port map (PADDI=>nCRAS_c, nCRASS=>nCRAS); + nFWEI: nFWEB + port map (PADDI=>nFWE_c, nFWES=>nFWE); + RCLKI: RCLKB + port map (PADDI=>RCLK_c, RCLKS=>RCLK); + UFMSDOI: UFMSDOB + port map (PADDI=>UFMSDO_c, UFMSDOS=>UFMSDO); + VHI_INST: VHI + port map (Z=>VCCI); + PUR_INST: PUR + port map (PUR=>VCCI); + GSR_INST: GSR + port map (GSR=>VCCI); + VLO_INST: VLO + port map (Z=>GNDI_TSALL); + TSALL_INST: TSALL + port map (TSALL=>GNDI_TSALL); + end Structure; + + + + library IEEE, vital2000, MACHXO; + configuration Structure_CON of RAM2GS is + for Structure + end for; + end Structure_CON; + + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvo.sdf b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvo.sdf new file mode 100644 index 0000000..bf5db84 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvo.sdf @@ -0,0 +1,3036 @@ +(DELAYFILE + (SDFVERSION "3.0") + (DESIGN "RAM2GS") + (DATE "Tue Aug 15 05:03:24 2023") + (VENDOR "Lattice") + (PROGRAM "ldbanno") + (VERSION "Diamond (64-bit) 3.12.1.454") + (DIVIDER /) + (VOLTAGE 1.26:1.20:1.14) + (PROCESS "default") + (TEMPERATURE -40:25:85) + (TIMESCALE 1ps) + (CELL + (CELLTYPE "SLICE_0") + (INSTANCE SLICE_0) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_1") + (INSTANCE SLICE_1) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_2") + (INSTANCE SLICE_2) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_3") + (INSTANCE SLICE_3) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_4") + (INSTANCE SLICE_4) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + ) + ) + (CELL + (CELLTYPE "SLICE_5") + (INSTANCE SLICE_5) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_6") + (INSTANCE SLICE_6) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_7") + (INSTANCE SLICE_7) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_8") + (INSTANCE SLICE_8) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_9") + (INSTANCE SLICE_9) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_14") + (INSTANCE SLICE_14) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_18") + (INSTANCE SLICE_18) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_19") + (INSTANCE SLICE_19) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_23") + (INSTANCE SLICE_23) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_25") + (INSTANCE SLICE_25) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_26") + (INSTANCE SLICE_26) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_31") + (INSTANCE SLICE_31) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_32") + (INSTANCE SLICE_32) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_34") + (INSTANCE SLICE_34) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_35") + (INSTANCE SLICE_35) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_36") + (INSTANCE SLICE_36) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_43") + (INSTANCE SLICE_43) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_44") + (INSTANCE SLICE_44) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_49") + (INSTANCE SLICE_49) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_56") + (INSTANCE SLICE_56) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_58") + (INSTANCE SLICE_58) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_60") + (INSTANCE SLICE_60) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_61") + (INSTANCE SLICE_61) + (DELAY + (ABSOLUTE + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH D0 OFX0 (508:569:631)(508:569:631)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_63") + (INSTANCE SLICE_63) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_64") + (INSTANCE SLICE_64) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_65") + (INSTANCE SLICE_65) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_66") + (INSTANCE SLICE_66) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_67") + (INSTANCE SLICE_67) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_68") + (INSTANCE SLICE_68) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_69") + (INSTANCE SLICE_69) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "RCKEEN_I_0_445_SLICE_70") + (INSTANCE RCKEEN_I_0_445\/SLICE_70) + (DELAY + (ABSOLUTE + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH D0 OFX0 (508:569:631)(508:569:631)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + ) + ) + ) + (CELL + (CELLTYPE "i26_SLICE_71") + (INSTANCE i26\/SLICE_71) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH D0 OFX0 (508:569:631)(508:569:631)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + ) + ) + ) + (CELL + (CELLTYPE "i2099_SLICE_72") + (INSTANCE i2099\/SLICE_72) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + ) + ) + ) + (CELL + (CELLTYPE "i26_adj_28_SLICE_73") + (INSTANCE i26_adj_28\/SLICE_73) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH D0 OFX0 (508:569:631)(508:569:631)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_74") + (INSTANCE SLICE_74) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_75") + (INSTANCE SLICE_75) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_76") + (INSTANCE SLICE_76) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_77") + (INSTANCE SLICE_77) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_78") + (INSTANCE SLICE_78) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_79") + (INSTANCE SLICE_79) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_80") + (INSTANCE SLICE_80) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_81") + (INSTANCE SLICE_81) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_82") + (INSTANCE SLICE_82) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_83") + (INSTANCE SLICE_83) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_84") + (INSTANCE SLICE_84) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_85") + (INSTANCE SLICE_85) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_86") + (INSTANCE SLICE_86) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_87") + (INSTANCE SLICE_87) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_88") + (INSTANCE SLICE_88) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_89") + (INSTANCE SLICE_89) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "SLICE_90") + (INSTANCE SLICE_90) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_91") + (INSTANCE SLICE_91) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_92") + (INSTANCE SLICE_92) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "SLICE_93") + (INSTANCE SLICE_93) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_94") + (INSTANCE SLICE_94) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_95") + (INSTANCE SLICE_95) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_96") + (INSTANCE SLICE_96) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_97") + (INSTANCE SLICE_97) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_98") + (INSTANCE SLICE_98) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "SLICE_99") + (INSTANCE SLICE_99) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_100") + (INSTANCE SLICE_100) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_101") + (INSTANCE SLICE_101) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_102") + (INSTANCE SLICE_102) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_103") + (INSTANCE SLICE_103) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "SLICE_104") + (INSTANCE SLICE_104) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_105") + (INSTANCE SLICE_105) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "RD_7_") + (INSTANCE RD\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD7 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD7 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD7 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD7) (1250:1250:1250)) + (WIDTH (negedge RD7) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_6_") + (INSTANCE RD\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD6 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD6 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD6 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD6) (1250:1250:1250)) + (WIDTH (negedge RD6) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_5_") + (INSTANCE RD\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD5 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD5 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD5 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD5) (1250:1250:1250)) + (WIDTH (negedge RD5) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_4_") + (INSTANCE RD\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD4 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD4 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD4 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD4) (1250:1250:1250)) + (WIDTH (negedge RD4) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_3_") + (INSTANCE RD\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD3 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD3 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD3 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD3) (1250:1250:1250)) + (WIDTH (negedge RD3) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_2_") + (INSTANCE RD\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD2 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD2 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD2 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD2) (1250:1250:1250)) + (WIDTH (negedge RD2) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_1_") + (INSTANCE RD\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD1 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD1 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD1 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD1) (1250:1250:1250)) + (WIDTH (negedge RD1) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_0_") + (INSTANCE RD\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD0 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD0 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD0 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD0) (1250:1250:1250)) + (WIDTH (negedge RD0) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Dout_7_") + (INSTANCE Dout\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout7 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_6_") + (INSTANCE Dout\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout6 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_5_") + (INSTANCE Dout\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout5 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_4_") + (INSTANCE Dout\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout4 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_3_") + (INSTANCE Dout\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout3 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_2_") + (INSTANCE Dout\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout2 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_1_") + (INSTANCE Dout\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout1 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_0_") + (INSTANCE Dout\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout0 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "LED") + (INSTANCE LED_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO LED (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_1_") + (INSTANCE RBA\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RBA1 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_0_") + (INSTANCE RBA\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RBA0 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_11_") + (INSTANCE RA\[11\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA11 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_10_") + (INSTANCE RA\[10\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA10 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_9_") + (INSTANCE RA\[9\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA9 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_8_") + (INSTANCE RA\[8\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA8 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_7_") + (INSTANCE RA\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA7 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_6_") + (INSTANCE RA\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA6 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_5_") + (INSTANCE RA\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA5 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_4_") + (INSTANCE RA\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA4 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_3_") + (INSTANCE RA\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA3 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_2_") + (INSTANCE RA\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA2 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_1_") + (INSTANCE RA\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA1 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_0_") + (INSTANCE RA\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA0 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nRCS") + (INSTANCE nRCS_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRCS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RCKE") + (INSTANCE RCKE_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RCKE (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nRWE") + (INSTANCE nRWE_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRWE (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nRRAS") + (INSTANCE nRRAS_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRRAS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nRCAS") + (INSTANCE nRCAS_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRCAS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RDQMH") + (INSTANCE RDQMH_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RDQMH (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RDQML") + (INSTANCE RDQML_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RDQML (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nUFMCS") + (INSTANCE nUFMCS_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nUFMCS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "UFMCLK") + (INSTANCE UFMCLK_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO UFMCLK (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "UFMSDI") + (INSTANCE UFMSDI_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO UFMSDI (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "PHI2") + (INSTANCE PHI2_I) + (DELAY + (ABSOLUTE + (IOPATH PHI2 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge PHI2) (1250:1250:1250)) + (WIDTH (negedge PHI2) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_9_") + (INSTANCE MAin\[9\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin9 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin9) (1250:1250:1250)) + (WIDTH (negedge MAin9) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_8_") + (INSTANCE MAin\[8\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin8 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin8) (1250:1250:1250)) + (WIDTH (negedge MAin8) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_7_") + (INSTANCE MAin\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin7 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin7) (1250:1250:1250)) + (WIDTH (negedge MAin7) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_6_") + (INSTANCE MAin\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin6 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin6) (1250:1250:1250)) + (WIDTH (negedge MAin6) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_5_") + (INSTANCE MAin\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin5 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin5) (1250:1250:1250)) + (WIDTH (negedge MAin5) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_4_") + (INSTANCE MAin\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin4 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin4) (1250:1250:1250)) + (WIDTH (negedge MAin4) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_3_") + (INSTANCE MAin\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin3 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin3) (1250:1250:1250)) + (WIDTH (negedge MAin3) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_2_") + (INSTANCE MAin\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin2 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin2) (1250:1250:1250)) + (WIDTH (negedge MAin2) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_1_") + (INSTANCE MAin\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin1 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin1) (1250:1250:1250)) + (WIDTH (negedge MAin1) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_0_") + (INSTANCE MAin\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin0 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin0) (1250:1250:1250)) + (WIDTH (negedge MAin0) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "CROW_1_") + (INSTANCE CROW\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH CROW1 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW1) (1250:1250:1250)) + (WIDTH (negedge CROW1) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "CROW_0_") + (INSTANCE CROW\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH CROW0 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW0) (1250:1250:1250)) + (WIDTH (negedge CROW0) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_7_") + (INSTANCE Din\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din7 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din7) (1250:1250:1250)) + (WIDTH (negedge Din7) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_6_") + (INSTANCE Din\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din6 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din6) (1250:1250:1250)) + (WIDTH (negedge Din6) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_5_") + (INSTANCE Din\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din5 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din5) (1250:1250:1250)) + (WIDTH (negedge Din5) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_4_") + (INSTANCE Din\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din4 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din4) (1250:1250:1250)) + (WIDTH (negedge Din4) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_3_") + (INSTANCE Din\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din3 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din3) (1250:1250:1250)) + (WIDTH (negedge Din3) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_2_") + (INSTANCE Din\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din2 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din2) (1250:1250:1250)) + (WIDTH (negedge Din2) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_1_") + (INSTANCE Din\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din1 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din1) (1250:1250:1250)) + (WIDTH (negedge Din1) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_0_") + (INSTANCE Din\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din0 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din0) (1250:1250:1250)) + (WIDTH (negedge Din0) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "nCCAS") + (INSTANCE nCCAS_I) + (DELAY + (ABSOLUTE + (IOPATH nCCAS PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nCCAS) (1250:1250:1250)) + (WIDTH (negedge nCCAS) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "nCRAS") + (INSTANCE nCRAS_I) + (DELAY + (ABSOLUTE + (IOPATH nCRAS PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nCRAS) (1250:1250:1250)) + (WIDTH (negedge nCRAS) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "nFWE") + (INSTANCE nFWE_I) + (DELAY + (ABSOLUTE + (IOPATH nFWE PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nFWE) (1250:1250:1250)) + (WIDTH (negedge nFWE) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RCLK") + (INSTANCE RCLK_I) + (DELAY + (ABSOLUTE + (IOPATH RCLK PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RCLK) (1250:1250:1250)) + (WIDTH (negedge RCLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "UFMSDO") + (INSTANCE UFMSDO_I) + (DELAY + (ABSOLUTE + (IOPATH UFMSDO PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge UFMSDO) (1250:1250:1250)) + (WIDTH (negedge UFMSDO) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RAM2GS") + (INSTANCE ) + (DELAY + (ABSOLUTE + (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_77/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_88/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q0 SLICE_0/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q0 SLICE_68/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q0 SLICE_88/B1 (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_0/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_1/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_2/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_3/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_4/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_5/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_6/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_7/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_8/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_25/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_26/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_31/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_34/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_35/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_36/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_43/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_44/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_56/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_58/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_60/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_61/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_63/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_64/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_65/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_66/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_67/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_68/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_69/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_74/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_76/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_77/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_79/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_80/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_82/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_83/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_84/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_86/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_87/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_91/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_100/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/FCO SLICE_0/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/FCO SLICE_7/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_1/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_94/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_94/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_69/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_78/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_90/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_90/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/FCO SLICE_1/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/FCO SLICE_8/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_77/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_88/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_43/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_77/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/FCO SLICE_2/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_94/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_94/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_68/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_69/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_90/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/FCO SLICE_3/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_43/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_68/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q0 SLICE_68/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/FCO SLICE_6/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_44/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_56/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_75/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_75/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_78/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_94/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_95/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_5/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_56/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_75/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_88/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_95/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_95/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/FCO SLICE_5/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_6/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_68/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q0 SLICE_6/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q0 SLICE_77/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q1 SLICE_7/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q1 SLICE_77/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q1 SLICE_88/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q0 SLICE_7/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q0 SLICE_87/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q0 SLICE_88/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q1 SLICE_8/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q1 SLICE_68/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q1 SLICE_69/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q1 SLICE_90/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q0 SLICE_8/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q0 SLICE_78/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q0 SLICE_90/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q0 SLICE_90/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q0 SLICE_94/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_9/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_14/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_18/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI i26\/SLICE_71/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_82/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_83/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_84/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_89/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_89/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_97/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_99/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F1 SLICE_9/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F1 SLICE_14/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F1 SLICE_18/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F1 SLICE_76/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F1 SLICE_82/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F1 SLICE_84/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F1 SLICE_89/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F1 SLICE_89/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_9/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI i26\/SLICE_71/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI i26\/SLICE_71/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI i26_adj_28\/SLICE_73/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI i26_adj_28\/SLICE_73/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_76/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_82/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_83/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_84/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_89/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_97/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_98/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/F1 SLICE_9/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q0 SLICE_9/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q0 i26\/SLICE_71/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F1 SLICE_9/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/F1 SLICE_9/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/F0 SLICE_9/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F0 SLICE_9/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F0 SLICE_14/LSR (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_9/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_14/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_18/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_19/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_23/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_32/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_49/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_81/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_88/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_91/M1 (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_93/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_99/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_101/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_102/CLK (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_14/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_23/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_32/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_32/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI i26_adj_28\/SLICE_73/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI i26_adj_28\/SLICE_73/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_79/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_92/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_92/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_92/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_99/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_14/Q0 SLICE_14/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_14/Q0 SLICE_14/C0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_14/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_76/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_82/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_85/B0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_86/B0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_89/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_98/M1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_105/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_14/F0 SLICE_14/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_14/F1 i26\/SLICE_71/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_18/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_95/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_103/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/F0 SLICE_18/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F0 SLICE_18/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_18/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_96/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_101/B1 (0:0:0)(0:0:0)) + (INTERCONNECT i26_adj_28\/SLICE_73/OFX0 SLICE_18/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/F0 SLICE_18/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/F0 SLICE_79/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F0 SLICE_18/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F1 SLICE_18/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/Q0 SLICE_83/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/Q0 SLICE_84/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/Q1 SLICE_19/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/Q1 SLICE_91/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/Q1 SLICE_100/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/Q0 SLICE_19/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/Q0 SLICE_100/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/Q0 SLICE_19/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/Q0 SLICE_100/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/F0 SLICE_19/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/F0 SLICE_19/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/F1 SLICE_67/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/F1 SLICE_87/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_23/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI i26\/SLICE_71/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI i26_adj_28\/SLICE_73/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_76/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_79/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_85/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_91/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_91/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_101/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_105/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_23/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_32/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_86/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_92/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_99/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23/F1 SLICE_23/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23/F1 SLICE_49/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23/F1 SLICE_84/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_23/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_49/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_76/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_83/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_85/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_86/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_91/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_101/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_105/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_105/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56/Q0 SLICE_23/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56/Q0 SLICE_32/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_23/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_49/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_86/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_88/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_89/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_93/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23/F0 SLICE_23/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/F0 SLICE_23/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23/Q0 SLICE_56/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_25/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_36/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_58/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_60/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_61/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_63/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_67/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 RCKEEN_I_0_445\/SLICE_70/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 i2099\/SLICE_72/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 i2099\/SLICE_72/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_80/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_104/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_25/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_34/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_35/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_35/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_58/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_60/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_63/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_65/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_65/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_66/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_68/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 RCKEEN_I_0_445\/SLICE_70/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_74/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_100/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_25/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_34/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_34/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_43/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_44/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_56/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_60/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_63/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_65/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_69/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_75/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_78/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_87/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_95/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_100/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_100/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_102/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_25/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_31/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_31/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_32/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_34/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_34/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_36/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_58/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_58/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_60/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_61/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_63/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 i2099\/SLICE_72/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 i2099\/SLICE_72/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_78/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_80/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_85/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_90/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_95/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_96/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_97/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_100/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_104/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F0 SLICE_25/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95/F1 SLICE_25/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_76/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_77/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_80/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_82/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_84/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_86/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_87/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_100/CE (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_26/C1 (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_78/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_83/M0 (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_85/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_90/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_95/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_96/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_97/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_98/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_26/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_58/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 RCKEEN_I_0_445\/SLICE_70/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 RCKEEN_I_0_445\/SLICE_70/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_74/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_74/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_103/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_26/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_49/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/F0 SLICE_26/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/F1 SLICE_26/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/F1 LED_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_31/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_58/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_66/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_66/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 RCKEEN_I_0_445\/SLICE_70/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 i2099\/SLICE_72/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_80/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q1 SLICE_31/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q1 SLICE_84/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q1 SLICE_102/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q1 SLICE_102/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63/F1 SLICE_31/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63/F1 SLICE_63/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_31/F0 SLICE_31/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/Q1 SLICE_31/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/Q1 SLICE_82/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/Q1 SLICE_102/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_31/Q0 RA\[10\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_31/F1 SLICE_61/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_49/Q0 SLICE_32/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32/F0 SLICE_32/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32/Q0 RA\[11\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32/F1 SLICE_83/B0 (0:0:0)(0:0:0)) + (INTERCONNECT RCKEEN_I_0_445\/SLICE_70/OFX0 SLICE_34/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_34/F0 SLICE_34/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/F1 SLICE_34/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/F1 SLICE_58/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/F1 SLICE_60/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_34/Q0 SLICE_35/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_34/F1 SLICE_60/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/Q0 SLICE_35/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/Q0 SLICE_60/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/Q0 RCKE_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q1 SLICE_35/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/Q0 SLICE_35/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/Q0 SLICE_74/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/F0 SLICE_35/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/Q0 SLICE_35/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/F1 SLICE_104/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/Q1 SLICE_67/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/Q1 SLICE_68/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/Q1 SLICE_74/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/F0 SLICE_36/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 SLICE_36/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/F1 SLICE_64/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/F1 SLICE_66/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/F1 SLICE_43/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/F1 SLICE_44/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/F1 SLICE_43/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/F1 SLICE_69/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/F1 SLICE_95/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43/F1 SLICE_43/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/Q0 SLICE_43/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43/F0 SLICE_43/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F0 SLICE_43/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F0 SLICE_44/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/F0 SLICE_43/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/F0 SLICE_44/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43/Q0 UFMCLK_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/F0 SLICE_44/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94/F1 SLICE_44/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94/F1 SLICE_75/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94/F1 SLICE_78/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/F1 SLICE_44/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/F1 SLICE_78/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/Q0 SLICE_44/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F1 SLICE_44/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/F0 SLICE_44/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/Q0 UFMSDI_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_49/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_81/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_86/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_88/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_89/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_49/F1 SLICE_49/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_49/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI i26\/SLICE_71/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI i26_adj_28\/SLICE_73/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI i26_adj_28\/SLICE_73/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_79/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_81/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_92/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_102/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_103/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_49/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI i26_adj_28\/SLICE_73/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI i26_adj_28\/SLICE_73/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_76/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_79/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_91/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_91/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_92/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_92/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_102/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_103/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_49/F0 SLICE_49/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/F1 SLICE_49/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/F1 SLICE_56/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/F1 SLICE_78/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/F1 SLICE_95/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56/F1 SLICE_56/D0 (0:0:0)(0:0:0)) + (INTERCONNECT UFMSDO_I/PADDI SLICE_56/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56/F0 SLICE_56/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/F0 SLICE_56/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/F0 SLICE_58/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_58/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 i2099\/SLICE_72/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_58/OFX0 SLICE_58/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_58/Q0 nRCAS_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60/F1 SLICE_60/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60/F1 SLICE_61/B1 (0:0:0)(0:0:0)) + (INTERCONNECT i2099\/SLICE_72/OFX0 SLICE_60/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60/F0 SLICE_60/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60/Q0 nRCS_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q0 SLICE_61/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q0 SLICE_63/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q0 i2099\/SLICE_72/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q0 i2099\/SLICE_72/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q0 SLICE_87/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q0 SLICE_102/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_61/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_64/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_65/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_65/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_66/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_66/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_80/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F1 SLICE_61/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61/Q0 SLICE_61/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61/Q0 nRRAS_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61/OFX0 SLICE_61/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F0 SLICE_63/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/F1 SLICE_63/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63/F0 SLICE_63/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F0 SLICE_63/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63/Q0 nRWE_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_64/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_64/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_93/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_93/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_96/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_97/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_98/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_98/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_99/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_99/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_101/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_101/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_103/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_64/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_90/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_93/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_93/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/Q1 SLICE_64/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/F0 SLICE_64/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F1 SLICE_64/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F1 SLICE_80/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F1 SLICE_104/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/F0 SLICE_64/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/F1 RA\[9\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/Q1 SLICE_65/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/Q1 SLICE_87/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_65/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_66/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_67/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_74/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_80/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_100/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/F0 SLICE_65/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/F1 SLICE_104/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/F0 SLICE_66/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/F0 SLICE_67/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/Q1 SLICE_67/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_67/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 nUFMCS_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/F0 RCKEEN_I_0_445\/SLICE_70/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/F1 SLICE_69/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/F0 SLICE_77/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q1 SLICE_74/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q1 SLICE_103/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94/F0 SLICE_69/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/F0 SLICE_69/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95/F0 SLICE_69/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 RCKEEN_I_0_445\/SLICE_70/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 RCKEEN_I_0_445\/SLICE_70/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 SLICE_74/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 SLICE_74/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 SLICE_103/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/F1 i26\/SLICE_71/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/F1 SLICE_83/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 i26\/SLICE_71/B0 (0:0:0)(0:0:0)) + (INTERCONNECT i26\/SLICE_71/OFX0 SLICE_105/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F0 SLICE_74/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F0 SLICE_104/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/F0 SLICE_75/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/F0 SLICE_87/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/F1 SLICE_75/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/F0 SLICE_76/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/F0 SLICE_83/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/F1 SLICE_76/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/F1 SLICE_91/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/Q0 SLICE_76/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/Q1 SLICE_76/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/F0 SLICE_77/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/Q0 SLICE_77/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/Q1 SLICE_77/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/F1 SLICE_87/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/Q1 SLICE_80/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_78/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_96/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_99/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_78/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_97/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_101/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/Q0 SLICE_101/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/Q1 SLICE_99/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_79/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/F0 SLICE_79/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/Q1 SLICE_79/M1 (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_79/M0 (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_89/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_92/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_98/M0 (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_103/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_105/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_105/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/Q0 SLICE_80/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/Q1 SLICE_81/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/Q0 SLICE_81/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/Q1 SLICE_81/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F1 SLICE_81/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/F0 SLICE_81/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/Q0 SLICE_81/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/F1 SLICE_81/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/F1 SLICE_93/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F0 SLICE_82/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F0 SLICE_82/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F0 SLICE_83/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/Q0 SLICE_82/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/F0 SLICE_84/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F0 SLICE_84/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F0 SLICE_85/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/Q0 SLICE_84/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/Q1 SLICE_100/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F0 SLICE_85/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/F1 SLICE_85/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/F1 SLICE_86/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/F1 SLICE_105/A0 (0:0:0)(0:0:0)) + (INTERCONNECT CROW\[1\]_I/PADDI SLICE_85/M1 (0:0:0)(0:0:0)) + (INTERCONNECT CROW\[0\]_I/PADDI SLICE_85/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/Q0 RBA\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/Q1 RBA\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/Q0 SLICE_86/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/Q1 SLICE_86/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/F1 SLICE_87/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F0 SLICE_88/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/Q0 SLICE_97/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/Q1 SLICE_96/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/Q0 RD\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/Q1 RD\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[8\]_I/PADDI SLICE_90/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[8\]_I/PADDI SLICE_98/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/Q0 SLICE_98/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/Q0 RD\[6\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/Q1 RD\[7\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/F0 RDQMH_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/F1 RDQML_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_95/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_97/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_97/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95/Q0 SLICE_97/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95/Q1 SLICE_103/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_96/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_96/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_96/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/Q1 SLICE_96/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/Q0 SLICE_96/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/Q0 SLICE_101/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/F1 RA\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/Q1 SLICE_97/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/Q0 SLICE_98/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/F1 RA\[4\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/Q1 SLICE_99/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/F0 RA\[8\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/F1 RA\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/F0 RA\[7\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/F1 RA\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/Q0 SLICE_100/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/F0 RA\[6\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/F1 RA\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/Q0 RD\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/F1 RA\[5\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/Q1 RD\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/Q0 RD\[4\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 RD\[7\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 RD\[6\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 RD\[5\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 RD\[4\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 RD\[3\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 RD\[2\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 RD\[1\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 RD\[0\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/Q1 RD\[5\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (0:0:0)(0:0:0)) + ) + ) + ) +) diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvo.vo b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvo.vo new file mode 100644 index 0000000..8cd98b1 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvo.vo @@ -0,0 +1,3678 @@ + +// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 + +// ldbanno -n Verilog -o RAM2GS_LCMXO640C_impl1_mapvo.vo -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd +// Netlist created on Tue Aug 15 05:03:22 2023 +// Netlist written on Tue Aug 15 05:03:24 2023 +// Design is for device LCMXO640C +// Design is for package TQFP100 +// Design is for performance grade 3 + +`timescale 1 ns / 1 ps + +module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, + RD, nRCS, RCLK, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, + UFMCLK, UFMSDI, UFMSDO ); + input PHI2; + input [9:0] MAin; + input [1:0] CROW; + input [7:0] Din; + input nCCAS, nCRAS, nFWE, RCLK, UFMSDO; + output [7:0] Dout; + output LED; + output [1:0] RBA; + output [11:0] RA; + output nRCS, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI; + inout [7:0] RD; + wire FS_7, FS_6, RCLK_c, n2010, n2011, FS_15, FS_14, n2014, n2015, FS_5, + FS_4, n2009, FS_13, FS_12, n2013, FS_1, FS_0, n2008, FS_11, FS_10, + n2012, FS_3, FS_2, FS_9, FS_8, FS_17, FS_16, MAin_c_1, n1326, + MAin_c_0, n2263, ADSubmitted, n2242, n2459, n1413, C1Submitted_N_237, + PHI2_c, Din_c_6, C1Submitted, nFWE_c, n6_adj_3, n2284, MAin_c_5, + n2316, n26, MAin_c_2, n15, n2463, CmdEnable_N_248, + PHI2_N_120_enable_7, CmdEnable, PHI2r2, CmdSubmitted, PHI2r3, + \n2568\001/BUF1 , PHI2_N_120_enable_5, n2472, Din_c_5, Din_c_7, n1314, + Din_c_4, n8MEGEN, Din_c_0, Cmdn8MEGEN_N_264, PHI2_N_120_enable_4, + Cmdn8MEGEN, nRowColSel_N_35, RASr2, InitReady, Ready, + \n2568\000/BUF1 , RCLK_c_enable_25, RCLK_c_enable_23, nCRAS_c, CBR, + LEDEN, n2568, RCLK_c_enable_12, LED_N_84, nRowColSel_N_34, + nRCAS_N_165, n2208, n2209, nRWE_N_177, RA_0, n56, XOR8MEG, RA11_N_184, + RA_c, n2478, RCKEEN_N_122, RCKEEN_N_121, RCLK_c_enable_4, RCKEEN, + n2467, RCKE_c, RASr3, RASr, RCKE_N_132, CASr, nRWE_N_182, CASr2, + \n2568\002/BUF1 , Ready_N_292, n2469, n2462, n62, n1160, CmdUFMCLK, + UFMCLK_N_224, RCLK_c_enable_24, n1846, UFMCLK_c, n2470, n2272, n2471, + CmdUFMSDI, n2461, UFMSDI_N_231, UFMSDI_c, Din_c_1, n2324, Din_c_2, + Din_c_3, XOR8MEG_N_110, PHI2_N_120_enable_1, n2464, n1325, UFMSDO_c, + n8MEGEN_N_91, RCLK_c_enable_11, n2427, n15_adj_1, nRCAS_N_161, + nRCAS_c, n13, n2481, nRCS_N_136, nRCS_c, nRCS_N_139, nRowColSel_N_32, + n6, nRRAS_c, n2138, nRWE_N_178, n33, nRWE_N_171, RCLK_c_enable_3, + nRWE_c, nRowColSel, MAin_c_9, RowA_9, nRowColSel_N_28, n1502, n1410, + RA_1_9, Ready_N_296, nRowColSel_N_33, n1503, n2414, n1093, CmdUFMCS, + nUFMCS_c, n11, n1417, n2322, CASr3, n12, n2164, LEDEN_N_82, FWEr, + n2476, n2475, n13_adj_2, n1, n2214, n2328, n10, n2458, n732, n733, + n2290, n728, n729, n8, n727, MAin_c_7, MAin_c_6, RowA_6, RowA_7, + n2468, n1280, PHI2r, nCCAS_c, n726, Bank_3, Bank_6, Bank_5, n2278, + n2314, Bank_2, PHI2_N_120_enable_6, n14, n2460, n730, n2262, n2473, + n738, n737, n2474, n2253, CROW_c_1, CROW_c_0, RBA_c_0, RBA_c_1, n734, + n735, n7, n2451, Bank_0, Bank_1, WRD_0, WRD_1, MAin_c_8, RowA_8, + WRD_6, WRD_7, RDQMH_c, RDQML_c, MAin_c_4, RowA_4, RowA_5, MAin_c_3, + RowA_3, Bank_4, RowA_2, RA_1_3, Bank_7, RowA_0, RA_1_4, RowA_1, + RA_1_8, RA_1_0, RA_1_7, RA_1_1, n736, RA_1_6, RA_1_2, WRD_2, RA_1_5, + WRD_3, WRD_4, n984, WRD_5, Dout_c, Dout_0, Dout_1, Dout_2, Dout_3, + Dout_4, Dout_5, Dout_6, VCCI, GNDI_TSALL; + + SLICE_0 SLICE_0( .A1(FS_7), .A0(FS_6), .CLK(RCLK_c), .FCI(n2010), .Q0(FS_6), + .Q1(FS_7), .FCO(n2011)); + SLICE_1 SLICE_1( .A1(FS_15), .A0(FS_14), .CLK(RCLK_c), .FCI(n2014), + .Q0(FS_14), .Q1(FS_15), .FCO(n2015)); + SLICE_2 SLICE_2( .A1(FS_5), .A0(FS_4), .CLK(RCLK_c), .FCI(n2009), .Q0(FS_4), + .Q1(FS_5), .FCO(n2010)); + SLICE_3 SLICE_3( .A1(FS_13), .A0(FS_12), .CLK(RCLK_c), .FCI(n2013), + .Q0(FS_12), .Q1(FS_13), .FCO(n2014)); + SLICE_4 SLICE_4( .A1(FS_1), .A0(FS_0), .CLK(RCLK_c), .Q0(FS_0), .Q1(FS_1), + .FCO(n2008)); + SLICE_5 SLICE_5( .A1(FS_11), .A0(FS_10), .CLK(RCLK_c), .FCI(n2012), + .Q0(FS_10), .Q1(FS_11), .FCO(n2013)); + SLICE_6 SLICE_6( .A1(FS_3), .A0(FS_2), .CLK(RCLK_c), .FCI(n2008), .Q0(FS_2), + .Q1(FS_3), .FCO(n2009)); + SLICE_7 SLICE_7( .A1(FS_9), .A0(FS_8), .CLK(RCLK_c), .FCI(n2011), .Q0(FS_8), + .Q1(FS_9), .FCO(n2012)); + SLICE_8 SLICE_8( .A1(FS_17), .A0(FS_16), .CLK(RCLK_c), .FCI(n2015), + .Q0(FS_16), .Q1(FS_17)); + SLICE_9 SLICE_9( .C1(MAin_c_1), .B1(n1326), .A1(MAin_c_0), .D0(n2263), + .C0(ADSubmitted), .B0(n2242), .A0(n2459), .DI0(n1413), + .LSR(C1Submitted_N_237), .CLK(PHI2_c), .F0(n1413), .Q0(ADSubmitted), + .F1(n2263)); + SLICE_14 SLICE_14( .B1(Din_c_6), .A1(C1Submitted), .D0(MAin_c_1), + .C0(C1Submitted), .B0(n1326), .A0(nFWE_c), .DI0(n6_adj_3), + .LSR(C1Submitted_N_237), .CLK(PHI2_c), .F0(n6_adj_3), .Q0(C1Submitted), + .F1(n2284)); + SLICE_18 SLICE_18( .D1(MAin_c_5), .C1(n2316), .B1(n26), .A1(MAin_c_2), + .D0(n15), .C0(n1326), .B0(n2463), .A0(MAin_c_1), .DI0(CmdEnable_N_248), + .CE(PHI2_N_120_enable_7), .CLK(PHI2_c), .F0(CmdEnable_N_248), + .Q0(CmdEnable), .F1(n1326)); + SLICE_19 SLICE_19( .C1(PHI2r2), .B1(CmdSubmitted), .A1(PHI2r3), + .DI0(\n2568\001/BUF1 ), .CE(PHI2_N_120_enable_5), .CLK(PHI2_c), + .F0(\n2568\001/BUF1 ), .Q0(CmdSubmitted), .F1(n2472)); + SLICE_23 SLICE_23( .C1(Din_c_5), .B1(Din_c_7), .A1(Din_c_6), .D0(n1314), + .C0(Din_c_4), .B0(n8MEGEN), .A0(Din_c_0), .DI0(Cmdn8MEGEN_N_264), + .CE(PHI2_N_120_enable_4), .CLK(PHI2_c), .F0(Cmdn8MEGEN_N_264), + .Q0(Cmdn8MEGEN), .F1(n1314)); + SLICE_25 SLICE_25( .D1(nRowColSel_N_35), .C1(RASr2), .B1(InitReady), + .A1(Ready), .DI0(\n2568\000/BUF1 ), .CE(RCLK_c_enable_25), .CLK(RCLK_c), + .F0(\n2568\000/BUF1 ), .Q0(InitReady), .F1(RCLK_c_enable_23)); + SLICE_26 SLICE_26( .C1(nCRAS_c), .B1(CBR), .A1(LEDEN), .DI0(n2568), + .CE(RCLK_c_enable_12), .CLK(RCLK_c), .F0(n2568), .Q0(LEDEN), .F1(LED_N_84)); + SLICE_31 SLICE_31( .B1(nRowColSel_N_34), .A1(Ready), .C0(nRCAS_N_165), + .B0(Ready), .A0(n2208), .DI0(n2209), .LSR(nRWE_N_177), .CLK(RCLK_c), + .F0(n2209), .Q0(RA_0), .F1(n56)); + SLICE_32 SLICE_32( .B1(Din_c_7), .A1(Din_c_6), .C0(n8MEGEN), .B0(XOR8MEG), + .A0(Din_c_6), .DI0(RA11_N_184), .LSR(Ready), .CLK(PHI2_c), .F0(RA11_N_184), + .Q0(RA_c), .F1(n2478)); + SLICE_34 SLICE_34( .C1(Ready), .B1(InitReady), .A1(RASr2), .C0(Ready), + .B0(RCKEEN_N_122), .A0(InitReady), .DI0(RCKEEN_N_121), + .CE(RCLK_c_enable_4), .CLK(RCLK_c), .F0(RCKEEN_N_121), .Q0(RCKEEN), + .F1(n2467)); + SLICE_35 SLICE_35( .B1(RCKE_c), .A1(RASr2), .D0(RASr3), .C0(RASr2), + .B0(RCKEEN), .A0(RASr), .DI0(RCKE_N_132), .M1(CASr), .CLK(RCLK_c), + .F0(RCKE_N_132), .Q0(RCKE_c), .F1(nRWE_N_182), .Q1(CASr2)); + SLICE_36 SLICE_36( .B1(nRowColSel_N_35), .A1(Ready), .DI0(\n2568\002/BUF1 ), + .CE(Ready_N_292), .CLK(RCLK_c), .F0(\n2568\002/BUF1 ), .Q0(Ready), + .F1(n2469)); + SLICE_43 SLICE_43( .D1(FS_1), .C1(n2462), .B1(n62), .A1(FS_4), + .C0(InitReady), .B0(n1160), .A0(CmdUFMCLK), .DI0(UFMCLK_N_224), + .CE(RCLK_c_enable_24), .LSR(n1846), .CLK(RCLK_c), .F0(UFMCLK_N_224), + .Q0(UFMCLK_c), .F1(n1160)); + SLICE_44 SLICE_44( .D1(FS_11), .C1(n2470), .B1(n2272), .A1(n2471), + .D0(CmdUFMSDI), .C0(InitReady), .B0(n2462), .A0(n2461), .DI0(UFMSDI_N_231), + .CE(RCLK_c_enable_24), .LSR(n1846), .CLK(RCLK_c), .F0(UFMSDI_N_231), + .Q0(UFMSDI_c), .F1(n2462)); + SLICE_49 SLICE_49( .D1(Din_c_1), .C1(n1314), .B1(LEDEN), .A1(Din_c_4), + .D0(n2324), .C0(Din_c_2), .B0(Din_c_3), .A0(Din_c_0), .DI0(XOR8MEG_N_110), + .CE(PHI2_N_120_enable_1), .CLK(PHI2_c), .F0(XOR8MEG_N_110), .Q0(XOR8MEG), + .F1(n2324)); + SLICE_56 SLICE_56( .C1(FS_10), .B1(n2464), .A1(FS_11), .D0(n1325), + .C0(InitReady), .B0(Cmdn8MEGEN), .A0(UFMSDO_c), .DI0(n8MEGEN_N_91), + .CE(RCLK_c_enable_11), .CLK(RCLK_c), .F0(n8MEGEN_N_91), .Q0(n8MEGEN), + .F1(n1325)); + SLICE_58 SLICE_58( .D1(n2427), .C1(RASr2), .B1(CBR), .A1(Ready), .C0(Ready), + .B0(n15_adj_1), .A0(nRowColSel_N_34), .DI0(nRCAS_N_161), + .M0(nRowColSel_N_35), .CE(RCLK_c_enable_4), .CLK(RCLK_c), + .OFX0(nRCAS_N_161), .Q0(nRCAS_c)); + SLICE_60 SLICE_60( .D1(Ready), .C1(RCKE_c), .B1(InitReady), .A1(RASr2), + .D0(nRowColSel_N_35), .C0(n13), .B0(n2481), .A0(n2467), .DI0(nRCS_N_136), + .CE(RCLK_c_enable_4), .CLK(RCLK_c), .F0(nRCS_N_136), .Q0(nRCS_c), .F1(n13)); + SLICE_61 SLICE_61( .C1(nRCS_N_139), .B1(n13), .A1(Ready), + .D0(nRowColSel_N_32), .C0(n6), .B0(nRRAS_c), .A0(n56), .DI0(n2138), + .M0(nRowColSel_N_35), .CLK(RCLK_c), .OFX0(n2138), .Q0(nRRAS_c)); + SLICE_63 SLICE_63( .D1(nRCS_N_139), .C1(InitReady), .B1(RASr2), + .A1(nRowColSel_N_35), .D0(n2208), .C0(Ready), .B0(nRWE_N_178), .A0(n33), + .DI0(nRWE_N_171), .CE(RCLK_c_enable_3), .CLK(RCLK_c), .F0(nRWE_N_171), + .Q0(nRWE_c), .F1(n2208)); + SLICE_64 SLICE_64( .C1(nRowColSel), .B1(MAin_c_9), .A1(RowA_9), + .D0(nRowColSel_N_32), .C0(nRowColSel_N_28), .B0(n1502), .A0(nRowColSel), + .DI0(n1410), .LSR(n2469), .CLK(RCLK_c), .F0(n1410), .Q0(nRowColSel), + .F1(RA_1_9)); + SLICE_65 SLICE_65( .D1(InitReady), .C1(Ready_N_296), .B1(RASr2), + .A1(nRowColSel_N_32), .B0(nRowColSel_N_33), .A0(nRowColSel_N_32), + .DI0(n1503), .LSR(RASr2), .CLK(RCLK_c), .F0(n1503), .Q0(nRowColSel_N_32), + .F1(n2414)); + SLICE_66 SLICE_66( .D1(nRowColSel_N_33), .C1(nRowColSel_N_34), .B1(n2469), + .A1(nRowColSel_N_32), .B0(RASr2), .A0(nRowColSel_N_32), .DI0(n1093), + .LSR(nRowColSel_N_34), .CLK(RCLK_c), .F0(n1093), .Q0(nRowColSel_N_33), + .F1(RCLK_c_enable_4)); + SLICE_67 SLICE_67( .C1(n2472), .B1(CmdUFMCS), .A1(nUFMCS_c), .B0(CASr2), + .A0(nRowColSel_N_33), .M0(n1093), .LSR(nRowColSel_N_35), .CLK(RCLK_c), + .F0(n11), .Q0(nRowColSel_N_34), .F1(n1417)); + SLICE_68 SLICE_68( .B1(FS_12), .A1(FS_17), .D0(FS_3), .C0(FS_6), .B0(FS_1), + .A0(FS_0), .M1(CASr2), .M0(RASr2), .CLK(RCLK_c), .F0(n2322), + .Q0(nRowColSel_N_35), .F1(n2471), .Q1(CASr3)); + SLICE_69 SLICE_69( .D1(FS_14), .C1(FS_12), .B1(n12), .A1(FS_17), + .C0(InitReady), .B0(n1417), .A0(n62), .DI0(n2164), .LSR(LEDEN_N_82), + .CLK(RCLK_c), .F0(n2164), .Q0(nUFMCS_c), .F1(n62)); + RCKEEN_I_0_445_SLICE_70 \RCKEEN_I_0_445/SLICE_70 ( .C1(RASr2), .B1(FWEr), + .A1(CBR), .D0(nRowColSel_N_34), .C0(FWEr), .B0(n11), .A0(CBR), + .M0(nRowColSel_N_35), .OFX0(RCKEEN_N_122)); + i26_SLICE_71 \i26/SLICE_71 ( .D1(n2284), .C1(n2476), .B1(MAin_c_1), + .A1(MAin_c_0), .D0(ADSubmitted), .C0(MAin_c_0), .B0(n2475), .A0(Din_c_5), + .M0(Din_c_2), .OFX0(n13_adj_2)); + i2099_SLICE_72 \i2099/SLICE_72 ( .D1(nRowColSel_N_34), .C1(nRowColSel_N_35), + .B1(Ready), .A1(nRCS_N_139), .C0(nRowColSel_N_35), .B0(Ready), + .A0(nRCS_N_139), .M0(n15_adj_1), .OFX0(n2481)); + i26_adj_28_SLICE_73 \i26_adj_28/SLICE_73 ( .D1(MAin_c_0), .C1(Din_c_2), + .B1(Din_c_3), .A1(Din_c_6), .D0(MAin_c_0), .C0(Din_c_2), .B0(Din_c_3), + .A0(Din_c_6), .M0(Din_c_5), .OFX0(n15)); + SLICE_74 SLICE_74( .D1(n1), .C1(nRowColSel_N_33), .B1(CBR), .A1(FWEr), + .D0(CASr3), .C0(CASr2), .B0(FWEr), .A0(CBR), .M1(RASr2), .M0(RASr), + .CLK(RCLK_c), .F0(n1), .Q0(RASr2), .F1(n15_adj_1), .Q1(RASr3)); + SLICE_75 SLICE_75( .C1(InitReady), .B1(FS_11), .A1(n2214), .D0(FS_11), + .C0(n2272), .B0(n2328), .A0(FS_10), .F0(n2214), .F1(RCLK_c_enable_12)); + SLICE_76 SLICE_76( .D1(MAin_c_0), .C1(n10), .B1(n1326), .A1(nFWE_c), + .D0(n2458), .C0(Din_c_4), .B0(Din_c_5), .A0(Din_c_3), .M1(n732), .M0(n733), + .CE(RCLK_c_enable_23), .CLK(RCLK_c), .F0(PHI2_N_120_enable_4), .Q0(n732), + .F1(n2458), .Q1(nRWE_N_177)); + SLICE_77 SLICE_77( .D1(FS_7), .C1(n2322), .B1(FS_4), .A1(n2290), .C0(FS_9), + .B0(FS_5), .A0(FS_2), .M1(n728), .M0(n729), .CE(RCLK_c_enable_23), + .CLK(RCLK_c), .F0(n2290), .Q0(n728), .F1(n8), .Q1(n727)); + SLICE_78 SLICE_78( .D1(n2471), .C1(n2272), .B1(FS_14), .A1(FS_16), + .C0(InitReady), .B0(n2464), .A0(FS_11), .M1(MAin_c_7), .M0(MAin_c_6), + .LSR(Ready), .CLK(nCRAS_c), .F0(n1846), .Q0(RowA_6), .F1(n2464), + .Q1(RowA_7)); + SLICE_79 SLICE_79( .C1(Din_c_5), .B1(Din_c_3), .A1(Din_c_6), .D0(n2468), + .C0(n1280), .B0(n2463), .A0(Din_c_2), .M1(PHI2r), .M0(nCCAS_c), + .CLK(RCLK_c), .F0(C1Submitted_N_237), .Q0(CASr), .F1(n2468), .Q1(PHI2r2)); + SLICE_80 SLICE_80( .B1(nRowColSel_N_33), .A1(nRowColSel_N_34), + .D0(nRowColSel_N_35), .C0(n1502), .B0(nRowColSel_N_32), .A0(Ready), + .M1(n726), .M0(n727), .CE(RCLK_c_enable_23), .CLK(RCLK_c), + .F0(RCLK_c_enable_3), .Q0(n726), .F1(n1502), .Q1(Ready_N_296)); + SLICE_81 SLICE_81( .B1(Bank_3), .A1(Bank_6), .D0(Bank_5), .C0(n2278), + .B0(n2314), .A0(Bank_2), .M1(Din_c_2), .M0(Din_c_1), + .CE(PHI2_N_120_enable_6), .CLK(PHI2_c), .F0(n26), .Q0(CmdUFMCLK), + .F1(n2278), .Q1(CmdUFMCS)); + SLICE_82 SLICE_82( .D1(MAin_c_1), .C1(n14), .B1(n2460), .A1(MAin_c_0), + .B0(n1326), .A0(nFWE_c), .M1(n730), .M0(nRWE_N_177), .CE(RCLK_c_enable_23), + .CLK(RCLK_c), .F0(n2460), .Q0(n730), .F1(PHI2_N_120_enable_7), .Q1(n729)); + SLICE_83 SLICE_83( .D1(n2476), .C1(n2460), .B1(n10), .A1(MAin_c_0), + .D0(MAin_c_1), .C0(CmdEnable), .B0(n2478), .A0(Din_c_4), .M0(nCRAS_c), + .CLK(RCLK_c), .F0(n10), .Q0(RASr), .F1(PHI2_N_120_enable_6)); + SLICE_84 SLICE_84( .D1(n1314), .C1(n2262), .B1(CmdEnable), .A1(n2473), + .C0(MAin_c_1), .B0(n1326), .A0(MAin_c_0), .M1(n738), .M0(nRCAS_N_165), + .CE(RCLK_c_enable_23), .CLK(RCLK_c), .F0(n2262), .Q0(n738), + .F1(PHI2_N_120_enable_1), .Q1(n737)); + SLICE_85 SLICE_85( .D1(n2474), .C1(Din_c_5), .B1(n2253), .A1(n2473), + .B0(nFWE_c), .A0(Din_c_4), .M1(CROW_c_1), .M0(CROW_c_0), .LSR(Ready), + .CLK(nCRAS_c), .F0(n2473), .Q0(RBA_c_0), .F1(n2242), .Q1(RBA_c_1)); + SLICE_86 SLICE_86( .C1(Din_c_1), .B1(Din_c_0), .A1(Din_c_7), .C0(n2253), + .B0(nFWE_c), .A0(Din_c_4), .M1(n734), .M0(n735), .CE(RCLK_c_enable_23), + .CLK(RCLK_c), .F0(n2463), .Q0(n734), .F1(n2253), .Q1(n733)); + SLICE_87 SLICE_87( .B1(n2214), .A1(FS_8), .D0(n8), .C0(InitReady), + .B0(n2472), .A0(n7), .M1(nRCS_N_139), .M0(Ready_N_296), + .CE(RCLK_c_enable_23), .CLK(RCLK_c), .F0(RCLK_c_enable_11), + .Q0(nRCS_N_139), .F1(n7), .Q1(nRCAS_N_165)); + SLICE_88 SLICE_88( .C1(FS_10), .B1(FS_6), .A1(n2451), .D0(FS_8), .C0(FS_5), + .B0(FS_9), .A0(FS_7), .M1(Din_c_1), .M0(Din_c_0), .CLK(PHI2_c), .F0(n2451), + .Q0(Bank_0), .F1(n2461), .Q1(Bank_1)); + SLICE_89 SLICE_89( .C1(MAin_c_1), .B1(n1326), .A1(nFWE_c), .C0(MAin_c_0), + .B0(n1326), .A0(MAin_c_1), .M1(Din_c_1), .M0(Din_c_0), .CLK(nCCAS_c), + .F0(n1280), .Q0(WRD_0), .F1(n2459), .Q1(WRD_1)); + SLICE_90 SLICE_90( .D1(FS_16), .C1(FS_14), .B1(FS_12), .A1(FS_17), + .B0(FS_14), .A0(FS_16), .M1(MAin_c_9), .M0(MAin_c_8), .LSR(Ready), + .CLK(nCRAS_c), .F0(n2470), .Q0(RowA_8), .F1(n2328), .Q1(RowA_9)); + SLICE_91 SLICE_91( .B1(Din_c_5), .A1(Din_c_3), .D0(n2458), .C0(Din_c_5), + .B0(Din_c_4), .A0(Din_c_3), .M1(PHI2_c), .M0(PHI2r2), .CLK(RCLK_c), + .F0(PHI2_N_120_enable_5), .Q0(PHI2r3), .F1(n2476), .Q1(PHI2r)); + SLICE_92 SLICE_92( .B1(Din_c_3), .A1(Din_c_6), .C0(Din_c_3), .B0(Din_c_2), + .A0(Din_c_6), .M1(Din_c_7), .M0(Din_c_6), .CLK(nCCAS_c), .F0(n2474), + .Q0(WRD_6), .F1(n2475), .Q1(WRD_7)); + SLICE_93 SLICE_93( .B1(nRowColSel), .A1(MAin_c_9), .B0(nRowColSel), + .A0(MAin_c_9), .M0(Din_c_0), .CE(PHI2_N_120_enable_6), .CLK(PHI2_c), + .F0(RDQMH_c), .Q0(CmdUFMSDI), .F1(RDQML_c)); + SLICE_94 SLICE_94( .B1(FS_15), .A1(FS_13), .D0(FS_11), .C0(FS_16), + .B0(FS_13), .A0(FS_15), .F0(n12), .F1(n2272)); + SLICE_95 SLICE_95( .B1(FS_10), .A1(n62), .D0(InitReady), .C0(FS_10), + .B0(n2464), .A0(FS_11), .M1(MAin_c_5), .M0(MAin_c_4), .LSR(Ready), + .CLK(nCRAS_c), .F0(LEDEN_N_82), .Q0(RowA_4), .F1(RCLK_c_enable_25), + .Q1(RowA_5)); + SLICE_96 SLICE_96( .C1(nRowColSel), .B1(MAin_c_3), .A1(RowA_3), .D0(Bank_1), + .C0(Bank_4), .B0(MAin_c_3), .A0(MAin_c_7), .M1(MAin_c_3), .M0(MAin_c_2), + .LSR(Ready), .CLK(nCRAS_c), .F0(n2316), .Q0(RowA_2), .F1(RA_1_3), + .Q1(RowA_3)); + SLICE_97 SLICE_97( .C1(nRowColSel), .B1(MAin_c_4), .A1(RowA_4), .D0(Bank_0), + .C0(Bank_7), .B0(MAin_c_4), .A0(MAin_c_6), .M1(MAin_c_1), .M0(MAin_c_0), + .LSR(Ready), .CLK(nCRAS_c), .F0(n2314), .Q0(RowA_0), .F1(RA_1_4), + .Q1(RowA_1)); + SLICE_98 SLICE_98( .C1(nRowColSel), .B1(MAin_c_0), .A1(RowA_0), + .C0(nRowColSel), .B0(MAin_c_8), .A0(RowA_8), .M1(nFWE_c), .M0(nCCAS_c), + .CLK(nCRAS_c), .F0(RA_1_8), .Q0(CBR), .F1(RA_1_0), .Q1(FWEr)); + SLICE_99 SLICE_99( .C1(nRowColSel), .B1(MAin_c_1), .A1(RowA_1), + .C0(nRowColSel), .B0(MAin_c_7), .A0(RowA_7), .M1(Din_c_7), .M0(Din_c_6), + .CLK(PHI2_c), .F0(RA_1_7), .Q0(Bank_6), .F1(RA_1_1), .Q1(Bank_7)); + SLICE_100 SLICE_100( .D1(Ready), .C1(nRowColSel_N_33), .B1(InitReady), + .A1(RASr2), .D0(InitReady), .C0(PHI2r2), .B0(CmdSubmitted), .A0(PHI2r3), + .M1(n736), .M0(n737), .CE(RCLK_c_enable_23), .CLK(RCLK_c), + .F0(RCLK_c_enable_24), .Q0(n736), .F1(n6), .Q1(n735)); + SLICE_101 SLICE_101( .C1(nRowColSel), .B1(MAin_c_2), .A1(RowA_2), + .C0(nRowColSel), .B0(MAin_c_6), .A0(RowA_6), .M1(Din_c_5), .M0(Din_c_4), + .CLK(PHI2_c), .F0(RA_1_6), .Q0(Bank_4), .F1(RA_1_2), .Q1(Bank_5)); + SLICE_102 SLICE_102( .B1(nRWE_N_177), .A1(nRCAS_N_165), .C0(nRCAS_N_165), + .B0(nRCS_N_139), .A0(InitReady), .M1(Din_c_3), .M0(Din_c_2), .CLK(PHI2_c), + .F0(n2427), .Q0(Bank_2), .F1(n33), .Q1(Bank_3)); + SLICE_103 SLICE_103( .C1(nRowColSel), .B1(MAin_c_5), .A1(RowA_5), .C0(CBR), + .B0(CASr3), .A0(FWEr), .M1(Din_c_3), .M0(Din_c_2), .CLK(nCCAS_c), + .F0(nRowColSel_N_28), .Q0(WRD_2), .F1(RA_1_5), .Q1(WRD_3)); + SLICE_104 SLICE_104( .B1(Ready), .A1(n2414), .D0(nRowColSel_N_35), + .C0(nRWE_N_182), .B0(n1502), .A0(n1), .F0(nRWE_N_178), .F1(Ready_N_292)); + SLICE_105 SLICE_105( .B1(nFWE_c), .A1(nCCAS_c), .C0(n13_adj_2), .B0(Din_c_4), + .A0(n2253), .M1(Din_c_5), .M0(Din_c_4), .CLK(nCCAS_c), .F0(n14), + .Q0(WRD_4), .F1(n984), .Q1(WRD_5)); + RD_7_ \RD[7]_I ( .PADDI(Dout_c), .PADDT(n984), .PADDO(WRD_7), .RD7(RD[7])); + RD_6_ \RD[6]_I ( .PADDI(Dout_0), .PADDT(n984), .PADDO(WRD_6), .RD6(RD[6])); + RD_5_ \RD[5]_I ( .PADDI(Dout_1), .PADDT(n984), .PADDO(WRD_5), .RD5(RD[5])); + RD_4_ \RD[4]_I ( .PADDI(Dout_2), .PADDT(n984), .PADDO(WRD_4), .RD4(RD[4])); + RD_3_ \RD[3]_I ( .PADDI(Dout_3), .PADDT(n984), .PADDO(WRD_3), .RD3(RD[3])); + RD_2_ \RD[2]_I ( .PADDI(Dout_4), .PADDT(n984), .PADDO(WRD_2), .RD2(RD[2])); + RD_1_ \RD[1]_I ( .PADDI(Dout_5), .PADDT(n984), .PADDO(WRD_1), .RD1(RD[1])); + RD_0_ \RD[0]_I ( .PADDI(Dout_6), .PADDT(n984), .PADDO(WRD_0), .RD0(RD[0])); + Dout_7_ \Dout[7]_I ( .PADDO(Dout_c), .Dout7(Dout[7])); + Dout_6_ \Dout[6]_I ( .PADDO(Dout_0), .Dout6(Dout[6])); + Dout_5_ \Dout[5]_I ( .PADDO(Dout_1), .Dout5(Dout[5])); + Dout_4_ \Dout[4]_I ( .PADDO(Dout_2), .Dout4(Dout[4])); + Dout_3_ \Dout[3]_I ( .PADDO(Dout_3), .Dout3(Dout[3])); + Dout_2_ \Dout[2]_I ( .PADDO(Dout_4), .Dout2(Dout[2])); + Dout_1_ \Dout[1]_I ( .PADDO(Dout_5), .Dout1(Dout[1])); + Dout_0_ \Dout[0]_I ( .PADDO(Dout_6), .Dout0(Dout[0])); + LED LED_I( .PADDO(LED_N_84), .LED(LED)); + RBA_1_ \RBA[1]_I ( .PADDO(RBA_c_1), .RBA1(RBA[1])); + RBA_0_ \RBA[0]_I ( .PADDO(RBA_c_0), .RBA0(RBA[0])); + RA_11_ \RA[11]_I ( .PADDO(RA_c), .RA11(RA[11])); + RA_10_ \RA[10]_I ( .PADDO(RA_0), .RA10(RA[10])); + RA_9_ \RA[9]_I ( .PADDO(RA_1_9), .RA9(RA[9])); + RA_8_ \RA[8]_I ( .PADDO(RA_1_8), .RA8(RA[8])); + RA_7_ \RA[7]_I ( .PADDO(RA_1_7), .RA7(RA[7])); + RA_6_ \RA[6]_I ( .PADDO(RA_1_6), .RA6(RA[6])); + RA_5_ \RA[5]_I ( .PADDO(RA_1_5), .RA5(RA[5])); + RA_4_ \RA[4]_I ( .PADDO(RA_1_4), .RA4(RA[4])); + RA_3_ \RA[3]_I ( .PADDO(RA_1_3), .RA3(RA[3])); + RA_2_ \RA[2]_I ( .PADDO(RA_1_2), .RA2(RA[2])); + RA_1_ \RA[1]_I ( .PADDO(RA_1_1), .RA1(RA[1])); + RA_0_ \RA[0]_I ( .PADDO(RA_1_0), .RA0(RA[0])); + nRCS nRCS_I( .PADDO(nRCS_c), .nRCS(nRCS)); + RCKE RCKE_I( .PADDO(RCKE_c), .RCKE(RCKE)); + nRWE nRWE_I( .PADDO(nRWE_c), .nRWE(nRWE)); + nRRAS nRRAS_I( .PADDO(nRRAS_c), .nRRAS(nRRAS)); + nRCAS nRCAS_I( .PADDO(nRCAS_c), .nRCAS(nRCAS)); + RDQMH RDQMH_I( .PADDO(RDQMH_c), .RDQMH(RDQMH)); + RDQML RDQML_I( .PADDO(RDQML_c), .RDQML(RDQML)); + nUFMCS nUFMCS_I( .PADDO(nUFMCS_c), .nUFMCS(nUFMCS)); + UFMCLK UFMCLK_I( .PADDO(UFMCLK_c), .UFMCLK(UFMCLK)); + UFMSDI UFMSDI_I( .PADDO(UFMSDI_c), .UFMSDI(UFMSDI)); + PHI2 PHI2_I( .PADDI(PHI2_c), .PHI2(PHI2)); + MAin_9_ \MAin[9]_I ( .PADDI(MAin_c_9), .MAin9(MAin[9])); + MAin_8_ \MAin[8]_I ( .PADDI(MAin_c_8), .MAin8(MAin[8])); + MAin_7_ \MAin[7]_I ( .PADDI(MAin_c_7), .MAin7(MAin[7])); + MAin_6_ \MAin[6]_I ( .PADDI(MAin_c_6), .MAin6(MAin[6])); + MAin_5_ \MAin[5]_I ( .PADDI(MAin_c_5), .MAin5(MAin[5])); + MAin_4_ \MAin[4]_I ( .PADDI(MAin_c_4), .MAin4(MAin[4])); + MAin_3_ \MAin[3]_I ( .PADDI(MAin_c_3), .MAin3(MAin[3])); + MAin_2_ \MAin[2]_I ( .PADDI(MAin_c_2), .MAin2(MAin[2])); + MAin_1_ \MAin[1]_I ( .PADDI(MAin_c_1), .MAin1(MAin[1])); + MAin_0_ \MAin[0]_I ( .PADDI(MAin_c_0), .MAin0(MAin[0])); + CROW_1_ \CROW[1]_I ( .PADDI(CROW_c_1), .CROW1(CROW[1])); + CROW_0_ \CROW[0]_I ( .PADDI(CROW_c_0), .CROW0(CROW[0])); + Din_7_ \Din[7]_I ( .PADDI(Din_c_7), .Din7(Din[7])); + Din_6_ \Din[6]_I ( .PADDI(Din_c_6), .Din6(Din[6])); + Din_5_ \Din[5]_I ( .PADDI(Din_c_5), .Din5(Din[5])); + Din_4_ \Din[4]_I ( .PADDI(Din_c_4), .Din4(Din[4])); + Din_3_ \Din[3]_I ( .PADDI(Din_c_3), .Din3(Din[3])); + Din_2_ \Din[2]_I ( .PADDI(Din_c_2), .Din2(Din[2])); + Din_1_ \Din[1]_I ( .PADDI(Din_c_1), .Din1(Din[1])); + Din_0_ \Din[0]_I ( .PADDI(Din_c_0), .Din0(Din[0])); + nCCAS nCCAS_I( .PADDI(nCCAS_c), .nCCAS(nCCAS)); + nCRAS nCRAS_I( .PADDI(nCRAS_c), .nCRAS(nCRAS)); + nFWE nFWE_I( .PADDI(nFWE_c), .nFWE(nFWE)); + RCLK RCLK_I( .PADDI(RCLK_c), .RCLK(RCLK)); + UFMSDO UFMSDO_I( .PADDI(UFMSDO_c), .UFMSDO(UFMSDO)); + VHI VHI_INST( .Z(VCCI)); + PUR PUR_INST( .PUR(VCCI)); + GSR GSR_INST( .GSR(VCCI)); + VLO VLO_INST( .Z(GNDI_TSALL)); + TSALL TSALL_INST( .TSALL(GNDI_TSALL)); +endmodule + +module SLICE_0 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, \SLICE_0/FS_610_add_4_8_S1 , GNDI, \SLICE_0/FS_610_add_4_8_S0 , + A1_dly, CLK_dly, A0_dly, FCI_dly; + + vmuxregsre FS_610__i7( .D0(VCCI), .D1(\SLICE_0/FS_610_add_4_8_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i6( .D0(VCCI), .D1(\SLICE_0/FS_610_add_4_8_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_8( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), + .S0(\SLICE_0/FS_610_add_4_8_S0 ), .S1(\SLICE_0/FS_610_add_4_8_S1 ), .CO0(), + .CO1(FCO)); + + specify + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly); + endspecify + +endmodule + +module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module vcc ( output PWR1 ); + + VHI INST1( .Z(PWR1)); +endmodule + +module gnd ( output PWR0 ); + + VLO INST1( .Z(PWR0)); +endmodule + +module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO0, + CO1 ); + + CCU2 inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT0(CO0), .COUT1(CO1)); + defparam inst1.INIT0 = 16'hfaaa; + defparam inst1.INIT1 = 16'hfaaa; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_1 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, \SLICE_1/FS_610_add_4_16_S1 , GNDI, + \SLICE_1/FS_610_add_4_16_S0 , A1_dly, CLK_dly, A0_dly, FCI_dly; + + vmuxregsre FS_610__i15( .D0(VCCI), .D1(\SLICE_1/FS_610_add_4_16_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i14( .D0(VCCI), .D1(\SLICE_1/FS_610_add_4_16_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_16( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), + .S0(\SLICE_1/FS_610_add_4_16_S0 ), .S1(\SLICE_1/FS_610_add_4_16_S1 ), + .CO0(), .CO1(FCO)); + + specify + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly); + endspecify + +endmodule + +module SLICE_2 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, \SLICE_2/FS_610_add_4_6_S1 , GNDI, \SLICE_2/FS_610_add_4_6_S0 , + A1_dly, CLK_dly, A0_dly, FCI_dly; + + vmuxregsre FS_610__i5( .D0(VCCI), .D1(\SLICE_2/FS_610_add_4_6_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i4( .D0(VCCI), .D1(\SLICE_2/FS_610_add_4_6_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_6( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), + .S0(\SLICE_2/FS_610_add_4_6_S0 ), .S1(\SLICE_2/FS_610_add_4_6_S1 ), .CO0(), + .CO1(FCO)); + + specify + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly); + endspecify + +endmodule + +module SLICE_3 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, \SLICE_3/FS_610_add_4_14_S1 , GNDI, + \SLICE_3/FS_610_add_4_14_S0 , A1_dly, CLK_dly, A0_dly, FCI_dly; + + vmuxregsre FS_610__i13( .D0(VCCI), .D1(\SLICE_3/FS_610_add_4_14_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i12( .D0(VCCI), .D1(\SLICE_3/FS_610_add_4_14_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_14( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), + .S0(\SLICE_3/FS_610_add_4_14_S0 ), .S1(\SLICE_3/FS_610_add_4_14_S1 ), + .CO0(), .CO1(FCO)); + + specify + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly); + endspecify + +endmodule + +module SLICE_4 ( input A1, A0, CLK, output Q0, Q1, FCO ); + wire VCCI, \SLICE_4/FS_610_add_4_2_S1 , GNDI, \SLICE_4/FS_610_add_4_2_S0 , + A1_dly, CLK_dly, A0_dly; + + vmuxregsre FS_610__i1( .D0(VCCI), .D1(\SLICE_4/FS_610_add_4_2_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i0( .D0(VCCI), .D1(\SLICE_4/FS_610_add_4_2_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20001 FS_610_add_4_2( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), + .S0(\SLICE_4/FS_610_add_4_2_S0 ), .S1(\SLICE_4/FS_610_add_4_2_S1 ), .CO0(), + .CO1(FCO)); + + specify + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + endspecify + +endmodule + +module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO0, + CO1 ); + + CCU2 inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT0(CO0), .COUT1(CO1)); + defparam inst1.INIT0 = 16'h0555; + defparam inst1.INIT1 = 16'hfaaa; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_5 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, \SLICE_5/FS_610_add_4_12_S1 , GNDI, + \SLICE_5/FS_610_add_4_12_S0 , A1_dly, CLK_dly, A0_dly, FCI_dly; + + vmuxregsre FS_610__i11( .D0(VCCI), .D1(\SLICE_5/FS_610_add_4_12_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i10( .D0(VCCI), .D1(\SLICE_5/FS_610_add_4_12_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_12( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), + .S0(\SLICE_5/FS_610_add_4_12_S0 ), .S1(\SLICE_5/FS_610_add_4_12_S1 ), + .CO0(), .CO1(FCO)); + + specify + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly); + endspecify + +endmodule + +module SLICE_6 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, \SLICE_6/FS_610_add_4_4_S1 , GNDI, \SLICE_6/FS_610_add_4_4_S0 , + A1_dly, CLK_dly, A0_dly, FCI_dly; + + vmuxregsre FS_610__i3( .D0(VCCI), .D1(\SLICE_6/FS_610_add_4_4_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i2( .D0(VCCI), .D1(\SLICE_6/FS_610_add_4_4_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_4( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), + .S0(\SLICE_6/FS_610_add_4_4_S0 ), .S1(\SLICE_6/FS_610_add_4_4_S1 ), .CO0(), + .CO1(FCO)); + + specify + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly); + endspecify + +endmodule + +module SLICE_7 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, \SLICE_7/FS_610_add_4_10_S1 , GNDI, + \SLICE_7/FS_610_add_4_10_S0 , A1_dly, CLK_dly, A0_dly, FCI_dly; + + vmuxregsre FS_610__i9( .D0(VCCI), .D1(\SLICE_7/FS_610_add_4_10_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i8( .D0(VCCI), .D1(\SLICE_7/FS_610_add_4_10_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_10( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), + .S0(\SLICE_7/FS_610_add_4_10_S0 ), .S1(\SLICE_7/FS_610_add_4_10_S1 ), + .CO0(), .CO1(FCO)); + + specify + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly); + endspecify + +endmodule + +module SLICE_8 ( input A1, A0, CLK, FCI, output Q0, Q1 ); + wire VCCI, \SLICE_8/FS_610_add_4_18_S1 , GNDI, + \SLICE_8/FS_610_add_4_18_S0 , A1_dly, CLK_dly, A0_dly, FCI_dly; + + vmuxregsre FS_610__i17( .D0(VCCI), .D1(\SLICE_8/FS_610_add_4_18_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i16( .D0(VCCI), .D1(\SLICE_8/FS_610_add_4_18_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_18( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), + .S0(\SLICE_8/FS_610_add_4_18_S0 ), .S1(\SLICE_8/FS_610_add_4_18_S1 ), + .CO0(), .CO1()); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly); + endspecify + +endmodule + +module SLICE_9 ( input C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut4 i1_2_lut_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40002 i1125_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 ADSubmitted_407( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut4 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hDFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40002 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h50DC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0003 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module inverter ( input I, output Z ); + + INV INST1( .A(I), .Z(Z)); +endmodule + +module SLICE_14 ( input B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40004 i1988_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40005 i2062_2_lut_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0006 C1Submitted_406( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40004 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40005 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hE0F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0006 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3JY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module SLICE_18 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40007 i13_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40008 i3_4_lut_adj_21( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdEnable_405( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40007 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hDFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40008 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_19 ( input C1, B1, A1, DI0, CE, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; + + lut40009 i2_3_lut_rep_29( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40010 \n2568\001/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), + .Z(F0)); + vmuxregsre CmdSubmitted_411( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40009 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40010 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_23 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; + + lut40011 i1_2_lut_3_lut_adj_2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40012 Cmdn8MEGEN_I_93_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre Cmdn8MEGEN_410( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40011 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40012 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCC5C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_25 ( input D1, C1, B1, A1, DI0, CE, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40013 i3_3_lut_4_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40010 \n2568\000/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre InitReady_394( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40013 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_26 ( input C1, B1, A1, DI0, CE, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40014 i2049_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40010 m1_lut( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre LEDEN_419( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40014 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_31 ( input B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40015 i1_2_lut_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40011 i2_3_lut_adj_27( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0006 RA10_400( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40015 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_32 ( input B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40004 Din_7__I_0_462_i6_2_lut_rep_35( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40016 RA11_I_54_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 RA11_385( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40016 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hC6C6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_34 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40017 i78_2_lut_rep_24_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40018 i1259_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre RCKEEN_401( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40017 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hF8F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40018 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_35 ( input B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; + + lut40019 i1_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40020 RCKE_I_0_449_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CASr2_383( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre RCKE_395( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40019 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40020 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCFC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_36 ( input B1, A1, DI0, CE, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40015 i771_2_lut_rep_26_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40010 \n2568\002/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), + .Z(F0)); + vmuxregsre Ready_404( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_43 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, CLK, output + F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40021 i919_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40022 i886_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 UFMCLK_416( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40021 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h3A0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40022 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_44 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40023 i1_2_lut_rep_19_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40024 n2454_bdd_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 UFMSDI_417( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40023 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFEFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40024 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hF202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_49 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40025 i2028_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40026 i3_4_lut_adj_12( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre XOR8MEG_408( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40025 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40026 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_56 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut4 i1_2_lut_3_lut_adj_4( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40027 n8MEGEN_I_14_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre n8MEGEN_418( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40027 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCCC5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_58 ( input D1, C1, B1, A1, C0, B0, A0, DI0, M0, CE, CLK, output + OFX0, Q0 ); + wire \SLICE_58/SLICE_58_K1_H1 , GNDI, \SLICE_58/i2095/GATE_H0 , VCCI, + DI0_dly, CLK_dly, CE_dly; + + lut40028 SLICE_58_K1( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\SLICE_58/SLICE_58_K1_H1 )); + lut40029 \i2095/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\SLICE_58/i2095/GATE_H0 )); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0030 nRCAS_398( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 SLICE_58_K0K1MUX( .D0(\SLICE_58/i2095/GATE_H0 ), + .D1(\SLICE_58/SLICE_58_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40028 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h7F2F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40029 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hBFBF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0030 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module selmux2 ( input D0, D1, SD, output Z ); + + MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); +endmodule + +module SLICE_60 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40031 i1234_4_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40032 i1_4_lut_adj_17( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0030 nRCS_396( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40031 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFA88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40032 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCFDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_61 ( input C1, B1, A1, D0, C0, B0, A0, DI0, M0, CLK, output OFX0, + Q0 ); + wire GNDI, \SLICE_61/SLICE_61_K1_H1 , \SLICE_61/i16/GATE_H0 , VCCI, + DI0_dly, CLK_dly; + + lut40033 SLICE_61_K1( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(\SLICE_61/SLICE_61_K1_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40034 \i16/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\SLICE_61/i16/GATE_H0 )); + vmuxregsre0030 nRRAS_397( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 SLICE_61_K0K1MUX( .D0(\SLICE_61/i16/GATE_H0 ), + .D1(\SLICE_61/SLICE_61_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40033 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h7373) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40034 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40035 i2_3_lut_4_lut_adj_8( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40036 nRWE_I_0_455_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0030 nRWE_399( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40035 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFF7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40036 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCFC5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_64 ( input C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; + + lut40018 MAin_9__I_0_427_i10_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40037 i1_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 nRowColSel_402( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40037 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCFEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_65 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40038 Ready_bdd_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40004 i1_2_lut_adj_25( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 S_FSM_i4( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40038 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_66 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40039 i2_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40040 i2057_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 S_FSM_i3( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40039 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40040 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_67 ( input C1, B1, A1, B0, A0, M0, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, LSR_dly; + + lut40041 i1129_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40019 i1_2_lut_adj_23( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0003 S_FSM_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40041 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h3A3A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_68 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M0_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40004 i2024_2_lut_rep_28( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40039 i2026_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CASr3_384( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre S_FSM_i1( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_69 ( input D1, C1, B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; + + lut40042 i6_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40018 i11_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0006 nUFMCS_415( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40042 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module RCKEEN_I_0_445_SLICE_70 ( input C1, B1, A1, D0, C0, B0, A0, M0, output + OFX0 ); + wire GNDI, \RCKEEN_I_0_445/SLICE_70/RCKEEN_I_0_445/SLICE_70_K1_H1 , + \RCKEEN_I_0_445/SLICE_70/RCKEEN_I_0_445/GATE_H0 ; + + lut40043 \RCKEEN_I_0_445/SLICE_70_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(\RCKEEN_I_0_445/SLICE_70/RCKEEN_I_0_445/SLICE_70_K1_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40044 \RCKEEN_I_0_445/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\RCKEEN_I_0_445/SLICE_70/RCKEEN_I_0_445/GATE_H0 )); + selmux2 \RCKEEN_I_0_445/SLICE_70_K0K1MUX ( + .D0(\RCKEEN_I_0_445/SLICE_70/RCKEEN_I_0_445/GATE_H0 ), + .D1(\RCKEEN_I_0_445/SLICE_70/RCKEEN_I_0_445/SLICE_70_K1_H1 ), .SD(M0), + .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40043 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h1F1F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40044 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h5540) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module i26_SLICE_71 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output OFX0 ); + wire \i26/SLICE_71/i26/SLICE_71_K1_H1 , \i26/SLICE_71/i26/GATE_H0 ; + + lut40045 \i26/SLICE_71_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\i26/SLICE_71/i26/SLICE_71_K1_H1 )); + lut40046 \i26/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\i26/SLICE_71/i26/GATE_H0 )); + selmux2 \i26/SLICE_71_K0K1MUX ( .D0(\i26/SLICE_71/i26/GATE_H0 ), + .D1(\i26/SLICE_71/i26/SLICE_71_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40045 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40046 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module i2099_SLICE_72 ( input D1, C1, B1, A1, C0, B0, A0, M0, output OFX0 ); + wire \i2099/SLICE_72/i2099/SLICE_72_K1_H1 , GNDI, + \i2099/SLICE_72/i2099/GATE_H0 ; + + lut40047 \i2099/SLICE_72_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\i2099/SLICE_72/i2099/SLICE_72_K1_H1 )); + lut40048 \i2099/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\i2099/SLICE_72/i2099/GATE_H0 )); + gnd DRIVEGND( .PWR0(GNDI)); + selmux2 \i2099/SLICE_72_K0K1MUX ( .D0(\i2099/SLICE_72/i2099/GATE_H0 ), + .D1(\i2099/SLICE_72/i2099/SLICE_72_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40047 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2F23) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40048 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2F2F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module i26_adj_28_SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output + OFX0 ); + wire \i26_adj_28/SLICE_73/i26_adj_28/SLICE_73_K1_H1 , + \i26_adj_28/SLICE_73/i26_adj_28/GATE_H0 ; + + lut40049 \i26_adj_28/SLICE_73_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\i26_adj_28/SLICE_73/i26_adj_28/SLICE_73_K1_H1 )); + lut40050 \i26_adj_28/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\i26_adj_28/SLICE_73/i26_adj_28/GATE_H0 )); + selmux2 \i26_adj_28/SLICE_73_K0K1MUX ( + .D0(\i26_adj_28/SLICE_73/i26_adj_28/GATE_H0 ), + .D1(\i26_adj_28/SLICE_73/i26_adj_28/SLICE_73_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40049 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40050 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_74 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly; + + lut40051 i35_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40052 i3_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre RASr3_381( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre RASr2_380( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40051 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h1F10) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40052 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_75 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40009 i2_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40053 i7_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40053 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_76 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40054 i5_3_lut_rep_15_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40055 i1_4_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre IS_FSM__i9( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre IS_FSM__i8( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40054 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40055 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hB300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_77 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40056 i3_4_lut_adj_18( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40011 i1994_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre IS_FSM__i13( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i12( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40056 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_78 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40039 i5_3_lut_rep_21_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40057 i2065_2_lut_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 RowA_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 RowA_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40057 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_79 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M0_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40058 i1_2_lut_rep_25_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40059 i2_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre PHI2r2_377( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre CASr_382( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40058 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40059 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_80 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40004 i1_2_lut_adj_16( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40060 i1_2_lut_3_lut_4_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre IS_FSM__i15( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i14( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40060 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_81 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40061 i1982_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40062 i12_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdUFMCS_412( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre CmdUFMCLK_413( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40061 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40062 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hBFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_82 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40063 i2052_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40004 i1990_2_lut_rep_17( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre IS_FSM__i11( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i10( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40063 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0302) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_83 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, + F1 ); + wire M0_NOTIN, VCCI, GNDI, M0_dly, CLK_dly; + + lut40008 i1_2_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40026 i4_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre RASr_379( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_84 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40056 i2_4_lut_adj_11( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40014 i1_2_lut_3_lut_adj_5( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre IS_FSM__i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_85 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40013 i2_3_lut_4_lut_adj_15( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40004 i2004_2_lut_rep_30( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 RBA__i2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 RBA__i1( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_86 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40009 i2_3_lut_adj_10( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40064 i1_2_lut_rep_20_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre IS_FSM__i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40064 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_87 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40040 i2_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40065 i17_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre IS_FSM__i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40065 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_88 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40009 n2452_bdd_2_lut_rep_18_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40066 FS_6__bdd_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre Bank_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre Bank_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40066 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0062) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_89 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40064 i1_2_lut_rep_16_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40014 i2_3_lut_adj_1( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre WRD_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre WRD_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module SLICE_90 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40039 i2032_2_lut_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40004 i2_2_lut_rep_27( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0006 RowA_i9( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 RowA_i8( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_91 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40061 i1_2_lut_rep_33( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40067 i2_4_lut_adj_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre PHI2r_376( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre PHI2r3_378( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40067 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h8C00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_92 ( input B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40068 i1_2_lut_rep_32( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40069 i2_3_lut_rep_31( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre WRD_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre WRD_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module lut40068 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40069 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_93 ( input B1, A1, B0, A0, M0, CE, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; + + lut40070 i2060_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40019 i1512_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre CmdUFMSDI_414( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40070 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_94 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40004 i1976_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 i5_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_95 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40061 i1_2_lut_adj_22( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 i2055_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0006 RowA_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 RowA_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40071 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_96 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40018 MAin_9__I_0_427_i4_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 i2020_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 RowA_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 RowA_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_97 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40018 MAin_9__I_0_427_i5_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 i2018_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 RowA_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 RowA_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_98 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, M1_NOTIN, VCCI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40018 MAin_9__I_0_427_i1_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40018 MAin_9__I_0_427_i9_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre FWEr_389( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre CBR_390( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module SLICE_99 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40018 MAin_9__I_0_427_i2_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40018 MAin_9__I_0_427_i8_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre Bank_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre Bank_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_100 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40072 i2_2_lut_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40073 i1_2_lut_4_lut_adj_7( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre IS_FSM__i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre IS_FSM__i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40072 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hF0F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40073 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h08FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_101 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40018 MAin_9__I_0_427_i3_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40018 MAin_9__I_0_427_i7_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre Bank_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre Bank_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_102 ( input B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40004 i1_2_lut_adj_26( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40014 InitReady_bdd_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre Bank_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre Bank_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_103 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40018 MAin_9__I_0_427_i6_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40014 i2_3_lut_adj_14( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre WRD_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre WRD_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module SLICE_104 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40004 n2414_bdd_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40074 n1_bdd_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40074 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hF0DD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_105 ( input B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40004 i1513_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40075 i2_3_lut_adj_20( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre WRD_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre WRD_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module lut40075 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 ); + + mjiobuf Dout_pad_7__713( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), + .PADI(RD7)); + + specify + (PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD7) = (0:0:0,0:0:0); + (RD7 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD7, 0:0:0); + $width (negedge RD7, 0:0:0); + endspecify + +endmodule + +module mjiobuf ( input I, T, output Z, PAD, input PADI ); + + IBPU INST1( .I(PADI), .O(Z)); + OBZPU INST2( .I(I), .T(T), .O(PAD)); +endmodule + +module RD_6_ ( output PADDI, input PADDT, PADDO, inout RD6 ); + + mjiobuf Dout_pad_6__714( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD6), + .PADI(RD6)); + + specify + (PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD6) = (0:0:0,0:0:0); + (RD6 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD6, 0:0:0); + $width (negedge RD6, 0:0:0); + endspecify + +endmodule + +module RD_5_ ( output PADDI, input PADDT, PADDO, inout RD5 ); + + mjiobuf Dout_pad_5__715( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD5), + .PADI(RD5)); + + specify + (PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD5) = (0:0:0,0:0:0); + (RD5 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD5, 0:0:0); + $width (negedge RD5, 0:0:0); + endspecify + +endmodule + +module RD_4_ ( output PADDI, input PADDT, PADDO, inout RD4 ); + + mjiobuf Dout_pad_4__716( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD4), + .PADI(RD4)); + + specify + (PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD4) = (0:0:0,0:0:0); + (RD4 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD4, 0:0:0); + $width (negedge RD4, 0:0:0); + endspecify + +endmodule + +module RD_3_ ( output PADDI, input PADDT, PADDO, inout RD3 ); + + mjiobuf Dout_pad_3__717( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD3), + .PADI(RD3)); + + specify + (PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD3) = (0:0:0,0:0:0); + (RD3 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD3, 0:0:0); + $width (negedge RD3, 0:0:0); + endspecify + +endmodule + +module RD_2_ ( output PADDI, input PADDT, PADDO, inout RD2 ); + + mjiobuf Dout_pad_2__718( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD2), + .PADI(RD2)); + + specify + (PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD2) = (0:0:0,0:0:0); + (RD2 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD2, 0:0:0); + $width (negedge RD2, 0:0:0); + endspecify + +endmodule + +module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 ); + + mjiobuf Dout_pad_1__719( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD1), + .PADI(RD1)); + + specify + (PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD1) = (0:0:0,0:0:0); + (RD1 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD1, 0:0:0); + $width (negedge RD1, 0:0:0); + endspecify + +endmodule + +module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 ); + + mjiobuf Dout_pad_0__720( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), + .PADI(RD0)); + + specify + (PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD0) = (0:0:0,0:0:0); + (RD0 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD0, 0:0:0); + $width (negedge RD0, 0:0:0); + endspecify + +endmodule + +module Dout_7_ ( input PADDO, output Dout7 ); + wire GNDI; + + mjiobuf0076 Dout_pad_7( .I(PADDO), .T(GNDI), .PAD(Dout7)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module mjiobuf0076 ( input I, T, output PAD ); + + OBZPU INST5( .I(I), .T(T), .O(PAD)); +endmodule + +module Dout_6_ ( input PADDO, output Dout6 ); + wire GNDI; + + mjiobuf0076 Dout_pad_6( .I(PADDO), .T(GNDI), .PAD(Dout6)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_5_ ( input PADDO, output Dout5 ); + wire GNDI; + + mjiobuf0076 Dout_pad_5( .I(PADDO), .T(GNDI), .PAD(Dout5)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_4_ ( input PADDO, output Dout4 ); + wire GNDI; + + mjiobuf0076 Dout_pad_4( .I(PADDO), .T(GNDI), .PAD(Dout4)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_3_ ( input PADDO, output Dout3 ); + wire GNDI; + + mjiobuf0076 Dout_pad_3( .I(PADDO), .T(GNDI), .PAD(Dout3)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_2_ ( input PADDO, output Dout2 ); + wire GNDI; + + mjiobuf0076 Dout_pad_2( .I(PADDO), .T(GNDI), .PAD(Dout2)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_1_ ( input PADDO, output Dout1 ); + wire GNDI; + + mjiobuf0076 Dout_pad_1( .I(PADDO), .T(GNDI), .PAD(Dout1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_0_ ( input PADDO, output Dout0 ); + wire GNDI; + + mjiobuf0076 Dout_pad_0( .I(PADDO), .T(GNDI), .PAD(Dout0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module LED ( input PADDO, output LED ); + wire GNDI; + + mjiobuf0076 LED_pad( .I(PADDO), .T(GNDI), .PAD(LED)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => LED) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RBA_1_ ( input PADDO, output RBA1 ); + wire GNDI; + + mjiobuf0076 RBA_pad_1( .I(PADDO), .T(GNDI), .PAD(RBA1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RBA1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RBA_0_ ( input PADDO, output RBA0 ); + wire GNDI; + + mjiobuf0076 RBA_pad_0( .I(PADDO), .T(GNDI), .PAD(RBA0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RBA0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_11_ ( input PADDO, output RA11 ); + wire GNDI; + + mjiobuf0076 RA_pad_11( .I(PADDO), .T(GNDI), .PAD(RA11)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA11) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_10_ ( input PADDO, output RA10 ); + wire GNDI; + + mjiobuf0076 RA_pad_10( .I(PADDO), .T(GNDI), .PAD(RA10)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA10) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_9_ ( input PADDO, output RA9 ); + wire GNDI; + + mjiobuf0076 RA_pad_9( .I(PADDO), .T(GNDI), .PAD(RA9)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA9) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_8_ ( input PADDO, output RA8 ); + wire GNDI; + + mjiobuf0076 RA_pad_8( .I(PADDO), .T(GNDI), .PAD(RA8)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA8) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_7_ ( input PADDO, output RA7 ); + wire GNDI; + + mjiobuf0076 RA_pad_7( .I(PADDO), .T(GNDI), .PAD(RA7)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_6_ ( input PADDO, output RA6 ); + wire GNDI; + + mjiobuf0076 RA_pad_6( .I(PADDO), .T(GNDI), .PAD(RA6)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_5_ ( input PADDO, output RA5 ); + wire GNDI; + + mjiobuf0076 RA_pad_5( .I(PADDO), .T(GNDI), .PAD(RA5)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_4_ ( input PADDO, output RA4 ); + wire GNDI; + + mjiobuf0076 RA_pad_4( .I(PADDO), .T(GNDI), .PAD(RA4)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_3_ ( input PADDO, output RA3 ); + wire GNDI; + + mjiobuf0076 RA_pad_3( .I(PADDO), .T(GNDI), .PAD(RA3)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_2_ ( input PADDO, output RA2 ); + wire GNDI; + + mjiobuf0076 RA_pad_2( .I(PADDO), .T(GNDI), .PAD(RA2)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_1_ ( input PADDO, output RA1 ); + wire GNDI; + + mjiobuf0076 RA_pad_1( .I(PADDO), .T(GNDI), .PAD(RA1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_0_ ( input PADDO, output RA0 ); + wire GNDI; + + mjiobuf0076 RA_pad_0( .I(PADDO), .T(GNDI), .PAD(RA0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRCS ( input PADDO, output nRCS ); + wire GNDI; + + mjiobuf0076 nRCS_pad( .I(PADDO), .T(GNDI), .PAD(nRCS)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nRCS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RCKE ( input PADDO, output RCKE ); + wire GNDI; + + mjiobuf0076 RCKE_pad( .I(PADDO), .T(GNDI), .PAD(RCKE)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RCKE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRWE ( input PADDO, output nRWE ); + wire GNDI; + + mjiobuf0076 nRWE_pad( .I(PADDO), .T(GNDI), .PAD(nRWE)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nRWE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRRAS ( input PADDO, output nRRAS ); + wire GNDI; + + mjiobuf0076 nRRAS_pad( .I(PADDO), .T(GNDI), .PAD(nRRAS)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nRRAS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRCAS ( input PADDO, output nRCAS ); + wire GNDI; + + mjiobuf0076 nRCAS_pad( .I(PADDO), .T(GNDI), .PAD(nRCAS)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nRCAS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RDQMH ( input PADDO, output RDQMH ); + wire GNDI; + + mjiobuf0076 RDQMH_pad( .I(PADDO), .T(GNDI), .PAD(RDQMH)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RDQMH) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RDQML ( input PADDO, output RDQML ); + wire GNDI; + + mjiobuf0076 RDQML_pad( .I(PADDO), .T(GNDI), .PAD(RDQML)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RDQML) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nUFMCS ( input PADDO, output nUFMCS ); + wire GNDI; + + mjiobuf0076 nUFMCS_pad( .I(PADDO), .T(GNDI), .PAD(nUFMCS)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nUFMCS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module UFMCLK ( input PADDO, output UFMCLK ); + wire GNDI; + + mjiobuf0076 UFMCLK_pad( .I(PADDO), .T(GNDI), .PAD(UFMCLK)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => UFMCLK) = (0:0:0,0:0:0); + endspecify + +endmodule + +module UFMSDI ( input PADDO, output UFMSDI ); + wire GNDI; + + mjiobuf0076 UFMSDI_pad( .I(PADDO), .T(GNDI), .PAD(UFMSDI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => UFMSDI) = (0:0:0,0:0:0); + endspecify + +endmodule + +module PHI2 ( output PADDI, input PHI2 ); + + mjiobuf0077 PHI2_pad( .Z(PADDI), .PAD(PHI2)); + + specify + (PHI2 => PADDI) = (0:0:0,0:0:0); + $width (posedge PHI2, 0:0:0); + $width (negedge PHI2, 0:0:0); + endspecify + +endmodule + +module mjiobuf0077 ( output Z, input PAD ); + + IBPU INST1( .I(PAD), .O(Z)); +endmodule + +module MAin_9_ ( output PADDI, input MAin9 ); + + mjiobuf0077 MAin_pad_9( .Z(PADDI), .PAD(MAin9)); + + specify + (MAin9 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin9, 0:0:0); + $width (negedge MAin9, 0:0:0); + endspecify + +endmodule + +module MAin_8_ ( output PADDI, input MAin8 ); + + mjiobuf0077 MAin_pad_8( .Z(PADDI), .PAD(MAin8)); + + specify + (MAin8 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin8, 0:0:0); + $width (negedge MAin8, 0:0:0); + endspecify + +endmodule + +module MAin_7_ ( output PADDI, input MAin7 ); + + mjiobuf0077 MAin_pad_7( .Z(PADDI), .PAD(MAin7)); + + specify + (MAin7 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin7, 0:0:0); + $width (negedge MAin7, 0:0:0); + endspecify + +endmodule + +module MAin_6_ ( output PADDI, input MAin6 ); + + mjiobuf0077 MAin_pad_6( .Z(PADDI), .PAD(MAin6)); + + specify + (MAin6 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin6, 0:0:0); + $width (negedge MAin6, 0:0:0); + endspecify + +endmodule + +module MAin_5_ ( output PADDI, input MAin5 ); + + mjiobuf0077 MAin_pad_5( .Z(PADDI), .PAD(MAin5)); + + specify + (MAin5 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin5, 0:0:0); + $width (negedge MAin5, 0:0:0); + endspecify + +endmodule + +module MAin_4_ ( output PADDI, input MAin4 ); + + mjiobuf0077 MAin_pad_4( .Z(PADDI), .PAD(MAin4)); + + specify + (MAin4 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin4, 0:0:0); + $width (negedge MAin4, 0:0:0); + endspecify + +endmodule + +module MAin_3_ ( output PADDI, input MAin3 ); + + mjiobuf0077 MAin_pad_3( .Z(PADDI), .PAD(MAin3)); + + specify + (MAin3 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin3, 0:0:0); + $width (negedge MAin3, 0:0:0); + endspecify + +endmodule + +module MAin_2_ ( output PADDI, input MAin2 ); + + mjiobuf0077 MAin_pad_2( .Z(PADDI), .PAD(MAin2)); + + specify + (MAin2 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin2, 0:0:0); + $width (negedge MAin2, 0:0:0); + endspecify + +endmodule + +module MAin_1_ ( output PADDI, input MAin1 ); + + mjiobuf0077 MAin_pad_1( .Z(PADDI), .PAD(MAin1)); + + specify + (MAin1 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin1, 0:0:0); + $width (negedge MAin1, 0:0:0); + endspecify + +endmodule + +module MAin_0_ ( output PADDI, input MAin0 ); + + mjiobuf0077 MAin_pad_0( .Z(PADDI), .PAD(MAin0)); + + specify + (MAin0 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin0, 0:0:0); + $width (negedge MAin0, 0:0:0); + endspecify + +endmodule + +module CROW_1_ ( output PADDI, input CROW1 ); + + mjiobuf0077 CROW_pad_1( .Z(PADDI), .PAD(CROW1)); + + specify + (CROW1 => PADDI) = (0:0:0,0:0:0); + $width (posedge CROW1, 0:0:0); + $width (negedge CROW1, 0:0:0); + endspecify + +endmodule + +module CROW_0_ ( output PADDI, input CROW0 ); + + mjiobuf0077 CROW_pad_0( .Z(PADDI), .PAD(CROW0)); + + specify + (CROW0 => PADDI) = (0:0:0,0:0:0); + $width (posedge CROW0, 0:0:0); + $width (negedge CROW0, 0:0:0); + endspecify + +endmodule + +module Din_7_ ( output PADDI, input Din7 ); + + mjiobuf0077 Din_pad_7( .Z(PADDI), .PAD(Din7)); + + specify + (Din7 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din7, 0:0:0); + $width (negedge Din7, 0:0:0); + endspecify + +endmodule + +module Din_6_ ( output PADDI, input Din6 ); + + mjiobuf0077 Din_pad_6( .Z(PADDI), .PAD(Din6)); + + specify + (Din6 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din6, 0:0:0); + $width (negedge Din6, 0:0:0); + endspecify + +endmodule + +module Din_5_ ( output PADDI, input Din5 ); + + mjiobuf0077 Din_pad_5( .Z(PADDI), .PAD(Din5)); + + specify + (Din5 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din5, 0:0:0); + $width (negedge Din5, 0:0:0); + endspecify + +endmodule + +module Din_4_ ( output PADDI, input Din4 ); + + mjiobuf0077 Din_pad_4( .Z(PADDI), .PAD(Din4)); + + specify + (Din4 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din4, 0:0:0); + $width (negedge Din4, 0:0:0); + endspecify + +endmodule + +module Din_3_ ( output PADDI, input Din3 ); + + mjiobuf0077 Din_pad_3( .Z(PADDI), .PAD(Din3)); + + specify + (Din3 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din3, 0:0:0); + $width (negedge Din3, 0:0:0); + endspecify + +endmodule + +module Din_2_ ( output PADDI, input Din2 ); + + mjiobuf0077 Din_pad_2( .Z(PADDI), .PAD(Din2)); + + specify + (Din2 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din2, 0:0:0); + $width (negedge Din2, 0:0:0); + endspecify + +endmodule + +module Din_1_ ( output PADDI, input Din1 ); + + mjiobuf0077 Din_pad_1( .Z(PADDI), .PAD(Din1)); + + specify + (Din1 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din1, 0:0:0); + $width (negedge Din1, 0:0:0); + endspecify + +endmodule + +module Din_0_ ( output PADDI, input Din0 ); + + mjiobuf0077 Din_pad_0( .Z(PADDI), .PAD(Din0)); + + specify + (Din0 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din0, 0:0:0); + $width (negedge Din0, 0:0:0); + endspecify + +endmodule + +module nCCAS ( output PADDI, input nCCAS ); + + mjiobuf0077 nCCAS_pad( .Z(PADDI), .PAD(nCCAS)); + + specify + (nCCAS => PADDI) = (0:0:0,0:0:0); + $width (posedge nCCAS, 0:0:0); + $width (negedge nCCAS, 0:0:0); + endspecify + +endmodule + +module nCRAS ( output PADDI, input nCRAS ); + + mjiobuf0077 nCRAS_pad( .Z(PADDI), .PAD(nCRAS)); + + specify + (nCRAS => PADDI) = (0:0:0,0:0:0); + $width (posedge nCRAS, 0:0:0); + $width (negedge nCRAS, 0:0:0); + endspecify + +endmodule + +module nFWE ( output PADDI, input nFWE ); + + mjiobuf0077 nFWE_pad( .Z(PADDI), .PAD(nFWE)); + + specify + (nFWE => PADDI) = (0:0:0,0:0:0); + $width (posedge nFWE, 0:0:0); + $width (negedge nFWE, 0:0:0); + endspecify + +endmodule + +module RCLK ( output PADDI, input RCLK ); + + mjiobuf0077 RCLK_pad( .Z(PADDI), .PAD(RCLK)); + + specify + (RCLK => PADDI) = (0:0:0,0:0:0); + $width (posedge RCLK, 0:0:0); + $width (negedge RCLK, 0:0:0); + endspecify + +endmodule + +module UFMSDO ( output PADDI, input UFMSDO ); + + mjiobuf0077 UFMSDO_pad( .Z(PADDI), .PAD(UFMSDO)); + + specify + (UFMSDO => PADDI) = (0:0:0,0:0:0); + $width (posedge UFMSDO, 0:0:0); + $width (negedge UFMSDO, 0:0:0); + endspecify + +endmodule diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mrp.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mrp.html new file mode 100644 index 0000000..58e1c07 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mrp.html @@ -0,0 +1,368 @@ + +Project Summary + + +
    
+            Lattice Mapping Report File for Design Module 'RAM2GS'
+
+
+
+Design Information
+
+Command line:   map -a MachXO -p LCMXO640C -t TQFP100 -s 3 -oc Commercial
+     RAM2GS_LCMXO640C_impl1.ngd -o RAM2GS_LCMXO640C_impl1_map.ncd -pr
+     RAM2GS_LCMXO640C_impl1.prf -mp RAM2GS_LCMXO640C_impl1.mrp -lpf D:/OneDrive/
+     Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lpf
+     -lpf
+     D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/RAM2GS_LCMXO640C.lpf -c
+     0 -gui -msgset
+     D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml 
+Target Vendor:  LATTICE
+Target Device:  LCMXO640CTQFP100
+Target Performance:   3
+Mapper:  mj5g00,  version:  Diamond (64-bit) 3.12.1.454
+Mapped on:  08/15/23  05:03:22
+
+
+Design Summary
+   Number of PFU registers:   102 out of   640 (16%)
+   Number of SLICEs:        71 out of   320 (22%)
+      SLICEs as Logic/ROM:     71 out of   320 (22%)
+      SLICEs as RAM:            0 out of   192 (0%)
+      SLICEs as Carry:          9 out of   320 (3%)
+   Number of LUT4s:        142 out of   640 (22%)
+      Number used as logic LUTs:        124
+      Number used as distributed RAM:     0
+      Number used as ripple logic:       18
+      Number used as shift registers:     0
+   Number of external PIOs: 67 out of 74 (91%)
+   Number of GSRs:  0 out of 1 (0%)
+   JTAG used :      No
+   Readback used :  No
+   Oscillator used :  No
+   Startup used :   No
+   Number of TSALL: 0 out of 1 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
+     distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and
+     ripple logic.
+   Number of clocks:  4
+     Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK )
+     Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
+     Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
+     Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
+   Number of Clock Enables:  13
+     Net PHI2_N_120_enable_4: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_4: 3 loads, 3 LSLICEs
+     Net RCLK_c_enable_23: 8 loads, 8 LSLICEs
+     Net RCLK_c_enable_12: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_3: 1 loads, 1 LSLICEs
+     Net PHI2_N_120_enable_5: 1 loads, 1 LSLICEs
+     Net PHI2_N_120_enable_6: 2 loads, 2 LSLICEs
+     Net RCLK_c_enable_24: 2 loads, 2 LSLICEs
+     Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs
+     Net Ready_N_292: 1 loads, 1 LSLICEs
+
+     Net RCLK_c_enable_11: 1 loads, 1 LSLICEs
+     Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_25: 1 loads, 1 LSLICEs
+   Number of LSRs:  9
+     Net RASr2: 1 loads, 1 LSLICEs
+     Net Ready: 7 loads, 7 LSLICEs
+     Net C1Submitted_N_237: 2 loads, 2 LSLICEs
+     Net n2469: 1 loads, 1 LSLICEs
+     Net nRowColSel_N_35: 1 loads, 1 LSLICEs
+     Net n1846: 2 loads, 2 LSLICEs
+     Net LEDEN_N_82: 1 loads, 1 LSLICEs
+     Net nRowColSel_N_34: 1 loads, 1 LSLICEs
+     Net nRWE_N_177: 1 loads, 1 LSLICEs
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+     Net Ready: 23 loads
+     Net InitReady: 17 loads
+     Net RASr2: 14 loads
+     Net nRowColSel: 13 loads
+     Net MAin_c_0: 12 loads
+     Net nRowColSel_N_35: 12 loads
+     Net Din_c_3: 11 loads
+     Net Din_c_6: 11 loads
+     Net MAin_c_1: 11 loads
+     Net Din_c_4: 10 loads
+
+
+
+
+   Number of warnings:  0
+   Number of errors:    0
+     
+
+
+
+
+Design Errors/Warnings
+
+   No errors or warnings present.
+
+
+
+IO (PIO) Attributes
+
++---------------------+-----------+-----------+------------+------------+
+| IO Name             | Direction | Levelmode | IO         | FIXEDDELAY |
+|                     |           |  IO_TYPE  | Register   |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[7]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[6]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[5]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[4]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[3]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[2]               | BIDIR     | LVCMOS33  |            |            |
+
++---------------------+-----------+-----------+------------+------------+
+| RD[1]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[0]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[7]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[6]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[5]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[4]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[3]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[2]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[1]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[0]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| LED                 | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RBA[1]              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RBA[0]              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[11]              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[10]              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[9]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[8]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[7]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[6]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[5]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[4]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[3]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[2]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[1]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[0]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRCS                | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RCKE                | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRWE                | OUTPUT    | LVCMOS33  |            |            |
+
++---------------------+-----------+-----------+------------+------------+
+| nRRAS               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRCAS               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RDQMH               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RDQML               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nUFMCS              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMCLK              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMSDI              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| PHI2                | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[9]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[8]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[7]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[6]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[5]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[4]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[3]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[2]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[1]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[0]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| CROW[1]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| CROW[0]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[7]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[6]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[5]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[4]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[3]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[2]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[1]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[0]              | INPUT     | LVCMOS33  |            |            |
+
++---------------------+-----------+-----------+------------+------------+
+| nCCAS               | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nCRAS               | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nFWE                | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RCLK                | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMSDO              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+
+
+Removed logic
+
+Block i2 undriven or does not drive anything - clipped.
+Block GSR_INST undriven or does not drive anything - clipped.
+Signal nCRAS_N_9 was merged into signal nCRAS_c
+Signal nCCAS_N_3 was merged into signal nCCAS_c
+Signal PHI2_N_120 was merged into signal PHI2_c
+Signal RASr2_N_63 was merged into signal RASr2
+Signal n1426 was merged into signal nRowColSel_N_35
+Signal nRWE_N_176 was merged into signal nRWE_N_177
+Signal n1425 was merged into signal nRowColSel_N_34
+Signal nFWE_N_5 was merged into signal nFWE_c
+Signal n2477 was merged into signal Ready
+Signal GND_net undriven or does not drive anything - clipped.
+Signal VCC_net undriven or does not drive anything - clipped.
+Signal FS_610_add_4_18/CO1 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_18/CO0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_10/CO0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_4/CO0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_12/CO0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_2/CO0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_14/CO0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_6/CO0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_16/CO0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_8/CO0 undriven or does not drive anything - clipped.
+Block i2135 was optimized away.
+Block i2134 was optimized away.
+Block i2136 was optimized away.
+Block RASr2_I_0_1_lut was optimized away.
+Block i1137_1_lut was optimized away.
+Block nRWE_I_50_1_lut was optimized away.
+Block i1136_1_lut was optimized away.
+Block i1_1_lut was optimized away.
+Block i637_1_lut_rep_34 was optimized away.
+Block i1 was optimized away.
+
+
+
+Run Time and Memory Usage
+-------------------------
+
+   Total CPU Time: 0 secs  
+   Total REAL Time: 0 secs  
+   Peak Memory Usage: 30 MB
+        
+
+
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+     Copyright (c) 1995 AT&T Corp.   All rights reserved.
+     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+     Copyright (c) 2001 Agere Systems   All rights reserved.
+     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
+     reserved.
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_pad.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_pad.html new file mode 100644 index 0000000..3b975e0 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_pad.html @@ -0,0 +1,418 @@ + +PAD Specification File + + +
    PAD Specification File
+***************************
+
+PART TYPE:        LCMXO640C
+Performance Grade:      3
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.17
+
+Tue Aug 15 05:03:28 2023
+
+Pinout by Port Name:
++-----------+----------+---------------+-------+------------------------------+
+| Port Name | Pin/Bank | Buffer Type   | Site  | Properties                   |
++-----------+----------+---------------+-------+------------------------------+
+| CROW[0]   | 32/2     | LVCMOS33_IN   | PB4C  | SLEW:FAST PULL:UP            |
+| CROW[1]   | 34/2     | LVCMOS33_IN   | PB4E  | SLEW:FAST PULL:UP            |
+| Din[0]    | 21/3     | LVCMOS33_IN   | PL10C | SLEW:FAST PULL:UP            |
+| Din[1]    | 15/3     | LVCMOS33_IN   | PL7B  | SLEW:FAST PULL:UP            |
+| Din[2]    | 14/3     | LVCMOS33_IN   | PL5B  | SLEW:FAST PULL:UP            |
+| Din[3]    | 16/3     | LVCMOS33_IN   | PL8C  | SLEW:FAST PULL:UP            |
+| Din[4]    | 18/3     | LVCMOS33_IN   | PL9A  | SLEW:FAST PULL:UP            |
+| Din[5]    | 17/3     | LVCMOS33_IN   | PL8D  | SLEW:FAST PULL:UP            |
+| Din[6]    | 20/3     | LVCMOS33_IN   | PL10A | SLEW:FAST PULL:UP            |
+| Din[7]    | 19/3     | LVCMOS33_IN   | PL9C  | SLEW:FAST PULL:UP            |
+| Dout[0]   | 1/3      | LVCMOS33_OUT  | PL2A  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| Dout[1]   | 7/3      | LVCMOS33_OUT  | PL3C  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| Dout[2]   | 8/3      | LVCMOS33_OUT  | PL3D  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| Dout[3]   | 6/3      | LVCMOS33_OUT  | PL3B  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| Dout[4]   | 4/3      | LVCMOS33_OUT  | PL2D  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| Dout[5]   | 5/3      | LVCMOS33_OUT  | PL3A  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| Dout[6]   | 2/3      | LVCMOS33_OUT  | PL2C  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| Dout[7]   | 3/3      | LVCMOS33_OUT  | PL2B  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| LED       | 57/1     | LVCMOS33_OUT  | PR10B | DRIVE:8mA SLEW:FAST PULL:UP  |
+| MAin[0]   | 23/3     | LVCMOS33_IN   | PL11C | SLEW:FAST PULL:UP            |
+| MAin[1]   | 38/2     | LVCMOS33_IN   | PB6B  | SLEW:FAST PULL:UP            |
+| MAin[2]   | 37/2     | LVCMOS33_IN   | PB5D  | SLEW:FAST PULL:UP            |
+| MAin[3]   | 47/2     | LVCMOS33_IN   | PB9C  | SLEW:FAST PULL:UP            |
+| MAin[4]   | 46/2     | LVCMOS33_IN   | PB9A  | SLEW:FAST PULL:UP            |
+| MAin[5]   | 45/2     | LVCMOS33_IN   | PB8D  | SLEW:FAST PULL:UP            |
+| MAin[6]   | 49/2     | LVCMOS33_IN   | PB9D  | SLEW:FAST PULL:UP            |
+| MAin[7]   | 44/2     | LVCMOS33_IN   | PB8C  | SLEW:FAST PULL:UP            |
+| MAin[8]   | 50/2     | LVCMOS33_IN   | PB9F  | SLEW:FAST PULL:UP            |
+| MAin[9]   | 51/1     | LVCMOS33_IN   | PR11D | SLEW:FAST PULL:UP            |
+| PHI2      | 39/2     | LVCMOS33_IN   | PB6C  | SLEW:FAST PULL:UP            |
+| RA[0]     | 98/0     | LVCMOS33_OUT  | PT2B  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[10]    | 87/0     | LVCMOS33_OUT  | PT5A  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[11]    | 79/0     | LVCMOS33_OUT  | PT9A  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[1]     | 89/0     | LVCMOS33_OUT  | PT4F  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[2]     | 94/0     | LVCMOS33_OUT  | PT3B  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[3]     | 97/0     | LVCMOS33_OUT  | PT2E  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[4]     | 99/0     | LVCMOS33_OUT  | PT2C  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[5]     | 95/0     | LVCMOS33_OUT  | PT3A  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[6]     | 91/0     | LVCMOS33_OUT  | PT3F  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[7]     | 100/0    | LVCMOS33_OUT  | PT2A  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[8]     | 96/0     | LVCMOS33_OUT  | PT2F  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[9]     | 85/0     | LVCMOS33_OUT  | PT6B  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RBA[0]    | 63/1     | LVCMOS33_OUT  | PR7B  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RBA[1]    | 83/0     | LVCMOS33_OUT  | PT7A  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RCKE      | 82/0     | LVCMOS33_OUT  | PT7E  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RCLK      | 86/0     | LVCMOS33_IN   | PT5B  | SLEW:FAST PULL:UP            |
+| RDQMH     | 76/0     | LVCMOS33_OUT  | PT9F  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RDQML     | 61/1     | LVCMOS33_OUT  | PR9B  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RD[0]     | 64/1     | LVCMOS33_BIDI | PR6C  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RD[1]     | 65/1     | LVCMOS33_BIDI | PR6B  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RD[2]     | 66/1     | LVCMOS33_BIDI | PR5D  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RD[3]     | 67/1     | LVCMOS33_BIDI | PR5B  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RD[4]     | 68/1     | LVCMOS33_BIDI | PR4D  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RD[5]     | 69/1     | LVCMOS33_BIDI | PR4B  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RD[6]     | 70/1     | LVCMOS33_BIDI | PR3D  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RD[7]     | 71/1     | LVCMOS33_BIDI | PR3B  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| UFMCLK    | 58/1     | LVCMOS33_OUT  | PR10A | DRIVE:8mA SLEW:FAST PULL:UP  |
+| UFMSDI    | 56/1     | LVCMOS33_OUT  | PR10C | DRIVE:8mA SLEW:FAST PULL:UP  |
+| UFMSDO    | 55/1     | LVCMOS33_IN   | PR10D | SLEW:FAST PULL:UP            |
+| nCCAS     | 27/2     | LVCMOS33_IN   | PB2C  | SLEW:FAST PULL:UP            |
+| nCRAS     | 43/2     | LVCMOS33_IN   | PB8B  | SLEW:FAST PULL:UP            |
+| nFWE      | 22/3     | LVCMOS33_IN   | PL11A | SLEW:FAST PULL:UP            |
+| nRCAS     | 78/0     | LVCMOS33_OUT  | PT9C  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| nRCS      | 77/0     | LVCMOS33_OUT  | PT9E  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| nRRAS     | 73/1     | LVCMOS33_OUT  | PR2B  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| nRWE      | 72/1     | LVCMOS33_OUT  | PR2D  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| nUFMCS    | 53/1     | LVCMOS33_OUT  | PR11C | DRIVE:8mA SLEW:FAST PULL:UP  |
++-----------+----------+---------------+-------+------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 3.3V  |
+| 1    | 3.3V  |
+| 2    |       |
+| 3    | 3.3V  |
++------+-------+
+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+---------------------+------------+---------------+-------+---------------+
+| Pin/Bank | Pin Info            | Preference | Buffer Type   | Site  | Dual Function |
++----------+---------------------+------------+---------------+-------+---------------+
+| 1/3      | Dout[0]             | LOCATED    | LVCMOS33_OUT  | PL2A  |               |
+| 2/3      | Dout[6]             | LOCATED    | LVCMOS33_OUT  | PL2C  |               |
+| 3/3      | Dout[7]             | LOCATED    | LVCMOS33_OUT  | PL2B  |               |
+| 4/3      | Dout[4]             | LOCATED    | LVCMOS33_OUT  | PL2D  |               |
+| 5/3      | Dout[5]             | LOCATED    | LVCMOS33_OUT  | PL3A  |               |
+| 6/3      | Dout[3]             | LOCATED    | LVCMOS33_OUT  | PL3B  |               |
+| 7/3      | Dout[1]             | LOCATED    | LVCMOS33_OUT  | PL3C  |               |
+| 8/3      | Dout[2]             | LOCATED    | LVCMOS33_OUT  | PL3D  |               |
+| 9/3      |     unused, PULL:UP |            |               | PL4A  |               |
+| 11/3     |     unused, PULL:UP |            |               | PL4C  |               |
+| 13/3     |     unused, PULL:UP |            |               | PL4D  |               |
+| 14/3     | Din[2]              | LOCATED    | LVCMOS33_IN   | PL5B  | GSR_PADN      |
+| 15/3     | Din[1]              | LOCATED    | LVCMOS33_IN   | PL7B  |               |
+| 16/3     | Din[3]              | LOCATED    | LVCMOS33_IN   | PL8C  | TSALLPAD      |
+| 17/3     | Din[5]              | LOCATED    | LVCMOS33_IN   | PL8D  |               |
+| 18/3     | Din[4]              | LOCATED    | LVCMOS33_IN   | PL9A  |               |
+| 19/3     | Din[7]              | LOCATED    | LVCMOS33_IN   | PL9C  |               |
+| 20/3     | Din[6]              | LOCATED    | LVCMOS33_IN   | PL10A |               |
+| 21/3     | Din[0]              | LOCATED    | LVCMOS33_IN   | PL10C |               |
+| 22/3     | nFWE                | LOCATED    | LVCMOS33_IN   | PL11A |               |
+| 23/3     | MAin[0]             | LOCATED    | LVCMOS33_IN   | PL11C |               |
+| 27/2     | nCCAS               | LOCATED    | LVCMOS33_IN   | PB2C  |               |
+| 32/2     | CROW[0]             | LOCATED    | LVCMOS33_IN   | PB4C  |               |
+| 34/2     | CROW[1]             | LOCATED    | LVCMOS33_IN   | PB4E  |               |
+| 36/2     |     unused, PULL:UP |            |               | PB5B  | PCLKT2_1      |
+| 37/2     | MAin[2]             | LOCATED    | LVCMOS33_IN   | PB5D  |               |
+| 38/2     | MAin[1]             | LOCATED    | LVCMOS33_IN   | PB6B  | PCLKT2_0      |
+| 39/2     | PHI2                | LOCATED    | LVCMOS33_IN   | PB6C  |               |
+| 43/2     | nCRAS               | LOCATED    | LVCMOS33_IN   | PB8B  |               |
+| 44/2     | MAin[7]             | LOCATED    | LVCMOS33_IN   | PB8C  |               |
+| 45/2     | MAin[5]             | LOCATED    | LVCMOS33_IN   | PB8D  |               |
+| 46/2     | MAin[4]             | LOCATED    | LVCMOS33_IN   | PB9A  |               |
+| 47/2     | MAin[3]             | LOCATED    | LVCMOS33_IN   | PB9C  |               |
+| 49/2     | MAin[6]             | LOCATED    | LVCMOS33_IN   | PB9D  |               |
+| 50/2     | MAin[8]             | LOCATED    | LVCMOS33_IN   | PB9F  |               |
+| 51/1     | MAin[9]             | LOCATED    | LVCMOS33_IN   | PR11D |               |
+| 52/1     |     unused, PULL:UP |            |               | PR11B |               |
+| 53/1     | nUFMCS              | LOCATED    | LVCMOS33_OUT  | PR11C |               |
+| 54/1     |     unused, PULL:UP |            |               | PR11A |               |
+| 55/1     | UFMSDO              | LOCATED    | LVCMOS33_IN   | PR10D |               |
+| 56/1     | UFMSDI              | LOCATED    | LVCMOS33_OUT  | PR10C |               |
+| 57/1     | LED                 | LOCATED    | LVCMOS33_OUT  | PR10B |               |
+| 58/1     | UFMCLK              | LOCATED    | LVCMOS33_OUT  | PR10A |               |
+| 59/1     |     unused, PULL:UP |            |               | PR9D  |               |
+| 61/1     | RDQML               | LOCATED    | LVCMOS33_OUT  | PR9B  |               |
+| 63/1     | RBA[0]              | LOCATED    | LVCMOS33_OUT  | PR7B  |               |
+| 64/1     | RD[0]               | LOCATED    | LVCMOS33_BIDI | PR6C  |               |
+| 65/1     | RD[1]               | LOCATED    | LVCMOS33_BIDI | PR6B  |               |
+| 66/1     | RD[2]               | LOCATED    | LVCMOS33_BIDI | PR5D  |               |
+| 67/1     | RD[3]               | LOCATED    | LVCMOS33_BIDI | PR5B  |               |
+| 68/1     | RD[4]               | LOCATED    | LVCMOS33_BIDI | PR4D  |               |
+| 69/1     | RD[5]               | LOCATED    | LVCMOS33_BIDI | PR4B  |               |
+| 70/1     | RD[6]               | LOCATED    | LVCMOS33_BIDI | PR3D  |               |
+| 71/1     | RD[7]               | LOCATED    | LVCMOS33_BIDI | PR3B  |               |
+| 72/1     | nRWE                | LOCATED    | LVCMOS33_OUT  | PR2D  |               |
+| 73/1     | nRRAS               | LOCATED    | LVCMOS33_OUT  | PR2B  |               |
+| 76/0     | RDQMH               | LOCATED    | LVCMOS33_OUT  | PT9F  |               |
+| 77/0     | nRCS                | LOCATED    | LVCMOS33_OUT  | PT9E  |               |
+| 78/0     | nRCAS               | LOCATED    | LVCMOS33_OUT  | PT9C  |               |
+| 79/0     | RA[11]              | LOCATED    | LVCMOS33_OUT  | PT9A  |               |
+| 82/0     | RCKE                | LOCATED    | LVCMOS33_OUT  | PT7E  | D7            |
+| 83/0     | RBA[1]              | LOCATED    | LVCMOS33_OUT  | PT7A  | D6            |
+| 85/0     | RA[9]               | LOCATED    | LVCMOS33_OUT  | PT6B  | PCLKT0_1      |
+| 86/0     | RCLK                | LOCATED    | LVCMOS33_IN   | PT5B  | PCLKT0_0      |
+| 87/0     | RA[10]              | LOCATED    | LVCMOS33_OUT  | PT5A  |               |
+| 89/0     | RA[1]               | LOCATED    | LVCMOS33_OUT  | PT4F  |               |
+| 91/0     | RA[6]               | LOCATED    | LVCMOS33_OUT  | PT3F  | D3            |
+| 94/0     | RA[2]               | LOCATED    | LVCMOS33_OUT  | PT3B  |               |
+| 95/0     | RA[5]               | LOCATED    | LVCMOS33_OUT  | PT3A  |               |
+| 96/0     | RA[8]               | LOCATED    | LVCMOS33_OUT  | PT2F  | D2            |
+| 97/0     | RA[3]               | LOCATED    | LVCMOS33_OUT  | PT2E  |               |
+| 98/0     | RA[0]               | LOCATED    | LVCMOS33_OUT  | PT2B  | D1            |
+| 99/0     | RA[4]               | LOCATED    | LVCMOS33_OUT  | PT2C  |               |
+| 100/0    | RA[7]               | LOCATED    | LVCMOS33_OUT  | PT2A  |               |
+| PB2A/2   |     unused, PULL:UP |            |               | PB2A  |               |
+| PB2B/2   |     unused, PULL:UP |            |               | PB2B  |               |
+| PB2D/2   |     unused, PULL:UP |            |               | PB2D  |               |
+| PB3A/2   |     unused, PULL:UP |            |               | PB3A  |               |
+| PB3B/2   |     unused, PULL:UP |            |               | PB3B  |               |
+| PB3C/2   |     unused, PULL:UP |            |               | PB3C  |               |
+| PB3D/2   |     unused, PULL:UP |            |               | PB3D  |               |
+| PB4A/2   |     unused, PULL:UP |            |               | PB4A  |               |
+| PB4B/2   |     unused, PULL:UP |            |               | PB4B  |               |
+| PB4D/2   |     unused, PULL:UP |            |               | PB4D  |               |
+| PB4F/2   |     unused, PULL:UP |            |               | PB4F  |               |
+| PB5A/2   |     unused, PULL:UP |            |               | PB5A  |               |
+| PB5C/2   |     unused, PULL:UP |            |               | PB5C  |               |
+| PB6A/2   |     unused, PULL:UP |            |               | PB6A  |               |
+| PB6D/2   |     unused, PULL:UP |            |               | PB6D  |               |
+| PB7A/2   |     unused, PULL:UP |            |               | PB7A  |               |
+| PB7B/2   |     unused, PULL:UP |            |               | PB7B  |               |
+| PB7C/2   |     unused, PULL:UP |            |               | PB7C  |               |
+| PB7D/2   |     unused, PULL:UP |            |               | PB7D  |               |
+| PB7E/2   |     unused, PULL:UP |            |               | PB7E  |               |
+| PB7F/2   |     unused, PULL:UP |            |               | PB7F  |               |
+| PB8A/2   |     unused, PULL:UP |            |               | PB8A  |               |
+| PB9B/2   |     unused, PULL:UP |            |               | PB9B  |               |
+| PB9E/0   |     unused, PULL:UP |            |               | PB9E  |               |
+| PL4B/3   |     unused, PULL:UP |            |               | PL4B  |               |
+| PL5A/3   |     unused, PULL:UP |            |               | PL5A  |               |
+| PL5C/3   |     unused, PULL:UP |            |               | PL5C  |               |
+| PL5D/3   |     unused, PULL:UP |            |               | PL5D  |               |
+| PL6A/3   |     unused, PULL:UP |            |               | PL6A  |               |
+| PL6B/3   |     unused, PULL:UP |            |               | PL6B  |               |
+| PL6C/3   |     unused, PULL:UP |            |               | PL6C  |               |
+| PL6D/3   |     unused, PULL:UP |            |               | PL6D  |               |
+| PL7A/3   |     unused, PULL:UP |            |               | PL7A  |               |
+| PL7C/3   |     unused, PULL:UP |            |               | PL7C  |               |
+| PL7D/3   |     unused, PULL:UP |            |               | PL7D  |               |
+| PL8A/3   |     unused, PULL:UP |            |               | PL8A  |               |
+| PL8B/3   |     unused, PULL:UP |            |               | PL8B  |               |
+| PL9B/3   |     unused, PULL:UP |            |               | PL9B  |               |
+| PL9D/3   |     unused, PULL:UP |            |               | PL9D  |               |
+| PL10B/3  |     unused, PULL:UP |            |               | PL10B |               |
+| PL10D/3  |     unused, PULL:UP |            |               | PL10D |               |
+| PL11B/3  |     unused, PULL:UP |            |               | PL11B |               |
+| PL11D/3  |     unused, PULL:UP |            |               | PL11D |               |
+| PR2A/1   |     unused, PULL:UP |            |               | PR2A  |               |
+| PR2C/1   |     unused, PULL:UP |            |               | PR2C  |               |
+| PR3A/1   |     unused, PULL:UP |            |               | PR3A  |               |
+| PR3C/1   |     unused, PULL:UP |            |               | PR3C  |               |
+| PR4A/1   |     unused, PULL:UP |            |               | PR4A  |               |
+| PR4C/1   |     unused, PULL:UP |            |               | PR4C  |               |
+| PR5A/1   |     unused, PULL:UP |            |               | PR5A  |               |
+| PR5C/1   |     unused, PULL:UP |            |               | PR5C  |               |
+| PR6A/1   |     unused, PULL:UP |            |               | PR6A  |               |
+| PR6D/1   |     unused, PULL:UP |            |               | PR6D  |               |
+| PR7A/1   |     unused, PULL:UP |            |               | PR7A  |               |
+| PR7C/1   |     unused, PULL:UP |            |               | PR7C  |               |
+| PR7D/1   |     unused, PULL:UP |            |               | PR7D  |               |
+| PR8A/1   |     unused, PULL:UP |            |               | PR8A  |               |
+| PR8B/1   |     unused, PULL:UP |            |               | PR8B  |               |
+| PR8C/1   |     unused, PULL:UP |            |               | PR8C  |               |
+| PR8D/1   |     unused, PULL:UP |            |               | PR8D  |               |
+| PR9A/1   |     unused, PULL:UP |            |               | PR9A  |               |
+| PR9C/1   |     unused, PULL:UP |            |               | PR9C  |               |
+| PT2D/0   |     unused, PULL:UP |            |               | PT2D  |               |
+| PT3C/0   |     unused, PULL:UP |            |               | PT3C  |               |
+| PT3D/0   |     unused, PULL:UP |            |               | PT3D  |               |
+| PT3E/0   |     unused, PULL:UP |            |               | PT3E  |               |
+| PT4A/0   |     unused, PULL:UP |            |               | PT4A  |               |
+| PT4B/0   |     unused, PULL:UP |            |               | PT4B  |               |
+| PT4C/0   |     unused, PULL:UP |            |               | PT4C  |               |
+| PT4D/0   |     unused, PULL:UP |            |               | PT4D  |               |
+| PT4E/0   |     unused, PULL:UP |            |               | PT4E  |               |
+| PT5C/0   |     unused, PULL:UP |            |               | PT5C  |               |
+| PT5D/0   |     unused, PULL:UP |            |               | PT5D  |               |
+| PT6A/0   |     unused, PULL:UP |            |               | PT6A  |               |
+| PT6C/0   |     unused, PULL:UP |            |               | PT6C  |               |
+| PT6D/0   |     unused, PULL:UP |            |               | PT6D  |               |
+| PT7B/0   |     unused, PULL:UP |            |               | PT7B  |               |
+| PT7C/0   |     unused, PULL:UP |            |               | PT7C  |               |
+| PT7D/0   |     unused, PULL:UP |            |               | PT7D  |               |
+| PT7F/0   |     unused, PULL:UP |            |               | PT7F  |               |
+| PT8A/0   |     unused, PULL:UP |            |               | PT8A  |               |
+| PT8B/0   |     unused, PULL:UP |            |               | PT8B  |               |
+| PT8C/0   |     unused, PULL:UP |            |               | PT8C  |               |
+| PT8D/0   |     unused, PULL:UP |            |               | PT8D  |               |
+| PT9B/0   |     unused, PULL:UP |            |               | PT9B  |               |
+| PT9D/0   |     unused, PULL:UP |            |               | PT9D  |               |
+| TCK/2    |                     |            |               | TCK   | TCK           |
+| TDI/2    |                     |            |               | TDI   | TDID0         |
+| TDO/2    |                     |            |               | TDO   | TDO           |
+| TMS/2    |                     |            |               | TMS   | TMS           |
++----------+---------------------+------------+---------------+-------+---------------+
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "CROW[0]"  SITE  "32";
+LOCATE  COMP  "CROW[1]"  SITE  "34";
+LOCATE  COMP  "Din[0]"  SITE  "21";
+LOCATE  COMP  "Din[1]"  SITE  "15";
+LOCATE  COMP  "Din[2]"  SITE  "14";
+LOCATE  COMP  "Din[3]"  SITE  "16";
+LOCATE  COMP  "Din[4]"  SITE  "18";
+LOCATE  COMP  "Din[5]"  SITE  "17";
+LOCATE  COMP  "Din[6]"  SITE  "20";
+LOCATE  COMP  "Din[7]"  SITE  "19";
+LOCATE  COMP  "Dout[0]"  SITE  "1";
+LOCATE  COMP  "Dout[1]"  SITE  "7";
+LOCATE  COMP  "Dout[2]"  SITE  "8";
+LOCATE  COMP  "Dout[3]"  SITE  "6";
+LOCATE  COMP  "Dout[4]"  SITE  "4";
+LOCATE  COMP  "Dout[5]"  SITE  "5";
+LOCATE  COMP  "Dout[6]"  SITE  "2";
+LOCATE  COMP  "Dout[7]"  SITE  "3";
+LOCATE  COMP  "LED"  SITE  "57";
+LOCATE  COMP  "MAin[0]"  SITE  "23";
+LOCATE  COMP  "MAin[1]"  SITE  "38";
+LOCATE  COMP  "MAin[2]"  SITE  "37";
+LOCATE  COMP  "MAin[3]"  SITE  "47";
+LOCATE  COMP  "MAin[4]"  SITE  "46";
+LOCATE  COMP  "MAin[5]"  SITE  "45";
+LOCATE  COMP  "MAin[6]"  SITE  "49";
+LOCATE  COMP  "MAin[7]"  SITE  "44";
+LOCATE  COMP  "MAin[8]"  SITE  "50";
+LOCATE  COMP  "MAin[9]"  SITE  "51";
+LOCATE  COMP  "PHI2"  SITE  "39";
+LOCATE  COMP  "RA[0]"  SITE  "98";
+LOCATE  COMP  "RA[10]"  SITE  "87";
+LOCATE  COMP  "RA[11]"  SITE  "79";
+LOCATE  COMP  "RA[1]"  SITE  "89";
+LOCATE  COMP  "RA[2]"  SITE  "94";
+LOCATE  COMP  "RA[3]"  SITE  "97";
+LOCATE  COMP  "RA[4]"  SITE  "99";
+LOCATE  COMP  "RA[5]"  SITE  "95";
+LOCATE  COMP  "RA[6]"  SITE  "91";
+LOCATE  COMP  "RA[7]"  SITE  "100";
+LOCATE  COMP  "RA[8]"  SITE  "96";
+LOCATE  COMP  "RA[9]"  SITE  "85";
+LOCATE  COMP  "RBA[0]"  SITE  "63";
+LOCATE  COMP  "RBA[1]"  SITE  "83";
+LOCATE  COMP  "RCKE"  SITE  "82";
+LOCATE  COMP  "RCLK"  SITE  "86";
+LOCATE  COMP  "RDQMH"  SITE  "76";
+LOCATE  COMP  "RDQML"  SITE  "61";
+LOCATE  COMP  "RD[0]"  SITE  "64";
+LOCATE  COMP  "RD[1]"  SITE  "65";
+LOCATE  COMP  "RD[2]"  SITE  "66";
+LOCATE  COMP  "RD[3]"  SITE  "67";
+LOCATE  COMP  "RD[4]"  SITE  "68";
+LOCATE  COMP  "RD[5]"  SITE  "69";
+LOCATE  COMP  "RD[6]"  SITE  "70";
+LOCATE  COMP  "RD[7]"  SITE  "71";
+LOCATE  COMP  "UFMCLK"  SITE  "58";
+LOCATE  COMP  "UFMSDI"  SITE  "56";
+LOCATE  COMP  "UFMSDO"  SITE  "55";
+LOCATE  COMP  "nCCAS"  SITE  "27";
+LOCATE  COMP  "nCRAS"  SITE  "43";
+LOCATE  COMP  "nFWE"  SITE  "22";
+LOCATE  COMP  "nRCAS"  SITE  "78";
+LOCATE  COMP  "nRCS"  SITE  "77";
+LOCATE  COMP  "nRRAS"  SITE  "73";
+LOCATE  COMP  "nRWE"  SITE  "72";
+LOCATE  COMP  "nUFMCS"  SITE  "53";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 15 05:03:28 2023
+
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_par.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_par.html new file mode 100644 index 0000000..d480245 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_par.html @@ -0,0 +1,321 @@ + +Place & Route Report + + +
    PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 15 05:03:25 2023
+
+C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO640C_impl1.p2t
+RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir
+RAM2GS_LCMXO640C_impl1.prf -gui -msgset
+D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml
+
+
+Preference file: RAM2GS_LCMXO640C_impl1.prf.
+
+Cost Table Summary
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            -9.822       909228       0.273        0            04           Completed
+* : Design saved.
+
+Total (real) run time for 1-seed: 4 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Lattice Place and Route Report for Design "RAM2GS_LCMXO640C_impl1_map.ncd"
+Tue Aug 15 05:03:25 2023
+
+
+Best Par Run
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir/5_1.ncd RAM2GS_LCMXO640C_impl1.prf
+Preference file: RAM2GS_LCMXO640C_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file RAM2GS_LCMXO640C_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 3
+Loading device for application par from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+
+Device utilization summary:
+
+   PIO (prelim)      67/159          42% used
+                     67/74           90% bonded
+   SLICE             71/320          22% used
+
+
+
+Number of Signals: 262
+Number of Connections: 662
+
+Pin Constraint Summary:
+   67 out of 67 pins locked (100% locked).
+
+The following 2 signals are selected to use the primary clock routing resources:
+    RCLK_c (driver: RCLK, clk load #: 40)
+    PHI2_c (driver: PHI2, clk load #: 13)
+
+The following 1 signal is selected to use the secondary clock routing resources:
+    nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0)
+
+No signal is selected as Global Set/Reset.
+Starting Placer Phase 0.
+.........
+Finished Placer Phase 0.  REAL time: 0 secs 
+
+Starting Placer Phase 1.
+.........
+Placer score = 1223575.
+Finished Placer Phase 1.  REAL time: 3 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  1220793
+Finished Placer Phase 2.  REAL time: 3 secs 
+
+
+
+Clock Report
+
+Global Clock Resources:
+  CLK_PIN    : 1 out of 4 (25%)
+  General PIO: 1 out of 160 (0%)
+
+Global Clocks:
+  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT5B)", clk load = 40
+  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB6C)", clk load = 13
+  SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB8B)", clk load = 7, ce load = 0, sr load = 0
+
+  PRIMARY  : 2 out of 4 (50%)
+  SECONDARY: 1 out of 4 (25%)
+
+
+
+
+I/O Usage Summary (final):
+   67 out of 159 (42.1%) PIO sites used.
+   67 out of 74 (90.5%) bonded PIO sites used.
+   Number of PIO comps: 67; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+------------+------------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
++----------+----------------+------------+------------+------------+
+| 0        | 18 / 18 (100%) | 3.3V       | -          | -          |
+| 1        | 18 / 21 ( 85%) | 3.3V       | -          | -          |
+| 2        | 13 / 14 ( 92%) | -          | -          | -          |
+| 3        | 18 / 21 ( 85%) | 3.3V       | -          | -          |
++----------+----------------+------------+------------+------------+
+
+Total placer CPU time: 3 secs 
+
+Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
+
+0 connections routed; 662 unrouted.
+Starting router resource preassignment
+WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
+WARNING - par: The driver of secondary clock net nCRAS_c is not placed on one of the PIO sites dedicated for secondary clocks.  This secondary clock will be routed through general routing resource and may suffer from excessive delay or skew.
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=nCCAS_c loads=7 clock_loads=4
+
+Completed router resource preassignment. Real time: 3 secs 
+
+Start NBR router at 05:03:28 08/15/23
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 05:03:28 08/15/23
+
+Start NBR section for initial routing at 05:03:28 08/15/23
+Level 1, iteration 1
+0(0.00%) conflict; 559(84.44%) untouched conns; 717961 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -9.776ns/-717.961ns; real time: 3 secs 
+Level 2, iteration 1
+7(0.03%) conflicts; 496(74.92%) untouched conns; 699022 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -9.822ns/-699.022ns; real time: 3 secs 
+Level 3, iteration 1
+9(0.03%) conflicts; 252(38.07%) untouched conns; 765745 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -9.822ns/-765.746ns; real time: 3 secs 
+Level 4, iteration 1
+9(0.03%) conflicts; 0(0.00%) untouched conn; 781820 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -9.822ns/-781.821ns; real time: 4 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 05:03:29 08/15/23
+Level 4, iteration 1
+5(0.02%) conflicts; 0(0.00%) untouched conn; 781048 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -9.822ns/-781.049ns; real time: 4 secs 
+Level 4, iteration 2
+4(0.01%) conflicts; 0(0.00%) untouched conn; 780690 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -9.822ns/-780.691ns; real time: 4 secs 
+Level 4, iteration 3
+4(0.01%) conflicts; 0(0.00%) untouched conn; 780715 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -9.822ns/-780.716ns; real time: 4 secs 
+Level 4, iteration 4
+2(0.01%) conflicts; 0(0.00%) untouched conn; 780715 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -9.822ns/-780.716ns; real time: 4 secs 
+Level 4, iteration 5
+2(0.01%) conflicts; 0(0.00%) untouched conn; 783401 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -9.822ns/-783.402ns; real time: 4 secs 
+Level 4, iteration 6
+0(0.00%) conflict; 0(0.00%) untouched conn; 783401 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -9.822ns/-783.402ns; real time: 4 secs 
+
+Start NBR section for performance tuning (iteration 1) at 05:03:29 08/15/23
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 783401 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -9.822ns/-783.402ns; real time: 4 secs 
+
+Start NBR section for re-routing at 05:03:29 08/15/23
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 776978 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -9.822ns/-776.979ns; real time: 4 secs 
+
+Start NBR section for post-routing at 05:03:29 08/15/23
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 260 (39.27%)
+  Estimated worst slack<setup> : -9.822ns
+  Timing score<setup> : 909228
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=nCCAS_c loads=7 clock_loads=4
+
+Total CPU time 4 secs 
+Total REAL time: 4 secs 
+Completely routed.
+End of route.  662 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 909228 
+
+Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack<setup/<ns>> = -9.822
+PAR_SUMMARY::Timing score<setup/<ns>> = 909.228
+PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.273
+PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 4 secs 
+Total REAL time to completion: 4 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_summary.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_summary.html new file mode 100644 index 0000000..e2f5eb9 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_summary.html @@ -0,0 +1,83 @@ + +Project Summary + + +
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    RAM2GS_LCMXO640C project summary
    Module Name:RAM2GS_LCMXO640CSynthesis:Lattice LSE
    Implementation Name:impl1Strategy Name:Strategy1
    Last Process:JEDEC FileState:Passed
    Target Device:LCMXO640C-3T100CDevice Family:MachXO
    Device Type:LCMXO640CPackage Type:TQFP100
    Performance grade:3Operating conditions:COM
    Logic preference file:RAM2GS_LCMXO640C.lpf
    Physical Preference file:impl1/RAM2GS_LCMXO640C_impl1.prf
    Product Version:3.12.1.454Patch Version:
    Updated:2023/08/15 05:03:36
    Implementation Location:D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1
    Project File:D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_tw1.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_tw1.html new file mode 100644 index 0000000..4f20fac --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_tw1.html @@ -0,0 +1,434 @@ + +Lattice Map TRACE Report + + +
    Map TRACE Report
+
+Loading design for application trce from file ram2gs_lcmxo640c_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 3
+Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
+Tue Aug 15 05:03:23 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf 
+Design file:     ram2gs_lcmxo640c_impl1_map.ncd
+Preference file: ram2gs_lcmxo640c_impl1.prf
+Device,speed:    LCMXO640C,3
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "RCLK_c" 283.768000 MHz (213 errors)
    • 
+                383 items scored, 213 timing errors detected.
+Warning: 116.104MHz is the maximum frequency for this preference.
+
+
  • FREQUENCY NET "PHI2_c" 120.077000 MHz (97 errors)
    • 
+                106 items scored, 97 timing errors detected.
+Warning:  42.739MHz is the maximum frequency for this preference.
+
+Report Type:     based on TRACE automatically generated preferences
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
+            383 items scored, 213 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 5.089ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i14  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_418  (to RCLK_c +)
+
+   Delay:               8.369ns  (24.4% logic, 75.6% route), 5 logic levels.
+
+ Constraint Details:
+
+      8.369ns physical path delay SLICE_1 to SLICE_56 exceeds
+      3.524ns delay constraint less
+      0.244ns CE_SET requirement (totaling 3.280ns) by 5.089ns
+
+ Physical Path Details:
+
+      Data path SLICE_1 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560    SLICE_1.CLK to     SLICE_1.Q0 SLICE_1 (from RCLK_c)
+ROUTE         5   e 1.441     SLICE_1.Q0 to    SLICE_90.C1 FS_14
+CTOF_DEL    ---     0.371    SLICE_90.C1 to    SLICE_90.F1 SLICE_90
+ROUTE         1   e 1.441    SLICE_90.F1 to    SLICE_75.B0 n2328
+CTOF_DEL    ---     0.371    SLICE_75.B0 to    SLICE_75.F0 SLICE_75
+ROUTE         2   e 1.441    SLICE_75.F0 to    SLICE_87.B1 n2214
+CTOF_DEL    ---     0.371    SLICE_87.B1 to    SLICE_87.F1 SLICE_87
+ROUTE         1   e 0.561    SLICE_87.F1 to    SLICE_87.A0 n7
+CTOF_DEL    ---     0.371    SLICE_87.A0 to    SLICE_87.F0 SLICE_87
+ROUTE         1   e 1.441    SLICE_87.F0 to    SLICE_56.CE RCLK_c_enable_11 (to RCLK_c)
+                  --------
+                    8.369   (24.4% logic, 75.6% route), 5 logic levels.
+
+Warning: 116.104MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
+            106 items scored, 97 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 7.535ns (weighted slack = -15.070ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:              11.061ns  (21.8% logic, 78.2% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.061ns physical path delay SLICE_88 to SLICE_14 exceeds
+      4.164ns delay constraint less
+      0.638ns LSR_SET requirement (totaling 3.526ns) by 7.535ns
+
+ Physical Path Details:
+
+      Data path SLICE_88 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_88.CLK to    SLICE_88.Q0 SLICE_88 (from PHI2_c)
+ROUTE         1   e 1.441    SLICE_88.Q0 to    SLICE_97.D0 Bank_0
+CTOF_DEL    ---     0.371    SLICE_97.D0 to    SLICE_97.F0 SLICE_97
+ROUTE         1   e 1.441    SLICE_97.F0 to    SLICE_81.B0 n2314
+CTOF_DEL    ---     0.371    SLICE_81.B0 to    SLICE_81.F0 SLICE_81
+ROUTE         1   e 1.441    SLICE_81.F0 to    SLICE_18.B1 n26
+CTOF_DEL    ---     0.371    SLICE_18.B1 to    SLICE_18.F1 SLICE_18
+ROUTE         8   e 1.441    SLICE_18.F1 to    SLICE_89.B0 n1326
+CTOF_DEL    ---     0.371    SLICE_89.B0 to    SLICE_89.F0 SLICE_89
+ROUTE         1   e 1.441    SLICE_89.F0 to    SLICE_79.C0 n1280
+CTOF_DEL    ---     0.371    SLICE_79.C0 to    SLICE_79.F0 SLICE_79
+ROUTE         2   e 1.441    SLICE_79.F0 to   SLICE_14.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                   11.061   (21.8% logic, 78.2% route), 6 logic levels.
+
+Warning:  42.739MHz is the maximum frequency for this preference.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "RCLK_c" 283.768000 MHz ; |  283.768 MHz|  116.104 MHz|   5 *
+                                        |             |             |
+FREQUENCY NET "PHI2_c" 120.077000 MHz ; |  120.077 MHz|   42.739 MHz|   6 *
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+2 preferences(marked by "*" above) not met.
+
+----------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+----------------------------------------------------------------------------
+n1326                                   |       8|      96|     30.97%
+                                        |        |        |
+n26                                     |       1|      72|     23.23%
+                                        |        |        |
+----------------------------------------------------------------------------
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
+   Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 310  Score: 1346529
+Cumulative negative slack: 874289
+
+Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
+Tue Aug 15 05:03:23 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf 
+Design file:     ram2gs_lcmxo640c_impl1_map.ncd
+Preference file: ram2gs_lcmxo640c_impl1.prf
+Device,speed:    LCMXO640C,M
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "RCLK_c" 283.768000 MHz (0 errors)
    •             383 items scored, 0 timing errors detected.
+
+
  • FREQUENCY NET "PHI2_c" 120.077000 MHz (0 errors)
    •             106 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
+            383 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.342ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i4  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i5  (to RCLK_c +)
+
+   Delay:               0.325ns  (38.8% logic, 61.2% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.325ns physical path delay SLICE_100 to SLICE_100 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint requirement (totaling -0.017ns) by 0.342ns
+
+ Physical Path Details:
+
+      Data path SLICE_100 to SLICE_100:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126  SLICE_100.CLK to   SLICE_100.Q0 SLICE_100 (from RCLK_c)
+ROUTE         1   e 0.199   SLICE_100.Q0 to   SLICE_100.M1 n736 (to RCLK_c)
+                  --------
+                    0.325   (38.8% logic, 61.2% route), 1 logic levels.
+
+
+================================================================================
+Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
+            106 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.430ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_406  (from PHI2_c -)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               0.411ns  (51.3% logic, 48.7% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.411ns physical path delay SLICE_14 to SLICE_14 meets
+     -0.019ns DIN_HLD and
+      0.000ns delay constraint requirement (totaling -0.019ns) by 0.430ns
+
+ Physical Path Details:
+
+      Data path SLICE_14 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137   SLICE_14.CLK to    SLICE_14.Q0 SLICE_14 (from PHI2_c)
+ROUTE         2   e 0.199    SLICE_14.Q0 to    SLICE_14.C0 C1Submitted
+CTOF_DEL    ---     0.074    SLICE_14.C0 to    SLICE_14.F0 SLICE_14
+ROUTE         1   e 0.001    SLICE_14.F0 to   SLICE_14.DI0 n6_adj_3 (to PHI2_c)
+                  --------
+                    0.411   (51.3% logic, 48.7% route), 2 logic levels.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "RCLK_c" 283.768000 MHz ; |     0.000 ns|     0.342 ns|   1  
+                                        |             |             |
+FREQUENCY NET "PHI2_c" 120.077000 MHz ; |     0.000 ns|     0.430 ns|   2  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
+   Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 310 (setup), 0 (hold)
+Score: 1346529 (setup), 0 (hold)
+Cumulative negative slack: 874289 (874289+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_twr.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_twr.html new file mode 100644 index 0000000..eb0175c --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_twr.html @@ -0,0 +1,2242 @@ + +Lattice TRACE Report + + +
    Place & Route TRACE Report
+
+Loading design for application trce from file ram2gs_lcmxo640c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 3
+Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
+Tue Aug 15 05:03:29 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
+Design file:     ram2gs_lcmxo640c_impl1.ncd
+Preference file: ram2gs_lcmxo640c_impl1.prf
+Device,speed:    LCMXO640C,3
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "RCLK_c" 283.768000 MHz (233 errors)
    • 
+                383 items scored, 233 timing errors detected.
+Warning: 116.198MHz is the maximum frequency for this preference.
+
+
  • FREQUENCY NET "PHI2_c" 120.077000 MHz (95 errors)
    • 
+                106 items scored, 95 timing errors detected.
+Warning:  55.096MHz is the maximum frequency for this preference.
+
+Report Type:     based on TRACE automatically generated preferences
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
+            383 items scored, 233 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 5.082ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i13  (from RCLK_c +)
+   Destination:    FF         Data in        UFMSDI_417  (to RCLK_c +)
+
+   Delay:               7.980ns  (21.0% logic, 79.0% route), 4 logic levels.
+
+ Constraint Details:
+
+      7.980ns physical path delay SLICE_3 to SLICE_44 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.626ns LSR_SET requirement (totaling 2.898ns) by 5.082ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C5C.CLK to       R3C5C.Q1 SLICE_3 (from RCLK_c)
+ROUTE         3     1.372       R3C5C.Q1 to       R3C2D.C1 FS_13
+CTOF_DEL    ---     0.371       R3C2D.C1 to       R3C2D.F1 SLICE_94
+ROUTE         3     1.278       R3C2D.F1 to       R4C5B.D1 n2272
+CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_78
+ROUTE         3     0.528       R4C5B.F1 to       R4C5B.C0 n2464
+CTOF_DEL    ---     0.371       R4C5B.C0 to       R4C5B.F0 SLICE_78
+ROUTE         2     3.129       R4C5B.F0 to      R9C9C.LSR n1846 (to RCLK_c)
+                  --------
+                    7.980   (21.0% logic, 79.0% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R3C5C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R9C9C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.998ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i12  (from RCLK_c +)
+   Destination:    FF         Data in        UFMSDI_417  (to RCLK_c +)
+
+   Delay:               7.896ns  (21.2% logic, 78.8% route), 4 logic levels.
+
+ Constraint Details:
+
+      7.896ns physical path delay SLICE_3 to SLICE_44 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.626ns LSR_SET requirement (totaling 2.898ns) by 4.998ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C5C.CLK to       R3C5C.Q0 SLICE_3 (from RCLK_c)
+ROUTE         4     1.063       R3C5C.Q0 to       R3C6C.A1 FS_12
+CTOF_DEL    ---     0.371       R3C6C.A1 to       R3C6C.F1 SLICE_68
+ROUTE         2     1.503       R3C6C.F1 to       R4C5B.A1 n2471
+CTOF_DEL    ---     0.371       R4C5B.A1 to       R4C5B.F1 SLICE_78
+ROUTE         3     0.528       R4C5B.F1 to       R4C5B.C0 n2464
+CTOF_DEL    ---     0.371       R4C5B.C0 to       R4C5B.F0 SLICE_78
+ROUTE         2     3.129       R4C5B.F0 to      R9C9C.LSR n1846 (to RCLK_c)
+                  --------
+                    7.896   (21.2% logic, 78.8% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R3C5C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R9C9C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.889ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i15  (from RCLK_c +)
+   Destination:    FF         Data in        UFMSDI_417  (to RCLK_c +)
+
+   Delay:               7.787ns  (21.5% logic, 78.5% route), 4 logic levels.
+
+ Constraint Details:
+
+      7.787ns physical path delay SLICE_1 to SLICE_44 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.626ns LSR_SET requirement (totaling 2.898ns) by 4.889ns
+
+ Physical Path Details:
+
+      Data path SLICE_1 to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C5D.CLK to       R3C5D.Q1 SLICE_1 (from RCLK_c)
+ROUTE         3     1.179       R3C5D.Q1 to       R3C2D.D1 FS_15
+CTOF_DEL    ---     0.371       R3C2D.D1 to       R3C2D.F1 SLICE_94
+ROUTE         3     1.278       R3C2D.F1 to       R4C5B.D1 n2272
+CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_78
+ROUTE         3     0.528       R4C5B.F1 to       R4C5B.C0 n2464
+CTOF_DEL    ---     0.371       R4C5B.C0 to       R4C5B.F0 SLICE_78
+ROUTE         2     3.129       R4C5B.F0 to      R9C9C.LSR n1846 (to RCLK_c)
+                  --------
+                    7.787   (21.5% logic, 78.5% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R3C5D.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R9C9C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.800ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i17  (from RCLK_c +)
+   Destination:    FF         Data in        UFMSDI_417  (to RCLK_c +)
+
+   Delay:               7.698ns  (21.7% logic, 78.3% route), 4 logic levels.
+
+ Constraint Details:
+
+      7.698ns physical path delay SLICE_8 to SLICE_44 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.626ns LSR_SET requirement (totaling 2.898ns) by 4.800ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C6A.CLK to       R3C6A.Q1 SLICE_8 (from RCLK_c)
+ROUTE         4     0.865       R3C6A.Q1 to       R3C6C.C1 FS_17
+CTOF_DEL    ---     0.371       R3C6C.C1 to       R3C6C.F1 SLICE_68
+ROUTE         2     1.503       R3C6C.F1 to       R4C5B.A1 n2471
+CTOF_DEL    ---     0.371       R4C5B.A1 to       R4C5B.F1 SLICE_78
+ROUTE         3     0.528       R4C5B.F1 to       R4C5B.C0 n2464
+CTOF_DEL    ---     0.371       R4C5B.C0 to       R4C5B.F0 SLICE_78
+ROUTE         2     3.129       R4C5B.F0 to      R9C9C.LSR n1846 (to RCLK_c)
+                  --------
+                    7.698   (21.7% logic, 78.3% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R3C6A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R9C9C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.458ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i13  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
+
+   Delay:               7.801ns  (26.2% logic, 73.8% route), 5 logic levels.
+
+ Constraint Details:
+
+      7.801ns physical path delay SLICE_3 to SLICE_43 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 3.343ns) by 4.458ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C5C.CLK to       R3C5C.Q1 SLICE_3 (from RCLK_c)
+ROUTE         3     1.372       R3C5C.Q1 to       R3C2D.C1 FS_13
+CTOF_DEL    ---     0.371       R3C2D.C1 to       R3C2D.F1 SLICE_94
+ROUTE         3     1.777       R3C2D.F1 to       R9C9C.D1 n2272
+CTOF_DEL    ---     0.371       R9C9C.D1 to       R9C9C.F1 SLICE_44
+ROUTE         2     2.111       R9C9C.F1 to       R3C2B.A1 n2462
+CTOF_DEL    ---     0.371       R3C2B.A1 to       R3C2B.F1 SLICE_43
+ROUTE         1     0.497       R3C2B.F1 to       R3C2B.C0 n1160
+CTOF_DEL    ---     0.371       R3C2B.C0 to       R3C2B.F0 SLICE_43
+ROUTE         1     0.000       R3C2B.F0 to      R3C2B.DI0 UFMCLK_N_224 (to RCLK_c)
+                  --------
+                    7.801   (26.2% logic, 73.8% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R3C5C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R3C2B.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.352ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i13  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_419  (to RCLK_c +)
+
+   Delay:               7.632ns  (21.9% logic, 78.1% route), 4 logic levels.
+
+ Constraint Details:
+
+      7.632ns physical path delay SLICE_3 to SLICE_26 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 3.280ns) by 4.352ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C5C.CLK to       R3C5C.Q1 SLICE_3 (from RCLK_c)
+ROUTE         3     1.372       R3C5C.Q1 to       R3C2D.C1 FS_13
+CTOF_DEL    ---     0.371       R3C2D.C1 to       R3C2D.F1 SLICE_94
+ROUTE         3     1.471       R3C2D.F1 to       R4C5C.C0 n2272
+CTOF_DEL    ---     0.371       R4C5C.C0 to       R4C5C.F0 SLICE_75
+ROUTE         2     0.513       R4C5C.F0 to       R4C5C.C1 n2214
+CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_75
+ROUTE         1     2.603       R4C5C.F1 to       R9C9B.CE RCLK_c_enable_12 (to RCLK_c)
+                  --------
+                    7.632   (21.9% logic, 78.1% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R3C5C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R9C9B.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.293ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i12  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
+
+   Delay:               7.636ns  (26.8% logic, 73.2% route), 5 logic levels.
+
+ Constraint Details:
+
+      7.636ns physical path delay SLICE_3 to SLICE_43 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 3.343ns) by 4.293ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C5C.CLK to       R3C5C.Q0 SLICE_3 (from RCLK_c)
+ROUTE         4     1.063       R3C5C.Q0 to       R3C6C.A1 FS_12
+CTOF_DEL    ---     0.371       R3C6C.A1 to       R3C6C.F1 SLICE_68
+ROUTE         2     1.921       R3C6C.F1 to       R9C9C.C1 n2471
+CTOF_DEL    ---     0.371       R9C9C.C1 to       R9C9C.F1 SLICE_44
+ROUTE         2     2.111       R9C9C.F1 to       R3C2B.A1 n2462
+CTOF_DEL    ---     0.371       R3C2B.A1 to       R3C2B.F1 SLICE_43
+ROUTE         1     0.497       R3C2B.F1 to       R3C2B.C0 n1160
+CTOF_DEL    ---     0.371       R3C2B.C0 to       R3C2B.F0 SLICE_43
+ROUTE         1     0.000       R3C2B.F0 to      R3C2B.DI0 UFMCLK_N_224 (to RCLK_c)
+                  --------
+                    7.636   (26.8% logic, 73.2% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R3C5C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R3C2B.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.265ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i15  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
+
+   Delay:               7.608ns  (26.9% logic, 73.1% route), 5 logic levels.
+
+ Constraint Details:
+
+      7.608ns physical path delay SLICE_1 to SLICE_43 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 3.343ns) by 4.265ns
+
+ Physical Path Details:
+
+      Data path SLICE_1 to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C5D.CLK to       R3C5D.Q1 SLICE_1 (from RCLK_c)
+ROUTE         3     1.179       R3C5D.Q1 to       R3C2D.D1 FS_15
+CTOF_DEL    ---     0.371       R3C2D.D1 to       R3C2D.F1 SLICE_94
+ROUTE         3     1.777       R3C2D.F1 to       R9C9C.D1 n2272
+CTOF_DEL    ---     0.371       R9C9C.D1 to       R9C9C.F1 SLICE_44
+ROUTE         2     2.111       R9C9C.F1 to       R3C2B.A1 n2462
+CTOF_DEL    ---     0.371       R3C2B.A1 to       R3C2B.F1 SLICE_43
+ROUTE         1     0.497       R3C2B.F1 to       R3C2B.C0 n1160
+CTOF_DEL    ---     0.371       R3C2B.C0 to       R3C2B.F0 SLICE_43
+ROUTE         1     0.000       R3C2B.F0 to      R3C2B.DI0 UFMCLK_N_224 (to RCLK_c)
+                  --------
+                    7.608   (26.9% logic, 73.1% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R3C5D.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R3C2B.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.226ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i16  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
+
+   Delay:               7.569ns  (27.0% logic, 73.0% route), 5 logic levels.
+
+ Constraint Details:
+
+      7.569ns physical path delay SLICE_8 to SLICE_43 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 3.343ns) by 4.226ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C6A.CLK to       R3C6A.Q0 SLICE_8 (from RCLK_c)
+ROUTE         5     0.873       R3C6A.Q0 to       R3C6B.C0 FS_16
+CTOF_DEL    ---     0.371       R3C6B.C0 to       R3C6B.F0 SLICE_90
+ROUTE         1     2.044       R3C6B.F0 to       R9C9C.A1 n2470
+CTOF_DEL    ---     0.371       R9C9C.A1 to       R9C9C.F1 SLICE_44
+ROUTE         2     2.111       R9C9C.F1 to       R3C2B.A1 n2462
+CTOF_DEL    ---     0.371       R3C2B.A1 to       R3C2B.F1 SLICE_43
+ROUTE         1     0.497       R3C2B.F1 to       R3C2B.C0 n1160
+CTOF_DEL    ---     0.371       R3C2B.C0 to       R3C2B.F0 SLICE_43
+ROUTE         1     0.000       R3C2B.F0 to      R3C2B.DI0 UFMCLK_N_224 (to RCLK_c)
+                  --------
+                    7.569   (27.0% logic, 73.0% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R3C6A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R3C2B.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.159ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i15  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_419  (to RCLK_c +)
+
+   Delay:               7.439ns  (22.5% logic, 77.5% route), 4 logic levels.
+
+ Constraint Details:
+
+      7.439ns physical path delay SLICE_1 to SLICE_26 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 3.280ns) by 4.159ns
+
+ Physical Path Details:
+
+      Data path SLICE_1 to SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C5D.CLK to       R3C5D.Q1 SLICE_1 (from RCLK_c)
+ROUTE         3     1.179       R3C5D.Q1 to       R3C2D.D1 FS_15
+CTOF_DEL    ---     0.371       R3C2D.D1 to       R3C2D.F1 SLICE_94
+ROUTE         3     1.471       R3C2D.F1 to       R4C5C.C0 n2272
+CTOF_DEL    ---     0.371       R4C5C.C0 to       R4C5C.F0 SLICE_75
+ROUTE         2     0.513       R4C5C.F0 to       R4C5C.C1 n2214
+CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_75
+ROUTE         1     2.603       R4C5C.F1 to       R9C9B.CE RCLK_c_enable_12 (to RCLK_c)
+                  --------
+                    7.439   (22.5% logic, 77.5% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R3C5D.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R9C9B.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+Warning: 116.198MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
+            106 items scored, 95 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 4.911ns (weighted slack = -9.822ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               8.437ns  (28.6% logic, 71.4% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.437ns physical path delay SLICE_99 to SLICE_14 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.638ns LSR_SET requirement (totaling 3.526ns) by 4.911ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_99 (from PHI2_c)
+ROUTE         1     2.159       R2C2A.Q1 to       R7C9A.D0 Bank_7
+CTOF_DEL    ---     0.371       R7C9A.D0 to       R7C9A.F0 SLICE_97
+ROUTE         1     1.026       R7C9A.F0 to       R5C9C.A0 n2314
+CTOF_DEL    ---     0.371       R5C9C.A0 to       R5C9C.F0 SLICE_81
+ROUTE         1     0.304       R5C9C.F0 to       R5C9D.D1 n26
+CTOF_DEL    ---     0.371       R5C9D.D1 to       R5C9D.F1 SLICE_18
+ROUTE         8     0.947       R5C9D.F1 to       R6C9B.C0 n1326
+CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_89
+ROUTE         1     0.497       R6C9B.F0 to       R6C9D.C0 n1280
+CTOF_DEL    ---     0.371       R6C9D.C0 to       R6C9D.F0 SLICE_79
+ROUTE         2     1.089       R6C9D.F0 to      R6C7A.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    8.437   (28.6% logic, 71.4% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R2C2A.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R6C7A.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.644ns (weighted slack = -9.288ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_412  (to PHI2_c -)
+                   FF                        CmdUFMCLK_413
+
+   Delay:               8.543ns  (28.3% logic, 71.7% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.543ns physical path delay SLICE_99 to SLICE_81 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 3.899ns) by 4.644ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_99 (from PHI2_c)
+ROUTE         1     2.159       R2C2A.Q1 to       R7C9A.D0 Bank_7
+CTOF_DEL    ---     0.371       R7C9A.D0 to       R7C9A.F0 SLICE_97
+ROUTE         1     1.026       R7C9A.F0 to       R5C9C.A0 n2314
+CTOF_DEL    ---     0.371       R5C9C.A0 to       R5C9C.F0 SLICE_81
+ROUTE         1     0.304       R5C9C.F0 to       R5C9D.D1 n26
+CTOF_DEL    ---     0.371       R5C9D.D1 to       R5C9D.F1 SLICE_18
+ROUTE         8     0.945       R5C9D.F1 to       R7C9D.C0 n1326
+CTOF_DEL    ---     0.371       R7C9D.C0 to       R7C9D.F0 SLICE_82
+ROUTE         2     0.513       R7C9D.F0 to       R7C9C.C1 n2460
+CTOF_DEL    ---     0.371       R7C9C.C1 to       R7C9C.F1 SLICE_83
+ROUTE         2     1.181       R7C9C.F1 to       R5C9C.CE PHI2_N_120_enable_6 (to PHI2_c)
+                  --------
+                    8.543   (28.3% logic, 71.7% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R2C2A.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R5C9C.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.644ns (weighted slack = -9.288ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI_414  (to PHI2_c -)
+
+   Delay:               8.543ns  (28.3% logic, 71.7% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.543ns physical path delay SLICE_99 to SLICE_93 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 3.899ns) by 4.644ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_99 (from PHI2_c)
+ROUTE         1     2.159       R2C2A.Q1 to       R7C9A.D0 Bank_7
+CTOF_DEL    ---     0.371       R7C9A.D0 to       R7C9A.F0 SLICE_97
+ROUTE         1     1.026       R7C9A.F0 to       R5C9C.A0 n2314
+CTOF_DEL    ---     0.371       R5C9C.A0 to       R5C9C.F0 SLICE_81
+ROUTE         1     0.304       R5C9C.F0 to       R5C9D.D1 n26
+CTOF_DEL    ---     0.371       R5C9D.D1 to       R5C9D.F1 SLICE_18
+ROUTE         8     0.945       R5C9D.F1 to       R7C9D.C0 n1326
+CTOF_DEL    ---     0.371       R7C9D.C0 to       R7C9D.F0 SLICE_82
+ROUTE         2     0.513       R7C9D.F0 to       R7C9C.C1 n2460
+CTOF_DEL    ---     0.371       R7C9C.C1 to       R7C9C.F1 SLICE_83
+ROUTE         2     1.181       R7C9C.F1 to      R10C9A.CE PHI2_N_120_enable_6 (to PHI2_c)
+                  --------
+                    8.543   (28.3% logic, 71.7% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R2C2A.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to     R10C9A.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.536ns (weighted slack = -9.072ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               8.435ns  (28.6% logic, 71.4% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.435ns physical path delay SLICE_99 to SLICE_18 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 3.899ns) by 4.536ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_99 (from PHI2_c)
+ROUTE         1     2.159       R2C2A.Q1 to       R7C9A.D0 Bank_7
+CTOF_DEL    ---     0.371       R7C9A.D0 to       R7C9A.F0 SLICE_97
+ROUTE         1     1.026       R7C9A.F0 to       R5C9C.A0 n2314
+CTOF_DEL    ---     0.371       R5C9C.A0 to       R5C9C.F0 SLICE_81
+ROUTE         1     0.304       R5C9C.F0 to       R5C9D.D1 n26
+CTOF_DEL    ---     0.371       R5C9D.D1 to       R5C9D.F1 SLICE_18
+ROUTE         8     0.945       R5C9D.F1 to       R7C9D.C0 n1326
+CTOF_DEL    ---     0.371       R7C9D.C0 to       R7C9D.F0 SLICE_82
+ROUTE         2     0.513       R7C9D.F0 to       R7C9D.C1 n2460
+CTOF_DEL    ---     0.371       R7C9D.C1 to       R7C9D.F1 SLICE_82
+ROUTE         1     1.073       R7C9D.F1 to       R5C9D.CE PHI2_N_120_enable_7 (to PHI2_c)
+                  --------
+                    8.435   (28.6% logic, 71.4% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R2C2A.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.485ns (weighted slack = -8.970ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        ADSubmitted_407  (to PHI2_c -)
+
+   Delay:               8.011ns  (30.1% logic, 69.9% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.011ns physical path delay SLICE_99 to SLICE_9 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.638ns LSR_SET requirement (totaling 3.526ns) by 4.485ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_99 (from PHI2_c)
+ROUTE         1     2.159       R2C2A.Q1 to       R7C9A.D0 Bank_7
+CTOF_DEL    ---     0.371       R7C9A.D0 to       R7C9A.F0 SLICE_97
+ROUTE         1     1.026       R7C9A.F0 to       R5C9C.A0 n2314
+CTOF_DEL    ---     0.371       R5C9C.A0 to       R5C9C.F0 SLICE_81
+ROUTE         1     0.304       R5C9C.F0 to       R5C9D.D1 n26
+CTOF_DEL    ---     0.371       R5C9D.D1 to       R5C9D.F1 SLICE_18
+ROUTE         8     0.947       R5C9D.F1 to       R6C9B.C0 n1326
+CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_89
+ROUTE         1     0.497       R6C9B.F0 to       R6C9D.C0 n1280
+CTOF_DEL    ---     0.371       R6C9D.C0 to       R6C9D.F0 SLICE_79
+ROUTE         2     0.663       R6C9D.F0 to      R6C9C.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    8.011   (30.1% logic, 69.9% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R2C2A.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R6C9C.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.400ns (weighted slack = -8.800ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdSubmitted_411  (to PHI2_c -)
+
+   Delay:               8.299ns  (29.1% logic, 70.9% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.299ns physical path delay SLICE_99 to SLICE_19 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 3.899ns) by 4.400ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_99 (from PHI2_c)
+ROUTE         1     2.159       R2C2A.Q1 to       R7C9A.D0 Bank_7
+CTOF_DEL    ---     0.371       R7C9A.D0 to       R7C9A.F0 SLICE_97
+ROUTE         1     1.026       R7C9A.F0 to       R5C9C.A0 n2314
+CTOF_DEL    ---     0.371       R5C9C.A0 to       R5C9C.F0 SLICE_81
+ROUTE         1     0.304       R5C9C.F0 to       R5C9D.D1 n26
+CTOF_DEL    ---     0.371       R5C9D.D1 to       R5C9D.F1 SLICE_18
+ROUTE         8     0.680       R5C9D.F1 to       R5C9B.D1 n1326
+CTOF_DEL    ---     0.371       R5C9B.D1 to       R5C9B.F1 SLICE_76
+ROUTE         2     1.068       R5C9B.F1 to       R5C7C.D0 n2458
+CTOF_DEL    ---     0.371       R5C7C.D0 to       R5C7C.F0 SLICE_91
+ROUTE         1     0.647       R5C7C.F0 to       R5C7D.CE PHI2_N_120_enable_5 (to PHI2_c)
+                  --------
+                    8.299   (29.1% logic, 70.9% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R2C2A.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R5C7D.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.271ns (weighted slack = -8.542ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        Cmdn8MEGEN_410  (to PHI2_c -)
+
+   Delay:               8.170ns  (29.6% logic, 70.4% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.170ns physical path delay SLICE_99 to SLICE_23 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 3.899ns) by 4.271ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_99 (from PHI2_c)
+ROUTE         1     2.159       R2C2A.Q1 to       R7C9A.D0 Bank_7
+CTOF_DEL    ---     0.371       R7C9A.D0 to       R7C9A.F0 SLICE_97
+ROUTE         1     1.026       R7C9A.F0 to       R5C9C.A0 n2314
+CTOF_DEL    ---     0.371       R5C9C.A0 to       R5C9C.F0 SLICE_81
+ROUTE         1     0.304       R5C9C.F0 to       R5C9D.D1 n26
+CTOF_DEL    ---     0.371       R5C9D.D1 to       R5C9D.F1 SLICE_18
+ROUTE         8     0.680       R5C9D.F1 to       R5C9B.D1 n1326
+CTOF_DEL    ---     0.371       R5C9B.D1 to       R5C9B.F1 SLICE_76
+ROUTE         2     0.513       R5C9B.F1 to       R5C9B.C0 n2458
+CTOF_DEL    ---     0.371       R5C9B.C0 to       R5C9B.F0 SLICE_76
+ROUTE         1     1.073       R5C9B.F0 to       R5C8B.CE PHI2_N_120_enable_4 (to PHI2_c)
+                  --------
+                    8.170   (29.6% logic, 70.4% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R2C2A.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R5C8B.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.250ns (weighted slack = -8.500ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i1  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               7.776ns  (26.3% logic, 73.7% route), 5 logic levels.
+
+ Constraint Details:
+
+      7.776ns physical path delay SLICE_88 to SLICE_14 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.638ns LSR_SET requirement (totaling 3.526ns) by 4.250ns
+
+ Physical Path Details:
+
+      Data path SLICE_88 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R9C3B.CLK to       R9C3B.Q1 SLICE_88 (from PHI2_c)
+ROUTE         1     1.616       R9C3B.Q1 to       R9C9A.D0 Bank_1
+CTOF_DEL    ---     0.371       R9C9A.D0 to       R9C9A.F0 SLICE_96
+ROUTE         1     1.583       R9C9A.F0 to       R5C9D.A1 n2316
+CTOF_DEL    ---     0.371       R5C9D.A1 to       R5C9D.F1 SLICE_18
+ROUTE         8     0.947       R5C9D.F1 to       R6C9B.C0 n1326
+CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_89
+ROUTE         1     0.497       R6C9B.F0 to       R6C9D.C0 n1280
+CTOF_DEL    ---     0.371       R6C9D.C0 to       R6C9D.F0 SLICE_79
+ROUTE         2     1.089       R6C9D.F0 to      R6C7A.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    7.776   (26.3% logic, 73.7% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R9C3B.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R6C7A.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.196ns (weighted slack = -8.392ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               7.722ns  (31.3% logic, 68.7% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.722ns physical path delay SLICE_88 to SLICE_14 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.638ns LSR_SET requirement (totaling 3.526ns) by 4.196ns
+
+ Physical Path Details:
+
+      Data path SLICE_88 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R9C3B.CLK to       R9C3B.Q0 SLICE_88 (from PHI2_c)
+ROUTE         1     1.444       R9C3B.Q0 to       R7C9A.C0 Bank_0
+CTOF_DEL    ---     0.371       R7C9A.C0 to       R7C9A.F0 SLICE_97
+ROUTE         1     1.026       R7C9A.F0 to       R5C9C.A0 n2314
+CTOF_DEL    ---     0.371       R5C9C.A0 to       R5C9C.F0 SLICE_81
+ROUTE         1     0.304       R5C9C.F0 to       R5C9D.D1 n26
+CTOF_DEL    ---     0.371       R5C9D.D1 to       R5C9D.F1 SLICE_18
+ROUTE         8     0.947       R5C9D.F1 to       R6C9B.C0 n1326
+CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_89
+ROUTE         1     0.497       R6C9B.F0 to       R6C9D.C0 n1280
+CTOF_DEL    ---     0.371       R6C9D.C0 to       R6C9D.F0 SLICE_79
+ROUTE         2     1.089       R6C9D.F0 to      R6C7A.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    7.722   (31.3% logic, 68.7% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R9C3B.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R6C7A.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.179ns (weighted slack = -8.358ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               7.705ns  (31.3% logic, 68.7% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.705ns physical path delay SLICE_99 to SLICE_14 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.638ns LSR_SET requirement (totaling 3.526ns) by 4.179ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_99 (from PHI2_c)
+ROUTE         1     1.956       R2C2A.Q0 to       R5C9C.C1 Bank_6
+CTOF_DEL    ---     0.371       R5C9C.C1 to       R5C9C.F1 SLICE_81
+ROUTE         1     0.497       R5C9C.F1 to       R5C9C.C0 n2278
+CTOF_DEL    ---     0.371       R5C9C.C0 to       R5C9C.F0 SLICE_81
+ROUTE         1     0.304       R5C9C.F0 to       R5C9D.D1 n26
+CTOF_DEL    ---     0.371       R5C9D.D1 to       R5C9D.F1 SLICE_18
+ROUTE         8     0.947       R5C9D.F1 to       R6C9B.C0 n1326
+CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_89
+ROUTE         1     0.497       R6C9B.F0 to       R6C9D.C0 n1280
+CTOF_DEL    ---     0.371       R6C9D.C0 to       R6C9D.F0 SLICE_79
+ROUTE         2     1.089       R6C9D.F0 to      R6C7A.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    7.705   (31.3% logic, 68.7% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R2C2A.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R6C7A.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+Warning:  55.096MHz is the maximum frequency for this preference.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "RCLK_c" 283.768000 MHz ; |  283.768 MHz|  116.198 MHz|   4 *
+                                        |             |             |
+FREQUENCY NET "PHI2_c" 120.077000 MHz ; |  120.077 MHz|   55.096 MHz|   6 *
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+2 preferences(marked by "*" above) not met.
+
+----------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+----------------------------------------------------------------------------
+n1326                                   |       8|      94|     28.66%
+                                        |        |        |
+n26                                     |       1|      70|     21.34%
+                                        |        |        |
+----------------------------------------------------------------------------
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
+   Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 328  Score: 909228
+Cumulative negative slack: 648187
+
+Constraints cover 489 paths, 2 nets, and 415 connections (62.69% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
+Tue Aug 15 05:03:30 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
+Design file:     ram2gs_lcmxo640c_impl1.ncd
+Preference file: ram2gs_lcmxo640c_impl1.prf
+Device,speed:    LCMXO640C,m
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "RCLK_c" 283.768000 MHz (0 errors)
    •             383 items scored, 0 timing errors detected.
+
+
  • FREQUENCY NET "PHI2_c" 120.077000 MHz (0 errors)
    •             106 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
+            383 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.273ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i4  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i5  (to RCLK_c +)
+
+   Delay:               0.256ns  (49.2% logic, 50.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.256ns physical path delay SLICE_100 to SLICE_100 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.273ns
+
+ Physical Path Details:
+
+      Data path SLICE_100 to SLICE_100:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R4C8B.CLK to       R4C8B.Q0 SLICE_100 (from RCLK_c)
+ROUTE         1     0.130       R4C8B.Q0 to       R4C8B.M1 n736 (to RCLK_c)
+                  --------
+                    0.256   (49.2% logic, 50.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_100:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R4C8B.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_100:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R4C8B.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.273ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i8  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i9  (to RCLK_c +)
+
+   Delay:               0.256ns  (49.2% logic, 50.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.256ns physical path delay SLICE_76 to SLICE_76 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.273ns
+
+ Physical Path Details:
+
+      Data path SLICE_76 to SLICE_76:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R5C9B.CLK to       R5C9B.Q0 SLICE_76 (from RCLK_c)
+ROUTE         1     0.130       R5C9B.Q0 to       R5C9B.M1 n732 (to RCLK_c)
+                  --------
+                    0.256   (49.2% logic, 50.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_76:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R5C9B.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_76:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R5C9B.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.273ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i12  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i13  (to RCLK_c +)
+
+   Delay:               0.256ns  (49.2% logic, 50.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.256ns physical path delay SLICE_77 to SLICE_77 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.273ns
+
+ Physical Path Details:
+
+      Data path SLICE_77 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R3C6D.CLK to       R3C6D.Q0 SLICE_77 (from RCLK_c)
+ROUTE         1     0.130       R3C6D.Q0 to       R3C6D.M1 n728 (to RCLK_c)
+                  --------
+                    0.256   (49.2% logic, 50.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R3C6D.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R3C6D.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.273ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i14  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i15  (to RCLK_c +)
+
+   Delay:               0.256ns  (49.2% logic, 50.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.256ns physical path delay SLICE_80 to SLICE_80 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.273ns
+
+ Physical Path Details:
+
+      Data path SLICE_80 to SLICE_80:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R3C8C.CLK to       R3C8C.Q0 SLICE_80 (from RCLK_c)
+ROUTE         1     0.130       R3C8C.Q0 to       R3C8C.M1 n726 (to RCLK_c)
+                  --------
+                    0.256   (49.2% logic, 50.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_80:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R3C8C.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_80:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R3C8C.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.273ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i10  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i11  (to RCLK_c +)
+
+   Delay:               0.256ns  (49.2% logic, 50.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.256ns physical path delay SLICE_82 to SLICE_82 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.273ns
+
+ Physical Path Details:
+
+      Data path SLICE_82 to SLICE_82:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R7C9D.CLK to       R7C9D.Q0 SLICE_82 (from RCLK_c)
+ROUTE         1     0.130       R7C9D.Q0 to       R7C9D.M1 n730 (to RCLK_c)
+                  --------
+                    0.256   (49.2% logic, 50.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_82:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R7C9D.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_82:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R7C9D.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.273ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i2  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i3  (to RCLK_c +)
+
+   Delay:               0.256ns  (49.2% logic, 50.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.256ns physical path delay SLICE_84 to SLICE_84 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.273ns
+
+ Physical Path Details:
+
+      Data path SLICE_84 to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R5C8C.CLK to       R5C8C.Q0 SLICE_84 (from RCLK_c)
+ROUTE         1     0.130       R5C8C.Q0 to       R5C8C.M1 n738 (to RCLK_c)
+                  --------
+                    0.256   (49.2% logic, 50.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R5C8C.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R5C8C.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.273ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i6  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i7  (to RCLK_c +)
+
+   Delay:               0.256ns  (49.2% logic, 50.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.256ns physical path delay SLICE_86 to SLICE_86 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.273ns
+
+ Physical Path Details:
+
+      Data path SLICE_86 to SLICE_86:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R5C8D.CLK to       R5C8D.Q0 SLICE_86 (from RCLK_c)
+ROUTE         1     0.130       R5C8D.Q0 to       R5C8D.M1 n734 (to RCLK_c)
+                  --------
+                    0.256   (49.2% logic, 50.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_86:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R5C8D.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_86:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R5C8D.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.277ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i0  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i1  (to RCLK_c +)
+
+   Delay:               0.260ns  (48.5% logic, 51.5% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay SLICE_87 to SLICE_87 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.277ns
+
+ Physical Path Details:
+
+      Data path SLICE_87 to SLICE_87:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R4C5A.CLK to       R4C5A.Q0 SLICE_87 (from RCLK_c)
+ROUTE         6     0.134       R4C5A.Q0 to       R4C5A.M1 nRCS_N_139 (to RCLK_c)
+                  --------
+                    0.260   (48.5% logic, 51.5% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_87:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R4C5A.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_87:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R4C5A.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.290ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RASr2_380  (from RCLK_c +)
+   Destination:    FF         Data in        RASr3_381  (to RCLK_c +)
+
+   Delay:               0.273ns  (46.2% logic, 53.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.273ns physical path delay SLICE_74 to SLICE_74 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.290ns
+
+ Physical Path Details:
+
+      Data path SLICE_74 to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R4C7A.CLK to       R4C7A.Q0 SLICE_74 (from RCLK_c)
+ROUTE        14     0.147       R4C7A.Q0 to       R4C7A.M1 RASr2 (to RCLK_c)
+                  --------
+                    0.273   (46.2% logic, 53.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R4C7A.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R4C7A.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.301ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i15  (from RCLK_c +)
+   Destination:    FF         Data in        FS_610_add_4_16  (to RCLK_c +)
+                   FF                        FS_610__i15
+                   FF                        FS_610__i14
+
+   Delay:               0.257ns  (49.0% logic, 51.0% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.257ns physical path delay SLICE_1 to SLICE_1 meets
+     -0.044ns LUT_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.044ns) by 0.301ns
+
+ Physical Path Details:
+
+      Data path SLICE_1 to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R3C5D.CLK to       R3C5D.Q1 SLICE_1 (from RCLK_c)
+ROUTE         3     0.131       R3C5D.Q1 to       R3C5D.A1 FS_15 (to RCLK_c)
+                  --------
+                    0.257   (49.0% logic, 51.0% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R3C5D.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R3C5D.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
+            106 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.361ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_406  (from PHI2_c -)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               0.342ns  (61.7% logic, 38.3% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.342ns physical path delay SLICE_14 to SLICE_14 meets
+     -0.019ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.361ns
+
+ Physical Path Details:
+
+      Data path SLICE_14 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R6C7A.CLK to       R6C7A.Q0 SLICE_14 (from PHI2_c)
+ROUTE         2     0.131       R6C7A.Q0 to       R6C7A.A0 C1Submitted
+CTOF_DEL    ---     0.074       R6C7A.A0 to       R6C7A.F0 SLICE_14
+ROUTE         1     0.000       R6C7A.F0 to      R6C7A.DI0 n6_adj_3 (to PHI2_c)
+                  --------
+                    0.342   (61.7% logic, 38.3% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R6C7A.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R6C7A.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.361ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_407  (from PHI2_c -)
+   Destination:    FF         Data in        ADSubmitted_407  (to PHI2_c -)
+
+   Delay:               0.342ns  (61.7% logic, 38.3% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.342ns physical path delay SLICE_9 to SLICE_9 meets
+     -0.019ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.361ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R6C9C.CLK to       R6C9C.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2     0.131       R6C9C.Q0 to       R6C9C.A0 ADSubmitted
+CTOF_DEL    ---     0.074       R6C9C.A0 to       R6C9C.F0 SLICE_9
+ROUTE         1     0.000       R6C9C.F0 to      R6C9C.DI0 n1413 (to PHI2_c)
+                  --------
+                    0.342   (61.7% logic, 38.3% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R6C9C.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R6C9C.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.585ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        XOR8MEG_408  (to PHI2_c -)
+
+   Delay:               0.562ns  (37.5% logic, 62.5% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.562ns physical path delay SLICE_18 to SLICE_49 meets
+     -0.023ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 0.585ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_49:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R5C9D.CLK to       R5C9D.Q0 SLICE_18 (from PHI2_c)
+ROUTE         2     0.221       R5C9D.Q0 to       R5C8C.B1 CmdEnable
+CTOF_DEL    ---     0.074       R5C8C.B1 to       R5C8C.F1 SLICE_84
+ROUTE         1     0.130       R5C8C.F1 to       R5C8A.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    0.562   (37.5% logic, 62.5% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_49:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R5C8A.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.885ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMCS_412  (to PHI2_c -)
+                   FF                        CmdUFMCLK_413
+
+   Delay:               0.862ns  (33.1% logic, 66.9% route), 3 logic levels.
+
+ Constraint Details:
+
+      0.862ns physical path delay SLICE_18 to SLICE_81 meets
+     -0.023ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 0.885ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R5C9D.CLK to       R5C9D.Q0 SLICE_18 (from PHI2_c)
+ROUTE         2     0.145       R5C9D.Q0 to       R7C9C.D0 CmdEnable
+CTOF_DEL    ---     0.074       R7C9C.D0 to       R7C9C.F0 SLICE_83
+ROUTE         2     0.196       R7C9C.F0 to       R7C9C.A1 n10
+CTOF_DEL    ---     0.074       R7C9C.A1 to       R7C9C.F1 SLICE_83
+ROUTE         2     0.236       R7C9C.F1 to       R5C9C.CE PHI2_N_120_enable_6 (to PHI2_c)
+                  --------
+                    0.862   (33.1% logic, 66.9% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R5C9C.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.885ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMSDI_414  (to PHI2_c -)
+
+   Delay:               0.862ns  (33.1% logic, 66.9% route), 3 logic levels.
+
+ Constraint Details:
+
+      0.862ns physical path delay SLICE_18 to SLICE_93 meets
+     -0.023ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 0.885ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R5C9D.CLK to       R5C9D.Q0 SLICE_18 (from PHI2_c)
+ROUTE         2     0.145       R5C9D.Q0 to       R7C9C.D0 CmdEnable
+CTOF_DEL    ---     0.074       R7C9C.D0 to       R7C9C.F0 SLICE_83
+ROUTE         2     0.196       R7C9C.F0 to       R7C9C.A1 n10
+CTOF_DEL    ---     0.074       R7C9C.A1 to       R7C9C.F1 SLICE_83
+ROUTE         2     0.236       R7C9C.F1 to      R10C9A.CE PHI2_N_120_enable_6 (to PHI2_c)
+                  --------
+                    0.862   (33.1% logic, 66.9% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to     R10C9A.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.146ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        Cmdn8MEGEN_410  (to PHI2_c -)
+
+   Delay:               1.123ns  (32.0% logic, 68.0% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.123ns physical path delay SLICE_18 to SLICE_23 meets
+     -0.023ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 1.146ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R5C9D.CLK to       R5C9D.Q0 SLICE_18 (from PHI2_c)
+ROUTE         2     0.145       R5C9D.Q0 to       R7C9C.D0 CmdEnable
+CTOF_DEL    ---     0.074       R7C9C.D0 to       R7C9C.F0 SLICE_83
+ROUTE         2     0.300       R7C9C.F0 to       R5C9B.A1 n10
+CTOF_DEL    ---     0.074       R5C9B.A1 to       R5C9B.F1 SLICE_76
+ROUTE         2     0.103       R5C9B.F1 to       R5C9B.C0 n2458
+CTOF_DEL    ---     0.074       R5C9B.C0 to       R5C9B.F0 SLICE_76
+ROUTE         1     0.216       R5C9B.F0 to       R5C8B.CE PHI2_N_120_enable_4 (to PHI2_c)
+                  --------
+                    1.123   (32.0% logic, 68.0% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R5C8B.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.173ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        CmdSubmitted_411  (to PHI2_c -)
+
+   Delay:               1.150ns  (31.2% logic, 68.8% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.150ns physical path delay SLICE_18 to SLICE_19 meets
+     -0.023ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 1.173ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R5C9D.CLK to       R5C9D.Q0 SLICE_18 (from PHI2_c)
+ROUTE         2     0.145       R5C9D.Q0 to       R7C9C.D0 CmdEnable
+CTOF_DEL    ---     0.074       R7C9C.D0 to       R7C9C.F0 SLICE_83
+ROUTE         2     0.300       R7C9C.F0 to       R5C9B.A1 n10
+CTOF_DEL    ---     0.074       R5C9B.A1 to       R5C9B.F1 SLICE_76
+ROUTE         2     0.216       R5C9B.F1 to       R5C7C.D0 n2458
+CTOF_DEL    ---     0.074       R5C7C.D0 to       R5C7C.F0 SLICE_91
+ROUTE         1     0.130       R5C7C.F0 to       R5C7D.CE PHI2_N_120_enable_5 (to PHI2_c)
+                  --------
+                    1.150   (31.2% logic, 68.8% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R5C7D.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.573ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_407  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               1.550ns  (26.5% logic, 73.5% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.550ns physical path delay SLICE_9 to SLICE_18 meets
+     -0.023ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 1.573ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R6C9C.CLK to       R6C9C.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2     0.310       R6C9C.Q0 to       R5C7A.A0 ADSubmitted
+CTOOFX_DEL  ---     0.125       R5C7A.A0 to     R5C7A.OFX0 i26/SLICE_71
+ROUTE         1     0.296     R5C7A.OFX0 to       R4C9A.A0 n13_adj_2
+CTOF_DEL    ---     0.074       R4C9A.A0 to       R4C9A.F0 SLICE_105
+ROUTE         1     0.318       R4C9A.F0 to       R7C9D.B1 n14
+CTOF_DEL    ---     0.074       R7C9D.B1 to       R7C9D.F1 SLICE_82
+ROUTE         1     0.216       R7C9D.F1 to       R5C9D.CE PHI2_N_120_enable_7 (to PHI2_c)
+                  --------
+                    1.550   (26.5% logic, 73.5% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R6C9C.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.708ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_406  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               1.685ns  (28.5% logic, 71.5% route), 5 logic levels.
+
+ Constraint Details:
+
+      1.685ns physical path delay SLICE_14 to SLICE_18 meets
+     -0.023ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 1.708ns
+
+ Physical Path Details:
+
+      Data path SLICE_14 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R6C7A.CLK to       R6C7A.Q0 SLICE_14 (from PHI2_c)
+ROUTE         2     0.196       R6C7A.Q0 to       R6C7A.A1 C1Submitted
+CTOF_DEL    ---     0.074       R6C7A.A1 to       R6C7A.F1 SLICE_14
+ROUTE         1     0.179       R6C7A.F1 to       R5C7A.C1 n2284
+CTOOFX_DEL  ---     0.121       R5C7A.C1 to     R5C7A.OFX0 i26/SLICE_71
+ROUTE         1     0.296     R5C7A.OFX0 to       R4C9A.A0 n13_adj_2
+CTOF_DEL    ---     0.074       R4C9A.A0 to       R4C9A.F0 SLICE_105
+ROUTE         1     0.318       R4C9A.F0 to       R7C9D.B1 n14
+CTOF_DEL    ---     0.074       R7C9D.B1 to       R7C9D.F1 SLICE_82
+ROUTE         1     0.216       R7C9D.F1 to       R5C9D.CE PHI2_N_120_enable_7 (to PHI2_c)
+                  --------
+                    1.685   (28.5% logic, 71.5% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R6C7A.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.684ns (weighted slack = 9.368ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              XOR8MEG_408  (from PHI2_c -)
+   Destination:    FF         Data in        RA11_385  (to PHI2_c +)
+
+   Delay:               0.512ns  (41.2% logic, 58.8% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.512ns physical path delay SLICE_49 to SLICE_32 meets
+     -0.008ns DIN_HLD and
+     -4.164ns delay constraint less
+      0.000ns skew requirement (totaling -4.172ns) by 4.684ns
+
+ Physical Path Details:
+
+      Data path SLICE_49 to SLICE_32:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R5C8A.CLK to       R5C8A.Q0 SLICE_49 (from PHI2_c)
+ROUTE         1     0.301       R5C8A.Q0 to       R2C9A.C0 XOR8MEG
+CTOF_DEL    ---     0.074       R2C9A.C0 to       R2C9A.F0 SLICE_32
+ROUTE         1     0.000       R2C9A.F0 to      R2C9A.DI0 RA11_N_184 (to PHI2_c)
+                  --------
+                    0.512   (41.2% logic, 58.8% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_49:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R5C8A.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_32:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R2C9A.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "RCLK_c" 283.768000 MHz ; |     0.000 ns|     0.273 ns|   1  
+                                        |             |             |
+FREQUENCY NET "PHI2_c" 120.077000 MHz ; |     0.000 ns|     0.361 ns|   2  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
+   Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 489 paths, 2 nets, and 415 connections (62.69% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 328 (setup), 0 (hold)
+Score: 909228 (setup), 0 (hold)
+Cumulative negative slack: 648187 (648187+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_drc.log b/CPLD/LCMXO640C/impl1/RAM2GS_drc.log new file mode 100644 index 0000000..60696e6 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_drc.log @@ -0,0 +1,15 @@ +Results of NGD DRC are available in RAM2GS_drc.log. +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... + + +Running DRC... + +DRC complete with no errors or warnings + +Design Results: + 318 blocks expanded +completed the first expansion +All blocks are expanded and NGD expansion is successful. +Writing NGD file RAM2GS_LCMXO640C_impl1.ngd. diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_lse.twr b/CPLD/LCMXO640C/impl1/RAM2GS_lse.twr new file mode 100644 index 0000000..4779f7d --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_lse.twr @@ -0,0 +1,291 @@ +-------------------------------------------------------------------------------- +Lattice Synthesis Timing Report, Version +Tue Aug 15 05:03:22 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Design: RAM2GS +Constraint file: +Report level: verbose report, limited to 3 items per constraint +-------------------------------------------------------------------------------- + + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c] + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c] + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c] + 115 items scored, 112 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path violates requirements by 8.575ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK Bank_i3 (from PHI2_c +) + Destination: FD1P3AX SP CmdUFMCS_412 (to PHI2_c -) + + Delay: 10.811ns (23.7% logic, 76.3% route), 6 logic levels. + + Constraint Details: + + 10.811ns data_path Bank_i3 to CmdUFMCS_412 violates + 2.500ns delay constraint less + 0.264ns LCE_S requirement (totaling 2.236ns) by 8.575ns + + Path Details: Bank_i3 to CmdUFMCS_412 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q Bank_i3 (from PHI2_c) +Route 1 e 1.220 Bank[3] +LUT4 --- 0.390 B to Z i1982_2_lut +Route 1 e 1.220 n2278 +LUT4 --- 0.390 C to Z i12_4_lut +Route 1 e 1.220 n26 +LUT4 --- 0.390 B to Z i13_4_lut +Route 8 e 1.719 n1326 +LUT4 --- 0.390 B to Z i1990_2_lut_rep_17 +Route 2 e 1.386 n2460 +LUT4 --- 0.390 C to Z i1_2_lut_4_lut +Route 3 e 1.483 PHI2_N_120_enable_6 + -------- + 10.811 (23.7% logic, 76.3% route), 6 logic levels. + + +Error: The following path violates requirements by 8.575ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK Bank_i3 (from PHI2_c +) + Destination: FD1P3AX SP CmdUFMSDI_414 (to PHI2_c -) + + Delay: 10.811ns (23.7% logic, 76.3% route), 6 logic levels. + + Constraint Details: + + 10.811ns data_path Bank_i3 to CmdUFMSDI_414 violates + 2.500ns delay constraint less + 0.264ns LCE_S requirement (totaling 2.236ns) by 8.575ns + + Path Details: Bank_i3 to CmdUFMSDI_414 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q Bank_i3 (from PHI2_c) +Route 1 e 1.220 Bank[3] +LUT4 --- 0.390 B to Z i1982_2_lut +Route 1 e 1.220 n2278 +LUT4 --- 0.390 C to Z i12_4_lut +Route 1 e 1.220 n26 +LUT4 --- 0.390 B to Z i13_4_lut +Route 8 e 1.719 n1326 +LUT4 --- 0.390 B to Z i1990_2_lut_rep_17 +Route 2 e 1.386 n2460 +LUT4 --- 0.390 C to Z i1_2_lut_4_lut +Route 3 e 1.483 PHI2_N_120_enable_6 + -------- + 10.811 (23.7% logic, 76.3% route), 6 logic levels. + + +Error: The following path violates requirements by 8.575ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK Bank_i3 (from PHI2_c +) + Destination: FD1P3AX SP CmdUFMCLK_413 (to PHI2_c -) + + Delay: 10.811ns (23.7% logic, 76.3% route), 6 logic levels. + + Constraint Details: + + 10.811ns data_path Bank_i3 to CmdUFMCLK_413 violates + 2.500ns delay constraint less + 0.264ns LCE_S requirement (totaling 2.236ns) by 8.575ns + + Path Details: Bank_i3 to CmdUFMCLK_413 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q Bank_i3 (from PHI2_c) +Route 1 e 1.220 Bank[3] +LUT4 --- 0.390 B to Z i1982_2_lut +Route 1 e 1.220 n2278 +LUT4 --- 0.390 C to Z i12_4_lut +Route 1 e 1.220 n26 +LUT4 --- 0.390 B to Z i13_4_lut +Route 8 e 1.719 n1326 +LUT4 --- 0.390 B to Z i1990_2_lut_rep_17 +Route 2 e 1.386 n2460 +LUT4 --- 0.390 C to Z i1_2_lut_4_lut +Route 3 e 1.483 PHI2_N_120_enable_6 + -------- + 10.811 (23.7% logic, 76.3% route), 6 logic levels. + +Warning: 11.075 ns is the maximum delay for this constraint. + + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c] + 357 items scored, 234 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path violates requirements by 4.364ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK FS_610__i13 (from RCLK_c +) + Destination: FD1P3AX D n8MEGEN_418 (to RCLK_c +) + + Delay: 9.182ns (23.7% logic, 76.3% route), 5 logic levels. + + Constraint Details: + + 9.182ns data_path FS_610__i13 to n8MEGEN_418 violates + 5.000ns delay constraint less + 0.182ns L_S requirement (totaling 4.818ns) by 4.364ns + + Path Details: FS_610__i13 to n8MEGEN_418 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q FS_610__i13 (from RCLK_c) +Route 3 e 1.603 FS[13] +LUT4 --- 0.390 A to Z i1976_2_lut +Route 3 e 1.483 n2272 +LUT4 --- 0.390 C to Z i5_3_lut_rep_21_4_lut +Route 3 e 1.483 n2464 +LUT4 --- 0.390 B to Z i1_2_lut_3_lut_adj_4 +Route 1 e 1.220 n1325 +LUT4 --- 0.390 D to Z n8MEGEN_I_14_4_lut +Route 1 e 1.220 n8MEGEN_N_91 + -------- + 9.182 (23.7% logic, 76.3% route), 5 logic levels. + + +Error: The following path violates requirements by 4.364ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK FS_610__i15 (from RCLK_c +) + Destination: FD1P3AX D n8MEGEN_418 (to RCLK_c +) + + Delay: 9.182ns (23.7% logic, 76.3% route), 5 logic levels. + + Constraint Details: + + 9.182ns data_path FS_610__i15 to n8MEGEN_418 violates + 5.000ns delay constraint less + 0.182ns L_S requirement (totaling 4.818ns) by 4.364ns + + Path Details: FS_610__i15 to n8MEGEN_418 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q FS_610__i15 (from RCLK_c) +Route 3 e 1.603 FS[15] +LUT4 --- 0.390 B to Z i1976_2_lut +Route 3 e 1.483 n2272 +LUT4 --- 0.390 C to Z i5_3_lut_rep_21_4_lut +Route 3 e 1.483 n2464 +LUT4 --- 0.390 B to Z i1_2_lut_3_lut_adj_4 +Route 1 e 1.220 n1325 +LUT4 --- 0.390 D to Z n8MEGEN_I_14_4_lut +Route 1 e 1.220 n8MEGEN_N_91 + -------- + 9.182 (23.7% logic, 76.3% route), 5 logic levels. + + +Error: The following path violates requirements by 4.349ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK FS_610__i13 (from RCLK_c +) + Destination: FD1P3AX SP n8MEGEN_418 (to RCLK_c +) + + Delay: 9.085ns (23.9% logic, 76.1% route), 5 logic levels. + + Constraint Details: + + 9.085ns data_path FS_610__i13 to n8MEGEN_418 violates + 5.000ns delay constraint less + 0.264ns LCE_S requirement (totaling 4.736ns) by 4.349ns + + Path Details: FS_610__i13 to n8MEGEN_418 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q FS_610__i13 (from RCLK_c) +Route 3 e 1.603 FS[13] +LUT4 --- 0.390 A to Z i1976_2_lut +Route 3 e 1.483 n2272 +LUT4 --- 0.390 C to Z i7_4_lut +Route 2 e 1.386 n2214 +LUT4 --- 0.390 B to Z i2_2_lut +Route 1 e 1.220 n7 +LUT4 --- 0.390 A to Z i17_4_lut +Route 1 e 1.220 RCLK_c_enable_11 + -------- + 9.085 (23.9% logic, 76.1% route), 5 logic levels. + +Warning: 9.364 ns is the maximum delay for this constraint. + + +Timing Report Summary +-------------- +-------------------------------------------------------------------------------- +Constraint | Constraint| Actual|Levels +-------------------------------------------------------------------------------- + | | | +create_clock -period 5.000000 -name | | | +clk3 [get_nets nCCAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk2 [get_nets nCRAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk1 [get_nets PHI2_c] | 5.000 ns| 22.150 ns| 6 * + | | | +create_clock -period 5.000000 -name | | | +clk0 [get_nets RCLK_c] | 5.000 ns| 9.364 ns| 5 * + | | | +-------------------------------------------------------------------------------- + + +2 constraints not met. + +-------------------------------------------------------------------------------- +Critical Nets | Loads| Errors| % of total +-------------------------------------------------------------------------------- +n1326 | 8| 104| 30.06% + | | | +n26 | 1| 78| 22.54% + | | | +RCLK_c_enable_23 | 16| 64| 18.50% + | | | +-------------------------------------------------------------------------------- + + +Timing summary: +--------------- + +Timing errors: 346 Score: 1874657 + +Constraints cover 476 paths, 187 nets, and 480 connections (64.3% coverage) + + +Peak memory: 53284864 bytes, TRCE: 1122304 bytes, DLYMAN: 167936 bytes +CPU_TIME_REPORT: 0 secs diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_lse_lsetwr.html b/CPLD/LCMXO640C/impl1/RAM2GS_lse_lsetwr.html new file mode 100644 index 0000000..d5f78c7 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_lse_lsetwr.html @@ -0,0 +1,356 @@ + +Lattice Synthesis Timing Report + + +
    Lattice Synthesis Timing Report
+--------------------------------------------------------------------------------
+Lattice Synthesis Timing Report, Version  
+Tue Aug 15 05:03:22 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design:     RAM2GS
+Constraint file:  
+Report level:    verbose report, limited to 3 items per constraint
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c]
+            115 items scored, 112 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 8.575ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i3  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdUFMCS_412  (to PHI2_c -)
+
+   Delay:                  10.811ns  (23.7% logic, 76.3% route), 6 logic levels.
+
+ Constraint Details:
+
+     10.811ns data_path Bank_i3 to CmdUFMCS_412 violates
+      2.500ns delay constraint less
+      0.264ns LCE_S requirement (totaling 2.236ns) by 8.575ns
+
+ Path Details: Bank_i3 to CmdUFMCS_412
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              Bank_i3 (from PHI2_c)
+Route         1   e 1.220                                  Bank[3]
+LUT4        ---     0.390              B to Z              i1982_2_lut
+Route         1   e 1.220                                  n2278
+LUT4        ---     0.390              C to Z              i12_4_lut
+Route         1   e 1.220                                  n26
+LUT4        ---     0.390              B to Z              i13_4_lut
+Route         8   e 1.719                                  n1326
+LUT4        ---     0.390              B to Z              i1990_2_lut_rep_17
+Route         2   e 1.386                                  n2460
+LUT4        ---     0.390              C to Z              i1_2_lut_4_lut
+Route         3   e 1.483                                  PHI2_N_120_enable_6
+                  --------
+                   10.811  (23.7% logic, 76.3% route), 6 logic levels.
+
+
+Error:  The following path violates requirements by 8.575ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i3  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdUFMSDI_414  (to PHI2_c -)
+
+   Delay:                  10.811ns  (23.7% logic, 76.3% route), 6 logic levels.
+
+ Constraint Details:
+
+     10.811ns data_path Bank_i3 to CmdUFMSDI_414 violates
+      2.500ns delay constraint less
+      0.264ns LCE_S requirement (totaling 2.236ns) by 8.575ns
+
+ Path Details: Bank_i3 to CmdUFMSDI_414
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              Bank_i3 (from PHI2_c)
+Route         1   e 1.220                                  Bank[3]
+LUT4        ---     0.390              B to Z              i1982_2_lut
+Route         1   e 1.220                                  n2278
+LUT4        ---     0.390              C to Z              i12_4_lut
+Route         1   e 1.220                                  n26
+LUT4        ---     0.390              B to Z              i13_4_lut
+Route         8   e 1.719                                  n1326
+LUT4        ---     0.390              B to Z              i1990_2_lut_rep_17
+Route         2   e 1.386                                  n2460
+LUT4        ---     0.390              C to Z              i1_2_lut_4_lut
+Route         3   e 1.483                                  PHI2_N_120_enable_6
+                  --------
+                   10.811  (23.7% logic, 76.3% route), 6 logic levels.
+
+
+Error:  The following path violates requirements by 8.575ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i3  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdUFMCLK_413  (to PHI2_c -)
+
+   Delay:                  10.811ns  (23.7% logic, 76.3% route), 6 logic levels.
+
+ Constraint Details:
+
+     10.811ns data_path Bank_i3 to CmdUFMCLK_413 violates
+      2.500ns delay constraint less
+      0.264ns LCE_S requirement (totaling 2.236ns) by 8.575ns
+
+ Path Details: Bank_i3 to CmdUFMCLK_413
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              Bank_i3 (from PHI2_c)
+Route         1   e 1.220                                  Bank[3]
+LUT4        ---     0.390              B to Z              i1982_2_lut
+Route         1   e 1.220                                  n2278
+LUT4        ---     0.390              C to Z              i12_4_lut
+Route         1   e 1.220                                  n26
+LUT4        ---     0.390              B to Z              i13_4_lut
+Route         8   e 1.719                                  n1326
+LUT4        ---     0.390              B to Z              i1990_2_lut_rep_17
+Route         2   e 1.386                                  n2460
+LUT4        ---     0.390              C to Z              i1_2_lut_4_lut
+Route         3   e 1.483                                  PHI2_N_120_enable_6
+                  --------
+                   10.811  (23.7% logic, 76.3% route), 6 logic levels.
+
+Warning: 11.075 ns is the maximum delay for this constraint.
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
+            357 items scored, 234 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 4.364ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_610__i13  (from RCLK_c +)
+   Destination:    FD1P3AX    D              n8MEGEN_418  (to RCLK_c +)
+
+   Delay:                   9.182ns  (23.7% logic, 76.3% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.182ns data_path FS_610__i13 to n8MEGEN_418 violates
+      5.000ns delay constraint less
+      0.182ns L_S requirement (totaling 4.818ns) by 4.364ns
+
+ Path Details: FS_610__i13 to n8MEGEN_418
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              FS_610__i13 (from RCLK_c)
+Route         3   e 1.603                                  FS[13]
+LUT4        ---     0.390              A to Z              i1976_2_lut
+Route         3   e 1.483                                  n2272
+LUT4        ---     0.390              C to Z              i5_3_lut_rep_21_4_lut
+Route         3   e 1.483                                  n2464
+LUT4        ---     0.390              B to Z              i1_2_lut_3_lut_adj_4
+Route         1   e 1.220                                  n1325
+LUT4        ---     0.390              D to Z              n8MEGEN_I_14_4_lut
+Route         1   e 1.220                                  n8MEGEN_N_91
+                  --------
+                    9.182  (23.7% logic, 76.3% route), 5 logic levels.
+
+
+Error:  The following path violates requirements by 4.364ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_610__i15  (from RCLK_c +)
+   Destination:    FD1P3AX    D              n8MEGEN_418  (to RCLK_c +)
+
+   Delay:                   9.182ns  (23.7% logic, 76.3% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.182ns data_path FS_610__i15 to n8MEGEN_418 violates
+      5.000ns delay constraint less
+      0.182ns L_S requirement (totaling 4.818ns) by 4.364ns
+
+ Path Details: FS_610__i15 to n8MEGEN_418
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              FS_610__i15 (from RCLK_c)
+Route         3   e 1.603                                  FS[15]
+LUT4        ---     0.390              B to Z              i1976_2_lut
+Route         3   e 1.483                                  n2272
+LUT4        ---     0.390              C to Z              i5_3_lut_rep_21_4_lut
+Route         3   e 1.483                                  n2464
+LUT4        ---     0.390              B to Z              i1_2_lut_3_lut_adj_4
+Route         1   e 1.220                                  n1325
+LUT4        ---     0.390              D to Z              n8MEGEN_I_14_4_lut
+Route         1   e 1.220                                  n8MEGEN_N_91
+                  --------
+                    9.182  (23.7% logic, 76.3% route), 5 logic levels.
+
+
+Error:  The following path violates requirements by 4.349ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_610__i13  (from RCLK_c +)
+   Destination:    FD1P3AX    SP             n8MEGEN_418  (to RCLK_c +)
+
+   Delay:                   9.085ns  (23.9% logic, 76.1% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.085ns data_path FS_610__i13 to n8MEGEN_418 violates
+      5.000ns delay constraint less
+      0.264ns LCE_S requirement (totaling 4.736ns) by 4.349ns
+
+ Path Details: FS_610__i13 to n8MEGEN_418
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              FS_610__i13 (from RCLK_c)
+Route         3   e 1.603                                  FS[13]
+LUT4        ---     0.390              A to Z              i1976_2_lut
+Route         3   e 1.483                                  n2272
+LUT4        ---     0.390              C to Z              i7_4_lut
+Route         2   e 1.386                                  n2214
+LUT4        ---     0.390              B to Z              i2_2_lut
+Route         1   e 1.220                                  n7
+LUT4        ---     0.390              A to Z              i17_4_lut
+Route         1   e 1.220                                  RCLK_c_enable_11
+                  --------
+                    9.085  (23.9% logic, 76.1% route), 5 logic levels.
+
+Warning: 9.364 ns is the maximum delay for this constraint.
+
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets PHI2_c]                  |     5.000 ns|    22.150 ns|     6 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |     5.000 ns|     9.364 ns|     5 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+--------------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+--------------------------------------------------------------------------------
+n1326                                   |       8|     104|     30.06%
+                                        |        |        |
+n26                                     |       1|      78|     22.54%
+                                        |        |        |
+RCLK_c_enable_23                        |      16|      64|     18.50%
+                                        |        |        |
+--------------------------------------------------------------------------------
+
+
+Timing summary:
+---------------
+
+Timing errors: 346  Score: 1874657
+
+Constraints cover  476 paths, 187 nets, and 480 connections (64.3% coverage)
+
+
+Peak memory: 53284864 bytes, TRCE: 1122304 bytes, DLYMAN: 167936 bytes
+CPU_TIME_REPORT: 0 secs 
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_prim.v b/CPLD/LCMXO640C/impl1/RAM2GS_prim.v new file mode 100644 index 0000000..d45f192 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_prim.v @@ -0,0 +1,819 @@ +// Verilog netlist produced by program LSE : version Diamond (64-bit) 3.12.1.454 +// Netlist written on Tue Aug 15 05:03:22 2023 +// +// Verilog Description of module RAM2GS +// + +module RAM2GS (PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, + LED, RBA, RA, RD, nRCS, RCLK, RCKE, nRWE, nRRAS, + nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI, UFMSDO) /* synthesis syn_module_defined=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1[8:14]) + input PHI2; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) + input [9:0]MAin; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + input [1:0]CROW; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18]) + input [7:0]Din; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + output [7:0]Dout; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + input nCCAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) + input nCRAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + input nFWE; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(36[8:12]) + output LED; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(22[9:12]) + output [1:0]RBA; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22]) + output [11:0]RA; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + inout [7:0]RD; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + output nRCS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[13:17]) + input RCLK; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12]) + output RCKE; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(45[13:17]) + output nRWE; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[45:49]) + output nRRAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[23:28]) + output nRCAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[34:39]) + output RDQMH; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[16:21]) + output RDQML; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[9:14]) + output nUFMCS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(63[13:19]) + output UFMCLK; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(64[13:19]) + output UFMSDI; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(65[13:19]) + input UFMSDO; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(66[8:14]) + + wire PHI2_c /* synthesis is_clock=1, SET_AS_NETWORK=PHI2_c */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) + wire nCCAS_c /* synthesis is_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) + wire nCRAS_c /* synthesis is_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + wire RCLK_c /* synthesis SET_AS_NETWORK=RCLK_c, is_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12]) + wire nCCAS_N_3 /* synthesis is_inv_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + wire nCRAS_N_9 /* synthesis is_inv_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22]) + wire PHI2_N_120 /* synthesis is_inv_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(38[6:13]) + + wire GND_net, VCC_net, PHI2r, PHI2r2, PHI2r3, RASr, RASr2, + RASr3, CASr, CASr2, CASr3, FWEr, CBR, LEDEN, Din_c_7, + Din_c_6, Din_c_5, Din_c_4, Din_c_3, Din_c_2, Din_c_1, Din_c_0; + wire [7:0]Bank; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(31[12:16]) + + wire CROW_c_1, CROW_c_0, MAin_c_9, MAin_c_8, MAin_c_7, MAin_c_6, + MAin_c_5, MAin_c_4, MAin_c_3, MAin_c_2, MAin_c_1, MAin_c_0, + nFWE_c, n8MEGEN, XOR8MEG, RCKEEN, RCKE_c, nRCS_c, nRRAS_c, + nRCAS_c, nRWE_c, RBA_c_1, RBA_c_0, nRowColSel, RA_c, RA_0; + wire [9:0]RowA; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(51[12:16]) + + wire RA_1_9, RA_1_8, RA_1_7, RA_1_6, RA_1_5, RA_1_4, RA_1_3, + RA_1_2, RA_1_1, RA_1_0, RDQML_c, RDQMH_c; + wire [7:0]WRD; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(59[12:15]) + + wire nUFMCS_c, UFMCLK_c, UFMSDI_c, UFMSDO_c, C1Submitted, ADSubmitted, + CmdEnable, CmdSubmitted, Cmdn8MEGEN, CmdUFMCLK, CmdUFMSDI, + CmdUFMCS, InitReady, Ready; + wire [17:0]FS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(86[13:15]) + + wire LED_N_84, nFWE_N_5, n2414, RA11_N_184, n15, n2262, PHI2_N_120_enable_6, + n2257, n7, RASr2_N_63, RCKE_N_132, nRowColSel_N_35, n2011, + nRWE_N_182, RCKEEN_N_130, nRowColSel_N_34, nRowColSel_N_33, + n2015, nRowColSel_N_32, nRowColSel_N_28, n1426, n6, n2328, + n2457, n1425, RCKEEN_N_123, nRWE_N_178, RCKEEN_N_122, n2324, + nRCS_N_139, nRCAS_N_165, nRWE_N_177, nRWE_N_176, n2322, Ready_N_296, + n2316, n2314, Ready_N_292, nRCS_N_136, nRCAS_N_161, nRWE_N_171, + RCKEEN_N_121, n2336, PHI2_N_120_enable_5, n2209, CmdEnable_N_248, + C1Submitted_N_237, n2478, n2477, n2138, n1410, n2290, Cmdn8MEGEN_N_264, + XOR8MEG_N_110, n2208, LEDEN_N_82, n2243, RCLK_c_enable_24, + n2476, n2475, n8MEGEN_N_91, UFMCLK_N_224, UFMSDI_N_231, n2460, + n2227, n2253, n726, n727, n728, n729, n730, n1502, n732, + n733, n734, n735, n736, n737, n738, n2284, n2463, n2164, + PHI2_N_120_enable_4, n1325, n2278, n1503, n2214, n1417, + n2010, n2474, n2009, n1280, n33, n2473, n2263, n56, + PHI2_N_120_enable_1, n12, n10, n13, n2272, Dout_c, n78, + n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, + n89, n90, n91, n92, n93, n94, n95, n15_adj_1, n1, + n2462, n2472, n2471, n1093, RCLK_c_enable_11, n62, RCLK_c_enable_25, + n2470, n2242, n2461, RCLK_c_enable_23, RCLK_c_enable_12, n2451, + n2014, n14, n13_adj_2, n2568, n2245, PHI2_N_120_enable_7, + RCLK_c_enable_4, n2469, n1413, n1846, Dout_0, Dout_1, n984, + Dout_2, Dout_3, Dout_4, n1314, Dout_5, Dout_6, n2468, + n1160, n2337, n2008, n2013, n6_adj_3, RCLK_c_enable_3, n2467, + n2012, n2479, n1326, n2464, n8, n2481, n2430, n2459, + n2458, n2427, n2480, n11, n26; + + VHI i2 (.Z(VCC_net)); + INV i2136 (.A(PHI2_c), .Z(PHI2_N_120)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) + ORCALUT4 i6_4_lut (.A(FS[17]), .B(n12), .C(FS[12]), .D(FS[14]), + .Z(n62)) /* synthesis lut_function=(A (B (C (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i6_4_lut.init = 16'h8000; + ORCALUT4 i1_4_lut_4_lut (.A(Din_c_3), .B(Din_c_5), .C(Din_c_4), .D(n2458), + .Z(PHI2_N_120_enable_4)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A !(B+!(D))) */ ; + defparam i1_4_lut_4_lut.init = 16'hb300; + FD1S3AX PHI2r2_377 (.D(PHI2r), .CK(RCLK_c), .Q(PHI2r2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam PHI2r2_377.GSR = "ENABLED"; + ORCALUT4 i1994_3_lut (.A(FS[2]), .B(FS[5]), .C(FS[9]), .Z(n2290)) /* synthesis lut_function=(A+(B+(C))) */ ; + defparam i1994_3_lut.init = 16'hfefe; + ORCALUT4 i1_2_lut_3_lut (.A(MAin_c_0), .B(n1326), .C(MAin_c_1), .Z(n2263)) /* synthesis lut_function=((B+!(C))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(80[15:31]) + defparam i1_2_lut_3_lut.init = 16'hdfdf; + FD1S3AX PHI2r3_378 (.D(PHI2r2), .CK(RCLK_c), .Q(PHI2r3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam PHI2r3_378.GSR = "ENABLED"; + FD1S3AX RASr_379 (.D(nCRAS_N_9), .CK(RCLK_c), .Q(RASr)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam RASr_379.GSR = "ENABLED"; + FD1S3AX RASr2_380 (.D(RASr), .CK(RCLK_c), .Q(RASr2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam RASr2_380.GSR = "ENABLED"; + FD1S3AX RASr3_381 (.D(RASr2), .CK(RCLK_c), .Q(RASr3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam RASr3_381.GSR = "ENABLED"; + FD1S3AX CASr_382 (.D(nCCAS_N_3), .CK(RCLK_c), .Q(CASr)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam CASr_382.GSR = "ENABLED"; + FD1S3AX CASr2_383 (.D(CASr), .CK(RCLK_c), .Q(CASr2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam CASr2_383.GSR = "ENABLED"; + FD1S3AX CASr3_384 (.D(CASr2), .CK(RCLK_c), .Q(CASr3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam CASr3_384.GSR = "ENABLED"; + FD1S3IX RA11_385 (.D(RA11_N_184), .CK(PHI2_c), .CD(n2477), .Q(RA_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam RA11_385.GSR = "ENABLED"; + FD1S3IX RowA_i0 (.D(MAin_c_0), .CK(nCRAS_N_9), .CD(n2477), .Q(RowA[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i0.GSR = "ENABLED"; + ORCALUT4 i637_1_lut_rep_34 (.A(Ready), .Z(n2477)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i637_1_lut_rep_34.init = 16'h5555; + FD1S3AX WRD_i0 (.D(Din_c_0), .CK(nCCAS_N_3), .Q(WRD[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i0.GSR = "ENABLED"; + FD1S3AX FWEr_389 (.D(nFWE_N_5), .CK(nCRAS_N_9), .Q(FWEr)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam FWEr_389.GSR = "ENABLED"; + FD1S3AX CBR_390 (.D(nCCAS_N_3), .CK(nCRAS_N_9), .Q(CBR)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam CBR_390.GSR = "ENABLED"; + FD1S3IX ADSubmitted_407 (.D(n1413), .CK(PHI2_N_120), .CD(C1Submitted_N_237), + .Q(ADSubmitted)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam ADSubmitted_407.GSR = "ENABLED"; + ORCALUT4 i2026_4_lut (.A(FS[0]), .B(FS[1]), .C(FS[6]), .D(FS[3]), + .Z(n2322)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; + defparam i2026_4_lut.init = 16'hfffe; + FD1S3AX RCKE_395 (.D(RCKE_N_132), .CK(RCLK_c), .Q(RCKE_c)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(141[9] 144[5]) + defparam RCKE_395.GSR = "ENABLED"; + FD1P3AY nRCS_396 (.D(nRCS_N_136), .SP(RCLK_c_enable_4), .CK(RCLK_c), + .Q(nRCS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRCS_396.GSR = "ENABLED"; + FD1S3IX nRowColSel_402 (.D(n1410), .CK(RCLK_c), .CD(n2469), .Q(nRowColSel)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRowColSel_402.GSR = "ENABLED"; + ORCALUT4 n8MEGEN_I_14_4_lut (.A(UFMSDO_c), .B(Cmdn8MEGEN), .C(InitReady), + .D(n1325), .Z(n8MEGEN_N_91)) /* synthesis lut_function=(A (B (C+(D)))+!A (B+!(C+(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(394[12] 409[6]) + defparam n8MEGEN_I_14_4_lut.init = 16'hccc5; + ORCALUT4 i771_2_lut_rep_26_2_lut (.A(Ready), .B(nRowColSel_N_35), .Z(n2469)) /* synthesis lut_function=((B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i771_2_lut_rep_26_2_lut.init = 16'hdddd; + ORCALUT4 i7_4_lut (.A(FS[10]), .B(n2328), .C(n2272), .D(FS[11]), + .Z(n2214)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i7_4_lut.init = 16'h0200; + ORCALUT4 i2062_2_lut_3_lut_4_lut (.A(nFWE_c), .B(n1326), .C(C1Submitted), + .D(MAin_c_1), .Z(n6_adj_3)) /* synthesis lut_function=(A (C)+!A (B (C)+!B !((D)+!C))) */ ; + defparam i2062_2_lut_3_lut_4_lut.init = 16'he0f0; + ORCALUT4 i2046_1_lut_2_lut_3_lut_3_lut (.A(Ready), .B(n13), .C(nRCS_N_139), + .Z(n2337)) /* synthesis lut_function=(!(A (B)+!A !((C)+!B))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i2046_1_lut_2_lut_3_lut_3_lut.init = 16'h7373; + ORCALUT4 i3_3_lut_4_lut_4_lut (.A(Ready), .B(InitReady), .C(RASr2), + .D(nRowColSel_N_35), .Z(RCLK_c_enable_23)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i3_3_lut_4_lut_4_lut.init = 16'h4000; + ORCALUT4 i2065_2_lut_3_lut (.A(FS[11]), .B(n2464), .C(InitReady), + .Z(n1846)) /* synthesis lut_function=(!(A+(B+(C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i2065_2_lut_3_lut.init = 16'h0101; + ORCALUT4 i2055_3_lut_4_lut (.A(FS[11]), .B(n2464), .C(FS[10]), .D(InitReady), + .Z(LEDEN_N_82)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i2055_3_lut_4_lut.init = 16'h0001; + ORCALUT4 i2_3_lut (.A(n2214), .B(FS[11]), .C(InitReady), .Z(RCLK_c_enable_12)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam i2_3_lut.init = 16'h0808; + CCU2 FS_610_add_4_8 (.A0(FS[6]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[7]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2010), + .COUT1(n2011), .S0(n89), .S1(n88)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_8.INIT0 = 16'hfaaa; + defparam FS_610_add_4_8.INIT1 = 16'hfaaa; + defparam FS_610_add_4_8.INJECT1_0 = "NO"; + defparam FS_610_add_4_8.INJECT1_1 = "NO"; + FD1S3IX S_FSM_i3 (.D(n1093), .CK(RCLK_c), .CD(n1425), .Q(nRowColSel_N_33)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam S_FSM_i3.GSR = "ENABLED"; + ORCALUT4 Ready_bdd_4_lut (.A(nRowColSel_N_32), .B(RASr2), .C(Ready_N_296), + .D(InitReady), .Z(n2414)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ; + defparam Ready_bdd_4_lut.init = 16'h2000; + FD1S3AY nRRAS_397 (.D(n2138), .CK(RCLK_c), .Q(nRRAS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRRAS_397.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_2_lut (.A(Ready), .B(nRowColSel_N_34), .Z(n56)) /* synthesis lut_function=((B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i1_2_lut_2_lut.init = 16'hdddd; + ORCALUT4 i2_4_lut (.A(Din_c_2), .B(n2463), .C(n1280), .D(n2468), + .Z(C1Submitted_N_237)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ; + defparam i2_4_lut.init = 16'h0400; + ORCALUT4 i1_2_lut_3_lut_4_lut_4_lut (.A(Ready), .B(nRowColSel_N_32), + .C(n1502), .D(nRowColSel_N_35), .Z(RCLK_c_enable_3)) /* synthesis lut_function=((B+(C+(D)))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i1_2_lut_3_lut_4_lut_4_lut.init = 16'hfffd; + ORCALUT4 Din_7__I_0_462_i6_2_lut_rep_35 (.A(Din_c_6), .B(Din_c_7), .Z(n2478)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(315[17:31]) + defparam Din_7__I_0_462_i6_2_lut_rep_35.init = 16'heeee; + BB Dout_pad_7__713 (.I(WRD[7]), .T(n984), .B(RD[7]), .O(Dout_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + FD1P3AY nRCAS_398 (.D(nRCAS_N_161), .SP(RCLK_c_enable_4), .CK(RCLK_c), + .Q(nRCAS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRCAS_398.GSR = "ENABLED"; + FD1P3AY nRWE_399 (.D(nRWE_N_171), .SP(RCLK_c_enable_3), .CK(RCLK_c), + .Q(nRWE_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRWE_399.GSR = "ENABLED"; + FD1S3JX RA10_400 (.D(n2209), .CK(RCLK_c), .PD(nRWE_N_176), .Q(RA_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam RA10_400.GSR = "ENABLED"; + FD1P3AX RCKEEN_401 (.D(RCKEEN_N_121), .SP(RCLK_c_enable_4), .CK(RCLK_c), + .Q(RCKEEN)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam RCKEEN_401.GSR = "ENABLED"; + FD1S3AX FS_610__i0 (.D(n95), .CK(RCLK_c), .Q(FS[0])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i0.GSR = "ENABLED"; + ORCALUT4 i13_4_lut (.A(MAin_c_2), .B(n26), .C(n2316), .D(MAin_c_5), + .Z(n1326)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ; + defparam i13_4_lut.init = 16'hdfff; + ORCALUT4 i12_4_lut (.A(Bank[2]), .B(n2314), .C(n2278), .D(Bank[5]), + .Z(n26)) /* synthesis lut_function=(A+!(B (C (D)))) */ ; + defparam i12_4_lut.init = 16'hbfff; + ORCALUT4 i2_3_lut_adj_1 (.A(MAin_c_1), .B(n1326), .C(MAin_c_0), .Z(n1280)) /* synthesis lut_function=((B+(C))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(80[15:31]) + defparam i2_3_lut_adj_1.init = 16'hfdfd; + FD1S3IX RBA__i1 (.D(CROW_c_0), .CK(nCRAS_N_9), .CD(n2477), .Q(RBA_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RBA__i1.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_3_lut_adj_2 (.A(Din_c_6), .B(Din_c_7), .C(Din_c_5), + .Z(n1314)) /* synthesis lut_function=(A+(B+(C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(315[17:31]) + defparam i1_2_lut_3_lut_adj_2.init = 16'hfefe; + ORCALUT4 i2020_4_lut (.A(MAin_c_7), .B(MAin_c_3), .C(Bank[4]), .D(Bank[1]), + .Z(n2316)) /* synthesis lut_function=(A (B (C (D)))) */ ; + defparam i2020_4_lut.init = 16'h8000; + ORCALUT4 i1990_2_lut_rep_17 (.A(nFWE_c), .B(n1326), .Z(n2460)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1990_2_lut_rep_17.init = 16'heeee; + ORCALUT4 i1125_4_lut (.A(n2459), .B(n2242), .C(ADSubmitted), .D(n2263), + .Z(n1413)) /* synthesis lut_function=(!(A ((D)+!B)+!A !(B (C+!(D))+!B (C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam i1125_4_lut.init = 16'h50dc; + ORCALUT4 i2018_4_lut (.A(MAin_c_6), .B(MAin_c_4), .C(Bank[7]), .D(Bank[0]), + .Z(n2314)) /* synthesis lut_function=(A (B (C (D)))) */ ; + defparam i2018_4_lut.init = 16'h8000; + ORCALUT4 i4_4_lut (.A(Din_c_4), .B(n2478), .C(CmdEnable), .D(MAin_c_1), + .Z(n10)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ; + defparam i4_4_lut.init = 16'h0020; + ORCALUT4 i2_2_lut_rep_27 (.A(FS[16]), .B(FS[14]), .Z(n2470)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i2_2_lut_rep_27.init = 16'heeee; + ORCALUT4 i2_3_lut_4_lut (.A(nRowColSel_N_32), .B(n2469), .C(nRowColSel_N_34), + .D(nRowColSel_N_33), .Z(RCLK_c_enable_4)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i2_3_lut_4_lut.init = 16'hfffe; + ORCALUT4 Cmdn8MEGEN_I_93_4_lut (.A(Din_c_0), .B(n8MEGEN), .C(Din_c_4), + .D(n1314), .Z(Cmdn8MEGEN_N_264)) /* synthesis lut_function=(A (B ((D)+!C))+!A (B+!((D)+!C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(321[13] 335[7]) + defparam Cmdn8MEGEN_I_93_4_lut.init = 16'hcc5c; + ORCALUT4 i1982_2_lut (.A(Bank[6]), .B(Bank[3]), .Z(n2278)) /* synthesis lut_function=(A (B)) */ ; + defparam i1982_2_lut.init = 16'h8888; + ORCALUT4 i2_4_lut_adj_3 (.A(Din_c_3), .B(Din_c_4), .C(Din_c_5), .D(n2458), + .Z(PHI2_N_120_enable_5)) /* synthesis lut_function=(A (B (D))+!A !((C+!(D))+!B)) */ ; + defparam i2_4_lut_adj_3.init = 16'h8c00; + FD1P3AX IS_FSM__i0 (.D(Ready_N_296), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(nRCS_N_139)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i0.GSR = "ENABLED"; + FD1S3JX C1Submitted_406 (.D(n6_adj_3), .CK(PHI2_N_120), .PD(C1Submitted_N_237), + .Q(C1Submitted)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam C1Submitted_406.GSR = "ENABLED"; + FD1S3JX nUFMCS_415 (.D(n2164), .CK(RCLK_c), .PD(LEDEN_N_82), .Q(nUFMCS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam nUFMCS_415.GSR = "ENABLED"; + ORCALUT4 i2049_3_lut (.A(LEDEN), .B(CBR), .C(nCRAS_c), .Z(LED_N_84)) /* synthesis lut_function=((B+(C))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(23[15:41]) + defparam i2049_3_lut.init = 16'hfdfd; + ORCALUT4 MAin_9__I_0_427_i10_3_lut (.A(RowA[9]), .B(MAin_c_9), .C(nRowColSel), + .Z(RA_1_9)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i10_3_lut.init = 16'hcaca; + FD1S3AX S_FSM_i1 (.D(RASr2_N_63), .CK(RCLK_c), .Q(nRowColSel_N_35)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam S_FSM_i1.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_3_lut_adj_4 (.A(FS[11]), .B(n2464), .C(FS[10]), + .Z(n1325)) /* synthesis lut_function=((B+!(C))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i1_2_lut_3_lut_adj_4.init = 16'hdfdf; + ORCALUT4 MAin_9__I_0_427_i9_3_lut (.A(RowA[8]), .B(MAin_c_8), .C(nRowColSel), + .Z(RA_1_8)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i9_3_lut.init = 16'hcaca; + ORCALUT4 MAin_9__I_0_427_i8_3_lut (.A(RowA[7]), .B(MAin_c_7), .C(nRowColSel), + .Z(RA_1_7)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i8_3_lut.init = 16'hcaca; + ORCALUT4 i1209_4_lut_else_4_lut (.A(nRCS_N_139), .B(Ready), .C(nRowColSel_N_35), + .Z(n2479)) /* synthesis lut_function=(!(A (B (C))+!A (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(48[6:16]) + defparam i1209_4_lut_else_4_lut.init = 16'h2f2f; + ORCALUT4 i1_2_lut_3_lut_adj_5 (.A(MAin_c_0), .B(n1326), .C(MAin_c_1), + .Z(n2262)) /* synthesis lut_function=((B+(C))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(80[15:31]) + defparam i1_2_lut_3_lut_adj_5.init = 16'hfdfd; + ORCALUT4 i2045_1_lut_4_lut (.A(n56), .B(nRRAS_c), .C(n6), .D(nRowColSel_N_32), + .Z(n2336)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; + defparam i2045_1_lut_4_lut.init = 16'hfffe; + FD1S3AX Bank_i0 (.D(Din_c_0), .CK(PHI2_c), .Q(Bank[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i0.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_4_lut (.A(MAin_c_0), .B(n10), .C(n2460), .D(n2476), + .Z(PHI2_N_120_enable_6)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ; + defparam i1_2_lut_4_lut.init = 16'h0800; + ORCALUT4 i2_3_lut_rep_29 (.A(PHI2r3), .B(CmdSubmitted), .C(PHI2r2), + .Z(n2472)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(402[16:47]) + defparam i2_3_lut_rep_29.init = 16'h0808; + ORCALUT4 nRowColSel_N_34_bdd_3_lut_2115 (.A(nRowColSel_N_34), .B(n15_adj_1), + .C(Ready), .Z(n2430)) /* synthesis lut_function=(A+!(B (C))) */ ; + defparam nRowColSel_N_34_bdd_3_lut_2115.init = 16'hbfbf; + ORCALUT4 i4_4_lut_adj_6 (.A(MAin_c_1), .B(n2476), .C(MAin_c_0), .D(n2284), + .Z(n2257)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ; + defparam i4_4_lut_adj_6.init = 16'h0080; + FD1S3AX PHI2r_376 (.D(PHI2_c), .CK(RCLK_c), .Q(PHI2r)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam PHI2r_376.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_4_lut_adj_7 (.A(PHI2r3), .B(CmdSubmitted), .C(PHI2r2), + .D(InitReady), .Z(RCLK_c_enable_24)) /* synthesis lut_function=(!(A (B (C (D))+!B (D))+!A (D))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(402[16:47]) + defparam i1_2_lut_4_lut_adj_7.init = 16'h08ff; + ORCALUT4 i2024_2_lut_rep_28 (.A(FS[17]), .B(FS[12]), .Z(n2471)) /* synthesis lut_function=(A+(B)) */ ; + defparam i2024_2_lut_rep_28.init = 16'heeee; + FD1S3IX S_FSM_i4 (.D(n1503), .CK(RCLK_c), .CD(RASr2_N_63), .Q(nRowColSel_N_32)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam S_FSM_i4.GSR = "ENABLED"; + CCU2 FS_610_add_4_16 (.A0(FS[14]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[15]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2014), + .COUT1(n2015), .S0(n81), .S1(n80)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_16.INIT0 = 16'hfaaa; + defparam FS_610_add_4_16.INIT1 = 16'hfaaa; + defparam FS_610_add_4_16.INJECT1_0 = "NO"; + defparam FS_610_add_4_16.INJECT1_1 = "NO"; + ORCALUT4 i2_3_lut_4_lut_adj_8 (.A(nRowColSel_N_35), .B(RASr2), .C(InitReady), + .D(nRCS_N_139), .Z(n2208)) /* synthesis lut_function=((((D)+!C)+!B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i2_3_lut_4_lut_adj_8.init = 16'hff7f; + ORCALUT4 i1_4_lut_4_lut_adj_9 (.A(CBR), .B(n11), .C(FWEr), .D(nRowColSel_N_34), + .Z(RCKEEN_N_123)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(23[27:31]) + defparam i1_4_lut_4_lut_adj_9.init = 16'h5540; + ORCALUT4 i3_4_lut (.A(CBR), .B(FWEr), .C(CASr2), .D(CASr3), .Z(n1)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ; + defparam i3_4_lut.init = 16'h0040; + PFUMX i2095 (.BLUT(n2430), .ALUT(n2457), .C0(nRowColSel_N_35), .Z(nRCAS_N_161)); + ORCALUT4 MAin_9__I_0_427_i7_3_lut (.A(RowA[6]), .B(MAin_c_6), .C(nRowColSel), + .Z(RA_1_6)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i7_3_lut.init = 16'hcaca; + ORCALUT4 i1_4_lut (.A(nRowColSel), .B(n1502), .C(nRowColSel_N_28), + .D(nRowColSel_N_32), .Z(n1410)) /* synthesis lut_function=(A (B+!(C (D)))+!A (B+!(C+!(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i1_4_lut.init = 16'hcfee; + ORCALUT4 i1_2_lut (.A(RASr2), .B(RCKE_c), .Z(nRWE_N_182)) /* synthesis lut_function=(A+!(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam i1_2_lut.init = 16'hbbbb; + ORCALUT4 i2004_2_lut_rep_30 (.A(Din_c_4), .B(nFWE_c), .Z(n2473)) /* synthesis lut_function=(A+(B)) */ ; + defparam i2004_2_lut_rep_30.init = 16'heeee; + ORCALUT4 i1_2_lut_rep_20_3_lut (.A(Din_c_4), .B(nFWE_c), .C(n2253), + .Z(n2463)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ; + defparam i1_2_lut_rep_20_3_lut.init = 16'h1010; + ORCALUT4 i2_3_lut_adj_10 (.A(Din_c_7), .B(Din_c_0), .C(Din_c_1), .Z(n2253)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ; + defparam i2_3_lut_adj_10.init = 16'h0808; + CCU2 FS_610_add_4_6 (.A0(FS[4]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[5]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2009), + .COUT1(n2010), .S0(n91), .S1(n90)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_6.INIT0 = 16'hfaaa; + defparam FS_610_add_4_6.INIT1 = 16'hfaaa; + defparam FS_610_add_4_6.INJECT1_0 = "NO"; + defparam FS_610_add_4_6.INJECT1_1 = "NO"; + ORCALUT4 i2_4_lut_adj_11 (.A(n2473), .B(CmdEnable), .C(n2262), .D(n1314), + .Z(PHI2_N_120_enable_1)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ; + defparam i2_4_lut_adj_11.init = 16'h0004; + ORCALUT4 MAin_9__I_0_427_i6_3_lut (.A(RowA[5]), .B(MAin_c_5), .C(nRowColSel), + .Z(RA_1_5)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i6_3_lut.init = 16'hcaca; + ORCALUT4 i3_4_lut_adj_12 (.A(Din_c_0), .B(Din_c_3), .C(Din_c_2), .D(n2324), + .Z(XOR8MEG_N_110)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ; + defparam i3_4_lut_adj_12.init = 16'h0020; + ORCALUT4 MAin_9__I_0_427_i5_3_lut (.A(RowA[4]), .B(MAin_c_4), .C(nRowColSel), + .Z(RA_1_4)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i5_3_lut.init = 16'hcaca; + ORCALUT4 i2028_4_lut (.A(Din_c_4), .B(LEDEN), .C(n1314), .D(Din_c_1), + .Z(n2324)) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ; + defparam i2028_4_lut.init = 16'hfefa; + ORCALUT4 MAin_9__I_0_427_i4_3_lut (.A(RowA[3]), .B(MAin_c_3), .C(nRowColSel), + .Z(RA_1_3)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i4_3_lut.init = 16'hcaca; + ORCALUT4 i2_3_lut_rep_31 (.A(Din_c_6), .B(Din_c_2), .C(Din_c_3), .Z(n2474)) /* synthesis lut_function=(!(A+!(B (C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) + defparam i2_3_lut_rep_31.init = 16'h4040; + FD1P3IX UFMSDI_417 (.D(UFMSDI_N_231), .SP(RCLK_c_enable_24), .CD(n1846), + .CK(RCLK_c), .Q(UFMSDI_c)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam UFMSDI_417.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_4_lut_adj_13 (.A(Din_c_6), .B(Din_c_2), .C(Din_c_3), + .D(MAin_c_0), .Z(n2243)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) + defparam i1_2_lut_4_lut_adj_13.init = 16'h4000; + ORCALUT4 MAin_9__I_0_427_i3_3_lut (.A(RowA[2]), .B(MAin_c_2), .C(nRowColSel), + .Z(RA_1_2)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i3_3_lut.init = 16'hcaca; + ORCALUT4 n2427_bdd_4_lut_4_lut (.A(CBR), .B(RASr2), .C(Ready), .D(n2427), + .Z(n2457)) /* synthesis lut_function=(!(A (B (C+!(D)))+!A !((C+(D))+!B))) */ ; + defparam n2427_bdd_4_lut_4_lut.init = 16'h7f73; + GSR GSR_INST (.GSR(VCC_net)); + ORCALUT4 i2_3_lut_adj_14 (.A(FWEr), .B(CASr3), .C(CBR), .Z(nRowColSel_N_28)) /* synthesis lut_function=((B+(C))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(230[16:37]) + defparam i2_3_lut_adj_14.init = 16'hfdfd; + ORCALUT4 InitReady_bdd_3_lut (.A(InitReady), .B(nRCS_N_139), .C(nRCAS_N_165), + .Z(n2427)) /* synthesis lut_function=((B+(C))+!A) */ ; + defparam InitReady_bdd_3_lut.init = 16'hfdfd; + ORCALUT4 i35_3_lut_4_lut (.A(FWEr), .B(CBR), .C(nRowColSel_N_33), + .D(n1), .Z(n15_adj_1)) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C+(D))))) */ ; + defparam i35_3_lut_4_lut.init = 16'h1f10; + ORCALUT4 MAin_9__I_0_427_i2_3_lut (.A(RowA[1]), .B(MAin_c_1), .C(nRowColSel), + .Z(RA_1_1)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i2_3_lut.init = 16'hcaca; + CCU2 FS_610_add_4_14 (.A0(FS[12]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[13]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2013), + .COUT1(n2014), .S0(n83), .S1(n82)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_14.INIT0 = 16'hfaaa; + defparam FS_610_add_4_14.INIT1 = 16'hfaaa; + defparam FS_610_add_4_14.INJECT1_0 = "NO"; + defparam FS_610_add_4_14.INJECT1_1 = "NO"; + ORCALUT4 i2_3_lut_4_lut_adj_15 (.A(n2473), .B(n2253), .C(Din_c_5), + .D(n2474), .Z(n2242)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ; + defparam i2_3_lut_4_lut_adj_15.init = 16'h4000; + ORCALUT4 n2414_bdd_2_lut (.A(n2414), .B(Ready), .Z(Ready_N_292)) /* synthesis lut_function=(A+(B)) */ ; + defparam n2414_bdd_2_lut.init = 16'heeee; + ORCALUT4 i1_2_lut_adj_16 (.A(nRowColSel_N_34), .B(nRowColSel_N_33), + .Z(n1502)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i1_2_lut_adj_16.init = 16'heeee; + ORCALUT4 RCKE_I_0_449_4_lut (.A(RASr), .B(RCKEEN), .C(RASr2), .D(RASr3), + .Z(RCKE_N_132)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B (C+(D))+!B !(C+!(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(143[11:55]) + defparam RCKE_I_0_449_4_lut.init = 16'hcfc8; + ORCALUT4 i1_4_lut_adj_17 (.A(n2467), .B(n2481), .C(n13), .D(nRowColSel_N_35), + .Z(nRCS_N_136)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B+!(C (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(48[6:16]) + defparam i1_4_lut_adj_17.init = 16'hcfdd; + FD1P3AX IS_FSM__i15 (.D(n726), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(Ready_N_296)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i15.GSR = "ENABLED"; + ORCALUT4 MAin_9__I_0_427_i1_3_lut (.A(RowA[0]), .B(MAin_c_0), .C(nRowColSel), + .Z(RA_1_0)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i1_3_lut.init = 16'hcaca; + ORCALUT4 i1558_2_lut_3_lut (.A(FWEr), .B(CBR), .C(RASr2), .Z(RCKEEN_N_130)) /* synthesis lut_function=(!(A (C)+!A (B (C)))) */ ; + defparam i1558_2_lut_3_lut.init = 16'h1f1f; + ORCALUT4 RA11_I_54_3_lut (.A(Din_c_6), .B(XOR8MEG), .C(n8MEGEN), .Z(RA11_N_184)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A (B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(99[22:51]) + defparam RA11_I_54_3_lut.init = 16'hc6c6; + ORCALUT4 i17_4_lut (.A(n7), .B(n2472), .C(InitReady), .D(n8), .Z(RCLK_c_enable_11)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ; + defparam i17_4_lut.init = 16'hcac0; + ORCALUT4 i1234_4_lut_4_lut (.A(RASr2), .B(InitReady), .C(RCKE_c), + .D(Ready), .Z(n13)) /* synthesis lut_function=(A (B+(D))+!A (C (D))) */ ; + defparam i1234_4_lut_4_lut.init = 16'hfa88; + ORCALUT4 i2_2_lut (.A(FS[8]), .B(n2214), .Z(n7)) /* synthesis lut_function=(!(A+!(B))) */ ; + defparam i2_2_lut.init = 16'h4444; + ORCALUT4 i78_2_lut_rep_24_3_lut (.A(RASr2), .B(InitReady), .C(Ready), + .Z(n2467)) /* synthesis lut_function=(A (B+(C))+!A (C)) */ ; + defparam i78_2_lut_rep_24_3_lut.init = 16'hf8f8; + FD1P3AX IS_FSM__i14 (.D(n727), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n726)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i14.GSR = "ENABLED"; + FD1P3AX IS_FSM__i13 (.D(n728), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n727)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i13.GSR = "ENABLED"; + ORCALUT4 i2_2_lut_3_lut_4_lut (.A(RASr2), .B(InitReady), .C(nRowColSel_N_33), + .D(Ready), .Z(n6)) /* synthesis lut_function=(A (B (C)+!B (C+!(D)))+!A (C+!(D))) */ ; + defparam i2_2_lut_3_lut_4_lut.init = 16'hf0f7; + ORCALUT4 i1512_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQMH_c)) /* synthesis lut_function=(A+!(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(58[17:46]) + defparam i1512_2_lut.init = 16'hbbbb; + ORCALUT4 i1_1_lut (.A(nFWE_c), .Z(nFWE_N_5)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam i1_1_lut.init = 16'h5555; + FD1P3AX IS_FSM__i12 (.D(n729), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n728)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i12.GSR = "ENABLED"; + FD1P3AX XOR8MEG_408 (.D(XOR8MEG_N_110), .SP(PHI2_N_120_enable_1), .CK(PHI2_N_120), + .Q(XOR8MEG)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam XOR8MEG_408.GSR = "ENABLED"; + FD1P3AX n8MEGEN_418 (.D(n8MEGEN_N_91), .SP(RCLK_c_enable_11), .CK(RCLK_c), + .Q(n8MEGEN)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam n8MEGEN_418.GSR = "ENABLED"; + FD1P3AX LEDEN_419 (.D(n2568), .SP(RCLK_c_enable_12), .CK(RCLK_c), + .Q(LEDEN)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam LEDEN_419.GSR = "ENABLED"; + PFUMX i16 (.BLUT(n2336), .ALUT(n2337), .C0(nRowColSel_N_35), .Z(n2138)); + FD1P3AX Ready_404 (.D(n2568), .SP(Ready_N_292), .CK(RCLK_c), .Q(Ready)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam Ready_404.GSR = "ENABLED"; + FD1P3AX CmdUFMCLK_413 (.D(Din_c_1), .SP(PHI2_N_120_enable_6), .CK(PHI2_N_120), + .Q(CmdUFMCLK)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdUFMCLK_413.GSR = "ENABLED"; + FD1P3AX CmdUFMSDI_414 (.D(Din_c_0), .SP(PHI2_N_120_enable_6), .CK(PHI2_N_120), + .Q(CmdUFMSDI)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdUFMSDI_414.GSR = "ENABLED"; + FD1P3AX Cmdn8MEGEN_410 (.D(Cmdn8MEGEN_N_264), .SP(PHI2_N_120_enable_4), + .CK(PHI2_N_120), .Q(Cmdn8MEGEN)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam Cmdn8MEGEN_410.GSR = "ENABLED"; + FD1P3AX CmdSubmitted_411 (.D(n2568), .SP(PHI2_N_120_enable_5), .CK(PHI2_N_120), + .Q(CmdSubmitted)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdSubmitted_411.GSR = "ENABLED"; + FD1P3AX CmdUFMCS_412 (.D(Din_c_2), .SP(PHI2_N_120_enable_6), .CK(PHI2_N_120), + .Q(CmdUFMCS)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdUFMCS_412.GSR = "ENABLED"; + FD1P3AX IS_FSM__i11 (.D(n730), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n729)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i11.GSR = "ENABLED"; + ORCALUT4 i2060_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQML_c)) /* synthesis lut_function=(!(A (B))) */ ; + defparam i2060_2_lut.init = 16'h7777; + ORCALUT4 i1_2_lut_rep_32 (.A(Din_c_6), .B(Din_c_3), .Z(n2475)) /* synthesis lut_function=(!((B)+!A)) */ ; + defparam i1_2_lut_rep_32.init = 16'h2222; + FD1P3AX IS_FSM__i10 (.D(nRWE_N_177), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n730)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i10.GSR = "ENABLED"; + ORCALUT4 i3_4_lut_adj_18 (.A(n2290), .B(FS[4]), .C(n2322), .D(FS[7]), + .Z(n8)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ; + defparam i3_4_lut_adj_18.init = 16'h0004; + ORCALUT4 i886_3_lut (.A(CmdUFMCLK), .B(n1160), .C(InitReady), .Z(UFMCLK_N_224)) /* synthesis lut_function=(A (B+(C))+!A !((C)+!B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(386[12] 409[6]) + defparam i886_3_lut.init = 16'hacac; + FD1P3AX IS_FSM__i9 (.D(n732), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(nRWE_N_177)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i9.GSR = "ENABLED"; + ORCALUT4 i2_3_lut_4_lut_adj_19 (.A(Din_c_6), .B(Din_c_3), .C(Din_c_2), + .D(MAin_c_0), .Z(n2245)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ; + defparam i2_3_lut_4_lut_adj_19.init = 16'h0002; + ORCALUT4 i919_4_lut (.A(FS[4]), .B(n62), .C(n2462), .D(FS[1]), .Z(n1160)) /* synthesis lut_function=(!(A (B (C)+!B !((D)+!C))+!A (B+!(C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(386[12] 409[6]) + defparam i919_4_lut.init = 16'h3a0a; + ORCALUT4 i2052_4_lut (.A(MAin_c_0), .B(n2460), .C(n14), .D(MAin_c_1), + .Z(PHI2_N_120_enable_7)) /* synthesis lut_function=(!(A (B+(C))+!A (B+(C+!(D))))) */ ; + defparam i2052_4_lut.init = 16'h0302; + ORCALUT4 i2_3_lut_adj_20 (.A(n2253), .B(Din_c_4), .C(n13_adj_2), .Z(n14)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ; + defparam i2_3_lut_adj_20.init = 16'h2020; + ORCALUT4 i1136_1_lut (.A(nRowColSel_N_34), .Z(n1425)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i1136_1_lut.init = 16'h5555; + FD1P3AX IS_FSM__i8 (.D(n733), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n732)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i8.GSR = "ENABLED"; + FD1P3AX IS_FSM__i7 (.D(n734), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n733)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i7.GSR = "ENABLED"; + FD1P3AX IS_FSM__i6 (.D(n735), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n734)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i6.GSR = "ENABLED"; + FD1P3AX IS_FSM__i5 (.D(n736), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n735)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i5.GSR = "ENABLED"; + FD1P3AX IS_FSM__i4 (.D(n737), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n736)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i4.GSR = "ENABLED"; + FD1P3AX IS_FSM__i3 (.D(n738), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n737)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i3.GSR = "ENABLED"; + FD1P3AX IS_FSM__i2 (.D(nRCAS_N_165), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n738)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i2.GSR = "ENABLED"; + FD1P3AX IS_FSM__i1 (.D(nRCS_N_139), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(nRCAS_N_165)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i1.GSR = "ENABLED"; + FD1S3IX RBA__i2 (.D(CROW_c_1), .CK(nCRAS_N_9), .CD(n2477), .Q(RBA_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RBA__i2.GSR = "ENABLED"; + FD1S3AX FS_610__i17 (.D(n78), .CK(RCLK_c), .Q(FS[17])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i17.GSR = "ENABLED"; + FD1S3AX FS_610__i16 (.D(n79), .CK(RCLK_c), .Q(FS[16])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i16.GSR = "ENABLED"; + FD1S3AX FS_610__i15 (.D(n80), .CK(RCLK_c), .Q(FS[15])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i15.GSR = "ENABLED"; + FD1S3AX FS_610__i14 (.D(n81), .CK(RCLK_c), .Q(FS[14])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i14.GSR = "ENABLED"; + FD1S3AX FS_610__i13 (.D(n82), .CK(RCLK_c), .Q(FS[13])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i13.GSR = "ENABLED"; + FD1S3AX FS_610__i12 (.D(n83), .CK(RCLK_c), .Q(FS[12])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i12.GSR = "ENABLED"; + FD1S3AX FS_610__i11 (.D(n84), .CK(RCLK_c), .Q(FS[11])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i11.GSR = "ENABLED"; + FD1S3AX FS_610__i10 (.D(n85), .CK(RCLK_c), .Q(FS[10])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i10.GSR = "ENABLED"; + FD1S3AX FS_610__i9 (.D(n86), .CK(RCLK_c), .Q(FS[9])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i9.GSR = "ENABLED"; + FD1S3AX FS_610__i8 (.D(n87), .CK(RCLK_c), .Q(FS[8])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i8.GSR = "ENABLED"; + FD1S3AX FS_610__i7 (.D(n88), .CK(RCLK_c), .Q(FS[7])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i7.GSR = "ENABLED"; + FD1S3AX FS_610__i6 (.D(n89), .CK(RCLK_c), .Q(FS[6])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i6.GSR = "ENABLED"; + FD1S3AX FS_610__i5 (.D(n90), .CK(RCLK_c), .Q(FS[5])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i5.GSR = "ENABLED"; + FD1S3AX FS_610__i4 (.D(n91), .CK(RCLK_c), .Q(FS[4])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i4.GSR = "ENABLED"; + FD1S3AX FS_610__i3 (.D(n92), .CK(RCLK_c), .Q(FS[3])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i3.GSR = "ENABLED"; + FD1S3AX FS_610__i2 (.D(n93), .CK(RCLK_c), .Q(FS[2])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i2.GSR = "ENABLED"; + FD1S3AX FS_610__i1 (.D(n94), .CK(RCLK_c), .Q(FS[1])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i1.GSR = "ENABLED"; + FD1S3AX WRD_i7 (.D(Din_c_7), .CK(nCCAS_N_3), .Q(WRD[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i7.GSR = "ENABLED"; + ORCALUT4 i3_4_lut_adj_21 (.A(MAin_c_1), .B(n2463), .C(n1326), .D(n15), + .Z(CmdEnable_N_248)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ; + defparam i3_4_lut_adj_21.init = 16'h0800; + FD1S3AX WRD_i6 (.D(Din_c_6), .CK(nCCAS_N_3), .Q(WRD[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i6.GSR = "ENABLED"; + FD1S3AX WRD_i5 (.D(Din_c_5), .CK(nCCAS_N_3), .Q(WRD[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i5.GSR = "ENABLED"; + FD1S3AX WRD_i4 (.D(Din_c_4), .CK(nCCAS_N_3), .Q(WRD[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i4.GSR = "ENABLED"; + FD1S3AX WRD_i3 (.D(Din_c_3), .CK(nCCAS_N_3), .Q(WRD[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i3.GSR = "ENABLED"; + FD1S3AX WRD_i2 (.D(Din_c_2), .CK(nCCAS_N_3), .Q(WRD[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i2.GSR = "ENABLED"; + FD1S3AX WRD_i1 (.D(Din_c_1), .CK(nCCAS_N_3), .Q(WRD[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i1.GSR = "ENABLED"; + FD1S3JX RowA_i9 (.D(MAin_c_9), .CK(nCRAS_N_9), .PD(n2477), .Q(RowA[9])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i9.GSR = "ENABLED"; + FD1S3IX RowA_i8 (.D(MAin_c_8), .CK(nCRAS_N_9), .CD(n2477), .Q(RowA[8])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i8.GSR = "ENABLED"; + FD1S3IX RowA_i7 (.D(MAin_c_7), .CK(nCRAS_N_9), .CD(n2477), .Q(RowA[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i7.GSR = "ENABLED"; + FD1S3IX RowA_i6 (.D(MAin_c_6), .CK(nCRAS_N_9), .CD(n2477), .Q(RowA[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i6.GSR = "ENABLED"; + FD1S3JX RowA_i5 (.D(MAin_c_5), .CK(nCRAS_N_9), .PD(n2477), .Q(RowA[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i5.GSR = "ENABLED"; + FD1S3IX RowA_i4 (.D(MAin_c_4), .CK(nCRAS_N_9), .CD(n2477), .Q(RowA[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i4.GSR = "ENABLED"; + FD1S3IX RowA_i3 (.D(MAin_c_3), .CK(nCRAS_N_9), .CD(n2477), .Q(RowA[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i3.GSR = "ENABLED"; + FD1S3IX RowA_i2 (.D(MAin_c_2), .CK(nCRAS_N_9), .CD(n2477), .Q(RowA[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i2.GSR = "ENABLED"; + FD1S3IX RowA_i1 (.D(MAin_c_1), .CK(nCRAS_N_9), .CD(n2477), .Q(RowA[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i1.GSR = "ENABLED"; + FD1S3AX Bank_i7 (.D(Din_c_7), .CK(PHI2_c), .Q(Bank[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i7.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_rep_25_3_lut (.A(Din_c_6), .B(Din_c_3), .C(Din_c_5), + .Z(n2468)) /* synthesis lut_function=(!((B+(C))+!A)) */ ; + defparam i1_2_lut_rep_25_3_lut.init = 16'h0202; + ORCALUT4 i5_3_lut_rep_15_4_lut (.A(nFWE_c), .B(n1326), .C(n10), .D(MAin_c_0), + .Z(n2458)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ; + defparam i5_3_lut_rep_15_4_lut.init = 16'h1000; + FD1S3AX Bank_i6 (.D(Din_c_6), .CK(PHI2_c), .Q(Bank[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i6.GSR = "ENABLED"; + FD1S3AX Bank_i5 (.D(Din_c_5), .CK(PHI2_c), .Q(Bank[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i5.GSR = "ENABLED"; + FD1S3AX Bank_i4 (.D(Din_c_4), .CK(PHI2_c), .Q(Bank[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i4.GSR = "ENABLED"; + FD1S3AX Bank_i3 (.D(Din_c_3), .CK(PHI2_c), .Q(Bank[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i3.GSR = "ENABLED"; + FD1S3AX Bank_i2 (.D(Din_c_2), .CK(PHI2_c), .Q(Bank[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i2.GSR = "ENABLED"; + FD1S3AX Bank_i1 (.D(Din_c_1), .CK(PHI2_c), .Q(Bank[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i1.GSR = "ENABLED"; + ORCALUT4 FS_6__bdd_4_lut (.A(FS[7]), .B(FS[9]), .C(FS[5]), .D(FS[8]), + .Z(n2451)) /* synthesis lut_function=(!(A (B+(D))+!A (((D)+!C)+!B))) */ ; + defparam FS_6__bdd_4_lut.init = 16'h0062; + BB Dout_pad_6__714 (.I(WRD[6]), .T(n984), .B(RD[6]), .O(Dout_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + BB Dout_pad_5__715 (.I(WRD[5]), .T(n984), .B(RD[5]), .O(Dout_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + ORCALUT4 i1_2_lut_rep_16_3_lut (.A(nFWE_c), .B(n1326), .C(MAin_c_1), + .Z(n2459)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ; + defparam i1_2_lut_rep_16_3_lut.init = 16'h1010; + BB Dout_pad_4__716 (.I(WRD[4]), .T(n984), .B(RD[4]), .O(Dout_2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + BB Dout_pad_3__717 (.I(WRD[3]), .T(n984), .B(RD[3]), .O(Dout_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + BB Dout_pad_2__718 (.I(WRD[2]), .T(n984), .B(RD[2]), .O(Dout_4)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + ORCALUT4 i1_2_lut_rep_33 (.A(Din_c_3), .B(Din_c_5), .Z(n2476)) /* synthesis lut_function=(A (B)) */ ; + defparam i1_2_lut_rep_33.init = 16'h8888; + BB Dout_pad_1__719 (.I(WRD[1]), .T(n984), .B(RD[1]), .O(Dout_5)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + BB Dout_pad_0__720 (.I(WRD[0]), .T(n984), .B(RD[0]), .O(Dout_6)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + OB Dout_pad_7 (.I(Dout_c), .O(Dout[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_6 (.I(Dout_0), .O(Dout[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_5 (.I(Dout_1), .O(Dout[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_4 (.I(Dout_2), .O(Dout[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_3 (.I(Dout_3), .O(Dout[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_2 (.I(Dout_4), .O(Dout[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_1 (.I(Dout_5), .O(Dout[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_0 (.I(Dout_6), .O(Dout[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB LED_pad (.I(LED_N_84), .O(LED)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(22[9:12]) + OB RBA_pad_1 (.I(RBA_c_1), .O(RBA[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22]) + OB RBA_pad_0 (.I(RBA_c_0), .O(RBA[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22]) + OB RA_pad_11 (.I(RA_c), .O(RA[11])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_10 (.I(RA_0), .O(RA[10])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_9 (.I(RA_1_9), .O(RA[9])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_8 (.I(RA_1_8), .O(RA[8])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_7 (.I(RA_1_7), .O(RA[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_6 (.I(RA_1_6), .O(RA[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_5 (.I(RA_1_5), .O(RA[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_4 (.I(RA_1_4), .O(RA[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_3 (.I(RA_1_3), .O(RA[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_2 (.I(RA_1_2), .O(RA[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_1 (.I(RA_1_1), .O(RA[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_0 (.I(RA_1_0), .O(RA[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB nRCS_pad (.I(nRCS_c), .O(nRCS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[13:17]) + OB RCKE_pad (.I(RCKE_c), .O(RCKE)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(45[13:17]) + OB nRWE_pad (.I(nRWE_c), .O(nRWE)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[45:49]) + OB nRRAS_pad (.I(nRRAS_c), .O(nRRAS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[23:28]) + OB nRCAS_pad (.I(nRCAS_c), .O(nRCAS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[34:39]) + OB RDQMH_pad (.I(RDQMH_c), .O(RDQMH)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[16:21]) + OB RDQML_pad (.I(RDQML_c), .O(RDQML)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[9:14]) + OB nUFMCS_pad (.I(nUFMCS_c), .O(nUFMCS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(63[13:19]) + OB UFMCLK_pad (.I(UFMCLK_c), .O(UFMCLK)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(64[13:19]) + OB UFMSDI_pad (.I(UFMSDI_c), .O(UFMSDI)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(65[13:19]) + IB PHI2_pad (.I(PHI2), .O(PHI2_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) + IB MAin_pad_9 (.I(MAin[9]), .O(MAin_c_9)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_8 (.I(MAin[8]), .O(MAin_c_8)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_7 (.I(MAin[7]), .O(MAin_c_7)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_6 (.I(MAin[6]), .O(MAin_c_6)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_5 (.I(MAin[5]), .O(MAin_c_5)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_4 (.I(MAin[4]), .O(MAin_c_4)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_3 (.I(MAin[3]), .O(MAin_c_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_2 (.I(MAin[2]), .O(MAin_c_2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_1 (.I(MAin[1]), .O(MAin_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_0 (.I(MAin[0]), .O(MAin_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB CROW_pad_1 (.I(CROW[1]), .O(CROW_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18]) + IB CROW_pad_0 (.I(CROW[0]), .O(CROW_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18]) + IB Din_pad_7 (.I(Din[7]), .O(Din_c_7)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_6 (.I(Din[6]), .O(Din_c_6)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_5 (.I(Din[5]), .O(Din_c_5)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_4 (.I(Din[4]), .O(Din_c_4)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_3 (.I(Din[3]), .O(Din_c_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_2 (.I(Din[2]), .O(Din_c_2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_1 (.I(Din[1]), .O(Din_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_0 (.I(Din[0]), .O(Din_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB nCCAS_pad (.I(nCCAS), .O(nCCAS_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) + IB nCRAS_pad (.I(nCRAS), .O(nCRAS_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + IB nFWE_pad (.I(nFWE), .O(nFWE_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(36[8:12]) + IB RCLK_pad (.I(RCLK), .O(RCLK_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12]) + IB UFMSDO_pad (.I(UFMSDO), .O(UFMSDO_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(66[8:14]) + ORCALUT4 i1_2_lut_rep_19_4_lut (.A(n2471), .B(n2272), .C(n2470), .D(FS[11]), + .Z(n2462)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i1_2_lut_rep_19_4_lut.init = 16'hfeff; + CCU2 FS_610_add_4_2 (.A0(FS[0]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[1]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(GND_net), + .COUT1(n2008), .S0(n95), .S1(n94)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_2.INIT0 = 16'h0555; + defparam FS_610_add_4_2.INIT1 = 16'hfaaa; + defparam FS_610_add_4_2.INJECT1_0 = "NO"; + defparam FS_610_add_4_2.INJECT1_1 = "NO"; + ORCALUT4 i2057_2_lut (.A(nRowColSel_N_32), .B(RASr2), .Z(n1093)) /* synthesis lut_function=(!(A+!(B))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i2057_2_lut.init = 16'h4444; + ORCALUT4 n2454_bdd_3_lut_4_lut (.A(n2461), .B(n2462), .C(InitReady), + .D(CmdUFMSDI), .Z(UFMSDI_N_231)) /* synthesis lut_function=(A (B (C (D))+!B ((D)+!C))+!A (C (D))) */ ; + defparam n2454_bdd_3_lut_4_lut.init = 16'hf202; + FD1P3IX UFMCLK_416 (.D(UFMCLK_N_224), .SP(RCLK_c_enable_24), .CD(n1846), + .CK(RCLK_c), .Q(UFMCLK_c)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam UFMCLK_416.GSR = "ENABLED"; + FD1P3AX CmdEnable_405 (.D(CmdEnable_N_248), .SP(PHI2_N_120_enable_7), + .CK(PHI2_N_120), .Q(CmdEnable)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdEnable_405.GSR = "ENABLED"; + ORCALUT4 i1513_2_lut (.A(nCCAS_c), .B(nFWE_c), .Z(n984)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1513_2_lut.init = 16'heeee; + ORCALUT4 n1_bdd_4_lut (.A(n1), .B(n1502), .C(nRWE_N_182), .D(nRowColSel_N_35), + .Z(nRWE_N_178)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))+!A (C+!(D))) */ ; + defparam n1_bdd_4_lut.init = 16'hf0dd; + CCU2 FS_610_add_4_12 (.A0(FS[10]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[11]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2012), + .COUT1(n2013), .S0(n85), .S1(n84)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_12.INIT0 = 16'hfaaa; + defparam FS_610_add_4_12.INIT1 = 16'hfaaa; + defparam FS_610_add_4_12.INJECT1_0 = "NO"; + defparam FS_610_add_4_12.INJECT1_1 = "NO"; + ORCALUT4 i1_2_lut_adj_22 (.A(n62), .B(FS[10]), .Z(RCLK_c_enable_25)) /* synthesis lut_function=(A (B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i1_2_lut_adj_22.init = 16'h8888; + ORCALUT4 i1209_4_lut_then_4_lut (.A(nRCS_N_139), .B(Ready), .C(nRowColSel_N_35), + .D(nRowColSel_N_34), .Z(n2480)) /* synthesis lut_function=(!(A (B (C+!(D)))+!A (B (C+!(D))+!B (C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(48[6:16]) + defparam i1209_4_lut_then_4_lut.init = 16'h2f23; + ORCALUT4 nRWE_I_0_455_4_lut (.A(n33), .B(nRWE_N_178), .C(Ready), .D(n2208), + .Z(nRWE_N_171)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B+!(C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6]) + defparam nRWE_I_0_455_4_lut.init = 16'hcfc5; + ORCALUT4 nRWE_I_50_1_lut (.A(nRWE_N_177), .Z(nRWE_N_176)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(255[14] 262[8]) + defparam nRWE_I_50_1_lut.init = 16'h5555; + CCU2 FS_610_add_4_4 (.A0(FS[2]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[3]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2008), + .COUT1(n2009), .S0(n93), .S1(n92)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_4.INIT0 = 16'hfaaa; + defparam FS_610_add_4_4.INIT1 = 16'hfaaa; + defparam FS_610_add_4_4.INJECT1_0 = "NO"; + defparam FS_610_add_4_4.INJECT1_1 = "NO"; + CCU2 FS_610_add_4_10 (.A0(FS[8]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[9]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2011), + .COUT1(n2012), .S0(n87), .S1(n86)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_10.INIT0 = 16'hfaaa; + defparam FS_610_add_4_10.INIT1 = 16'hfaaa; + defparam FS_610_add_4_10.INJECT1_0 = "NO"; + defparam FS_610_add_4_10.INJECT1_1 = "NO"; + ORCALUT4 i1_2_lut_adj_23 (.A(nRowColSel_N_33), .B(CASr2), .Z(n11)) /* synthesis lut_function=(A+!(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(48[6:16]) + defparam i1_2_lut_adj_23.init = 16'hbbbb; + CCU2 FS_610_add_4_18 (.A0(FS[16]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[17]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2015), + .S0(n79), .S1(n78)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_18.INIT0 = 16'hfaaa; + defparam FS_610_add_4_18.INIT1 = 16'hfaaa; + defparam FS_610_add_4_18.INJECT1_0 = "NO"; + defparam FS_610_add_4_18.INJECT1_1 = "NO"; + ORCALUT4 i5_3_lut_rep_21_4_lut (.A(FS[16]), .B(FS[14]), .C(n2272), + .D(n2471), .Z(n2464)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i5_3_lut_rep_21_4_lut.init = 16'hfffe; + ORCALUT4 i1137_1_lut (.A(nRowColSel_N_35), .Z(n1426)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i1137_1_lut.init = 16'h5555; + ORCALUT4 RASr2_I_0_1_lut (.A(RASr2), .Z(RASr2_N_63)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(143[40:46]) + defparam RASr2_I_0_1_lut.init = 16'h5555; + ORCALUT4 n2452_bdd_2_lut_rep_18_3_lut (.A(n2451), .B(FS[6]), .C(FS[10]), + .Z(n2461)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ; + defparam n2452_bdd_2_lut_rep_18_3_lut.init = 16'h0808; + ORCALUT4 i2_3_lut_4_lut_adj_24 (.A(Din_c_5), .B(n2475), .C(MAin_c_0), + .D(ADSubmitted), .Z(n2227)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) + defparam i2_3_lut_4_lut_adj_24.init = 16'h0004; + ORCALUT4 i1_2_lut_adj_25 (.A(nRowColSel_N_32), .B(nRowColSel_N_33), + .Z(n1503)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i1_2_lut_adj_25.init = 16'heeee; + ORCALUT4 i5_4_lut (.A(FS[15]), .B(FS[13]), .C(FS[16]), .D(FS[11]), + .Z(n12)) /* synthesis lut_function=(A (B (C (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i5_4_lut.init = 16'h8000; + ORCALUT4 i1_2_lut_adj_26 (.A(nRCAS_N_165), .B(nRWE_N_177), .Z(n33)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1_2_lut_adj_26.init = 16'heeee; + ORCALUT4 i1259_3_lut (.A(InitReady), .B(RCKEEN_N_122), .C(Ready), + .Z(RCKEEN_N_121)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(84[6:11]) + defparam i1259_3_lut.init = 16'hcaca; + FD1P3AX InitReady_394 (.D(n2568), .SP(RCLK_c_enable_25), .CK(RCLK_c), + .Q(InitReady)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(134[9] 138[5]) + defparam InitReady_394.GSR = "ENABLED"; + ORCALUT4 i11_3_lut (.A(n62), .B(n1417), .C(InitReady), .Z(n2164)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(21[6:11]) + defparam i11_3_lut.init = 16'hcaca; + PFUMX RCKEEN_I_0_445 (.BLUT(RCKEEN_N_123), .ALUT(RCKEEN_N_130), .C0(nRowColSel_N_35), + .Z(RCKEEN_N_122)); + ORCALUT4 i1129_3_lut (.A(nUFMCS_c), .B(CmdUFMCS), .C(n2472), .Z(n1417)) /* synthesis lut_function=(!(A (B (C))+!A (B+!(C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam i1129_3_lut.init = 16'h3a3a; + FD1S3IX S_FSM_i2 (.D(n1093), .CK(RCLK_c), .CD(n1426), .Q(nRowColSel_N_34)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam S_FSM_i2.GSR = "ENABLED"; + INV i2134 (.A(nCCAS_c), .Z(nCCAS_N_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) + ORCALUT4 i1988_2_lut (.A(C1Submitted), .B(Din_c_6), .Z(n2284)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1988_2_lut.init = 16'heeee; + PFUMX i26 (.BLUT(n2227), .ALUT(n2257), .C0(Din_c_2), .Z(n13_adj_2)); + INV i2135 (.A(nCRAS_c), .Z(nCRAS_N_9)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + VLO i1 (.Z(GND_net)); + TSALL TSALL_INST (.TSALL(GND_net)); + ORCALUT4 i2_3_lut_adj_27 (.A(n2208), .B(Ready), .C(nRCAS_N_165), .Z(n2209)) /* synthesis lut_function=(A+(B+(C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i2_3_lut_adj_27.init = 16'hfefe; + PUR PUR_INST (.PUR(VCC_net)); + defparam PUR_INST.RST_PULSE = 1; + ORCALUT4 i2032_2_lut_3_lut_4_lut (.A(FS[17]), .B(FS[12]), .C(FS[14]), + .D(FS[16]), .Z(n2328)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; + defparam i2032_2_lut_3_lut_4_lut.init = 16'hfffe; + ORCALUT4 i1976_2_lut (.A(FS[13]), .B(FS[15]), .Z(n2272)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1976_2_lut.init = 16'heeee; + ORCALUT4 m1_lut (.Z(n2568)) /* synthesis lut_function=1, syn_instantiated=1 */ ; + defparam m1_lut.init = 16'hffff; + PFUMX i2099 (.BLUT(n2479), .ALUT(n2480), .C0(n15_adj_1), .Z(n2481)); + PFUMX i26_adj_28 (.BLUT(n2245), .ALUT(n2243), .C0(Din_c_5), .Z(n15)); + +endmodule +// +// Verilog Description of module TSALL +// module not written out since it is a black-box. +// + +// +// Verilog Description of module PUR +// module not written out since it is a black-box. +// + diff --git a/CPLD/LCMXO640C/impl1/automake.log b/CPLD/LCMXO640C/impl1/automake.log new file mode 100644 index 0000000..ba3df24 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/automake.log @@ -0,0 +1,1016 @@ + +synthesis -f "RAM2GS_LCMXO640C_impl1_lattice.synproj" +synthesis: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:21 2023 + + +Command Line: synthesis -f RAM2GS_LCMXO640C_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml + + +Synthesis options: +The -a option is MachXO. +The -s option is 3. +The -t option is TQFP100. +The -d option is LCMXO640C. +Using package TQFP100. +Using performance grade 3. + + +########################################################## + +### Lattice Family : MachXO + +### Device : LCMXO640C + +### Package : TQFP100 + +### Speed : 3 + +########################################################## + + + + +Optimization goal = Balanced +Top-level module name = RAM2GS. +Target frequency = 200.000000 MHz. +Maximum fanout = 1000. +Timing path count = 3 +BRAM utilization = 100.000000 % +DSP usage = true +DSP utilization = 100.000000 % +fsm_encoding_style = auto +resolve_mixed_drivers = 0 +fix_gated_clocks = 1 + +Mux style = Auto +Use Carry Chain = true +carry_chain_length = 0 +Loop Limit = 1950. +Use IO Insertion = TRUE +Use IO Reg = AUTO + +Resource Sharing = TRUE +Propagate Constants = TRUE +Remove Duplicate Registers = TRUE +force_gsr = auto +ROM style = auto +RAM style = auto +The -comp option is FALSE. +The -syn option is FALSE. +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C (searchpath added) +-p C:/lscc/diamond/3.12/ispfpga/mj5g00/data (searchpath added) +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1 (searchpath added) +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C (searchpath added) +Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v +NGD file = RAM2GS_LCMXO640C_impl1.ngd +-sdc option: SDC file input not used. +-lpf option: Output file option is ON. +Hardtimer checking is enabled (default). The -dt option is not used. +The -r option is OFF. [ Remove LOC Properties is OFF. ] +Technology check ok... + +Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482 +Compile design. +Compile Design Begin +Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482 +Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482 +Top module name (Verilog): RAM2GS + + + + +Last elaborated design is RAM2GS() +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... +Loading device for application map from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.17. +Top-level module name = RAM2GS. + +original encoding -> new encoding (one-hot encoding) + + 0000 -> 0000000000000001 + + 0001 -> 0000000000000010 + + 0010 -> 0000000000000100 + + 0011 -> 0000000000001000 + + 0100 -> 0000000000010000 + + 0101 -> 0000000000100000 + + 0110 -> 0000000001000000 + + 0111 -> 0000000010000000 + + 1000 -> 0000000100000000 + + 1001 -> 0000001000000000 + + 1010 -> 0000010000000000 + + 1011 -> 0000100000000000 + + 1100 -> 0001000000000000 + + 1101 -> 0010000000000000 + + 1110 -> 0100000000000000 + + 1111 -> 1000000000000000 + + +original encoding -> new encoding (one-hot encoding) + + 00 -> 0001 + + 01 -> 0010 + + 10 -> 0100 + + 11 -> 1000 + + + + +GSR will not be inferred because no asynchronous signal was found in the netlist. + +Applying 200.000000 MHz constraint to all clocks + + +Results of NGD DRC are available in RAM2GS_drc.log. +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... + + +Running DRC... + +DRC complete with no errors or warnings + +Design Results: + 318 blocks expanded +completed the first expansion +All blocks are expanded and NGD expansion is successful. +Writing NGD file RAM2GS_LCMXO640C_impl1.ngd. + +################### Begin Area Report (RAM2GS)###################### +Number of register bits => 102 of 862 (11 % ) +BB => 8 +CCU2 => 9 +FD1P3AX => 28 +FD1P3AY => 3 +FD1P3IX => 2 +FD1S3AX => 47 +FD1S3AY => 1 +FD1S3IX => 16 +FD1S3JX => 5 +GSR => 1 +IB => 26 +INV => 3 +OB => 33 +ORCALUT4 => 127 +PFUMX => 6 +################### End Area Report ################## + +################### Begin BlackBox Report ###################### +TSALL => 1 +################### End BlackBox Report ################## + +################### Begin Clock Report ###################### +Clock Nets +Number of Clocks: 4 + Net : RCLK_c, loads : 62 + Net : PHI2_c, loads : 11 + Net : nCCAS_c, loads : 2 + Net : nCRAS_c, loads : 2 +Clock Enable Nets +Number of Clock Enables: 13 +Top 10 highest fanout Clock Enables: + Net : RCLK_c_enable_23, loads : 16 + Net : RCLK_c_enable_4, loads : 3 + Net : PHI2_N_120_enable_6, loads : 3 + Net : RCLK_c_enable_24, loads : 2 + Net : RCLK_c_enable_12, loads : 1 + Net : PHI2_N_120_enable_1, loads : 1 + Net : PHI2_N_120_enable_4, loads : 1 + Net : RCLK_c_enable_3, loads : 1 + Net : PHI2_N_120_enable_5, loads : 1 + Net : RCLK_c_enable_11, loads : 1 +Highest fanout non-clock nets +Top 10 highest fanout non-clock nets: + Net : InitReady, loads : 17 + Net : Ready, loads : 17 + Net : RCLK_c_enable_23, loads : 16 + Net : nCRAS_N_9, loads : 15 + Net : RASr2, loads : 13 + Net : nRowColSel, loads : 13 + Net : n2477, loads : 13 + Net : MAin_c_0, loads : 12 + Net : nRowColSel_N_35, loads : 12 + Net : Din_c_6, loads : 11 +################### End Clock Report ################## + +Timing Report Summary +-------------- +-------------------------------------------------------------------------------- +Constraint | Constraint| Actual|Levels +-------------------------------------------------------------------------------- + | | | +create_clock -period 5.000000 -name | | | +clk3 [get_nets nCCAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk2 [get_nets nCRAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk1 [get_nets PHI2_c] | 200.000 MHz| 45.147 MHz| 6 * + | | | +create_clock -period 5.000000 -name | | | +clk0 [get_nets RCLK_c] | 200.000 MHz| 106.792 MHz| 5 * + | | | +-------------------------------------------------------------------------------- + + +2 constraints not met. + + +Peak Memory Usage: 51.215 MB + +-------------------------------------------------------------- +Elapsed CPU time for LSE flow : 0.609 secs +-------------------------------------------------------------- + +map -a "MachXO" -p LCMXO640C -t TQFP100 -s 3 -oc Commercial "RAM2GS_LCMXO640C_impl1.ngd" -o "RAM2GS_LCMXO640C_impl1_map.ncd" -pr "RAM2GS_LCMXO640C_impl1.prf" -mp "RAM2GS_LCMXO640C_impl1.mrp" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lpf" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/RAM2GS_LCMXO640C.lpf" -c 0 +map: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + Process the file: RAM2GS_LCMXO640C_impl1.ngd + Picdevice="LCMXO640C" + + Pictype="TQFP100" + + Picspeed=3 + + Remove unused logic + + Do not produce over sized NCDs. + +Part used: LCMXO640CTQFP100, Performance used: 3. + +Loading device for application map from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.17. +Running general design DRC... + +Removing unused logic... + +Optimizing... + + + + +Design Summary: + Number of PFU registers: 102 out of 640 (16%) + Number of SLICEs: 71 out of 320 (22%) + SLICEs as Logic/ROM: 71 out of 320 (22%) + SLICEs as RAM: 0 out of 192 (0%) + SLICEs as Carry: 9 out of 320 (3%) + Number of LUT4s: 142 out of 640 (22%) + Number used as logic LUTs: 124 + Number used as distributed RAM: 0 + Number used as ripple logic: 18 + Number used as shift registers: 0 + Number of external PIOs: 67 out of 74 (91%) + Number of GSRs: 0 out of 1 (0%) + JTAG used : No + Readback used : No + Oscillator used : No + Startup used : No + Number of TSALL: 0 out of 1 (0%) + Notes:- + 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) + 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. + Number of clocks: 4 + Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK ) + Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 ) + Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS ) + Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) + Number of Clock Enables: 13 + Net PHI2_N_120_enable_4: 1 loads, 1 LSLICEs + Net RCLK_c_enable_4: 3 loads, 3 LSLICEs + Net RCLK_c_enable_23: 8 loads, 8 LSLICEs + Net RCLK_c_enable_12: 1 loads, 1 LSLICEs + Net RCLK_c_enable_3: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_5: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_6: 2 loads, 2 LSLICEs + Net RCLK_c_enable_24: 2 loads, 2 LSLICEs + Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs + Net Ready_N_292: 1 loads, 1 LSLICEs + Net RCLK_c_enable_11: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs + Net RCLK_c_enable_25: 1 loads, 1 LSLICEs + Number of LSRs: 9 + Net RASr2: 1 loads, 1 LSLICEs + Net Ready: 7 loads, 7 LSLICEs + Net C1Submitted_N_237: 2 loads, 2 LSLICEs + Net n2469: 1 loads, 1 LSLICEs + Net nRowColSel_N_35: 1 loads, 1 LSLICEs + Net n1846: 2 loads, 2 LSLICEs + Net LEDEN_N_82: 1 loads, 1 LSLICEs + Net nRowColSel_N_34: 1 loads, 1 LSLICEs + Net nRWE_N_177: 1 loads, 1 LSLICEs + Number of nets driven by tri-state buffers: 0 + Top 10 highest fanout non-clock nets: + Net Ready: 23 loads + Net InitReady: 17 loads + Net RASr2: 14 loads + Net nRowColSel: 13 loads + Net MAin_c_0: 12 loads + Net nRowColSel_N_35: 12 loads + Net Din_c_3: 11 loads + Net Din_c_6: 11 loads + Net MAin_c_1: 11 loads + Net Din_c_4: 10 loads + + + Number of warnings: 0 + Number of errors: 0 + + + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 30 MB + +Dumping design to file RAM2GS_LCMXO640C_impl1_map.ncd. + +ncd2vdb "RAM2GS_LCMXO640C_impl1_map.ncd" ".vdbs/RAM2GS_LCMXO640C_impl1_map.vdb" + +Loading device for application ncd2vdb from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. + +ncd2eqn "RAM2GS_LCMXO640C_impl1_map.ncd" +ncd2eqn: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Start loading RAM2GS_LCMXO640C_impl1_map.ncd. + +Loading design for application ncd2eqn from file RAM2GS_LCMXO640C_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 3 +Loading device for application ncd2eqn from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +Finish loading RAM2GS_LCMXO640C_impl1_map.ncd. +ncd2eqn runs successfully. + +trce -f "RAM2GS_LCMXO640C_impl1.mt" -o "RAM2GS_LCMXO640C_impl1.tw1" "RAM2GS_LCMXO640C_impl1_map.ncd" "RAM2GS_LCMXO640C_impl1.prf" +trce: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Loading design for application trce from file ram2gs_lcmxo640c_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 3 +Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:23 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf +Design file: ram2gs_lcmxo640c_impl1_map.ncd +Preference file: ram2gs_lcmxo640c_impl1.prf +Device,speed: LCMXO640C,3 +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +Report Type: based on TRACE automatically generated preferences +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Setup): +--------------- + +Timing errors: 310 Score: 1346529 +Cumulative negative slack: 874289 + +Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:23 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf +Design file: ram2gs_lcmxo640c_impl1_map.ncd +Preference file: ram2gs_lcmxo640c_impl1.prf +Device,speed: LCMXO640C,M +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 310 (setup), 0 (hold) +Score: 1346529 (setup), 0 (hold) +Cumulative negative slack: 874289 (874289+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 33 MB + + +ldbanno "RAM2GS_LCMXO640C_impl1_map.ncd" -n Verilog -o "RAM2GS_LCMXO640C_impl1_mapvo.vo" -w -neg +ldbanno: version Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Writing a Verilog netlist using the orca library type based on the RAM2GS_LCMXO640C_impl1_map design file. + + +Loading design for application ldbanno from file RAM2GS_LCMXO640C_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 3 +Loading device for application ldbanno from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +Converting design RAM2GS_LCMXO640C_impl1_map.ncd into .ldb format. +Writing Verilog netlist to file RAM2GS_LCMXO640C_impl1_mapvo.vo +Writing SDF timing to file RAM2GS_LCMXO640C_impl1_mapvo.sdf + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 30 MB + +ldbanno "RAM2GS_LCMXO640C_impl1_map.ncd" -n VHDL -o "RAM2GS_LCMXO640C_impl1_mapvho.vho" -w -neg +ldbanno: version Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Writing a VHDL netlist using the orca library type based on the RAM2GS_LCMXO640C_impl1_map design file. + + +Loading design for application ldbanno from file RAM2GS_LCMXO640C_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 3 +Loading device for application ldbanno from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +Converting design RAM2GS_LCMXO640C_impl1_map.ncd into .ldb format. +Writing VHDL netlist to file RAM2GS_LCMXO640C_impl1_mapvho.vho +Writing SDF timing to file RAM2GS_LCMXO640C_impl1_mapvho.sdf + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 30 MB + +mpartrce -p "RAM2GS_LCMXO640C_impl1.p2t" -f "RAM2GS_LCMXO640C_impl1.p3t" -tf "RAM2GS_LCMXO640C_impl1.pt" "RAM2GS_LCMXO640C_impl1_map.ncd" "RAM2GS_LCMXO640C_impl1.ncd" + +---- MParTrce Tool ---- +Removing old design directory at request of -rem command line option to this program. +Running par. Please wait . . . + +Lattice Place and Route Report for Design "RAM2GS_LCMXO640C_impl1_map.ncd" +Tue Aug 15 05:03:25 2023 + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir/5_1.ncd RAM2GS_LCMXO640C_impl1.prf +Preference file: RAM2GS_LCMXO640C_impl1.prf. +Placement level-cost: 5-1. +Routing Iterations: 6 + +Loading design for application par from file RAM2GS_LCMXO640C_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 3 +Loading device for application par from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +License checked out. + + +Ignore Preference Error(s): True +Device utilization summary: + + PIO (prelim) 67/159 42% used + 67/74 90% bonded + SLICE 71/320 22% used + + + +Number of Signals: 262 +Number of Connections: 662 + +Pin Constraint Summary: + 67 out of 67 pins locked (100% locked). + +The following 2 signals are selected to use the primary clock routing resources: + RCLK_c (driver: RCLK, clk load #: 40) + PHI2_c (driver: PHI2, clk load #: 13) + +The following 1 signal is selected to use the secondary clock routing resources: + nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0) + +No signal is selected as Global Set/Reset. +Starting Placer Phase 0. +......... +Finished Placer Phase 0. REAL time: 0 secs + +Starting Placer Phase 1. +......... +Placer score = 1223575. +Finished Placer Phase 1. REAL time: 3 secs + +Starting Placer Phase 2. +. +Placer score = 1220793 +Finished Placer Phase 2. REAL time: 3 secs + + +------------------ Clock Report ------------------ + +Global Clock Resources: + CLK_PIN : 1 out of 4 (25%) + General PIO: 1 out of 160 (0%) + +Global Clocks: + PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT5B)", clk load = 40 + PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB6C)", clk load = 13 + SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB8B)", clk load = 7, ce load = 0, sr load = 0 + + PRIMARY : 2 out of 4 (50%) + SECONDARY: 1 out of 4 (25%) + +--------------- End of Clock Report --------------- + + +I/O Usage Summary (final): + 67 out of 159 (42.1%) PIO sites used. + 67 out of 74 (90.5%) bonded PIO sites used. + Number of PIO comps: 67; differential: 0. + Number of Vref pins used: 0. + +I/O Bank Usage Summary: ++----------+----------------+------------+------------+------------+ +| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | ++----------+----------------+------------+------------+------------+ +| 0 | 18 / 18 (100%) | 3.3V | - | - | +| 1 | 18 / 21 ( 85%) | 3.3V | - | - | +| 2 | 13 / 14 ( 92%) | - | - | - | +| 3 | 18 / 21 ( 85%) | 3.3V | - | - | ++----------+----------------+------------+------------+------------+ + +Total placer CPU time: 3 secs + +Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd. + +0 connections routed; 662 unrouted. +Starting router resource preassignment + + + + + +Completed router resource preassignment. Real time: 3 secs + +Start NBR router at 05:03:28 08/15/23 + +***************************************************************** +Info: NBR allows conflicts(one node used by more than one signal) + in the earlier iterations. In each iteration, it tries to + solve the conflicts while keeping the critical connections + routed as short as possible. The routing process is said to + be completed when no conflicts exist and all connections + are routed. +Note: NBR uses a different method to calculate timing slacks. The + worst slack and total negative slack may not be the same as + that in TRCE report. You should always run TRCE to verify + your design. +***************************************************************** + +Start NBR special constraint process at 05:03:28 08/15/23 + +Start NBR section for initial routing at 05:03:28 08/15/23 +Level 1, iteration 1 +0(0.00%) conflict; 559(84.44%) untouched conns; 717961 (nbr) score; +Estimated worst slack/total negative slack: -9.776ns/-717.961ns; real time: 3 secs +Level 2, iteration 1 +7(0.03%) conflicts; 496(74.92%) untouched conns; 699022 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-699.022ns; real time: 3 secs +Level 3, iteration 1 +9(0.03%) conflicts; 252(38.07%) untouched conns; 765745 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-765.746ns; real time: 3 secs +Level 4, iteration 1 +9(0.03%) conflicts; 0(0.00%) untouched conn; 781820 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-781.821ns; real time: 4 secs + +Info: Initial congestion level at 75% usage is 0 +Info: Initial congestion area at 75% usage is 0 (0.00%) + +Start NBR section for normal routing at 05:03:29 08/15/23 +Level 4, iteration 1 +5(0.02%) conflicts; 0(0.00%) untouched conn; 781048 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-781.049ns; real time: 4 secs +Level 4, iteration 2 +4(0.01%) conflicts; 0(0.00%) untouched conn; 780690 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-780.691ns; real time: 4 secs +Level 4, iteration 3 +4(0.01%) conflicts; 0(0.00%) untouched conn; 780715 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-780.716ns; real time: 4 secs +Level 4, iteration 4 +2(0.01%) conflicts; 0(0.00%) untouched conn; 780715 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-780.716ns; real time: 4 secs +Level 4, iteration 5 +2(0.01%) conflicts; 0(0.00%) untouched conn; 783401 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 4 secs +Level 4, iteration 6 +0(0.00%) conflict; 0(0.00%) untouched conn; 783401 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 4 secs + +Start NBR section for performance tuning (iteration 1) at 05:03:29 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 783401 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 4 secs + +Start NBR section for re-routing at 05:03:29 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 776978 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-776.979ns; real time: 4 secs + +Start NBR section for post-routing at 05:03:29 08/15/23 + +End NBR router with 0 unrouted connection + +NBR Summary +----------- + Number of unrouted connections : 0 (0.00%) + Number of connections with timing violations : 260 (39.27%) + Estimated worst slack : -9.822ns + Timing score : 909228 +----------- +Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. + + + + + +Total CPU time 4 secs +Total REAL time: 4 secs +Completely routed. +End of route. 662 routed (100.00%); 0 unrouted. + +Hold time timing score: 0, hold timing errors: 0 + +Timing score: 909228 + +Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd. + + +PAR_SUMMARY::Run status = Completed +PAR_SUMMARY::Number of unrouted conns = 0 +PAR_SUMMARY::Worst slack> = -9.822 +PAR_SUMMARY::Timing score> = 909.228 +PAR_SUMMARY::Worst slack> = 0.273 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Number of errors = 0 + +Total CPU time to completion: 4 secs +Total REAL time to completion: 4 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Exiting par with exit code 0 +Exiting mpartrce with exit code 0 + +trce -f "RAM2GS_LCMXO640C_impl1.pt" -o "RAM2GS_LCMXO640C_impl1.twr" "RAM2GS_LCMXO640C_impl1.ncd" "RAM2GS_LCMXO640C_impl1.prf" +trce: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Loading design for application trce from file ram2gs_lcmxo640c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 3 +Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:29 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf +Design file: ram2gs_lcmxo640c_impl1.ncd +Preference file: ram2gs_lcmxo640c_impl1.prf +Device,speed: LCMXO640C,3 +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +Report Type: based on TRACE automatically generated preferences +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Setup): +--------------- + +Timing errors: 328 Score: 909228 +Cumulative negative slack: 648187 + +Constraints cover 489 paths, 2 nets, and 415 connections (62.69% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:30 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf +Design file: ram2gs_lcmxo640c_impl1.ncd +Preference file: ram2gs_lcmxo640c_impl1.prf +Device,speed: LCMXO640C,m +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 489 paths, 2 nets, and 415 connections (62.69% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 328 (setup), 0 (hold) +Score: 909228 (setup), 0 (hold) +Cumulative negative slack: 648187 (648187+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 32 MB + + +iotiming "RAM2GS_LCMXO640C_impl1.ncd" "RAM2GS_LCMXO640C_impl1.prf" +I/O Timing Report: +: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 3 +Loading device for application iotiming from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +Running Performance Grade: 3 +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... + +Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 4 +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +Running Performance Grade: 4 +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... + +Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 5 +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +Running Performance Grade: 5 +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... + +Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: M +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +Running Performance Grade: M +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... +Done. + +tmcheck -par "RAM2GS_LCMXO640C_impl1.par" + +bitgen -w "RAM2GS_LCMXO640C_impl1.ncd" -f "RAM2GS_LCMXO640C_impl1.t2b" "RAM2GS_LCMXO640C_impl1.prf" + + +BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + + +Loading design for application Bitgen from file RAM2GS_LCMXO640C_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 3 +Loading device for application Bitgen from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. + +Running DRC. +DRC detected 0 errors and 0 warnings. +Reading Preference File from RAM2GS_LCMXO640C_impl1.prf. + +Preference Summary: ++---------------------------------+---------------------------------+ +| Preference | Current Setting | ++---------------------------------+---------------------------------+ +| CONFIG_SECURE | OFF** | ++---------------------------------+---------------------------------+ +| INBUF | ON** | ++---------------------------------+---------------------------------+ +| ES | No** | ++---------------------------------+---------------------------------+ + * Default setting. + ** The specified setting matches the default setting. + + +Creating bit map... +Saving bit stream in "RAM2GS_LCMXO640C_impl1.bit". +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 46 MB + +ddtcmd -dev LCMXO640C-XXT100 -if "RAM2GS_LCMXO640C_impl1.bit" -oft -jed -of "RAM2GS_LCMXO640C_impl1.jed" -comment "RAM2GS_LCMXO640C_impl1.alt" +Lattice Diamond Deployment Tool 3.12 Command Line + +Loading Programmer Device Database... + +Generating JED..... +Device Name: LCMXO640C-XXT100 +Reading Input File: RAM2GS_LCMXO640C_impl1.bit +Output File: RAM2GS_LCMXO640C_impl1.jed +Comment file RAM2GS_LCMXO640C_impl1.alt. +Generating JEDEC..... +File RAM2GS_LCMXO640C_impl1.jed generated successfully. +Lattice Diamond Deployment Tool has exited successfully. + diff --git a/CPLD/LCMXO640C/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO640C/impl1/hdla_gen_hierarchy.html new file mode 100644 index 0000000..8e04933 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/hdla_gen_hierarchy.html @@ -0,0 +1,9 @@ + 
    Setting log file to 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1/hdla_gen_hierarchy.html'.
+Starting: parse design source files
+(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v'
+(VERI-1482) Analyzing Verilog file 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v'
+INFO - D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
+INFO - D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v(1,1-411,10) (VERI-9000) elaborating module 'RAM2GS'
+Done: design load finished with (0) errors, and (0) warnings
+
+
    \ No newline at end of file diff --git a/CPLD/LCMXO640C/impl1/impl1.xcf b/CPLD/LCMXO640C/impl1/impl1.xcf new file mode 100644 index 0000000..262d62b --- /dev/null +++ b/CPLD/LCMXO640C/impl1/impl1.xcf @@ -0,0 +1,50 @@ + + + + + + JTAG + + + 1 + Lattice + MachXO + LCMXO640C + 0x01285043 + All + LCMXO640C + + 8 + 11111111 + 1 + 0 + + D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.jed + 08/15/23 04:37:09 + 0x4B06 + FLASH Erase,Program,Verify + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB + EzUSB-0 + \\?\usb#vid_1134&amp;pid_8001#5&amp;887acb0&amp;0&amp;13# + + diff --git a/CPLD/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1.ior b/CPLD/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1.ior new file mode 100644 index 0000000..bf3668f --- /dev/null +++ b/CPLD/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1.ior @@ -0,0 +1,138 @@ +Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 4 +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 5 +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: M +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +// Design: RAM2GS +// Package: TQFP100 +// ncd File: ram2gs_lcmxo640c_impl1.ncd +// Version: Diamond (64-bit) 3.12.1.454 +// Written on Tue Aug 15 05:03:31 2023 +// M: Minimum Performance Grade +// iotiming RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml + +I/O Timing Report (All units are in ns) + +Worst Case Results across Performance Grades (M, 5, 4, 3): + +// Input Setup and Hold Times + +Port Clock Edge Setup Performance_Grade Hold Performance_Grade +---------------------------------------------------------------------- +CROW[0] nCRAS F -0.236 M 3.076 3 +CROW[1] nCRAS F -0.216 M 2.985 3 +Din[0] PHI2 F 6.373 3 2.684 3 +Din[0] nCCAS F 1.094 3 0.245 3 +Din[1] PHI2 F 5.890 3 2.684 3 +Din[1] nCCAS F 1.106 3 0.247 3 +Din[2] PHI2 F 4.774 3 2.292 3 +Din[2] nCCAS F 1.207 3 0.231 3 +Din[3] PHI2 F 8.665 3 1.537 3 +Din[3] nCCAS F 0.786 3 0.612 3 +Din[4] PHI2 F 5.483 3 1.881 3 +Din[4] nCCAS F 1.180 3 0.282 3 +Din[5] PHI2 F 7.162 3 1.124 3 +Din[5] nCCAS F 0.802 3 0.635 3 +Din[6] PHI2 F 8.125 3 1.435 3 +Din[6] nCCAS F 1.142 3 0.086 3 +Din[7] PHI2 F 8.015 3 1.300 3 +Din[7] nCCAS F 1.259 3 -0.010 M +MAin[0] PHI2 F 6.577 3 0.639 3 +MAin[0] nCRAS F -0.004 M 2.291 3 +MAin[1] PHI2 F 6.880 3 1.958 3 +MAin[1] nCRAS F 1.424 3 1.006 3 +MAin[2] PHI2 F 4.559 3 0.456 3 +MAin[2] nCRAS F -0.209 M 2.966 3 +MAin[3] PHI2 F 5.604 3 -0.096 M +MAin[3] nCRAS F -0.323 M 3.369 3 +MAin[4] PHI2 F 6.263 3 -0.211 M +MAin[4] nCRAS F -0.086 M 2.536 3 +MAin[5] PHI2 F 4.291 3 0.703 3 +MAin[5] nCRAS F 1.052 3 1.326 3 +MAin[6] PHI2 F 5.837 3 -0.133 M +MAin[6] nCRAS F -0.017 M 2.334 3 +MAin[7] PHI2 F 6.302 3 -0.241 M +MAin[7] nCRAS F -0.106 M 2.631 3 +MAin[8] nCRAS F -0.086 M 2.542 3 +MAin[9] nCRAS F 0.549 3 1.796 3 +PHI2 RCLK R 4.937 3 -0.562 M +UFMSDO RCLK R 2.296 3 -0.152 M +nCCAS RCLK R 1.639 3 -0.029 M +nCCAS nCRAS F -0.229 M 3.059 3 +nCRAS RCLK R 1.104 3 0.341 3 +nFWE PHI2 F 5.086 3 1.672 3 +nFWE nCRAS F 0.037 3 2.231 3 + + +// Clock to Output Delay + +Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade +------------------------------------------------------------------------ +LED RCLK R 7.152 3 1.423 M +LED nCRAS F 12.128 3 2.429 M +RA[0] RCLK R 9.839 3 1.974 M +RA[0] nCRAS F 12.557 3 2.494 M +RA[10] RCLK R 5.747 3 1.141 M +RA[11] PHI2 R 7.990 3 1.574 M +RA[1] RCLK R 10.012 3 2.010 M +RA[1] nCRAS F 12.750 3 2.545 M +RA[2] RCLK R 10.522 3 2.116 M +RA[2] nCRAS F 12.564 3 2.494 M +RA[3] RCLK R 10.341 3 2.077 M +RA[3] nCRAS F 11.973 3 2.372 M +RA[4] RCLK R 9.672 3 1.940 M +RA[4] nCRAS F 13.443 3 2.679 M +RA[5] RCLK R 9.440 3 1.890 M +RA[5] nCRAS F 10.958 3 2.155 M +RA[6] RCLK R 10.605 3 2.138 M +RA[6] nCRAS F 13.114 3 2.628 M +RA[7] RCLK R 8.842 3 1.782 M +RA[7] nCRAS F 10.779 3 2.148 M +RA[8] RCLK R 10.258 3 2.067 M +RA[8] nCRAS F 12.925 3 2.579 M +RA[9] RCLK R 7.160 3 1.425 M +RA[9] nCRAS F 9.857 3 1.950 M +RBA[0] nCRAS F 10.935 3 2.169 M +RBA[1] nCRAS F 10.976 3 2.184 M +RCKE RCLK R 5.747 3 1.141 M +RDQMH RCLK R 9.890 3 1.991 M +RDQML RCLK R 9.338 3 1.859 M +RD[0] nCCAS F 7.488 3 1.591 M +RD[1] nCCAS F 8.012 3 1.701 M +RD[2] nCCAS F 8.965 3 1.912 M +RD[3] nCCAS F 8.965 3 1.912 M +RD[4] nCCAS F 7.951 3 1.691 M +RD[5] nCCAS F 7.951 3 1.691 M +RD[6] nCCAS F 8.012 3 1.701 M +RD[7] nCCAS F 8.384 3 1.785 M +UFMCLK RCLK R 7.986 3 1.598 M +UFMSDI RCLK R 5.747 3 1.141 M +nRCAS RCLK R 5.747 3 1.141 M +nRCS RCLK R 5.747 3 1.141 M +nRRAS RCLK R 6.929 3 1.373 M +nRWE RCLK R 7.375 3 1.459 M +nUFMCS RCLK R 7.996 3 1.601 M +WARNING: you must also run trce with hold speed: 3 +WARNING: you must also run trce with setup speed: M diff --git a/CPLD/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1_trce.asd b/CPLD/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1_trce.asd new file mode 100644 index 0000000..80934ca --- /dev/null +++ b/CPLD/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1_trce.asd @@ -0,0 +1,13 @@ +[ActiveSupport TRCE] +; Setup Analysis +Fmax_0 = 116.198 MHz (283.768 MHz); +Fmax_1 = 55.096 MHz (120.077 MHz); +Failed = 2 (Total 2); +Clock_ports = 4; +Clock_nets = 4; +; Hold Analysis +Fmax_0 = 0.273 ns (0.000 ns); +Fmax_1 = 0.361 ns (0.000 ns); +Failed = 0 (Total 2); +Clock_ports = 4; +Clock_nets = 4; diff --git a/CPLD/LCMXO640C/impl1/synthesis.log b/CPLD/LCMXO640C/impl1/synthesis.log new file mode 100644 index 0000000..ece5a9b --- /dev/null +++ b/CPLD/LCMXO640C/impl1/synthesis.log @@ -0,0 +1,238 @@ +synthesis: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:21 2023 + + +Command Line: synthesis -f RAM2GS_LCMXO640C_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml + +Synthesis options: +The -a option is MachXO. +The -s option is 3. +The -t option is TQFP100. +The -d option is LCMXO640C. +Using package TQFP100. +Using performance grade 3. + + +########################################################## + +### Lattice Family : MachXO + +### Device : LCMXO640C + +### Package : TQFP100 + +### Speed : 3 + +########################################################## + + + +INFO - synthesis: User-Selected Strategy Settings +Optimization goal = Balanced +Top-level module name = RAM2GS. +Target frequency = 200.000000 MHz. +Maximum fanout = 1000. +Timing path count = 3 +BRAM utilization = 100.000000 % +DSP usage = true +DSP utilization = 100.000000 % +fsm_encoding_style = auto +resolve_mixed_drivers = 0 +fix_gated_clocks = 1 + +Mux style = Auto +Use Carry Chain = true +carry_chain_length = 0 +Loop Limit = 1950. +Use IO Insertion = TRUE +Use IO Reg = AUTO + +Resource Sharing = TRUE +Propagate Constants = TRUE +Remove Duplicate Registers = TRUE +force_gsr = auto +ROM style = auto +RAM style = auto +The -comp option is FALSE. +The -syn option is FALSE. +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C (searchpath added) +-p C:/lscc/diamond/3.12/ispfpga/mj5g00/data (searchpath added) +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1 (searchpath added) +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C (searchpath added) +Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v +NGD file = RAM2GS_LCMXO640C_impl1.ngd +-sdc option: SDC file input not used. +-lpf option: Output file option is ON. +Hardtimer checking is enabled (default). The -dt option is not used. +The -r option is OFF. [ Remove LOC Properties is OFF. ] +Technology check ok... + +Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482 +Compile design. +Compile Design Begin +Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482 +Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482 +Top module name (Verilog): RAM2GS +INFO - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1): compiling module RAM2GS. VERI-1018 +WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131): expression size 32 truncated to fit in target size 2. VERI-1209 +WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136): expression size 32 truncated to fit in target size 18. VERI-1209 +WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263): expression size 32 truncated to fit in target size 4. VERI-1209 +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... +Loading device for application map from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.17. +Top-level module name = RAM2GS. +INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding +original encoding -> new encoding (one-hot encoding) + + 0000 -> 0000000000000001 + + 0001 -> 0000000000000010 + + 0010 -> 0000000000000100 + + 0011 -> 0000000000001000 + + 0100 -> 0000000000010000 + + 0101 -> 0000000000100000 + + 0110 -> 0000000001000000 + + 0111 -> 0000000010000000 + + 1000 -> 0000000100000000 + + 1001 -> 0000001000000000 + + 1010 -> 0000010000000000 + + 1011 -> 0000100000000000 + + 1100 -> 0001000000000000 + + 1101 -> 0010000000000000 + + 1110 -> 0100000000000000 + + 1111 -> 1000000000000000 + +INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding +original encoding -> new encoding (one-hot encoding) + + 00 -> 0001 + + 01 -> 0010 + + 10 -> 0100 + + 11 -> 1000 + + + + +GSR will not be inferred because no asynchronous signal was found in the netlist. +WARNING - synthesis: Initial value found on instance C1Submitted_406 will be ignored. +Applying 200.000000 MHz constraint to all clocks + +WARNING - synthesis: No user .sdc file. +Results of NGD DRC are available in RAM2GS_drc.log. +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... +All blocks are expanded and NGD expansion is successful. +Writing NGD file RAM2GS_LCMXO640C_impl1.ngd. + +################### Begin Area Report (RAM2GS)###################### +Number of register bits => 102 of 862 (11 % ) +BB => 8 +CCU2 => 9 +FD1P3AX => 28 +FD1P3AY => 3 +FD1P3IX => 2 +FD1S3AX => 47 +FD1S3AY => 1 +FD1S3IX => 16 +FD1S3JX => 5 +GSR => 1 +IB => 26 +INV => 3 +OB => 33 +ORCALUT4 => 127 +PFUMX => 6 +################### End Area Report ################## + +################### Begin BlackBox Report ###################### +TSALL => 1 +################### End BlackBox Report ################## + +################### Begin Clock Report ###################### +Clock Nets +Number of Clocks: 4 + Net : RCLK_c, loads : 62 + Net : PHI2_c, loads : 11 + Net : nCCAS_c, loads : 2 + Net : nCRAS_c, loads : 2 +Clock Enable Nets +Number of Clock Enables: 13 +Top 10 highest fanout Clock Enables: + Net : RCLK_c_enable_23, loads : 16 + Net : RCLK_c_enable_4, loads : 3 + Net : PHI2_N_120_enable_6, loads : 3 + Net : RCLK_c_enable_24, loads : 2 + Net : RCLK_c_enable_12, loads : 1 + Net : PHI2_N_120_enable_1, loads : 1 + Net : PHI2_N_120_enable_4, loads : 1 + Net : RCLK_c_enable_3, loads : 1 + Net : PHI2_N_120_enable_5, loads : 1 + Net : RCLK_c_enable_11, loads : 1 +Highest fanout non-clock nets +Top 10 highest fanout non-clock nets: + Net : InitReady, loads : 17 + Net : Ready, loads : 17 + Net : RCLK_c_enable_23, loads : 16 + Net : nCRAS_N_9, loads : 15 + Net : RASr2, loads : 13 + Net : nRowColSel, loads : 13 + Net : n2477, loads : 13 + Net : MAin_c_0, loads : 12 + Net : nRowColSel_N_35, loads : 12 + Net : Din_c_6, loads : 11 +################### End Clock Report ################## + +Timing Report Summary +-------------- +-------------------------------------------------------------------------------- +Constraint | Constraint| Actual|Levels +-------------------------------------------------------------------------------- + | | | +create_clock -period 5.000000 -name | | | +clk3 [get_nets nCCAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk2 [get_nets nCRAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk1 [get_nets PHI2_c] | 200.000 MHz| 45.147 MHz| 6 * + | | | +create_clock -period 5.000000 -name | | | +clk0 [get_nets RCLK_c] | 200.000 MHz| 106.792 MHz| 5 * + | | | +-------------------------------------------------------------------------------- + + +2 constraints not met. + + +Peak Memory Usage: 51.215 MB + +-------------------------------------------------------------- +Elapsed CPU time for LSE flow : 0.609 secs +-------------------------------------------------------------- diff --git a/CPLD/LCMXO640C/impl1/synthesis_lse.html b/CPLD/LCMXO640C/impl1/synthesis_lse.html new file mode 100644 index 0000000..5a4ea61 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/synthesis_lse.html @@ -0,0 +1,303 @@ + +Synthesis and Ngdbuild Report + + +
    Synthesis and Ngdbuild  Report
+synthesis:  version Diamond (64-bit) 3.12.1.454
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 15 05:03:21 2023
+
+
+Command Line:  synthesis -f RAM2GS_LCMXO640C_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml 
+
+Synthesis options:
+The -a option is MachXO.
+The -s option is 3.
+The -t option is TQFP100.
+The -d option is LCMXO640C.
+Using package TQFP100.
+Using performance grade 3.
+                                                          
+
+##########################################################
+
+### Lattice Family : MachXO
+
+### Device  : LCMXO640C
+
+### Package : TQFP100
+
+### Speed   : 3
+
+##########################################################
+
+                                                          
+
+INFO - synthesis: User-Selected Strategy Settings
+Optimization goal = Balanced
+Top-level module name = RAM2GS.
+Target frequency = 200.000000 MHz.
+Maximum fanout = 1000.
+Timing path count = 3
+BRAM utilization = 100.000000 %
+DSP usage = true
+DSP utilization = 100.000000 %
+fsm_encoding_style = auto
+resolve_mixed_drivers = 0
+fix_gated_clocks = 1
+
+Mux style = Auto
+Use Carry Chain = true
+carry_chain_length = 0
+Loop Limit = 1950.
+Use IO Insertion = TRUE
+Use IO Reg = AUTO
+
+Resource Sharing = TRUE
+Propagate Constants = TRUE
+Remove Duplicate Registers = TRUE
+force_gsr = auto
+ROM style = auto
+RAM style = auto
+The -comp option is FALSE.
+The -syn option is FALSE.
+-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C (searchpath added)
+-p C:/lscc/diamond/3.12/ispfpga/mj5g00/data (searchpath added)
+-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1 (searchpath added)
+-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C (searchpath added)
+Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v
+NGD file = RAM2GS_LCMXO640C_impl1.ngd
+-sdc option: SDC file input not used.
+-lpf option: Output file option is ON.
+Hardtimer checking is enabled (default). The -dt option is not used.
+The -r option is OFF. [ Remove LOC Properties is OFF. ]
+Technology check ok...
+
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
+Compile design.
+Compile Design Begin
+Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
+Top module name (Verilog): RAM2GS
+INFO - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1): compiling module RAM2GS. VERI-1018
+WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131): expression size 32 truncated to fit in target size 2. VERI-1209
+WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136): expression size 32 truncated to fit in target size 18. VERI-1209
+WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263): expression size 32 truncated to fit in target size 4. VERI-1209
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+Loading device for application map from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Top-level module name = RAM2GS.
+INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 0000 -> 0000000000000001
+
+ 0001 -> 0000000000000010
+
+ 0010 -> 0000000000000100
+
+ 0011 -> 0000000000001000
+
+ 0100 -> 0000000000010000
+
+ 0101 -> 0000000000100000
+
+ 0110 -> 0000000001000000
+
+ 0111 -> 0000000010000000
+
+ 1000 -> 0000000100000000
+
+ 1001 -> 0000001000000000
+
+ 1010 -> 0000010000000000
+
+ 1011 -> 0000100000000000
+
+ 1100 -> 0001000000000000
+
+ 1101 -> 0010000000000000
+
+ 1110 -> 0100000000000000
+
+ 1111 -> 1000000000000000
+
+INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 00 -> 0001
+
+ 01 -> 0010
+
+ 10 -> 0100
+
+ 11 -> 1000
+
+
+
+
+GSR will not be inferred because no asynchronous signal was found in the netlist.
+WARNING - synthesis: Initial value found on instance C1Submitted_406 will be ignored.
+Applying 200.000000 MHz constraint to all clocks
+
+WARNING - synthesis: No user .sdc file.
+Results of NGD DRC are available in RAM2GS_drc.log.
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+All blocks are expanded and NGD expansion is successful.
+Writing NGD file RAM2GS_LCMXO640C_impl1.ngd.
+
+################### Begin Area Report (RAM2GS)######################
+Number of register bits => 102 of 862 (11 % )
+BB => 8
+CCU2 => 9
+FD1P3AX => 28
+FD1P3AY => 3
+FD1P3IX => 2
+FD1S3AX => 47
+FD1S3AY => 1
+FD1S3IX => 16
+FD1S3JX => 5
+GSR => 1
+IB => 26
+INV => 3
+OB => 33
+ORCALUT4 => 127
+PFUMX => 6
+################### End Area Report ##################
+
+################### Begin BlackBox Report ######################
+TSALL => 1
+################### End BlackBox Report ##################
+
+################### Begin Clock Report ######################
+Clock Nets
+Number of Clocks: 4
+  Net : RCLK_c, loads : 62
+  Net : PHI2_c, loads : 11
+  Net : nCCAS_c, loads : 2
+  Net : nCRAS_c, loads : 2
+Clock Enable Nets
+Number of Clock Enables: 13
+Top 10 highest fanout Clock Enables:
+  Net : RCLK_c_enable_23, loads : 16
+  Net : RCLK_c_enable_4, loads : 3
+  Net : PHI2_N_120_enable_6, loads : 3
+  Net : RCLK_c_enable_24, loads : 2
+  Net : RCLK_c_enable_12, loads : 1
+  Net : PHI2_N_120_enable_1, loads : 1
+  Net : PHI2_N_120_enable_4, loads : 1
+  Net : RCLK_c_enable_3, loads : 1
+  Net : PHI2_N_120_enable_5, loads : 1
+  Net : RCLK_c_enable_11, loads : 1
+Highest fanout non-clock nets
+Top 10 highest fanout non-clock nets:
+  Net : InitReady, loads : 17
+  Net : Ready, loads : 17
+  Net : RCLK_c_enable_23, loads : 16
+  Net : nCRAS_N_9, loads : 15
+  Net : RASr2, loads : 13
+  Net : nRowColSel, loads : 13
+  Net : n2477, loads : 13
+  Net : MAin_c_0, loads : 12
+  Net : nRowColSel_N_35, loads : 12
+  Net : Din_c_6, loads : 11
+################### End Clock Report ##################
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets PHI2_c]                  |  200.000 MHz|   45.147 MHz|     6 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |  200.000 MHz|  106.792 MHz|     5 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+
+Peak Memory Usage: 51.215  MB
+
+--------------------------------------------------------------
+Elapsed CPU time for LSE flow : 0.609  secs
+--------------------------------------------------------------
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO640C/impl1/xxx_lse_cp_file_list b/CPLD/LCMXO640C/impl1/xxx_lse_cp_file_list new file mode 100644 index 0000000..1c1a02c --- /dev/null +++ b/CPLD/LCMXO640C/impl1/xxx_lse_cp_file_list @@ -0,0 +1,250 @@ +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v diff --git a/CPLD/LCMXO640C/impl1/xxx_lse_sign_file b/CPLD/LCMXO640C/impl1/xxx_lse_sign_file new file mode 100644 index 0000000..15202f1 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/xxx_lse_sign_file @@ -0,0 +1,250 @@ +LSE_CPS_ID_1 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:8[8:12]" +LSE_CPS_ID_2 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_3 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_4 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:80[15:31]" +LSE_CPS_ID_5 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_6 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_7 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_8 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_9 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_10 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_11 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_12 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_13 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_14 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_15 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_16 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_17 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_18 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_19 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:141[9] 144[5]" +LSE_CPS_ID_20 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_21 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_22 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:394[12] 409[6]" +LSE_CPS_ID_23 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_24 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_25 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_26 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_27 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_28 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_29 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_30 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_31 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_32 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_33 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_34 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_35 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:315[17:31]" +LSE_CPS_ID_36 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_37 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_38 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_39 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_40 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_41 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_42 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:80[15:31]" +LSE_CPS_ID_43 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_44 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:315[17:31]" +LSE_CPS_ID_45 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_46 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_47 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_48 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:321[13] 335[7]" +LSE_CPS_ID_49 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_50 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_51 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_52 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:23[15:41]" +LSE_CPS_ID_53 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_54 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_55 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_56 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_57 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_58 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:48[6:16]" +LSE_CPS_ID_59 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:80[15:31]" +LSE_CPS_ID_60 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_61 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:402[16:47]" +LSE_CPS_ID_62 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_63 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:402[16:47]" +LSE_CPS_ID_64 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_65 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_66 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_67 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:23[27:31]" +LSE_CPS_ID_68 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_69 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_70 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_71 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_72 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_73 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_74 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_75 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" +LSE_CPS_ID_76 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_77 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" +LSE_CPS_ID_78 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_79 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:230[16:37]" +LSE_CPS_ID_80 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_81 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_82 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_83 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:143[11:55]" +LSE_CPS_ID_84 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:48[6:16]" +LSE_CPS_ID_85 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_86 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_87 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:99[22:51]" +LSE_CPS_ID_88 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_89 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_90 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:58[17:46]" +LSE_CPS_ID_91 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_92 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_93 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_94 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_95 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_96 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_97 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_98 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_99 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_100 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_101 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_102 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_103 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_104 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:386[12] 409[6]" +LSE_CPS_ID_105 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_106 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:386[12] 409[6]" +LSE_CPS_ID_107 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_108 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_109 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_110 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_111 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_112 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_113 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_114 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_115 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_116 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_117 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_118 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_119 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_120 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_121 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_122 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_123 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_124 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_125 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_126 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_127 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_128 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_129 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_130 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_131 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_132 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_133 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_134 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_135 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_136 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_137 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_138 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_139 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_140 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_141 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_142 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_143 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_144 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_145 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_146 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_147 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_148 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_149 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_150 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_151 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_152 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_153 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_154 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_155 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_156 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_157 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_158 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_159 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_160 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_161 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_162 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_163 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_164 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_165 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_166 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_167 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_168 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_169 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_170 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_171 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_172 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:22[9:12]" +LSE_CPS_ID_173 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:47[19:22]" +LSE_CPS_ID_174 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:47[19:22]" +LSE_CPS_ID_175 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_176 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_177 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_178 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_179 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_180 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_181 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_182 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_183 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_184 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_185 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_186 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_187 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[13:17]" +LSE_CPS_ID_188 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:45[13:17]" +LSE_CPS_ID_189 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[45:49]" +LSE_CPS_ID_190 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[23:28]" +LSE_CPS_ID_191 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[34:39]" +LSE_CPS_ID_192 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:56[16:21]" +LSE_CPS_ID_193 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:56[9:14]" +LSE_CPS_ID_194 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:63[13:19]" +LSE_CPS_ID_195 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:64[13:19]" +LSE_CPS_ID_196 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:65[13:19]" +LSE_CPS_ID_197 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:8[8:12]" +LSE_CPS_ID_198 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_199 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_200 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_201 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_202 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_203 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_204 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_205 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_206 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_207 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_208 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:34[14:18]" +LSE_CPS_ID_209 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:34[14:18]" +LSE_CPS_ID_210 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_211 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_212 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_213 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_214 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_215 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_216 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_217 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_218 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[8:13]" +LSE_CPS_ID_219 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[15:20]" +LSE_CPS_ID_220 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:36[8:12]" +LSE_CPS_ID_221 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:41[8:12]" +LSE_CPS_ID_222 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:66[8:14]" +LSE_CPS_ID_223 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_224 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_225 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_226 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_227 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_228 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_229 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_230 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:48[6:16]" +LSE_CPS_ID_231 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]" +LSE_CPS_ID_232 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:255[14] 262[8]" +LSE_CPS_ID_233 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_234 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_235 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:48[6:16]" +LSE_CPS_ID_236 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_237 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_238 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_239 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:143[40:46]" +LSE_CPS_ID_240 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" +LSE_CPS_ID_241 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_242 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_243 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:84[6:11]" +LSE_CPS_ID_244 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:134[9] 138[5]" +LSE_CPS_ID_245 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:21[6:11]" +LSE_CPS_ID_246 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_247 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_248 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[8:13]" +LSE_CPS_ID_249 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[15:20]" +LSE_CPS_ID_250 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" diff --git a/CPLD/MAXII/RAM2GS.qws b/CPLD/MAXII/RAM2GS.qws index c95d0a67102033b5f5e4bd35ef482f5b09a834f7..0162b066b3064596811d534ae9011313d32846dc 100644 GIT binary patch delta 57 zcmaFO@|tDBBE};V7h4M+VPIfLVEF(4KLZ1c6$1m)k&W+D8O09+MZo|l@ehPS93}<; Dc2N~m delta 57 zcmaFO@|tDBB1X=Mi>(DY85kH682-CdT2{dnK+R^9vS z)>L)R^mO%9pEK3x%+t@{z`(#%qQJgO7#N%PgXdjqm^r&xIoMNh3bJvsaZr47wX!v( z;N$0@;1Fcz;$r9G;1r}#m81A!^~;Px%GB!DyRRnOhyR91`T1W3(+l^%`aiNy<$upT zV9z@IYSJ`;o9?v2Bhn4?4Ys?fd}?O4W!>odTC6iF7}{+3?ccBxtLrU;uu3VqtLkU^ zqi94%O`n3qzsrl5hPn-@CFP-!GBd{Pmx`E?6c%ywOf%HeqBYJ3n=dhDl+@ZL!4F0T z*-by5X5T*NOuFQdZ(iQ6MbRu>wzzaozFVFlZ`qTAlW{LTAU|{S14K1w#YvnGhGwZ4 zlf^}PMvH`BZdMET-SO!dsCeXB995K?dowN8@7o}KC-|!M4!7R=_}g1{s9581e~3lr z6~6TMpsPhTEWdTCYf$rd2qIntv`}iN8bI?F6xHWvneYT4iv@YUT^HkH`@#AdLSAL1 zUe~U!`0u2g$q66>zJ_PS;I1kDyMP3TBRIItDdOF?7YR1vw8w*oj@9BPjNCC+E>tpTcQvgXQ937y9o4RG!ap`GcL zS#?$eIH%m>fd?*=EU}NqRK6D({gU7{?x={n77IM=<99RN%wY~8!7*jtq=UVV{6MuN z#iRr94zozL_HzsXjp~NliSd}&Qu%DamEjY1exn^Lr5yf27+V15YAT@lK9^GbWl6Ij z9j=y~)M&Pgzzxq=;v>@ZZ#nHEFgBD>WrmyoWz8h3^KESx;C&KNEqcF(9XBa{zozPU z5y7h0`MKmwqng=PKT`D~aTyd35S@*jR{#g84zw~?CpZ`T5#gZ(PW@x=f=hEmz@IP_DYt=v*y@fUa2mVXK!sKn6; zzl@xg8?E?6;H+@I$kbfhVi+FS&DL{{y^JuiMp+_B>ReT ztKPqkje+cHt??Cu=PSATuklJ&TgUC6XmYDgk4KoPz1i5k~QIb)#^2$3ukey$XLQId^}C2)M}Y7LUN5e__A^yR?zyLU1{|eBk7% zIdl@I7=+e-zN#U2vvc%|b(zq6wezt1i)njYPtD!+W3eZvcD{9!KE}V(SI+rgo%dG{ zBgYFEGT*0(W!Fh!`Du7n4=QStT z+E{9Fdpq;^aGpD#oNKSh9Kq?^X7zSX_oA`0^5xi=QmGdLbl3ZO4@V1s zqXX`Gi#K=^2P1B5jARb)G+={N;#bMO41(+3dYLw-g7xX^5ufNUy>*|W$4&!q zTeQ;EgAkWg*^WB@T=HSH`kjh)^4>;yBmg4td9ljm2!|5PgHr;|%m^c!^#A%&6r5{2U28J`s1ap!<6g$17 zV2B+;9^=6=<{}64=;_NWWDaOc4C2*b`hh*R>;R9jAd%d)4c#Z34Gm;{+O^#v7+EvgLD~u!~r*f;$VUy;#hKt?BE8o zA-HWv>hG@Mv5K(OLEU~1cjY1E1BBUF?OCO4cQ%oV-hMO-9OP98sM&Vlj>N>>C0OVM z2bf&%ymqSYUc+7c`_bRG0phxtU6_6G*v06xHe)u&2Z)&t!xA@F_svJOR|>7xdAz~* z4mR83Ap0GM%dp@51|z47_3Ru#TGV#zNYHC!9fQRf`(9y3S-F~v!3;hwsOk%U6*E=- zx3e5I{a*Z(^i!^J>Yd&Qi6X*lxlCnHc-ZE)$^7Y6z$xN|(UG}8E^m6=*Q$)0?5J@o z@xck2n5yIEAG@swce%f8p4u2wtB@U9R^FoT|A5EX2In6jsBvq(5us_=lZAS| z?usqn^k4CjM7xLG(zrJ)3@zS?t|&gZheYf7g_EBxnhmk|U%2-^_^9nKo>5=w9?Zi! zs>=&blLG6?#(d+Nv|h`cBLn2>^r=umtkU97%Hj&7OQUGhux;^aS;qOx=JQ(C|LzC5 z7&`4D*HKOY(b-qJc{(dZz^CgIhSY)4W$w=EGx`Qc_p3FImvcYb zYs*ZqCI;hGpO9?NN5IR&`0BT!o`5mB z{8)I-5kw%N!v{?Nw9mk6M)CRUHMS}H6^`JF+1{(tq#?_E=N6NXZNO=9;By8+=H}yV z@HupL%Sxgl-2pA>iN)yv{SwR5<^!=q5d^X}DfUp3-rJQXYZ})1#;d-hz(-!}Iq+ta ze>=!FBr6+wZYQ1f?aA-;`ZfGia6OO=QxDOy{TATad9V|vBj2gE{h1~Mzk%AvLfqi_{pyNIqYC- zZs3I&ByE`qIF%-^rskv%O9+U9E>qSSvklb!2o(w5Ow`#mmmmJJX2+{SNoH-I9FVj| zhRviuNu2qlUvP6nJ6DpM-K^_azJ4r&r$WV?akNrJUTcWz(r@~-#?JQPF+geyXocB) ziXZSo(LB0ez!iTL_gsof@v?#Q{j8zqrumZi#l0h+9kmSa!ua{ascU4^V~SMFui4rN zQmPxk1iU@%#D^fLI=0nXM&j?&WvpE12Yk~s5L=tiSqT*ksvsHbPUbvMho4OP8Md?( zHEBY)y{Q10iwc{rYiBsPrN)EHNQWioM>=H`JvQCwyUDZe-Gr<@be1Z^TD!AWbQ@Dt zqdUcnk0U~kcRho>&Q%&RzjvhMfa$J~Ay=;$sMv#XsrVTvxJf^_*uxG%l%$x5Z2#TH z1g0r1sxb7u;w{L$PGHt+8ir<9=IFh}ebeN^yxVg4l@+Vd-le|d4Vgb|vem5P=^aDW zP2nQ+G|#c5CG6+k@?+C}&5&LUA%0k%qg(dPwXk}zzX6E&oou*K8*k1Q$LkgdC05~? zhf9ChJCd@g8Nku!lM5kS=>0{`qqR|CpL$qC*Uv)k{>$rY1RaBk59b4))quwZzG&4- z(x1B0DWvl?$XYK-qG9;049%T6QNj~_zVbv--A+&8)NWwqOah@K-`>zVGtOn1fm4-7Z7Xgv|47yyWMt))c`5_C|G{zCVV4bkOC`XbqjZqyasdl+Y zM94?{Q6GY-qWFnBgKzuDBd^=sejM{%=4#k{d~U@j*HV}#@`dzZ_mEI4NC@@r#^R5u zTIL|@%+}9w`wm*vq+ba}P`QI=>s+nXJ_vkJ`rPyD=83`6{O78x=rp3` zi%KN-Ztu2qMyyu&E z6D+YeWdc~8sNF+CigyT=qm)Eaqq=c3Ch$JQ(uz+Gj=|+N1I3r@ayRF?oH;2P+Dmn~ zZZ<_{Go4upg*p`!f>mp^M5g}C(X=-YF1XnclY@=h9sd^VH%_0T4Z~F(ORe3uYUr;n zfewiQFlx*q18d1e+lO{iS>GV7k}sp+$Z#=QiWQojRExOq@*jer!_{rR$WB64Ue)Kp zh3|u62aL}#iTn6c6=XA@)Cwz-n3T=7G=r_Srp(8_qLvHPyQBdI(wN-wCprT=NV+uT zNY9SmB5NxPH;+M5bIgxVMT@MRIL)FXZ?W-QP5ovrrl^dHgI@kVokv{bLuht*Xa9^_ zn@&T>8=zw)xWrNWxFQSASYK=2v!J`yB77=18gf9n`)dI-Lh4ANyYEF|@8oN8Fp7J^ zL06gF&bQ%gHNxnqwDr41uw*>sQ8}S$5ygS3qFwdR5hZ?+X0y@uYsuYQg!P3`KJE2xV*(RNYbW{)1{4diq284UI*;FLA1frZwvfP?vCWL^ahOLds(^F z?ayJiUKKR1niv-N-6eYI+AQlql3)#fN(&W(K(WXa2!~Pg&?!>v3aB&Kb0d2`+j|k$ zI#W?XVSbYn4jB6oNX{j2V)Xq{hkFq4sQ8~D;Q zdPTkkpOn*vJ1@|2c<1+By;X9KG&q`woXx0D#=SwL_ufS6r%o3}1d1cyGrwHyT%MEP z{^|}F8*sDiv#mB5)DfKXt@K&6&EQFq5(x3CIMR=P{!yAbf1S%(tAZiE?6x2FLf6R> zqQdIV{{|}5EZb*;DPH)m;jsW{bDUz`!bb}2U@dRJk!x6+dO3f03BeW@-5yn8m^TI$ zW!b=w#Geg1gZ`klpS*_n1L^awYnDS94{vqg$) znrqlW2w|7cQ`f3I(RnSGg3n{!>^I1ans)sy;C^eyDP-i#sp)wh;>wG!;Sk9YyU~(b*vnN{_an@fs^%hvR1iqC>ADuQ`>j+ z*@Jx9S`U}ur@LLX0YkMPnnjk?EYkU8 z*0!z$(hr3gO?VykgO)R=@=@tVbcKsiYD>VN?RHJMbK0qLv#e`kd5>6sP&3y?=j`h+ z)o+#n1J+ZJpAd=(8*FiE68SBY9)o;WsaZkZ=ZfG1EJy3*!~9vc>Ty2&w+8Qaw9iJLx zzkuT5s#|fGu}twLKA)nSww4__ZGGSNJ{V|1^SWxzVrq^aQ}fh#ewDHbir?B{nFrc?vQN4+4=6SSAK_4pH(g1Qixa)AN3BDT zDwmbU96X&zRmUZ%h)$mW@wWeBKN!Hmi@}uP@69(HuVHI9*Ye@iP5zj+$`>@f7}%Zp zEG5A+3t>6N2mDIAuZsxUEAQPIyw#<)DB1-2IFA2ZjTsVcaji4bM%=}T`#wdI_7)Ow)YPjGZ8`YkmbIJT`naux^D@jd@f_3!cbR;} zS7Kn(wQI#5@Qv}ARF!@4GV?0dZHx4*tFE}kQ0vCK6z6P6BF;Y66 zb3RwY^~88^A`BiQGVh5{tqC}AlR;ymNs^!P*GbyM_@%S@ou-5LRI-@n=^NA1kbh?kApT%8aZ(fG?!rC?=1*xksMIx zD;3b{Hp!ja(8qnxUt?bH2+W~L)|wpZjhf)8wFpLd)<1QmB8g@#oNMQtX5=p+QM_c; zYc|Oq?#DhK4QR!$E^ut#E}aWkXmc8aw$GApe-9}Isl87;0a$sMc8X;m{;}-ncxnh^ zy$S^=d?xPjXd|=Vf-2UalEZzOri6j?9X0jPFBCgYQfayDaZfpyj%8w1B~{D~Hm${3 z`Qg|*)_yS%ytCZ!r+-_jEv@B`NSG9;a2wxleT@C^`xEKx^C>0oz+uH1Xue06Ql!dL zs%`HzxK+AvE^aLxnps6TjY!1_*!ivDyibHxGZdG=*(65XZ{6pu>XDu6fP1lXpu8aJ z+^EDtAa6hKor;(GYLP84;QO_1(;=nf_`Ig6h4dH0B%DvSrxvt1XTaX7ZgS?ea+T7} z0g)6!VuEI&)U_fLQ`5eo=oJfW%f(MS#25{%+!;J~+}J$Keomb0)QpqHVxM*CC4kG_ zZ`YkTW~lWwA9gui2uwNj5VJ_}_HCp0(c+JG2z#Hd7Ed;^IvJNy>AjpaB8)cD1rS%- z3se$B>g-vX+b^=wL3+o0n~{6T??8@qh~N@J9@mjCgTMRg?UgwxoS!Z4Z4UsumA6$n z2|qQ?O};$1&0UV~iRYib>nppe&2zF`ehG2Qn`(r<_DvAarG&lxn+R6Or`)Dp$nM(4 z$a%@;Out1v7Uxqf(_v%rFW=2eUa^>``rMD-T1%ldfs+K+-kvcoEhMhROp`ys)48G0 z1$e^z?4|-Jr0$}r04SdZXq~_`_VFRQ9!5zyTe+O`8wWDnqVNe9d+l?_0~Xc~o*SANbBb|C9}X?Gtqo@t_Fx<8x5xy|mP`@&nzFT+b*&}61ADUBAP}=g-OOcO zO=mS|{4m#Vz(NRW9G%7qsKVfrADN~#$j;(-fBQ}L+d^rQe2l%2Tx|5MjqqhMg{!M{ za_DW}{Kx|M#xe$KM z6Y)A2Oz-l&GzM-ghq>0ShBRiQo@*y>eL!U9ip5VZpJ7&vwtGkz+2LMqFLhg$MBYs1ax zoS!Q6`7Eh2K^I|Cv<25_7P6dOU3}Oy3sIR!IR?kO3#Mw1Wd8YLn2c7EuIssX}&dBKVF~1(#b*R1Fa!%9!_aP~@ zr<>cppt0Vz5eE8uZ|gUGxGoQJ!kQ;>Ey&-WEL|RrAr@Jld_y4N=-jr|O1bT2d8jVJ z79|F+m}+wF1pL6usAfag6D$W%lJ*Maa%vGD_o_KfLVOPLGU>l8T-;QCes6N7KJQ)s z+iE7@Q4d)JZt`)n{KQ_U;%C8L)1PaRRg`hzwN=)H5cg(ShnWEP<_um)+d-f{4K>GA z4l>9$FBG{^EX(6s902Tu;}-0W66$lIu*`oEktsdcM8w!wO>}7hhANI{URcZ{ik{(J zQ;n;i?D}>5N{_fq4e(}}g8aO%H?RV}Vi3TwTu{pkQnSp!H-5zhiYV>Bei1qQq9{sD zc1NtuKG0{seZ?kfIPH~(xf3G5?VZYTL^KAnNqGz(IBcMnKBkW1b`;H7Ua?HQ?rCGW z#6)-I>yO$_ah`Di^Y#aKF@jGT`7$?hhFVnlq|x^x#5M4Uy3Ogcvo|gesHMLx&h80| zaRCc2o`wtyFOtAR^*E&zhc7!}=u1WQD4ZDLk!jfL*FnQ7;8ahWnje%m1t8=or*RTP z`^>nJbPnC1RnyZSNo&}La4q5PMg-$3iVl-1k7c3}5n8cFTPB@ji{?sujIRFXSuEyt zL$ubi#JacRUisOA_=enuPc?T5O&I_ekHf2oJ?cE#cFVfmlR@)=>QQqAFk#N2%vjd= z*5T%65OBjBI1YR8`q?a^70v`L+@;#yrrNtN3LN0B1=dDy*#>$eEHSBP&FcT_BN+Sl znUXIq^C=_lAN_7y`nC-0hPl#F<24-nK|~qwPF0Q+y?oNRCdxe6Ec0kFWKgenP{Cv9 z+pF*MsTakw%ytrhanD_2${~emq5f4I>Hiq&WU}DCgsSr_8JO6xL)eYxxqDo+WM^;*8)JDj+c$x5dZpzl87%Z^q zXXzsTT}_$j0_l!!U5NHjBss!b8fD3MI8_Z1by|ZlZPY~h?BqTn1BD(sVa%8POL1q7 zK|%&tR!TkfPuYejw-EFjUv2+;**sEUlc4R+!xX%7Q&+g2p;`H>aTyKxBG$Z7w ze7F>KwNfFWO9N+}1cYFv5;wVj&(ktA!vO26kHQEv*GKh?1mbV`E%C>uFQ2-Qle&BI zB4A=S?r$b9!4u^eksm@f+oYYDi$a#?R5|@L`kqLQQm^NNZG}uRJF_JX?*uS4XrF(; z(@CfQdFib6!*{tWCi;P7wB$*8Vw_I9VN+w4MrChIK_cPHsQTN?7W!I>!!W8P zj8k<;MnHy9>4h;R$nzf~8LHoo+M?9ooRgeXtGbTL!%jfc# zPeqbxysVRByj#S#d=RS1?;#_5Jk03?3h3{U6VeWQq@-X=<`iqmm4z8G%pW}uFnvUv z)W_q>bUO3T%}d0tW5kyEgx2Mo4mKg&zhV_=-2TE!2Lckz#tl!BHLfZ~OQjgp>((}v zl}i0Tnq=|6u7P8a^sHKz{*v=F$x+?6G^m$78Hd^;qhJ>bH9geB<0kw5(D^w(9${T5 z$Vq*lT@vIenPSWp&(?s{l^X~D<;_wh0Gmac0BmX8$E!Cr;CQ3)N1-$!+~t%QQwYq% z`13=Ga{gM}bGqRq-#3lk-CiQdxs`u}A?EA)oC9KSLpuCo{)(gMB{_b3Hs%#iXDAA( zoEv2nTL)APA-Ehj2?p7Y`va4pR8kgdR)I3i>fTm;@{X%kdM<`=HKs7#d)mgwz3xmzeOwzYGbg9EFr|Uq~R`9oC&I zjjA~oY!EmDKej$Hfh3&jW=Un}Rx&svju$fX`JkVVw=7g(#`qKaVC~-${@~y05Ob7H z*?_Y`N~SlTP3;8pBwB^<*f6*U2f2`gC~v^*U*m6{RML6!@Ry^|HrP!^dhQ*7%^#Q| z{+$4t{NvAcH?!I6uNVei4GOSvZ_>s_M?kSRdlYZg{9(imm`&^MF!3S;zb2;sr!di{ zq6R?xlOOdr>0E`KTzeexqM%J1Lx+6o9)WAnv_D1;Ke@X!109eS-jB2A-3Pg*+3UlS z*(?J*6ar7>xEo|lHRl!$^$m^_%j&C9MWYTR<}a*o_5MKlIcw+IZuh*}!1?1tkN}Sl zxIF%8AkCvtT=A=0Gv7L)>dx{%^s!A!m`QxU24Y~?eYrHkqozf`xdIGClpEWC6Gx{@ ztil$zjH6D9KyRy(>PXEP@|6)!XNbsCy*fPe;xO1->*3a2rmVfJ)#4-}3^ZcRL)};P zcfeswRQK9b9mI`PI+s`PdR*Wsb8B;PK?9l4jK9S2n6q3cJ2CH!^_o1h zFqn<*1ea;&%leGh&QvN5D6A$l{eQrdwbTyqj_x&~6H3@S_ajkJe$dTi@6HRj;x_)Q(|#nj)0i zc+ul6v72zKB7vIY%sJhMAyRfI^TwmgJvq|QYxrS)fyDGruF8#YS?4Iy#dF?j9(p@< zphVL!TVHxtUb6E@GPPEQdk6YH3AY!?sFu*7Wh(e<-FVI^$+YZs4a!5D`waNmNM=O7 zhV_|LCe)Qy-_`lKjeFjsndX)-APo0VanBs41RNOI`U7G}g z6o=!)mIJem9k9Zb?&nn#8 zMGM~7Vfj9r2S9Y15)r#xST;TN>6G%xq3hK{JHWrmbTTM1qodnR+r)5GZMj(QQ++u{ z=;&X5zLSE#p4EnHh~dBw?8u1Y+LT0NlZb|G*yvB3e$pa2;mf7jyw$tHJA}Dw5kQ#9 zhx&@q>kCWE;NpPzBqFozAHsMZj->v;71|Abq3w?gQc1-(J~=WIDF5*1v=B$=qczIN zGapM*Js#y!hvd5`I0v6_=)A=qIG%=k|Ck(xK9%jcWA&@I{$e=CI%CY%Xrs}>S1@Hg zkBF)M4uoj-toZDi9q$YZ9i2bp`fg@IV3Zu{>;jGWk$L2^I#`Xul_HBHqARlQu&05q z5))yH+C-mG(IDj=uRCaW5SGOwD z#v4xv9;3ApJt|e8((?rDU1csS(oN%5TVnJMQ;!x&arq9n_kp83VWQmuxq!G0tg!>T zy^KR1p`~`aKz&^CBPponwMGP`3&Tm8(G;g(rlnWOT}dBp0*0Y?EkAh>W-+JBo`>t(f%; zEO|eW^Ow>w`2s&Up#Z5G#axX2-UMA=_QllDK)kM@mH63H*ITf=mrvnguN}!dvw~K< z&3wHCFhZ%o5%o;BWWAge2rSH|lflkeMopijJiS}DMW~oF@|CILZi8?Coa=ec-xhAV zf2@1G}#`t&al+ZW`e<&3ku|Xr-YZB-u zxI8Gy6%x*9J1a@Ik%BTQ2MOOUEXdOxfqV4|VoE9Y?_@UEXWiia*8UghsC4q_RkHYv zhtnS_i+iDwNyGSCzU#>R_WuCa0mX*1XWUc;ZPCJgJ9Z&R**Ya-m(Pu&3iZ~(Gg#sBRbh=3DoYc{;b zt?n^kD3<5aE_F`o*-y8G0ztb@76;V`!$5R4AdW`isYFG4#v^|gUo~XQ7G9a*HDtp@Bo!0t1VE|DHWD3c(jPGXn@{w@iHqTgS?!dhL0Soc^m~^@Dz1~<1wNs@Z z?!u{EmM%9GHs`Em;~;${Yr+92>PCu}V}{%Hmm7BKeg9Gyg#CvZE2EVo6t#cK*C2xi z9e-u#ie0+3V3KY*E1x0@8Ya_RyUkcHI2E;t6DFyoNun6J*}rK%Gj*k%juD5k^BvF* zK7bVT)4rw-A?Xs;gskWIC8AlKvh<+mLNsj)%b+ zoSU<{54zmWmb}VG=-rf*YP_)YO$Mm!5?REbzUju&MFfsY;dnqmEIRtK;kXfr-+5^A z#Hkrnbgzlh$u(&IJi{W{68*q}x5c0^dSZ)sO_5wdS2&ZW_j-`fJGu@N<`7E}Pk=+Y zFMy+d^DXia;yZTm)^_MjM(CujpMiRerz&&nw?T809CslOYGogSPg#?WpujwFfn$K~ zh3ae?-Tf#H&Nx0)R3mwC0#tM)e+GDLpAYTGsOHII1Z?64)!IOB+5J$gWuAVv^je;; zKzpK$a4iV-(X#{4+|K>(v%CQXHt<}3@uSz|tzgL#yt{{xKC5AT9_rwr8sz?zj5$O0 zR-BoGOdbEw0fyv+=<|N&du#C^gSV|t3+y<$SOn1CecSG1NoMFnc`?8cn(jYC{^n@S zs9}^YHlYP4_5yejRGN^)fmf_`?04l`SC1AYMCgf>BT+N*-qm)@R|~n$iGrWXL)I;J zu?%`Q$4(Oui{M#%2Kc???cHFlOYDpogVC zR_@ZI1+E)McX%O|+f4UJy4E`9rlv4(KYPGFLDN^!kHoYF148EdD27OMp5Y3pd=klj z`(0K@9y;L;1O=Uxn9oBJuEAmS|j(D%4h^mmvw-2ZPJSE}tJ zdi&g~ArIh7jK_E_&NUUvoj1Ul3bA4D@Lc=mwg$_=CV$Y|Pp%z|T|DkQP?5NgBdZxN zf~Qkq_OQMw*tbAl2tjJEzYh)IJDpkI+tQkF&rKQ?bZe%Q|C?;#2r*bm60s|c+nmI> z6Be8~_(cvBV^6tuElEHD+j#h2{4yZza;5Pn);&D(Tsa=W|kHRCUS*{WU0WR?@x5+9sl zBPOZoTRn1i7A&qV^z@eW85LZ|y(J&Q200m`7I(m+EmFS=fZ#-sfWZ+l|q8Z=c1tz8x<&VYJ!v*9em8Ne$~b;+c?I zSf0mz=URleXBool7#k;aj~?R^|1A6LpMuk5gqaT)!vK~N!g}S>{s5)NbPi`~*RC7# zYlZw9h|W)Lb6a-Y1DyY1LwUMjJZIyw(7%IqNrSW?`AS#v*%;z z&2aH=6^jP1?%S6@3i*))J^E`QJ$&|RiD#Os;ZNcqjDUldWcokaH*NB6?|{@bBsy(* zOgtn6=++rnIa=IwmC)Mj85{R($bH|7q3aFQTjb2?dKLWerdw_8IWrpgiox`_B-Rq0 z=FUqV&xt3{=Mg}6{VhOxI48|A@Gso>kKrl8-+$g1M zqL#-_W7Y1cO$gZ$Y7VNRl)$;~xygN`iJuJ9s>&_q6ZHP(!1Q>A!uPBr@hs1~RLZE!>9Y2*p z?Q7F=DYJ~1zfXVr>G8=dCD!F*h7q>4TaMdq~~=DXi^_7c=%229DnJWUi$I1mE9H5*9T`*EuwTTeaa@Z z5wojINjJVvz%xKJ1nn>Wiu2b1%ai>{~q_z~Oi)96xq`#OQ~Z}Q*# z+O8sKKYZUJ{ytXJ#f3$acSkW*jj}!&lKXk6*)LP(#{W=BQFn_dIaY%CfWr0{K?{?D zf5Tn>3@@y?-A^H)luTek=|SNu&5BkZyH+mzBpsQU^yzyC;Sv7nUorzd3>%kpPP3E) zCoGWGQ!V+MRVK{iKl2iTh!yOj;Er4b!1QBE8A1Aq8P~G?V?mSedM)70?MysjT5d42 zn}u~fNyNgSRHQ6&(5*BS-fhs=y8Z7q^DmmKQcd-7@!US;v!2ppdz&?--+>egTXamHn4+RKd3YAMEopZtR%0t*WbK~~Z zI_j=}!Dpd3=vK}TNcXB`c;UBGw`bt|M!gKH30_9D+7~wxa>F%a+rz45!INtn% zEA;M?KJ+gVrD=igdgClgw{m>;O4yMcQLu+l|5<3s!@Kc#C*QB|uXl z2upw^glZiE(*HElia6?!25n>3xI8X~D;aIA>j>ax(`#C~ICZI;P;X5jLIMI0MpPnP`4AMPD@(CvZ zmL5Yzldg9Np3T-TOX1xYBJqSZnG1pBk()%dTWqPI>_^Ho zd+IcY1#*Grc~;%r@&+Nb!__@h2_kYsc~jWuGpM5l#-n1lM{8xh@!eIdGL~e&_isJ) zol|i{Hg*ih|FOiHFZ?>*%bwxUbsk$7VhuXXSNeO6}K z`*a9z^&AS;MmSa(VHs&D()7H3EfI+N~_Lo1(bzCM<_$ml>P zPW2`?UEo4H#t-(zug^dG^SZ`ZKVwwOU@2U0fk;p?)mKTi&?Gkt>JYI$B@ zA#~zX05I(Gcn&S<>ky@guR+g`0lLhmp)FbiBVy9Lk9jxA=Ub}?Di#I?^0xr@F%Z|=D~FID#iYEbJ6I%BOir8+3+7jXudyY^!LqKTQ z=-VCscschJP!RHbR(?GM(fAQM$R3%1!Af?7RazO4D3A^u7vm8}eyuHl<7l zNoF+jJ?3KjgyWcB((5{GRd>Zaqr1_Ex*P?QF~O2X4syV0E8u*l%9MBR!Fr-BPDRsY z460Gsj$3<=f4^ zC$j$Z!5lHS(I*=F@l!KB-9}i09YXX$tjS(E5%y7)wS4Q?G?Dj>*Yv_PhOcpFJ-se2 zvogp$bDC`#Bed7a$&Ijjb7rM5BX@F<7Ni1lR{=^s7JA@R@8SEdvK&4ME}V&9KEBXC zDp$%h^0KnCCsi{#*_9e>cu^m}HExNe-FAMrbk2xWF;EdoU+^bzP|w5zbpf^SM$g3# z6BKkUgkiz3+s~r{(;vQL%FnhOzrouSOg{+64F!Oxe8`F)%Ak|h=Mu*GKi(8fO z)32EVx08cDY1IT__zz_&W14IWty8QUV@9AoH{wA%?6O zgrj*>ZVUUu#YeMBqtacq@_|Drl&`mmYiWdaw z@23#2A=qPQMeuwzjwdJaw`JS)kez7O9CRWxwoA`lS3^T9T#;?JX%^!WSj>S>JL3nK zd7FM~M4ES@{qF5ZiWL)a8n5-EM1qPl4?UtcScnE0`y`&=M+pYnr_ErnS(s2MK!V2J z%e+#_u^bn?mJ0e?qvBCdC(wI;{VPA**cUg(3m81YGn9PthsZN+N@W@3mRH|yx(~jl ziIQGT<%#K`f=GE+KO%VK!cb-Ixh2>4tlZP#Di!|zxL)4yC;4~@Gw(uy81xk@lM zhmud)wWxIeZ57qpb({aK>NcD~|4*CN+T6T!6v?QNrA^?oMlT9T)Ij56)Hdfge@~5e zL0my8TrV#YvhZuBRmgfp(UM!o89}s%kUBngI<6{Ov1)##D~X4lua|ttqRfhw<1A8p zqgv922Uzk=L0-CArGtr1_&J}7DqrO=l1Itse%lqdvCbZ$p%zVT7Ex01NV9rSDtZv< zgW_j1GDNZL!mG&7-~u7nLb+^V+VtTC^Kh)g6Mt0qNq7O4HX~eJ-7LQHCCyklebz27 zSznKqI<#IIhvUw-L8~X4C<1}Y(?OImnxxkBPh!^i41qANgc9yx|H;VB5g+46kL+F| z%YO=yE+^PMgjA~|u>VLkvL9+;iIZHgg8}sxkUsHK95vr3|6ZLL{II1Ki?KwD(Z$x4 zF@GDj`%heB><f>%QF`oY*r^tv zbnw{n$LX*&iFv&Q#Plr7ULm5x^_0W@*2G0gbK&^W_0dqf&r;#ZNVldjQl@V?b9I2j zZ0@R#JVMHG-PKG@@rB{~CqCY6aEgmQK@mpZ<_o*STC;zeI-S1tM#>Xk?uw&yfNCzu zAy(T^J)33oOJXi@OmBXDaSC`mK{-&UHRfmg{e1Id)kn|Zf16IvUtJ8H;eDz~ObT?r^)K;nTvSY7Kwuyj8k3xUbu;y~Y= z$z-El_X~uX%2u-~Teoef;^rGO<1+3-i3&?6$x(Uvp?my*wb3~KkU-rk2F_RsGm=GY zCKrohAe~crqtVYu_!E)deDDa$LzWS0A;pFM2wV9Qb$NZrN1wxkLo$O;1$SQuWjX80 z8}0D;0+@|_^oJg@v=R*Uw{Qlqp8oR_5^Zdx?IZ)1M&aHjUtsBdtjrs)QU^!6&@=@y;JwXS|(=5`PswU%pPK~th( zT_s7>(g?cL)^;;7UN$G2{Wr9nR99h7{t&qjM$*HRz`%1%H24Yl&EgP1?II3-dZqck;_Za9Z45D$AWFVvFGnGKzULw$2=%fj&|)6 z`B)_-m4DEJv?J}r)7Mq=+a$+G6!TUj11G`h%-u%zDEv*|!ok^GvnM%cJ{*w80m5l_ zn0#%}X(WP&6w`~>#5nQT5cSeO{}WQ(z=M+@FC|+06qr?_~+;V|Lh;Y=lB3VoY(Y?gOdaJ>>R-7^Z-6v2k_zCr>_lG4&cKhw|)8C zIe-t37WL)Bp06*C*!0F(BOEHYxyUdb<$cZVWrFv?86w*!h4ZW~e;m{Gsy_N~abl-7 zlznjS5zam0)dz>Q9$tNL7=NxO4t%&{--i!4yA>*ZaZc%Eu`fCO_lL{(5WxZ-kx&-*%k)Og~Jl8uWX#7a?Y8xA8!MmhA=*p+WOv} z>jF05PLuILzDfLZu4h~`7v36x!`$p6+X0!iZw{Fkk2AtMs3Y3Tgeu+s3D=07Y%<~4 zxu8(Hv09Y-=)<-3YeHBq21wO*ZJmBS$nf~IjXWSELJfL9Qi> zPZ|yDrOa%yThydmpKIblM%a*;PqORb-r)sRvzwY@qYk@q<=1c`yKdRA8)vs?1O4`> zi?re=I7d~v6GG2KHqhAjd&UlDjyzn^N1u!0LoD~fIi>M^ahR=_rTA*;q~=8P=VOia zagC47deCSpFRAlh)js+V1AX-&hxEl+BR+l4?#~S1gIwNj`l`|$*YAr@U%SnVYF|DZ z#iuXM2Lt%rEk4^61byNFyKNI*9~^YS4t;Ro!>*?fPS`QKd>|4k-9Cj6wJ#rb+5GQg zF5P^Ho0S80i+$sO@n?JbXNV2J*{0gZZs4pOfb;H6(ub#acEA2=Zhe5Be;Z%6)K{weR%ggFeRx;PgFbMV~iR`{*-7Hdf;y*BJZm8j-E9 z4Zt}vzy>FK`UhLD?8%4Nxz>}>E4i)EB3(Y{+#`m49#7VWKku?DmeT z$tJTmW^U+NK^N{18cyu*&WY^MnG5zvE__YG&}{g?)(71+l1X;xj9DqXKCsVW3Cu$#kR%^WHqpvF6vR#oZeeK2^?aPOl?u)}& zXWuhV))C^TkKK-Id|w=F*4IDSZOGgvm-f+zvo3ImZ%T}S?l|BXGXIY)kzY3sJXY&M z*hS$6M&V;T&IwIc(`Sy{0iyImd?%dvTfwd8JHg2T6z$YDGm{Bts3O!hzW&n$-+6RX?K%cD@ z*H^v>S}pMD>(e1PCL6f9EWK<)_zb}z-mb~1%ftLMKXvN^A7a6LI?3E-%wC71rpkCe zeb+|(vRc(-gUdKR>=B>Us6IHXrQQZ`8OI0Nuw56Q4Uln#`F}x`Jtpyu#TL?Y?e^*< z{uN{NHo`;q&3vfuepQ6uA>qRxeB`FYJ0$Uy7J8@L=*^|2SHNGRYW$%?Dey;cFKxnS zA36qq^h(?&e0Yw*AH5g13IEb~{-c-UHsMdefAogjCj52dJjke86{-ss_ z8z0`SrYX5cLz{jc;DGwQOU?C&_WZtAb_QB}E`34^NkN;E0a#k^x#R|M~T4Zm2IeAmBs*pExAs+lvWm?ta z!6?iH`7;IPSt&nriBih{_taO)5BJICj}H(#O=EaV~z4>`}Aln4jGJ&jX&#zqomRM=|@RD!oS%T^o_-_(N%q`<0Ku z%#q!y%rvmrno*i5&kqg;mtB+;mlGZ2j-Q*=2ZUrk|ke%wWcuK;5T5*V%%y?BRURU=g;lnl_ zCRIHaw+U3Y;>YUcLiE8;Np6$(Rbb|i_S6$! zd+NC@+c(WVx<#)c50LG21@KdU?ujiC8!b$}b>X5+=88_hZSVTXgIVVt>R+vzONO15 ze70YV@C@T(9eYD7-d2|jy-HhoogZ_u>=iK&i&94paLyXd%y@qI#^ZUKI}4f~??eaQ ze&Lz!hcwR1!a9LG%y%7BvR#nF{18A6_O8Zz9X#Gf4Q_*#x_dliF}xVNRax5PWR8$u zDD0~}%}YtY1EIePTd%LCUx{ar2xnhpS&)-QRCCEN#-o2O8HSCoWPn;3hQ1#p*t*c2 zVIL(OxbeY|zx7_03jNHt!2ECSL187GseH}FC;T#%D$TQ^X?6kC|280V%)|U|1HL6Z zPjhC5hs$EYCLZQxSyjM1&G!qM9&dGl=k1BjJU{wlaShL-G$@qZlUq|*S1e6oW#oJ>#Y^5NbM5npRKIgN z$1DI`2DYx8RdQZrA!4zfIS_{t0xwoBX~>mnIH3^#3yaim)KSN!LI9m zPW~5!YueF5c68vM=%I@|^qc0`B>v}uJqP;>VMNx5XCA!7v-%DelsQr7L zA*DjkPd8M+Vm7iJ-%Q1R(Ld!p&}|Q-+@%^6zJs^*T$MTS$U0SI$18B7 zkEgzL2)gaIM!>oznXp}3wZZl02(dm|J^$hYgF-Ipfd*FUk^a=%HD<+=_7j{RwqN z&H?syeM0I#PSw5>4OG5U|Fr5a8J-;#2B8QRsc?kSJNl<~s4it)<><}2b`uY8aI~=N zrA=e$W1VV)Ek!@_G|^FaC_EoFFRSu0dtUw6mN)1>q{@8l8Uvh+bwzbS?Kic!p42*X zTJ1M9xsNDk>{t6P8HXPdepcg-tN()j_2+8pTOs&6>f;*oPPKU^44%+jrsD@Xw#fkh zdsGi;%tg^-+(r8I{Vvg4qvJ{)FN!|x)7m4vrQ)lJ~Is=7o4weY{kFR{`<^ zT>B;O3E^D@E*xH_%UREVTe=JzwtFg#M@`C1qzF$yXp*H%xt2QEUadT zuFA8oD^*viE>pcHRs2ppCjxJ(u2AeU{%zH*in|Z>eVy9G(4Eq6zmCMfSsjsQh1wT& zgg!cLR9&qKedt2xl!RwK&P!G`Z}1%BIUU!iu2y@MD&tQnZh>D^8+~}e^hq@?sqU7J z(5D|A7{~u{5VQ1C7EIzsnSYQyKcDo1p}r&QXEFZF@mOR5Lc80-(dS=IAuzojEG zAJYeU89Q81oAU^4xI=ZNVgcH1b$O99uq|ULG7=JI52^aZ1Ods>IJ49Xkr>HBe2aG7%l)OTFYI4}4i^<%3m zf-P73s@i8oV}si8=Ot{&a7pbQs;gCroy+RO7TZ-%=sW&-SI4(i@e}Y%s%KRVhTYBx zezF+zw)&07VYRXUVbv>Y8=W`QUZMJ-`p@Wioa4vxk!0Pd@As;Lr>+pkt5O^IYW1NP zvhGy9p2pylYpVF-{|5j7|NnRaY*I^T6HyesZBpBs{u?z^(JuTJEfEyE2-W$#Nv2F@ z(l--nC^)59(^3eEwkTN8jVNxqbmP_^-Ke-Kb!AuX#Jz$-1$CjTmTo+Em~=Xlz~xNt zJ@4N0?mHQ3qA4OeIz2q!1Z+n1A>6#}+rqO<*Ykz#$x1V|A^rT-jT|7LrGQ#q@f~$c zXkLOQ@PFvc>IZJak>nniMLdGq^E^!SB{lN=_sQ4*x}r@8xp zU{(uo+^rPb=^noHjbrbp!%7!0x{_`fdxOhVAJ0Ge*pN~zPo(GtO6!vsl7k_o9~gCU zN?45N$c|vz;%IhhION6mqB%vib7ves2JeO6D(dA)(^t!G7d=FJ;oOo{r}f5YYS}P^ z?4|;;%H`Let^uovff$R0`6Wk&2I!$5C{J!}rg$z#{DGmbf0CG`%C)HpT=TM2UjxsX#|bl9{jxm2&UJ!xMM6|Ra}v#Sx8$v{OtiNth+hd zQ0VD>ltp=9?eCR(yW{v6_bkk^wSv%nc7ATxIkD+dQF2OB&82NjtQa#pTpAHJDdx&G@rPxtD-Q)npumm&3|{15*R z4OjY~wkPsw7hbf1hWjROGNo7HN~HX-OeJxZKwT+^UE`P*bFmq=ItA`gih99b!hoJE z4pFS+c_br_2YqBHW;&{-s=QhdvSzX+YLIkzCXQyBou#UDNU|k{#?O@C^5sza^x*GS zs`7Ke_WPRdmO7{RE*F9qIUbw2n-^VVGN11~&^n>n~3%Kh7d;#zFx3)e;S3~H{ zi#`kM7JF;GWT~mBRNmZ&ly`{diYUM0zE``2I75EsP0R%59XU^d6d zZNE-HJ;@u}FE_pBz4|M6x7AxAiSbhCEYvwm0tP!YYm$|Ar9IhN>8rNvczthg0zSq~ z6Qgmm)};;mY?(58;$>T--t|PN8{%b~|7-kEH{?}d545;>mjpt$XL_@N(n9och8I)^ z+^SiaN+Yy`@=T-~`;}--`M!kgU+F6pfkAcI(z*Ud{0Sn6KIcz<|HP6{Ff0^m;m|h2Uso!P2P`QjFLAMj{{FW4Q%u~oRQX&59w8c+d@~O2de}Q~=zN%S0gJ%b8d*i) zbAA8lGnS&m{&mP#uNH4Tqm#tn&X94S#;ZAbj^Z(7RBIVrerwZYo!R`7@u~OR#UUGI z^mI4h8@Qrs$jf8=KN;J0qa-4p*IFaAj|fM*U8_2qCU^S9u8 zhGEs?X;TXWD?e_zEY<{ZL30EKPtFGEQ#MteW3Q=_-hT?F20@+&*IxU+X^e zKyHbmHEE9G;vQXc5P;KzxijyMUcdN4t5I26|%vEGRqx*F5uWFc0;9Ok3I z1F5JN5UAPa>^*Woad>V{N$k|jsUdP7+GxJ;;(JSWR>)TMa1WBZHa3c=Sa%m5uek@8 z6GL?3>}s>^;g-RsT?uo-y(RUOh+#^uv*Wcqi&t4os8~hU?=M{Z;ZmwZK5-$Ou*V6o zJ@Bgjj9H09JZ+@m8Jdu~UL2?7A=sCL-N>e!sa>BzSlv<4Z@!JIu;n4R!X*6L$>wQY zy|UZceS7^!T}^si{d>h9FyFYRMac6+o$NR>tQN|-bg{nmbd{^b%(;|Gm$P!+lnNu7 z0_q~{+@hT&sB8ZAXwu2&iW1diywrKiJbjd~w>N)FcN0W@P9{W>6y;r70@R-8e5l=w zqbu!czf{K?2wHp#Boq?j;C7SNsZ#6By8V!DgButg&dI)0I!JXk6yq*6%m`(Fg#-S? z#!-u|zGrNtjzeV#ZqIuz5LuNze0h5IwLT!Z`UIk2wf?M{A{0+OfiZ@%JjU_Pp+oxl zD+`CJVLJHmQzNS8q=Rm!4<}Ino~2`t&_Wl;zfpc)sbxiLNys^i*A|^_QI(FryS2um z=ec3t25iIKz{6)98j~;<)EFVdi;hN3A2d8|6E>X2Q!+mFQnV#zd@T}5b1$LG|0(*h z4n*2w@VJFF=^t0NX*pz~efBG3V(04a7u-m;CQ2Y4UFAF>>^u~E33TPWLh#{uZL zx5C>KI6Z=_opvaflb9D*$etH(9G;OnJ%U@U3 zJKJt`cXP7YJnj!%AK2W$16%me*BZ=r_dM*gUB)uL+%ZlTWV3_f)9%V9%St+n@ECx4 z0rt8Yl9C}y!ujp7cns`|G?@;OcyzcC<^y9^-{GIAfMIcJwf$i=fYz}5tnD>xHb9Ur z=RQA4)+{i#OU3f0KK9;9cQN|~xg`{&F)+iuy3UJT3N=pc$A2L&^tTs`q zyzGavi693`{JufoGhaj|sYu#KN2Z?x(&;uLd<^Zb68pmm3m-j0ThzI(nAtt`o1#kY zH`TVs-?_SEO%QP%#Wj4+f_qL&`NyJHky~ti%R*kQ)NX1LP*ty7xO!z7srxIg0+#8w z=Qq|VfKg-3Lf78!ppepbag|zWpr*k7)2dlEc)Ml)5MA^bQjX%&_EEr)AIrkr3JOkLsi!*Vj8X01Vm-Lu}_>99HVQ7ZSa)NI*+$+endhgDuf@zUpe zLiYV+;mZb!rJ=AFTKy^&9ep3KlbM=94G$6%S4ULlny@`mP;{@Gc$9nLlP7zQh5Q#? z8=WQJhk#3@uf9Nm8%1~>ZkB58n4A|})34b!wi2zB@*UOF`qMhEd)HHO&!?M@hv0UG zYa{;WZezjm4@2>(F#uX|ei?Z(49TA`yap1_K#DVEZv>Q+RJMt=^$kF0>#5ujNE=Fg z2mfUBjQ3v1u8bI3ZA6euqp-I9o7#b~XDEvv#D;(>ihMj^yELO%&abU4dDAg^P{^gY z1Y!{I-wDi4HeK2<|3e>);LXwY+#9VHrQ5i9iDw|tA(QfUOb$-{(CF5Ik?!w>2^E?YiP=L*>-fy+ch7*8XQ^?ERyPo|E54(J*uNVuWH(CsZ9&z@B&E1k zP*6AKvYO-Tjo>v%((|-lE1kU{`6T%D5Buo9pDG#8LpDP6StbJMI;Uu@-GA|&;+7|miD?Uc zy1hmUxnMPVT*K0s&&?X}zbkTKEvg-Q-FJ79{ke%pYKbaUV=_8jO|NRkqfltS+yH5q zNYe-rgK`QMFJ@Ib_t;a0)^Z)XD*0u{__*w!(f-CrVRpfaXtn8@E0`j>h5Ug-Xhod% z?UWAFXgsMDbQ$)Wi|Nd--zu=4`PkKCly)71`!W0dD~|X7uIBs+A#^?-W1k2`H2-SL z)-?}i8xX;m^|L-UP{|@#RIp2>Df^o8HTa`AIg6c4Xa|t2wQ;NmKEvS%&_+8?OAF{Q zB5TD9@&WlKqZ7Qai|!+v=4QQ$=u+3Dy7zNI)GXcvh|TxuF&P*NSGKkmFp2RY)#?A!roYvBzG$@g?Kj)knlf8HH;ag=!v+g;v1T2nPm1))T#AP6vALiysso%#n*D=TS$MJ zdh-_*6)dIIc_Y~(XKlnS^0e3z*-;`#qdhD}w;kp|hasAKvAb)tP4c1`@im*sO3*|8 z=7+MpR`1i6&3EoyYK>O=r0(qM9Mu{?`9lfcclyAi7IF6F=vfRk&tl zH?OgL3iAxs2Q!gPGz^Ez5_ogQNW)B~M=WOfowk(^*?Y}hP0@chBuKH`5v!SPy-!0|}#lrI_zW~Nq%Z9JB_!O<0`RfF`q~WvLq!#LqrG)vj zwCn3&d&!TtYA-Ct6H^`eQRG~!CV}}@v)=bq+-QxNMGBGRFBn~Yq6n*)Z&&~%G+ifY zYC6`Bhaua&Ig-1eQLV`nB7G_Km*cJ@n-7kOSugkYRSJHJoFRlKPO-&+98K4rGcg6+ z&3?+OknGgMG#0+Ze!w;hCF?s{t|CuC!W}@g`*Q5TY^^@pszpdsY)y#2f_O_BG$tox zZVVBASrxU^&f0aZx(@2wYn0ZjHt-YZ8X^W9v=YeyeW?>~?(W?IIZ0 ziHLI|EhL#m+R|CkG|U8aF!&B&LI6%Y-<_wf{8bT9aloVTS8M*_OwQ|E;n_@QW-@_p zdHLWd<9g3Jv2rI*r?~2~1s;)`LCTEV9@! zi+uLfgn>tHQLL!;aSfaAly{mtZDXT94jyUZ#REp#2>Ps zb@h8qnCb9eSF#S-P{i#A7<`xV*2$w2zRj)9Yl-{;Uz%Y=Ke%T;BhDQcJAN##vf*zx z!t1KG^@pNa(m=SBk3Y8wze7;sTn^5WCw`SlYpMdRDP9kHGBXOz_t_H`j4mpOK7Z3OChqVtoyJ-Y#jGf={ zYD}3Na)U0%TlAM*zEM(+3=*YD7(b19RLQNK5%yv41{<=(?6^ zT0`BMTlud5I47#-RjgejzX{=1_Mu6(Zp$ah-BEz0_DAv;U)pRBC@MZQP$=+}YM(B; zy2N}XON48lr@3yMj&*C~F2gHCREeYV-Y$0fX<<%?w_5zr6G_fa`(}N8Mk~5p z^u!J-|vd? zT1pzFCfLr{GjCS@M3b2-dv{5Pobi&rq-w~V5lvN^WnIN-Tv8zWJDGL*l?whYPWq1! zey?a@G)}ZN=X`CVAA)6u%GYGe^)4`FN*7sy`B~R>C4}R_hG^L&u7+c4vzg&%dP~#- zh9=-poB61sdS%P+lD_uj+DN;JWzeWCC9FZ+1|v~d$;^HFuCa4w+5=Utk!aG2X@_u7`49}}#r1S$01Ow)g5-|Rz&Ki6NnvAQGnbsBT^m!8HK zEV3dbx#pl|I-W=R<1ze9K=@nzhJSn*r64Q;-c9ckl;+qLDgqi zyAN58EC|s@7efc*AT2T$#31;?_yS$Cz15Xf!?2eT%NK6lc+LfZT;pNu9~&~v?-RV0 zPt5xhafj%s67u+2;8-Zr4q;iO)3Ff;WWBsrM;&GCY2q9|?hHo0hg_NG?f|s~%TU|7rR`YRO2NxYA zB#^5|6(g$8AcKVml{X=#iug*%wX&0hfi5&hdA_;Ndh2GRXFujBA-OUJ{Bco>V%y(4 zNrMV+f{2{E>DTxiwkd9RS4Xa9=aT)WS-AY{qj{pJ^F6dvs{h4FnNi1uxyMi+7K`9w zuXmwoh^<6lRrfHox_r+Bf_D{Wq!VlAf>;HIIjhkc&ug_f8?^P2JT`Z^Em|xVdn9Lp z!d^0&GXoc$57UTP*vtLeO6v2ryVh!_o-?HoQ;SycZCtT|PcDus6F+Em-n`S2eR8b4 zTu=-Yfve|4Y0}~);<^uJ=`>#&z-!3?z%~H2>-zkR)lNXb4pfN$(LMMvEeIm8h6%~@ z5N8n(lsdtKnoN#`*oWP&RLlnU5Qu3kL(-=3%`}BzIUqh?ZSMs9MgE?63-JF;lqLTMe1D^W=5m_ zLlGuxBwWvM_vNe&OrI=4u`rlW&u~WAZQRL^(*vH4lyir5%z7WX!z~D@4WG}e1rh7u z;#>DMmm5KNC!eT)E9(-&O9$cP^K&+*LF!87t>xz{4u0Nfc1K3Yy03y%#F>AhP?J5Y zCNLJ_qTapO;?pPP+W(*szAluO1=(Tu;%c&$JpNHVT_5MSXQ#Ijs(u>X6S>Fx(ecff3=e3sAHMbbS-j+7tMvF%Qu=EWA zU+*86I(LMh-#m1ZJ&7gNlD~xl5i^~5ZEcUxi7%25{&bU~lV{ay5l_{+zTX+~gK{gJ z?R}IN@8SBp&~U|Ptq(<64|t3Z(fFc}MZSx)!gJ+)G8xe)=;dbn2Z>~;!cDIK0$gG4 zU&>QAcOgvUcjY~A&5kD22Q%r7oseVo$jv{z)z36KcVT+AUC z(^I|koeAY_%(|Mj!rsBMsV@i`mU6S6xg>4;JFRRGh)&&Q=0aU_lXq2y*`L=0!Ox76-TCc~l~+O(3aw^CoKM4| zz-n>_xsPUZu#TF50f_5}o|UV$mkckj|Hjc3|1|56a;}9YGj1)K>hoSL*ZRg)#CHwu zdj*AqTqgEWR{B0a-C=j!XQoMnT%>NGZYtQ=UwAZk8q4n*GT?8H{OQhplvT<6^G1&S6-FdaMWZz#uIyk&c-|1$@>ZB6l-pa&-5Xl@K8hgET5Oe77bOx-C)< zmcO=e>CVaCRJfKE(V#t%SlQP!AN6t0lD{7N4BBJA>T*Z;t+jECvU>5bj}>FcRAY=m zql_GN%OPnnZbXgCbOfT{)&=0U%yggIax3!)9+pgF`j3*d;Tr$2`ydXy3x>k%2l#tl zSO?m#D-jOED?v?I(NCrx&*l(|EH9oBkYIFfhmLCTrFJs`_quO{P{Fbn8g9Il z3uOsVof*%ZvycOZdv{sWZA$x|EY~ecdvhE_O`9RfC8CZ3Z5=QlH>v{JS+=^2V zU^$uJjT=pIr~5B5T;RumZKR^tq=+rHyoDN@rpI?fJhV0#DfVn5N&3h3i#Bg;A~6G^ z4l7qzEWLd`L7)xn&L0$E^$k-PJc8$YH$YwhJ3)I6ZSGaV)tK9`6q*l9)Ja9$)W=k6 z0Z+jG<9^~pK1%cGnfQ2r+|ItF2h6ZxuiI>cT)*J$ZuAQS(-8Nav3+LTbvm1l)S5LA zIqikCqi4tW1IZN&c45ZY(OCwR(q9 zPgUMSM5?n)5PnE?Mx(hb16{Xu?}xv<>He+M)Ou%w#MX#)Db4wWmku6nJJ$~jC)s~} z5x&Q@zG^DAz@oJSlWkx_VXDb`$T$}vul<4RT8adAyKHZ{LSda;tpMJrI8&zQ5)
  • ?x%bNTH0B#4hoBil{__5fiBnDv&=albuhh34$tE{uR^KTLJDmH`0#Af);B z!=PyR*I(XhufFa{s72yqiW+u$!M*bl-oeQTVF3=F(H?M-o!8mE#fGNuSqcieJBW!x zlwQG~AUQmF9R7Vr1)hu*Px?U#PS-q%mE{?d%iTasEJ{k61SNkT38zp-+!240%a%4hdC{xAAWngy zJH`Cvj~UnxcdpqoU3pi)Bz(QMkc;)?D;wk+fN{XK$a5qiMEl17JCk!7oAK|8;SzaF zv0lYCk+(fXPU+h0%y*S0wbDKWC4(fdb+orUA^_=66(5O*o!%jd!geYyA@47lX(zE3 z20-Bvk0Fo4sgj=%$ObCN9G%0Z5t0(NChi8&*zjSstdZnITdy6P#64E-hd?5VA3_3l zZ-(MPY%Hb%%ah1;eWrDemY;qVdUQQSbpVfU!@dO+K#Si?+YkO>%kpM807sI7sKpQq)_LmucNHb*lLEfx@*P}BHw@B@J7^Co>e?)R|}K9&HrvZ9+J zk?pBrfou6ICbM$UT>kzqT>JxjWty%*S1hq_*=X9Uth~%+QM%cAeSIFwFn>;-r&|<> zn>lCV(xTxO%a`alqD!ke?eMlG(_!BLfCG`WsF#4^jpcK0=R9X4*+7cNqWz3 zd>;$bKam<+8GSrOY*6>5;O#mf5=Y4*hN&j$wqN$Mf_n@xvaUiwU~GScgd%+tZ?ogS=9^WK5iUqc>4 zEV^(1=Ag)+fjGau7XA1lhSD7&nuG6O9UyK$aA14qreOZ^mz361kQ4chCeJg3`BXlF z7T}3OVc9E%Du?q@z%Z!$Gds^;X(u;4{@OnYU6D5ukaTpxUB^4UdU`R4P(T6N!$ZUc z2tfpaAni!1_wsMD!S8xlvc}%735R0ndX%PP?9Kf}J32#BKx7WIrbh%&@~}z@0)4PQ zzRfZg|K;#3=U;y=F@22{13Cu;?He+VdpIj(*t@^6Y-Vnz$4!0L-&{ zzBpe9qax)h%7^f-1rvJ$)QDFY#%=M@EIc^}I%T3kMeNL`U79^`)UUIY0O8tW)=3R7 z_TmbzZL{Ktl3pSCFQ=||<8J_8`elF1oTmT5&`LHzDl&qpA5D~J#Z`ynnu4lXgn6nzYUSAmoceRbKN3B~brPr&%6 zJJsjczOy%FyYIWJL-czrn}YYqC2y^XS5~0XLVwOO%gjvDvAK6 z@Ur8$XyZ6*4OmLU{wdUCp<|1B%+CF4cGQ27Jj)8Pc#(CFz$EIZYbo@P3lv?U8DcrV z64?9K6Tr_8=0T;_PaX`BK!QNSh3se+9eyK)Md`LGJ3o0I&9K%uDRG>7$$1?)=bKPj zlw#4;yRks5ZT<^$Jj$suHQUy!&g_R)hL)6ttXw|?b{y4GtvM!O7q(8T$Bz7kqp ztPdTkl*q@YI`2K3`+{YWRlio*kBNL3W)K@T*VAqZ{M5P$y6l-UTb2u}WBm)j%}^KR z+Wx(ZpC&c$&o#hGFx;mph~9U=KVdRB#lr8h9yB3olMHmQicW(n`EBSN-kZ}xstiYD z#8Pz?Y`Y}jfY+US=%!+*4A-8(8#{&tc36UF&+e5k%de8^!I2#oziYg$pwPToPXM}|9%Mfp8bzh8vyK9r<*06{R6hZ^mEL~7NoNHR+e0=W5N z2gPdzCtPYVz^HCzAs1Dv56Bd@$BSW{fy)$8LX|w6*|bY;S3&yGzKg9J9p&TIK6P4!i?wM6Dk+6?2Eluvw9PM zCBhDY4O7BHer~ZbGkD(rBEKc><&_hNOTgp$r8A`*h}Op&?%dfy#I_W|p9&GHSx%q0 zzO@XEYG;sd@5j?jVj99rzh`b+c|acX^C1dk7&)>F)$2h)+wdl@S!#kb&Oi&EuBzad zZF+(%IqY>lnbVIEp$SVLcpOMR7pxpzb1wGWT55YQ6~v4rhO^-XKqSej!k<#axnpn# zO+TtS;+USg4$V2Wq#Jo5mhN%=(YaGfm>11wf4KIi;|#(IzoS zK`)sMYt>vo5*Y()-5T%ei#2e^FLZXiK*oJ!319K`cp?W;y+{?9Rf*mG7jv@G>90)s zP1_3MPTmybMv?z)eDghpN$C4BZ7}cgaELs1SIytt+3>ZBoWSw`nPkUY1`*DYVTZEV z2D;~Ok(j-aa8gCe?DxITKRrGhYIf}gtT>mac< z%Q;U(!%o7y`MdKr(+sij=*OL$(=nV9(hvh3jLFQ8QH5S+ z3c1U_c$XV%{%+d84WV(H%hW8om>^$C_GGqO*832gKLtnvD8hbHB_M^{56<<(+Tlks zpLw0tgw>3bpkwVEV7aI5oBTC3Fpxt^Pf~rmt^kZdvM!R6?_M?RU;C|_L!itr`geb~ zoJLjDu5t%A|CW*DZmkl}um4R8-!@M2SucksiZ}LoWZ!^G%8d<1!owJHELA zNrMmDH5|GDV zw_yY6Nr%IHbK{LgZXTrOHvgoPIjEz^h!q&IKa+_$Wv9^6O}_ie8bAYe(zSg4((gfU z8BWOls~)f;9w)jMaJ9VZMB!PCL7*Zkz_uf5=*}7|f6#I=7kWW^x@;TN z??8ZPw!c4amZ_p*;MK(yB8ue@U;MxNf8}_ZDH0L1k94}fV*OjqSVvP|a>z&p^5<4& zLG*8or)5noE%Fu_o~|HfDmOzXKOt1r$*T394S;45RG~`h+t{{sHi(nW6_;N%1g6rg z@7qkip|Om1+3vl@s6fZq(`OmgT3}6Zhx(0@Q^((Rz08~!>v6y3c~KC`dZnHaNaTAJ zv*?eBG}v4rMi9$qyv3zaby(O*iKn7+x$M6sn3KIM{+4gB&)&VfHHFBB z06UmFg|Doygxy-JqE72~<@UZz6s3J(OI--YRoUC!^qUv;XB@p?Yi7hy_2a8;H*`{2c*Kw`kjos7hGAvzmb!PJ1r%m9#1zTC!(#2-Ch1d zS;0S%54~gRBOd&>)I3bqNYL%8Q{jnvq$$u^%f0(v)$U)}fiK-7E~#CGXzgvn%&EWj z+gHyLgBK~F_^gpJxPURK5wVF!FQ0$-Ak*-w`jn5<-RKpIfR0qBIlsw*v~y$;qcjy3 z^J@FluEUSsW0oIN#L)NDHdAlbv&=^A7K(j7sKfq6^b}}dJ99XNi_pSnMm?UfeVAjO zLyMJt=ET!w$4vev`9zqBvT><(O|HK!SIe0Dwo}@6HJT9O_Lqn=?(JqYzu2(uq>rf$ z3gpR-AkP}im-x_Gl4sf9p}GqCEY!c94(;HWy0FnxI5$ze?iig#2cLrivQ}pgoyKoh zw|?<&C|H1f4Gawmy=1Qs9#?8F_~q^IT|NQ;2Mv5m)&dWFV^`|+GkrdF+P)+O@e8EkGzAxF zsdUd1w^}7E-xFw&t^Q|(+hBN{g*{FcV8UN6B(|1|Z~bC9uDu@^G=tq~3FcD+%vnTP zEs!AQD{~hhb?(RMmpA`1LkDTVg=5lvIS7A`0!C;~4@~3)=+_KIzw7+> z84CVka!_UU1cF{q%zmpu0iQVPb#~%Dnxw40`FAAS;Y_Fub|Yo-gRGXx_%*SFM0W@A zTm9dm!!=dtmsT#Qy?ikN$XRN)>;T&mkwd4LDJV4_sp8g4Cki5gI$!Fl!4LtV!8&21 ziA%%d2E?-y^9^_g&|ZlLe4mU{WK%2Qc__`gSrW=GV@4#uf<3VZN@F6IT zCe7u&G(#J%^GVFTYQQ(Gd;(b#`AfMLKEP0af6hZZ>6l&Ud79+X;ZvKjyI9E@%K(Nu zdzROFLL|`ibuH#Xu!Zw?A2kz9En*^B+R}S`-}u4H%!e41-M@4*+D7CbMcv{I<>n;@ z*BYYy4Swc!xo?Xq`FJhr`>W}`K`S7t?a#VRc!gcjk3rj_5!GM=j*ny-2do3rut-|05rb~v1RyTM6HfqXZI0Cj|x#t{NfbytGTx569c z+sDc5*XA1^h;MZRd`gb+dunAJ zCwTT^j)Ez{OJ9O@P5Z5r31H9s;)&dVLa-NLrDH3>iqhE0rfV2vyOJdJcJrY08< zVrcwI_b<`HH!)E&Sg^{5Fx+AQ2NnxgS?(B!SRhuC9^wCS&sV?yy+Kfa6FQ}M7PY%h zc&+DWqI0Ehri}85+2*YPVDliHGJl)kFrf*XC0f5`?)%dXZY(X8pJ80ar91_m|%;W+3IX zhB&cfF=N8;YY5JaBI~S>Oop6g$`BN@Z z>qxrS4sqA=>xUS2+MeO%*JZ+7KbD@YF3Us|D~$~+(nd`?X5%*Q+=hYWtMv%!?_-oU zXpMjVlw4->H(x){*zB>)$M>iU=MCxOK%9vK6uU~SUmlrajY-tczu8oIf2{^6KRu-MAV-I7j(U8NbE6~f#PHTQr4;{5XyVeO`a#;`LTY= zQ=q0MRiVRMsu)n77PDD7zg+N!7);6{Vo1L8YXrOL>MNG z-9koKPks7xMm?RPVTtF9J9Wm=Gm*rC8jNkg`*6I)Pi;~A4m^P#`I`5=6ZhD#k-U`b zgRX*zi7D#RQNmk5azhE(53HOY*9_6}KqBIZA|-L$kQ~c2b4_w0ojcJOg=zt8veOmk z;F9SdB5{i}77D$)%yLQ0G;eq`^ngKv5Mo?$oo86@Gh z5JbD6ylL@q7ERB-O8*o<3_;$a(R3}_Mv5wqwCEyS8ekdt+7S5d`+qigT*um&Bnmxt zl)T*R^50GpE`!)_+%l!dXDI1?NB8YZ!;% z=ce$iarP+U|7Y}oIXfCHyOB$P$^T*~3)OFI^egQ{fiGG_lf%U0p9Kz1mT1wTi-Am9qj|c>tLelC=VJ z?6d84P#PYF<<7JD|I7{ zsOOgZH{i`E$uKQFpREl`7OX|u71;3N8|)GzhEelB_C%yl`8r9!f%8`2$Su@UUPK(B znF&V%CIJq?@L#9qV2V)S-rF1zuo0~Zp}eo@B?W8P{?p)QV7%%XSbO>@T7xDx&@j zKyxPhO-ue@4~20$Fm>Pk4M6EIAWlJawK~&%{i07$CN`+wZe`?1>C3k@ zPON~*)<|2e3!=xk;_wC;ugIY^8>PI;%<`4kF9@Z2NqpjW$#@1^lvip)h=|^r58x{6 zBq0b5FWk;qQ}lYASjqM}*&sj5uk|^K_7R*Bl#XQ*eR^n8Ht9IvarYAYhx~RTRjEFq zq^d}bjIR4w>;=@`YFU`*A3!SF;X(L3wbQHHnB6kxZdp0U%)QgGasFfTE7GD|r8Nyx z8n=n*u>E561JCj%(vGJslI0mf35X4vCLN! z_APTb*U~M%kIxb87|y+~3rL5tjfU-mY!A&xVC%)?Tn4Cu_V0JMn*SQs5m)2aiA}y{Y+bm~fXCpX_02y8$&nNwsJtX-16|24ohH0Rk=Ftzxh_0&7i#{% zI$1~xU78)Xr^+3u_7aY>8RO}3`H!=^>!leBG1H3BQJuI-Jm^THSrK^3R~(1jnN}Lp z952douFyR8I`XlASqg7;v^uz;&_@AC+R43r0$|#YhH7x^@!KZP7{7Nc_cQnzE;j0? zeUe}&4;>rZvysu&sYq+tU~v^?Yz6OkM!n6{Eh*SbOU_|k_(kfVmPriic?ms)tolt- zXEjf{zq$$PgQhtZpvHenE#X{)qgKTXIYg9hyVw>O@ef+IM)AE5nYoFi*NyQkjdaLP zFDs+kY`+=VMxXmvRh}F4QJfQIL(roie2)4>p)N#N85kuf0nzPK_`Ivw^8Ly-8#C!b z;+%OSDDnd8H{#Y@_3bFhz}J2PlKan!fI&W=$C||NeHG$lISo)YQgH_W#j>feJ6tE6 z4X*HIMTzJ1i)*6Y%RVaUvh-TrDz|){&I~MJZ+!Y`lhIkUT zBL>>I*Aio5FW1iTyiDki+sGpa9I{1$A4k^88%=T@HF!4lKCfS=jZUP zP58hBYt=obeRU#X%RVb()jO(c%t=Q-Axdz8Cg59P&Ssv?e(=L3!8jxJ!?I`WK-F+W zoxKQQ_SM+|i@emVf?lH2aJ{GI)$BzOR+eVb3SOra>%1S4SLl5=vC!juh+T#6V`fdW zrSYq!)p#sbWj=>{j=3d03v#7hy@*#S>%FaISWr>Kp2qCPR`l!Jqd&5SKXawaX30;K zI$r0jHr?1U3x#y52&MI-ov(nbgegwicY?294}|t5@s2vL#}iy+&m~ZEy@b8RZabEX z@L*|oGUqy{W_B)g7YQ)DitD1pJq-#H5j2bM<_jCFV#ReoiE30@ed*>~dYS_1lhRPM z+r{8CAEh;iUGjsithLlb@i?DPu%N6$s-a8-1!@NNSOTNXtCmxiZ(Mfo_Q_k~yvmDZ z)(~+EXCgQhW)i!1j=y#GuR;ZQ`{f9is|dKG8hETQjEb2$_};4bFZ=Uot1CFSj5CuO zEmh5m+Q0t!wk+m1kmgUHy_kw^hrT=ZQ0u|KwyKP3z5P4Y)qmIdi1bOCW(~=ZYMJNX zISBa)z|}t&TBvT~CqW+bK7A@shD35H`rp}%;4SB^iHg`F>-dWQx@?TJJ<9)*|5}kS zcS#s67VVB3J_^Qwj39~3qBzEWQFvbZ6*KzC-ly3AH_*R?NY(G*SN}l~D{ejXJREf) zHDq~Z{Fe>GEe6Lp>+KLzsfk|*)gTwlFfco4T3A?u9NPn}T9}&2=%?>*% znjCmnXo#=tAy4L(ozz_CJn21-^|zAbvf*#5>;zSW1GF5c6g&HAk58j6O727*$HQR8 zrO-(eds;;XelYSyjB@>7$qbYGx>k5)@N8?PVO7c&Y!mQ%LI&p~>0!fI{afO0gr#-U zcJgWHL}`d0Xrx%Wc5fBLsr}=XTO*dEVD3O!a+!{vgl}1~ztO#iO?`Wvc9Jac_3tBV zN%6)9DgSUapvtFr*v?0-2xLHIZyJk%oktO7U`&EFaG|)K|IFv3nxbtRG?;l+Dl{ zWC0wSCM>%!8Fg#J=NdLc#fU^+S&F`bcF@C!9Y|`Wyxn%wz!@w0wstawtI(C*fjZu~ zKW>1eW_Hp1bMuFpCRi-83H=sSk54~9aoS6#uv%tOy@eOh$|y?RRDEDV3+Gc}|KIxK z57MRn7@b7}d~Z^mbQR0Se`6_wsnBhqHkzsiKFdJP@rO_6>zSO3Q4_lF1$-eS2LO|b z5bWKXA^)kIXN-@n#Z+mcTrS`9VO$8v-h1~JMG)!8+(N41Q$&chsA z9(+~vnzcx9u{u1ubYFf_Pzt)PyV}(!q%S~dwPMWN5_9Hk*-|yMl~E|Dd}voW^fYGt zgz7k;3&O@smGt|OTtfPm&b2*k+I`Dqc}}_(j+rC z{s+%I4!^L{4ZfQ$y}s9rg@{`DL$K^Ny?N01Z6RKE=xzfj=EjWo8JtC*m~5FQuPu}K6YbjRa7$TNQ$oNbVBI*v z!q56teQY`{zq@RtwQ8_0!Gb8Zbsu8=>?R7A|B;|1KRZ9*FA+|Z(@+*aGeH3)3k1@# z0`^w_+IeMMjrYxvk^cR@#LHoni}x?vD3pg&Ks;Wojs5++g%winJ=*1V^@N|94rk8- z0Jo0&vAxz7f_}No`3s!K&)Xx4j{Xn^jp=q56#50uNA}$y@A)?h090zK#mNEmKyHvk zR{zaFQCa)XWIs5jwXy>4eEpox$$vE}@ToegB=k`3Cm!&4tUhmHC!96*@fVB%INSB- zr2s4nOjZ)h=wT-itetuEuqG;fKSxsk5;|Ppg~%TOku6(|vYWxSnxw&QK0mu(wmw9q zevjD{hP-!B{^aXqbjd&VcA zjKD#*aqgr?TJb-&=DevdpCuvm#bMufSk8p=xVD~kaWIapvD=3|=K?sVbi<{uKIeMc z4L;nq=)(t`6V3+usL~xf!~xet`tTtR`sx$rX-__j5`A?~oOK${UVcGGv~Rmt1k4Ki z(d~|pOgM6$P77zPY9G6CE&8kw_zinCTh||!8r}GR>W%Vojamp*+g|A%J7zw?r5uc}$1?TIOm%9l)uR>O&~$jy)QZLUc7 z#lZ%1B73qR)OIV_^9j+Qjva*!#=*I$v3!|zTR~`?T>|&o{LItGkx_>YxKi53Zs@}| zVcrY$+oP@!JsiL}qRJH&I-+N~{qwQL@-=vqZJapZOlw-zaNuR!V!QqyTa&f=;GER> zzBtTQ&Z6xWC-|deyIZpP7;U?s8b}rY7Ij>$+D9K^pszmozb_6MuJ76Ky94+jm$#cf zs&vQOW%222x9y_Zm(SywPlIS9WV;__L7@Ey zzT-KLi)utUVv#+nh8r2x*)i4%I72MILwLp~((2{|4|W%QaFC7K7l(7nzBoq);CwV- z1|A&1r>_mL^+!GVkWu}vL?2bUeTrPi2l%w_`6v1uRqgB3w|mNl4cN`}<^21F z@BkZ}>ZuQ_e&5v>n;&W9vob&52 zmaRY1*cr!1A4l36J5l@SvsU9hAAMBm_Rm$x()a9+Jk^&E^Q|w=CgE&Q?PG&ul8yN3 zg`@F(ai)dS*FV^;Z{A^Uvj+9i=aTqXg@pJ{>Vv~t>TLj*QGAdM+ja5T2pLzH|CdzRV-nw3>}c`aw7r^#Tc_pQ z?hZdN^?&NKUlrkZNcivvAGs;>p4b7_V*m18tbbjT zEzU^|R(Vtv+kG!r>}GM#c_D@Sj^StSM*O1Gw=^z)1^yxRVPlI)qiu7NuT1K@*Wuk= znv%OUwCVNpOX~M7HP<8BOZ#416e=a&{|wFWj~TgE)wo+kw4nc04UHR#fF0UL3v?rq zD?qSSe+up2YtVtqEIEZ1A%3kv2+k5f&q4mG-UkJt}09Ms4>y1j&8a`}j2fyL6r&-4AJj`_TNOMUB9 z!OJHW(!_Z9N)ZownS$aW6(Xu>v8&5(6rLPIekKAXm;Z07FP9(g6Z0 z^DkzYcNMcIROx*)z*7!NbKEkF&n^sRj_g$>PeFmr9mRN5DbNeXE*rAy0kw{)vVk~U z9BF@+RcwP)i`H26fLfoZewI??yu?08RsW^HgT;fTRVz-*YGf-Oq0MQ17N1St+r^4J z;8TyqlTzdJibK5AY{l#9{w#dh#>1ql$KvAx)vfrcdbyNsrv`0wZ&ts_TaCqA*NWux z_-j#d14Ul{Sd$q&V!_6-kYUNHsU+Aob*@POwG!-#{NeF_-Cuxgrz?P;{e`Eu zf*G~2ed}zv)vj<=b|!v}3Jr6AWRf-EA?FpXHK`;RgSonW67vT)0VA;129k_!FI z@4)=8$w6V7&Z0c$VwX9Vs8ng56HT)VsQy>)n13GTfA#LP@H|a>=@B$Gsd|`~Wo-uY zG%sc}JziHVVKdLq|3c&$!R*)h__dp46Ja zCN_&PFo_A93mlU*Qp@0}C$%Q9?+u&9t!N*=`!$@k_;Iao+jQg$X#Ursf!X>_+uM`R zRO9RSQgJNfWAVSR%Xrp(Zl|+%%K3rIwP}u#W?XNZX(rv%UczWbJin(CNfndWw<5&% zq)`*t#4a%gCNW`ifn%~pY8gEBq}BvBv003PNle&W;FzqDS`i-4-{Ts`d8)0&K)Zgc zJzsAPZ#rAwp?R=aYk4J-zh1z4Yj}P6y)6V@Z$a_vJN)*F-!btz7~n}`_-)hq_x9{Ie*^DY5=R_ps*WcCC-`(`5bYZ|mH$@$)2hznATj<{$TSHY%tt zOy-zPjLG^}T7pK(IH_d=Qcr44V9{o2j+sT`5leNgV-YVr*Q2$MXEUb5<2T8|_lpAa z_9LAio=Dx1y#DhX!5PhGex`;JpWZ1x#ID+Zt{2;NW`O!ALAr4`f8}LxCIU1@;jpd; zJea6N4&8j9i%!Nz%^IKALLdFH{ICvlvca^Dmj#2yjM^XQ$Y-8681;-UQf=pJN^+@muhhMD!x4Tq0F&X$5~Zm zzak0XMjuwvA?UVfjezxuWWsiB)dts}Kg9ZI_0lU#3V3DAPaY_=zs2j@99FXWjsf%CYoN#D?7iEby^w1<-YDKvJ z{It3v=K%YL{zK~DDyn@Z8mN4x{+Q~o8J-;#2B8QRsc?kSWqq9#8c>Lp-F# z^#iRlr`0~F$$eTmW53#0)jq8DPL12I_BDNF=mQyyzBPg$S06tt|Ge7#bOSu0d7q9S z>ewa&{O?sgtTAUrk8wQ9My{C=y|u;hjOedZ`-1ieXLMX6{h|GdBKDN}7KC_BeQ)dd zrjEQ+@R(#nhkHfmapCOI*hRJ95#Bu-!*jX|s#jEL^Ga>_Vt?eiqzcU?eSTNL+!am7PD1+qJKW;wv7M^rsed~rk-KYXGiw4nc+KQJC!&LYt|}(%`yhX6rHQ0eL}RJmm)zIje+i3(VS6b{7Kmd*hRH9{01+!J)y>B)kVcL z^yx^Z9=ye}7R_*_@zh)(7=+KkWjf!1-&_a{y^p_BME_q8rE6s&mR?r*(W>eaMO~r*vGS0ox_xqCUT= zSf3W1W9q+4pO2~XQexsCz0b-SrvyK&e(VK|7`v=Cv9eKZ;`6%tk>R}B3#v1!#NSo* zVTO1P+spDxK8SlrORlo5#s`g32k&!Xbpq^BnRlTJC zcXb4Q<RaklSBT%WMf<39nW0agk#UczR1dL^%|BMXri#3mRgo83=(buo zRQ&S)0{{U3|9AmxQcY_UQ53yxQrnt-H)^P&U1-&!C4yoXp*kOLk|~p!^vy&X3Qj53 zv=oA(EeaNNBZ{D1x^e9X-Ke-Kb)((6@((Dqpc@yus<`R7!=%%Z1TJTC?|J9mci+iS z6HOD*@tKi@CSWt758>u*-xi)_x}Gm=Pga_#4e6I}Zsq_1Ed|u_itni7Lh}+diT}fA z*FLihN1E%p>brTx6Mn%IQjuDrlB7E*{8Of11LzBw-7%u==%R&IkbA7W8@~i(vCbIB zboS9@WLB-Udr#Ymo*{bT3{S{nE6pLfzOucw35_j8oa8X6jgla3yvRKO1ie~-6K^~u8XPYo%>@??r$p|mk|F*z7g`hk&(Q^I0AM|K3= zmd3KnBOx!o7tJZEoxAP$F?cWhR*{w`O7`RBewaOdgCC7o7T0Cs9^Jm+ z-rv%9e>Wc1bZ{l3pGG0{{_w9=K+wIu#a(0hs^W??&0(~qqni(T!n&KI4TYXQKv|Rr z*8g0s%MIaU!n4rJ)(S%R+4;FW=itiWGv~6|v4b?4Ao|{sJK2gOJoEoY*})Bu9ty0+ z9r?!t@`e^`x8|$0*=vLIwc8oWa3*o#2q0h_14d);?i9~dE#XU%$B06@I{*Lx|NkC7 BAWZ-O diff --git a/CPLD/MAXII/db/RAM2GS.(0).cnf.hdb b/CPLD/MAXII/db/RAM2GS.(0).cnf.hdb index 28747003919342ff39fbf29d7abe783ab6e5e131..178a749a8df78759b2baf313a5c8682a09725e0f 100644 GIT binary patch delta 3221 zcmZ{mS2!CC8-^QuBuJFn#0;hOo{8-@YkWqnm@REkYF3amwrWwMtq7`$wrYlo(P&Yk zLe;2EQ?1$BMg8BnzJveZf3N$xpXcB`dC%SoVZ3mz9eMzG?(g|X_fP(1JjXvh2C(jK z6YBQ|&n+w8Llk2{HCKuz#8~i|@JXp~U$L{W;Zr|p^le)i36R4|x_B3CeHhCk53qqq}y*Kf8kp?(U*h`v3Tlr>PRjMQ?J)3==u!Z)gG4JJ1V z{i#+njs)zrI1^F1t(h^suBM1|gU^@*J%H%JTgQV#dXy?L%hs<5_aIQDs%Ne6vt>c& z53yg6qKnyZFJ|~%-#l9Y6PoD~2v$WVr@JJuNYB~gJElS-^~~Q;*sc&i6l!>s%IPVz zUZ(g}ECghNK7bkAk_xUV0GIe_Zeu27+Ja`tC2y+1P*Wp~hdYZpq$&tija4aDu21CzMw{BFImk_k^WV& zN!;ScbuGp`#YgM!Ya{0cK+)#2^mp&_bcSmgj9QnfhuZVyD~kvon^ftGtmjC#<`gfS z%9AoHW0bI;R#DNLGvOA*a0}C`0XFUP=mSuP$3XrO`q$;?1^RcB*B@OSD*Eu~+w{oAtMvdOZapLBiiLhb+sTpPoN-_+dUVdrM|V}HAe)I`Il0${iJGdyv~Lc-*~ z^@93Ndl*04g)e)*==!?rZxDvE+aUDD>B)rNZnQnp2d1oa9t9lqm~?S+ly~*=zN-J( zow1|kLGpsl(~{IvcyY*cwy##1eGcg>D{wb%qtBP_Q+V&Xg^sMK$)QNhUJZ*Iw6LzR z`5*&X7zm*fe>u2%N;UugAdj+C$x~$fE-(~gKjveL#?&zJfFK|wC_g}MaWIs>S*US# z=yJh^(f$9W;j+;*eK9wuzYTy#HdHnzE?Wo?7wXTl>l!tQ+5kmH zJEQ60BcF6G#sa1m`~6q1uoF*eE)Gn`m^Y+LW;#tMYkYQP?nPF*wcpZ01H`qzEj<-M zY$PaIrp9{Tb2~HLKi9w?&4CgEO6MhV`b(%w)}VIECf>i++&>PEO;bW(jnxW87_3~M zwBO%852|u&XvBz^`URR}(yoYZi1_pfd<(>F1$GPsJa0n)8Io5U6I-Ku*+J);IW`_8 z6dtL`gN5y&Dqgc{7 z092^`976V~K+XVRcS&#@G+!NbX!ayoU=Jx4zDraONwRDkGRYY1q$l>Cwdl&F6OGMi z)e6R)OIG#oIIQI8isu65Tf@#$gLw!Si%Y|efNNFnZ_zu>%YX$jI-o&!6@m{Ll8#N!S ztZ}dmbxO~cdqtJxY1U6LSl1GCKuTC$ON_1muF+Y!S!y^`YU{y9`KVwTsR33%i@LHr z)_L1J$VVu7lGCo!d`H5w4&2k;Ey$|*T?Y$#x>|4PasOjR*!a$OusDreo}_I+Gjc{~ zR*+DF;rtg4j-oYSYc%asp$M;PQW^S!Xo zUdn0l;WVhtxq6M6(QeqQdHAPHLT9oSZ!1Ji_XC~QZfk%7+fpEucF2vPjBN2rVbz3>E4w3v! zUTVb zKc0RN1_yV2qYCVbz!eQPW-7)dPjeUrW{{H?!1WoA*<%t9=yI-Mi5LLL*mkYlZCH@U z^#(irbckPflEg6`Cx=rmZ(xAQ9gWs*0!dSd|6>yno2sCI;uof5DE#M6-%Ez=?8+NA zYXAz$OK1!oL5DBtm(SI#`}A2K3H!M^8ul~l{cF#pEz??^b1fVb2k8Nrn7uK+mzZuP z*vsZJCG3_L7ngF+x1ee^e<4xNh3*8Qu=&?mYI%UVdv~1_d6`c_iFFfBJJRB7pyk~( zaN8Tmu#-067rg)ZIU~OAxDtdZxXx!ityI+Hi&nZy_8G;Ds;o}a{*xeV4V1qH56sYm7T0x( z`)}|-lVOM@dn}f~l8yjFu;P+TrWPz2^&vLGa)riqnI}eR%}D~JZPyT!zd1pBVU_!x z_DUEb(udg`4F2D3?DBs8)cblb-R_;U_j}3pl3(nvzwbe6CT%;S===~r2b0am;l6x> z5b5mi9g6;t-_~G_5_Ru9%iy1i=B4sp+m`#VSee&8Dd|)A@SYH8qjPH})jDR-2b;LQ zU5lGkGn>@TD*F@$PO(T7__2&e=Djmsw;OpNJ*DB;yzQ46B;yNSug1rVIo}hwSEtW> zL;MRxJs+h;>$eF@FHSR|zYr*?+cOR~1j3U(KZtm9;;j%PdwX~+wWM8lSBlf+8-2;h zJTYrwBECC;BFrXRga#=`g#e`z%Z`fP(AcdNg)F-D_8(<^(|8feM#i9fn1%H{S8Vrw ze;t{5#W{yr#P4gFST`R%&ZR5`i~JtUr5$J1gzY}#+QC3+QpmW6sf+VuX{sMn(ouXN zfVF7Oo^qm+)pmhN8Bs2I+oQr=3(V#BD7t2PI-9C{+ZQ*&viyt-%I z)LB#?_pk-daTz$g+DgbxgdllOt>-0B@ybA`aD0`@R^nlGaAXaoe2LXK4nq!Ci2d+T z%~sKj%W?T60%qLlE@T)L;}G6np;?_?N{;7({P_UIZimOA7n5Q_a9E9@cqK}O{iWLj zjuJ~E^8H#Xt7NEo-=pO47p_I!LkMygPsHvOi=EeJw>HIL-GNk2)!BKQDTtb%*|4Ec zB9*|Oa&*eo$eXca4y9PahW|j67;-3kgFt7F7LI2<1^1wbX0TyV0UpM(HlfjzxU@F= zD*-^XTqXKwjZ3u%{}oZ9n7Sl{E2@RkI1w6{3-1S^lnI1J7kD}+6~PW!A2sBS*xmVa z6{!2?_1tXF_`srA6i%plpz7%VIZW$%&EiN>iEdFdud+ ztROZxDm=QOf{*-=TB$p|VOK7bH${3K5krVbO!(cU-NuFAdW_%via;z)ao$tRkk%GK zo7^8=v&*+?+$F`Td$hNZ9))^e57^lF)VxmLuZvt8OruUbeS=MLS` zUp|R;mAjnx9^CC=E$-0`k=WW4&1PO+<#zZA!>{kLeh`x}yjW|lTdBMLh$!Q=d*rAX zcctrP?Qbngj*I?_3x&56HN?S&GVZtZS>|QDZUt@2M(Dd$m&Q%i9z=~hzxdfPJ}1SQstQSGKX|L{yeKyN}aKjV6+A#N>SCKYR@Ps zT3WG1OO2vx^mU%|zSng=oO7M~`d#<`_woPXE*B;WW3AC7cA9@@hVDQ2zncjBk4Mq& zIFXPNraU5Pm< znM7|8x2~tZ+9$utY# z?vwiOv(M`(@ol$dx|30Rp{OP<)Wt=lE&zET6s0$KGQf|Tc^al_FQa3&cer#4DW$%T z2L4lDt}*GFtLapU6h-QO>}qa%RD$}F9H$BpIUj`X9fBw|&HPUW71iXebj-6qHMJGU zbRUSGap7dM;jT>ZT(rA->np3=40;y<8%t2`kkbJtE-DKZ-8#P&m4hMhbOe_x1h&KM zqnv`O@xvy)9O0M^UQqv z&792g@hf%)YwcOs1Zd19z+ThA`D>231Qaxer@=?$J#6nFc_eE;vyI;F-p?1N_+8zN zJUgF&GFHP8G1jacv$3h<|A!5EGw+|(`sjPfc)+2+grCi9MHRdX-jLX0DH&HHPb?NK`tE0FPygF6BFy2ybCA{vtd5ii&-b3+G@!9Y;lKLE)Rte%){6aW85pnD7?-|3| zC!nEk?i2^lIdq9m!o#5_L;_RtLB|sPJc1+R`xn^OtDn21Ke{Q|a&IM?Sh6@B&N^7d>lO`XPL%Pp{u-r~=(n zZc3H(K+K})^I6wF9 zUbooZAnu~(D;%pIPYR*0E&s?YlEncj1#afE_kTYN9IbWWbR~XzFy1o44OQ0;U9MQ8 zcnTiCE`qE0?~p3q!r9W3=rhN8hj^vNLOkxa(A#mgH`M>Lz)5Gv*5;s(s?ZyM6;AaULFrp=|zF-r=6RJKwcW=bok1!Zi+;g3|#t2vCJ~on6=hz-GfA%0C zztQd=iSZ6_v9d=SbpCzUGg7aRM9$r)0Bqlwk*U~YKRGK z3kC{JDj5x7SOs|K|q;PK6+H6te2!eXf!jXdd+Y^e{c@!n`gpb-|om2JchVQa_-%=#D&y5BujTgA|odwApU! za^HHTY=7Aqy7@#AWJV~eXLpKu-)4($K;(KysOEPAzPc0*DdFVxQVxBx z+bBhWpsV`Q<2QlPJ*x`U#$&a8uI}q~HxrzQnqr4?T6H3|Tz!H5Z75N{NY!J$@MtEE z*sa3iH}B9-Wu5xUWw|TQ>Wz__fNHAKDn42EwxWC}$Ik-<+tF*bseL0K9(kFCei+Qc zfMvFV8xhIjm|g4rfI*G0Y1#Ucp0?j2$GMzGl|M7#P8R2s2dy{U?iJX;FH!%he1O_5 z88GZ>VJ7c=FXs`iyWv>h`YtbN*Z3Qf%AXBcFbwEF)r{=vL>ghP39941qD$Z|!xY!G zGCJm2EdBTEA0eacSrsEvPZ;$NP!fD1R{7u)Q7nY!onAr$+(kxp$e11i*yv+mwd$x( zPDp3j#Z}5+L*m-hXb$xsKtouFDUHT#33n~@5HyP7Gzit zrJ~of<9eanx_LIu9yQFztZJ>K2y(8zY1s zV->l@Y^4p7Y%l{A%q(!uh=y-Fc5~h6zpbq+DojlM0{BqJDG zcM~JE;iOK@`{!Bv`(qM2WY$2cQ_YPVqDoKNR_)v@+rFCV)B{;pn&sTdwR3S|1^dH% z+#^|=T}`7Bs;2}DG?OnbU&ov>Du;9P_~qlW?}$L!hp6LOtogI1)E3Z90v;bB?o`Dj zr+#B*@i$@TAur9=#D3lMwJ5M8)H!tw#YS-P_U4>nY3d%&qV`zHs=BYSvp(h}K z<1EfA|B5{B&PVF~!s#S5vi;XNpW`5#O4Prq`Gvd|)+O1sG`wq@17iaK7U7A=$%^hT zDv)5$9>HXKo>G&Ek#trsyF^1%V1J&8)wsT#rdi?ZtQ_yb;_ALN1>5~6WF#IHR@-Tz z5RDxdA!AT$BMCeER~6BF>M7h4J*l`eUv^1U#VMw5ld*;mD1mk>i@G%&272+3m6Y7e zB&=h%e(UI8RGX!jPF+kSy|s{ZobREt7-4Yk>xF|D3B+x`QfsV-G=D#!w;M|Y)eMW` zg&9lqIHDsz{Prc0F2Uqdua}2RluI5mdklKaZ*)Jb_fl$oYgo*C`ont0Apk-GlQVq8 z4=DstrU`TbEhkf^{8VFJh>(8LWxRIe!Jwox*@RJE4;cJ)g}}!Hy%|%0*A$Ba85lI4 zl%RU-r#1tg4?d#Y)TbsOi}Im zgQT+4F@BaibFVr7lO+#V@m{~6J+uIlz!Q6^xMLf1sUEW*1vq$GfZYTcPJA*TT|&q+ zmj^>5;5Zd->PgmPx~Vwbr>Do@);mI8s^uJh?|3}`hld7;!y=o~G_g(p^wU3B(sJrg zbHw2>mW0IAtmRE5#A(mOX|Hcl#Wr&dNS$JvNJBB6YpW^yBrI`xDqeGaOIb;$6L+$Q zMO(pYXmL%Q?1=YAc>m2|+OJIbG9BjL0V-mzr1mry8|fSSVPNwFm2h!yWO^8;VDx_a zg8}}&M52Z?)B{uZQ3);lh(U!yPw0`bf|=}VR?g2`du11`znN5#&E9T(4N4Dh)Dzkf z*)?$>Z`9rt;D|U(M(O74hNYc~E@i((uZ;vAgu%)uTylo`iE+;?E}bRcE-vbQH;n|W zb^EIReyCS3G5uRndn+fBdu{)Y>Mk(yd~NHSr}ti&kZZkVZp|g3z~Ueb8Pig3!II%~ zBVXaMlomhQD4#57U1Y9uMCmG)zqjOitG($}%dd#-vzWQ>VG9AzzX;B=JtqyBpk)^+ zj$d5;kr%70gL?7yB&h57QNO5cUNtHJ^13&+D@ZF2&+EFzq5bm zJ6qlAbUF`7ZO5&D$$#frY7?|&Pl#PW>HB@1LmO3_>p zcCEBzp3MZO|KhagI{sfIm$f`6aHSU1x~OJqi_p(emb#2JLl+>no3y}+(&w7EtG*_1 zNuOYajnH@s2Stg>a{TEKm(Pc^N5UFEJ1*)wdCOB`TogIN;anGWr3MfW{KE?4rdXgK z*SV2cY2_z{et&OH{NpI?Cz(Gy`WX9Z^mRP;Yoq5zf1BD0-FA0gPd627_x`dgT=#Ny zH&|~&ib{zYZf?U9BH`-0Ldot=sb+TWSgwqi7TPG@c}pfUc}_=6O$pmHe-%V#2E7o1 zcY~0AA@qZO$l;I49Mgj;dQ12uBr<%*!tK+s|B}q4o_}wbxWE!dl`izfhH#sHAY@Ux zv9~_GK8(jqXMJuX`;W+sj?(^4FzE%saCaHSU1t9-nT#ix0b6{GQ(;OCUqoqK@oxyW z1K1V_SA;VYoB3bnhWYG;HkN9;`C$?zU=%iaeTu+|56A@PLD1U^!#&rN`-BaDV1A~I UbYb>?$_It*j`ra<0FzMy)x3}S8~^|S delta 529 zcmV+s0`C2%2Brp(Pk&Vc000000027y0000000000001Tf00000004LatW@1^(?ASw zV8Hku6GFg~pLknyOwo%tQESx<2MFG`!&#s5WgRm(nsYqg-(MKxDDgnkOs#CdE8YJj5MrUTZPJ~zm<`ij6+ z_!ui}GL7eORFtS}j6WrD{+y&u2^;ZQaaP|*TV;uGS>y=E3tiNe8bLJjk1LFtVu^lK z=SE_sl^+-Soqsv=Ps1dLQ-6H&A@Y;(%Vgr$MlX#1I+YhSZ7bH^{pD1+?$zl! z*c?NGN@a80K8B|hgsbmnN_KxpHMe`mbZy0Srj6p8HzZP%=agb*N;shXs~|LU==DJi zMnf?g1Q3Xz&*o1^oYI3TdQ142No4q*h1;iN{RN3>y?;0;afu}yR=UuaTg-k^yhU3|Www7wA`Fz000000055w0000000000004Ii00000004La)K~%OG#0eo`jW;IUph{Urg<-nJ345)M^WA!H$N`kQap34hRSOMC0nzMXmVX5ReX zn>X(p1z?OENR!3?X)F8K53+rv-(SNTeUkAC;NoZPnIhsGy}jJ%7LZ&z3}2c-6QVn; z>`O&RB%TY`U&oP_%piij9iw~Q;1h4oQ&A%uK$4BZQNR|b5mnHs3N)wD8E!PD6s&Gw zau3#rfZ=8M;(xEj1!-?h08=WrdPB#PGIEi1vr7_@m5#dx3Q^ysUVn{iC1#i5D$wU_ zOgwNvGBSo%K~cIHq>`o-Z20YX{ASkcR-q7(r#hf@T?ORC8YpZKD&V3lI*a;yGrODIyq<;tTYIjq-?!LICwS+HhfLdGw1)zhE@ z#(&YP&n$AO1UF*v%45nEfMYhb9JV48d3^%$p-awOg>qb{aN|S6EL3ePaxPMDEsEGz zMaboDr0}A^Dvxm?in|qvN3`WsCj_mL`pwt+jJZ)bUxq2Kf#_CERPeA#3G(wv>$9kT zq2q2z*AGVVion=`a_o$(jbYhWm3^^b+t0_M=3DdM(1?$^1z910OEEf6&=gqRaua(}5V zRm?n(@yDN6@UnzI4n0;Fb&+YzFNHfR9rJ@JJ^V1rF?_dyj?khdElV?+CJO#wV4i28 znkYIHY{cqv676OM-D?|oMWCIHlP2^;jEwXWc?Y*2ZlZwCy_OM{9PGQ*IqaxiOe%UvnYOU@xk|Cn*znGT5gG)FMk2st7wZhb_`ZVh)$zZ$~AV-=$5@}#&WY1yVhgM zk4)oyt!Hjf%>6Jg<8^dLZX7$u!{Q}h%(L2Ro&xY3lF3{noaKJz_+I!&l}UymreHT% zlIj*oWJ8vP$$iM7Artu=^K%xK2c8_@6ai6$_cLfPVY*p}1Jq4OmL|**8Gq}FS89#A zPlh0$pp_wo$NG>5AxAyNLRr86%wbj{o#CcUk$bn=##SAFuEu)t^jNY-W8Z60;rihcW&Fs_(A%)v-`p7$PGG8HU8Y@lSmaIW*ImAX>;QR>B>{z?Ok3$o= z&VGefl=xB|&7!bZXXLyTCVw?a!=!=8VW`oJPesAAn~=M&b5F)7!m7ilo6yYjK$3Ck zW`$^pWo9+aS;o{WR#Ga5DE8(M7Jkp~nqeMmX`X`GMBE+8VNoK-GZt|aW=1%}rGYG& zYe)&%j<@AW4Qsg@#ejNHo;S`2c>{i7&!jn-QGULG1>o$nab{*(U4I#879PjEmbwDo zGea9X{Bf5*%_DA>ai?VBpZ=_EIani0{_CI7iF!J-7k@L4syJb6r#SO43%32YdER-GIUup|F-8{zx~IXEZqVzuXJMJ= zlpOQi_3l7F&-E>y4tMwtc^=mdnq}p3Ms7{c(9I*nnPdgCrR_yx55TZIMF$Nt)baCe zoaZNk5lg9Y7ACKH*>aR4A?7S*9AUP6xVLWkQtMQaX^z8Pm4CR(DaK&wA{Lsbt?L$^jI z$sQAVC31evu%c$%d4Z26ET*nYe(&*k2A^Gv(JE_Siqw-b4i5a4smJFu@6P5aG+N7v zi7W%ti}2u>J8s1(A(GF9F3FKYtRjJng0DQ_%Le=n6@N*-4u=fR6&2NnGaQ-S&;-c+ zhTWrIk7UAe%USm$nWq%uDp{I%etoI;Jx?~dU+XD&X3N55&La&(9*JC2NT-pHj=|3^ z@vR`XnCGua<~f+>_%tVR5Sfsd+h}~s_`Ftte?i!7zSM?bUMi%>YeYxL%e*TjB4^B( zw@fPWZ+{=Z(BV74YY?B#{H@Atd6-tpYC*&?UARPizkqj3`1=Xe7AtvQ&0v8B0}Vvp zQ#l~qv_4TvW8M?{64m_9*@3z+*xw{HWFoih-H-DBETyOi)pJ@8+;7+=@^03Ky6kyKyoDVG`_MSc z7AppId=D-zBY8*RD@x3d#WZjYTCn5?9#i;FF(;a^E|eih{`Lu&-dH?HmoE4xkfaN|7&X$;Z?f4hsntGh+NsN}XKK&qtuT;Kw!}_|FEX*RXRjA=Nd@Eu=%q>Ik z08V*lL}QBY-cyWuaW}60@O1V7JC6pPjkBh1|v^Zj{o0|a!^>ZBlmQ5 j-mV9d<#=BT&3B7=e-q0E^y-@u#{yaM1CQ|!lTHe4-&5q> delta 2590 zcmV+(3gPwl6uT9WPk&Pi000000055w0000000000006rR00000004La)L2n(T*Vds z?qv4v?3QHjnviv)D4J|+ufqePsH!T|M&pe`Z63%%qreO35(URiQ501b+N_e*tQDx8 zhvpIi<*B`PLmc|hAJB)&NW8#HU8xVPR8^OVrb(qreLz);z<=p??%hC27v4MT*_ktE z=A7@GIdf*#8o)TK6vG<)pSEg2%$SNvTj zd2<>ONxH(ta9n54kQ5EWrmAp=(}0~JqG~bj*o26ON(xFi9I!)*50hgYjY*PMrz_%6b5AYbOt)qcD0Np z^0G4C?9D{J44f5-EMI|qfovk+&cRy~A2T?o;Hx2QfFIPF=#hI#<4l0XCt$y|1grv` z5ZCt~@SkF|&$C95_S)iU^2N*7LhLH63>ZoE5HC}PC|wPXy632GAMj=ekGB#Wn}V`| z$4oUx{eS75J9lKFl){R&g2+87zEcK1bcio%H5qvS6C^!_jF4Xl;2S#V)qS>(cq-V|a2d6wtJ z@_%nT;uT%}W`Lvxbals8b*TyX%Ww~eHXVa{=t-{|us?D(W)$deKzzPUR1^kK&>;_7 z)~Ir?{zgj}=ZzJ!g|Vfe8F*k%f z3VE)LlGqM?&fb?%^rinVo}?aGCyh9J*nbp0cchBk!Wk0h!`#9SNJ(xHfdw_3Im|ov z%%su4s5tjWV%G!rtAp=0!N}IP5oI-%d>zU+rtk^$Uw5RzS?9trhw1IXYPIAKDwWhs zFkSU;mmRjE9Cu>^4~X<@7G~#+_`!9lI^@iMJEH*4Z?RC%JoY~YY7(T(|^s{ zG)Vbf^XMwIaS3sM0Jj5Jd@?`5Ir>~WzY71aAu<-vOzNzHWMML=())Bw(@FUt!fxoB z^(fk7Ih2>T%Yp2y-&K`!m$eQ^7LsT=#7fAD2Jq;Ra?5UwK2OWgUD&KS+xfK#{8LFM zwTQ{M?oxz4;0cXFqx!0v)|6ySI)D7BEsL}fKqx7rq9w`YMz`pgz6UAJwpqiV&wC`N zkTn>ETt3OOuI+TmHjiPs2m_nZ=k%*1o2ZA4bcvif0xum_8-id!8>vBq4v@XMSqsJ} zv!KEc%5eRq)Kecb_;sP$;e~QSD&^$S$Yr)fOC4sK@)e z>$dQ=@do4CZ5EHT3)G|H9OkID`=Yh&*7xTLF)!5jGW*Lr5H0%3@e}Ze2dXqSiRr*( zV=*SJWJQ-n^yFcjR~^S?>VJzqcf7_z2up(1DxD}*9keEv{%GKg!Ot~(%_p%@|2$%n z9wV@3@DE$bzR&EnRPxQ2DWHgxQPJXC`%1lm&Ytez#Q_x{VU1Y}D;!WdMY}Z)b4;k1 zaY$aYDffg;88rv%U(AXevwHQ2+%m=h8+Yx3qkGpLjXk3#36uZiX!283Cq*SFz-Q zyduu6MBzc2GeK86WMQmM!^NKKDZWjmoXv6w$ZAl%145L@%AU`qh^LQ}D!X7WX6}h| zo+Ph#s`p_E4UBV*N4SuGBlEckW?6)_`N5C)3N$fCv<$eXHm3~mB<|_;^b1M5IdyED&j5?o-nxUpU>nH%u)z>fM?}=mO^yi z9ro9lvjP6vh*Q2Ug8Z?}$3wQNu!oE_xJPGjW52?LtWvzNaq0=+TvNolZouqg5r#S@ z_pw}Cu8Qi2e1C&i$>|4ig$vC9S(WFGQR~nd(B~(kq=yqLoOz88fRjvc91U%Ul3anD zEcS{*ET5I4zlP2GZKXSJR(apup$A}DP0AqNiW27YpvweUQpB<#q&WO`=zg$Da3bo?%MjGa8ihNx)vr3mU#`P}n?e;@7S&c1jV zD|Ce?o_`Q(FXnZWL=R43VV|z<T*H~+n z937X1xO{4+%4fsQo6eHLDMnJ*!A*ya1)hi*SRE{PzxV9p1x3qNuKcw!}L?zxW)KIFs!Vdv%a4(PNri#xUJyfIxiSx~J zjDOQhxUfUXyJfS%UqKh;!DAN(h&vOKjC@N8x_?t&Z(r!wt=Q3dP2&a?blUKFtc*s^ z8B$(g6`#}G7_f}h@Ul=r49`=D{us9aA+t&PJ?45MoG^kl+hyE~mC-(DETbnkJW~FD zVIxGkV+rX`jodEnV~%gE%U2kLJU#F6pcC%p50|Sr!IQK>s{g7Se%vIG|C0&|ZM`rG AnE(I) diff --git a/CPLD/MAXII/db/RAM2GS.cmp.cdb b/CPLD/MAXII/db/RAM2GS.cmp.cdb index 0503533f7ed2f96cba0be4252f337c7c13cb89bb..1da848387e0d0295320dc8303a2270996f603b1c 100644 GIT binary patch literal 43889 zcmeFZ_g7QR_XcW1K~zK(L`tLx(xvxAq)8J2Y0{)f5drB02zeC+q(uaz6Q%dwTcmeF z?+|+EEg>Nx<@&kzm-|P2*I8@!tnQPk`CoeJlIy=m>Yp@u z@8#{{;r>`$UQ}H4+2a?!E*~8p%g8=^{7ha9Pfr@~+J!Q>&q$}YPV#)WIRReFb=Mm;tW?$pc z(X=nAyPU4UR34*$>|945z>cZ&%$#5_!#q4#e+fy~yl9B6^W-=Kr;(I)(|XzS!6UxG zU-a2tStrfFzGy-)vl>^^^MuFB=s~;dvs1v`=2+PU(R_bNDUI4cKy(}&_91P33oYp) z%e1&6UZQ7e#nwW%{)p2v8bfN*3F9kuW;^%%nEjw(xGBXF-QYPQKC%#?X2q`BBX?a1 z)B|3LR@gfC zOlsOA`K`pLW`CdX%>XSw zYzZ?sa5RKtwm--+EvtydT1k1I>we0%>btMG;<@bmacyHpMHcjeAHnI%8QdO)Ng03G zojr*h;&;P+z-Y0Rl)ABeT*O%gSRJp(76Fe>*DGWUSbAHQ3NQw4r$kaq%wYksPUdfx z6?^kBCHL=99Y-oDZD##^)p0&r6;Jg^528FzQ-hcP&aXgrg%~9uC+UJ-8f@+G9tg-^ zA`yr~C$7gJ&-I?$h<%z6OOOfwFb>X`s9;E??Y*pf!Qg<+f*fa4#2*KKC;ngsZ)xPl zTAf}S;O>Rtw(;%J&?My-oV!%6PEF3;FPvweizi-zuiOCtVazQAoRY12$^~qWkvq1i zr*2qE2yJVH&1fjKRYg~Gw~!uEX!Bb?!Qk{WwJ;jW)`}51QvqS=2+kmF6f&kqL1xo+ z0OELmf9q2RJb&QJ zCBe=6@Ii0LEz-(N9#ZZ^xrCgZW!NhUzM2~Ya?A3mMV__(+M#b%0@)$bt*bLFm$68c z%yzrb`DZFGBunXce7FQDf9Db4I*{ZYs0aBQZXHX7v9|JsaI$^)6|nj2yw&OYK__K2 z>+uD8Cw>rE z?gUPvF)#z%HBbPT(Fz({VVe*UUT^~*95-Xca<-jT4sY6EVAbfJxcW*lAK><{d4wM1 zH|S&A1ENaQ>3=}O@^aLKPwQ*=iaxn!cl{BWBHtWlO9MptS=!gF>EDanvp1B>HqTlVCB_%Q;#rdT~ApGJrelE3f-o+9Pb&jko!0-f)h} zVmloztAVtED`=T4N~gIpsgK3L%ko|J`M=J;(TPxj;ri~`%aKMw+VM7~7o*|0`bS8~ z4C*xx2loLs+!)5X@G+`%C@F$JQz6Q$m>By3a2g)Fg2qhcwPlk+Nw)Mp|1DRLt3(4C zku`wcOfC=>n9?nKie85v51#a+JY$q2rW!(?qoZXBzSYn;cs3^yOa9-B4OoK)+?K4k z!Sq&e44S1(+*n_DN=mB)0Hen@7(iPLR%ge}iRUValvvsNR0i(pQGxxG1w|x&8}AIs z%5>cVDCE4jNVlE{`D0UqPNm$N868{?-*bcjImdwWyES4UbOIlAyOJ|XMvu_EO#?g| zGCg(eX(lNgQT2kj^_Oi{0QRA;E(p@w2B;cMPPoUEDs_rQr$s0P705}IL@i1Ut zARODSfshQgpnror;WQgq-p>H>BJ)_Qa+dYOdrFr=>JpRWter0&yRs>Tj{%7yga}Ojg=TmNf$dhwse~f-BG<-`^FMIG^x3UcPU+=$Odxyh@_W5?_SNG;W(M)2uB4XY_ zMH}5m`JR|2SQ>bB@9(iZnHdJce_2|2`SwqRlAAV~RMP$jsrNsqF1Jarl)VUk`#H%XP}wYP9|bC0L4I5Y_vAtC9KtgRH#H z-XZ?4(f{k-|1+fjn==3B9RB~l_Z(|Yf3VCGh{}@$CdjuQjmpC1i_EVT-~;rp+LWws zkgjRlBvB|mG4cu)#FW;V%K_UO<^JTJ+YpPC;;U!njVA5$yZE3qP5Sy$3jA@_>2Dxd zSwbv92}Gg&5cG3~aUwAzn{Lx??L-SbnJbyBzgZl+~|8`K1S!bn@Y? z>)6k${z0gSwi7@?>fJn{JDjJpM@7^vE}2H0`J;ADm!jC%c!oy4Z0`-Sd#htxGFpZZ zYanwX_gUBCj?%$FvrkC(-HdW=G~kRlrT_zpb`{J`g4_05Jim@mJ=NGryZ=;k!VW~! z_8;2C4_5Vi_Z+hAzAPL%Kr+~6j{03YTc#{>ZQb<@&RLu9Nfr~&YGqOo#d+V^VD9O- zP#yspwXQ}k+|zQXlbVq`fgP;#Nr>EAvlovZu)mR`;aSlm0MmXc?jOM{>#kIUPuy86 z>PUhn~m34 zrw8&_fSr$w>u7gcRONQu3*m>Fwc_6!E|kwDfV!TyD0QW4e80u1GZP-b^CFA%gRv0 z@@fUW!Yf75;-ZKMy+g*)RL&=YnVR2jrl_^Y@At`{di+pEy}u%eGU$k{M`j=C`XC-d z@PR{Kco>9C z|9wa6my(4o0Ejm#Je^(kgPE6g1bSYRDXFoDW8Uhnbx#T0y0h!a-t)Q1U6lEz?Sf)= z_jY(<@p3Hbk1D%|agtzlyL5pJtbX7LH?sm;^|s^i?Q%2qDUq8pwOqGnI<@Oj6v6Ip z&}0@*zE4m?urar}xm1#(+(w1vmo0F;C?c^Y09q_s4~yDt=o>kEs5ZSanb3UDWWk~% z7#f%9-QXLQ!px@*3|yuYHRiP$)McD*^0oRXeoyjSP=dD@cSGn_AZXfZBuRxnkaa`<~eh3C52A#Ek0C))ZbHtDh{5yij56qT_apVfykm zCR#KjZd|TA)&|S@;k5C#shLTT;7;>QP}#@-dJJB<&~+?su`JbFd8bheo=CZ+hNw9L zb*#P;En}I5a>g2RA)>vD?@hTYi{ViXx0cg`l06lwYP|oX7@R!U7W!^qr9bKz_VwV^ zg%X2>)QsY}*tfLZA?7aYmjj-Q<06~u_r5bUi6n<}^yfsMjhr$nCc*Hy71`|L-!In6 zm10tuHNQT18(n-kVCij((h0Oyr(N5j6+UrT0W>@OF7a&U%#(|kE~tlbsBTU?%cUa5&IYTF=PvP1Rb3HB><JtRy4J;3~${#EBwwC|E-4c!wmb?1(E<;y7X98O5RK1(*B zF|nj}iL4Fdx%WLAG)Y(IGN>KC(b%~xA{aFh`6XxlmwVJg6Qw!hu3_1a1T|(wJM4{f z<#PKNwrS$}+rw*tW>rYF7t*Xh#fE;Nlcd=rqmk%tF?(yY?Eu(eH)l6aC-KNG z$^g%J$Zik`{a$tJG)UVj&PzkmW{hxc;A5=WQ_;InWxwBltY#5fW zyK{M|nLn}N!C22!9|+tdcKH*Ae&}*Y+N@xC15fCyb(j3=_x;~xji32+#J4~sdG?c( zofUf5quQF5C2wLMA`7T99IW5+y$YaxkgSPia{{AR9|F0juQ_lpy7roHf^rc*plhgU z;3eaXrxa-wbr9D(gjf6UP|}9m10M7>vX~RB&sljV=)LBKo3~I8^=vW|2KENLh27%ahbvbdDogeKQAhZ|x!-R9vLw$Xv*A0N({}Dh2G-$Zi4= z1K$Q}fO=#XOl0iGd#BwQ(Kpx*P6T8ECL=s`om)Zrz;nRicUvI&#b^-Kl*q?FBROk; zWCkgAb(Sb@JVQAS!Fv&m*WW^A{Dy?Dx8l2Zf5VUw`e^=A!=fEBBBxhIcIztiH@E_y5&L#vK8qK$4b$MV%jZDM1m45+m_7kiCJ9A z!@RGj1G-MH=hwd{*SGcaj!5?aFv{bbvKP3W-bw(Sx@g-As4-f-(9lPMo!m}Z z9RZ$1PIfN4$qR73xrGP+TDe1OYpE=?QL#ekDzz!5br9WJ)rtSk>qk=b@(}$DNltYO&Cpb5tvM4-chZfF#1mFX( zd+XoA6qYu(rD_Nc8^HP5eh6eXI%5RRU=PJ7h+h{CADSDf%)&@E4iNhw(~R z(ZIQf)&BWV6}S11#5CH%ads~5tJJ@D(*Qq);nHElsEiV_qW$b5?q(Bl%yEvr@ib&| zTEAmUFN3dk?GO38@Ev5|tGMPYxKhG!&iuz;<$I?@<1Fa&|8ArM$xre9Z}D?*A8dB~ zp=5}?+Rmx@zO&RBJ=~3LO)}Fw`(A!Jg|)#h+r$JG9Or(2TRFCG zCB$(*utV1*-AEL0D3Hou4Q!`v7SPhJOm-=Bzn;Ql7*lMn@#}_sEM@$C9 z4Y6LeIGnmQ#u37X%Xsz|L)h(($2+K$j3|8kyz;VrA|gnMKK1^~yW;Kt7DAwYZmj?T z&B-?EBomWS5Mzm~PEM#Z=JJjNuvH4?98o{5orLiCgxiw~%aGLxLj37G;qN*3P-0IS z4|gvR&$5mf7DN=E1d(#k1GdfYf6)Un+o%ugZ`ft(e?EQ|S$G&CHe(0C?^^OmD=}HRFx#7 zozz^VDV|D^J?n%VZ_SrC-S%4ATLpGJlYCZbwe%Zutk!KwZ8gOdix&MF7cY%eQdb1f z$i)kgFE~Z|TwK;No5-&jlVp=|mJ;0dU~keN4Bt83$0#T@n?b%8*?1#kr@5t62OV8z zu9P&*%;_s_vKLxyC~wlWo$ijWedBnm+rS+D;qBKP0;79^DCo7Uc9i!aeNFO6O~g{3 zQ5*kgZZ~vy)b6wENwK|)xNfLt&H12iRD+Fn^IjXWv9s3Mv6LXXIdbtgwgKtJj-FgD zN*IFu4lQNr$^pQfRr0o_V}Y)%uQm`*=B^MaO)2`R^9p&y<8i zFw@bcs*oYib7y}HCt-Rc>NV_f=GP3C%*boFY@niR&+XtO7pni@UtO7}LtUIpb+bu* zE(^ll!`s2kiwm(!DJzNJDRv$SS&}@TX5CIq=XWnH)^vZEyBtJPD;AL=4HZOJed8qR z8s5zin*8(S{BrxrEN=ej5f4zVhySgbl_k2@-2!5(*6-3tJQCDrp04IzY zjkh6&;aHv0QBQl&o?&SCQv+AiY(z8UWPVca@J`9t1Ap*L6vMpmFEwXEuW0W3$m+u3 zgM_vG_^qMHr{V9vk$-k9jm_W+f&Mki)l1pZALBGtLfoZ_J*w5c8NLSwg^By^#L!D@ zuzL*NjJgJdiA~fp+4oB!h)Q(lXZg76jsJFR4 zZA)`UT%9Y{WV`zLQk3h*z(sJSPNfNL4VBkMaHp+pJDWcx_T`Gwvc$F4hX>9GQ^ojV zpWx8mCyK{WU2vKEpB|Hq+peOdCt~sgM#UVL6b{@nJc`T3PURIVD_&uqZNJ(M6&^*Q zv1tb<{jbzDT1xHC3wSnoMSAPTGn9pc$dwj2H1FnhaGd;c0x;=X5_hY2rc0$A)_o+- zt3Id2dT;3pE|-f!W@e$9V# zoT10KZ~RsLor5jAwhE6e-TOon=l*~Gf`diI8O)+nJ!@>&-*Dp~gIIyU@pHCLDDY?b zZlh_5>k>!UjZ1&>0$a48J?0+%uxq-%-_#K?c8Jw6hEJxyRJpm={0)aAl6k71Q|TdZ zxNle!UM7b2*-wHL20w#i+ry4$t=XnxrMWd|?GxRF%5@Il+iym{@Yldz1`Xr@UlK}1 zyJcTS1)y2Z0{$avp83lz1f#x6m;X`QiETL2$y9wbAoQer;9-Ps>&x1IrvgZv8+ZI? zgpN#DzJ5967sBNJe_MbG%|v$rfUX{oUFBecCi{bZ7sj}9KXK9R77=bJJWOynqNRvk zb?V;^u{}j7)w6%%?xfJ~_wZnmPU8fbg?jVfWltpIl4E8)ybczo-SABsOp)mmk*{;i z5|++*w3)$(?kkgst_9saC0Nidp)2H?`$*~65_C6DW`FVYx7WAzd=yM}4q0>zgG7Mw zB8_HGZ+A?$qc1M%uJin6FW2tz)TzJEtOK3zr+M{{n~QGUWK-mZqnj2vMVSq78Q$%A z?FZAoVE?KImCq{~e^gtBlhPHmU;dc!#b4gDXXf!w9hB7lTccVvh-82q_rxRyCUOLd zo-zLL4xCq+`m7;lsJ-nrc&g{1e!Oj50}f{^c4a2LM3RRCg=?)Pl$vB-(9PE8GF_Ld z^3lwXlSRzGeTR^W&Wzv-24==&4}&jx1>1)ITE#O2v~I?aihR(FJfdBC`%(X)2kUnK ze;$A&ls49F82}MR-!;+ch(6z)?mqQ(aC0Q^gj(tWzxS^ZzrYj?&jS$3&ehKNEIVh%T*=1oAl_rs#q5&TUbW_Oh<9W79&B>S(ex0?1a~&ptZ+2VotHwn)Ry6etI& zmm?TH#(T78;Bb-G$&7&~iU@iIk3qHagFYz-32ad943j4#YRcGqt7iJ_qJdRT zSu*6gm%7Je=yNJQSY$MMHmDWi@M6DS{d_^q{zdO^sBkqvYRoFUEf|&deocm;`F^cF z@FFkRn-{=%?p4naROF;&k{sV1(se|%Cep0do!G=OzDdPd?7IHZZzSLOPBB;&z3WD5 z>Ouz#Dc?Y7pM}$e%VImA3*8BOj-+E?MD7==2{ULc+b`mJ}GG$Nf$5f zd!kYc7(*kqRyuy=EH+Bi?dg~%v`-YG&h|QX&tcV5$A8)K=gZ(WrXr0;8?^5ABb%=G z=srHz!W-u(1_@eLAAJ?Ev9YLZR~8#~-F?x~QkGeHYJ4SVa0@(d0*)(wDxYgx;Vx>& zEh_GlzGv%+p1{6d1-eqmM1{P_`rG%*o zdt{^^mh;$!`t#%U>HQ3c?;ua1pREg3R32qTTHoLP6H?qw0sxt1F18lbW-;+Wf-^X% z<(*_hzzF^P2DPFCcw`Fq5$S91eQwzJRH^5A%O~KVt($c~B-6(pZhfaegFK5m0k-OO zL_jb7j}iOEUp&f@Z4*26wY`EoSVaL!{1>g;o^?+x|3oMVu$S>@b8Z@#4cB|^q0u#2 zm!kBqY!~mIRPNoC_M=|aF|6nt@X14`KcVxyvH!C(m1o$ceoYBZC;rndiMiJ@YF3pX z4^91&kymj^|83XHb4!%Vml?)dCy(%lusB@d@=Pje%)45c%!5z)&$z@;_48UouA+Sl z54eB%l>kUP%1z?-qvt`nFf`L#z%VDPud9^kS7z#zJ>koW*{{Hx)0!h?{PwZ5pNaZS zI}byhs|{-^$G`TzjaFGXG+F#>kq;r-Oxvm--q?@3vAkxY2HG|f6{vkTIJI`djJJ~} zzV5sc%ib$sEG$zw%ooR)e0D6F9rg3l&~}^{n{79S1B_3wIJsPJH!ZH-N)%y1I#9Gu zM*vO#!3)KFy)GA3(X9@=tG%jizHl7uam5;_a zy43R{gFw=Mfc^3efw%9hd-pr>G~SZ2=o^|){KJoaCgF`+8ux{(MO!V78E(|1p%0qA z*o}-Irq)qzxaf`DvH7mU2(pQ)>J8$X#GkMM6Ljas5p0PQFL&lBMvz-7lH> ztWO7mzc8uUS7sfB7*1G++b-~K$+9oKb$Ny9O=C0x{QA}%u$6359xBWC^?I_= z&486nUk2GEM`+Uns~6>RetUKyh1|-*cQv1Gpj9ewPY-u%Y##%q&Rdrx`0EbEd)9#n zPSEvMm4nww+~woE+VT)%_@LG>Piml4IR-}n%d!wXY9Bq6k*$=i`sh_v;>t%#@02F* zU2@d6*{MMM*e_XVbdZW}+_oV$(FJU%kK|gWmRCU4KATuW_3GiDp4$)J7-oN zlF%F)ha-{kT9jpV7Y&9yMactQMr z7~OR9Hk$#pu5oYcE&!3~&_eu5#KoNkW zu}nod)@t(V^6)n$qv5Y%F${=wUc!&~91i`b8uB9aao?@CF7<>jeu)Fw2Rm=o7f=Hu z3Tig}i`)Z3++zVuk7^51u0?ksVqxlWlUn4%>ZuQ(-)hPqr79s~#&Y|S=Vdep^HLe> z*k&nm@Jx+4VpbYlKT|DaU-_Hy`NVoHaJWyWT}G2#jGBTe_6DqFT55ya@P5i zaED)9+LRG8FJg|m$eN~^nA;v#9uJ0oAYH4!$CC7(5OI3DY!iAKh;xC_-k|?4Dz8r* ziDnz-XrZg^{g778(UlyOKH89;*=l;h(!etJph;Mg-Q&=$zxD-N1B(nbWS#mU9~Ru~ znR^ovv(o4~-Z5d-Mz3Ics$b(JcHku@m3@if4+RD;}`L<1g51B^#+to>&%V=;^;hs}I2LBhkW5Np}~R*V~2V!=NS1^JINn zl>vFT%iNo&KxGJ|p2*>$mP0AvRg3j7aPU%|W$}O|i2WCEBsA{-=_G3TdcCG4Ou=tq ztyD_~^2BO12#(xBzC=}jk<1Ft5TlB2D=n8O{P7NCFgRwCdb6tJII1>C2ivy6+~wx} z1y<99U@`!!dEg>~V>A=@^}Y6L zWbIW>*S-6$v(!ya*B|EbF`gFc^s`qF;f_7;mvqVcj;x-ILiI*E;y!;UP8pP%5pP0v zFEqP;XCMGHDt>jgeB?6uqE(q_^|QnR0*B`VwneBDlEG8!^~J2x_4#6@_nyS_W^4;( zkMJ#i_{u9nDc{8dG7e956Pd;n#Z2QxMhh`h+6LuU+tbUkhI#n&`GmrVvyPsP;c>N z&?$LGeeNNu=1FnbF-@x+j`w)t5z-97*~7H|!%29Tp;#PcZ)U$`S^DRVdvYmCycU-g0k&gmTsj#V2ycWT2!*v;WIPxV2e7 z`7lMc8e!2EicJ_C;V*g9eZ?;#;AMe*urJISkz%LU--raiVy1U;=o1*Lj}UJ@E#VM` z_2F|0jn&M`Cy z2ECGeFzxgy%Io=??*r$zXKZL?10SSF3X?gH5^G$mu^vXNxuw=UI=O{A(lI;_51%yV z`{eT~T$gwag==ai@gI5XcjUxCXNHsm4|JBst%5#LK56W6vMURsLKSzdxfax5->J?Q zv&(jyg-<69*JhRU6X%lX2pp_mjr<+~bSnV?see$u9dLxV}A!kz|NM z2}W%(M`7f+jYCF!tu+XxRS)0H16ADQl2${a;@a&#Jxp4e_S>J{RPN`A8!vw8;q@VV z{;RJyA@XZcVTj=R&iH$2HrEAitI)Wr!1v;IErpu#A29Rk*dPu!OW~$dN{u!7JA1<$ zc>hJTld{6^`Gjj`3GM=ao#WT&4UH~5La_7cFVcHYwi-!(RRv*XZ#Wmy(ijTAw69J# znuSFgi-!E}e7A3N3+Vwc2=1j@3|wL8r&25&q6)p$sa z$PDT_$wHRC5(>6wKD8}PT?MPa|86R1oWKadKg>LeZMFm|%%R<;3r?+_lCm};i|cE* z$+@X8E2DaX0bPf$gW*UTMnup0D`rlV?uc{oo%2o*OsTK!?@_<^eG1R3{lQVw3YmFQ z5wbt!=(lo%xc`ejr;A|zcaugV4SYwEp?Mj9yXV?y&TF966CQQ&J$-?m3x*YFKia-8 z#@L106KgzTX!8vMON+p1Dl-(AkAKE7G?Cme@(x7xd}O2g@6t@}dEh>Aj_8n>_uXJ3 zTAguQ_+XD|%gE;E{72tGwj{^pecpuvXY`eytOBsS(77^*GnOvj$?(!r=FVOs55tn7 zl29%AQT{v2FP43GXR`los)Pr!O--6MOgPk)cbgk$&(|`q%PXnY z*HpQk%Q4#!NZp>swL?>jU3vaM!~*6oO$PdahXKO!QgB#_>5MuVm+uEYB0plF!@U$m zIn|sWFxy|wK@6JOPbhe-Q(ql%=uun~eVqXwMvhj^&#~*W7R4=in~~|-^YD&xK%ZI- zjLI~Y3ni5$__>|7hTVLypE9H05UgWG`5~5Bk1D%<4Bu;RT6B7gPO(d@Vy`KH*1qz2 z*nsQ`&?4(M>GflJCmp}RgxE4dD0^$?)CZ&McoLHW<-ZFCGO}3NH=bCb+5SOcnS-XK zF|{X?{$G&oy3uh&%){`tgJFl>Msr;3`FG{fJgELfn>uMA0cWHQU+py0LqNMe5K+F- zqLo6e9punOLK*2%Jt|P}O@xh4wAb4s$qot>P5$>)jZ{?-4)|1$Y!XC`IPZok)$68= zV}@=RL$zYo@DD*E=O1NY)FV78o*EX4V{0V~;6W$gXHm%bN8vx9?#yt#3qxoQ z4^Y2}WV3SlJEX4XU7_E;{{%%G*e10JJ8#-PEoXEep?=+#)QLvpmP1;b@Z6t{67cX% z&ho#%6seej+icPz|50go@H#sYY09)vpA1TUqw*?TCb2n z8%XGbG@R3pn2!^tKOiQ5*Kj8;@r2*lltx!p*#4!P7>- zN=I}Yf?TI&?ut-{Po{-|vpjheNE!8?iJyL>AjTL0LCQc*pU>SKPkvI2?~)_C@39zeaN5c2tL7_}KXa%{73pX3w7F@haB+RIKfJ9&l@Wi$lOb@L;ccVpk$XCl5UZ&Sx~iBwHNc}YbfGOWgguoO&}ByW_U8Uj1@S6ss{e3jF8jes7U zg7rSx<=;gexe)4pgY0sqybB%L zk>u1ZX5eZ5+Zt6yU}DsN`R1j69{NZ>%fmo@^e2FJnY6QF3@<>q(!Qa+Z!2M12K37iR%+c#aNIvS z>~Au0cbi%~q}CDz+Ky+76-o|I#F%z zY3XmQ)vGT7A2fh(0Y1>I!t1gS(`=aof1)m*-H$+RB^2&R)u)}g0n~1_mYV6A+BHGv z^5_@euiwx)e~DBq*mTmRmRvA#RQ2`cdB#wLqj2S;3YO)F%V(%FS7F9f3E4c3pTdK} zV>S2BP+LF`?Z6($FOZ_brZU5?jFNxBFc~aD*~qipLB(@-{opEew1U_7 zer#XO@Md_35y)A2ZbvqVat}>Sh^7jl%N<+0m%X78^kVtdnQTWYfw4319j+B>s1`|+ z3Ljsl(HCddTpeaITeG_395qKbH9Q=M2G?sZD*h(BR*#ho$D|6H=Dy$&-P`0VAtEAO@{OCmdif?$4$;D{cu5D+$iMuQFjyJYS>XOdPhZe(9&geH*nwRvf++tw(IzudL9vqIvH9 zq?0QBWoF>xlj=oNk(Ki48x+K$_w$jA#1S8U10ES=C-^r9qK)C0kgCai2}WbstU*xj z41Q4goZ?_A6YxBg=;YW6gh_{_$O$at!9gZhCSJUbePpw{o<&t?+X@qbE8W$?k3U8u$k?NXve_1M`nw#7tslK~$rp1f1(;#prz- zuQo9Y?})^T5>pRcK)_=oPk&|x5_(e+iid3LnG?43FCJKsIsY07A)^bHb z;??TEe#d?Z{t;`lvo@6uqAsy5251}Q?@+N{<&^AS^}w81`s1c&+TVzIU65+ft@M8_ znRi$9d3{>fT@#aysBfKK-g%)h;2CpVh}H^2VcFlrNKKBO;;>57|6-iP8a6Ln;oO(JhcGqt!%}N|< zKM&0i*oE@2!D0ie6Vc#_-Kuf^$!N61dJ2ga{Y@}q(amB>w)oN8~9^m`tJI{UU~iU38~%6qZ(v#fsKHo z5!J5V0|Rw)$KU{X8Pd_XFDIbJ=I{U=7%a7LbczEE&SPwdS$FNV+89ryXKqhR3pJo- zG^|djxre{Yh-T`*r|li4eGgBMFgPqMDusNfi6rKGVdY%Y8@}!TMJ!R20#(WauGI?w z5UGE5CL{^x-8u;sMNbKH z1fnEgP~iZBe`MBu9vv}=f9D8SoqLlu_Hg`&=f$wXzDp(8vTNMy!v=l^^?|znw7>IA7Wj1`}P^FQJ@!5X2!C$E0D|@7}?8Fpji!$ zezd~q(V?_veSPctj^5KNBgANyNB3hf*ltC>&g{R-D=sxVxgsOf>P4NQD|NJhc?GOr zAh~0o0wwi?6Tzo^Sj7B+w+b43e^p(h(c`if4LL2F-T26l&{VaNbpG^e3?F13@%?6E z9)u@yZRzhYG1;@1taT3fd1z~|VYh9w(>LzA1oSwzj-=YDe^wg8I#Xrv04m$FB)CC9 z8@q2$^<664C-_}wo$m&RteM|ZDGP-aHoRdc(1#}|bNJXO(2+}jki^ntfS9OWv_{K| zn2FlV9`R>5CP67dn#}T0_}md&x&S%c=C7uFLD29l+EWxolTm+yy7p7MtH!F|52!;X zMpGQ2CQfjo0Tx*wNc}huV^@i``I&xyko#G77*bao|F&nFl83*SwGpYdaFF5<+QNV& zx4AoX*AALq9K#yNid}Bwkn;J(^fCl8-cbm$hs2AqM77H-k zf|b}caRvXPi|Fq^3TvaNelMAM+wD(8pPP1SCt0CzKU#XRng+m31Q zkQ&Stda6aYHVghtvt4;)-qiYW2?J9y`Ch9RqEDN3@r3-ys<(+@*2_tWODEG;2$Xp9 zK~cqNR#;-aj~O^4=)^-(sJZ>|jN+QXrw?Bfq07~}69e8gupkp3JL^c6^&Qr2u{U|& zP(>fDL!Amc7tqq08;7K%^9U`CMIQ4PJrP-DR6Ebt2bEeaDc2~o;Z+7LJduXBjcP%{8-EYy2>U9a`}R|oHRvk4OVZm$Ac85)$mHt(IJ?_sCAfXZrbW@S_1 zV+z7bMU;8(&40tagI94HW%q2zSG_=-oOeKHItgFO4HjQh>F_ozdODmia3t zqD8P8(;W7f!*(xIh81=l#4NKDPUiF?^h>0ix4L;f#Zt%C0T)&$Z8xb=sr|31A`*{g zhJ~ZW3aGa^1o{w*7ZNi!f_u(MCD2VAI)k&uX6qnMjHG`NpxRB*ZTprI>>7;PK{X(o z*YF=SLuRvUZc>rHR32*XM_i*RIGR`wJN6hdOC|H1s?J=r*9DT6*GW4d{&W_iexLa< z_2(_W5#K+QNFwVQnA%TnUR>Z|p;@d>fd+UhihIwwMUr!>a$bYR`A?0yoRUKHKM`gM z^bS$-Z!4dpxgHji*m1*$Ca*Q81}zbeq%d;kj)Lrt*nNm&D-sLrWI|k2O--0=0;Yd^ z;7*=8ZYTj%R+D&{6f#HUH2y$B@a~1XaYutK%4ly0?j|K9<7$wLBf^sUgDU%vaIl`~ zC^$~y1F7dg5B*^GLH3qjLNBC}{%39sRH+-ai6DzYt0}45e^6N^P~rY_eMRblJJVWz z475cnONZ*QJxa~OP_1{67io3I6OX61O;Y)OG}jc(nTGOIZi#>4DYA-t=hfd()jFf% ztgQKB@bQfgmbcneEOFB-Js#dMiWMrr64@JntQP%e8Xn?H*Q#o-%N{m+DB`W8MSCD= z4aWz$Brz4Xqzgm9L zhE&o3SBpEe>5q@Jz+53a_P&2Tu*|g7xAYt)&GA6@H|KA8oP$@BK*r+WGWxdPG$E|P zTxqam@C-!FwU|CK^ln(Ff!w5I+jJqqfG7QZ^13!If77aZvp4Z}EgNnoFfFfVvS{|N zx0yYz=h33iqL`d_U(v(hB-o7yi`zUC%&R;}AvB`qe)N*O8|L-a$hDkwuAL(tk30OP$H(dk1xvP9J4`8W1=JrL1dFhl#dZ_mc$og}TamU-h?CcLzr2 z^}7B{HeS`)Dh;G}2W-kI;7HRGgvlVAGJ$O|8bptI8D6%;F zUGf&~thCbb$1Y!TV)Z}XTWMysbNKWX&1(fEts}nXlM!EasyIEua)ouw2kgxT^n?87 z6Nvzc?fzE!CVk6^r4j|?Oc9*`#JI9)pc>WD)$5?}n21gQ?B9G8mB{KBfZ5^A-D$A# zM~cmmTwhr|8&xcuBALy7Tf#IMyPd{r(AWAE+^l9DE|tc&?qV(=h08vRMfs^RlY!xT z+~s5C2R93McG}}EXbf=u^EVM}`&yec=WlIVMP6yfJA|*W@%D4$U#r~_M>HWBwR^if zTL)Vn+p>LA?y%&Ej7krDJu4*Vn%qj3m0Q>UtrYaT4U1HaitJwFOkm)LCX>=O=x-;;j^H2;H33d` z`#*&BTNjCwZ`<=r3nir?%-$di^O#c+KC}^-H+L_Q$`s&lV z9M`#>2QVe4CW>d*)rx(tw_GlB>QyLno9t+i;Ch2@0$%=+etWlEhj(8ZFP#b6>aq%b z+9%^g?cN4&ci*(GxHB@Hr&7K>w$Lr>)3`k6kk=N_bMa}cE0e7A8=1lePZLii;|b43 zIrqCX!L`p=@9ezSYULvoJu}5Qz3ib(-rYN~zTElcibvC%dJ|olrzjXyV{8yMv`DE(?Zvm=bX6Scx_904wM zsYM6WyW>78Of8T~CvF6~nfxEF%&{^SfebQ-q4Q z#K8va^|ao4sQI3_{NB3n>x=~1UJ!SK)?HL$?7|0j|0p(Ph(RdNQCwycLF{zhSl+)_ z&iY<&_6L@6`}mdjy^-tOV}(8~yf>pulvYy)gJ0Y?nUYJ5?fnXnzfm?uf3EDvqPcbU zK=bJ{ehY!vi};})$3||4q*vg~eKR&vG@OPY=ncUe;eMr+KzjlBB-Tmp8u-hWlb60;l zXo{d8QtoWBFEcr{eHr)dHvXjaBde=sxggoHl&Ctcz}o3eu{7^2(~FH@cm8;?Z=gq1swA5 zzf`Q)YL1x|v&5>HJx>bvcm>p%$-fevYH*WytKjjUHB5`+*$Ukn+=~3n%InrQnssXc z12W2MD};0Vs1bL!kJ_REYBs|`r+S2&r-<;awTLoL?N&tb-qtFj4rc3d5mPbi*|$N^ zWIP+*UXM(P{q3{i%set}DYNb^Gc3O}ry&u2il)(8+iw8FGGO^s-pdjr|2ubnhW#bmywCG*i5x?QZ+UizHc ztixoRBREfiRmI>N)82ap&1K$bC|+rEu>EozWGY>h^cvp0nygx5*4O2r)L*9?zE?G5 z@SnUP&K=?P;f-^zsD!?*gnA%+5T5G&#dc$7wVBY z%rAR9mbRq1lj*`py|pHr#S-^NHrC)~T%J7Ots!etgKD zIDeWqe7RK~xuQx-FIa58VxvyMMsO(XlFW1cX^XJ)7Rh|6Hg7jw7HZx;X=YGMiowr| zBQs%(CEy2SjXFnb2FI#I*4ivJxkGRyRaN%4m7BdiBVvi?F&Dc1ZO&#gtb2dAUkG9~y1J9QE5;($zg ztObA7kiHLk)yIj6x?hIrvQoNmw|j1S8pL#A_v5;##1lK=m$UNA;ubrfm7Vvt$h=uH zuWIQ>yfe|2_CuFnkbFE{2D7x0u8EaEgZJXQFloC`_L+loKTCf);%*57BqR@z16G1M}is(XaayJIs|NN9CzQDXPta`?Us`|MVxt!zsrlAjg%%^K;>q&?f|q$4wM zvXHH|!L-o7R~m&R7n5DA=S~ZMS&K%eq|r=AhkdY9*+XLL*=WvxKdVblPiN9;8n@EtkLNF#pECYen~;tjj3Zs>Se zaC#7La{j*C36kk z?>IvrzPnN*^d=XDovnr4Uj~aAVV#QkWXg=6XoM%YJ20(Adm0h4Tbk|>k;-4lyh@k5 z`_?lZ7Aq#XPg)i8%NbE-XSI@qH;aVK_BKD8XUb^hOwNiGIEPbF4L2q{a z_6p%lT6aRlMg;C49OANHOy+gMKiG$HVluB6e2=a!rHlgHWZrcXGH(?tlNo(?%St=? z5M<{642NIf6a@*nm$XyCyey5srVDe7`twfK3wYjXc|VSzVv%rCz3HlEAXPCP=ZWUZ z8ouesE>nfeS>=~&Vuf5*=8I!pa?2H9!0|{LslYY;*VEG#A(b^I2lh{@wGUB!TDr3j z&;MzM&LurddD(Tb=Zj66t)hIdDDUWVG~KsP+Z}n@-kbIu48BirU{$GfT(7m2NeJ#y z%_~Aj-Xj+Juhnxn^z>6^%s!#zl4PNpv-5F2kuk|PYNWm<$qz`1rLtSlSt|TVapdWm ziwWN(+$ISZ3%*_W*OT`RzFu_t%+g6EIrt_y73U=R0$uJ^w!EHE#tRbQ2HMz2Zt=50 z@Ci|%*t0$rN4&`l){4Q`2|plqte$FsP9@2-B;o(k6EgT&ZYgB#^tf^Tkt?-iWY zqEUwX4ne{@M^c}+_~9KAREMm~*7yuBD4?*CTLsR4NvU%ky56>E|CH}xU3L)yAzZ%o{wve*dgjA9pOg?!Wi{%!Ep;&oDr8u#~##)>Q& z`QJ=Y=BlS?xp!l-53_w{?qr=1(kA7QbE@yhjPRGbBs?V(lJK^*kYsJjJBD;k@GJd( z0saC>a$LtH{p@5M7l<-8x-9rI5M9SI98TtEI4K; zNuRjGh>lp5XQ*-tNODnteSMo4n_cp0nn4M!Q`yAei-bQVcIH_qo!7XDHL%3_glT;r z%tHZ7`&Y{!y4DBq=S4hH>HMoh(n1V(NK~466;|lc%v&Mv=Cq#2)A3{4I$8^Ff&7M~K znH1-|L%8xA6zxh%r+Oe(Y}EsgeNQroJu_)qOo`51hg+>_aZNdMUJY(qTooKn#_fIL zMI@e=pDQgUMe|}GLc3*x)FpdUk`gKwsm7b!$=PYqTpyrxH0}ol->Pf#GQBmQ!*5Gb zX!`Ta4-sfENSJ)QQFKG1D32z5i#PC>2);VOD*T;-pLcvam?V>;Jzsg)s8Vy4(MQMY z^8I8&HOf%Pf4>-Qrerv5#}2<)(dXKAX_rG zG^)T?i$dN0Mga`&Ch#6?i%Xm5oYVYdzQ(!<>9RekXtdVqX%?(h730XgwtX5Ot77m? zazO>-tQwX0FB9fRaIb21v`r`MxExFzjlx<P0CbCIql0Hp%Q)vCOr8PxJLVp~rn*DbO}J>Cfv`&6eivZtwn zHP^Qx5tYm(C}+~l-Qe3r=VsRC6^{*~7+xl-;&&xHolB(gCSfb)ec<)pXEvqxUG+JM z;hTi>G;^4zxT362^GJj56CIv&O>Rpwrpsc-?@HG8XPd_HpfI=A;>6nQmQlJm@{CUv z$zYxnf1aRNme^ZXUnc8qOp?Wy3A$gp1jLTj?+z|1(;k<>EWRvG7E8h%wd`$ivP0Q> zXASON6MU5j6D#InIG&TGO|uC>$+1<2q#cm6I`S06+(gJ?DOpnRs+bm1u2YNi(t`Py z(J?K^a@frJG+9~;ksFuAt&)n}#VdUXLQD!0@nic=_OKoMPAe;sbY{9A7tOW0QW{ht z8xuJ}Apw2F4@wFur{(1hf}6BJcpJtR9k0l;W^42NPMPMIQo?#^ zVg+8>dDIS=UB`Dd4sMgh_DM{uF^gT1#U}dwgBtTYGoO0iFx|-;@HGj6@ji{KqI@Wk z<-YC?<(#@Ts!?yJ_pkFQ1K3D$K&w%HnRc|lo;P0G1wSje@xokd)D!EJtq$E8DXQng z%}PWs>m7>iQdwM0i*o%raO22x;CrOqb#tv+8Jrb*BGUgd`f!Ji*&f{OqQI5OMXS2J z_#c-6<(}|X9fQk+b_M5JL%(locU7)v-#|^WVtXl$n!&5Rrn3qtt0%ISXjDjLw z>|qox%MSG?yUad3*~R$CNN>gLuvfb)b82yGsbP*{AjSg2x80a&(FqE6tj57Qypo)| z|7K6xu9M`4`??^-dO@(>9*sFill4p&{^tRE7i$!Ymf1{~4Vt;l7o1-;+kC`y*&{gC zJ}9{58G~;Y9U{Cc29Ni~RPag{`0CHgm29t)8AkYblll(%h_!lN4rvB;*_iZBrT%RC zuNM9~!8gdrI}&+AIwi^X>U2u*T^ani;5prV*0E6dEBck}OA`v`ntXO2SHxdv#Rub0XRb;XX zsv;9<&k16FM~cOQuu|SD*35`w|8_#M&Gjslz$^xG5Y-XIw#H3_jZyY4$BU8M!9j9q;Q?SPPZ_)pBa z7MlgXBx<&c40qFF?+`66N{ekGYIIDC4WhG2w5wuT>=S%*4Q^WOb-tAr3#G-uzRVLM zv|c!e`ViUyA?L8uo@=q%scq}~!XoOxfEHOqNeldtYq3Ifuv=A3i*17MuE9+Uo|D9S zbuCWzWk!qT!a3E4&<+UMiTevH6Dy0TB~A^HX);=ibJF63h;B%9%ooHtcB_hMu}<*A zHMnW9*7?@8;12fMG{%ror@)cS=(ao&HklU+$Zs*KVlvMk(wDKu2GO!MCi6L`W6?KP zRs2G5u`o?4EO}Nqj1&ezb|B0#rUl)T?u8k5<{0y98P(`s8OW$r-#jBrPMbkQ*`y+_ zpkuA+YnMe~bzcUgIw~AyVU<+J1tDYD?}mjE&$I|mKIFID`BU)ti?`iY#rR!SzN=uI zRni`+McsPYs+KBTVxp{0p^EeR>l0t+a4+yXVtoIZH+Sb!5K}^&tl9xK3_VnuKCM4;n4wIsyV~D8s)>H zT)+SL8A&AWKh|ZdDD0|H*pbY!xQ{ zvOIw>MtM>()*t4RjJC@}-#V-775&{vlbKaN60TBy-<`-CoY8i7Y9C()-zwZ~GFT-E z&w(rz5^Fw=QFy|H-_2E+YsCm&wpIhrWZS1svIr-r*ne^{UaK_o=S_%JG5AGsoUF+( zN2UlnGj9lMY?KzZ{@1l`Q1cCnR|BVvL)#OzIk@9D2FlFzX&+* zf@97OM=NG==B~VzsIq_D)!op?G?@2q^RH=j5RG0*%5#PO&Qsyp76sa6izAE+oJ4U}UYk!Su>qRg*9s$Epmg|}gZ7IvJ8F2Ql4 zGP^+b{N6=LGFgM0?~u^$2?bwuTb1>KFRJ1DuASh4X~$}0sl%(eL}e4&@?>Czi4=47 ziAb>CYFe|_)6bM{*fSti8%E?)DgLy-k;FCYZN3TXEtZazn#dNtHID?=0-GxVbY_vT zw-(hPRMr@zOeCNmc_Q)vndD?8fZ(Rf@|u;v9~}vU9O*|##L;q|QJ50PdL-Bsgh;?s zRj~-cCX;UM^=Ze_B4mfGU5_-25F)Lj!C7UKI=qUIN^;tstx-SleUXFnwzbmQNNfj%*47zv6U_O$A#Y~kxnXIcIlePwZb?k!`@h^BzSKM4&!)T zv1;#-3QS`&B?9;%aqOxI*K(<~BvvEb+W!=%Z8wO6Zo_4{&zUlaUFjgGL4?}QMxWjCG!G7=;`Zae=BB}LuyNw;~jOAwuDI4z&BcR$2aQx>5qa;_GK`c zdFST|nPF>RAA_GBSglv~XH~ecA0o!=r0C2StBUni#U9yjg(SCpY?7argqxh3{Sv^$ zUoE(c?1yT`zR{HE%}Y;~8jn4~XV0MGI3YGWo$`_tV_lRhT{ejF^}bDv*1-YFlcH=o zXtyqT!er(CWOEajgHA7LK7Yt+=vvOhDHqJ6I1oB5FvxHo**^Z{W6%rDyH3 zUcXQ9`SKKZ$899EsM{+z+2f+%8xk3Vo)k6T<+aD2U^PZ{_w`k-`4=Sd%J|@ zHw%sjV?R11+$8vE^(@m7{ADs}#DH}GlL{-X652L#Jdz}>ti(Oyio#Z9@0Gf&p1-lR zClppnw#9wxSsUzpSf>jcl!=y=HOgxgZ(${5je?vLagmN@J!W40^qSx%Gjj^&6RfbU zoD>8qCK0eYALy+Rw88;%5Ql76hnn?hw^SbrK8v2UNB3MdaoH~>!9K~e-(lu6lYEEp z4+w5pd~X{=@(JOMk{szq;jk*~(r%uKBn*n#pZ&~z2JmmwVv}T!JHl3BjTeY`b*~v% z+-v5ZjTNK3NvqvDN3$~=_X_c3x_3$oqkKsCcDK-|MEoxlNBT=8{3Z3o$_`-HHHQC0 z2DM+a826>D`kldn?C$MK!B2{Xap8NFV)w2HSyW^9+o?8XxdM@$T# z0T>dQe9|%PU`XfXsbe~|E53*I!T#`^NLa5Ymn^PPHjZZnpJ;*8XO{?$=2p(?P}kAm zVD!Txfs8V}dx5SsjrFoY$2tX*4GQq8icvTt3UzB39Ba@|D#~C6of14W-ks`<;}*fu(Xfycxq>6tQD_|$4yU~~^Y|K#-NUR@QU0(f zy!O-d^L>)*b^bxdIOjO*Ix$d&6Du$*^ZpTqwp zocFRqufB&_sPa>qRQBua@+Wlt*py;k_jdKBx4%i(WRD-x=Mh=9c|g|>y};g2_MnEpBe%M)W6kAPTZ@a-CDY{HchV<)qi!GD4JJGpFD??b5KD1qNH&}n3SlenM!qp>|5ar+HEf;IE9J2e>|!J451 zl)K<-ZQc4_(d{?*h?FAEHy+-}aLOWl{kd4%PS|j*9}w>Ey`WlY#%hxp4y(+rm8Q*r zgitTA<}8JeD%=6B$6W&4D(lpv z^-m>LIOPu2S8?HcDcp@g6t;05-Lv78+TWuWywL7a(x*p#XhWxsKHof2kE0)WySTmL z-Jjdrq^0%)Kuh_TYJnR+pcs4Izf|pu-dKP+#+ny>&62P9y2Y=4)y9;j%rGRY1NwY! zHXJiZMY4L7Ka6bHN+mDsJ;bv)U5U!^h92y(w82SBYIIM^j`JkfyOBYKYcR^!a$}B%dfXwU?pF@!ON9-om%dD2DhBC)gRVP*H{P78Y?#ii(MODvhBX4r zF{WratnGZLHLL+5AsPiu>US)=t>Fet?f8NQ7J|mhUZyVn zdvMb7k6N4s^5b+TUh1UCEgEv2i5-&zi~13hQYAx z>Y%yN?|>uNip?ECXhrA4|6O58NalFZpmPrk%itq4PQOW?SL$;!VVPSZEYv(E(%IJ- zofMHmN;DxX86BY#Va9o0z@sk5gGS)LJ{v_}n~kDbPX&FiKKl}@!Prn$y?Dw3m|LQb zH2i9elFH45%~B(Vme z2v0(8m^E@d@Mjp3HhABakhB*=4d#WrG-mvkjF*QbhR;K7m=kimn+(aH!Fe;7%77i= z80Q?vDPx4>S2jWtYw)4m;Vj9R5tiVQD`r(cq|Y5*XE2TV1F06Q^Sp4ELh`qzbsmxr zbC%2>*~qOSsp{q78MwdV?uDeiE$gmi$&cJbNX9_jJl4H7cs0hreN3(LkYwBgP2Hw~1^sB*VC{>~aF( zn&agmIp#(XA(=nLFq4oBOCaL7WsHz~aU&%2nKjyWS%Yv5Ys7JeA^8P&FC;&C6CoKP z*gTGM#uy>_yP}bYWbOpWcRArUg=GHx)=WYY(PkQ!V}#_FH9|6<#-MSRHLx1>h!w{f zhUEQsFC;%Mk$Wv`%u&mm+yN1qSYTKgBP5TjeIAnePzC8OCt&!<2jJagmi#me$rX1m zBla)x2t^~l57q~A?&(BG7m@a@{pXtT=HfHZp4cY8WstW zhaJbrk}nz(l4QazYhVFBum_JagDm-SHD!!wOH~P+f3@7_oT)X&h>Iu4p?O@e(4*k@ zQM2kCkGKfS-S|~%?5^)UFOkkFT&K>+iJj_odN=+sRgJ&wjX20Hk;9-J*PQ2N3~L}# zNQqzhIX_l_3>N8%i?CMUK_l>A%rZ`e71!ICF{*H#zBn;!tklt7TQD>zKNRuQQ726bsQqa=hFcFVhRKC|KjodZ81=ApLL9c|QOT4BSjlX)-W{jXkP>vjmb5=@@&+Oy8U@WK^$87c)*4@wJ^y7c=hO`=#Kwqcs@^7*|41LmU=3m;$}nrtJEDNcIqk=sb>RRDyYb@!7P~eFC0T+8HC5;#_vk4(ib49{u=_EA-jED$7et#epz0pO6J^Ml{Djpl5GkR(1k}fL{4p#xP$S37t#RYusIf}Q zqHjsYXtM^@KavnXZLEQxVaGA7 zfk=o(ArA6cSBw#IK&~jwPecEH*;h+#-n4yatw+F|2_|A!Wn{ z7K+kk4J?r3<<_`-*;=Qb@>xPu0n!g9v&I_*T9Givw+84y!5@`YVyBq*d``Y@0i=i%1SnDfxbU!b?Q2_H?{K0&z464Xarbi@XJMWj3~ zn3Xf5q72I!v;_|waC2+;4g56MNP9RL4!A0yf1SYkSHEgL+#1>idTj57y^rM9NJRXr zX@RD-0=F3(SS2i@_vjI(h{Tggh=2UE?PL7;gxy&WG5^34#21CO zSlbJy=fyI;26#jU73x4-u^B zx^-&gCC?cF(-C$INqolWCB3|tp*JK{6f+fEb zy4joom8P~vx%+!q&hYW%o8`klQ-DAO&7+{%u$&Qi#8%`CV2|=dLC*N7K9s=qV;G;~ zn7t&8tYC));s|VqHY^kzE6ix`g{W&TLfey)GG|%@VIt z&C?U&$Z>>xaYyGENsM0axiUlkoCb3Y{2ZEgSptjYcvzFR;J@ov^rb>vJcofw#UTA} z(0@vwnchEv0P#S%198F6neyKi#%z3)HKJDp9^zq%$T!VVm3l8&;)i9RKT6jY7Z2l) zxY!4OZU<|Zuz$GC@2U7v;zFh8bBSE*K2JXxlQqUn9XXveiP$w&d~P%AM4UJn!TMD~ z`A3CWXq}IeqaG_wJoGh_$Zw94K_feUg+$JCK#X*O(v<_|1cD#Yd`chi$9PQ&&5y|o z<2-ZG+@Da>z7?9*i2MLfv&7gCbI3+L84Z!nB?p-%WVI;t?=EXZUk3+#tO0BWd0?-a zeidy;%&ujz{+nAu+pt0$6PXcTBVq#wAyWRn5;9_FinY3|L0yiAHRv7SAIf&})^_jY z@d8!S(k)c)`Gdi+9&Eur9p!Z`epi9A|7syW(I9qg6k;xdBEZraWN!=BGO+;Et*6xK})WO z#YJRJaKX#1@c@lgu*O6BPz=)l2K{RUKAWnBTceplb8A3wm<9R_buuD0a10{Zi-yb^ zF~f#T_?q*)U^T1|Rs#?9B9;#Qv|*>%*eFC5gY>^akIzgqXl{)-?-L$!GQt|PtVA+v z(2-e2Ms`H=W&uWhj#snBK5LPz@rq=OE^9E``ZTr%85CdR_hGStC33u)H8!E5^^~=5 z=(NU*)n=xnD`X=c;s|V<5_w|?E`iJjBPe;^KvOjCijCY7;6;0-yi|w_CYclm#R0?p zu2@bc!0?=rP#&IDIqx=k5ZP4FdP1K(`nxRA)=RJs_=m>pCBG@uKh!6BNxmw($rp+w zqa&JYl&CkpsQN|uhd28K>v5Mx5sLY-LB92JjC9p}6Bsuy^Fe!~|1li#Lb3fXpI(kwERiC7FglJPOJZa+>T*QnhQP}mG3GuM zzq28awuPmt>c#Uz0B0JKv>PK+{-soZUzRCpmX94>)&LKyg;lr)_Ys_^5RwcE6od4? zFr_;ooD# z1O#$R1VMZ~tcL_1aS>KQH6DJTV2KgC`;!TA=9ZvY^pHeijIW!p1X_h=aOjGO+yWs9 zxLwa+1&)rED!*z`cg4S{~PrE`WWls zJtSX~LLlNHj=;t#BjN%F{gy&Kw+0=U=nsF-G%l_mGQqIKoR?t-vqbPvEvJ(LKOj@$9aXbvLui zcry?aysD|J#(!Agwv%9i*D{f*oMx+9V5JV2)Fei7g#j0gVQLs#vxl{^ZlIrJokO>dGC4OJMWAq3+yA^_uPB#bDkgH^PK0Ld*A!s7bKv6&Dyl^zSB4FxL(E$xiifC+&?X@4h^HbE(E>c9J z!}lVvv+)0+1;z#{K_YI{b)g|S0}=m738H#yb>%rDg?vHY@W{_qfd+99`QV}c8|;XP zizl@~RZaZ~5-d%(q?+z=0eeIt#zzu0;G+W)wDuJt zp^i7d#6N|NHwv7uF2g+Hbsi61=JkH;Wrtkx{j#fiTXp4$Ux&De5)y5>g0}E?{H-C& zksnWb29JtkHR`mn!Qc8y`12oIS@B9)M6%bvsy z{2j9=YtDsUlVF-7;3aikXi!{O`|FB{7#F_M!ZUI~2@T?b^UjAjc$N4Q5f=l#2Lb;# z*f&C$ZDCQzg?lNGib#+fA|G-Vh{TsAe#MaIa1gsG!3&h2;t#6|oGWi@P0i1s{Ms+m&vqP@<_ZkNOJk`58vm>1iFgEg9C#V)*w1OmNO6gsLqqC^D{c= zyvWBn>d6%lsYmOLL{&}wi8{7l)k%+f4@FW>ABCHTj)0eayoHJpknkJCUgBL&)PWLc zI3GNT_b_`l`<9b1NQ`nr8PSdcWmg&j3BR?Dr_eAYoX>d=A7;;%v9F|%$d|Dm6CGch zvSLL`OrYX1BjKaN^L+^kpA(!9)8Orh#MjhrmNv^jC(sdZEvQb_;bVytGgA@4(dKo~ zns%31^*XuzSAy!8js`79;sAWip~oQfR6|$|3cbh&Tq*PtZZ-&kS!7jS(DzTNdI9e{ z>-_eO5;~ra1}x6_jSr?lc;X8)P$21+kl?&;@F8Q5^B>lZXvhlrH^eeZa`w1DMagr{ z<>YAO_2HObG($-;9f=A@!b|G9PzNLs6Okb5ec8f< zJP3)%ha7mTrEnD!#0|u`K&bm}Rlhscbw|Rz&&wdX7$=UzfDtk-yCM>N?-?V15E79O z8GZ+U#o@}h0V4#!ep4GO>J@LCZ+7@~WJCjxd_o=+7al(#0v}F++_$Q$g_JAaYHM1~ z1w!4=sNK(|W($i87ej17URFotPvQa^5EmzO`bmQVPnbg@mEyujg7YH6b4$nj)jzH_ z0J+e(K&6ioSKp=dQ8IvcpUnAf*#rxodk*j>B{Xn@*oXx0li@#NzES>PFSErerPQD=GLQ zF;d8wk&p9n1d&0J0dX!6DdwH3{&(qAcO*PNI0{|{(Z$^kqh!78icc*wO7IfO=ZC7c z@)#5%AMQDFkL;oqG~V(FeTclRm9T$J)!#^`x}!mJN5D%HIke~y7rgQ5tGc6rEcz9X zK!iSJqb?`vI2ZZgq5d#CB9O3q%xy@#U2s%McwtCX!h4AL@vyQ35{SSo2v1^McpYUV zN5bR6&rx6c2R7$Xi8i)Bk?P)1NEi?aiDaEV@N&=yaXwyp!PP)l@LOX&BBm~C_H8)$P+#{_z`@JCM_();D3k@12_Ip7d zHlNqvM;x9ohj`>O5~$0GI(Q{{;fdA|NKBD+lp@4v;LP0T0}47zMoqt8nhF+NlSr- zBUt*Ei%Mgk+J&Og=6w)dj~++F&kc$V<9Qrtl>S4?%~BcFekaiI%o$8#H=4EBkuoec z!mKbE-?u|tFk2EA^gDWn#f9_13qAEzRnqB)U(tt%8qhXk_fu*YpGX>T zo!W>CM8uI1_x)Vk2#Rr$=L?IAFQ`3lGsir<_IU7;x~_3C!pyo};#UkGB`a2he`lmc zL?G__xx9}0hz7@Tox!mP6nw*TJc33+gLr~UGix?V4oh#xZv`5o1Ql(4PyHb3FiQTc zqWD1=C7|F}V2B2xoTy_oMLy@5o2&NnQR3%S0{$nY@|$S@4V_1bi~6~(Af`qn)|K}2 zxM<<~o2vVL*e1e5kB3xYb-wQ^(eRi^P4$tF zi2T_3ax|KwBpK&sQQ{>Y#f<1NFszRD#0va-_v*uFoD120ifTKc(a4~=w{6GN`R3XO zp@BW3XcnIMlPMk})OF3E-sU=Q9Y{k!apyKjPL?x1Bi%g3(*cb}&Tucil;lo?CHXw! z4egqB4`zp)5ue{89zY`}>hPTNzB$iRT$77Z&Zu?+2#L!(;0^Zd7PeW4qzET2e2p>e z>OJxy2ZRo@BkF*}KNL_MVxrETi1k?TlDaN5C?-Pt90{Kz==V}g_#8s%BLiN0l}SQk zWjQ8TUHxb>q5C|N*!2MlkeAib;Lnao*dut!YhNQEc+ltoEhqTc2Z^&*NldV&g{;a8 zfaenE52lLlNVw-74_>-lO6Q4n?0d#4WoVjXeeh)}NxHSs#CWK1W{1%l=6I`>=J z7J`JM5JVN{i^#)%hxy|<*)?zN@Y>f0R#im8N0js79@!Qdr7JS$RSEkywS8)VXt)SR zWr^eBpQwZ1kxc5vfM1mj8X=hFqXRyULBd~@LtMPYf`fB`K!UB~^~ZN|t?BE>Ve?1i z!&8v>&p*muwd#J?=LCnSs;NI6iE3fD@R{^6#RT?Y8iXfYf5ePPT~5>y2ayjR>fcs9 zrI}XUzjHPLQ9|O+(B_SuHJLxinv^9Ze4cSWoPzf-J0b?gfG5>RHPxg$T1=o~iSq;^ zJp3r}| z|BZX>RY*MfWN~zST`XTpU@r`bB-=h7LrnZ~c#d<_nH1|lqT?(|OuUyi3(OO#i9QyB z0&P0Rgp0=$Mn)v+a-z;hR6MspBt}_rySo32k;oAyD43_7nR@w!7hjlp>E#zc^wFKq zJ-zMumtWlW%pbB7A9?A;kLV1iU;5~a&ob@)b!|;*lMDwV^G!}ipoG$1XQ;~(=fCcZ zXa6WE$$U?()ptsqzP@q3{xRzuUcSi*0&h$_`M32ZmF)Cul^%DAvp;8-IPIoDPh=4# zZW#nN?UrPIy)&m6TV$@&KN$G9p=7;Q=f91iS)JPChAAIrUA^taqJXYs==&|q7RwMet)XryTX17f}|Ln`#o_S{G z*_}IIo_Y3zgY!@>w8|`Je&^AnBh_oN(uFPpH4!umG9sG~0O#L^J;W zleqdlLdI@W<#v8d+;7v?BV^9$>e*$wohMXJKQ%cgrDnJFrng|KVnp=F&v*^Cxkp^6 zdwqrHd8zRhgFU(=AORqXWE6>IaTiF`8)A@fLxrNMTd z>TKtJ*?C}z?L5=j&ZC{}JVw7Sv7Hw>+qu89ou_5z#1h+iv$LJEo$b6JJGU;eowqvM zIn~+DYqE3A65F}*+r4o(cpPo&Z08->$&CugM>XSJ)q(tsS8-M&gY##;=w zb4_PES4!YjQ}42|bMPuE+R06B6QBY+`8P(FHQ3IFN@~tYsfLC8iCpJICKmkphGtb1 zXT$&2nR7d0YC;Q|*>3V7LOXOrGTkCst{NCNXR!q5d$sj?Gs^V#F4K=`Rgr7=GtMdH z0d;tDPFldVzY=7hZYSI>(@QLC5?tH0IfoYKzFUU@+a$YuU)Lo;XKxF?uz1nt!C6leeX^MW{$4FSO)(N-`0pMHMZ%TI5c znfWLe06$Q;*cw+0-gVksu_6;oO!fy@I+kU>uOJ(=KHr4Q|c*w4znX3V(&XU*^A7MM1A_CI;&qR8 z5NE~o=nqRfB|H_ud0&0DHps+8UQpPS$S(YPXnSEoW~#=cLh z1S#q&a{K()`~CaH*GjpY~*&?Kks@CAY%ue2?tz@1vvg z{fZ4QxAO<3-NMUUz|MV&x{YR_%lwk+o1C0Esrml8ak|X?lIa#zLXmk$cpePeIrCw0 zHt~e>jMB=kjFXNKb3h)>3*wyZ#5u2=yjLwC_vjf3?e8P{V?3-&(ELxu*6-0Jd9*5I z2JHLC;wEl;)NEHpuWJDrCFa__+vm}QWS$Lpg81JRR}*=BpAqu+vp(WIqs>Sjq+Oky z;kiaKR|h=N`T=cCDQKTl4moE=aaN)p{gTQi!8s+)+kq1fFl`c?W8%EqiF2Je*O{Ge z8!~;rl8wyMiV&~$63+gp+pOA?LuDdkt02BB@U&a!d9JJ=>MBC}MyYYFlyID~vf|umSqP1A-?H9TE{es=V&4#xARMp-dfz(;f19#-S$#b zyP6~ILbwn@jf17$%bX&?lDV*Z)gyY|+-cxChbEXh@{W8bZ$UX70=?zlR zPSC*(xt;Hqz$SO{NVSoZ7ER66z{ynXT9FBT7FJPp#3!6YM9%5QO-{J|jLU4wgCDNF zfs+<+ZEd;}IJBF{eLo58BCoGxGX3P*`TN19*pf$0E+oUrmdkAC=;Hkqxu6s3`WSz4=LLRF7 zR)wg8^J}W>zO?J__f^vVFxZJ#c(j;4+AW#UPGquKC}A~c^=p1;?!uIrb%QSmvMWw3Uc$Tj74 z+0J=P9<_0rfmR@oD0WWAbF$$L%y7=?<01zlIH8Y;v*{7Cwg&CQ>bSNa6I&A{ID<#& zW;wDx))Z)5WCpYIHOgO?urDeWv>OO{8})I(>f9qVECadb#!kOQ0PLqxQ*G z?Q6xdPf-FZ7k#YS$)9c!^%b6H1gh6kdXGwM=zEZ7J|apW=i*gp{l3q(`2LffedkfY zCZT;yS5h~sMMoWKvs*(ry!^u_BX*i@r1J z{;HZcQ9@??`rOCnE1iAc*6RBe_2k~lsM`0}T75q)uI;h{a^HF3Qd6v>#QGb86M{={ z1f=k2UNw}Ed-Unf9=)%rS~AeiD7Kp?uc7@bI)1h_lCOj-XxIMJi_|`?*}y!i@%%NR zBtrsW=MEwNM5kFMK8E6G_2Y@myV{(?%jUWUBj8-659jdSmP|Wm+GWP9=(5^5XC=cq+;@Jcj_e+xeUmol zq{R1c_E>BW&T}muwQJwq*`s}uJ8wGN3S{=@5biA<*Xkc;=X85bfC}uqnQ?Fyne-j| z6~TEbtf*b)*PWp*;be0TFWY_Z)<-+!314~CO0>g+)b^C`bLj_M>7noErtOyFbJLAq zc5%xQzuxkeWCsQ^z#}0rqyN9yJVQGOH6Vh_g26l2Stx6^UiS=S>$Qc=CpxdKrFlga zO>26GY41(8B?W|@h*W@gv248@5F_MPwbEK}Ahk<#Hy)DvQdDVn{NoRAb{idoky}sBRi?oly%rV4|N7(9M*6*~Qe*TBsqqr%qRUUJH zbN-)sdFO|=ztmZv+Bb;cX*j)Yh||f)o~3P0V@$(o$sFu-uOHgvVPC^($y<=q_TX9V z_&alfFV4L1!I^Cz?u;U_T1(RogNE>_yZPCfZ95COs)t>Y(B?4dui>zMGDrUFWFP5j zkA?PqTO;!XXT!dypMT-$LKOa-M!Vh1!$9miZSGz*+rLY7jSfz$(1Ll)a}Tr`A@814 zaCk~MQj#V5R7kS+Ef&7OLe^mSZ@}BN2?^M>k?`oCzOlNu67U{cnkafqi+h*Fu z=_YIpHF}pXj1YIvo=Ty2LE!i5!GH0lqv%AvtTI!6RJlJx=IFE1B&FuH8lu-%kS_Oeag#XTJ;y{YX|kVfA*V5&xlAF}V%(sux|#hN%9N%cBwg3$Yyi@d$Ncn=@px6OZv|;BN*4gggd|~~|N52) z@zE4KCARj;=B+vnfm=(2jHi>mkJwpO3m}&ztpgxCtjQ2SE{Y96+_uF5vO|)HVE>tK z0T5=nqoL~yfNU`ryoiBhbpXO}$pL8@GAji+Z0>2C=~RtCx_+1K&s&L74~fvHut#FZ z5SG+gK_t+U@!-EFE&y^>EGLFX$Q0586(Z!cq}|ZwW1=u*0ED?|(j*oD*(Vk_mIjcE zl179?r9NcL4lpBnlM5k-wDbbqAE_mJVL2{^{3dD$AO}sOn~&hxjj~3lWlgS{O2P{iWb(VaT8`kC2ujgQt+sT`@wcGbzBqElP_+MvCAp0pdf( zq!9_@Y684I`XeC5hO`5=??qG^*j_hjeti==%Z4-1(hFP@v_(jecGC785PAWdvlZz+ zRRM^nn%E1fM#usILE04UL#pQz$E|5cbXv}eo z5n@VUJ8Sz(lSA6ZLSY?pUy3iAy|EWUCa3E+YrAf25fC$*F6N8>HNllSsai7?csgr` z{^V#4NRw?!lJDv2?2uI#I_r|1_BCd-%}${-r$VX$H=YnYZf$UZ?qpGGf62ueSGL{Q z>LAxSTeon=d*Q0xFp2OQZm`h0Pn#D+m7#54hEGv@b#$iX%nbtR6P+ z1!o-{Hxwo>6>r#w#Mt$w0i`Ex|D4^$DtJm#h4Z5MQtAXoYN zKJ~D?VfK|gm9ou}xW%LvJiTqFZ`ky)I8R@d(${5|!(8x`K4sWUnDRoOp0(4ws{tx_ z>XY}GimMd8&SqSTj9%WZ!h;JJOdKwF&sY^!AJeu&-unCiynZ{*rZ!p;;Pz^s0`BRg%hgsup~m5ogZj3LMd-{h%|bHAk8s4 zZz9*Lq&^TVv$BnQyEm*J7gUwsw8zs(xBzyU3#^YK8!mjKS(n+6xLaoDHnw_d>;3Z@ zY&WEp8_Eyu2HFPIHNJ(aZlFE?!nVRq_9{+l^pVNL<}<1eSAgDsX*%NQjY;(uGq-@= zbwr4KflwHRj-Gd2VHj4jdY|+KxBCNOj!X0EW$BA+(z-@CJv6NwRJOqDHhI~Dw+L~7HueI%;C3-|bs?XxF)3awZnR#M)-j2iGI707 zclr6?P4(cGR&l)%;kaFu3ofmI8!U)9ZfF+5a*dsyw;(Uz#u8|U;5}izuq?P;5N?O0 z)ID7m+&owMI4$6IUbX?RzXP&>+a81WzUC#^3%I#5FBcbYta@XF)VS3HYjC{v(tM1! zeb_H5#2dJsQk3{>DGRvKr%1Uzc!jxJrrt8lU>|^+V+PyeaU+Ynr;EewiX?HRb(+O>Z8b8wr{Kk``h>>xIa7{pC`jLyR#$N- zoi(LX_PsDcPIK=61lx|96yB+zvyILQcOEdE*I4-LOQH)V!IBU{YAUQB_~qOkedFf8 zJ6f*>S#wO~eTe)#X^Xj1_d+c{wK^dKwrCqOLkiK`YgFygS*%6^VFSy?NO=0#S4!NN zI3q<{P4fnoqtDKGa7fr)GTZ>98nRYVp)HQoR2&k!g8 zf*sr|@r8XMSbfnvXEqi_??FSwU!ubx%4~zfJ4w5VTC!dnye$)6>Uw#~YbRoIL}}Lb zSIqQtW)Mo5z8@qL(nm+7ZES_E-yz;hp*Z~?X}!p-l%6gq2OExAye3b@&>3q%svm#4*c)+&iNzbj-_DD@!UXm!gn0OzG_ zyWDWw3cWBd^UbVOEUp)3B;&p$&YH-=0K91(bH&&S1JKUa#o}g*J0@q^l(zsvpMn`{ z{ximg3q1ZvM;ftv$4;NKx@B?Urj%Wl;^P=9YH4M}%p{*2ge8ymRkFvcKfZmH_5#;HFKTFAZQVqGaVf4@j!IByag zw7V+Wt_-n_`G7ad#EZ0+;k?^S-^#BaMTM@nKB{>1S#aT`rNLd&1aH9wmft4@ia(Io z0D`clMeJGi&kwTvra3Ql7X?wLX!<=q;5=EyV*u;@c=SyAcT5KaVlPSkE5!?&2 zbAngKgeyZ2pew3|ke24GUW^R$)a=2dds2E-bHZLlFwz*#2+k%-UX!p{=HF$giwY^4 z3-2?=0vnyxvQnp`IL!-KC~;xwF8MY{8j1tq>1`?9uITkQf8Z%uD)V$o)nkgec#n_f z540Hp?>)6VB|v;BRR~L3Mz)r&AJ$o>6iM76!Ho&4D|8kvFsJ%;Q=zkPfosiilQzHw zaPlOvI2WWZJ>Kmu6h_uD@olk@k9oLY@ov_pk>$_1U$a$B!3A>fbx8ymsKo_`my3a2 z6<6m17+b*w{(lLYA3S7O zu3XoRY=5q$#RY83sU_YBaLi{cxC@1NJ1v&Gwv0k@!PCn+by{xt3#tpAuE`86be4}O z6he#h^q%5v`o0!FVF?Q2*;gHVtQS^WFVvoDoQ1DCt|W_k9|ce6rF69-#~BNruFe1% z-BY6XIy0cm-)x>@Tg!8zjD@?Jvo;x9!8S(LMX^m8TZ?Tdg^kw&O$4P`2jV1bx5ReU zR?-EfTg7@?ouwjCK`9gXUU}<(B!s6eO7E(Azv>TJ-y$tT92f4%w##C>uYCyHR8X^Xi5v6bx5br zh|Rc4DSB1b3k4T0s24U$nm-X+=&Za?m$tL&@7;S3zF_?-*|u40%S-0!29+sWSMMyM zHgl4y-qT$@j2O!FCF7Ko0|BoNb?saaL!?bi~96_2T7HW}pLV@XDCsIcM&>Y*str#6O2-~y( zNVZu)t1H^J*FaSZ1L^~zlq|<}jS; z%ga*gD@?k+zNuariETO2S^gpea~L+Rk5&bxh2cCY^XJ62(ZmuVVIrayX=}Be6WbXo zL>#x^Mt<9)ZC7F{;>PU9^s(F63PFxd%rwqcm=|t|<$Pc(*fuU{C^em>KHa4A{*E13 z3$|UCBy!xOU9h1vW+)wk8-a9L)3Lwmq7X>TS?AOfeuuT7bXw95igl$$Z(-D57u!Q+ z`1q4uX1NF2jNG;-WSb|40&aWN&-~+oH!ZkuMdnWiwiXvqnp2EkI|pW0<>i>5T^$k^ z^?{Ja!_ZFzrP!8f;qbP4=DsAlv=-YC{)D9Q;}*X(F2vioSoxz26^RPCt&_s*lIVXq zh|X~Zmm!fuPX~m@sjc25A_y0i|D;6PbD-_0g&@Li8K-zRL7g# z3W@9W>TKgTSEH{(rX+kOC|xh( zpu%EcA&r3+Yy&quy=QDhNc~h&g=w48IGoj*#wcB>{Vm!is1TtPA(>JF>6F+! zpq2%YG)c-At{J31+13KcNzMhLqdcjG`;B-TX{`<_xawMP+pO(~WpPf>QNExJ7kAeT zLs%es!SAuysbRg4+Vzc~RJ%c+EfKO`k~ayANo!h&kX7c^5o24H&f?1Bfb1I*y{l!@ zc};DXtvePMy(HD6+UCsTLi952LVf|YEPyboj%%B*beE#{oSpV!anZX)VtAb2sSv$P z;?6?(*rRuql#u8zYVi|SHGVl3M%L?@ZMfj$)J`$7SbnOg2^XBrDp3d^Ys9+4&c&5O zrj#GD^7JKCNDgas>Y@UDw@Hh(rFPYD##@LLE7W2e;m>{A%VD_^ZA_zZ*mFTKctUQB8*X$KOO-&h zB0_iwXRWbCPqPT&5jQSYpq2OP2|yj!BYuK(hl03TJV%UMWC~{cnV&pbbh1$OZ>8B zq}W*@EQ#7_NgNMK>#H`@^bL(v$H*c%a9{;W`G)rx8IyVuo?7CJ-&U-aQldBU=%d9` zq%jVzsB~$#z?T}?+nqK^+N7#?Er|;^rIb5Am=2*-3i5aFGRL2m(wi1l^g?|_seRF~ zcryU-lzIM;l&(t+i%Mstl#Jv`>$PQ#WKk*CG6=V#&9)6XO-}^Ew)3)$`>Nws4fTN%w5IEVi-8z9gj)w-(!W$+iPxyI?LXuCvZc>2*mP5+P)yJwYkZjy|%^ zNYZU>{u`!3Sc3jhU9~N1FAz-kWt-2^q(T2WK19f*SXea9>NHeJgF3~?+Mk$OlLHF5 zEpb%a5o0T)!Ev$dR)^gbFc7%4tZIl5=z`cOv5nx*ew%uibAehC7q&6apH`-F&KBEX z%c*6#f(;ur_zv3llQaQd>Y)HHSyFl*?Y1;nfcI5t=1*CjExKUNW7`ewU*q!Mq_wz! z4JWkmg^P+rNK?!DScgb+b5EMv1!<(3U6STkMp0Vu^ok_%#DlXHq+uJhqbeGU?cgaR zi{H(Q#a3Q8xW;hZG;*Q|AN=(R=ZE^Wu8bl#E#fS}=lws5mlM-5^) zvs|Ilu8e3!3OppmTd5b-nY=pW6QwsynMX05<#!t45y6%dO2IPJx3R6)`KrF=6^ZD2Y!1ZXEp0bL z>q6IW5zA@uZ@1=!uD@fwKnOsw>#LgFhEyB7egIpc7qAJ1tR84x=!JOk1lzc_(R<;V zG66}S5P$&Wb2<)Jyuj;Yz;Rm^K(OgVu&n^dWy4F{i53UQmaE9AE|>MUlMX_HpSZ)4wy&hp5ZF;H4M>j{|+W;wiR zrDHCs!1^g|XM0t}%ZktgaJRsVQhov;=o(*pF^Okskbjwh#;Rg@=7p0ojNf;g&Qg$X z&O99#|LF4q9?l4vNz+;w^_vY4@7raW7w9O=nzXVINU)tS^C__H_iKB|K}A?kYr$o*n^N(f5VXVMG)DAk-! z!C7#DQ;`<8JdTps@5Nhv2HSiLc;&cuMt`PpT7YmtLx!aFQ1@w=yR_R& zHHw&UeR@@=xG#9tM4*)B>2D#b;Nr}b?BeAQ+D#NaH2`3nR*Ms+5WbdP$V^Sr7=T&g zf{j@weoeAo$60esy&;9G>lwC*^Q546oU#0oEez$$7St_<#FIMbs>biS( z_Ue4BGqdUvF+_$4vE&zo5@o&_L{ShFK@UbB5JAvGy@XI0L{AY!`XIgZQYH~Bfko$@ zoxAMj;^GH7EoS1RD z1>2k{y~R|M>Z(t+f&lon(^)J$ z9|evp2kW*L$W%BA6kzoa9*=n;F`84zE0BDa*3(P<<_^*V%FfWjNuGd*gWm_|e5R&Y zDm7(hn1!STcAo{F4+%A3g{_sfPmAYs0?7*t59*f5WNI1IG?^;Fhy=BAQqL9b4?n`|nV1}Q zyC){cM`I%uXj>{!3_qq~6Qd)sGsE?evXY#Ko%_q@;+*0VqN9Oe7}{Y(WV33M3ZEu8 zTuqL_#o~?ApJBnnJipyX-hvuz?0j2SZw5fs0<;#*`Y;~9D1a0vdYBnxR1WM!hy!u3 zAhpJ%qpePI81B!`kF`2&w}chI*hat$xC^al{M+2&0Ua)tf@ulA0Naf|%nki|&$Du@ z62g8koN>RVsxY>D$UV4mdFgu}EMy%*3`t^a;Su+ex3Jx@xN*G;)>JJ-Oe3PgOKvf( zj;sQ3=-t{Y4)Lgl;7QZKh&rIulWw?wXSMz4QyZ;FMWd2#$$l!!4as+b5BjF^_zdks z#Bt^23J{pJ&6bj=YV|M){yHOy6_kCFH(3ifW8l84<49*Cw*J(ovm0(`y$3>!5Y~;& z-;a~xy70)s`|gEEW3clFa9F~%@k^o-F->yBRD4EX6VBnAyWUv=@^N@70%Y|N0Ko z^OBS>I0g8;JEj3IiyDT8V)GGFB=q z)XJ+xYH2lVW2@HX&VX`geUE?UU~i_i_0n4Jkz7ZjVDnpSG+CR9?+hTO8IgI z`j+bC4b;&w2Xf>_6br9zaQMr;=MISByxJ1#QIfThR0a2yWnj%Y+Qu2}N-ZMy1CJmZ zPr^3VUpU`A{6-WuFJGW1x!gfn4Sbfbf!lhDQ5}49w?-W-?iE|fnzXF}%odG=20CWq zW*{MS8l|zPv9@`hr$+^T+Nz`EiP#vY&68=K7_!}1Z)$2wZI;d74N+pseMNfrDElUhoc0 z=#-I#}#q08OShL|H?W225jCS4zoP~c6k@Uwn=A2A}1vO802&;5zbJF>eh%dy&ArC%toP! znu)yqph_Q#g;^l%5b$8V=|C>npI#eBoDOgeR8*#X(MG%mUI2T&yeJ39Rm4g!0ANEG z?z6k`MuoAj+7!TH>8Aw?h4`Y}Qv7BT*V*F&6>E|Pkf2PSPqLYcDgrkSPzWJfij?FJ zo=$t|8&LOg?`PV}VQb0*!%Hd4dv=Rn>K}q}o&Q3znVPdkvPS)g}_L*CU6Zr97Y8Juai&I2kpa1!emn11boq?2h9TBQXirLCFAQh5BB8#Iz%HSOo z;d7Y7DB3%yQ#IyETlFvHf^Qn!9{GzG;`OG}kVPfGOT^_7(uea@ptZFsE#k<37&vm)o?b&&yQMQ+4S zdQI@*tR%Y37WV^F!bRfkT8bUK<4%=7OXNkAkf?vwj>?=L(a!&ZJGRvXEoT`kU`3&c{ASvEx$b(IYf6hO%qje+B2DiX9FbVEIWXJ1%`&0n z5FONjj27ueeIat-?a*~k?15f4*T)s3e!b27J<8_j2)<4T z-SZiWjv%Q*VgBKJ<04m(`a_OP@4+Q-ypW_8Aa>(-w159lGedoIkN>>`p6a3CJa9HR zU?&Uq=fzWzS`{RH)O_d-*4!JvSiK9n&)o|sl6p3s=LHq9j#tysm`T(q(MLD&7rzFp zYS~=TT+yGN(_QLRbb?+5L{B?KShoEX)kCrLTQ1bms(#W|yqU0z5Yej6jZzY7Yv0^U z`%ZlkI28C%ivNF5nn1Y?>`9v!kXKQgKe?p6FotHBgNYLsZ)! zS~AS#^nnR*)mu*-c+ZpT=~6RMl0hs?&uy9q>pO&Pum%eMjQS)uxL(y(D2wXsrvU*d(c+NNW9JWd`! zJ__eUl52;O9!SYP$ra>UrOfU@M?lojt$e&D3K2?n$sgcm zv77eT>s$%61}USs*%+x|hmlvOnv-d@m$$8?LTk}W#=zVIsYRh&MgRS7o=qbs9Ew2{ z;v)Y+t^w2%C#%lE{iC%-bmx1r3+8JIEjh2(ZJs41m~ijt1};Rrn_=m$0jTtz(?KH>y|i^oDwE}v$X!x!h2f2q4rZ`F^}f625% zBZo{+5FR#Z=tRyaN@aZgV9_#=M9O+sdg3ya@WsFM@`lpuyw7*VC6f$nLX&c+-j(aO zm&s&)iZ~ zC&a{!XnB0sk3Hr4gM)USb$sPvpI~l8u=$;&TW`i*p~q*G>{WRlRnRG-Ki{hTEzo(n z!NX~LLMaUC&96CLu05>xT(yh~?>S)?a)4ZZ(=9s`QKPMk>G$5hzLcLeZX-#{|G+pNcTZC)0MkQFa zm{0EqzMkRgW2pwnIB>pCHxhkl(uCZgk#E=)z<@tK8um0tabI^VCKhct(P z!eTm-&lcYhC!ifnId9ZK7tDwg`9A_J%G2O6Q&!AfvJ=^^DYW~YT&WUgw(DyIqdf3I zD?{UKP{+1ud%~w3w)pb~WyJwz8aCC#rL5-TUpl5D%@SXIyUv0e^dXExekfc`ngxA_ z(KXP@<-gcm)Je8Ookp7kQ&wK@sK2PypQmaXeUG0Y*{qUi?XQ)s|2Foyk@71h!yw8) z!_VrWp|a4o0pEMnd+lxGxnW(fAmKddQN(i{mpkYMjk7Z|{SR|BU7`FbycF;RLh_tf zinXGZD`!bYw#T4pi<+AC1R=ybJa!Bb>U2Foo#$%kmT32z)dijZ=pdh#olYFTswaoK5d zR&hVEegzS7vbO-W4FFu$FGA<4B8YFSZYx|%1q0^khY+SmZKY;6L7q|9e#TvnO=T*)ryj9udFG8JPSqrhYWC}VS$cWPxN=*{QZc?}MRB(Saq)D`e(^~W zd2uP&6aVnu5cp9pC(1oKZdbbF#?1abdcLyJ*3|1!7nUh)iK*ZYw1w|`xd#DQ%T>Uw zJ1q5B26~h6O}*H!Wzbo z3d#>1@jDx}UyHS{7yVSW6TA3b=}Ms9SzDM2yhF(8RE1^sp=qPz-P8DIXFrtC;a61k z9PAD?8p3#pQMRf9%Zj(GTtr!0A_A0jcV~ZlG>ybB2}9;09)&q?G0w$c1}3iNd08#A zjz1)g`7VhiXsfb>%T|cNHY`ZQoD_N6#Rvsrj0x=F^3T*sshf6?!uk+>5Y=~4?G~X| z@pFq#d2>HnyPt+XXS0rFs)U||>O7`mE|w~t*d3e{`ZOwNofFn&4laPI1hl|IXM2pc zJ}5E9TMj5-)>Z;L4&MXv_$QtV3pTetw^v)mw#+|A$U!Ux1eV3uS9r05R+=@yW%i7? z7adjbwn0#PtcUR~0TMA5_>yZqtYtA?Hme!uc4A*`>f~Q->3k@fZ$h?Yxt!}cxXnNJ z{7Dz;oA%!4{@J*`wsv}?2nK)UzP971Z}B`oOD?$!Ftd(YDQ$by=gop$`7DG9i0IG#Xui@@6|!F=ch>#cHh2F*0^*l0hKX%a{|kA< z5AGEjBfnEy5xJ#sSP8^q9)PuKYuRzRUpP~DlNmO&+@+g>-%sJVFvIL!WU3d~vxzLw zZsgDJB0wR2tGYXE@?t%m?X+&f$^7{Hz|ME=bh>VVA;r!brN?U#8TNj9N|^8An~okQ z*IQf{iE+fAoRNVkau5BW`*_KFmml!>ZHjxjLiC6W&8q8>!jJ8HUSP;Z`&h|dEgSLs zzK8QOhx4#nemhLw-lBs19!=Vvm2O!J$Y4l;MbT&j`{ulX-dgG>o38;8Vs4c(FFN#3 z(_$a8=Vn6ds09{ zooDy6N+i>OGn?;HMv+tCNW9)4UwS>F6s>yL`kCMmf3ZoGt#`5{+8az%68+65;s*_w zKfSur{hh+I(mlG3b->1^*kVDNQjiYyYM**x9-9LBZm|~~>v>JQ>#BLd^CU&ilHU=@ zjY;}&KSr;Cr8t8%&|{&8y=(K@d-T;ln8xt4SaJAvS8_Pqg%Hc5aKXJKKJJP342JA@ zA`cHb6u=c0m7`ekErJ@40{q*tr{?u1`gw&`5(=;t42Bhq4g57Tj!h8yn-^r2Cu(U$o~34Zq&l ziJwt;)*m60Y|-Afb6Gz*zTl?eO6SwTE4wtFXE%4xAU@H;NUx4N`)9~>t4!nVl(j_! zpQe&mv{!?-eG)HAjJK`Als$o3A+v)>DOskm!hX`Tm&j-~Ln$3|ad*Th=Duw^DrRgS zJqu|a2%F+s5`CVL;RR_%-QIR7AUE(7Xn*s&uvz9KDh%P)WD}QQES6B{QTHMf90+}> zp!X6f!p2iD3TA|x1-Ui{DgE#a77WM48Egw^B#9yA?Y{q%vlvilTzcy z9n8yzL=l^y4qhv4EItIfvnQ^{WdK^dc$Le$Gy_gY1mh~T?gUrk`Bzi5W&34)w6F_> zOPJC>DR$4l6J{|Ek#12&=zEcSt2e?UF*m|V#i-44MHZLT=Tot*idE*1m7`#W`YJFCsIMOiZ9>%EORA7g0%G-&ctn)qVJO=Fz1nWBa=|JBhjh9FpOk<`%HQucgk7QVy?` zv*fE$BwcgKnvxf!gavkpLI51SlDE*_t3JZzWr@J(c8{ATu$u`FI?!8n(P}3+WhZnm zw;yUcU;@^SyJ@>*`a=yrYzGE&*Q4%vAg3SlXGL`sLo&u_mo`s}n&t5#ClNFID!CFL zCQi$^1eP>b_;VQLRt;frah(Q5q97Gl3jzq{k!6C76Vl46xQ0}i|YeM*k>^+F6p%_p+l9bujZB&Uq%qMf8Aq-^-) ztEYqy@H-FQ=y&U0?o@?1`E&bKu2wkOH%8RJ!$5_sjHB`IyX3rX<7VWn2TlG^FWH&B z?anKq*})C?6@91?iC25$-3c62!+ew2Nm`!&y9)t-E`3m|>pOxEuD*lydmFQ&sf!-L5 z!RZKi_y~}S!Y>Q#`w2V;?&5<2lALFD46u@Pg~BMtxfz@~~X))(X{M2Nl1D3xo6?)z^556uh#Iupu^I*QoD| zW*%QY#C;Fo3XSE%rJ%1|?V9d-tC++5ht2V;QH()kFn*`w_U*2eJN1BYzPO*ysE0$g z5(JOq#EzGwum`FA9UwLswJ~48+ix`-x<|C>*C|s+3roEzwC|+WsNlcq^Qiw*&X2eF z%J8mcvg>Aud9(j#=U|UNs4htxJ^`ofU`y>FXPeG>^pMMto3ZtC_~*6lwkL&ZHdVaB zK94Sbf2=oAe!I;*x`*GP+``StsJA1r=dQ$?gs*K~6OqQQsqUZM*W%oy&DuR3VV@)7 zr3sF^_2zF@J#S`4A8I}Js^*^%k%8>bjG(6tK0};uAt&%M`cGmueXl811>keNb#-hu znt3&9J~RJ$=vb-ba-t|EhuC~>m+im0mRKD;9?i_axkD}*`Z@7?GxDij==>hzr!QGX zbg+u{&C_ny9414J9u`%^l;TwJqx?)>U9@NJacc#vPr~iw{lI_$(zY0L|LZq67WlBkvu=n zH#pyj1^4X55*b<3R1|O4I?;4?R#&T0mNLmHX60IMR=-mTA6pa9KUQ6Q{~#hfyMIIR zVJUx1Q}g4tKRdeH&|Wrt(4g-5OP#aB{~G})saBKhrJ-*V^2$r(53RWKt#$SHszgHA zbTHb^ePPGfp`ETk)0JJ;t{iSY)bUuo>x1l=$qW4`#`UPzM8znsqV?vXYWsGxNz9)NqjMyjYlx7!pz6w*_GS0z~fXiILgW`+5J~s|X-P#w8U~zoOV;KR<+Uf`_SyJe;v_z|*e2PVTlUd%& zJYS)zSGO!>{@u3CjojkoXJV;dUA4*^PA$t#T<)8Yc!cA>vBmWsZr7)V%lvAov2+X3 z$YH!U0ks#OJPl(A)}I-;Qjw_rOICe%yI3u$)x$@1Bh4@lTPU$VH>&pP&lYZX@$hoB zpYjD0`c!WJtfHXFj0UB6+=xHrWN1)#=(3Vq{@(oDWQg6NhlTj{KMz)$r+m>3&vD}b z*?d&&-Kjn@&4yreq@*++l~H&C&GH)qLgc)CsHHk9wXC~#-q~)oV8|;jT4CxR;H1#X;drp$xZPn_m!!kjk1t-~LZDa6rABU+TY3+l) zV*D!`^d*a-tiPAnYSU@Se0*{FD#74Jge*>kbq(g}1qcIVvshp|9z=@zjjJH@AJhB4 z6*&hzvG~44fhaYWWqw3Gd0HH^(OM?&y`1|pBKuCemH1~B{=b$P{RQDWXJ3mJ26`Opx!8uMB4UA@51qQs(;S&ia0KZWADy!WO#AqEPcyjq^chr_P6O z-dr7I_5IVZg;u@SK57_+o%#5khs5sTl8d}C;|w1|%%rTR^{%jM?gM?m*M6!Ut}*jn zz8J{CcMqtx(n|NMoa==JT?FMD?r;t~x*vE~j6qJ&k2u{j+PfaPv?>)2zj++DZyI_T z%|rNk{2P*(rkSIAs`g*>B#VtD+)1!HA8+L)l?>hl;HE%yC;)a zxjjfCNcMz!Y4`|gq-vR-w2u+B9zW&F1E}&_jsa@;dmW0e^D2FXp3U4t;tucYE^NXF zN4f4YB+KtT-)jOORL&JaC7QyTDh(;j#9X^PhIZ}pf|y(JW7tVaqbm&s;`nBpXV-~4 zK1yLS%ctdn%(8QE6vk(BK^BAc|0e*=?C9|xGa63^bdD{8U$cuFjs3oYUWWZr&p1pv zrriAm^xCH$2W8}S8Q)g+|M=+LC=Iu_jqr{!2sJwW=jrkJ)27Qnp3*NF$cn~=bK8&0 zB?Z3~HLI+%+nj=>xU7$ft=V5ss_t=|kSiQ>rpJsgDUI0EyctxHEf1ygrS&N5D01Dx zx#^K@p$wBO!Y?y<+-T`G%P6_a+MWi=z=)#xN$>0YAn!t0k;)8!1t(eK-O8f+RZ)bzH)BhYxHMf(yW72!#fMg#Ma=XFx6;) zp@qSTM1}s(kV{K)!h2rp#nkezRabtAO;H!9(}0z#&3Upa@yZgc)YXfKZT+VyU5ucr?o3(A1W_|9t}R; z&-}d|W^*|_yO+1lQ@*^Q7B|xs0>Kxh;OOQ-cTb3f$MN6_hpWaAKMG~CNLe1; z(tiDMFkSQtYX)&?i!XhaG4h9ert=6hkevJox%n)L4%sY6O1hiiG}=Zd>JJ~3 zwP5MMf?k`f)WnI`TE z%@XM6f_FM~5?Pt`yMnb4%|z1ZeyHM`lRA{eJvDl}0Fi0^^*IH-jCs>wBW*>^=EbHT z>Zy6_qyBaJK86lFc5ydi^R$00rYyIcjp1tDeQ5T4qy3^*HYE}g=Y_bJKVC74HK12W zDQR7jZvPY2b8ym4D62PfD6akUv(apGONI>+78PZYaK<1PeuAjJr8Y1e)+QeWF6dQS zn(zk?VfkD_;mM>>o#%WLZvdJa%wJf=5@D2B7Hqy9&zUc*vu4$zfO)I*Da6|8DYR$P zRks-3B?!f)#zl@u=>V>OUIxxedODr7RS$88+r2g2h;uHM%xMv?x__9vG`XL!*&+33 zRL!xkq+7s_=Q5j`YVsn(%pYgbysb~EzbFC-c1y7z&*a%@>@Zunc`xtW4Bm$0`k&os z(}GxsD*?n016RYfJL&jVe*3875{&>U+kE_4Y%6V@99GFZi>!|W! z`Sy3XvUuKRudP@f1s}3-CP!bhLuhhwG{w7 zhHqy{ruF$N#s4o{;Ltto?VkI@`dbre=yWJq2{-&{UmiI)B|M?r1K-QbFTzjgf9mGe z+tAy|<9cD-X{cXuwfheUNVv(gFtC(X&^Tf5nu`zFj*;Kuv*eEYL=h2q7qHVSQz2*q zQLNqoPPu43Vwxigb$VhdW_a+ex)~WoY)VxAd6P=gC1uA`+umtuarsc(OF=4FKBuA= z#Hft2C@vrfFL=~!GOq!G3lJ}8^7 z@n@$I4Ez)H(Fu0Gyf)F{$_;CEKVcw5u|LXiBA4F!MhwkjxX3?wa*3O38vJvyMu_K@ zD11~**?}X(+vlR+JD6(k_(EFmS=VsR_d9Bf-}E1p2&H}|QNmv%vI6w%TCU0LoV{QU zV{E<(It_m_o0xM}GP+9-jB}YQ<;fbQYs4)O>08y3ju{i$U@vLLd@YMnx` ziuIMY>kt6H{(f`>U>`}Gvz)r712Zeb3;U1=(*we-a)>D2iyl@C+v}{&2g`Tukn@dS7jpY`K*5 zX^`o-^rlC%bK4bmXzDIP4vbYcE7+*MAwO_0Xy@#Ts8{M(YEsw3hB>Fuk6UuSvnWrz)olCJw17W_=@q4IB?bto> zKHx5$kqZMr_(!}q#hw#uKJ^ARXvDH04^MM()RMi{r9rTD-02)oL4Nbz*(7rtl?^F< z`^vbqi0}2&+CTq6F0&iAcby7VRpls<2%xSFV|88HmYZDq*9Eg_ z7Ld6=HMZOPs`nm%|9eI5Rafvm`nb~V+Q+I3NMaQ7<{bT*Rl7DPGo@N;=@}{gQE*hYq`}(p(y9*h$YEl zLBmq3nH{i^0lut&_M7rR8P}&Cpn&nLW4s4QJ6+_9+-@C3i8?zyl{1Jn7Gd(J4QU>nal4MI%aHFr(i4vCtF z^6mRkMk%*56%I~-nMOyY;6p6jQEqQar1q+Q!vwf3CmC9^;FQe%L_GkocrjrbY&G zTdt2WB#JAdPtLV>>{)XTs_w8Zo;qJ@s3K)O_H^ zPX2qLW3B=ncbuzRyeQXpXl%DB3=wEEYX9v0!7u7R&Ub+sXV$dMyAM%(n5%8y6mOjL z-;VsC_qZ=8+5Pe;`L6GyhiBK-4{_HqUN@lT1IqqzLNq^j#tQFt+))beWa`2&hplb3} ztTnS^wZh>3#&Wq&4Z476QOf0+BTggOVcL*!4v%NXxIf~MJTBUjDT^fke(8nS`rpk2NCOh=SA*BbN$b4w3~4q)oN|Fy2lJ04KmTZuS0%z^H`45#7!Ig z<^gY`Dck>rmbCyFt}8zzTU%6QdF5!kVwbiQ?^-*ol~i5j+wne?V!7s?TZBZP<}%g| zhVK|d?wu(LBWWBRuZ+^$3!UG$LFe7+Os3cbs9FxPcqe(E!1hV@Hdo1fe}Lket@XCO zh@V?kk68I4BpKa*I$f9FJ`HZuJ^l9B{Q6D8;V~EDi}!2WPi`z?7q#+PU(xOrQ|-g1 z&vYo%c|chbP{mBajEK2-A!Wxv1;hOyi-((iP<$1mJ8d5Dk3ahF=YAe#B)6!aqn>M! zJ+gps1^e0$9h)Z==fOnolg_6mKacA&Zf2B6_EPlxh@(W6y=QS}*J|`AQ-}B44R&b% z^a|9=OA>B0&ul^R-4;AX_rVjp120FS<9!HJM8$m&wAq7b=+%rsF( z1_zT{rNc)Y=LO}tGpa574@FTG4o5mwAJqo|{{rwBO(qsXj<@l6CFSN+0%az(Sl5o#Ozpe033GBJ{SgEYFWphtMPm840Iw zTvIxLE~kQ;iHoCL`2=tOS<~%A<^wQ%3s#7gx;XI9&ppdtJI+VNZmh7VR<$VmUM91I zL?6|SV1g!5vZFJ)t(m7;7z-xAMjN zCz?B0EFN-RHZAArXsf+>@t7MFYUAjIbOE0-@``#3Zb-|xPcy$f$BVBx=a2>VvDXl; z84H`I((Mtc;6gY?x7gz@_h#Er`7&3S=IE0_2xED)z!NvHCQPtBH1XGG(pL? z)&txZsPm{+P{*dH-m9cB>g*s#SsoL`=?(A-mJ7zi@~y?N<9OO&EG#_y%HScb8YeFO z4c!Y+6eofS2GsFHp~53NXK*|)JqPl}7d(WH=cM-sJyA4jpuuh&QpZI=48jM&bNGea zI+UuZ-Cjf+r{|B&N*gk-YuILWkI$u44Uvt1v? z!WuwgKHh9+1u-IzxBX5#_Bwyr2*Pyt&WW#Jz2@YbGtgA8Iu+$ym3#BUuQ}I%^-DW9 zqAYcHqQgu6Be0eXtDK7rBa2;u<5rH2H1rJ zheX8^|Ki);CmM>}hp%Dfjf!YA2L%Wcyg!4uq>xEN!IO+p2H#YA$B|4+zS z7KIJyIZQe#{KQMEP>^%nsug-=6xBAq4L@?^`1H)g70-9^lDSyJQoK~5&s1oR*<;vCu92#B^^Lr=};gsYyuS0U4*7!=?&A)D{E zYeDOm-%=LV7F6%vbp0`TAmXrti<&4K`NGubH>8 z=uO(ZJVJV(38UknkjodYMpC&-TmmB=5CnFvg1(2|J+&#Qd}h=6+a}8hW~90g3@=9A zgLhA6{!TrE>>Ukw;PfaLM10$GRVkQ#;_nV_7vMGqj0z|~vz*$joqWTApk{9!% z%3}&M_z><_ATSf+(|-4r9pQ_cu~_p&PWdkozh z7lL~XxhtT+OQl<5{6m{rDn4<&C>Zd*xW9b8Hqu<9mc$1`g?pZ7{{0zcS#((6tB z(UQ}iL)oiy^(=m#l7;rN(VjIY!7i5D*37MCSve|i@Mo!ei2AP@;W;IbF<#HBpo6M& z+d1$2jbt5SU4Xonp0wD8umxpssMAnhRHw$~yD2_u&tV0oOr_;I>dr+WGIOwy|D%VA z^#*<(ZBur~mGf-Lp-dB3#xB#uxhgA-WrYBRQAG=vFW9AzsPa(-^n`V~?aiIesN_on z(`S*@+>w52+qjQ!HdHpaP&DL0)(K!0_*rd}PIU|r%%1$-P5RochVE*&svmbla=(AZ*$WD6Q&)FDDdYO(4f>iN}nC^c@*QJfv@;s zVH?SC#%E;pgau!1yh~iH167L{DtDS*4gY!h#iqzx>8^Ncv}Wf0lN!g& zB|hzkGYKPUqL9SF4>T8ba*wpPGiA0iNkgx$QLZ-8&Thc2q+>sVGG!hW7%(u5!CHGK zu@0`3I{_o^gFWox#8jT&Q#)xI6zi60Zy6Q8rMy=_VDYCipvQR{#dh$K!fplQB^%xp zS^zKXHt4GH{e8G4Nu0T@)+>jk{t?C{8R4SnwR;#E1Sfqw+>(x81W^GSL8lMc_Wv@Gg7lBheenhV{o!LJYXO z!)h+<3K6v3`rW`o{NwHfn`e_z?=du8Pd8Zo(^(VJe{!ME3WC!EI~J@A6{eKVfo}r{ z**!}{C*|d=>B1hAu3pQKQV7uC?HVYx&Si1Nr^EP1Cf_*c4?wL^pJiA5xzB|RuU`%N zyX8%c4c2%K{!LCt-f4Zr?veg(8l;p9-)BBlYk|{bi9q4|>6fP;WsunlTmf5HccFc5 zq|$E5TSK5$Z$BPXIYG&ZQvt0&e}Qq9lpD_Fy_zWS+`-f~Xdmwv_w5%*opb-yO6eY| zfmlu&JeR_Q^q~EMS3?Hzn69qpy9C$Y*$aXb@Ay{_dVLx9!zEtIkx9HDm?-E*}DM?pLB-+hbk6I>DD#8kp#VOTm@e~ zgBAeCL{cqb<706tytLuM1SoC z?%O>5gNR|Kuqg5c9fLp*yEja)>rmF9bEr=MF$rKr0N(%N!J)5<4BQWh@HUba5z1}= zm3zM=sP3kcN86^7wjKHuzj5^#O z2NJLl8=K!yKE{$CGZ@uzpi+g%r@)mt4?5wKjW!?iOP&Djk&-3u+E@4aE=?*Sikl|L z$%2WTf1OH`4!=L9kKj-GZ8|+F1La|W;^jq|b&UGIlO*YWYoW^KFpc1=Nqi5>PP3KnODP&cF!i4D=TT|?S4?gw|Xe^PRL??wz3A zMB&r3&Rp>yr&`d&0{2D+fj&y`l(zh`Rz;VHI6_gFje4WywcG$b_dQX>^5hy-l=RDs z!B47}#Z=q2(FGczcO{_ExzZ=rCD*~5gtf@M?;T4f|DNZS zxF-ussl!g;BB4L=j>S(3z$&p+#9!DZF0~<;QAiuF>^C4Nt8Ewr+dR#snDfD=C?#Gt zq=qTSPipP4RU6((Cm>a$oKuJlnME#=)bPvOM0m0^5oO{+B>l(|3%2+sx1$!(@zL%Y{@X}m!?K;(`~9)4 z^nY5jd{mdjkE29RgJ>@2(k)e;;c;OJrb)9h3+;4GWnSd!aP~qM)W;@2z^0oITlN#t z1bUh`__&63ZMci`O~IF#o!cD-N6=e<>=^I^3jwg#ypEt5$B+(tD-+5VJ*BP&U*_d_ zUULg@FJKpDSYt?0eQBLyro=~B=p=bnASFeTFWNjizVDC%Y@{VF?DiXAGdL9rE)6Ii z1{u=10K$0g4uRMPYFe|auYot+My<3k?E~3=HLZ!LhMJ}qDlyu+pkkR*Og&()Xd1AK zZ>J~QwfMYm;mi8RxE7puEqDx*B%za`UclpSk&|wD*CNHMP5-KE`=@mYltx3*^Tn$? zVJlOwr$oEk!?W84lJkCaPND81B*1ISJkyFI4Pva=D!5bcUlFWzkZxdGrU5uW^~>@W z&dNH(HzR3uqCu!6C#BwFxR+o5X#cSrHtv$!X3`yko52Hh)!0f6iN-{3gF1Ad#O zD~nRDAuACS@&!vt33({#C);ezV}2HXH=0}^|1gnrXYgVAA&kUA+mSyjM?xF4_Z>`a z!4PfW&#+OL&11RgK*v;ukav=3>5Di{d`K-ft8>`^;>EJw!<92fbEPm=k_jyYjTzbh z2(P5I>5*G$p4sFUPYYRx1cj^p>Md%~Be}xTZZd6JxKwm)ttUrJ!=9w;J(#fAK8Xd? z6(cIKBRFB zdYLjR*s`*L$#+vJ0_(~MRR_n>OK=P4`Y(Hce-VJj7CvpR(Yvdl?Qsh0yrnZ(Dq;VG z)&0k7;TtVNQQ+?-z%{_MgS^Il_QJX#>LcJ>zdS$eMZ4#m$cnSsAl#W#%F4h}-F&_0 zm{tlxg^MpW?G^qy+|(}9rU1KAyMLjugX4)L;0S45f&78oAqY5~x_%k9bA&jQ?ZVJU zNX_JbOJ5uTI+ka5{PjyDaT=Xu+58p)3Srf~Gu2o&ayPFE(Lp&M&@&{9TImCsBOr~) zKg(tLp&1)M9$EY2qisomC;<)UUw9)<%XnoRyM_D>dfkaB+W0yMVa zZd^jP`#CqrCvp^Kk`x}nr?I-CwFRY3+Y(Y*i6$*+m+hxn()Mj02!jqp94QuP0$O&Z zKq@qX+aHJ-9>@7G!*T=Z_u($zCbwX?`;`)8KHoI*L(m-?YH{l7U}6osXcX8YHnK*B z3|>3?NFgREwclT`x2g~(*vvivLMz}GUuWHM;QBWwFN~opoQb&8(+swyxKU;fgZ%{h zG!1%F=J1c>VM)Dz?yI^tjNHxIkZe6pwBcQ3LVk>hBfW58!4FFc^A2$Mg3La$!)7Fx zy{YhtlEVFw1+5&_J;@h;MO)#}w8KvS@8;)Cy(w%$U z=%*sb7qRV%E}kp@C49U!dHjT9FMAPD3EWgsX6w~+7xR0*0nGp#NlpLT?L8vS>eXwb zOz~%XihsU*3X4ZBFEp>Q zLH(+s`OynijQ9{X*O3MEqc!EVT;tW0{{sKUXqHHpn|K?twZJ|<5t+z2QXR#pyT_Bb z^w@abZ%%Hrz{fd0ht4GAjFU#CcH{V}zb?p$YgW6dcCe+*z0J%yBt%D1 zultlZo*y-#&ncGe>bi}^&g`B#c((S%(*J%urV;2)dWhZ_y{x4%6)7vrZ~NInDET{S3s5Wh21`;wtX(?XV;Pu^L3_?w3~~LZdu_ znYu$-0t&Rp5#C9;v2Zu=FInM{A7RQqwN#n4f7Ndr*WaS>k?BM1qL0$-qQrl{tRNPxGiD z3iNk9;5C`{={EPbSZNtlm1pNO%#>HQ#lGroEH?ha7?(QT3OFK;;<`k`oic$4CX&e` zY%MWc5j)URag!FLXLwI2-`Gn=wf_}8faq%aMH7909@mKt+0rmW1O zk~gdk%=URw45T^Zj~rJ>e)Wk~M;D92DZ}m@=B9Q{O>`;pYN5%Z7)}$bKSBWFUqQdp zDX`yn>RpQQqXyKra>7`Ytf}TUvHbeL&*Iuq*%QIy1KWfe5|zf^v@el#@s@7m=hZS^ zHNH!{DVw7QbSdm=wlM$3m*Su?rh&jQU-fmDNeugM(X)zI%oM$MG3V&;KfdKD6NqMh z6FpgtL)+LC+J8s8bn5J0cEtE>;?**Y3Al+;NR?E-xw3-dvwEYt;1}dCGZ`7?^Q1kq zv{45$e%3h6k5tW0ksoZ%hOM%N6}rZ}r|Qan5|YLyAGDAB-1ReWAIF5GEGyXEolW@d zW*Qop5QL_3|Kpn}bC`u=eiZMKZaZ-+g~Zlbzw!e2;b*(0VAZ)0>9+`SD;&)K!0?n07U1;qF@#A{{Xx|L%+#m(%@#3 zxoK8eweR&RNys3TBxl9#V2!dx$ZAo(+(LQI5X#ISE6V5>I+`Sw0L^zH8)G=|I;Pdu zF@cSbNn1W958rhTj7tPdK#!-$vH8_<^+&v5Fd=zaCipr(Uz5gh8{JkY9#Zo_^j~?9 zK^bc*8FmSBQZ72*_pi-iRx1(h_I^4yo0F^&oHqvW6tWegwF`7vXf~s zM_R;aVwgsOv4Ggy(4XHM{G{*)M~$miX#{+xJxdg>I2`#RYaJ5>WUjQEE6j*Se)Sxf zr=$5n$wbC%o) zU7r_6<~||eC2_o}t4bFr;3@PVnqu8?K@^S)^NJ|g_+xFD3!Q*qzZl0QYI{|idWI+yZ&k52>xI8hz>2~qLD0^!QH6g{6qXrV2U?yvCMzv*_~Oii@k9hO ztW&9l@i-zn%Y|QYgu(_v_>B_Jeup)VNb8L?j&`wI_?v1J_6VZC)I(jkbf8ajzmES$ zY{hWcx8Ec-G#_^~|F7i($^QvqPW0;ny;8+!G4}_1k<-0B^IP}(l zGCz)$!Xe2+oNVdGwo%zB8}bHp${GD4Ja&6_XbyJGb={omO`cuC-`Up{eA8>QGW_|z zZ7TSLRz_S^rOKZ%Lpj61=~`_PU*0$|D>XpI4Wb-((v91CL3mpXt63{%F;+>$8+u!B zGuem})@zg%Nk@b4I(Pj#GMFWhlf8Z3Be=hBe2YxhWvr2{HFPZZ?iL01kc|THb)pdV z=Q<(~f>&DXGh6mK)Ut!LN{J{|<%x{j`K<5{3%{Sjd)(!%bG(`OfiBc+{RC$lPgltT z+jM0s0O00VRzS?z=$lr|7R-BB31Dj!YRu*v1m7n+7#81Kv$ZpLu@>&TAi>6s{{_OX zTO&31Ik}xz5O`FQ)Z4)k&Favqt)0a;lqK&fdE}7bhiV?#bW1(L{Oy5i!>Rdqg;pGsvZ_71`q`A%HfeHm2*>w}U98e` zaA(cHUSk&vWQvoHzaz^<2ld*ZK8bWv<;g0p$U6AFZqJlH8xc<4qTO6Y$DX+{4>Xw< zYfEZ_M~%I4+cL%;<=)r_OCormJ*E+AS3kBrJLd;-Zlx$+~xyrFOqKm~5 zf-#DQE*DZ}H?bCoGIiAo(PRQXSCSm*k7O1Ziv?e8O1SVAIR{0Aryib|vM&95DCEH=gw>t+0zjmAY_%Z2nO1jwFT1}S;t$z=?F1a;U%S5YNbm7e+ z+gsq=!R(sH8r}G=`aUKxzYt3rqNdO<4ynmp^@+=gtm(2+ewig*%qLWsXW84FY?1kl zWIo&yT`Lt`>>pOe3^ZT(6^yekUB>U@`8+(QT?>~~F+L`3<5}qKX?h072%0B8g+?YlUlboHdkmN+l zzs6>Tynm@?bA!*7trpfSVDQtj0DP)a^@5WXP-ixpFP1L`CFhs?Ym;;|`I|&>oBHX3 z8b_1-tT@iA!A+8jf-kYqbG`;Ypd zG3qT#n6|rkT$r;I4TcGqYg#Ard;eL=9A|ZmmE9G^50O7#UbA=mnvRTyP~Y6&F)*2T z2tLnR=jyCGV$209=%0qvlR`tKC|Z**d@-NgO0dbEjqg^MxtZNZqzf~ z7Lm}Vm@b=cK$m@LZIWY$b)s;f4?!1pi6ioKsbWuh5Q%fua8W<9&5lQF?=6sS&DkjMm zaa<`leQtijH%WF1J|Xxj;a`xiLlR;*DA=)*gl7h-%(!2YgbfYTq7+%zh{>`v>!il! zB<$uLH=zvOXXZ;~&x3tWQe_&gR@GS!4y)c2D&s497ui22=dE!`? z-0Jw|f8sVrrTN{C6>7?Tv!Rv!Kuo_yNK9h)%_ElOQ}5 z%>VA0ox;J!ro$RHtz~@MH7ze_pxdbE97yCj8S8->l{7?kHG2@Sqd@Yr=p#64G> zk|c{nz-Ul&N;&O_j@aU~YUAF@22o%ZGc!>I(=4@a2<63MZcz&UNm0{Zve=PC#dKLE z3g~jUPZ?}wSi$$(X>T&qWwGEp9Bv2Gaf@i!Y(rY4LD%4mgg;LTn!L2QBpoj~1zTPC zC?>07J+mALmG!Ras(RAN;LAmMLyhu2QQoFXo^T}I9dbI0@QcEq6n@p@j4;uXd!t9hA?97@g-LIqcRvlKa#(KsDV<}-Lf<6~8f4WY z7UyK7%6`C&??S=hTlpQ1Jmtc3*jB73Ue(MhENvcgTZzJzKut%ZJX>^@$iG!F_z8J= zN6m%?-=Z+Ca5<|+cBHFF(KEu!w##7BbANs1z|3*rv7cc?5w0%(L&*fD0ER?Df}uF!8|RRJl8QNiEA^r{fb!hr_4=x zz}W0oUodEVSF@MRa_|KiY)PuJIN2n8dqyhoEl!Tho3`H+aI+P=Jxc|mf13RcNXOlh zz+|2fbfakQ=|gA-y4L5N^$}%s$yE`24<%go1_KvFQa2xoD!WXHptRx zP9$!XRBIF!{Px8l2*EQ95kDq@O=6+6QlF}ynC@h})q)!ZvhiujS*KufLm|AQQx$_B z5dOtl%p0wF5_gs&%C5kl5M+yv+(R~7o8K?U?@MYF;H6Pt`01qoRgLEJWHFwcvMRIK zr2KfXB|os|Q{`P+nC^20hp%x1c3d2}^L!wY<-YD&<(#kvZ%EQF>l06Yo3^ml3#@mX zR&1ZpTzy@C?O?q4mE4kkFF@I=!VJoZolAu@3-wu~RmPSSGiIfQ`nAYaUuD?duCd=I z$`@*@592srYlL|m|y z1vmTb)n4&B!RHEY#U$J*_@v<5v@f?eRT%uJ=)`}t&hdFmiWBfdmBUwwj@gZ>{p!g` zuuha`q~J2j2k6nlq^wb|4GH%P&bo%&v^&)s(rm@v4#Cd~cTWNtotc8ux+;|<(20>u z^B5UQVqa&Tb3o@2`SX<}W{Bc4Q9hg~o2}r;y6C)YwL)5i-H%Gb?Sfwx{^?{}lZ0m! zD=9duBv~hv$$sTlao4ukbtqht2Sbv@it2erEO8B+%#tL`{3+-k_}Gegs7k8r%@oaJ zj=wf}+IC|u$jcQjXO)C?colCaL`R8Bg|~_dX!7DzTRra|e6zeotDK_&!Qq_(H~5a0wOTPD?N;G1)|vdYV^u}uFpIP7Xx^DAc-(6< z3CxE4f7(hS&MIlQ%QdV5?LE;p0&dhuy4PIh&0e04>jmFegPRuX1cz^>#d&euAn7Wb z?@_MU*oV*#2r+h6x~)j`O$)~HWfoS>-RK@0(4z70*)*DG80jUg~LvHr3Db;pHVN@V!zc7UNL8ZlhX|Y#C*CjgU3*sERRmHS8B>3tY+_X3-IM%Z&d;!PR>II9^ z*h8k>CLDF!q}$R&*ks-$_@)+_cMY*T)?l~NT6KA(w70LW=n>v zeFzq1M5C{r=-b--xKz~0hr4tyf%ij30ZxCS&;vq?b($5#Yyl0U@2nMk`NO!5B3G## z71PrJN=KU&EbQAlDyva1Aa<-~1@Y!J+ezM``36rDRhHi>2w9QeucK4UOE*Xt=A~6J z%iDf?1y8P(qLCgVIUmyM?kwMd6I>09S+1$|Q`|%;Xp8BA~O9 zFHFvBilT#>b!;)FeJW>lH)N|&j3(cEw5t{rjwOLj9(o_E-}$w@NR62C+VR?a$<_!< z2j)wo*9g2r(j*~lc$yJk@IDZms~CmFlH_a)#|1aQabKUK81~kSBN2|?3jp}4WKtaS z|1KR*1#tH&q4mG22;@Gv=|bfiQ6|Hm?o+moF;A51PYjy%cw(?mG@XpL-jN!|mEuTj zUFdT(3bVy=k#*d(Rta5pDdE&PR=S+1QRX=TrGo2M`;<+WYl?(;zsj!EbxoH&1C&SW z5^t_IiFjW;`EZtEZ@-S=7qaw58Tqm#v0@ze-vGz+H60g-;~clrN@Y;3can7mDOXmy zRHHCY6a*OBTiHLUaEO-Zc{)v3Ht(rJX<_Zos|imnTk(j}7;!*=Rm$BtoVzU>1=!Vq zGi%*18WyX3Gse;H?EVroEHch&RdQZew(13LyCo+CU$3j<^7*kuriyJOXN6^1&fx6e ztsB(^u+`}bO;;wvLg8-{ ze1&A#m#sMV$a-gLln*%NBQ_X`f>Gv|{$0;tlgFxJ91lpBwSrf|kl*Sue<8&fjn`Gp zb!HUy$(DGqDhA&z`1T5@GlOpxe5bA|VfF|T9C>Oa$`P%zCUwD+c-$3?`<;jMp&WgffZ#y^DSu8QHCi*XE3Nlv~4qBHaNp-iEhKm%6Av4$^ z+k|#_keOn?=QBYkv^NDKRs{ARZcR#_yO=8!oAc0WuH;48N{iq_t@#<*=?h0@Cy>5u zpKYaL6>NULG%MT506tk8n=FZ(QH;&0!A;uBg6|2^>1gl`qP;Am8$Lajc3tuYRsNZ) zzQY)A#k5+caetv;cE$H;aa`1gzzs;`I%{h(UzXzY`tt>9Oty=f$?)cusu=u)=u|My zD%qf4#Ua0=30u!kQDGFwMa(g5R#?&6qG;hi8qMnGF3a$rNkxj!r~gf&CgG!ejT_Rt9Zzv`4fqicknFl+o>>- zf*4{fS>DiPk96VJC{;0kExQ5h4Zib7VR?OnI4(%!&3ZeN!q+Iu`^}S)9&9hiMpLtc*!y{EO&({4yZ6!&C z%UQMZswBidjMo(=de71)a>Cv;GcY^z`);E5WdF%qYsZ^H>!YDXFQefMJ9P$T)fvi8 z^IPB-)cyBVsYz`Ne}hJ6C*X%lNBCAv;7ATZ>cyzx6qYDLHoNsUr8%U<c19yn%-ptWMn})R+}GbE**vgsFj^Ac z4tcfj3zKBIB-vk+WSu18$!dO8WyM${2{ZQU4z5{ywJ1ykYC0O6(Vzy-B5i?4?o0Lt z!>qvjfwxFPy8^x|n`PNL!6?oXN4$1Pw#o}|+aC(3^*)Xhe+GPJB7{RGJD#*CGDPeAviXtW`G zqh{m#k+VNBGRyOv-g-$pzyF-1!M6#1MEFM<@LhtR?9VHZWR-dx(a5UJip_6XC$4Zi zEKibHEl)H}3SK?4WgIsN9{;;)d%`z3Pe!59O7**=S-*q+TG26UKpP9=YkqS~E{QoL zzTQ-!3DYR=Qg))hP_||q+3VQpl3T6eZx;Qd(!D=P?6Lc?w1#P`hU3EABgz~5dK(2~ z-rgd~R!OqCZ&i4%6(syNH*19C8%SD&da8L29Vm(?d|V!dr}%>6Ev< zSuy+16MVuUCsUmTA5R?Z5FCD{@76Ii#WtfPTr8Zr{&28%6CU}-)qHVQkx%cgih2Bu z;7c7ik@dCx$|nnjkDcus3U!V~0WPx=R(u&pdVEl}8pA&>IMUB<^g*5=!nP(gEl%lE z=V;ajVfL;{}ZB* z{VQuM&{bU*Yk@9xdm2aVIcX^VZMvKhJbJHH{GAT3dVqd@Omf}pA7qSkj>E3=y4!J{ z%W;36qg(!&sw`ofI8L?w?ZyweLPz-J=fOWnw)!>;EIROmA*S=OV2PVNLqbO{)8Y^^?W=b{Kq&M2bNy58vlu25Z|cyI)vq z!|b;Bdc??u))s~Li`LrYxWBa4e)Ijs+SWSvi^1uGwk+KcINeja4U^#!teKbHuF3ES)(jn>+z-CiR+{fZ-RBW5&e!kT z$#BXdeEqpt+kV+_t?w4@`@gnYX~t@k84jz=u9c?EfP_#lu;w$auWtiuj6P17-3Hd< zcCOpN+8&M>?rU6i8(1^0-cJS}cUR#yXg%%{;AUB;9^F$!TgPIL{F}M(;bXSsKoqud z9@?|vl-l>x3!Y_r=Je@NAKK7qqt7>w)Z^&8-zRP_`9ELU+n}ZP-9StEf7Jrle_Szk z@BgdX7rn6nbBtAA_nbw~e*VJmefj#7rpz$pt$q4DJ{yi1q#{{8#J9u^TdCw(y^rxM zPgkOHyrGA9rl>h-NsaDE+3``5>kpAZg=~3QAMVbQ`#4q^Q~)o)crqZzL%q}bQ1^}l z`ch#->f2tRFBOCIzd_gYuh*ZSAT~_r*61U~Ny8ce<``479M*O|)Ed?Rkr0i7CiOd+ zu{=xF{V(v`fPEM=upo6Wc!7bj#@i3*OT{4lZ_uBs&!z+!oV5JC7H5I{DBTJ9^w-8e z8wse15Q9_&H8Db^9PZ~-A>i|qRD+JV%m1qh=z4(b2@#fDQ}XaM$mnkz(HfFf(|^{A z^uzi9!HD)CirsRiivepEV76gV;ei9(rv4U^JorSRE-P4Kp1?n!ss=5Qq1tH{l2JER zYm5<+zbo2LaR-JaLQB|oS%UD(@gOnB@qhZKb)rH@zUqhdrDBl&H|RvQULUEd2aGik z$&HaTpR4O!%c)o+I_Q|zP{->%G4a07JE;Cg!1Z72a70%JjZl=-{S0{vGbLNGx5^Q8 zZXDO;h~Og>PQP8B@9waMs_G@{q@jISCcmapT-OQ2qxVBo79xd|Xu`M=Vac&8EJ;f_ z9yI!4nT?{a%0|(wr-IHc^ga4arIUgk+J-fNjZ?-*-hV5V>|KoJSDs8nE6T7r1voh# z_*m|PnI-PYEJ3{&Eb%lMI-gJQFai1EC-u3_BPbp8r#eD%SO=A4se}{4DFN>~jxlch zw%UG$$0SB1_lI#I+ZB?8V~z)jDUKVL)g<3TA7^5RNTGdL1K2oajF5b`w8}%0j>m^G ztb-|Lz29ohuUopNh3f0R0g+EA{@gi z1|9xAMo2Ed|3Y$g68?Uf#=P|gLlTLn>WDEy@;xGZKZYd3Q{;vRK$iT*Mo8uz^fnLN zYcfmR#{>7F@*5f< zi8TmC+B0@^jTzMCc;HWQ;Qm(H+&=^NJ8m!}5qPSO7$YR#E3$b=#%>JkhB<-R6F3y` z^0{Ps6NX^yLEOh(9{5uX$#0|0 z{S%UJNWL7LJ&ju4gd-4q+}tomNFEirJS3TcQgyj3wJP*m-2~h5G z0%03Y058vyU0Y({c>$d)c_Rb&Z4Ak;YYEBdpd7obaSO8K_aw{QFUyf9ko ziy>cQgyj3xJP*nHI7>3NM{XE*;6~xFLUdAKqskar@>z|LWG)#Uk7HLzVznF(QKpzB z|0`|opDekt!wKUI+z1`c;CxgWBP2f{8hJ?Kgeb%ELO1|i@bWAf@3k4<5}|#>Lmbg`R2d^KcmY@*7qP~`VWTVo`@kbE0{{B2 zn_y{;@mvv70RoN}PW40W>;EoYPt6*+1)ArO1J+i?um&Q9l%$$GRfTp<(%@kQ3vsgo zG@@611DjncSmSqCSF3QHzBn<%EZ1>ws=6_2geAJPPmHp!F|2_|xiz?<6!U~p*2wX4 zYrMc;m4!9l&acx|GO0KP{j|V(O^vD^FxEh%+#1|$d3<#@R@{`P>O zV~xjlug1SzSde-ESp$)BYtU239pQHqSAeVlqdv#Wtuf<;hKx0?{i?oHvgVwE&hG6$ zq^bu@Y&4&bpr_z-dI@=<%No?@c)2yc)L$orH9mexUn)Y+3+R9$^8ktsL_#zQnosBx zalx_68hKoRms{g2v&XsqsQYoQjbim$eWqfKgzjIFMRVA&^D*Wcya@D<^nnbTlQ*Ia ziw*Kd6!18w{g|_^h>Zu3CD0&`3$7`I@30J-ko1KW!YauUJgBKc54l56$x#f_|AyVq z2yE|-n_9krNQ|a!aS?TWW_~ip$odVE>nq(9Xc86(Qox!8SZ)F8AwjR9u4~W2*$5+{ zL*h&_)YPp3jj%*$-@FDVFJo8(kwQu|;pwuxbXmi0<5if@h&VcMz~IEj>h6)1Chxuh zYvfwTISk{RV_O-+8i4ED7boR17lB%W_ z8@bkT4%x6m9GzAFForb{sc8)~#S+7;L0yiQTjRi8CP9h~o~Tpl%VZ~@^Es8O9x&Dj zu@I6tAU47hkq4;D3wVJOR>`g5YcR{A?@Y#Mvj)a`QKI{Ru?8Zc2?Z?~SwlmPT|FhN z5%G~*<4Be_mUrikiuD858u9oaxno#tP*2tjyxba>uBk!=b?4lnFBPt{00CVujlBL- zz^AxcqebKfj&TlrSQ#U4AW|M1`Ir)8M3Y7Ilz@YmTVu?b7lS$Pin~#3ge98RXkLey zV^{-`a%-?!Lput7@9HVwF_O5ku*0i9n(u`MzxXNbZhd(Y~9 zI=4n5;$KY*G_4i5&Dg*yVHv$gk97tjJwvh~9zKs%d{_jSiCkH!4Mux1Ds^vttG>Lv zgr8QZ#I+wm*FV(gJvCjA)l>S`ph<3l{5TdG2$a zxDF2q8FZeR1a@HkY%#&tXUU+d3}ytKSv});}g~ZBQyinEWnz*hxW~$!sz{#|C7gXEe2?Zdkz@Lo7kl=SiGDR!Za?EyD^iv+A-&WY55h z_A&p!5?G8v9oF)~=~=OSa=IRAiGjEXYtTGDkL$2fUe}BZtP++CTk2^tmX53vTn5t_p9gr;l_ERtJg3~L}xZjGCXjfkh^%SF^nKDs9J7#x=T$Txp~ z%a8|VYB?iFH?<9T*AZ((&uHTKc=BTT@Xr(=RMP{Zpjl+ZfWV>B5QCy zHr~5eNGb;Df5YzO0%NSHSR%A<9{YrcoHTn#3+h)(uKYO-X5+XOE%|g=g1Q_J^=J$J z2j8JD6;!>439gDk`rn|xQ6H0VIPoH9mS{BMPL{w#Rx?hyHWx~vg- zCGZdj+<-Sn)l6J0@oJI&)dVw3+=suIVITafI#_2?rqf&eo{HCrH6?mOuJsMF#+WH= z(@B$vT~o#97PC&o=@lbbzg#H4m}#Al3!|Rlg9p)1iKAV0e~*y^zF8vYIUwc?L9{FC zS-<85%_sE%e~j0p(ENxjVFnwX1Dg92YTC~Oc|Hg@$F>qVpkt(@|02>EozNUjV%+DN z{@i5^#)iP*h+2U^W**or5-&?+hFe4PivF8ha_!^%7R3e*LZtkCCB#N(Gb|%gm*ZiL z7*7slJ9(?Sckvyt&r~8d`b0;ZL{Axl#v_;?%6bZ;Wj;gdvIadW$Abm9 z|NQHm*}UPw+4G$SP2X7JtHkzm$w=c{BD8NFGt!->W5mTQ$@NrZQ$Z6fLG(v2=&}Se zs2mRxT!Vk$qP|p^JFNa9eW@6v|4lr6y*}ggl4b^NT7v5+`FX(N7;!NqgCf#jWO2cs zCYnMbascOfL1Q$hfD2x3jk~E(!5SaahhmWaH|Wn1*vJfzjr%ZzB9gsm$oz^mB3}%% zM)VN$3u^@afj0s5*jSG(TCIUa2*KWX`xCVc+Ki9HZ^YLaJq3~YQ1E%IJ#iYMcJ-97 zM&LoCZ;d^=P)R-ICD@|V8Z>zTTZ6oTh-f>Nb!g2R8&J`$@rGoKww}VHV!R)3D%ODP zjl>1*B5!csQMgsX1|!vx53ojjx?&^pMc_qyrMy$|h?4vNG7&))e5f0dngoh1&_ zt_e*r!Inf|zlpTNw4^0dRHoAM-CdHUoA0jQ-DO;?Y(A5u&wbAG<9(ja8oyM9UK`>{=g*Q_%b9hix?H6(m= zI3FU|hyP5!QSv3R{*E?}i(l3r^UP0co8vof66kb}d8EA|;?x)9+1AuY!^wNprBNA@ zqo%K@xJSAw-vqWs?HQcj8MThU+sKD|KA?NPPm@Qp|4uSDqp<)Tk?`-)5u2s<&plop z@j;oC%vTBMe2W~%{iu$Je6b^X-lv+8s@E%M=v13JR^Bl54M})=WJ*@uU(*J=dro-y z`1d-_J9(XlE+yxv&kM*rXK+Ud@^)4N99tGMJU|Qfp*wb*_klXZTdC-Q1TAA+fCA)R zy4Sfje^Te(J0EALx0xWVC7$@!NF=_RK$;yAsPS0vlDcs;2P9l1eR7dptR*MU= ztMgD|4!rlzu$Pfo{EAN4IoF|6?5rqFBvWq|hs@$vK)Kb~C%FM(QuFfsU zN3OIzE|5X|AcA%&F8(#O78f4^i;PqV4%jzo`$Rf5IxY~kC|q}>V|}>SUQ!?TozKf2 zXke0okv#FHUe@Bm&wGgs5Q_Ya5_?z0;$4l;2#Fcdo4dNj3=`gkb zCOabH;$7OHT+@7l1WVICb4hB{vHEs28lhu$dLV%WUokrpakd{Trj%SxET!y3ICH0Pw^Te`8uHgCZ_Zk#6ucJuzyZ8_Rit*f-%*k@(`?ZaWi$}QH z!leHea>aTblLIiaoENBr@Ho!A@PUTUst;D{Km;03d|e-+T+@8Q{wvy!rBkD0qg-tv z#A6`F1@)t7%qU?l_@a=o&`4f_4n!^(g$Cy!=VL#j1QMVMan5zv?pdjQiu&>SqV=q1 z>3!F67gBMQlq)WKR`YW*=DTGkmg0$Dt$RtG$H}NV+Iw7l{_{F88u2{dD{8}g-Fu+X zdLA!&S|Z_UyUI~291)u|0AFC9N3rlh>K5tN*^LWXC=UG zRP`TE$D>C`VwuIdvxZKL3p1lEcz%~R20=Bi^Vz{?7at;sn|Ka12CZ6qu>ZQYznfV4 zqk)iz5f{i6@#~lv7i(2Vf3ua|r3U)IW9M-`&QagM;+gyHSsb)<~fJ$HL5f?nq{XeuJ63^ob+-JyA9ej))HqOBZQU5b(FUQ3v zbsn-RFF=AV_f`M6@b)n-yl!0C0|`W67KA4;2Y4N2B={H^K1%!?^*x`#}W`{&X zVS!@;FCr2|J!sJ1qhf-USL8zuNVqKAbmCkfSh&;0LVwXL=8w{IM!Gx+yXR4ya5KFviSaS5k2*NFWt=Y*z0?sfl1z%n1)A@ zW`hPJ2L2xJ!{JuRFG%&DNxBvejT#cD>463&#k)Aky6{m$Be0}h5Op;C+?X}z;Kt%( zgT}z5`lxX4yzD|~4rmaTzprhsdBfwtOU#S=ZmyR-Vgr-nNb#m#c6r`aHwQFWcjojn zIyN5R-5gB%?_rIxMKCZ=K+G9ko_n3IxR`rD!{?uaG!`*Z><3fjIs+6wWGv%iBi_x4 zeee5TqB8Dt9BE8!xJln*!Qoy;5q<0C5F0efDQk3WBy&2h+^NU=Q3#~A_Av$xxG>4U zNb|uuYwAS}jU3|6m1TGq?J=jg+MH+~TQrFNNDmQ>!DBn4(RhS;1Cwrrya5{YG30q5 z9}PYoA-}?>4V~TaAI!X|<1KOIn&uOBBK)tUnvBLTYoCz&X>IW-Ms5f!@Xy-LNF-~E zu9Q`Kicw7x`QYq3KxxDvEpN9bVfh2E|Cl9TY5%Zn7;yn8_Mn-W%5pCBT$ z;Ry*B&*t)7#!i#raHQo=Jth5?*k}7IS~W=&5%IclrK2%|?>E%B5e@%7oIa-+2$kfh zd0hB;>JJ{wM=35oB_Sd|Zzby3lx{@*;{xuvpg_AGNWd16V1y78)Q?Nfkq>^5=(%7= zW$hoG5!Iq%!seVK(&8I&Fb5=%#s~ogJjJ_`yw0a8M}+#f88b04xMXfg0EPGI^g_Os z+7-+rSA0Nr#hCC38}EpI_u5raQb$g4wBSPq@s#)vYDY98S1@(m(gs-b86h>#QD0Jz zxcI7EiD>Xl6`tbZsJH-$$cJi>_%^eF2qeB!cN3vp(|n@tsO0~(bgF-@h@Shtmk5vh zjWXK-324L|!fTY?X;9Q+Ajt?HU3`cDnRqV6MQ9gxVgI;3cBi`jXu$3sdznP^_~;QA zygucwItgibGNFw=cZ%M{I^rhsaSq;hg@4QWX8qrCKCkwldA#D{i?aT^{_n&ETFD!W zW-+6dvA}Uzmqd1a^cW?WWMHIzC3{Ay#YJ{wz=;gv1pZmvr&egpDtkuHecwxriTfN! zngbfKIr}vWVav1zbyCwG4cHw4FO!HKAD}T})rExT z6sx}-)*9SQWH9>`d<_lekI08Ccs-wxL0OMLoC`!uyj#_CeU`>i@G^+5?)Hca-f#3C zY!l&$-&W<=XG``Y!3PSy>Y_x1uR$N!MJs4L@l*N`#rDR2N97mOsmCTRzOK%T&t&@5 zyZ3u7E9mr?o-3rujr2+doRDW`_hq90kh0GzTO+Yk~x7YDh3Te1y0;@E$yvk5Zoal!S=< zyp@i`@1#?+Ln5N^kdg3j1U&j{NN}E*a6Y_DNSM1lGG-3N*&%`Sh=yq!Tg)RS=x?Zo zgpVHQbKagY@goB9cv8?G36B9UX&(2JxXMS5HN~G&&+v8z2(RhmNHrvUj&NQ?OlX6@ zcExULXu|GK2#ub<|5@-~PGSS=PG5W4FDEex)7bEYnGy1mI_8OSb+ji&;Q##R;m$PT zmy>@sVQzHtHXs8M3SoP0^<{H_K*?0Dk&f@AUlbtO^f`GRxsInM#0 z6Ok`InfCHI&@y88Z>r7ibUYS`R$R~|A`tie9Cf}?2bH6wBQBWz-XYsC4-c6`pt-~a zZIRLQ-%n7;<-_1&`#tgEd&~lVD0}tvc@5`vqd9%h_J5X z#|VwuziB;2Xn5ufCb9b{W1~qdS?xaQ{ufFsJz}FXgL?lL9#s!}WKdqN@p~N^l&nbP z*D@&Qee)559rr$wts#TPe?S3sBX)mQZU1CCo?Qm*8Wk>=vWC#8oMAKT-&gbRkZqXf za|9yYJL>w*td3kQgBEe|N$H$RTwtDiTq47{8uf^am(_p2uTDY)p0ienv*xI{hm#Kpl+=|e;fXdAJ6NGiWO9nUTl8N>-xn^}uda!7hFr?43t8?Ee#imtw= zeiZc>C9ley`(cz26MhAT=-Mb@G(|pmp?&*uS&ouin?3>m6H@tI>1Zqxix!0^*n*e_ zkyuyTFXN(v@1*M9hHauaN^(sdiLR?OA0@SSq?sB-v+G;WQ8M&)dpEHwXZX2TmT0s` zNixn&qI5Lqb0_N5hs`~2>bvS_Pdm=-+NBSp2`*%ZDXQ&(M(f&SocD1AMcz?pV2>!8 zg(vgL8J=~o{(HeELVo-&!XjtI2Q=u@%#^^y4fM& zVmvndcw9MZbcD9{2ww8Ua|NeI#YD`m@WBrfXV?)D6Wf46lxvz#kocC`Or@IsNO%@> z6ufK%YsYzF9s6b0EYIus2V~c`tsYOv6OgYPYBAwRI3MouBn$j+*pdr0mV7IL(S-)L zTl@T5yd*a3i?pu~N1^7q^To19T>J-h(A%x=@PxQR6}|FpK7qHCZd`TVrPU}1O+(!u` z!0Qm_~1o^*2Kmt!K{pP+;qeL`2~sAc0vB zp2R#s^w*H^`GuJ9Q3CHb?;t71#JlYE_PM6{MB6vC9hzfIxS)rC#EjOyh<7AhmDj~% zuk#TV&(Xf;dIB{5$>WEFdxIw)>9NlDy@YQ8keE#JW;Z(AgxSOcZF=Sj7ymGkC=n(o z$VtykzV^b4FHFDu+KV4~^`+;Y-u(P)FK&M3-FD)YmtTBEXE^=xt1muFGC8iTO-8YYxk*3(}_f!1=l5@n^~H^bWL#B=lSms;czA=WP?<+#=3R?1(rE7B8yg5^q55b~$2v z`uU$~G2lehU0v{d3raTbAQ5K+f|JcTc}o=>D_ZhYF_eV!`>X~n;mL$NzR%feLk!t? z^iGwd#|)a?Bkp?Y&N4FJkM_3naBn*g%g((EZ0E_|cJAwK=SkVQ zb%E`?+}qCWz3n_NI}df(IiJkXzu&j?w)3j&+_AuRp6iY0+TM2FlAYYBfP9QI-c=pQ z&v+GQr6T1xFY`IZJ2l>7^mt#^+s^w^dBxPbZ0wv*zw>X5E^D-%_m$L~lTr;U`4j)0 z6PY0O=f$le5L_iEr+>RQ=awKXYjK%3*b$)}x+a-!kt|mY3~M!=c&&4Ouj&WAiRCV{ zKtw=;dEi>QW>c~jqyuIS)wn9@$t&MK(j%rAJ2yl`$U)=QknOZtla zOmMD{qsxnx>i-hg_c>E4;XD#nETDy~&#C;6Lo)YjV6U^mjk%!yadEZLN9ImN@*yrP zL@x8^@?rSo%yKpMHL=UgzYh$IsgG_8=Bq(F=lSVgdzFsN8F5lV$mX{I&C>tr=QqFh z^yca5SGfTA!OF$fgj(>f)BH`m4iX^~?@acO0dHOQ4^?D?)@R$0nOy#9^n9M5z6=&$ z)A2{uj|QY_AhaI~vko3&FR#oPZ!e1fVW)O-($PZu&q{kco8v!o^8uSjEo{?UGYl7T zKq(FsufA&MtW-Ss!_rQfn9>KFchqN_f=o=j5oV&yjf^EBOS)QCI#7!g;9-0xQ02msWa9Tz4Dp?Bo58b}>ERC4}wVkM@f~o(u$Ka~Cc8>*D_5TxFkr#w*e2vi_yGy*|h1Spjz} zTmjNrPCl?IV;&`w=O5cL%X~`fzag%+@1tajxsb`77jHqyhP?U6+^+D7eFU^0)7H*5 zAiqWtLNpzfSp?ubz4oX`~DTxw>depSM&WX<8+yOB(seR zGIt5j(?Pqc7JXElZ9L)JtF&^w;G`qO9FT|eh&cE5;=HV!yjv|G_vjf39qyx3(&Be~ z+@oI;+ptGR<zy-q#(W_q_mr^ZIH*66+~Sow6BpG*GdTo zKld8uWIuwAA#ShPv?!!qICXvjM!Er(^^6rL{A?fj)qnT*TG zDW)PTP=n^v734WTAUG$qxlHWDKCXyW1cH;U%I!@9=L~iGoB7?QKufr=#WsU0x zFSoU;Ins`X3n83yBh-6^QzV$u{f#XyHBU0vs&r0DF+KQoPPPc`n!6sr4S5U9Y?}(_ zHF2J{g;3;d0|h6`n|%hpd&3_lLpp5)CzHa-qMP_LVNa!*70#(j;0?>wRE!DV8_lUnAY>P#Emz`}cB*V#9kEP6R&T_ek zed~u&oLKZ5ywVr4VlRoy~L;iw1s# zex~q<|G4VEXc_kCxY}PgKhewv>htkvpJYsGgIp&6O2z(w&~RLuHd>XRZTrnhI9Z(S z5B*L(oNaD652=q%ShdUi%~|!k1Qh+gU+s?vnaJg^Kk~yeFH7c3ArratLH>5|6IpEC zv9v>H){n)L_Lo9@`gmV0gdm+Z!s;uknF=!D_$}3&lY#SEkckcmE?T66^npw{^x&RV zMb2TF>%`gR(Lf%1$hZ=;yGQRuwP?VN_AMGPJFP=#3CAs!!`iu^aQj>)f7SrCWg;%d zJRJOyflc|w3>SEoGI`Ozu5t>QEbSsELfSS`gUtW;IHwhHQz0jV=QcU-c;I>VeX+3P zQUUTldN=H%T+1gYO(;UjM=|cGzKtoI*OV;Rnkv@_*Raeh>b57t8ca-uJZg|RBhKZ) zBkGYkto@!i_jJe{){b1a&&zH*xe@OiUbZ!35Auj&=WslKq=lt(9uWHs2O>D3pActT zF0z&e?ZoPYw%uZDdjx0jsJT_Uy)DqV!bw}Ao0EzXn7KUUitiKB?s!n2HD8f>uch=JmDpe> zHgYQoxsY@5s<2_-w~5nbdcXfvZ{MG93zRmr-w~kq^HQRTPku|g)fvYLV?c~)} zxyC=SPn8c&Xrsh z1DT_(}nMd>*m~}Gxseys`4ZO*-lZ|CsRf6dtDJRH`^&iRc2i|wJE%{jd6_C1c`I_FmT zJfjg8mGL08J>~mc`Tr+;Rl}C!R=lU?9Ub5&{eQ|BG#X;e7*$ zAhWRX&W)T6+n{?!vJKk8=F^wgHqyKzM^pQ&rTiHEfFtc8?Jc$d$}9kZHBzM)=F2w7 z0Z4LbH|$nSqqJurbxU(M8fjjU6}nQdoh@5W+gyBBI^n6!symdz;kI43CGt|$@!hw+ zLCGmj&oGhIo}J<+6Wxif&=het<>@CV?Rg+2YpO`cK8DcVA+0NIc1S}~4{0cg1Tr1c zxKQXJ%}sZS6=}R(qldJv)YM@ci^d+({O-jV+qj(RA?je{|8Lm_o%+r!D$s*F^_rfO(bQagO5odM|^QkNtPIv zH`&Ww>Eb~tUC8r!Vi z*oZf3yo|OPCjtN^QiRv)O;6-n)Y0{@?KGwL?5+fz_8x6b`hV%wsi!}pIj=gZak>fk z0h-i0t`7l2R?1>4Ag zJRi9!pJ~N>P+G3Nqixm_K(49@+eWLa0OF_V4LDb5!?q%iT~^hNAPuFCfVK2PooT2e zm=V5FO#sAyeT!00>;VvBYnuSsVDjiJ522uR!cKcp0py~ZT+`+rR{+^+VthWTM97TT zt_NvRX|T<0^0ER5Lnhi5BgC2lFVPE|{~CCHL*|?$?GwCX0NHK^c)DAmg9rTeXk4;hqpM92|UGi1gLXA{;G03uVHDMp6~Kh&;T6alfeLetccDQqQGhRg&mX!BlJ zp>`cP+d78Kc2!3gVlS92vjF5= zFdzLRh72SB5;5DTi>72^Xeq-|tg4 zfLOf>*tSRtBY(eDS32vWojz{85If6G%>p;vIIau0W7Y;2@RUWZ{Sg&s-1N@Nhl~tt zJ_b(NC1HfuFpAPxk3+HRb4{}Vv%^$$j0L2vmE@}m;pH5NxO~8kreg=oIcl9&Y3DXZ z4dNa!_GsIOM6(x3+SNTA4}fIbaaHZpsTEe+jC$1>Va{!B=Y)#?h9?3N*iam)()Hd8 z&N{!Y$IC0ax4^G3kQlq(G~mK<+xMd4sk?C2Zgy2X^`YWr#Zwo+hgco(Zm@m-_0;@4Js^em)u*RS@d!^* zyxx>oJiTS7uUM+7c;oNCu#Z%_`Nb~b_na1aK&86o}Buee+P**}A9nrQ`c3rT_sMMx5fFQu{X*)+7 z5z=&++_J)@ZL=&6TSeL>o!Th=mBvahq$PpMAdPH!TvZ;HbQ;FIsm%zbe&gBeP-M)`A zU)zp2ddsDHy?IqZ?CM&aSeNlj|HeW-sGP zDWZdInV+{3cstk%uG&rD8R52EypzU12=zvQg;;aU4!GS;wl?NEZkJW<(ki&!Y{{z5 z4nA`o9=*2lo5D*i84{KqfUthpC~r^AdmaRkOOnLTJKfVqf}7_`AE%XgW919NYj|=} zR2j~@45V9{mtd>lCSmEcE1h4wVOxxl2Dd?v0dGmGRFUFsFg#+s`OII5H*h;CH~a-R z72M7nZZ}59+fJE!#W2Ip5x6;Ku+1MgvbcLXKin=!5?5OMzz*9Q-1LZLxcuB;U4Ovl z4+067xRb97I9k$K_pR@C*#N}Tq7#clT6Se5gkP0ScXT;_)|6u#3epX+Jg|}Gzd1Q& z7*}j#-6iftyrqXSc2>Cafax2g^nktSBzBfb=;;D%yug5$clfV~R;jLNj@6sw>0Yt< z4}P0o&^aSo9hU*?wJkS8D$(mryu?#hBY}{%sW1djANoq^lHffpMH|eR)hg#cJLACt zVRyme4nXpdwF(PM!%Jrq0Z8FIhqr7DEV0J1>vO{t^StU2I%Di~mfwX7LniTr4_276 zLx0!W8ZvuK8dEPcB0_d&pc31N2)Up|=sJ^Hi4cC08mTfbtSQ*Qtz(&Y*+!KA3~ylr zX|8#x0SNn+v8kd@&)DhhRER2oI?ERwR$By2svUGzvVl6- zxQx0c#ctbEs$;P>`06{oM5Fc`9*P$a7A{DfFgLWDXhNT@he`*p$a`+;2fLrV`Iy?= z&&~NnEI>wjzYeNmf2dn*5hIAiIyMKNzWIziDEj8SImHYHHHkYP@`;fp(Kp=W4fS1Y zmA=^_-la0~wnQL-zUctmZ#1|P-02Bm7a&R%%QY-_8v+$TE}B>5c@$TIb)!!0)#fRq zGJ3ZdDi^F|5EZs@#yd&7i8`{L32=^7c3d#i^(*Bmubqg=5v4`fb4i7mb7l}qxux`f?P9BR{gilTLf||lMIBv##?qM^GNGNhcRdR3Y1?X^(x;ydM(7Y1xUo4lOgY;nuPOqucyKaGed$Oe zc5m6~vsU*=T(~Y}B(E6^6?M3PZOhHJ#G{W1ZFBEabZu7_zi0?BWc>c7b|KC%vbd3Y z*w{Mq863EpQpa-!)*fjmC7EiOOrbT#)G%BqC+B;IpmmNefrx?x%E+)ze&WSwX<0;LHiIT){-kuiM zZdx#Rtkj>B(w%za=3Qe2kcGSCTWyL}IAQ8uxwT1Avd{3tQ?gXy>7=TcYsB3(wo3Hg zQA=Kn=OKziXH?2fS zM}Bi=w%nzhSXL#}<0lFbxfo1K-qo9i7#Y9GE*-$jeP80#6@$ za=0v|yl!Hv8COXTTkJHGIaC2;TGF;^JD<5ypBBBt;TdhbntozI`t*_%-q1#;L6tsr z4}H*8TwoP=U7N2|D}8!SinwyykW{wsW?B`VG61h>^Pw}p=*3e~;iPF8;VGO{VnLeQMlW<^%gZ*5d1p9O>4huubi0xRV*;wUa8akuiEW)ptGIAmcAeJdo_4qZ zZY6bOOQ0o)kapJiEAd9+x@*fQI4hpw!f}D(FQ~3~8ozT#TE$c4tR|ttHa|~qs~09T zuiZ6x8&73#xTm~aidKe9-gqig!q+f7774Aer&KDQ0x`r0qpWy3!?{3n_mt?pDo@YL zh4>8|^?`_xrP^TIVSrRz!1Uu{+h%OoRsdEQhsSOiX#mbO3Tor+GrrxN6A(i8GQG*W?8t*hVkh3DPRIv3|QJ z{*xx6lHb-#;-pxQnsLoouwxY{1@XPwd@`y8(loq*fVX3f#J$1m66u_{@X*&tj8nc+ z*kfApwD==otXKMYz+(;947ZA>d&ROro6irGQGZWT_=AEGk44h$2c&d~wi&an(pd*| zn&pad)l&45q8BPI%%~UEO4^k$8Fh44*{2KJSzMOkEt%H{>v{HsJ3p7KZnes^%*;0u zs4bkNYVdT|03+a~%lFGuk6sk&P}k1Z$ywT@su|8lR6-xn*75uqKWhgkzK3eRS&5K( zQ=3tjh0M{nq{DescCoEiJs}kcM=q)*tq)s0j&N)}NG;Ni6PQAfV<-;l@FjgdIrzjj zvI{j;6x%7A zM6gYcH=gSd+qjpvL#~}Mwu)^NVm&Q3|FfNnZFi;Mq=IvI{lW+HW!eMYitW-+N}UQP zY}@AtR#ueK&08eRxhsIMj%HaqZIRt%5*>#n&}9?jSE+=0ieBXBrr1_ej9&Aki*2>q z710aZ90TgS7Qd>_qa`yq?q!DyvXBBY%*19&(Dib0-hQrFX2$FyBHwo2D8 zQUd-=Eh6;`c{85G}NDG69K65RVwj0{c7}mH@{5KEj|N zw3ELmu|Ui&6uB(@EqB9^+rmOv@`Au~rUg$wE2WtueR77*+A6l?qvP$S*mkM)vDC17 z)!_N!jnS!wv9M9Sz$zGOI!k_pQGZpZX2j;Vb05j5-z6KC$i7?2vg)Yk(fdte+i7gT z8>TgCfp?9z%VP7XyfU1@?X0#Pv=dd5>PnsBy7ydSs;={Ii{+%YXq(I}yZ(l;xzdVl z6H+y=xO=9Cs)BXpB6{Y9Jwm8Ha1F$2I)~ou8SofKyl^_R<3-Z)|B~`JF*74G~ zVjF8Dy!C9^#G8N$`Rxs{L7p6tmY#+N=(=&+puxSHq`~(m>0H5 z+R$nc@uO|SbGWR)wvtw>g6v8u;YBzlZY^x=$Barq;GLHq0=`4P)0`1R5y1IYpf%Jy( z-7ouAn$k*Vv1sHA&1(z{QIohh7#-w3XBoT*Aom{7cE~(NDZ9nUx}hrQs%)g3pVBo_ zcv#y#M2RX&&*rnu=lsHwE_a29Bsw04uzXT>(5JWG7~IZXp<};l3qwX6tsxU9N;}0^ zxKpsvS=PPUON2rejVClAZMX3QygrEsrPy~)-M-sIptKlqNP{gB($uO<_^?9ja?#2m zK`EYc>F?j#M^CLKHn7;{aHG{lPwf;zep7B82y3K@r!0@pS~CRF3k7Z{U8Ze9n^VQM zk}cY1O|gw^Ii<}Pw9z(WL+Ls`L=I`R%}j=4r#!tYPbchqsAyY&cb8a?XsOWk1|_tJ zFn^mwZk6=QsV2{*9wAnRQabCt3|neoMcWFtC1QQU>Y{CdZMj&sXuE2472HT%Y{u2P zjJ5m2*tSb{@!Z-{0|a=})JDT>FKoy75Z%m0tLse(9G;quE9H=m2)SWRCavsn!SuPH zR92?8DQSqKYn7Ob<^SkLo&li$Gnz=_atzvNWsJAkFQrh(V_Mg;&{n(!+-~Z$ z#~Pf`1({7%;W$-YKLUh}c;h|2{*M`zc)KaPk{J8IQ&tUukVcJ@vjT1_=koJQ7cd z5bjEO*2Fe&D_*a*Rkoc7p34}nlPo62%$gsitXg1 zwC%JM(m8u9_$s#1NqiZ!FrBqt3U6p*MF^1`JlBQfa9`EfM=(K^q>7|t+V*9x*7RXj zILG>JM%$#-Rg&r&v9O%tIRywnI%dEfcKW2)VZ%0DD1L=|i*tc037?y#$HI-=4%@7M zf~?M|4I5a89Mz)86Mh9=R)h5Eew!B}yyg{3cWXN!iLSZg0;7uS=5r>k!v$>HDmLbY zEhY}zbeN=vt|!@FR`n)hi?&%6wsC!R!CF&YvF(OfQ0_`AwyhQ0?I11MhIA21u?=ZX z728;GvF#HmuvToF)TuL^H;T5IEhyWdZI43O{}8oe+cL3j5}OID4H=n~ST>j+729CD ztg!TdOpUgg1_T@z-;EHx0OA^q4cr)j5x0s`SmGs5MJduQh;^&2{wsjog-yKE##ZSp z%sn62Dz>ea!uUjJ#kQ1C#p+Z6gl90Oq}bUiN+V{lR+Mg#4;Liy5?G6x#FY>ECtOi+eQE4lDTAfkV0VyUtA(WCC!x9-i*DYHf*FHpN(IF@` zGIRVel_;g3LuD7+DxJ^u4JU^iwb8G9--d*zv>~nd34FZ%gKa|F+gbwE33q0y|O$rGC2tYog<0345j*qhpc=iZO9}7qqb>UV4 z1e;C<+bV#tm`$SXV}5`v(?I9}h$n@Wru31FQ=i1WvnqgGSx`Wh7$95C(@KOawT>l^ z!1+i3p{t{}6+o^pC?I6UIPF#v7c5L~23u``QLdtrWIW!}aHa>Q z>{KPct+3AWDdUlJmMfb!P&zsb7g)?jc*(uI3F^MNqyp23a)vZ6!&eC;LUN_tOrrEr2_$}AdQ%HFQZ-Zwq)EfgCv&8wdt9ke z`Y?_`h4xrr_&qK=LHP05(jD1HmqREeITVxl78B{-Rz^LzF$gCSB?7l1)zoa8+g$H1 zp!9T7nO)Ff`I!B*X+EJ-a8_I}Ax$yA<#8j%b_N5mIfGd~2E1}YJ9B?z6lnnB(kinI zPvbr*wr$o!mCiaV1J49$l_2M$n9ZpY$Ah$rZA-iWm zM!F8cjcIMm_*BC%p3o4#Cg`<0NHxMUT%U3y_ilg~PqDSQ|F&0lY|u7?1)}I_xZN}< zmV0)Y2wU{jJTU>BZKxx0!N&8wr_FqLS7|GnV``k|VZ#NxOTi&TtF@A}-oD|XF1o<6 z2sXZkSYB}`vmz|>_MsMf^ z>{?&+X*i@Mw(%y-^&ya=ZRQD4Dgakh$W zQ6a1q+crw!jqvC)(p1$**J0x+VvH)%E~q7g(Ag@U@=J(Y;@OXA5lU@0#@kNS9T)3f zI~SFji9owv+Yzy;NK_fl{7SP?F8gt2&-~8+`{w(9vn?cxlo3L* z{xs!h!I}+G3gHj%h3AQy;dW)$h)m5)-1-%NBqt+m!L)-9d zbmiHrt&%!p(^)J$9|evn2O72($W%BA6kzrD9*(;qF`84z zE0DaF=If(=a|dYy<+{+~37&w5gWm_|yr!mDDm7(hn1!SbcAo^E4hu?HtW&`hrDZBC zAf&`r0w$5HnDoL{cfr@9AFy&MJ~=!YAQB5;&Jq%WO}f0e{xT;4rRZ>o`AbO=AoH$? zCRk8MOcNH(zzD@+fikT6(R9yGfmOl9fF!$IK~1NI=^l$sIUzg_ENrc;b4EO09gw`R z@Q`kqOs1AWO_Qk-j7U%`CyiXu{_rEbp2?{ZmuqrrVk|aVfwrXr#qeV~HaRvLJ3Z0} zDJ#i2*txrMHqI$7AvziehM^rsL^i87sqkrn!`0*{Tr6Eb^$8X{%=6oQlMmNu^Sz?!Osh-pMrc*!lMHIP*R4!&J`!66>i5Ikub7*Pk6M$!xS zZ>@G7d2FKn2OivZ^1cyecL@JfIPSuFrvyo00030|BT-kco?)iJp;A*u}!ygpi$sk&uy#fti_snURT$ zP(_+h*23A8P|U=_`CIp3{C_4cg#X_X$Ohd1=zs0FVN$qPaMhH+e~khf;vLFnk3EZPb+~E1|#BK`UScl5r&PVp{nX#T~S?6Q&H+} zs-dp9hNkCTDeO&K9V?cqrm9;1WzZu3bb57Gebvn|YJ8TNQO@u3=_H@ct)}lpuXSkXMRJ98JVloKkj09>*$VEwkSQ_MRC~EoyZ9tx zVreAlB`eK(Ynt0*ud!f+IH+h*OgxL+H~OwpcSLj{%NN2N&iD7M= zpnQgHjCmm-7rO$PIaISzD9?plqD{VWsJS8)NdTKm&lbDrGRB=~=&WZ>YmqtKUL~1* zYnA{2Uth^Ce`}1uzpa}lEvklqOnb(Rti>&@Cfubc44b?KYh+d({TS5e~~y9^|^*oYUK=|r)cvK0PP>TB}M9Yo4FOa%P=BOe2V=j5@F>$PVN8;w4hjcoR5{lC=r~;0kA7 zF-TbIsuPbqD6mH*@Rzlioet7Y$mUNyQWi%O!X4c=+m~c=i|z%r=$Du|7iu6CF;8bh zg>J~VL)l}Lvz*r|$0;Vi;;i{_k^8YBHz7hP(Y1wdeMjlEtlzmE(O&!$UebG+2&(H9 z)U#5bshJ&=EwTD*Ea>^S=v@d1Ha4aTWG*JDgE!XXBlUcdY zX+8dO$VV;|@!3hO0keXq_DnNjGsP(wHgqqA@0udvQe-1*t0yhhDyGyeKK-^izVNh=PX|VIu09qR*!0%55=PF#4b9xO@za0`6Nrdv@00x`v&HcI;Z|Ol z;cC0PQdxBj;b~oQE$S6->~u?KX~iJMMWaM*SXPN5 zx4iD&rY#LhMjUlceBNyTpb^AV4F1fTJc4cyhNMckwsO1#0f@^Q$m*K-dJ9ZCA>BUa>emf<8S$j6#N`4J;L`@WveM&`#HvY4yXmoO;lWKx? z?+wy)ZaUX=X^ON?=_uGT15_^ykO6+9DO*#6Pyiy1%;|9#ibB z4vDnMeKwrd4c=KbwH&v7)-AdrxGltRMTVAN`<=w)T3m~m-ie&%x;pP_n^+}+#kqrf z4GRpTc}{&a4DwcuVn+fhd?0ElJi3Z&sKOO=p4QZ%L~s*F`MxOJzB(-^$Nc&iD%ER< z5o7nI++W=`eZ*O|&11(%G;dFwdQ6!v4=nKK=f!%4P&Pbl0I{2*^7}-1Pj;>e5(X2y zv!vs7nk;tp2mWknI&{v@xsIGr^KNvZcX9hvPbh^DWB19OH5)xHH9w1?-lUpY!lPU1 z}^u2S+7@#oaP({=Wf z>}M~p@PWi}rtpWurGz~8OCO@jRQ|JG=Z0<0nRHL<;YFW=C@@Y1ro z%_WH+Sq-WW&swIyLcDEN){VKb(ytpi7U*LKP4U!4Fb$8rTg@VuI9W`Vh-nr%n`gl1 z2*#wDxcP;m;K1dH0K?#s_ICX^f{3>XQIm7c$traamg|A5&@bYN@)AqsK*=PFuTg*- z6Fe9a6?ufFXB2Cj*gm@JfWkGChK!p(3)&xJtjTv| zydO&r>bAO%$mgVD+Hvq0g)=rw*(MmG0A=Tg>!kwaVxu0*>vFyBM1H%eL`kgG`=wY= zyiniVtVNM-^i<9J&C4`Gf6|0Moj#2LhAyk#=+cCFIP!wzT<6L02uK5l+Rz>0O}Js& z#v-l!qnmJBR21H}S{eqjDxvbh<7y$MiF)8;a~jNTwA&BSW+vvG268 z-Z>qaJBf?^EeEyod~z0|YnC+`zz_IZJIChGJ49Og7a?!&nYHeLPHM@G&ExVE-`BJ< zi_ezNri+cb#2NK6uS^wRD_i<3mczbbwDp5xc8+0wtN9`P_>ee)Z- z4*kYmM+|6ubKx!;Rs3KT0G%sTJ!pRB?7o(P5(&+@4__|hcDoB7=QbRl`F<~1%~az` zmLEyiF*VE2^Pe>-^)-hCxgYl*M788~~KU z+t#^+jDT_6TV8SURR8!>11rx9z{1nLK0wJ!Dnl<+O_Wv4_8jdX!yGIz8ja@7zG9rzhJBaZjV|684c{ zVaI}4rv8=>xN=MI1l3t=^AodZ_|6ygQqqcomZp2vH+I7}$ZAAjQ22g&K#@J3EZk4) zHsd7~>-7aeA>%^;I_1`5rsdn&gUHJ)@b9kz%gztVeC!bqC)b#XM&(9Z9+}{b$Uxmo z`|Ec6X_p}R)eW~^O;p$U&!U~feJ|Ep6mVeNttv#Ah5il zajjh!ExMmN<@g%X27BH8>S!}N zj|O|Vs#G*_LMFtAvc>tamC1SjB%wbneiO#kqn4?gm%~3wt@pg&z#qObD#2xNq+XlhbQ*fi7TXK}LapP+u$r0kc~y)IRSW)c%|_!NZiFoT zE(7=~{<}ZnI6b$UPV{hjrLD8j#RVKW4dc+oJ<6&*7nQV^#O{8odt2MgOpL7j zY*e(gO}oO!F3w=w{ESL=v=#7Ci&i2c(XWG||GHO+DlCIXYcFH=1JH1$~(_sofWfoKv+8KupuiWJl@GtjT`Bs358@8eeCa$Ag12gLs*b2YvW!{PPS^ zd3&!mH6`Sq+<6V;1#8m#No^q?-alCeIy=!0Pxx9Zp^~FUTITCuHlA5no?JMr&_6PF zdyt(-_@o&_g$k&k=kM>8cef3XM`qcXxlI%TR&Kt_)udLme@|%XhZtOIv1dZgu|nYo zGJ+BvxZ;CiadLK9#fNhzc_vP-+JfdT<)Ht0{eA8ZRPUm!i8h=xBf-2|gAs3u22T6W z;iV&pyEXD)Zn2E^o#Z4V36DuG-X<;C z$mGO;I)}ng&&gCt5xOk)U%H z$r>9UV^^;JNW5-q;%u?jzN@Flg&eaMC)CWO3B(i0ByN3EZ85A6r~Pw08NNY;CAS{p z&t@=-S@se*TzdqIJ&?g*4rkS!$5a`U*GFm3JU(mx<*$|LTO7tz{Kh(*b~T4-+%8}o zb-Eq(&0zj!jA8y8hz(P^ln_U*0XVud8$P^!!;9sce#49Pn|{NK&Cul;&G!H<8MU^U z!SaXtNC6Z+y=6wSo2X+<%5Rrg^uJKbZ3VmPQV99|rzvG`3|XHbzvRE3VN3j;gBJu| z`%ekHcb%iUtZW=}Ja)`4NgKkJn49&OuTti&WhYLaicIf2=9yplEU-Re8lw;d+PC&| zh13hYK2Pq*M`}SsOLEx{OlY&NB#+N~`p3LTNFIo=s8bvfgIs>Iu!GtH&W2VBO z$PAdbU7&^9#;s77e@z}ir4G&!{mbP4Y2>Q^2bX7uX#+hFSzPvv{ZT4aL`lxHr{ z@Co4TG+R7iVnM+4Rdp}!7j{l&Z$o0^x9k?%yI!Mv*9VK+_ycf9`#@{9^N#P3!Ring z!(*d@-PP9$nm;q?M;^nyl|rs8Dz)mkUt0T!k`yRVgz1Em8a9sFN@C;HZOv()v@QNX zc<#p%mk&qXu-qOULFp>P+v*C`{qgCa)tu4c>mO)@FrLgEzHYjDXWC4SGyk!kel-`) zeu5QQUPmh1<^$phU% zF|Fru)IOEDQu!E8?qx&C!QmC#ttH7)^HNP-*?TwHyfkjlYV&@99sO0MCwix1S z{Z!J)!sH!`0R*rDfwQaKqA>nc zMgA#nZbTvg=lQ1`zxc}7HZj>jsRww-Iz^oKv`4t9h(V$QLOPC&PSzVVG>z>w*9s%F z)l8XA7QJKbG@nbP)5w|OC7%l{fE*!VuqMc5yG$oxLmdRK@=jrkS>RW=bjTuPiLC>D z)M_du2NvfoXAOCm_L8(B2e{hCe9^Tc1g(*%APnf17$~0@s8b}EXC&AW8ssFyPfbPC z+FHsy2DDmmI?o+#6?i)&@*v@cI{Hcy1oe(L3>d8`sOdgx-ex$hY?QR~Lel!ZIntxp z#N-Vgsm;(EDsu8TC#X9owf>33j4h_NsUm%;WvEe?Y4(ruNYkP5oy~BdvPJ?MhSRDK zT@?k>6kFzfj%`aDaZ=G$=7L2=I#i4JRGXls`jzxRg?JAhlWz$X@L{HNUdL7>%b)FZF|CBsr8FSA&a1!*N4v81$PuR(C7qOK%wGB0^;KFw zh|G_Y-J)`|fvhBL>!!nI_T7`;GgO_0hfY560?*KOMwjTYK{ExXhJkWrlk)Ak!U z(qwgZn-~s=hn+CH6*B#k42FHHV=CY+Q=Thi^Bsg+ZG7`3?!S+UGM$1BjE;sf7YOM8 zRNnJVyQuUO;>ad?Tz&G1bp|NQ4yRO)obve|2H(*1$wyMjB6~2=!V;~Vb4+YN>z8ai zKX?(Ra%)FEfw^7ZH)Wwk0n^S|H9J;sjX00E`6_!R;uABT5Vp|6%4osmOMEFxSoWHV zvLvdq3l|i-5(`@{s!V#SGS;l<(=Sz^o|<~DaMCZ~-@N}cF83uNEhlhUdNV5%+`+1M zZeLO9AG@355L?x0)VpTg$%moaTwk}~&pvy#BG!hp(B@9en2K#OWW8X^L2zO(xe3aR!OI4I54Vv|yU9UG&Vc#IuptLqE`E z)FpKK*+6(4GYZLE!VK$}BkP3Gm6D?jf#&;Fm` z6{X$o5#9cR?+(k@CPFX#KJj~}Lsn{!>93k`7P$GYKa3lx?LS2rU$M0Be}rgXMEYvQ zwf=@ms2chq^w$*g=&#{~Dr#UH?N1>=^kBm&%Ab81N~nSGno2P0>2P7&&_Hl~?;(Z` zn%5ykc@+M+vH84f`>>D;r9~vFunWaGns~xn#16uG2|a)hlBnyXQwyckuQlUp9~v0i z=NKSL8^`x*g!H&$nDo8Le$%Aly1idqh(}z7#3BwFyuRJJiU@zjr{X_ybG0v)HtOnj zZY*iBs_&?ChLgn2Vwe?&NF?WQ)j(CW4sRV)5| zJKuyicw)TF7X3iXMNf0Cc|Nw6$bK6s@ON0*9H@L}&QC`X6Ti>P+g~x!D$hlZXvz#L zCygPu9+v2tqih0-UN`|R)igOF#6o)2C53-VdZY)rT5#XPB>giKPX9p>YA6r++^$D_dF zGezGKP1Ve5Px;im2L3|qtL7OY^eOLizzU3PQd`Aao!(I0s!h^{U#21Abt7ZZ5O68Z z0dl=!lvw1I{BYOYIAx#pzqDjL%?L2z^72nSmFu76{!H}Cfru5*FvZY@B95 zULKsbh{}~_VwW|Xv5d+2(AYa=D4W?+*2+-tn|@K8g;$_vkwGYM|E;el&`w{J;#71` zT+T4N;~@6dl}~wgm~P6AHGqy(y!G#Bh$OL)Kr&-A>p4QI>_=Y_*hcwXpaOnQ4Uv4y=TpQnnh9 z%92TD9!Pu1^p`&*5^tJ8%xFmUj{+GS9ekIEu*_r$j6Q_$g9=0n>m5UtB$~q_+N>8t<|4UWl_vHr;Yy+ygmh4MWR^%E zYTt3(XV@V((=CiY-gM;TLfJ@DO@BQEGX~|##ln!@J7#nY5&4Wy13Y82nRIWEB|4IX z|K(ig92~>KavCSX;D|#)`cZ0MA62M2y-@mt>f6-c-V{}L-)X@B)d(tNRYl}0UMn7O zT7RkF8}Cd$dS9m_+>KYQd}DDdikaP&_`9WfuH&j9HYAC^^JydY_L$5V(KEyhfqs^w z-sGON%pQ6#CbO}k#XMYxV*@u||Mq&|em^4P8i0#2h>%R+C?-6;jd~;P(%;~M_VZEt zMeVO8{XPsZxp*c$xu3&~5s0}ZP5KJEg*V(;8SzDREFpZdQ_6|D1*bF!y!D|}5P9)U zDk;C!#;vIz=?P`NIwN9c%MN%P=@Va{diOfnLP_58UnL;3d4o4^`G*T(BQWb5vrn*_ zW-|kIX{R`!3tsw#ddRx&5iR3UGty&wz-`^$zZ|NVEBax)_VQ9{0NxQRVc@Q$1Z~4L&emIC`RYtQp8GG`VTg$&+u=oT_6iC>c}6hE z*@;=tt+b86#ZBjb(F1Y`KkJ0Uyl)9nbkhloR>!8`0bc9z+#TFa7X`fi1gjbKBos99 zp1H;Q$@3JPeLnZ;VKO{|p@{E)n@Jf=R+`Ay(Ek==$k&y~=FJRMy4lH_&rtXE7@*;BIEExz6z#ZJJ)_NSIB35#eOrvPj^j)pBK7g1~8O&~jsgUFNL z&i=?qwfLVjshzD5<7Fx1Kc&)osaCI1D{@4}+&bV}7KC#`x7b+x;P48<`0X z6T_w~89D+x7<13g>1eyG6qm`S8YsB^otIIspcf5J5Gu(YVH>-~_}-;w$Ac-(;>~BL z;F*9&(?-4M1PYYl!40L`KyREgjC|4G$P6iMC-KeVb4A&QE%6>+55dhJhPZcu)(p5R z?77}dQ-PJ)<5z%!%eFig^)-(5afRN71FAFnMJ0$+v(iiG^)AXMC7Yf;Aj)N3)UNfc z=vA&_34CYoUZ>}eTeVSHJE$tPjkd(tzs{a$>*la`BeV9r%;hX&`vE$0^!q#1U!cCc zaJ+jPl?hg8ruQD+U)nU+U^hTeJ_c@j(HHH=eYw&%B$JZBNB-HAfA2a;3}R!eU08?c zNyjArut~QS3w%1YkbbF9V+2jRxUiY<4(z#W3&4$Jkt7YggVRKE+`rSQZsrPq;83=KZv@El|Jjz*iBewHpZ|nTxB7eY&Jv^L2WtLhblxNQF*d3oG$5Rm zE96VQ9wT1dt)Rod7t;&$pfm`0M_n|CxwTVt#CcXv(yeLv$BRR@vN=PN8}z!O^q#L(VtQL7;PuhfbB&bI^%v7=!_kbL~Q|d-I6r*hU?`^NJ zjWkb~}-B4J^=F>`C>4$B9Py^kCb)+K*gk^uoMk?l2}#a{!?_#(X}o=&nzX zv=?ZP?qzTF;C7IbZ=s4~c5!){zL;%=7|*TUFpasd+NU)jhlx=E>ykFswfv;_-?|kW zG2$X^pZF@+TqUfxnuK~WU|Pr(x{#|>*)cR#_a1`EMm|wJI@P9Uo*COv*sUyjtZd8$ zFD`t6O+32Ixz=p^eO@l^nk3GAf$CdFusHN)RMrsXCnZ`#RXSPaM9R^5OY=|4Jw_Q) zx%!CU(PJO^2eAi13!+U-S0 zbBJ4!EcF5BiUvrU#&+-XQ7rD5NVHZ?(+S;+VTs&!*hd|}G#s2H`JXSbs~0ss>|ev} zwewL3WD`@iZHR-|>I4SyK`}SlMU)%G>mcYIouA!nv%1}?azNUt~ z%vmUc5HGjT)<_Ml22C=$J5^OVxxeMxQv9_}z`Y9qJ)~RP1)j~XA0&iZ+E|xzbMvzE zavAs^guIv5xv>|$T%S`xQBiWrYT}Y5%9s>%l0a5#!t}u2k@(Xn`2K^?4gVzH zLCx(hAWfpV_sg5(P^-Uj(|$Lsif`L6I;N5+u?y-QBC;EN3f;K|k#<hR{U~dmi_D22__%x+QI|zhbS7i->nx2Zt_;`cWKDY zXRRIlB>v1=^36Gt2Pm(o2Kl@FW0ZZwoW(pM+26XkUjt~q)CBKP=B|CIP0$A0`0pkH zS+@Ux4lQ!v(%P@}$>}{@Twbu>#uFLmE5`%}cEf!M%m%7mTCc1fR4CsBK*$4KcY*g;%taDW2{40fQ^C^4xNrQ-Q8W zX}jx|to0*2eO9?`3C|6?>xaWzjHN_IHP_%%@&{c~4`{RI!e}Nl5 z<0l^<_MQ=LuyVSTQ_vvN0#VDMAtldkIA#%lLzFimSwC+9!bJLPtZK)-`zT5Ki$2R z2&gV#BaM>%pvRwFY6%+!SYOV+pUloRxVE9DNOrREO$=!K-A}~nI&`iU#`+4@+ZRDk z^r6PK_I%!ZwZr_>q)^{H-g^O%A%mh0v*}KfMMH^liu6;+~c7RLq?+Du$grcYQZBkKZbW!yD z!zgEk2F)jqJuOaho6`~f!h1V@-!^Wy08quyLVkK74Ecp6GV1d^&4|(L=L**6aZ!8^ zNWG+WsoC8Z_z8<4UV)=j7rRzACO%JHySKZe6k2Kp3CYsBy~sxOITE0(uA|0Tpm-;R z_(O4-wqdq~y!TPu!=GpIr+leH!?SW3OA$#MD&CX;I5j zO{jF<6DtoAtXtr3cQGb2gnIL#@KrdMH;Zrt0sanNOFXb|XZP969*!uvXux>kE-r0_{=SG->G`ZDQ0m^d4hWd7Ji($mhK zZ^SE#*vGe|5PC!3w?Mp*;YP9t*RFoNjnIlaSU`I0MP!=jojRRkrw-}>S%3j1gTeyX z9X3Pf%U_r=C}9)u&>c5J)6G%q%Rsk{ao08kO>?Ny=x#83j0Qk~_}JF&WH`Hv$i>n8 zQvH@cdJH{H2dgGN_3^E~K-j>k5h3kPJLy9-0f8_NeG7Z(^xk{9vd%pW2$mEbpy0dkOgeSTvtie6$tM`l z2Os$4&$ZI{(|e|+r8Qvh`o|xIH5A8cn5}^Q7bI}kR;9ZfqnGqS-VitF<6i1tn*@UH zZXG=8`ydxbK`cA@(yew?FShbM_Ye&(?1ef#&wr1jQ*T^%f9K!G(;4r^#uDKFyj~<; zMu|E>`j7Q{S0P`32X(s)lJtC`n0QJG9fAHQ=ix;Y2>Oi5|jG=9#FWE{B zF6E9Z;36KS!L(-b6exIK_sd4y>7;OuY_0zKZnPM4o9`6XyT3{4Z>$Nd0A0ZwEz04ja_h^~!-dqK%sX%YF?0$6 z2F%EHiJQ2)9pgtX^sX*4$Ib|#!Srr|qaH4GiCuF%m%)_-%E$F?!uoa;0rwM(se|dn z;YaSTLnORPEr_%_Yxk{7mdp~V>gMOA-;1)IM4vc*9NwS&@L9w5n?OJAGm!_=fuIKq zUfHZlj^fm1D1}P8YL%lqr0UKFMvwV|B3{>`=c?>TXO4FBxt#1d#=IAEBWPPE zsor|2!XnPZ8S%?OpK0`IA6ZjfUAsr=SdH;xSQJlcYQclJahBs*t%K4(-+5IZ>zkz0 z{9V%llzsS&*P6JA&qKd!Gxk=AP$uE`dm?c^YomH47KhnVg?||PD$#wf5T*jqP%5s| z(1jmW1h^U4IQs1eNvGi{bz$rIiR7h!=5F>*Z=A+Bgk6#R4EY&XwH=EqffG>Bp(7;{ zXA|1|pZE}t@+MtCTsP)mdTfciEAR!BXaAkq=Ub+T&YIS;PP5v=WlU^b1J9qbdfeT( z;32i8xo~ex3*wf;s|*8Gzw{3-`v!XPHF@+5)>)W(D)^bA70RO+?AlB$`>Rb`&{LectD818Fk6U}=WF$;J9 zEW3i)bp-?98g*k^vfFyzO)dcdub<0eP2p1XSu%C5>}QccanCJURE{7DYIqP9J#6r% z19C$J)`$onMhh6zbqubapZZ=*78aedbQIBEu;g@dxzUkp!&?xEDaB9lLxo6Vg+<9N z(Kt}#beEQJjgK2Us{aDawiaNfUsw0W$QFzr4hJs+!pF_{pUI)_+7u^7$cwR=pNPFt zQ~5650xH0NLKB8qNep0^iY=|pbPd0*ATr6Wy8uBR+o$Q)(Wc(19}ze$exc(~aOI$! z=4?WDBb4snj-et|HSb6H)Ff^K$ujlnGR#VZ)jK|N%|5-VTqCC&Fq2TfGZ&Op>rJxO zDxfc_&psA5=AMqYW*8S&fp;%I2eI9R`^Y|jA+%E8xMWoOU$owhw z6Dqd_Jgu>i>F?ZwbD8vv@S=UZGQq>q+FvP=hhNRwb!76w(AJqDSKt}$#Ng}Kf#tiS z{;$jS@I_?1O|djk_l}kEObjn68*rt6^BxoQsFY^ggLLK#_Qny1{6%zey3gIhX#iR)8MW}#(g=_WOtPMo^wifp zfOZvo6CW!jA&2URGI+p?d@N+uT{a19gi|(UjmE}N;GQ?Evyel#SVtZwKv-Wfi}tFj zZEoFHKODT;L++s}#Q-D#g@G6NQ&?KoIVji&<#0fr2T9ewos@%*SCRrI^E#Q|MW z{FgTN%i;W}&bJ7hx!EJ}CV`pmy<1uPR6~ZOM;+V4>m}w>$D+u9A-eM)>n%=EJOF~( zjP^#gX2DFFrmK$iwxK9KcLFf?obmQ@JDcga0Xr;N-WQPtj?&_0<#AF0TGYBnQ7kh~ z(}k+It=qdWZfR2xf%B?D(j@NU&b#-^C9auU4@#($u_Z8teHaK~j|#wRZH=I)k`^q? zAirdb8*VXqDAI&5N1VUeSRd>`ch`U1O^k|^I9u9PdLu0hgZG2SBKvpZDA@L)#m&vg zrj(6YMwb{l@E6nq-@A;A^Eq(S>pLbMiQC)pF~F6c4faF4L%CB#yvONV<;9U$z*0B@uw`@uF~iMGbli)Z z_^=Bv-Vv`biI)s`3;=2vx%CqeGlahXGCZR1UA-aY#}eS;XTl88X-r{P6M#b^^O_{+ zW&pcHqYk2cOuBY?0i|+u)`aQ=0U>Tm za@e&%iumV`?-HvOtR%7Gj6d`}1C69fJx#jE+^`&Q(!y>Gh+7@J_v3-HpR-?f5RJNm zon?9Rie`sX{?rjA3YU*LAw#B$&oSO_vpZl~yxP%9pgXz8l;~L$EM`m}j*9>;x zHAs#~6JhS5^c~N};ye9LB%F(1>6^BdGmr;xO<&5osO1r>Lj}ED+{on15cf>uV)f9@ zUV9DhYIma7Zf)zPq2SV~R2A#$7HWV-=qiI%XAnjSK;(M=rKLermLkap{~7SOLtu^g zng2~}5kFfl`vm6k->=t$zVi>;Xe2t@F4^;vZZ`ct>)hr!9%3gazJm@W`AZK+P8erdgEY?NemkR1;D z(bU`nCPc2kBa|Ar{h;2ax-m=n4z<`GrOJ_?FH`fQUzC7do(Yj2we@YgRE<|W!MmC2 z&)F^<;7fGE`L@gaq-P7QRz@A-e?)XK@25zzhTpa)_PT<01JJ@1>zNKxFsI4Q#AH9)56 z?jxKy>?VU^D+v4z=W_&_9R{#H8uV!xA6PG4vOvfGy<{#Q&P8qrGg!d#ZKA*aZJwn- zmv{;V=T^q8LhqatHb=2~_Kr6{{*&5x)y?JMr=yuiDG~oN*%n+KQ@PPutZmR`d)FR~ zgQ`)Of!=Jq!yQ+Ej=$2d)7s{Nq~JRM42&3`2E^Bflxy*`@V{?B2-Z z=6$Dzw4j4ci3>4^cEwi3Nzc+|<>m`v0F)xwt#NiBzq<#mS5+vKfm+o_DsWLK!6 z?{qZK)qgTof11#c+n->b=5}L=$)-Zaw{-F2YkkRZgyrjU-Fjs^=7jXejL-KiI+`-y z_dbZ+h?E$HzHvMd^>IY5ftNc#E=r3T>LrNT4@U`2z3upYX6)iCHMhEFfs4qHq0h|9 z%*V}dQk{uLs~nwHrXADAYUrG#>2Rc3`l{K6Z2g_6V(6#p5@e;Rs{xrunL?d(xp($P zL^$W}nnx^|S~1!%OgaAi#Y+H>KV`9nCj`F#<0&{)Vi-f=$=LLbA8Ll z=LP+@=~v6d##hf_z8^$V4y(cA;nqj`uCf(I(BDR`+f$9je?Ru3y@M_gHy)w#N6o2< zU@PbMI8@QW!ljhbHCZ{)GLWl^ur@Vj4apu_-xX07%WGyoi|PdZ@!G(`ZHNW|0uB zB%Fr~Vu^As_Rb=?cQw}I7b$wXyJ*uYHf zX;{cH3*<=#wi|1^oF1d(njr>3O@m(%w~F@5(4leuBY*RR&hdBEZ0>k)H?A26#%oCP z?AIdt>w@6%+J(5aM#BM%>5b*0Ev;?W{3lnQldh3il*YJ#fo>c2eWo;}Mzdc&gznmB z^jxX~LV*4C=6yq_dE5-E3%O-b0O0y_?tzU@U2_5Io>N2(|K(n>&0>$#diIV|=?UQL zgwcQSondw_`U+ouk1CPeDHUC$x#la2@(lK?S2Gy&`uWM)YoYJDDiNj8y|F^gu=Z2} zuFvWCDsql!t?(gax>&I-0Pg;Nc(b*{d@j5}GXs{Sz#@JwGN6*qLB{@jPmc!qRRk&Y zsPW4=8gVz-?6_XwyFgZ;om2aiAL<0xN?x=r(CskPPm#A|=i_CEW|tGgTdKOcBwv9t zzf*wqlZ0%CsQuRMWtSuJc(L@0n!p>0*DbO)85mPztkIlKjj9U8s>_5M6*q>&hSbXZ zX>Uly?^PF>_a<^Fk)()UKr>^D=xg$$_3YINbff}2`EWqwc_?KP_FD2w4LXMUcR=75 z+KvbMTiENTV(*;k%{cf7h=Ki$$YC;In}RyFFHvFOiqP5eL_H}Gt;YJ9kj zYqZY#kJPqCg2FlJw;KQ9T!w9uo6lcgnaK90Z?-4yN|*V!<0^Lp*C;bo&zCPdZ+$Kt zAM4%W1v>`f**$i>1XTx5%`x)PvIuv_+h-9}%BJqQ{tPPrSeISe(V#zX6hr{a=&v+3 z`916CuU3M`FaeD*fF=C*tH&K4>E5@1x>IP%$Va`YoG)rnj3r9HSY7@-d~=1DO79k> z`4FELWc!Edt9_6WgV*EZhCgTf0VZ$#i+~Qfyrqh6FKy>nXiH@ClZ5-h=2-=>3}A?c zw3uP%q;hvpu-BDfVe}g4Wgns?;%C(34m7wtz{Fr$w0)c4^)U|hkWfaNQ(x}h@~3Vs zC5ru$Yw5-#?cqi3vImyXPOd%WH1fv z!P8?dc8u%Z4{~c=(lHkFxw=bD=v|8i`tx*K_o5&Vb|xY+a{V~;OY z*PrrZjhGu16@vWn*G!~VEyj@)M!c&zD0>{;lHckd(Y+aaq3H3+sCE9^2p96Fr1Lc3 z17%P6qj)A<ubH(T*Mb(esvCraL)^kT<@&dVCba;m(zr2S7*5O6bh@%A?(62j(2!BVSAfpKB6$jt9?gXP)& zx>#<%+(eLK>7r5Iiz!UfIG7$p9@*hiBfzPvoR8mh6Lb3f*xg1 z+eZ#54~4hos(DK<7*pfDsAH(Pm@f^D*+T*Me@EWqBrr!F#>ZxyJ)>a#qja_Wa4Stz zv$YY_jn54nqY`74OGur#yi&Qp&yLXDp@jx)=5r!z^oGaFOl}NL!I6kqF$tA4y`x;V z>aW!?ERlje$(yd0{8*E)neh|se;2sgYzsy!eA*2VKNRPsi+8{xbb(ttk?=slPQ-Qd zr^Y299Qk30hIQ2Z=`98WrBh8ar(U-COXD14T;qpmB$Wm=&vs~x`X8DYqIyy|nbFl^ zllQ^3R8X?T(k^=2*9Z4kQp7m<5IirV!56_ZA$`G(#?Ycm@!XBZ%%aPDb3`LG5?2K= zuip7b<;FKU8v?P8nfXVRMlYcbh*w*s#(kmv=dEh^|xx`-EF( z!IqH)c*HQ^$G;kMs&%;(*T8};a|`1L*PtRc)Jsnponmu>mPQP!bqU%_RPn0OGlZF0`m>pOJuQ*!TDyY zb@bWpNMNh(9DTjF2KBl}-WF8%WkmCj#=BWS1)2@GIS2K6sS}oTB^Af-X(#ja>ON%0 zb~LAGv}~2h=wB=)WJ6(G_(s)zKst4}>6m2ZiUa(UHm+LE9phM700r)E>p*v zZew#K1eI;HbJy5pFNsXY>*%p;V%>Eb8om$v+GH<!CM7}3nljW<-Yn^8L;@ zBq1Xw;VuZe(d-c`6@JP#VnsRlJg)PzBT|!8A zAs0xdPZi&=@;&#+?$d03GgsXG;*dmdgJ+3i*deJ9;kY5b3;qj+VWu4kwY!!emhOyO z>Q`&-1n9ot{-&pMiH$%)OXA@`f+ImFp*9#w6Mfd|$hcffHM(;T#t8{KM)HrXc>TuT z$F7nRQJ9z>m&cu)c;sP&j@QkFiAOW?qnr23;b? z9vVVoTpk*=k8v%D9m->T82BtDvIOsv_~?X_{kKaKC%(j*T%vP{>&nDwEg>{vM?yvd z(g_D8geC~)9KnA^9m)hpf>6SRiM}LcBpl>7EHQ5rr`N=VM8b}jqQ}{>UXODe6DK4b zNl*1HY4Z2}dHv`0Lq~{|5j7|NnRae3xr%6jc;}Z=bxOP$(_W@+h`T)l%q# zrIyal-rb#cXJ(z5E!~hf5~|pmRQe#0sfE9lbHHI27F=$MD z{KGauQ;j4_s)C_-&e^%MyWO^vOzw8>chCEtd)ve^*j&cgd+&GF!N7jcWNZbDA-~Vo zBbK6TwxU_w2uL!|WM^TfWdBEF88G6z7+xebN#$k)kSulzKE3(z{k}yGvd}?HE~B(; zRtp~nZ;YLRfn+Rm07si889{F4uu}NEvGLGV#7<=~wjc$|Wfk!E;S(Q@jDsC$N})6F z=Z4bE{f_Z<+sZ5I=eTeOK(oM=0MB*d;o0G8fakezaCUeH!1G-gO_;@un)2HE1uhH; znGLQ2$qQK?K+o3RZiRv1r7&V*oT!_&tcMqo$ba|UEyA=dffrXLQ3x$&+3@kXy%!F` zK%#0KD9AONYf;q>gr#6z(lW0XztCLyp^omh107Gb7Pocu)Gr|g6OG3)HzX_HktLZy z4YX;Nq-fm8qYBJiJo$>?mM3#2mkc>%H}Tj~b{!_#?B_RMhp2o7FM5HdNT#U-HI-}D zGFAwo-8pfo03E?7i*h#gs3CJut44GU$b9xQ)YUt~^?w7DVxC*hwxUMD%h@w9-*R(k zZM(y*gb}rBx}n1MFfB;~!MJJ#vHyhrY!^8eE+=H-uLAZY$hfw?bjjO}%mPQI8N(fy zByuH*R7d~F#O$KjA_rBu>f=T#T}b%@fF7iABPOS%h@xG2asMTp#p)6}&8;fdJERxH8+SWR~Q(mwDVh+uQzod++51%Wl}b@=PfyJJt}!iXZ=R2ha8 zBW5ithVSA*232(Tw0gbWJzZ@b2iB3PC*L^VD{K(1Pt7Hk?s|%8|Ik3bpx1#oD%2^N zN80x3{#Y?<07N{vY!kd>!NGlPU3E#elqdbJ-@q;c*E#;dfKVlTmqSWqBS{_Zn7D?L zkr2%Zs!p+Dc3ANlk`c2bl45Kkt9xH79Yq*xR_sbY$C|dInqqCHw)**}gQv3qK#8Iq z#wC`Jknpj~-@_Emi*gDmVMrE_aLvy(S>fguiYa3FpeVOj#G`~OJP)yNVW$7)J#P+- zm_lKd6M3Xc(|W~j05Ra{y}~VjuUA$hHq^HjHK*wrWu)kZvg%_Xip&#dj2zbGCd{0N z<$>8Jzy8cZ>#=~v4&S4M{jy~EZB^2wAUC$A8Q1{y^af6?s2RIjdAyDO@Ye=R7KTT} zI?;se_$l@P%ZUTn>jj_@eCb@W0{y(x#dDs7|apY~jN3qbNs(5e)%^+1Bh zd{)vS-9CBF-JWY;6}mSaZOh7bcY!G5*%z2QsEeE{Z~JL0NJi^dIU0h79!)d9ic<5* z(0`Lyh=_}W1Zqd3%S`;1QB60QoU>Q=B80ElPk!F4$h?Lffp6dZcIyfZDT3Sx#{*VN z0V}?B7t4^HfEP8YX3%yu#=)KBdhFMidX58t8Zoj6TD--YN_*1^w;Jf_3pZ}@jODt^ zy-0|di)J+CrnDU{5_QxZGCF&*(H~rZT^p@bpnX_MK;gz?WE*^@2R*^+ljMNiEE$UA zgMLFN1l|?uN!}M{>R!fuf~?rh)Rz=3pzls|br)dMyPDK{X7sm#3jV^YFWy7bv1^GF zm@XY~yNu#B!IaYUPJhus$Hbz9W2qM%A01pnT^K7`-E=(*Yy$b2Y>JT7S$>U~BZA^0zZ!r|H_`eaJCW`6p X-Iu$?T2WaM$pFXTUzYy?00960U2_<; literal 18612 zcmX6?19T=$vyRP;?Tt3c#?Bktwr!gm+qSc@?QCo(Z*1GX`R{k;JY99VdY-B2uBn-> zK?eZ=se%XnZb3k-z7LjfscPcrWMOAZ%*aX4NdKEy(8a>qn3#?IH}P*y1|}v3rr(U5 z#7dIH(iYAp#3IHP&fjB$r~jj96#RcC5CX*i5X=-FRur~Y@|}Dr;i!l|*r>D%=oocPDXQhl@~9R~ z5t6htG%8`u#e6iH<>62xVJne(wSpB)cz{B zgWl+idFvK+X4y+~6<$l7CiKhN1c`?`on#RmzV@wiq-8?)-}N$0L`U6Kd&7N_ zMUly7tgrWwBhQFcMJ$liC)~Fk|5-kv24Td6)s$U&&lQ*@QYyMqCz8l5bCI$HJi@0i ziqm*RGa_sPWMU5?Gly!%$>libY#_J9#q6Nkh6er0%vYDod-LtW9m4GFM^y7)8 z?`_+U{*NvdxAav7q23eB;^lXO^VD}gMk|DV=-i3x-brqzSo&sD)#sNYt}Hd$x4 zoXj31$VrB$GG)ik?W-$RrLt(Dc>F^19hIVS-bpq}nGWVep77Ydxd6qfVe%!aS&Hz9 z6)E?r=e`9Fdu{tWAnuYB`*apKITbqUlk?w&AK;Q&^W5_KIH zJZ*_DTeDtkao6rtV#YRAnZ3!=5InfQbW6C=WTmFQIqCN!q2-;u!?k#XjD3J=rL)pP zb}m|b<}dOn{bgM@PW%!Smxkx(&}u`CXhxoRgS$#}!tSlO!w8v_FrmbGOtD8n07B7> zr|tsd@0!5FHbTgKGUPjHoK;7J`?-g(dmbfA<1v0t9@}%Xc{5m6`4p*Un5hLTM)VMx zdsLLHfXs^_g@{D@Otsgv7os>`WauDbG0>Jil8E4xxCw`~xWWD!(iBu=dhA?i{5?So zo%({#f2pY9iOS|$)Tt)YO;tss zb^4=ZoeG*s^amPBV=+T4*0>Dg)+^*(9vY^!SQ!=C#=lKCQ18Y%MVsHJqZi)4>c^ZQ zx(#}GA5C8E!uG$o3LxgJ!nBB9Kjc_-#?ljp=h6D7ZdiDJALWJ+5k`I*c}Kr>&V4^d zzH|aD!PnR1ga;l!%~O-cp)? zedY23@#2B*>c4m5=XFFNMGn(v0N z{BSD&7Vv3zHY(%ZA!G`VwXx9zc7N_tx?UuBtQfJwj#C9vgDXuA8!0`m_Coo{nxx-r zMT4&f;U9c@2-ZqtY^o5}YZ+5{m+_pE5&EgTy!_>8zLBr4K1vKfISfrS@){YLDAsACW|0fb#=Ls@o|WQ4HseV{6+#F< zaD?}(hv>QPQKqo*M$i3{Dz)Y(a%`c1`>PwDy=w-3UxHZfn+V}J&J{;xexwl(uKJYK zo3HSg#4ZWJ8@p+CUd;hNTYw|aIR!nZJ}VER@iX9HLM*A>%8LWZZ+#Uskqx<3>t>`nt_c#aLvWT)_iVjnlg+XmSlzA>8v+aD0k0gn{J<=6DWIV6*29hrbpS77lQ zax4Xk)6QIWhx?R)U&s7h>c}`#xF+Teg5uD9xSB58qtk{@>*A+JN!CLrE>GtbDT$`v z+|k$|cl1rK!hml8Ns=?e{1bz^wUa@(6Y&5^*v)6t{75NMh`Yzh4~tT_pCe|Rd-Ijg zw-optJbJbbDOa6o>X&}GXK~X_e+T&rGnvXLb#=RgT;3pS)ilNfZ=f+NymxVWjOey3 z2*HbN?y7F_UK2k$?hH5Ci!W_dU!rdyQ|7FyZi{nSPO)qJ(5ni6i2rKk;&TImaNe-vwwE;sonNT z=99(&I}m!%6o2S}eN5x&t7&X{seAN+0q1L`rxV(0_UbLxh)TEn&Tve0wwgg}9Pc*q zA$4*^lHP71wi_^EKoo&?QR?%wdNE#<``9%@v$fh2?Vako#PHWo>B;+F@Zf#sc@kOw^Hg?3qQfH`;W}ue9|9E_uON6N0c#F z6_t;yuM94^)>VE+zAMNkM9sT+pGIplqM2Xns-2w%Tgdru&K2(=KJVlsh^lY6cgx7~ zk7lm#gN@Nvkp!xp6~2fsU!dn5X!}mShbwxkLGRE%4%pvw<^a+iMM--7P4MGtlq+Iy zZJ+6)mKJ(qUslh^*E++%n-aUcvU~kMzQ7byzZAzYKhT0f-@+|cUk@LCUbgpG0ke+*7^ZUa8`)`T?usXpg7wZD-bEU+!Xw7e}W=cLcBbd@jDb z9=&XS;$OS?f5$zh3vUe3y?j%#;)D7x(mdOk;951L(;dGGZd6gNhJSnw?|gYr zNAD^TFNjom9>BD1vdIMN%7Ux_c#9#h6v zY2grt#su3~@hDvaLlTXA@&-Q^_ZWhFKu0DhzqTb*zzj)BQ1Q!@ElT**(?_E6;E3zN zacNH5R4PYw;ejlT4tFIJ$$7M=LscU|fs;}pK2#0PORap)wNiffHcAZ}!p9b4}D7sU* zx&SBLvab_g^3LfecQU(6xtdM)sW$gWKhs3QeRSfx0GMs2y{u%cN@^}*cU`$L0OX<_dPYlGEqbNO>bUBhPR&_(hZm6ju33F{Vq<7+baPifT(>2hMy>L*K)v%T2Pao@@_%noi_+=4 z+D$<5r9f>Q8rTfMAX@+YRX>uX!9nhfDGs`(c=1Zt`V$3GQ7VNY{aWNQb|4d<)W*`9 zrOhyJ>;p}C8Emm~GbYUP;&A>Ksqv48izA)VapvdrN6VdYy3Z1;Qw%+p8m-H5D$VtL z6`qKWY7~P%?ztNfXUKZcDul=cl~9?2{TC94h%fSwwGB*Zl%y@1!gJXV(MQmaGcn-I zFeW|^QVDJvLGyEYO&ar7pxoepy_=y{=lD`oOHx%A22{GBR$TIwoD_xQVUY(iveRBq zNMXy8H0C-D8QJSU_#3eA!~4xHMyG(;*-flV`p`p;0rf0F-5)L9eQ*tbQ2auf15U-My*;y6mATe zoAjDrrGFdkT7Cn?;(}-SXy~H4mIy5j&YhU*0dqT#ITa#sr5!dw^BWxfC$4)|=#JY<3CEne3zKlbQRC zUT8;xew*9>#+;n`S;{u{8`^nK8`^cg;q#5`Z*+ZQEp$H$J~X_@J@D_YK_#jSJrcnB?t-pK_LrOZyTs z4US^uMpihgURDNFFGk_axXqGGFc`8O(mH-S&Tb$(&MiIm?U{NU8&wQhmqS>xUTedL zB}L4!t_kV?XsE~OE!<*fFQmUA^^NZ}yO8*XcZ>JUeX@3vVCbJ?; zJ;lnUDhlaUA8$@8*lX7Hbs$mc1bt-rL{6bIJ?U%g-}2ZReCJVYL7zKER#r|*`{MI4 zT(HP0^lBQpAMgT_!&hZf`Pufj{grC;?rc-}jYuw4+Ml2E5H^(bIvk_#T)~5HFN>t8 zDr_#j+OhG#)Hte)yF88-HzLb$$@(WpCMR*U6%lRMf7iJNj?aij+cQrN9zR5#`?O9| z#FsNSA!R1WO6pukvLQ_*<4x&#?09qu8d~CEByqb>Wt>ioso*WOr#*pzi>|MDRBXuf z&T_8s)p;y(p0V3#b_`KuoG0f`oLBBp8@b5x(T^IlD#>-s<7`GL>b;$wo{!xzwSjk! zuaoscO}dwrj}Y`_+wOvPJ=q92yxX|1N;`*#7&Y9g= z3^Bur5;EWqr(B=4M^><@IJeoiJG&rKxK=U&=ZJaT5YTNK5gD9S#? z%?^qMFniPg#4{RVen!XuQp92YjF$4D=wmc?jcnG$g2YrkU)4DJ4R1AkqE$s-U+bFF zz1WV>RO_1Eog54ECh%Gl-1K%|wbWD=+;ntb#oH}ztXM?P=TqTg_^(Ra@5rAn_Rey> z!lVkqV_rVF%Eoi8&kU8!TM)#28vb|${&)iZcntn{3jTN$UOfwICKGEW6=vJUXTv@^ zKST_CFI%vIk)d*6RechS9=XB=#3?6>wMWTFBk%2lxorpO^Z=>)WCw z_2sA4$zomD9K<*)0-M(tj93ijKo^RkGd0+pHtc~%cw^o$i)sxIx5l+ejC^UAjY`@1 z36|Db%OzOF21gZKZMgP}uxl-u@F~B;K8OzUjjqXH+v2XtslU-bDQgCu>@^V=nNAwg zxt8UYl#)$N$TCBuj!iR`*%w!T@Rc^@YME%tDLcqkvS+(kD(6N{;#a0;aVZb?ukg(@ z{blK`9KV3N7XI0XXUy@pMazd`x;X)Wa>kM(G@*69W`pt}{owA*R%P0(nMJ<3+FO~^ zCOBqVC(SOaCttma=sb?7?j%0BQ?J_s8{p@)K`=?wh4T}4@T@Y6ja2O+i&s!%2mSo+ zkgN0_xZL?@yK1HPU}>t`ZYb7!9@Lf@%S^<+u#t6N*P?M?`q=D)dl&1Z3h!`aX?@nu zcZzua&N4M3JBu%8Iz6v5;LjSWY=s3>Ta}`88XY`He|Qav<$?tOj{Q?oIuKklAO6S| zwFtDk92Bb|_fJ#^o&m>)Ce8#a0M-*6;m+#NdA?=KM9LeFuQ$s+Z|L3X@~|Qe}X-p_jS&xv8~@>sRz_hCz=h+Ua^)3A$boVe`68h(Z7Dtt#hk$7zh-2Fop_|euK{|;+our$uQ^nFhp8MK ziWI-~2#8LOEi;cB)TztOQg1Q%{+ogee5yMjDW5LhRS+4jYU*j zDD}k>X_d}4(2TEX9x_IJa#3TF+)JKw&qY!1yU6*B7@91LJQ;H1;fDJh@UhpYEagfu zqeAIXf{6>FiA=lXxfB>0{x1gHIfDl)ruqQyf~Xr#?p*DouC~V&zy3QDyI@u?!EVZp6lvtHo=Aw*YX!cfD;~mk0OnwK!Y?5xt1diWqiT zgT@g}9U-W-?*DVah zPlwe6ht}kEMbU8-*(IhP|HTkXk`3LD5v_`WDdA2`oiz# zjFz1X_!phg%cC|*v@^uqybd#G5TYzC}zWrgHsEmfBlvDSw(xj`QZ$>k9K z$PoKCTIT!vFc^DpKbjw^2Qp}$^7mcZ54)wqBFnGtXeWV@Tb4aP!@y$tUlP{kkOK_g6<^xv z%Ka?6y(C^fQW7R*? zLL{^9v}R=<)S=qiv>^y#0>OzEROF610x~ds?3_XnDdhbPPOos}iE{CI?@9J&us~p+ zcbYNGbaV9{PmB3%UGx?tmuZpXSOHz9;jmIsWb?%KZ77|fMHCqa2Uz^w03~W_F91V$ z^OFZNzO&gK?wCQah?}#0bl~!fd(aQ3eKmLIS(D0>0xo^?Pg3WTm$$d)jqmkr2y{GO z*dEh?JCguYvp2f)s|ETnI|(n&$#9%5D3mYwBUv0TwG=!Xs$R%@ zQ|+7kLhv%8%8aZ?JFdF1O!kz(t5H$|pe|e7%&!x<5xSTCPiLbD?OcaJB2wgRwH)XL z+;JPc11MZ*JlwQbJgQbhQ42_B@Kt7+mR(S)7EI^ysXs{k4MFUc{fY<3`MUqD99g}e zH`Ga=cu&lI+Mg5CZ9-7p`)p(%u?nO7HN{VktNA`Jl-*1ezhZl@{Bt!BA4s-4o+kDf zKYz!^*;0XFGI76Prta5GC@ywL4y^#|=o+XGeso`=m25)fVU!n&1MoMUFaYGVYY`70 zoPseQ+$$)@Gwd8_Q4tZu2mJOLwEnnY(Uyp$o?hVn8=)(tJ74It%$52*s^8CJJ%M+% z{THL`&cj1(7hH=lH)1)yFqV_X)FT`ZsCYEG6={EspK+=A&^K(>QrBtTek0C(MCxBg zI$s)%!l-@&GWor1oppJYs>>eLhz-&C^5CA(=kT+=9@~Rq(8P{NJbS!bnt}f+n{&fi z>PxutS?s2HrSo-TQu|sT`u1+=Es%;j_Hy3&Hmw9?^ z!4P*x`zz;U`Av1j@4cnDOys>f-c(&(ADk<7yQ-^NDq0HNZrWLWx-Kd@I#gYoU0iFR zq<-n2GHY#ie?(4c^u*Bk_C!i?h{Bo}1DBdzT<)ElYtA)STX2^iUGDFlE6-1l)z{Wm zH?Vx`Za&U*oe7ROH02m(Ue#&GA7_L>+eE$-8U2Y z$5(ZXw#;`MIHSSF+0&^;9}$1j4AK761U-|ge(O`>AD^olZ09%sq2 z>x8S>IAf#dK?>00TX;`ejcXtkWmh>UWi9X*1?A&1p#9zBl&aiI(MnX7$>_=uoUFdz z;DO`V%_O-nj7~=&HIL_!Qcv_xO5DKW{B_aH#Nt-pg6QKa26GSFYEr=8Y9n!fXo=Z3wr zg$hNHZclG*yAHYs!Hc7d*)%_Nu2v!^mlGOQDgI@9iR8Gl^ZK+u!@7&$POAwf5A)Ce2gRmpZy*#bjCc(0}j+JD8u+`+`h2SD{4K#9O3WmagG}wAO#~YknXA5&r(!qz%Ta$h9~n%tnq^3_0&!1 zn{=vk5l`CPJDyDoEbi;7Esi&l+pM@5C>XX9Gf} zjyT6Jbz|wkSa#K1IIyGW>@X4oCuk?aw7cHDDRAUI(wq*?E5L;VkLj@fmY9Ja!HJBx z8u5o!k+*Wv+ioe@2gn?Ayl$*B-P~DRHyrh{mKoUrmoe0dYta!&7uX4AQ7Ty%%1LG% zDPzDL?ldK(p+HG)L?=XJDRB(l&T20%gkGnQC;HqVjKC&xjT^|d#_d)2vEJaW;3cQ$rN`Zz z{|4*;0=>ZaIZDs!(Wap#PD0~GZR7INJ~0dh719!Fp zeh`+lcW3yrz(p)RrS*@91jlNR@A$~PtuPN8?P zBeVqg!S8=k5fN0xDu;{*8jEYWSujTd_Ag z1Id&HNX(>hp++ixIh5*&#o34+TiJ>V@SE3dxu zYJu)m0D@bUAAnsUpQ;ZZJ7np=_TcbNhe99E1>sF)pvp3GNw?<*)!Ho#+6U*3eSfuQ z*jyh>_NlQz0|pUG*UY^aZ07wFQh01A9u^zwshgs&8X|>W(4p9WaZHR!S$29DAxfy) zff7#YS<+713(epr)ET#s$Xpp53e9NA&G zBVUwTjK02-^(tcAWMH*%9b%bclaNgFY%k5VDlL98@pW&aV`nD z9*Q<&h;}204;Q7esG3Cx>8as+S~wg-M+)_TQhiEZ5Ja}e%10B7{p38|H0|AjXjK<` z$BgrX0~hn?O8bI3ZvkakVeUR^OlRGdI8rp%*A2buz(A`(|u@ejti z+Z_%E$A5tv=XB>^PJThi`?i5}IchX9Y2=he=P2tcWNNDp9h_dJisB z(v)(Z{%Yf*RJQ0sn87FL2KaX~5;1|KG@A%sMl*VIx1;M3ZpW-$ujKhTy{qC2iCc8C zacyh_N5S6z;_MJB-lAKejI1 zaJxSbBi$aJCw4!enLH{cv93;UH3r>YmaYm1J6^p_Z$70*pKQI)bh7y>o{@UyuPO#R zJbhGevb!JNEN-f8b5*?6D2pYtz2SwtOAJtPo3EHIYVCB z)e)kpcqZ(z$o+OEL|OGF@?#LX$7F}S%1Yb>V{7lpL)YT@zd?haVF!xqSX*ZtN+y_B z)9l`7(^y+aC||^B%!ssGPu`x9@KnCbCKiAD5mxGTu~=v8WP zz_qH3A;D+)VHm%AMM*7^ADoxLw-HS}6wuK_g|b%>B`I+vFPN8jw61To3eCTQ zGh+vfkx6xT%}_V@w0yG|@bwI=qOa-wo_o;yIVo-nUB3Ogb;{UbT6}t-WW8%mbQn2R_6yyKk7GFR{;7hF?)_n&(c7fV;8E)J6^Au@!(r+q0pLBWq${vCdk0xlV> z7#W%R)5Vjz*^}@waTi$K+e%q>bj6W2bEDxd@_Gq54*Zv)%({7{LM61?2H&xJ;!D;n zmM+6eU&Uf1IRw<}0B=VR2`=3lS>?0w3euOPzJrI8K9l6x+48o(9)ViM3mBc~RZC|^ zNlL-dQm2cFrR9ZzrLxG2Da${HPFWuGh*KZNKi8+h>|+;Z1ijx-ssLP!8Z~LY@-?!B zm_|wueWws6M6g?mu0wc5AJMslnYdNa4BRfB1qQ!7FJ?y3lpBhgow?i@Uf4!lS#(B- zu#wNL5jmA|ZpNXZt&HXe77q}K{Gh=&f6nE&Bf&y41k>XPMf0Kw6)32_+R6%n8Vt<- zO>9!KYy#fHc+wTcZYNg(`E6R+JZKI+8TJqD=}}lz!U=LRDiNgRwjulS>o5w@U+jIA z+RSPz6^U^1@caseOM76TYY=UCgSFw=MU+wi@YTHHDWS82x<6|&NM zGRbuqh^f*t?oO*%cTz{E9C4c{Tr9zv^?ODSqZWx)2-bVvdh5xlr1Q>1q4_IAhuxbaf&q z=PFDKTG4n6EI`tB{@Be9O}l#)$}6A83J6gRfQGHATmvHor1nfK87;K6ew$moT4znO zRsY0pWa+XUp^O%XqN{4P(f<8ySpTi% zU`%@wuZpaB zGW%8KL(1X?4Gu}9ya~7eL=LQhJmv6V3KFh3;CSnvmw5c7uo9!oFe}woUHiy2dFQTb zj+|n`K}XLvF{PpcvdLI05jX;#eL9&~csWBF;8oo|U%V+^an%GrDLzq+#c2P7oBPA3~+14B-KS|=Gw;D;i) zo8Yzs%y+}l&3h2bGsqxMGX_|bQXrQ3n)&idjiRI6M_D&Y_>18!8BR`EzOD31dDSPs zzm-eHyyg?@ii|0adWSA{#_(y~?Tp|Aq`=abd*qxiUQ-Vb_m}OFv^HmxbOZi!o#9UB z+N@oUU`BI?_MSs@Gdxc1VXVd&X5zr+OGj36M@=_#Ax(Adn-c8WFspvI4>pHETB}U7 zW&x4Dl5Oe`0ro+WL7$@xH^=5mEBZ0&DK-G>4)^j2W2sBEld-HrGa3cJL%X)H_2+Tc zQrpjqtX*w14_ODMHufP=qZbbfB#xtv{BFw^9F*hf?SHf|5{xs5lAZMT+;C(7Eo=`n zgM9#o=%)VrauyD{cyQV@ms@pnhEOB)ZKQ<#8!QZ`ipg<*nMVDEu( z9TdN>1w1vyp;QGH#w4+*3w7=}sj?d#9<(cv{Jr_-jU8A{s*ii3!-;*9Hr~x8`9a;z zWSl}RmJSkCDqxQcTnX(Ud}qwDjUx&tZa<(!5Q6>R?Ro|Jj-3^lmk8PlZDwzG7wox; zjQ-Xvge!L~9gg>vb#h*X7R9kn)emPxh>L;z-WG;bwQ+Ztf|MIp+mk8rEkx?9Y|Fw{ zElx|mxQQdk&di$##v~bBEk7iSX%I6L`}$UiD+`IiYMWr{WeoOWfc=UddTN0#z}JqJ zrm?VV26r|06(vXcQJPuDFK|sS9={kOc0mb?6S~AfJnHzaP%}@7I3%+`gGm zx02A!RYd0PlmBiFzugO!J{>3J<~ohQ*9?sSkyUbDY>VU!9m;*BXzbtU-GH21<1SZ( zrS-%YKb`}$Dl`|XigGut3J9Nim*h9)3hP%Eh^EUwXRhJ{dI6wsIK6OFwQlI4zRk5= zxeV3!@Pqk!zpSrxz5|5D_A(Wo_CwNOKl@ljY=yFLXgEk!nU*qn_$E2asAQUAz&4(I*ki7E=M^wLzwi-oNsu%9;@17eR66&)>F}&j{3v9RuzBYr zzELx`diaph2Y{S+&v18lHgr`L@~ASXi2>IF3bzt?02`n7UCZ?Qms!ECQfvI5u{l{2yNwREd8m+b^EE(yq4zqSP7 z#`pWOu-RbUl@zwOFd#p9{hw)BN=TY||u(y$bRUzy71!H}gSTgq! zPU>F#wM6=ycUrvmeRChV5PZ{r<^F!6=MAQ)=F(T+Kkm*_I9)=- zT~7M-J#!Mj5TreuTADQSutqG$L0d^#E|PekyHeXy{r!n(B9v(0Cx8EvH3bt_?00jT zK{#-Md{Hf(|%QT`? zX#t(&YkviQviSH~?` zuuBZ4X!T9pMH>U_lIO_#@(`ZCG5d);9mbd>QG{zy3)o2H=^a~Ty6@tl3P}_f3I}vJ zk{x)K)NyhqyUoO(*m5F&{W)E>b_dfc9*r7|H1C8*nkkUM*>{<<-Q!}J{8ZN9YSv)B zI_i6gm)Q@2K%^tF3RpXGEZ{wBrye=5ZH1z$%T8fw3lo!S4pn&5$u@6%;EcVBPHnkz ztI>BaY8TEVv7L^H)(1)CfpEF*xpk`Bv5l$8+0w9nebd3Yt+1+)nOuZ`9F_--2S2!` zuLW_e33!H1KF^?21L_Z@5<*#;5+xnGyN7oGoG59+8~mh3{>9U#nn~T+)sZEa^z4Qv`p5+K(;twYEEP@UkmhL*Wd#3$Tn+(rR(R@ zgpY&6Myf}yrmp73=l){kk{l4x4fvm zcw}1!0z$mrfq1mVQ3)P4mUxLILoQ6j@3JWx<>JtbP1>n>G7&Yd4p;OZFyX{RXkebq zNa(O#qfc-(F1>so8v*?B5R7?>6uDfNR_%`ro5Yz2NAc0|q~y7kzjG8H+#!!AW_RE~ zCsK{efW;lsFT9ESbs~Q+`R$o3n6W~E7)AaZlpZQLf$OvBMR``y}D^|`@1QVLY2ZWTn7@jEy81;(88Bp zAz#;kWgSwuwXp0hvj_84_@4wE6gPmD9<@6RE5!?~vh1SofiNNZ%6_(2R09%; zs%Vb)8ExU*0uy_>V=HgB_-4l;>$ZJGf@4ai`Q19iRbBdhY+)Qgo{s=J(ZgT)TrQ$)R{w}t*XS2AN~UcH;@Vejp%%xXfF$u`i9 zYEQ3y13Z~oAkHzWS!$csN3?KkW;Gki{HAK-eAdbcytCq4fA7W6H*x;`g6Plk)zt*a zw7CR^qt?hjlq_O$54~}DA!1VI)Ta^`Kw&-V{lbMpFjdSt#vOs1uWTKPz)Zbdfgyrq zGH>l}miSx|x%~!yw~5GeF<$4cB6FSde$4N3qKQo4O{9mBVV!YQeK(UGj#X@N++z;+ zvH70z1nsi6laFPl=R}+PW#a3c*Y3&qjXIfZ-KZi?ZazVJp z4cU!5a4A|a`zlmB=z1O`-%9`mU5Z`Z1m{JJ;~ zw&=g7zDEnB8sE>)=^8pC@ale>x`(tMmTloE>E;WZV|<=+h5Y`D)$DD$VSpjkq8jk~ zb9r@Ji*ecptJU%mAkf7ewM2(YNX2jg>z?wL2DT@)baU38q_zBAiT9zJw-ZHo(f8_q zdEO%Dh1xB?R{`#?+NPH$>I2*tf}9WG74>riNU6uk2A^@~?FMMh?H?CEw(T}ASwH;` zrwk=Oany(M$7x7HKOAqj=&1JI$GJPugN>;8Q+XR27bQbXaJx|PV`O3coY~I?7C!$} z-L%n96wSrY<9GAoH|#v-2~Ls&xXl!T@8mAq_twy-*5|ed8;7@y3S9b8rZ(%8~A|Y=lfCm zpiAUNA_aaAfBLRk&gV$DUX?{X1P($1s;V-?9V{(HhEAaeH4Kh&e@M8`AH5CIk0cKt z0se)N+sV)|pnPU~&|^}O8G=MsB4^NDbDlnU-|_IK%a7aH#py2QbUk&rtuxuzks0^| zl2bL!W1fD#83)@1;*=e$`teZzZqBN?nTGR0R;T^&2<<<`q>3DTfefp=`Z+HRM4mM- z{xIX;n_k=!vR8S~L-(g$d*UCwvs4?pN+tNL{ho%aDJTF+b;rliW+D~bC*=Oi8`S%( zq;HFhv88+cP_9=6O^JNU#+$IWbo5->@=hd&z1tW0y^c(N&jR}E__qLa4xx`zzIn?G z1kB)jn}NCme(OFH&ULz|6(04#^@_00>5*YxIrLb_zI0lzQAtd8i-ER!nm);a4(r{% z-C2;iFc52OW+Tk;G{$KyIRySv6c;bVBtgO z%rSBuYhsWrw8;U})-vfWI`X&Nx?E5s+SoHP)lI>7WjI$8zdRpaotg?>dUn0UB#IHI z?iKYkSGED#Drg9#>Ddo&&s{{HOx$#m46&(=t~ZQSx7WiiFDniE zC;FpT6}R3`LdV*QOnG`ZngoKFo*tj-Tc{&jcWXKw)qSKtR_D%MVnrQ14fFD{Ao}M? z)M-LF4Iv73*ZL%j;aRVM<}e@WNYwJ2TueI00tzu{0K;S_wXc6=@+~Kk1t`7}9LAo~ zRa)i~_t^W_Wti2df|f=oEd<_>3_7CH<9FF{X#`co`qII4(JHnoNrf1e8%*nTM=7&# zF=+%mHN`D9(pBk;_wwvlo#uiF^;$58`{j%6X3#kxj!UjBX`2zID|8_r0YUAhkyv6{ z^lS@8CBvrc>Y+Oxd zO(dpy5)UsS)eZRyC|9+?EioCoQ1es$=DbX~+-BoF%v)4|9yGo#o|9K<*P{QqcU=~R z9ZGTzF6MYK@!Ox(Uc8E6&RFS|5;ht(K(mY@-{bfsfmNQ48rIn-15G~EI(&c9z9 zbP#)auUCOOE{{R-N<*iHIS97(1LrC2t-(X5yCFQboS$i@x2-OY6SXU?K0nw72rcL7 z4`b7Y5q1=^5~50fxBZ(6aurWxmZk*``anfw>lvEWfh9*)t(+gVO#^;R0CB9m@Vyx( z^$|L>Mr*Zzg~XQ+o}%0t)@v)AW47%}33WQI!XFMP<=wLdoaaqCSi$Dph6F=8Sj_*b zRYKC6vN0_YA~ni64W-V~PRvB7-$aiuBrhT>@iikma1fv`QgzMkQVWyd+cLF1l~)bu z$(~g4O&p7Wef`czEhmhzZ6tEPV=|KybIl&GDM2jS3O+fMN2#=$@XLWqya(8nM8&ca zhmMcFF8!S0nx5#P0qcbvhHAZaDUs1@E2bgw`AuoErA_Z-7p)qr4j_yFxGuZKYUNPs zdo*+WVuNzFE`UwRI6=tUA)+U2>vZw1IK(dKv&Ukd+;DsNPyRIcMC8Na`WQH-T0LT@ z??WkPl1a&uEy9cK!M6%vvxajjV=>5i1;vmNMq$4g2Mn2-sd2t+s>c0)ST1w}EMF&E z-^khHWCIAi3I;udERkQA;l11&c`+^&CiM5$v}S$xW*-$A#dv_95s$TE-14)8x8|W# zz*zncbhhW3({4#GL5S+>8nsO=y!`&_&dEP-~Z6Z~+n>`2I_zV`*TD z3dl-mqdME{)kqiNS}fKfK1=^(u7zQfDb}GpOaEZLhHg_K)}cL14|c)VIGh~OJh-=3 zZQhW#0oiSZZUfawS9aAD;fiVALJbUa!Ht-tZZRU%cVgC#q&Ci`G!3QXDok4=HdPRc zKy||ZryaT1!NbVGof0vT;8k#V=nTg(dFH>aGO|^8pvY)7uAl28ra+4SvkRbjA(FH1 zm6`M=FMO$xv;LNmB;{pNQc8q$v;SEp(N;nHWV+WH;y3-r?fHTBl-Prys|gyHWI>F7 z-${_0Wxh$DsTxw>e?}pAchn*|)YFfC0f+E(NO>UuRi_lxh3D7%{{KX!Sf6 zGi;8~`sw0v>(f{-eB4_42Qn-+D&2O(w*F&~$BWmm*&P#GthT#_knBQPN`5^5f|bv? zhgP3v@tZp19vFqhYU|%i6vGZngb2qi(N*wM*bP(dh^gJZ1hI5i)Ka%vvlF1}f;~@1 z=@48w&L~MejT|=iuJ_C<3i#1MYNB_DmV9lRJhZ{`q*Pbh_%aOqxMOz zCALC&k~ahIrG%#7-O@i=;bixAY3#%oo0AJvE_PiRJFUfp#_Wj6h(TK6pqS7Y!JH%b z&!|HhC;$kPm4lgtsjHL`dDny8+)qe)1t++DGtm-3HioL%nmnU?(Kx|sC18p*ks^# z@^0aX^)dc>cIp2C00960cmaG@Yitx%6uvE`@}^KIlxKO`E>)q>2TN_4oxQs|W#{3{ zZ0SnkNLt0MNu{&|QZ?52ry3Ge3_%b>LafwA0*Ls7s4>)ti9uuH;~$R%O-&?GQWccq zIcMk2?sm7G6xN_q-OeABj z3vjjBk{RaqWL6H#E1ULSMA(r@j7`sg6|(j4_rAA28X5*W(3FMlevq3=GY`7P*Kep? z-|&D3?f}pP;3@!5@xbRN2G;<1ss|2F4BiCbX&x9&n81wM%DRT>9vBib5x5#8&tOFW zdbaLX8%zYA12ZPZjk@K?dUPg<{AcH#QcT-y7UgTHEYZ>3Fq;&NG#$d+kgQ@?mSlxB(5BgvqH(i` zDlmW6=qmy@FCAxb$&@3`HXfhDF2hE`d4Ba}h|1S6&kqbzqdj0o& z%r1&8b)hO(1Ki9+FQohdfIdWHBc`XNl%idAru8iDVs(iQv?97`lN(Mju!xe^a-hFg zcp^I4jvE{Ri^;BE+WWr;5e&_r3IoG}fFv8O)Gmddo>4J+9hz;zCP*e_Ix_{b5( zSVdCLcZ^&@$%qgH29>GUaVM$-Ov#KphNPIQ$?Bfh%C93B>$(UAS{>wA_fAYx>@`Ha zUwk%jbP{Z$L_wKJiEBwn^x(N4V2k!e$%T|CB$OLm3vx|Xxb+~#6k+(GD34E)QNk0x za`qkU^j*E{pA2&$3}KZUc|=uY@kt{9(e!LS@mj?1msP`o9kfB~1!*vog!Tt$@yL;Mj^9m-!w_ zQtgj_uE1nrctosIMCBxJx`$Z{Y=5==R0T}r%wm{PKk%b$a+_y1_#-R=`#<$n-xqk% zz8S2sp4{4Z`#$D{#0t{NfDxH*V7-7@Q?hn{BSZ@WCRzx&GNs;#2wKMs|#T^L3A^IuEn-!VYvHh_2?Qb_P zz?31#i*Pbvn<-#rH}7B>vO_RXqiTg6Ph%43C)eY@zSR9D08k@F7J)WzvB#pfWEE}= zpmP^)(&BN;wcdMdh?om98uOak2#<|Ni5&7ey9>}CJbXqyX>@-6Hs&Xe4=G9&W-QNf>n z^~JkrIFTQfapxb6Sp(&Y!j}pk?=F!H9;l7+w(6 zSdQ~WCaZ4-M;Lz?NUC9cR-!(s*neZho5RDm(D>^`KBGdNg&I^ll@) vSUUoUHT0MjSEE@D;yZ*Qmi$M=r&3IBHJ600000004Las9y~n2D}%z7~+)zp9jtZ9tQFD0bctOcF|>kj*dBN~@J!%ufSZAD1G@vy0&W4$fcd!xb~oTQ z;QPSsz)u5r0CxgE0Coj-0X_-!p9202_Sj&lcX916dc-dg*!TurG_W+Lr z|7~F34!i@{8OFN+y8=H0>1Mg=vnBwEYV+`>o`sVz6xXBc=z_2LF5YIJ@EnOULFtK5pq0BcdYC()Co&^gD7yXv@7u<#SO^7%0L9xa^ zgvau;Sq>&b;*5)oRE7&5ZiwXlqatHiS$|QHlAAkaFp{G&jt>ks#q&KKeyp5@{4~Sj zgm^wA#$cj11k>DK@G`OdbJAk1&3@{>jo>!yjZ3WB(SNz$8(2NKJ&Q(}_ctjYa- zNsHve!f@nE3qcv5@+rqLmtKbljh7#mEak-{ON#xlix!45AH}CS$p42(@_$%txqn}- zbXXIp62?wj@7R=Q=xR?=CwC+zj&k6V8(PFi-Q&Z2`@Se7yC~h% z6*oOvuT_Y;_-xK?nSK^O0*T%~qd!zXn}lA6lf1CRsroP1D%YYc<3Cv!t$!hTAu4P5 zf7WSDi`%M?og>Z*Eh?v|^Wy6haT7LgbtzZw1akN}wmNAijA!*-W;%UTlk2>w*d@-a zzgA)wreBbBSEiqrbT_8gNV+@It0moo>E|SUBGaoR-IM8OCEbhZm6Fa>@p^{+m1~jZ zY4DL;e-iN=sZtY=LSmYO8u6N50!p6i_!LwrmH{y^pH{<0I+}P9@;d0sf?s~qU*x{)^`+wfOyu47|P@x|+L1Uc~ z%5n4aF9>TLE(oqG-{8_h^3*T6b_rP*M;F+={e-R~@p{pzj3!NFBBxSq)7#VrRQLMb zs5^k=_R#x zn^=pq8CH-Naeqr+zuAVn>D4W~Q}vkmy#M6s>A$hEve$1xM@RljSDqa$cp8^lk56t? ztxF$MEYHKKUu(5KH_T=y=TlmBh$EM9y^af7TPwJP%8>L6t1iLTgG0U+Dm;b@ ztGpepsVnPBPoz!K`p1>`JR8dIIH^_FQf^=Lm$Kv9C6fb0o2}al?VZl)HbX8=6z^xr zD-}9T7B92~9TUbZ-zcQctNt(8+ y?I#oGb(u3R*>mxRKr>MX|%BKqT{S&hx36KFEq;c;6 delta 2287 zcmVpzXrYm z+ys0R_!jVOV1Hb*JK+Bo_%85wzz@h9L$db(?g`un*bVp| z@W;T%V15UDa2fhZZ1&#)u1bhSd7VvFgf8fc$cY!~E^=StGaNv8u zEx@h7zQAq3?Z7r*Kj2}&CD4B<@KN9mz~#Udz?Hydz*C_g0k{t0F9S1mXT!D5$QpoE z5U&Q-0AGRm^}vn5PB8y*IG=9dcLDAW><#l>!GFII>brq|7x?pmcLVPM{uHY4Is0ijB z=A@XCbbh*V;kvo0vvi4z=Ea-Ld|IdnkBv=CN-o zpR0@GHModLOMM}g+8CmXHznvI5))E*TYrfOQkWlANTtBkG+ku8*`m8|2ST zTVT<}q?pX~hG2r<AH^&ER8PsYUzGP7#VhAiJhHeTPTWDkv^e61 zqpW10cO4|fyVZvq>0wQvTHrllt^17vQ~SMT>hzXnOGju~df6TEQs0l^v5pT)$qy=b zJ!r81fHSX)x_E7D-$hm7M=G!OIU3;}IV+QQ!1XG~1n*Y(0|93}r621l`BZ%)474 z8&+Ri+}gU@c;eJEtbcz$Ca{;TuvL>DX0tb|g~o*&g>j)PiYVWV_6GfjPLEjIpKQ@P zm%3Qx8qa4igU1>JGuHNI+O~Z{Xy0$do@D=ndn$~{jju3^&eN9PeJdNAP{2NjtLxDA z3T6Q2$4wtLKv!B%n zOY3Sn^!YETR>u^mpBdUN%>O9LZrFWS=)IqH+xvcDYwpZAmbpZw2^@da)}wzW+mQ5$ zpkA`C*xe;v|F=HtgqP1{vdhtbX2}7oh3fCqS;@sbq0M!lkTxZU`5e8d9+Z_Ogk2Ye z@$YDuF|b2e6@M5|IJv#TxT{jdhVe1`+DSHd`HTbh9$UjT%`?Q`j-FjSS-)+0p12;t zH;eRHK}&_)yoD@nX!QLx8u_P_p}vc~oYJp8Zae6;ljS9;Szv*$X516a!dT}(+nc>K zF59(jEgOb=v8S|*S@N%S+q9;mWwU*SP&R+D%ihcjt$$h0)tXs{U$))6d`YNH8_4>u zTCW=O;;4=0apAP3dz7K0h2O0()sqAzO+=K5L?v%R~$3CLf=QP|A`x-c{ zS%0khth#5dzqr>HPOmh)k=;*l>!)QGw*1}RcY#&)%F%6_x6ZD#XD@k9-O?DNN!skv z=5x71aASRO9h-M)rI6@0Qax#;mQ6b;u>AS6ZDZUR+qr+b_`^7V5(wS0000000000000>{00000004La z?0xHV9LbR%VV~?~JSX7Jvy92yQl5E5R(faLNn9B^aM0NNbP zKs`O=La}k-2!HTb|0VW)^Jo7>zE6&DgnjGZuPUoMd#2}s*MESdr-R^BSJxveD>ExA zt19bH9z1yPef)ihKR#1a4}OH7YU}(WY6MBtYMTAi!-FK++pCfn>okz`6Q)vc`%Rh#(t*>@a!Iz!~ zIq>`w{Own^%YPfSe~eH&3H}j&@QKaY3QvQE*=Z$FJ;ZC_Gc{E~#%k;0GLBBq67#6~ zg(=UKR*l(gCSk)=TQM4LaWG>ljfSzw+9nR$Vf;Ego_YAP)rn1~9h%ljZ=TQF<~VFe zr%jWzT8;LXrqMc$>gJ@=tP`zm^Dt;0n^tlb#-`mmNq^o1acCGN$r%iqm*ygflP1!* z><`oYU)sb>(dr}@oy43(jj(M_;?}v%2bfT{Icde=X^WVB_$X@D8=Yf@kHgo%jJb$g zr*Uv@5#ItB(RoKY-4^ymR>#Aj-EP&RAPJAnajV`r51WZ259EuQsO8+fvK8Ss7eG?G zacSC}qksPp))VtEX<2BJFg|Zv!0WB%apVvokUFgIIgrd2;A;Z44{M#Hc0GRs2mK53it zpxHSI>PaUCu8%GsI><>5D1$N579u_YGCP1Gj{eAwiP}jV9d(jc+@3LJuMq|SJ`PVn zKGFfIacQFnBj_@=q<9=AK}2#5l80wWa?$>3cJ}1rH1H%k6OlP)>aFwH5X3S=E>?{9 zq<_(RV``oA^B}$~O843>XNSiXnD4cH6q3{6lpUF=!!!4n1%Hg^pV#B1GV;%pD1mlo zi+{3tfQX)FYU%^Tv3OrJi}6(z6q^dsZD^ChprLmb1zB41DGl||W-Bq!GojElApxSM z3C!=eYa3Qmo*`QZ_?)@e+_lby)qh-(+82aRh0oMAswBlrmBd7)-44&8W;&!*YTHE> z70q=(Si}}S5t&83JX9#K{_Bi7H_p@D#)+cUjgiUwNErAGslWl`DX-TImTfc|Q1B=L zxfjGiqhaUzsl5X!3Lh)HZcP5yDWDr1X#f#W%=?&rVsih)+5`46S`NeuKYxxxJ?PVl zU-fIne%N;Hct+9h1=_%-{1ux*>@3LNab*46Ov0q3x6I=R+iw}e4)wcG5RjZ*2VJ!g8 z+UF)RzQ6IU@Oe9pn16XtC%SbWACtEcF(5L*TAA#$J~bU$-s(5M|0Rl_qQubRFRz33 ze4Rw(u{FWR+klU5J`slCn0ci+<6F7Xm2aFh?fYz6)STYMf+lBY@5N^+IM9I_6(X1QCXRCW#YqQqsI_uV`owZgz&wpG*P3lSl0Jj7{d2w^T z8r6_ia}W?ygqYgLsDJD{sq4oG$}qp?R>G-6VNrfig?4d-1$gO}muxrvf`W68fJ()5 z9m|hcUdI$!rIhW-{=Kv@LC^$28NYx;at|dW?q>wx9Nij| z{HW-E?;=t)$OiuvE1!BmSuf*HszKze#)F1+J88M;;C;KQz@#*E>)X{O-IOPK6cv=s zCU;*#cOIxcS_wdH$MeT^ey1h{Jec4B%rT*Z2@W7jCUh{t0mqRW(*erJJuCFg&KUU;4xI zSW7>mT=~Kt96G|eX`IbR2Ddw)b%8y!_6RTv!Cv6loVSj{84c1@h&Q__u!t-A#Z5Bw zlZgpcf1Y5eA7*s?1WOtl{lf19mb8_PVKG2*19P@F1t(*itFx_EaBTeqIJc!R;~i9Y zm1*)nA)7M@KBFBEZY|-WlO84MOMoZoUx#tbL;E;84^NH9u2{HJroX!R4G?W=j^%eL*{KI^>C$f4AjC0YJ$;f^8l{>e*slK&AEH`e+6XQ zB`iXmueDZ_p8U^RZ`u~|N$bMQ!=YMo_NWac(&7DC@Y;D(YXmXev?iD~(N95;`YB*< zJjxdg)A9x=HDVmy~XK(fo|U`Nvs7nZ=Q;Z={iTRR9v zm>)*(@DQ+<7yefyCmkwpHemyzf47yZ!f%h(-xz-SsU-rsA33=HZxOH0{^P`Z5_foA zh#liorvm0t{>xq%!(+^OcuYTng^%+IIg&o=JE-V)sDHzu3A&+MLIh+wz4mxrX5{1j zZvjowGtE}zv2hyNIusn58wZ&v`n!#KN>q3f8|Mq^%{`=23kW)fdoaCY$EZBY(1LZ+ajiHPVIz)a1$m^vPWf2%}zER)9X1?AVN6tLzVjfkJ(O93Jbtkr{% z@qJ`VL3s<2k!vqu_3(l+ec!Lq(F!i!GS*qcK;9#k-sa|}uw9o|ZnuC!?0<~d1MAq> zU2PSL%(IFA9{>M0hNv;Pe^l@U*JjLve~+t|{tN!>C3NoF>j;;7L77O?{2jjk52j&$ z_^2^QjTSuB+WfZf85#%yGJp5qnW_K+M*nA)PO04o0;ahc1pgBy{8tuJ0Ku){faSZ} z{oLgiPz^c`O%Fc9hgzpz$GsXSoramlRJ~~`ol{eqH*-s0&EwxZe=fr-&)Xs%@Tg1v zmbK@Yn8RV7`%HsDX?3PFGiM%mBFwv&mgmge>TJ0@YcJHR{T3Il!Qb|}yYbCsqKw_g z_Ieg$b^?Dp57iInKF}p&)d#JM=|=b(e)`v)%kBQjnf*y{9yR3lF}}kCq1oJY#qr&_ z{B!TTVq|@9ySy-We^8p6t1h}&!Y0%8ZEW;!2-Y}mJ&7>0cd4k4^rdnudP>WSX4ar^ z^T;gEn@^4CUL4=MDE|R(ELxgJ@)etUHB0?bn!1M<>@vt4zT;t`UF={-<`T**0RXfw zE0cJjt;BcXpW#tdHehFAbv+5q2A)>?>x0AEv%S5omxs@Hw+<>B>xT!shx_Xr&$cQDyZa7Wnm^}f z=AXN_eue6IdhK!*?Cr1D)(-&q?$+kc#$j!D>ltz3e~RK%Y^P$keax(*D|Y1!vR;+A(Gm5@C`0j#;wc^ zT#oC7y|*slJ0~sf$wC}L{9u7yXEH)q?wj%QjcI(@SsE5BQYtGh3lVS5c!s-n(#9eZ z4@J?ZZfwa$CAPreNz)oBotS}6IWzYue*$=ZhCg}^x3bBt$f1;Y8v0krtBm)sVq_Cq zt&|n;ikh7;;odp-f!uD3IKZVlF3S1#%#~U>!bQj(D5Y76l!{x?5iYus;gag*%#8Om zejc5;(nw;Lp>!<)CWKfHd25dZ}6(V3=j^D-hC^Acr0kV{mZ>xL3(_K93_Ty~g$tLQ7hYE~1^dnf2Q_-u7GAK{m4zamy`vS1O;_0iB!lMorS(cY0g3{ z))FioQ&j|;W_MIUKL*o4PZbi*vj0T}%z{gjT{WM9zPRkdD)oH-)C+`-hXGS1J`7Ifp+ylwp#{)19dY?Ro%nc~-2-@JW`Tec7y^#jR!w z7u?rzp?f^r;11_3n}tRy`bCy67@ASlmmw(&QB1i3*uyL|#|l@4kbj;ga)!Qo*l5_B z$Lc{0iCX8LOqH!9wb0Xclg1>Ms%gM@wUE2N-jLs+GDMiQk;t>O<;oIURaPHk8`P5UwLLp8b<9vnL5l< zfBBl(Ng?DY>nOHLY~c+L$MUUey5cCY9uto<3+Dq?2wxT|pPw$~e`6skrgyn>W2-7@ ze}tS~q;-8F86(52|D0uF!>hJ4-3HsVG^;GZ=>`UaG>$XaCml>lRlC!f3)|gei?Qu? z1Gk#fa5(=~TLGyUlvWnZBmDOT!gw?pD(YagCnQDTEOBMYJX%?j?2MR)rEPvrMJ%nD zM@uUzqO^=EmnDM3e-U!%3^^dF5NV*^P?iR$!}! zb;ZsVX6*v;O0VQAX-^JFR}r}Zpu3lR%cvbuyt&35292b1a(>vvt%!%6=4;#7uDHW` z>-+-Wo5@>+fekdI2m?gN)tcqdM0P01>OSUiNZNTGVy+##f3M^Vxq7gRFLD!oCfkR; z0Dm=R4R+cr^Hx;1J76+Rnw%{Bw+XNQL9;H&`2lrpHtUTJMkK0st{ehYX+V1q+&g`k zSGEq=q@CTJb>v83lYg?eQ8Al)F3I=s!=(WCMxxo7trWZrCN|P7YVkTL1+>3k=1SA( z`O_UPk{A!ce9f_73VUrF~tD>3}3ka2Qzkogq@%6(cR(-p(}$Oykm9z z;&%eF*9hu%CyrS^!N#b>$fhc2Y%UW4Nv-0!7fxCPkSph9)s@DZ;IeH574H6s$DI>y zcFw9Uf5ri6LRwABaM$f$bi%#4YwaR#d$OnBgS|Bu>&hQB9VaenZ5BV%pk!?BlMZmD z_3tri#Ty+E69$UVP~)e`rfr@E*f0FoVT{!sX+mhQ%44_Py9!*%ns{`WthEPQTI~0G zTLL$0jvhHwU@x32;v@VxQt0J{LEktircHO`e|ED1Ni@fj|sY{mXW^o14G^-E}&`Ra>G{&MEZY;D% ze+ifjtA zo+FVQPk#`q_$nJ|&E6Rfc+_D=s$JTf<#E`990Lwi_C`0+XS`&~)b9SZ5NcmbIwN1} zTr_xXJr$5EmiNn|^7diXvZrINSlH*Pu!=S^x&4(u<3-qj+T;ar|7I$+-VLKDe;LmQ z__N&%wzUxjF$NzB@GqnB6*K`(?K5KxW;9q2uqd83E?S}80mB&%!7F;R6C_e-QLhzc z$QPCpxEx2T((L21X`%WgefOwBmYtstQf0ylzEUv`Ix%CX!wR zF}ru@7-KC&eid3$+cD%VTTY`0f5yYPw6_&@(j_;F>IHr-UZ?vA@prSFMg@d6m2BOu zOd#B>$Cz@u?nV%D3EO6VT0kbcjVaB{lTPsPouf$KZC?~UBA|hTc)H!WfY^bJ4+euc zneJS`2o0h%k6>bbR@)cLSdPbkkrmFy-t)Q4*xwvQyU9u{<%>S@kWXV&Ss#*zGX zx-3CLaLj`Mp6++bBfl2iV}q0rhvhlH1B}wNPb^omb0v_Ro+I|Kw7NQve=wecDE0&I zOhpgK&L|O$sj893eE#ht<_=E4%(@6x)g=~kXy-(E{Tm!bhN(hYlP_Qh?ybec=V!Zf zwGYY6S?=a3)+)hdvIzis6}KqZ6Vdk6mlTl$I`_hf-X=}BR>C#x^o$xG&s4((oHeV_ zYF$Wa#N6VX-)543o9$B`f6V>UgUTdO<;6Mtk0 zLrH*(l9JzRvnP4w6EH)yn?~~#mfz7!jxXtd=p~g z37-ovIv^dM9CC6m248LUwX^7i7Bjhh8>TaF0A>LX?7Dite|a4-QQ_`A(^blL7~26o zsK>1~?3%LNA9({@ehkXLaa^{L*=e2;#kB`6jTIf{=pZnuEh1N%_I-{b+_aAi2JmqK z$(L?6sdBT4KQxJicyfr%y^v{bTc8@--dqz=38^2^KtL zfgvr_k#t(DOh$(ebD|_nX}ySG{Ubbtn-9B)ky4J0ksCo?`wq*sD)&P1BKB5}6xb95 z9n52MZKl_@74ep;#Z4sJdbeKb|-2jCN6uE}`AyN^L z7peI-ZfeRft4)mgbosYmGgsfS0!JmC(5ZpWs`?`v&?9SpJ zhsROp+!kqxSif^=0|%Rb?TT&6k$yy~Tw_EcBKAO(t~$PDyGN)$)Ud*e4Uw1bJJ$AZ|Rzb*xeh~qf9cq?#13h*PbLkxS^8b94D+1u?HwLM^Rr@jZChvgVU6Xq4RYcI== zOI9jbQy$1~*DlMV+oxH|{2Gnj6JE4k+t-n8$;d)vJ~s!OY}d9zTn0oA`hxHbSy_k^ zmmJ!zzg>HgBPn~0S` zHA80>`VgNBw`)@?T3tzxp)ZuOL*QJXae3etMEZ||W|>FE%h+veR#vjqcGha03VOz- z>QW!L(c4-9yB#>_txFUt`JLbdp#M2|L6@5{ar?MIay&GD*Ovh`fnHSS+=(@VKRhbP zhGT!B_8igwsJzOjf~xNv3ZF#ZK$+WXVd7%eYI{cS*=9cJyU!7nMo2#F=eO<|hh|l^ zs~|gG7XPRn!R4qy3?8OgupxWyQ!16Db`?juoFyy>?s857DBpjJW8adF%Mx=)M`r>G z#cWXpiUC!BZZtlOVFu)=Eaz7qCEQv+`*imC7f6VQbH(!f%*v-EvZa}_{mquBh**0H z`WDJ!%lyts|INd(tn6SR)!-*X5E>WmsC0G_2U; zB$tX>P2phD#1O1zo5Yv)wBzI z)hCL0RG+9;kDGWFHTcCcrWpIGB`Vvv!Cz9~`+<5S>?`8ANAQ<5_zI&6x?(_7nCx{zig7gg={+AWdDp-tvmEb<%*Ye-HA?Qy(3R1-@Dt7Gjv!ceYWd(>rZ!!KA z{3`9(;a}D8E1py^6~ix(vaeLOaly}j8Rg#7O@Wduwx}RhK?S_RxIoN&WtCW|Dd2Wail1Wz1EBGIeE}vM*tdo=tr8#r)gvs1m z!gNnCZGUe1q$V20B2dLD5%?~*KR5kS(nhtkSTYGI=zh3K_`dpIPu~_)|10`eSW)yZ z32xG6o%g=lucv)?%k;0OkL6-YSFG^<^}n8e&KLK;8WrAuzxM0t>w;?O zQ2KwjHEeL@^Y_CA4&!{X|c|Kd)3x6eQMXahSo35*E+BFh}+d>)#D03cPaOZH(s#Cw>9UH z)@zNoTul0k+g0n|ZN`_@Ykk*W3enZ~#jU^RzP}~X&#Aj=wL}TK;^x2GgPwH0R(Ac~ z>aNaLh)}_M?tCpXuP^qrs#_}Vd)4ILpoZcm;j2o0UDx$nuh)5hyff$ieXp3{z36+r zN>oysd~YukC#v<5K=;8-!ej1xtL;6`bbU5%XzSH1_9Y1*3Vl~MvrhMse#RNB@cAa-b%D=V7+aYi5_uEfx<8AAE*}97g z6y@Jf*WaqDi^hw8`GEc4{r;=2?FuTv@b0(1xu34?vYD!9iwR#P5Hiukdz0{0318QB zjp3eI(D+(L_KK&6w*7vFyOil~*mm-Kb3a`cXUD6>i{i#B?A#C4r;Wc2ao^nci|Q;b zJZ-zl3KmP6x07gY5i{Dj zx~lj>VWwDr(x?O~+xsMGwB>bGaf@nsG0`Y|sNnmA8f}(cRqHWBQKJy{7NO=g_^J2& zILC73uZ5d7pI586Fywiwk)+pbat-bI{`!-AtWs@$gaq^SD1rYTnViP}O2y*K;ML^e zhe%Xjq{D$S@-Hb@0{yeIF@8rUf_S(Mbq_ZoIxkp%HmcyrJa@P9Og)wQS=Dydv=+rP zE+3oRdlsGB8*`ZP7|pyQeTXF7G^re_xe`a!mlays=PQaFg>(ri93;^1=5+q_W8^zdQQiG2YE&>w~rHn>n14<1By*MKj`^tVlHmKALN?|RBs?^Lf zHlWntps*%DSyW+PkDu<04Ju_*S6EY&o|)js29qf486PWQMIh|hp?dRzH!>j}PnM^@ zNYBzx229I*vpZZ8X_TeTLgY4x#?4(;>3j`;o_Z(yS*k3g%Px-9DH!(WaI@Z2ba*bg-dXxJ$u@g>)BOC}pSO|LMw1Z$x zREuuf$k3dHSkM)_LCIv#LcOxjn+m&O7&hxFnhcII@nSptmR1|?E0w)@cdU>p!K@Fh z3y@T6?2$}wMjR__N;-QM>+R3`fXr{uw*A>xK>L-9apG)VIxgcQg)ss$mRZJsyolrs ziY!D4e7CaAeS9to06Wq-#RvHKK7sru6M{@37|~^P+v6kSWRTE;LHo#aYCll@&X5* zsjT(gNhDsy4u2C_>yNeD{v0q4cqSMtY%&gHV|G`6jzx!95UgZSWFZpK-RcnD?Sk!} z-YH#5J6^DlwSTl^?;Q>8LQd+(XPo?|<$CW}NSx)oTaFPl@5GVa>4m&TBI*>hd(dsX ze@qKn@7yp2?H-gH@BPezrmS`nB%x*Q(yrK>Y}b_+F$u_`lIq$yf&fJ@lozqFL8S~Z zUbd6K1S+;R=TVawD=`y}*%UKkNE~TjLl1JYk(C_gUFVZrD;oy)x`gSkq?3IsCx7mm zEtY!pncM?kx3{U39v=8pbI54y{>W(P$-#MaAyZ69;tK9Zlgt^f6GkR74;AsIEqr~k8pDA zE4a#nf@^;*x2Aj)9Y-;u@!aK_vOjif0qdO|2w>jK!`E>ErbO;?ugOjT)02a70j8wz za_{^=0MoOBaRD~K8bPS;c7LE=72?VGMKS-_25NtR(UNoTBuP3)PesPnIa)^dj#mPh zULGD7U|MYV4q*bAHV%vnFeS;o7N|(d0ham^>XzkqDl-L5Br>lV_CWSGdLBLolyPKB zovK*KL{2Hls1;>ySjL4ic17*T zeuz)VFzY{OnLfmqs=biDdKTc+Z(15*+Y9QiaF=u%_c7w0bZ|qqYBx>^BNh*-c)giK z36POSl0LVhBOpn~((Lu^er3D7Q9}q14>y&T7tJI5_l1qIW`9iWJ56a!+Grs&XqLFV zY#uEyOLj(-aqW7!q#}A!l#r$5vyhlrgvyWuk|IR|&7OMGieKRe53!F6n zI}930=j8kl_kX^Jhn?nY+t{wSLwLry!1w0cg@Fw;qzD67Z1_2I#`m9(!G*&l+Kl;qjaq#9i?L>sb2;e0k3{#Vo*{`1?nz~QPPgmUz8Gg{|xlq^YORVM+Hhf3Tw@74NCTlcxMacphgqC1MA|t-%i- zO9N}UlYaxl(t3^=rCiT4qonmbGfG;|G^3>TTr)~q&o)ETHmkYie5H2h@yl_iXVd5K z)Se*-$MDp;M~0`?eKI_??v>%Gb-xTxt$Sv8YTY-(Q+ug48V0>!8<^V3740CQFBmMR zYZqqUv?P(9y^-CiOP*oV)PqPQO-+#VTU5IXPJblaR@L%#1Nq#{JG4t(fcZ4+`s9wDl+h<-7ys`t|&MW~xR}zCErU zHTe`X+V$(%%hki)*xTGW^n29Ua)0EQ9cOWdUp!Q~(>s+|zx0br!WH~kOmMX-dE7|`%CC| zzpyI5fN!f3Ccb`E(g#--ShTxbMWnY1CGpe3jNm1gj>M+4 zXnuno8vo-_AbP8;`_K(y{_6k`U2W;4jI~uC@4G_ztvs`^BtuNE&O{9=&eE1<7QH)$ zu146lS8BPmW$#ytcHCM5+c+>>&womL9yB_kdu6i^T1n6_vD~TNb|1*3-roBq!p=#h zX`N&VO{X0-Ppxo0i(AcBr;Xl)ymbXoXbF@5YUKRcA`P?4=srC#d!-FY-=}^dg2C|T z3djQ>`9B{BfTdaEZeB-1JX)6i4DbDMw-<-)P&6sFSStJxf}73PVVr>K^M3><3Yckm z1&n=6BgNmM10_3463%m9U#u5@<)VT$F%0?)3NHRkv^d&ncFvEm5(MIiJk%*UnO_^} z$B&SHyVFRbi$?g3UpNwSBb<*xKrf=>p#J z#roD&OSR4s*9|?^e}a$upkj7aIyJ~F@N9^hR}jMLf?(|!R@XO-ol!IRq&{pL! zG|Mb8OD{3?Jlz2=EM%qI)Xxq~or`%=G?}}+jMU}Q5=)=Yk`rN^Z#BS2Nf_5#%_bTm z`95O4CAQi%VqQT-^ndK<(X)z#%X5Su>uxD}euadYICATv>y7XnYeQ{g9#tT7;6@od zyD~FBFDU)1e4ff0NR< zkgMYVrf|{EvwX^__WwIgK~gQrT*gjpToKv-q+|05URaeGg1_s-6J7k+LbC8tFOU^-3E{|=Iav8RYacEN)5&3hosx7gqCOEmsJ z00030|9AmZl07d3Q51#`>tlTHvRI)YB1EE7C`injYb-Of+`St#2Jw|hs3Zy!lVmn5 z06>+H-^q^Jo!Fp?$TdrS0000000000008|r00000004La z?0s2t97&QMA?-*z+|jD9Iabn0G1JrC?3u<|$sVmVf)yDVhlhu|hlfXm z$DiE0ckc)I`v8A@rl#(Fk>($NLDWz1_b>2gy8eEF_fO>S0e<<%>h9z3@4ox)J5>2k z5j=>_qvolpG=s+FAH&$zS39WSOV5KGc>WRo_AA@vjoLp%sGS7=06+M|=4^$hLBs5{ zlBgcyweXpmsvu*vb#WO-r)P(~e z({7z4uY))=jFRLG2F*)z5yVLoXXNZv{8f+bQxPxJPwl}BDn_1{j(&wXg{2t zJ-IjyJc-UkWR977>wGo@vCNQ*72`c_v|gK9=lnc~FAKR2kyC%h|Cnh({_g(8N)AB7 z2QulqKer)B69x{#c0#V%2s)=>+kPqdZ))m4AogE({S_pCoJ76H7!Y3IfarK3Oh`NZ zsfGjHb?Cnvhf=Ze74Ni~(`(^L&}k%QqtQCTcvu?-%ReS8-@|{NG4=1;`2oP@9zny0 zh_v`$Zv+=@$VR9a{WSrq67N*=s4&^)?be1$TlVLjHV*aY9_gY#MWk)RR_iqPUA;_A z{Svy~AKUBTUrtVp(-Nn*D_?JJn(4Z{ z-}l9yL`lD5k@@=N2JQ1(DHp14za{~7f?aCdR+nx=3HjXAE}IzM5q5g@iyejJG&p5P zX6o?F{Z+vq!5 z&^wEQEG_wzhI(kTl^E!mP-vQv08!Hf=J(sR4XY{7kSzp!&RlHnTIa%Qu1M_*!l%M# z>Kav&;-yMrqS9`M=TI{p(kiv>qKb;<6j=XtMx7hy>2Bjh(dx#? zfCwn& zeM~HHjFWC*r=R&$j4#ihZPN3paCII1j|z$mMm*Ra%pJ6gUQMgT$?X68J$M2 zLRjxEFG3pmtmTE#?TfG;oxqfb0s*NB8m(qHV-E1iSLlGCVXhq=Tk~Mw`jb|Inc1~} z>!y(qrb$3dTM*1`(-tbC2CXKzXHggjasBLaMt9GYWqS_3o>#8=JN0g6)<|Gj$n-M= z3&|A5LKuR9PBCg}!t5@~ikm4;q6Z;!XoBuy1;j7=fw&9X=(*=0uoY(fL)3hh_=)^U z=^x{@+G;jot&LuhtgB~X{bie`^|eQTkMMubGi6m%HKJ1d7UIzB(gShFDXp8R&0wB4 z^M~{HsZ!B7Qz$IEKxMybHB=$21;APR+(gFrH@+1JG659&m>&f{b9HX;T@CRi(z zoz|zOL(5zJ=J&ru@l%u-TKwg8u%54zh&;9?_;?%e(ak5q5F9hFG-rG(SGw|ljgzMR zfK7{<)4N#ELr`3i+tpSdJp^hVBP4M^glE| zfBJa)A^r}dW;^*gX}g~hfOB+fO!A|m|GkY!)gT-Em#lp19%a3ZKdAN;f>}i7=%U{-~JVnPJM#^t~0I;$}=f+g3~ulRuht%kko{v z1_|A(ew%RAgrg=Lbycnzl>YBIM}e4fkFvKsijJdrsJ+E*aHpMrbP$qn@@;BTcoF(0 zXep$)cNZ-=HpGi?BKMYU&hDB=LGz`t#`Zx*c7D6zf zXSa74A8t^LX$p2u4H5#`F4_TbPF&Q0TNJ~Fu70j&${p|wYVQ3&<| z$L73s9L{Kvrb4_I*-e2(T+uIXlA#}Fbo>NM8XNt>6D;+Ue+gB8ejl);t!xa70g@Y- zv%M)e8RJ}?ZMA}9>nFguErl8Hpt`F}lm8LfoI&s@?Rao&2^XF8C`n%eJW2m5jAI_! z$Ju#!YCLwu!kr?|_gmASoc~A3uYyJgC&TG#NKX9AnfnYb=j<|DvT*JT+IiC zCkg;c?h$PB7*fxF7V9F%4GPs0zYYC;Moj!RfS~$Gt)loGQQ}4Dk|!$Mp}6W9+mF>edEP2k8=!2}-@e1JW@0C;Q3pmF4oT9@YCOyg5O%eyqHawTZ6*+u((vMbb;!d;4me8-2 zXrsX?hkfUN1`M&{3khzocru=Tk&wLQoX0=#N5A3Rv)TF5z{5KIg0@ahX6_%H!A+{2 z0Kkd5^)SXvsaGZV*V3?E1j(7x?BVL34&4FJdCrY`z-tWXdbQK`0J~%Q#(FWr1qb;l z02P*NNISu7`Xl{6dKaxZckjM{Y`cU-i1W49YSNQ`|5@vG+af+`U6^?|R7=htw1GrA zygv(GId5u>AcmXP1k)z^DF{+O1?-J{gXtCE8V&Br;vx6Hf6j6zmq1J|fv~qnOfG>K z&m|C$>@qso(KN(`CGcu^)uZm#4nh&;htXR+1nlL7{}stehsv8x*nsG5<*M-8qxCn2 zpMGk8iGc1$4(|UO#Ot&FIPspu9bOk=$N1E#fO(MrvKPki7;_#T(~n@`<9tGnq>uUz zD*7Gj-*9MxZs?W}0hvy(Jzkd?`FQ_ZKvVQgvsHOyoJO_|1&8LwK_-g+Zlj(M6`sV# z`GR_L52@4wf{x)HOf+!%HSMM&%zOIt$#q+Qlmm^BDd=b-BKid|Q?o9njtAl2DiI#b zr13jJ`E@DY+>fCvL?^&n*Y0NGMd-a=&L+DlkHyr4|q_iJ>tf{V9|b=EMD z_dfC2y=+U{eqG{xHw!34E0J?xJr=t=t3nZGHu3+&|NoUCssb(*T)edzbMN2bPNn~U zj6Zw3ocs1F!mVA<64Eq(gYW;HX_z0*XUtKf1sAk7zwK0p210<$-~BhHDu95||B0nj z9QT2MX>JC=|3C@(icL#tlz+?lUa`rPZ0z%$#}Di7=sFTAnj= ztFz_uti36(_FLSf21nZK?kYEziNbRq`{r4U*$Mo$JJc(jUqF|PRUfo2rW@faIN)D* zzO?%%XZFXzdDM_=#rO`_f@X8m6~}ky%g?>@?vVAp?efChL1}KTy69pFo6N(1x3Po2 zAz0&p^f%PMZ$2}kRB_<$qWpWjifCyb$yaRZ)hzYL zY3d$cuPB#cCmvUa!V+)1OU*!tW4s8MiAeHe~Ndpdmw~|6}^lsVHOL^6QezOFEf%R6ZXY3 zF05w7`L$gY&8mB7hKLd)m)Sga`AKHg-R-^2t@ZuG+UCYi<>2Z5`r#%GTzCxr%5%%5 z^4xrBer2h=y0kn~T3RiwmX`2RT9_+Q`NYE!a+-D(JpIBPU_q0I)m_wo@Y|<5)q~C5 zox_9m?LC{#=35a;>{o`4x8-f_^evAXiqMG8)-O!iu($ghcv%1X;IQ^|Z*S|x;j`VX zgUZJG;lb|V{`$t#t;)gfzJr!_&H0)6XYQ?Ep*o)KxLgH$`|Gv!0|36ewYjr#Sliut zN?f?2ILF#)nI|DEN3{rl$A_NNiGK~N$qiG9;?e7)nR9P{_qXfSgTvjY2YXKs4%asK z@wU59Llz!N0a!nA(#N?TwUK@MPq&2x1`*N0t&N#bvO=ZjLNR)stYFG$j~~S?%3fT+ zh(l4K&>;D0FAQFqXENk%hp>K%Ao~;_oye%}Jv9(cp?LtoNw5BYFgZ$LB3>w%to^X- zQYS>?`9A*U<{t8&@GOmN5Z?TF&)$@>unbwT{m4aR>HTnEg{*b>+?`^s>|%OKT%2E6 zEGThK1{e;5={-k1g$iUng)V^kiVBtVAE2NvYidu?B^Ogr^zw31(UP9h$M!~dfh9qJ zrV$-h$Xs@L3n_?ygTZ!CKf{ewaNgQZn(6pRL5%eF@{{ zMfbmH>q^?!{K|W&eGS%_EEBE>DUqzZRU|Ufl1Pl(P>NW8XUaD1jHGw$r7`ZEhD-O3 z)r$njM7cE7#BIEmSzQ_qxGOG5Qrix`!HvndZn=S5Z@sYhW&?cZq{Tg1h(m}UEU=yI z*nPL$H!~-^$TYs}EDZ}5DU}tMg@`w26~iSuX=7dS6h)u8u_YUo*aCwmO>3ldG7EId znYqtg?w{d*hc3abY;sF&C?%eT{uT0$;yo+{xs)uD74YtvoiO31IQN0vZi_g;Z8|Q> zIql4qS~gCLgcOiZrow(9SVwa(GEdeHkSm)z7i%CCj znhw%ShAbd1+e7?Z(UZBqqr}&o^#EI+g2vk>XI{B~T5`Zqsk6XAut%6hn zTw>~*BZK6C(RF3ua45sHp%4g4GYiCX+#3@gPj6U@JxN|cLQQpKNSvE@RbK`Oheq$0 z6+t`}G+yiFUaufMK1U7`?esJp*Pb6?&c>+@tO#}mxY@!@O3uBmE1802MKpNUB3Vl0h zUu3{6xFp#f@)_uh(nythzJKZk0av9i4@fO?L8UGgr&jV&C7$b_cz`@3pXAWiCdPQ~ z-nBZz5G9{3t>_GPnv7Pp!$++1JBP3`e)gIkxgY!(`+=oeYOU}#2F zUxuVCL^0(CU=Op<94lNE%J_Mj$Qk=?^_6Fqq+!$!l&Ql!@wcj(ofJZjvW{Y_#1`K0a4g@drb~$u z>oM^tvvA&Hg>X`#^7-jvJ{F>4dY4;&GPbIc_9Nu2}Vh zrCDVO-ZU^6q;Z_VKJH*js@k2-T-fd&Ta0bD8@Sb+hQs-{+6qX;ptQ1J9^k((5yqp* zP*De?Js~LyXNfCI=E2I6WM{-YEN%01Dq?BHJXl&$5v65RxhxSJj*vrV$N@=zg-8R< zo_gJiU*ZQ3u@52eEhsy6nf|T)V#hgEumW2(tSfe|Fl!fxS9&F1NqcfYx{AmR0NuUh zTSo1O;>|VgFlZ#5lk>wSt~)&JG+)`qcEugmTjv+}-b~&q3~ZnwMHnDDuGTDvCbC08 zR`)TFL(0 zJ94{Ofh3x)0_|3R@b&8M&|aTKUa00`eKA(Wretu3SB2k%kKY& zn7U-CZWdP%O|uH&0IgI`Ph%{);VMFV)*(2;h2pru_{LR#IJj*UVnS36sD<8mOMxwV zkqRy%7JDwE3mho9B;xE)k#&MTnV}&?Haz{2$t9o~?9Hau2w$81R5$FOgEOMN>L%Hg zMGq>RW6X1|RPJH2H~sVigovfa#4E4;>!1cHV((F>J#D$a8pZWalz7W+|ID00v4@R1 z$tg6Ug@X=%PZwozS0YBIXAn5BtH^FI>k<;l@$?6wim$Rm*6f|()kMllJR^Wf3};!wl<=FAjaTB0sdt)zJeyeseNXQ!Hfp$ z0T#v6#ziZ%J774&A$Ub^c7j9-E$X$R4Ee%R0+(}URhoTVHciwz{Fy*wBuiRx*ZIQ1 zrOe~=<5pZxk4vEml~=6@i#Dlf%0$xhAZGUt9b>G8$ge_6YCDF!Wy@(4!FV{A_O`-K zy5vTGQN6&=#p`q*BmQ=l)2M*Zrjo6@l?jBK^%zr{Sz+JfAqcsIZ8JYDAQRn8yC`Y- z&QYZAwl9hv5zxRvJl*bGK<3rFAF?a8Xk7 zdu^5_xeX9QaLPeaXs}w@-+zG({v+9`xQ3qQt5qv&>!ar6_$4_vwss#?wnoipyWg?P z{_b;gwaluWTh;Zgkt=0~3beJ|#|L>>btmdDrHV6@R45ZDoKG>BaP~i6Hjg5|yCcWQ zxfh~WTYm%0L0CU)Mt|_z;lGdXkAem#o5u*^>5U=HgZN-|kd@uAdFpp)5!z*8Rvk`f zC@SL!6lAA!yBA?|dMysH=_^~Q)@ae;&jEm+0zZFI+kF0F1DY_Umo?vnn0UgO0*nqw zhbM=e+>60iTYc>;I-$i(uGNO=%o~7Nz&*RJ-hXcpCnhS~y=S^g*$!hnpa=E1)rMVD zmir@bfEzR-aa^{L*=e2;#kU78jTIf{=pZnuEh1N%_I-gO+_aAi25?>h$(L?6sdBT4 zKMje5cyfr%y^v{bTc8@-bCW<6_Rb8q0dSte%B?ut;>-dqz)59L2^KtLfgvr_k#t(D zMoWhdbD|_nY2AZh{Ubbt{|>u|ky4J0k*hvl`3}pqD)&P1BKB5}6xb959n8B5!8be_ z1|3#e-KkQpt3={YaBx;9yD$3Oz&<$dr<0K#aDVvIy zdscewb$F4;tm0YUpmEfMQ?E^Xk%vR$!FIns|vm1~ShM9UtC(pAT|Z1)KDhZ&)pW z#6mO`Z0~)DWZP=jUA=b*2XP!H7jFelNCAE%c8FmQTjQsDC40LaqqYZ3?$r0d^ROIa zXu`b0cI{=^amh+0Ysv%p?b>CrNPL#1%&*bdJ>f;$wS67gmW(V!=5uqf$#!ik#A#(f zVUa=sH{7l*B*po*6d3#ILj6r{*Y;VKS1%zUYbl0Y374fgB!kNs0RW*!S2?2;Jw8@#6+X;1$EKfL6hA!B65?i<&v~ zFDRTVkW`}tI<`**m$Fum8+?uZc?E|8U(u9;Sv6H<8#nl6MLhEg&kFqc9^`g^VP9n% zH~8}!d{M;+odUlY`zpa5g1?}_7uB>2{9fpoK=sKT63?OrzgWf;V_&hs9fH54!1n|7 zNZ41zqgp*~+F#b-D~u}WiiziLB@f4~?Mk=cFD8D)(W-$8{$BFZLu9}3jmKRJzn1)q z3h63X48LkhZ-Ra>>-aYVzZU&}ev!S4{CmOcN}%M>xX3@HA1(Wr719-XDDG60qJUPx zvBR&0zh5^cdWXVa+?27yuciNz;@@KUdoj(n_Qq;D?-zbE^smMLvI1HKi|I!tP+c*0 z{A>B|-4OJrABAbfD|ZS1iWJ5uXZB6;#9}LEG$J z?dbNwr@f|GtyXII#be=6;3?8|2^8z9UK=Otj??t_0b1-9Q?bWD`#$PtQ)7lg10Rj&+{MU>!4L7hzZH>m z!}~w+gNJFQ7}jpNcUbv4`U)NflBxm=USHz@$xLU;ui76f<3l$j^ zuNqID8)AfHl9lrc{>P)sCss1+BxOTs&RjfZGPjm6-4jgPpPN3ZiAJ#qRIy3~zRT^; zO}~`1Q7tVV0)!NFKinjISN*T2Zwspb75yu$DEgNKH)*rZdspq()4v6!2M%q&8baS? z`q$IPaxtYVR(St^`d?2!=ZpKlSpL5!^slF{3#z3<>Hpo9{}eY{>uYXYq#RmNw66$W zO-@wsHrvkCU%vo(aIobdjtPV*_L)~lW`4!+wX9~V5)`jTF6_AVj2 zCLgN#iX`4`!S9>z^*%Pac-U91@0AOB=)OsK%)`ErzHdB#AusoiX+z22CN0)^@22%y z<@FA6yPB*zT%qSS#a{8g3nJ)EO?jm6wZdC2rhLWhs`c+S-%IPYx?5I?y<+y_*1s2h zpHp_#TFKDXzuQBe^u1Pf{m$wxzE_A)!S|x?wW3=p?t9hb-k_G-HwoX3%-5?t-j#Fz zzE>jPz36*?y+%}0dVFs$6DO+mlHex&t@Dn#@2#%)DAV-WxS_3AbKtw_`vpJEA-2+0 ztZUdfee<=pS5nOz+WU7S_1{?giL(9b@7D2yhn+ukmM1-~xImNdO~NCRe%g3l*ERay z4tZ<8-+p4-ZX4gr)@-IC0!12k)AMgs(?#ROctBKtdawVgXS;$*FueP%Z|gCb>1MSii$=${2N)RfhfA{HroNMww0)F4%aU5BvzJ=xe_k11S zjq^EwTlT7AdPVAr(|f6&9HOMc5K)k0RW0!Pg+~;GS0DeW;@07{_OAtEwnG;C1v6Ut zT~(9|o83cx6Mq%;&#EdqPt`=iPA?fcE&1m!Ks=|Q^7R#CU zo@TUZbycy2!c4K8Q3+JG_ejoYv+Js27S-^7VwzFtP{H>IGukA(s+MAgVn*TXJ;O}z z$#IV3%2NxsYd))1aaG8(RwGF-*yQrrv;FnQ`B}=I}n}!D;rgCSf2Y@d77RI{j6#`Yg&tc z;u)8ZP3}E~&W(*Z%y^7u{*XRE5^k4NuGCzKqw2~EtmKEqE~D@nX8YY z5OGq)t+?mS?EZ!rvRoVFsh2!@S3`0Dqe8SDkdWL;Wjb7Q-Za; zz#pE0Kq+h}=9C~2li4T629p|klyDJ$n20E4Fd7?BYAoo*8KKx$w)?R`rDjhGYdKV< zCYG@Qr3MFuH37<^3OjoIRA+2ZDRa8Qnxgc~`aU+8L|xDLSP3fvVaE>Dn-{!`3GsNc zJpDy_mWDE5TIQPF;gU$BEOizlw?Q;+?y^efW$@Iy*UwUAAzgNHtWLqOKarDvrOrY` z0c+nmVCA<{y^=7BZgXVeFS#W$?4{5a7<-R}-}{$2AIYG&bTK}xKs8Lwg#>>2dS$YWt<3zdi! z8}1$935VXwI6k<9t}R@GBPC~lNI`(h?>QJBSVB-1EX9TSUi2G3#|M@Wlm)AIq!(=Y z$xjt?y9Een?7%6upKN%i=^5_+;=6_56x9&Fb@`FOg-dL|jO z5Xi+hqN>1%XhBg`ih>Q)~G2p!z!tz%Ai_KnTJ@&?~1M z1Z$#NbkjzL<}Ad5uGkGqCVLj@m3`h&*bT$5Sy$0yaFmG`+u?V!+HhZ~?2Wr)g-i)% zeOz6Dq*`MSV|pXvSYcDr*|S)0f8GUTes8wz&%OfMFJp`oXYbIAFZUs2=!gidHDYd-7 zb!RGTeRqy?oc0IWZGR3J2Rsvu6*d_MvN5}>KgXg&EC^OID6$ZV=yr7o?{LBPPw$j2 zr5!KW$J#$yviFXLb|EMA;4@Bs({jCc3P_yg{929?H1EEV-RXtABI*>hJJ4;sXG{xP z@7yp2?GBV1@Au3vf~Kr?5+tEzj?%8!n{3yW7cmLQqLS*`ErI|=FqHqWu|cH_FkZHk zzyvC`Hs?!|M=LQCF4+__Vn`fmUqcUavXPY>=AGt~iz^!jce;e>FQb#JD<^+$n=O`l z^yNGFQaul{wxUOlM>5=X%`vv~+5EXsJyZ5ne@ulXZ-T3lz(sAL-`!2U|skvA; zTz)P#Hn;=;3zwRQb;ET{qs)Kx`%!7g{yw)N`trK~#)dB?s{J5d1ef2;F*dlAj_ikb z1=m%EkRtPYHW&=%J|)Ke2!97qC`rB~baV$$C|%bN@OJ=3kGh+6C28|^El?{xYOcb7 z*Rgg*))1UqQMOl<-P!9o3XU=H#)^`(UfsC^D3n|+@aa7+TxcoUJL-Ro3koeWZ#E6O zfy`V{GSh1>cR&|PW_n%a4xmsnv*5N4PCQb#n%zc=LeG|&uq)~zHgFWB(x2bt*jI3g z1qIjsT5e7GC_0W}MB};5HD!O~)&kZ$I}pIUnTN0A0!)eA zfdHmw2jc>4fHi_p-R^%ty(+|$@rz>qu?^Jz{Gui2-bs>lj-HB)t8=uB?j5fLFugoH zF2JC5)Drsc@piJi{-Z(KD51R<4ujiZ$_iX|5rdTK()i zN)mGrN2jMaIJ((Pk5P^WGfU#pnKx4s9M4>!3v5q5iEw>)TtB-sJFR2Yn_Kp}cU~ji zCTg9QvsF!Rkdc2_DqXxzU0-=l(!udtmG7C{1D}uGdU`Ou+iYB#t*WH`2synEo32kE z;uA8=`p;RW5AdaGucEJ>1vvGamPXk2g8EC`BAv#4g1E;W+>Nc;jZ?yi#X~AyZzfR! zWTcU#&#mYPNYb%1dwsiK*)DI?5W>U5O{L{U^8o*SX=8t^8B_aBQyP;tTF4BVB`zm-xX$?BlBVZ_%F*@pp(W zOun^WEN9J`2Xj&|WtLjfk%o1}N&>>9vfkwNhbT(glLOMhNC^wD-Ale@4-tu$;bFeR zppkS=&JTZa<9m46X}+?J?TR~uSDXucZ@yg^*g!*yFmUx|IW&xsr60u9c*tbgU%x%OE4*)vrtpN@}S<-C{9H+EMz8QX=o4p&xBA zW&V8opp<#FxL-=*N_lV`)F_uU_3}9^>3-%5c9f*zIdyo_lwSzXqs*p6>|nSx_`zdo zU@d=la$s0m&oQHv>se-$w4P^1N$Z(rl(e2}MoH`0W@y@GHMg9v)b2cfIqvjq`W&9x zGX&uno?7?F@YK3bhNsrOGCZ~Jm*J^(&kRqk`(}7*FV#lFpciZdQ#-k$9VGMxgXMJX z!t9%tB+|1tvO9IjGi;iA5Q(Iz337gmYIlFZsU)C8;US_yosugzyCt;iBYi3c%CnwY(pSB&#Mt4IrvgXS~_Erjq8x5_IO z5wy{09R&@3bhnbacbZvRowyzvxSKk5UpWt!uUkM(U_{Bq&JH20k^-I5~B+Ri<-TIv%<5^)< z{^n~|<#$?Lzbct`{WMpV!e04sM_GSv{V{`|pzhjbvp!?$jWCG6GVZ03-jz$>hEc|P zA!RIE3RE`r8&k#)`qfi9+)*n&QY9y*PGP(EyOi4o;K$Li2LD%muq2GhTs{8`J ztxB49{i=j(t}L))r&K+Fbl{;{7anea20O#&DYGZ%p$%D4o z-q;yyVLS1r`21Je@YcdcaA_*X$1r@tMB@#y6j!M;J`$1Aj`?k2Mi7%rm{+IxX?{kQ zq!ftWDvQr}x^yc z{9g0mJi&j70%lrX0b?K2 zNb%R`K*`RMg!A0j=j+8^xu{@G41+#{f{Q;BEsl1Yo%18C1c5jr4|PgT=GR90@nfXl z?lh9k1Vz2(D*I4XRy{w))}-|vMB!nwg*V^2Pf)CHUA0u} z9C6*yWBo_?xDP63SEW;f%mUAbsCfk;tS$)FKE?}|r)JIa$^w5J@RrNwGb1AkF$%Z1 zVLdS*oR^Y=O`l&vhLsh1{9VY>lgdOLsB;D(89qSt0v-G!bet9YjJIu zFJ&2to&6kk7U+N7czMoZM%#vTJ`)NK; z?E3id)5|{4z6hG+d>DSS5Xlj4aX)|c#kyM&l@Xa3$Nfh2C zrvkYu7~vked6rK(&HjI-C?chnWGZ9lH7+AzcMnP5C&=bH8IHNkRd%%tO=WrWL!@u4 z)7g%@C}YJh$&S`&_Ko27|E7&$`agdu_%^nO2Z)c154+KgfhULZ#hJxxqdbou0WSlZh!p7ZDFx;ENI`j?n*`w-b#H%s{clTbDr70`(&%$jQ~Gqc>i8#D&-l}M;0A{3K=HY@^dpp&jP zCKx;Df2sy7`ackp;c(h>gbed&5lo?ew=7WU>vF~g1QJTziU^>6F7 d+PLKWWx1b|>o*_{1G@&H1QVHQ{|5j7|NrdB?1KOR diff --git a/CPLD/MAXII/db/RAM2GS.cmp0.ddb b/CPLD/MAXII/db/RAM2GS.cmp0.ddb index e75f5b34d1352b4cca9d25e175fe58f6cef440d7..835d779b77c7a0d235f4accac43e451003f76fa4 100644 GIT binary patch literal 77067 zcmV)7K*zrn000233jqKC0001M0BZm=00011WpZ4R5Ha9RJ zFgY(WGA}YPF*zVpN+3*WbY&n#WNCD1Z*DTb3jhEB001s30RR91008C%0000000000 z000Xu0RR91004La%zbry6xSE;3Z|gzPyPSZ))&7oHs8+*v-(DT{^EmKeOCD6 z`f%%u;eUPh<@SGl{v@>G2xdh~)l{4)y1ue2snz$frB#$*P`s(OALJW_Ex-q}!lP)Z zI`IXnTD_B2s=oS0VOF%_NzIQ^$G4TLqe@jrX~P$%;!Sa`+N#g*eXuEh5(pJV(HEzx zsW2-lpKUn4l10%{7NDTN0uELZH4jO<=@gT8ge}t1xSO0h&awN(6-W~;v|LOG(|H?QYE|MO?l>1;ZRAfEaj_J^;u~{m5Mi|2SwMn zzS63%S12m)ZD>hB6$T}XFE*tO#i#Of#cg_#;)#zY6YG@y9PEO;JCD^*A7MDd^^MSBQnsc#fieXm+6iVCx$tDx$8 zC8MgTF=S?J=tc0)&HwPkRsVC!H2i59t2`zDAJmKRzwPWEQMRIlzi;#BFVTOO;J=F{ zF+6RH^M~2|&lrrN*48sY`=2MJO}G2G`hB!*d}l1;HpT%I_nRlD;$4%w2dvF#&Bqsb zvc}=F$8(a=nEiok?*7jd?}f{KKl3KnROulZypR9c7Ah{S zP?7#jK8EnQ>?=EX^Kt%=#kPZuaVXjiDIWA_bpZhvNNjj&gY#tphR4jo-E0ibw`k6r zN7=#lEwt90-%K1kaO~%3&RK4cks8IJayAVy3%D;9UT#&12M+id0111t9A>G@TWC(P z`&4YSVO4;7@%#(Ciy=qi>Ln=sy>T%)FAcmmJ}`f^Dty zkVey7+cf8^V{_~HvA78Ol7{vjOW}Ul#ta;yIsg6>w|@Vbi>6a;dJ$Q`UEq2LtE%Q) z_>*GDGY_4}|BG;5Rddd^@)##gR$WM!B2;j~l9-&c&jcIAzA$Sq78ei7_GcvlMclWF{sT?A(;u6=Dhke@+up-WzhzcVzZ zVCCa5a*hO#k!D8mpx{eNu;kh#bAb0X3N08+a#sshm-S-&13%X$nLPf9^+*dQGQC0N zd==kQ-HO@VIddX(k34Be`q?avx z(!Mr)S#@i@_O+u(41a>cn+(0E&d2Q({v^V>ti7ca5=Z;W@=NX@yI zz=$>P$TPqalN8adz2LxgZc6aN&m`GFmb)2`F>6WjptS3iU}w26k&Ik~1H^m=+FGzi z-yd-u+HhXLtO8Hz9q%}y3H~x%I$ADtUmQc$5LV|sYn6Fr?a{1_ zW{AB76plZ9O@%WDy5SCqv@34maf{Io#jS4RsAo6j=NS`5%MJF_qXpaP>1!>~t!u-N zN+U(2ofl38?wu0WV1H?p1?2?%6|ZqP?OU(FSJ-0W$o&{b`k~>U^kU&>tA$o-0Q{&TD#towy6X(h z=k9T9tks8OOgMkRCb8Fo)bI0WQ}T?a1aN;&9*y9sk^IkGgVvh%#&^4{Z*+`x2bH~$ zZp}~YXyqU8X;q#cRwmZDAdd&mzr(1k_u(=0*YO9U^Mf3Dg8ZE*hZ`Hu$E_pRqxW>= zpJi4(?Q7qlH4h*>#>~TuDC@s}%6QF&|Kb^mdSM9vgT0H;ju&dA*$^&<$Bp1@kJi3m z$%6nV<9~KDxT`O?Fpsd8Ap|d@P66n~7p%oL@-VYgaRtK;7T_>)cUG0+5je?8}-qxAB_6=0dI#138PM)RKx> zvrqY}1z)0x%ma-n{$NZNL~9M1j5#ZSE9#zT;f=Pge%hj$p|C3`e%@D(roGEbM#{lf zHZ9p!OqsI7k(;&+r-&8DWYkk0y2Mi-y-YU9J%3#;>h-~IAiADMH1-{+ZbplIK{@u5 zgaIZCGB{8;Q0jiHMbrY9Cw}zz-*bOw#>LgtdF3D5T+TLGi8 z7I(8z0VBJ6-;$4(^tk}@4BBI!n9Xw9Sqsjf*^L!AMf~W_B0WQlx?o?^jtGkvXlsMs1EfEY*B%hpy?#sy z_m0Q4t!qqsHL}BXAYX*a16PMpe@k^1?U~o_5urRu2sV0hVJBFzUrwUr8u z@C;+Y44!s+jNK#W(2~dZs80IttUEdmM5$eX{KNBFfmG*5k?PJW9aT`TI zwXx*N@lfPu+=}`BP-;#@Qsa7KX?Q*bW@M_X0ezzmkn54hs5})duI`a>%R-nsHaL&W z(u2NT=n>?dbn7;Z+-B8zOx=3Gvz``*pi;|GcxrsGa(M3;$}@M8w1%eTsmo;S%t$bg zH;kcgCMj@7ZX{Z30-aw%#A#RboL%oauET(5=7zZrt%x+ zTOk|6f|>omd4*-gg91*enPfAaQ$GWRNT+iurpSGxxIUgH46^s3wVopH851Y40@4MZ zJv_)TJ&=2U>V)nVRKVR~>=SFZ=!C(%ED@|K9{J}W4RL35cYQI;N~c>3ieXSoNW59} z$MZ|H?CKmVmNrQ$bQbGS>Dv+W$d&dQYRi>+8GTHW7PH|#m$!Aee^&x>w%6E0ZY+g@&t;gsm7^wb?ag1ghsH@ z&G?B8_tH|O+*un=vyST4&AFu+4Ar$cv49?~Q&VKbrJ$V5r9BmXexDcb`h8Sjt#YF$ z)Y1dpFuh(t+s`O4FX<`He~M!GcWA9$vHHFjuFhI5H_;lyIivXKvD9Nh6&iH!7w>A# zb#PS$$gT9N==;=v($;T0R*=@3@F&HfjNugj>Qf1W*P3=g$ej#@rd|5bBG-C7IA{#o zFEAhLRk|%jBrhbbox#CkXka+Bw)av#3je8)3=W!VN4^NIMuI=>$XKNs&f0?BjFq-5wm24x_1J3GuJ3eepqFu$_b)9bpl%cgPOIEpQQs$6S;4uXk}&B ze*QfKi-#!QX@ya$YSC$raf+WW1Kypi8e0!U-~PVG^;jp5=3sgbP`sManf6{TM)zKg z@e0O0oX0o<;hSz7O$X1Mq&(kzXPscdq@#L?hNU50hK7S^%_ElDz zGnDKQ@xALacfo>lHy|_E;mk8Pqk_7)k5l$Ld#rMrc19?*99AWNj9kij?K*A0_SQSn zjDpBnpxN8~U(>r4mV3$VlGbJIE$1OO58rKL*tGUE?!Hp$9qy>4gDwUAyhM@fmt}P6 z#&y~-%46MAdgdK33Y+;I83u9>`P&lOXALcub8{W%mG#=b|x8V z#zF7D0J=$kHH2c-SD7h*8;Dh+AX5q^WyaYTLbIzWFhiBE6^_fTu~1;^@ft>Z978H2 zpZ>tDm%?lr?)0Gb#2$;BC)3H&e{6LfL*8E3}+=-C)y;r;b!>5p8V5cD$qZH z`$^ZhfoZi#uEB@jKrJ%|C2*hHU&0;Gw}o|{2ZPd&%>-VdaJ0h!3cIXy{!XuPjfT4S zz@r+TJ48*sOW+<+$Ov4j6W1o#Z7|v|t{KOD<+{tAzUr?Qrz+*h_fanqJF>B2-FB)` zE{YDGYi?x|V{@C7P~R|s_eIsF15ajCnI8XIT{PzxfTkP%x?24mRjQcVJ-uUVtAuu@ zACarCpvX8boCc3oJ@9$%=G3$W+2IuIvbXF<^6>K8t5#3 zm5X6??`H(3d_#drgOXVB2B@%pZL!r4DX@P^22HS&0`U9k(oD>kDrtxa=jm-VlNAWz3sZYc=JXVlTTB{H;t#jTaa zc&Rs7i8yRyN2))dzqICwsm};o*w^0jGQoZq^XmTux9vvvhnJ>Ze{QyJXr)S}yKuPd z-|nXMyWYgiEdtKUoY>Wu<)<~x{Bnzz#AM#9nUK;iw|K$Y-t{J~^L8~}@UjnSD00Os zvZ`*go~evr7}=ont0-1BTSrTdU89JHkF7mA{O`a~zJ;?_iF!qOi)3|oPrlK5=0(b% zZowUXD7}t~cD+eP`We>4uic^3#|iYP`JdAJpVAR}23hAQtHrn-IDl5KQ5{tUb_a>j zj2K+wNQBX=569Q+n}n_=ug(s4(0!H!*tL2NEj^(2EZ`2J_TtdzKVZM^!f{mYgBsRw zZRHMi#l_KDyTi6rmIZGSPu&Qa05v*1ZAWINKH?7WF7NnUz}g*dpZU$zO}oQ42%-3T1y)?0_S(W_dx6U{yXKKQ{Gv>_iUbHkK0*O-nkX*AUl4^a8ZWe+ zu7>xhf{mRhM)EfC{iABa)me8n(Mb4z+8w%&TIYJH!(YIoz}gWz4gIp{6?MOO$GRjc z(@j6ZIf^AbLvL~>aDS+Bz}l!eml`9HdM*zCjdryBEQ=Z!bbR+k?9PQj*De`ATdJzG z_Y3#xqO}Q#-B8A5&YF9GI@C|#-k;>Kl{yCUqwu_|m4By6S3c9evXRy$4u2V12<@#X z|4PZZh18UZoj{JO8M)xYpV(#W&b>F#tfv7oqhj33ncPq+FHL&wJz?}5SqhR)lD7YqZcbvVeEv#k8!|NHraK&IFAoU93 zJr_zj<++tShQ*{}@yl<>`jW>zu|Z2o*xqzMpJ|)NMh~RXcAPSAmNlpi1#%fnyDv_)7H4Qq=fO zHjGWOHETtIcRIqqZTDZOt^JY?Olf0XW7Z_beuFK$ z!OyQX>gj)cO5$?N7Q+LBd)`3q&x^8n3&@Y)?>B<#;{tHX#f--I2=^(FQE zhSq&xeP4HQ7LxdY2yY%BUbQ=PKU~flq6Nb)lUW#b#@G9f-rnme?vOKpzre%0SHZR$ zYS~b^I_-Mrm#|eOlv5*$2hE$L+<^~QsV$9{P}o2SuUW$+_ks4*q)=EWNa;!LooBVY zBWyt)8yWfKy z!CU}$-COAc&CQcpSd)zoFuVZLW#-z<>25nQoLsu0K z3eBTvXVbLV#cg{6;Cgf)@o$8yqdr8^AGj}a6=P`iy40?KOUB51IZ7mH=3&n5WMJT- z)sre*J0!IKWG#y$=Y=aK0dgG%t!%f&Z9LLRB6HiURGa6oo$2*0l@)n0QcanL!bu0B z&=$iA*(5#j=md3x^nb6A&4!=%MjhW3vI1J}xJXJ7sH2g`PdnAMRJ%hOsO212HZERo zLZClC9YDoc8fMyPi9)l6ZNtf0?kDiV#VG!B+Yn5t$9LNhM??Q#_Cuv*PiW0| zKQw88#)LbE8tU-^ayJ*z( z4OTX7lHV{FoCvv}9bHYW3f`13NEm}P!IS$%O$wdyKl56J>BWO?L=Qx7Xx5~m6k6x# zfe&iddSjYegDaal*6sO63N5}M*_e|Efix8Z)jZa#hQ~^9mbDk1t&LBnja$Z7n{ubk*IOxnY z=L=4SS{t-dy{vt^JDkQ$UMoty@y-s8BWEZa___;3^|Gjx%iFM?sG4WcWI zJOPjoN9!>te1m8@*MA4(zd{6_5PA&?6SHO26`7h zg*FWK1+?cP1b3on)@Cxb8>+w77kMrnq_Rm85gOZx}Bhc^@Icn9iK%O!R zXYhX^S7Yx=FsnP*ZiW;QSaTF5trI55_vzNatsZTX)E#bl_x&}{Fpf8!LzDSnAinu} z(ZXn$eKzg9ax5n2-q!JZ&7tixRqFu#wHsbI7sU^Yx6#$y_oel7K07CimgnHe9Z&@A zo=uDMtJW#_gvx>AjAE*j&s*nu7F7PP#nKw?@e~&8fq|Y->f17sayM7VRR!Rn; zNHTUR&STDE`6Q@!q-o`dXN`}MG=reo8h=foZ6S4OOsSn#Cmr8`9GoWay?czxPgl`~ zPOqu*u7%cB_B9!KRAkb270};YIFdr{q?GyhJ1uurFxei~pV@64ZBLm>z=^foa{NX1 ziaS0?N!KS#5xE1n%@fGm3JU9j)YE6yI;v->*2(lrFxQBFhF;u4O-sI|1miYYWi@Nx zBCSMx+yTcTfn>w&#RL7Gi{PB^nSHE@4$a5 zFi+fVvngtx%Cv=!Z&KjFyoe?CJ`8=P0{dF2ElS<8a_EI(p&&)x0+*>x)`FrICrVO+ z_TQLRT~2U`?kp%PV2AT(z?%-~>B@tPv}B?m*o%Dj!Hd*!m0ManoO{6+89a5Aq8%sc zS4*Bn!!FW@_6q#vg&n*Xp6Y#SJ&sF_zuhPngPL9_#pnuApDxnLNX1$f-gS_*y+@Gg zG`cyhmcJrjTA#FJExED11Q>Fxctfs>8Qm547PU;RwFS`mB!vI^_8lnY-t|JeFONS3 z`4lH0bn7_1yIa$>BacTy6z(PjwWsorcGA&g^Q?chw+KXvnN=21fd^_KDZu+Rf4axc zWIjIg3oYBPz?yMYD+{w`AG)@XLi#FjL+(Aq9j?L^Yr?8I#lh8ndVKMZ=a zXt}5bQ#@g-H2NrB+2A@p;H7*XxiU_H$sw$dh%v3TCxshZ&P|D==(5tVij4!e#!#}< zzX|emI)E#|6<>25b5GyPL6bVFRjNZ=zXFiQM)V~ICp-7PqU{MYx;r+wV13ahk#(8$ z%$j}l!YkIwr7*boJjVGmZNp#(7x2CmReVw%bZI`#TPDujeOu-w>}kF!fK@r z`kd8mMnHABhYhB(?^NroI(f)wuQwDQ=-N#i+JB_HrwdruwMBnL*UjA=yX&rAly|w> zvj}9lB@AYw9_BcHgXsJ|)WTZeZa7*kCF;$$ zHfqlQK`+>r3nTs9oz(4v%1lt2aJL!?OT&K|p)(g#`{=|4drSA82@PeU*=_YsI$@}! z8G!nDegh8pl6kVxPTF=!A;*4zc zEqBD)k69WXocFc2@(1(XmXlPD4_Y5iJKEZ!?JfVm2LAT`5<+!)U7(ZkYFG(5zSU|h zP+-BwjvsF*9m}Yef|9VsWNnY?(*UTEOk=J7N8a&ao%@!vIQSn6E zDP@6hYlODg3Sgc9&c`g8K__>rO$n~9mOM`|#5{mHjpogyl?&7s)_r}jz9~}qGq_BW z;F*+ov;t?;F~-Apk68kaylMZFpxP5wN(esTEGjX!j(yn1%?Ia#7}GJzGEP|;9D!^b z!kpk+=V4w{(hNrYw1WNgm?{7LCUVkJT4zAyZ(=RjIU5h8mU-2ZCt^cTO=eq~Dbc#z zs)6*bf&vF<*#J&Owe8Pz#?0@$k)rnUvzyIa)ZhnK-g= z{v2{=XWZu2iX*AYk1B{h>8)A@7zQs&vGt={?^ra`y3BHmw+Q%mc=Pa2(<$LW?_P~$ zrjj6A5Jgn!8T96&0>j>7w0vmJ%Szl)eOgMBDkv~O(s~BSW&t?(%QQ;SOMwgV->vXv z0=U^|_=NuhBOAYfY^))td(C!$xVp-3Z!mM*+#>Q#&e%6(#PUqntJ#Gwa2)H_}>0{Dvdg{ zi`r+JDQ6``En)Cf41(>_mzUF`a5d_|Fjf%o-n(H;=a1&2o+~KfZwkz9RPwkA+KrL0 z=TBTg%`Yo(BE2b5k!^$XseFcY!&chzEUx?0s}0si%^EIDnxjFX)5T*nqs?c+A(Gat z7MYjSWGePWhMGwWj-}SURbP^azi7?>j9MsgAo{CEyrmvkOXv^Vt-VD6jSy(s-ncIq zrl-i?AjYylb^5*_t{aWh+2J6QQ0vHdx{V}jwwixq6;qsvmzZoj7yolkulFxf*6WIC z!5S}JaF3CyEA>mDTrs0|#gd?%1hjQ_z{^tXQF6oKE?y3&e!~?wifKy+E#NiGpR*F&=-Fx4ps%&OaD6XY z_-r804<=bXz6KBZHk8V|*hc4$?yzJ5SP-*dCi|7ga3|eHSL(%;BPj2k-U34w6S^s% zcsW_wUee+$Ev=@ka~WEcLbg4O5m&>Hqv&7(4Lhfgces;NwWxhi>L+qF~)M?81%sG@5P{!G~*y~ z4TM4K?;AkNim7xzl?%VVfpz?)lEq1F+(XdrIQKo(7cDUEf>3k1krVjV4I*zm{e*eEl8oR z%{tRmLH!-$(-OuZ2MW2_nC}Dpu=WAgNUS|rn^vhkvOq1q53gk?lkjzlVEZ1_;u~W-bc}i1 z=om{maFHBn5LaviwY*_mMy(dB=t`;NGChYl(vUYDgVoKqOOdN6a{~pA=S9k&W`Tj7 zomNufo5`egh*qk%nr01`jh!&`(2c#Mjo48;Xz^7AcE*ZBAomOu@l)@jMn!YPl>0N2 zHM;_Nw%_&TFdwz6M(+K@{uWe`51MZ^{+2yv61*8*gY!=7c7a6@g7g9s=f* z)Y1IOpQ=C=gOAmC3_fTV?QqfH+Wf7IJmMn!-@>3ezGw9fcXj_-tMA&^pwyu*I=E)L zbxMPA@WE&S;WPDGOWj?!sQ0R7)=xUVuL3zQ9~kC?G!v){uS{ZV{-RD?!b>D**ZV$% zQmNi7ydBo+D?xl{_T8v>VkB2x8-g zSna82;dPnd4o^CDrz1z#i^Y!V@Q*;&c>tqpw;G55lkvXFe_gO{k?bx6`VB7 z3P7)k2S=)ndJwE(ycskseKI9ljAXT$_Zq7Y*YP*gr5cjB2?a3FpIk04_vt8^S;72<>~ zVNjX7ZpGxvA>--VYc&sT!YEq+@Bel z$o;!o;y%Ty_6{ustdTb;w8R?*d{xk6#OA{6Gj}Sb>~o2b*LrE%o1id0DiUnhEV__V zhyOuKI`p#6F>TRWRkY?UNRN?qa41dPs*(qB>X9Cp<+4qT91Yz%;cAa{hFi;+X%F!7 zEs|j4@Pu$0w?XM#`;t)%c&nkf_+dOfAO+?fB$ax^ZC)~NXK*m4ll8vgQq#GpTbE6i8rFAe^iX^TM{A;vm@ecf4Lte8{}W7i-; zrIGH(pf$)XTGQwZW9`+EwDz4E#-3+MMQi)mbS4gFI0q8ZpeR$5*8MO{=oN!6g;2HT zZP;LA0V~l_%bCy$@*)H2L#65-@Ha18Pr5Kssm0mx=p;IaBWuBCE^gNUzR^D7uoq%1XzjMGOX1bH`3vDO6*kD%}!J2-+VDf~+u3lp^r zVl+x>o$fK5b2gbJym&*_W9Z>rsl-REPddgt=w3R5e!aa*Xt@E_7#$x2%46i-ZE3;ZD8psDRy@@LXM)&oW zn52J32>ODxPJP((1!vYTQMd@!8lyY%1tYSgC9kvv8>`Ss`ht~%aD{Vd_`QE?j27ex zg*7_DY`(40GYNPX?6$+-BwA^P)WZUP48fvw>(}6lC!_y^H7sr#Ns&Q(X+P4f(;$Ff z!rs1MEU*Y`Jaym>nq4tQYnx3X?^xhNcZRtE$-}pGC9TvGjK)68nvK!gK^_UF3nC7E zTRTb>2Bh!>JA;FUP&eO2i-}y14b*s2?%w#eex?Ph3)+8Sbm9wsqrv>T9KL>y5cCB* z?r;uTJMN#j9M;~$nP#$|$7p>)YwaF{Di5RkBJZHJwh@qWsN)NEW;MKPXY<7xKWCCJ z(B=VHd+P5Fk{JM=1Hs7OQyrc2lCWX&G0vFIlngEL6ayE03O}Y`kHHKcoJ=%7`nPtF z=ZF4yRvNRlqtsR4{2&Tnxt;hf0523WzF;Saa75g$?vLDY2R_<^@S! zw}WPV!4BtgKd7RAYrYYn>w}Ed!y@`z8NFR=Y1m1 z0Z-G?iAt}jXpz+x_5|dqjfS^@;`NA?ly2=+YLITObw>Ad?VzCgsJZCLWO^0#hpa+R zgfY7OpW5fi;*<*AGI<#oR_#|4%`f*iV$QbO?&g?IDzpH(RkoY_7(h9HU1Ym zuq4oZ{O3bfH*GSR1LNkRc{BG8>M`vLJzRL+;yb*m^+uRF3m10EWS8mIqr~pf|V zP7^Y3e_2ZvD!-y4q1gieW3e`TPG)!2l(pQA61TD9=#@cfD8) z;^!XL1|D(AgbUlS#tFF0$O>UJaih9G(n#-7#YHmai>y4Wc@a(vHmGY>0XnI+g%=(` zaU^+pnp#?ISvv3IS^zJsfWjA?+AEO$}_{i;~y-D!%oWSJ^ zo~l_pi2l)pBm07DYSz%sm;vE^!7Qk9#a1x&XZ-04PR9G+G9U|OfZ4-0{Bf1hiO|e! zP=!ZdW$d?PtJOq@!7Zp|8q~5q`8rC)R~eJ{{b<=b400e0x`XqI-9AwFu36oWQ;)W0 zI5rX1QT$$iENxA+OBRyif9>Z1$=gtmifVN4*2mkN#!haz8~>DRj=p9U47tA`_q`~Z zoeGRF+@tR2wD2k{X*dE(<$NA&>?l)$mXw@DxP^sTJr`sFTpPzK-q&8=fElRlBsAtig7t} z!3FIadhf*wiQQnd{5O1=pqiQs;*^M*#WET*sl-_HJ1vdsk6a6N0FQwW3ySy~LTO0L zO0+z1t#wB0obzS$py~RoG&joQyqo-c;5ar@( zqN#6b+{-(_TA*jK7;%|bky9IA3!&uW)tU#ymWE;MW=ihS*Fz|OGta-#kTc)b}B?B0zu=X#1Fw?UT&Qeg(G)r9Lv_X?IUi$!i?fur))Zl($x>oHM zD|3J^qw;yno0$}r<0kD39pJr9%r8ogmTC2S4=t{~gMO=@+4_QvgU16ul20#kRUxZc zIL+R<*?SACnbW#h^0n0a{S|t#wvDw`n?&T#i9pM`A&i!1Qaw=|&Ie*|8RqjC*~@wS zTU)ICLXL}Bj;`N6UPH+nKcx3hLM$A`lP9xdP}k0BbZ`E4@{}8AaYU1J+!08LFr9Xx}qzCb4SwCpO?jk_= zx|qjYHFY&zJbHshotb6@aPkn&Q$sE1z+mBzYpCXOb=Jb^EE0ljYA);qwb#(2rV7lS zsmzFNHiI{n_~1^qH56G{fgkA(S{5V|AgRyHw3a^fekh)rN+&L`Xj?#$bA^Z6xz(7d zj!s;h_V}_N_jOLDfL7*5)>jayz3PXrC`RkD3P^bdW<;2ES#*Hpg>qyJVetw7i%CH_$P* z7i0^fq7LA@JAQXf)7V!7k{X@(k$BxHccnqp|N7t720hY@#cY|lH^J}yKSxchH1hVB zZrU9zARi3r#xEO22j8l6|ATgi>kKs}f>8dNq z>ie2rz9?q3WaQFO9b%F3Qd-`tDc*G=hb(~OneS9*x18LGIi^g$wK6;q_lnw zk(0`Jh>+*y!K2I*2Q-b6)Kz9yW7PR~&yokc+)e*x)UE*wBz zny6zxH91P8lWd3hPJz~Xsdr7;mEJQ4^TE|~wEi4En_BKXAX?L6N3(_hy`43O3guK` zpcLf;+?B$4Wp*FG!GVsk$a90vYR#ZIj$ z*42X4{MP|iupTR3Vf7h&cEV%)(LRg@Hrq+_Gc2$Y>(&ccL8c7PVt1HJ!AX9X#I=f9 zlQV=qBvbhSF;J;B4ACsXTW4RC){dBH32Kp9`aLv+9)59J9;L2v=M-6D{wER?~QkXSS zga3j-d6A7@+EcSXeVb@KwS2bQ!hKiaY6X%9-gs#2s=u9PjEd{d|D=}1>j~;|;#kM>B-_v`|6R zlv9srtqMGPBNw*jJR9!=AJK_RCgN#P=UUGtbnIO$Indx(Yz71?%|PVW)#kVyrSj=@ zKE8@#TgUoTrEm}(?(@;ws2v&Y)RVBZxN)1Nl9T-;JfJr_=;{s@@O9 zYdMVsU`@Bq`TGwRdLnVAu^{^n31)R*7$xnf@;Rc~i&s9S+8;{8t>}4)*15ON^Q0GO zc=>elcBeyMv$piY0D8AmZS3P!LVm7zYVrljvpl1F;H?=}O18H|s2BN%8msBq0W~mz zzMp})Pb`@E1=7v!yP9sES75lB@E!nT#e#Hi?ysgJvDA5{4BQL)4d+hPy+C&&GP*By z?d!eh?4^Br;Y`|6b{AbtKhE1(WW-4<>@gbW`B=b*%c`Stw04zKlqn0k9a1l&>G4!& z!8g)Xe9JA3%^;!UdmA6i=RehJZFs27Hxa=3h3RXl-COk{V63N#uT2G66T)|EFomX6 zRC5DoZ4V2vCeNpX?W@Js(e8eyB|8N0x1yHqfbbuD)H8GndA?VzoiN~&#~!0Pik&al z(dsy7oZKR``B1cN=0@vk?kP01h-%FfXmufQE|56|-N&ZWqmv4ZO(>^|qP=_O4C+xqU1o54gJ{0^e+TU8bohyCjrVLxlstr~ zrH)P>r_Z!?717xtBWT}1owDc3QQe1GspgcS)*IbPO2cnZXYTFsG<(c3s_|u(HBAq> z;F2(Zw#CYau!rTj(^2Q z_5P#ygU#;}4i+YKfp@+7g}?5J8th-|oyC>|S63j|yoT**O1k1SA>}!1v*sMv9ORX@ z_LQTCXmh`KZoJl}yXHJOx|+=}$=aKt)cS@R1j8JD?oetTuSynFhow@*$ZHLJY2#I& z=u2dwSVUO|rT#eNXTI^LBGefxcHxFbcNE794x>i&4$`z1}y+KS`v ztoSi}O(@K9f22hh^SPH?*za9A@X`+dYcn;i!&Pz(wi;=JdcmLL45qWcZj-C&#@FEd zH>y#;rz(h?m0+A?!3vqj@C9eqNQ2;o!%+Bwx9Jtp99SCI3dQ?^9nx*#=kgXaU$7I~ zZ4e-5F*@-DJ2`bFS}#K#UvLGzSj%sO=gSQ2t}(z7b{nS8-; zMG^fpf3W|?M_;g$diceRyd#6kzF<9EGp1unWR^c`|FOL8+uGT(e8I^TQvVOy*H{Mo zXMdeLS}OvwA^x-*Xsz+_KaVjHy78smM{7-PG45hD#L$|9JPW$m9o%i%zO5a5KSJtR z>5p9A913x`kK*eH{#tX+98`xv8~FQLAI&*1sK=LfT+R7X)|!zA;|pJ~!}$-)v;q1t z1WT$>jzep{C1%GE>;}stYxk|tvN`OlQ!ZXy!N;4`!@tDl14mFhQ$qY+x(15jO z*8u~%2fkWnsCQ80;5H(rj-#+JzB$j2C;}hGz>hqL;#fz<(S$V$yq|S01MuJ|c5$06 z z9~SSItA`KG^V_PSwX7re(5N_x-MC)nywF}M;SKcW)o zd1{cmNBTwHOSjQ9_<#L>nnBI8U8TcQds&OQCz1sfFZi$5VN^eQt>=rrDd7cc!Fq2@ zVDZ9}dNx68`%#?cpW2wxc!2y=7T#bkv-diPzKSSrKIl!kU#mW}93vNt)nU__?0G!d zi`H61*AEuotWa9RnZ#~73g}0cFYg8 zGU_h26AZQHhO+sTb@%qO;O8*lW)wryK`7ghTo zwzm4?O!bGUu9-94r%&INzQYhtwI^bEVQoV(%fCz62&w!PUEfhYXqns1LWOVp+71#Ld`=LL{L!TTg@qlVOiEC>c^?^=uF<;)^~dg)C8{}jjy1la7<$Z*lgP; zokTWt!4OVZz!8AwP9WF3s5L6R60ddU#vZF}}A=YyBxFR-aJ+Q8PiUB&X&1L!S1?w$m zD(q>W?b?EdYUi$(xHZ)BQ37hk3m#SJslIg8$PloyEDnW9$=>`=WjGowZeGQ6qF}+%*@FK=^*S?BFnkEXS?Nm-Xt~tItofC4*QXnw8R-W2k1i zX`afn#y=mg_AMR~)B*2Q zqvLMQ8fd!WY?fb1!bZKoEfukKGM8^A$f|A>{8mI}1R~{4mhqY58XvlX?>->4Hc%b+ zM72I~n9Oz;IwVzI1xnbzb?NEI4kpczgnZ^hLh@yE%yFd;w_(;{@;l9+0!#VWDgM?4 zu}1EN>t+7SYIPI+mW=#+$3j9zl)bEygb~Hx2{`B zKDTl++mawKZp41mh%EeBXcoDyD;Qja5*iPKMLI|zn+mu(tM`wJeK!$ogmGl?BtkZtov*J{)1R=c|Mef=KU zb^*WkkJ@HSXXFKwMPAMf6=uLnL6Y_UXh8YOY}c{1+;`3!-5pBsdp>c3&~YWriedA< z(cu5=h2P%XpRp+XV5FJ{EXTe|NRnUwj^-a|Muy|Bl`E<7&W={GdAo{6C120DO>$Nc zC%}FZTiE^C;@ilbFR`V`ei+G1;tdvO!tGyi!!m;2(#DJ3;De06*tPY6-nt&CTWcTRr~y*7tMZe1@amQHt$(xVk)al zlX=sV<&zd`eh=ar->^FYNz?emV4nBeq{m_%Wk-8$k>dv%+ffWDOUC-3YVtqHAoZUs z30u8F_mrqOo8Ig4>4GP#=4E{Jq*2S*&53njF{+hSWswPUce@lMl;WPGxN*bJhlFgo~(ZC1_M?#0a2t81j zfpE`UXu6<3%Zk3r)vy-6aPvd`Cl(VxCpe9FB6d-5JBqr88Pd8K_q&D|Gm48=+aI!T zam@5R*coUmnV;k{PwZ$GChcac zw|97!4!heo$0-_iJP?0%X5l4h?H|sawCry@y9^)a9J<(neY$V#CR0&m z)am+Lbs^3fnT3?C5p|v(i~X<0%wrd{H>T_4O+IeUbyv6J!9IfCliAVoh)1&mYb*TL zRB}$Pd7lknWgA65`p2{45K+dBr`C7*s&{+Ef6=U)B7VkOy44pN->^H&DHnz@K7nXG zsu&yba6o=^zS`-CUTgABcY&_MjKjR5rgrLH5%VL4FY3ZHIZFYF%bg7FCEoI0=6Dl_xIY4$CM&!Vz0{T-3G#< zq+*f{LEw`V);GQ2FM|P5?&;Pk zEwBz*y!Ezokx?1s{LZ->UDs1>g&FKDsCdm~7poHgzqay?xaLOd=(~b%qXWZ7tc))C zeCYzkFb^W%e9v!sH@15nUJmbtTqvHI;K`2mNe>;aed-(rJYJ^QxTLtvc>^#=5gWh4 zc=m_R2DB8J3qI7%YA!2AN3N`6TpMcWjc}1UU3h7xh+Y^Kqg+u4UrId{Nm_OzbN}o< z6@7W4YGuUFqn_oofI3u~VD6AyLE;zT*Z)3sNU84&K=TeH=27qd0CsjjyI#YMgdNDX zJ{V6C41)Z3P6XrnPKnkZlMEkg=#TALtz2j`0rk*ZKbxztvltJ-Kc5W@^nERHw-YiQ zt0n=W(Rkia51B(e$aYcBEy}yy2#3oyXPVEJaKu!|Jn-2~oU0PG?R#ph?@)hC!(U9w z$uGW~**-&c9Na-yCo&}j8q82(jErlz(L7-H`p6Zb?V|-Xv|Qmk;bCb(ebcOV@&tac z{F~HWbCbC>trbako+`RGqtOrBJ8d4|kiBuX0;r}K>k7f2Q;F3f9Bg_+@-CLW*m(mh zO6kLh7iRLm$nsHR6_(|+Oru{P3rKPt_hrJb(IpD`Ya`jJEO@x9ck{=+AWm>U2VD zH^Y`X6kCbg9>(oX9ZKr2$ubhviI!G8h*Ci;W(r%=X)?HMm$kI+r zz9Q>a?dnTKohHkwYS}jR&_*^&2troQz1YXcM4z6IT~_Sgr*ZOCXGp${S|z7|x`s+y zTx(`m-<~~6lPeW(?2(g^$f@n5?!d}pQ`{#R_QHv~h?M@O^F^42)2KukQ_iSltGTUGvjQXqjejk^+?I^iK-7cCJVcEZk}5 zR_^rUZhACjic=vW$zrZ$1^ztKh6<1Nz08$OMQ(a|7rFNH5m-?UOrHGy5!oqEKCgc; zeOBx9tCj2k6Y#sxDO8;yK79bK=3$nE0qP2p#!5dA$dmyxN&aNy4*gt$-1I6Xd3tYo zojp4GMCyX;!D)6|PZlZHEbU=iHm6~>`u)+ON_HpMx~S_<$Ah(PDVVt)1L65wKdGnI z)QbJS30`yNd3^X|r>o_4FW`wRRy9;;wR6&aZMP<=`&ockI2H%Ft>{wX8G& zst_+f?3Hb~u5#H&Z~hl1?2aX(Z{?1hN?WamKu3#&qsWv;VewmL>7(sT@b$x4uh!?Y z@RJeHB2Xx&ZNWe#DN^{lzke7 z;;(+hU)N>q^3_=gO5HS%wGem@gb0zC4_fOw`>NO10HIHBlj#gpP(69gJL-2PTX@C= zCxnJ8-9$yZ3hQ1V4cR5#l~J0Un1+i$?t*c2yqKvGrzbLTg!tuw{#29 zT?-d1-FLRzyU&7r(t~gGpL%Cqp!4$rrnUkvt^0QNIzcR>_)RgFklv((TTCD*-u}t_ zbfI>l7Sj+B{{D-Ik}W4M-to3-D0Zc{tNh`1_k~ zK#`Q{k#MQAS-^B21F{GHxutF|!YR$#@L_&gFf^-0sIXtjE!r!IxL4jyttIe7tY;yK z*Zs&^0~g=4y2a>OoWW%{Qv`F=FwuH~&`|d>;=9Otr1Z2!Z(7cz0S0dza%bbn--b1n z*SLD#0gtK8-8LZ4qJF@!42EN~N91fmXX%|=mZqjn_r`z)-_n=*<;fFy8E#7F z*Q(@>@nklxa2bk0LB7~S&2)?&UI)(NJ;vBgoR(12b0uqtorAlQEm8s_#QpVW(|E>> zZ#)`Mu~Ad_f-rxP%^Gv|UK@5Y7O*U&!@rZ4r6|u28$-C3O65J_HAR-7n^mm-Zm3_< zEPYrCzT*zfp|d$90TFX~U3+0y740$1gB9Zsx6C2|*! za_1j`zG7b~Km|sgiUv~ZncC}(B6H4iY>&iM0FRCNywSEND}2BZbDt;a%ncf+y$H+z zy_jJD+>Zv)bMt#UiK;e~*?T>rr(J zog&ucKW`+oKl$dTZaO_TnTIU~nXP}220f1-FGO))TfAONO9+<51{Z1fbk}unlP_WR z*1ULz7L%1v^UMU_^w;}^*L92I&@S|`Hz9B}Jk#EMd)So%w^BP;1cd1W>9Zww(mus9 zYS6baC(I>#3XQJbvjHg$H|%S_4mJ?Zg*8pC!_W7p3B{wEu2M9s)fOR#2Yf!LM5m1N zBvkrDfcfanDtTZqiuv#d&uL=UGFiY*eGt-`2%QQrq6MeN?}+!wLK+7^J$4a&U(GEl z*AM*GB)&j&ZmRNb#HB6EU~cF%Cx=q=2YrUGShdT(ZDa;}UoV-9GS!h!VH_)lMRt-d z1}Ni=*4@2smD#n8EwB?;vC@csxuXQ()wbpvdQfW@u zCKA^eE;6=#*AIpYPn$dB+D^&ns0%(kv^!>0e4YDq`PCdYMsq|elwvo^f|e;?lAltS z!%2NXH6ra+jkt-no3Dfm06@8ytz)Xb(~b2HF6ZiuZ6dkPQRvl&^59!A3VI5e))v8u53`nWW%GAEK*8lmnEIJM*tI?5ZTjCHZ zvHT~9bU}Avqz`Vs5+S4-etpI1a_+E%NZ|JucZ>)82KA^R!5LBI@SRaSXjG}Ah;@2N zDqq#DMHM)c=V$mp6^)-XEzaB6a76Vh&YPMS+|I!9PUnVi((-eFB7SXrLmaD1UrX-s z&Sde)*Jmmpw)-P%(STehc0qq!&%Z{bZN)5M`zD%t*5t{EFs+IrN`80AyTe>`;^u+E zFI;e1f96mRdqmXerxpM4yi>nukvkq_rI#a3=)w2Wu_;x|y_`Sl)+M{=p&U)-}ZGE@uw!JvLxfPxv$ft|r zTF?Cl`aNL2QnX%n;&KR=$dviZ&^TR5KdDK~%1A$%eMoZW#tGfgi2u*I;YGJYn=o5` zHxBET1^=6Q#4~qNXV-DfbpVEM=h3Fdt&0HVii^(MjryQ{u^IDWD$iYMO#YlcfcGvRA;b&Yjo(_wCF5YIOs%wAE{cI=#Q3efWbj@Ah$ErE%GsF741>FI+z z`OvD^KOw|2qYN_Q;mxltT5K?SM~B^k!g!F7263a(xz@hEG4D|4V~4nviD;x@3bjF0 z>k%|0R)Vx2@wdlFZZZ7hG0bOwy0I8W9k41hQB?Fdkap5E<`3&! zag7_xC~f9f&M41_i|lzuZ1{kZUs8!Gm1sTAUlE7C#fLnX51ETEJXMD`g9-jOd(snUc#ZykRaRNkpR}F4@3W`dEIRorgVA0~Fza<-U@{tDSa?pU@H? zF@CMg=DsVXAPPns%07uRH?Djy!T0+N0+E#3*7RQxmI<}rN@9IZ$+hIn%DKN?jxRnulhz-8ev#n^EcHF1 z6!7P?-cH%h81aGdL(?wu$;H;bDBLtX@Si zU7QaW9r=&21)`{L`(M;Z@08s#-ZLEsB8F5)2;*!}56^BkMxFzkbAUQ0W=wma_LYN9 zwO@})07$gwlM-*qr+F-K0Sx+#tLdEs`z0-5T@pJnUj(|~OeWKNH0s<3|B%(gX}Y`D zx~}bT^pG)m3Y^PRni2J>$m`596Y2cB=?bqSb`&4CQ4HC}75?acG|tW;avO^SbWTZe za*?HAL}N4?+Va7hf}X1>9PNqObkyKpMi*~Gn2$SD%VN2zY2a|@)yC;p{B~f$izFE) zPIDv8D2G?{&xjuzKv#7Nwcmet{N0F-cTx=j)@sztcOKT3QM zk>w4x?uyMEo#Ny3v(Y%7q0S5t*5T$^=1seK1edK-g`iG8dbY875U6PYuYDT-Adc0- zo7yU zT}sYf?Tu*Q?=-I-PnqUA8u-bRx5M+?D(n0UZO z71^NX#2S~E-|FIjoWRjYbuQ2t)$1BMWecdsos8_7=v)&lI28{>6iiNf240K)kQIv! zm0^6>h49*A2Q_LI{d||qQ&r9ITPmVFnV7v7UHV|@py{&#E3-B;y!41Byp{Csb6X4^kZm zLeaz|Ffsh1JMEgIa{5DM{i8cqL#KqBv}*kZ@hoeWnhftPV!GnwehU8dHb(oDovm+I zKEFbz$^Y!lW7lnkn5hP?{gu1!+=nJ|K{c-$WAmQFcjN>_9~H|a^;KV43hoJ#yQ#(2 zFBAYH6Y->&Ry%cU=+j~m&UbNTS~tU>9&=vd)GFJ zjB1OW>4-ubz5Twy&U+$Insm1umZxi`mp{oWIn%aa($j(nDJeQcj6O;l7p~S9fArSxa_m!-P~_g zfPHh4yOmlM<7mJpOw4eAL|TGCAUdt+Ki2U5lw|i0XrVz-U*wZdGQfM4^`Z_ZXK-^! zMLYlpvD`V?5Au$2*F|vpeR^GE(RrYyS!YOIgjU9_5hL`1 z?>qQuDe1M)_akp;%riUswz$vmFNL&UU==&pIF#*0503E)`ifOoutJbATCUp^Q!)kG%_=r}BJDpVw?|V##?__Fh8^sY@QR1A4v-0UD#O>CklU6M zDCWd1bE3gEA$yeq`|jUZdVuS!AQr1POsK+ZX_x-#>6-?#!&kL_;%xvaOA(m)i| z%&36)P=ra8+$cy*YEE5~HC91`fyI=_X6h#Y(s|>^cxj*adAs13x9EGFOTsg2OM7M@ zrew02@X;4$ug1w;wkw*d^R{uPuCu08j%WGig%?(@|DFXGXAxvxgAbWJDI_Ki+A@{S zs_Q)_e5*{|+Ta9A7XZ$OMyKuEhCN2du|gExbV0=gbmE3;A*qxOe_faxx$!da&n4$k zl(t|%_CO~3D$24F;Om!s4gtMJ@4W@BX3|HuU}_!^QRlx#5?@_GL)ZOvreJa_dQCvA zd8F?he{#|F=LCvAAgwzX^-APkGN)kqHe$LFJeCoUaqVwv3B8-6cA>SEBP!Kb5uj;Oc00>>9l?}xIA#&z!b z(}dTH+w8h^(oVi7Hp)@(L`|=8Xq2m4E7`f2WuRTt=@GNW9PRW@iHqX)T!Hs_K6S&4 z0JeP({k7T9xdl~puOa5rw!!!`z9t>L(oo0wu3nkR5z}dT6iSM91jpkGB7}nzps$;C zp2lvrA8$@!`=IXb2H_2{h$q-eEo-i)#IY*VIn!r?9q6CDb52oRtS8^mZAHjEETdcId(gD*I(_(?uVWwnBGbip7=8KbO0@3& zgAwP`Cb_mp+Sj~Hr#B5`_B5u<6rCR-ARE9u*oF*l9{-L1pg6{M@)O@dtodYWa`{p~ zuP*0*f#~(jU+bXF<}da7G0yZE_K{D!k=>-xSsVGv7zv{0NS#g5Xq?Z<3>3(LqAz1+a(ywt9>0Kj(7#)ofw@O5yXVc|LcRp62j zOWv#?G=JviTdugLjbm=>?Azj>1~5D43NLemQ~WTvFIp>}P;s8gkwCU4l%%22vZ7k97u{+ z9vnl=-<-9^#TAegr2B{u%lL)cg@zA(1da$dPhCs9`?K}BzKV5e-!v)!3LdU3v0H{c7VV|jqeu}L8mLH&yw>3i%MIiFHTW$N_kBfh zE+NaKlv?;ZJI9UcJ$%MR_eT{PC4QdVyoSwRN&(W;hEJE3FJ*rGcjtXS_E(098oP#j zPh~z2vx5@~-}Qi{b2!UT{ScaC@ls!+E|;Hwtt=7qZD-k4eB4=g+*=zF9DWYufw?(I zs_j3WUXZ(#lY=;N00?>ZBd&s7 zmzTyRpkQxl@jQ;lQKCj1zwK+E)q$Je$ojUc2T`#c{ z#FbaMkK{+5qrqBiEQ7`?nk8b447;R;MatJ<;PM9#Pys{F@f}qLS@=oA{NNN}iMIdy z3b1t|j(ag<*t6!FfJ+#3; zS{lnzgf%BL{=%fqVW!2{zWm{Xa1ZwbAn+Cu_*=Bd(E&f$H+hL-7^=}o~RXE zJi^|>UY5g?FXh`#)~N?wwL$(iJ4wWi}^ z!+MPK_w^=-O+&uV2d|YKEtK~48FS1fGreZHaa1?6#jKjD8D98gP4K9To0@aIi_^P; zr7ci#`VYKucEu_*zB-vmd@#g9iwQHJ>I~&1ZVRm=dyK8TGUNO6__wudp0^gr{ z%+UNFGM^WgQ!gcMoi(C-RcSB>PT3p3S~3c2US9jwj64}=*MCaLP270k+bzYu`@U$J zu&DogPb@qkuK@X}8K?}~hhGygj34riQ_InKFEu)}j1d{k@)N#y1?r`eEZ=FUua?-t zsF!N|qdM#;yq0oQkX)#jnpU&h;7PdGcj}axk6iM>ec(29qRPaYy)F0jPQB-1u3#sV zyJc24x>k zVjDe7hC%C1OPxw9eWS$dsp0d&z|!2>-QeEO@@YK+xU++cvsdoHS2 z{u3;(IM|&dmF^keUjv_vg930c)9kr=cqUJsM`FWcl*<2Nf4j2zPQmMwE_uzx^PdFU z+M|5tE(F^W8R}2@NZ>W;nCK4QyT^>@{0ed~Npd2u5jx|EndaZf_2C-NAvi=> zo%bxnMU?{eueHTto>G6XMS^^FfHjvKNGYUy5W^`((ukJEDH*K0}3(c@%&kW6QN)#qwN*z&Ba=BuO5 z_d767$}i?uowR?0KB$}4PqMjxh6ObzjJy@-%$ead4j2;!_b(o*h2QvNlp&1h_!il` zC>-&ls&m^~I=&H4ol~N;d&j!Q87B9iWvNItpL&By813$0>NTY?1vh2~s@Y8U|*c9kXK?n zJg;N8&C_cKo+T(+;BL3szz$ldb z|FSLVbA|a6h)l%)X+9JcmPrAOv&zbn;(~;ai~qLz`TZYG$?f8nkC z<}R2QM*N#9sMvaK*`=qNXe0S9k%Ro?Y?Lpu@-MBUSl^rE@Grmq7C^uyS^4o&lk-s) zcVOhU8sQ;Uj(`&L%eLzMwHKat*RVQsZk}q=@8RO&|KRywo1hh26;ep3Q$NBRrw&tA zkyt!Z$@|_lP}meSK>w;D*cCla1)01}8x;QLCyIeLWiZ&|NMB_W!QH$ZIi;xjrV5Tc>i1J@c27Sg|&hZ zyxkrR>T0)1jH34=zFGKzH0Jl`^KjPRep+a*)y6R~?z*Eo_c88`QtXBii=wp`m+UV> zT-b}#kbS6x_bO>swm9R0=+G;^%7zie?p68^V`6Y_ueb#$u+bK5OwlJM!Sb3dRcUO6 z@b?c~B#;D=dxf?6%bJX40sstJZ+%k?OOx)OmcfxDcSm1$t_kladpE11(=^8IexSCg zYpkq?Cg*elW77-M1q_lgT^pj67q^EIGohLv1!d6Cg2y|@2EW?M=uxl4#Eku*MJBm4 zeFrUSlhH(ThkFVOr@Bn=$lZ_+EF{+_2#Bv9ni& zxx=VnCa}Gg#GR)1br7B6{R9`gmh@%|bF5;?c3!pMc0v#R;l8zk?C@2lgBjWe`)Hhf z!gL<`W@TyFe0tNJ!(ks#M+DvbEzjAK@#%4Vl9bYn6%K`lM{=3*X@j*5e){)V9ppqcuf&9sZ+ zl>&VtOWJGkxwH26103ox)#qqSyKA` znqz|{@kkmNR2yXy@O8B$&`%RJcC|MlWOsv_74}x<9_7Fb(}53O6#&1y9=9sXR`g2#0*+P&?La@D^xLL?_N1CcU}o z)LqfdyltIAS#v*<(aIGN(R=ZL^$l8#yZO-<4&8|In&Busf z?c(9_-j^>ZO!7{4HkSYFl3SV`|r z2~EAm%cK1#{KB2EZ`DyppPGI`b7Cr1bXq8KjC1k(%qC56iLDc!CintWkx1+SY&Tqqsdc< zf-h*#!9vdWXspsjkM|l8W+)>oVapA_xulpUuis7`8$8z3XP54P!A>>BzjF-k;;go> zJJa0pgm0+DJZn1{P#n9*wB=gA$#&Cy_qO$zTW0taVdJl|PhHiPt$i9_!N{!?A5i{) z?yNjwPZpttV}h~r{;GMKmwQpt+oM4e4Lp|`Cy*_t!@VUe$FD=2RZ6A%wg{n|_8iC2pAfiS5EECv;!a-t) zvw&Y9vV}&s!H_%xJ&^ocWhn_AMfMD~x{8G17DmtADvw65>Gxx3G0Dp+t#m^~k?;#l z{69o2?O7^A4n=BPHU$c(WD$l7OSJajfJ>1!m9ZN9Vh%cXI0ul904_CZQ#y&M_H8 z9e|0+`bF_w_>#+2GI!u*l`*=)P>-E*U^e^8XoMzy6!)1Tp&^qhbDZzl@zW{9DS_GT z6(Aw)U1je~ka1AZ01eZTYyVuOs}eV+rx(5p!+>M3Az>1{vh7?S>eo|&g%rt5z`jg+ z0XjFLmseJ0r&%72`Pit^Djni6q@fLQ1~!z1|XpD4mnS{-QoZOpQ5hj?IY z9DFhC%>iWphz2%t7FFZn%1Xs-FwL8?X8xi&ha$O*kdB(zFpcuDNSH2{H8(GsK~mPh zMO#3ZzH~o3>P;n_Fq9^i{KM^LsuIHzQ{m4tUIj5P`)DtBNt$AgR7PmJy#3fH9UpIw z(j8F+J*g$mX%Pu>cGSg3I5G4{K;rnv5=l-Y4Ee}rxhG+?LeEi7yFx-{c z1(n|%PI6E)g7nQ*-tSFyYqc>;#Vcn&`3{VlO(v8Qpx88gL{k#49 z?l0$^DNsLHnPRG<5qf8}6ps;LH8tF!FwgjbRbbpo$Rm`Zw;YHd(KyL{pm0%nP%m(^wnvhjQ`E4|%?k{)1l|uF=pqMDWans= zF_j$W*iu8YI8~8Mzb)Vx2d}GAZYjILE5gb#BZ8GW8$hmlH1)aq8}F>RNHNHdpDab5 zx$iPQ{0RqQ+!+ zAEa*+vRDLdHqgNT_H`%Nxl#7{329F$%Te%sWeN=Fz3gYs`lyBKgIZO<#djEdC?6F` zdDQNZRc>lg{uPM}=WO2tS0`xeg<~vj2$wSRS7<9O@0O0K>r-H|PSk`L?mvq?Q}_HU zuE`0D3ws6g_)p9GLb6p@?#d zTC`{Go}(ev%X`>=!QTTe^{9kQ6T zBbOTpC~h+q4c>sOx%4rI=0D0@D#K+(qepF<@KNSCk#T$k5GdY+D62A5V?OZK9zG$Q zvbGk`HHXA5O*tacW4@h%WhH{e=jB(k9H@*<_n@*ioM9gg4Iv{<9(}2f39gf+rW4<{ z5UQ{RG+*(Ns{rd)rMrJ^pyX5uP2?8^s&K(DX1Mfx2Rok_O}uwS9;VPbn<1zSS!@>I zejt+{GbW>q7vPE%^FEYlv`(e{dF(wUk3v5q`$hk;VoLPE4ZJt3pL&Hb|B7o|3>%H^ zkBj<61F@B^-<#CvU8Z^nx3^@63wkWdYVfQKg5egl)(fxN1-Qe|KGwy%4!`X zWrBU%XrlWW7%CBxTTXxU2O`wrRL>VTSAE#Hktb)q`_qcweV2~+k>_JAE(0;@mq`U~ z{VnROggFVFYY&U?p1hDstD{IprJY@5iRKIciN9RbLhB^0G2e=81#^t)&QV%){LvFe zdv|q`_5DQD&^_>=9Fa*5299AMRa>_+nlQp0o&VI@RZ59dM)u#tSgJbWoPUFrHjSCl z6d-@U7=7*w!wp9bx$-}YRJc|soa4TaS(L+r$%608SIg{EQNvfd%u7EEPrJE7D1P$6 zY*L5S(@GJSGUCgQB!iu`5arjWIMAO_LqbkqL5|!*i@``m!7veEAvb`HaMC|VMU}NN z+pi9uOVtTQu!NMV#{u=gLzRDFnY`6_UVn6hkFx&f4xTp$f;BzaDRGFi7P=M0CSIcg zD8SV<2Mn6(iNWCjlU+1z+EkN_o5h#|e|eJ+hl|=|ZKyFfdVxoK!UF&~g37^0S9&zG zH9ofpu=KGw<<+Rb81#B0#`BuS;7nv5wPjXv@k1o6kS|#8(?6b)$=%p@d9bvFblnFu zZWB77Vf0_O_p`V+6d{9eztt_;V=9qFi9Ib6_AfpIY3yPKlprgks(!;s__auOi}JQ# ziPJvEjZZm;1oQ)3V*BDsClAwHvKrx;3Y{A?Q?mesPc#V1>WuKdudu?}eiha1=i{eX z>I|pdXNrK7s#~rI+7U@E6Z>UDQU$h<@inB7DYa zTF_x7{W-ztu47>ADnOIU>SLvLBzbTDHI$CSHN9;`;}`?cUF0Me`*2_sq31~lH{(_s ziE|U4o8C;jl14f&a6>=1T)wI%yrPlm;16|r1l9=ndxJVgCOQ%Vj{3R;&%d8A2Z*+1 z;%&4H(4KL!IHv6JfX1&1Z9cfjetvbdDZw!OS53x-1k}GMt~rGPbH}r4hQvV?;TUT^ z(Y*bWT#*csof}j<%7}YZSvX;?KHsllAi7~$tm`Tj62zxmVlKKPe({3*T%9X@`=o%da^VM){-bnvj7DU$y#y2#dnQ`|-kr@7r3__I!63DqCvNylpC4N{^ z0}8tqBkN|Gwkr{xX>Lj(o(XTtTlrsdyPR5lzz||6}hPX)^|JNq7D~t>6f{C)AiCq~=geN#LI4pm$LMp_g23`FKAjwZX%tkg~DCcf75zf0kzi-)9cX#i|;bpCgF^&dz6%<3$1Mr~6FH+3r;8j@)1*OlQ?T$oORY;J@R~ zBJfheYzX~hJ1OFeJjfz3bf0M~6Bb9!5Vcgspck(U(AO4j;`lMtzSunj zdURQg5^n7Lj*gqgLfhI0JppWx&frsRSp18?g(~s#%Tv!=7jSfR@HrAEJj4fIHP{|1 z1uIX;ka~hYJwZp;f6G{`+oTYITzK`oH;6AujFyf-)zEO6{oT)W*F*z%ZOu4ZrkFN^ zHWV#~T8{Y+Z;7G-=Lu7)#o~Uw$v1KAp5^n4MBuY-WD7dztQlA3w%0Z1>x$ReLPs#@ zNTAmyVe1(4wvSF43XZFWcl#9^YoBH3shYGEuYzGc5n3}+T$8l$WI{=C5}}T?x8#M7 za{p5kif25ti0A&lh_wv}^EqSUsGj7N=vs9RSkB+_BHB$-lX88&IanO7VP3=HO(Zfn zq=Mp?fPJ%&k{CYPOL+Z;1fj}+8+6bjw&_fGHY)*qV>uXE>XT_XI^>IBx|lZ3Fg`7| zL{5OlF!K6Nal%zD`QZVE0f4*DD)`W4pf(g`#I?vvWi@Po%nu1LJmIfvyr~P0L?n%5;QoKpvfLNfKKiQNA$&bfPZ0M^=4&}cSct#uE!OaT$S>MVE99iHy=lp2@Ms2pU$qh@U* zBA@mpb1GmW`@rG#kwoj9Ne$&;j6uD+3$n{_19)vGSKHDxd0UR z2f29eC;OW5J5j^pIw>=aG`MlmZV`WmGsO8Kl7k}EGGa@S=pq4n#TGfHO1!y2H84+( z<0ez+IpS$fmRHLtT5HawiAq8Rei4Q0GOlyCkAjSd?i) zLtEiOd0Fp}^Ieg3U9^(NybD&p!oe#O16&!Fao1dLm9IYH7XrZDz`R9RpcK7U#Nc>% zf#1s#d8-|kkd~TY#n^mU{Zz%`mzZ%%l~Zog{+%CxpNJ;x1xk15t_+BJuN9R@7Tn`O zW`jKSWIWyMCctGbe-53#cUN5fs7xjbDyZiZc5B?!JAs}6g}h}BAfl9YHu^hkRPr7c zrq0|TL&nywc{-d_Vse{fR@@e)`Kw`U?ZIAF+wREqw2;{O52ui=G*63=dE!9xBq+7c zFv}!dm?p61=;R(JQJ3>T7TA_WZ%A&am`UlF5R)c8AAUEK?0jD}0oL8*$`%HLMMx?l z=hv;mq0c^p+l-2O%12dv|J|TMkj}2C<2C~;*e`Mk#EERHNqs@0y9N3Lm06#Pe-s_s znx`Sdtxe${6hu=RV?Oh!{6i@sh(tL=ogdpC&QB`{`_KZr>oG!Xuur)LEuowKb?KaB z4j`-^#2t&Yt$cx3VM3cmVQ@rBh>@_=qbVZGz;XTu(lu6T9PLHl;_H+}Kbxin_`6xOo%=a=e&IR)kuj-YS8B(WE@VUc zZx^4l=evplO+$RXRYN_o&DLAl0Q-j8j;*-!wap0q8o#^DuWYtm)*Qn9(fWNf%`z{u zQLqQA*)|*u^2Fy7V@e7b>kwyA;>7H4<`q43-6>VyonvmmnY!;IKFfQIgSF%CAre{S zK05#_SXTBw*n7wBNT085IJVKTZQHhOXEL!pvD2|Ju_v}|+jb^4CV28&|NH&(1+G`U zYORfPSJ&BHb=2PbK$3HWX?KgV-yHD148=mc;BBV2zQ<`;d>>TcUG=hvS~a=zsE?PT zIXCGeCSQde6rlzgT0wq@1@*&ulx0NKfS$qZID^%bR%?JMq(swT;_~IGm)>EF9yz~n zJy}xU0t*s??Jn}Y)2->y-ArlL$xH5Uu{Sj*l%=b$a#l9johI0xq-57< zd+An4Wa?A^5b(X9@!#2pzW4Sq#@ z{`(qrUg<87+f_57O%vNPZ2X`hhod%UJCPdz%aj$zKJb@kY=F$3yCYjM?8H`xI`GwB zd}7Bi)#6p!Q{5c5J*s)={*9rU?)%3@96^{6lC#zX5jM3Q%wQ$nmT6hJ_a~h) zAT0$EOefyB0hdk?rk1+b<8rG-w(_c57et}t44hq-2&JfRoueSQD{}ygt_X9oOu(dx z;35+>%#?JNwS|g2VZ|uib0gZ&Bt6pdr}ARfoR7}#aORdGU}a*$TDv%LHLD8fh;<*A z*NkjJxv$oebp(MuguwvDrs~Xv+tiI(gkbH|&ZKvp1vEh+)CT9)b%Xig1-K!gtT^?( z4NTb%z`>{k8{V81@hwQHblg3{Q`}F(Cw@}8m@1UjOu_;9iNH<5uD!u$-wc>BNm3N~ z;&o`V%RP+0L0fz%M8aZ8aZ>8&TjbDM2BL-d%L7?72Y-A%g*&0Uzc01N_38-lAJr>^ zCv9~2wCDJOVCv}C7}gRaP7cmBtXy}vjP&VvjFW8n|&UoX0Yin+VkrZ z7CEo=bLB}`Q|r5*Vr4v>H=&_F5+A~|8&X`CWH9YeAE=3$$dc!e?BDL8b4B?9RTmcG zBGr~O9Kvs!Y4kh+79Wa{9|K8)&P%H=cZsU$`0cbRrnE-W!nEnD7Wp=KMPPO%GWgWU z`Bb(f!?5nQ(p|rvf-42>LN-N^TMu6FEV{zgqi+nHolkj@j5g1^#MBbt){%cV>JJlf z%JtX1%E0U%Rn8?L$(mhidP(YV$JxLm$YuN?zvRDzLtuh#5!E>fG#U4sFi(_hAWv-! zVr-aE_hQ|#iWI@j)w#R-!fwjOEEs2ul|)>$aV^DE_2Y=c^yYuZdHg%))mGW+UENth z4|F|Gxrjb;p1NrBWsbxgb~;a~9%g;@YS!_U7A#BoE~=x1_v6j%5k0~g@mSDRN~1ZC zOK4lVFK3Pw3MttngKpZU-a7^kw=l;xv~z4TocUG^PKI<`Xa&Rpp1_8eBk2w&@LbF# ziS1+-7Bd(po(Rb3<_q&cCzE5;j(&Vd%HiuP6({rd z{J_d#Jg6ZYI8hC12cZXNs$iD78wTB;zFhv}+jQhg?;AT=k(^-4I}-4Ha@#otReK>v_{SGO#Gy&_pFJ){V&y{m*av^iFO3(mjsTD~9{(`F(K zIa^!h*dEqiRXvkuW6>pbeioOXqa{!PPF(<26c@4&x!toMVng zW9{53!yX!Og5g`aeN+`lmHodR3=;QEZr$fC)U>0Rk2Sdt$NqVAxp+55irG{$nMG%zD^iN=@Fuc*z6WVxbbD*ly}nFE(H0rTD|`Q@e* zwc?)_=D;0E5?aVTy`rT7z(SzmL>jF`L*hF+wi5OIo7mvYJ(N?`G+1jUUxdfNvAP=9kI`I6k(4;zB=L3 zrE7)!Hxg|4@YU-ui^+McE_nz-JI;Gf{X2R0-G}gVdXz!KLbDm0zBkQgWoI3Yommfx zcqsx#B{|SLYIinXaBaaXbd>5D0SRd{TLu+hH?NZRh%TbzpWLltDi>6GY<*M;Jsm9t z{Zw>2BP`G%fZxrgVD}uS|FUOQR1w2xPbEimdc4iGaZ|{$apimp4COY#7CY0R>hGp)3Bj{`Cyqw;HVwO$J!i1^!av=NSa3s}{>#zN}r|R_^1LjM= zq=EO~ln&PLFDPP-u3<16eH-IV9*{^T+o#CU$@A}ye!>m?B&-W0dd3ywRDLJ zOv^X#(On>LR3dxg6nepoEv0g-}3CU)dU6CWcISc`&-4X@BYYCmn z7?7xpsG`SR5Vr^L&TB|Vo$RtI7V5*_>8X8y8yj0FCLaq(<-cGSt3V0rFiv5_`)~@- z&jK#Pr?+GxWBzW7plhgh3y$!uwRgDu^a)*lNxh0%%`D>pz5zDZf80ypSuZ&Y5n&VV{mlW|zR4ljVg}U14xY zhvRW(Oh(a8b%i6%QW9^HU$1%p35oZdtQkE>{Y9VL<=#fIETTl1YOw%BJn&fFG$WDq zfLXprgCbc*5aSoMj?2cFRDS#n9_6r)0g=c6iOH+w`}U_gk$>Yu{*>c#U!&~K8s?!lr8t@+PU&hejfEt8~y5I24O-<5;KXPr#NfA=W461i)OI`5t6icoQC{7E(c3vg z0^y~Zoy(FPx%g0_UDk6-Yrf*a?kAF+C{kJbJdWS3R=0=%eqUl>ULDzEQnPEXZ>{cT zXW*r7CSYvV2o?Nrkzc0pK854I63XD?Ua@<;g-h$l{ZVvgddy9wc-qI+OM~h}7W4(! zhd-z~v$qyFk_4BFa)~_~O3SBgj?)!9_o5~0W~0^+75{qwqWD2$imax(Q`j5_dVNs; z6%~H#aGzUijL=coJQi5jbl6sAc;0*}%o{Y$Ys44Jukz8AE&-<#6&i|vCvius!R(%;>Z0D4@4qH_`EBQHd;$+;x0$s+!e2GT#!S;WG0gT zTm!J25*$XVkjsVQVyKR;Fxr1?{LHFdi!oOJR(|*|PW6rux+UWghOF(&K@BMp3=K%e?lvM_&cwy*Cf zz#SS3jsX8%*@~SVmzVp6CvR@n>NFvE0`wAz5yQ3cztQflvv5Z+d?*rq9=SR?^5kvxeK)p)7Q*fukp2IB=p$KqIOcypBXX#uSmC#LF8F^|33>jfFT(XdAB@nA ze67mg&loQHzmR4?|Fas0|3Cday#M+5U)ZjWH)7v${}<9pz<*Yykp8DX8}mOO{|ozj z9`gSS@LSwP_&=*;(Em4W|2J*lEBgOd+yDPd8uMi|OPxFj(@1ZNUDw(u8ivZ;;h#Cz zA4mHo#x1}RyWv_cC9os8RXULLmy)6m_sh)g<<$O#|4}!e`@z)$hT;)jpi$SL)uGE7 zjs@sOZg1(Q#G5JTK+M|BNbMJ)aJ^R{*=`$&HG&{R)9+J^PLaEYDn!&5jO-p#cgaBE zb+^?(In!=@q+knS-TPu*%Y5RG`!z@zD3{zi?4Uke$bX_b92ch0nku{}CB2{ahvIE0 zp+J=XL<2m9gLWZq?NU*9u1B3jC5&h;iAiO7r|dauAUERk2;F-)Exg*mL0TZtoMPK^ zjy2_$Do|S=t=^3I3meXeL}kU&;{9{Ah*^wYmegLLuD#TUaN7vS=#F60Q%UAgfkR@1 z^i@K_qEpoj+rNlSyd9V4d*th`?YT}4*2$10@m@Q41N=eoQ$FC&g$kcyc~>lSsHEPng1w(bT+Lx+K5^(lKQ^V_3`JH~LL{ zj<%OzKjIIcQ20!dFw{qPwW&qdsCV5dr>+IMu9776V1^$oVNw2#J4g9gg`6{7u%W;z z=CpkBl&-cMAzKG&S~QK zLt@90t*|8>by{>qrilR6bk+h)l$-_rEgTU=3+29_bBr@fYs8Adj=D3BLDH$?d=bEH z#gK>HiciBFAO_{MdzVY9AS0yN+F-6Rk}z%x2Rh!rP>@x@M{)9?VzG*x|1nyKpukCr zA{qBo+8ZCuG##L#kN~APve5WWO0j)sty-bxQI^Lgx58LF=lZLLk{Y9XXmtE5xw!h* zAZ+)J7$#ekawCiLB7e9ic8>f|S&c~5geRTmc~Qaa1GnirJfA6Idw^fjY&Tfme;e5- zk8?&`6q@sbN(ZvDpQh3@p$({NP8=eT8Oc3HlQhbgrm}m+(i))*8V<bU32_tXa? zYNu@~#Wz3tM{~gQwjcTJ_NZc52`hkj;&?81@BGUZ1#MNp_lU%bQ?RJs zukG) zWgg-2B>R0sbNh^I>c}_8dGtQy^-%6Tc6;IW;D3nS;{AXo>UlrIC{PGQO<^&HCUJs0 z22iRxxD&85_`6pnRDpX0+KxHS`Urf~@JXTZ>LS$Cze=0kZdP!I9pk=;<>P@ zfm4HmBFVcpT&@fSdL8;Ma>>~7hV&Ybv?A@3v7Rr?qF3{< z+QZkm>#zkjn+3{Ci=Z56_Z;t^jZ8rluz)Y6IZuv{YK@|gkYc|IkQ*C?-bULGW3^EZ zp@AUg#&oxuSw#f%W6&rVM$(S72knVSG-?5@#4I6z=Ku}A23hdw_{;cZ`-0% ziSBpE(dGcZ$s^^O@$r()d@Ob%(W4y8XgX^dHFIK5oqSLOw3Ks|j@P4I}*EU!M$L;tjLEx!Dy+!`!B)B0|_Djieptg79ei61AYCB%jhSo=sN?Bw@+JU z8P08B9`cBuBYoH~H5kQo7#%#RC6R$n0oRys_--`T*ft<vMVCPW&!H!#TDbO>k9f6)a8sf5hg*AuK=7}nnh!#Dwc-W8fMh{TFy zKlxdsA06tHDksO^+OVmHpx2%_d`&Iv|J7*VzU<n-d>fA*fYX`kVX&eIYHKaq;jm?_e3m$=4HJr>wTvba?*j0S)(1_e~HOn2rpZM87R^w z$J!u4dBw~c`b(Ao$j~uSRxp1}^ad$XdxvXh z)npP%xiz{Yn&YAiW>#VcRE1+}+Kbi|;f$`+m}6I2sKpzL({N&#lxsGu1cu7UqPp0X zIe~wY9fA}vm9Uyp%Oj>5vgD}Y!P9%Xt0`4gdnQqRz-567Jg2@ov?=?Nn8`y<_CK2( zh8`*?24Pi44+g|hxIyMBQzZX`24FJzH?HUCVP!TiVCEj6!ya-rcNqQY&>aV)~lKM?-OFXFjR%aMzZ7o%WQ=(f>4%@m_;rZuen?q7UvhG-;g$xK& zPJJCn48ZoUDOJ|YLm7~cDfuKb5O!5sN%{j+1^U%?z*EEJArTS~e>2kYlSV0ATG&ek zVsA|1>uL^a;I0A7<3~>6(U+Jlplr5a;Satq35Kh#NkM2c3E7@te7Gm^=Z%T864K$0 z>k#W>G>!Fhdl}Wus+-FRDw9)=9GBoD)l*2RnWh^R`$9S?^x@^!PdY1eAIaj+ z)mlQ`Mp})3)lU%D(lw~qO=YQL{#%->FZg(|-FJ|KVZhYq7SPH)5uXca7s9a2HD*xz?p` z;|pT!o`M;^Q+SY-QYha4@m2h6gl2Dy(+y@Qz;41Ek}nu6`^Gn{>Z!tC^jQAFkGhjo zK~WCL&10hf)2MmIzm3%>&7RY-UE4`Z_yMLT`~-rr+=@qXqb4YVu|_Gp&#~RV4+t^@ zNX$74b8^04UpVZ*LKLnRh10YnwKuDD*>R+Fmu_})0`VYK;6yc#ku2y}UXbH?V-CAL z1BaB(sc~iugz2Sqq-*(Wsnn!c(#H3#?wL3+M`&8Qyj_Y%4<8@Qa;4NhmuMP7%lR0p zcvlQ|eL}QJKpqahfO@wPWyqsVV`HxgkGk8)9vU|kz0hLte z)n;1mPVjp00L^D$N)=ZftH`L>+=Vczs*=&h%mhY!S4J z8*DKjuYsgU{hC=76+}&uHH1+dM0c_2Q)5`D0MCWum?mB3_p0Lrtqj1qQAcceO+t7t zk?vo_GEI9VR|S0;YjwV%wPBmYBhr?!2<9T+Fu4ubMNZsLQc4{Obos{3-Cj7JNRcd> z!<=+th)s`e>UGx;t(@THmm|M}(B+T{!xZMSJh!ZX$lLdLsOw6hInmbU{ALdmsAXH{ zMR-i1^4I}}{@(TXr}^B-fsoDyu!G|zrA3{*`&Fqf@aG8&<4vd=bsGK(&ld)n4355q zmEU17pDMr#CHIX*R!}yLwfz0XvHT!QOeBekgEO(iKQK3$zTtQlR5|rD>F4=|I%gIR zy<d$S#)sJ)7}tQA%v4mRs_Q0aUe9iO^EZe_IdsjGiqh-X`3)NEVHeO zaAwnK4u$2cWGLkmG53E#5e2mH>+USL@jhp7jRx{?FnpGR{=+xy=0-BL|<2a4TiEYcRQC??=J-^79cdS4rIZZ zO*JaVb#Wr_y3iO2DlM|g5&yAU+Af&O>ke9<$RPHGdie~=*pfmjCTJHi%yx)VgcH4b z06-YmPlaq{yER(V2Rea3Vajv*jYnD^IcU&fft@fVb)-k!zeN54Q<1B!MqckU8}sbU z)FuAr40i9lM{}8WH!_df9=8$MtYRj_>yR4PuV4SeO++EzW6EvI&#r-u<|d$l^be}N zJ-2-vB({5qK1V;mw)E>I%!>at- zm>&{(pi=dfEaCPSSORaRC?#qq(LbY;F_X55l_&;y*h-t7nX z2<8Dvv+=X<(z0EOai4(55z&qlNccBqZEVL(as zATIj{(SDS4)g?;VV5CaLNvXjHQvV&=eyoM;LMf4ls5vmAzk&NXSY?kdu_d`zDH%X6 zS$G&8`X~QpzT5l)iRTQQ3odIQph9x3h}s)rcm|oI>r}Mv3o}1{1~T-PY>d{myQ^Es z%tRuw=3P2zA({DSz{W~ zaCVp8H@80C54tuSJ1-^5Lo+kPq0$6ymdJwzlc4Rtu!;mzemwVAKoZwULl7ZsIF zqORLJA%L=g%T^E1hk%-tz9e)LU%`KhI$eoa>!yy%P+2^;Bo|p z?6$g(pGykE0$nq|{KbA}FCZZ0q3r!lQ1HNY{Jv+I z?wY}1gs{tXcuTqFRShsVhT913)x{9Mh52~2B3@V8eFK~YF~pw(_hH?}0>gq{xZC>Z z)4cQh>at@b&)IrX(q>TwYyAMaOsj#@qj!vH)+-5y67MlZQ}Re$fyHCjm)>5%I!*3o zpE-v<5agSjPLP1iiL6(0wg6-u-HDK2zLdTaiA^z2ASHAH6W0-^kP59S>O1+*NO&1P zyhOaQgr@WbhNEvObJ+F?MI9$@?zP==_KKc>SlFiv+b0}c<-0hM(JHL8)e=F|rq)QM z5L^Gp(m92e#qENpGR*YKxZ9i!27;D?ZaAA&=zVun;YhBgrG_RRS}m2RrozTX1;Gt- zULZ-B%tud(r=ForX_N{$v;42XZIjjHH?VMo>A4B{W`sNiIBIo_;&q7Djz|d)PCFgr zpDgpb-S?rGX~MfYy(>4loYEL~=!@7LM7v~el9QO}3A<~`hkr1!<(JcKGiFN>M7vd6 z)j2F^)nApo=R7lMawY66+s;8G=8}c-D}#GJhdY=TFxS4RST*}Rnc;jS?A4wmSf~O4 zyfhbE$_G4_dH)77C>(NFWtPravDr{%fNkIij*LwrYWg(lINNWX9UX%@!GU4x2C}&O zU5dY;CV_Pwhh3oILsw{_@FOqFi+^}V|3uD!GNWTDdaX6m%BZAzis&(DT0&k^PO3rW z8EVJ%&*g^9O&WXA|26%yF%+NcT+oRY?h?egsQ$8EI*AQRxLk~-fY}ZAr}C584AB?I z$GcGW%dSaX;VdQew>z+b#d-gn<&4z|C?nVRO}2pK&Tu$)gILjA9{VvXnqfvFRRr#+ zAiQZlE`d)^dGWQ!(nhIZ2YP#n~! z{0QN%PbiD2kY4cKnsMCxAVPxKNaj%+vQ4{%=ptrN48@>DTk`9-BNXCIb?<9TjJq{3 zU7-hDiy~F&f5Oc=qct}G8hMydn3d!6Cd(h|-EpgQ0DvfcsLEVlOx*vtbqRbe?oZ z4X`Tb>z|Cgop$sf@6gGQY@2)RiR%oRk@y_v(f1XVZ03RJYwFp#1>>}^9pMF)7LRH= z9YhpO?sLH4?}|ywY|y&2>kA5MxCk!ADugR+;0er=&df8QCA)RE9`C;EJ%9@;L(2_QN?K&T@CU)VUu zB%R_H{~L?^^(POrB?DUHN_I=e5E-xffBdV zmV=2xPEQnIE|NvK8;a7lGIKv4o0Bd1_?CrHzOe2N`0^$WyoA3lFA#G0}`xFj^V1=e`X?QAb5uo z$AP+z2X4D2zmdqSIC1~IOym4-ZjTo*f-fiaSm)AE3Kd|MaRPKdr4j#@N>v&=z*nLQ$IbQc>J8X7n1r<>n&- z-);tDS79Z+v~v23D}N~<>y~|@m(G7@-|LU`D_N^ApPB+-^D2{ zc&e{PuWt>jmd}EW{SrVBPZgJl9n);k*=R%*rEA8v@b*$_Yi=6e!k|tc^ayM1}9V~21`6j zg0}{w-v+jqRGt&Udm}dx>nM3-(p9w4c>bYL$Z&>&*tY~r6Je~C;Ej}?UIfNqq9Q!B z@f$Y79=`|i>*M)i-%d}}21F^ADC>cEfbK{Dun;B9x$6yXD;axQ)|gMS=GGDr;O zR%npcP1&h<4a<^cjc!sjy#W6XVN@X_c=Q^I=EN#aHK{XM%L`M98-?bHMX2c1jM3qU zt-HXchpISe96gSU;x=wb(j$$UzZXd8}~O zlM~R-fAVkJ`3Gw)%`#h__kqrlpLix@=tkgh;JO+i)R!C9r0ZfSNMEN9nUMUBYxabx z2K*M*^nuqgF{SZbIfgJTv}XF8f(ECXjA2r2nW08Y^mj5E%X&-C+d$8fgu#cC5gol} zm7`5(0XAkfJe8D+g~><|vRC_T310_lY=AegM(V@8j`zmz1ZGi{HLkWx=JelOg@=-S z|7vt%3nvuKliVGJ^e+-xXtBJZP9x}I0k6Hw^f6Uz>mnAl!yNAX%j zftR>mK`6vL#w172M?FN{E9`n(2se*4;Lag9HA#R&h2J+?N@O57sYp4tBdv?XfW{B0CU%akBEp%0W0d|l<)BiIEga^0^`%3iB%>3j zp^w`RobI?~jh2vOcsNQc>%QaW54~VT$d2nDjg!XHFPjBFg+2OGT zDp#i*4ZXPPHYv%;0XbB+v6vj}Gz32wAQ`d_GwdOU4YV|&#jXg#Hqs-b6Wma5iH=aj zQa?zN1K@Uo1Z%RXqpZy^gQRXwr;v#VZ(+h!>)BEY7##*&NenVdSY(tdKBK@GT`vOA zWLd2Gde_8479kV&HIM0e-7rlKu!T}{_Ezyhtxkfw*+UL}FZcGxEBg#LM-f>v-|(Q^ z)0V%>ySEVK6vSA3L6-dZ)iJC9DD1whj=DphktG+ggZ?ZOoCVmtYAB8_Wf8sby7?>> zV#Ww)LY?|Y!PrF8!AXI^+JJKj8HKMixE0WA%x3;KP3NI4;oCFI>wMF1VqVyJ1j+5KPj<*wTzWgn$U4PCNdD|Ne9t zxZ%QGW46!{J3uI@GsIlq8*$gc1QjiAo!eopEwB`QCU#Osxu~;ohQeBHuqUSuyGpDDXQ%9GOTXZl? zE4F{PbnxNe>6~sTs`bM8cjGD*&jxW%d0m_vzexbfF?XQ1j1X1?Gz;Rp;*_>0v<v>NuH*E9 z-jg7l82*8g+rf#fy(TN#b;PG6i-8fllC%*E;EfFcH8l2pY2ux%MFPVqSJ7wFSK0$x z0QXZaxhW4Z4N)D{`64zo;~}`$rvG&A$;KF+CIKnnfP*e5wMyo+!nhzY{g(j{%T}bt zxT(_|LR?Av>A>D!&VSjY(+Fv5cWe9uRrd6c(EiclVL?-WE!dhJzPOrMK@^WIH3tQ{ z5489F{wb+3|9(DSsEHdxAj`40qtFW$pB&?2wEO3+-S0a7r2aXYYG>~Vf|5jqrV=gL zS1i%M44mxJgN5b!_2R1Mimq*8E#5^ud#MSCoX`f4MT5l->s-T5y<6BO;<#?wK5kAm z3W+m;uxD}_cDRCZYXoJLzJE-v1X3wW&O4ezUd6+Dn0=a*3t=V6jZ~o!EZrudgxjwJ zx3wrEkP5~T+Yw0iuho0hDEaVw71|1xd7W6v=WTp(=e^VO4+Z(%V~?^X*kE^LMp8OS!U@}egX5#NlW}V(9U#qqe z<5jj?lJatVnw6yq;AA_PpF?-!z;1IWvK{<(t01Bm{|f`?Z2YFB72E}ut`)Z5%JwWM zyv=i@clrHBacF1yopcFlZC_82BzSt4W47ljbodU> zBw)8lE;`YNOvA+Ux2kzDD0uG4&*AqJk&QHl-nCF$-=GJa)=PL zi5qfanRQA{uW%+^TKj5cj@$&&nQ7WPE# z^Thd*buBWv?DVb7dzK@;7eTup9#9g#IjlP}Gl9^>CnaR3K|EHL)B7NPppUEuUpfLY zO{Vb(xCk14CJ#wrk`r59UNq$-F_~yeQeO0jfoc(bk*FRTWNpc^NhP;0TgJ}f4MvEn zdQ7{(5B|addK5gI|LhlF8jErc7P*T9cY|DyhZBfIq6mTC|1%iyC*ME4fnRdHJsZ;F7?HXzWSBTEl)m3UmruBNiHdaV#xmOfuE(~k(YEaj zAffK7o87;!3|+S?XHkz~9*)uCYIQ5VA`V#r;h~sDdJUwxa*e7w!R;5#JmF1v-XxTH z=<7;`%*$bv{hL;KLt9Vi+co8%_4D;uBed4RGLYa!qU9r?n=h>gZMVfFQ0P{U5xJAx zy!RTpzu7>LV2Hp{Lj5h2s$=ZX6;6Uh!Ve|WAAy7NIg#*mNY^6RYoZj!#KpzwOf!h( z;0kQ0a&Y5#Lzs)=0-S0=yq-Z_QLQ;Vmw9Tu-7@R;|%S z0>R;(m=~7Bcuck+)*)EkKRh=(IfNGbhSH%h zZ8V6q@fR?Xhj8xZtX_;WpW}o-%MQbG^#CB>zXC<8>@sfwT)7E=P-?}R! z26AhAF_Z(t2e3-VvLdRC&mZCp&8Bi_Unhlvq(v$vXN*RiWod+~9w4U6~(Kn3}W>zNBqCE(Ou3fb-Q8WcR$ z|EPHnS8&;9Go7f(%EfqeB)+XjcVS8Q{nP?{!@wZme@;CpSbj-7II}$f;|Np*0Xf2a z2J2W6)E}AsBI}ttP;re3{KNhejJ3Z7bpI0Lq;SFRTVwb={+_mNK~=jqU5mUX-?zahAA z)NmMo?cYQ{J>WW*wV~mT@_!U$^tx^Sirb1gyNWX?qJl+r0-u{$gED)pTr{ns=objN zsPEO+OJh-CFxpjNs#;H>&w=EUlP{2~toP5z0-5+J9Kjx0k9t!YZ;H~puus?z=V~jo}^{z|hwKCk$hkRB|sTo1A2a~_mRrC8*kR*;0^%qvX zi&%|L&E#pu5lH9b8NskBvI>e*SK=Q*t5ux&(z?a+vH>MY5MySs&R}7u$W%r*M(B;R zc_(VaH(c%qM*9j19|duzl^DP1%USu-v815wE$wm3{dS%fTO+XQ#`|%bUo^ZzZCJ

    UF#Raim~8#f5zMBGk1KM&9f(k6ao=Q6>-57{Jl2HFicP~SzSTka7M(*KT;2AN)1J&w0+gXx0~i z*HGNZ9`G3KjQeNzk&NdEPVQyZ_v7iwhLb5a2f#=uBbA%8Llqjo<=W{}y2KqnDe96rIV?9IYpqB3^xJ~Y2i^^_!`b$>i6&8x# z?*q|Ehd;H;Y|oo@WugY;B4%8J1uGj4ew<{>djR;x+lvQx4wa8tc_VqT1<_E z6<7$<2YJ2q%h(Gwz+@$|NTJfTxcFTKSBBz7Z?ACx1EHcBc>;Z0io`|4 z--!uT>BqWQKzI!vDDNPPS$Atp1sC?RXe$byDNM*737&q{jp-}AY&DTIP`{wK0TbiU zu@=f_BOH@;7`Q>Qjk#ngAXSS@MX9e-U}hqSiUdK0(_4Un1Qgkn3<(x!fblV@Z{iHt zyNJPy=(b1d{Xo0i_MzFYQAp&;sJ+`K#QbS+~z?0C* z9e=W3aN)CG9Ups-%V>wu%|cN;IWafnk#0TyUddCcYL1VITZhNgHSyzXPxcl6TLPa% zb->;i^OK^N8X!p?#G)G2C)&J7<@-S0cSy>*;vi0o7qX$quC4joN_U!jZ5VtqcG)h} zAt_yZ{=iW$&{1zOC42CMe>0#Gn&Oht8=0OH&6xt{j5ELl*2kyW4Qa!4R`<1u>=G;n zLw+L3x$VKXqb$H^L;sF%q8!BP(iv=7{@wLDv@!kPLa7;|k>!8U%cRo%`|%RYEJ zh0zpCV%mt>`I9iUC()7vT$I~?l^~-2BS%q97Isk+Y{zYqrK)FC8!7Kk;z zq$aQ!JUnx#E;;7MZ;`eKe>0fd=dE%M=f6x|!qkmgpy4Ecl~s1kr$P0q=nRwjY-2T5j`+d{5`lE4 zc$&l09Tj5uChG=qTi(%pNNKOxjF{pF{$qg6D#rfhiqHEq6uiX|J6@ytV2tcT-xWY4H{d+jAG1CDY&z|L7h z;y|J9O*`pJ&F!4dyn2|F8k`T%!B~a%3{i}@lkYG(x+hiYnf=6Dh4Pe(#*cM~qJ{Y| zUH-l zHhDkal0*2IRQhoQxbA2BEPft%kVl8kYDP{FY3GfZ(tZx}Ul*#g>PMd|S@0KpQL;b>;CzoBCY_dmXG(W-+>xW|wSr)uaoLJqYQz@38WKmyzW9(NHtJ60`51#BRmETqUht8lI5uxnQj+lX1Lw&VLz1^ z`zKK%yuov#j^Do(#gx;x-9F+}?^4II3zs=@?(_|VuGM8N-`G(cpK7z| zz8{t+_eNU}KiQtObC^oR(0_V^RkTqb_6?8g<3n-|52FaQuPZU!?k za!T#+8aNm0mb|%Q^VwPBzx{yL zA{$wYX2~p0iIgVf9u!0Bl6qs=Il{dD)s?XU)q)Nt4Sx_$IO4PISNh7{3Sa}Z$#tPd z&9gO#hQy&T-UXSp)i)^S56b`~4 zW^Rbm&R%So=-NHQljcp1&=J~bUucgKjI2c@a2%h?9nQgfGxbsSXU)t=I9-famr?qL zJMb%Z>UUVF%^>kyQ0>!^Gwv6(xbZmVVo&Dn-@Peb z&}$fo?M68?iIX9?x{eZt*kD8ap*SZk)f=3>VCp*H_;TVe!krbzTmKH-S-?l;ty%rZD?wgLD z9EY91Wq-uAQbkiPW58BU5yIX`4Id0u?E&3(MG`WSW&y=`N#G5rw2i^_Y$z)Gl%8=h zHWCl~aV*kTr!mfr5;!)W<;LLe7P2;IBby#BC#Xkv1qDU5JD9h(*fnUNC&MJjd2XKnXxwtoNYBe*qb4c%x7Unk46p6A=xmG`+jaNnT#bq@q zwC0g(S1No`+mP4S!<7>Ja}LtPr-A5-ujnM6p{Jqn(_wiF9Og{!1NalbMntdwkG-#K zj%4Z8^q83$$IQ&^F~fMw%*@QpY`2+dOk-wdZZk8FnVETg-gEDb-7otCHa0S%v!X)v zNU5kyDb-4qMMHmRD@v(p7@8;?d-`%(FeNshDytjcb)bgbFb{YuJX!vN1nmXa0MK{CIjM%4NO?Z z8hYtRI5)T0cQWD?D~l!HHW$dT7u#mPQovUe%ZESedKOC9jr z`pO~6Wq9a)1>VEKL(2K!4t9~ML1leS;V9!Kb4_JH2W{|0VvmYp};04s^Cg{8Xzytad5As^PMgc0Rsx zhRa`yKzHoRN-|xC7DFBE%yjgX`Gqac{Jo)9qDe2dzOqXc=ANbh2|8q-6#RF_?CAjH zi zeCJf7FGb)Aat43LeL(&++~LXeakI8#9Jo?p4Z0_7l4sAl3?xo7OHL9$1B!J6km)YH z$27X#)p2IVd@`E!)WGIv1Mp1(?EPf0scsOqTm1{@QZ^|&=Q18{>p9w(wlobPX~p2+ z$9h}{&tJJMo0r`)bbR9xq)V&8@s1z?E|A-l>tbUu2v7syJx9m;NL~=lz)nArF5J2$&;(w{rJ5SL%BPBgLZx(U*64ORLZI$ zz1sFO_<2jil1?Uq=~IDbyyvKK&G$hFi4MRU!bKY2#ooPlrx*#ky0|24r@=Rj&vx^lH7&h!aX8B(PRG@;a{VFjMDg^?e09=L3B{P$1h_tqM&AG1ReNK9`KT6jKC2P2H{}ackJvL6dVUTc` zG!2Em-67r{Ib`+xECAWnj*sT)n|leRp6gX)P5rDdRRU0jtTX7nj5=C-}Nf z^U|e{KV7-U2`QY8!CgJi4T+vmkJ`?g>`jO<1wy!l;xVwS!oNnu&LDqdglz39Ds#V- z-~b9vOXryvFf{Ro3S*xk>0con55i}+g8EfaH$)`D{@3_v|7fmkUoRC%zw}IqX5DDgcd_!Gpe|}?2R~9Auv>Vri z=77z>1d`4bRgZG=;*b zqMrlY^yu#t>kkuNDkwzvct>W37Gf4$aYLr>1Ko9KKSC*5vk-2Ki3ta}a{pdQj9#0p zU}8X}#<#>7XbpF1rf}hhS!Zbqz=O*}Ga-Wt5u5!nthbC>Nw2ZD93!>pVCjy1Zv*T~ zp(Trt&kb8UaK+m*O5l%$3_BIC0!V|ae2(~<2}UMOSEq#JC5`dgopj;>!qHNP7Y>Opz<*4QL6jp1;35^(soMdyJ%Y0Fb*K||41P?OywdiQbO6pGvf@nVj)X zJF5Qttd6`pJ3kT9_}&kZkR;yy0Rvf>w2+GJUJ^%E9FcR6Uq5Ru|w z-zKOTTGAb5ThxicW2eVh<<&JosRO#kol$U810*7Bg^C# z)oY2EUhXzGIN$aO7_!z6<;Y*H;$$HC7h2G7p?;}6I+MsZEgvC~X07v4}W z@bTcI>68&w*tn7m4hvasv0-Y>X_OAx9JE>678u%lOI2;2e68-uqxwiYLJQ4(x}%Yt z@5wEm!*t^-D^VI-m^BKk6VML7xel~LKS1=Rrk%R9`f(){pmYRbyhox3XDG8FUWYC8 zm)piHb?I_f`aYwNqV~nu5T_9%KrbW>tHzhom=xxB`yGPx^4ewHgiO_$%z00N1k9*F zA2rmyI4dbNqs5wh1s`LOBWNafG{Oxsh$fBFK>Z!hwm?cF%Tb1wG%EE%Dg>ZdzEI?5 zQZGyW13mp*USNbl&Ojm5;#Tr%3L<(FABoo1f?FQ@JQkLoph}!cz%(RUa1R$soTYa6 zhL5%*6=T!xR}*tHo8npKjViGf!go67CCYU!$Yfq`lwcc(8T~t2jZFRNeR$d;950QiCCD%v)dMNyQz0&N$)vz6NXq^O zShAPmnfByZZtwRS0S9VC@>m~jbkyJSCzq$^hRwM2bow1IEd(4#EI!v}<*BXPle#h> zww#dKuRCzrf&)}q&}s*w3#L1TX|o50k|1k~-NSKMDCCMK=)@daAj7UuHCHaHOHu1J zu_;9*-fxrKquz`+*cM{~ZDD&tp(Y?Fx`u>rQ6jD2)C>vBw5$u5$&5#Tyg>nUz|s+> zLseek!kE25FMj4JkvQ*Xdnq2op7a%qC>G4jwXb?|cbsyPGIHt6#5!;``hn;y=>nHh=SJgQ=*)_&3UB zb$}FEw%`TPIW$W8%Z|XXCQ!Bng|eJ538|;?Ue!!2g%RY0z%j`Ey)dZUX?73|{s6(^ z!^6GnWeCnrwf}H(DY3iFs&tCWSIafx3w;N*L=_DG`En0C5p;E2LMym>8~0t{9qT7u`f5fCw(46ahpzY zn+x%(n~Ms*R4>FF&1?;ufaD(d#BFAd)G_aaB6AqQbt%2zlM+xPGj>oBeiROBw8ENBfyq&y+q=%XDO^^Ga@pq;ZOG zpLMQoGTW_u^{p|LmjC#GI1h7LfI;0jJV7jmlB)*`R1BWHIZ7p5g~sBpk=u1LL=b~! zJ>M^?QHn>(7w#C-zXO3JijXY#M0+q@kYQ&-K$~w}2K?z$uuxf2;}V1+DX3>yv0fy- z&(By>?+n}KFR&;SLdWB+BW3w%_)y~BR98pwyuSW*@4P^RkQn@ILvx+YWvrqRVjT6XB_tDm4L(>E%v*(BqU#u6Zr{-T1!mhrc7oTw(Na7_Wu9$S% zCC1mR3&pyeIC0hCY06Q4vC9D+Q}l1G39fd%rbfm*TaWO{yo+O&NfOI>YHZ`8jRY9| zy;96z!hpDIP>$`51FER8JJs!^Vku18_z{lW>+g8S!C&80eL*=6ix(0#1QUXK6aM?L z=i4V0-=}l^_}jJI_9L>kIX+fZhzTxw&;I}^pD(HO&LzJtedX zzZ+cPNU|obmVL144sQ2yv#5*bw9YWoih6zhiI+H2XIgZmkN7BC&U_b|Es?Lk>B$nq z_SPCDk|!PGBLlogiNRvwb$NMR(kE-OHPNsH(QO2rd)y*1ZoPiRO=u7Ri3 zBqcT%83?0in+Mk>6=#PBJI;Ou{fg{WkiP?TCU>Zwc8Ed4a`)a$`5EeaXXvHdjwu)t zP;Ys0wq#L((-tv=qE3IgNw-S<#N{E1yyG|TPwD$X``he2wB4pqIK1NX#dj zK}Ct*{!o*cdsRQ-wyCN9evf0gq|n(MNsVmd{&|$)Fjq{<})e6ytO_h zjHR{#?2WXfZ%rHmx zJ2Ky$?=@rlB*4Jb6(+;*CC4DVsQrsgvO6tHs2 z+vGyKw$p`o!FJ8aC++k%jP93isJPRzdZIlM4ya%5G;p`#H1%y~<}Op9-u9OD2Kp=v zi?Rkiw#URPr@Lm*Ex$FQ$UO;{Q-O{a*;IeJU@Dbc#a~``B-ldiMVdm|PfL0FwKIB2 zi>>2~6xd_Wm`~|nLEj}`u~fsF`IrhTNM?GN=bsD<^&nNxD3tt0z27k$1B+qUT8(3B z$*RYs@taD4Qvx=hg^8>z5(*uY0eEz6Qd(dn%KSStHZ_812IHr(N)PcC!jM9j_V0nv48;Tn*(6h;m8kH0@!M-53REQZ`r5W@+Abh(Yd% zcbt{Xj`^kW1*RBl@%>l7Um-C&*a}O~M^OZ7^ym)cC7r}bES7Zu-aRAuh-K2fF;W|m z+$a#$$mGKFb0r}6IY67)WHFeP{Ad#6>0$6UJJXVoKNSx^!TS5^M~1~UhGMSa9GD3OtTe2H^G+m=spce2vZJLQ@s=XWc zK6%e0Xt{p;zD;b$df)C(7`&48a2=U~`gJC5{T9E0+;?_@{0uy3+Y?_+A~64%o#Tl;`YrltuWpaY9Oy92+QbHq%q!r zA?0@B-+8q12wxHhPq><~N6=eHs4)HHThK0zeqvZ(GOmMgDvv#cP8%t_XoI`hE-0}T zT|r&qu4su0TXWfaCJ%ee%~b?BgS?X!_&F~o3L<+t-I%^ z!+i;bSd&htXKQeo5wY$X_ChRD)7Kg&VTEBNC6$yiYIVilpMnIHZGUNc7n69hPW=4!@B(;^T!%H9tei&vXhaDY=w8 zBRqb2J{exKPpkIU3U#v-WMeOAT%}2A5$)y6>5{BKGZK-^w=WW->)b~Z#Tc7Nx96#SrN|($`YU$6+u*4Glsca8^{KF1k(liG(E|0CHXe)w zdShy3lC)$jFoQjkH^zsRHRU(zaEQfPZt_KXENg`;ybztb-13V z!+^kmT7JUlu$6JamFlZHeJ1Z2x}ZJepHM(Sb^rE!A2vAPLX4W9A?7!CE*FqFSr{N3 z?GS%~^AVNtgez6nf(1UF!o;$(`VKveF3gDC1XNlxyB4*bBN6DL+MjS5nHU1Vm89rM8k5jrM%bVub!NX1w=t=l^nL9L{Ygyy)|cO z)3EQT+}(%p(E_*Oc;A3}6G*Q;AgvI9H3%it)m&`ss+wL_x>t%X!VKH>n3aMc0G*ctqaBI=ZX~B1=Daw9*Z>m>grVU1->nji(vocH2A^OAj`|+98GTwy zMrwRNdt?#jI8BUL%tQD-ip89G;TiYy4qDbU!ujTQlnu()x`bC3=^;g^h3;#2sqaWc zSwQ+-f8(BpHu#mu3z_4sXu}4Ub)z=Nc*K>znjUEL5WXh$w4I3yOEy{}cT?Y!gCRUT z>ifWV>)Tp{nfZg}F0966utfo2W{)4z1RIr*wZRmfYqvN|2C@!M@9PRCd(J>8Xu{Fo zneFfwyy1*qxjFD@B8H8qC9e1B(g{4wr{w6Gr603mT9(e~k}5eVSphTs4szc($%F*F zj;x4Lop@KQH8U#6&V`&ahqAtI@v5%jnj6l$pRx4~PlSvZFKKJ&2?NP2q!QVC|4w_X zdttm18G@r&Yyd$T9T8&6W>^$rT%uZ1Ju{eBZqS!sy6>Is4C@zDnz@+CB4h2i!7;C( z>w~#ehfP|dPa(RLvb4|FUOX5*`T*T~MTcHn^gxwV2Jfyslk{qTP|{Z^$VOgt-^INA zJB?Uczno&nUdL$j&W~-B;^v$OlZVxo3c5q8=tKd~d99v~hJB>&QRxxgG*jZUGZYa? zF3xW51L^Q27CwRf(;3w~J(4?nOzGQPSuATaysKba7dD-G&lc_Hm3L8x%UDc|`rZTuYVJ7I8IDUTNk7a2XwKsWv_YS% zg`S*7uSKZ)v1^6Oc2F=O#>c2$)05yK=mzhgqc9AWg6CW>4(VX9HA){Zw@SR{w5-+= z-Qg1HE<6tuDcNUWQn8Y)uR@rMhO<*(GT(d$Pjqp^c94Bnp_9vSt$8Caq0dqQh5XaQn6 zP)OHCbjDTdEVZij_NRgA>`5V(F5cw}k#WZ>pDwsbKa+#4a3bRIwxa>$JJ87dh{5Kh z8@jo6cv{t^r9A|xaVvd~e9N_SZ$_7%|Vb=C_ zZM@6!cB%X2=lz+ zG{5a}jtp>rL==Pla2)}Vc@v^7z4m>W%rCOw^cEk0@aR<)tD+n7(ox`TOLy4TyE6mA z(L0QPhQXf?pc*|>`_F{w8!wgXAyLV3IY~ZGf$Yiz#_NCr>1V6Y;`NP|@Hx($2>XCS zn+3ay+RfWtJ3}DAGY=+6JC>4;%}}s0HKR$7kE9CX^-ia`>EK-L{MUk5;X*17bi7gO z9LOXBJ{tRiWqIoo`zyBJXMYv)`iMnC3`J_c`oeF6p@t&#P;y|Sh=dp|3f5E{%3SWa z@~&4U^4rMy!nJwJU;V8AKh!Bf#otVzVqw?+0j9y{L!jbyS1z%KR`{a%!iKgG`iFX~ zch0{qNCLtZ9WN3A1My$>%3Q%E^8djOX8ZjQ_5NQAp_SeOP|iq%!BE)$Vo!rFto$#w zFz!Fp^N#<@8-VwZkRkuY9s`k>=3i`Lgny_lx&M{7C+0sx`j>qOY#1`ef3U;iApfCm z{4aU`ivMRw|FRbj5ebL=54MOT*gw>o|0VDLSJ(f$>e|rZ8V@DjEE`2CHGuJMIt@lz zt8zXM7kwaZ_uO`+_{dJy`_M?Zs`gQ=b9>v-Nm-&S=JZb3H|gwrE=1~%R1>JKUQ*SS z(Y4^ztG?92xR>5c7!*MX^@!K^G9q$!Pgl!$5IY#yfd9yyx4OpLKM(VEdg@3%O%`^e zl)5R!!&J*xGjNaNDIoaKbX-j>MM&+=B%;#l8x5DTgXvd7vqY!RJNpO&W($*qP0z4t=FO=!$A zk~ngPZHub@w1V;ZIABKP9lDDqphfU0BXZri`;9c?0gu&kKCNGZu)}X|*g;k#6G-GS zJZvB$!Hz)0YK;sGsy zFO5k3Dc3`Z`wKH}oDLiFw|n*ns0%SR1e#HA`8!G;J;(%q3WD?9n#mnTW%6_zGHUZ` zgGGISmJPdm=0qki7GIXu{0=)!z4sX@xYL;#mAXXMeHiuJw=u z8X_T&r}5nHN=_>t>w#qlQiA|`UgH4+QjcccIhJxx`n85<==FQrYE@mE`-M@e#P-Gh z?%C0&RnNT^15)uAT+gd;W;CD_mO&o^0YB)$3YS&Yc}xGVHTZQ;CR(mQz2im!UzxC7 zt6>VZmp;@m1OncK`xrj#WOzKMt6tL37&~0Ir{U{xebX5^M-Wtk!);C{VFPJUQSVFlg3fy-4&^A(Mo-DQ@7Jg20m#!X z{ZNX5bEG(>8-4IC%~<7@y=Efb-iYVvT!(M!^Pg>2C^E461!@gd=X$PPwMMbQ=K>!fya;f$w%5ZB!ZNn;`j(--%-xExotegd{Wtsh=QJL&{Sk96T=Si|`rT`M>J~Hc>Uz3;%{AFIa z3Xeyky4YLqp=cg1peNp=N%I2ouixWPEQ!85%X=GgJs$j59KrcAWZ0n*<=!cxWi1a(hHy=gj7Ih(HfqZ>Y zC5UZN-Zb_K021}YnfbYlX`pzS1=*(dAUud-*l&aC;$UTpgbYd98{xP!tI1fQwEl3# zqn>20!UiASH7!v%>B5$RN$WxaO>-4*Kb0haYn40d~12ULA6&y?LJ z>L@j|f2NcR`ds@yqhyQJFr#N4kT*$%gXpfbEVq-SmX^o(;U&6UY$0re--DY(;t!r* zJ(;D;OCJKZ3Eq?c4T+UX3`C?uSsVn0ttE*>67lQDAG`=!2JS+JT9}$7vn!4wi6n`n ztT0?v$^_x}^qTqhnQ`SJ;afu^lnUN1m{xh-jwnI;hN<4>6>Q#FG>2A5-GZ+Qf=T)9 z900p}@<`3BVMWJ5Bi?;@t#P87x4@W-+ZuE)nAj}@=VeDKDbKZJ<<~;=D$Rx}ez0p* zn@XT9#%KWXiDg1@3{hg<-)Qc4ga0$uPRhhP3*BnjHm9nk(%W)%4%p3jf3Ohvq9?JF9f)ub@A1 zhbDLZ@IJIAB?Oin3hWMzG+;D{!n|r5G(VbQ_j{0C?ibi9K?^?Q5&}HUztkv`09suJ z@vGcX%;A`+v_%;y<|OCkI&eqPA>B~OB{oi&cXgs{2x7z%?HgLw&?;?Kw#$D6Eb}tH zE6&A2PmLTy2SX?xGBI`}p14DMrcLsV9)3`J@~55qfF*JcJ+o|-9UGMa`?VsYxA6?( zj2)t;!Wdxmjd#_?tI_sIC;I@7yVYpZiaLO)B5&t3s2?6f&k@TMo41kzC`;RaWnn_4 zHYz{hFt|}frM?m`R>-vHZstt_PCUWwlLCzC;A#e=&Kupe>Q|7L9@hQA7;Ah^9&z6ESWXHoCS5i6np$fYJtx)hk}CSPGpQ>v zjNrTGRkETy$YDt|vMSRAJFZOR3?Az$iiZ(qQ1(9vR;Tt7(Q*!0oH?h)x$~H4H@&gYtH<2 zO%hImTsdAdhFTE@>f$iUHeK_7F@NBZ*+@Tr5|6FNq}A3tbV{HnnG(i z9<>Puiv357#*%j{4+=8KMkSIYDkO2L8E&~?)MRoLY2_4ADg_PHJW&&=e{Y=7$ymR? z!P?}O^%tyRwrRh@QpD z9WtUJQ#(QR3qeW(1f;A|6O+yTX`qNT+YH8`Q8Y-)gMoOvs%5KY`g+zftm`2GydqmN zOhqmkz#l5iQ&m51cgdl7{#)Sh)1h)@zNmsBb5AvcIQ%(#*zMDiCsip|V53!jl}cTK zWDDt073pe;BppG>01x|SBUOW|Ij^O9(na`jju8n#yz7Ja+WGsn&(9YJYB|11E5}do zuBb$^T8OLtoA(z(-K_^Rnp>7eHK$68)!cvi;9ntxT+_IrkUr?1eX1_qnI9+w4;259CC)_ENIxL%OPsjT#HML<@ zx;9?7d6su{fmEx^d+z3TcVQR|w6;4;Khb~SjwHa;S;uPF}vATH8 zr-7g*9+uga+Pw0ItO5Jh1K`P-ODUzQ%O~eTUjJO`bnpaf)cAS`p|!q{*{I9%snwK3 zYcd{5yT2x!9_gKN_`^vxN3NWjom|69zDt?$_J=6_5~gDGN{7A&#mH;v#@I)z#*i1) zpkK#&^ln1nx?}<`9O~~>>RG1*KIP#=vQGx}jTj`S5o>O}9L+yur@rcY`|jf6nYmA6 z=8b8TQjxcTWGhAfhrpp&fW`0_&mRx#66+B%p~tu|o%k&bQ%7>fh0Bdz3I)##Y){oS z#_EY=H({HqCfRU=qOa5T(s;xiNgTq~R5roO@~hCbc?~FrA{L|r;zKi`%y)A)`R|8( zJyuxxq<_>eP11_hLRymY!|IJA2`3Yt`&D#$A18BeNH`Mq0s;gN`1XMCLZ0UIsXvu^ zmtqzI0xvhxieQVbn&Vi=HRx#Ww*vJx($>0S771YQlg6iN9S3Of=C-%?-`~=QG;gq3 z&Hosd^3J5lpjk^+DwY{TiZNMjv5ud%gk>enq)yAdn|~ySA8ch)+~Yc#i{6^a)+_JM zbUg6ywj@}*IdnVBbU-p6kkyFiDCOiTC*8tf-6V}~Mw#I6J3p$~{gN@nyXCBixJ4x# z$arFt`O*7cCD7)Tviq{<3F~g9?kAVf_{mC+b(l`3CSJa_?`)FN>GDKfWsAp}|JxwZ zc-xs=M;ZsMIw4n4y_5Z5wIpXUxY+n2dgmLD8skt}E8W^Pdg_k42F852DLtiKmk2_v2tZ?Wqy-aMuh4c%OWSL@$bg-;LJ5-y#k z9VZGqF6Yy>il5N%LFeK>?X{B*C#b|uM~}D>oFg?^6mpAR@3bA zT~02Tbk)0`HXW+v?Qmy7@UP3xw0YZkmGcqOPy zxKfK#Td8ofHTfQ-Sn?pPkqzBYY!9sx&_8Gp%X@)#HIUgvkE>7RGf$lYS4rc95bucG zkc9A4V^RrLh%5F@Sk)Y0ee=4&qRnN&fr}(#Nn%Wj123bToWU4v@um8QN#N|vJ*=MT zYA&^=G}AnXb#Q^vPY>Z7Jn4h_)EoC-2|qXw=>?2bJ#eGkj`uaUE7xy}!sg?P@tY--!3J89 zF@S;4ru{R3^bB*%*Zk4t(FH0mQqvrosLssbsaAS1s8Ke+UOE+Y8ThGXdPku$-PzO*0l z4zh1o=Zz>_%1zrS$3r@%Xv=Wdm$tEO2S+^crfh(CP{R*3rG?2S16+UX7B7y$KHwxt zYqntW1Q^(Q^D&Mi_#f|+&F(GT+(0FqNaJ6H%aGx@VluFBQ);bC1y#@&}K=+?C_Sl(cg>8c>@?IbQf`bpd$I$0^aIkRFOj*umQ zF;VC8k#i03qlMtXI-a-XHp+CHzalPbM7UzIhr*CZ46HR~ZG5 zXQ>mMmERS`S3K=TjOFoV1ttUSXEoNw!`)$Su~|7*7qn!PENqy2yki5jZ82LN!KZ4w z7lywQ(Shp@=FAjVNbyjYy!z~WQ3)EA_B)aZXUpYjhtE_G7RfX>+Jxt0L~8y+X@Umf zBJR-|w3OBLEQ0R0Rb_C?~f2Ut;r1iN_dXD|vF4-k(-SX>z3~K#3Q5iY3UJ zD2poql?xbmYX1_(yd4df3jTE2#fTN#GN)6gslHd%3obxAy>O@VMAU=d=-sBMzvJ*~ zkrW)VRvu@i1<*~-EkD?yEBy*TE0GWydRAN$bDd`xgGGX#K=Q5}#;T3xF?=>Gh2?c1 z8H>CW+$Q(Q&FSQx?b@A7nejPMbs{vv`e5~&)ElWO^3G|6dvHpyM%{j12wbokS4b-e z`7!{~Gtd`U3;36*t%7CGA)vuJ-wrkkTBBE&0YHKf5fJnSjK}BE{hI-AnyKg08+*oR zZ3glta?D7eu!TU9=KYRR(KCFxJFSuEw)8DPi6GY%iF*sfC9x0xrgWA5|Fmi|z72V< z%HfBWXH>wjvHgmu=K$RIVCJka{T1B`p&n0eYw9uz`807`EfDp;~$Ig>S4QadR z_r0P2V;Bp{XG2eemdhVSuLW0#hiY5X zN<~tdjLiL<~eTw5GP5fspO$LtEdHE2va@q&0vWt0uPVnMA-xE^& z{!C%Hw)|?(q2y_V%%3?%P7n)`+Od~l88MY;4hAgBW3jV1t(e-Aa_tr6vV*{3JxLh9 zg4qbRPVJdi5Hov9FaJ1eGWl_ad7)_d)?2y@%W7P;uw*qqNy1LAqPU4F`?TP3RR!-n z>vGBI$XTFh)jZd`R1Qw_&n{`Y33_%TD-8f80sbj_wMC|>bbsVg$D)5Gt{!%>dAM|JMwL}dN;c`kSui;X&t@GW+ts#ZT+_5 zwac^APvCwD>o$Y^(NsLKE1mhXOWY_FzN^9H`IYb_x7d!&c-x3(&9%OlN$x@W2K?`z zqG%5f0Nuhp@hjtdg_$&T9&@Hd%GNq<%Odzeg2zikN3b+%7lHx<)UAM*G2WQ==t}of z9+PkTrXv0fO8i;B!R5oKrXIwnNLn!&k|@W1V+bF4{ZHJ))P;JxUZ{X(r$3~_kYC>> zVz2Gi9^HEL8@bh1E~9-goG`cR-%oUL4%Xz!1Ufsj=%}#Jd=s`V!FM8A89BTlj%mcg z32|#WTd19`{cTN+liZM3sFF#x3)d(miDO7lTg)YJtjj985QGy_E{m$@KJ}1ArAMV# z;fv^rJ(xk4}2&1}?rdsV@1hmvz%FgNtUrz9XZ!X&4A zsSFqyYjzp+e)f#6q|B9Ab98qRVB0*rF5q&;c5v*{YA>!bUk%Se z&}~nitmc-&1Koq>ki|sf{l3>p8Pj)A#KgT1Vd;@|yvi7k_CIIM1>1?WB))$%fmx(gfLV0b0vRY_@=y}Q4dTo@L$`YkuLE0ZW`_+!LvopiI z^PFy{K^49puqT9U6cg!^&(#f&u{0NX?@TA7#%UB|wZ>MOz<+q_qsEY`b2HeO!`6X= zu3dFn1pV@YEwm>z{b$98scAU>H;?$^S$?)`1J6+8Q1t&?RsP#o4*hcUVmxO;CsRc# zPQ1D6uh^?*6+$awXl$r#TCg2sh9;?g?AD4<&(s^;muoC3c@>zgemUOhgPMi2byB0V)vjZ2&FD6${=A|`UI#@JnQL5*0ex$?O08183{bjCSVJS_OZBd~Cb zkN*pwV`px|t)(%%|K4FVK)Y%lVylgB#rBWQoYQK0tVaU4hyr$0V_m`iT-e} zPDs9|Y9!G496D#qPc8V+C@bcBYLMAP#wm;$tkey68G=%@2YKLOF10UoK>u=4k9gO7 zyuxT@NEcpzGh}Ed6J+%+b%QU)>gZB*koeoa=8%jN>^&cLBjEfgBxC4Rvk=Qo^qvpB z=q^fJOGvTN)?Ib9U7?Y7cwh;OgT3OEO}2f zC@`M)MdTJcKSah`7>$uvqLk`9(7R>S%PQ7xYHlEN{22M9opfvRD&~@Dvs^LcA0p7M zINa95JZ(LkFyu!PyR9Cox13$sTAZOfPBQ;+;gb%@z@lth%?pckO_M;n3Ml-ppwLvA?*XNL} zME(1|zZ@A4>f|>kTxJ@oNUKEh@bUzPC4TS)OGsR48|J}mrz7{?!f!5TR38$d@DW7h zl9IST0Y;F^&tr1YEsoQEf$$kbGM~r|Q%N5Nd93~xB%YEr!{nMw%bC<8_DvAomjlXn z!td8>|0*td8@bv&fbe)x@M|f+GGi}&8>xvWTUZvHl6Xj44Z|5CkJzE?4^5o%crJKS zc;i|rzpai&jV@h!Q+}rHweo#XcsTLv-j2$b z1-G0{Q00xvmx|Nb_rw%y=WxkAB90LV=cq_;G)^#cBE%=iFY$ic>-pm>SM8OupjP@J zc1PlxmH)Qd@~D{fJlAp&3U9*qLgO^Z<5Q0PmT^#yqJUC)o)+vr2r7g0fNy1%UW>P=88_{YU(0TB& z@YB)hIN80QhjY>?)?93tpm2DfY)@uJJsPmnh$tNYcEqO@KEiwu>byl|<;L!ZvT!@p zha1NH3D~hP3*WK01Zd{+OMB1+9yU^mU)Po>w_Y{b8lelO8?%aEgC+FtAAP-?1EDu+ zUlZL=*m_<@U<>D*_F1f&g`b-LmaJem!uHXszKpF?!@AHNAM=};ryKfN=MamSqpUVJ*;hC^-WTu#RB-+~ zxzpVnr}YO=Vd)M@DRD1i$V0X&scm5jGT0+#WhbUUe&|og{J)0Tb(JGE?d!NGYM^#Q&Knld-uhR5 z$S7JQwHjUACB$3HFxtad+LSJhC+|aBQ5tBNq(SmQg=8)`r0oeg0j&LvjcoLZ2AxpF z>2ci;F^2tFsww^%*!~ZN3E27q$S{#Xr~i8>;-BU9{~D|KAAjLLTW3%wZMGI8U~~Z-z|AbZW}5W(Yr5_fXL$pNGUG03 z@=W~&Z1AN6)$2L|DJ@_}jHK>Iq9XZRcTGyLj&uNsvttD=!t3SHd{xo3Y8RFWEHdt` zDy$sjc8#$^AYoJD!tj8wU+C#fVsl zr?jbg*>qDyA$-Ze(@}I`Y894K)VMpxyZYp}!OI3nG*BL`sY+Wk706Z!8itKd0oLdH~^lpkCps+Ep-$k5W(n# z+$$L_Tq(~Zf-pXbOku@pCUF$Js0|tKe*URSH%}zFGhO$h%e8uRGcHs4!IZ7KzH*vn zX+>3+*Le?L&lPEmuGILUpDyA`GIH{|e?|&5dpE2hFQ*6|??eN3U;MH0bUyc(EdQ3Y zR3}x+|Doa3nIlj6kgF=A5wG!7*s`>klJZWo{Bzns<4x18(9h&To`pz^HdF$0F_pFw zyQ~7PRE_;?p1nd*N0OfARM;B&GF-IJBiAJoAYTS|U7?I+C{oIhxU54?F%*-l&eA4~ z1GUHeO@!^VCXfe4ptLGdD5t1S7FP_Y}F@ zFpqix1q}B!`meeO@uK>`kz7^(8Ept8mxvXoDx4_Xf~^Qa8F z_3H@Fy`~x4A7u#u8uwxju4?J8(#er$%f*mW_DuOQrLyvzlaof(eAjHnuXdp~NmmYx zVo}k+8l}>~LaZfby|&hsuQm^6*J1Sq=H;M~h+b8gvG17`+~>D>j__p5Dkq@+ENCoH z_=Cv16JLe3aBSVTy`V9lpPBYYdC6DTu&9k>q4l$GBX^Salf1}B4kU3AAItgf+30yu z@Wra><>+rZ70%VEqAy+%IE+P(Af!~)Jl@Q4l$F?JxgKZ$mg02six=_5SQ>Y}XH&Ey zAZF9+(?a=H$O5{%s*+e?v`XPrR)Me!NuEJ%3i~-qFBKF*^Js~CX2melEQ}+p_78Me z9DU zsO^Vy-D#b3y7$e&39`RNhMl!Lt;rUOzbYUg`FL6x zb9dl*_{&xFEp0q?Wv6*|M|gTFVsu@2zIfJ#hK;I{3Q^3@VGi&hSTeU#Jb{AtsBzji=&;h=Wnif~TXDb|Egmhl-B;Kx5SA`U zwKKb)$49MJ7`Z|?`2!p#-a(YAAjBX=N`OE}js=ho0)n(iZvtxQ zEk~(R5+D=_O*#Y;2q8cc$`{VP_h0{d*2;SK%-(M@vuB=p_B)w99kn5=1*XFf|EmA& zw^T&C&Pqrm-bsbP8*3e@_~1AQkzg>YxE{An=g5BGtH(cQ>2zgh1H_-DIH+s@X%?h# z7xEe67niT6(H#k!j3QlB%}|HcZTg%qx7Dc!HX&1oWO2@lEm2nSr#p*sl}=|A5%p&YY3h@3SoR zFlhRoeWCIq-~SZEIBvMxTQt$czB)~QhtZyFjd(JozS;)D;n(ExVFO3mM8p0zNPr>b#qW^F*qjue}4dC0NvnGVT1nnP5i^qX=rB5KPo z#_(&ftiEFtBY_q3_EQ#eo8+!VX(^hbi!LO`D&Cns@W=2)wH1`?L$gpwin;6`t;G5t!dpA4m&p} z46EWQ6*{Q$eoEOp+n^6-GI=i#=Tlz4q=&|Xx zle-rtxmmf3n4Rrdg}SQj@*JJ@@pY#2L3LM@ot8xP=@DCArVs_7606zmk{kS{(6$<- z6+05)80U_V>!zB_XB?=x?{|HMDXZDshb_jh4L=o<3Zpll%}&ZoDN;s?*$$x}7MMiY zVibrEEEUhJ2n_oL4^;wk)0wPf)`$}+hKn)R)V3^-`=e=I!kJ64Q1ef-Qd`qg+nck$ zwy)N^bC};%Wbn!0Q=F382YKsz;Z{ZIYHbg72XhR%E>hifSViNLZwqfk1xI0B@9izy z-)?(2hbv*~q6ZA~#wa1?-9&Q(jiLj~Jwx7L^O$(e&Cakq? zNB=U1{T{g#vyfA<6{hkf^_>Uigx7q!R;qWHIWLur{8U1GVD z@-}7p1yUkdH&QVCcfS~!_1w62`-K*6+bB`jr~SnpU17ja3Q;wt;xG^jlaCJJ^LTb!zE{di=-2~HwiZKDiT*M zhfukW9@mFiq!iLz2eEh;`&Kx{I4;<{k2v3Bt~vU^QAPK z4tC75vu>`k7QQq)I<7v(U@p;`Yy3X4{QYHv;QVIJhgsdzYtaPLFn{X4}Ih>|FA6>$l=mhay%1s+TrGnDnJp*U@SK zrgmDRf+^i|tq^E!9Sv-rFtwv3O)YQBKEH zUZI~>m&cZd>_T3mR~sTwk7yxc53E@gvTUzaPTYAVb={cdTI~zN^QX_cDuPddRhP9& zrK>(dBL4ZB(}}C=YVqfF>z8`xt{YY^i$R6eA8wJum(>rE|E(yKyhMK_#d`if<;+KEHoc>F% zsu>b6L$@xHVfNOH#wy3zmwF#8O$ht->eKKhv$y3nJK1cTvKKOTH^X(w3_YRBJ_X1< zq4hf_XNY`~3(bKZLX}}2Oy_vdX7j24$HHdomB0?#vPoF5C$Sw(5JW4@O6i{jx3N`@ zQ0(MWHr?)gt@=}&itDj*tf;Pu$(V;OocgYc(fa`J{v*b{)7v$DFe--oEfzmAw?P!U zOW|_X`OlN`e;M;g)EzOVWOr=$BfW*8B+$gcwg^te|L;}wV=2pTOQ&PR=N{ii}q z)++8bm#|NKD-mgZYdO_X^xRDr-oDZJm;~P+ zh5+V9Q{)%zZs~nGH7H-<0em``HdOxR;-ik!Cwfqo(g4hnaLQLn%Y}|#vL^VX? zc9ZE!hU1fGc81_ac5Nf8*|mMApGJ4|Ms2d*9=vCuzCNe5I&}uHf~s-3K+_`0wcG74 z$JR}7wmrNK*DBC1?2F(Wi}vqSpPCyPB(k=esIpFQ8!th@P6S|`4JG-OMVrpT4@Lc zhB`$3H7U`ZEGk{pa)L3bT~if)ftnjxpxJB{6L6(X(Olb(aOKGDZaE&qJqP-MF{LLDVSY zOEj4r9SJ(|asMnTcw|SrvajvKHPW`PYW2aS+#Bc2&G(!!gS;a5m40~@d??f9Xv?B zl-eo%h1rh36MYlEK5CS)?bWppO-m}lf>z!?=48F zRL3}j`$3c*Dv$*9O=Ju5Y9Ft8Cs&k@!?q$9XVIKKTBk%{IF-9IttqcMgI{eG$2QFE z$JC|P1pY++VxF0xZ8h=#g=Kpm;q*kRUKRgNk#sAcB920Z^}gw>r#NlAZ+%AMCBNt# zOaT@__(d08)P2K8Qnj-HdCnz%HJ?pJa7y9;5zyt~@c=1$J`|fUXc|(ZqtaqHF63|y zBr$OHS)*!LlI*1bQX^kag%X*+HtsXfv-4N#!v&-OszVT!Erm)^;>%Ei!u{cG2iA5! z(;kjc&g3hBmbB&Fs&Q{8_&@p`!Kt{le&dorNk@b}v9pjcv<#3hv=XZt`cY-!z_4EQC%- zf>J<@X8`6S>}+Vu)31@c=r1aI+a2xZQ`+UEZAVmhFK3(IfZls0HN zM>yf-F^&pv!2g!eGQ&oO{$je%3sJ?jiV>d$dn(mSOhmkk1>~hO3>Lh`7b<3reB6wf z1Rj#TQv%=((%gL25P6=<+x&IG}q1{A1TXP!pCYBrX#d_0#kAMuji zJ*13OUQRe zq?m}apgqzurT8O<|HQ1^sE^-f!J`8aoEXOXBd*)K+dCOZ8+zOAT|TaJbTk<@-L>R2 zE9`gko9U{ms52kH|1MuqffCfIN@Txy+VKXs77c7msgbJ=wKNGZIg#BZs%8pd!mH6+ zz;R7edY4g%_tVZUwoTkEcyhcul_>^LRV(*AeA(Hr()k`RTvlaUSYdP3Chj)h1JG*F za?rB9u)6x$*`98nK*Sp&XHM+HL>qV0fIjG1;QPvM_ZkC+4a-61q)h*7!&jVq@H z5yKvSqgkc?+%+JwJve@YJdzcZNk*8sdM*~L$jUUUj)e^>0eldUB zYtn)`I{x;18im_d11I^Sn@7u31yko*r{iMmTtjFvT!V~49P0C~<(|2&q=1+}RTxKc zo_lP>?ecv=z(FY)65_$Z3OT!5-f{Neg3L`q2)@|GvYn|b1(GiAlXLx9D+aD{#M+u= zEk{g-XVYLr70U2gF=Q!p7)Ne zps5t6?tSIZ0NXIIFJeq+1?}glx??hG{0g`p*vx?&lNe7IuR}>Ti)u&~x=MFxH#8eF zAMH1*E3DkO@-$R*98_18H&~_M86v}awUZKR(tdRi^qMWx6?gVe!!g{crSF`n7_Pyl z%+?;5n@0TW1+BjbpR|mb8hXMUY4J?ipiU;|h6w3wOPUEXeEykHWB;GP8i#{9%gzjW zrHUBCJW~|StVmv&x?`|%Z;#XHCH%KQHsWc--S&5%g1*L~uy+_ynBNg+W0*e780M4KkLmG;&Q>8=H*Nl@Gp})ChyzJtKH6nuaqt>RP^WzK?wgSbyy9PdSdB(V{<-%co#F zxbq<~T8WAshVs+*AlKJ@Ucz!U=^sgZ>JEnPm^+fX-ZnV`InCq0(!>R@-Q!zR<(jGv z%DNJ@g~-^RUs<2}pD6W!s2Mv~1opBB=~p|~H2=YBD9j1FbR6y}&Im*JX5t`+dYy@` z$izYtSN=Zd&N~-5c)rx=a@yjEm_WJ5OVo8gOSA15MbAuQzdDDjkeh6c99{xzeXsY( zYF`^E<_%pQQG3CJEebzuGc5UV9B1-st20PAQOf`+k@}9?O2&0Nk|^1IRupd~Q__52 zy}afzYGokW9XL?)NZod7N5}_iz+=E;QX#96Sfj9%<=&~HS+IF;A&lWtN`aOLnrr3; z-`}r|J6%ZPvw`It<#eA<;mLn}+ob-F@ce|~=y3rV6&`EN*;hIK+T<7K9aQRb4+3bl zWte7ClMXD8a*lKf^_eP|wX@u$yQHbMJ^+i)drfdQw2m+Sk9XR8;-z8X{Ns~OGuz01 zZz8tAyuqyD6*Grei@8TK8BFd7gV?8agsm{_xt_nS7$5nr{OIT!np47Qt9YwQ-HB`6 zCIOEJGCF$K-s*Gulq`up523dPMaJUy`(Lu@`ey&iTS3G_rEdxVL79b~m-8o63Q0Wq z`)bB6p+m?_zknr1wmy@28c~1=9RP1LowNzI5Q2*~!4zM$5en33eC--y5b9m9yDGkA z;eBAnP;d+0HD2*%%%cZUg8-T}ce8pe=%;4*0*r?;?6nEwVTyx`fRO=!>cnXW4pV;PN3JE$YHJLM$!kY-7SVe zTDcngmkxYVfRmOjui$)7ki~l$2Q=Xnq{Ly@k^nN`-rTrNtjysRkgg8OC9d@jvnFe% za!Zs7X-9Qyb${4Xmr2%2*1CHoE1>4XAnK3f0=gTVf-?~uTF>J3B7ZrsbeJag(xhpq z>v;@gS_ZL}v8qhtRLv}fo6~bQA1p-o7S%iUnR082u9qd!>gRfI^Dq?04@2@eF(#yXV8y z_1B8!{P~($g`Q9G_LJ+>Fm4hdu65^Wl|JLv)Pn$JgC>6t%5@$|_5D-X`H;EE7 zf4&_x8}Hx$gt?G>aD+_H(W^Ull7|xi!k1jMo!_cG?T;NhyHvdbJ9)jbV6%R;8@%Ae z!gNIsMonvwZoag!e!=bG?;Od3mpYPcXMg%+@2_V!Cx9AnRNLTcU#gJD%2v<{credN zoTDi!%W-B5i3b;11#Jf~*4nnl!gjqkZU_IQJ2KYtx30}3gWqMK%F6 zBR(9U-d`b`SrdNj)@1NG^5nJqGDu_wdFmM&{f{%!fiO^W+64ib@rCFXLck{>bAwf| zwVdBF(_k%M5o{XQTX<(a-Gp=Swv||jyX|(;jp-&x3-C>qDqgW;?rWuow=w)V`v&*z z{FOJHx5IYG{N6T7O-^YKQpU%+wdS{Qn*w_J+bZy&Vh7AH^zu?OB4PV!`udVK zAqA5Db7^+|D)Jh;`2IC~*WM3RdrUG?d{wW}X!XLA&Hyd_{kp94(RjPs6CVu_?qtbJ zPIrS$4-o}h{i#Epi#{q!CH6&}4*tDWp(9?%o=&mW8nE%I3tt-me^%*GF7}X47t+fR zH=fG|{8E-O_IoK^AvJpE@isskRKY1rdUt~an?RG=DT$1_^>9e^X$YVILOlaX^XXFR*rUytA53pKz?-UZu2$sYiQ}pzSd023 z^0k#T*w=1>6m^Nfp{ZXU*HYB6JB2=HI~3jc-&A}W0^!UEA64yK25Sf|?(rp>g{;3W zxQtC%4L>PGyQf4Ns2`!KM6so7Y(!vg+N?g$S9c+EGam_~^LmzIh>l_3ISDah5I}SJqUw=NEnF+z2 zqR$J!zvw)DBGWf&N%UimySIiG_~0pNAjZ+h-f#vIs^PCutZaqkwbXZ#K#H-TqF&Pl z$VB2!j(=z=$%YkvrfN5rtH?&N;pcqrs?tw__R3u=%Ba#VM96d*{1IJh^_B$68dL@k z2=K_;H9fK((KE9~E7T02S6p)kU(eoMxeLuBJ{*oEPfB;6{|`20L{rX4a9Rl#YnZ|Q zd2C<6)~>C0hPY&-h53CZmO?hJ9(}GcR9n(wO!F*do${HgTs=PQ#YqYnK3~dX1uS+n zYyKRpO*o{&bG>X6=F|;1LJE#)5jyqQr{E|{zQ{7Pg3+Wo|2i94x@{Kt zJt8?fCA*PJa}{pAQt!76JFOtRr$@~{V0s=qIioUq5QtOKNA2GV4G=uwn>!*!bxzmE zXF$g!_j1!co^ySsy^>$C;o|C8bdAk;q%ox-g*WZp>Vp8mAs|68%8{b9+ejl(anV z`>w3$I+AY!$3LOKp}*OszLJJQ8LapqSc@Y3PM+BwEf8>hDZ6N+H`f&I+F1ng8;`Ol zfVI^4`@r~#kbdml>y~4t+3R|bgARER1v@9sCw=@85`4>ns%|fiNJb<(@v|4hi&OXf z<(cocnqP>T);0x#Fq(MAc43g|-1S=@KMUi<6qsWmZPc92)+5h`-WlSY6~-7D>UBY9 za@RtVA)CBkKB>@g-@kAf@o3ccpxzU~lecx7(I$@`yKYZ7{2N&KOiX&}@ge`Ntfy~S z)$M%roy8DgX{KvJCFkIi0CD&&07 z1=zup%RcVjl6|~r;HzBuQ+j$UI<8T~%v{eKjKmcQ%OR7TrYkV*Nt>0aff$0gd#6O` z`>bLrzbK~_Vp*f^h0D-lp4omb;{h$2$Ww6(?Em>+Gqu-SriFgHN0=BzV91+a-h|%cL^~fFm^2Hd<(yEib(wwJ6bNu$Org$&=-s_2=JJBEVcK ze4C&D*dL=r($@Tr^E*!cB)fM2s7)u^4Y}Wz2Klu3ZQiW?bKX42EeDuTN5HFz>cASsie)s{)BFaVSJT!a(qn5G|X4R$*QF|JNv-z zT1tHKzledL{G6;?ivO#c&X3lrk()eI8YKd)$)yw4^<}=bm$2?Oq4^9wS|U++ShqCZ z3UG()cz+mQT4ZfnmiF-%Xgo7P`Zro2KaM{*<)e{) z{znS_+R1M{R@&mt0W_Y)h$gE*MuvZT7!oYk&Jju0n@sn3srF6!ntOkBX0crYiL1uI zA53(MH1YVfypjDTU6f^+EK+@QyzVbjZx*IysMydPkee`4Entx@_*`evPhdp!F8ltw zQ;e^UKWF=wnA}wO?)nYq8r5LXgu+wlxReUpyfW@TSFioJ#0GZ8*y`l)1F2@@h)w%s z(8eLi3>K<+IS-)h^7c|QALdm*o)*_HdwcrBXb*Z4*S>v;O>Rg|!MMaVICLnRAfbD#*g!%JZtXVQ0<6VEQEckb7`_!>x#|{sJj>jac8(lHK5{}#a zP^2+0!s%e9J#gPD_li<0*&*#KwaYb}-NIf}=#Yq3h?*OC}TC*wcQ$HWA-B$@PfdUaIex*u4Yz=pzZAcg@eaE4KW)t4^1~&(J0D<&VXd zSH7L&aZM`AXGo|JjdmiS_tQMjp=(kuTdcVKyt!iV5j)Ye`xBT?a;hV?a$|L$ZV#dq z7cAbFDXd+zDq!q7nSB!)<)1pYp>m?qVwxe&Q6CU7`4bWbFMI9Vus6Sb)63qX6S+I` z%5t5bZh~EVU|d+}n$i7hc=J7fD8uDPgl{*lypSVT4`dqpNi;&I?!~O$Fm!8PhW97F zz82-)<5Og?s#&Hmo1UH{IqCd0dmNGDUY{SzCo9hD@h8Y{jx#RtdU*%`gHisz)86wv z{h+|@eJE$ar~IC$%W@E(X5-^?Jp;|c4?B2YObK4Ru!d!OQK~PLSf!||N;p<%GFmBe zBSen3ok|^hZu?9S6F;$B(iEjG=l?*z59Eb5u=^}Oa|zKAd6JDZVc@rydSCs^%;T9a z-`)v_nfde$Y~KYU)S!q3nqs=R!Q`X+$^sqR^4pt)aPfX4-u;l|3zDv@!p$!dxY#!z zY4Vr%&8nSPi;AEJTV;Al^g!$0VUK0f?lw##crNn4Dv+7&CHJ_jBvPMnZiVeE{V1nz za8uaeU^1dN6aFqX*D?J1gKB&dzTMlX2R-}(dDBiy6Px^2)4R5Ha9RJ zFgY(WGA}YPF*zVpN+3*WbY&n#WNCD1Z*D^73jhEB002lZ0RR91008C%0000000000 z001U40RR91004La%zbry6iM^<3a*hNyKtpGhso!d^2}HH?EAdpRz2w_&wTTFUg=F?h~}`i zQ~aoJ6o=~bN1>>mS9(yNzY69=!vAM^M&VB=-@KAkDavx2^q z@0CuJ6v|#ow~7ZvOK~1kw5>GY>sKFyLxumH;8b!c4qwPON*3Q}RrdAOjH2jkLG{_! z3d*vom6BIsR<$WMQW{R>qaP)&uSFE~#PW>dN@+u3R&(*Dt0l-+uZH%0#9yUry1v@0PgHzqH zF5(N6C8%cee`c-uA1K<4)b_ff?X5=A4f3}S0se?+d^%z_Ef{fy9;OX-P1fMyKy&2> zR~K?*p`$^g3C|aQ?*wi-#vk_nbOMd`TsgP57Yulrznp+`#Wmd3!TD-G!)^Y;U2O!; zH-8IfEi-W4aTtZ>yx6HI{-Z$+#o-T5Qnb$8)uFvYl8h16${aWi(?{k-W_<$LErsH6bwjnESG?Jh@d#1h}H}Z z^l(13?ljj{&G}zZxphBAVFvt6MthGYvLClF{Re2y6M<}H=EP|*)uFeubJ?4n->mYQ zbNaz}OG0(y_V=fr)fNipZurs`gZuQpS^ib+MFp&LZ1)6)Zi#U@F??Sl`ea8RJ)#rXL zx|J%DGgV@_jr>57_E5%vvvrhU3AIU1vhvOMU`>YsOmbff_L7l1S3yCWBxTii)>Uni z-+?z4EJhU`(uMLl?Q_KzTL(1fxxn9BREkD@z|^otjMH-0p+6w2$-~B zF`+QQ4GE zuHIZ>`DxC3fb&bBZC+SGBi`Mj)=L~KsRnaz;5J!pZe#MOSa!c!*=;23LfYPcfO9T^ zMz`2DRcsL{#xkN|VpJE`77S?DMWwy7+|@|J<~}IUc!f$^tZu!-t^*&!O;QT9xxaH8 z?dqnZ+KCK1N%E;yUS&kX$ig3-&ESMGPNbY!FOySyo^>Cc97=suQ}J-U%8RIR*$ecj zY!hqbM<;L{`jThNwb2$j?6=WPO{f5}j^?+AjXrF3(yV1c>y2DFMJg?$JA;1Gu4EOg z#4NWUXPE+xVTf<)+m|YAQ*tkh9*+D0tkD@cztFjzl>X;Wy7_66^+>z-TSzz%RfT{R zRCdo*dNH_(73)*Dw7xqyN)}hVWj;fVG5nvSz2#Kxp%!BcTm!kY z^CzjIMWX}(>2iUhSq21kEMGT6nHA< z)Ov8H@%*208M@KAWl#F|uB~7Ad6X-R+*|^C$7+&?@(oE~fB%cD5J*1N_=1;et@USHn(ZN-FIdtA z7|PE~IN9*0FW95h+F-2*Jk=NctESxsc&|ogErF(en(>;kA*OHZG@y&p1++2Hh@iEn z%&-Xd2o1%mI;T#LQq~n+`#DB?7^FL9;t@q@{oXX>*UD|p&`I+!n9c)#tdo2a1uZ)! zBd)^QAG#owXMnxy-O5Zob59gc^-L9~AmiPGNhZw85wI?KQ2}ExAtMi-w}lS|HETr= zE^+mVCt?{!BL3GY0Nr#g+L9(E%pxdbRJorP1Yq3VY6C$+XSTIg@Z9^-w7e1iNpwwQ3f6v$;* zqw^Yu@BPF0TNLq&;Xt8BxhF40_vesR01zy8bMd=OT>&^^L zf=0^_!+v|Quw8p_Bde|M1xG=I%Uqe&7f+xJNmX9^$jnGDDBg02b?g~=%pQ@;VkN8L z93s^Got5g;dfbXa?FORMX>1b7iXotV0fK0g6w5o(wNNwMfdNK3XsuD+>Qrv5MU93{ zv)uR=B|e_Zg6hngNff2mB`SKhla)fZ#^lJ{2YaW;-<$em-A3m&Y_;-f@SohyDbKXc z-j_F1`o3RjMDw-QEv<8wA<(FgF2U%uiGJ)%EIRk39=4de_)&vc@TJIu0$dSZ^jaoFihYxzMmRs^7Ptr0zo$ z7^KBpkD%deuFP7`chH4{3Y;-!xM1b@IrBPHr#b(z@{m~TdI4D#rxttC)dMUn!#)6;&IL8d%yqkDAeF{)uc5EfsY%pDeE2rp* zWi;Z^3u)b+zYtF?$1!H~L!jv~Q>tC9WXvSPxsniX1USE0b0Af2KTcY=;tVcP5(u&x z@r?HKHf?@$#nCDE4I2JnR*X59OHuO^8OWV(h*b?HM2U~2`3UZ?uH^(;nD97dD7eOY z3`3zrK|k>vo!PZdOXzOe8x&_?Lu&=+K`B3>uw>}WHjHmeubyv~p+!EwaBx{9?7yJ3 zMWHrDJ+)Lg_ay9j%$3;y&;GihV8G#eYKq)Yr@fa@?P};yr@c|%ue*9e6qJL2lz?Wt z8`-Glo-FpMoX@P}+MwMrGnWU`jk-;Dqi3*t3~6Ou)2=9x@z8mq6XWR7kP9Azim#0W z#E&UBrN)n=;HnDTot;UBb7P^@HPC{lo&V`AtAeII0P35^mFX0?Ma^#~wC8kOZ}rm7 zgvpa}4A0!`x08-#R-TH1i8yk34BvSM5a@L5wTq5+QsB=J7v&$M)0wE+Y~4XmPbHBc ziYYLzQla%9sDdW%q9nal>(2bV#J7Ho`44C9dzmv$=Wz7U z!g}GhdTBquiuis8Z)x;)0_~`CjEd~OV4d+}bSTNebVpR#Gj5^PM`GGo>Mf|jplVJB z11HNBpzYZwM|9+=u+0$o`JP1u1BR4U>xvDuBiBdd2ZFYCWc1&EGOt40Tj~CL$c&fP z8SP9fAsFXfH?R3Wpq;J^_Q?c8tQxE}$qo%5*c%|v@n{+~&HY+f(~KK;xgoeWj464h z(ZW@)1k9RNv^g0&&OIQ1T4NgR+wTFZ9+;C*ppgNU&P?cm8M#|5CU~VfmaGjOINeK- z-(rTvVqUPe*zI0*T%Lu)t02n@ziwm0Vs-~t28y<4jm7SxN@0A+0iXD^Y5_gEe4f@E ze`3|rYI%*+!^`V|MrfH2(FyN2G zYF)9uwpbF-##q*~U^=)%UDq%Ch2Z@MWH+M!etat|py9WpG=1M1t7U}T5(2XwUKm2l zVQpMeGh@`JO=1`?g3d~St?~7pV0jijX=1{5~ z3e0jTrSjsXV@v@OZIVWFYFe^ z&DBcHgjD{Jaht7j*P>;`0_ebobyh*mny_9QoYxwWFss>POT$-B(U6>TnV%H&9 zC{XO!QZOK>m`Zz|AexHMj)m4b?bW@0-4$DByGUUt6ra=FzBMU@J|||D3Xod}Q6!?l2DH0%73r#9I`* zh)R1g{NyWM_hu#(ro8uU+A=j#+FJut%cB)077U1*C{m1tBjJCv#io`!<=Pb%uC*{8 z44TISOk&Q>7iitLR6DAYtB?5kNhT@oFaVCigF){i zHIim?ZIW*A^O|rtoiy*i{@cn3bSSg%;RQZ*db*dMZ2w5(LaJL$bZg0%E`SSvY)S{~ z&ZC-SAMw4C`s~AGc+MoyQLixXcA|8|-I}R*mxR9TPD^mxF0GU!XH^ zM!|qgCvpk6ozAHW2WoBa{(iU2b&hoif?}zw9~4nS<46Gln3oA zFHX_O199xTSLa!yb%gTLU!dWJ!==Bph>9FlCV@B-pIYOS}dZ&D;lVd8S;N zMf78;7c8yQgZ4=1e8T00)W)sAJQh?IepXt#nnpvo1tb^NIw1623q`6*}IruxVo51pfef#oo<|qQuiMl(ca-t z@ju!6 z<@O>!^|Tm0xIdfDZTfB%(42e0U;BO|r)GA$+2`M_Gwco$V_tBf3IpkRr$@p$!e0<% z1Z)0WnV({hr_Bcxn8j8Bd>5=;;>xqFkf3cY3kh2mvAoFp)o4xG@~Qxy&*&medVDi- zA1xT4opGDzz<|!kH_Z*!DJCxEIdpD=f#BkcDDlw;5`uX(I4>GjMwKU%Kb7keDFjcW zA!a~k%#{TL8lC#D5L^erv`OqLOI=a5NjOKkjRdHAwn;>D7rdoH1=d@#4+7rK!B_*? z?aiBWLuh5Z^RzjCRR53&CK&|BtW@zEt*)NaUR`gowO?oCT+FmNF^u7Ny6mJ=jUz4n zRbYVg4P;8@-$_eKC@?H0iW?8w-67qYi90E{lLD)lMI#gfg=9fHX+;|aX3msBM`G+P z;}9L8$jBVk%3JzlSt1BQG>O_$v(Sd(E%O+iWaLn8ZO%bv@-^r{ZP2Pr+9}Ja#$(X9 z$Jcu&d)ZiIV~ig^6p~>PWxcEnniF53+=5K!IZVxV0TylQ7|EdW4A0&J9rxx;0YkzK z%FBsru{H*Jg8)>%tZmV(eMMIM8U@IvyYS!A0AK;3s=l*rTBOYSv zPIJzS-+>BGzYPIYEOO$?3Z~0)WmcJ4Fu*yiI4`1=dINa(KD z_*ijUP^_Z4g?2nmo1?@*5E_3)7_k0%cJZ||?25Ab z4zRNZdeNThx2l$Sstg9(Fu-Vu>cp{LbZeLz-Q#g7zw##&ot_amq8AnIslXV`NLTY0 zKjeIXQng_HqMmdGX~ELMQPx8E5|g^qs(ZynFxfl?_7af0F{%R%^HYghGlg@HU0n&G|Z#E>A2=BR6EU-e^Z| z0kU-vhr^T9rTvxq%U;bKoqB}qHS~3DelJR?M$eAO+Ctd!A}9p%iplPxYOjX(U=(W* z&S;4+&}zYU%H(+ReR#DHVep^ZDc+}iw^Q;)KrYW{KH54p(XQZRQtQad3+7_((cm1 zMOW@en$3B^FDIlAc-=FnaE`TU;hd-OyuS?ow6{bVIL@_8yTd08>{o$-rgf^&Khs^b zpx|yRs|E}54-hO)tM#<{&Swh#7-GpLi-&Gp_}bOjTdBdF@8V3ewKK^ht>J5p3g)7z zwyo2s(V%jI{5~U( z4dlHbSbG-C=su_jrAngG-VfIDCm@dp5u&i_JUcy)Gmn(TI~m3nf>N)Aab?~bOQWXD z6K~-!5%=MzM+^9|U7}fIsZ4$aW^Yh^NqwkgB)nO7RF%5dwU}|WG8h6|-a%Djc@VXG zu6iOKXsY>`(3lI?y4j)^4Xm!f_4s+|sOkav2q4#Lxt%fC)j<0iHw!PdtmYK8PClyB zBCgd==e1#Q#hu6?@lqG02j$#U__t10cRdgt1V^p_=(}W z@KH(`1at3in6ef3IO$wU{7`|*@`;7Njxmlf@VFXzZF<}&RHwLF3WBa)!I|n|t(5=e zga3SvD(Hl2t<=n4rUPq#!CRW|nnOkQE3gb?(B=W;E(M<$R%tG6{H(w$v{E@SxQ*SY zbZ2pH*=bkO*l5b7BJ5ob)jx?kk^djXso1JutDBxG{vi#)!2SwLsY6f#St;_chEO#= zfPtdfmQv+D3JlhCf>2b9-EEdq+6fAroqG?N3*LuJInkGB+JkNuvX~>K3?3cv!GENl ztw-unvzI+7%AH5nTI~+c*inp4EVr{G-+5YDGO2ylRmOYR83P#OGAM-H`;)F5JtY=P z$tKwYlVoQG%@qjpux3{S4((DqxgNoe0q;-<<_j(v!*G|yL5j+rFt}9uJVh^;)PCOa zwiO$^q9kJxoTB`UapKW6YIiu5-8j}zi-*vvEP=5OgZ*bKhf=vpyQ%iIr4|q1REdLz z)uHnNEtgX4(=X{rg89}PeY~v*m_EXfnqiG+QIFf6*_>+4(_h}06P{oJtkiz7(Cm;3yG${{h+$p;`Z}Q)$B-1&*&xk^pi~hsE3- zV$!Fts)J4!D_rMqp|FlXq1_?l{wG!;4{?aca|5^8?Z|DKvNo;V<8TYB2|KcPf2#&nwpdTUf)OSk!VD-ZB@};9g@XI7ESQct$c)QTTZqR2uok)Ge&K5s(X>()-8I z^LwhbXhXjBRLlMzL!aI%@SmJ)ylGD!(a3{tJ-15egk2R$sXthIeSRM~zoxLej4EYu zJ_s-T!QpiYQ;*5sVv0{BFMTDTYfiQA?`FYD!I9S@RcjG&s;FH!W?b*!`6 z-kAP6-QbFUJsV7EJE>EiakMk>@-=s#{D?8^pDO|1%P6@^v!6=<7lUAOwCh><^YkWZ zGCNn(%GPo1=Q79q3n<{*9Wz?3^Yk#K;{1u`{4qlee{Sr2 zIX8k_RW4D+F{Lf;Lsgj%KjPDlJe_p)q%T!fX8QCtJTo14<0E+G&Fx0iHS_k!$K)%5hTZJdJkb#t>{h`p`$+ z9t7Nvr?LYce*wwwB45r%HKXoa`np23{?1>BEAnwC-ep3ihZg;ATy`bJVj#*Tq@G<| znV-UXQKg3c2{HCw8`K}Er#$?;&$hmF&{18izxK6HAiDu5N(NmC2x&7xEVfNsOpev` zf=M*;W?4fl=}1946k%|aD<|Qfo9Ww{&vfkf=T>|85DL%R+(tuC`1$f99V?vL&UEI6 zwMQFtFe}Y?2u4%H-b>YY#F7Bs$Oe@q5v=H%2N7d4$Bd*FW7Uxa#;uS?!>8JiyE~1d z$9^g^o#B)#TD!$id6C}vwccLpc{-N8!Ko_e&t*^qH&aW-jqSm7=*dHodl%;x85E6$ zi!X%gv|yt$<+5gJrSc+QxSt0fuTO7!te4hBwY@Jg(~8MoJAVj>mRcz_2{)3&CAyJH zBY)d&lZ7)BUWj~JzJDdH?Q@5!mf3HGXsz)MAdkIavDJk`IYPta1o=fB2I3aHG3l63 ze(z41W2@YPgFYhILRf4pET#?mZO?u0J3Su|oOv+u*nWHul?h8^52(?@;>Ac+ngQ?4 zFlMx9tKszG^nOa1sgt}JBNqFJNapDmkCFS0ps+9JMJ-FTNtQ7Z=L7P?31=@gGh*4L z_vE*d>Jhdij+ty1BdgPkrdHY@t<$k9N>`H*A^079G{3T!E`5w?ul%sz`mRj^dpn&# z`&pl}G3jwu=fzSgC3tRy4BLvOZWcV8yE)qL}&2c5;W~|dKz}LpZ6WjbTG*Tpy=Ot zEQNL4On2H9u!8l#M3!5{Cw|uMOk-B57~98zDRPGbBrkO8X=>cNZi~BjHDx*ugYcc(njlV-kO6y?n%MVABSzCcS^S2Tu@^*^swrIg7^*`ha)Pf0DDcR`G z#4~@;)nkR}S^Te7s8(uD7&JE$_MY@%R6lkOIWxGJ1>1+=ySFs%Jf5D^Q|TVxN^h_a zV~5S)&lj9Zvo?TDJ_VK~Dh$l1#=MI0Azce@p)BebB0;sYBU4o`vV_*rPElKk_hBcvJ zEkSSxYID&of{kZ;i`KHihxxT$$Fqjr>-P<=U~O-~ehUobn$(6GMK4IduZ!*J8-rSgh#cs~~Ma6H}3s^&yIkWpc94nZU+H1cGJ=37;e$xxaz z(`Gv)kM*IG=xx%IlrK|se?G^c3csW2ICv}2Xy3)KUv|%F_sg@yI<0d{a@M(eO?vd0 zoizE98gb$1jg)ATH~6C&P-Qwp4Kj=Eek41q3(@n-R0y|s@8pEX&a^WHBpB{>+s*hRLqNTrfPl_>2g3;%6{7LABuE_(u@Cd3PUY_ z77C-oWpdiv-ygPk16P$A@X1(^yHkc8l>49Wbhl9jYd0%ZV(c%5n9smppBRDk=CxY9 z3u0;#V}UUBH3(lJ!4K;CJf}VA=6)-SW^Fi3@_?0SKAgOiGSvT0e`e@v_0f*J2YAb2 z9W2?Kk+jwSACWtOcE$EgMcl^NkRq5;F8WT_Gtah8YI`dXq{v%#2K^C3B`!}G%=8Q; zM|WC5xi>|ZvA4%!Xs616dNU|*Qq>wS{ED||ptrMVvG%B|m=0hsIMvL~v~Wvrx}0Q+ z6+_GI1&^4p1; zS&y~cr4fQWzHl2c4ve5h6_uaA;BTe%M<#Cm21fOP25?iDRV}`DoISybgRguGf2Rfq zymAm|8~_74N;aqMU~vShmyIicHg}|M^X=l1bThY_rUIp4+X;h?z__Z$#gWvyz5=J` z){&H|k>gYlw~TzOul|OXWRCw$+@TFq6JPW4tNU-fE*zvCnU(K0CSqWsUl+bQFs}a~ z9R}^fn8%dtu4aq-aqSKl3fs?;4!4GCi@gK(CWz1zH^$JVMSEz;&8F6Q9R`aa*bh|e zQ*@)^F;p0^*yy|rqaoDdhbqIb-DpH&1TtC$dLt1Q*4=>|ehf=on3hZ&zzTk={ z@_d=ViBRftUV&LF%3?B3EsLiE-J#TEhXVh?e>Vr#TF4vOx$*`ZzUCrdGy&%`xKhXz z#9$={di!trQrr7NmiiVO!e?<_z=!J(BYTkA@xZI;k-SCQd-Q@guAW+J&mdD0^agc1 zkD}fKE6|?92dxKM@K!)9(~F-ww$j^vG3*hqj#(qMJG_Ph_$;(zwA%AG&5RS*F4TRC zl|;Kkbck00D6*vpp?_vb~f$-(#yQ$qxHG@9Q0W6-H5L`9zWeqQJ z)Y1kmz+}zJ=x?%T?#FNJtA&Mo?7uRE-U&}=4&+*}s3SgkuQ>rzMtKZBa@!v%Q*aKu z-SKtalslHmn!7Ok2+BT>Mn}0vsiHTxax!g6J$%6hFT|pC>8nF&$TG$G6`p8{&UyXH zZH!|JIU4y+yR&sw%YB{IV)CsWEPTm{H0!qN{k77J)XbTa3wD|DdIA+5s=#IW+h$<; z9%QjwNV4s*X~fd^>Ej2ZSMqV)gPSasa~C~RB+L> zPUEdw8oUKFiz0r^{)wA`RCwhUDsm}`e|POnLaixuQ+ei3iu-3yd-2v8*553*cO6-t zIe%>lov!LV3@KlFtIf_5ay3w3o@f29{`*s$1+I?~BKTLBB*d;uP2&ep{c|5JGXiTH zVbGx!zESRe+3lq5D_ehRgL-KX4eUZuYpc|gRj1q{Q0go3$MDM|{4;j(j(U#38i`qM zqf#3;Z9k>fThK`gc{Up#xd)0xzmBF&?un9-F&=9Iy3hC_Gt|q0_mh}#I~=(}WP9U; zv=}rIdcp7fm&c%wn~ru3(rT#%9I4oT=Fe2W(#;JPRoflIKTxY>0hoRc3MF^Ov1{iq zVB@NhDgU-u8$RlEslFPYchy4+UNqqSZ!n-+U%Ap$;#=(f6u!o*hmMgx^>|tp-nybT zXhL|EAEec;h}W#P>DeCl?1niAa_iTuuqkm}v&IXO{8k%i58)2dY=1KJqz>?4d2sNaYLmj7&|&`)}4T z-HT~k-?tU-yruj1e&khp4OnMiZ9s1ng&K> z?Xot>l>hY9R@x+io($%T+;dzpFPN6%3x+sS@WCmH9N-J~u(k_6%qxQt1@p)q3#_$| z+}bn3UI^q1nSlu2qNCqv0K9T#u`lh2)6`7h(iiOEoF^4-*^~Tluv}<`Wu*wtB)uC@ zHpOVTE{y)4$R~p}W;`P2o(VQz)Z{jVQQy{b@d1#p<?10A3~#TUFq+j}!y zoX^omG|5bD?>5Y|$+xUUG>OMz|1jr@j4yJJ*0v$rW{PYvPir|Y3?)UdSeWMgGkE8# z;r@q7khKx zxr)G=C-qE+y$7T6rR|9<;8w*KJWgAT*O~aVBPw6;4sEd!(7?gSTJsz#hzGf^MD8qP zM+`K-VrVYJeUW>7EfzYVvhYV=a3{^$XW-offAj_arCFPb)?XsKgU4c6LN?^+fNyJ$ zJA4Q7*34T3lXyC+)bL^Cp9nff2Q6LAQ6QI*rbb?<+eX)0#xByH#Vqj}bo1?Hayrg0 zT929^#s4@Op=3cC=>*3;GAo+BsH(s1x4NyB4O&K#**hPw;kDe|!>Qrs-PEZ^BWtog z=Wzp^?}u8PFgLxsqBcA`ur_4G6%{=kkMrGzroBJ)4og;+fE;HkokxDmT8|6sXn($2 zwB+y`3tJU{8do9rd9XIJ#79cqJe^(cXRyU-T$Q2_0b-hc3(usjwfTCNWBaXm{Jg+l zBD7idKxbcO-Ru>4VQ*9>YOwv+N+TW?*~o{aZPoH)$BvHa31 zs@>uS-MKZ}n#gj?c#Yqy2{cASsU`D=Q1a7iWzb`>E)bbFp_spEGpK6^1-=|Je5{Ch zn~7~rC)w!Lw0e|!&mxLW=sB3SQ5Mp5ewmN5Pf|-@p4+^7Lu+m@;0sQu1zQL&T#w2Z z+)R6FO9Uq$Jm68T4{}Y~xQm8-fuiI1g0;#G3AV>fDne_1TIrleH1bA+@!zd0fJeL? z7lAcT0H1@x&ae{y8+mdxECCe0tZ7FzvO};JV89prT1N>VvT>UQ*j+tAbR_X9*Fx@m zfDy}jf$CE)J0qPPYS_abX0m>QBNRS7$P-QY<0IZPXjps}Wl6Wi;yYIqxDIBLesH+I zMu$-I)2|6T*nfM}COA+Hy48vnKHE&Sa;EmqLw{ww$`z|8Olz0TQNqqReyH_>$LF%% zvXSvBG6ROpqpk@}S%oHjIL?FHlbJRYIpyMfrP>HM6P&&G<6r1k+pxbS{bGHM0Db_? zW<2(Ss;AFvx2V0(x~&Ckiy?FvGUv-wTWN2yZ&bxK+&Zt_We)Ty6qeK(LT&qPr+O6& zSSj=(wU@QJpF7dI)M{oC#FqFUt8?4@r?~d&DU-MLoTzo_pH#W1Zrm2uARU6)kaDA; zvOD}q@o%fsP)T)+T}NgLL#12y?D5UQ>xN#u@~K6?4|KS68oR>PeUaXE5b)${TWI*$ z@AUos2J445C`Z2Ac#KfF{%jLHdjCUqJi_!mv@bj%HT>~t88=0*rxsNBGONh5SUnH5 zh7XW6P466-PdD+1aKu>JQA?da*NI7SKN~&~_;?IGeV|@m@uVKFbiL1wp;wm`_#kI8 z$;hw3G#@MWu9#pZSzTl2{@XE@u#!A8$%L2RT7|UM1|#eI6L-qjb<^`~lSfZf~? zo61outUa26E!R+ng@iG>`aUXY0Au^s2f7dvp$fc^O78QE(x>y04Ij@wdX} z3K%OFbkn`r1ZuEVwGLpDc*CF(p42M`cW<6`?bE*23}cekATjJrC;IwJ30jh2w)g60 z7{dreyxuN2kv=s%OE2aww}gE_3c;Y*HZ(3aUPHNRyroj5bNUDAtl1Ylj%BEs?ySrH z=V4pB@t9%ON4A)BbFU#2PVX30Wj@96Qx;ppK__b-4`Hlx+}d&N&0*Kh+SYDzb%u3V zXNRO!2QoUD9W#-@nhb2J2Sy!1+r?Zv3)i8YTU4lTOT@XzkFRYD4D_Aoo=NVN~nw zIqJ5$p*2&>ogP_aE%)}u-%UqRx}jU;UaBiPpNAs1bVGG7Z4YX+R#~h)Z-9xf@f*_N zousCH;P7^mksXB3=Z`njl*M0YVa4O#cbRbfPvwoPO+x8P+3$o~h7+n(_hiLz%>2)*p=+p>rNH^vKg5~R z0Phu4I&rl_r~;_$qoa{WZOsKiYC>FuRT0 z%nRi4dM%(RDXz$My12|wEY<>Hu$ccdW9=S8$J(n99KZ|3!dff{mXj;T)B5f#YrOU~ zFYP?nLuhIhb%4baL~o$ABdA7pT}x$0D{x8vLK1dDApe6IjWAuq#e?3Rp7T5>3U?_* zEVb5JEksEr2&O|2JutsZugZE1S++xKdM)>D(r(r#?dKe-+z_ngXf=w`#$8Ws3l_32 zX@R8cZV7L$Q>+MeFENAWq}XJ6R%6dWyV(%Hp*J>D=%}yM^2i43iuR=680ws6^sd^=Cqmdx5E zV9pn+v*5cj1C54AFgilpZx|(S{6z}?-lfM=o$vFdbvCxQ$o(5==jXpX8v|!U#<_}U zxmN-CNhIva1FF%dGC62)vs2b)s5)Xq*j8W#2xe*52Tj$ac>`?-sa z+kdIG!UMvG4{*g~m*-QXxtHl%^2rvzC#1@6$kpFbRb4xpR{QUxa&x;_oDUT8Rp_Jq zP$dc*OhF4SXyHV4r~nodvZ=Usu5o2H-Mx%j%urxI zfpIkrN}bA;Q|;_FO8Ze=poqMtpD+v_1G&v!>9$dw@M}i3R@5W>dlrFClo-pXZfk|y z6TmB3VX80D0sLy?EAJ}-4Lm(jj8!A4K_@;`5PPb1L`R92flE2~n(#``#9JcLmS+mg zTTi`?D6nUW%vUAyn{V)_IKZ(cT8=UO8*Addpx&f-=9jMDsM|4@oZ^n5JIO`B`vPh)R*s^xKUD|)g$HDjh8DVY z+_aOdXxv%?_%84cgHOzFynw16R5=wElUEtnz<iT-u=vsKW&X#+MSIz2PYQ(oUc; ztLy?wwoQTWaVnJbwGP1#dDrY!3kT8lL} z3sW)VU}d)B1*%3W>i%96;65qNwd+1Q53(a zIu60QRA&Zd!D&05)X8IQ@onBs$I(z~Zz%QgvDMTjeChzTh|z{YCO#1DHXA=*LsJ6P z)WPEpd^Cwid(4`%BL76He^P;=MbR3l8r#` zAvF2K4cX|$n-VgtkzD;r&w;&{ z^25fVW%H@+F9#$9J&P8cJRRd0%WW=7v4CP$QD7ES%|1K8kND>4K&MFW1(d(D7c9Sy z;N^cv?)miBCv~o;D62*MyepV?p_A092luD;(`uOvyjQRqtM5;3Jae-pCz!m5@#*{6 z-Sl}tR69?#c~)QDnqLHW8^K604^AziWhpPq82K=3O)~OIMs74gg86OVK>D?hvKVh9 zsPO0UklXkZy3tx&Gj*hBP3%1rt%D$Z`O9O8hO15zjx4S?4z07J`e)=gdjC*?p;U2X zz5Zs^dKs~MlBR$ zd@jgkv=;*8dVJpJYem;%Em$)T@(I5bqU^O&Q_#|bR^opLQQ-oYsoT>}G~#S8IXded z<$?(#)9s0L{ID93g~9tHmeZV>2FF*^)GWMc8L6|-YdtxG>$&(|3)LD|7MOft8vl60 z&9H!51&-0yqjxQSBV84Fqv8w$c2J5sb7B@cCV8)hSR-xY8S?s{AjDmAtq>!~K{JD=%bgD`j(kibq}zNp;iVQQ0v zKgIvFFW-_%S5+^UdshB=pw4#+Xs~|_@rL>m&bm?SkV{kr(1J($m2jH zDqpZ?%oGTZ!w5S9a*wlY;0Fy^!1ryPQ?I`B*ugR8Bi;Lg*J{=|IlnC@_<~W9yD>d+yk_ZQHhO+qP}nwr!g`Tl+oiZ`j)B zbW*9Vq>}DF=QO5RY0RiMOI>#cW5QF#m=T#4E3*4Rq1cXa7EhsqQh|1(`^=k}KaVZ4T?$Ha2HoxW4 zFCH$X-V3^lJF6%c>`rm1XukI8lT~HY3pvbm9)arxOdwVP<1@c7yp(fKTlg)V(q((F z2ZltJ&m8;MjP|GT9cZ7Ku>FF+-*i7mj5(##-;B)BEyOFMQlMz`azXc14KrXB_>DQ- z+rcaYQCYJ3LsvX!PWUNNIq>0S9=k%J@z$q)K*v&r0vd~Jt4)=PV`ZDvtx?O<+ zZ97d!D8g%fu2YTPpJiiT(1{bHracYWZay$TB|DiywdaBHIb{af(9TI|UX|LC8p2$C z;3a39>ym3`kVO*J_iWMDqu})a>VLtSk6!QOkGnzVFxL&shVHQM<)-V%psXk{UdR?0 zqZWt?`fDq}uN!0BR`uBz;M+mqtYk}LAdI(fT=ny6JUd_> zxB^KWXTt5P+I}3r-_%ZJv{GWcCSBLFXK)v$`HOjAzXF^&?~G-}H~G{0doj#8 zND28{I?l&Pi-3kw{6OsQt2v}8KyLkIYob3BU5J9cb7N2A{F^nsf8t4(myPJGN9DNP z*?k5ppN*xkIFpN1OE!V^%;~^L@M-d=MG|9;h?nXS8(3$mm&_g--}POo1;W0TeO1;Z zjWxcM6+gmRCFKZpR4wa3N558#^#oPb*PUwUPpXBuj7Kk;*! zdZ*mlKFGIBqx9I>^@g4vDHsu5sGyXhEHHLJX9E_p__Q|9T|m?;*T5yeZgz!JNP@m3 z8?VS2!W2QAw@&EuapZd8@tbC$S+qAawP{xtb))Fn&y6kVeP04A6>`|_oRwRt@Nw{_ z@?vrCYDu+Bxvv=|D}n^e>HS`zv|is3EZUUH{2@Ln2DGT_>$c`P-@>{%Q7EV$hs9%Q zT{;($%tgZ|lF`zrY(e)Ej6)m7`}$DDF}sW0x7hnMA5Z9jV=xvXLU}EJeyC>Ei59Z5 zKa|!P!zo4|>8+8UIL_mJav)g&Ka}oFZ4&(QC!+BiM(%SzXRML?8)W=hH#|v=w5esX zvCpONmMiolSfTI0XQ5F&s|p$;^G_yjui~A{c7o)+q}4Fz!6AZ~l*2}tHPU0t{R5sb zD)}dq1(QNfGbhxLb|3r8nn=(xQ9PTRcru4Pnqc0yVq+jbj!+G>yGDtVR$kqm{u-&i zVx9g^hto+kUm|^j`Bapr@r^%!h^}b=AGJ#4^_txQ`dH+eWD9|gj+bQk!wyizi^1Ey zn$hreY}+&)3#%LX)4=3^6xa-*JVc~bnU;1ao)jKo z*bK2QxQaeL78J?;9-_}v)Y=-v=AXv1>M3{GMqF=4u&l#oRHm{$j|lIdIjL)an8)SM zivq4 zx7Yk36<1*z3!0k(Vb2)xrk1g{}u+EfzGzwoXmu|uO$X^?{cr(Pt6(c zSv^C{2&$4_WL?02nMKtOi5wz~ZG>lkKir5+*k8L~jP_Vo@XsxpTOyGy2<-N_&}G1x zw_8S=1RbUkrM{~m6^}BS@Orx2%=(jcZESXx&M)}zANBVtLc9D>HF-KR=11g7?ml5t zP%FDYXhWU8T3Sv~2P2(1I`?LHYEPLd251Z@EenLJwB=8BNw-^SUq8V^P$e0>UOX`3 z$(jzCX7T`OuiT147J{k6nJ$OjehXxC1seNs=3uWz)<@q^T+4>lJgC`C{swIbQaWIZZdKmRX2?*>@R&ZF#Ct7XvStx` zT;v!Qabjss9@?<2 zaZ=PHnG1~;{X;%N7FCP1)NrlLKN}j-mewK*4EId^m(&nWiLOQ;N7L-)wXfKFMc7#S z$^9ikTgUF;$!`xF?cH2?Q4iF_tf7XNwxLZIi~J$+oo_deJ@4*w>zY~iU87!ILl2-X z0N^O0<1Kh4;Vq#hmB6Iz|Mp(OK2r(DEJpBIqDwLoE`aBJ&iQ@Hc)SE{_0 zNnnl<0Xky`ks=e`oMkIoam&8rbCjEXWEd;5-^Bl69yRJ@aT`g^wH2Z1qiPk$1^IZ> z9Tn!>2h1QgP9F_tRpB`?od0oGP$jOO=>#BAliLQXhLZQzagjYxeJc;UB=Gq zyHTm$AU)pZxSM{StA^18xDAP+7AF1a9Np%4(gry5`jRW!fb!*mZ1I;cMGvN@@SOQo zU2VH<232%RnsS+eZU`>);)&P0{~!M!QcXpE*_@w(=SWV50U`-Pj|k;9J19^qNXYJ? zfKCPsnv?Md7@UIu&+B7w-R`z951(pIzF)+aJ?ai+r8x27V%DjCRy541fLMm{)VDSD z!r<>cNkyI=f_3zk-PuPsA~`#qY(yYf2~@|}z7&PnDf6x*TtMN$^`#ecb}fHqs{9;T zZdB2oe~2S@jn-FuUtWM*Y`pQkWITLGTShZStJOZ+y{3)iViiW0kpWeZ zLZ%i7Ni9Wfud`6S3hw{JkKDBX=bht+LJvj*V?Ku3(5k}V@K@|*L_eu_t_I5vHld^c-g7a;6KvgX+ox=I(rj zzk6r$-!TJdMU@h7k$Sjlr1c_nw?e;C=@$qWOS`B=6d-Ft^hOj)X$#1T^c+yHa^ony zCeha#A+$t($s%0tz{)^#_h|g2!Y+330H#=tmhWGs5f?QAnEex=d4-!v7BZ2qMP}`R zUM2qgru5AdR?qD|dIuSFp$O#)HaYC7WHMVrw(fGa-xTZBzE})}!XDW|Z*Q^ik?C4t zWnf0Iw3+Rz!siT+1F3v;9xAy}MjDEZkT6Zk15KXrun@()Q=^l3!?9QCS$NUoiZ)0cQO`1L*>}$xqRG8bOD^&Dg&(@d#ajhG@b7 zj)ywjf*8OYgMT9FL+0ym=Sz+7g87T8wMJ&QE4CN#>`$hxcrULQKf^f(hXJnL-M=ZC zb^TxNXp(n8NBii}X zs+M^b!d zgo;io3D*^k_r0{HwswW&SHAu??dG`C&cB*>I@i5D(FL1)+betA^!lh1_oaK9mXSU- zb`CSX(3t^DOPIBx(S~(om>%=*Y2glmey#dCqg$9sv?shYnGg6Gw)G(x_n5l)=lkTw z%68r|t-?hb24rLEikUC|qpEidCOGF}9mVC@p*hcDZJRc3G5Wit1+!{`>Z0LuIb)_bbAr#Hgv~s-Y)V5Qq+CPu=)b6n=b(Q=mX*K< zDb_+3p5B9W&j)imB#(LfTZ@Gzf!pJ6Fpw8v<`?HTNFEB(9bW-y%fQyyVGl?*$@Ag2 zI^zaSg2q+`le*$4-ubS~4oG5jSu+OQWC!Bd8uZoYe+*;qW1wdJbrj|n6%Z?j-DQbx zd*b-^wbdkBBn0CkD>ozbMBs^`@L#SFBg*vnK!($R$ZPVr+Y%|C6YU<4M;zwd;2TKF zM5L!v2Juu&a2|Wj97)k9V&V+>iy8>rcZoLDMDJZ8Kt=~^-QT_ykIT;eR4%Zq0njX+ z_P~HKEn)(YBAp^;)ykg=!T)xl+QmB+qH19mBiQF0ZnB0W@_y zD=z{DjNdhTe)dJeN|)2B^J)~7yR_Q&YC@}{+ds5<45*?-V}*#Sn;wE7005hW$9ofH zQJ26{*~t_I$CGnr1zB@7?2=XV;0$v=Iih?pP!*S$)gXEcc>r|;j7~jpwzMJpW504o zNM9*ooQEXx3z{;b$JP8 ztVr%h`YdhUB9{xk#q~oj$w?}1g3#K4ZwW#*aWYwGIFdJ8knBUG2+VAh&>Dh0U?&lC z_SZb-QR_@E7^Es`P-@=iQ zXWHC98eq76(;`+@uj?ngvi&26GNy`Zh_p{?r=gv`TpBCD+}s1{&)q-4!&p#E1BOjq zrDWyqs$@yrghFzK5Ghr$xX+B9)prwVXBV1H_r*M_l0F(%S1fmxu!u6I25Q9^Qvdg* z@>rxgt=TqG*yUV&HmlChW4*(8P3PXEWHh9FNj)E<6tKJ=;H6`;SFuT0!euo}>9zmn z5lsoD;;B4rWzCK-qCMZzN)@)-tx10haaj59wlteuW8rE<{5qSR5S7>T1oR5u?qIEC z7&Tc#)>&vYoF9MeLC9c5@7dUOF`)X+(!zjY9FMNY$hI2{~P_RjAy|GO5X#SRN}g&8B(5l^4u4o}qdn zrT~u$#WKn1VH`FCgz5sfV|#s4^b!Hv6ISbcWcfx}^&+>Qx(e24l~AqZ=6vK3S!8D? zfteMh^~?J9lzD;1$P1p$n-#lOcJZ_Rp2ap|ahP7bFUZ2!by+X!+V)?;4nAl2eEtoO z#g_{jH!yJM6reSn()RyIeT;t;|HxLMaORKu`_i><71u_+jM%33Z-lh-er&{gJJNk_ zyU6gMfW=aR{}ffd&!q~4H}$Do-~u3A9x)6zSDCXNnc%LQwJ{lezujXao~^2W?KM4>wypjhgkKZ4R!F zJV!U$!#mjWymxBM2`8ug*#;<*7Fk}dvI#nFNQ$WjWp65&Hx;vJ1drZ4IvO4R zC2rxg=fR>2ZkPTPu|Jna5u!Ry($Ik3QCuXHqFsGKgsKouhv71liFro())p~V+z+SZ zG`ktO#9LRAh+@P&uM0penwI=;Rj=QuNuVsck}xORvP?Rsp~KX2{3E#%WPd|SbQqAk z^?*jH26?BNp*ZdnFY1>sSjG?eV9{`(DEy4J2vuxpKz95Gon37J+W3^;p5a zZ|_m7>*H@$?XZQ%gaB&pt7X=AaY0A?8r()}73?~ZHde~i*kWx021jpDC;ZzZoi4*t zR(bE*DpV(m$Bl$XrAH1jHQ<$NZr0H==$WAFJ;zY;-+aO_tyG6flonYK( z5%(>PdsxhdCAxd+JwI#gW3n=SOI*ot)_l2+%`wk4AJx^f7j zQB>_NCB}eU8^tL8C3A)l#)2WZyXY?>!zz=za|36}nME0l!CJhSqHC-8>T2Kfv%$S& zoHe4E?(18V%B96N8e;8nr`T9c-1P#|?SuKwsp_$&XUw>@gh_6zHoX~5-?FV4O{WCGR4`=O5e<4Xb~a}RQ;xWLBzGj> zU|q-nr4ALw($vVHNZixMm+xrIUE+P-pFRAUN!gsJ&FR8qNyOErigNIsp4+eK1ME2V zBg1`d^_t{@y{S@T&_{BeZx%sh8dbiyY6fss)ERc0ZRC1{hJ7ysd%_4yGX$mq}Z zFY#J_^a}||8aI=l_*-@apH3IDa$^`4Oyk~7rL%2J3ES*f^BUz zi*gZw<_aZE;*`y+gL<8yve9f7k>oE4Bll#6AxN)JUUg^FCgd!%rPfJNyUHX1b!>Fi z`&0Lltf!1M^>GVLbqx%4T?=*TcyN6UPu1GdaZ^9qzu(8D8VgS)3hW|=7x>375FRiP z7y>>M^*s}VMCfrs?aYltK`yG<7e7aj7I<-Gs=wZFQO?crk9b=4qBzilRPIswx_$tFKQuUHB5~h-KFO^$>!vLr3~2iciz|e z=Z`i1FO-Y*d`&)dfz9?#4c)NRX4DkkR775ylQGR(HdQm(g1Z-u%x0tGLF{8RvbozG<%5e- zA64gO#@7bbbTDh^RNOsuaO!FtqjcBl9Oe;6i)uOx z)VEmNoiwRLRgjN;p>g^_3K+4^H9P3$X zpzE_#g4u3s_&pan=fhLR+@6N8k>+Z|Hl{T!Z6c(ae)E8%Dc~q3d>~bG*iE+?ztM6y zLg@l4T0O(i)Z0gpBf%8Va5!SLpsK?%`$^h&jlm&AA#h?$)~IkMy**lzRSUl5=JT|2 zxteI~z3j2NOz#GicW5nxql>cO8Hmk@z=mI3jvVqvi<>=N7s`2I_?+T2p02lp01#!N zW37^bEz6B8fY+37pA9A2))}5i`b_hk&Ev7k@;$9*q>7ils#{e!GNAYE8`=}wagHm= zt5fuB5v6!tNOb-=dykNmxURvD#`}QH<)Ja2?j%wgRmFwkN$b6& zd!FtK`QJ78(Ajv>ui?@d&eZl*_tk)6+_IJ_w%J}8=Qb0tJ_)i2q2USW$u11!g74IB z@*&dABOKrQ5!sI+f{_Ae!|OKP%*fN&w#%92k^{tuV4oq%M#&`)x>kq21m`U`n=J~J z)C(`|r4LZ`0=oJhc`?enB{J*3EtgjC+Nnq^Ux#_(4vVXyg(j9fYe&^F^%evV31Af0 zZGq{1!6&30o0gKDmY1X*Mhj56j~OGgGrzk!Q<_2Jcu9DeRf7_?0!_U3H~FkxR4%m} zQvRF?cM`}tRoOC7iG;Og?^i(VXamCMr>;3jNlGuPHfBGxhd573Qjf_#?Goj)>7AFk z#OHXM!Kzr@RJb(IP>PtlF0hidF$1p$vKZlOXn+8iivD@i-!nn#e>GFQhhK;_+GVjWCha0vu1?y$L6 z%Q4Eq)^NDVqqh(b(q=cIfAgL1gh|Z4TIqb8P3~hsF1^Tm#4`+uR%&k6oYAwI+GYtv zecxW`n9&^T#MW z4Kol#VFn|0zN=IZdpc=Fowk6Vp|rj$|x#GjTtFdE5pZxyjQfeT33KOIz@+ zy|cnZx}ogS)nV<0DodFb2J=T`0_k_u;#M^3FVQ6q4b9$tCQueMnF@=K#dfb@etFZ(&63ZbJ%0`29nPKY6aQ)@=> zX2RYslR;0)F+!8@&tK6b07ROhtj7mi@2*G@E=oKX()QJ2xg1rK6t+!1`t&>93CmEu z=T2pZs<)RcBM8fgJGy2>#uBtM7>jsXn|?61PW&YlXba=!l9#U@mtZE;vAr%nx|Bk7 zXoC=GJ8GpU>}Rc2qvr%8{>cx2 z6*H>AQX^1q*M=o6?GQ3gR9M=U`T1b0MBZZ=;-urVJd9&!YnBj1(~w29wF5cQ+1fpH zB-F)|MmW#vGY(KCr40jSWui2_r0Jtr54kl?Zj*O{{>>~3{qRkVHMRtgzWhZbH@)XK z{1he2yFwmGWTPXFj+~yIJbBHfcu5@HEAit-mgdr~dbPmtveRvm5hX3Bo2K^5uNvDP z_bYCT{^XNQ{W7J9r~vFKp=TPkR;BV-7OoSN3~&iFUr8x9yg9Pww%J}K+2`!K*tYEVQn^+g9r0?pnh0=djo_J0%$$_ce^CXJVhXg}qjo_TzEEi%D6N zt|RC+0G3nu!OFjnFF)e{C^}S@>X(Dz8dN0)UV>*SKc)L`L3eSZML+r5aj)3 z4?q;$3s@$1E`+A zV3>tHOw(VXmv_bZc95P|F^YI}*qA8-zvwS&G`XBRz;(9Fj3%6E{EaOVa~+|;O%!_6 zQV#H0jN*Xe)`(t9w_|glrM#d6YYJDqcrJBg1D^>phLW_r@W6XPHT+&oz6|jBS4@NU zfd5cq*CulD$+`V>ph`XbqSQ6#LmOjpQvSpIT`%yu0n)1oEH$;Mlp*{Z;2^{Fo{(b%u_0LiSSm)hRR-T5qNy^U(b8fWhO-X$treQ zhHAq2zrC8b{(48rBiIfHghhvCGrXr)Et6K_={Pqn7^(5>2*XC|pL3U-C7+>5_){|p z3tZ`o+v3OLPh|@*;Z1GspQPe4_lGFKN6AWepYrpn?3d`!gD4($82Hp~DfoirYZY!d=XO2l>pSc4*V&y8-Y!??K1ykBtzBnb zjF>yAsMle66=&t!k4(D3d^(2bFc!C4(H%-d;($$;ql+#a*K1oug@ptj3>$}Mx?I(C z8x(AJUZI2enwO4&%{AFdqvJY+o!Wly+e@FW`8Ji=A3OIE(}ZK{ti{6u7PYByeFl{= z#q1vOt~$X7Z)}Y(H={`Ab^GdaWLb!7J}zM{_7|J+1C&-bqH9NpsZzQ7-o0c0-IemXxDpzGoqwU$_YO|Y zgFj6NPUg&02w3}(EATrOQt19Y#4HDRh25o^9h4;mDu^OUSmv;1VWW8Cg6fJ@&?X%d(*U2Gg|u zk-EX?oBlvLp@`=-LbVKSE^IO6lD+FfAy2};0XAon<9O;q0b1dLRYOBRYop1`p9i@Vs}!#-2TBs(~(C3BkPs}i4+6O2=pd8^!b7`sZ2TV3ZKecSvv2o zAx?>U2?He290#FS-mHuqJ5V+V@e%0%zL?-&hRra`YO@QM8<5$fH-8+$*&ALd&2p=W zQTo^QZ|y@di3`219mTw4eAsLReH^B}DS{KrUR8}O zXatQ@MSH`1O8hQx=f!2Fh0~V$Nvgv{IY490wUI^2>^kYoL(LteF!kU1hinr|LPIX_ z(smfnS>K$W2Or4}9|XEdbQ6vcn*$#s39jkrVR>`UBCCbscE6i&|i$rP4!(`x^&C8 z!rU1V2ckIu5W|w#x1E{X?O5w@qk$fx#qtmj&&P_yYM7bE})WuiRV!6*13lt9vTa2uMgD8lgc`vFoQl^O&a~3xvrCk$< z37v5m%f2~(AKIaUD&#v8eA7nVW)C{Md=SQF4$=!qH8oNH^juzt6J_2*76uXX>=!ai zI~&Ey%2ZJN`*DYnK&6FM*4174xIFb@8O?r6Kh_PqXPI&tO>a*Lfx->@Zp2murK&6& zDa;P0nG)wor?FGe`0=*}LYEv(a&Ixk9*!Ed-(H9s9Xt&9szbJP(|*X#LG24QITrl$ zXF$NJ4&rqZyn|ErId*RP{j9@A3Gj{5@hvfdHl*&qZ%v>G@7tku&s$T`Li0V)P*)j% ziCW>5DjW8mVl<0uqs(ih0k9NTr%&0bIAkUW-BH!J6fqSi4 z?(Xg$Kc^@+6o3e=9WWRcLB0ryK@fsrQMaoLS*QrOOLg$|z`GQMMrSXiJQf5xQj)5T z-CrI=o8wS}fMn`SbT#xW*_I$)pJ}XpujJu(HmKlNlb5?Z-wxTYEQJM?_;$c5ax6Os zCf(N}GS*O%iUY{L@H2r(#PMhNx0HngFp@H5Z_l6iG?g|HzGlR-K{5$3My?69s2_dj z?eyoTINvT^0vyvBFWFv5f|73H%1iCreMFUw|7@gYlNsE%Cb8{K5K5PUEZmd^gI4|a zjfhfdX$aOf8xGc#r%pu~*=?uv)SIXh$?NG#oiNl^y9YiPm&q1m08$oAg4*A3HmgKP zU2M6!rhGFR4H*aN3Nhz?TR!L5$E|Q~8poeHh<~`kGK$jL%S~1?ySA$t^(JmSOk1mT zi*1+M;pep=SCzd>AdUB{KSrWGYecxz%v1g{R^e6{#C9bALlSp{cu@IahK0H*t}{Kp zh4tkbYK24?!}#8UX;L(C7>h~1*8_0i)uGT{M%k&u!VYAh4rchn)xB!oxSyzGUyoq_S%jVZ2~ExhxT&@0 zZ&kfm_kD>ml)e!25X42vXShyEu(<0#o_gEFJhhLJ@UEWWU11$!sI<&)vHGaNHmbec zYHc-@7~jM4%$Sq~Xp|FR>-m-JcBmzEF^*O;bS~GGlW!?4Gs{;|U)Ler!-A2zc&*;~ zvGD!i@vSq{Nb~&!vhqQdlm%_%arO!@!Ok^R_M%>&_jbdDp;d+L^uzIl8nNpsOY~VY zMgxd}Vg*}GZ%R5p*JlE~j@8I!>VOCANLt1rmP2UjFngRk#U~=fmGJ21#|&l#yN>m! zDkqcnshwMpA06)PF{=Q^<#f9i@IPb!GY$1W(`JaCBkJT2TeZ!yA{M;vII*s8X5xoo)V)qKB z#6PDBE?#5}k*}rkr2oyN%HL1E>eo|w^-3MEUE>hITJczokyDl* zk3{Y}5d1}B3}JZkrbktBhFfKl_h{A;wP}_ER}({DY5id+l_OZo`;bBqjOha0!6QpS zRyz_;IO?EPAB8)mDS?UI45g70(!b)Z@V~@54Sy6Yvx7q&<5M9@x!{hQ%pq?$h#j4V z#%v##@hgECs-Q6E+nZ<#Uz?TcKtJh4^q$^0pYEJN0qREY#Sw5 z4BS3$LPFzEgj>p!*vm8bob{zCXg59%9$a4xr`@OviS*2ZCY>v{p5sX}OIFHL^0`Y9 zN|i5VaCZ}O#Wl}lix8|Qd|{Ij+C9V$?w-oY8oWTpuX$Wov}V*|^H+2+4&tBf3xVC5 zRf}QDLk(%{0um5!@f03FZY!gCxorbUVhwjq!Ka}aWtu_~GCxye+Y?6e1z7}(#nDidA<^0=fc(wk z4cUyd1#wQEZYiH%Fr#npqS?ln5|_GY;*c&i(7<0q4}XsFBPDDanrh<3UCMqL>GT~< zd0WTX(!h;Foju`d$g86i5A44kZ#0R>QD8jWJK{7__XrMlNiVr*qjUw3O(|;J7BuA6 z>ytwI15*``W7%AlO_iAyL6Q>0wP&e=Mmv8l;6ye?OCZ$i?<-YAO!4AiFjj4aaJE?Cd0cVoz;?QZ* zpy#*iDF5xVFoBEOjZzJO_1s9|jWV_!lsrNR?poDe6qgZVgFr$wAhVo;P1 z7@P%u^0Mi`ek@P`QB;1+kA?g$edj>o%f^0!qziFe=M1RA4)OI0zk$(Oxf-v>CQin= z026vqX0`*Q-U+=2p@8xl;SUn=tNfJTn^D8AWxQtUBtHU59%v591lfv}UHN3-Z+$G> zaMf(ZFjl9_i?knk0DJKQdVKxU2o#he6X$@ULIj%dC24P8bb`-c-@icENwE#T9`GN( zQTWpvG2aQE3_aOosYK4?4ekwU%P{RDRx-#n3Hopc9BgR$2x_=pd8B&mP@RcuT!6k| z&X7I<*NE^36L584Iu}Vag2)Lp>LQAtY3DgQ#X-*m?bwNzY3(Dfv=yRCiBKH|z!RiY zlhz|Hw?L$_x$930<#}wetQvrEfHb5RF$ls4>;>=J^JqKP1;xdP1>sy%1Gc;fj&Wjv z%<)D8#37uB&)sD$I@&Dl+QTyX;+7@~q2e8z?HzLc4Jg{7V9F4qd*oaygx^`*krvRgWBxY9SPZYKMoz{m-w~!inlfY!9ho%LP|;L)e(5XPWaFZ?&UgiO>7tw3o+Ol!I*4RaxE58>B1cXy5&877RGd;YCbh{REx}KJ)ei@pZiuAWhLlOkJ)fC1?N}p zjT%47kkDqo3=N>~hVvH-!&;(}S)hfZL(qU>$UJ(j4EN3uQ}u z2Spnw0*>`zU9BU@k2#F>=vsE43JTDXRZQNgEWr39-UuiI4&P0cKaK{@_*of#*~3`XyXUt6uh5e^4* zAQVK+g+$Z>fg!+q8XdFstF4c`wpYvQWx`hk2?xlb) zv4dM~Ls!9745N*icEg|bY3PL@s{m*#j-qK?yTn_AQs;$v4&!vxBS}ryO!mr7txB0t z7jTKvBH9T?Y+6O`Q#!uR$EMG4+PiRA55A-Nv$u~6UMLrC^>C}JI6p@4P$%ZkhIfH> z?u4Ya)sZmxB}00b3WHR@!gv`%wKqEkm|BU6HwVSns0rS&@%H*QjW(V7MES&-W5~{r!xo{k~V<_VJ_A?cL;=gq`)w^-KUDvh9CXS<)1o5)}9 zlGmz*AR>iC5#^_~mId69-9*AZWE_|nN`hv!BZ^XuQ<0`dN!2*tB9aQGUWoz}UATq| zj>VwC?GKY_sSVnx;*?Lf74;9*S6yW!hp0*(%M=Is`l2;qNcEd)JkzQfZ@zob0uRIG z&5HP%k)XK7WqN3GgdP)KA@1VP9;exQo>3hr)li>{TE>){0{ryLwIqzEG0NHw zly#Om6r%HJW36!2d32kZzk(a)gdEIP)Z~B|(ETN`O>x}lXwyP7RFlKQyj;G$^P}-! zsj4{d#0V`6I866>;zxM4c4L3HqHec3AQgg1V`n zApkL}z#pk$7@5uW?!@sv99Q7AJ;=ky6r{fY<2<5OeTf~e8S=WzBqfX#R!LOCRXes> z507lh2yY(jms&#}r{=Bw?L*j%mf6(odsG}ScqCg5=kGNak#KH%pgFb4g`3KRTmQ6wd>wR2U*l!%^>L zB0sUwrEq7O7S{783X1F^MQZ41qK=qzWkLj+xrqV)$IFh*LK#A=ZvlZ79hx+53w5A% zVi*hL6w{zr7Br2g?w(w>W=AfUpo`eA0{`Bmoo?jMH)MuLs0S^WtHRlYU_GI1Tbvhz z7@mI-g|#>=(CB153&m(b6J>o}-L3vC9*og*X)*HQupTmz3=b~{OqWj(&93=EJAnt} zN+nV&ioh-p`S=*L#)PQi(r$N-Xpy8yVT8rx&VXeG ziD)ETO|*V4gcK!^Ay2_HwmT`ev<4ycH@Gm}pM1X*tH|Q`E37U`i3%&X;FRk)0f8v} z+64{{i?OvH#k*Z<7#a-kV9c!S#l+)X3Y<>3us&}9rrx9)iAIKnRg81G=3pyMt? zLUt|`rB`mFO}oJYuqiPK=CDPRWr$T!a(Kkcx#Q;oYD}unzExF25+ny~IC(JQ^BZe2 z&5R$&alajIrM9M3tgToO1{EvYEFjd%7Rxj5>D!2GCwZs*jW_3{6wL7yV;5Z}q$Rpz zj3lF+cOxUI_MuyMB1KfgYiqj?mQp?hj?K@y-#vBP5u=x98?$snH4gey*sl$XYhQMW z&8(9CK_VgWB30R6-2limn#D1SdqcEn%^7E?$>&Y7&A6(?C=Ziy^yN8^s~zd}luh>>fE4tPE!vfVED?UPVcX$w)Z@+N;SI z+XVdhhHqx1D5$OmM z{w*wUe<>xi<9Y;c2Vgbwsd3M_oUrz_ta`j0Kc)I7unKB;*K>4y+Tntq*%2{;twJ$B zeUHD>+5tl6u`mBxPj+r#ExHU&8i2vyjNuT*Nv-o( z6b@wO$Q$zO-`u@11!+G~M8zfwMll-~<@xg$6_$$P5GH4#m=FAwO3hM|PL z4KfIU22?ZOrYX2gX|!Y<#Xj>q$*4GJBhp!}d;xL!C)QP&Xff4WB;;4tZ7CDWh zh9@ns`Qly0oGh0{ChrJ$++O(}1_aRtk}emMro56U?0tgfkx&1Yg!kWNtlM9tB@kJp zjJUugAgh%BY0oE73zcLGz2|M~W_>rnDb_$DZ;E4Lx#c!7O^bF9Kd?Lq|MvEc4J|Yv zQ2bxfS++8`-2(}s{UZELHDBdOA^w}*GY&i%)4&cT=L_VR>Ph}uK;l{AHdGpjym&;Z z7QpfHDp8);;9=Xy$3)&}bi5jo;U-0*7VusZBwv+pmNOR4GSLC#U;{dH%V?SKL$ z+|Ye|9b_Rqqkwz2&ru&B1nc&5mbu7tW;Mmux)AO*sj*f(kMURAqatVzHB|Z4;OyOY=pa5@pn!uVm!B1+%E_~Rx@?h&RwMK z3o7XnFsO~Kgqm(n!yCpfBM!!C>D9tjF0IIm*)2$rF5Kh{{R3ig^!|+`tz!m5%z+Xt zTaai%H0V++L+XC9V(G7h(j1<=3A{BDkjh=?(Y^S=Sf`5su(<9CJ7ql3A2~8sv|(yP zJ5f%a0Z(=sayBlTY<~>9*57u~54xQQA&Jl!+wU@d4@tqz`{$xAt8^TBsVjf(6F_&y z8cg8aE27=@cr;?CzV0R7@az*f#l!7vqJ@N7wqn3X-E zyG>7|aL(RR8Ev#$S-scSLRDV$zej4pB)ka?ws3u)2mfwfau$G~z^uld=X1F}-dUT3 zUUst&ZpfP$l=Cxe-hCSE@0)SJ$o5Cp#9nzL;@g_%5p#_IdgP&K)tH12>IjBC z4GyKx{xs90XjVPUAU)X&&$UZHn}N`z2T&%Z;+NN?jw9M0p9gJ9Gj`@uH4@i?kjUU3$7aFyM+}@#)M!*|c9H;9J z3f9QmtB;NYte8g={CDrVEoQ?Vfh6TFgWwSw1+vUfuOn*=niGcP5iW%+w%DK}uq+b$ z&S-|ehVMaF!w$MgX(*x>cJx6rI0X2@j}pO(K~0R3O`)LXSpsWFFBX-2F<0`(k9unD z{w$|~s2?OG(rWe=rjvnHNJs6U!x_16|eaZIg-zxpSmm(ad{Oi4cU~EmdZ~PLFU<~HHnL=#HjR|-75-ZoHR9b5d8pS zX;sd!Jnn3kPHO_29XvH%Yfc*&W~R8S&skzdtyoQUyll^k)?tBVCc_Grk(7(+jBN^f zi6cw7PCW97!Gwk|%0H!c8*pJ71<{`?zyKFVHy60bR*AWCv$-Jk$7M00HZ?d$MR3jA zqNcUz=+5=Ehaq%fVpX)n6PiNabXA$0g66jvl_DA%rQw5m_2rI~y{nh=)8*i~2CkI+ z0m`H7&Cp33sL1i0GXb@Pv$}-!7f|7&@&^K~;{bql3VvzKfpxsL7&*BvtsEXCH{uEY z(gk#7Jnk{BTE<~P=*10s4ZU`=x&MqvoGF{FatL%osOWH4xA{iHiT@1_R4fcCd-{$( z%UUxrNMhxzz{a~KTN$7M4~Ot#Mfm~b${g1h2kc=RF+Ydu=GS1`=_*6$rA;?NtoJ#B zf`s#e8Qn|jg#)LBIrLIheZnW;*~4cOXhMdsCb%70>UFTze*j>G)+l@P~BMp(S{>3YqP&jzcpMQR5cCx%J9Oa-&JEQ7K9`&&}0(j!OZ zKmp`(SGkGUs!VH1zUJ*-KeRc{JEI1d&9;{20wMp{>LM_dZv??_L5uQC;{HUp#pbDM zM)QwoQ(^+9+Y1z4{0$qC)HDEsqL?O8r;N#SBvi#gI;me9O$)EqcgWywCW546nhOob z!2iPPB$XZi(g6mXh9NEZk~OG|!a)i#UzZMk%hMFdl9*)}{1nMlS27hegJfv{lFXN) zJC8O%lqq_vubyD!KJq*rg$o%&eK4-T`damN>ZdUGS3S2B><&DxGP$oVxvz(+G^)2- zm(9W*$yN-Qe%K|c-97q~xII)<9uA0=aFbz%D&YR-R@L|r6bYgTOEw3z+R~39RdwSQj?Spk=Cu4DR3D%j}Qo3CUz#a;nf-mu# zy~b@9iiFq+a(xysr$(_KkMSR8Z?+Maqzu+DY9&h!gXQ;+#A`3}wsn-+5dWYjY|c~< ziv`^#ah<0@6boA!^GCLCURhWk)iAIYW{^S`kH5_C_MXV^xEwrcN6F~a_Yg0yTCr85 z2~jB$3WZUwS1X-xUl*sj0li5A4?OyDVwAh>lMr{CW;#kbnXDnWMJqK(;IQE@wxI;4RIgE$EGfr@}nFx0(-D_e$-qt7wgxK`mQ3 ze2!C(n~f|f!xnR|qB!gzUkO`PlikKN_YhQ^H>L)ws8~imzEi`TdRj87cNrz6HaBgT zDdMb8_HurfcIGa|$|eTvvG=-wQY1}qpj{@Z)Y%|YcJdRV%H;6H=J}9i-s9-CbZv0Y z`z1ooKtMH3|D7EQ^4z@N=P9s&1WP1=_X%H(SXkG0B&7g;_+$(hf-?N^^4uuUhLBs3 zXy~pHKp$8Shd2~B>MS*Fx;FXPHd&sHc^6(1uqaI#ZeIJNgvHbvvAP~^onRD4Ch-CC zglC$PGz%r$Q!UjThEeK~&7?G%?0^Ij`uPO#oT{u3uqbCCc_>+yLp5jMHnE}@bhr~O zR0ePAwLite?k6#K8c7@Ow0&6{JZar~6!wocfiLTB_KnI(bnG_XebkWy#NNhkW=M=3 z)zqyF0I7tf4t0MR!x~(y)iiY5tnTRinY|;;2}lREIBYc7Nib6H+3)V4QYv^K_E8Ul zPPs9pjpx&S!uG)5$0m@w-JSXy^y)DKFWEkw{OMZ%#yLYWb=aq&YbW*QWxsTleZ&s& z57wkAF>tTTlDBnc?Ls#*qnABZG(N}_cn4mH$z-+q~r5!E7Q)1n$! zx09m2pWBh%fwhf_lB6_aD=j(6kk zNcl}+EdK}?Nbk{IEY=~=L^a^$vd3o><+Jk%>KK6Xv;zqwP3^9}psu*o`Xs75S)?C5wM6s}Jd6n*K`` zo_rCb1%pu2TH`w#QumE(zvW%zBkYul-r>(nFrWQ^9k4i(WrV~_Ct^}_Nia}y5d8DCh)Td^d~y!FIN+A50YR+R3I{0$neI z49AgT153QcYq;VW1Q5E5_0ME#M3Ji5(h&?=_*is@yV-Qw(sYSIf);D(G z_h+yVYqrLKIhkr@hMYgbKl8CXfmOq&g`vXT6L z946+jon){}{S7T-0!o(h4==Ss<2um~88Pd`5Khmopqs&UjgBz+cfS(}$3;px3Z~>X zb>A23`c9~i$XXz5wSy;4EZE?u#2PwSUJELe-@5?qzN|q@@utB z@TM=l=XQ$4CCF*L0u)s&bT`FD1SmV2{BEL4V0}|Oe%hz$1(BGIuc_+NYVEDh-hqP& z2SP{1L0L%urv@R~27{#_(%tY9aSIW9Q4f*hzo)sV^C;GS8N+E|Nxlh}*QvVrYRp?F z#foWu+`oQiND|R9zrXF{^7zs%x_=T!2~f&wY3jN!!HCj4G%Bby+g4qB&|P;MY>#NKmqjAuSztb0mJb#6Wp4ITCz z33J+uCVRREl%-(-2ZH-gTO+2^`26PPFSNrgP#Zqjov1si?V7Q<+Bk@%47zP{AkMj` zX)5Ht`3;2GXaWDVHf}pSyz6;tXM9 z+3${?7Vf(4&*!IUj9;?5Z$lA>N0@eBQNir1$q5K|xpX}^bKJmrd1dkf$M{QR7I8cl zvqcgj+|E(d9p58^E%BG7o*O>2WQo|FsL*clSfsXSbW*!T_yI)vAKK3AF|H~ zX7Fn~8Tdg&@9Xt1j-%ym-Z)9p;je)YkpLp6bQxs zkegT!5X=}isdEGpqwKK z=jm7EVvZ~r*}it8XWhXju~=4)%d;I<%iAA8MqBExVBCd;>|#UyPK^d0B9VYsH&s-y z=_XI&Ks8|pSHD(}v3#Bkd9xu8S{ow><;6_prB|_IC6b&}1aEj-{9*1$lGZ`l&K$Jw zG&@u+6wO8qaIrE^+^JTa{L~OC+V#GU#s^(p)r^^;sv1hVW zwQ8Tnmn^QrLs%NohQtEUJQu6Mcr>U?d^_@I%hs$LW*vJf*9vJ6b{eo7K#!ma?JHg! zkt#1+2>k@ac!lro-cE}#eMB1~>rKpJKQs)%P{L2Z8{=V}Sfr5ZK?53J29eqz9*}9X zfp31jRW-Cfw`QixfOJsj6{L4i**{-s@7w22eAKdKSvtabK<4+Agr!A3%VT`5IOsNd z+?L*zf#igiL7W$E79jc<9lkP{x5RS2r^re{uaM(4?hjBd+hfbw3$PX2F(Ng=a+px= zH}(vPI$uq4=#5qlM_FR+I()aFdMXA*aMbLm{5wzU0zR8oO-&R+l}#Uaq(jPyh+4`o zF<37IXIrT4IZ*AV#ZR|b1=Z3Qsr-keI^$1n>!}!NGq`V?T;4nn8PIGY{I1VTMlchI z799Q8KMU}M@%grG2HGcI1UbTCp8E^mXcKZB8RYh5qT&yHDF6NAymFGdDm-st z!PZ>X&XK>>9}>vGhJyo-kEe?}ceN{05EMiR6B8;S3JKW@Z^6cf<9WEd?(YhT3DY_E z19G;v|0DD_2sQ)(!I$d4xDSr}`8kV|gdl6sb$nf_6Op2V`MLi77T`++1~eY7mxBM| zZZ`ZSM2iX}5o+Nr-0TbTVgEbG3Pdw+yVA+-ZrK0B*@5D~$Al7a|L@`cH*^16b3YsD z|CbH%@6AFrf>|`lC-bPG{UdXaVO?=6E0k_& zkO_{d39>@St|l73mcbrAaZa_@kHD``1}tb3od*uJizh# z5IbCk%-?*5f89it^!n6*vhFD2?tEBYRIsP?btw}8DzQhgk7C1S;zSQP!hf~nM70Vu z)HJ*za0guI#>e7XSqf&TT07*(wRc6tQ8d`LNK(JhM?(arhE% zy|GRMmDcC??EQJ14bd+R3xfdbzPH|*@g4o9!lYrMJY-#I6eSGF*A%ti_v9^@l_QqL zELnf-DrVaDk<&y3#^13H&l3d9u!y+x-29>5|Awa5*%U!r8q|rw+dfPZ|NC7_9!jl3 zP@a&yp0ww)%#ncCHg2qp{noO9ag~s4HTczQ#x<->+O-IvWm0T0t^a^G*RI$P@ zGWa#WL*-ZQ=|In|8gtiVl`JsF^kYqjCit6F4NrN(FVrYex%-c%T9U1}IG?y@u+bIp zYcIlP6AK|M3b}fBd-@#`*3)bl$d9%$MtU^Av{HjYy$(dl7!giTp}V%Qx^sT0q*7TG zTL;&kKHyLJleQ53SX{S|SBx-xkDsn^HC?J=vnq~lQE4Ng(5t13N_ZhRZ1_l}o)57- zF_@WDn(UNksyZ0>aI!Y+H=77mcj ziW4oWJOV2Qg6}z=yypaUWnd*#_!Ss~xSbpYqAv()fLCGl7S*}%noXhUARS2#$!~Gy zra23{Fb-swN_ETpE`(sW>>>=kb4eHTR2KL`Jy1{(Ax} zDY1M}$~_$Z6X3Pp@QlQ2p%_lKxV1Av9dKO3l#g1ZA!^zrlqLG~o+3WrX- zHncnlj+z@MU^ZskxHQ_o2uZY+4%kC*^pS!xFexf0w8s+CrR3GXW9Us`B8B}-ky29n zJWqmWR9{%Ef0(6IegfiH${1w#L^51srPO_ziguN~D+{8?F<0jq`}rU||0O8}oXjR< zG`j~r>pe!5iUyd86*3Ca*A?+XaPd5@H@{*1$QZLbG7I<-Kw|WZ79v2s5}^|PDdCOj ztlnAiFv>Bf4RrWVMOmS;!8jSAYTHB^HD4ynlPRs_0{78?tL;m=NU$V=%D};XQdmIF z(6F-_ke7eAItw!Y@ObVe{xpz-421F-H0Px1%Wgyf;Ub^L%6jn=9do=Tc+o<=x^ab= zAFT=u+fq_~ZzknAqbvI<<1%G5vXnC0rWAZM z?bQTv?Ik1S71ceh@FUB(s?9r~VLBe* zmWER$f;ufM&`|Gqj}wX-X2uiIJ?JRVYPg-OMAn9Z8z)KgmZ~!Ie(sJO{%%bEf9J|D z+j-#RNT%Y+j0i&Nj!b}V8Tw{iQMhgM95KxtGFT`X=2^Y;<_D$n5-X3K`r>w(j7N*+ zBI9F|!EE(FHD=4cO}+6D_N+F z**6OaO=prG+^x(Ceo9a+2v+61NP{Z|oRi8&jupb>m{xWVY2q;#e7_L81`{frbrLE? zVqSdN(G*79ojKEhBV^FWSG9|%N$0kL^QqBstkH2;%lW5-%L8O==_8d2TI~fvH5bFQVAZ47p#hFcW_Fw3n^w6OgjLa2lUiuxIYvysBiStoqZK0A z2lDwBf@v|dk{4cm!Sd6K3r}v)Vy`4{-UuhcaOE{p8!cRo*}pi=zQp;%{~VIBaw2Y@ z+Q#7XZosI3tOPue5-Edd&<5C*6E%VF%Vgx=E%$qw@&^Zt*Pp86soVHCn@&IuYPIz?Kl`#=cRd zVzWqfvNFoL(0Ga_f00v6dp591`aFIcrXy2mqhPpQj@d9@Jj(4!_@@?EcA&)EDXy>W zSM{)hFAetF3$RCaBHm zoK2yvjlp8QvQQnt{#YZXnqijsO3|cJ16DwaY=l6!v@`WA#T3Ln<&CBbkv@%tt*%r( zt31&u*rJJ6C1Qc^#fRg}pjPP!*lp)RKCxl&dcAry8-|FxA(<($v`M|(T{2H}h!fAj z!J`TLZ*p0h_9*Ww!g7cmDPom#Degl(K;x<4t7ze``(E$+6gJS&3%@u!#K|mA9z2=m z*W$J9-YuB997)oKqkrccQWbN&@XG00@@d8IaZk(!I4)5&G3F97vJhsGF};{aSxJL5 zcp}-pNh0w1S47gt1%)zUKcxJo;%a5yj%L~M=$5_9Sk5Ykz9>YR4_5Zd(^p|G735~yao+-OE=-~Fb^-aPKwwUo-)ST z8bgUrEC&vS995L`y05D!4tPZaGUy5rkB(Dse$Cu%TR#2i@f%QagS<4ETf)6vt{JSQg6qF2i4*0$pMYn=c)tBw?nNU(7_-Cct(cOHO+ho!CgtH7;8;Wb5sIV+oNv0 znr<`(vCS!=x!0|uw0Z}#u<4x_*R5Dns3u3YS^aHbZaHr>A$Cn0MI$+z-coM(XXzC| zox&5Z_L&k6h$3?MuahttNCi+bZd`R=w370vp`Nl#f>I=Q0La2;qWEH0_COZeEYOUy zy(Sc|`fKKr%$lLueq)En{;Hv}1=FHk*n#wKi#^#ZlF-H&JLNh=B@DChlSdpBrHe^+ zrMfVr^!5R)`Qm4^0%y)IVRxejK?XeXP9N4aSkFbBwI@=jp?LQ%7YgoA4URFHAh}_9 z6s(z;{R($p9q)v8k>(IrfW)m-rSc}Ah?nZf3Cw8-zWEMYl6J5>7&fzYLt-KgTFU@c z9iWelM;33VRfaKJyxC$}S3L;6kT6|#j}!9o(-sxDM+#+VS`lJ}#&C~H*EwW~c6KlT zhcg@6k?2(5U|dFT%AxI+c>!~YMhk)`Hc146cFNj^Yj+XGToM$`fI0vk3RO8G!LAk& z+F;0Wz}-;H?i`JT69rCc*y?%2BF>ZwBAzEJq8AoqKNksDC^1x*U~Q>!!QGNp<`&b zP7%)^VagAvhdbn@IYjhdD-CTqAj%^!ofcwK85jTJL^-k8I1di;Ml`+e2!H^Ij<86w z6p_u{rul>~;$i!+HP=vXaly4qc0|Py5XQJ$CsuC3I|p2uAgd{j6)CUw!iWwgSg=je zHW+|p9rv){G(56^sc2z*rBdUg5VdYodQi}B=xE+jqfZvn2#Z!f=<+7Ye4MEznLUuL zNyT{@?ihkh)8kURwL`#P1y!9UGJw1TLrZxn_$5HZf=$`hL!5KSPyh`h7AV*2>~#)0 zJxt~lcxOvUL#*gTcvdB=i7WRAlZM$h4NaXd_w)LNhEl;33Sr0(Sa27v!qcjMZTxZq zP#;1Yju_w6cCf4CabwSXVm_y&^|`>6wM$@a4iCS*Yp3SOYCH!0@AUlz;m+p#lQHYqiL=pID|KUlxth zL`mrJzB^;X%D?YEqSRoH6F_TtcqWY&{ls;ihn>#p(EDrnkp6tbJ^s2}5+)V|SGNtJ zDJqgQDQf5}8ZpxC64TOb>OU;2*%t{)Z$31}nk48gjD{- zqN*4>WdhqSlGTIm;-RltNhbH-28tHd3?(R}+mPWP8&HfC8R3-8MKdsdYm#-c`+m8ncyz|l9@#J!wz0L;_- z!t&{slE=}N7X8-DXcyt$3xO)Vk&2aNgm6|53SdF#%oe6|$GaGxYCjQMaF*kC_ zd%!g65v!g;!BZ@{OnslgeShAx%}J@7#>GPUx6CKXc*F%`DWdv1#A;{o50irX{FCfD z!|X?xj217@6`z>WxQ4iwinF?C-{z*0bb`zz8nQtpio6SqpsbfmTm+Ftp_LNrqZ4Xb zu`l@uBU|eV0Z}jih=ncFNO9-^1`vM92pg z&4l}EZvmBVWg%C!h^eW{ARfLv+f@A|S;j%k!-QzZ3sY-G4JGtcDUx_cyEIi5KO0_( zb0gQYckNFTMM{;3)qk2qCJ2v>?oOI9r(-QIVPz_wNc5fIc8#NxJXMEU8%`0wwG~LX z)V`p;U;pj2#3-we6ej%+$X@)z=(e8}QE5U4QwTXnWKlQp;xEP@t!o3GV!}u^H^!5cWCOnyy1Cy%9|Co*6B+2?$Ppm$^H~I#_v9uYl0yEK)KgDjN zt?bOk2d|YCQ1FjQSAM1;!(vk$P;a$Spa@MHLIc~xK?;dB;E%5}YpYeBxCTyEjS|OJ ztD`k$gBA1Pys#Y!`GGMURAOsz5)9XmJ~`tajf!xSej?#+73yFoqY@qTitO3v3zDCF zhb;3-#CD^iW^2E^j`77p1<1V zmn9#RSS(d{F6&Nr0g+Qv_o&szGFQQpW1AV^O5#$5Js38EHc3R`5;k0gn0OX-Ei&ha z(SNLYn8UW@_sp|Wlwth#SXB;Dqs)`NEh$7yr)Kil|ukXdTU56$~*>0RcL2O&mz$@$m){&g=-c{ zv9ZB%@)T76{=))AH`w7iHj>8>eu0EVf@EkvfVB+%p7(IfVW~LdF{x!?2)b6KhMw(A_+Ul1(g;*$~D}Om3ws&irk}>k!}^%OG5gXHgfR zq?a*GR08oB(t1lip?*-llY%pDxUj-pH7G#~VGf;w!y7O{b<)W2$4!}SQgYv1g_L-a zOWeX$acMwU-fj|B zT17P()ub#Y&kDx7TQX8qd3D;)Wu;!i1TBAJB!^#oUojFEG@vZ;4kA{_ND+Wv@B{+F zOv$nxe|JT~w`GrDnGB>txHU{-(8$Rw>>xw2li05%WJNLjq4;|!PG{3U3jTC~N%crfa zIV2>SfaXaBG%PEHNsas8T|~%%YS5xV1<(F~Ver2b-~+H!ZL$ukw51FQh*)`=fNv#o z?ng<$HOQFL?81$bAZ$+TuDYal3mmHev4GQHaX{f!xZ%FO=Zua^bg(!zpjQo|9!uyW zx*$B#Mm1&nSu6!oRWyCoCd3@0s0d^`-W@UUwZ|a|48j~s?k-+aq=P-21I9yTGh=XB zyvcN+4-xbfc;jFAr?WsLq#1fX=g&J6vTa!^@S?23xf~=2wDUm{TZ3vhi?#KsAr$;A zPs#e{oe)b1I&d}uC|o&xfU6!k!t=!bfP`j+#0Nr{Ro|}v5X7G*aKi8iR$*!nyWF_A z(g7voOk#nY+)xToAdGENcd*oGc2Qvluf`hNZ!i`Lf@pe8JL0pwqH2tRWwAvub@Jgv zD2xuJ8E8DeS}Wp(P9$mwr!R8-c9N#9)nyPIw)Xk2fBG*wkMSelN77@6)kGds`AhPd zshhUOF9V`gO?L8M!Z8B&-I6*mP%GXFvCCWu8c82CO5Y?Mp_)VMho%93^E2qgg@hxBxQ%)3XfXoSIYq_3 z<72U?wT+E)HqqvgNVt!gH}ik=f440xHdZo&KOO>0S(JA?{(*CS_amaKmKL4T%?2pc z1o4lKUXKui-g5^njI^FPR8%T7?w0f8Ojkl@hu1nfuLA2Prm`qOdyGJZ=!7ZEC}A-0!;sNDjOkV$8XC8?e-JDj>9#`77Wvguv`a-*n(_X4%O5 zYPdr4nR$Ebh8}<;{ez4*qW*Wou)Sh$Q>+b%eaD%N3tVdV&l^^B@i^4AlQ1|0wbNxy zM0hK4p6!Ty4a0jVW}9_)WgT!$?U}+9(qL17{-5N~x;ZLEq*Tl$`dNxMxrEX_8+(e_ zRCCmO5C8kh?h`uCbbick(8}m-stgwYocdG#v8%;v3*t_7VqOzU8pQ4f!#`|)RdRDq znj1xP!|=dyR+B`!dnm450zofqaKx2SbyuH1Wi4MI`Rxcu8Mf<3BEZj7vzxgxS8M&z zH;iCe$xs<{hs6B#9-^hUst=Aj>}s25s5wW+6>vx4-P4>vYMSeWU`a|qKx>*eC=`(4 z{^ZDRD)o5BCV7 ztIv0d>Hz3%M+k?M(MJ0^Ut;f+ei|O`-bvH0Fn`Z^+l-BIroK;OerOr>aUd6T1}wMe zX4v8(r26o|+;}>h!o^!DDQ#CERA3V>%IcvQeWqYv=gu^?+gU7bW)u{qgfB)YTMgeK zh>=-fDB{?$vim8)Q2`!U?Uh-U9tWMPpExw*OBF;vzqA20<_{RXQ8+zJi~vw%YTU`x zzon0l))~bKu@32|B)Dyr(FS$xH;3dr;6q6ekEIFWiPe7tM_Gko!`|4mq!DNp=q5Ro zM6XPs5)E9H(_@06oVT^>gL*~avE#MMH@3w%t6Y`F2BG1fbv4$Jq21>O06> z8LNNJ(oUS;B>Ro-;tC3TQKU#gaf8SQht^pX2Hn)v6`=kphyl@o7@|Iu1iGO%+reQw zS1TB(1%E=f#>CF$qbE!qLQ-hHkTNUOrC~L=f#PAD*9kIs|Dh+RJ*Mdu@rvgfe3W^9 zpxXh!or_{+NK(Ul^#k>kYU2PwZ=8usiC!7ni44L4p~U39PuMpIrJxgDvZKjYjD(4* z*R4>7x9fq@tWnweS5j@H=W>@*EOmr)zfLu7lZS6AMWtpuu@~+NA0$P#y&$zZFJL?lO~(GFlpFx z@gPe>Vo+nvq^|@^@hFaPwZ`rk7o3!SC_dw@5b1Naj@-L6x~9(G-Tb=2C&GL(h^AgW z?FOKmFNzcR?pNl4s4v4`-)q~HhVj89?ti4T_){ymzSdv%QE5kk*{jxU%_-TL>0m`| z-KL|J(!MIikDFC_6k&}O4fHl{qXf*RlAYH~%9!eKUtErClW6{aJcdsI?Y-9Y2aX%c zp~I)OcbZ)29>qXX`Yt;_Ic=uuyTT`MI3TSdaBiR>%xCR+D7P zJU$YQO9|#xG%g_TEa!zjHCjASnStXNI|VnhDP?~(mjpPqSd&qTF73k)O{fay)6^cnDi~Pjl6|yHO@it z(mz2swv`^}OxYl)AhY;iHtLgk)7~PxK;--e`)ym>zYf>SWhk4_!U|M)c)?!%3h$&R&dyqWWgr_dZQ3@#6VJ2c*F=~!p1xSJJ!$ala= zWE=z9ya0J_dNUrn$OuO}r9n#zGvD5p0niT=y6ULf{hQo7Vl1ms?|>E3${n4u$?Ou- zUOnGxI|xWAO85(Sy|tlAnpM{gp;5dDg`OLmdA;_V$XAv|ES!dzFv zP1(Pl?YgKtzyUwD#?kh;*!`NrP8%od)nTxlVLeI9=PEK&nAEi*?2O@#;Z}CZ05{J{_K~t zJip+}HP6sDie5XAK_o9LA`!f8qP=;lcudNJuOTt-ml4O*uaTU}AeTB>p09i(edBc*j={RzWPQ0`j)ukrE(FLeq0 z_Fn)j;V;>v@C$fvanDtcdGla#MbcZs+o-=+9Oo^)m#TE5eIK?=uy;`l1b8=fFr;(K zune9RudM5Q*d1r_kvRuQhCLA;HKMKi(O;pWXS87j)&DwQagOoLpXa1o?r=7ibUJUn zLU}UKrbZcOKpZ)c*j>kTc&(g9Om42M33N__-ifFF5ShA2djqE8l-|vOsQDoD8BoDM zo25OzhY$69fENu!{t4`RZ%-4>{34luMq!kUf=bcI$PtR zLP?a)O3M;u_B)e$i$))cjb60BW_iw}Wl(f-6J9yfKXls{yMPB!PKO!jcBNhwjl6 zQC(p)d6({9Op;;h0AD?Bf9WO`? zu7i8Jvy|DU+lB(z@eIZ6+$<-KMPKEI6Z0AAT#2{3Iv5qU&>Kf0ki+vN5Nz`X<+sk2U7Ii=-X*tCtC^Q;Cl60lWbaa&*9C>q^*Rj5t-jOB$X?p$W-FAj)H|tLA(|j7y z6ieTuRPqIY#cij@+AFH%GkuEcw~l@RQyili;!vr#Ll};hc{U~!;X$-MW5lPJliD`$ zZOKmpjQYsTsn+@%${O$3YMMT05Y%nC0zITnlz6TjLF1 z-A_b~G2djISm-zw*(0-0Wk@_xHw)Pp?)Z&W>z&+P9QM1KYYjqC>c<_L_J{`16Y2oI1xg!J*nw5VdrsxiP9=x)eF~hjWKMzGM>+XxY-jQ;e9qP{0L$bHc@Fbc}Zu@>r~!1r0xJ7MTjYnOn0%mq#@DYOm$J?yaPbrXe?ht zYWBSosvbiKMEtJON-PgpJ%eyzq^puo6L<@3tJxzH(lo9rYLomHkyt$2L&s`#q9$%| zEhm^%Q%ClcEz>4X1iC4DrU}QtJk?nAvsAh{JrJ)D(QSclHkp75LWQ)0ocih0YO={? zo1c?jCLRu$u)#J4<;s_Rwi zxge~Kx?{@63_(67cB>5rLA??=iaf(EPh%HfE}>?LIAy{&q<7k(f^3puQs3<1h$YlZ z&Z&8*m#Y%VAas2pAIV5C`_Z~#*u5yNKrV{c~2*UP?{eemMv+j@#PLpFY-%* zz`VC{-T(*s;E@cgudkp1n3ALJ zc{PAV{KgpDF{s!Q7YsNzk@xt*i5;sIr> zpW{X?pIk(&$>dOsBU%@_yDoA2@b5GgJ8wnzj7SCcoyk6PD)B1Jy`1Nd`4s7EJk3{B zv354y!~n!OcnB>faU7J`Zg-a0a(E4*qcX}8Jky1ZaoVtGoDX~BX^!{D+P>Mrl#nG8 zxl&|!>~dRb?)4&^S#TgW`u`yLN5|gf~L_m9YG-dw4uw9Ulh-d%eRUwov*8t zG%LrW@I1*`R9jffwtfAE0r0tM+77PC-T3#~IMq30SgwT0wvs*Rs5VmD`8{a)_UCGV zu(7de0VR4TLAuqs%ddK01U5tzPa;7ttvozYF^8&v(_p96mMdlgQ308+afzZTAjpmO%Ky)WTkxOtP=1QpI{N-rhhgN-KrAvY;G%G#MkN8=%_khbAn?+Tk! z`7WJ{2UhFKh5AK4wsVJzvxaYR`*uD}7GIIsjW@x80lw45H^LDJLLmx)GPLPF3UBx^ zD|bv3jCC@dq00M$y)UnPbg$CpeFDaO<8`c42+oX_Z~*Sx^NIxhO6+c(f-)%0|jtX*u0`T1)I7{=JfbC zi-cPx9_GLJpyG`JbH2!qP=Ob^#w|PYtvMx9E=*IQfVw?4S($ZT4zrTZZ)}_g@+6F$ z_@|C<*jDT^O7K@tDa&AxQ1StYNn#6AdRYfB%ga8@|mgsRd;aUW32EJ)9h5k4(Ry#Iyvq|YdQejQGE znl;AcVU{O;8Gc~u0j3|ns5^aZuhCG&Gz%T|l?7){MSXZkIbD4lk54Nmg1|S?)QFKv z;A%H0`<>9K$~pOHG6m^opz_A9`#f&3k06HQ9)^JbNY-m;jcRZvCC+q1*1-# zGM%;4$9+@9xm345-;qJZgN28oeB~EoaIO1ehpXXV?{C=F_+I;B_*mf(Qf!UJ+S~pv zk6fF6hR6j58ne9^Dd0bEMuxZXj9=&Od~Km2aPj9Ew6sw5t{)ZN3? zEgzU_ktQ);7o_*NmO1E33L)LA27Jq66I?J!;=|+YO2pbnhQSJ%crE>4YYGFBK3?#2xvg zGhR9vpFnL~GW&$sP>R;uHZ%QKuPELpSR3UqjBKn?w6!Y-@qr~}Kr zXM%buBM|P94ik{&hmzI~Ny!){Fx9FleDW4jE`Q%T5yf zhmP+&a^{~W3X9gq%#5MI@tK-!6wx2@rnc@Ti9v+pxR!{Z(z}CC8-zOx9|{Qn@PyZm zZD^BaAL+nm@D2rj!6D0 zuYG?DWvVPJL~?vBE!(lI|C zd)OpB70;V%!F`j!kH}FL?|YQ}caK;*74eia9WMU^x=VA?ZDnuj+;xJ`?bU%i3c=Dt z?Lf^2c(cfwjlbiw<_L>AKSTtq)y zmK~towQL}4mx^wcOMBlF`w3m=<%Nqx5gor{59iMUPmSrjxu#DoiEDI!dEpjOzn~+J zEi7$qu{;c-<02oGM*_*t7-3;YNCsS#o{*T@+uFk4GjE ziHSe=q$+sBa@R?dto~!k$9o}k^FcrEWxoi44p7K@$*_M1d){nI4&T?%`kt+Q=#Rh5 z=g-vAPJB%-mz~NOok?;Iig$)IxRzd zYa_EqLF)~8tFXR5zPLTUmQ<80Q=+gWA>xJMUJ$cOtQZpp;tQz?9=0T;?AEJ;I94>5 z^Jc$u?4>O&bLu35#Mxiz4~O8CKF)uL(r?Ag&2i}Lumqfg3jHQ~4MG+7D}B*tT&-o= zIK?oLOeuA#yi#anyX!tkwW#+HWzN6dHLOHekE`9!9&;8IGd}-45Umz_QF~7A79xs% z#nXz-!wr$A^YWVs*jqttts)9s2{OF(=8%vBb#HH$9L=5zZ=83UXtNGhzZ$X+!hAwo zW&XBf+9_V<Ab3yofBW+Gj` zkSo!S=kT!CxD(Xr`M$Yf)$Dys4zf+1N^LMGJCe~n@%{0b_t*()ky z0W*%V%PWGDo)>jn>FqTEEuiIc`i*1qa0OTT5!rHHcE?h)&#}A1&oWJ*wfvtL5hH<+ z><$SQuH0R&CVpwJ)dnRh&$cb1_XOOv*!@q1hEf71s~C;?%63#AKXg94)0HA}6o}0T3CC|%soS_7a)2vY zT(e6167{Cd{WMOH@tm;_gq{l~`0B9l`$uf&6(p*web-?ya~NwQLTDUY?flBWhw~OW zP*KcMjbe-z0*`0CiWqmzhklf=)lJV{7)4d?<*|JKG21@J%ZM_xiJv$K0?m=i5^k+W zWGoqd#AFbrE!#c-wdZV=R^@evEUZ|`3#*e)cw^(g`dm_lun#$*m8y0I+JuyHymp2Gv5t)?2ExRZ7J7%lQ)YNi3wAdJsgG5qTkz2c{>i z)2nk>VyLH!3^#@$o}BVCnAM}wNdw$0u-Do|(-uBRFlxD;m%adqwL&q1kfiDWR3$|n z5|3YC!L}zeWYIen4qLAJ6@R72`+U);DJzwv@6tf@9z@!ib&rWV5N=->70fotAT$qu zLqAkiwLM34br)iWTO(S`={)PU;bf^9e+fbtbSh+{#ClqVTIm0ES*)f4; zAE(A~y{O44Mx)%~=BYnKL|C+$b8T1tWXqL3qh9=F#9Z~}Bg3f_>R52)`5Dai$dM=1 zO&l`(<|p(i-#4gIo?L22!?7Yk)eJ(yhp(#Ij#cBD60)JRLW+bPh^2VN$C$4&vAfUU zYVeUS_!V(<;rq`P_U|_#^b-Z!j5)7Ys+^I7E94WMYW}gNdfDhZX0OM;$*fv6TtpfV zJBK~-UUszf>t6CQe7mo_w^wul}x9Y%|crrjnT=J(VQ_&dcrosuijJI$EnaV z1M1ZL2Mj@A{C-rNFo^AmFvggB0&%jANOP=Vh#2goItjP{{`1TO|>B6sm$`@P`yxmjl%?8d2q858G$V?_7d{3 z!CQo#N?S~T|HJ+r{Q;ol?h9q@p15FTa*Vp6XzrZ^3P{erDE3$`ON4?t_A|cRR zvzNq|Z$k(7?=6qhG%)60QRZKXmY5=XF?EzI6D~LZ=9q_rHzA4$qGNbVFdfsyh~*cH zZ{@5~=G?cNOj5IC@cy8Ts*w^F@m>;3iPBje&V7Qy99_jkqS45>Rxt7V%B(fVF62p$|ql5*qL&gZ~8HD|x67 zHIA{QgNTALQ)Cy>zU|{4p6pXU;^Q$_)JJ3X-}@m z#~d6RU(Y{UM`ZahYCpc1)p5~>pmMp2t<_@VE6GNq;k{2r7aN^1TQWxb57DtJbHbtU z{ubl#76#2SPJQP@*kVAooan7NFNkT5eAg^xH~8J?h%t$JKhNS+^a7NjOrHj~)xN%#{timCchA zuLR4U%Z|h^93-^+ZI_;-UkcwmgR%ykOd6Doq1NpwmBy;(JC~hhHGW%Jf9-$ZRN54^ z=uMVmXAJ39jrsQzAwQn+Cmm70_gkuoI2lJ%wJ&K@y@iu|tmbZB;T4lgP7$OY%D{$h z@kjmmzhxqM3Wq*B-ZAP2h5X-4$oK8s@|_P@lMfBuqn4hq)a1iA-7NKVYJkln*dXt$ z@6g)t0^D_YS>0zoT55Es3BXM;&>4=@Gt-TcEKV6F-l4HoA8tAz=iM`-$~X`IVw{DU z)Y+&1SXPTX*ShbuZDwWRF+R@Ia}=7ko3jed@;yqA>3C&H8_VXn*BzU%Px#YOdMZif zXkdpA#8hytvlu0eEr^13)p3g458yWki=t}qGy$4yezoG8V^`SELPW{tnV}}PjATZ@ zq@#8$RbX|&&~dp(|5c9E-{#NA8$paw58CXCw0(odrN`GHI`;+i zd1_+ISbe!f+!VsR#(1Pnq!hGw9ol%__DOiBxxf*xHgwFn9;hTpKjZ9<}@g z#t+i=ozS)+mV~}AB*{FVn*npONXx5^-ZC(HzMM*VtY?Y1IxeQC6~}<}lUZU4G$@GH zjS92(1W?A%vQ9ScWCrE5DF_714_ZAvwl~NR1PaEFF~4p0R0NGmM1jv?cce6eg{^c% zdl;eiQKfq7KAL=;OTu6sOjs&>g%P#gJr}+{fbe7@;eA8H7w8^Rt}Dh zHhogDD3{UmRv)0Rj4+}QuX!~BFmS7AR??=fC&zc@l1&;@>;o+bbANevAn{q>;mPSm z<&P^LCqQ=54b{_bf!%r4^(K7jEK+?HH@Ee)1c!Xuik`F293~1Rgty)$TE_h9waL27 zafuv(I6fpwa=Dk+WS>^(Bx$AgKczDVk+p=9sZ+3(X8kC9 z8nRS!&3g*9!{=fMLN@(XYqPezz)D7vOMjuCNz_bqV($=O@!c{6R;PMBsDu$&^SEnZ z>4Fh1v-(H~c;9azqZ-7xkV0-^9`DGWUXi@k+!o0SgRejQ9#)IXu`h_;ieVs?yrgi! z+r`4xf@f70%`y4sio*&K7LI!X-Wa`p{IF-U5*&Lwp)M{gdKFgapn~m~H?dFijObxH zU^Q&Fe$~$eC1|#~$N-G@Ls(+)V>pcSEJJz=fAueTO(?6ahL(7NV@7ir9V=W@#$-P$ zG=QfBmKP{6Z=o8H2RW))=-J(O;rWa-6RNi{>a)s_yty0W*ss1mCyN4DAEIErwW+a4 zR%BflN^JYZzpE(>8|}xeJq}TD9LIPigl}pq2B!6DvVHH7PVpqar8EKmB=?Rh*qKxp z9f;aQ7avv^`fFFqLARKC-f2S>`>mY1NPXZX_K&us}s+QM_S?43wh~S+RFRbvK zH4n@@H#kY&9YRJHG_na!P7yg^*6$FzpezVm^5&lTH;k@`2K`K8NIj@R7UEbJVdGUl zVGN0{-(8Q6Z$nLRgyrmS0cVTq#`X4??O(?^c`tVP{k+UtulVCCD#>8o_`!*BB71)C zAhU3=MK8y12g%BtR|*N?PM&6JGoFI`sfrj#ajppVQ%Ot+xmXy)V%25 z1hr=rP!5uYiUxvK;q~v}ky;`d{-RvyvT@ikS>p9S1VTOY2nR|k;vtt+mGqav@sB@J z3I|`TzB6{cqp6i6Q(tUn%2p;$(|C=T<~6G9{Lue^UfWMpF9TdF(!9V;tfz>W^vZ)y zelxDgtW*8HnaqnM42eqQ^g&6J*2}ePWbG}G_R2th74F^N^%>k3e!(6V)@C)FZCwhU zZ>=`G9{!nP8JLf~e7HiwO+01FzQ)j3r)en%LiJgJuS`s&A}MI_i|6x1JW!L?j2Rw__0g>w6{Q5I2>T|tivx9H{g1E&-WvuYyEZjF8Bdw6 z;z4CXHf!q>hExMtMQYUgi{}x8MDmW^yR{6h3WbbH!lx4~tEv`|JxNuAY6bQ6r+<7S zZpIGP7qj+{|9*}1pJ?)Xkkr$jOtaXnEc>GU^hDX&i2Xr)eV@HA^k~?@jRi^-v7&Zf z!Z7ysoAZKXMpJI|8)$IaK$OM*=6b;<2+$h5;^&R8l zmA32r&HLzZ-@Hh^{U)|nPylP8zSe@DG=v`pE#-G(?FRG~mp6me)wcxC`~xdVec!#YIc0 zG(p35eWhDTUY0CBkpABBt>;xL&milB79&8gw?NanuF8BCMOX{9DMZQb8>V8Brg1P6 z`}(C*{y)UiQsfem_AC-7!M8KI@}&S-?vV?385mr4-|p$}p$rAzmj1QjvtX^xJ^Z~% ze&IzZmu{%){CwZXW~|&Z{w5?j;h14;MjbmUwdu=dq;zlUuZ{wY6zo$T8M3y6m4G zJ0mv=qr5sNZtN5M(I)>OmMwF7bzcQeuE~Pa?sgR}Hq-^`vNAr=0e3+4M6OiTyT0Nd zv^^42P?ln?CgM9A;yXK(7r@W?6+v|*q0Ro0O4KyX`Du5K!(_4}TF^UXG@tK$ zt^dg)5q}6tO2+FC*e=BW`%4Oo7bfWQKtT|aFxYRI3DWWXsL&#R9G4W@E=dHVrCo7m z8QPVmG}y+M(xwk0*8)g&Pni4}NXF@W$IEg2JTa*@q}srz$*DO+@m%+ zssX>&MPsoaS5!E1K=65Z-NKhJDAIgu?XED506yYsm?D$RwYVxypC{YHB-_(2xF)os zC5DZ)bzMrWVoK&S<_#TF>8K`RwtRyomH@zOTpP)*TLH^`Y^RZfO;az%GzF*9YcZc; z3V$WeGMBey_1zzM2Ei*LyYpnv?O2uN;$tt`$Z8k2%iv;Mgm1wN8emq6&<#%DgNFnt z5!}mi#+kGHT`Y(%SVoaKvO2$sa30VeGsqwih@(vN4Sa>!N)wxYFm^aD(-(VaGi-{1}AgJuG^SXG)?=zc7xu0yW5MDg zTYI|S2pT^4=!VrRA zwKJYbj6VrMSSQfgY`KKIws2830|XaAaSsLuKj5{)osywCxEsn;J*M&2lA6y)aZD>FB!er*b2wx zp%@PvjnT_8bLeMhA z3<#tzRjC`_&Gf8j!d0XoIvewb57}h!bS~ka&UDGBZwiLErsx zi<~^%_*P)CG47Br?Hew4Wg8-mgXQGld`PdS$I$p}e^_e+@G;b8b}GG5*B0u@kZ-bo zJVFH;fY?Ep#bZ+4uS4~T=N|K*XMktO_wea?VQ#vZ8blFbnp7^a7pHhdPq5O7SkURV z6kGINnHu{E%#nSnCc7;Mw}*RUoW0-}fA1ZN^n~Q{hkW-p0k=QD6enr89PUnGnQ_v} z{A;wO)ZKIRkgsmD@eS)2?3`ZZMDLaOhlu*7rB84i(v>A!wjZ^x=q4tU$ZGFW98ZN2 z<`4C?8-JIz&@7fTZXwl#VW@&wvSi} z11m%uoVrZ%iqH_u!xd#SHc1<@kerU78dCYnOb)j3KKlQNN?`~<`-Aha&Y;{C_9vw} z);nr+Ra0;;_GQXxxoke{!_wz(A)5$4#C3LVUK&<^J^K;Trz92cx+RHx;+BjwDi$!7`Nbr`MB=CWH1CezJl{BNZKdyF3ll+Cv zB}bWIUL-}UyW!|Z{*ZDseJgzKOKMgBP68fQ5oP$Tx ztPa~W64_f=!dqbu#Vksy6T;GxJEe$7c93(>x{D^6<1Q%BmJ&Rb|2mJh+pg0ZF8*Ch zX3(v1S-PoOf@X}L*X(U8RmZ1zc9Qy3zzr%#Bm>Rd^t-jAMSjc4j?dB(;fG$w3r6>^ z_i@Ikn9GOnY9t01WwQVAL4^F(u*;fxeob%tjWO~;wC&Wcpq|n8+vYKEQ$aRa8U-)b zZ7uW|;%;E1AT8L*boNzkzzlY6Xpw71yk%)E&Z0|%9aIwT~}vqG!3s>d^vr zMeM=uM>$fa8R_aLm{AL_xl5DNGcUhPHAgP`;MdaSWKqZt(T+37$V&FoKkDw6tMrQY zd}JjYu9X+rVJnb;Gx_S1sG6Q8br{egwo4fd5#yF&yKLOzQCCi4QPTu!-yK-2KTWaq zVsBeWSI+kd?*mBl8<7J2Qr>0@SrWfo9H!YBXJHkJN$*vft9-idPNxy79mlx^2ugj! zzrZUkNFv)xme>ueQ$9`L%??@Y6M1jQet?MZ2{-u*YO*0ggVZXB59K^u;lJU zY+niBAv8^xNX=KBdc43H(;D>xVYbh<2y&KiELKVq^()K`;UT~{Y+%g;CyOp`YxMJ% zL{;VQ7>>~FnA3eTVh$2JWyo?o%A+H(Wp-Or)$Be_JRn=h-obizu5y4e4o{tn`KSWz z#J$NA#n_eP7;6CKB5q9aTo%y8GL=%la_FAp6<;yzb-!P2UOLFIZ6+};HJyrY-1q|7$*=7FV)na3T@AUY2@f_ zlglv3a*`~cx9eP;rZSktP0=3igxv-WvnV)jqVGs$`4e_jgX#8t77r6j0^Zhl1ug+cN}h8E|1$p{LJNfq>%X;=?SGMym{pzlpH}?e zCjH-D`aeFFM18^ss%ZVb$B<%l@Cpa59uI&kje^iez4vuc*Y6Lu^d3QZ#dII5G!fl< zxR>BIVcyQ2Bthnz^D!Eit4d$&y=PzhgQ*Ax5YEk=TP2xEM3yemIOk*(gaP48-~2?I zdXtKJG{cj=Z($n)*@B(0<()6p?8c8w|AR~^b*##$nG8F`2E_oXV(GykW9JzUx~!h~ zIu9aSeS#ESs+V%-s$4Z=IllaAD>k36S`k{*koCJiDeBU38=lz;7|O+U_NzS zSk@-RgY;f0K^05&^3Ar0^gK)rAJjq^**By>zWvq}g}j`r03P4_K5G`={zHbn0Cp^s zpa){()`#>2iV-3~vs+;|is1$1YQlh{FBGB3#CokuR|yiRLj&-I4;6$Q9S(wKwi0zD3so7@)5qih5BwS*$>k5_J|(x{|8OIO|TW>tPo58>B)VR2IU?-kOPve=go zLt)8rgNN3Se;S4qIF3itRYg}^?Z%<5Of?$ho&q3+)m+#EC9V2d|0*&i{*l5fxf`_UgN9%?cc+R~62Rls*sRTYga8hlCYZ{W?rHCw~hXKiI z)r(SFG5KOBmmn>7IE0D4@l3-I?uA|O0X+Noq6xUOKx!~x1k$SCA8I+V&9h(@=^5$K zYdAvF8*1);j8PbS>!g_9{knA8pO6)6WgQKwVqaWTm)!a7i+_u^yU$0?>A5$NNUfFa zwW{fy-Ti2n(U!I8ipf&@x;m|f0-7$s%rxE~k+yHbyuQ-(ogOTu5$5E82Pr?!7+30> z1ZTZJQX=lzzEry}H#p1(LczRw&j%WyRuJxokwjy!ep~!yD5`G9XSTe|HXmV+OiAif z$E93(XcTi+G0Z~IU|dCd%D4B-6sd~`h$Zd;hCAc&FT{|~_D;*_cp8?ODY0@S44DzG ze|wNtY)d(Ti6-F&^cxS1EW~880$#(Rq|L;>AJtu(vmz0RlsK$^Nx!Zo6xjU*^}QLD zkl+0*ziwmX(l*SL>;y-q1ydeSi7?M`TPaqg+c4zWjFHOE4Y(R_4dEmF}1Tc}$(vhbF_V!XOn>?FT{>VK)rb5eVv8VWpQQ zQ5l;&m@ri%%BlvdS{G_}XXCr#6NQDeb&7ZayRsflKm5_)^@<*>0NNZ5^jy^!_4A3< zSL!jg4(d`{KmlJB#kulhX>3W%1#Km_+j_1a>IU)-nNJ_yS;Fg`=i?)odP|4P-=rh% zrBWf5RZrlwuM5wiuD2>U#D%0J&iM;MoSc(+$__bm+HhA^(9z;)E?9jbAD}Gw$BkV; z_;&f=GFo^t+WF*K?qDR%&dttl{z`=|n0ZM(Jg3~D3QhSssiDF*)+tO_u3q>qNE=_X zl?@l~QMQKtP%Tz^cV5fyUe9qtxogKQ{3SyeIEi-bKN^y7Mx_T<5%H}M)~#HH8n$!A z4HT?eT?g0EPfQHpDC1v*mLpaM`S^sOKYt5$#bPF_I@aXKDmjmh|2?o+z6w{JefM*8 z3yMv`EHh5krwEC#i@A!14TLRy6!bv?_ri&2llzqw76kW8^if}TE(@q&8nhHxSN3-R zZX8`SJniK3L68F9@3UVDe30L0Wps_5Ovcg2(VwnD1oMgViPR`$ILGNLA;ldFLkg1? z2z~0L%~5}H55MrFN-PBOlXu3}2xAW+=?O`;XQDYxR|Li}0iYtW3Y&vz<~-=RkT5;nu7kjJeL zl#clEH@8ISWP!wzJ~f%hmnRbsl360elRPCYv*WLy zk2@6VT|Z-xmdv(S-)|?}(`vk2rzSxUsn<`U+5B77z<1;$DMtX@$b_CJuoE3Ee!-tp zZR>~gyP}Mo@vYEPo*LHteN&1>oo1uwv2ehs-;6WGT563lAtX`THYHO@vtx$IgOREM363Dz-J&cn=nOuWEn zmoMxHhDq!dk6HRX-gvNM8lbxSBuH7J2Cn{z@jQTau4YxJ$^HCC4ZL<9=%hXmJhJhZ zZ!wu?Sl2JT1^D?4`=eOSIwXHnyJ?wpWv$x7}Q&%iKzwQYjY{Jv(y? zU*B$R&dQY1Vk&%MT6s;5!Qj|{wI?h5e09Mp-C@c=KepcU;aRJ;8*flR!B8fFF45DiLxg9$so82Q1Y{L&qDN#AQjjI=gi==C& z4W&n|tF=&>g0koQ?$W?13t0JhoF@o1pV|fIi+}SUgD$Yv$Zlnc0ef{$!BeWp!M)?xh?7J(j0Gxm$_fQ? zS#~a+L_SGm8s4j%*#`xH10LYI|tGH5Q-;=I(Yf0xr#jE8`0#N zQ-OLdcLE5i7Ux-uS;PF3-b}uN>SUetq)-{!p5~^bC2nMoZLObQ(Bp=ppTrOHGO>N80<`M=ww}#MPV86ULozRhS?Le z4j~Qq>DtVd#k)kk@s%3JwJU7!1dE8lc04YDB(Hj}FX9{54Yx7=jKPWurGIctg(Fs8 zN6eToZbY>e=(_7Q8I5--t#aX>>Wkw^N<>0uOpjwgM8oAdxd+831kE3mUSMy*wT!c69PYx*OS_si(Ti*oa=6i6Q7 ztY;OL#8WOHCy;O37_5|nqrSXABi>=%LzMH}txgn9J2P8W4yUyk^Ne<qJvU68$)_*1{*V0cJVXi^5f)ldV0&8ji6JF|q;YLWf) zaG0L-8}`RFU@sX_!J9(qlK#gpl9EZ_k7rdn<;))ah6MrPsfed3Unz%-)S5SEz0^Ht zA{m51mcs==HYZaY^_=Sn#xyZ$-t=-wPJ$I^K-JnEd1DU$N%aRcDR{1@f#LRY95@bC zPTdohdNDkAkpiB!(Gg9!PSxk$L$Bg;F5=QU{wE#1n%bbdE${)S%TA+r*4bHF;5INoxL@$`{;n<)FpxpS?MCiv-pdMx*Eok6iTE=ALgdoTj~CAs84)sZpBYt zRW`|sh|zil$p`@oWb<=U1)7d2i;&SzryjHVa&&ovXR!;+#$H($T+MCV3BU#gB6IEw zBV{+-ae(RX(0%%Hj7De4#zi3+<29k=@Aej*d zgqF|zHQHeJdjQ5}7OHB@tRdwEavI&l{D6*I2( zto%qEPxrL^7@Ui2WLuJaYN8Q}XlDSM+HCnh^;9tdYAAXDd^CfT{(qnZ)H(;o*!a2S!{jWYVOqq=>Pez;s)E4F?ulT zE#A-FCwiULunz0^YkwwX#nY){Vz7iW3U{7CF>xQdj5$O8{^al;UgQ1iP)5zai&*&T zs6__E;=F}~13+o9juP`Uh`_}@H19iHQQ_01vs!j*A=(tpp@g|ULY_S?BcPUzM|u>f zzA6$vr@*m4?2B2Qk+vY>>c96fs6Qku=3f^Bhxshc~lh&53}}tt3#DfxeMTG z(F7P&kK(&T3;DJuo=tM_TIQD7_&dG?Gcyo|&K>vI-9-SS-(;u`hm*NK)3bgfi^hal zY11GyckoRAWGjErgxs(zUyw!oWnXKo~BV~nFrl*5JfaB!6hznEN z%^joAO^d5<_xcBTGmk7&9_=Rqf$1rpMuuu~=%DXA0R512<1w{h$a*qT#hi_;)9^Ux zg5|(`vP=zhllqQ+=T@Klu7hQ5*d*-@EstWGQ1TJ0-fW>~sxVII4P*%IU|Mj^IR5E*0QPF(s(% zMWbYvJ7_4DAU=FBq*~fM?gIT3o_cMV?KzzfRw4najV=S)HGM1!MM68`4dk0yt#BvL zL$J&kt2kd4sW;hdLF3do5d<|&{^ekbsA04RQ5TE!i*P*S=SLZs~kUG*h zZvaGG7=H2z{a*5dCDn>eMco*MfP}*QOv>b(#rf_Exk&ahp|e{{Rr^G=yoL>RC0jbP zNIWL;^Q{4r>dc}eS+Zm-Vgr!Pkqu`uF>!C0%~7vJSbXT8&3RUFrVVvo8Cj|CSOAL09cJeGRxE(n3C9xhU8Ez+jao zKPt5n>;vtHmoON|pgxp0O}dminqk&_68VpC(MbA2p)e?C?gzxMAmPxHQZmql!$bxg zKXCXI?Q;{aC4WiFdQcNSQX*N7GB&+4dc(&9-t4W@^yq3V)_mYxX!-Vgj(-)$%cLBD zeiD39R45JL%`{TBeS1Fzun?V=y%lH*kx!NI(}P3y zB9c}u^e;xdT(mKD#2F%O)YwtjKRaavP&=r`av&P_sP5O>Z!(4vVXmmf{fdh! zhmmss7poA31P6Qw=w`&NkL9;m0aVcYq>)cVI!^3JWzw36Sn^=r?11*0O#czxn<(rX zN}hF%M3%Brhf-nhO&T@i&AS%D9WKdhx3YzqM&leLrDGT1tP70uZJN3UB;Q0)AqYTC zbxNA!H`g;MSQDW@tDaQ1ap*JCK-XuFyS#Vst_xA7Ax79oKo_>C=At&Ij{gV`9WPI! zp;4kQB_l8@bUcZEE1%0grEP8&7nsKbA%l>Y4BU|4s?5XU^Y)%nm#On*x(#D7ciUOK zrcH25y((KSL9s=XN`^ZjKM(e@0dqP=p~&7q=QuKf*Gr>p6Na;O!4ez?yK@!f z?v~P(ks5{A5*Ykn!TdGBh%ovHVh3_?;!*m;Ifc=Oj!hh6p)>P|E*I@oKj;vazQ z=1aPf@~BPlgDIuJr8EXl^?s-AWP0L-))Re;)XPNLt!oW1g@=g!U&!cgJ2S{;Zw=g?TS^#ILR6 z=1$2h<7~5y&$3YY29LV62TL2l()BnuK=st*`{vUoQlxg~7K2sNyaMVSLV+kUa9ppl zdoIFn!%_P9lB>6zVc+i0!0_u23ln}(`MtfrmKZ}k{4&ps@`iYR5j39viXu$yzRd5D zdY2YU6%K8%;~_xW+Xqr9i#nu^r|Vb&C5(u{AL_tVB>2yHyKxkp<-@0wIg_1Us>1xU zj1%<21p;th*4y^rPlsfC4Wbs`uN^M}qEO;oNn>wYb&Q`QA4%r~nf$&r(ACln$xW(f zkecQKbBp=lx-PkF#c+;nh9_#?K;rKQ9}3xr1)4dZT_yFx#+*}7O|f1eNNuM=XH!!| z8wV0{Fw=|+u_@zr$2joLsF^LbVFI8mkrYvRqk+m|2h>)x4(;>1`HBsyK!Y}pHQjtn z_$i1fh#54;6&y4_llC)BstrpYh=DvFxsrVHeB*by8ym3*hfgtlzJK-*>p5b6bT>x; z9hrdsH%(FGLX|*+66>s^^;VGw=3zOcJ*;L)H(4{WJ<7;q(ct=_Iq{QYP0ISCaoGb&?@XvMuvs$iOhs1@$IO{rJZ-L$(=?dV0E> z0$$1STXFp0D~JA0wTIM-<4DG#6xJ}qv`(_N=e+B+dN|vHPNYO;OnX&uI#?P#?_!eB z5vY;+cd?O*d#p%_Qu#^sN!9zLCclt`A&1s_QaodL+RONbWeLB-U-hMS9a1hDEUn=s z@luOcuWx6!pq4*a9+OjO`pJ!j+4MCbuy?z>P6LO6LmO9IH>nT5ntxuKM9nr;yAxcZ z?&*f`Q9q}KnBnJSeb2r1IX%K3{6$R{KcZ`(_XQWV79o>)z}ySM#m9b;CowZtr@}6E z6+HS9jz>gxv`YN2ga!HjC}afVg#X{U`6~2Tt0i<}jmtOn=MFM4OBlwI-|)nL*o<_J zZG66W3qZbnpO?t8O;w-5dbe(UPl@vw!=xh;QnQ2?Aj9Y4oYU&RYjj%2vMs=-$-jg7 z8gGfa&=ceZ!u-uobn5~a6OKhf=Fqd74K4v-V7~J1z86V>wI8n{k?{2kVoPVW=g%;< z)7`H~?S>UwmZfj|dnMJ4Jm{<>dqs4a1y0XlY?X&BDx>;`CuirlUc!jdPgQ8m$C>Ct zOUiDRpeNr*7mj_vZPntLZ+hi^c8Q6_2jyUTfXuC+Ha{}_Digv~2x6|pvizIiA}?U=VBKl#QpFG_YkM@<-2imXzyy6Uy? zb?;I2X(S?9qEK51N51uhR81a5VnKvVM(YwbC7|g;UZXicTu$wUMzXMD6OOAItP&o| zHZF2LByz)IKvHVRF1adw``Y_nE4Yb&YwVTmIy49JjU_OeKHR|^e_FqB=gSK#xL(5a z;$GqPn6OE9HRF8eCn)dFC17YQW~*Y;C}cYeQJb!HNW;CfE7AwDr?@g}DNH2^8hFFj zv3Xb*>My2RQdzN{U@r@ytv5m+{n#ufpOCI*9Ttd_}yG&Ci$>j zHaR4;)U^cYPOrjAP@bcnh)8B#@{6g9ti>gPH|Rne#Cb?fRZ29Hmv)O!!P$kbf_Q)^ zHX>AGrZJM6Ykuq#rIb|Uxo~>po%d!7wqM7_vH&*wvRpH{-qoMR*)*Tbwx%lG zpDIEEj3;9-E5aG$vkM z3}RV+{w-w!RpR*W<`8%EWGe*L^oB9O4ZHe&d|eRXd(ggdRP)6mjUBCsVflI7+rjbi z&rGD1N|@N*U+alxiD@dO_QH~MwVceiohz2a6VVHA_aX{sG~$LY+VZVGebFb*MIptl z-%6d~6SXa8|M@3Zimt=3;`{YdNK-QDS`&CcKok_$%6r3(S*C2j=M!p!aK`-7gQ%U7{eJ9x2pJNj!{Zi&UvuiB|LN zV{ao8VfgsmuK9)}7Ce6r#^T!>quHJ;iUL0#Ocut6I?^t+duD(7@xu$7t*PhIlpDRn zJAkl?^xINzw(PQFDV0A?P8lof2`sK8sm_^7Z`||W1hwfXsi)hycLq`8yGC>Tk+6z9 ziI{(aZ(Uz3+G$Ha4sfc@0KBcBc7{tPjgnHo2eJ#ia|ydsm+z6)E@=8Ccym23>3z>3>f#UC=SJ*HW~X{5^29Wkdej z@9^jpABvI?B4=V4E|0G~4)+J9I(Ntt^S5I(o=W97{7zB+riSL+0XMAs^>TE#ryvi3 zy`J+{=3pzRqbwAbV6!k~Yyz;VepHvNW2SK!2eHHp8(y-tGhVBmIX6|Xvyom`(nS7{ z7F;`?+2qsdXh23#wof}i)>52rzX3Y3xlfRJH~5bI;3jRNk+`?Jndmos!W{h+zFGhV zUfT-ev1+^qqpf-}ko-$sO^E_5etUdWA@74E1Ja8mAH!5EAyH_gOL!<)`hPo1dmO~n z`_?PFH@_)@K@Vw%F|eW+QF^Bx6Mg;P&Tya;i9lwy?a05|kIQFH zK6d}Z>+~dIn0WQM(6(Y{8pFa`x*X(vC~p>Z^4#d!SBL7?cBSdlS$FJv9Q+(hMsvbc zB7@F_4LwB5MQh?lq$GQzt*IYP$8VQ{yTGN}_GyVa<$cCwN;d4NTeW`IsaV+zt+bq; zQ!G@X8Ec&7la~XX*(}jP^^|E$Vu{pb{Rf#jO%LveYO;i6VHE9Bn%kr7a{<}0Q&tEm zHBHnYSW)9e<$G@t?4sK|(I-@@3r$U<(KFotX8rO?lPD?Hg(k$MHp|NYCiavn zOm=Ak1XVo_%~NwyoAsj|e3EOO1WKx$vVAwE3hb>BHi+N`AuYJj!vd7&O3>J2kFm#? zW&f&B=fKdi-Kl^KVg}KN>`D%KdP-FjZYUoYpEZ^JrAF{NMvhHuTHt{3P#yA_NpNwh zH93KoEBEOAMXrKmoIXI4{dy>c0k9%)H+9v#$lJ#=?)O!PBv(|0KIWl*bV$ur!%}Im z67zw}AXqCs9e1!EOZ=qo_W`xatkJFZHBiql*7Z}It7%iL*5+ml0oQXz#>NcUIZe)%ymts-)s^+uRS~P21b$W?|NY3*Tt7O4sDJAb zCf2L52;uv=>EB84BsR&linz#N-{76&e_ARLLj>4P^=XGax4(Az#7(-)o7Le5vU62z zPAw#2yy-1F8LV;>aRQMKUHH_F$lJINLTrPJ{oPHCbz+8^;MFxSwc3O1cT>7y<_}BD zZAqEZ*3Y$L$M|j z9U(*bVe#edeA%Ub@(?5X(()|u9JLH261#CBlf9(&Z@wxUiKo5qrh_GOPAX0kt5*%R zduG0`@P0{BepFx(odGwv^$5hapiu5H%Pzi>vB$f;VnZDcRNU_6aoZd5)eT0POUvU! zhtzLvgMrs-9JnJs12vZpqy`xW#ND9&Rvjy&zqwZZ=`-B+fEP{Enu)=|7pQ5n&y=Zh z4s*taQK`_ks(wj<)>qj;uy#D;EOQ=b?mP$$u#Hs(Rf@a^e7Q|`e z>x@o5aM#tVFq8{Y>0jl)UR{XNP_yfhUYbX^CWXQomnOR;_k3W&4w+)G=rIbI>_1Z{ z4X1?b{I34R zLky0>8J;=PieAx2vuZsZ>hFR~`O%&XFQ^|d;_K(J;O7o^vTE;1aNxV>+bV**7lCA71 zv2HWR!A%l92y3nOq1k(y2Z2`7xVZLE$iUMT9Zmtn6;P1I)zG1hhy7QK#^ zg?~xb9@-_u(SVY|O*_DNW11_o$XoNpDZ3L;ZEnzlYHeuhj_Xmux8xsFyA_#>qQZRx zz%&a-_;=}(8j<^krJoRi&1uwPUr)>+#lF@#lgBg3XvPQhrr;yZ=QvlBor0*j$%Gq7 z_9%nlS;AS@Y?y}(S^jU#HW(r_$n&1$$_+p29hukJsM7b!8s1n?O4e3*KFnyrw({oX zJZ~X_muHANSUc;sOOA`JX)SH|et*uu6nko4t&AyhHP?Dpb(87Cm6=@&o%ydJDvrEuXt2u$66-0vDfulSNAyFR4R{nm zj*xzoUErwntUoehUa#y@jVBi^(XTr__=D;aFs=GKxb)E%w~;u&)kR~sVLmHS{$>6P zla*pD`$p8x!;EbctAf1}&CS}<-#lE2VKu?_7d%=0n_QPBRPyu^Ry6?*-y@mv_0It& z8SAZ;I~^qs6ZhP6i>v?@hP(TcgKZWW>z^u52_!A|K1_U-n`?wCoLspsOLR`dHI~Z=DD}Gm$`Dbd~kOe!sP!|fA$V9$#oITtzXm5Z_M;_Kw|L(LYu9z)Vt zsb0Hr` z8XEMmlbK}SqZPB;0a_sblHzSOHck}jt`!|ImhN&!9E1j|ID?U!X;yRi?L2H4QqkqC z*yQ&We+M)o>T+I-_dMf%;aCwSl;?JSb5w%S_D*ykFxx7EhwbD>C&Z!HcxOTdSP|-+ z@Wi-*=l~L}Ak9yNl7)$ZBffixui_X=U*L6e@uTL6&J;F(6$WvYWT{ci6G2+j zon}M^u3BsaSIx@^Z>-f_h$PKNLTyKg3+~;6Q@(ps+YQ#b5`WjS2u&~;yj+EFp0RLk2lvU{R$d9`?6YHD^U&O>1_D@ApxK<6ipK^O zHJ9#^{WUGV5bGq-L@mDrBPI$L(i`a1M_zCQiP{Z8r`0{d2R$Hyf6h_%yV~ppQZf@6 z*;cC)NNE;(5%{xyPj@2h%4*iTF9#`n`)6(~V{Hh|FCbU^G1MAg!b3b`cbwj}Pyt`lnFw3KA zSMNmxIW8(Y<|gJ8nvvnHH54pd#rb>(ousD^vv~91@QDPpc}UqcFViY24w4AW9?T*0 zUiQA!|GTwO_vNRXy8ipvab?n;eV)&>D%$ac)*D(@d1=Ske8Ij?-ew;jyE5V%+*9Kp zDDr++a%16BtxqQ`_;Al|)$aGi4EMsH)X;wlxn^W^Q)L&E8Ruk6ab4O`_d=LtWqfmcH|- zia(oG;S(GefOaSCO<5vuM)G^`s_%!=@(p83^YQ7Z zdu-H|ed17N7i8bHwB;HTsu->1+YxHpo+0WPm8f>RTXpI|D0 z1Ap$*lXd#Gi6$43)=tS*(9fx_7E4+!IqdK;4nNypLtWu50xx+xVjx8%5k3^M_A`{% zlzA4Qkh@@PuLpTBMQ%u5skzwJ?q4{D5u-|_>Ag+EihSj2@l;qIS_F zHgFMN;Q_OlTIO!{oSB6WL@e!#uJ`2k^SiIG=_%;5KHXJ^RkSaYQwbBP?;mG~HT?A{7roX2_E;>)lb9DZT^^?Ox7gd? z2IVH(AWfh+206c+K2xOdm*?9-9?|5ZcVTz@A|^0AVZXkOrLaVhrt~bNUUwuvj|?;z z?PtAfoN5nXFKDXNy_C4bG;)|+#10%(z{XbF-1mRSMP{IujRLaq7Dei+Ne~szpG85pyk7@Jd zzMv(YhNDvv(8OeEw0(?DuHMim=!GM*XP}|48|llMHobZ^_S|bZd6@>te|4%T7ri^A zOVe+?r=gs}ej^06A>%WQ)*7t!P~d)j>3RcV3Qz@i?w-zrJhj6M)ugSpW;nV{v!mm=EjbrD;7!0i{ey3&-hYC`^b zQ(c(2Et*(C^~AiBT5osd4P8IBIWF0)n(Rr*#&B!Ge*x$McXf&wLv^wB%JbVFfb$gb zw3;GcAqa_j(0yrSd<_@zGImQ1Tso@fIkj*LAh8@m7_Phlmbv-NVcw>28{@jTbts|5 zvxwu60Jt6?>B<{!zp|BSH%EXuAgtF1AHGW4CnA*jRcIr+Qpz+^b%5LGAx~ zq{_Gq(m&&AUlIO}@c4FXT$PR``YmLDDMU2rsb0(Z%smFk)D36?-)u6FweaZ}>F0jj zg$wEWk|XEQ+lVx)jxPTX1&a%sfZs-35vyGdzt<ex=D6ZzM zH?F5mYnMvW9~7Mw4T zmC-Wy-Vbl;+6QJur4GK&r9dA}a+J9Heou^issgCu$y0}w?SC6^+@=A(RIA;y9q>J< zEHs!X2N7g#&6|DJPF#@hdAReAeHg)$7gl}k+nU(&G;8hZV1$8X*m~>mYU}yvkL~=I z|M>XMeWoR0m3+E2x!Wh#~1d|Gzjpm+PaeX>Kqg&K|?!M8Wbs|Ws`#yW%%T#)BQ zT%i0^868JwB%lBcUJ;_VNN9)_(=)tzO6bdkNln)#iq?8Tg4JAhq%h?B046g+t{6#@ zg(gb$84Yp_a+v)+L9-g!C0?s_PU3+zk-gi~_yX}v3$}KbmwCx(v7&}YS(DnW zaQO}y-62nJg@L=RT_fwZ%r5PtNZ8e<&_0}2Yu(TKx^e#qML)kwYVg9&K-Z(5Pm1G3 zmqvHBbp(dzbkdTvC6k73b{2Gvr~-3X=^qOi4RuPdmEFFD&szM@o`=0rk~7|N(;%o` z<%Vqc^yc{tE$acm%@vI)Ciov379-Kq6)I}@y?(m>iiF@4#XC&n@Y}gpNe@&5>!)Y5 z+Urt*X{g!L>@#qdCEmj(^~_~LCFW*wmuZJR^Hepkdk1n!5(*%xoB-($(-m3iy}l!q5fLU*khy)GrEHNUwM}&3 z=Chu4$m3~MYv9O9fsmrIL<&JatLYXIPfogaHbD981tFeSlaWQqEl)4?M$J0pdYQF7 z*R1s*KCNk)U!jxEWk_{~ahy`c|FjR!pX>VlX2`Yc+5rfUsi@dX&{uk2+Y`9NPPCw;&-Q8T4ltN{z!SZA^VkEkn7>k zeVG$E`7wd71Jg@#=*m7 zc=-r{v{mV4&SlODyTrpxc6T_2yE5Aad6!hkW>^%nbSj?a)U(Raly z_0$RR#$t;!(siILP@{VyYdd&6kSF3H#veRqdsqf$RdcuBAw14+Fuu#=BN-P!s-WU+ zpsLM|!2Jw&!T(6;47XwG6SRZHKaPB}5Q|anFb6`N(P2;O(3X(Db(To4b!>X7afnU{ zo{#zxzOE~#Zo$)a*y4BS@>oBjEif5>*HUd(mTTY<>c%ql^sTR)&>A0U$R@;5X6BT-HP^VoJ%!HC3kfb*YFh-ocP1<-t(tFlLs2GMf??m1) zAygd3(M-dd^A&m93M?lkWr8&wziZ` zV51e%>KCR&x$;`tWU8y=;t6cEm$%v*o2-5Eez~#AFTZ^DfK~pEVRz= zKXXT=zL+m8B77uhRzf#B_wASM*wnH;Seu#_5xR%;hUcez`1@GTw`MJpi)KHy1hzFeC3=^1m(4fV46f|yac<5DnJYqpBAfFM+G9rD zV9wKj)i~VE>q6S<3>xajU)KfNPwUVu0|m&zoyv(j5+c9yb9%I;&*WQ5lOEV(k4{ro zMiwDLZ$@%s#}+cc&m+FDmGxzd%4JRg9l;Cp9l@h)Yy_3O)z(3@&+e<8HE}ps!_{v<~m7!go zTV$P~p$Gyoal>oL8Tc&Tpm&$i3E5EJl02ww3Pecw*dS8&zdVsy$n*oa6{47qJMw69 zlSV4k4f7iVLhL!!gG$7GJBuw`n9W&X-m|^?f~|`k`#b#Zh}rl}GOnOSM{AGEst6^? zd{90#r8lqx!~yR$-*^_uAvdloq9VbhbP9V~&7&V`rP$qXF6%d+{)&QR``Z`IpZKtW zy28ButmWcN&$}|`kdgXQs*8$qRs}_7KrKuK2KYicqU%a@H|OqGKkEQUd=Gmju-DN; z)JDyihl&5j(kXI#B)uW+*h~-}_p8UXuY@8N&9NY~B}UJ2H>2tYcDpj_HPmt*I>t1| zVdSvF=dLAn)!fy74B^@dJRieJ=SI3`dRDSb*i7HUCKifQpb=y;naFRa`+%{5d-Y3f zF}009=icnwJ-E?0_q9#lumtU`!sFROX0xt0BGlYZC)y8x^-j@L8%A5}4$`vMV;8fZ z4Wsk+=cBO+t$26&zltNy+pRdCh7lwqE<4TiwFaFx zruE|+`J99hP6X)B%*Vz#`PXjz6}vv)%{(f2O;P)MV_P^E(|=H6MeF8ci*PAC7x?So z%8I~kAS@60eS`ee^!3fRvA3`N^_})p>9-N_hhm5nU!k<7nCSV*^zSEJlyQ}M#%hrZ zQ;0FBpgk1F#696RUY-Tz({`C|iK-vOl-8(GAFfN)E+g-^JQ>`+ofX#rSqR2Q45N<1 z#TyzHoG`#54zxk*acJXIeD(y-I>+wMh>e~7VrcjCUWLhpP7O@y4m7o4`lD-1^Q!+x z4Mwa#mS=pbtZNeMM2%WhrDzf^@WJ1r6FKO|)s9tk>8dIouKu~D!DY@fb?0>HH`&&6 zH{a*nH{Bt#ECnh#Cr+*FLphSe@910>=jBP@$a74Vcp9_Lu|xjdoqzCD2Z=ie93tFZ zxCY7J@&A|Ip>g34X^S?9`+n-hai?Pf-~LlsUj4;WcN|)WTR#qc$+Zyx z+iCi%z3l(%iyNiK*|gJPKCj|+f{$uAU_XkTpaD%PGZ)fUt$R2tF|W6X2Sy%Kk3 zZ&E6J8?7BhEmIt-W+2m|wIiuzn}ws3QJ9XG?F5o80~NbjGdj8Ld~R-~NX2Yo=4Lng z5n3jS7_HPh55|Deu0IAl{p?C_?P1F^v{-ebKw#=^35D^cu+B^uNBF_Q+9A#?>i6ln z`RAYz>Bi>qXFeENGEvfT?BY^AC#>Tzfb@(dhH}1^{%G&>t{7NBi}ge=umE#qOqbSG zo{>K99}C%%SWjXeqqrg$EBfdP6x}XTLoWweDq3qW|AOc*orHoY<%hX$8`#aF^GE)0 z4RujkTMdds9EH?@tz0y*7GDnBZa@$w=@6Y#p ztDn(iwL3l^q>0bG833!5F%_vUH`cQ9og&E13gd5E9$Z6Y)^pK-Dui^Gd1J|_ zs!t{}Q&+}2`R2%^=I0Rt`nKe~y?1j?zvbX+-9VVy&<2cJFs3Kc9ak25m*Hd#mdj06>KZO5QuA{4(6u5 zmH5T8$U%vrOLB(e(!^WOsgb&LPS)%0Vd$LvI^S+Wq@k`4X}$W3akM0o7nq>* zOJJ8LB|z6^Q86&P)nrzB^WU&OR|Ti7GdlmIeUtic)f)y;dm&tKy5hU{|5j^Lh?=JM zKT2Bybk2iQtbbsyy1xPcC^>-e*du^^C$|enZ4Bl+@eg=QD_o3yNho;X3hg_INw}P`z^I5_;%wfhwG!HrlXp+ z&99?1HyGAoIw2BIBCa>AXbZI;7HdBlG@XmmWtiVXLW;F5+4^{AHH0TZp+af_F)Fq` zMp_#PyGHGrOIHGSL{Z;%uN5t93}m+#7JmuV6k#;SBCyh6`xU53{$5xBma*P-bj!>R zy=Su8+{^F*)OZ$0g*O>{R+;ZTOhXyYZJRsm!l&M_6Xm-D(K31&n`P5c0H6ek+s3I` z^)<*oGwSKm^hh<*0!6xCpQ&s=lYymnTl?g z@z0N>N+Xau_x5;>9Xob(6n;E8L)-L%)rB}T^+QEnzlqB~*9C7;j$3i&yY4BPPDd=M z{5&m(=zZcB<7Roj_s!_jvWq@$o-xPyMXcP)GOf<0jG1#v7%JQ{5)s)gXiz=TAd;Lv zJ3Fhnz(Bi`+X{JKxgE;^3hKp)Ed9OSx4assa?6G&pu&@7atumPNWC|DM_%}JM!@ty zw8ksop18zOBqyKM$(QE5VdtMa1X>;A3Rj7OmIu10oST)q@05LIi>C z?)>*O8JWeeoO|lT`5pi87ZE%*yLQLF>}*IKTKDA2d8ADCyv2AeZZ(Ok${J<3OJ+?N z)jjPvSv6XJi&6RR{=@HS*G|otxbi?d0%4?U;KVCa_!7VR%ts(0Ee68VsE%Jf}`X>28&s14=9Vk^!zx3q}I2A7X zD*H3YSdP0bGKgK$mzje8hT)X7@Bt5>cTW3wv$ci|^j<(-_y*7^OHlx45Y zg!ea33#)OQJb?>7);{^^-F=6=QqdY7n+l5W`F`>9MwEl-soZNhy<`JS`%vv4^YbaP zpJ(FzY`wW3nMb^V2VVJphqL9k=%Mr&_mGBMIOfTZ_xhEsD_%7(j_HYMHqh5a^W+}x z8X2mK^@b`pt8{pryTxyGBrg5)VebC@T7~|%ic}-rP6uL76UTIQJR|Z^LBRDPaO<1Y zW1UN{ZY@9scsGK}6c>j#hh5j+Z`Gf{vVxhW0n8_ diff --git a/CPLD/MAXII/db/RAM2GS.db_info b/CPLD/MAXII/db/RAM2GS.db_info index ec93250..791ee53 100644 --- a/CPLD/MAXII/db/RAM2GS.db_info +++ b/CPLD/MAXII/db/RAM2GS.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition Version_Index = 503488000 -Creation_Time = Sun Aug 13 04:50:24 2023 +Creation_Time = Sun Aug 13 05:45:46 2023 diff --git a/CPLD/MAXII/db/RAM2GS.fit.qmsg b/CPLD/MAXII/db/RAM2GS.fit.qmsg index fb060a4..2c68733 100644 --- a/CPLD/MAXII/db/RAM2GS.fit.qmsg +++ b/CPLD/MAXII/db/RAM2GS.fit.qmsg @@ -1,45 +1,45 @@ -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1691916639926 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1691916639926 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1691916639926 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691916639973 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691916639973 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1691916639988 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1691916640004 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691916640098 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691916640098 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691916640098 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691916640098 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691916640098 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1691916640098 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1691916640144 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1691916640160 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1691916640160 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1691916640160 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916640160 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916640160 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916640160 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916640160 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916640160 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916640160 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916640160 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916640160 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1691916640160 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691916640160 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691916640160 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691916640160 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 40 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691916640176 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691916640176 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691916640176 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 338 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691916640176 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LED~0 " "Destination \"LED~0\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691916640176 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691916640176 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691916640176 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 340 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691916640176 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691916640176 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691916640176 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691916640176 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691916640176 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 339 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691916640176 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691916640176 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1691916640176 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1691916640191 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1691916640223 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1691916640223 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1691916640223 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1691916640223 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691916640238 ""} -{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1691916640254 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1691916640332 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691916640441 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1691916640441 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1691916640816 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691916640816 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1691916640832 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "22 " "Router estimated average interconnect usage is 22% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "22 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 22% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 1 { 0 "Router estimated peak interconnect usage is 22% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1691916640957 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1691916640957 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1691916641098 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1691916641098 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691916641098 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.25 " "Total time spent on timing analysis during the Fitter is 0.25 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1691916641113 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691916641113 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1691916641144 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1691916641176 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5345 " "Peak virtual memory: 5345 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691916641207 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:50:41 2023 " "Processing ended: Sun Aug 13 04:50:41 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691916641207 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691916641207 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691916641207 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1691916641207 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1691922990504 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1691922990504 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1691922990504 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691922990551 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691922990551 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1691922990582 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1691922990582 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691922990707 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691922990707 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691922990707 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691922990707 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691922990707 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1691922990707 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1691922990770 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1691922990770 ""} +{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1691922990770 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1691922990770 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922990770 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922990770 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922990770 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922990770 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922990770 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922990770 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922990770 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922990770 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1691922990770 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691922990785 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691922990785 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691922990785 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 40 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691922990801 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691922990801 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691922990801 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 336 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691922990801 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LED~0 " "Destination \"LED~0\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691922990801 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691922990801 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691922990801 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 338 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691922990801 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691922990801 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691922990801 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691922990801 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691922990801 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 337 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691922990801 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691922990801 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1691922990801 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1691922990816 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1691922990832 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1691922990832 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1691922990832 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1691922990832 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691922990863 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1691922990863 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1691922990957 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691922991066 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1691922991066 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1691922991457 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691922991457 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1691922991473 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "19 " "Router estimated average interconnect usage is 19% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "19 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 1 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1691922991598 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1691922991598 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1691922991754 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1691922991754 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691922991754 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.25 " "Total time spent on timing analysis during the Fitter is 0.25 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1691922991769 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691922991769 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1691922991816 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1691922991848 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5345 " "Peak virtual memory: 5345 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691922991879 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 06:36:31 2023 " "Processing ended: Sun Aug 13 06:36:31 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691922991879 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691922991879 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691922991879 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1691922991879 ""} diff --git a/CPLD/MAXII/db/RAM2GS.hier_info b/CPLD/MAXII/db/RAM2GS.hier_info index c65e494..1fe70d4 100644 --- a/CPLD/MAXII/db/RAM2GS.hier_info +++ b/CPLD/MAXII/db/RAM2GS.hier_info @@ -88,25 +88,25 @@ Din[2] => WRD[2].DATAIN Din[2] => Bank[2].DATAIN Din[2] => Equal14.IN6 Din[2] => Equal15.IN3 -Din[2] => Equal17.IN1 +Din[2] => Equal16.IN1 Din[3] => CmdUFMErase.DATAB Din[3] => WRD[3].DATAIN Din[3] => Bank[3].DATAIN Din[3] => Equal14.IN5 Din[3] => Equal15.IN2 -Din[3] => Equal17.IN0 +Din[3] => Equal16.IN0 Din[4] => WRD[4].DATAIN Din[4] => Bank[4].DATAIN Din[4] => Equal14.IN4 Din[4] => Equal15.IN6 -Din[4] => Equal16.IN3 +Din[4] => Equal17.IN3 Din[4] => Equal18.IN0 Din[4] => Equal19.IN3 Din[5] => WRD[5].DATAIN Din[5] => Bank[5].DATAIN Din[5] => Equal14.IN3 Din[5] => Equal15.IN1 -Din[5] => Equal16.IN2 +Din[5] => Equal17.IN2 Din[5] => Equal18.IN3 Din[5] => Equal19.IN0 Din[6] => RA11.IN1 @@ -114,24 +114,24 @@ Din[6] => WRD[6].DATAIN Din[6] => Bank[6].DATAIN Din[6] => Equal14.IN1 Din[6] => Equal15.IN5 -Din[6] => Equal16.IN1 +Din[6] => Equal17.IN1 Din[6] => Equal18.IN2 Din[6] => Equal19.IN2 Din[7] => WRD[7].DATAIN Din[7] => Bank[7].DATAIN Din[7] => Equal14.IN0 Din[7] => Equal15.IN0 -Din[7] => Equal16.IN0 +Din[7] => Equal17.IN0 Din[7] => Equal18.IN1 Din[7] => Equal19.IN1 -Dout[0] <= Dout[0].DB_MAX_OUTPUT_PORT_TYPE -Dout[1] <= Dout[1].DB_MAX_OUTPUT_PORT_TYPE -Dout[2] <= Dout[2].DB_MAX_OUTPUT_PORT_TYPE -Dout[3] <= Dout[3].DB_MAX_OUTPUT_PORT_TYPE -Dout[4] <= Dout[4].DB_MAX_OUTPUT_PORT_TYPE -Dout[5] <= Dout[5].DB_MAX_OUTPUT_PORT_TYPE -Dout[6] <= Dout[6].DB_MAX_OUTPUT_PORT_TYPE -Dout[7] <= Dout[7].DB_MAX_OUTPUT_PORT_TYPE +Dout[0] << Dout[0].DB_MAX_OUTPUT_PORT_TYPE +Dout[1] << Dout[1].DB_MAX_OUTPUT_PORT_TYPE +Dout[2] << Dout[2].DB_MAX_OUTPUT_PORT_TYPE +Dout[3] << Dout[3].DB_MAX_OUTPUT_PORT_TYPE +Dout[4] << Dout[4].DB_MAX_OUTPUT_PORT_TYPE +Dout[5] << Dout[5].DB_MAX_OUTPUT_PORT_TYPE +Dout[6] << Dout[6].DB_MAX_OUTPUT_PORT_TYPE +Dout[7] << Dout[7].DB_MAX_OUTPUT_PORT_TYPE nCCAS => WRD[0].CLK nCCAS => WRD[1].CLK nCCAS => WRD[2].CLK @@ -164,21 +164,21 @@ nFWE => CMDWR.IN1 nFWE => ADWR.IN1 nFWE => C1WR.IN1 nFWE => FWEr.DATAIN -LED <= LED.DB_MAX_OUTPUT_PORT_TYPE -RBA[0] <= RBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -RBA[1] <= RBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -RA[0] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[1] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[2] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[3] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[4] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[5] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[6] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[7] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[8] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[9] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[10] <= RA10.DB_MAX_OUTPUT_PORT_TYPE -RA[11] <= RA11.DB_MAX_OUTPUT_PORT_TYPE +LED << LED.DB_MAX_OUTPUT_PORT_TYPE +RBA[0] << RBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +RBA[1] << RBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +RA[0] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[1] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[2] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[3] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[4] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[5] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[6] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[7] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[8] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[9] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[10] << RA10.DB_MAX_OUTPUT_PORT_TYPE +RA[11] << RA11.DB_MAX_OUTPUT_PORT_TYPE RD[0] <> RD[0] RD[1] <> RD[1] RD[2] <> RD[2] @@ -187,7 +187,7 @@ RD[4] <> RD[4] RD[5] <> RD[5] RD[6] <> RD[6] RD[7] <> RD[7] -nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE +nRCS << nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE RCLK => UFMProgram.CLK RCLK => UFMErase.CLK RCLK => UFMReqErase.CLK @@ -243,12 +243,12 @@ RCLK => RASr.CLK RCLK => PHI2r3.CLK RCLK => PHI2r2.CLK RCLK => PHI2r.CLK -RCKE <= RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE -nRWE <= nRWE~reg0.DB_MAX_OUTPUT_PORT_TYPE -nRRAS <= nRRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE -nRCAS <= nRCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE -RDQMH <= RDQMH.DB_MAX_OUTPUT_PORT_TYPE -RDQML <= RDQML.DB_MAX_OUTPUT_PORT_TYPE +RCKE << RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE +nRWE << nRWE~reg0.DB_MAX_OUTPUT_PORT_TYPE +nRRAS << nRRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE +nRCAS << nRCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE +RDQMH << RDQMH.DB_MAX_OUTPUT_PORT_TYPE +RDQML << RDQML.DB_MAX_OUTPUT_PORT_TYPE |RAM2GS|UFM:UFM_inst diff --git a/CPLD/MAXII/db/RAM2GS.hif b/CPLD/MAXII/db/RAM2GS.hif index bbe8de77bc603e6e1862c1aab82adadc6d0fe75d..26016a1c02ec88515ea0f079d0b72ccffc4c1089 100644 GIT binary patch literal 596 zcmV-a0;~P34*>uG0001Zob6J}j+-zP-COEESei|{NXD2)aCd1+GE@mnA<5SA7?W7y zF$EKKH1ywVAf1PT+Ai8vD?m2qUi+SV&-vW2N;NgStz<61UR1R#3uut3F-7o0BeMiL zGXxR2#`qc|gTVL`TuUXOmq?{^f$ajrCawj-49G$F3RZHt-6v^j9~FZ#%)4B~CHTWsV0)*s;>o(Gyr7~Y=w*a)Gggdhw?ldz5Yc^#$DBJpD<(_<&j zd;L*a)T$5Xj8~j*c;LUfd!5%SX)GI6i literal 596 zcmV-a0;~P34*>uG0001Zob8lPZ<{a_!0(p!9W3>-9g-Rc2=ta^BxOpVgCtkWF($DD zrUMf#D*f&=khPV9wjH+9CT!Wf_w4uQXZuS{OI26!p%gg>J6=|zkkD|)#u&kmwa5}^ zPZ31!EylMP87_=J!cCpq! zl`2Yl;2_yI(QJ*E@%X**Va#MYAi05AaS)6Yk8RrU3Cy;ekZ2uk0ni&+qEH)Q3n{Y_WwJ|r&=x6#}q@%=3FgXJ5|b+ElWypsFNAdEb+ z^CEv0E?+#(!yw*7+xaH$cKxC5#Irz$5{3_#cr1j_i$M?ugGSgwUA>NiYe?+aVtQ)f z-04n)tW>AYDJu(I&#yI?jDrqi@(QyjHOv!T@kD=`XH!U?lv>^-1*>x%RMi}WI@bH9 zq&YrR4SURz%Y2m6Z<>B$*;CuG*wnH1so|Q)GPz-zG)4Qp!)*Ky({FwUd3!u)ru0=J zQkS39@-)mJU-8HP@AF?Ln)AFU&s}+Rj{V6W=OP7&BNN*bgPPQ3`kcGiwlOs^=FY@& ijp;95gJyvH-GGd+B7f9#`SbUqwaU2S;N5pD&>nzZT`>Fr diff --git a/CPLD/MAXII/db/RAM2GS.map.cdb b/CPLD/MAXII/db/RAM2GS.map.cdb index 5bfcc1930a3e1f259a884c135d62fae5634f9967..04f5b07b1319712dbeed241377424d550eef1d4b 100644 GIT binary patch literal 17914 zcmeIX<98-c)CC%2;$-59ZQHhOJ5Ov)Y}>Z^#I`54XJXsA`MvL2_rv{k|A2S(T3x-m zx=wXh?X%B0yMKa!fYiW&exE@=Y`zcH?^fN+$=S-@j*y9qo{653P}tSV)|8N)gOQMt zi-DP$ftitsi%>ed z#+uen?|WRGFWl9ur0Bmlglz1W(1aD40M)vA*}U& zc(r-vRBCl@BWmuU+5=!AnPbgVo4i$^xrJzyN~WzpmLk-lxsCmmA;Vsi~=|Mg1CfmOJg1m8x#3i?gNel1KH8 z9+8do%g(yfmrUT7x**`{{867}>hsCvDy=|Gx)j&*S ztJ`Nk|91m$r{hs?=e3s2X8Yl38{OvL^V^c2dW^3)r^4C~WTpOsUB!JvuiHKwy^MvE zj0NQ)nHc()&FLfMvySv+Z6#~53iO3E%#vlfo$OR?J!{vBrL8Xdmf9$(3iJ~7WNjv2 zPbKTE`)R9+r4sct?XBsv{~P#!i}QcT`9JUYKkE4ZL61`>;MTuuAA35R`RF@yn?qxI zX5AJYJucnO!`wCz-k!05?dyLvU)*Y)Fs!pTuwO5I3lR2R>c8~YG(1?FCB2_c>Rzw%j9ldGmkygy9eaV`Y!pYUmv}%kygfSZVWKkaDD9;5Z;mN9R!dqBC*O_=R=C>rB$8@#I926szatR)px^zV43!^+ z?Se+?APoKtePAcs@J$@s?KpmSGkUBBjz?X7OF1eZDLl~6M_1X_R>00aNCWD3ztYoI zYVyx0j}LigL#6@9)Xu5J9P`e{CeVjaY4$8@byXzzUa&S$B>-=%bb8C0D%o-aisy$K z%f)cW5ZL&zbx<^U>S;vFkx$pZca5s<2M$&;f$I~F*>j&H#A7;_I%0>j!N`V>r^=^c zd*u8cThHUpm9DplrLX589@~~d*wbZLH|o>c-}+n!Hbs$pHC`X*E2n1hmZ$hKb*zYy z8ex}Jl?SM64_2L(UBbK?iymb&xV}ttPmQM)clE>FaMsyx!zx}VA1NNWKGF<@9c7*& zA2M?8m@%OZTiC)y7x;c6gy(Tj5`{`ECa9%C9*xE8HU`R;LuqEF{y*Lo_|)Q{W8(7W zqslL>^o@=#Ml(AseNL7QI7IZT+MWwV>je>D(SSN|ZwVLlAs@h5Di%d=y`{QbD|D#~ zogq~@h(YMCaH!?gSt4>U6^TD`TM3`;Y?>em&4IjskE0@baG`4N`q5%7P+{~aagb0a zvo7gTQFy{ch`3;|20rpTo3c<6dn<&l>S0|Ju4kx1AX@K<2#8ZF`@a(67K?-qLT`)D>j??)&j7X^i!2fB;kQid*^qn>6*pmq z8{SfW*4=_H6;RY2d_t5lkO+I61hOanz|TtL7aoix|1tDM3ZYK)dRvh|d;D7572FJW zImsT429!|K@K6d}la`C*c!=ag%+iwF@mEwtRFs;3ZesWGv`5}8D(H!* zkg2`gVWsvQ!bEPPWhsfYp#M%yji4qr!AMB}^6|70&2-xYh`1ajJC2pAD3%k62qu+& zLpjoDF7Bl1FYbicj7!K!TH{|iq`Vi)hKt;8cXxXh2mj4M8aH4dqJqfA|DJ;K(jmo1 zh&-A4gs8nB_%E&Syb`WuSgHuN&G=4yHYcgxeRpfB&+$y~-zOOWg4ZY7dH~d)e4#&_ z_!8KTH(p!6?uQ|nn5gOZ-F@0ecTeaQ?Cn1i^+mg8J$DYgP#kUJhJBwDs=Z5(KI}b+ zwZl1*8OLjel3qMSPEhO)MDuT?)T4=G=}=e2{)xL$XZqU0v(nq9q%$#KHv~u#;Y_-m zJ2FwTzw#IFzbkYX0O45q{aV0CKnl6TCg7mvbxlkNvA3IfQknns6(b|WAxH#!L`3u` zS-wj-aD2YrZ#{FcJ6&b2_7%T~o6J2e`k~@-{3gQ2rMMNs2G_ZEF|cS(_-Y zkN&aRx)}3Jg@1HB>l1i{#;8N82#!$QkSBsINjNe+fL7*+zW5>tph-4i(7XS9_ zko%v{DLu`V@(7Sa;T*|zq9fRzWj(LHvDA{`ny$2B{qzu)ZLnjau#N0xhC&0YKx=OQHkP(0LPv0`_k zgU#2>wS}dr9230a#O4(L^oX+*o|SQYdf*OviI+V*=_gLl46+Qm0uc@i&2bHj*&(Xu zd=}O3Etgq-b|_Q=c09ykm{BIPZ}Z<9K?cs+6(chEBFrk^-N7E*(U79B7(u*X=-zUN zja!a=JuiZ78En4y;!{0le>2HdSQ+^_N{W+Ri~YU)<+Qbc%0^@UKb&ZbF)=3{j&b>p z7v=~Im-O9rF)@UCFyjKbgzUDTnd^I_ML_I~K&jlmTq^p+%=k*&i+>HZOk)n8Qz@8Y z9i{DNKTM#PSKV=*<(sDk!IOkp-?!1FF7-%Tge@1L%~S}GT=`0G6)3`E0!+VA`mj!X zFuJ^D`wb7$)Bo=m@o{hjQ%`qh5|DennPBrAsgu|)--LVcxhy=wv z+TiCGeU_eP$b4w2{1HV+N=;SYyY_DyHAaY~b~_@jXkpsun|4eMRqrO2*oygQPdW#y zZvPAkc`zCafFs1i%;g7$y5P<|_lqlhJ_Hj5mCvP#V6z=~E=Av2hYvaz=4kKHg@o=D zapr}p9y~RX5X(HSNGXrI4Y@{c&1OtQXWoc4{APM5E{ny*VfB7M9Bob?Xj{e4srEB) zG(R*s{bXMY^^E=YdxHDDhc^BZ@9F3Eyr9lfg4Nt=Y=Z+{Pqyz$(WulAHFpXVC)~H| zBl2*H##eliAX#a#Mc1S$xGvdsTMnmuABa*VK&pMpK;*hp1fqx8QY4Gtw1>MGDa<(yPjtmYAyOBn108!J$EMy8gsQ# ziiy&tWZRX%g#K?7>O9DL>U=+tXlTR@H*1xbNJaonRgpK)XIsT`=&F+$NyR=Il%4B@Qd2RnOdN+g#Toc~^%x+hFf|j*?K;nG}tOpG~Nq!e_wY^;2Nx z-s#8^{1FMTYv#|BG|kV&XaTjL>=huQpKm%k=28m!r_kc@WI^<41eR=2IZ~{@{r5VY zh2L?aqF;Sx;*y%%g5tzTY(eAt-zH#L>Kdp#Y2vhu)c0Q{>)jl=3nMuv^znVg_LccH zU?Ae`%!Ek)T>J5+z~=j6$!KbLu=?8L8nbCSH2hm7d~}CHtdt~C*aWDt)F&VR+yIqN zkJ|b|^QXyk(meNf@83}g4?GaniC}dJuA}&S%_fthm(XGnhll%gEzaJSQ~rDF z-Z?{qMW(V%rWc&PBd$~=f|bztxK(3Ybj<#y%bF95t)`ab@0hAPG8hj;qJ%VhThe$M$`P8?dB{oY^_GI)X#tr z+FTD?PGTxnO+lVG60j?S4`l$hWY@l9cQ~;Q=w6Q8)AMBds`r6$K3emyiSQ_m@!DPh z8Y?VnxMkyCYrro{TVHU^`@$QCgMsro%TQ|zWc=vW*>8SmENY<3mvC^L!>t}y{^vQs8$Tuo z6z7XOVuVD_VUvw5NboUiX6mI_V|gm`<_v8)IzaZJbgLmbflPpeXvgq>KclwVQ|p!{ z=3}d^ZF-i%Pyf!q=Bg6ky_5G(U;UDkc(1vv=&1&Hx9N1LuF~o5?E8gY&xq2-j@SXa z!jSv2*TcG+Zy338OY}`7WO$M;hYvAxp5D6qt=F8Qh3s?=HwBc?0cRMqy2kJF#0P=E zC3NFK>x>^V&pvuWFe2C61{X_t6}wbKrg}Y~K6(BgVfGhp6}^UrS95- z|Kwv$T#6qD9$Pe~=RbrPsFZ)z?Y^Su^MuFz#HncGY^h|g?f`$|oAyHkiRpim4Bg~i zB5pXYz<`D0lW**71f~2hny;)Z@-5Cf%3@>RTCY7|uq?0yYx;-BIWq0}gkPgCS18Qs z7>EG0i2d4V$ zSMh|WCw|otCcJdz(b*{}ENU?~?DG>x_|Yh&2$WJ0Ll|={Nw{NEIH-ZfGdntF#o3s_ zSJ*mZd|Mue_W$@0Dt=^B1ttuZ=AAE)D>))K3!ON?WA;lE-N%pP(8u0@# z2Dcz~XR;FM&crw$v^gGXFW~XOL?B0rt5?g-H%BOdLYGIlkb(Sly-_1iEco{XWs}pV zISI%A>ncN#c^e_C| zx~A$gJ8pQ+-|1A$!*V!w6ALxH?XgT`1S36pO?Ji=6dSD56Co&}9R?G!INw`En`BKR z1~RPdY)N#wpz06UnUeTxHFZsj-EQo6^ZvqJ4!C%;;0`vl#mIn>Fu5=jsv`C4c3i(W zlmRqrF)U0f(*1Nn(WZ%xN^q1E=OGJwzp}%58^3?1V||%dP16O@ZO^_-kzbg)BEJxZ z;wF&e;Eqh-oCu60RP{uHp;Vt(>p(1?ZS3tN;c=`ydA_sJvFU*%Msm)yNH_`NnfR&M zllBRzcq~H$a=GxK^7L>Ph$z8nJyP;)VjH79Dvhli0yJ=h{18?cq-Fwwx07h?8+Wr6 zWflSjaxD$kmVH%#pc>8mQyGXF%Ql;(Vd5;A<*t%s1^kJQnddLF+D0EGfh=0=F?Maq zpliXmoBt9e1lbM|%lAKkNQ5W;ZS!xYcZZ3wx0}k@k+m8U=fSo#R1Oc_$?GWINT&ic zZhae_#}gJ&^3x%uH9(W9Z(IEB(Xv!Z{c^`4|u`{ao)>$J+IPc($+N% zJByC42)_?V>%oxu&8Uywyim)r*Qdkb@JX+2;Rep6mT{uR#1EHRV578#h6VSnh!6&X zP~N^LPy9w7oTiZ8h2BqG$QZ`VOF|r*%-ylx4&zrs>-&F-;*fe(((Y#XG{;k)>x|UL z;r1tY(@mKTQA2>w_?j(2DQ^weQxRY~cm3g;tuv(wD)K>rQ2Xs9=7(R^pr7RR%OLpc zUeI@y5WRm@@bwjFYG+wcK9;6=dUiK@38d5QA^im{oA4q={mcdV9Z6E zUJm&I|3lPC_Pzwe9`4!07kPti{~3{xsi_xeA&c^uxPXbqhlt=??L!E)Zfhw_s+bZ9 zTNkVkndAQD_jn3D@g`6`g}KBxZPSKNDf#R!@fP1Uy%M|@e86jfW`4J7lB*`L+P2kA zE-PiUZQss*SlaH~f_Y#pCznB5RHSc$*j9=;$k3(q!fxV1wEIt$3OJLW!`sE@_7E4zs36RE8?hyt#Y(z8hcd$Y*$%HgDonQHAlg2?Fz5gUCZL(-m>E{`_POhvSXJJa3R@781#{ zmwfenHNbp->SieZdfOiFWT5wxTJCkrJsqY!DE!|3#i)R(lK=26er{n3OWv+EW#g%B z@aH<5x?xYUp3d?ot1!gC2M-o*)3X~m2E$O!o4eICvR~xZ3QjeL_*Px%d{aB{$r^0Me6e5*fc z+A(FHtpGw2TBW9T8931?oCH}?A3xzbyoCB$IoLO0(c>>|6Jm0^1BN#E;?PtXXTbrK zYrt_!RSAO{+tY@(lbYLRuDu*$aV|SeRExZGHXP(3n)iLuel7t|VVZ(Nf_0%vP$Yt51Qq8A=Qo)b#QbA$2Jknvr4EYz6H@kS6g7F9uE84&N03#@4d^ zPLW`+)Hb=;V1n#NUb(c<$3FF0QH40kg8|l+9IJ8z3TlxU*+N?-8AKfw_r$QD)?+^4csTYJVu{ zA6bv5_~@-y@AO&rjjIl?7*HJp5><7dQ`ovH2fl!z&UJ^63BMSXkV&4rxN-4uhyfVVNT)> zEnsu$hsuyXYwo+|$tkB$CAifX-nClqhz6=GPFKLQILldz`F`PI<}5w;Jy_#jF5nR? zK%-#(akE(xx>ME~jN;%OEvhG;FXQ_4S}bHhz>GE8j>mIv+#HCzM&Ca1I;F{K*jd8{ z?k#GEp~HJ)e-QLT)Zmh@s&2&KHF_6~iT|Ads5Jcy%VK2yPJx`rX5t?!J5i23YwT8N z{;WH?{)=eF+c~$@7e3&D?=1W(fn6|K0&E=arU%<=la|+I)9*Lngr(_}RPu@3sn5AS)5DAOPcAXP_QGN~++Nm`~)v!Cn|Lq16Y!7|}A_7%j z;pv8QaNpEMBl%3HD4t`edlbp7SjKU|&T9D>>ONpIcAaq;{kgjN|}_#7)}xYtPc(^pd82+&y~b)AZzwaQ~amBseq) z4veF~zP;zun&`^j^UZ?6ril%^L{^9V zW8>CvKe8AV1h@R($V3PVsN?XhyGqepxq!%hei-yTiHhK#r4$JB_WO|BO5myk*8gtj znvoa`gKs{Vej5R>?C)!&oY%ETIn4^0>gwjN*AZO{NB6q^Zqccsxop}k_s-Oa&tGEY zA%(*E3Dh2WUV$e?-Z$TiAlcQCpimVzpcdh8?LLGEuKUX1mKbPQ@0E!6cu=83HQ;t- zAZgeE^H0Zeq*zYPY_|xrnpihA56eQgfaX?SLs@}2+Um{gzI49oX!YurXgq*hvCfN# zSXt}sgHbfZB>k^I=O@oBXj&bQj!=NgJGejdw~-nS9!OG%L{^bj#oKg{C64cNHI*XI^PTVN_kK5$zx>Ulp+RTrdoB>llot-6=2`piF6_BmUI~dWkK$EV#he?&%AB1K z6LU8;CN8Z`Jq>Js9+mI#`H^b0RI<0KG$I%9e?YJob9$O0*IRK6zr5JWGd+&+epnBZ z-TruHF?lDD_k@pqP{jDoydQoKqQ%**z5WS(;(MJEiQ{ejH%F1{VLn-Og|8Q8T;OV^ zRqER9by*95u~fYSZsKc z;Y}NGFb*|rbP44kjli!ja*mD2`oy3)6HDr#9oBIfHJddpCdYx6Ah9e~9>p!rhm@C% zC=Tg4r}Yf$m&Xw9*C6Gv$=o^q$G>>UF&}je9)bY3+pD;trK>qFm49x2f}3^fHn15I z_q_dP9XaoP(08m;?fTaA>%q@3^lGM}GJYf8!f_rhdmn7MXFrMfjhiJbAflWbQ_6Kd z|9EO1s#k294^K-NmR+rE4oVC*uT9bitG*%3mZ^j{`6DX>=C++Yan}+l&VI-5g^s>H z4lajg$ZiLJx^Bs1UtZoWVavv-Bw(`Bu=^IqY9c})eg7rJek8t%D;zb+I~fZTmk*bC z0-SVu=&NUnB;)K=s>zvFERA!|@S7^n)a}f3l&3;c4C6R7h0yJ^7J58&8@OQhjWQcl z^(>}866Db(z^mH2u>EiwZ^)ThtILt`F2|!9)DZSEr?`uR$OWp!+fYP?(Fq>X*8mWo z915GrIO8In-G^RAyD9a;mu1HKWtgB@BB!AL9nQ)k?i|LbaoukLo!}WobOcDCn_vs@sV%+oKJH<(%ZJFE>qv5pYrF-K2~C<#O6Q!x2~BJ$tmo$ z(qOU4RKSRN(j*|m<^#&UNucou(jj;zjcw-VbKy;)WIPJB?9qlA*&yGE zLc55wyO~(E%v3WM)uSlz7hTlnjPaJkct-U7^c?y~C7KH?bK)UDsj`srh5Cw>nTG5Xa!&Ts zvyHZfoe{e|UfWeieDf3g7y`%)9$3HWo~gxHawT{wdDJ4tTiE&O>uzxcI;S~yNW3E- zIgrN9(@PRxjFR3}RtU3p?o_bTLh{5>A|T?H*?a}RhQZDN_I;RkgM+wm$T>M8?m}p1 z5cYL#?=FEv3r{v{W4t9WH~KpRYcaFV+<5dSd+YSUKB_c#Tm{WMf9Okf1a$Hc_2+t6 z3bu}VQ^srdwhg!EdX$~kfWcFP^Ox*v{uvLaqmf4PZD}~UGvi~mQ^SFSW{qMP_^xLA z?qgJ?)Y7ZK;6oPJ9Uc0|-D1BE+4G?u1d;9Ul%SZ9e=K0^;$7~-ov(0aXDqTLt>s-G zgLX0DA)9;*sz^E*$k&e!D#MD>n)|aekV)82PmuxZMBj>o(5Gy;rw%u96r}BWs=~Pu zeW7M&*)3i7koxQq#bZeGIm{c+*dP8yF5&bwoy^|<1w`@V=kiS=yhV?DUEcK#<7d7OIhEyu<~Tcv~aeeszQkud7@@em>y+} z$s@|eWN=T&qZf=l$s~?HfE$y>e6_OCLRRIiXkINFLac@7fuvC#l6vtqjwERGZ0LgUcL%3vPtPA_B3_04Ca z?!%{E9+9h|knAr&(HU{n`6Hg=dazxSfmg$ymtTNz#wae{mHCf+b))i|gz=e|XpZ}Z z?H1StRPf_uX5RGjk?#Akp2izwg=0qTN8Y{lDE;LIq3OU!otK&ZNy3Xl67z@kG4q#M zoow@{+ok-(y*GWDl-}v<%u&5b#v)lo^Xc585Qje5P z{g%+kOElu7={AGZAvJ*L$oh9;#burE;pwlpo;nSlu`v9AVS%%U<2C#Yg3FYb{KYzi z+I2gd6%y+$9G1=Y=a+1Hi*uf!-9)8++kNM}tFOY98UCFomu3=YD+ga_BJod;x+$?r z{a9X|C+SX5rmQkG?AS(-2?Qe5X zdYG9autl!5!j=zMur@-@gCF8w^&Izoo{WF+Ck}mN9Mowr&YWiaGG5j>q;n^ob~fr@ zI{lhey0eq$dVa5AXVPV7dGnsO-pK}27{7A4pG=X-M{WM#q-&}C#8J4UJ4mVAu(4e? zJZdnk!J1HAh4zFvLWgX3etx{GVcZBxI{ejh@kBW_&3YtlwxOmrtcZODwRS|aqvPvZ z`r3Bk&9Sjjaka&JpM%4{i<2K2Pz;b9v}aJWxTIsR>qL|Wm*jEfZ=V?e8rhUtkm~SY zu+vWvvCXf`uZHe4!6ah1jn7x!>2H&m2h#?lAV|(LG7hl zLur)Lc}3_WzLl?8lLSs8bFpI#B9#&DWEH%XU5AXU9N!50 zw$pU{p*ychv7=2WtA)%I6@iTl2GECZs0Y<}Mg5Ik=JfW}BP%KzDJa7vJmawFO^)#l zml>(|s`ItTLsPeo*YCsP`L*|72E}&M&A4pKtw__FEjO~~XJGj%I9HMU9C zZe?|wUbrvB7H*D3bY6!~Vy=zC4>4s&^bLPkIEz{&kB;?>`Y4Y9QJjs2pR=oMdML_Gh~;qOO3JL74`j*_12m*iAMp@CZjS34 znm~fZ9uV7sGog<|Dc}Peelw{cLke-@qt421RPpTCglD9%g74mOQv;izLh})x;HF9a z+)(i>cR$9+!H0Scxv&Wtq;L#CAKLZkb&6cRe`?rHg8yCY0&AQGxv_VWhk~h?a+f=T zj?eM*{}lydgb|uYFq))1eo^sNJR<*XfteedP*u8Tkz2t3yat{?M-?do@M%4!|J{}K z-9sJ#W&+xXZTmc+Xbaqwic$WP_aZJ={8N8K5S9~R5<*rLnNAY0herllSv&79Ds>x zG&wwkon%%y>z+xWfH^g&y|b2MokF^aJ=z{O#c&KuW;x#>KK;Foq3IrbWn2>nI*lpfk~dPg~hrHgG}yZdsNb(W_d61=?gS&ubFb{#_~$2 z$^#1v${xHPI$q2Q{b%vbPSX;e0}FiStIBVxx&sSri31ylXEA(xRC92693`*{=sPKL zpCzT^yk=6@`L-fIlCSSgeSw~G9ur%nyt6U6Dhxk(#Jwl1_`A;9) zZHqY1(I?4U7Dhsq??${TmFk(%Bvw(Fw79Fg>bOrQp@o_!Cs?-l=ncUq)FtP+P0TPV z$pV1l$3#u?mfll8$;|fx$`8r*r^()cM{^L;cqF~G%GW1IFsU_-5eksG&3?Ly8t`Lq z{furZ^rE(XI=}6Txlq;=9}WgmYUjf;UDLqrFKpnSIUVvPo2e=YF9u@be5T_UR7w^Qkc`m}P$R@g zp&qi(UdHo4Exm>p8RLw-GT*FpI6oM}h~!OH{=-6O{j~iJjBWC3#y6`LOfo>xP0KZ+ z+_DwV#g2_!U+4U)Pm=#r$Isgu6API|=W`RXBj7`FxKS1uzbS<>e_?D?n+*r6|ZXK62OW`mnpx<}>$x z;J(|U0}nH@4Qj|3tCaaDEYjN&lL2-N6&}}x0|AeO^aV0=hGDo0S#?uq7nl{v#P{Fb^;CaSb99%{O_ZAW5F~ztohvz<&q{I?l2@I;YV_%!K)2I#5Qs?WPs?Iwl#Vn?<` z32=_frB26Nt`uQNqUtV(*%P^vkwu$lBqwyZv-wbldmPGsmE0khW-Zg|@_r05_)A3# z;-vYg^xUEYI`7>25SX(K6K8qppYGg(Jl5(^<012s4^gv@qMn# z{T#9ABIBqVOJNCU{N!BX$eAs~?4)oULw5L}zOh`?y zC!2F2HMR>$zKs8=Fd#bRnZa+a>}^axA74IdGfI%SZLEp3Eu5hObNkYHbM| zhL-5zXE^@`Y5{gi>Z0lRtqwzZ4ZQ6gD~E}qG$sL1%S^+1Hzs-yS&>qgqb0;^H^eLk zM`ljsI=rujqJ#m*j)tbxGGd#jUcS_9d@ zZ6GNf%7&}SpbDOPdzD@|OSFCoVXt9(e7WQ*P-0L48pu|neoA@}V|YFv*EY>^YYyMt&~j%)SQ z$O0Ags-9ezks=%A4iQ(cA}KMesydwUjG(1lKYKcL>yPzxf1rprY{@8Hej1iDn11S| zjp>GGry|)dAJ*CiI76;};=D-WvCwwkhITaE+0wH0s{!+G9FMRyN<<4+``&SK8kFvN z_cNEiPymYJoKXqXX5p;OKG<+T$XZ7vm1oT;q&m9-uFgQnneiTmcS!@8t{~IHw4)4Z zKCBgc8?v54Lh(uU{^FGfn#yn8K0w1?5z_%+PUfpGm;)MbVK9KwPbe~n4uz;X0R-Yb zUo@EW)#(0_wggdTUao!5;ICYp|IZ&iO=P;77Dl(t=RI+YXi1RUYEpnI58xaYGxqErJTpS9KU+Kr3s3zPb$GA(XXD}>?{G*tGx4;u zq3k_Bos@rLi*kmnpst6$?O8Nnh}JM~aDxS|={i|;WC5X+b??NSr$*D7exJ`%TCA|X zmi2MS)HAsn@8To|=60M{k94D9nh!65x&8w03QWyv)DrXhzI@dUSLd5`vN7Q1H`&dJ zsGp~(K!+r-Q`bV66PR^Kt?JhAjKffy1iSiyRmRd7J_hkQ2+TB@Shi6W6iu2y`#-eT zzrOr$DE0v=q|AFKPEtG+R-YnWunMi?lQFLuX01#KS`s8Bd`akzs$gij^a+44$VHic z)aHR2NF*zcjX`Pc11l4NuMUyb*}sa;_-mIWDIUAYgWxg>y=cJECDoj_o~wJrz`Ouj z5TJDDVVA0!<6mGCnJtMlhE(R)s#+XC(n~RB_K%GUO51qsp=KB*S&9aYlSs)Nsd^J3 zutfQ_8NDTVUd@=N?6;XK2ApVHer>F>t3Vy>ox!QBWM^#xFGz1BrP4sigieEgRr~8a zc500EI8jd&Mv|dTwB)pYktCFE3nGh91nLe|hB%J9&;_rpLGm#N4)!?vYR0A3L*_tIaY7(R! z5t*)GpF1n8z|CHwXjR>|i@Z>xGqd#?7R#SXUX@XM*KeIm?Ykk+?Mq=X z>)EF3dFmS!Ry}^;`gqj#fW$LGgStzRQ~qMQWdBzFwH|V(Ju#_{!oxG%Yy>$lx0tSeN$cr^qp?wmhX&w% zz}!h_ve)#;$}fY2U;uRRMmsK@&H(TL%%r`tM8H*nbk}^%iL&x9ACQT=I2cfT%YH)# zw`{L;3N~WRmK*rWRyF?0E{o+VkKom_-E6crC1V#MzHW|odAHv4WVCZX=t#9&VkE#|+0a z?6x^WMjUL%=sh>Wo@6$G8jCFm9P8XV`5iMA^~ zL3n5ugt>vSFo!yC*iD3qsOfGjuOZ!Uy?59YpRV!~gdt8oAEL|K)w-KBw=O-90xJd@ zy$jRz)vNy5Y8P-FUe=blqEg5dCcza2RzlZhE`|VgXpg#qaVBO(j9G4P6GIn(yArHo zt@Gc7(M#8=JeCevtBo;Nskv^2?(VCnpdIJ;0^TJK`NTFLShe-JqT?8CI4hrC1^8zn z;*z+G(IOMQtG3tepaM}+t9~xoV3VBoBVa@h5>d4q+fKSv$0-a;8z?^sJ;b%w9sL+{ zCmhyO8elKxV+cvB7hE*KJ+xKos!4%EkJI;ZV5!O}T7TTUC_HMe|7#(r4?n+l|K?D9 zL$nwpM5fTz$J4NAkQNF^V1ntDZ!O+}Pkx*_fs*nPYKv(PH%M(p2kqi(D@Z0FFhDo` z6;NCYC1I;fLTmK2GpFDo-Q~FQDEM8WRz=G%&l?^@5vzsidy&JLbuLMs430>2sm&&6 zC#<>+%G)tbw;Q8t*Y8S`q1&F)>w#KBzM%4gY%C&W_gg}{koGG4RB z*vOdgxereqr7Hg|)=7dt`ulU7O7m4kta<&=$YVWZ&r~7hquH<|BIKJbWXP(?0`OoH z(iF!>J*Ru<*gjrnV3u$s(?gHY=nV>=U}*y|1votyAv%tw(! zO8wbFwU07`TX~tF^zH}dMsae6B)8?F_CvcA=$fpkfJN>i!AO1UB_vvCKWp(zR$J8{ zJ^K|XLt@@CT*>JY{Ogqp^|XmW6(-_o`Y|a`{b^HJd&w<1)P5NQg8@w6Xi5h#Z=_1F zESTWljr-ntO$UB8NhJRmVYEgb>atTV@!H<@mXuxQS2&@-@k`Pl{55mcc&u$Bv^Y)58qlPt1}0u@ow21rgz1Bm>*=D|R?&bL ze@t@{;64+Af&o)t4`~voiUaKY|3;_%n+g^W>u^dj4{x}nw8%@!YFG;HGv!&zB%FcfF>iUAP_)3<2x=nklR4bTy+tyQFRaZv z3nIJ^_=P7KO%!Rhmf7i-!v)37(hUsh^kQ<|Qu~ zZ4hL|wzDX{Kldo%MdD(%m-c*n+Vm)?7EqV2*m;mYq_QXPCABiy-6Ah}8*-}@cNg|} zAsdG;QIJ_fq6nzu$qHZwVvRnP-)Ga;9WqAq^<->cr%xV<)OV&{VV&5i;B z213XZo!C5#LjmkW^n~2i9cXdLFE25!{b3XJHDx^)@seHMebmYWz$N4M!iuLIa``@Q zMQP9Nw|ps?J{icP6GyXN{d&2u=?27`#px|8yQfvCNh`T!B7~Jn=MWyU5my(`zhaZB) z>7v1kIG}-C3|c$*9-__~)-y}S=Pi0V?B9B-TR7Frv;_a^qkpEe$%e5&d8=e+`N;6t zEGc=^@T^e7ODAu!vnfl`a7dzkVq47a^4TqQK9XNB`v)T#&TwXm> zs-FDoWl%t3UBTuI|F-5%X(9bKW=G28iM!q{8&QZTwRbfC?^4a5C zn3y!eu1Lnba}9T? z2w+@*rJSsMOQtt4H_`r1?7WbV{+y(0ZWTQ@ilC<%A(pDc%Xbjqzys?uQ|IBLH1?eC zvW^qp#a~N2ZHDeKeo$7k6YqolPnM|8URvpRN`RY!Hsm$Ad`?hYzeQ`eO^pJiWc&IObz#t>Y+;R{#Hy%}gVET%^(j`Bdr^u#lu z-;~TL0O|ZzAR`AASd#(>%aPa!24K2Gp5MCjqXBPdN#B3@4FFxq0S(jc13&mLVe2&t*!*3e5Ie8(}Km+2b zAqV8h$m{~e=7tt|big=Lb4_dySSNXEb?6aF8Vk6ViRNU2gSTKyaED*BGgZLio4E5( z{#HSZ%^m+Jul>WWn_uG)v%W7ZTJMjI#Qm;{wDAQE0`m3c0qT<^XNe~CbClxak7aM7 z-^gD>z7|8-ZdJ1wD~@qf7W2oV&Lm*e*taGt7?}C9SWK}lkkUgL0x6PUR}6VE3MMkp zLa01!Un|O^BIHL8HZv1j0nu-B_wB2X9g}Tact}MUqMy&sgjoJ92#e4YrVGD5SB>fW z^>HKnwl8=_0mJtz>9V<;Kkhe5mR67Kvwq-K7LTq#vovS9}%I!GN zC0>76MVCb)%>H47xGODWICGKwbVgzkrv-;fZ1SF?3|>+wb_t?hf|RRLWk{Wf^1Y46 z3BdQzqSla(`qu6oMOAI*dv$ p0XzvYH2xFvL$qRY+NPzK=*CVzuCB=HsPobA&3Sj;;r@f${{zl^W^n)j literal 17971 zcmeFZ^;g|m)Gl0#JM03*-K97bcXyYK6nAIi4n>N4Def-C-QC?`TU&N=V*{c!(; zJKm9ztTk4WnYl9Md1giuj8C6Fl_NrYY(IUn`dHXLT6GggCks1UVrH&y%-@)Zg+Uh9 z#>5<)OvFrFj4UjSEKJN?#46InvKG!J#A3!4&L78W`a%9HqF3bK=92}~f9*e8R`LJ( zZV)Hwz84xxTHuZ#YZaA@R>6yPTZ6J;fVHUaXQFJ*c}emX(h2HuaZq1!%(KoH+9sUN zA6Gpm_MP~_6UmI=NBfNPw28L+)qUQ5_w{|QbI-Hamxp$1Q`0?6+Dg@w6!*GeE4B5k zEAd3vlGeU@yP0~1aI8dj@boMgKChU-?p!VK2wd5dxyYueLDZ(>S;K&>Wt~(actTuF zQafHOmXD-*eP25hPy`!_%ah-)e zawoC9U!#~aoQy0Ba^T;l72`VTP0c)&|9iRry_x^(D*qb@|Ldo16dsg`waC}W=$};z5e6yc3Q>u6W>#kH%T1YtJg>peXCVts?F(Q=V3+cU z;VHv3c$7d&cSIiKR<>&NK3Q0*eA)Y~`re6DPUjxZkr^KbTg#xTqhr*dv6uu3N}i`d z;hJ-sb&lj}wv{Sr>c#<+*UXa89tH-{`7aYSx07 zcAwwvD|7P1FdPPstpHnKC6Vd;Xc~!Fv*552uu`=7QSGou@2ZRKgJTbwv+72;%VuS& z!u2-_HDv+JHlw5STa&m+HD8iinI=>7InBwS#Y?y)v_XW;!pj@1*K1!-BcS_!xM z80vU3`HJfug$K2fOpxkp{@OyQd(SA)IH1mx=GTy6RG4t~w7<*R&OwX0p0hCFU8?s> zQt4LGy~#pQk3dVcdb@OYfoMr>*JQe>q?-q%S7e0<;_NG|=t;WxR$_mqp>QO2)iCXT z;?O2p^5+TjwsL+>m(8-z)a+AafyV{1e^q;%07j%VPO?2RNu0^9-ZelZ*ITO}rYP(E zVOz~}@?l5nzcWGWK4p2~{Tk<9xwco9yM4(f0nnDzja4hsn$b3>G-VCm@+pDK$1bnK zDFtMpXH%L)NTKV1uTlm-Uoi}b?Lnb0144l=Mp@ZmX47KZ-xMY%7Pe6JuX|HR;`m~`OBP9#0FU$ zTBxto5Zq+ZDd^WP+P_A_XiTBPYE1no$QcJ7BC4!3oFz@QDrS6WQS6L$7z|0 zNJ#9jh|!zxqc-S+Oc>o1o9LHsUd%d7Op@ zP1^l?VV-^C0L>%Nk)+T#F@}{DbvFT@jDny}m?r^4s?q+v{-joAS`HP+_csaYRx|2} zHI%0-$4ALaspHc^9O_=e?Dut}Bwo6&%QWuq>+9A-H16jrS2J7`KmA7b(&7TP2y1rE z2Y-&nWyHPH7w%xw92Q|NXXiK9I6XCKnXaU;tG+C-@P1)>{AY}MDkbUyrn&H5*fM|+xWL(3Kw3V`o#ilW4aNZY2y5#Ojj959dP=xDqu+uNGSkbiYnbmTD>9H zQy7I8X=wloeR2F$;Wo*~~>+@K#mCBc^#0rMy58NWOCj39mN6QN8|In}|r%<)A z?&5)NADWZ~y)>P_$B^MSP(UE-AWUh};AL%^VBl7K&2hL&OeDMLm*-cavSC)!L+NCxO*}qeDCd=65wH2P1_!s3n!!IR+p8 zsx72KvDpu`k)vwb`2~zrt-{@QuQvL$S?Z1_EEGY)vzMn_Ih-3s+``Bq(6vu+hzT0q z+xJb-?e;u>>FA!eOj{Ks+Tq9a8rj@@Xu#(;{xlZhFDgXDKqHR-d>GWKSqb6YLLp8M zyP9VAe8aR!$KGMCzEHx#5RgD!p7loAz)6WKwpOuhLDV3>5CU($5$CTIMW?Z#_(WQG zMp!v4@-_V8$Dq$=Tw?Sbh`?aSuTu|U&6zjH@N&P@v%iS}zHbYJv5uGih#DMnY3!Ck zLhg`o;A5v*Au^QcrsqH;^-$mCHF8o9yKQAte3icFQ}y$4PPsd z-#w=rAARvu>kw(*%pmhG*oOs)@|8s0jpKB@jF@X&ZMWp6T{2X}_v5%?B0E7RhZc z#uaFmVFWk>n=U<;6XG)PioTkpUS0)I?)2MQ;Vr#X@xEGjW{CzpG!9IfcbrS(Ir9k! zer^}~t|6g!s;B3M^hC5nF(G`(7STJ9+U$Viyzq^k1)i(txHg~1-yr3qv^M7=Li#1s z$f04raSx7R1KfpVU4Gh^(PA?HH!FZj#fs(JKsFA+zK=ZqLdVBaMsBuTJrz^}CCo4J zeypu6N@<%OJ4x3_AV$s{Ki2k~fW`_Nf|nyE8pdHdx+k$x#bi?WlQ0||kquah&W72# zKKEV_ewgyTVm>l}wf>V$U11CA{HJ^}r6OJZ4}8a|@2~2Am-ML<==dW3`xn&aqbn5u zb!no*i zv4B71I>Yy6d^GI{6K`<*pE}D>pRI}gG#oNmW6(wgo%3Hf)Zi1U4{*#N65TqMY~V)0 zy?}WNJE!!We?A!c2S-`$^Yfakx_y3;Gi`D9hTd;{_4b)aqJb}^`b;nw-Ysl){H%_- zM!wU>Sn`+g2wUasw-@rp_G*1J;X<%t^lFYx%Ga)%v-C@|we6SQDtgyRYSl1|-Q$Dg zk2o#nlL?(BqiC)VGH)d0SlnNw;#aEsv3Ai;G!>p#Qmn7^j&kmbRgR7o>F+ z%KNG!qeXhTYA`8smo3Pr;xMvH5&-G?mO;e7`4_{pABO2gCEP zj?Y&<$pt`B9%(t2JEE|;w4=~_Ou1E|7BdfiSVudmevJqfXy2x7%LQ);lDOrxOGuvT?p zK<;<;Gq1Fn0QnB4+(w({xs(W-oU^X-b1?jLQTx@HIicyw9f`g7L)uVNb(ig(M1P(WEG%<4KqwIrxNLBJ#Fg0f{TkWA zizOdL7WfWN6$oP90VZ#rt#GAVAK|PM2b@NqTPd@ANqXqi)>Us?n9+AI-lDIbA zg(R5Cg`rkSoQ*OUoC$2G(g}WAyG_}~$@=vcrI}aOU&4~>A(##XKb-s^(fB#p=A(KG zSqV8o+s*oqrxTIKtj!gigHpv07{oC|4gF_JX6t@7x9_jhsZBKXQnk_V(Mm}`zUHVE z$;1Y=elJ&j2Y20)wYtRMF|!%EJ2=|xYP!STQQ^LFLs*8K$KyCY8wd7o4d9W}-+muD z`-7WxlSVyT@&7^VXpG6#@z@^a_Boe7&7H(<(6K?ch9;GONcmbyN3IZ=rcPFSvFet| z|LtPp<7ucA!Qw>v4-wKk;r+b05`>sY614&QET_9t3dxFhY__fQ@fH?yXc??TI z_j-zbblk98z$9TXtpm6s_y5O+`=!KI*gKwm zpLHg11BH6+Z^)m~7%}}0I@X{H1iF(#$trPPws)My)*W~4{C|rq|*g&qSE>Vr{4LynYM*vF$yL8@~O(= z<1zjUC0LeUlBPwwN2*$@K8A}WJJ3eaCSbt;cOX9Ug2Az)y>Fd_p4S7JN9+UF%IEI> zW)E^et#rEt!{k{k)ZR|~=}SMZa8Smk$=c;@8 zns0`QkpPElVO6LZj&lS|O{Pf)TH1IlIX5aO#6w%;y(D%fU!d&Ekmng8%vM7nIX=c^~aS8^fWWfwIk{veYG_Q4%@ zrXiwAK$#UO!OtRRSg}D|T}_&L-vOsMaSvR4=Z*k!gcq3v_*m?uFQ+&G5?OmBabLbM z*ePw&XsD%UeEEs1C`{80dD;;D>ik*5tKmi4_Uy|L`SGtmbn@yb2|DN<0?bhb)J0t^He?14?(>)3&AHp+k3oF|VSt;u0zZV*or)ZhUzWB|ukYt(sXdo4UDQ+7%I_ZR1` z>KcYkz+7_SfuipLn&%vkcL=|7h2m2Zb^IQbE=DW)FqGtEPgVGBQ26ZQ3Fl+UMzdo5ZVdxRk4o0dJC?0 zCLY46(G$v-J(KdB<`+iRp3aF}> zapOXLpph^B2k!e;T(+R^K%;Ygna0!tV;#-ry;T%t7QV4}y_38szr3TpU3HIy>nGoX zxh1@qP4#9i{@RpQ>w410F{z314w^cyWuPEHo(=!E7P#8-wYYfVZ{b^M z{ch~z-y1VAj{T;r$0WJY*dnI){d0Sp3~O)8sN^cFq*nlWJQL4)VSp<8EgkhJG@!04 zC><)J^Hc*7>b#kX)I!M2#T5ng@RWe)RrxYk}4lXn|vsgQh!XSuGEK96PxHpLF^7S@Ps>21tF$5ruPKdMw3vcXNcj)UX7`<~E>0DYQ3J{~?LnG?3%AshxZIIYRm+__iZUj)u%B z_a1MajbZrCg0aUm%)94FN$hFv$L{GdJom-Ha=L%;1Yp4_Jy4L!pOIhZOigk=R-^OX z>e$ir2EnTRDxefxx+JUzDaHRJhTzm1opAqY8V3I6I_;2nh7|0SVcSJSA zD5YP|tGWMJvKhWdU%iQvCE;~dhp#S9$o!*3vJhfjexCH_z$@s1jxz&AGi6f+V9_zq zA=~x3kk$s9?Zw%Vz@44h*LIVc`u*$})A5S})oz3m((-UP>cYV&KO^npjNX^4E#^ot zSoA7D-q3whL;Z>>p`pEwo0PFzA$RseaUwl8_sdp%eNxWL8{2&`KkPO3jfhc1?e#hR z2j+#<@+Lu}*~B__8I%S42vM@(3@ou}N`s_U{Ut9?6tkhXjjul4T7U;cIDtfdnUC5g zlmC0R4`CGqf*JfP8FTwVi;UA<#A}pcI_w;h1&YL;m>IiX!nhjaCO`YB(Gl9!=Ovqb z-XeWzJGV>W9Z?JxQV?#BzXI;foI#*V+DeTCBV}n*?CCF8t#q6)7)#eg)(eR(+rJcm zciqp5LPaudW}xxL3#~4yZ0`rK7clLT*~!54CS5y$72!!T0cxCjhh1PWP>j^ft4CND zh@Y)E0a|}@urE5(IzM-XM!_N9#m)UpAsKR&S7?}@!Y1M&@C?+{ph-30La)7-O=qJr zw-b0%&1UM*e6T*Q&s zvihQ@gb3R1^PuOPy_Ir9KIExv_ALr}Xig^snDOuXVFSuKE%rQi65lJH8CXA_!(7!N zpg2Pctr0bhQ!*md>;if4n?F*-dkKU`zL@yVCMHNz@8K2hHN^e0ctdwLWc!@ZjV*_0DwmEb^5LdCRi`%^M#d-V*!HvzvO67poVuvpq? z*ms;$v#pjCyuBkzQj?(g>)(1`<0T8Q6`Vp0*hgrP{wM;RZeH-+cRK+#3j^0ihEK*tiFEPLOLnsP+ZJ;bMw~OBI$Q8ZlX_EQElc zxIgo&nV;Ap;3FD=qFZne9KoXC89wKCYfdaW^7RM1b2D|;@8RNCR!w*Ag5Q-V!2`m#PccOiH@-90TTM&yvD+J zD=PibSDX<_KRY2S!_&`K26~<6qDC=E)`%~EV=06&^mQI7TD;7*DF8y&Lqh%C)s5!m zB7N(kiJm$2$?CJyu-F1$9rWXfuznw6XrZ z0UkJ;?xm_d9C@!rTB8gFEBvZ?OP_^3Brw+)J{aySDlu&@VS?2aypAi;_)E4)ugRNp zx*;;x<)YUAup2^Dl>?&qt^Kwjr%;=B0Tsq;1ts@uh0={p9c58PEF@@3wABREOLvzv zJgD3fl`SONy2j@PjSJfmg5VhGh#Z%AESpF8uvEVxS8+81|Allk;pb%(MMGo&6TlB^rLiJC!$TU93(^SnK*J(tAn zuaqd@G`Sr`hx@9fue-CgG!3q+GYKSsRh2n_h>N!?u^ z8Ve{4P9!>=?3Wu0xKcd3a|i5`kH$ppCm9P&NL-}#PB`-}P(Hh>`8*B$@lt06s}Y1| zUeb=2gvUjD0n?4zRa*P(^|Uii_H97!?MFHFk(u!uP3#+Wn?CD+Vs}yNIi~K+(?y}9 zfjpavl>$@>d2ePdr(-`M4~JC7YO+hZ1+gV(@NUz1Ruy|=d&{0{NjuKiWI=dCKt8k0jmo0?16+ooHEaLqVLS7&B)9NAcfTRj&Nq)M>;txPS6-V4c_i}cR-KxH?v-IHrY zf@=c<+(sgpRuxV_HiUC0ivwf7dS74QPq*!~wAz0-MFL>;(eJM(R5=?n2Kv=*Z6Olr zt~+v@pC~uG#&}#>eFtqmpU+>^RQb+0_%%3cEdIoU#fJ6i>1tg-7ap(*pozxfcsvcS z7#rcP$uqgmEV7NUhWGtxz5YXDE9R}4jc@V@31J~Y-U5bQc#da9I(z}3jC_#N zN!jD1g^s+ubMQk!)K}rC6&zM4%>)u-&(7@iE&iGx-<8v+Tu-Sw~C4#2!h{d?V)iti&yBwN-?!*3+&~Pd)*aywz zxzemXLfc@fB2G|T&DhEFRc9v7-%GWi3v9FB9Mr#MS$%P=!qd}M#@Hb!Wg+Xa9u^## zP-E!MzMYVe^Pnq&7)t1+<$aJ`>bO$J?76C`Ks>^QK{6p9AiFbsGnz&O7Z+D z6iwiPlsoY=(YQ`y!%^yeJz3Dn54}_WWkP6hOj7(rUo4LfhEH!Iv}d{V0a}VK!2MZB zAc2*gF?yGqi*JZTsxKwI)T=D66#tUSh%iwOaTPIEDOt)RZr(n5l%AQ1Ke}Vkh8U-Q z9`Ve6j6k)xR>oouEs#0K_TBOi;WN%0D#D+ZJoj&tqL8w%&|@~!ys3FjVt-_8R@XSK zpL|U4QmGP2^p1gSEsu|J@|pQzL5ow%3_-1!w{u9}DRweZJd&r=^-JVoD}OKJ9j*;@ zC`-fxdtSR5XP$AFOjh9jOq96Z58;klEA#0gS?08@UO3BXyV!ig#J7!Ss1Gf&if7klL}7&Z7zv?2Ih{LgOMD}5G0^VNNr*hT75`K* zq%Q61qrW2LkZM)F3`Cpz@nT-By@G8I7deR=K_E9@i-)Wb9qfx9HCX~+OL6do+?m<{ zo4Go@36hI6b1W3KNo=ijnIB}XYm{b1HfEm3bP3t8g%QZ2v&D906boJdrk?Wz$@Tjv z;*I5(SXy1ZtNopY`;$;_dVQ{_%UN*9pj%nJVCFO_aWl1Cvc<8OQ)hriI@6lXT5;&c z@gATgo!|R%@|)iC{Mt!bZZG%w5S{(~YHXF>Q=sJVDCLB~hdi`;`j&Ma@Xj09vJiD@ z*}>T8IQ5kGOAeA%cvU9xdIGv8Q00ZOs_P9Vx`gYn%?bx|=L?6%QHeL%@4ni8{c(1d zj4>^g&EHb-jA1WBAAD8M zoIt^Z@}*Q2QlXgy5vi=^EIjit+wy#W0+%VIaql^#Gvg&}Gn3@(=9Ek%q<7s$1g%!x zoq`(p(4s?ooOfC{DsLBi@5l!k2PKbuZs3nzC`y7va*FD^>|(DSeOeJ zY42|k^ivW}b$V`}{oQsrXH8?R@HXMc>4T zGyBTl88`+mOk=pv`@XkIkJpp%SCRB}nN-}|J9EO*x*^OJ_9YM1W#phKUJ_F`e}b?N zJ4=&M2PuS!jCCzewdQQ$wiC3X7~zbu4u4;;CrZsE5kwTa&iVwBtG{Wso|KxgX8m0P zoKg%NDcKGBze#OUiv{VT-wjYR@b$#&|Dn}sG+&y7!x+1Epw0p>0?+mu@w3-%%Sh#T0#Sqay^AN$?b-@#yGjqN z4&;jiS~G&l#cBT4=xhF-^-Si6EOI*)|>iDU7QrI4fa>=GII{{@sK{1`ho64%@gMzpHH!kJ0c zhHOLtwi6oa!~eA^^-iU5are$k39m(sPcaIL{m4QfmSa2?)b@SY=Nh+3oys=5#PY7= z_b4i&SO4;83Ove7%YzVm!x0nLVd8AIjqlD@`>SVdcm5kP zt*$39uDg$LqC7Tze&GW<7S;oY?&_1~p>mgg_BG!TO4pn19gQ_uRI=lv+O1F7$=d~m zEV4FJA-CVU^cg$LD5TDQPULerAaXOAmG;B+EUJUv*M1zEJO9nS8(3fZ@jk(PbHCwO zX{%Fk&RlpY!CYIUKG7n_`f*luP{~u<_E(DfU07pWT~(}O`$(4x&1DJF-6U3w=?Z4m zj4o~9Cs9exBDHo1IE}8k0wNq}ukC=^{#nxYQ@dMkPcSw;A+Dp`8pkSUNa9bJKj`3! z<5?NyCEIz^bG)U?AcRcKJKuZYw&{GG0R{(K$gbWgP$l}0*%1s1IXak^L5gyAkkhJ* zWSX1)82f1+O4O!9OUw50PJFIwiTzdJ>FpHt&9B0JN-Hu|=TnVZ;{UuG53N6o6ESmU4tu8R5 zjPSAsi0VKf#6_L#eAL&e-OI_UZbv%fQck~_=_?&A&&N}CitSfbv|cgEp*@q)>L}>O zIx$D;_i%`QeMtdw;i}@mA;vR-7ku%Ij)w@y-*$o-

      o5u5E{#Mr=u`gS?82!0#H z)rYwKt4pH~obir8T1tc&9O8mDPKMY5@1!B26|jKW)A0oF3LqR?q2Y3w9`c&_sPoqd z-$Ll_aEad%r-nZH(>wz9RzEprIeU>86UHvDIt)TU_I7Zv;t)>^Est?Q21&-E%&Wm{ zr`8?-3mDRKwJJrv7X_(L9N#D&O(H`)amyG)b*qxl7Ak=ty^Ve_ss)9?8K?+ zHI^ebMbe1qyK3AD7oJMY#3S=5>CK4**37FIA7qw4Wj0~2Ufu8pU1f8gD!E2Ytn?&F z=E>sFJ20E^Xyxr2?=}-gxl_kV9%3k>Oy`ob6lj#zurAnCks3);Ws8#Xm7^#?*~uti z(YO&PRq9+H@&XQhoJKqN0AbE;Wf%32lq%7p(s!g(Wiyg_!{^gf@5(dAvDM_76yT}= zQBv=AZeWKv>8>px{cCV^aeQ~iW~}3%^AH}}c(LI*=qS&r0OFu|>p*-INt4uJ3zb}z z@P5l-^&%F)L^YW~m9wU}zPf5MYMgoI6zd!x$p&P4c~X94!7z1#%x4?9gOHTlwEBVa z+(Bx33kN-N@M^W4C!ySAvC+?>iW4GJU3XF?yr_oXPROliHl9~Wx3{zvDd-Q-w%K)XwqNH+ zOn<*iLUFD;3sz|IqOW>s0ckX5wNX{n!XP&I=-o1_88u|1@bo3pG*+WiVe}oj&Nt>Gen)b6&nxc(cOh>L+E3a0B-qkNgkyw$$?OVRxLm1UjC_`~>n55fP-0BWLlSWQ%a6QNs@J@SVj3aP{hAVw1 zE`8A0t}o&Uu>gTz&Vq5yrAUsr-zsmWvG7gHxmE>aRdM%ON6EGH*bvI6qbn&Y(A3Xh)e zu$n&nslH~MuBRHjnxysq3u4}n4~@G{i?=2XQp#AiE#Hm|W9;w(w$J06P0^=8rAOFH zs|NhqjF$2m7Y{n_xFtx#E;ZAWx}g}4Rz)CB78~oeDS^|j#kw7%ZzBEOW{2g&aV)v^ z-k#b|N6OIp{jQm&jauzdh1$2WSQPY}Q+R{&f>8vMbC(w3_%1$@v<5U{%`!2VQ72?f z@;Il`*+atgJ1OiTuEN7@jzK=I1l+B{VIBO9mLK>{tm^)@&Rc0Gv||1&}_2nfuB)l;1>t-|07h=N-6 zD7c~Mv5_mr7(?R$+EMnL{sA5BkxI3T?c31?70NQk?P!cH!>gnwXLszhuW$f9PmFD# zcld}2+Y3gGo569;i2ECp%49U?kTbyg8nuopSKnKV&3PAKNsWY8*UDOQ%0_lg8*tUt zh1&aRjc`BF|?V4$asTHD6bGSjz{~;5EJDs_Q@nB; z<0?4+#IY|0Sn&P>2CIgZ%yp7*KVUn!Y-8cg#gC9lYAXsgr|py6k6c@0vjs>tTo!kF zjC(n4b5IaEZ4M+!+ovwIKqr>5NSp3(ettxNAv6hr(e;eFT_vsNa;C;YAySeb(A};d zQd38VeaK!i(E26wQjhE_gAGLvwVbEibP5@vbJ3*8S(WWbReONB4Lf-PX%R?#fwyV) z*Uz1Bw#Mfy^x6&Rt5sMfw;RC-A|2vC)kpw1Pvvt3TV_ zn)neGR%pPG{5H6c*`sJ3J@QfnVX+#H?RSQrcnc?eGBH~+Ve^FFOqk{PvmB$;DG<_N zhS49IP%N7V{0E*^PHP>D+e7b1Rj}a=b&ZZX?c`Q(BCWBKt~A4- zrxcTWW|o>4l7P}%B=wPUWmdqU@}rBYpe|fe7KJUco2C_&JAuWi4G2hLm5NdPj1}gb ziX&h%vMrex0kzf3{wz7Pew8YAH3shP;ylijMOD+r~>$FXlCC z;8|v{qhsr_@>3Nnl-&gluU5^>6DQ>o*8z{5J7Tr-X6lrA@_kKq-<5*UROb#qiW#;a zZ!+oVR-ChOup0|`QA{^{BneZ}w;si_Jn2eHC0qBJ=7!}1oT}c7O5x>k0JFd*8TJ587v1i2a)_kmAuRufxyEQw$spn!{ zo(6SlQq->+ri)W+lP=<8!qsA&43LfqZa~g;VBnayU!0(fpKJN9L8Mk_&75w&9tAOy16L z%Q1&#Rivi`7jmjqM zb^Edm0V|+ld=2LEMV*Z&cTIyv?cRp#>Rz{~3uLRHP7o%})(Ya0b2u_z<6)JHa7Y@7 z$hUCIZ?SH1p>}Dy6=mx`<~{61^2uRATd3q3MHRO-=-9-ucf~%v-h3LJeRqjp>Ovob z>r_}gXM_(fBjq2tcGM6cWF%2-v2;M|dPD2;6GW2}GzLQxemWfWPeh^)C-S4 zQ$}}=@cg}~1oku}v0`^*cb6N60w;dk#!|GGY`^2vPak4x0dYH50`b!I;_a*gaU}9e zN*rcMD&mrg^qB-n)8p*Ip$BPe7H4SY6@h?_c~(v5yIKU5r=oheNA+)OuwlpQ?$z!- zQgFMVZ1|j?E=$D1I&>ypMw1pnjke~-7dCaEC_8Rz-^(~8p)7o37I4xCE~*S2aFcz+ zYFMb7^8#-Z@4T1v*oG&?&iGvJ(PgG8YQsghT~|3SUQsd<2pXh=(No@J0Ql-?JO>L? z%tsR?tzK!>WSlgI_$G*6&80-648oJRbEV`Lx(|?{o5ZFLE`*l?Oie<} z*YK_}wvb+*jufMIbitK~{#ZYIW&NJ!>>)F=dvPG2TwEj5{0*P=6IFNuj<4vh7$QlW zUGnJ-tFnn}wY-*eN|$4e;#K4b?!sfe9p6_6djtwcK9h*MW8uU1@1a4KmxS9=T&0_+ zVWovCFD=yU^LudfCmwnqQ;~_F88Fbk)5If#BJ6!oqhv|HjErt-)Hdc8pptl)uy_dh zNQCVS8g=>xis79r>fsObAM0I!{Wh%=#e=#_w4LV;Y6nV9|7`Gsi;U$+aL4`M;pr|@ zCvfxEdwua+VPKo@e|oN|jct(b#IWa+4dO87>-C~b?X9@7Vr_hdgg#yDKsY$T|X z^wuG3+{AONU+yKmZNZ#5>Oq!Nu=@09TwE$<4{1mQp-R@yteLHiYMZv#z>uQbz)X>? z@~Fs@EmCz6jak9^gEZYXzK*rLuf8rOR{7wj@d$3)O-(I$a)##OES_;9MOy(5Tf!!K zmRE#SL?Jjvl3x?ut#WYLrC2MI*=^z3eMQ{s8vP*fg7!N$bUSKo3V>QD+n4;@)c&Do zyfMc8`sh8+jIx_R)K(n`9F=!c*Mr$`XEc<09*~`fdBx66W!Ji=nSI~)!H$~NpcmV-L z$d?SN;SVmFNpAPxcLi}I&f`f2aj)%))3~#Umv^X-uC}lAhC2p2xG~ge*d)}B^RpXS z`(|@XbRQx3ySG@yCTEC^KS760NoQEt}$&jkQ(IF`4}7B z&CZ5X>vE0NcWws(-D;ctbMEDb=)wx5x;5e%B-em|m~vQzds33JI6}G*bduF7Ggv|iqMe}ws@y(>48=drdXcZ&gZoQ<`j4ga$VrX-m!el$^wNZgAL@So)l=`%t zoz|tdxG9A)*1sm`TIbT7zvoE#NS&P%AXiQ(G<@|>PVrp?)t>r)#cX%@gpDVQx$5yv zd<2Vw<58SI>*i^S1zAr8$G~!P zO7jKh$%^A9L-B(X88tQu)DU^Bn#pd)&SBA}&uf&HM7_;x7m{5eyEO^yqQHlJQckzl zYa%$7x)RS`KGv#mgBzXuQlJ3GJ-adIztILRBBE0mn@PYS1H*NZhBCWLq4{e=tp|BQ zqVa1F>f)g;#=ynfO%`92X6>YE&$l0;StYBYz|NtAqh^gry`?5}I&q`*GQVM#B!}9q zzJ;JkctOUXt%urmws0S?ZQ*gc7CpMYleP0vBwi3QZLJXgtkT4<9^>xUK0XzG;VyR+ z&iQw;}m{(o%5o*Ztgo6E)QD9v;H+H$nX155DY- zXsCJ8^o&Hisu)D0Ulab53)&zLd*?z}6B`*nVBSpb(WbdQ^U;vr(-!}+BNO~(O^Byd zUYk(+Tv(n*yt=4~&5jE9fJqoc3n8y8Tz^!7CJ%i_5}jw|KRL9>f#)y71p^C&yLztG zLpmasjj^oB!FY40Hk4jjI*NVxL%l?Mx=Q780^l+duPCzXhnUwk%n|hM$vkO09~C&G zS|3i7eJfQTV(o*tq*vE-d?Me%8^R#B14HfHARzOswoFY!TXC2D8$Jg=Eoz2lNn_6v zj>a}pL=^Izp8~iq_KUgcD+?o7pDAy8Sat)rZ<{3xz0MZFZ({5$=?X(T1s}?AX6*cI z7vh>%#|$Riy<3{$S*Z zDOLthyD3AV{vz5CLz@kU`xRg&R1~tM74BC26QLc4g_%8@#Mjhy{rnYdv~G_?hEB-#h<>x>1} zq2IQ`^>u=C|4f`fabNuCQZ5nCPOCw!!kU*FS^hWd{kipIiGxLzgv<;K*C*lbV#Vk!n#^l)?)7Z9 zh>C}7P{$EM>0n}Ga2_xZy9v?uyAz4@0}#3xr#7cA7Q=qmO{m*aVivTolhbOXJq0K~p9zR-DM zrb~<0NWY+9ArK=pR=JiFoSewZnfBJf2rlgi)3QoNw?yZ?$Vb&j}GK^^}#hmrOq|l_|w& zKF@6esDHrch;OW;>7vsBhVhlAsovt-UygCL)M6ay$y!9m$7V_&)vB2$m4+p?i|v1( zTga8sPFBQ>y{@6QFqmd@>#MIB?&{IF@4`+D*64R}a=EKf{C0Du;V+?^q-8#1tZ{b| zAg~y>cH6^t5wA=R=EjWaLTsx}L^})eM%4{`F(331WtJ;h@JS_vS-98pAb_ogkgjEC zo<7+L4`U4HygDof4Y~XATR2BnRHSW~4AgyNG=XF1Pr0BkJ$e0c%F`?{e{8Y7_ZGGP z*BCKgO2?2F>Rx_gz`c)sVZ}I}GA2@KYRrLa*?qi!B)>$dip)KWd4?D}3kyeSt+;?e zI)M`8WalaP-mdJfTBV5cm}(mP=UA**>4;oWHH5QmIj(a#sgr)`jayzD?(crxfo7V8 zP8P~a-o#I$l<&00+(gM^b%pJ6<5og1Y7}qWfI~%!vSocAZW&L#HHaA-l+leOF8bwZ z(O`RwJ-TZZRB5?=fxw@q7yUj#S!ZWkAnltT`-E^(9l_f>a|6B55IQeopq;~OdsN19 zCO21;kHzCbaT$xcjP=y>!_(z@fL8;EwD)-weZ7Taw}5>>M1e)UW+*Y?S$|ZWDE^Wq zR>x1$63@B*q4E(=uI-1pjF`p{D;r(--S54f0;$j#(kC_j;6*_wDKlUO8cynp(76{P z)M5ehy$sH(BjUsN!v|ia<M(-^qNhjy+-_rY&~W`7-d%ht;@tvok`u}t0_ zDw$cBF7nVcSzIzfem!sKzD4C6mNlg~CmSEG{mV%##94YPxjwU#&am9NNG2LenqUrT zqThj9K0TfXKSMv`w0<%;DnTj5xY;4DZ9FJ|dVsx>mgQ{Kpeow~)Khhr>3`f~aAYIX z6Cnxol}HqHhqAvfkOzuS6lGF7%kY6+G|Fv4EPR%|@224ju-uqcn?UD8S~_B5SL6>Q zaE^3C8n}pgspi#6AW;WIUcdb|oO~9nqUcwk0qP8-Ef$HG>136}&}F)EyD4lwIg{|O z{k>_lk(feX0@ZnO3|46(TV`cW1TxGI}VQEEub|g50}H z7*=SD5%(IhVo}aL;iXJTA`7R%6mu1K^Fp}=r1c6KL)Mw{qznqIUPALW=LvsNqpTNr zi$^{UXn~_b4s`3`wJO2G%yDhJ>@gX4oP;CCj1`$gKjH)`uRIYvVx~r_ofdt1SiR zIY+i`dJ+$|0p25#L^=slwW~EVs?834%-#&i6UtAHOP{9wpyvDG%YUAWGKcy^3|d-L zk*UnxMuJ_8FeBray4H3(vnX_AFiOzHY$h^0b*fKM&^kFv>J|3`&W~-uCi`4h(%Q74=yFm($=bJG%%`|(CUI(}(D!a}$TAKW z4%H39b4?(d*5Da)1{3sw=9q6|4#Z7dv3yI9H=dg2xp;2Gc3_6RRtGRtR=CHX2+Rq+ zVl3|3bB4;v=W)g8SrX44`|KKWkzI9Y>4=Q;!^0%suXV%J1!I?pv~BdvtvH~1`t$y+ zD(h4=`wVh+N;@bU;6Guq#*#~RB&@eR@cCOvhko@8?A}sAgz&|$%@lHaa5nGyiPLh? zWEK+mll^x~a49euI;D_)O};Y5|I*l~lw|mHb{mmRlrK8|9~D0dKYseFrjuC7$b+kv zrYp4Ia9!gs&QyJ_1YlO0mKNB90LLO+?$(U*ac57`Cvt^6^t=b^yUIpNXtekSukeT0_#x*^ zNy4_o+?_hyM!(ef^gt<@z5fWeh%(sUetXHorde)^wIm*(8^mRy`1hfkAY7=(aC*q} zL1*ekZGiOq?+&M{dv_v;q^@zTcIm@1d+MU8+g5^NxTupoF(qt0ZS#>;b?(SHT*U5DyR(fO_4G7V8}@ zoYoZBNLGz6mMyS9ZXVDrPxU5~un4fOMAQ4*7y%sj{vKml92v%N%(SjxI1EYcx+L!t zEEf9ZEVFJ79C*F}7?b*6z=tWyJSCP5nf{N)hGB4YC$4+YW?)YmNbAy+3pjDy$R-Nc z?sLY9r|V}6xE1?RUmWBtT;mVFUiW_t@OT$0Ef@}$nSJc|kbmD_Mls-mZbK<2 zk&+zPw(^0U;gkIs;9f_woJ=L={Ph|w{$-Bv%qNz+R|TXpNNqXwhDV&)OCAfa1?1@& z>5P9P?J@pxU)K9K^MDb$GQ6WcElIS9N^a(r?Qr+`-8sjvk>Ws-4aCoR)FIRCu;=Sv z-$LA!ln~+>P+@pOXKNzx`g%1N61R*>9_oGJI=y+w_2Ro0nDfZOyx0kP^i}Ms$n-=x ztBkCRd2$3XhcyOMkx&afwsP#SS${os_}=HoW$7;xMQu4I>q;iWzlqXsc9Fp9CrWCV z$0rB{TUi&VzYT#TM*)bB{X4!s$$<~D#FY_EEUf(YwRq7l zP9mgT11ykA;^X8qjb{1DLO(39$QN@ZTDKm_>aR|n)=+$>?QaYt`_xmz?or!R#=QiW zQJ(c^?4cR$5Cv97=mh8*F)}P_gkDB4j=&2gy>KRsfQH%kE*LC%f{~RWK4?%I*l*xQ zZp;-=$*HIX5g$<62(I})+jGX?q$G-Dth1&4f0}Aold=0~{3MY}Re#HB57i%3<;nuj zIjm(iVB7Q0+Az}eYTd__uH`4EF;(AVa5Um^nNqR)D4vxilF6YJ>U=N%7mG>X`0A)FxP#Ov6SB z$TGCQ<8IED7*eWM3p}!VDY{q`WFP#DeH4Uko#J$UUA0`1yIW|YU9Qq~m+II$`$u!Q zykFUbry?KhpHRVG*aq4sXv)a!l9b4 zlu5);UuFAzY5LUqkRsclj@zQJ5F*y^ZJ*`W)}Wu$pWM!QH=#q@jWrr~W$v5IJ14@L zY>Gq1OaqYbC_Tt3?(~xX5P^N!a{ejCbBjQPlu)EQVTQKId!e@ZL8mpyz6Q+ z|C~>jA=B|w4B;MHcgqH;9X^2gaeY*4nl`^1Js0xLu1U543(6=zo6y3?tO5;~@$$@C zm^QGf)+CC>=J?m>!=G@BemBlYMeOCDgo=VRespAoT zYf*ei9Uh)uR?kDH*hVk2wAreCD`dxi?OTuZQ_Gkb6Lywf8Aff%(W7Kv3LUb_blq!a zERbB^si44PCA6#;+AsSevMv6PC^w$X#p1+?n&|{Wm{@ZVCP7PGtg#mepyKlN?h%b&Ku%Vx$gkT~SfW5bKHlv;FIHz5RBH-UgJJ7USYUPlyn z+>0&DKQ}jxc^vr{G$pv9{b|bnbrEi3iYwj%h{|725}&*LRdC``_`C6CZp-2skva0| zwO}UWLWG<5vyp_-aIP`NshgiNy_17k?P|nVV3ZFLUUaGfEk*{~o8Bm$njwrT{W56O zRT%ntNp+M-36CTtzf4TzaOhA!g+^1G-+STCc}_dlU&_%-w!7#MM)Pq)XZKdf*y3{7 zhZp?DIj*j3LEc*gI8n|Z#@?f0;ktZ{mORYv)DF8E=iN2!0Zg8WK{X)ILnU&@+*3E! z)&O0zaW%>xAj~<*J3rnj&y65qD)MJV#^U<_nKtp9;nNOpbSQ71G%w;Ho5g*mGFVDQ zvk}|c$m}Oq-hOj7tXL64L~82XBIT8dpbGvteeGJz_Cj=(z>X5+S=izs5py9YlIPgG zk+#lEomk0g`p9I#3=1u@R*7x7UQ|9TJN(+VT&NdpQ|-x2E1g`yOigv){}p4DRByK0 zKhj{aElC5zmR9=>CCatDv?l*NCTBkdjVWjOuta>RdwPg8F(Y}v)yj3d6J*n$v~+)8 zRxwK-hPXTVjcZYYBh#sTg5<)^?D@XV#$fXkUZ8guX1#PD0_%pmLsJqLVvVcdf$w|1*wtn*6-9YkWOcf`&rt;NRk^pU=_c#^zLT=tv%*}FL_c-6aDvR7OFf4q zjzgt8y!It&VYai5!RqXaQKraNRMFHjFhC5W<+;)_Rjg@0a7qPB{SS})Kda3;jXxc7 z|0Y|)fW-SN`P`tusX1#}Kg=a4N-LcmCDMgJ=UuprDg?48<4;-WC*J9b-!+)d`|9ND$!&IJQG8b9m_HUDu%B3NcHTYChZtF_u^@hzcFaTFKWfVvu zZs#pq0)Vw&9@Xo>4MX2(m}dCw_LmwM*Io^}mC^R4MsQj6BrhkV9(iOuM7wmf36KA2 znL1;wk_kBPGSMb(qH!&Xst|7>An~rC-hG_$4C#}r3TgR@RcU1-C^pN%+1yuc=Kg3* zzNM>(G%5buO`l?q5FVS#i_AE+3Hyf& zUSoH5%yjkAxJtx+Y8Judk-Mto7+vz=@F~Kb2M6+IC(_c7N@}gzoZMTa<47n%6v1sb5#A zx?oKiKcWr*uIaW!jUNSjGqaqX>&c*4nmpm=L?(u84oa=8@)lWMqF9UQ(Yr8Pj;LP; znprsd_I&ycZ}xBc54ApADcfcrQ2MD<>tK0<7h4K$<(^SC4wmwrIY-&tTsf~>CWIgD zuuu6P>9NoIh)zdhNsY6G^@#jH{-~_sU%zRn@2pPj^>TMAEvT^W?5e5))Cx{Gb2*<# z>v;9R$K~MII71c@T?I_xGg+aZdsaW}{!T4^Sdu^+_@oxb#5&A?vogo0DAQUOisU!Z znMjpKAJCeLcIKOUD2#mDLy2R;Q0H9Y){wssWOB$9m2h&#tyYRI6Oj{-`(=^v3&%cQ zJ{}%R&!-hGC*U|!e}~hndNRwLM_28*;`B57>YDeRCEGN_zMEWPLnDk-V8hS(HtC2; zx=Y#7<~Un)8jPQdc_ko+Xv8#E&dqCKt7vCuOKY7+m4F3+rY@ibW79??EetTOi z`%xumuEe?2EcLlEYnn}MI5#K~7am=R`ns#p7|?C1m!*FB>A0%{ogp7MbAxqWQwz#H z3!yg?sHwymojY@>WCV`gN`SD?oLiwEC$iF7nc9c#V7p<#Potw}(7>OOskMfAHd=S0 z6ylyGrQ@_WZ{k6>@Y`{4xBt%M|9#YysD!|?+akTTMT?O@ zgoIy#`N{b$_XdiePv~Z%6{ABHK}}d+P&$wf783p;fvhIB#pb%+{tT;>SGNB#L$TW~ zI7JCm`fB2QVNBg@FdOeCkzZztnusD(H%0P>YP$}H^?~R zXD8WyMTB%1KP=D{)c;wC{uwhhote2{cj*7`s+T4BxU%}j+0WdgZs?J_$qFQsGsbUs>c3pbcF#hwv@HNl7BRN8C3oZBp>2t%rA65G$dec*&xB$AiU^`P<#58 zchGnHYiZbUAo|ePb{xniR*Fqh=l2_IxGK}*tYzp*d@dIo{L*XS5)|E7Jf;_7eSc7J ze7fNsQ(9#nAVI?So6V4@ObO;BglKFCLQ|0{%o*Xr)}>R{Q$Xrwq=SJ;8|;p;0pWip zRFew5QtvJ|G&}pfGLE5UTQ!Uf*=}_XoC~O@(>>&*E9DtrL+GI~aE5we{EC6CE$L{|O3 z@kKryb7qTF?)r~bfTUv=I0iVokx!W+IOkqd@f}G2ZM6xR5LKj=h9it+D%H!Ed-A9{nVw1};W?0OI8GGoM38UwuA!&_}Sy zHUpjTPqE_WkDp1iq8>~ok4d|TPWvRUMcQ#rUnN1%r|y#SB5x#xC1hPcPN55lL_MJA zrDJV`J(%WONPw{Osw6GncTqT|H|%&L4I zhmlb}QHo6PIvqDmX?w*^~9iCs)*g!o|-H8b zmj6O6q+Szs)m2xbonyWujxd>N6LJFt4sgy2Xh&8aA#Ex8n5s+>as>=Nlk!*Fb>v>4 zeDg*@x3Vn+4BYzWe>ji!{BY)ten6qxFWKV6bWfU20ynVaMRJHXj_!hq-5xu!=OZpg zh?_a}3Amexy_4+`K@GY#AJq*DkcfLCF7hH;q(9UZ`XnjnL436({T#)2+zQ>&Bmoib z^#~1bZ|sU)vmeBiAl8{U4KeuWGu-pO*Il=k3QZv}4k6H)s` z{o!erE@2u;D$<5dOXcVM>ggZ^6=&BP_1V?s?)nbHsk5i6=qo7gh_!ZJ#krKk;G4jm z%fM(+6Y*GFaSRe|)*erH)0Mx`Nwh1C^k*82b!NM`i%Z=OJ}Y6dEepGe7Z~v zyMgy|+8x2lyiGv857R^i(PC?7P1TXV(@%%m6CJA6TC;PTb$UW0ch%9+OA*}1t}p@; z_Rq6@M2BnQ=ciB_zHe&_g3(9|TCmvK{+_f~Au3gj@BQwys+oM(7fLJs;@Qp|hpBnx z%i%n`f;zK@g%#J_ZTKL32|7MYAoNw^2l3iQaxQ&BUQQ)(7{Yi1Z0>_(Ce6fE5QZeK z|HeIT$Rj?RJUqf9(+G{GEec(f)w#EFvV*)a3f)qUG@M0UBIY`Tw7Cb_gL{YKTd-{c zOXzf@gdPbB_V%O`JFDnU(bG1Q|Cy89vWFkRNcJ$}vkDA@@OMs#1zb6Xt)J`Yad?8o zj%aOycJ^CXaT$MX7`P(ZawC5QF;R0kpoqi}b@zP#ZTrnP(6HHmfKxsbJi8eZx{X&UzAI@r-pB#`b_aIk+k&baW$17}_8kIH>ed%9h!C>_0>^i(tha7V0&FuLl6J|S z?$z1}?19Ddg*pi+KOx}X|3wMgj&Y2|+S(?S$8%#Ea(~1elqY4@`lim;;>|K?Vv<pC|(*2u{SE(>M7%;zc~tT1m6v+ z)qY#Xc{k*=d3Dh`)|Z_3(o*4jN3hQbTe+#vvR=)o}*r>j?@&pel}vWD;zS7EE}njR@R z_7>(HzjqMY%)p-rjV1zg0)i)3xv6x}8U`@5O)>$PJZC>9&os8-zxgq(e$ zb)xb-`%ad-+tF)Bw6QSj^<8qS7niUMISD$#n@pr2sc+tmy!$-R8qDP9J$ENG_=pq9 z0mBA3r|?cW`8#>QcG+(ETRxtg0Gb@FQz`cy#Eu;MWH`(^v&Bg?q04fRN{o2xk2Vi(K2d?HZon8 z8c~S~RiOO|#_D>tQHNaBTe6oT{_;C0gh zM(O<#K3{o9lt0U+oW6U_^wO=^bZQe3MHz!E5bPHr5{%{x$St(oGMnD#N=EKLnSD6U z51E6+TlY;h;bc&UD;eYd_}N5aFY@wfB>qB)X*|??F`EOP?p^1_=sDB_`EY0kq548{ zLHZ^Y5YUNXg=Ej~S%~qo2ON&pE<4$^8F8>=gV0Z0pW^9{H2n>YNzDF*)XO8bJNrv2 z-gGjW94^7|rh+ghdpYI+WqhBl;1v7Iyw{EK>&{5~t`lAqN{97#h4H2ns*tH=|!*({oTlB^3)M_3U__*u$^22#OW5kF$3mIa(m8I(` zo#$Qyh(-56Zf;az*S?PKafm8wybC;8ldJ(_`a@Ph@Qqy=3Up~bMhF`}F zVrQE$Jwf+DHK)ziZ8ZL8J)I(Gw^3E&y>)JpU0_Fa;b4=#%9{~w-UauAEcRt$UM+io zSy=ZfIK05B<^9QF;FNlc9x*1O3#^DJcpR7%Mq*S+Vq?|_7S$uuqR<|XV|`xuN}b0S zB|c`|KVaaxXK$^YT2K`+Z?L2-x!O>;jnqxpRNsS6nv}8?JKu){!rX$T(oTI-nTs>` zE~N2R(x|+%wS8)SG7j+(;Cb*7RC20tSkQOtmOJ=Z%yMiMaw!&XHWu#&8;v|a{o``N z(;zZ4fee&!IY9v%(#`8K-1>k}HifCTk67b#?-c;&To?RciuGD?OkIh9BkC=G+CXp{ zj=RlWFli2@%(_>Axaa0Qs7{SVu+MMm^F0b~D1b#-`N;8`H{2hIx?@jfmpX<3R_au} zK<%ip!)M)dr&xGrq39_CdmxiT;N;1|@6ZAeKQDq6L%oIXDkevDA<|5&s3?J0xgS*Y z;)n4L=AE1>IQ;FcmCW6Rp%Y7eeFkNUOU>tAnb(998_{r)eXN%X%XDnB%?~r76iUl$ z3#Bexxn4Pmwqi0W!SCgVd3QH%=61||A{&11xQRg+)KkAp9+RlQq7Q^`vP?UkxUTb>%9-9C%@6Ul-JbT3Welue?hi*{(4?gLs?z7Q)j+U$&MI&iL z!=#~s3w-<+k_{-?(^sf(I=LBMZ%>$WuCF!7cHnkP=ej&g%=m9E!jjgcc(?ht4ut|~8iFZRNS{G^IM3h?A1cN|1?L{^9*;-)O>1Vwg_9*p%d=$H`10X;pUwKY<`uKGt zK!W2~CvJA1|8Y0>$)f?3nnym>_9{mI>*DIkyT9r8C`?8|PHN(Yu39TXMFP)^$gdEo zmY&oFf#3}`#rSx@9f!__5%!%5{m~{rmqZ7N?UKRPWeld=ACax{q0aSf*#=W2_X^B= z8(-sHir%l4FkL@!VB+5dZ#1Red%`5hYd6fZ#O|b2C;^ zMS6W#0y-C(CbzfHOEdhHXxkQ0-$IYPotm_?tUJE_O>Bl*xkTwj3}Y&jbfbG<8`fs# z!Xjs2`$Ny*yM^x*X|7H4!X`t5JL!Ix#m5=ILB|dKa|Oxu^E(ALnRIL2etayQlgNcI0sxGwy%{H&t@kJdlk9T)aSaL*x}!%>{HtG~=h zR`Vwy(y-vr0d%luQMS!;FG&o0SJDx2D@gT_JUpJ@v^zS;nW2-7kCTm0i8ZXHkV??p>o(8SV z?FX%6b?tT7O~8@Jx^(~Xy|Llrcw6wVLYw~29leTs8SMR(r$=RR3YZD$bN){_ST4%+ zu3IZI0&Jm(s4y@KJB%xNTPmJtIf5E|&9XlfA&eG%{DCo6${w@@7p`F$6C$0 zbI5X$DISy~H(-6AamE9MUUXe$ou;*ge=e`_aQKjmqoe6WLiE)VV}gLG<^kk0|7-`U zh~@8}cEA*#tFq`~Tq5bsXk%pe5@^UK&KT0LSu9sCPgmP`Y-(42y;I&OxHuJZ^Pe7` zp|3l3>n;$STJ9a#EE-);To;xcYS(w~>+Rd6i4>lnoWQ;^s9ll;uEY7rqQczcZ#*2O zRg{z{{DU|ZG`Gq`IHp>jws2?Kk_31n45=hSt$w>HmTqeKvDtO;SGdf;by0*$q@Bj? zawvDzEiFAN$`b*4s(5Dj)N0@6uTaCOw+J^oDGsZq%X+K6-mH~segR+4?kTtRc}A(q zZKdb;fCk=9H?Oe+J9iu=9>e^*G?ebJzIUzCIYTrNxHwNV{&35!OHW~G*FVGXoesG7Kko$$S18mGnH4G3ahMg?lfw{}{Jfw(_%+UQ@QM0Xp*na# zUfuYHQIsg4?>$5?S{N_fviHjVKpO9~%p5ET&aB&@l%ofaIs5quHCjZ!^rQPY6~|Ba zSt+aTnVHkET$o2(XB8P6bJr}Y-oXWTj|{gEKcV%+@Ud&JEo8k}nE`C^h7(1Mr=ika z(jxw|sRp=!;4_BGl)Z?b1+zLz#d#ef6xn9rmvutQuB`s;%XUab)5jsb>hLD z2O2gRg2u2GfYZZ9xWy(dcK`O|0Sbi`hZRT*&1v?E!$=mq6;H$cmo)^fhFEg}w{%<3 z4sd%Q851Vu2`S1grJC;kN36vP699saoFIh}TDD}wQi^+ha+jaKz*!3nr_mX!j5=<< zebu>{So^8^q-pl>Mmr{o!PC&%vOlPl)KK;2$3Sk!-o{0@V-*jz=W-KfQDH-sJeSuo zH(zn%v~#q~FH@f1IyKEx)TdeqPEy<}`C0MPO|d0~2}51{9B1n@(ssS{(nyY~{VR2_ z4ts2JorZEP%eAS3b5?a5JF6Y;HNoY$%^%2a$S8^;|cHg75e z5%6n2c-xg(^=)%<^x9Z_E3GRJl-xFd{Uwux^BOQY+Tkz5iJ6N7OJ1o5msdZA`q5D@ zvW-M_IuFP?Hm-T_5_Er!I5r=eS3_&bq=c4UGB6g!{UNu1Gy_GvS5!cPTNS;7vxM5c zX=9Hz13p0KfIsp?SbNJS=Uw+zh&sFrm<;m;+;lSbnOu>tb^(?On6+;($G;Gd5V)?R{F;$Qo&#J~JKIi@9FNVR1!QNA(o zkVvEdZY;T03nDqPq;Te2cn@Mn0)1Ls4%B>y96@#De#81cnW4A;YZ>xh@!7FpT-^{T zmEbMtVisT$q62fXrIkD!{>T9v4pi>62qgGt0NSKFWEQ|X?(iMA85e-~ny=tc+OO## z)6Kgg^s`7=6tqT@4`>NLfky4B=Qp4ka62sI)TzP`=6iN~%XxmWI4`xaQogsbz?fUn zSZU4BG+v-5w%CMPsnQ$J4TgJn?q#m7ZMvAXHEMotzDV-n;dywPeA&;Z|yE#?waC)*w)je`p8}|D|U1X!};#cfIJ>vemd|I45SeO8?m(R*E zv+W~!DpKL|yN&n>;s)a=>?SpjQ_KG{4p_5hFnjYSDFH|-Tgx$HGdIpr`;FRGM7OO< zD_dG*dM=&D0dxE}hg|ie9x9pq6BpoN{?k<7I-p~Ww4K3HCN zH1GNZGEhF-yl#9aVS3n!KJH(4biZY`D0UHvp43D>M$yr$cA!FM|M`yj16T0>0gijOVjcQ{BQ?l?RquO6>L0(n)apC!rZMhb?b`A z$mVu4Elyx^Ysa%*#5Zwui^#O*K}V2fs`~LIP-xisy76Lmp+SVhC?p%qtU1WT@JWip zI3zobz(d95WYy2)ex7TU)|)5y!$TRgE4DWDLNIoIw24Jv6G*HXU^^c9p5mHtnM3cCM&j;T|T&v3JRti@UbjY@dur=d2@!8tBodV+r~)0&fqIjMLVfTQUH^3D zj^lIf3@gcRTvZSeV98Od2b(R8}z+obp6)--k|7CF6!3H7}EYlnW{vnsP8t+KW|Lmi$u7N zxyk;qeXsXqPqFU1mx2f;`W~!m0scGMjC%fgk-gesenMWVy*m#%dE-dK*t;wHXNem5 zV#|3Bgps)C%oOq_B9(kf#SFhS@T+dSLWS5C$zJ<`V|Lo?3Cgejs--G(5DPoA*}S01 z02ab|!c?8uSAbM^vZ{b`rBb`)4G~{M#Lv*uklhz{Ei=YT+5L7$5}*TvPa6}nFP6qc zixLP%Q{=?S?ZXf~5?vj6_s%^&VC-W*d9(KmUlp1nW%PHdMsx8qmp$}WKor}a@cyI1y=7?`mw zwvIrP1`?($(e@s5W)cBkEJ7D2md7s!CvvQ}QmvDMg#u69F0NF| z19tu)x!ftQj1>s17ZWsy#TtfwqrfeObhL+dEn!uwBis!Z9&lVJh*{}*D$iYew@$oO zI{YXX^uaVYGe8v>i3F_DRB(f<*H889{lvTH-iU@6-|JdI^p;?FaCOM*$v^<|Z)_nl=`HvV_ab#O5WF3r7x0p? zh<-Bxv`SkA-ufoz6&B7D|0Y zs@G;DV^nTx%+-#Oj(h!-i*2QJ+YIPFHMgFauQH{Z1`W+!Q}al z{_Jmqc|AFwWxYm%GQ4hF59@)OZL`OR!Z|rLyI9zq-OF0e#>DGZLEb1koh(5$NT)d` z1IMTn%KU5%!6v*|M=bkYuRFe9`**jOosTZDtE5}@Z``X05Tq#!sH+DGAFIW0AA)|T z^(U=_yx~7@M%oZ=EG>BCjaPcNo~pTAfb~g7BDRz1e;w0PvqTd?pKcx#p19T> zYq?ky+m5t3zNCEZznyo9{DyTuDsZPVpMEJhzk?59kFtyC8kS$d6E6xuZY)rJB$jcn za{`?_oC?nRP3H@e4mIZsls9u^BYm_ODly(B!e%@6>o4=j0tEDSqTh4;nM$;tEqmL(ap>yp&w>(Wog9Vk0H!4#Zia7PmF?0>UFU>4-)b~^q%k|oK}Ew} zBMZrbkK>+z3B|7do{c{_!=CV;QoXmw*iT^lN!L$|Nv2ls72o9f96WHBuM=wC)YZ#X zt9;pRUZi(Aw2hb9tN<4XRNMGCG|#FO>060z;OMsU`X}ZJ7df+^BdpzE0Q|(!&unSY;u1_*$UtnNsEXX8Wm{?k2PGX(?ka(F?*oB^`q ze8{<7Ng{0A1pvx5JLzbsHu84)kfK(xnc>7`zf}icXzBgh{=g>^Z--sS=mK8Qy zlm?q;&%Ir_c+XDnTfgt)x$EP(@9VhhJ3bBoeB)hB<(jMimz4wSO~1^I_x4xonpaL-uI*Ws5wrf0}^(F}RKB)YQ^Dn^IjLlm!r626l>SWk(j4LBF z*D@N4Ld4EKhZyMN<0mbQ!=NybfEF_HGTN~dA+2zMbolj8Xafz3mmL?gRW`=X?ON(2 z41bkJl>6P!u4!uueG1K78d@lL$UX!SrsWh3rV5dVs^9-uuCLnZSu4;G#3&&;fNmAw zz9GQ!V1R;;E#x9OU40NEbx=hS{8fiuV_<7dVgS`z!l<`(eNVP-Gf97IOD@49 zSd4B7H?GQg@S#P+yIoM(vsPJTW$y}FKH$mok*w)?;&D8vvp|beX?0gyT&I{de9_DT z1|h@p%Z6@~Nbb?*`1zS1xD_K0;!G6+CIRXmJ!VzL5oemu@%vn_xW?_STpi-}_){9y zO1OjvZbfKq;L#6SMqA=GCT{rcn6|U08r{M?$iGoKpY+(`{5zn&+s~@Pr3D?6kh;bG zMF%x{znhq#@(01-24y6Q1BwPhb%2t#V)}pf86?H_Sr$3r%M~MBHFE$j5xvr73@b^a znD88d70wBFc!S`Dw21^c9`G)czj1+oqOdV{TNUg-N}A}q!WSz((`!#x_GvjfHLGTM zFB$06sQXis&~iz6>+$az*rt5xdR#9gA|s~GF)rCjpkv@488@K&9rnt#;a>p{G0 zTdn?G0Ov7^iq}TM@ol~$CFfZ=(atwA#a%U)YVI4Y{!>p))*&?}$6jBNWEB;sU0_5T zX%!Kl1-lCU@}NP^vvs0fVk8}P;Xz)3yNV>mZe_$lz4}|+r6L{)dsT(}oUML6@j{ZU zLu4$Pv7RR>vPM)Z*kz;0$V)5`Xde@Q8-z1{rNrDVB)ZB@zHj+Ek+0CmG4ev6e7{0> z(NlEH1ZTBCs<|YNuh^&qZ*^a)nbt_U?>R935*&x}bwR4Rp>O)&gH^vc?y}NI-q2#M zTRZUrj%;0djF6*#GwFhfY+Y%LkgZ-_>M1mCN~J!8qyq)WBr!(F>;Xf)%07DKw?!i5 zLS$sxf8;LZg7Tm4sL=%z3V=X5y_I-S~AL{d3x(B2N7B(;~o|J>14>CJrg57FZ zJC(TH&1)(j9tMJfT^;4NFm}57TBpx_GB;m=KL}!#I)k^;!{lZS59FwBG%YdBiYjtN zje~VQ@l>d?Gp`s+$rST!SW3w<@}CfwnlMVq&^*~JRH^Fx^mQ?7Wew^nZE1E=y4)%v z1(V|>MUq3HQi7ly`~ONdT}?cDX5ynMcIe@SBHuoR27wE}pqoVy#yl8Vqc^!)4KxUteg(AW+K7s$EjFc-6U3jyH32)n8ccYuSY;?yya{#t9bfyb`efF+k`>+PD%e zND6-arqKfB${3I=P8^ruCQ9Zo!IzJQW>mUt+s)w+xdcXe-{A@Vw`AaNC_#W0VWR*k zZnt2k4_$4#-TKl$#{rbq}yxG>cLD*B2h(b8gIDO_(@AapoRqRN#eiD|=)$ z`eNKX%zSse{fW(5-+AIRPY+Hx&i-~0;Sj~;W$i-Z@0tY>*GJ!Sut7BJUiY7y7uqk> z{DboB!2rhllg$HgIEzWlJD8c{bays;OYHqwc9C%utL*CEgFTJxBQqOVSQ#8ZWc5K2 zvEmn@cA~^pb_#*4q&F@&9srEFP*~Xi3-_RnosN)2^(bEM<%NUfeU!sWoMTgZ6zyWtU%k-6pAc$|@Kp;0TuM|tG zAId-cY^61~W`wD)@2Hxkm36#p7n4`hIyyvLO_tNtPl5;I{PvcOf|_B=a4kQSkl?Uk zg%E=S)ykqEYxhv{hZV>uprgWKd|~0z(C>Ln-gTNT&`Sa-m^W|hr|E< z9RBxCbYU6npT%HeMHs11zJvW+lg&wD$=U{*JPoU1f$=L6+s_bV+~a}J`RV*?U*$(E z+y$hU$9uwi7iZ8YD^^`=le4&F%3-IC z$7i#vFp+RxT6Gno@-@8Z1)3sRmKxGEuG@21C4_d<=!FV&1fwj<*)n3L%t5UdHFO}$ z*)LF6?+&&64N#VOUO79e7LCkh&%u2A^}!__E;k=W)T$e%2HV53B^?Cgs(Hlz6aKS9 zZf4V!ls^FI zL3%p8nQ2)-(O!Rk*9Dx#>JmH93LBHx> zu!-L=j%9OjC*zvxHT_ckv*DD!RIN`~6+ror&b0rDW>y zx6bwm8-(k*xx~_4MltOh>@OGeQV>Ulnv;2?oq(altJoGm#DmLL!b=wH-I?fY&akB} z<9Ew)b{@EWBOmq)Rl;{UtVUOm)S=|)6_kvGXiiXdsvUPCYQU7txD%CBb0t~b^JdKr zgt2DDu2eYIv=h@+dlj|SFFqSMIROBaDB594Vl@eg9KQGiOwqh3r=S{vWbr816|T!F zw^mb35yJ;XdA%YPC0yZqgnb7yeb?{#OJT$m3ai}6BUO{vD_Q}>famuLul)UfS&KSQ z-*(I@&@*aD(aW_Bhd~sXC(al-V#sZnIUkz^W*`6Na~rM40v0=byBbks$y6Lo(xnhL z*W?+v1?a*C=2q00U9B$FMt}TkIVKCkBVwIyLQd)wdz7`q^jF)@*1|x}EP@gBL+_JK zZu9KT`xpzu{7-%L4+Sr_W>!adoZLEa=ON~W#EOQLg;Aqk%X)#Su2_9=Aw&xUCbkgv z!L)iy4s%UfN6|m&yYvo#`dQPlt5JgEQXtTnwwwy+X7js~fxpqKwC1 zU~Qx>a;7fv^BRzh)-QB5giIrrXMR1U=F`Fd9$+CNE)Ei?9f>Y8sar+^-DFBnU*3Tb zzG6Qqe48rsMs^Usef#^ZOE6>!@*egK>Lv{>a)Tmh@$J3YsH<9b{-(KxL z3IJ-v$RcR-b~~5$=M`=P(1i;(W$~Ehy4kx(h?t9Jlyg(s02hg7Y7RyFx=YX>T!390 ztyH0X*lJMa<`ZNae5MCI!RnLbptDUfRVe`dhE52)E3}ZjFHbeUhWi9rv74zcsd~_8 z&2x1#V1-@H=sjclyM+q=+#9dlL({Qqi4&ME9dNsh;WfdM^7IzI=%8a_QQEQWi%x(J zuE9>957d#HQ(#0NOi2%MnNkoN9-xLLB8JmhCoWw!6snWqYa>x1N;F>g?7*1uydExE zP;M9V1XKyG%rPzh(#iUmy xy;vOr#435xifdc*9K>4;MJ)Aigs+Wadb{;vmsl$*D=L}b82rofKL7v#|NmWUTWtUU literal 17714 zcmX_F18^q6){Sl38{0NFwz0`Z8#`Z&-IyEOwr%r^ZEkGi`}5wb`fKX+y>;eR&-6WA zJ#)LUz`($&5W&A%Ffg01i}TBBnLE2!JJ^%4@iDV8vyzFsS=;_32 zqQx_YMWmPm!fGeIEmeM8PHwDrv9erFotokjZw z&sJI*_D+eefie3`79op~Z#9#fpI-~QI$JNfI=MWpzC7)KV1LL+FBf*}c2Uama&>#y zztp2o5)Nvu`6eu)W~9VRou&Hxt!d2obU)vx(1yTVo+|4WpNn*YD+DlyH#WgZ_sfV$ z-Bs%F)NEXklR`g*Lpht4>8ftjgdPx&UKDOz;3MZc{v%B?zC!(m&sw!joD%g;FUG!P z;KLa+n>WM|?JQ|F20H;LS-f_@qLhG;XJoGFaH`H!D8fyPAM}ks{gcI^n;C{UFMPW6iygA`R`n@2X5nn!8>k7RtnY` zG3|`X*|)esn~-bERpaZ85hS;4K(exFM8%Rxd8!%|IoBylz!U>Oz5K;3yAuOy#B8jE zf3e&Wbi2`T1Z#H!X_{ewc8)(| z+jxkFI5F+{6$$y=rt!@U?J(u=bsXKh*-SKK@Bp(t{tYAFosAQ3vg9Wg&Sf{wO;0b( zRX5I6Ym9APSg%|P*CeL+WGr_%GyKIhRd%o}#Bi4=Zo`zJufc#%B_TN^N6eY$%}m>D zeW-k}oSbw>H|B9!dS7LvZb^PxdAwL3xP5$Ui0gzUUF{Z2J4vBbR4LSbFPD~c0u<^T#DAlRrE(vcqnH(iQL_?a;l@i{ z7Q6F7gFg5YSOI_48R>ow7X1WJyfB&==*jWKYpm&e7W&H^-Ulms7AmOCx*<*%a+8=w+zPt8o&+()LAtFUQ{Gx3 z_M5en=#fr5Np?Og&Ar%`7@~`u*MR9zA8Y&!zWF@dw%u0R+J5y>v)D7&ZTtXq)36*f z6eI05WW~qcdLu&w7*8IN^Zt-7F+(&4@ME*Qw5pmsBLo?B8mEKFcC#x-FpBx{{9u)Yk=Ct&VB5@?8y_Fj|q#PA|W8fV??q1A zwRD9Ck>e)DZ66$p_`)42wNYQ9uwolJpC|d2g)bj#B+KYW z!b9EW9(?F;-Vta-%LITA%0=xWMi-xNI4@~-O*2NeLr0m79Jg~hb;cb#r2Met*3*9Z z_c_}?6gU~}41#aH6phu37X!_0pE~jO@CJE~-vQPI_gT_%cRkk|YV?LmBqTDy*Y_!N zhj7Wx_ie@pb(!dI%vaQ?>$C(q(>8B@gPbI$<{)X~iNJH{ar75%KB%}6ELuy;LBF0$ ziiA$0P}>Y&^n|s0rXK4B>`k(NuqIDIE2TB^MU0WQx;F9J;y6SAUE_-u!B$4MSwD<* z9b@T`M((^G{Lz9pRUE=0n(Tnl9!`J6itGEgi!2T8%K=%DWd3lZVv>tgwG+u49jWnG zS(CP9pu?&k|4F4jXBbn4K7T(QOz3B6A0){;(>REeHq>29Oto^1r@W{z2h_90 zpx%Vv2R{b>!(qHoWH@fp(|Z|!>Ez*gUT)NV&$~$RSs)c(KFJ|KJ)^XtSyDe8d4sow zypWI4+%^1e0kvys)Pf)D!Ri0^f?8kJjO?fryJ-0?bKujnB9A5TJgF{Ibve=#hR&Nk z#bwhM>=dJBo1(_A^7wFP*B2Ll_BEkfg?Y>Ro+XCh5fLe`&^s;Azt1!ikq?&rJQU9% z#{xtdTV}9!vI&2yJN+C5B{;$iOu?l|#GLrJ;$XUM<5sMXWiK7kPy&4rtaubBCcrXE zzc8A;`-$@baU1O{3*}zJEm@Q9y6N1EGs%o=k7;&vJz$n*sf^EQl-2ki=3@$-P0MJ? zGR?hERi4ufkQ=yEv)|P+$ zmOemg2PH2+E&t^Co=(_|!W=>C55(&W;BQPYw=pe)SfZBKWf~3xO(ee`N@(-wfKmXbI8NPQR@XM#x zk7)Z!p)R&P7B;r*b5MlvrX5Of0{^6d$|v4=`~%)KCzB#4r~Fwq$afHgXI>-Q=VIsN z2C=0jGJfnLr%gS2{61MHqA&W1s(zp@LK!>;YId$R9BrWP6J7&80HX?gUQw?vWTaVxA`|?i!p%Q}8PKM@}P_ zMvw{&Rv^Lux|JTh4s9L|MWdY4n6y&CLRtkHZ513D`(cA#%d!UAj$qAoX=ySkm*F&9 zKOP=7Aw}>pZ*op||8?f3fWd`Qnw?VTu%sSI6^L9>=5;op*y(w{`80bD4O~|BY;&_1cu!UV&40*x8t>dmZ~0{DHk?Fp z+~AzQYYC0gi5@|s_nHsmHyqoqunzE89&_94xp;LLou(!_pEym2Or2Te_og*vESt{c z^1@LIvfxZUw>30p;)=$zU_{o-uceSEX)oBch@)$8 zl>N6^T7-i!WwU%0_)TI#B^gy2hT^Gz*K{;2!ijImq1V9DkyUd!yS zFDdUb8z2FmD0I#&Kjnt1Z;K}9vBZ-#-x%s{+W?ou-*6_I$^lnWG__RxAOP-#ptj|X zbI=4s)z#QeQhjRn@99ho_hME<`vGIL6PN!V1^hb1c%BTH)OauKC^H|2(UrW<;7Ymxzvs7v`>h?wb~#&SSTvL!qVyVKcTP=M z)hLd^IV=~h4knKjoh|OD`5FKTnX8?0)3#ewC94^{4$yZnG+Nmin8jij#Q}?#vtO9| z!u%H&zOeX(rGUkA?Sh7L4mq+#!IbMVthB?`lDb-XD@H7st{h-ECvVGcfwCRrU$RJa zyJ|RY9;SHHAUJywKGj+a%fn907Tx-0a+9egYr(Qr{^*hPs(H`K|96g*2Kr<}*&IIt zR5N^vuUpfj#)P9;sl7S-Q_q2LX7xOjQDfavUj%!<)f1&R22UTmC%Z}0+ZVh!zU&vg zIlt@|ytz!c-jXOa#Cy{P%Z79kXt<`viQ}WH4(rnO5hdvGB13@Epb0nKmaa2roaa$FMngZz1h!)vn2NlKV_4zTD3%xjL_M!x16UG(4v@Y zNq(uh_WUf$xv6f<)3M~$5hxDun4?Zye7y8t!y|;y)~~uBM)_rSC8ZIK{=@R%=tz*c z42H)p)1YP6!m2>JHO<28-dp-nc*8P5b}>yaRB>#5z6{ZCb~uo)<0fZQ_)dLz*dgD2n>ydirACYa2pv`3zvVKdoz73}0dGC9_@7Z~#!siGN2^R}8{pgKm+?DOyoO%W0%lA;Sz~DK9&oU4gGbugKV0DS z(KjSIwKLK@N{3k{q5Bq+JaM6&tL$jS)4LY<6@s|WYp2JF3LFRHtbY8eU%Hw|`#9tC zm}lSt>V2$py0=Zip@6<8yXQ`R_r295T+(;oSGOo`E}F~}WaqdCSE9LlSUj0e%seG* z;3V;u&06T+NG;-U;z7cn9G(;omZ9XPgbykM&NQ)lxXASWi3*R07_-_h5M3DU{*5-Q zkWM#SoJM0Py!k_$*ip}IURJqSk#AE%nvfKF`mQb2HVPlOb7%D{LsT!7lldVDY9y{j zzj3OSmbKOtIL#Z1uOpzeW#Jkh*mQSbH*8)S*mQPa=Of7rH|LLBxk=-|Q7wgBDMaIN z1}{mGK;iZ>wjPB^X`c@(0BZ}#)ZRB@viUaZjjXx4RNO)gfx|{Y#tD7_04D~3X92(s z0pObea3KKr#2tj!9mFdJcxP1&VKv*rwUtSyx)t})A2%w(ik5(hfnP+unKa*Kz&0EP zpV{i20W^VUXj|!nVC*p_-HcS7f@NGw555*IW!gawkOu@Z8GaG{mP3;!2H`iann4cC z!?iCEx~QhDG<8o<w9kf0 zi_6@|r$tiM>h`1cq{xyk(_mIbT{PlbDNpU)JTIlbl#3w1JNuE~KTqOv&l5`Oa%E33 zFv!NQad<9GxW4;i)!4XU&bnTS>q^muJQvNt(&dF_VT4VvY(#BggiG-8!*p1#aDW%= zfdv*SxP09}0&V*=XvThbN=;hquJmqmF@a}9*+%K(@nG#Jh+DG=_igzfS1Gc%)o`P8gV(1b?j5!^87{tm zaF5gakkLRFnAp_~cSXz8byqgm88`LTGKQ3JxzpeAsI`tf8`FlCRl6l>g2xfzDY4JK zPuWnkRsS4%I!lxnbNQday*!=|e1Q(VxBY4mcZ=b(G1bjwkIl_}Go19eM+bQwFe?E2ue)W|n=^B}*^A^15)>I!0fkj#qzVI?z#CS4*m**$;O<6M;shuIfJ9 zvTQK;V4?cs+u(0s{t7_?@;@>jW5i&VkJh$|PE!HlqcFSDqsfMldj<7|v1fi+&u4yW zC06BjN$)JZKtc84dQwywdcnUzSicEXP+zkH`3*1pIvs5XG_UbLF+Q*#NOgi8g-(HI z#xUbnZbC}8>j@vRpDdK8j>Pv9pK@xXLPII!&+JgL`s~2h6SJ{kqTe=oGSyQ58nl)< z=pCk80PwC!=tISwWsRF^qj6RVIpIpWYdE)~b=L`@fUNIE zo`2^!g_BQ8&8c?t?>T+s{#39{^KP@&vLKT)M>Rl;Fy06MajK;}3Y>S`%HJ?1&;E^v zKxL1h>If!!g4sC|h?eL?_b8-j0v}G!OkPihB|G!v(J5}fxn=&hEGPGt7k)YRJM^HG zkD__5fB}*RvbRZr$D6hDti-tgDfSvl{R8v(SRqq&_<%Y&BMm%g?Zx*l zpcg6py%azjXZ70{%X9#oPdhEFBm?UP5U-Me_NnX04y7i``G{uE^&5gu;#TK7g`aK} zopRVjLFK{5>L8uBmZTTCYP^#h`r>{XmVO=8_(E(d%-T~V!nbz|PPGA1kVyDyv`8P- zodk7SA|XQfFd?7BlswzRMCt_^hE&9+4k}#9Arm%&w9d+Fwu~(E#B2@_X$$5F<;_n8I z(L#4~5GWj4NWx`})CIxsCD2ZkV(f2g-#}tF#$oo42q4dX<*OTYVOlrT@v=9+!l(UK zg-#YkDqx5|Sk@>0z|DhftjsH2p#v;rkGy5Qq7^9^3+}Nj#=r^fHa3`P>G6+IUzpfH zPiD0_KlrsQ*-+6pmcmd9UsSbMOR$$53L$*K4Ve7Qmi=ulBI5{G#5uac97!+QxhwKb z(i49Q!-#uW*;N=1N?)Nl9x`9Zxn;`DsC#1B7P2m^6RpC^Ctca?kb9!S6fz;?lO$OX z#0fCY2%0b^#L!?}TTB4`gkUEA;e4N=SwxC&JyZBwmhX}Mj2~RLY7X_g+=D#kKgpy9roRWN|9Bv5@@1^I1G~D=jqIbZO-mpr`$4`rHH7ZAlB>9AtM0~< z?JRQ+zphm_&_7diUCX@DPFU z4$ozP0WqQRpE%||*wx6cMqw@?V5@k>$gieYTd?O{!l-XNFW(L!eGJ1yV1eec03W>k zQ6HrHE~o1rS=hM0-Kh8SFD3Ckz+>a+_Z0M=ebPvj+iZl_WpofW;ByDL#*U9CQ<7kh zX*40$1#2E(1jw;1NI}C{3ji(>g?CqrQY(^B3DPZoqe^3qH^fgf_2nB ze`$F0pKD7^Zf^Ik%|Q35$Ev_4Ut%F4;s!%v;xjLSj<5?L)z3>sP ze!tP>(4MzoPu@d}MI}Rw^5}hPl@kDBqV9gGS^MG;OqL$ezBz%weNF_VZL?ge`6t{` zyc$$%=t`EcQ_5G~TYKGx(w7%MHFN1I)H(%-vTW(j?-f#roA-ZUZ|{a6r`6|p@ zYs!79xDl+dcK)cV2R;$<$U#%iLY&5KR+xNCCJ%w&Gse%CM4?R&9wO2ihf!ueWZxhP zGvEHsTr_kfT4~=pobdgS!*V&Z+ujb~es{EbhqBrF!_Tm-AmgqcHw@mLu66Dy+n)W0 zmpC5kq`!6Q^fVgvwH$ph!|&bx1w`xA>RP)#raVps4{upi+(j*+O9JHNr@t#InhXmz-7f+QQJOLr6F*2jwy`-%=QXAuB%}$7-%~%=t@K$!=K0w{WjZ1 zd+_NnSR7e`)jt7Y`dD8F56-CJJnYgRx43)H6Jfv+HuF0Y4#@f-%1(2j@W>H2f_% zJ<1ke0f+9>T4eLa@OWj+C^Cu;G)9u0t;WV+x(}J>_zTKzMR`7L)nSClE8yLsAyT*I z=v`<_n}=sxtT)z63AsPSTr6dl_&E2W83z$54}~xBTqIgNa{rwP(ZyTMs3#(xMu@k2 zrgmFReQ4~ycn$Fg5v3Xs)>ro}=-N!ACj$tw0X+}xSQ>vYn-T-2YYaTLiw@4A)>vbD zA~b%2W>}5|#R$%ZIK9p<=z=Y2u(aa+aBg0NS)LwI`fj$LM+QCio;eHe?-1ieuuov) zr^&krPV@?|WZFqigk(ixpXm?$0}^?Zj04|g;7;3E<1jlZfqnw zDU^f=8BVTc#>2i~x1S`!Z`gB|L7z{uQp3_j+o8{}Go65ekzGe}Mo*JINM#k&cR2T( zjVXXJ#0cl{+*>W)s6DB5&Mb#59#(&P{z^cz*^$czaT7b)-jAecI9&@)*JhX@`F4@42LeXVUETFE^FmfIc@y&5XWw)T} zS9muz46N0+S3HLF5OhU4exv{s>k<`TZ1>^NnBP~2bTNZ>2W0`y1T_lE(Kdcr%4!0L zj9n}LN(l1qel|g9yJbFsz!5Xd!5gqW^O|Aob_34z7TDe0(JvG<_55?&3R^`DH&O-L1u-aSjB5!y2!X!-=Cb!}e&;(?fn+VeE zR&%MY5wgRV^_gP_bs~A{Ip`ht!05c2Z;fbJ^ehp3bqly=2;7^B=ENW@R3yc(QBj*| zrm1k3m2DqXzfE1vw6sdFIE8jE62EeL{9E75OKF$b-bL{(5x6(JoSE3jyK0s&uSRH= zS=ebMa(qh*%wRZ}+a*1ZNEjyeIJiD$m-`4^G%C9o5H4wcF=9xkzA`Vph-D{NEa}?@ z4;M)pza=_?+uTIKmPu=Vd#oEcp}WM9ejDlzm_sdC%v-ysWgm`P;93h9&Y8#guFYMb z7`>2%xwc)IXp2b_--@AJes&Atb}<#H*%4Q7G1f!i1K(KR#X*sjVw67LrwB?mf}u4` z^{)8$uTxmlgHDOh@eZc;`}?}r;jhYQbiyl_1SPyH1Biy9g6 z@jSre-`PeUZmWdIDawb3=#BQTE1f0ZxL@Zg+}3Ju?&#MZVD4vO+t7bmenj1PvF#)4 zXy#mjU#@WY{cK9(+LJqmure_UeLIhUZ^NU}!+aOHaOB3?Rh&R3IcFIpR|mzn1G zr!WiWUl$JLS2IosHFhS~HjMoi=t;(`Z>5pd8t58{Tv{pa4Ox)wA>ee^2NjPe`M=*RxMj%Z{zELY?-!}F22~) z-x@5}!k#-s`aQ?`EV{404m(8M9mA`54!tEgdC$)JIJ1U*8qF;Zd_52*#A=zE4PjR( z7KDC(B4cg_*F!WcZu(psbRt`j%PRL$V3)26hW<+iKD_<9X(mt7^iiH^1TOB`Nzhk3 zANK79Z#%)IFL4*vM_j?b3f6E!{5R`wEYS<e?d~O42#3t@4wK7s9Df?msQRZh!gdoJjpAtUX=CbxQ2w$z^@8X^TDV z=WiHXUzQMChiB9knv}}mQlV5=RP8xCiG^l3%=uvJ8#p+c`0Y=*9A_3t?P6WF)aexH zdYKsc6rq&a{lI^eZx*LDJ^j&vui(~Fx1K3)-;HPcbCQwmzr z6$74Q4gB*evSOC~n#taBKQTi|0(|zTR?<%DPUKc}MSfVI8NRlrE$%<;)4O?^h6SJ= zCrrrCg?qWx>ltfekI^7imjjWiE2E+{yE4*A>msB0Q&RF5y?isB%WIuljfDK#`MEv! zCROY-?VLN6)IreBx;^K>4@U4OD`cj@7S!2Svjp{rh-K8%Mf?R*pLSuLtip4NUH$QC zzu?6Bl96AS49b~lws?_70_j7mAe% zH$cG~KGWtONh|RuW#he*R7Pk-1ja(r@u-J9N!~CF3=esIH{qB+P6wZVapJX0JwUC* z#&fIPM13G^AnXFNNd(c(1DiM&!(+y>n@*t}a?)>{qXRGaL}pxN{1k~c6cvw}-+%elZG0mXMCXptT$O5%iF}Hy5i4&Cb>!;< zrq*$=^cC{}4L&}ifqTf>)Fr%5N+y?;+S)te_vJjQ8wlC8oM4^1L07fIz~YWP6^(Of zq2KK1(W!>eHC=d(oJPg%a{FsRV)FBr`##N1Tz$DkCvFnL){^X2)|bsreZ9FwhJhiE z?;#y$jdqUhMk8I9_^#8ZD-mT$9A=A)gXckk4icaj5t@Fsf zBEoUiU9dsN%hGi(T_d+o@0$462MMHLcf&?VeH&98yVI$6%^)0JYcw2hCH4)PIW7R4 z50lEsNdh^Q9@7ZoJ&W%BuUSEX!}_&z5aa%Koppl(OiX^mBvMSi;{4!Hxr8vGUrs5~ zltT3WdC;Pvqi~Lt@%|WP>mX@AxFxi(Qi3o;tzi*U!^H6rn3AQ>&Nsu(Y}d-YqMD=- z^7NxSd-L{p^PO>9KeC*G1Tl}(httZ`&AIN7+&HT2>AUqoVh9*Jb!IuSeHVcMF?j+B z9zBJW@@t5D0wuLmO^0knJWdUs9|c&Xx=|9a@9fB%h@3Z)2#woNnp5!*O;fuB-{sSn zg^PuAOU$C9Jjb{~>?L8yjUg4Acp`k@SRSNg#<%cOf^s-+bF$)%-KDpVqTX>W5468% z0m>^d_Il5R%Wu|dPjBT7b2WUFJ(p3P^IiF%)5?3o>CukN_-$8dKg7`}U+~O4l|H0o zboyhIzMd`OR~S(`X3zp4uw#w~Vtm4QLzzLFdSb;no1|=EqRFXDg;SA01Xmo5h1gdN z^TBDOfM96(LMzdUg_T|^CZW&}%GxJJ-Ix(hxGs)7 z`?s8*0~zE4b-0EQw8}G>1(5Rzhhy>M^ld)qMPliNA6005Oc{b6^OFD85lps?z`U)& z&jr3bU9h)mh?R)|yRjW_j|wQmEqXEkMS3x9Q8e5%OdkHTd9(itBhY>lY0)h6Q;NV8dSvlyW%PHftM4ZS=iQW{{0%uB zA@8pn_TNYO_$_dsa5-}ZzL_#V_p|K=N(@jMBNJTYB z_fW5Z@~w7Ddh@BUeT9H(x(qtAkR8Yw2>75diQzbBx}0I*TldcBn5$`(aPVk;Liw5w zn^Pa@UlTxp(m{%ae^d~kOW32KU5~F?Fz~9Ch)oDw*i4o`<%6XEN16oaGnnI6mF%X( zp;g9Ci9N-5)%EvniX(AeWbKa~xXo4K_OC)i&EuZ{nA;iJm8@NEfPb(Uq_jFs{4*W3*GAjS*@Kzu=bbJngG{xRc&5|E)3cCq!9Fc&BT2w z(k@uhX0$q_ep1DR>noocvs+_V*9*J%lJG0~=&p^DT{POCF(cx!C>`6vo-6l#mWei0fwu zxJsIJ`e0mpY42>eL4Zg^-}#Ui2oX#`bzqO`(6t~9FmE&P^O8U&=ec(Uv3EAGasqTz|| zSDCt*cibuggkG4EKW=02Wy*c;{N;Gp&x-0@SUC3le%{{pmOo%A=2&s9I6VsFqZC0c z+zJ6{GPlc}pd@UrX3$=?Uupj_FIYNE7E=3k(hEzM6S=bGtub<2!2dRWIDQ{- zGFIm7J+gZk(;TBTRe2`|p$v@~I%;#%4QSKy&Kmx?il~nWhFl({pokhf9km+_cewVx zvF~};MTS6a)X1%Zi~OcT`3&dJmGcHIA~&a3K!!0W{n<4Fe+XqU}-5%+zoAx z>8d{Wy(-LywIwiHx97)xI}-xVc*xIF*LCiir3!6i*@uOL>$egFe6R7X-N{490mIlTS@srUppH0vAwLh8N?Qu z=E53Xr-W+Z!BkZ>eJ|WH4qB$hh=oP^Dy+w|6W4YaM{c~^C?!({%hJGkNLsRsBD0L6 z<+ADgA)4h@1k1L9P{cfKEb$t~-__XSr225a27a#o4O}v}1&fse>4?M^HV#4f$wt|n zjYdJ$6CY1U#~s5X=OXVH___4kkT)?fQDEa^nCqWS@i*8U#CCS8m(UDX(PA)`*P5AY zYj3ahRlJEG+ioo&&_$c?TMAvJ{;il}3VsqO?w14B{}-_EmqH%;c!p*!^7!>({+ z{OCNn>j8UVegG+X2oCL>C6>4drWHT&vFbODL`C)PSX5=*qLRKRCYbFSym!FR&Ku

      )l3!rEmGIC1SgX|ors zD;~|Wt=!c(kv8^~xm8vu=>v`$do)#N0b{j_9q4}xWB%JPtnMlEb0NRbzb#1GZidME zA%}TdJAU7A%iyro;o2PRZ2rcF;#l;tVS0TR(P#XXSG``BCqB)WyFibe5+m)&=N?8F ze_!(TZ523QG4gxDNX>U~(imWRMKO~3yv0f+*zq)$Fd;jqP}mb%h1(VvM+he$E-uHu z;?Rx*GmO7H8*dNpC^p8WrN%H!!uF2B-L}3y*}ff9+|47-XzPNew12~T*MMdSKW--` zd+nY6t)G4Y9e<|0O`=B|L7s*I4E|Q3L5&s`U!r2e?k4n2O2^Jy#*rbs;Kf9pr>5fd z*89KW(>YDy_7_CK@|lTZz@@KnJBQOUAM(ei_&?Nxmd+mCmI~kd+jATH!@Hj8So?Bj zUo@-tZzARKM~$d2(IyMm;{u?AILjyr+KiHh5n%^7|6RJP}CO|{zQ3Uo?Tp_%VFiO~@!pL{?N>oa z4}9kDK(J$|OyNH2Jb&HEM`QEQt9wF!kjg{bwt4VX5Wt=%u)+ewu^=#D<%@(14sHOj z$L(!U(3E>N^nFMULG05!%(<*+x!C=4UH;h7wv+T}`FtePT$2>s>4&XWgOGEQZ?x<2 zw0L}z9V7zl_^#XTJL-AZ(dBy>;|4?eZzQ2sR%5`TQ3me8p7;)^0& zuyGn0=?aOalLf_a8P;o@$lssEVUX-=ptxb4-J)QQRZ{VaHPUR-Dpyi)*APCMLW92b z`hh20Af2Z__cNqpCVV%$`eMS&2#&g+A=~q|MJTEH^#)6Q-_`Hq817zVk>~vMp$T!Z z6BOht2j}xx=7hZE-#g_K%+Seu^S~Q&S9OmQGT1`|KS#D_@}V6T2qM(}WUb|p>kP*- z+%35Wk;+tP78t>apE-q}*Fn#e0Ui$T=6_~n2xeymHsrV*APM}fx4k2f2^MeGBKrg) z`UE2TIwJZyBKy3-fJ>H2YzpoUlfS!BT(aPOe~{lxrOmp)O!&jOCf9i}*%~|af&>#D zZ7^nfzzF=CKeM4gZfws=rJmpyz-bhbshu`~3rA0j_!h_et;+scQr;#Rq9R(KT!avA<@8#(xXk)Ff%$vd6Z@VlF9KcwN^O9Rz z#yk=ELyxCB#$(0rx7QoG7Y5}cun1RY)Kze4G}Gy;}W`-mF`zsCaj=C zJ%Sd0T{J){Ly*tw{|F6^(&7vbUZY_g6gKRnU30F>BdIX39gcRx%RZCX?AsDC6*uEh zm_&gUuk_~~t(7osa7S{sUJx@t|0Bqa{%u7ucI-MkX$F$7**%QwF;KN>>nJ=Ky&@8_ z?}zgS`DUNJ*QA(DK1#$`uWyN?`kFp7^?pEU6ke!IE9{Ze$0Tb2mt!ex8aZ^vUlDp$ z4f#sCr)GrcDb~92Ap-j0-5I1u%pAi~U-mHFb_uxbU|v*j>bEMqU*kH4ot7R5?y1CT zxE(V(hUalKj3YT}hS{}BG59!yEy{fsp3z?8j7PDlBZB=yydQwS%T%q# z$PXkefu6x>Qe&w?zLf6_UgcQ$Zp`$Q7^nDnFcgCLk+v~I@JlzjcxNX<2Dd-Mrg)KG>zVJeOw#Scms>HC$ z>dbeID}wuYzFMh#&5zGep35pMhD)avyXSysPt>5IgfGq7l-pC zT8%IW3*Zd+L1C-Z|XD^?u<*_b=XD+3^i7Kt0o_#{;);4oD!Mn{P9_?nPrG@yhE|_QR z)f!caMoRL)(R6!vig?VrbLH`>gIWc|ic(38U8UK0#3tF5WhIdOb)M;ofG?(wTl8&{ ze>-xIwob4d(><^crpf)&ljVnUz54{;V(3s}@3Li^YOW8baTDK6B$@qZeNo1Fa1-Ud z&5KJ&nXeCxR8%gB4z^~lGmp1B9Nmwf==eox07CbP?&6fcU*Yhc7t=|mT(MI}Cs}*_ z%@BqX=81(*OASibeHLcRN{7%5TOiyx_X4CZz^QRqI|HCA6H?D-)#2Y)SB9^okm|2Ds%FT@%%!JXVv76N{R0~1k!ZtAkdp$)t#RO93ckv! zRL9WNkiOaY`~q1J{kUK2*-T9O%#yA{*{o{@1@OyhP`aq=wNCK`?;w2dfx&%n5U1h- zg`BEGCHXH)!4@&MenfH&jnOyw&=$lDAc`|G{KOwmdcg zQ+CrhEnZq`PU&kcd@m;K{|v?euR>lydQ!}Nz;vIx`8~q$dib1oac#LmHHI?(cWUr? z@dz24_~abkNDju2h0}Q*JLL#*(<;*7!B?Gg2$n~KCEU_O5F{8F2;>Rwqiti0rHR$u zSae&gLdyiarA;oP$FiDG)3>m^x>V}8bF^r7{pLia;lx%Z8W~q!H!NZ$E6N5%j)q}c z#El_3NGcf(PDu?D9Ukkig2BlZFDa*~5^77N^pXHL7wY3kSO2e&9AS+vYy_s@i-A{#qj889go&b|27l4qz z@^kLNm4Zv#6K7;DXr@>KL;P5_CkYJ)<1h@cnM$5yZ5e6!rDHT#|Ax^YgT>Cx2dOow z)wk`v_402V4Npwquv&0bu_zkW@R(40x$>9SD5M7jEov)HFQ(x2pZ6VpFy;H+-S?d) zuX076B8AYoydVR{JF;nWX}CxkC~CODz+- z;(=a6Yg#BpGpX9={v(dBD9s0E+DWcZ8@5GwsUk&bVaf(C9J7jvuCn$NbUOJb7dF^W?8herN>N}gIU$kH9(fK8_-uL zE;RiGpbYoCc6Joih|XfqfxP|tz=DK}n*%di)pS#Z<6+s728walY{LE>`D44Nu?RV( z6MvPlr$NW%Mb*<^baj@wI;}XKxHOe>NToXXdjVD#)mFGrm8$`6W}?ffegL2k(Nkfh zm!*QTU3+%xIh0~|i4$l=bkn9VoM2!s6|a4NU$2NnoMbz0Z~)9Bzkb=?_dTd!=>9|) zm=*-gX9wZ0JMZ0m3hko`uT-Wf#R;>3VUxv<-Pno@l#Yq&VMQj)LRJYf@gWA?=<4q9 z`@6b#B|5h)qHqqsb-D+II7E6z*BjfrlJdT9ps!S*7s3u|=26{&XeXctP1^6KCG0HVb`E{mCrpX_$PvX@N?I>;4qryih!6w@ovGMyC#nQY z$&5ROq?pUd>z+5O2N8^YT>=BW4sz^!C#ETO6;baOpY&1HAO7ZZ8@c2Q%6Sew0ma^UMSO7>j`Xr+w=l2)sDH8LY92!rF7^0oH}o3ew7e5t*-M zy@07ITfVmfvV{o~M+mtxW!{n_T$O4m`$v5jj{%Tk6KGX396gl6V?EcxgMi)g*pi37XOSxvqtc2()>-JsQ0st8wc9ox5?99*^0sjoxEJ_C~ zZtlkr1|~M80?T|1$#h-%pZu=^tB-6Xt^)&Z-5_0S1G{`a5Ks~(!Hf}_k{0Hi3KYB2 zPjn{oiQY^*xh76%f(6W28U`E4P3@-?3G{^ZOl!W5qp8G{d%}BsCD8 zh82hgAp{F24s~Hkq}h1|1(MqkZK9yfYG49_6Y_MsI|jGi@*_)g;>KU%$}fYj+MSu* zY{HQP!ji}C@>dVn%ky9~8oh&gGqP-yW8aAOM<-kB!p*_$HGj)q1L-}?hnR0*g7sr8 zOCxmWm8VCv?o7CnykEzr5w64Wog;e-sA0N2t}Sqn|iY*2-~@5WiSe0?-Jv2Ev6eHCc$ zWSGFR+x@j;er7svFBUBxomwooF- zl1f{|Mw*b2;8O-#n)J!HkiWEWlGh#ixcNyIf%0H`Yl3u*?+q`kDOGaBU}^IDDw#x2 zVV{9(^L5<#!l{KXenPa;Qowj8E2Pg5 zfEO;ey%gJsymWmkmNE#%=_*2g6+-Ker_-vf#eYqTP81i%q_E9YB3UMRmY$zW8&GlS zCQ|n?+O_LHxCZ%AOQ=?v-P!MG`J?x@XV(g`grt`+e=>&ozdgO6jkd+li66R0Jcn`r z+lTPPLFFTW*Rd#&pjFiL7!M=zD%LbVpxNQ^!Qt`Z2z_92kc57O<>dtXPCAcVOvhs^ z^M9ksd@`diqe6HNKcCU;Xu4QT`(CpC3b_^}JxR%)nD}A)1{KI+=$UAS7WF2Rmlun( zb%L?#OWQuy@*3^vi3uun{{Uz9Q_(0ryz%^fvHYIS&y%bmXUwoFJZ*QTy wFrZhC4hN@vuswe@T-=3cm>4YPR>b{iWh+cp%J zwqV1wVJNnCrybs9sROvS?6h5zn;SHNhoo@ptmsYyEl~8=My-O_L1w4Qqclyw%2C9DiJ0)ATbW-NJbr=NCAU z^+#N0ipkCj3)`^llsn_JU;3tDro-cFNBR|#gFwIy&Hw5nn2q{q{DXrG3AAr3{42ss^k8s-X(3~(1dY{c!0O7qW`+ZidN^&F>Y!!DDa1tfY|TFmU_xl`TJN9| zl3S>ZZUP_LgtDR1hS!=(C>sb>NMF*v5Gng-~0nzM_1Ii#ue;0DRLuY!l!icvN7-5|eEAO z9adbt36~*8n|A#d)gV1;5!DK{Ir|e^e)8S=>|9_hQPKyPzX?P9zaE~zO6uZ|$d9@c zn*F%>?Zfc+Ugb7|m%b=4K`Sre9zKkiSH6bHF68(3ALRSHkFXC+ccaiBaQQI7UT|YE z7k}gN5SPi`Xfn#-u@@Mghd<|#?~SL^ap)z>Uoh7khbJ-FBNIJr&#?kY3_N8`-=e-G z^6X@Kw2UxPeX84glAmKcdZL_g-M_$z{g5?6_HR6WpUhsud>+N!3F2;w(iWah9^H@7 zuh-B`7_e6+4|}J4zdrvsT-1egoH$6#l@W-Azbg|M!vqE}$#eJ#cHRTC)&my-{+qoq diff --git a/CPLD/MAXII/db/RAM2GS.pre_map.hdb b/CPLD/MAXII/db/RAM2GS.pre_map.hdb index 821c5d9615e9969c24ac50d54eddfd0d51812dd5..ded3a086c1f01d5f7e995a06acfa92bc25af8a75 100644 GIT binary patch literal 16376 zcmYkDV{j+W7q6oYHnz2~?c^KVwr$(V# z0|$Yk1c8*flQDs?k-5{4?Lp)JT!?Z0Ur#{BF#pT{OJ8{ZS9Sxw@P^Jb5_WdI4n`1+ z-6`uxY*a^A`fIGi)gBl=&$L;;e$jE^P8}oGE~~YY732++&o49(8Xhizq?G^9Yz9Mc z4;odoOAIVYh*?Nn=x|)L3t`_>Oi0+c`}^Bv@zU|Sa$ULEW_qu0!S+gNQ}Nh$s#LM$ zY{~mc@pn*PNDZ#>YBp{;UGYW2l=S`i2B~jr-{7lQ3iH?!_G#j@^j)ovff{KPwtHHM zb-e1>Lff9hA;1{GORBk4FO|(sbKaHQtCi9i$u9lQGL<4yg0plgJ)YG1#9?mVnl6Hu zT!gbKOIGTEoXuVwSi2};$YWUyCtOOm5B}6QyW#`A9#WH3E59euwG$G=u7&{teb48F zrxwu~x1OIS{1U?)X035(N^mTaPFr$V#ZBv_0pVVMBbiBU$-%koY~Fgrg>cX7H{Ehc zw?6OXmOFRKwN`Zx+KBsJ{(XP4nq!~7D6>Y|T;Vne&!DdniPSu~5)GAHRMF=59jkR$ z6m*ONXHf_74d45{6p%(NbENe#6&Y!tk|b+;wZvw%UGI7x{kAdHO7qz1h+dn%p|EB6 z{&X2J#&zCIbO*RS>GHNdh|4%7ttmB_F_@!xHkm1fUj^XVRSk$(YI3T3-cD&BcjLN; z{~66s$08#+j5CN6O-|*GUoi|4)&Rv6%X>66G*k$gI)eL>%zie=@jB2?<6wKjK|YL^ znPw^xAsy3eb*B{aEmEVaSQ5t9njy8ufrXqCb?!}^H=1+LMq?MJuT_uuodfgLJTlf! zBTy~`j9pMGVkrgy(Nsjc-5yXGa7jFVvf62(LC=s@$xM0q!@B20Yi#Bt&U8EKq1|*_ z3%D+JHs@MDOkXBhc4@t_z&l$qR-Ez}Gsbl^r!x1@H5@H)-)~^oUT!~1#NA%gU%#!J z`YTlOLCi_;3gG=gy{C;$IF*3?oOq-H6!ePAoh#=DciZG{0jS@kOlUpq)?7Lp^e8ZW%vsad5*9_)D%T4f*K*ef9X9X` z3h~{tV#Ez+CcsGb5V%X+-u}>ryxYI8EN{z4t`&3nzNxh|ap5|X;t61Vl*}O~i8jl= z2ivd84d|9L3}|alI|P2m&P^?1^IJRms0b5fH%qQ9o^u|Ne!8FMec3POEPws-8V9{c z#HTqudXa1=osr|4!sO(^dotggI2P>gs%O`|J6`|#B;0n|XhF7&30A;+-YsJZ>ib)k zAtKY&0`qj3m18~HW0R^T`V&5>Y-)00@BEu7nlCxLz(>6;F)iQHyQW)Y47W2huwRO& zqXYN6C(pqaY%!0r#ZC3AZI{&7)lJ`Zf=$yFBZ8s2 zuH-C-x)aydL;aGo*qrek_g$vea{EZ~`2;ol9V;{6A?@49n%u{2g|;Sh_0Mxo*aqa? zK2`RevxVX4zF3**lPx(i-K@AtJ+-_{&WNmomu%0z*{5>@r$fzeatO_}D=aY1#67s( zqv`N$+U}Wq~YvmPGVyqa1U12vRtSatmiM!5^2#n z7B+Wy1?Qe>%Jlz{iQhYwT_&#nC$y<8(k~=DWQ;MLAn^VQadSyqJ_!N;#*BZ8k@SV- zT-l)DU~cU74KB1cQSO(MjXzq=d1^Vyw}$;Ke|DFM;l7^pNImEH zorl3OGzUkjJ#EPZi=-63%xlndzoLP#T*It#oMlzsRG$|#dnDakje{~1{%J1)#;9DyZd~5?p|vQo3dQ zD$R1`fdaIjAI9U{+~+j$sRXB9Jz;Qk&$Zk&ahOO&ybzBnkBO|AuZ{eh7YV%Nce2eG zH)so1qfV(@jLm+EV&V6w7ksM|R51y8Fb%1&fRA&<#f&}7@_ZKJd_RK8@=njI$8qtcsN!8KW}RR;A(WU=Y)HaDWQR-h zSuH?l8cAVBpQ2Y_S3QuV#|S1FD1ku@L~2M6iXQX-6Cz2}4!}l%py|ukrzu4y_&i~z z>72djM@W}dJTnX8<20zupMRG=gydJC1M<^^af&l~Aym>B>^D#_YJ> zl_)VihEdx%LK1%ujC#L&SxaGT5^$^R~i;Dh6FPEiV z4FK1<9ZilkW|ae!59ok83z_QG%v(L<-s)Tuv>2QeiR3FH2!vWoSGt15+C2PJxMzhjVW zE_SUH-L zwvJ$p9BW_YSmV3_2fl+tfY-cS2tGpg<|+-TZX8%7ZGNU(p;`ue$@q&m;M)a zyHhf=%dO;oVR-8`mh(^dhv5QGI*Io8O|3x1UuhWbgJoqDa3%D+iU?y zQLhbdXG_f>Tpfwiq_^E{G<|{53yE%dw=TwugU67Wyu=Bm7;RW?U&)Dckp&f#)~w9U z8Wbo~ER#x0HH@XP)g5ZUKsBIEX_G`SaUmks{cNJUr{I-RMhDzqCdXSGvc}Tq!^Q{p z*(L2RN?=a@c;bn>vRmV<(Ytm5yrHIQZ36w)<@o#OSe1U6qucnM*P)Cl3z8@1x$wg2 zYovlxGx@EGR1gSI$9Td2u1F@lAF&T-gc67cw?9Nf^Z?bM2pSl7@XCx74$+pArLxi9I zzNt9}OnsK{$X}rCxlQ+b$vh2)BY%|M{qhRtVZlAk&C8ot=eTCpj|oyzQ1R&rPKzFE zi?`q|RAw5V+-NgAAdJ3%KAhrYR;;)1H69(L4P@$55B3<1E?rHvPp8(7r`FD=*7m2? zE~nO#jG}@NvIa{rmWx3|%Y4_WHx_%RX$6}(?HFlGa9-RBD~cHyzZxtC&1_ozXD_5d z3tB^7e6o~y_AH1nHm$%4GNSaD*D-8iFec;7^_WH5{b#uYU?Pv?&GodbVVFSo{gUEt z#X>TORKpiCpSor46KkvQPdI}Uxy$gtVQ z&rfC?INg(SY<7tM-_r|etylPCSeXiL))J|}IcdW3&4M3_ekl2&^oQ~vDhbP1t3^y# zP2=Ut^l5w7K*}R)nla|pR?;}BTzWn_WAE#u?8}$U2iy^OkTGeY5 z3SuO!wCr|R#YB=C2#uVf)A`CYXTU0K_>pVceo6P7p)muO6PnFH<3zSuw)ph?ljcOGL(8Yi)7f$VHk3<9r_V4e*~k**&We=e-A`N6mB*BSEI3uSK~iS{xJQ+><{xl zEXFSGsJ_GzDV4;scq>TOV3D%i*eN7bobAd=8&oYn*@J?pINI`?ktZ=>(I&COkWQK> zQ!HA_cmkQpcz*xn&p%xMaBL|fxSerCx*rD-oh7z&xF%2C-RPR2y@d6l3vDV7|3&xU(h7Bd1lIsU*L3(J+Z6$sU{PQ?b?VI{0!_ zIX2+zNY1^qqw9!z*26ahDWv@psa30=X5wt4iN|;&*oifFIIVtpXtWCl&(Vx$U5UzB za~%(oTKcli!lVWkzST3!Rx4-}1&5#4X6s^UJA+MA6G>!dOpfNazsW?r6l1`PnR>$7 z2mZ~V%B&YpT$c8FoxbCpOBMeKPIitsq%v4#CLDzB=$P2|#IAYT-=5T@-id%EBMie& zsI+i`sDX)i{(~~+xb&%3z5b^Nwhjwd%JL<=rvnRE6Ps{Cor3KCwA-7hOGV8lvKB+_ z1t*^D0x|j_tupW!7G^;~2qYv_ezvem_~K@p@)@*pmIKX-B?^%!Rw`Y|LT8a&u1P_n zCAVmzXtra=+2RrfQv{MOKFth5V_1}Q`VK=!W1Ie=OHJnNR*EtV*3@G%7uz~`zvS-t z`RKU(-jRJCxt;aGw{uxjGX4A1=36@I$nB;QW*|!8Ii1j-!M9`c7{Uj z){zSn=)hVpd;1E8Q~v71hbt-8GV0(fV8tBn-5NbyaN9HhZFv&XVn7GZEXF#@a9{Gjv1Gk~lMq-?0A zf+PKTGCL0;l(-Plw$_Kg15xN6{PARd>xT zIkn)syK-O{Bj;u`gt9N=*U9%E*0f}S?`tXnjYvSDk(n3bM;o2G$@@VUZ6HpuVXkP- z;*4pQjj7gFOw#0dZh5HmdLqlRcQX#-gGoZ(YidFYWB7^@C&<@KccnD;_=?w2E*a$& z!vnr9iaYd&!hi_xnbw=`yT+W9SDj9ZwO7S-ySet-luPT8^mrqU`6DUkW7a&c(D!4JUs}%J{<|Cf zfVG_XUK%3nMeK{wBe$*m1w99ceRY6NAF@)VUlF#VwkxZpvBcp=i}=wzaiVeG>%Ipf zXPAdDu1YLb& zf<`X8ZhB1TAvu(}^g*Sx``%Z>gsl6#liL)`w2H=r*$)+7bAy0{Yf^@wsF_Sc|DaEa z4&n59m3L6mDPzR(bUuJ7?eG2J$pM`K6EYcNry-Q`pil7sl0CrC6d zVk}Lg%(gU zQM`05Dl=}T7{}q3nAt!Xq>Lj?RDtrCW8p7~Ljse4o;2k~7L!sg^eT$EQYx~I)-t9c z;O{BOu1yIj_erIiy~I6PnG7CPR_)#&9m*c$PAXbXuw{x>qQs#~9jobIyE-pL0gUHe z0gU&idR*wnfO-4htaDQ9n7Q|v?l>HE-Z}jufan>jnos{e>9S1S`<;0^=5WJ=j?fW4 zcxwTBT`25r0+!SHhG+kfW2*yM$>V}-##6&Rw_M}2K#h05`_$x7t@{KSovU*XJg|qZ zp>s}YT~I@}O7;2sgJr=f^Vs2eE{c%p&u@s6X#pRoyIQr*gQP>A9Z=6y8R65)+)v2Y zfBy<>Nv2e~;6BO?S#Q?JJ}2FbHYIMXM5C>?dG#&H5~v2Ub~vEie|n~8=NpGAE~Itr z+FCk{;qkb6QEvIu{vr0GB>HILsHkJ~+~}@DZ=q=aZs9cUj;UgIUeLADm6GTbf^TpK zK*PAAXVc?#+&uW$&hQ9(FmrP4aG2ja4rsTM@tZ^p#1P)?g6?o}tvN?+;xGAkH$s8C z+UWg=FvhgE+RacZstvNM+ldsOskdj>ch^#%kur3faN?(3>Fm0?v!+|RhrD%+a3{TB z+~{eyJq%yqrUaYUDU&7p98=m_!*9LaW;h)joSOrQCdeUJ?+gf)=f|qEZEpIS#_r~F z&w0M-C7Ml89?(zk^7c27JiQ2FtUf3bHEEdq8uCAH6!iI!XJ<*E*dFh1o~+huYmIHT z&eLbgnt4CBj&;FyYIjnx`IE%8=ih)v7Q3gN?#X@m_%jhHR=_OM zOvbbw{BekH_MInS{zLor>v}5i5C(SqCc(yGyhS|hztl;1wQEuj`ZXLvmgILihXUUl zn4hUlT7Sn1`1Y%N6i?_!ccuE_{dWo35Bgr2VkK*M0rJ>XQD`A#L!{*eMW+^Th*Fa0 z!=Xm%#ioIJn6!U40_&d?VQ-FGdaq^t(J$@Z!t68%=N%BlByCyaiaBoGdeqQgg9A{c zYru)NZhX=a=I^^o6+RG49j(iM!bKziq7%`YpdPEH0qDCCppbE|<8=iSUrJOu8> z9k5(LYaR@kWJm;(=V!1#*W1PU+f|*!rRy?_o$Gm>pmR|&)Q{c2XtM4@zCd%mOglN{ zGpVJkvnZ2?#s_Q9+?=gUD%g3{Z4`>84?Yr)x^2^8`+zqR=&s=Nz0qEj$A zF93Y?_z`$Q$Wn7(>MZ>ZV-oDr$)~!E*zst6+m1|qPI|4|_;22PpJe0sZ&Y8deD0{> zOdl93i2X&gvrI*%#vGHT@Xi7wzI>3VYVhL_*dVvdF7SQ@H5is<>YyFLvxXdPNIuYi zrooPFy)|~MFn3Xi<{NM&Ab;j7=)Hzuzs${8drj|qmyZK;^h4&YnE_W#oVkTXvYO_# z9@!ZR^DlsH{5Etsothnbs%WJWdFEo~ayk&aP2Cg9sY_N6eyM&Pmq=#bf<+3cA#!X*4b|>h z-Dmt)!R-V1&Nciu6WSMaQJmyODOFW_(OH z`yegG&m?X8wU&KUj*nLS1y)#fL}K?>_He^lv&6by}bL9)VA`WI+|+v9mPyngOH z*+#*}0;!bu=!X7N3LTor;X!%7Ie5b)2j^f}JWNFmGbi9E-fBs5ZyS*ePIF_C6TNcz zH^$x3QmWgArmC^orA77HJ&!V-dLv!fE=Y~l?P#&xB6L$HyYcRz6d(z7lP)DE4HbN- zBD%?N)GypS+w&UUhm5b8YvA-e&7cgKp?N%^s)-Gb5^^J36QdNiyFosWsS?Mp8QzBw zon83PA8UNzLEXG|)4{QQVN=m?^Mtid_nvRC8eIY(2r)nyk1)l^m0GSxJDPR>pZYGq4*!{Q7Iar<21J(~@|8B&XI`!dykU5@$0{L7X< z*OR;i=X+iK13;Cpj)q^RG)%fZoip3qCAAswrilxR!kk15d6dS?6F5)uGl6{RMSFl< zjqTeg&y4M;twALmH0^O8w01IJ@8J02xDXW6ujACw#RL!wPsb~MQex+*Q%g%LFGtop z)*u(Vp*Nu7N1L`$plpBMO@&@VT_4sj@$dcpSL8bOv^B$WK}yqE zBA9&&oAcLL*7CG7D;|K*A}qc%_s&U@b*%sv23$~7eG&W6b>kJijM4b;B_j@>(&@D; zB&lm0=hNsRkrrjcmg(U++B*PAX6k;t#q-kI{{$SvL7+w2fZWXplP*}~ra8bB0Y8jv z+ZeR8F0iHSrEA8s-3>LkZm^~9#jbc~|1Q@-bD}-i?1Qs!N3n(WSheRVc%DN#xZd}l zF-B?!JRavT+Ow;_dbK~K1eZi5oGBPUV0sm!dt@GP^a__BanfZ+=?OkC2l+@;cRA>& z;*8kMm}&jOs7AiUT9`Q)GCzr^&|xjs8m^0~;aiAei>)xVCwLwczh^BtrtIar(kLo< z+eCOs>7(58!Y&ft3`?PU`>8*1FGUoIvmWb!+D(a5s}&xyr>Y4@GPT$LdZb3-)AQ$x zpPmc0eCFB9BLbTI%SYm!(6ennat4<(yBedW_a#qxo$yJhrWIog7Y{Uo&(3@119kbS zc)bIU9jN^E2GT7P!6w7<%JD(+oUJ37zwItUx@FQ~>7KjLx%H-%W;ZK+NTXZ6v4f;T zF+ojsrC_-EudBuHbEuLUWQ{&97XL;cz@__tW?gN9<2l<%TcxArkJ;PM|6O!;4k0ta zS)iP(nw724b_^o)^)?r3ZCcKR<;_$(_Yqj5)q9F$$v%l%VoP=U$k5wKf(^Db%Fm2*p(20#qqA3jnVEyH0vfWS2K%j8F-qnt!4G8{TKX>XTrPqATL& zYsSH+rGNsbJ7O7g*L(NI7xAy-+MexcV@hTBCeV@IA};UYV!btcQa47V|K>;B^;6wz zXM&5&Y@J}pJrSw@>Pz13Q~s;LPte#+{mC_NTHIu#{PAdMk$Oz5$S=82oD--3*G| z2R}%5j)Tng-Lx#U_GY2N6cdspTDyu>C?QO;!NK@=VTV=5-e`{ zQaup$qlXlyMwN`prIRWR2TZ}HmXEuQMYp#Sc8d3cE^+q9cS;Qk<tQwwl^+nc0YcX?veL^E{68V%++bi(%&L`^e{tO3 zoOtOIm{?~zRGwftT_MX7CA^TV%PP!5w8-+fLQJ^K_h+C^`YTX+abZ~MQVjpO)vDeL_&0M9%~VeKuh+p z+?u?b&laNjF_2p%QA0yzMu3sfD`FI<_UN~61>s*w`Yi|2!*};rvr7lYdr=?6#@m0ALckZ zoo1}AO!2yNXpIe$L2AzV7O1Ihih2!Y@*~*_B9j>=0+bB%3VAe{8>S2H-~PiW3L;JN zex!GK!o+P6dZz+&j7(Yu>-)Cxhh`;fgi9I>w{ZIeOm@EX{DATwf*kN}+2pauQz#tm znl|W|V{8OVEvTT97vl>%m7RU&OVeLZ<$Bu7|;`uw3aZopDaLs;)i|y@lw@Y^j^blK*5mQ`v>A>m5#}6Tj)H{`m z4gaxV7Y|eIbZ6F&ms<^*TodR8!c}laY6D}w3}c<)M^mKi+jLq7yTFRuYW$)zTX7z{N*;u>BPpd837*`K-(Ehh!{GL&V35qEeht{yC#xQ2AxQ1&Z z1`=ka=2{{e>hU(JAhQ<@wVE0rX8x1o69eF2B|tK+Q;WC>#fn1`leR$0`~cj z#D3SNenXLStKpHzJt+u@FNrAA+!fN3$fZ@%%g8+|WOosJ4+q=msH3}k?#SO$?$7-p zC?V4)3sVQm^OW%RLFzE(Dlthz_U0idSqIHwJt$tBTCRPHwK1OX{VgDyQ1Wj9?&cM1 zA43x3WiKgk`zoVB2&P=lm+o#(+PK?3`$<|&A$JDnzvB1%cFO3d$gK<<+Bj8spr66* z{MlR1WKe=;3FFQ$FNN&G*jT(x?zKtsTP2QJh>i5aq1C{3>+SC>3v~r#YoRruixH}R zH$-ffa!D++b;RjDiELd(edunDbU%vt3}U;7u-#q%$d4jhr%@fyV*LbjghSjkA6-Y4 z59eDWwr)h%Pqru9o>ZU3Ye_KQ)uk)8`RP%_f&c(%t}=%WQ1`3xXcYrCm{?3`Xe!`XY_OqGI%A~Nh3bn1^J0F zNUvcNM8!OhC3HZ_T^8E8>rv-wb-{E5Bk1@vtsF>x19|7{)DsQdeEZ-Z6yl6&BaA> zqMe2Ga3urP1{VOgFSp~FRiE?+ulk?JG>FpzqbxS8FAPOyR@r_FJSU!)N1E)Pf9oF# z0n{bp@5o~NufpbTYukmqmty@@*MBLlPeUoLFGCZbo%8wGoCXqk&wt9ULSqn|e-1^& zZn=rQG2}knD`af$M0~(TcHa8joUyJqWM!pb$9E~l%>^F|5O!Dhc%MUjHt^rjzh-2C zJWxuCN)7HuV+>k@MF(m?G?4-Gq~68j=3VcSzKQ@S@-OcE!)l=O5r*4j8K}4OA2NPW zDgpDx3dr7yOg&@AL#32iE+aFXFy=1#j-+3TJpO6&g3oyxM? z1UG-V$EeW-nQ#oYei7`xu)fCqlIT8z@0?%XYX1p^d$#BEEs5^ks196trw(^U3!h>$ z@1lk(_OR>gOl~G9fT09e@+VTCewwJ)_Zar8CBZEjeq!i)rU`9#^cmFVF}(I)Xz*+e z_`49iEBMYK{5Mv?*$KiYC2QGgT z?U#WVsvB*fx7V{xJ`a%v=PikE46zSXk=Q-yg?Dqn8#2(U-~glfms@u5_k8Bdx#Qk8 zD0jPsvdQ>%hT{FZ-}A*8cH-=6wbyrA_uMmf($KZNL&Iziqc@P)hr6~$Cj-P&U=JQ# zXF`4FrZ&%Dm_{w*(&pwHq<=%)VFSh|!okgBLzPK*|AP%+hL$DG5$xv>yB?W zypJQ`W%#a_7ml5-2%OhQzDfpGc0$FXw;!Ty+&Fvb(-)YcVm{_WOiE4$)Ta;qC8euJ z79^Cn+TTMG?n3vt=Sv#yqQpUuHw*L~Q|}&!nKuLZyEXGg({Ya%zT-IW8rtuTrn2j# z`hnH=B;_Ly_9q2?On0<_h`pNh>3cyXcnwNB7+jchvp2zs(STJIElXkq6tsi0B?hET z-_ThzcJyy!`j)IEdN)2ie@T4z;(Ng7dO_>Q*^Za;~975D~TKZblI zGCpTx;*Zch2CqjpMgr%XNo&#B|Sfe$7ODktxpjeuDtVtes2HUW=XMsqNl!bsF;B(OM#F<7_sW zO4io7uV-6x9rLk}T0<7dk^;osnVYT_OP(q?8(nkNs3$AZ($Z;No->s$PR~x0Ch9Ut zZ&3C25Zqb1kmV{=zU2(Gs)DS+{lJq%N=!wD&h}qog=;yRO~;@1Mh?;yYOz}7_y5>I z|JCO~Vuw~wRjBO~KK5UC^x)zpa-wIhu!9Q6G=aJ;hpZm^*HBb%SIYaq$mia&;V}A( z%k{F2Tv+c+z_#@WY$IA64 z+f^F9I0K=f%gWggI6HgpJNZMF0%Soq9J?|`o+t?8;y-S+$cQ8-CAs@4hQ1cs&hgvo zrID&Hy*alm&KIhpXO`mykF{YAcE#jBe$p=z7+_9JVlYjE0>V`rh$w3liXRnlY?*}W z5#B8bX!QAeGezkJ*^JeaPgz{pt-HV--9FfP{{EiR;qG#@iGW0-0CWzbvXA5Q#6x$I zqI+1=I;D17u~No`^Ow4lB(X|CqF$Fy6P7rjgPw(v zd!CU*LxRbTprBXatki{^9fWQ3UF<$-JHYH(Reo4i<26jQD}tGoDLiL(Xn2-VK(tWI zoCi`w!ce`Kt5#5>?RhQldMxNmgZ5$BF|QlAfn;Zm<>Sli=K47Bn*jeKTS1+PNydd1v&Z_F43FDd?q`s8s0=hs>*|F&y)aG*_F1ECX=!c3v_J9|X*PZGyh;C;5k43-Z zu-0XuYhKw;eZanM2E30u?YeFXw6`$r!}&eShs3Yp71Y&p7zw`3P>rO%lSWqY;#` z>eMf?*_m%>oe)&j2YPpTRZ4!dN^xrzn5Zf!Qcs~uS%UPlu(5tOi{tisEbQBG$2@0y z?@`tZLXJyLqTK;5fp?vCc=6W*7N0)ZoR_;Vu$MTAIJjjQ4=0(z1sUT|} zkgL?})66UxviVQxd63_uJL?Rda?!{BEl=wN{#al;5&9F+^x^Yuz(el6UhX9k`AsM@ zIphSb<>vIl%--WE?ZPbYy`Ha~+GXDAI}={V?P}>_DWb_2*epb`f_c9?RlC)0)A}{h zmjeGov(@U`1#q}M3GuB1c=>$Y*`9{@_7Bjk@+}_RhygkV+wcjH7W{SvtbY&Ve#K@V z2@QPr!FHkCZ}fw|*cNQU6+DKby!86DODUVbl#o9rM@t5NS1H)G2d4z{5|e#BC%)E> zFXwv(v`8rWn#nxMDxdLmK0Ec?nnJxZ@8{$tdNzHg{k+1=g8Ncl(vmk*;22(rZ5{&* z=V6dBGSMN*!!xP%2qa1R8$2d4_Nmz~L1G^SN@dR8(Jx31oPF7`=%w(u9GHgwOk{c5 z9qp@|K;Pt!UB(k|U6|pt9m}lr>|g*-&RxcRFYghYuF1`Y?8XlKUcf9Ac*|~xhfp=R zFgZDQEQoG+tbJ%Y^NWKXMb{?-0M^?Ja7cC#$V-R+@yl@C6ri;2hxY=G_7nRh7yNp42JbC_Uk?WLrK|$$F?p$g!gR1711dTZt1XJ zIPF^8oD+Y_B#qZ>Vw$nuiwTTI)%Z*9;Ff&*e%$+A#AgkrZCStjQLn>bLM(Ulk`NGUXdcF?xEs-Y`=_HEJah{-Z(*E1 zTWL`#*?*1D(y7^gIOxlL;=K8+z_shWsw(T_VrCpmzr|N(p+K&2M5(2jZ45IDkS#75 zFL+E-W}%}0;;K~&@t7?4{mcg+>@;F>JY6z!_99Xv6l%O*^o#-wJjgC?VrRo_Zsgvv zp=)K)=|Z2i4E~W}rKH*;1NR$x6XRUm#v!Dq>La=pF%-chjWn=1|9?Asv4fP z1cvPGF`=UUZXhT2-_p!O$<(s0{{7YXA{Wu239Ir7RyH#T7RN|F`3Dvv%C-XU<&yU_ zN}zw*fdB$wj|V5E(ur|8CZri)8gs-`cvRFF)-(~3{7Li>wvha}Un^rK9=T4Y&t`@4 z9Ebcx&-Dt9^93TSA1saoH5r@9Bt`Z%=mRE!ql+ZU5Hm!gVs*5?0hN!9qv@G*65LaR zDiFLn=lN@(OUJc=$aEVCk3%F)Iz8i80;!g3$MT=b9Lg*8<0 zN>wkwy>aZIG7nk?8>F-*V2p*y1Sf^b(=*W|d%>Gb|40#A-VzEAzNo)( z13j_U40(xn-*ijq7IHtPr`vAtKme|Y4&07sS#&W7TOLb-!@s(RijAo+y+3OaqcgS~ zHuDhsrfofX^>$4ly{YYl^6a*jx8AS%Dh0+7E-{AD8jxPC|4BJ)fR-J-&~wN@ls6Hz zxX;i*^8Z?WT%`&R>MPl|xD6i;HS_BjvnFu5zvli*G$sIr7;qrC1{%;LHH(MB3>XpW3IV&s5Pq-C#mzH= zhh9Sx_7s|d1HJsMW{3P)FvnpA&UJtszzU7!yK#-je=hI!{Cn-UaJ%e`j8en~D0j2mj3>Y)CjSw7Z8O}ZEO)cWtORNeH+NFtIyQF`4h!NnGDrg%T#zxg})uR;e7`G z7;5b?+*W3$3iOip<`RjyYtIewK%3ai3*teAA6rn0q$H0JLA@8{pqU>`+OQ2ze@xYq z;z)sHO@5+M?>KWaDYvs`_o~b zup`*(XV19FGgYhWapL=a>INRkb9SbK`86YRK-iad{sACUk+$F=u6TuyHbv1f_LJa4 z=1#@KlEJ00{)Kpmk)DS*t!g;hw6gpYp zyk8$>WzjkPMNPn|+FO+M9BE)HhlnE7#h705EYA6UEUbNBqkUf;J7M0EPuz}9dE{R? zCjZZ=oG`t;bpgyzeYEt+5{T%?+<6}ClHn;hZWJAdSsFiD{I;fI_dP!j@~6CqKOwRp(V0p-*2qyA`_24jAaW7E{n z{dpmjEBwZvwV(t48Zxq59&-FXirqfjKwSmIUGsD#y8hbaG$$1--9;_b6Hg*)1x=bj z5Wf)TdFQ(n?JEY`E!v{@4^J{ug(kYJ* z-7bfM1{}Q@e^}8V28HQ+um}nLCB^HK<-SNdxfr+^aV$`3K1^Tm-w-FG<8DU3{1oyc z7Fgd0%8Z?b5-`Bqr;8C0>2Ke^H_x|+hQAZ`>_-0FBP5!o!(&7vP;X~sh|M|JM9?x# z30ZcBDwSbh_37nd;2@1&#fy^E`WB7J5x!;rWB;#P-Nzahbu4RFXrBO@XFd=bO~Vr!UtZ-xFus(YuKU8>uQyz&D9mpHqW)=6;wSnYYfBFt|$*|O)b@GBuxkp&ds{Vf`Zee3UdTD zzxdJW1+m=NvkzzXFRrS=8iZ1DO11)^QT^+_Sh;C397#PFn#Wd$}UIwqv+3!Ud86awIRKJ392dUBFbT_6mqNok0K|4Q>MzG=#sdjiJ z7M%ox?&xX6L5JKdIrP7Oe{Yc(P)o_&4g72$QXIZAg6F7{#LcEu{oD{cZVTW6T_``N z{C&iAVgO-1R0B{%A#-~lK4;YPmI}mHH3k2 z1t!6sAR)GX9QgawfG4(s({1sGjn?!OaMkhCaK8Y9emjmzK6dE2+4F$%K_ujCCc!xh zm5C@yHz6hi7bV4z$lTjZ2C5;X$fU3`IQvn}k;>CS*eBlZkqUrk~G%MlAx0~-4!WN3>TKmos8~M1c6rG0eGu;q$3;mZ#{PRW*ej? z77-gHRE`bVFHPF-3_5D0)3Yui7m!n;>y*v57!GM!+_U0z!u3TO;0=D6@Xt4kZx&J3 zU?_hy+vehYY{s%&w3&HT{=Ozm$8YgFylCw{wAt0-NNr7hO7p_Kk+aijVb2>70Pw#e zkj@c>fZuHCVr=Zi@STyR)T8|E(u^ph@RJeQ*f`wjVcV+1*gD9c+D7m!9Kz6N3c;mZ zewz=)#mse>mye2%ncn+J5Ex7qj<=cfV4wvSR8u&`nS`!yrBJZQDe=KYveLjFzeGKF z@DN198i8CIdSe?9jxqDS;5h0}NwMc5(ZElQIX*Vj_{5MOV>@7!@fQS%(L3qVJR#ALE#U1^@s6 literal 16802 zcmYhCb95)Y`}b>OYuoLXTidp6+s4+mZF_6mw#`p%wpo@jIF(E4(10e$kJrff>69Xd$ zp^_w_w1u+?p@^}C^UtvnUH@}2!S#QhfJ)*17ylO)2>j1>2fpxu&C*eEd6to!Q!K`0 zo+Ra_UXd^j039QhM%L97R#sjtD{I^@L`T!IvXMeV zLyMOy&zp~6Rnb&<^(C;em@u;t5s`WO&h>g~JI`vES$n^5LV=q6no94QSwHVtUbm|4 zn&F*!Ulh#0VYD8>Zaxt{i-dkJa#H%BW*gHxIwA(GEl!HNrESYA}3T%a{%$w@386%yD?IiT(7Wi*nJv0#IBAD8F|m| zj;|it7Qc}YEpkV^NWnv~jn3Lxp!Z)lcv6uj;T&dx`8Q;#z*%kD&X& zwQfD`a6%|qc4y8tnV{m5UHvmxY^E=2p~`ihwasLR#y1RlUNNb4N}sFSzDRB-o=6X2 zdp`y+g)u#iT8e>QLhrS=-1fR=DE1slNmkxWQQh3|r>U8yx|v4B(aj6HxnrgBD8R?y z=|g8UC-OdWAgZa4tJR`zw z1bw12e@aEk$MxGBy2bp+)ak2KMKH2f$W3tJZ{|yt1yUD`=RKItI3yVAHKbs2Z@<{a zy4^B^Ov6Fw_>-W}HHDZ)tcB2NdIGD%F4adaIeHzm$XFArDCuuStOv`r$K^i~N)8eq zE3Eg8e70o(imoL`5i8_su4^~c_-CpnI@6xxCU{O3G!~Y624jWpg^iRtOB=^Ycw6&z z7M)cK28pMKCfPN*bJCBJ5KblMjJ3ZlP+|4%olJN7hb0cLQCQ=;;$K6|em~w_8{|56 z&%p3G96D}1FYH{TI;+fNJ?8jIlSPCYX&2|=gQ?V>r9nPYo}LMDd${nY$%^R@9CYy( z#`=a%-!Bj?h^~4OzJ=LBdB@Ggp79eTIQ+eUv-S=cM|@>4;S;X$|furEfbVFve z+lpgisNt!dDmk7>hUcC;i>M14iH&I-T6pd<-t8r$`xp!;)x{-dn(bf()427UK+S#L zj~2_m#Y$wmHQ-jCaNNw-UioGJ++wfFo>6av#-;y)UkiBP?aICqy5qmvY{n9H(>@t{ zg3 z@5c28*?8;;-)gBodj~@$eCM0M(Y_tw?}V*;+Jz+ec#t;C&ipbxw;T>+t9X>7gne2~ z%j7Zd!R3f4^pqidd`?a>nY>-;jqpqu%nWOs%YACEDrG+C@ee%GT+4+w7F*+8GtUZn z_rKhNay@!PMugfFXA;9t{ARB!F1eTa($~M#AKz;=56zyI4E^dcGDmU-oJl=l06Rwq2 zs&Kc2bKo-xNisPH{xYtC$pCtOU?aXkvZTINazsJbj{!tWk59&q+4TYW2UsMXr74{wMa z8>1^W0lWKTjIZ9mbSEm+XbXXm&F8~eZYL(7wqaFo!>aT4g z_ZiWMT4*@c2}VW@@H2glBciF%Q;?CN_gAoGZ~z8tNBn*6k)mVDAj4Bkoa&RNbmk8d zZ0^`1)nWy+ZD3wk85#p7M$1raf; zZ4SZYW|5h6z@--9f^_J0fbALxo9=5U`c9g=6cc!Szm(8N$AK1dV&d;&QI2W<0LINfc0OJUNX#~I+f<_`jyc-@? z+|gx+TQKK)30(G8A;1~}FW3}t36z-M0V*Bxg}{Kt$=z#wdix_x{0O{=KSFjkk2X~$ zuiC-##1biSI9x(}LK@P`)k;?gp+Z9tszzIMLi#+vcY}uJndu zTcI4v7(`0EQ4%!$&1dYxRDTKmmePB5#rpM6%v(5Q^%)6^ct^}Q%!?qN=*&krB<(+8 z`$us55!SJqo4!mRn9^qWNf|JW+jUTqb$cIh1{7U;0x*e1Yd|>gtw7IdEdNSW1{9Z& zvH}g9R|Ds)jMrjnq+&5zN8gZ#?~0$$n#|m8N#~xju9fg$KeJ7;%D~LO^Y-t0!xNv| z)8=Nnw5H5VacWPTnBvtOIW-`x+_i=5QK!~DTz&NNTl8~MVuxu$fEjuD+82K6-zYEs z!#pZ4gEzJop>?9Mq^f?YXUCr~$Q#F%5otO&d1y}?6Kpz+Et$L@&j(2AG#rJimg$~Q z*d4oF`X>98@x7}C(gJ^FicO}Bu3_IQAZz?tUHT_V0mArHGOP-&Fl?;isW;t zwo$ydN5xjpGF$96{1N|6UGJOF1*Dh#_LPWnZo7)ZlOdD72nGaCY0*DCefW(<{c-Z< zU=-&R#eXTqaP9V#n#6)BabDoabiMABo=ZO`ogc>1!ZAbtZ39L^SCr=5!1716IzPDq zc7e-GhM1$I`FhjZu+X$_YFaLn-2=bP$l(1Ic45O>9mDmq?)FU~uF2+YzO9Xu54hFh z{AmiKIdkwnXPV3jw&9Vo&i3T;0Oghy{a)$F^Ai2)*nA<7Ej#y&ez(&Z?n^AwXGqx3 z!`gEG2F#Hp z>96q@U#L(HGHKuxi(YFIRWjfdu@Nya)v>rX?mV6-8aByp=CI1XxLLWvWJU4D-;hTD zcF+hIlh0jYLPsoD0_L!&3i0*S)Yd0UZ{ek-5=+jFN@$|Ps7$U*o)F>E;!$m zCsyHu`*!H3B}spCy0DakJq+j;DjKvFtM(*=fcrdtNF7IxNwYur=vH}^36nIC@}jHJ zAt@73=PO}FTvi+O7VAP>mJs>lkZ^d(Pv$`j^QLwU#a?q8Cq$`gRM&Hafa2&Td!=h& zSJ+cYFXmL4E-a?D&f-XAkWPmVizynkaE>X%1lZZXO(Qu?8#zrAIZX>WO#?YiTRBZK z6Oy6j5)sq;%284}q?JV<<32;m6czLG3+6?Poq3%4_|MST!& zU3khpXO~48*4Lm!xp4Z*S{TmG^!m)y>5jsG=?lcnxqEt>{WoC%`ZAO@=1AoYXX4@y6%{h$S^+NIYt%``*m zul%VUpdvb}6=m`J0+|ywS>WN@w$}sPcO@@cg}OYjgjo%G*^M^-jK2`9rH4tO&e-gr z6SPJ5Un7xz6D+n|h0d&dm8-x({W^H`h$RLyekHFtJ0^gEyoP|mGBFkvUoDYwtrTh4 zI93!h@e|8H`pGniaV_;nkQ2q6@--&)m3=__V=rvLklSil8}SlImj z;m6*5|KT-4Y3I4VjS4VIl6@#+=zc-zU{J-mV8+b#!~47$bH@)}KXA>PExs!p;NL^t zk)4eol2wo}z1Q7lrQZE^;_xoWdh6ax)kmeMjoz)7&gP#-%`_vi-9p%4s*y5OcCNW{ z=&?;)H>=6$|2IFGuJ3y(Zc@f1`A?El^{v!#?g~(C6A{@KlQ=GQ6wQL7M>yy17m5tI zK84&?(Qh+-_OV&RWUHcyGixxlX0dOqhY+RSm}66sydG`y43)cX zMQ$Q&Z%DTDOi`);WR(EBU$A$8@szyG`18?p-Z55Do?=Vf45c2e2nN1p2pAbSn@cD+@i;fDhc8 zl*-}K6!#runMr(Myzqr2rf8p4Oz&Y{xb}_#U(s`hY2~cB-R*x&VQtfTGMB?xQv@%n zc$=u1>~iG?8b4Pn#;g%tn1*y5occ(jxZSvJz;cZ9Q<_O3{xNd%wHig6{UxX4lM~7X zOG0^5j!5Z9;DLid?i}}KPGuHV0`+l|-Qlx=hz^6%zj%K_LGW4i_|ZwXPNnnL21sH@KP5}Br-HRTR<{8=9)+taZI2m zCpXhS7TuO}-qH9`VmpaM9w&(1NpL7ct+(tcbTY-BDZd})OWQ`2IO54HA(f7^wk3e8 z$8p|3qr_m55AWqOxuRb>b5Ya2+05C|Ri+E^*t%zJMIO*@WYG((^9tINh#* ze${7NA-ljq1r^qT+`SV2Lh&g0D(*rQgpm6v>Z%;%ov;*Q6dw_KQuxBZRamQeM|`!> zL`biYnbTgc81Dh%o0x1v`@BRwESiAt5YUWqEn6aYX-u%ACM`5FYyJ zmX6(&cdjqRVbQ+IZ4W(nO+|ng<1XsV7xi2>rS_z3i?)54@nl+wM^4U1z-bbh4N>g6 z+Q*@R#&JcJd%_(v@A8<;xOl$^z~Uu9T#9j;eTRWDWqcKVWUYVz{XpLV7dOmf*B-Zp z@_A)-x({8F)D}^pZa`(nmX|0Jb!Tg#BAu7)klTc!lBU8rC1%*hI!yOMyNgh(fAHq6&`EWJ~ zC&i|n+5>H@f80|q--~^f%QtcKN|zt>*~BgYrrFe~u}&0R$)M{ws)#YNJsqOouHuW$ z;#|d696MzTyk$xcB6wy=j2vf+PGGCD7-8m75Y zex3{bci1ZYOwuGQF||i1{N`WHrMESsF)+tYDE#D}gnlyV-@bE%%P=iu)k#KAC*{Y~ebHj|JHDukO?&VM1h zmMY~clSMg0$Yt@UvYXxvb*Xz%x+>{?QSDyq#VDgUbge1;>o9!F^CsJC3nxF!txpOk z%{XNTL^Eu;V4ZXR#1e}&f5Wbhjv#rWHSat-9QaPxdfZsBU%v&o@ed9ftk@TRxiWlkLjo;DT`16RD7Cs=%eu2K$l@;2NO)GaJ zd{~jN-mFu6PPrTFu(>z?S2}|F;;};*2QGJ6ft=yevu<$RX_pawuRp9$;0Nw#j&ETU z)Y+@+^2f;xF{HuK#~Arn0ylTO#3Q{c^5lrM4OH7R{;r%) z)@-}uFwfy$zweV{>%RiGzQB73{+$J93Woc*7Zz4kwaa`&`k1qY2;!Nq=Ff11;`>7f zwyn!eP$fKOU8gx6c#mW`A&hu1JJh%%HQ#T4e_|~=0B4lOtDpMCQ zENnHDnAtoZvsiVo*;rg(TAp8J*j%4wY|l4aEUZuQWMLSEhu9n5sgjYQrUVJ|!Hc2_ z=xl6pZLKXW)O*~gG&kv3aV^)ZF)eg7`#8C+IGbsiJ)71IBCp_e3gWExcy4T>SG-Jp zVeIm;B}Y&;PBpu@JUBPYxyd}+hBS5I@$ld+=-}ZsSaEfDZ3xk`Y}Fls6a00aiGBd7 z?lHH83^Ll+1qW$4Y!ucfT`^eQiwFznSyFFznEs-AQui8r3WoLg&5rGBaRd>stGM1a z&0lyHZ&$WJX(0)^_)?pvO$|IABV%YHRbba*k4}RXoN?0Zc{SioN^kH&jN zJO*d`Z$fVEUrx%OX+!!6Tmoft-I#pRtqBI@C^r5%XaPen33LK&6FdTH1C@KF+M;>v zSj}Ug)AvG2qX;5Sb*Cs+YkOl&Vt`71GF4wNw#iXV%__O7V!+g(i;ly{!!fLx zS;PV?>_Tdn{rTpHb$wwbN=0fIbPd1#>t!{#OIpsaVbFU$?2?8*LD1d_5dav2fJy|5 zw3<4bKH4^BX*Vx%#8^RH$)Sf327?}lq&*|o?zG`DuC#Z5L;4U*vZ&xiRN!)&*duHYkxqgNnm#A~jh z(?h?LK0mrS!6VCjB=C{(oE|n^G(r#`La}?=#FOM3Rhhljb@}w@(pp>#3)d$zAxq4D zyD}O2((gR;Nx7Ml#@cWn=(r?xtfLuqX271Jcr8PEYHr(a%q;BVVq6;-gBkOGH~Wk% z2bKo)nl|$T#lPO3N*bmGf`>JbaRZ)MtfueL*it%WJX=u(BguQltI~)@QntWAHBtbH zt~c=P2!LI`9K%y3?0R>)KG)|-3n zQ$6*7bFI5AlLyv@I$7H*q9|z$$=sN`uN*3dy9V=-e5}e zo(#l4*>MnJhQJa%@AmHkuwR@mcikv@BTd;qh1sj)EYP5e$k;N)x3b)k^{ZfgN<<<` z)IlIw;CTniQcgDv>JUC1Nisr^WT==P1NBc!i=LK!PVHX~RV3vCx?$vH4~omj7{}-* zBvvi-0Yjo$l0m;I^4Z#2+!_#V^tQ-Z#vButvD{97=b>h5oPb}^X1j%c@#KB{7Imp& z*UivoQ}`X75=pW&cQ(2x?%>$DnJ1Y$_DVJ8w=;)Bn!kI~zi&LX+b)Kfs`|^9U^o=v zYs>rQ8d&yr?2lx|ogaU(MOo3_^V^HRBCSi)(6CaB^bVwdVxZ9AH;{aUlpXWPt)xuo z7OeS`(Hy9Gfb2To>l8!QKV;cNled$}5Ypfq#LK8zJoPK5&@U+Y=dnAAtB7xSdELBY zIKBXtL4FJO7i)lqhV0#1VD+!N>tBN4!vlAF8T=p7YoNQ7zlSm`10i$=P8o4^pnIU> zO9Ss$!r|?kqwFK%E#~3Kg6b6(FnLWNd$2NGZs1>caqjzOm<9l>*aR+Gc=GcJrPW31 zUA?m9w%&TD2wU)!^y>C$XpohOl$J^fOBkTBSM-f&CvKMhgyaVFz{}h%Wt0omcl3`< zrL>^oa+=3_rv9am?Ji$Oz56pqoX1w1`L!;gx_by+*t0tVT2{&P_AVfajN|J`i%WK{ zE1&3Yr&?S2E3HC1#|S$b16)S>Uj^Zgk)&h$=CK)R~!{9|c2tR1jFKz4zqcoBS zfN7ay(v{;5qbWPjP-XC3D?7UUn?aFcjqL57sEs5{G;7}Ni8FNZ#I(5%g^O9x6AMl; z9ZF6{E3%yBc?PbHP9_>nO=$&-)YHy1qWb`F` z&a^oUGP^R*-z5EtjfVWt64%`2=G!Wyp%5z8@(Y6>P(Ri%;(;ZFO*WD5iyo``L9?62 z3X@&Q#U}2nfnX5)5@6`g9$q~qD)N;(lR-I{M6W@)z$%p?XbIKw7(?kIBekUI7&YMG5W75)Jr${gUni7 z|7K-%TxWf+5e~uh5n9V$z5nj<3q~CxQSj}Vc~=K4IQ?A1;e+2x{LHUZa`FnH!VBEk zfp3h<0Oi|0_mWJI+sj((=$D$^IbZ~!Y0qeaH0$Vx>0MwZ*)U1ZO6zMl?EzcGc`nVv z^yyt9kEh0j?KNsZ*RL}&N!9rdO|tA-E01vC!Xmd8aZfdS-Vv)PNl&@TBFG6{UY*LK zT1N4nVL#^VXjvTD?Ce8*!=S`O#FYaKl?70IC;mEVag-fAFnGO9*uhNVZB1{69QR7v zUv@AaTDLm>k7AOyC21|_1d~bLC=_+us1MEiTmgA}k`ZhoUDYqsy>DjXw`40 zYXnoA?gqRtHh3zl+dk(8?T8;s>(&b7JT`t`Mrd5qTmQ3OvC~3)E#exw{fV7wo4Lq( zs1_QXz}tc9RC6KjAKDJeAomP2$ZZLc35~A|gJByg;$STcu4L5^jOH5ymvUQ&uESX2T3Dj%n1#IHG}WOnsXQrmNjb#o1P>kNZ+HtL1@8(44cQ6 z6OihCAJUC5(I)fCrWGLdcm}K{$a#mJe2;uWW9B~Y_^AJcCAh^B+v*E$yQ1VqRmKpn zuj07qKg$5G5B2HeKTCf~&)i!;$-T0q_Nn&{gZ1ZxJIij6kAnYp>Rk4PV?j0%oRoxH zMH>7nN5UTUWi<90=-J_JTSX{%(x2xM5od!}SRj^8$Cr*Q6=Vy$vRl}gb%xE6kx7Xz#Nr!>c1{`R6B^qne+9(KQIam)Uv^;u@{oWt5J z8E@lE{?-P2>DOXOe};gCh3KT;WKO3a2^P#0Sj4LmUTZ+T^1&kX`E`rBBkC@v&(Ql&UtvCb0aYSpVUoW-k&5@b5J|p1G8A z&41uEn{>w7`qV32#yZjCqo^eZ!a)F;SajKa@q`Zhqpn$Dnm==fqzL>+5&Y zL^Ax6za$<&d6UX;$N-^Q8FwwX+3Zs zoeZ>av69h}+;rp)hMkI3E1{Of|ICiD_&qoryA%mmSSK%Ar>^xGH)7#_8(qu&Zk6RrH~lfbeF> z(8)=RSS5!`+6akA@LK5$RrA)>Fmr0&+FJTf{$@JU&WTX9Y+@WQ?;Y;bJVH}Sp7U=w zKROFJ8&r=j`Jz4i=kql4Sq1hij>a?Cf;jhHh?3ZpfC1SgiC2x8Splz1PWc{uLu<0J zLs)!KK6m!g-f)frZ-mrzq$VvtrSDRvq%8f9Fj$~^8ybFx>WyWZz41> z@(t&Yi((umsJ{%U?U7cNL_h4;1kng zfNW;fuDAME&Jm#R#Gj|GSr_X%?bM=Ddhxboe04ZPs)YQb?PB_3zKzpX(hiDNZm;Cx zMcwA#RWdf{hLdj|pyncjy)`rA!RK}A!q6kxde?fDUDF`UxjI&Cw1rTGfJj^RMu`^g zIJxz7ibRc|xv(BSg`AwjA;##cN+sk**mEe8(pF4I9UDo$4-s)FwnQvXuv{I2Cy2>J zsn3a?oGQAs+;+aTSwCU^aE?9GMq7qK!oqPYP6j((S}~);Mw{U$y^>#8yaQ2U$+CG~ zL&8o|D3o}9R+t<;h#TWS?#26p9QdqTHZww9g3MYY;!Z=?wUHWF2@dm46yhW{g=(U) z^m^STy1oL*C_V2o2gKSgORtGB^{%-<16sH0lyJ-&Z#_1!YbB6t|7Hvmjy~Zq+&w4p z_M#Z6OO+v3Dy@3{Y4_(VTJ>CHLmDEcz{V6pY_8p6-x4Wq=I_pk)Y01^W(=MB7Wl}$ z#UM5!ejk-D7FQP93%kr)Rj;p#j|F`$1t|COu79fYt>Zjngj&5SW{`QtOlCgdPAza^ z{ez!3lp+!CjCQ}w+|I&INM0Nn@np?r9}R@uLWx{L;N;#BC^3mSf`K!Z4h;Y%3{OFI zTfr7fE{#mxQKz6qX`c7#n;k?4D&s*6zFry_aV74bacmD=Og802paVAwP$wqQWs+&3 zl1B@emvZEk@y{rkKrOT2l>RX~P|IvNI|QZ8aM##(GSddl=P9wciwhu#sNgC`XB?^f(S>$!<;??ruRnH{oa#k+BmT!Se72~!SZl!NK9e!pIfC`7V|Mubw=oLbK131PDUpnsGg1eD;KP%Ln(A}bIj#f10Xi~) z-Grn~A&+QPVPMg&K&vz&3JuFHy1f^L+VAVdVAjPM=o&)uPPQ)#^J*33FH0l6l!+T2 z@j8;wg*v?^-K(7r_xp3hoj=HxAT*F{=rY(NmOK>F!XILUssl=?CU`*dsf02VzBdoy zvX1qKa17Kg5DI^=VG~@Xei@`Kx6Q0E4 zhVLWidy6_GuI(fSYV3lk2+YH&2&}`C5St1F2yDZt{5FxP2rR;r_^g@nT$1Q?;^SatBn&P6O##2e7YsFm{+-VCpma6cV;|~^J!`~4D}#z7 z=ZiYQ!c824wkm%ko%xVXP4Rj~za{fZ^W*LptslI)R7^NqljQ79qvWiaCfR92HL~*` zFrEe^#w7)AYUQjd6}h1dFQ)gIf8O0L1>Lh1$6NE%0(#au2i=R*ncZ*#)m(e+X!AEG z4EjAFX$Np#nOqN*(@)!bH4ivfvs~GiT@zTZGHy;iM^z6$O}~L8LII#C95#z!Rh2xC zJb3w}9(T_`CsTB{|*P2m`PuFa0`0Y>(_69_Mxk~qFQFN=}?swgILhNi=07esUl z#XmyWIzaHD$g>5$rE@F3hDb_nTC^}{#$EJPRM&>(rdMrlK@(ffE^ICIKz`%lZ=iGE zA3=Z71={j{%iPL^h9EzWm><5Ow8~1|`w0ukPQtDRn z_8G!w1lI$r+o>9`ONNszWZc!1Z~u!6;cIaE%h2Myxq~HYtR}oNWMwiFZy{F@j^y@a z>1!%8*7n|2RL|o^l26lv+m+<^Hl8P9o;Or;gj$qTVdBt*tKUl7(2kSnSD;tmbGy*@ z+}iea2hAsNo@}8N7e0=2*0XD?5WQn4U8|5A$Qi4`wWC`52A*d<*8{TKY4P874*-)} z@z3|8+#z^dUGrmu*d%7Go@HIO8Ay{i5GY&t?jfvK5wpY8zs|UIdaj|{mNxX5LI9gn z%$)M8O-?1h$19n9&icf~T06+B^LfBlNAt#R;n{}2+xaHK&m@pPj=f^0-y8u*X4!?) zqgVuMIj`J~%VMTIH}z=Z!;(Mah`a)L0tS@(qOOXghnS|gO{D4k&+13 z4I_<9T-)ac60vkfARaZ8-b{ST6y1L+JX)_5-K@lc`6zm-KzmL z;5q1o{*RE%FgTJ9sO8|n)j-r-PhWjc5%td`^1d1p-9%Yqd4qi$*8>c{M{8D>^T<=M z&SScapmkXq>YrNB)WXaiC`y+ePbWNroYi_SHSzpaXn^W9Vg8rR>WjWDsLl>ki;HXN z-{1%$tQI!0`;NY$+flLP(2$Y0TlQUH6Gvpkap|BNLkd#KSvjGR+WxP>w=?#h21Tsu zn?SxoA(sm^$n*2@fyemze{Lm|`uT3D;W=)7_wdSG9h7=O#N9^0CVWvb+ zEd1F00RbGbx-oX+b-x#^rtH@{A)VYG*tcR~=5;ySeSB5HB2jZU_hGV*V(=$}@yCO8 zQ(<+cf_eX7c>1_H>ou^2HWUt3aV0?GMK`exzzHQ$z*nadI(vL}y{-06fWc-NodyWVvTlW7wDwe5qe@dj{zZ)vV$(R@-AMhO|1q;7SK(@#7(oz zK&B(Z+RU8OCwg@LgNmDz`NTW#e$+y^{tmx*o2=@)AAe08Ee(HQ)_CjC7%_`Pt*8kZ z5I?V;0+79kOS$M`e$Z)~-I)yjQl)!n@n;3o)*QH=fc#eAeTlvA^GiVd`o8P)gKqU2 z8kI3on33L)>46MH#5JcnXz3?TmA z(l*aYoCmPSz@+CJX51NhyN^@z!24SBzTCd<&P+q<0kh+ru=4P!)oSaKh~H}~Ag1D_ zLhvbAbyVLaci$yl)09&A;qSh{BC=?0Ro?xTyMvDns;s_Be6-JAc>ZAW<^Bdzwd<5; z(d;`POP>2TIL74T#^HXgKm(_+27%H_C+S6z@`7JQ6=tSUg3v)u+V@)C%6&HDCcm@N z_`USEK?EQ~H}=w|eF}>!ZKtW*`pe$421l+6+OaHc*+I+a5pRqSJ_lkarR&mAhbtG4 z7Q2}T!xM7WL(rBe^(nh;w&QQJ`aCK4#g+Cr{dDO^g7=NoeINYR777Bx(&TtSRWO-2b?>Wk7!=p+(L{*wX!tUfo^Df-SmDlp>ZWpcf@+d z1D!uMl8H_(ynnW{5WiBqZ(5E6@3~^NiS~R&Eu0Bo;is9uyQ;yNwzomBuFd_UcxdBp zr_o2HzB>9&GuDJm>(dW^7)b`?hxNkS!AuQ_@;xupk`mB ze3eP2Ed2H>ZNF?SQV=@&)V9#T%RiZy2p(0;!j#C+Uq>AC`Eu~KR+N2>T%A$0UxHZP zc&EZ2&8lZ94jQ#XyE(WtC*gA^V$d(YxMx`-w@5d7b^|cFT%}xp-tT+B8i%M<6K?gU zYqVRhmc7S&etO`RcC+7%K-*~(0ei1V%jYaG9j>3=PyhVsm=^=^D}0HDSA0MxU|GC< z%t$qyoNUYPX%? z>7o6EWk0Upj>YKoA|3XIR1)4wkCeZi^|}h5bD-J3;0$t&Kjyj}N1FLyZ@A-~w0R## zPL#i`cW=%1I>eX@ufX_U4@bp|wX-F=DC^-s?Q%u?!&9CJh;Du40i`EeYXpLkfkRYl zbCQgAO8(7hPJ-j$om2R}FEa;h+HV)TQhV%p-q|V(iL++MN?&6?&)=5N+C}%PQr89ymX(`M#~Ro@X%w zc|8hwJqdX|4tYHdc@4ZtX9~fRxP?H-i6j2YkBj% zBl%7XeVPjr&8O5!(dUzsWjrM`&**3r&6urZ{#p(mt)b@E!v3ZoyYO(9C%iifdI;jm66}wTYUA+y+ zZj<&N@pU!uJhAp!*=*KWmIqD|-8MqmZt)d2E+8h4NjE3fxAnD6eYSfiY%HyOKUk;ks$R*3K5nJLN} zyVAArMZrt>Q8f`PEOkRPLGZ-kLOFackH32+>xVc3ol^kpD#t+bCeuW}8**+Znfx*{ zYm>^D@T$he!kP5kl$?2uW|;g^GycF%u<_4Q_e}1*b3-3#eVcuM<>ayiTs^KnqgG-C z=0$<6XCw6e{8$P@;(kOey3ik(5B99Zl!WrhKyWa}#Y?AqNTU>+B&Z)w&-61@E?aw8 zQh?&a!e`Ivs)s0lWx)&Kw=7s@eAOCqco9D3wFEhn_$ET!9fUS=TEqlVFoGtL9~DvW?-6MeG1W# zA{08ntO{^&)QQuR~)Opnf(_o`3NX7g6V=0!aA;tyfnm&kD!jl zRa;sVN+FXWF8&@;+Q{P{B|f=2%`FASChne@O0wl-F`VFG)3h{$`j`j@cIUv?UNdyd z95}-i{9gelgwq2#W4`nu?M%z)*GT_B@f9J9n(CWzf6+pUouZV}LXH?!&m!Zr$o1Q< zlHx;#y$W3)A|BkFc)NysnQ=j{_z?huL_k05C{BB9d&6$tb64K2cZDo4LNgwGAB4AU zaYz9!7LQx*TE~<1vpHoJG)qXV5aP-Uh zjv3*BKdR4-v;VC9M1;@(kelh=8wcsuM7HO)+UKc-L)vzj4y5qpt0*A19=l9~pBXhZ#q> zJ{E{2bVoB*GpnUUhhY<2$_T!5@{o*7wL^CGMs2Bqr2!X9|IIjH$W(*Q^d+*9;!Cus z2`#`#>qKyWgN$v_)@Db7|N5UlpY_6@%<8FPW7!Drkw<_m zr1q?HmDSG{5HK2jFsBZ=1ZVLdEyQ5fNqBA2^LQ>6QefAG@^m6yap}zw-@IwSE`f8K z6=$!WEoLy7yNLweWzieGeAX=mHqI9~!7lN0mr2as-WwOdFX?h!L-MwO*C9?XF&Z}n z4hRWQnY%fK-lu;eXyNs;yse7`%K+CzxeY?|+$W0@sC5dTb&r5yx4|-_#JpP@&!CG-+L58sS;y zl5?aIZ=noBx@Qrsh&J$xtot;|5(2{-u~%0;xR@C5RE<0P#!W8scSpI4uSq<48?+fe%FoGeF+Yf0vS@GqU?2_N=SZBYOTe0`2K zUFk8=JMc^PA??Gm;)S@`twdC^zNb8sPAuNhzOSGdcmyPc?49s!I?S?HK{O@)c98e!{5=sR{-46Y;YC$lF-rM*oV%MxSFORdad-l~TJBw@cCpEG&y`730Cw2)j$1=Q! zW+o+biAj8%*Q7ywww7oW4no*$S_-HjyE6!zEA;Me+E;^lue+Qo!ObfPx?+9hyqYjP z7vXI^W#i+*(7|#kq?s^}ZKfUTZ&vE5xYgos%){IL$8&@&XtK3nOR86<_O7J{*V$yr zi58TZ1k_MBG}cT!?_*x$b~oQ#>cG+%B60ol6DnnhXXa!BK40d4%P|6mVAqlrjY58G z5{`oi`;7VZuSZ+2+ z6|E;yghN$MkK48``|FW?67+Qh$lbIk)nA79n11}M%-Gu)*>XnFTHbN=oA1@97?4=? zz7BEqP-E-K_5L5E*AUm79o)?LadDQxiBlMxMu|ojX_vFDtBgHVi8 zM!0gM{b6&Z^~*UZ!GoTB5aC1W7hv>H4=btVM}9wxZ@<6YfxT6&tWi}^yM1oyP+@}a ze#aVWsL=-VsxS9nTx@MwxS1}eYn)2%i%0A)8wWRo1z=l!1crb`g;0VC3RdZp01v(e z<}r%jgen*be?pQ81cqahsR;beadN%7ux;6ru)VtC+2J|iiuJm(F%q#xHoEvkbbT{0 zOpV0K1a%_Ctb0r=KFz2$M`sgEn2cO=h+A~^^)7@m#a%EUR7_O19R^bD-}Wzd<9n?| z6oE=V=9i``Y*t(bfi3Osc0eTunREn-VUc3$-=sEjsq3t=Spg5iqcO0yM6d>_4E^rd z`8ti%(g(YobUGBUrOb4nCA!wTthUQO4NwB22C@aZA;s|SW@v@(P1Lb(WpJncTiU8$ zB>z{mp{3ZR0yZQF6@)F|*rE!Af2L(~8v@1OtUoH;p}=JoHA5;~sLB0bRW`f?HF1+2G)sw_Ii99kGE7SwoPls~ zEnUHFL^{babYpN<`Z5iqA_t=2D*Cq%@hf1quB_9C2}EKSt~qIA-CzRqz79jrzmh8% zW?_qn(@T(-m1{H_R=J@r+xHq&PN76Kk{ZfK;L`&&SW2w^RvEA4*TiJoeZul{JZw5P zqp_f8PvwAmj5PU+1R~hdO`5ALz@x>4T1a414(m8Uy}KR8(#0F?If_zzRS;)!K4{$% ziJ3JODjiw=#c9(#`By67X(6!{HHOeWE|3Y$ovQ(MtnkGzNsvGp8lRnF8R0sRKHWe$ zbcReZ8+95YV!PVc>n*7}^7X~L7tTJWN<0i)_gDL+t@4{ozAx@q!ayCNJ`oqx_f@Cc z0aarx^`Bafk>ypJNvampm(ZMJQT2L!<`$=wK*j(cD7E)X6#EQnsX-p2!WM z%fpc##vx2RW|}R<4PL}?hu^QbEM}-KFv3IGg>W6=v~N(c8HsRT2z0{WS0J8N;?~!1 zy6vi+>WNjX-pkHMgC0WieG;*xRmXWxUKVd?77{^bhBE0P$yEh1eR0wL7>S7b0QGC1 zLR+Z5(M}MEe+Z6MUR*U)s!DwiIGg)zkROcbz^}3I*aT3W?A;tbc{!WwJ|}%(z$h{_kfKxGEa#x|HcR6?Jp)m| zC}L1vCc~XnVy)CH@(+k!5V1gU^K`Qns11+u5V5b?LKq$^qtMUpbU`|&+v?_8s>_O} zws!0*fs^r3;wnDSVtX1z{5 zI&S2nvu#yZ?6#Z&J*RuRWoDhwQ5lwj<_TK(2c%k*KCv6Lk_WN(rTMG8RkqALj>ClcwqeANG{=sL3f>NDt(>x*pVx?P^vd z8`oc%PS5GrU%rPq!*edKe0t@;b2g6e5;K@*ckGuHIwm${9Ls%Kak_hbPu{P_?4w&To%gHfe*gdg|Not%G0Xq} diff --git a/CPLD/MAXII/db/RAM2GS.routing.rdb b/CPLD/MAXII/db/RAM2GS.routing.rdb index a15b7e9822f8b1b2dbe849e873877ef5a0df7d66..42882b416a1509d815e3b1196f80d6afb9074e3e 100644 GIT binary patch delta 1264 zcmVjeK^<*5qo#x@FfOZ<$%bDbuAKWBe9#aU(-Tu zJaVsmq-Lo7u%OnCVjS3-?Ejb-Zf}j-C|h4eZa?pRFVwct^)_VtCY5b9XqEeEI^R3m zolU19>|P}K#b+hS5@wc3)*?QyE|t1f4Wd{Jo7sDf(0{lzmTX3Gx;D28Y__+6Lg#hq ze6Sd|^MRBwJY*9`! zLt{*8R&JazYkk;{efqGgWhiH>wAEJfFy@6>`BB=pZlrHLmXX=2ATgA$q_4BGUckV5 zo4OHH3V)+&WGHV1vm4p8uhpT9E)X!V1fa^Bl@ZJY*@X?l@UkL|43knB2`W31?KV0x z*ziv0RmJ*xJ>?l9gb7W;#Jn*75l?ZhPS@*=FzFj%qq1W9%B6jsK5W-zWLpXCV8f}? zxsiz9V_r2~Etu_CP+1*0uMJ=ZIZjsuRKQF&K!1)AX9pXEp?w)A6&07S`)iaOW5tgE zqj-wQThAlci0ZtNbAe&Rt0vcV_t$f-flWb>K}4c96eJ$D3d0)lZp;hQs;)2;CURK* zSX5^lU4ADv6b2@usccxlK!VW)#y{dI*rU5LomXGbB%yNR3pnVJBrx4-R5|%GMe|7v z<$pD7`dVDljl~z7k@LuC=9WKGkRm!=f_EB5#^MV=1ryG0vu6rnV1bH?*{0@Kmu@J+kc})zU}mve&wUoFb!14CFjVclEo#l2Y~b3W zW+!q0^1+$93*}5n3xg06)DBISGexM&hJyR(Wei^$`SagAmNO;QMmbYbHtwS@9W#TULPgraJS)>0)-nY@W& z!82~DFiVvqzlPZ+Ez&j<2<^@6 z%sq4N$K1Ke(@v-J!oL@3{iRoPWFBm;R$yYrdcP zd0yju`aFoT}zx_u`U)^%fb3gX>2Jh};da&fGCgpGadg5iz;CugP+Yb6>Yp3^p zIy*S2EVn-!pN#(;%*NA6J@49|jpp+j8=acZt&-1SKfU5}cY1R1dlG4FkGt!nb{4dL zC~3|5!z)@x(|^mz>8&{ZSaMqQbIZSG?8AA$#~g5z10vw8J0-DIPTiYcP9nAC zk$dAKH9+mBIkl!J^T23){A(7uy)$l0w{@oE_UqBlNNtr}@4{{0HQhGtRi680GCMju zoK7Y_?Jjfq`Dd}n5@zZmYo4FCYfl}ez0z4Do56dH(0^D9HJhb#+N!qlY*x2`NawnA zzL`6xt;(w1bY59SF4yI<4D|YT>bWe7smSKKY*v9@-Az54G0=Uaww3zJ@@Dnfyq%Qv zlO$=1c9=KCOh;YeZa$jYqWLgZhF*xyn&#YWpkk4RMx8ti%z$Br!{$~6hNJSA!HKNk}f;y*_8|Jp0DT!Y(T`RL4QZmOFHyI#8RaFf8A4HP~7OTeT>q96*D%7 z?L!2U&`Xf&?QlYrE?60QAtFMt1u9Z=LlH&ID$q+&lZ?S!?Yblol^m`dN6WkP(k5FA zSK3G7L9h842ffn@8KWo?P|38QQiEbHJQgt6WzsERsTLR@2X|*(nJ{kA`ywiZk$Z?pmhRU2isdGU)=3-^SP`$v69U=CUAPfXMP$32p z8kh?grBCV>zy{`GWx&8S4G&|fm0$qXri*Ga_!Y7@tgxD^1iw!STLD1_RDc0T!oyf9 zthXh5$1`Q^O6CEcR>;7}&rIf;kbjZ+k%8%xIu|aAxmcMnG`fKqJ3{QoGo|^R7g7O? z62&H0Xd9x{$+j?>#<5G>NUER?u^+p{O|N?lF^H}UzFO6K13eiuj$)U%=^H2l!>$r; z&&DoslUQ)Y0z><;=&7Q&*N@x>)&GHYED+RsY CJ&R%h diff --git a/CPLD/MAXII/db/RAM2GS.rtlv.hdb b/CPLD/MAXII/db/RAM2GS.rtlv.hdb index fe911310157b839bfb5a9f9ba3f22c7c4ae5b31b..ec8c72ab1a9e30ee11c438a7ef7c5e19decd694b 100644 GIT binary patch literal 16298 zcmYkDV{j+W7q62IH_pbkZQHhOd}A9MCmY+gZQHhO+c&@azb|f0J>6$MJ$0%FeHzt+ z3gpOuXspPqw`k&%v(o`C~j zNfKY$!pQ_*#Mr{==i0Z1|G9wS{J)-nxM2R5|Cg5W{m*s-zVL=lAr?urnH;GL9U~;9 zGoc;=Mm9KEevr;LRC86CMxLiD$LlvLyl~&`k%pfDLC{eaR#q04*A`Gvm=Rfaw)f68 z9Mw^fR}d2s5jor%Z#(foK|x7u{mw>-b!KE@Bx0&F)z8^KznI{*|KgL)U`NDwt?-5l z>Vv4oHq^+%7^54yP?{1sKW~imjqMA1Bu{2^I1h5TbBy(vNJh6&8VYLD9;Q)Lb2zK( z>u|`AH?*n^2I6B(T-D$4dy2M*dJyCA5u-kMHd+Ag$ z#B$voHSwKuwQHrm49X-A$!rvHkc#E8l`ReAhDj|SoRsc(Y~83jT`&+3rM z#sdExJ5(!O_Bg8Um@92NTsePMFgtG|&lb@&Fls%SzsyNzQ~CHb@W|I^rtOk^Y0tZ% zbohW{y?oBoh}&NNd7n_vwa;9h*&su!ajS{P?2{HvLkpA1e|k(mt4}vuUTmJu8n?2P>I!ka+Q2yA zdc6MSh39F0JO#>Y$+QW?(s;U<;&8VG$uZtkpMM^EO{YUn*qg2=QGw)m|&db7q$gpta&4y;GE(cAWf^ zI?{W2REqG4V$@lqY1_8b!D+E??w8D4!6pqzljfM7=O+72q6*O6-QW67Qg?4AF}IG@ zccx!5haH44uy8>9wx$-L4q>OA28|jgtX*m8Ya2kTMJQg56FQelm5@6+w@$~szo%`Z zwlKvusHBKb`ynoX+xc#w?Bh%d6C2emMXo%SAVQK_Vp8H0*%{Zi`7GzfKIiKz!iiVraAS5ftdb8unJorBQ{wLWjrsKSNj}+}JLM&V zb6{tCUgQb*HU!3J3H$?al#X$+?Y>b0-%kI(%N~tz*=T1z9?P@j+Q_UtEXeZ?XZ*xS zqvR9giu>(($V96r-lh9fa4no?r%bioiqc+5^tdWdH(C;vMmUoqBb-A=&WFAX-!xsw zFI!iuiT=x_V9LK6+-NfrNsID=x-bl<9hi6EsHEPqa~se@jzZ8v03{8AME>rS{okHu zQ`7L->f{+9&HABRt%v{&qJMOx80oNbb05QAS?yEbiU2RNX!+C#zQcdPPT?y)4Ntp6 z9qwPXPaca!4JvwK#wZP!dS6E8n!#0?8MOEP!*)Xm?(UJn0Mf}$w5I;ItiLlFZP7X* zDfDs~kwtIDjj=B0Zzn9)Gmm>NE4YRQcy5`|5=QcqkV8rcoWopigcJRrHQv||J~_yZ zGR@z+2EI0~f9|9?1DRjs3Wv+0s;4eUbL_rp%J2qPf(TUmdhrcHP?py`+mi zOl9xCt45kvo6EmHdy?FDb=S0o(A4lKZ>uZ6|Za6`LsUg57MKs znvJez<#%e}lWFOYhm^O7mlmKMXO^3Niw6C5_!y$GwVCWUcY-B1p6>=ep5>x%*ek5} z)0$3w=5z29_U`(5_r98gvfZ->3WVOkze^w7=3aT$I&;q^jXw8FuPU0VxSCznHoxac z`R2DaP42HAO|KI`A?xT;xR~Q~=kMK0dSr1;*xQh$8Z8prZpo7^-Cp~dV z9bx7Ed=@*WOb;eB$nr5_k%Emhz|~`Yn2BF5S%fn1YG=@v<6%VF6|F6EZdj9RxFw2^ zMe-cj20|;mYmA*i6y@6Os-WT;Vj28u%pT}x2(7KCE<9n$#e5cJ5X;pjtt6Trb@suu z;h3KIn{OiovcM_hu53;Ic|%!BtEqPWAT%@6H=}u85SH(wk44b2waDEOYPHzQZ!yoX z8b4%K#0s@;Zuwm!%LfWe15^3gcID4W+I@Cbs~d!d0#!^d0Cpa{b`<`q{WjPNcgXnK zC4mS53)GqtHytn$ECI||IUjuqj;b`r+2nD*GP!W`CH8HRQ9tD>*{gGkoI}A&K1GaMe23qGdi&Bkl0(}UsJHt7w**) zGN#tAVQmTrVHLP9aRR2EB|>oNbo$*f39G?Lo8Z1Pl|n8o{T0c~6qeJVXPa+^4m z$Ts0H$Q&&fr=4e2kXaNI&RNO2awYN{yh>dJ2px3L(1Jactg84umx(hMk5fm?Rlvq& zY{4kJaqqj43~s>)`y{2@UEhF&wvp;B4iYu8kf|l z#x3RF|0fLnp?2^y_H$1$8O;wzoKOC@`&t+U55D>mZmD)wVqCB!sp*Yd{Cbb*#CbJW z;k>H7{djzWh(-`aXcbGbt#4e)?_|m@3K@GG*3>rarhl(Y*Lm?E}pb`!) zQ457(s7Amb)FogXXcsgNbqTh%&OzyfInovW6(CT=1*32ZHsQxYZF2wP#qfYS=ChWy zr7n*vrC}`FQqlm4zJrma=U(%5kcf(rC|HT8L!ggu&RuCW&4J0=P}4ZGim|2JqRCo5 zW=jn+;vP1%VzbdpbLmQxmj>WUlbzJqo+LNErZZlw(N><(H`iVt5KtJlATTSuz=)5& zUN2NW=L%jOs)?H4L1-C(0ZGz5uTnT)RwX?abiftd&A}jMAKcG-QW9 zP~^*Cgs1f^;*(iSGSl++iqG!Y9p{rQPFENHWttk9uS?i$Tnf~IQ^7L z;$7wpuhy1Jm$$fVwdKUx6~)>PyYV%U3HrvFOqw%n+ElUXmXx88B56rkwMh@{mn|L6 ztvGG9`d0V2?!{u2!hD*#xZW%}L>(E=T2&ay82~^cu-0xTDU6gKNQB2C0o1dqSgXIZ z(J*N(uaaYYr#DyCmev}VRHkRvTHFm>U(lpauQ1kAM4lyCn-$-3+E!SlarpKJb9Og2 zd+Z;vm^rVVxYr+cz-lcm_V;*j+Tx)`$Qj+{)}A0=naVMycfI`+_60sJ47lafzJw+N zA2U+&lIWFVv}wHISPA7H1}CL#Je}*YD^#XkrbI$&9J>RhUDfD-s~l}j3Iaz_a!GQ+ zXXp%v$_v=h&`aJ5=2QUnYQtG|TE1c?W&zRT;+f`QB~8yk;bpvSDX zrNc0_@vC4tFNu_qCjN7uIHL}^1yb<{UgjkMLjTzYy0ECJ@{pzU9fsF%c2RZKYJdwy zMChV$aLnOKJlSsVaDAGQ&*ZkgVclq`+X&{X$h$F4?vjVluULhcd$Nhv5TYvU)Y_V_ zAM}{o2ZQ=fI%V3D8~=z+ZJ?!E^(mJhrK)a0TU0$VAy;1?X@NC+xh}*7MqRuS9-Wg@ z2T+ro)TEit(g|DX&AD_}x7P_y+}S{>yr|``1K&!^(~+do37f$ez^hY$p4i?k&&Z0A z#u7xj??4!Y8=bJoE;5u&t4Watu#so>oX;`0A?VU0i@=ox5FyX6LJm5y3eH*?wJ^#v zixmmXVqb!bIKnfMr+F3%*rzf~z=V6NiVP9q*hFbdl(Jk}=d)Z!{!sbD5QbN)m7q8iKl;tBP;_+CBc(4Pq!`tcjB2!_b8%+gvx zhzYXSG&CCxS5b(kj{_WL0qV)cf#9M@f-A4ERCSd6XsL<}*Bw@RBB`~V@*-%=XcnCr zx3bf}LrOAe%vqLgIk(EN0s*S}W(zX?uOJ@QAF+f5=-2Zxh8@YM~iiASEu_#q(Ne{3F!Vg$m|H;#T(E0&O4}iJ0#mtHk z&287<6vr02%aOYhR%_#0Xzp61*zm4Mv8Gdse3_*j?jlAh5`Z^(Rr`!TXnw_a*D}g# z#hX&dGv3I{!fKJW9-M768)B`C)$5o*Dmd1VW=3RF4_B@f9|8ab;G^VdQVRhP25%!0KF38V7ab%cGz!tB5a zwwb=X9;+$Q9xD#)Ji(kld1;SRp?9FA+?BkN279%knfSMQY~VEgLoqAxD2V1^%?p}^Vn)WuT)DEnnyRYWGb!! z5=07Pqp6jesnKblIpk;^P8ke4^jcd9xWLIdtUjs9ADd<9=^xfV9(Y;-9~AS2g3x7Lhk5jP1X40(G=Vyb|zA+H~A?A=XlBE5AUS2aY!?G=QRo2%pzQDPzy>Y}K)b0+jeH6K!y2Pu3b>H}WEJihXjW0i~M5p-E+p zXiR+_H}DL<^%Ac}=zu1@2sGomOZ zN{eWXW_aBCt9Z_K6*XF6p4zWL6?d1K&lBZ7Tk>;?EUXue#Jv*oV|LngFQm*HEX7)y z0WV<-oE8j^r}=l_CE4wvfx9J`Iov{QpBw|Lk=dvXiM4rfl5%lzf`b@!`v?bdQb(9A z%MCk>(5myF76TN9L2AVCYC3odCv6ASrSxWDmKDX$B(ms5uZw4A+Z=Fcm9CXSGPE0{t7RB7#WJ>J z>zB0sUM+z1&h@hm46&~$yv?R$n{U0QY#n_ZQz0%+?fdsHtl78fuI!CS>OPzZhX#vF zdC+_}bE7UZ;!lkH?eJfB&_8GfQX z;VFMMpg$fz0+Bj2wBx##KN)|_ev42u;so4%3;f7$BS%d=dJlWU;0;vd0L( zEpLIC@$nkmo4k=ig#Ij9p8H-~Ry3W9fAv@|8vf{rpp{xrZCGlv2UtsKcS%g${d8p# zS|$0)QPndkM$gU6NA0ld@CsX zJ)i70vCq%yvV(ubk!|3_Ye4u7xUy+P?(W%9(vPo8BZp&e+>6@2xPqG0OTXAa0pq#L@bA^+!dSFzj7Jq^epQ8!*ZW<03f)qx z6~rdt_(!UHxuBI^-#za3+vu;FQa?zSbi;jf(cgzcsqPLd*`v%Ie!>q%B>_ZTC|Y>^ zTA|!p(IJA(68GBD2LdI5Y$l6fl>L0!ZU1LP<}ahKthJn**P_2y%odoR7J*n&zL{Z; zYsAcLvU=YSz|33Z3u=@gX&oOp;(^IB&c`6Wz|bYHaMbc}aK9o7fS`08(LFahfO6-& zf`8+xKCt_WIi#A;W!}^!xTi_=yIDH?CWd-~60Z^3?I)GZkMBQpv)hN6DY3{f#bS9J zzV>poIG*n>L&m&hhT^j*J1PjfMj3>>mf+0>rR(@cM7<*%>&~;pwjVnz3$5nM<&SXdePFM>}aeE9^(d{Cs-lY*|$QE*Auir`;_XZ zyXy_HE<+e{fUJ8J?YmJYq$b4^9CO^0FR5RCP@|sJhUf+!;-T1RSH9xF@QR7%udtOy zgg%Vr%B*Z?^!2&Y$sAg&dgk;yvYrhW*2l=nzNN6^nzv5MR(ki?OFKGLK2j9ZK0EWm z|MJk=cg{+p3t{M3syK9CQVTd1zPWvny}Jo})f4=JshA%2AWoojK73+55!jR?(?6$) z`Gh(*h!xwG%&>l^JfVYL?Ez#zu5f=H7Kd;A^V_a40kR`0@h5Tj_fB)#FhT6=)uC|Fr$ z2Li!k%JA2quxybo_44i*)N`08@iH{t?wzaaXLE_mh$ig@vba@07Itf0lJ$Hxpx?=x ze8$f*#G5W-#Wy?Ra3$TRCdqx{SVQ8ZPhqb>QV>hfG` zdwp}ZwWu2K**4Wx)wPvng2RJLvG6M_*skWr6pF5Ir~~Lxmp%{jw2s7^X_Kc@2e4Fe zt-e%W0a%@TBrkWIjLS;Bin<~J4CV|lINqDe{x_=fpdT>MSW}U z&2#(5YI+)o@m_9a$l7Bc0;DE*Z0}KJ={^b?-7A6-A7_?ZSA(qNW!ZpCga%3(=^R4- zZba0A{$ZJh6c^-zpVI*38LkMSd4E) zMVc9$o~f^`F3xVQcES(|T+a<=c6y_aw7n(Ko?o15F6A%w12mF7Tl42aYGiF=MD0Hf zsH1eDrD4X!$z?jj|Zu_|Y@7OgNGoLFvm`m1a~( z4q15Aj@9EDLFL$5b3`nA!A!+r1DpF&9XqMm-M1{oK{Wp|S2#>wgEl>%DQ4^Kv6I?N zf#Z!NYWe*Y>va?T%jOz^n%nAm^XYG{0n8M{h5Ti0NW<`3Z{b{kYI@ifJnQ?TF)^cLL^TO_O%QC&J7N)y>0-Tpic^jkiI|?+-M5_ho&j3RXo-TDYjle`+C8@ry4+ zDW>Nl(FaY^(}6v6I*_aWOm|2yH)e$a+ZZ5pYr79fyA6UxA_(%Rde($8MtiY-40Jap zz!EZ=zd~S8cxN@KXPf)hS{~>7JpDEuwZxNJsFN5l7n} zA0)zQ&|^A%&7BI2-GW$)IXIHQS_LL_-bA=BiUg~_a>oJHV-S3+aK-E9UMtql{1g#* zO?!rq6HY;CZ_gT6GnamMf5F-{>`OSqWQ@Y=-?VpTKZ2t6E>wvS`q(erd)9_gaZHLd zzFx~73M}w%?dLy|i+koh=DELr>E9kZ;M}8J&8W2r(K&_a{yITYSk^3L*3RtF|7UF! z4mewGPyPgVJ;B<{O>Ps~{%LacTn{u?Gvgb%w$35CS8(3xTn|vLCy6d4xaHExVq0)6 zpCdgHR10yZ+m~R&k6gO3{n_LAk3{92ZB6i$G8XsK73OJPez{G2azV^E;NLLBU)q%8 zMkz!O6fPw$38xO*y)NuLgXKZHE$pE3Zw3X5RkF9Gght`ek#IS;$4q9YFgzVau6q z=6)Z*b&lY8baFj-`t4QEtTwuh#^%+6q}vCq>A3f7L#)ss_yQ4U3u7F<8jfMr zZZI(V*fgfH>r0smK!X9z-{P=q&_YWVA7 z+%2X&t#0XCzJkI3DnZDLqEHnARP(g!^Q}D|Sf&7n;_o)8zVI zWx!IJ8<|Yy&dkgip z^z`#7T;G@YROZ(E zcxk+&@lrbAuegR$pI!Miru`wqxg=@s#Xxxlr)SZ-mEy7Qy}IdPoul~@a3D1?bA2>f zQnT_cG2ckO%=^(gy*#v%C1tMR*&rnTv!uEgn!ofVY|j--Prc9KV;`Dm6O+1@ZP$cI zIxD3L3-!+Ac;VvzpBn9+W$_YgbgpP|n*7F-q-3A%lX@s0m$rpx3zz)hjr#VUlToJi z+I2jymBD|jCKA_vAweM)D7$^@HRy*jG#$MLS3As46S@I%puv@QnaEUpj*}c(FBC=H_P%&;h zOZ1=A*Y-hhQG)8;4qmeq9ged}XuEu~c&hc4@t;(^SO>3q zOp-0|ESdh~w)5Qd?cr@HxD?L(%JHnwZ+2E#CzejXf{z&X&k+1#G`VYW25V4^4F9s5 zaz#ns=%HLKxVXCa?o0hgiYH6T$3xS~S7V2|MBI!U zG8ZhF&G(q+i`+`1I2T8E|ISN>5#FH_;GQivWv=#9_lfrpa|1Dz|5>ZdTB<)arN6!x zLzVr7{8RgTUSGprKedCV-Vc0ja_RZ7q!%WIChE~nJs+tnVeUaWp{;YRsb~l0(OZE1 zCBgM=`}e)TltDx{eey(Q_c)M=?Gg^};bMLzUqUxfc-H2}>AA6u&p7cYMcTS6JD>bs zYGn4dY|&9fm_^AaLxf+^s;cYy#F0UqqwohRc2h^7>r3J;t8X@(jP=WWtxlD+8U&T| zhIB^7!r6XdZ(`vgibEIB?idwxJRL6PaTi4poi`p#Ap*e#Hg>wDE`u+@gS&wyI<6@! z6E3Df270yf*yCZN;wsa==UXUByDW z3jXY>UE-ncpT!2D=pL8*$(6T-lLgR=icD=hVe#sUYRvLV>cyQfMqs>=p>d_TTTPQZ z#q=ukqj-p7z+*2;;p}Xpen9cU_~Pl=fO=$+ z4_HTq-rKPcs-R~tl;%H~MQ|#l10OgqsjCMz@lhTYO&mRY zN$)%h>b$0pz2B%z$~wBXoylHIEi^J{PY?l>qfCYWvT?C1q83A_=4J4{(E~4#B;>f$ z#Y2YVjZ6&vFtvlSjoA`l#foKB<*HQ69}$IVR>W?`RGo7;wKKVcI=aDZS&!?!{<^qX z)-lUx_dx$WtX0V`@WO8|?J%v$Q>KECip>6{G(4=D+lzpj7;nJmv1T{Q^i*y~HB!&b z^I}!2^H zhDpF>?4xr55)a)7JNICbn+fSgL_x#J7r-TF^G~}*W<;?4WQE9;nh4#l28mbQ($0p4 zTEXIt6A|yB1!{;;>owdrEH!8au$PsLGbt2=9@;;RScFs>k2)dL%_y6 z>9G4%Rxv51=cR6kSqH>}8`K^X_j?m+#6#pP2k)_aF@lv0I%U+_I>&KzJrt-Z-k&6l zTGoHhKlqj}nw~KS_!Bv&#rDRoF-vO`{<BM| z$^V5{EP;!%Qq@K?e}8Z6H;l=B6DLgvfkV|9)!2tnV!>-0OnOfjtZI4h?c*Xxim`A$ zsKC%!=q-~6gam)QYQ2Z@i_}7il(hTSox@LpF_Q3K(WzoAoY;b0%%5tHd-Fcx+`8ZC ztwDc*IdkraAAm+0$o}Mfl9rf9ftFaqB+F~gaXvE)`e8?rFdmSs+oc075|DQihs^(! zwn+P}1^54FNcp7&*Fz854P`~%cZNxLJ^ebSHugZ}o-Fpg`M9>9AKX3djb*rANOaHo zwKV6vu>_nH8zqDuUl4zr7CW`z$R6$55JiL^-*BZkOTwtxoHL4A;Ak5T459q7^`llIazKiMI-e-tacVa%F6)u%;dpH^an=sG3L{E*Ka>_ZNn_&kJ zxAvPd&$OPI5;wydVVXPb?ObI`o1bQyrD8wY1i_1g%bqRG>?!DggSFu(zx{Q$C|LU#k{mC)NrvlJ9SuVe<8r=qw{tVW z+4k8_)Lshl%6X1w@PBskRwLh=KE`Wh+Z~kYa1#fMU`$ zG4zN!b2+BwPANs7z-w|=#wYS2!kmIt0MK{PzX*P5=y(=9_X=xvkem_Q%t`c}%yh?> z8LQ_ax^?vLBb@23d}?GpGu9Qz;zXEppd|{ryP5;-&DrdLEhE;oP3<9lD#&LYqqQI7 z702wr)n6I|dIqN8&rngq%nkXIrRxa*h(zZp_nz=sP!F1%PHTtPyp~yEpz?3&u41J+ z4m7*)#lT~Bgunn%CLv~Zz(b+;j2U2EUMtT;740KwV^ZBVzV0&CQByu-|X$Lgr z_-+n}CmN2LD?emN(HX&=Tj5jupFCvDezXD;iqZ+{Z|nSySdE**TzCawdVc= zz?$J$`+DD9mW%SqT2sp1R#Qz!H4XK(E%dmvzCAaw4m|l6wka7KI}smffvdMc1811) z71=N;xXJU+1WxC%KgX`(w!1}$?+or!&Glp$h$parPPq2=0%ZIfm6fE3-(b zoI|#*tgdmUMygxW-<^*IyLbO}peQ&MxYJwu6q&0OHq^04U0-9fvB2>dg>xl+f*sUM z5OjT?{rkX*d5MRY47847O4bu|4!m*-nd%1v8CHCD2)Vk3>zu%OQ{~_Mwde3GxD8HD z2RNOdv132^Y^iDa<)&M4aX}tc!L9-bS++l+@;A-;9+1=ASqFByU*z(0`d3n(0qso| z^Fjqf5L90Byzlie4OABtYBKk>>x})S!*Q#2JfH`{oo;DiI=-D*fA9=+y|S=OnP0E> z>Qn8Rd(DK3*)=@6CF(o&;Di4&|FL*%!(M?0YUdln$-cU}IH8PM3{Q-mnpzTrEQs8Q zikOA}8&X~D%&df7^t`{bd>pVH1OJulbpwAK@GZsr68XA=Hwy7hzSEI#_8BA6%E`da zs#EF?k9R_veBN^OtyV)X$9G4>u;qe%V^r1S>j>t9&HusSypZmo&ld~wj>l1xJ>mbU z40loNKj}F0Auao1=D24&750sN6BW`m4RXfX`1aQ`x4A{A`vlJVCj~8;PjRI3bFzIx z8lnRkrJE3@D@qcLP|9~(u&m)!u1vVa*gR~>J&5!Q_O%b#wZ58q2`^K6TAgFtg#Jw8 za)QY5lCB6>`zMtjKX~EdJKQ?7?JVju-Pz~bD%5>#bq&7({Yj7`+X-O8#d5-ao^lDv z+K1cRgWH5ES?BMZ?3}s0nsMCBJ#H16hFF-CqI0EtK=He)Z~2;p?q|OU+XLTME22w3 z4q)^~{nZS$eev%jgX!*`pVMW9u0_aJ!kP{lxR|5i1t!; zf4x}&!iC5vk(S*PNDTwhy#Or<{BUFbAiR*PsEE4fqDq{F;(K9g>xlY1llK;JZ{cNB zeVRfBqy7o9-q>xxn-}zZ)T;8g;VwDi7XyhNz){T@c^Wfazr>}~V^a1{z+Q@AnoT?k zab(l!`q6QDW#RDy>d^k#Wa*Io6`31eZuw=_njhkjn|v%-JrY!PB$%B5-O0$+*1ee4 zzdCEUfHN8hH@tRk5KJ<*-?ns**w*p2^>(qgQt}D0&I2NR=qYe*-b0^*&27Kh&B@*L zv&C&T_DZ+rW{aGi{jZ#(`T51U6x%++(|6D2*LIuGHxxO~sW-_K=lA^(se(mRXadbr zwTuy03jg)3=g61p))#`Y1&zXqqKf&`xyiVna10u0FnF18 z8NKnKFAv%WHoqoNZNzf7t<$K@z4b$Q|z>`pY<9;&Dk>=e6qMd>F z&9n0o(M^_t?C=gW`eEYVyhw1P1S;b%`A+Hd;T#C5DOBsDNc#})Uo>xzjgsL%S!$y%H#-)-3&>7&%G%8*snyOs5`WZDgh`uK`_Bht{-p)9UI~=kOP7P< z?ld^IZ*Nsn(}jq8j~HdY&~94Oh0%mv{5;*eJd0-U`Do&7-Ou*tx2s<# zS2Ij7v8%vH>~xYIWJxc&6BMDxP0~82We5<*#d~+izQIDbpEU1!;Ou~ejl;cv+cD7I zMFFQYpy{-b;e!LMyhJA z`AEXsw4!z(xKK#p% za*aloF9q7$oAv>=bp}r|vP&#m{Tbkk3Y9G##0y@0$lC@+>qW_>nUUqq$)%a_iIFoe z?Xqw6T>-7@c6D^I6w&63dxBi7Za?Hp;JMr9+F!uegfGA7S)SyE@yZUlINDfutajYxi)?^*?_ZJp@bna=v)6Pl4*i zmYvz3#NVO#81cS{&Gn;UazCd#-MriNo{)oV+z9dHsdUO9%eSzBcL5Q^6I$-=MEH?- z-!bsQc^h~2MgOeza^iio`t1v>^p#m+bRQ8{KK#aQDo^JlPN8r6c)b-&{p@ zv!lJa5pjBja8(`Q@bA-|ddf*;7BS&=QZ^&w@& zJ^iSe?kIINz~u>f9!Jft-?g&1)b%x7+;d1z8*Sy)n%Qm7FC|oYw7zBi3$74Y4zXoR z%%fv{pAQuhW(|(zO#Tf~`-$8*>9u8C2sFYez~3HEaPm(eGSp8j1PFo(6`_U|*#FrE zbNs1BeZCkt5^_L*UyL*!7ker6g-DUZ^HB~eeoaOXJNQOx9(bN;a7}`!NDN;rP--^^ zkDT>a?Ru}8YCH#FA+}AB@P&DZpKBCIk|<>}XT@xk;U)G{QoUn?5RoB-DV0F3crO>F^X89cXq4b#XVk!0X$POy@>woV~T(Du|&BT zagKo&V(lx@{IUB|2joZctt0;?y)w8YnT5vIwrJ9NnXGDe=(RkO{Z@|8DK1A=n*t%C z6inw$C@9ts4YV;A?9XDaA~+#H6^V+P3_=@-{?I?Qx#?UG7^JW@#}}AN6^a^L;xK#` zie}Ry+}bxN2qhWXg3ARw0kYH958)7Vf-zdT;fH+F&3Rt5?qZinarj?r2X0?~PY_j}2Db zo^wP9?*8E2gL4f(zLDQW8;vsr8m9dw~f!X-KKV$O5PB|37YS~n=@ zk{sv!dlio49Hovc@dA{fU1(Gmxo#alU9=TM(1ptQ;y_5yC895j*w`y5kTn_#L$5Tq zg4CFeVznX0TY6L$r4B3c!iiviT;xED#@K5*yzWuZg~r%5pJxiWt~_z8B1Q*n6=!Ch z(AaD6R{JKC%Ge9y!IS_?Kw2au7Z@_N_n^`i7)-{f4bxyu4Its@pC>Ef$h5$5#1Lx= z#H?oYt|}6cZ`5m&uz|($47V2k40=;F^n?@V$^hD?cr=?Ff?By-c@31ks&+z_nr48bMNtC$?HPg>{jAmkbIjS zrA{Qyat5WD_c-(QyosRG*Am~idHE<3fA*{HS&`v%{@RUY0*;oU0=muU);IjYMd zG1^Zt{Ako_y~blW@>|*krBSrG%ge0CSD8|&SJ4ZNxTTw_KGXVu=?w_!=c#KX4!1LO zzn3JBEWsjQIVG&8`Vc|KOGskEo2mjyt_j!p0?`9}T!KjLm1uKeP`JUj#pSP?4Sbrz z!y-RuJUD1V7Z^vk7;HpXy&V*Y%k>+Mb)bXaryLEZyg%{KTuN@I&{Bir3$vDN2GjR< zcBM$(43oTrHdHu}#li0TNWX6EP?S?NH=Crh4sFEc$feWWhNEZiQuKfraRUxq4`P%H zB;h`~uRHS$))peJ98qGrXAIrS+od@gM3i_tyWNC99ji$J5#LmLZ~GK2d}KRu!P>6z zJJ|Ec4myV^molxxClO;%M2zS~sGTtWrJZ~rGvSRX#wzA|Z%}NTFgqb!9Tw_obL^?w zK_HvquvCA2S7-pGLF9hlU&sL)570k|!qk!G+)1EBs@bBJo|fo;EIuKL{}{z0b&SmG z>FHB^;{gGEf4c#DC3#vQi=g)u(`_{b30k-(iPcsXCkf(Vo2_?twzdbYZ#ueac@Wr> zC<6eBrvd!(Mv>pjLcc`k$-xB$EA)wgD_$TFjb?W6!2g9sf7i&&=>H0fE7Pa;*>>gf zbnQI1W=w5Q-S(<}Jxc#wi_IF%@U$!D&3m$vs6CVI6#d3?!CL zf37_E$RITz4QG*dzDUhRg|+ z&L5X;D6Gw5+{2h5?8EH((_tf>(7c5*Ot2*8uzx4QbLuiAN|=RHJ`}*Zyr#^B9xK>Y zV4_PGHIs47f6eczc3q!|ve_9hDN>+sdA#1jMqEA+OOi?e+hCDYV7@_K1T#UC;iF?W z9>)>dHZ^XiSBVO|h^_f4b*l(OE_09;a;~cM?5o zniyov{98YXm)Ve^;lP@r*nBy2+ZEW1p?%;tbAOvbES5`8cN}Z={>Vwpjc|rB73v{S z1tFTxCB`SNa82vX3_A?;ukuxf7uV~6(c)wNXu^$3Mi>gw2~1Vs{XHRY6&M&7k4}() z&&{9RO`{93%~RN@tfAzS8&cAn&d7zkwX=T&s=@3NN|;=5E!L|c3{fgj5N>ztB4IA_;duPga)@Bow3j0#ah8`$JqJ ztY7bz006EUg<@k;$7EEljY%tXJ(M{ZPD_TyE8Z|&9N^RqXluzGmtN0C?X))TOz+)N1#tB#fI0m zU$X~kfFoVPc1W*QNQ3;j&yu_ak@f+DLNwKLlZMR)=1#=@K@%L z_8{mVSJ;AN;p@y7p@LXkF0f+SYXQh~b_d|Cs*#Q`oWHeL-P>)TI^p=PNP7&MvJ90i z&Uj3TwDb!lX$0$w=n$O;9v97O5Y-%i7+xSXJNnZkuEobM!E>07T{iYKnAXG?dWRE2 zTT9fKaFw)nD{qMxqcggCy&fRY^bN$QP)g{N{wTN1N;mb=d!utn%S*tmUB=~#`;bdG zh3z=z1s!;M_dR3ck{OH0%AYDWNn(FT6kIHTOjoum3kX{~xp?h5-No literal 16470 zcmYkDb9g4b`}W(dZF6gTYqwk5wr$(CZF_6mwsqIG@%H(B|9Ou&K9k9rOftwMS1_nR zKtRqGw`YW)a+pF;Z@7N9a!W$+F?{D(6bc%8EU-ZH| zg?&PMWRGHE$8xoL;DLX`76Hbx_IGZTjm{eKGX{l7_Mh6;_ zh(}J1dUQg`V@~y~n&$0B#&3n>&&FH*yX;t+`TC#at&FXb*mGw#^tTa?j{CfDAxHd` z!=g9QtF-;T#SB-;K0c%lHpLVVi#Ah6LS&l+wrM_)$tNUY#+9`dYF^+EK4$c}Y~Cvo z#GAS0P8;!@RbTzrV?Y0Vxv#I~`eZ1}o{_awxeXyO3TT8Ox0qXvpu*puYBC>)`n9w= zTYQ2sFASBpwUtZiHkt!2r0NUbg(bu*F2yS^FQlq3B`Pl^k~g<IgdaT3HDWs@-DQiU7LO@uGX9Mdk!OgBEmD-pfzh1n+ZJ zs3~NyEChNan#B;K>9r6V6(0yqqz(C)je9>pvyv5=y1dSQx$@fJ z$XjQoh2&{^3bjtA)~WG8rQ2#V)w#p6BHekKq_()?JG3PJ5Ki&m(~51@(uyJV`HY5OjrdohCg)tZc=SKe12B1n;1KUR zz4Is%qrCeQ>t}ogNk5F{pT~4$nbY3f^6o!Kr!y8c&Xq5s#44^GXq^jvQ;Jtn5uTk# zIOmVu&4S(ES*j4fb}V-MJiE1C9b1b_2w^?pFh+nr$S~ zFjT{u&nl4kR+`ZCp{DSPXSih-e%-TLtrAVK;d6D#t%9?*o@}chB&0qWDjaXoh@QK{ zcivP^0YDGqWQ$)J&C~?frPo4UQI>dJY19yL|M8v0QaUTI5EozRe&-(jL7Goba8t+7 zhM5hec&6YJMPEH6Oe*}SGF52S{9<87crA2Da9VsMuZ&sLd=x!g6gZu9P$DoW!b?ej z64#%d!W=e4a?(LK^#SFQGJ%lPA>1*}@#4RV-|V6uedx=P^I-p|LGOkOVZ zhIqydrUo_Z3hz4EYTsW+_AvvClB8!PN70KLN(4g_~Xf!+{tcVIDneB zX~R#&^6S`@*6*6XE=Oupu^6KD?iU=8#)mU*%f{QhEbs~nQr-ox2+oI?cV5ytiU~Q3 z5X)_PVTKA0^uq=+uQG)tue!IJzzN}{GXW4ZA{^EGZ9;=?<4NL=l?cL$Jzvb2^qMpMowY1r>XM%GJs@MM}Yms2TZ z2_Wa53b|Q*jEF-q;-#%``3?5xP7Mv2w=n;{SKxe8#476oGd%`6;Yf_rTYv1r6Bc_>Qp6edEtvKhp0UMlNs)QK(YRS1te*Vi z+h~}39UC_^K1Lt+B4Ub@^I0A%t;x!HO^-jkh0(xR6j(RLKBzWYWPqy0 z=oA&be7`P*{e=XVGqM~Ytra^;CRI$sn2A|ln9%pZpCF{Y^qRbw{ftof3HTHm>PVUt zGxy$F`4DectS!4LV*I1K{JVW(M~!%aW;5LNU&dxt@ppx%QZ$>xyta$#0H-2X6^PSG_|tLt z(`oqAF?jVH_;^>m)3`%guI5ni_hs0?twJm-PP||ftV^Io{Zz-3jevK zMNRMPGjT?Sj-C8}0_-#q2npWgK$Tc5m4=ipXUK8tINynpVPys0vW~cHbu#MvFS>gK z{{_mPe`CrUlh>ctA7L;Uq9|lDNw$Iw%7p98xCLl~yA$&&-8$ewxJU%?eb3&);4{xi zSRdP>MmHWm!tsv~`=7A&Be=9%SNEKDIUOzRK{XlQ5!}ZQuSo)bZ-BE|A8jHZH6L%6K;huIDU#xYfo1<)zy*DZveub=; z; z&$gICtgOp|*M@7L7k83bfM9vbPi#hNNYMLG#f&&$mob?t%3r>4RMQcum!*8nC2`c? zrj;x@Yvz~*pE?^AC$!!m_Mg100i~8; zk^7{mw-E?}dB&UXZKMfMLad*#9L>9Vj2um+F1N@`O-~} zOqyixil-+B7ath~`Ci;?R<#Yo66#ZeFwb)4YSykenRG@j2Q*g4EI6ic1|VT5NLl}5 zTTtoBPhoac+%Skw%)NYblxsq<8~e! zj&}C>Ww%vAdroi07Jkf=9mzI5wOH8Op4}8HKDc2vDVuz**}}kPnu*_e)v4qOd|XU? z%eQ_xG4ei9n25p~nko*V`hano_fr)luV*NH%M~lptxy2~P2=OJ>J|z-IVc{w(n^_n z20WinW1S6f#?f{LC~h=`pvOM_L3D3d#oU3MPqI@wdD9`Cip`$CcU_d^>WijQ71cuD zPb+AG9Y~QOi+%Z`2C|S#fFfD+o{%aNfF=q7#J?(yMz!!~pLWNi6X?`6B)FTq>SQf5t3vRaG#e4mvO*UHe+*vWSK{u zut*Id=dn5!k|T+5z7kf%VW~-Hb0)-N0iHh&?u3`@ViBacaAfwcw1aW|m?%}1($ze! zaeiH+wX(x+3#i?KCu5?<2c4;{vp8JoSEqf4`71SAILDGf0?e#m(@0L!Mo!a2PSZk8 z(?CwsR!)=jghXID;a@{WRDc4;7!_rQgKoXUC_@!`*29E73@<)qrFhf>-%{gD*>zip zysb1`p-<3DdybXItcobZ`YEIc7hYf43gbE!!x@j_K-sg)PXust%*THU1FeGRCfLI| z#KfQR;47XrsO9WahK1}?fj<=fFz^H52aqE6N8$&`z0+v*$`&LkJShkxLmF zF3W_4>5PNMe`Fk&RpS476>X(A#US^=L8xP=p!DT3DE0nmvgrNE{9)qw zEo~@U(m0Yp6`dJEsbKY)&6U>INn+9{fp3480v{i~Xa};Ylo!EgC}@+a@ihupfJ7s2 zevJ$FC1hvc!*6GX|eUCnoWZk*D{cXjWqugu=H6r;&Tpo$PJo}dM%obe=zyM^arya%zv=x zt!SY(Et3GYbdZazCxiGiHcm~1?jsAvt@3H6PX*=}js%w~K@&tJ(wA=m;ail6<`0TLNd6%77UjWZF=?11 z&@KG=kuU5le1yrGbFYwMoa2@>GJ7%-q8lL3I)s{9pmnk89*6#M#G zZlAwHok&%=bxJ*ZtFoVB0b@yFf};Rg2%DilwNKQxYTknMUMrf1P8gLdF=I#Xa!Z68==2k5I%Z-WE9t**EMAT-_UhwDEL-?}Pk zb~ebi!_v#*d_H0jor!Bf%pgOt5&)BxEY}`3aPO)v)(mf0Y$y!;J|$Uj()r1v*(S>D zYp?}-w`6sYy*S47=VqhK8n8_nc_tm{&qa$m>(=%E9OG0ChffOej}4oz)hbwjEa6Pe z%*dB43Fl2Zpr@mwgp7o%bKhDymswQt)+J5!MlXe;xeCPtbD7A1aa-|*(ulQ}^DhW) zaa6Yb9p=Y|7XLLze7^>wNmi&lVZ_ojS&Tst@P`f04tt{{AxBCP(8z`*?S*>MWv(|8 z=97uJ#H2$lUS-8Fa=i>v zW4?rUq+lYEq1mY%g3%$@Slp0f0zEmonSMhYpy+&{`XtA46oEcP8heoFP=MKFJ5cCm zjBl-YnHb8{Mwv10%%UusMYVAtfvzWT);q$-Zkl!y3NgN!zOq1@GqYj6Z9{kN2eM`B zmbDcPpncClrItr4G7gKJxqH^SaL)C$I?fQr1NpT_kp=qd6&w=IE&r~t^Zq-qR7zo| z*dW)qDIc>4h49_ZH}<8>YULB+gBK4ty+U?Q>#Sn@8_p*s-I4ljV{8;Hc3c2@9{C}# z+0-Dj#)D6XJ!UVk4(ki~60M0qEwB;u^Y{^nY~0M55C3i?@k{g_qkhZ@cKw?>{lj6H!p;^PZ1YUFH`#84Q;rF$?$cp>h? zZUe%)REC+kruQys&w;P*b@cnag=(&HSGIN8(X>foo5%%v5PtpeyqXcHi}sYwgsb;3 zvcLBuoxQ*P8xgV0;^Nj&T$p*P%P1qhd?8_LreAR{T2TCJ3_Woa->aR#Jw>lY=dHN zFk}%dBrjx8ZCvDoK0AlQczPfh3^^3UHGjXm$ocQ@YI&)oHhOk~<yA)kbov8 zruH3N^1o5`cW|I3c_@67B9hWPRkQbSe z@U2XAH%UsibC#xxlidHq$xbauS?^3s9>R0Q$_)i)juzN3WHsoxhOCfBz4u$NLdtVG z4_JA0IZhCaV{hF#d-)h7jSA7mm9sZ+yTQ10Sz-W>dPEkBF1zi5NQbKTUme9RC#h)A zeCy?~3pZqkek$~M)jQ|-WN!2&chalWNcpPRg0*SDwBr%d!RV6@FwQHxP;KwiF|W9ygyA37X6vdR^4XQ^-n!vK{t-*9-r}r0Gl+B!GqyEXV~XjmWDx zxynAfI6GDA@e$gHs6oS{PO(k9(w^(??y#)*SN+eEN6jGI5?JRC+=FhjJ0OG?@vH7R z_+>`Am5Rdi%BV)|=$txd_TM@rPRaMutS9X1IDW1<&fqPot_sju8a90c)X56_5EtB z%o4FKXsLoiGI-gou0Wd?a1u!7;CPPk&XS(d@9f-M0dx`{mqaI@E)v25{>nN^uL|J= z_c-E?4+iSUSiWQi3|F%{rmi?{XqOG3!l~`CA4)5 znzdD`?eB3Yd{RS9(vR1Ij6 zetUmASj*Tv!`5ZKODpn|0#ylH5Y$HWKiFK8`ym#St*=c4?5CKx2jsVY!9B#<0p2ED zJlsKFYXx{RIsBdT+Z`m2V6F$atJ#)zq1s5|nxY$bPchBYPt#~>Bo8#Y%i9YZ+Z!=Mg0`Njnq0Al>m=`YK&~GT_6JYUl&JTz zdXA0#_j&y2W&|6SMHnFCdULwiRMD_Oe9lE~X%k-(Z)0V4=hu|eqsD7-t}GCrN`!wx z_S=<6(UnnuEPzsD%f{MpZ>YE=HLSf@CYIAZg);4YCVD7Gbq0107E}?IXTjBlOedXL zKfam(T(J6L4&EM zoT78RVB>~5-Smt>e3R@RLG=w6dhD3mVB%^VZyJVBMe0VvRLO&4BbVXhW_AM>?09@6NOY?qmYdXY4hi>@5nG6cfg!Y+4gJGv2!Os$smH zgrQ2;gTh;IdbQW97hDJRb3RN&n^B3d6pt<<1n6faylFn?3+*MUQu08(QSoC9OD3We zCg`Rl)+zSRN5JtVL#oRN);eBadl0O5N2zu-QI;>6yPm-2p=P#C-EVnvp2L4)@V~}~ zo|)NKvD901s$o-NgjNzS?Tzj25302ZBo8OvQjYoT%u$o%@7`?glT00~7l%sHLiP~c z3qgF_@V-0)mA)K=B`m-66wI?I&);--fAE*5w67Z+Q;L>c2lnpn?%whNCGF31O}Tdp zGwVGAXMCzX5Vq$fJ_+^Ugea=?mp4f9jaP{!zk2ewneb zovng&>0f=DcJrM8G>(rp&~gIoN98W>!Q&*(@5Qi^@ko}g&vY~eSIiIExEIG$nppjq zS<|%qak=&hZ_%I9g<6X)^0`mJZyvfQ(Z)Fj0pCP9_GjI1ICp_GiH@t-IdCx>X?^7) zsa?uVVqb#0ymrFz!TGOBRV#MoGR>N5AiY2(uB~KI-Ml0-cB}bL{{&Dm6tgZBCr@Rx za3TFn1lrT3>-D)G*8|tpECEP{zFKg)Oy2;du!|{vmZGxpiw zP_134&m`Vkt>1p_>~?+CyBp(bzJY?=MmEHUEl>x?{$?hgdHN{#%$sno`ROuei@VAP`ucPgJpVuF5(-8 zyITFQnxx0)zG+pHRq!3t>A!EGj)eIKEqMdFi8MlDVZ1- zH+J9~11~`7w$H01{nzbftyT0(&F&nq43J3I@C<3Qh==J75Ee*5!Zy_w7s!HLTGB%d zx_Sw-n^+EUb&+ecga>_)M|eW=Lyd~~F}0FT!2reS7Hz^dTGq@hc45Ny0@Z0>L#pfw z)#(J>eC-{9v}x%=iJ~bvN7~8W!NI`ei}$Qks3+evLh zAVeA7y?gdnE%Telv=K4D?}X^H3{w-F^3JHnS_`{^<^K#KAAQx*l}4H>H6iWb3FCB& zPVsu|ODm55WMLB%_urAq#~uGWak1M%QUf}HnQs!RZH7YgzGpx_k46NWG^OV4MBosF zt`>C2GE1@5&@(9S40AMpr@6#hgf9N18r=}cEj4T?vgNHnCx=SJ^`9_b#7UI}syd$B z?fqX7^!3HEYs@snf}VPA-3GnzfYfm5(AC6VlR~%q;vgbKEdmywCw6V;#3ddOy*~uF zz_BR(()CBYk{v9*4>nLm?=Fl`Z06G*IiW1{7~Of4oyz)EuZ1>}nf;n*gPZ}%Q@7H4 z)zJEQ0+3w!KY_qiubzSQR?xP}FBS+azVeE0l>w^vXuBx?#cy8^L}8Y(*qM>`w+z%r zF2}+i^Y>yaCEesZ?H#W}Bm9C<)rZ>~2E zcUwgDR>+(G1;fB_cG7R6PR8~I3ucNh;#CQAG@xF2V-b2I-=gk_xXI>m^sFo(#;9It z5_eLkebM{dh0yxs6KXfV8NsA=DZ4)OS4A`nQ20_}@^o3g5b?KL`5aM9QAoJx+4*#g zD&pjFh+#}&pjZn-Fh=@?tcy5iE*|M8SPFkgkx1xxaD1_$vaP*q*-;JU20FAglyJ(G z15EaXi&Y4y;i~AWtK^O(_i8#D7;Yo_7_ZJ19_F9p^&%jHazF|bqp6SRLHOvUV1^16 z3Xx-D#Bm8KmBt^Fn-ta*@0|!Cp-Vc%_iy!1=%ZE7SoTg1Ks$8GV`COaBnOfOIuF## z+1mL9H1(+lx=0!*1Mx#008^`P2crk<4^`Rf1b&jWHMMxv)pSdG;Y`2;V`QnNMTSk| zZpFsy{k7OFMft ziYR|WIjr%$AN!>EdA3F%?Qeu)e#YO1YmD6oY81!lM9D0JQvs4biB?k@E^Xr!o({yE zt(MduZ$lbx*6*l?*CzFxjk{iT?yTdiG26>{PORWK61(p#!NDsEAM?jELZW>^{j*Ta zWx3CT;A09#x+8wi#VNnoyZq&_V>uIkoU~}tAP89zd}GjAt9Viktw1rAzp5o<%d}tf z{q17rP_U>=Fai^BIM+ms+D6_{(P>gwp+t=k6_X97JR-7U(7TJC%$(0>vMx8K_=Lki z9c1e6aRa7@&{(ZH%sK42P6cr8EN5zO)=wC-=S$hj*5*_lkv@gXKNR0g!o#VSUhGmZ zH1Hfo&}b+3l+4X-RKEVLC3B-l>vTlgdNM_< zO3-X-h(i-C%U~Dt+hv)G`c~Lu2nN-)fQ}{_lBEv;VJNmFG*9qPJ>(_gcv3Y~jwhqI zIk&WP;&2mKViH;G@R}3AB0yXs@jS$8KFla#e$yEc;4d!Gfeu1@$;zN!xu@fbH?5AP z&QV{%tDr79*_T$}1=1~$9E5_ilMdon_J(O@8h&6WB+XTTw|!-g$>t!pty z{rCPPN!+sQ)B31K-m=RqQ*W1Ios5Y+VmUaRI#`Go#f5-6`5dK?y&6#T9+DDkY(w3YuxE|qSv_EhcI^` zQJnJ;++L}1rLpBV1xa}5{RQVOG;rb~Wnz)ujXQ^*xCFL8PPSxXgcD6?h=4@r*;FA^ zV$k?+t3`BZY_lF+^884C#S}6Br_($Gc7?nWOuGEVBKNDpdtj^>QYHgZ#a3y5DvTtR zggq883+PlzIYo9U|BQZZXeEqkI*h$2W}IVB0Lse+*t9yu>1!QJ?pNP^PiYk;d^Hv( z{-cbx`Y|J6YKfsbhnk2ztiF^&*27BFz7uokxtr)ECUAO@i)uJ!ynM$HoVmXJmC#%* zQtE(dqo_R>%g^;{4@?gnvyBy^w2bt8RWW;p)OP{GgXx0IomQlTSJ>*+D^SVO1q zNi7k^jw1FYK-uzHlxC)=rqBmiL*={MX*kh`$FFHa&QQcz9+| z(A^G`Pg`_W3bUx5c7_Deh{*#>>RF1gz5bc6)hl8LodQz?dWKny94H5uSlZc(`lw*O zlQBK`b`bHI!g_T!Jl()Z0l0dB4J4t@O7ZJMfgP1np{34yZ9t&a?b|!XN|I zz0y{qFbF_fx>5JL(>N0Ux91(#f1-rf=RJ#by)fa0+}ATjPde(5(AX2elB1ghPPVD+ z;Va4MqD`&T)=gUBl}D<;yBYz%HH)mwyNFE5)+{_8s!4Q6CT7n~;tebJ!BHh+<09gN zD|Y?XFXsH~dQ&zk24VD+azb435e0E?70}}n>NAh`)^ar~3+#b9Fz;4>dmvh`H9%~j z=3fn)W1h&Wcu2DGncYFI~Plrv~7 zG#a_Zl49La&gj=anq1rLGWx~}&z2^MSq#mUHu@%sQhFh|bD36~P?ir4snuGbBTW74 z9|L_!eWzm+=QD)s!N%14+FrzGL3_)VgYC`Q^dS4D0PxsXcAH+%lstd7kJ;VhIDUZn z(nxu#_QVAlY6AcD>1ldE;5V4-B}Y`@n9%;gSwWoCV{rAKD@0+Ag#M zRhB8#Ing!e3Nk*SamK=O25-SPMq2}(gF(Hq5iw9Xt+F}C4fTnir;fpWYY5{-?`PB8 z4lX7d+rHd3_Y54~(@&_-82NLKh%XqSXqXz=5W!U9&Gk%p4;}fJ$1aD`1heIre-^DT zqT5J*cb_Wfd-63x8=FUA^V|uK%rxt|VhI9BIA5t`CEH=I59sQ^+|_Ev^iy-pzFD;z zmW{2gPZ0mv&&!VWL3McX(9k6Qt8c*v^;Pe6lX>6AmxJ&X?sd~M4bekN@L_w`#|Onu zU+lqWBwrJQ5LHvY*cpnj7&pOf{_>5kpjL|i8jo3<1^SUheRHkl?~6eAl|^<|%~AKA z2J(K2yE=2w>%$81)-|`Wm9J|by1fVg zNtGwVcq{{CzI{O+r3;aun-;DsMH`JuE_ze8#P3|EK?z`Pr?wXwi}cFy74N&Db2a=( z+$p`NEcSJ=ebC*^?*KY9G*Ip|(85lqFj;x;nCAJ)VZPJd;_BSMd$XN>^V#W|BLF&M z>1f`q7Z_=6`RTFdb2&}pwZqA^@ON!>&EZ|mMsDU~bO_M{FHT9MwzIuq^S`QZ?j8k` z!Fv`J>3wLtH@ovvEMV~4o!?kbkJ57z_kb1wf<7C#9$YNF`!FSJ2YPR$oHt5N-zr_J zV3xwOi|oC*cC}JvE?2vUzzM9o@!VSaF6~5IIEf*=jGl6dFNoxw9soYvb2v(<);wxnDP4i8&o@Yz z`5nR_2St%A2;qzrtp<$?{LSS8ymUiYxQq z>(=hR*FoVpb*RYuE&HyUvB58d@u<)n19B3HS=pgp`k}9vvop+|e+pRTH-UV_)aR?U z@XM;np=Sey#@ABvKk1OHmFi*7PQoLZrX!%$nuTTz$|zK(?zv_5Wd^UV0GZptK%3xp z!R{pKtCy@~>@B*J8@N5NZ^c5->u@$0yNIwyqULS_pra0B@F#6kIdkWMI+0&vY_xDo7jZl0#nJQt5bWO-9Nit*P7;#?h%?jp~I%1`8x}L3HdR( z?Kk*3n>iVG6;@AO>D1M2LmDvz)asjAUSBq8+CzT!T-SWpZszwuB&9rbBb#b{yVr|5 zWgx{j8lN?pCk;UD^St6W)T+C(L#m5Nvb1m7vb;Ywpz-&Q!2kk55~Y>(1m?_{5iYl$7Q+iw2St}et$%<^2VqjSqDWVEd!etv7{Kc<8T#` zYSP1b%hEltIp+5y!+cuj!NI34-@f1X`6eKIEqLAJ9tM8rdfn{&y1KHDJ+kxyK5~rF z*F6EkI3Dr+#r~CW4OQBPJ9DAdL-f$h2`LbfFMhM|o0s#IQxLW~Z}gi5<4rEl+zD4S zcv6nB`j*(+ZJde+&PR#&h4FQFW(qqhc!U* zV_31fHf#9>253artzxaYiv{7uP4_meW4+ls0l$X%ZF*-o_ISncaTrFK7_Bo$3yV@R zi)O(k)!#K$LqBYswXD}!ex0j+@L5kX!AFDF%?eP?$gvJgr)Sn%q}TYj zG4IQ{!|B(X)(N#k{!Uyi!1iJ91-A=QC*MFL$Qxz1lPP#6B#9j22H&7~xWi;UiR^gX z%c7Hm;Dh#c*LDix*cHD`u>Uh^ew6Oy2ZnQUf zNASj(HCwe5ZoES?Z*VDY5A0B*xX3cMkp*u%5#?J4!%J6j;Tc%=lZi%W2>If3ZEmUr zX65zdh@L!LqBhN>?cCeRbYJ?p!q4dvls6)OjD7NodtVI#l<$%w^ z)DGWF)beHf z&D-EV*DlPEaClSkXx~2F^Q_T3#M^!Q!01ITn=jTQyM3X|A{DDh4tuh??Dg9>?*Dux zd)-_g&3}5rM@P!P`-5n~Zp7m4_TM}o2Y!znZ>Bb3J`>_#NM772f~xm6|@vh2j39 zv3d?OS;m8*$i>B~NvcdN#~?-5-{&cbx63O23KjDr$aq+QQh5uV-Pf~saA~x_e5K^q z9L$mf{Mt4_;Cu1iXVZGS*oDz&$MZ^7UP+uaJ+S;p`DuUaL+R(#u2NlYAnf~2K;g9R zg?J2gGGDuz&^eA~hF>`}>d36Eg2Z22d1Ruh^w}e*u)=g16cal7} zGH2i7uPkniyR3b@<*$j3`?A2>-Z!a-g1HrcMX&A1A3Nd9K8n4sDXr%lj{{u~0$q;+ zT@M3Yj{~29Y>t@&GxVOpsUNb#oH-wG9P@XKqIrc1UuFH8(<@tqo{`|bzSWz2G=IIN z@&jfLuElS3e>#D}BaV$t@W&@fN13Ct?=OcF$J;~#4GY;?37ufUah@;qfC48KQVK`nCO z1&m=Hg(0~)L5}H-2!cM53Eyl>8*bpEb68{VhY8?9vKY0`5*Ok!dJb}$UVUN7=bJ30 z{{8*2>?HQ6_Rl1ramg?aP*BZq5}FY$FzIoVyyS#cuM+b|(7>ZHpqFdpx3polCdQ%J z-+v}pNAb)PW?-UH2vsWm=*%tsqv%Wx&+AcH?sN{E?FapYawH zGRJRAivkod8Q|jYA(f3hGAr`Q)@ks_)tkH)V!CUF!yW#M7Boa6D^at`Gr)x((Br*H z56%b_kXrB-yn!8LzbL{2#Mjm}!OYw}N?J4^C7#L({L8z$*EuSFcTa)(F;j?41ohvv=v4mc1yu|_3&4C9Du zqu)mLRH8VlzATdKDoG%2Zj34aqNOWhtqBv?jiYqwy z=6uKWeIgpy=f>M@U4POq=6wttZ$GsE;&nx`<2L=^sf9(_wto^Daqk%}F`~Kh8mRvr zleyz_ng6@r)`qvf)($4fyg@w*EBEh z;l>940Wv^Uz{U9~!XW=<&FrVFeoSXr3{9*+@$lY3oYV{3C5<5~(vSfpegk%zyiYL% zyG(2&DtxF##yj$0rkV30azpoaw_=gN#w5K)LmMGLt;1zK*Xc}dMI`2n%-m&lFqxwb8NwD;!EQ0wBnmp%dj z;vg#kuz=?N0zPWv5bx!00RSL%ke9|x)Q=US;{vJiFYnGzdTFwrNnwLVY^YC6e33R|T{xNIOoxK8$ zPW1Y@$7!%fE}_{MXee{yfMHb&u}Y}*YF_K;Jn!++Y+AFHmqtghXnG9!ZB7Azr%I7E zVj~WJ2LiypJ5T%gehPZMDQ^p;n?nFV9fKjT{WoCPmERVnQU67W8}>196q<~_2al)> zd%@XGv0FouG4-{8c4!maWtf{R;xshvT&{ZoBe2l0k5mFbD#sJTTKCF4t^@wivuM+p zuuSH(kRE|HVqoGLLdT_JB-PVarVT;#z~#lk^)N}&J2ekQs_~jg_bMmL;j}oGWzfT+ zEh{7V0z%(4fo)a;rk*%@h@3IS@AUVW6P`;__&XFH5(R!1=0UgzJ4!?-TftLNK}=ZV zke(f=8ZW++EVB z*p|jQah}uq@!6UpR+vxWvuf1uL3X?BHW$dfU-F+T@}Z~E$Qq1v_1%M7R4&SIci#D; z)Nf4mg^x%k->WP~!SAJOAf?HxRVEQ&38JfhDpAb7js&X5*&XQw z-1~Pp@i2Q(&{__=o#2_Z5JF!g zdZBWB$Srcv;#2cZC0ec#UE(Lm2!QL{zos+{4`>N2RRLi!vx~j=)d8LQz8L9PZZ-*J zT^BN$0~KuduePq6laUYNqjh+Q-LxnbL<9S%9&YRmxD{c5d6nZm!dq-=9B4zrWppy;3Z#P?b^rY;{LFf(6ap zQ$*{ll_m2LQr2Bup02KXrzbg?HQN)|6I9NZjfxR|2}J+-Dh~mTE|G@}3R3G6`K5M_ zP#`k5ivTh_IKpR!!jcvyuYk6=&tZBzedV%Y>%G@vXW;6D+kK^rBAYZ2 z@m3aE_=OP?Gzq>Ea1dMtlxK=<EJgPg|5D6=T7xhxbZcCh1loup@Tr@vc+3Y|Yh zgTc$&aeTp>CZ^N{0@iBcNL#S}6^CjjwRUv7i=k1uPH-LVJe+$$5k2&taVOq4IL*eu zMp8K&Pnr%4*Jz$nWVT6>2R*67{o1gbQtUvM3d>=3y+22KL9G_HHe=oXOTG;nq>EpX zWI^dy#`qsgO6rhVn_PC?pcuWRzZ{t!gK->X$^-4-M!!4Yot+JePG$Y(Cmko&R2J>b zuspGsH)`N&v7B4c7z$OS*_7DvOGwQLF&W#U=iBc-+~KtkW=&9MOe27YlK9k$39#!SMJzNVDAxZRug?IeR8raf zP2|{U90s1;RTb{m;SnBTWCz8Y3-sZ8sT}r7Yw~RcK!pNl*|DAI6Nr9N z^h+n}i^&@-Gte}Q)}LRl`YWWz;ma8rEH@~qq3{{aMs0V)$CkF#lA~X1iC)2W`@A92 z?IXr#W!TbOD?}Xh-pJ+Wt@OiF9Z@d%H(oAz&plRwA>IyHI@y0mYin0t*6)wN8k(Ol?&x?@=J(n>_L z*_LJe3+qcUen}oqu@^J$@B~){tJQHX5P7EuS(!CTtQ@S(GtWv)it-qFFZ^A@Fet$0%vpo z6yif4J?N1D+~OKa2Y08DS5DdnuhrW&rdN1DVxTPDR{s+y8SQ6n3eF@ZgMCn)D%nz| zLtLc-+~04r!xKgz%F6(i;=1bhMD8O;YV8B<#L`Vb8@7wSTWO)S`kF|7$C6h*2Cb-} zu){zC@UJ~uh4XRLWZn*`e=!+zDhSm@KN;c}*qQZ(e2u=~kfaB%R5Zg{2 z!O`sp1XYzmS!hQbtrWwmx&pCwRZ?D>i}-dqkxh5s^=n(h_z9gG5k)^dy=nhW$d?ObZmbO@uZ^G_YYtoFnO4bYXo{W#oV_~ zVaBm;fSNk-^|MJFkd1x~VzmcP$lNP>e34G^6wt1#LmdO_t6%vLo&{Qkch G{Qm*c+m3ty diff --git a/CPLD/MAXII/db/RAM2GS.rtlv_sg.cdb b/CPLD/MAXII/db/RAM2GS.rtlv_sg.cdb index 621c2e495c0ac06fe285eacbd5b292348144d107..11638fe25e6c36988a13b7467d10cecd50b6a96a 100644 GIT binary patch literal 19172 zcmX6@1yCGK(z3@AubM zwaoPPZgtOgKRY!9aBy(t81LRF9GvCb_2rGL8QVLU+uD5M@?%^i(Di5ZzYzS%}8!vD|3XUYFDI4I)(^Z)3M^#9AQ?~Xlf zBR)vEulr0a1d|&?8-jy9$@=*|<71qSr#A`w$uhokXmMykAc5_T1CY5f92$;Kt9V;R z)~LeYQ|qHKOKu{>#&n|qKZP@ZlO;8_-Za6QP(jM7@1McEE_9|w4%pRvD9gPjmyff` z3hGWyPHn5t?N`A`4LUc=tEx9o-iO79hli)p*Ectwh@{ie?rB3+-Xm>snNTOQibDhO~@Vj`5}o$TEG^bCU6$;nXukjxJ6k z@097dP_gd*U}c4$taj&h6Y^$AaM_rWcXz#VOb(6)LNi6p`5< zoRnSVJzNcL`h6eq4(%wJy$SD&vHIvZ;q$?oBXz*sxV;0N5#nNeeP+AqEttIFQ?#`_pd0Et>_2WR^$di|qM-}I)#2N!k^_jD*&}*X2 zMxQ*RmL>5FTAj`S6z)hj>_}(Ih!Ky29b63?3aOL#ZUs$M*65-@NUJ#mZ$eudoa9j| zMKg;}=GLLxrz}gD%OuKXY5dT3+Y*Jt4A*Ob8oL@rZaKifScXwy`RAbWFE0&+36k{} zp{-l4C!n(u@;@>LFC^02*N>#rIQq-}m{DH0txv;nS23uG3dWtU*z)JOMGs5$y!2it zfw~huCEc|;$gc)z=Lpu_-pz7%6Ln~>%+}quHux{KZzC0NBfP=uz?#RAle5*jALwgxqmy&F`aAR`I%ovynyOriMgUo)&CGqsj-s}IC$Z9J zzw=(JVysT8vO0nJ*o7Hy?Mwmc;ta}LKf~@xHgik z&f2&4QO-(Rs%%tU-Zhet6W<|Y$NAfCaPi$C%l{|vya`eN3H*Gn6KgrJ;vjJ|9$ z7_O?j*q^f&mz=!5?oL9yNTtJs2^U) zA31YZB~$O&iF&2eY4!&S;t?*cvOdi8OMRlXQ#;*iP5>8Ts<9lwK~oYBhf( z9~{l->YYQD7cW$~OJaQz9;KQtP|>1gdEDfUYUf7&Np}GXaw6fZRe;H(N%9y*9wBlwq=Z4-Y!v@kVDBn%a_D?bxBl+CA^Zq2p zXk0HuG&VAS=Q_A`VT!4QgHCa)4U1+<$>-!pU7-Y5r|06TZO<>Zz^F^c_7-iarza3$Z;Zi`|gl(T{GFKcA(KOw8D7mdHLlp?o18Zd2d-kWQW1D;Hxb zQExSWh{rOWjS;=xXVN@-qPt>Fsu#k6gl$F%DGW!EA6^+%{gEb3M=`E-iD$5L-X*%; z3*xL!B=PooCp81zCFJzsEB`fgra79+kN+%grgkphKe{Eg1dxJx=Y!io1r~CfOf-^zDylJAo z9zyw`#2M#E{2ROdd9%y5{q|QK4c*=YW1z1xdsC3)H<3xp2n+dB(YTuB(U03uep97| zo)tDr8>Qb>LWO3O2-;EHBlt8D!Yf|aCvCy&^_=Zdwtph)V+GO3A!IYV)brm7-aP{3 z${z%rt*x);z7$^1HQHK#EzWDQ70bAA!}aheiJpqK^0){@UU4W9JVYVTR%Ryr@%+uV z$u=;{w42tnyE2rX^DMFl zABEI+nsqH*@L_hyAMzn#=gYuQt9_Eb5cXz2&{d&gAZ61BWH4d)((k_WJh?+vrf4D; zcjyx*5Mo1h6kD(och-?sE&o}Iwx@U5RM6D>07ti!0>5HNkks5hyUXQUCXOR0_U!{- zf7N?RN5F5icHi(1H8j~2iE)8DqF58V?|rnF3ET0`?Lv-W`B&Eb(U)EN{qC@KxeCt3 zbdl6-Dgz!#L7twuyRVq272F8!pC2*Eou93?Bn%h!WMz)cBo}@}Ay>^L_C_LilF2L= z>1WTnGBBJNw4-$B7-(ZY|5G5K`B1J=Ijt>AzJ$lPd`Nz!EvvmneroWg_t3M4tF2Zi zJABiw@2$_45giyD`UJljE@%*mstJe5EAN_$mMoP|z797N5~K{Aguc>Ow>g}X+P1s- z2n{SOORT$&tmfSF&0SAPk!3=z+I)?=fAC1uxAB|@wxzAPIkcXgQ+nl`4GxU6zjbuJ?$M-w*jXd3`=PMi$K~&taf!h|8DIXoE03IT= zwG8fhO|%TEu+T&|g+JYouQqO_)et8d@K(4t;Ehn@vVK?J^I6u|>Fec2E>cd;bw_gp zUP3Pxa88XP+1{V!o_LZ6JmLXnV#9}u&au4?<6SDurVgO_LgPy&DCYa%A zy_r{*Uvu_KK;qwP#lLb@uc2pD3RrLdN%UhW|ArYZT>$~yU#RUkzjJ&(Xn=dmrNZh3oR^m|S6{v(5q;p}~%q5W*l@wZ0mPA4;w#%<4F;ik^fL+qjjtqR8b+TMz z3Njk{Ogd|&qM32@_=F&fGyHriw{erGaj%{8d6&I88)^ZWGWA=xAK26!?>Q&JzG9xV z<|7cm%7uY{;uu6M2$hB!LMhM4{6fTml;K^9SmDM<8ZcR}oAe;bGHK^?xyF;6g$rpL z^K5c7RmDN!poK|`x&c8(CiB3cE)%a4=FJ>JN(ie=D9u!zBR)1<1`cm=(ff2!d+jcL zjN%rx#3t*OT*>9~K?K_oZhKy=PaUWl9#qqHo7{~xn`vsciHXZ<%b}%99YH~^eGvtX zhKS`P!F|1Od-U*m@U4ls^1aNPmtyE0X!eLfX*E>kW<0=GU$%e9sx3!#-U6 zth!gHtZWPT)84a^6g-gr2Q6TfyvQ0OOL!_rWx0m8b|Oiol|KId;d{}fvwVFEb{`is zy)L;;1-|K;c-S=0TzM{Q$7K_^cHF28f4MbqINj#Wnfr&_F^sHj>OuNJ2!X_y?29U$ zF?SM*{n&QyXp{ggu|Fz#UrYOh*&RxHj)d690Y_yPV9J|=YX-^_A2mG_Y;O1$k-`u~ zfR05D;h;*P!e@a~g1@$YA8B@(VXFWV-{UOh_>cjm%eCH&w|Xo1^RgY6VK*X>c z9ZTFQT;Qkw(DcC{)FpSh7R3&lwmTcVm_@_*F7Ftc&v7MhJ%e1VO(#j%)?TY-7z3Y= zgszlT_e}&neveP`A6hxA6({fRbhWttSn(2A!1eYrIF+N^v}ZJ|SF%HoStEkVm%tY; z-S`E=>RorruoPP*jQ6xEB}l0F(iZQw0{;B=`Iepc;gb?WF%l}_+mHcLuqnnAl@eY1 z*lb;if$;j!ny3`(&(a(fjF}Qi3*X;_|7q04NEWJ}zfP1Nl98pCqwA8S_rB$M_fUe< zagXqW&d;RB-=2gEWJ@(N|YyhJ5cvjUmB zNY^`x5pKxuB>O_01{v$|oc~liaRkt_asxJI9X!tWjElahH})yVw!7h4lAiC;R#|tZ z5lz;=v(@ohMs9VxVB379wK{CbR+AYq(`=#0K3L-T!>p?%T@ds8qAO%c6O2l`|DC&H zA=jiFG+M(_$GKk5U|l@Fwbj#1Y?hJ{{0%MJIPsjx1crO!wQ$aUO#bt^N`9YrE92!> zYJuKNH{0WT@s=0bKxuXL1P9JDmWn$~IE~gENfk2h8bxB#4j4F3?sN_c^_4yoEbiwb zI2JOVl1eOQDBMN2CB%Jxht8P4`{dvN9Kk&Iq`#l%XQ*bAkk$HTX_)HvHCWq4w=cR# zpI#p&^A37>(?|(Q|Irc|)-}U+B+YJfy-c_}15>Fl1U@+@&MV9YTlxkt?!LR1$OYqY zDA=OG8>VupeHAuJq1crDeN(I|!_jxSo{(A>HT{y&_eVG2?9m!uz%eU9fe77Obz-h@Jjl7r-vm*IrG4R1ND(6SggZ& z6%OO8gA$zH znuiYsZJL;Zb3c3AD5C&(dn#WRxiKC{laItDB6KX+?D}V#+`k~8*3Jy0lL>x?_vxEPmzl_Yc(~qb zCif^&SPriJc=v_!H%3rb3j0P@0+lU{Y`7$RPwVOZtc}k;AHk@kGK^Y<{rfLs4 z&L{kdKBC08&NNERmm)bFI?`)ARN--r#-z;n7P2^rxE9RyT&R1NySaIBe-Sfew<-tw z?8Lz7TYl9KLwItQqKeZ#IH zFf?6B+*{1nA2*zg;EWErF9s%UlGn&zET_ zoK{6IBiw1QDe45VULJKF5k(S3sX}xd-%75^2_1O{OFbo*qsI{;&1y(wOrsuK;^-e( zzUOHGw8BVnxbbe$R60BYD5ksPk;ZsqaBrv;9?h!mbo_6qd06!y(IN`LUsqC^5c#Rf zaG87ZX@BD*yX$yTs}>E?!KAuCe!hRSr`25lQxVL~42BO|f7n_XL z0rA5Hq!|tA|8f)*PK0fRnZ^RKATE3dQ|Vz+V!V`h-D3&{CK*cGkXV*?6@c&lhN%#L zy!@!dcJpU3_>7EjO6#4-*21q6rL9Rj;!W~djp_U3ONuy8SzHpV1f)jl1Oo|qrjL^g zUPYpGmwyVCRTk9}=go{*SdM75+3m)6fQr^lpZF7cti%X0zD*0W7L3(GP6XTua%NmD45SZ~9A zE$%+uHN?B-70$BW_e^@41d39X#vTet<6q@+BsH-<=^DCir>l$@3nSQ%$qA1S*hlU8 ziXJ@tk9>|d9Xg4-zwcp7mcda0Va_R8Pajpo+8YLp6F+XW*&3KmefeOUilD#sp6+huPpiyfEwhFcGWW1UfbxXCK+A+yK)}F+J$9D!e zyp_GvENWLG|iL)51!u{2R2v>OwCPrTyyn^7$i$MpXj!ReXU&)U-~CP(`44O9hxW){=z ziOAgoz2o#mgp6kFx}?gaRlsA(6mXHd7k8tY^l8YOjwuX(MY4>sp&)+r=T{7MK<0a5@oT2$wcFLECagqkB8sFgaLb?xy*he9bLqS4B5 zzvF(liW>nnc7F_^pMa|7&koZO6dt<+a0=P*g^x`R?MdeE;~mf*!h5Csw7y63hGLWV8~rfEUD~YQ5ZH z9r{NeO}1t%p;M!*kNlvlQ;x*iUnw^}fRS$0e#NC2etX%GdryXj11XJylb=wy5kB{a zUclI(@X?$#h7fVJjDoGuy7|-xVjL6BA*KBE7l~yPGzWB$>!3V*{%K3=QP;KMrwYeb zkb!w8HThbB8nKA#?^Oc)AWiLLFTs^xNaDqD{c63c-aQlfjp`6S^4cNvrW zbG7r1UoW#k7n#*$Q!WJ?yhf)F&fnI~><{&&zUi0K$Hb>?l}ede55QkakkZ@!Ou%lw z5+vxJG36@~CfpripiDdzJsk^5?OZwE&(q73)hihv3XMjU9dc^R8H1G#{BV2XG3AnR zJee?84^$kR$==qTR?DZUFQt#R%`9;QYoGbssXk>DTK=N^Ilo>YCtKqc*@qDa(*jEi z$q1^wD$<6}Lt~2#9T{!09B>H-SfWZek`zI@a>=DW|J?FQ94oT7e#-Il!f|Whn|$QZ zWa@m1D(|WHM3Aqrez&-kMDQT~7f!#Vzl0*LeXczg(HpNI@d`BdG%1V56B z+l`u+IGplgX@etveSFkB?cOs3;!$ft+_6xOmalo;N#=#mEf|Hh%azv4^vT>)e$7%& z;LVg*T?4z>wa^zd$T|z1AAG51tRy4|-cVtS_d7Pu5CspgziX^l7G5TMyw$)6{H2h> z{tK0u?W+ky=zP4(w)K9`7pH%nj{^q#$Ghf!(U~m;Jji*-0-6dv|Kw(ut&O*B+sVb- zTMQ+qL26ptcdO2V26|4sZ5z1NmOr01-l-w*yg zi3cx)?7_U3(f5;tG&~L`+@EnZm_S^~A7{HfRe-D?a2pdwc6V%sQz&YZ0rRBDB zaGYJmi5zcqY{MP%XV$?4sZ0squhq{>@uBEN{50ofqhTuP7uTj@B|x{Wi7?r3Zf^8! zMT`55%Z?`!FD31w!iFW=wpu5-9F`pE{8qC^t5R$cAMI)$=yG@wHL6~%CY#`y7k2werqz!5u!X}Ebn%M)!GK1?o-lJi`v*vbp5@FW+!hpnt6 zYj-nO71X`QX}_KM`?jM!jAWEsVL*nYlV*ClPZ$jqN5p8U7q;+ zhjU?50Ar}C8yv)QKF+i|mxd6l-wzw?2Fu-2`Xh1tsoeqPQl$yu?C2z;&_7;IHFoCf zZsnHk3yYL0aVBrnYsut=x~fXs_~n7h4Y_VciQ}j5a}%lw105Nfk-^j@`<+Rq^*L(< zZ;hL<0FC^YFDAbo`l2Fbrmf~#Xl5JDtpycq499=O1r;oT4(DK=N5PJyXTStS&w(5*uuX}Gj5EJP36?B;S4lV0}6Iyd7U@!Rd>M@#u*up~MhIU853^z+onkc+sF&$*7fcB0#DaCx_4(Y=9*W!BLn@F~9*HOrO)#rn z3c5)hz{!ym5m}KV+mG1mqqXZ(Qa8e0y55K!>a4P1Q4`BQ#fUS#(re<<8Q1b; zubpxISt@u8@ea26&)v4e8m&%zQOvR1gfquk!JnNwcFUR4wX`0T_p#6N&bh}Rr6DD57_J=cHA2CbH&E@%wK})%qgO06KABs8&#I& z(*}=@U7Yn9I8+p z=XZO*<=lckcCVC4nKJKN-R0r7UuqtmZb_L3;!4iOKn^NXwkMD12BIsg+A6Pu6uzteoj@+roCJkjr_`Ap?T>#JUY zYfNUd%&R}O<|Wz|JSZ=;oml6U{#$e8I=Kw8|AEECjJ27dx`T@_o*RACLa6Gq9tPZD z_ZRbJxu?kOz2;WdugPNusND5hNP8uNS2ZX-4Jp7*B#v4{HO=;NBbQXmt*BdPoF>@h zlzsAz_wPvFz90Nrq5MX+uqpbIh&~%VE`7>*JZh>L5w<=Cw};B6Jcq6{oOhD6$&6a4 z5%5t`c8uaf)81pW>B~Nfk9qq~1)Cxjq8VG|4CpifEOD_?BQ8d%;CTkzyp!_0B`8)~45fX| zgtRWOghOus4puBZFn{yCtE{Mqw^fk8b^>)TqXM+bHHCa-3*g<|n|XOYP)51x)s(TD z-%v95L~V6iF`32@=iK~a68_JVDy18KBSOLyFHC*?;*^BY_3FS*(L98*9`Rr_>C;2JJ%l%N9BJ}rn)@YzfP|DVqoI(1>Pjt4&>?CW#L2)L6qRGJ-6`V#a)wH1^zbF$dsRjO$S7I%XxI<2$sk##Wz>v_|tKOHDHrhr(YrT;nq%cP1wWy zn6J*WzIF)R4cnbg`=es9pxGl$BWqoc#J-HkqD~Cj0&j+kqBC^BmHVvFf&iZrGj*tOONTAH-dll zj2~I`Gh#~Ib5+32s_yD9vL0n>8Ivc1ZieJex)C6)h9irDRB440qz6Szy?jx|qEWNd zkVGj`2QO!AByjU_MRp2fS451w&&K8KrMB_?R9H-wf|go<31uhRLpznAh~aX1u~;L` z2OH$GWNc$SzPLLBouK^Rum*=ZVjvUVk27o9uC&V(HYfc4dqE1{n#7w6FHhVdJ#@4I zNyCy4WVXlKqXpzdQo;tp9jz|VQh|mJiUHaJ>Iy~IP6o^-LJYW<;Mn0`9)sdh+(itd z@NkUd{yj}N0Qyf1mBONsmXBL2nVozK@1Yv-(77PM06w7MORw8!Uk3+K2tFDF0ShEg zXJ=y(a`iUf9|VZjgphK*=BdjdkRy*1I@*1{a5Kl@kwHIaKN-J&`g%RCV7-m)nE_x# z>Bu3k&&AY78-MH^+V4;lmnz^-dj)N1`9mYd^|f=oaKZz3;;KW<5@}Gd$5F88&}m#5b9aBZ*6QVZ=Qm2;N2VmH(9!CJ=F5H@ zI0FoL?jl>42tr}fMqGb6JU!8k7?AlMVxyitAoM)ox-HBUW(-dz&=A=R>b-fI4hq(y zuR=MyUiyXCNKRw_`L!j&0bqDggH}+bj|w^eF42ZaFBsW}Z5r|KQoLXr zg6!rcPMtSUQ_CQrqvT9s97k(Rr0ATNcg!{1FFjn5W2GxaLT>q4No~ednteizAZ^a2I?~8j+yZYL%QQs-Ao9c84OM8Z(+lA5@WK@-=$ykWdm||1GsdcGV9YFY zw?ki&C^7u0KI!t(4GExSVLa|7226jBlKQGi%Z@;=&)e;#v_HJh4q2%GwopC#ZyN(; zp*X#7v>nk&;w-A27H$`B2ITWYn6#^R9c?rtQ_PgHYiaXK!f_^|J|Eh4O0Swa50Xj4 z#%e+-X2*`QE86CF5*Ef5hnj&+vNmc+-183+Q|u_~zOKE4F$oe?Epc1*Q?9QQ80(9wTy+R;jxX^^B2Cdl zRd>cGi;4D`cm#X>(z5JtC$)&W`C4j_N66TVor!#utvG;0 zE%8rSn?bCZ@CUBh-W3fe(bbp2ufTGageyU=q*_7>p-Q=tz8F3F@hcehHZu5e+2Nis zeLBYauNX!D5lLOJDzVU2AOA_8HVG5R?m*a6Lat}6Q6 zsQesg?0^?PjO6F2QVv5L9G$&QjEqc$XyXEu(zho+A9WjUcR;C70 zs6~4sg^o6N8dWQqMIl^Nj9&s24BtDfGBjOM*53*cr=4FplNAQyw;`-07h#VtcS-@H zsXjg($Fqq=#J%(a7gQbAiLI`;TJ{E**Im zT8CvoZ7l;U<7S^=Pf?vOL6WkgBj;ratJ^yk98g8Eppl{(#ERl^6WO?kqX&^-S1Q|< zDy(f|0hhaz^bj3njycJMAqG@ zzGdo0_DL2-ctbta8IHWUAHV+fz>&X}Umq*XATNr}uOymZbF=n_Ke08gj5Mxjy*{BY zgWZkF2Kk#Z!Wv;vnfFoo^>1hRoVu%Lq^~2Bs%=hKPD`CESaz?berKkW%b*GU!x+Hl zkAWkxW4Km&%=Wk^XfY8&8B6fU=-{!Jt!@! z*cFkXc@Mhfl!mV^*lqmtZ93wlSdUxN`$W-tt!%g5T5lmni@+GK)=p~zCGzQ@4mjdk zuMJ26#!*J8y}gl5OHzTsAOoRud--f4dWg=B>cUT2-2XJW@T?Kr?UK3zV0MQy-+-ukpxq+s~+dzg%D zex+$=hlY$dNsGjDi|4_)LTWRWP#3v-|G}-|^~Q~A1?zeu8We5pphnmFK585Odw?M_ z!hj!3EKwoR_@ZG`=qE0oKcd|rZKBMRSfXqJ63J-y#Rz}>{r)6hyXl25fww>J{`{s} z5l_K5bJ41S9Sm@7oqGjWoKRJ63K2vlB;V<0p05SO4|==WZo%)TL_cN$diiWX6{B`x z;|%MBovaNq>4xAx5-z&pX3D09AE1V)_`_ba+q6M(=bVs7*6|h+`D_W`Gr{mU2>N^Q zeNQpZ5^?M^-3Ec}ApLHJZ(6V2DMDuLoP_9NAwJ-M-g4ts%jM&eSsRz1XUG-X2G3UC z!mSAJ4!+#rU?+@di;Q6-K0@uG6-(>-U-GdQw19CZ&MrQ7mlOCHOWD&ThHJnMpv@)B zY`_ECk2MwW1Kzx%5K_UM?AByARuVd;bm{=tZcCcmlCJFbe30*(-LB3Nk?b<}fI+Bx zO-@$yQCG1EWPCr9eCF-1VO%gMFLyrD7zXq^h+$Ya@10;SIoxpKW^v&k6wXxsJKA19 z^mDL>W8@&U-l?v+HsT`n4<|5Th>btwC|{oBh)HM)^I*)idYqjGvMzjQT&IW=)oe7p zY=*Xp3A!QGd@B$4SNg= z_nY=k(K_YM?+POOO-YxoLVQGjk-O#*gJxMLyu%qOA(r92#As?_in__J&T5T=(ehe) zx!vGwlishn-~qNv$njdsbLaTxj%H`~%ellO5SxXM^n~1M(}nKS``FBJ;jaY~$Z(bp zu-Z&ygm0)s*dc{1D>O4$>;bM9mBr(o&rEiS+NdYW0Soh8ZnVA*-lC8se89lRt=9NX zzP0zzKE!bvB#6x)1HO&M^KjK}j1i1M0ULVk?=8_7=>B|l|9TNI5*q=!(zh&rv4SGPxjZxS_43VN5XWpnC6+ZiBimr|V-9?m_{}I1A13nc6 z@={kuOn9I{F8ye`$le~j;ZX0RjQKH|iW+Z(M+5k%sLfV_6y-cp_@q~=Uhr}MATSm6 znS~5eT5t3!xIg-r(+kZyE?p4oraSGnqFj;v!kM&N$oqjH)Wd5}^To|f0>j$Hyum6C zeD2*JRoe~YMUnvf4Q*@g{qFm#IiENyFGQ+{-{xHU()oO~fnV{e>0f=&-jSLnU{GOt zSz}lv>_TE~RhDMZ9O zyT3Foyf9uT1(9p54+a|H?;}naTlZZIwO2h zC3sdwxNAJX98T&-y;@(kSJUau(sISKTCMr$Taj?=SB8e&Pn-{ywaZqwr*9uxbsuR@ zwAY(?`kfs~tZC<>7I@`%-z()UveuD44}-YECFC#71L8a{u1m<3 zBs~4RW&Gx6Z>{iNBK;u1E`n;e`5-hMQNA56@F?i?huttr^%kJ%B@kTm#VW0J&xI0k zuwjhVHQD4a^f2ByN2gz6yjItwio1A0Ey_~S?)BY{pU0$<;`TO4ya41qL9v$y5vCB} zpZ^oodMBxlH|X@B8EV?jd-D{rw140G{Vu?f5To1@=1tTF5+N48dGP&+I^aL82kX~0 zY-2@E*=+2b*8s2)_dfY2&XeHSN95R1jek`OvMf?Yfr=g^VlBOgT5Pb8wlGqz1lL?4 zu%v#6JY#`?@*7$SokKU{Piyx=Wk{&^Gav#tta~lAWDH{NzW(F^mhl!`Nb%P}W}ho1 zv~j8MD`!L~UuVLB1K)5({05{7a1S5w6NZ5X0mq)Jpvij;Zn1!m35d}_rg^ zi&SG`yEnjG9hqUc{2q$7lQ7gyc!>*rKpm%=-2N)8FA6Ed12n+V2X}L};CNilb~TXz zMwb3bib4?3Ah}o|8|jUmV1 zCaNxIY{0Rf+>0oL=vzEbYNrGLrbNcd$CWJ%0p2Wf?Y@Aa+%tp)@V?|uEn9jlSWVcm zm&fg6zvex{5{)oLz`ldaxky@O7K$oORgzBrQmU)6@^IO6GW)i90 z)nn2a1AN&WbBvg``T_=|1}|TadjJ!S{1I8L==gC?b_PoZr_{Vt+?3zxk=*v51ku%V zN6Sh6a2=-F6>k14jAU_J{A&eJ5~pm9>d+wBynB~O)1T}Hi2y-yy$>(Hr#FE_DGDWX zUs>>bdOaC;@#QuHoFO_MfP+j;q(IL*UiOyuoglJ+mwQAvh%SGir?xIN@KEqt;nLyV zz4BMklx~FqDV)}R=KQ4X+7FVjn9EC$O{#+r3)(JeH{b~MvQi)aeyceV20aEEW)e{; zWP@pRJSzR;8V9$VP{%z6I}AsTHneb(Z+x7#;gw=|guu>u*i$D z?+>`Hx*+fR@l(?C(0usWUlnn22tfZ56mSvPY(g$o{(xO9wmwGRjb^@;ip0*gd;gE-VhVwl9&8H8Gp9t9X>P%Ps@*$q4a zH})9bQ?~%XmeJzZr%2)tVaC%8q=Um-oP6;(W^M5U2ZS3{swuSyZo4-pSt2pPxxk8S zEA_mH%W7figivpMD0mQhY`QS=0>P|n8K&>6h`5i~t%h}S4NJI6xdFO&HdBX_{!m3J z>#Xe@-!8OjC^cdV!*d4U_g8wIK0$!gXUfi_J?Ah zMi%;q#yR<9PB#O`x@25{cZ z@u3d@)9f>pBK*sHM8Kl@z#W;~#*XJsOXnhvKmZ^U9!g+E)Z^B@)k;zw%gWXA9%_Ex zxTw`aG(c4hTD4zDH*86cEK(>i-~Vz=3o}gZetAYSf<7^f1S(uuE~P*01a}+O*!~Py z2yWjYB((a1@$v?jN`*S#LviD^;f~S4vUCL#o|C2#3VY`0ps4IDO!@&fW56Pj;ZK0Y9)vwQS)ejqYJ!R-aeM75tRabCXMd`Gr1iZGmE@9jgl@J%>?5;`HX~v zlLdcZx9DL5>mH|jH9$y4nSl*1rN;_*HI>Kqi^}t;rOjF}3AC15&BaH~sN;T^SD$w0 z5)NWB@RZGHJ*;}!-N>mX+9L#@04cA$AY;diyb<;;FK?=0XU8zq?wD^1cz$Ft>PQcF z@>@mVByoCl8NcE5Vyizc6%_ftc;?h}%#2^NerCV8`^#$EClL0MHDaurQT5ovmh@a4 zpk#Pg)h3)OvDh~~Y*^FVbsu?EeAFnBY`7^HKst>+kWrc(!4J~m*niy`ZXecB{*yL& z8cpTlCCD!568@iO2b=OVW8K)8=i-F)xzm|Oc|nO+qIu}V^1Yfp4UirDuaeRr19mOF zax}7My;WW4)8IXhd7=bB)UjsdulK`P88Sj6DAQOBwTP3aeU8tvNhB$O!c_U zmgK4X9Y%k}&{F5ucjHzsw3)kqrIj0hwx0F?98Cdvv$f1*V+WuCbLK z^eP-NUQdpBwn-Xkr=k)NhFcf|b^xg!+upoce}_G)!ERjFLA>MBm*fbk-JsRE!p7jx zv^OBrPTBC~5#V`?yo+N@8F0M1vS$1FxV?1580x|NCD57j(0;L!)(HBj+q?)Z#H+b# zlUrqZoDDe6)n5aS~ol^jqAC@N1&qG$Onj$^-kw33{W<{WtdJ zLSWp);fO8I9?&r7?&W2!GXjwt^eP)MPBKj}{y`Z9{qL?zEmtiV{+sLKfQhR%K&{o8 z_geZD&j4OcX5evzk+?tP2Je~}4G=_4cNw}00~X|Gx_xneR-E?Nh_Et)L{+y8Fl z6=}0$yILA(sf`v;BwlWONuSW3`2J#ZvK>WlBs{%aLo`q~eo8j&T)Rq-?+k6>ZutcZ z4LF9jXu)XE7TFz}jJ$a@z|O#Co{t~@`pC3-Fl zdofZ!ejQwkcKPLG=|NdtLm52?L|SZctUgwq`-nx|>S9RglAhiwr(f0*=yavdS-}^0 ze{>qF9gx4^vN50QIza32!};KKA=tLtc@Ns$(1!EBrQRo-b_RmnRqSV)}&bkNe5y)4z`#gg#&Vpc|r@9mp-2 zeON6vH}|;A0&j~o)9<+UJlrPXnZT$e_~_a&wt9?le;acRVRS~w6H;fMy3#?}u+mBb zGmU96Jnv-w-^oM0+a#U!tNeMKW3n}#yF>Z*)D+sDQLetq*TanT!5;>hjX3T*oC9GB zP~fm=oaEcd(Yeo#I}vuzuGlzomQj}E-vORDY?i@xrFeGW`SODIHpcK#XDD+7-Q|*< ztha0FxZM{*9mbdUXDg_icjJ*x>OHibAhCveig_`cP zaI$S)DZ%+Lfs^+&iSt|p=LzKBD#7_Efs^aJ%W$$?5+{8v{4O40)Ca>c4PiFo+o)V? z(+&N)yf;L|Wt_i({^&NY-&SzZZ1CL;PChni&y1f(c8zH@6=#%}or2M;Gro6t< z=Y?<_ciqMu!lR5A!N73=`CJV?AC#1>McKoWvNgFfaW3M_r&jNrlG^p*oER~PB02DP4yx;;(BRaM)`Ct%_`h;3VGQ8 zA^5Fbrtlj+e6P*aL-Zf`){DdmCj;ZaYQXZoy~GJ;qg5noQy3>W278Q6ii^6Y-eP66 zAHbq;teqTsDpC_jC%{)eza}DDY1a|=6H$y zCbHwhEvjwCcgJS%ee96We#G2sfQwygKN0jqS&;o2V)!kNNb8EqWe{UPSwPe8tDl!bO*;Smk>iLTEG#QB>LC&!AkAN3mI)b9yViV)`m zz?{VvvpelGgEC%sggEzmIty{$PvG20CTt3E9)UhdZw%!j&PnK#eiq|%1L{wsjA#X? zDBoj|MHZ*{1j}XtGhj-JHritIxvPVdHXsan3T-sP0-NgKhm;c zhWcdepdUG$!Wi9;v5xadw@@dvQOZBbW0@}vTDiFkao*>BIKa-LEaY<*@v{u)t_03I zkf97GzwcUxb0~rHEZRdE&P{MAmTd-nX!p?q&T9U79{31~Y1%@2pKOTp9B}1*Nf6QQ z#|k(lgKcF9{=k0hCXPcJ?SeRE`lNr|wsM4a7wqyM;$&RffTEax4uY3{lrx@(IHyIm z25E>BV5R#_;q#{xIFG>R z%W$r?K2Pw_=g$;yR`dBu=!BrOeTegXL!1-9S?2Q>3OFT$KF_%s${zFitq`XyezL#R zB)(Kl_VEOtmlPrP1^-OMrRyMF);2FEaGp;1=iP*VUP<7*n83-o?J_>ECUA27Mwx%! zO8ER#0_U!T&+~gptdH;vHjP)J26FA4Lf6|VjK5xT6r$8@; z^G*Wiaf_2a72@PP1HaW8!+AG>^N98Na}hpyFY!(ZpB!Il3Vmt4_4ym95c0`yMX~QE zYZKu99Hy7d@Lj9pn3T%jzJ~oWR=vMxG9OotA zY9Bq{hFnr{jLG$P2fCM6X$ZkF#&a9d`%fOh4x#E`kdDo zK!uRcd&s+A!sl}2Ke1&Y&XtxI(hPCZw#?szEtGu&%9LJ+^C5w33UNLHT)!<7oWg)F zH;VK!6|SoTLYZezmI36@c!|TPuABI;wF)3LIJ5JTY2+Pyy!^hIdRX!$p2rotjng7If_HxlSL zUq-wtxJ>MmC8r36@OS&k#doAfNz_q%CxMhETY@E}vc=GYfmh8x=FxGm)&qACR}^e{ z4~(M9Wb4{PKfxN0+rE)0JGy2&d-=timNqW2*pI*~qfTauUME&3(E=4QqbRaf#q-HcUz>gJQBHaY=13^qcDg1rapIyptK^p>%a=Vctd&%h8hDPOmEp5RF%R)4W4q%ljU(hRt9Bhn9tk04WR$11~>ZMW6c*r^@WYn|L7`KdvtznWsSB&71j?j0|y7_@yy$;97V` z+2Z_Zzl`;WQ>wcuS2NQ3L5@bJ->&+CogS*nrYmYH{`F)GSJ4HPzbaoq)Et|KIy$?% ZdRzJ1T6vOq;Hwnlmwr2I`~?62|Nks&KcoNv literal 19171 zcmX_H1yEc~kj4_+T^9)+oWSA)4IYBKE(8lsSe)Pv!Cis`cXxLP?k>HlBOIK~+r#@tH9=0!R`x%rxdhm`*g2^sT&--)srmRh zsW}BWxVbsFIk^O=)#Rxatz1CV(&kn!Z+kHm5dK%hhcEw2;2=oUT8sMvTjGSDgioaa@GC;JR*}8M~B`^to->rGgU-))^V(~o>y0f9%&&BjL z(0ObSZcixdqk^#)#2Ud2VSf>FDgdDL*%EV}X zqsQZDVfC13eoJ7~^udQ}#eW+L)f2c~$=yb^nziyBDc#;~&L)mPm+u_&!N0H@7?9F$ zFYmxI40#D}XzsM9;;;91?DXU7bsJDOSJ=3lRdG=PibT&vBo2OOj@Dk1ADOwuy-G+1 z%#R9Tue>{j0&qIDw(h28xWDX+Unnd#y-M3EZupn`V?_VBYkwNSfySaFDTBK@u^8`B zN;(>L#)pmEx03O4YA(u>yE+$XpT0(1WPitfiD&EaEs?%2e6_uNxM2xy^1Ur6t`n-zBA;kx@HQf<~ zlbSRBJX@_6^DoA`L26OOPlNY#+Kp(%pB9Uy@GcS(=oIo5W{}hF5PKOFuh|^REjuziKwG?cY^y2>_6rta$4~|EZ#7huE+TjGDih z)tE>b_JqP~DuWo6`Gb1f16kEDYuQ1~RL&!0@?3dVUlS6EA+barlJIU{8lWM%^p^+e zv2#-|=NO~&Wma5OclSVtS*^gv5CuKW+ti=Aod&; zD*-2E`f0z<7oA|G)q9_TDW;`0H!x6~3uj#hvtQ`{z4%zzT&Z$$U}Hk@dG%HT_SH^5 zLx*p39;7_~Vbmj!N4!lX-eW!or!!2vFP;p3>E(p7-N%Fx32h4IHu54e#8Gk98_z&< zI5%3E+;~zqK2zReFf`0Na0?dnbYi$q!$RnvmZW@Udv&xRpTT2M&llu_8>Glg__ZVz zu9S!{^LHG}wU!^OeS57oCXLg@=}Z@&dxmUQswh32uiEc|aGZUc2j0his1EXW_c~%@ z@n7|gN%SWiaZ&+lU=ZHgSK)5#S{klAH?REx;?GDT+TL17G#M38#Y~a~fe~EdJy^lPr@de; zdvN8oEz=i=`vUViY)W3vG&twPNG8>*V zR+}PupkL-4cHhjGinJ|Fb3X~8NwQho`5rPX*=-s=^RvZOh0l7a+V==wJS3L%!#5Ax z8jy7*>7Pz`AzV5O-5h2KSTQN@@q9?3Y1Hp%U+rXf?6xAo;{c689iR9DMjsBoX!T%h zm5x0XL0VQh6WCuNmhG>JamJ9U>qk_0PjNvXmA)3ArmgBpUyDHKFn8Q4UT^f;kI-z$ zY(%uA<6@DEw(npZ9S5fho^!MmU()ZH^9xgj+P^(1Qek%skzZKh8z`r;sD|P0qwzEd zlfQE&cy{)&2}%owrBhEv+sbJh`~nHOY+bf4DmJ!2p{;g^7`R0Kh|9d3ghblqR`?X59-4jM99Y`_CqbZuDmcw}c;VS2xyX+Z-c7ori}D(N(r23yPt}A!4PBL~xey^5#PW>BN9_R4 zgkNr7{@AaO7$rtA{bs>>0lGLieNBu|N2lQwFa{JA>-Y{`FMx^jZXD-Yv1wcJo+d4?dCE-}V_378 zE4^GDSw$>-M`s1eLC%(lCIJ&Z@ZDc4QNK^D*w#I1d+$G)jFSbVRauyPR?@Cb%V8+f zk@$)~Uq+rIf;#!Hzi+3C!=m!TIqNaJTD`L5fAfcq_bbUnaXAqe$6J2AbzBMgukn91zuzS&fL? zytJYoOZ8}QE4FzLINv6dp_QJXYFTDQ@izZ6hQEFgCnhGP@PR#JGpq~nhOHEah^7de z5K$q4L#ocU3=&j2I2!Z6yd>M$!pY%{mz3h((;}%>tj@6<(cGu7YuMy{F;Dr1q%ed2 zk<1iRJ398muUR+-6MQl2-g!%1Q(2`R2B%rSf`$)2X5sd=mt`=;lTS@wD16#`T1aZn z7$1#4>Q)=Jwx+Pu(SK{06)J2^Dd}5T?f)J+2MY#!Shgz?_ilw}U-{{9O!uq9W4~>z zs%8(azV`fQRq|x}1=LFPXk^&qH!6pxGwNC$G;)mmu2>Jx?|tA_hae_Xyb9n z8?D0eurAJRLYp2%S&8ZW<2C8$dd7j!BTQ`S=gA)nQ{Ne1gp3f@6BRJFIWp{@0$NSoQ+W^Al(Ik#zbs6qKEs7eP&k*-p~C&2R~MN{jm2 zY@HGJuS_*cv5Y?ea;&V^lwZ)GsY(4_QqG#et5M2d%9w&T{sG}gSUO~C-`sFtwbv;7 zR9bb^8GgKDNM&5#&)f02(K6EheGIOpDR*qJaMHKITa;2|5 z{{*D$Avl9QxxejDkQt#(W9lZ&skVP{so*1z(Ym7SasD=qT)B% ztMR{CafovfuBmz-vM$3G{@px+q@%8}`>w@3Gb<w5>$^!E(YXKSKw!;N8pa|-`Z8Bst)w<=Zy=$-bhlJ`Sq+LtnUw@am_ z^1Q_xd26d&O4LNvA+cYJ|E%i0`Srcd-rP2z2^uTvPw;1RN zdyfCQ=s&~7o;D@z6gh+r*1?Y|c?|L$7uD3R2SUxrr8u1*gvemNdrJ0P9Wkw$bxd>7 zyOax}gj9_Yc$N#rxV)PafB*40liy2JkAYjw|MZ{asQtOAnKs+7+VQ}{NKT{Ke`1v)48-}G^U;Mv?{32j-W%}Yj&5g_~m^+tsSBz@TP@H-8gBhG%@MUPzn3M^e zU8QXyzYbwfdQ;3Q5>&YBEo0WqR6S@qdL!Cgy_zqGL$6+f6^Ked=MT(%n=vJ*Bhv=` zJ`(@?^&4dt7Ak60CZb-$!3dX^a1#0sYXJad2s1 z@v3x0YqhmbE(Hw!OV!eLpVK;OwG{1lo1)DM)I=5>cpH`-BuWvZfVp%2ni>C&#Cepz zyXH_b)+II56nS+Z1{_LNfT)zAKX@T8dwNl$zG3Gxy`{xT-twPME!NRDa{JqB~|lo9c!1q*Z|Q#**~t9C*>jID$82_pzfzzFm2rL zkafxig%8`gUs4P{ZG3kmxc)A{ z=okAMS!`YD3!x2g_J$_%_bT0mKIGO7Uf~KzryhZOI)$=@v1ymxq04#$@8}O6={tT0 z2Gx{5wMK>aaSuKSXBo%BJxEcl{GqG^0b+^J>aT_&UOw%zey?Ki6Z-79M)!64Ts^9YnDcZe;#9B zW;XnC+Q>RW+E99t@p!SKqbmjiNFd@B=D7_>lQ=%76j31gb14m(x>MCC#yBw8UAYkJ zTo2Mpe=Gt>d@Z7vA}o5QWOet*Z9Z>wJ*mUj2j(h>EPrm7W5G*P@f~@YAe^aflmx#1YMfOv@3Rd;l^ zR2-S;v+pMEI_Kg${%Ug`$@L?F1Xpkx^f2VFCZg12uCYv74RNjq?nq0I{Mi){>G{8w zPo4L}-p#isYsK7Vj-IY7;QL$rw6q&iqsHF9V+R|w-`~G>>Yh0p!WU?^7#w}sT9a&*)FST+3%D)KvP%dqn20bcpa`7iNedHDIs6k8-W!bzKtgjo_h$w;Owbr0OoS(S=%koc^S_YXyu~;Xs4TNjf znDJibf>c(58^jz89IRhvnV(xIv9^$iQwCK{S?`98KVo{J#lG96mg90`u(e8~B-H%gE#%TjU&_=AhOtq?x{jr-BuJI;QuU{+-mu%qi`-dtiD<2J8RQPVLbN?qE&Lh`vT-bX`!M|ygRXvayMmibGb)*Igpy~H z^Fq4 zmZs7pH8f9rWd8kv8Ie(1#CxYDIk7BPw(HqHH=Pn`CF;`4lOQCk zl7`wv9eK8|h`MS0X_(%-)?EQNTZ4pCEc45uN#VnNr zZ=J}}f>de?q1Cjl1)ma#H*3g7+;;Qx;G<4Mrn%yhc@wYPhQ878eG4t&-u>9)M@IlAi{mszUr1T9JuLnXL(k!AsqcZhjYpqsANWB!wD*` zqeb7@gtrw<-f~Q`wwdCw;ZGc1h@1JKkSa!y$)L_W#jy0FGxLC3ic7298bpk*2{s~%ggYBpi^ z_s_|{D5C0oDgDHJwPcaMon)+V{R~$flCHIVDD*jrC{ekK&7?c^mk4JglF4CpSC_uBhC-&437KDWT1k>%SkDRk*o}JqtQ>&_2`9hW+<%+w z{7gDez8!rSp4UIJL*ay`nONs5=W(XP^Nd%8d^k=|?^Vp%mV@W=M#>n=D)^bEus-h} zOs|%P1=9$^9Si5mo@fA^9H%$-=j#PGvgJ5qdsG=082|7~48Czbfm_LF9PRSz>Om>r z=R^+`WW4-~c&u=`/pJJ^#@z~k@dO4?$^q5$DKD64h}cQJnavRNRqkBh|6Y(X9d z|Ft+(@?53hgW_v82iqqfeKgXk(JtGknSugTg^1RR9OU}SYa^mdW?)x^! zv3$o&*zO8y;oHyu0*A4iQ2r<5GPNhXd|%Req# zySPhts|WEzInAY0I?HHON~?cf#u#+6*-bs!)bcvPd}q7qapqEJL6=87S;BQ1q$K@P zf+8t1wAI4Y^q3WW6;qlgY27dBZW!dO8f-xLFzqXpC^WNW`% zjduz(&W)e(3&SEeFTWN9*v{4G-E@y}9e&Ko>iH7n?pm()P6qYXxKDQU$bd>v;c@(+oY~Oj?tp7A^l?V{wcf7w?NGqBL1hHOwV&XH0G$~B zrs>Opux9uO7x#2s6C{lvu4;-TKQv6{cT_jIIps5X8|dZ@xYb?9tmJvPrb0*qvFawT zD(33K`}aM#r!Qf@^F$Tm0y%%FE8yepi#wzC(xZc1E^rzcIZc%PXbb^7m#a=$Q{C9w z5@k@N$+!uhG4+Y|BlANePZz9B(d=pF7UK5xKTtSjw~aRp|L#QH+yw6R8^aU!mcA?8 zRV5JKyt6^&_jr+GE>)_| z@zgO21DNwN$V8n-A@5Aweb{i*X zvcG7yw$JPapz+(?8$LBsOE-yl!z(4?udpHRKDRNJdSEjeNv15`OWJ5JIA4VDa209H zK{`dJ%a#=$s@H(Ea;pSvZg^*IW3+upl^Clo-;)rfA(B$`hu@4723eY&`S@{f=Hv(jXug zQeF*>JVs>P$f4mpmtwA>9`^{w9*e7$bM+HbB}};ys}he)U;UDTif2e`_o?*-^1l&ac0p`Vz;>Zlad%;erNJi3ZbgBAh+L_}Et12|2)?+5yTs>t2E& zFm!JT?u8&Ew5%Wtp-s^BIc)(AbTA|wavwbj-&LRaxU|36Ihe*gb|@wU55+eQcD(&3 z6w>*)pZnKf(kx#K?bo+#Lx_tSF zB??qM!bPjljgE)V@mO2@M$NQKOts#kH<0kUM~C@#5NIe<_Z4sJ5M+NpC@&oo{GnJb zkmq@K{!tpAGYr4YB@`jWC|q$adcsPAX>#GQh!U3X8uWJkr?Z@+hKfPO>?{vH3M?c zzEstZnR>v(=p)v1WN~<>H~y5e37@H8Vx^4P)!7G28O-7(Z5PUnZWrctqNb8i*P#_8 zvcu4K7Z%ApF1Cb-&ZL|eq>8q?XJndJJ-*YqosMQYxMO#Esi-`mO3&i~!*!>Ewc#V^ zhZvqN4xtG&aU=AKI%0o&R}d#f1zem?CB65$NJve6M=_!8SxWpn+IB2$DLs)rpZIPI`B+Z^nj|NL902=rVE>CmhgWE2@ zTRghvxP%#uP9nZU$i-TIaR)8ApY~I#O}?rrYS=E9bY}M19fekSH+&o1wad*{B6Mgr z0eVhK36eYhtc?`zP$Gx>h`19YIdaqmfF=fAKIeRlJVyqZJUM>RAvsDZ4p;JCmvQ_i zv(SOX_i{Ns-DJ?iT2;u4k9{3xe$_Cp*L=}eXVm|FQRRhi$+qXCDR~{e)0{0Dk6+s7 zlvYDMrWVBW-rYVHg{4!XF5u)B%jrLKpD+d@vAn=odE4^8WlyNDR{e!RXI(IlR>)z_ zP+=Y*SMp)>K3z=V8_@tHYNwOiAeS&-{L}O?7f~2`02Qr3y19wqES}R zZx6LLTXc}g(Z4uC?QJ1^?HgY#KxmE_ctKHEsX)x1hdZDx^Or<|mi;@0!b}!~9tSm& zVXcY!q?6}{amRB?p_EJaQMgBy4;6!E`tpN2Y)XAXbVlUrUOdlf76*kI1kqe5Dx76Y6Ctz<9 zesJGL$%?uIyXm+8$d*|hZ}p3HB7MW&s1H?(hbwW8TuYz+u0iCB^TBhNPhX+4yWZI6 zQ9T_&x|~`XdWoYCx!0d&cTl}8SqYq`lL#K7O=-t;x>zIqtc#`1f2OsrasqTc@}0>k z=LmV-EH3rS&9U0W#BR_0dvEoM*gVo>#6-n`+ASge*^>BybI4<)SMD*Wuz*IYO`a!r~ z5;Z5Tjhu@S0Ww$h>NcZ>&XOrEhtPM<6U#*>DNjfze>g!mZZH*xcH;mo9hl-KQEPNu zzP;x0-b#qG51Lw1BZSamxg^dm_tp0!n_cx$;t!^Z;~m43_L%#MmLx7E3K?g)q7z|h z?1391R#kiJpI2^pqPdXmZ`L9LGrr}LBtJaZ_Z&&aLC&6>=rInqti>T8m5gK z!f7Jy=KY(wui8$!SH-=2{lZu*P|I{DHEV>%3zRrK>|}*OU>4@W>M32_85x+2}+#IY@Eme1Jev5o? z35NS~%bW)-4Mw)I=igBovkbL*zsD>@{4c<9T~*rNsD^=I4CJ*ZZpX4zqM(F&x?59)EY%?+N4m{(?zdxSFxtDJJ=K zo5sYV%`^8WCi~v1W<#sWvTe@=)o9ar@>V7D7~G3i%me{J<(0ehI_X<}(@)S#oFLPW z)hOUm{~bNH6S{u?Bps-%YXyXfs31eB?7vO@E&Gb>`8DqDYib)fKeFPv!2vy5)Qwz6vf*Frzz_~}0WjucW_2iz3VX7g z6g9h`T<0)msfqEm4^Qr5QHfiB>6#&jY!D3KjFJMrq}Bzg#wg>Cd7w+d658)fjNY^F zH2!vZ`8TtY*(4mqM{h6qgFrIvHB#vTY|SvT6H_T-knZ$)URY$)aLV0smayJro*j0z z8hSjQ0P`(LVBsTtM#-!Z{3}_6HD>R5OB$F1I@uXqukm^2wbe~(6!bVIzz}m$c`egEkx9=sGA;^S}@15@Sr2BrrzDU1Q?LQLG^umnz zCJR|iBbwir!ifs~=jgx7L9b*5!^tV+6q1c0Mi@1N{Rs!@x>%pGX`YzoKrHTqwFov` zND80aTiA-24exC;RgG;7`hBY^q7k<6LWW^z$#u(#s^z$zAAAti#vHjjXyOIC(3JxB zn^dejq$V6h-KwV03c8V%eaqgPVP5e$`gd7rWmz@HjDUB z*B0`WgE8hhSs3wi^sws{p$`=)m)pfhmxSMk6UW!4sC>(zw?m?!bH&|4~lnv7WUKv#OU>7-W0RF^syiz{-Ln{I!ufKNN=P-e|}LU&?=?0 z^I6Yl0|Fq)*^urD&*=lrolhD zp43h3XZAQGuf z`+-6WvsBliZ7H(tr0L5eE)2Z!+-kJe4!r@ga}hd5bt4WK51nemU4+Q6Se}~kIb}#n zn-IZ$aipS{K;@OBIiL-hXnN`jW`9c-hIf#CPMN!`T01niD03`G!<^}j4}!s z-IV3KcoBPqbi0+Q+UktZXeJfC>)QtmAz3#ZX;#W&OIY|(Bt?fnyVssw)eo&lI6Tu{uq&A>376VBzkY4i7;P&C}z-2Bi zOs35&Z{vPX#(v_!Y$wLf(iBl1heTE^2jtHH87@!WJ0+$MQ7Ua_bdJ%+WFC-7@+)B* zE0k(!FD+AuX8SG8#c^Br7SwsMXUnpdD^ld@c#6@?l`&b70_8eLZ{sDjWPHI1yR`|R zXey)pZe=?vI(gKi2_yC)YdVA*xv%^o7O{d+#_g2R?o^otNH!sA*2A4hCdiOvIa^nd znsHKgKQMq?tf%M#Z$Tl$(5At)#%Szd>~gqad)J|bA$wF+h7dB9{>7lM5WEFyQaI#J zp8Qj!s%hRy+lmfx%#P)Ld?Fl+w&w~U*)Q1p6QwOXJ;V0L&h;zll^j*3Siyt(nHjh6 zbIrW1Lh~dFnlmDAAu;2h8T73T1Dya+bTXJJp7>iE_;}|726C09L%c5DRtEMuG6i&D zQ$jS5yxvO?D3Iq{(Qq1*?frPyslckR#~U-YXB+gVaX`@#m8zNKx7jvDEiozo*2;#q zyvm_|ur2w=D^5d>Um>b4c;sDbHkZqn%=(9&wUTXifLvx%hW19<4>@2*4A zjx(!+6ZbE5i417hFzVkDV93XbW|WDQE--qTMt^hvb{kGffgKLAMg~OwIKhgWapwm$#LRdmf)t=kz`7oC z-Ya)#C)G?!If%kdgnV-NQ3Wib0}}f~xg2iIg6Se%>HN}tLWcnfLDkU_I(`-B3_aHT zeJu_(AdH%|9+6<4rY{(vkP$^)DFAKFsK81b5 zlUX(a@S8oS?Ts@E=_s7!n0;YyNEV$SASL^8qJzmeSngp!x}AV3mrLU{;7uDjyuih` z1(^XVqceJtue&M}W-R!{du4U8kcH7qB(qZoN9I1URPYy23Wy>HK6fxSz0O3P4uxC( zy#CDS*`VlD(zrskIOz z3>6(LT#iyxx_QcOzOc(aSK+UK_)7odKY85XE#;)-xvpls5vD{1D^UZ{n5?K82jTn0 zWAffh>T}G@Uj0+*{Nv#2s>Pw3EyV2;Z#_<8%H>I-n@{d>kfo#tEs@LzP~?J|o0pqt zXh5J|*FN5J|4sTwd)qEAgpMu3D{#AC)|Fgau3c&obKR-M;w|-iy+OYmgN8lV28HqE zfcUlUi@&59vskbJhc-_HLI%!x2zqyV%+G$tP^jqQw*DeKMTnVN?#I_Hpp%d-F9s3? z{^;WDR>mF>cY&z-0U>$^_ec@ceYol6vE`oZ)nm{mfKq%4Lv)r{I@d8u3&;)zB6l%X z(mXnzGw3ghXK(lkjPVR~&UCOQ+;nC=A1${dGkRdJNUCs5h8ya8Lh7HH>pJV(`3k%9 z$DKb?~QUsb6k5fr*X??0r;c+xwia4m?1E$ zDUfT{A`UM(4N`~gx8)6|IxCYhNNbpX zS%s&^p<%Xz-B_c?65qg!Jz2ZpLc1Z~-NLk;2g36 zKPam8XSGSjzhM&(fyX>ZH8>s&4F;t={ViStHf7{3aqD9;S zvQtX|EvPB7I~~K?fbIJ59NIrzVX=gmkR-8&^0ZetfNs79zF;sLj)=Soa~)sQ=eAAVU6P1qw68FWOD zWu&5m$g8Os&6R=)F45sXtsIgg+t|HC5IPk65z+HYyk5D?L5ClWz;gy5X0zf71}OVo zyU!3#Z!zC8McgyhX5gSA2Tu)!1EDb=PzT+?9q&vaigEDf@1|6-2rwQdtFG@3(71l5r=_ z0Z-h^f01PkxC`v+5U!^qEUQL9X5`NbgC8kd<*Zs1E4;TIe00nRje5E{3Y)Y9-+(w4 zFUIWdk>EX{VHT)n=PbF%f9RZ7{b8xJ7qez6@k^l*_9C$EbuX^){M{u;cWzKCF5i4v zRi5E}V2B~L4k$L?93gLn`|=M0bE;o{i((tCipkQ#BCL5JdSScL;4|n0S|4t0p~k*O zUa?l=$&Zu8&Q?;aWQ8ye;PY~j^4bd6RQ82MY+x>z%Xw!!f2xSk%Vv;y1-E8~j2Q^m8 zNJe*vUg!fC!$G8!GKk-bz0pmVc!E;+!62hDJVWgX>ht_eAj+vI4HL%xKbc3qLVu*9 zVvDDfk|484497wqo=LHDaZ5C< zcaS}VjEvBs-r|SVkQ#d#L#pgMG=~xNBqZlh=r{OmbkdB!kpwX`w0NWMtK%kb{<0I# zA;`8CsCiV)v8rKSUrQ(j`Ve7FXz11WQn~CelNi-i^($uudu)w+F3kT;c5lVp$`bPq z?-LP&vb_q|{ZU>qSY}(<{g}4hMrj#z8e@;*9XY&HzpvY0ueXpirz}FQir?;5`qK3b z-NdhWT?xJ1lhOY`!Lz_)wZt`R)Dp?Zm!;-L2tsxmsrYl!aHwSfJAPP#?pxB@PoAl) zoKQheBvXh z^mWc#96^ioODfUVVs>KViQbiw9@-DL&Zm5nK5Z{MYng-J)6HaZ>g)s-S}?JlR^>)K zPTlra49eDaX6_#Aj9~QT1{*DW18y#)cJ%Yni~NQPi8srtlVaW+`s}X+WUNLD6_gLU zaSb|+<$aDLk_f-zp8;aGHI%3EF1@fSQI0Kdy9TSI+O^SV(-1X?2C=HF!vGldJQa`e z(vil^9XpLrJ#G9!3iJWM;ASKQtNDh^D0>CC8g~4={%m?xQH++|#$i7|4u?go$SS&2 zTRwY(+Woa%1PHtA;F}?WX8&lk229zs*IdvLNe;XOJ?_>o>KsJ%=SC$Ev)5sJ59jf; z;uJMY8?y!iAN-WF)*>8kJ%eZ_V4obZ2sU@qf`moier|X_Vs8o`fQ&0EU z_bCBNr5IZK-5X`WW_N3Mu&{|JjH3s`Q8@scP;3^GiIBn5)$c0#lNM-+=HT=kal~Mo z-nQ@ii+Bh{?66@t#HvE%b~K-ChYqsD!Lyi}V8_Z>&(!n^=hQ9oz4&kS8N~>tGD^65 zdpmkCRmQ>Rml?h*1zmE-dXGrxeS#LT|%LfHqMy z^5n0j^n0RPW(@9LNB_;=uMYYS@1fYbh9Kb~uJE29ApbH~uj_2_FK5*jPykMp@68GqNu0;F+sM1Y z1#l3ugiAAbt_;iws2dWb9wDPt)r}q*^0$8&c|mf?{>^||(GT6>B-t}VV%Pv7#Qq@Q zq=ygXvNtZM&4Tou{y{dm-5f+N3}Wl;-Q*1DeMXN*D!IVp?y`qc?iv7&vC=bBw4er{h06L! zpoW-Vxe-s(2k!KnWTn#oPB%S8uq|xt7`^?Fb3vyPKTNiI5)%D>Dtg`<{d6z=YxF~O zo^AVr(hF-v-h>rW`J$N+F)y`=4{Wkrn24w5`a zwIT-D@@KE&A;zN~)CXYuyu-9uBRU%F!d~|_fTZ&~+B1|L4cO`O9#+yJl`#uG$lkRK zZulD-|Kdcrg0m^{+7{5ULp1U=Fd-?%c_stVT#gA~^xF&LVWB$A%h5mq=Imxv=S>Jk z+uI>gQzOjilWsahna~^RG#f45q;?%gkUC}ki=KZsvU4( zv#}+GTq=S9QaW$RdZ_jHc07rBhp`^K@&HbBfLRR;3Z=<@-~5dJ@G-5Gky1&+wof$U zG_Wf7q%N~CR^;bcEyZwq%4H|ub}a#0$#GQ2P%`h|((oL!q|XI^ zZH4_yOH~4>E!WjultgEk%Tc!~OVK)y2WzO{Tc zmC;)ib!Pn}*>@Meh6cMHE-GsPp}q(i3m0UmB+A>Sx|G#%2}8a^5YWZ_(3qI{AdU1+ z%UqSvpc@ytYPO(N?_vq_$p)bJECT>)zBpXQy&1+18Z-x}2QG$m>=J@(>%^Cw zZTr9kN;DH9OeyfIC@z#U5Sg){zI*emxA?`0cIDtikr7gBglh`eUe)xAUr+}Fk8vVit@7o7M^w*R43)y)S*J^sFp9KRadv&#qBJ7kFclifmv zvA4$lD1Q#7on*FT#`qvpbaG&dz!0F5U<6_cq45ap&UsbQx^>+*`_`kt1fv_uqFQiG zKCwYJht!+!k9HJ_-!f{t>9!i|2wqY=`?iSsc25w;l3#+iA{>9+t-fE#Yllj-7aRja z;-RjMT*wWS&IWk3A65e$i}80_6x=!jR)cE90#6QsfSA^CGXve*>y+EWVV`R8TUi5k zn4%YI!V-kWv&Faa7%F|$d`m6+sM6kdSZ`y?qmFZYzh347AbxAv zJdILo?3rUTZ3J3$+$sd72nN9Gl7|*c$Zt9$m$m5J`XelzyEdOZzpL43tl8*w^|IM% zNhCe4f$~j13Jk2iAl+qBnU=%NOaAy( z8dC(1Pu1+n&l3J8USd-S6{f2q%*7NFjAErwzL|G5DsS3B-n13+Z&^BnpqYy;?bT$n z#XhUQ$#^q3kLGQ?mtS!K%#qc3eP7D|1VSTZ_K3OKc_6c7FaGx7;y=+)`!4xc_K}=1 zeM_%9jtj+un1hVONTim6m_I_!m|OLsCvAXwD!!l3oLvJ1y0k>017bwj$oVTeH3^Mrc*}*?jW$%ILsp=|Q-r&_RFj4%@YMQiWj1r+O3w z;D~+x_GX4EakmcQoOJIOasLyoH;+^!ELFNSpF|-nJ*@LTJ{^cWr8dhS;F`6% z_;=Pw4a;Ot^6ne)5ut@C4ZY+?fQrOsAd|A@kkx1Eb=m21Q88-}AZEyivWCA!`|U1= zx@{1}J(ImTtiL8%$A&lZVm-=x6@&5A7H#JVakVt94{noazp_=<4L8Yj!{5lhi-Ol# z$}RORGIhLLp%@TZBRhVd=4Jo@PbgkFZT@K|#RnFfY*#v{}U{c)TH2Fz5|2Txx8*e9Ub( za`)aKHWaJ#bQ!!TZN2=P!b}QEV)l84+?~oW;KBM3|Ix(=XnNHI22t?EP1v0a2FCjA{KSU^uN>4nW`V2S#4Cx?@AYZ8mIP$lKsWOB`nbo~8!OjnXEif9bC{jH4FL z4$6pcIUxLuHz3}bHBBNzl4%nr(I|W02A5GQ0A$WC#9@Rr__Xmm0e?Ba2UmxWX0q0x}PF}le3UTrqK6yCj@jgxB zBy9NZOX@{&hH;ZH{8kIsGIT@S^xx6Kc61T%%Hg|2@8jAhd@lpKlBIz^L!X(H#pnJ) zIMt=>-TQDzZxZ@se3X=acgB?W-X0&PY470WA+FJGC%gy-nB2Tedn@>y%PHHAviY2{ zZK<->C z-zbsTe7le~=V3hCitFIbD1Uh`chb)r>C-l%&ktjZm90blEhxL41Gg1r zuKl%U+v+}Hm@@5|wqqItKYolP&b6jQ|D5dfrCIpqAYz@Ax-!DCy|a#_@@3T7ouBmK z>gq*s#P!m=jJ$K+l4%|0c116am#sL|_r!O>r2Ph7gxn!0!%pV_dqxxYXwMM}Mf(Zkxf~%&~0|oH1(hmyRJx zwmEn<%EIx)cB_+vaPV+E;ma3}C)V1AhM{Zb`we^0ArW>ITNRu);7eC5KjAg3-v?B| z$?+%S)Hv~ybie7b@2nxB0i>&&qs*i zbAY2>LY$1_)a4_V1>dIPyYTcIMq%Gb-{nSnVVUIVKmAi=kH<(sLA~??AJHu@7;MVEjq@T}QppM*e(O$mavVoW~Zk`)bHHkFtvqoc*58LY#QKBp2sqD-U-e zpXV&Sag>EP*{{>jVtfvwKG(iDoT7Y>MHX3{;u9=e0L+jn(RL&!^p|ZmpF82R98TJR zFytw;QG*3GRl&)7-5gUm*@YMK=_kSIH)^W|~9O{HN zD)LYAnCDBw9-|@7LC_=ILWEDwdF0_7DZse_?I92670gHG;oMVza~?4(59cCu#j>q{ z5ADuzlBOzlzW{uML&(mw_bEk)eHEOX|4jRmAfnw*WN=Cb+sZNc1N*UCI1YVj(8?b3 zCFb3>a)fpl?D8MtWLz3VQ4A+z!FrT4o`*QEgHOd9;zUudf1Xqz>_ePfbC75EO9lRU zssQI|_&jZK7j;5D&lcc3Q-G82h|j}0UEuR)3vlw==Xp3ee?q+wJoNc<8Jwt$L|^ig z$nIj+l*LEehd3{IfK_~c5;*gGekOxcGRWsB9EP&Te4b;ey!grfQd1Q^CkptyqzJJO z{qqL$^8E7(WMJ7w)Cu)@xd7)Zd_K?aGX?&6r2r?_G34PqRemRzG!3Tp1E} zafWkwYf!-Z&{EE8E;(dA`*4@i*JIP*Mg1wfwqL~j`Uc3z6w1&KUGja}EDL3rq|+cx z05)u6$6zDMar+zDZ-?^z)tmbTHpDpvoTDg@+3y5oxc^7OOUNfKzxy8iWE|%i;3Ul$ z&T)V&wD$0nHDYPGB-7VA1>tckyjYwG9fuGuuOMC(TqgF*l2Zc1_`BoO(nr#xB%&1GO(3nwmS9QgTq*Qo;C1Vd z1#}#2@W5Tf6$M+~2VUYHr5f$ut;81GTFxs#C(?&*OA?b4x5o1mqgUhO z6SogQGp$5=s1KYtj6O(1Vn#-AG*PGCsFtm$YXSWotrvD4j}}#kD8G zVt)?3e{!I!u_}0gk*U7K^l6U>tKi9EH9W@HWcRdAT_u$|v_M77DvE5?@O<(!*XKTX z6cs6;jO=hNe8;7cU)vQlb0idQJ6)5RIB|76tJJrn@2_}ZSSzI{_3#2iDN*ulr)_go(#v*u=#cr<}mhbeq)UgvL>`3`=Okz4dqlfYYrL*d3Il- zcQ*^yLu06@G{OZ`SkRa5eJTf7MXL=dYS=`h3C3`7d3JlF1xpe`3qy>cW;lV+o6(au zV(97Rkq>gCvbh;%d5^UP(ij#7U#(t4pZ^c1%Iv{oypYYGHx`jBP$2K-t^7$xj-37J zWBw5Mr7>{e+IUCV(!v?PjE#s>s(UF{Gcx)ij@He*Tk{3GJXDoUSJYJe>&Y6fq6;d2 kRlb0zIW`YN@-+F-S1H9W19r~%3jhHB{|8w%(f|Me diff --git a/CPLD/MAXII/db/RAM2GS.rtlv_sg_swap.cdb b/CPLD/MAXII/db/RAM2GS.rtlv_sg_swap.cdb index cbc0bb73e70905c5152312ec089fcb516e555d1b..de7e9e61af56c3afaaf2ba10f80f1b2a4cd74520 100644 GIT binary patch delta 483 zcmV<90UZ9w2FM1Gc7Kl5m4Yr@xX_h5H-fGd6z|F)#k_P!Oz(nC{{W93gSU{tX;434&lBgqjyrD1Wc8C8Q4NOX7Y&N61}Gi-nAYXSDjzMf#8e4bE;B7Jd2tc7z+${Y@BLx8^P z3UJi6fJ=b!E62rMz-U^or{&lw*^OTSE-B&Uc-xZXC@N=-+W@OJTb|!&8z1K;=t-ohH7znJ%?t?Bac>%7Jt@@`R9C)xPajH8 z$xSUYPtD271C8x>`%Z*o3AMo`FjL(z-8$AdKM%Z2wp-*gL`FMdQ04_J)i{<%@A=;exTluKv2p~!9{J67Ib5XZK}mKDM>5%q5gsW>mo%$s+8D3~OaqUZV9jDLvI~PJ&-0c*EC`7elrM162od%C z1uH^$#wG&qh!_74CkisC2>EYBjhZ8 z>RIB?!hkx7_X=N%YA=1w!8YF43v7SuYaaITzMf$pf1XhLB7Jd2tc7!n%M1>yeSp5} z3UJi6fGdFUODDNKK(ASDOUtlRvKxN@ToS^`@wUauK~&Bfw*gjd)LZRpL$_?p)Z5m* z--*KMWxLUY-hXNZg$%MiUTDK9*Y6mbhfo4drDl;yXr@3Ij(c16>q)34pt^3m5A>mg zN^UBtc`8m?9%$@#r|(!emQd+k0yCM8;hI>Z{50IzN?03%fj2E9LG!>H&~)q@ z$7uA_Ijv@DyZ?`M;E$Cv5W#!tg(DOa>*hXRuNC0vP*~3$TTn?e*lw90{toi@5TTC diff --git a/CPLD/MAXII/db/RAM2GS.sta.qmsg b/CPLD/MAXII/db/RAM2GS.sta.qmsg index 9e58fc7..d84743f 100644 --- a/CPLD/MAXII/db/RAM2GS.sta.qmsg +++ b/CPLD/MAXII/db/RAM2GS.sta.qmsg @@ -1,25 +1,25 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691916643769 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691916643769 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:50:43 2023 " "Processing started: Sun Aug 13 04:50:43 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691916643769 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1691916643769 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXII -c RAM2GS " "Command: quartus_sta RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1691916643769 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1691916643863 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1691916643988 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1691916643988 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691916644019 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691916644019 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1691916644066 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1691916644207 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1691916644254 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1691916644254 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691916644270 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691916644270 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691916644270 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691916644270 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691916644270 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691916644270 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1691916644270 ""} -{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1691916644270 ""} -{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1691916644270 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1691916644285 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.541 -253.391 RCLK " " -8.541 -253.391 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.503 -92.361 PHI2 " " -8.503 -92.361 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.149 -5.683 nCRAS " " -1.149 -5.683 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691916644285 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -17.185 " "Worst-case hold slack is -17.185" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -17.185 -17.185 DRCLK " " -17.185 -17.185 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.694 -16.694 ARCLK " " -16.694 -16.694 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.367 -1.096 nCRAS " " -0.367 -1.096 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.107 -0.165 PHI2 " " -0.107 -0.165 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.163 0.000 RCLK " " 1.163 0.000 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691916644285 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691916644285 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691916644301 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644301 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644301 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644301 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644301 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644301 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644301 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644301 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644301 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691916644301 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1691916644379 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691916644395 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691916644395 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4677 " "Peak virtual memory: 4677 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691916644441 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:50:44 2023 " "Processing ended: Sun Aug 13 04:50:44 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691916644441 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691916644441 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691916644441 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691916644441 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691922994535 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691922994535 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 06:36:34 2023 " "Processing started: Sun Aug 13 06:36:34 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691922994535 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1691922994535 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXII -c RAM2GS " "Command: quartus_sta RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1691922994535 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1691922994645 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1691922994769 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1691922994769 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691922994801 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691922994801 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1691922994832 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1691922994973 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1691922995020 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1691922995020 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691922995020 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691922995020 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691922995020 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691922995020 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691922995020 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691922995020 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1691922995020 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1691922995020 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1691922995035 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1691922995035 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995035 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995035 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995035 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995035 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.675 -99.463 PHI2 " " -8.675 -99.463 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995035 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -7.924 -256.499 RCLK " " -7.924 -256.499 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995035 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.977 -1.340 nCRAS " " -0.977 -1.340 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995035 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691922995035 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.324 " "Worst-case hold slack is -16.324" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995035 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995035 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.324 -16.324 DRCLK " " -16.324 -16.324 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995035 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.276 -16.276 ARCLK " " -16.276 -16.276 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995035 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.015 -1.898 PHI2 " " -1.015 -1.898 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995035 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.103 -0.198 nCRAS " " -0.103 -0.198 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995035 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.151 0.000 RCLK " " 1.151 0.000 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995035 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691922995035 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691922995035 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691922995051 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995051 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995051 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995051 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995051 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995051 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995051 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995051 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995051 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691922995051 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1691922995113 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691922995144 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691922995144 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4676 " "Peak virtual memory: 4676 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691922995191 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 06:36:35 2023 " "Processing ended: Sun Aug 13 06:36:35 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691922995191 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691922995191 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691922995191 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691922995191 ""} diff --git a/CPLD/MAXII/db/RAM2GS.sta.rdb b/CPLD/MAXII/db/RAM2GS.sta.rdb index 5d1ccf66fea4d4d8e1cd55eaec0e1a5993b4ee0a..18942106575dfd4a4669fc2c456c23241de09ba5 100644 GIT binary patch delta 12731 zcmYM41yozl)38f{K!HGU_u{UBV8to!?(XiE;>F!v0~9Duad#>1(gMY$xR)>e{oixG zob&9RopW<{c2;IKxu+I!mI=}jgAKSh|32v)|6ShLzy06!Uy083KiM1ZB;X;PWYmQ$ ze7g=|2}e>jjd{${hCz^3Lf&a>L;OKSKtS7>^6m03w6vt^VUYbb4q)>1kn9%D82J}@ zZ9emOv;0ibX(>z1hqcT2G$*;{rj+xit`A#KbBNyMTtnWehlHhsM&QZ<7Z2A;XHWfO zCx1~}Wmn9|$d?hO%j*59T)(8iO+}Gs9UcC=rt5u6r*6=4^deI3-(UMXi4TlBOJiex z2aK;B`GH-Dfn6(4kze-6yQcV_u}3jpU#qXL@E$4kX}=BnFUu)-z%-j4MBfI^7Dv(*N~yDEAq;)Xrh`kD-lE?tz@#rI`c8FOWJ0 zZ!f;(Qyo#6Pu24vhr}W~^)9%`+vnTs#qR<~q<=bR9yjUZ2%nOCaszgg)v#vVNgU#Q zpIk1DeUE+8LOO58_J)^=zh)DHBnKj@W2SmVyO&PakA^W{ev9Rtm()h0u}R+fCJTJ< zYqRUN3hOOBk}ncph$dSYb~gVrEDrJA>P=A}JBnuV)oW^29GVHVV(;8IR4k)Tx~cBJ zYTm6vzeew(>Ztum_hEt|)pY(zP)puPknqM)fv$h%JC0=b%XjfG^1+r*0VQuq_OQyn z$CRW~7e}>Ul+2lVoXSsaWy+%ukq7K$t|9r6YRss{6H8YJtV3vNEf{j4%`_0;Iq`wf zw_fSBxtEuzgK3A)>mBXI8R|AxVz{@hHiCI4F&AB_bO&X)f#)<2Ius^VfZjj*9*-Z; z>Nr+UV!$t597s<{LTliOT*7WmZ30wg>nW`#n&cysxsDlfPb0E+kc32xDW`jKZp{Oy zuFwJ6_TQ-j@z{6gMm|Uz9hVS~YdO2$%#dh&Qnq1fB`NiXKR!$<7U#n*16sENcLCJS zVO`xm5%$F@+?UX*fSrS}o11gqGWss!cy#LG*j?S2!j`;itc~_1!qcRD;)WjQ-EXZ1jCHk$HZpF1!KSzJ@x@rgS^rgo?J+N2?8AYL}2#Ln`I$;ikMoWrRB86$I>J4(Gt*~|=5lpIU;y8T)6&rkOgTg9 zISNrhz|_H4Jn^8y;(8eVWX0A+kQj3(uuFUpL8yH`7eHFc#)$oJyipfG?jsf4zQj+G z{e5&1FYN7Z%e@IPk&OKOxx0~KN{C%dNX5c02eCb8*LC9bqY{XB&Bbb~!ckcl0@@0^ z7AAQm;9E!RUp*7tTi^;6Yo4Bp{!{uVM{sj%)ie0fOCV1klyY`rue67M^stjq38Vc-4O!VIA(fI~Y&B9^SAGsJ;u zlYFx@PfaS5b)O+QV3i50;}U^J_u-AG;W@BetDf9J@d<|yqUDrcr7m??Lu%Ca65>}* zFWmuVDShXYHmhk#L{W!8-iW`?xBizk>YDB=G0vVemJfvZ96p|ZASzP%rRzp;^=R<8 z3ZIySND3sK+nb?JgpdF_w5#nkA3HUO{8aD2y|A2UO?VKAl(_gg(zhw5=<7MvGz&IJ z0tDi1CdK=~FKjY<8dve&lw1UKI%rOtdvF_cg@SYr?u^qNbL^1Y_=t|*oWIrf{M>Aj z-{!ju>%XJZeC{nR4%AsIJwUKk>QE#3Yf*V<2e*+4G_{!nx~{jDZ(Ojulj6r6=p&-k z`hct0+Hzo^e%9+;>+9nd(EMypVj88ZsON1aYDn~9Gm9@rr5S)LnqsmlL_ucXf?k?; zfgXW+JEXg&H2eBYoi!pP-5uhSYbuKJ@gvP)Gi0~HbYk`K=4iM@Zs!y9y7lFP%uKc=90j?1Tgp=%d@~H*O8BzVviT6I4#EzP;ldEK39V-6R_B&a`!R%Xj;}*z<6h{FRiE zte<8;M&ET2g|X9?CtX3#u~f84FyQi(>gG z0j|sjGbK^979mZ2l{qYyENFHn+Nk|UQjnQ2CkB7HUwY+|Ijxk_0zcjQ;_fG$N8Wj|i|0@LRUEmn#{9WA# zHp1S8#8%%pWMCQf%wnK&wlFz%O|9VXOR_|2se)2r1|Cj`lMZI9Mv6E>`a;V@CE^x) zk0rfnSXl5g4VscUe%s~|pek5tvgtkU5u2zE0d0*n(y8I*>tNml zT<5k>9oZ8ZRz)xtL8W9`TOkW-MpkqhR9bDszVp zw`EH#Amt|mxhLcL0OY$6`XS@!NQc>JP(h+-JH_^W*+m=IN1g^%_WL&)b&7w0%28AY zOu=1L2h?`j+@WF!VR$&e!au!E685^KkH8+8VSnFg%94%b@O8G^X6KAv|=@Q~9a5x=E ziimKHODGhZ;W;oH$8i^u%)2XH^0%AUyXGFr+WSR~nNsFMs150NAAr|LdVLFU|TNw2@KK;vm_JQ1d8vbb{H>xuJX0clN zxRyiz8y<6w0&?D&Sq-KW%_PQCAO}u7!GWLyrj_AxHE8*ppy^S4&-TRJfKv%u9@K66 zL{!dwHzzL?qRN>1U5oQ@eXWrDI*I&w>3GBQkM+|ffZRrWKkU?yR{YDID!@fJWv@2` zm6*+NjlszK{trlP>Y_h{j}xB}Us$S9h;G=hB8%w`>}5s-U5!6+yFtAj9}0``e|0=} zbOLP_syR)_>F!~Ixg2K&4#;WK*Y-Hcxf^uUil!F*!tWST?jHhU!QAk(ZN&QFeR zNiP&aT?wunKm0pYO-4$jUF`nn>>a@Hp$H0O`i+WD-WBn&dG`xKa(kZo5om_TNlPy& zeABY|HP(GN8p(bAy&#dn*$kzq-;7)TQ+^S#_S|0QkjnQDI)O>!n@j@a+E*$}{@Y1+ z+}T&syUQGm=gDOq?twD)3){zYdd)VqP2&*|u8cFr7HYT3(Dj3(fHaElN{A#R;~=Cw z{(D-3KyUq<2$do@+yifooUalkx9+p=kCKG^k$L_S#DZHXluACv?M*N_SAO)@kKs1t zazAW}^*0sSqj_ogWN?>2i*zD1!f4~1d36s#|82qcD@PEs+7cg>%GW}~fkPN^s0_ac zfyXS(ow*R$l1j1D=gf0qp0ui)c7Gn4f+K(1==Ou;?e&|f$@dL+f9587goJVFIHj$= zH*>wjQa%dRuq^Szrih>fT7AYsC!zE%6Y}>TTcvW zv5HGBhL@GXcGD&%&6I*pUL;y~=YIUN0dWOr=!9CH z2ibXa?I9mBBnFW*TsG20M=M$A%vIUt7n)|bS)SECw=ZVq7;p>qjVRmMF{leh`b&IF zvlNJ>k~KF!Q=?q@`k^%9M1Xz*O?7W?0{UaC_cN*8WgI&B5Y+Y~9preH zP}IMiMPX~D;jgx()`@5rH+;YJ>@5+b@P@xDV<&BV7-!{x zBE4lR6a8TMBXO4M#;P55r@MvWp;b1=;UP4Z^GBd0?!}=~B9_7aceN=R_1={zivHx| zvMpIBUq^}I$7!2Tq_Q6U-YGvxHHZ`Nd~UR>zq~;%f<}sVv*|lZwvN&9wdbN@O~W-| z1z(#?!tgP@0LwS!$i+`ISS=4{kMc5}rEL$!pTIa;c0SKS51Dz@1~uL`r42@|3nDpA z(fbfJZJSwV)ucXIe9gAn*)A=XD)((EE`zx$O4cfFU^#9b_nt`szML}Jjss5v(d_%F|PY`6J ziy&Rt){-jX-IR+Q2Wuxj?#^sO|DUi_0MpA_xn6jKlc%bd+2FTL<;S=QbrPCf(=&Fn z`i2aF4w(jq=v)DR%@i)!`E$BzY#JbFBzdKPve$mhrJiTZRq7_sE$4pb&+zBDj3}9v z`Pu-byg{=I2QQ26YZ4&t*v~a|gx`^&=wME2=Eq*M<|o9lS%BPC$tU5p?DLu*%04Kl z3QyP`%Ica!NZLVK+6R4N_{Zn+N*6A=5G`$M19ApbfhYnZarzt}7v%A!Om9(TU|JGw z<8=71>W#Enn7c_KDr&$kUU;9_T4dvcflNw5XMB!!UBsaL+?cWl$Cyft>xd$y*YFfE zC;E#Aw_-oB@2rFQZuFKMzQ=*U#^z16>(>S?`DiCEom2EXfkuX$E9yz%SZoAOJF7O! z^jp-dN$$-}s?9~I-;f8ue(dIAX|!tjHK(IxXp)e?tI#k$o9^#HT8+(SQ`r?_iS(Vo z{e-b$G4(hfqXSl>*MxN$d@47}6-6YAN(&)Bf14yz_cJT}Vz(_Oz(z(3!Q;ur;Lq4I z=GfT3wNI`RI_cXpq3*_gs=rP^jJW-m=%*ud=OR=Xx;lJD<`B8VwRqp9i@}LiJNL`# zZ9P?FrzlVRmYN2;0f(&0UGG$ljgmiTrN9={NJxI<#;?5yOE_1Y=QE0;_rto>wY3}hhP#mDT$aHv&MZ;oxiNbtBfGe zB8hJPC@3jo5p%*rpQvw&umo*ak~^YO%cCAs|8nqqM*hCCn#bv>BYj!c2 z#ji(oL880xoVo~MlA7_b@_Nn6l(8ANIkM7K$L28=pVLg+n@ro*dOQb+m3uWPl6ndw zO>hDz=jxV$)|ekJ{XFHi&u89^cka;^p|W?EqhQa}wYK9b0V;pE6zAo+T>LNFW|?d; zC|hfTq}4+ho}Fsa1=Y55ydBAFEn) z+z8h$!mFh)G{n>?8i9Q@J=~R0bU(6g&ej$E*IrH7?~X`XOs~`B8BNkSfH-oT_yLy< z2=)>Xk{#T_|9g*{U2Fm(i)Ua!!@M@Jbdu{<= zJW4MS<$i3^5B?-BrteG~v~T}V0cN)XG5pF2z!j+@jQ17)^&~i>C3Uf1c2U42JA~o9 zu!@wi4Q|GP*DuR)oEf47TCLeVM~%}`lX5t+)uCsclBUG7wvLR7g7~kpJ0s*Si$zBCw-1in!IKq`Cs8HMP$L2-~L3`WS4j_bPDCfwY|MYFz8w# zJRMBF(3>RHPw)`7x_Bi>;`e7|z=MoNQDpT<7F1GTN-r7RceHMi5oT`oDW%B8x;~uR zXK{J3%3;KJ-`aKaod+;~MN0fd>6^jn@u1L?@~hXvwzjUW>m_3;L{gAm zZT$-`>_8J>&lGh!7V<^MS;x1EIK?7T=L=aq4Zl~M-Qif^eivm7(ni#(ptW`FJ*QT0N_)Ax4|FXWKNxys)%*@}f`XX4pbA z3IBUm_v`QJRMl$3z!%6>sv7EOg`?V@Y=ioo>ZHCgj#1_H$EJnG(pjV=R0yFM703va zlCX@i^fn72eML}fj7ls~)S}wKM=J5MKUKAqa)u;%UY)zhnDYyk#uDFw^RfeyDhJ@Aw@yjpu$Ez74nE z0ofijdmhrR(oIng`U`+_MZrM~kYj7y@!HdAz;|7irbfg7XwlS3qiy>Xk5gu4uk#mu}{{N-o}dDUp&2+(UPAThEPE6x*|P3kpr zUo~i~D>d|um>nf2C{d4991^9>^@T@RM zm&R?Ry*8@D7(K5osODL+Y-zR8&B-^Quy#{;u5s3NdUs%C@WFZmz8WRg!fK^R@}Z483V19&cti8ASk&AEH?+ zP&vpZu{KD`6oGn zTzH~p#eiv7J+b%pP!s-Y-t{xxc5WnYW++zy&o7)N5IfWY5vHE zCG+qRo+$}q6~`>dkhYe}W=nGL>)-2rymA=}=k03M_RK?zK1S8nz17Xu0ux*YI%{po zEX35m4B!h$ZIt@r-*S4@_M}54@kNHr&Sov>N&)3DH^_PfJoz>iJm^ego{LrPc~`2a zw^}I1hRxYWryPp|YnJfWk6>ONe^D-iv^h_MtS`>se|;0S77uZ%noDqTiVpv}f!UyG zgKj$F&WV~d=54e{5PVIHKMKpJJe%~Bnyl_*c7Zav;;I}RdiBzqAe8)d|hU4Y7iCo z&0H^_?34$T$2AwYARk%~%;%!n&Wageg4&uBR^i>rug1j z8)$`?DhV=MHyqw7*#!A^njjI^!s8OCNBj<*%TgpMAVjlEJYv@q9sk)N+OG>6iOTK2 zC}@WWd+L6$bdJ9uh#zrU%0_{Ikbt3zN<(nE8664MIaJ;7$a^U;BuY+EX))bpk-R%s zyG>I~>vswHg>*t8B-TK%GLUF4ostycUtM*&4gDMS!6;S4 z&POJV7RW07B%F}WZUX%E%$B-wO3oglNB*E*PkT2$y(9UQVr2_vrXyE_1H;OU*`^)~ zk4FR+M8Q=Hh`ns7M)f@&e%hj73SDoZPBus(4f2-SUfb~)Co?)iOWT0td02+vaDStR zMHZJKZD2-MIvRz^5kDUA+~oJUL-<{R6|PI?yyFhHqK1{2N}*VPvu@Exs%=??vZ_GN zRJIp<)q%#MvXe{MTuRb?al?LFj#I(~QlD_G;Dsia<-2>0pE!pjxr9xp7ht5DmBFHB?u5apjW_cRExEdr4)xsj%85ihw0<<~ z_E=R>!aPj`p4c6gD$C7kOzpt5VwQ^uYitofM-i^Xk$1KX{CV3Cb-rp)$$R7|e`+*U zADG`rs>_+6A~i`o5H`T?6xV>|7AB|$M1=*m!`b)%kGWUWt`UFYIEbL&R0wXf^h?nm zDIP1+u9o&JzW0)OU+L+9>CrryGYVL8_ZPEkqN)sgD+M1!CCQlnS?{cp1@_CaDKU3A z@)(=2+!vX@QqsAhOIePVzKAI{ntc^U0*K$*ekzH2L|!5lcuXpgC@Mx*Qxam@FC3jG4ZYFe&IYqCDx ztmehSFD*q(VhL*MG`qkG{hYq21c+tDEY8y3;lk3QFfoD>*C5-Df}A7wJA8cPs9e5n zb>NQD8*AkEdh_{lA@!ooEa1sN0i+R+pM2mcl?zx4*wgNBx6q^ZT zsgLZ20xZX5jA*SK#qcn1>ThebROi?xi>|F9+a~H7CNms!uadvH2#+Dnf|Sx$(KyVO z$0OK@pcRuoAg^CY*1L6fRS{s0D?wXwpiG6)XWEM}3?IlJP^9(_5h*Xv7yO zG-9n{e=x5*sNJz)4QOz>`!sq#fR-;4l+X^RUj2lFd??8kCh zv*LGl$w?fdbzPt6pUnznP1?CU7M2jy83~Djs@A)SV`i7fwcgPKU(LKm4wF94(1zWV zbLAWv{}rBR2(CxY-SrwCTN)3Qc55YiV_RyA5K{bbV2lZ<5KPsb!|X*+Z^Ij5Y@Tmu zIBIQ4tHg`*4E1n=@HF}N*{UV?nO?tdE?smd;e<;~dqj#?rm2!Dan)eFj#{-ab^65x<<(KvmHL z6LSdNM3kwr`mOHLmp{1WbG2l+pp8F_)oGIbwAh~d(Cy6Lw$*JmIOu_8Enec78Wfie zrTTc9-j&Fcy`rctc(Eebvts9)alPWuaX2ICy7+{Q?P7u{x61F) zn>1R1BJcY!{^?JfQE0crj9~o$N7?1LjlLVNwiDuQT`dm_ZgWk3A!k{>4vSlwiUs>I zOEuJ@{YFan)k61@{x6y6t5}rGYc6J^Y%UXFXfsXK5gax0BNRTwc3<{mlU8H_gqFMf zdKOU~LWhib{R044Aj=Dm5~e;dLIE;zX`(Rpiy%L$6^dH$X@BHNg%AE)FH;V3yxx{m+5flY(7sWEq9lVl zUNqj_Fr~N4FKT+H0DknH(egKfM1t8LRp{PGEc~1ty^5*L7krlM{J%!Np(2Py{oaT3 zDG7NZSPH`=4D$eQN05@|6b@7xGv*d@pI;QII*H?w&+eU(G0o+acvGHW_#=qza1|v% zz})MDY`;|{x#TInH9WP{<@-<>+Wc)g&8d`bo1HSh(Rb7oA~l;$c8W#+n>@I8yH{EB zUbF=pk83o1EJH)qo1#z3g(|EvL>-WCC|A6!XZE4jUdEXqh&xdXr^MCdXg6w5eos>v zIYWjLMb(FW4XoV@TB484Qa_J)!}TE_QX<|aI$_G|@e{})eyLMT+BnO{Y$+z(#4db1 zFYdXDlGsK<$m7vmU1Is>m}~rvZ`TK zAVXm6aEA2aXstl58Ik#1V%N9nhC?I`6qSTA%5|xVs>u+!kpk6T)-^G2!3J{q@CmyJg2z&!58=uLRFu8d93?C zlWrVx?>|zYs6uEuRt8Dgcu44KUNZtO~FiKFlrBRcX1{GX*j*6^i~{JD(p zr94XClzl<9eMMGJ7iKEI=SBe9z7nX1r?ObrcVWdk8eh;JV zjN6jaJ=@jaDMOM;;5xnjDypHME9A7ncOg`+QB6a`01I5rRo=v_H$%^fLD}*Pr+&%R z(`3M4K#dxK5}k4`zqdo;s@}qT`GKzh6j5=vO3DmGg}6)6Q_1*{JhTe^)wOB#(9cJg z2;3n-EUIb(VR-He;wlh(&LDn;=I3|itaFk}c;9n*H(KSVrYNo|tO4TDT5DgND?OqN zY1yGHEsA>XIi2otGkgep+@Ea5bFj)Eua|oG5C95Ece>M+al6I>lUw;C3yMqYg(PFA zDZs35SPH-miQiT)AOaS-AhQ@QkW|2qThrTv zD6sUo02icRh&^%5j$;pfcq-#>OxH9zG!*#7P0S71zg90`ba3Am1q!P4?G_;b+J z+oA~g5%8QK3ZS_!-g=yN7eo^1g`zxIYRZJb9$M@+MGxO&ndxbdr~(!Pv(JXK<=9rJ zY_ub;urpRU_77B|`N$u^M{&N_(4fI=k{-J4NdS;})BisMXt@9fO7Ia(3SMKMU6bvI z9AG|vv2oq5te%6V=r0u*m2yGT`Qdm@qCrSazxqOnRzzG{y&35N3 zAW?=IMq?%a$n-71)4{H-^T$7XYwgC7h?bjt3Pww)RyPZ_Y1*M(6H#91*2))q5JVv3 zCgF5jO^WCmY^AWDE|i_DXOfopY)>M=R*`VICA=T7L*Dwrw!p5bB@YN2H`asVwqo(N zyHQ_ReS804Ay%CogiXV4+ctpa8SC*IoW49`5hdYe-@y%2?HL`ggi!BdsebwBE+Z2u zi~iE@t1rI62D%T*oesLbyQq+&JY#WPVRZuwQ=e*EtPc_|4AwhN)QkotKQO=o(r!iI zagfik^`2BUwmsKGN;af>A)7|OkV~e- zD!_N18Iv6NbkI7`NX2-_{61=zvFelgA-~>>6-$;DMiUmA?wqQh!DqAM!ZJ4ny*F+^ zdep2BIDGupYosgH)0JL2Gqvy7+1?J)e;>n9xO0iAVX#V@DN{TNperyA}o?TrzK ziH#--gxK=AO9CFTmWPmg7md~V7dsJ~Cb>ZBunx-9XtgDG4cSlVeQa-ORlfwQlTGk! zM46VZ&DsMp5>Xf=V5v$O@%sDxHW31qt~dJBD5?+aq*fBLrBVJzv{`b|9lTlPmo{tG ztjgaKYYx4cP;eM<=v9ZK(_5av9Qt8XfE0ElmD*rT#0vimmah;he=d`w@@0&m?NEEx z`J0)Wy_iwGHH&5}4h}X7*Kl<*;jd>=)L2bYzcYx4{$5~iO4i3@1UI-(&29O(o$lJNI!hUv9D}>XKcrAfBh|@PXi=G1EH&Z{ zdY^Ot*YL)S0Ez|boTi6)hP(`W?8>@v!1&uoJ<)#wFRUUq#K}_r z&>r%R{r^lOBqWiSpO1s}*n?3X^M)LPDExncS}<-*ll>Lh_`k;j)LKHG`TmoC_YXYI zEB~f@gZ;m;7r2xIm*~{Y^!?BG^9)#Bnets@c*6nzHDOHKK7*hZVds2*ETt@futN8h z`;n0s?qy$Ad4hKJKKwQ@q2XARL+{K|QSq7D1Ok8AiixM@=DqxAZ>?tohoV}}BlCNv z5U)8kJTBY+E&D~N_14GA0uwx0R&{o=5Cs#x_qVvMF6cEw+6H+X6~5u_lS;!R$UM1*GC9K0UL zVh|4ghMIbO$rS^S(U;#1rC-t6T`?Heh=6}YyQ>UR@9~bY8FtYsb{;-VfCpL}a?M3o zsFq;sf>qutDNK^(#XbhDZ>+h97~&96!;sIHL|7j$an(qc-}bOO{ywA=1xFUULa<&T z?pRZ})YnCwV^#t}_}wXX#{l*17O*eBCjZM+iiR*X#KIXwHI^)Cnm;!1DBc)qCTJyx~V zy~`A9YFXCvW@Rq3b6RvqruDRIfjTx4iR)V_|dq=yNTH2k_JZ3t;L_xOlt3UhEhgsiLKw{nN~r z;2x#%2OC_N<{Ji0)Nj;#i6t#(mbSBcgU_4=2+i+=E%&?yeR*Mn>X@X&l%fpk=e0Vbyl|r_@N6~#6T`IrVD#A+Ri4%ct5cQ zacGYW#-yz1!Rz+U--s_$ErqPEwJB=8E89!z3Dhwb_7Dv=w$-&hVL=$050dY-AL|gh zCGCqd`7o-9qh|m1G7_g*rsSR{FX%=_*reyviGoQ%^AD|p>d>ZuQK@Gy%#qX?XOYzd zjCMA?0k7HoY;nlz*rI0RO6EEt^iDsswcf*GkL-Kj_Mf0i*$_dTe}+V;Pl@Ei5Rq77ugL=fRnsyYO}G*Z}v)n+i0bx{YP zj9=)e@{ISL(-4*^mA$UG;#6p4!tMbsycDw&L%=0mn~+3k}4{$b%1e$A?F9A!p9)c`@Kl z(T?n$Os6cLy`!JT;7Hzx;>gc+4omloFRvlef=5FnPNh$k;5TRkNS2#_w%wD$So>7~ z27lw@d>6y^Bd(RH?_Ry8Z?bb|3fBb{3sK1@aZ`jjPqUfIn2IP}x?6w8`hM zv&r112Y;JxQ9fG|K?oQ!w zW5kMiY{Y_jyr2H%232n0aR~+pMhgrt7Fx$dN-`z z%?g1PEZ7qhs&t=GZ>_ph-du>F0-nyt5uV6ldDW%0>aLe( zKUrhbj#+LsVkfvg!$%9>ctQ*@c@69}Uhe&;`U6uLJR^qW8kM#B?sN8Tw#e6dvEas_ zxo{BLb#WjEI0*eb3Gx2FXd2;A*M;?D7d_Z_ zwrW~e+tRGfd{V`Nhx%j-Q`P)aL7TO!OgV2)cq=nvJOl_)$#m#x%|e*nSz+aux{Meg z)sQJC?-zpT(Pau#=6}iy=tjBm4EDjGxqSi~nCYJi)9(&7?n|9tw=w(478?PYz&$FU epX_gNZ*6q9aV_loGR20o<|nU64Xzx1aQ_dh(YjIq delta 12698 zcmZ9SWmp`&_pnRRqQ$)wcXxMpcXxM}1s2x=#obx7xI=L*?(Po7UEb~U`+s`(y6#MJ zCOLDGlZoxbS)7~ykOWw*Lwx%8^I-n(^2zS=|E~YSbC&jvT6-_K2OOwaP4nRZ?fpsxNfC)e$8_IV!F)y!SppYdjY zY}|9-cW*qMHGXE&_b6P@*4DBs?p^QiH@BCU9*ORC-e(goHpAjq9bMm;>g&nf+nYbP zH<_k_5Yw-Hi@4!{&rjPQf--`C3y6BnuVq>`FQ6A;b{#0mSnleZnyxNbEjeJr0g`dUTD!TP^^C``|x4mrhJ}@$J9>;-#az&#tRfIAMiOUc76xS#N~E5vH`5 zULz;gr|}_)9s{nEiwEG9(GWm&Md*G180$~-Y*C^!X(JO+D~uYUiuAV5ZuDA~#e2m@+tp^3>G zRW|Fy;j5LNp2=3~d6V!9Cw}=3KfvI>^f8&8Aso2hCrrvoi6trjVn6#9G7X&7ovb4` zt4eJWXhhZ9kZGmD4<)09Dj3rfH?mqsDT) zr^k4)3E91Kx5tT=BxP7*i}yws=9#RH{x=f7iWU2V&MIH3u=qlreU{u(=-*{ zlj=g3veWU&-~)~-#s+e@WYDyP3;p1fuA)!S#kwQP!|-J6(qWxGJZ>hXA+p$i5lw@U1mxIt|?VIOGX%c%FjAC*UuZ_pHv^mC}{qH$M zZPFewA1Dv^0BQxJ7Uj})QtJj^$hPr~@s8uq-scnaJJEc&tj(ObNk?%!d)-vQaFqy@ z_bU*Q>94yjokTe(QiHJe*GRX0h<3L}T^#e+$&s&j8^c}ke55_=)%yXT>Q12O_i6q3rFNB6BdhLne&hxtx* z{`y|FQ7@i-S)jUyu1<9cV%qAfEN}c}m+ADzjclhP5~?_JKIG&dO$1%Cp30xb*FD0Y zZEu4&2$(9q^gs6MYBf(E3VL{yEq$%=kJ#|G|85aqAiU}TUlgK(x@NeFi~`dPI{c|p z60JRImK%rp#lSllt;(NP*x>vgr0Me2PTmKD3*hM)U#TW@Tuoru2JGW4qjELir!W5E ztudp4hV(-#7-c1zmB0bODgL~BCl7xE8QBs000`^cGY!9w{kL&S&5xVfCsY} ze*PYzhX?gz@!0lPkJ;$Ceu8wJy<2&$=rqez5>9^ujNDv>Ifnk*ryz&S7UGt!*4Eu$ zUV~R(b`>neLchK|hDvjiu^x*xKV)fgd1)TI&#Bz^@}I!CwEVg`yC1OhqS>wBoc6Q!a!$b)vw1yX^BG>)QG~E8_ zo4Fyre}VFRirvhSxKFwJRb|d)r57LJT14=Aq2E|!*+vaYIZXQShu5!lo}WIWyaWtO z__p?fG9NebRwNGuyM*Hv7ziq#KGR4yi{}E^O&2(-Qv@4Tabj0P83|(Umrt>eEbZ;j zfwx0mBZ^Q&t4kXl*T?bViZg?&{oL89vJwP7SsNGE-%^NY^i2D8d)8r@KMt zPSBg}L=yfrz9onchKLI<90K&1(LHVFNvc{f{??|9a+2KNI{J@~C>EICBR7A$m1F{r z1RkBp^56O1H8aX-x1%e5{DMxWHokF}_)^ax;UbNmVG!-0qt%_RoNWrzj3;udT2G8(z$$X;hTH1W5oNcvYs{nTjgQJRf zQeBUZgF05UwrgJo{=(X?Hf6U9U6)Nj;tQ4yDgq~z53HZU66&VUg$piBR>~AACk`v` z&a3?fYAMeiYABz|u=o#K;f=2@x<4}e)=2jhlr3?uTfWC5{9mvY6pJ9my`7X#dch!f z1MOKh*c)YshiO1A13%gOwKzdzmW%H;cG@R#}Q=a_&*B5j^1`H~$4r~qf zc5*|59$BjmrFojn;&zUcHipo+9p2w9c3zUay%n~e?#_pYD zRybC7VTkV|5n~HiLwkz?hWkF63v@e7PGxP7b9aY~Hr;%-Bk6rNe7B#%Iy-Q?ATze3 zbp4T2!@ayCB;yzz;acHb=!fw|zM1U{FX*x$Wbo##K?uXHeZBG7e$C!vZjQu2f0_(P zyzpvL(a5$3Ld_2gQ= zsq)BmI0z~J8F#~ztXgu0bW#16z`i5JC3b({fd3q}%Wg*gLh;>P&#&6;@ncr@2(h@{ zLojQSDF-xGoL#98=(wdzzhPYTrd3GdK|Ud`ez+{|#`|L^i^-%3SKW2%*Lr zn{HlEGR+*#fyE@5p@eMHM)^#~klvtI+9o%jQ&6WjY#D(KfcFkSf9pwcYMqpfv2%XE ziO_$xbdH1ck-gS~G??ifHSQXTv|gBK7W=M-dKpPh@{aY4*0}HOOY#S8F7)AO@8mkp z9w#rX68^T2LZ{89bv;U@xRX3=2Ldv?n0{y6wfzq3B^g#uKSe7`JLB=s?LfU7at6Ou zWL(y4k`jC<;PZpb;5l#m&oF~)AfRx=9yZ>C!QncA!_8o6L!2eVi_!e+p{Vu6I&bsS zYx4R|>&pWGf1f~*2NBXW-|ZqvY}M7}EV-`LrPQCd$hjQ&TR@ZFvb!?7ee&V2yQAkr zuRhP+U`LVhw|v&!!S%ikWw%yqh8t$qc77gSNdt8nz_MrBX`$|V<}|kX%Ybm^Gzl>7X`n`1#_r0*7~am;m_P#$8F1exw@x-01$ zBm~Oy0A+mzWDiHTE6t%X|Q#(qR zvjj_3C+K=P(A)MTU%OP+?V6O zIghX3cFQ;8(e6M(Llrx6S3_2FBhcO?&@OD28bPJ-{X+v%yX>N= zwM_}~XG0xD&1rM)g?etkH#!>^cpc$21*%hKx-g0jBbn72#1v^?E(=66<^;ejbgVE|fXX1zgGA;saSWR#REC9PRErlZYY(30<# zPI3*mh>wWb_n}HY+@ygg%9%>*mBvZsT6uj|PpxXysdW;y<=W+-Cn4 zaq_bknff2G^@^$*RT~|47JxWmJORgMo5E8Yg?(s{=zn$eLglM!kbHP;DHoS-aY0;d zQa^@Hsd%fj@=2&f5Arh)qI zkt#N8E^29qVprO1-QyO`KUHpf5~}*DGhYuiGGOMewK8^yaZg7~k0)fk=>X@fEpoU1 zF8{JxdyXJ49+G}*_o6z#>KyUwCndTXmgH05{+$%>HKnB}z~E0=w5LfWvEzu`0N?SRYdCdM_S4$7 zcZR(7#oG34K^Dk0+(JDJz_GPVlVPvIw5p$5cXfJjJJt$?l}LnM5o$;UxP_JeMOXfTzAOibg4gLo0()zHWKL&eK0`G)dQLCASP% zP{*>-2j8(Ka)`xa2(a{tLYaMTUlTcfmeO8I7@EQn*|tlY{@c6`sEgwZn=n06V2oi@ z2QX{kae+2s!iL>%Zowv&hg0E5A{W^ZP040pH5&v61L}R8#7V zw=u=KE+NtNh<{Xo?627D>96MCejjChbX1ZWFOw!-t#B1To8o)^C=nA&#{-kScb6wD4J(Z~G-M6mJ4}{^}25v)b28k2FU)$`YHX zHjuWvXX}$X%&L(ORaBl#R3Gf@-Y(c@;y~aLM>B@8*+&!QGp<*S%~EC)j^z$qE9Azp z5N9=wx6Z>E4^<$!HFUX?23H-g+58rRMA#=ZXBPlgDJ@E^>cN!S2ad7gF&a7R7uISe z`0r!U$Up!}y(5M*CdTN+(nDs>J|MIG!bq9!D>x>L2XTqe7Djf@Jh&lC+^>Sx>=+`G z4$rsWej998uI8p)m65%7-Oow<7UYPA7R(eRw7GUH;xAOT4 zgE*P_*J7TSOC+jZ?u7t7C|b_@;3qZqwCqr1M0pTEpab)b6@7G1_{p_7OnC0u)_*7~Z}s$~PsyNRiH9M>0k0~AMb?MqxE zpnyEb?j!EL8OKFlt_gWLpHTks%x{UlitOmwO3=e@)Ajm8KDMLNx$zZ5D0^d%ecXgh zo@WIha`TnEXR)O1YP;g^*&j(I_}3nB9Ai!oFF+53G;O}=2!XFIdw zzK5gs(g!B5^lk;fRrt{}0%-s}xkYpudozA(j%h3$5Sv8q;Cr5;o1;>lXT4e33H$)S zHAP{AYG4Z=n5RWG7E5QbN}gU0>FSYnF`B z|3K<$Q(5NU;-kk{cHgF*nmPw-TC7-RPjN+Mv* zqwuE}TvNwT?8R&KTd|oC7-Ui0fpv7u2tEEyWR??7^!hwjo9rQ1d8^wI6MvX-2}%ve zT}T&UOlv`}CuleWd&$G&It`#s*^P{jUKD)QuYfdp!zzt3_0oH;{ls$9S8LM=*?AEV zvp?TCp5SC~wBY0b3-UrhPmwgh(Mme5HmA5}hJFGETd%vRez0rg5y7mV7LAMG7 zDXka5ock!?3=ut+cPfvT5Q0v(e&QIY9Xot+Nqs zm;5z1+U5KN<3hBFX6KdB9D-JQyVp}Ldq>GoS^pQc?JSGo`z^E@&Q=M+Y>-(CIP6Ovf?T!(X&b}cBn-A z3I8W?%Ygy2S&LrqQN~E@pk-+6d!nq6b1`oYqc&^Ft|jeEN3&iT`vA#J{hbJiZWj~2 z;tz~*?hTTz%Q=U0#ef%7V25jk55*c5tqS7ay)#vRfk??zAsq)pFs8fYl4WNf&n^>& zGiJ0%;g7ck`T;=KRuX<_N*L4dIV``cZiTd&dB_?Sn{BT>ZeR{XlrExYxg9!p*PGH0 z9W)$`Xq$ZHpXC^H67p;(lIOJh5BNgF$SSWoLxC*EUh))~p)^OTz^u#$YcuvQZC@+q z>u{Wn8#ORAl(YRfbEtM=jl_50PTQ|AbRBlBG0N4qznKI4rfYbT**mZ;Xl<$(KTVhl z(O35G!!OviGLT3Z@E4}YRG(U7jIs;+r~mYOmbSTSIP{$<5gn8gML~4}5$A2fklZ1x zR2DEKpUfC^vzaHoi;Bi{5W9CIe1FmOcnO|Ur$;z?X3kU!4DHrM-d}g-wg; zElPt>s(x91XYGkG&xwo2P|!7BzND*MBq1s{Hz`6NfJwE71d_|L36~H)RT&xv8H$%{ z^oL92^&Y1NaZcuybA8s)RHzA#eW>V6#woqauwo5XPG8lfyE?v;XdLq zkbvOls@W*yE80?>p`~;iAtX~$VH(+_o*(T7W$H!i$Ol%8-Chu!qRwR=%OUeR)R>ss z`UH((9H4TBExL%gn)ei=sbYm$z5*Gmq*uJ&0tJT%KU%zSlB3z*oHQsZ+G-#z&qAdg zwd35ZLK!%q8ikTQ*{HRA{|oD<6YUNrEPzm!4Y5)OS5`FGX?&#wC-9b|*4nQV@sOng zqO35n^VZrT^@50b0-1uEJs&5g%1zvN0_KQ=tgbwzs{A4n<%k8?q}Ru1mHC+vX<_rdCij;XFnrq0U~D8 z#Az1A)|SlpXweXj=Ml`a0Uz)Y*h3W4m&C~fh#dG-8;NnB@<^TG!mJp>R&xe)VPwG`%lf2hBDDYayXvOiSL(d zJTTJY^JHcduEm3Fpt5M50OY+>P5)CGMbb??aT^toAVgjOz6~KwvJkt9s8a5mi4JKA zE9odm!lvd^X+U33n}U~ko(X*yR9--=BjI3;RL3Z{P0b-sC^zxvs;JB-0Pz+^bm09b z5Zyw4_02Gi0pafw^KEzyD%(~M`8eV zw@O=mq!$z@f!=E63pQc}FGwaLJ}-wmbQ@DAvZOv!JVH3B$umg&Q^O#W1?*|^oHkXr zeaUCq+6Z<1k%%{r?!0}haz}Yz&ZXK*+pDp*K{+;1$sl$(*)-tTXjY6yR+N4y#*xi8 zCWx_mM*^paC8&1}!m%P@0_i&COe8yCCk4jYC@Mp^IKO~jswsUyXuXRIIQp9~_&HXy zV4Fsr42j%{Y{W5%dZ5i-JyyC_;VlfAJeE6j)<(8J`UW$gv02TQk8kXc`^jC6Q0^h= z7DWq0p=p}RS{5LC{vahpepvomfW%!DplJR_JH4rkX1#C<_u+0iazQ^VJkY@ z4dr7%RE$(VMhjp3&^86)N!S6*P1?@`m?K@nv~3(Xjf;-i3vFGm)bguPoeV+nq?XOUL=GG`FZb63%+ zPG}L|56FZ+(e&NTBiEmfJfEwvtvHg(aMGDk$30qkjcTqO`+NX=#&jfTD3cXbN&rg` zWd*H>!jJ_!VOCD-8AVsE-KNC*b?5To-FCPZ+skZeLA04DQ9$1SVe8`9IJCTb@bG3; zx8@}C0_8UJ1<$X0hu((MM4-&@ibBYJ1Ct(*xam|}=8wIv26S}W37}VDZYtr6dPJS8 z5sw0LxDn5u8WH$KakehhdXGBewe?em2bPL)7$nc7T)oFIa`|)XZf8Ry1>sz2k0Qjp)g?+$&jT)!3l^i^n*OXhq*f`| zQvK!jKtAEriv)7Gk3(d}fZYTKN!T#1qZ!(X{0<&kO)GjW0)4Q+eS=D0^0rg} zNq{=88a3HtMGp4P`Z6icef>1nV9+uGvw@ zId(uy?=j+3Qfm`Bu-sO3cWbtB`uR1@Hd@0i&-P~3%t;)!YGclv4DO_Pq+htA{125u zu0ockdONd96%*uKDf%Sh$!uh4;K_zVLuUXzS~18&L~QIp}Cf+2JQH#JKKb>4KnLdYKtB$ z(Qa8@r)|M~R5Nl@N!nzJd6e~1xI#pUcY71Z_`FQUH*iXSiFGX}zSVI|CQjGF%MEJ$ zbghw4i|Q`Us{K)!FNK=jz`iDTc}N%ddH{_&+le<+IG9+XY2`4wZmM{E?w*fR@D8Bv zE@Rgc?=Rb-{d%YPDB*6&fdf93`Fa=sBH`YLC^8>FUhpp6U6w{!r&UIKVj@FeyEsJS ztPNY7uxxleLPs7oRbp~RK{!(yS@rb}+rLoeMSU)@47=bRda|tXV9rH_$35FtVoLBF zyP?`Qu9DdHr8>@h@?9a=Q+IWB&3Oh4w@H_Kn9*ZGa)=3$3@Oz!35;FktS%|1+ zHwQgbI~`^yqF*XRE*K%Kz3fJ1#SdW557v=oCM-u6*@=V4$4$ z5cB(2m2u^m9-QM2s!;z2wtQGaSg+VXsxz3mfu)7CSA{`}TF6v_bR5Do{~3UC2g6r5 z>J&pnDhZwz6lZ;@`bY(J-p0^GZ1Ka)S~(ME5`0t86A%k`H^X9+FlAyhk?VUN#~ zNvK#^c5Zw`qmNJu9FR7xUvKK%2~EZ3(EHKTm2}(iH=07*EUNyc6_%A61*^(-PEqfm zoJ}Ouj#Zgy2I|_7Tx#>U02YcCumf0)MPHT@i~Be~>&!I*cpbIYlQwgNjrTcl zzp-z`LpY8Yj~stTb;;0pVAcQu)}87Ezm_?uh$tkHh9CrLlvLK<9=~d4R|zX5?XDsO z%~01jZQwM>!6LEKMFLNx@`V!W%wff&yb*Xf)Hoe<$LlFuvzn{~=e-r`L>xQ`3Ch zsZ27IsNg|13)P+d6Gf$$8>O3HZ&~E7HQrVoEH3b7(&Q!-##~`WRs_cd5la4>MvO)@ zl%;S&N-bGq13og3$|gjZ2GS~7gi_MIA~eJ0IipePdX=^m02P(R;l4d@O&P`Nj91)S z=e{!2`KgSXGFvUn(#@7kzib9KjWS!6kGKQ_!gj76k6n+wU_|wNBmcsJQzG4_A)h|P zwn2l+I(TWeI&c(fWo}s&K}Q2UqU}_>LsVtutD&Gz`bfTW5XlU|?OIRB zeVrJF)_|K_DY+E7svH4;)PFi3x>#Cx>naTBY`d(?Gtl=!Qxmmk1Lk0Y_QFEW;G8%&%FAd>jnZz9O&MsjmFM|l`4P<#P)4?E$5%#*})VxsJaUCXZG0T<^1^`r~;#pq-g+bS#)hd zD-Jiknt-|^sO}eL_k;?|%V}%|Q<{{g zz%M(bK!=?d=4t568NlE7`p?Z+jvPvpJF!72>}De8cWY)k89d|Q)mk*oRHQFE(Cop@ z!k(c_lQr!#&8dZwZ)a30eaEbz{nSBGm^&j5w^uC87q!$ZovVpYcK|#j3So9uN|zIM zCQ>E&9eeI7n^8A6d+@W0i*gabdqig?!bVXA{%FpXU?c9TW8$@=et!J$BOz!Q|4WS@ ztM_B(h4ddhp8^O|)D0n{9M2skd|$nx{Mzo*x?|+CFX6Sc+!m%x`RT11Y;iTO0X)!d zuBPD|in*$RC(c1wfQEA1+9rqtR-x^!_Yr2@i{FaYZP;(vbm-Uk)MCOk;w{YDsqpfD ztR0>z8TAVP7MoNLC2|pH7EfE06G1B^{M*a-gLtXre5u@TUO@9y_@!l%2@C*eE^+w( zw(<1YT(#~iQ}f0V*W^?X1>cjAX0=sBZHm7jbs^{sw*!Ly8wd9~C+qSiua|WiVlB$2 zv`FobQv!(~oJm3}iIYR86WhrHInp`E-1=z5;FW)j2IJaGqi=H*2cSZ$|4WBaZ|9r9 z=L$mA4FFS6p+RzK4k0pi^Y54@JKSRt!D<|GrL|M{xaY`Qty@yW@G9C&v>8cJjudkG zFMumap{9SbbS8KF6cd@d9n_A0$z`VOt)M52@!Zb>31ADcdS0!6|9dtMQprlbCItGw zwm~nk4bQSSj1SV5{LhNWJCN=loxn(pg75Bla_cr>5F_zHMgQ63vq8KmSEo+&z8a+X zZ!VBaTZvYY({76cU}61Jg} z+iPRnze5?3gi=YF_f~Shv`aTdJ-Pnxku-ADy{Z4R46Lp&3v9h0eA>UV(MIod|CON+ zeq#AAk`1qFat6~NRRjPVW0y9OgIlhsKX(m(`Oo;|FRDYMj~2aZzAx(kReCfe^1i8Z zZ%Fw6T8cdnQy^0%H)3ZIu+TtRlBUubalDv1A9bYZ=JL%I|9j|+7)`XDt;1%Jn-puB zsUyVysyHiIpnsLY4W<10e3lWHy!0I7asn_R`a->j2$J)&$)ikbtMf)!iQ3d+9Zhgx zt~k+j61t)J`H35R9F*&>uUe8;Fv!&qp-1}9J^3HF^nV|}JB9r-7`lGD8lj*=8!xj1 z;{Lw|MW+}PbyqiyS^MX`IwKC|i;C0xl|$hs?0+4O#rOnGxNBMZM<_sNSF=gpoh*u) z<9#R}?CS||e=cp$Pko$2)!#!Wj|De$Pt3iWwgCRgic`p6{LTeSw;$0)<(b|DN8XG+kimh3cW0p}aY5I>8QSb7vgZ1$-(bFkgmHg3P$}`1Ri4znABt zmz?E^M+4~hOh81k+(x|wr;5!$Tw*D(UbPfMt(p`OnJ8gRk}TcC^Mm>h^p0--N^7tx z!}cAcPYnO>;{BiA|1RWA1FwLBhwD|zC=OEHWsNxu6aTK0Mge15%y!jn^wU|!T;_4B zO}vFXLqeMt-9fI#=F7;mfTyg`$ZzPj*j1lYDzR!6lw*p-GFczR=IplJ8{k5NN zZC@;|B6&ivKHGi;q0b+}mR&O=_%b)XwHF zDm&j=dc~u&pSFM4-k$q*1#Ny%_&++n-r#rlY9^lL?2zmITvBF2_I@tlV)Vuq)(Yt2 zNhM;CSwVHb*M6RP()!|bwUb+R}a|08b+e@@BeP_cb2PuM8nv&qh3xOUy@_;A2CHm z@5cLLqJxIfTNx}z8#2(ZxH{QjQ?iP4NtjEiUQhS>eMBkO^<%|zuWEgiti-_E*0L77 zQ>l8hpIKRscSM2>-*)n2n}5l6;^S^0TYPi{ZsZjI`;z@6$7m5aiTM_TXi>>di&r#;5!*4h@bK|=cmDp zaFp-Zej4EdAGs~T=)a>J@SpbHi1Ns7y?+?A1$6SSp$y%k_%D6pM#a|bzbowf(aqx; z=D2~|JcOR`WfO2F#>JeN>tDj3Xt^A2r$8G@_1r(MA2WXWxy$^dKWUEn@%1;|VlqVb zSY|}LQRzDK<2|%;MO*@|% zB7HdIwzpE`6;DXfI0h)r)lTJ>04ZhnuN&tf;kyj;YoP!mCd9|;Y1!@UJbpa)hZjT^ zcn4$(f9r}5731;EeUrBeOp~`$FqvRh!L);U0TT{p2uvrKH!wgjeP9Z~?1D)GGYh63 z%ng`EFn3^L!TbSJ1?C*n1n`y(j;v#v7-xj-4=$xmn6+wwKU1Wa&KMimxhR|c)6|%H z#QpYt?!+>(AZPaX{Y0l{_WKr1&--tho`4T9n_!HRjk-OPjW)Ywetk58X#mp!rVdOS zm?jw})>M25hUJqF8>s#dI^47F8niP&B^W?8+S#JUm;2KSsF!*$Hx*F6f>5cl4wfI5 z$yslI)q{;U14c~xC*Bf!etCAAF`aEN;v&90$inm?zk@~L|3o{CxM$Pq85JmCjeTGx zE9$}fNwo=-Iu~2=0=VsuV*cQ;1@UHNX}~;9agc$b&yU5!8TTNm77#u5^~H897UEZX zlOEk!6+JcrukF}CZ`X=T?XQY|A`m?`ZElSIn!{dFt@2RhyY}_4hyd=XdA=(+6pwi_ ztHfpoD>CQ@EA~M({r`j!*)Qa=(K3b^)yDaDk6D5am6G|`wNw`GBTAFo9JKe8pd!3 zx5c3aC&VN&>MpWmXdxH1x;392x#}u>r)5O>^PJ>fZbk2hsI;q;|BB07&LtY_1^s&M zBevA@AniBU8(z^7!Z$JMJyTeNXha9e>47F>y=5x@7$sd~uW_`_SXT^G+z7b<9m-f6 zwN}WE8&c{yXoJXq-vz_4e#S)j+iV zTRN1^D?*a_ixs#p##c&^ok@Rf?#?-Xwaw0W%cT z$XgfxY3XaBnUr?92yyq`!b5Wf^_IXVwz2!pzy2;>fzaU7^wM$pNyN43R&*&HvM0@;41ZJzE8$4JqI{lcP#<(C#0y|Xr zio2P$3)ob>Pf?TuESwf`8+Wuk*v4O?Iy+s7c(OGS7+qQDE}{TfD4k54%^!Eg^y#(n zH^RkBPCCIv6r^EusaFI}6aIV{2Y+wY3up;YLJL-*1-+eCeD;fy_PLN^n!Z#zcY!Z= zfxi!HriX|s+|jo99BkJLc<~}>pTmf)x2VFXn#DKKSs$GwweR43m7U&p<*u0fUEqAD zr%E-zJ@86>6EI4?P#b^EYH3T~|HeBaDEN$_nTa~Ef_%nD?c~VviR(ZImVDvYH#B|&g$rjnF3jS_Qia( zb#FMsSK^y2e)b{e5gemv;a+s6fno2XZQ<_WR#*tc2rbA4UfuFvRD-6#?x)c9mz6qVsY>N)|OABtADoqAny6OWNOkjAg`5D0jFe92f2 znCUF8o#viG`ER%cu*^_63w-8z8^W+SGf{Bcy^SCAwc*#(e~v)pO#s{yEjmHa zX>q&I`wwpKg`%`9`qV7?mh3KTS&%Pps8$6fnwljF1~h|r6Tlpg0x<;8S$H9MH9j*9 zloV+FJW=o=gmk#QTFwLWC@Rk6=o-l4Qd3`7OuHCi>}4>JTy20$?>_AE;3t4B%rFU~ z)|lX2gD=-%=f5{6tW#G#-z4-F=8>voJuq)vG1JM2Cy+LNuD%@ZoHELIJ`G{SJ-nvY zQxBlr-AS>3t)5wW;;!dT*8E?KD&4DmMogh< zawm~@8sqE13IxytV6m_Nk}x22KQN8kPCD(hSy3ehe5d!ZBfwnMKY$(v$vesL_5r4^ zi)sg4?KHy=0FAXrkzI{6(1Q9JJK%m)X}O=U<6oN+ZaDPd4;ROllg-IHcn2C_@#xY5 z;-h%1jDx&jL?3wIl;mj~>X~3fxR9R`fRXm7yB?Vcqkjp8>5Er+?LT<%U%mq=k5MuB z7fv9eue-beE{xgwiZGh6quo7Y*v79$)M6Cu@Rgdy-vz!h09gQI{m&hN5g0{_YQs9fr}G^LlMqk3;s4TZ zhi6MvEqIO&!-)fVfrGhthG8%m7>Ils@HR0=?J`jN0R8}$H0>e;So?ns|7ANgzg>#7 z51{sv8ppojC8qPv`YwCD+o^~^1FXR;DgjLJ4YbpQ2tTy~dR!b;64Xswfp`LZ-dfUv-FZ2qCtgHh7T`yL(+Zo@n&yVZKqw8x6z<@Ed+i67wX?#7$ct`HF99d< z{#7+c>$!YD((J#dbae`Rrl*Y`p#?bpXC1ZRqe>h9Ma_StZSCgwBlZ8!*+6T5wBY}> zdD=gJJk+YYfxvuS$rDU5mj{HzrlTDoByKx>`1QY>K%FWDfV)GD)gMLz)Bs>eSKir4 zV*oC|!oUf3|NoG-+lZs0zL;apa*ZYbM+(2kX7d3i+Cd!9E)2!UgeLyKE66DRzsJB| zx(fvtP7;oje*?tUl8yV(KU6wUXpBf5!r?ZPXTZNSEKGXryjCP52&w4F1ZtIw=XGVL zHUNzF6SN?Je^cyhZx{ph%f-T{LXHB}M!eh6bf#(OZD_B?|84@(&{cUpGuHtSP~ORl zdKiqfqyo?$jx$&L710zYvjcv?*Dmk2j08<~{2hXCq8#!VYaFyNzDuht0*eNBKV^iH z&aGpu!FCME!{FxEfJh6zHa`&Gttphta~e?r4|FczZT5`r3R~eD@Kd>@r0) zZCjV7()Q74%o#(XwTth^=_rR(Mrm9@6Z!Am2T|2_V7M(<&>9T4219JU$2br2g|@|w z+A|#V0gz84YP!8%!9%vjJJ9LBMPc zS|sq2RYTrM@RgiTW)Fwtd+7d#J~QVEmX~gSD=&6VlF1f$T@|z8DrjOjA@t=Dd_+Oq z&CzA~^<&cYt{#$}1q2+T{ovc8Z$)9qm}t0yjDVEy%iD&KAs{-rsL;EosUZg65VOe= z9(=Q+g{BDc=sI1VFHhrO=?3g!Z;=aH-Q;^+cNh3hf0c?Vpm*Q#n*go_XKHn{1EMm!=6!o{=ra1b zS5ZYzlDCALI5_0J%GKs1EeR9uXzDxC2fdXrmG;rp9MT8k$^imGJ{C^6znf4xqMJ0n zrJNJrwQmjBC=6b2FkAw!|2?cFM95BpCeINQ3$lNf9@Y{4GodL-=%;tSc0M=z{IwZ> z&9b6dUj;?(G2Bk`Nk;BisJOjUA-_Fr+4JhRa>~Koge01{n{m~$crh?x*#j$tz4j?A zTCieu-SLM@+dRN#-9qMSK-oD%DfNDNdxwdaF|Rh<)OL`vte@)D>fSzD$4|)KlOz$T zm&6=Q3YKuY01o*?0k4lG1@9%42A;Dmed^Z@sSCCF((wB~Td=kbSlbRXVRQrk__VqvP-~X`x z_(QbehiK7{?6*Ja8c&q3DXD2&yYzhYU;W^}`pJLwqyK+4;HOHM1|>|SA|_G^!&1a- zC}LI*5?1>TjyZ=e?Mo`r-;0CEITzc27k1JwYWD&rzMCv0-ViD8K8A3d9*zF?Slw;^ z!pr!Q1SJei2}1#zqPT<5KFT5MPcWzc3f$2r!^=V?I*J&3Mezof{Q36~;J1jn7_g|6(Y+nyU$N{)jtNC~sGp2Yv zM+)<7?39~BypK*z`lv13A>n7I@pk@Ib-SaF#ovZ%BvM1(%f-zn^S&|1ArHqA!6yr7 zhkGj?CeHg6L&w>TTNC5W70WnSg*W=P&gsOy$@e}(?p*FnqyraH$_|0Ca+Q-!q_g>z- zmXT|48Pl|BZh*uuzFw(D>XAw=u(%@^#1i%<0>j$i*akx=-Ar{|5Ivin*l)o4!n0&d zjI3ZWPxCXIx+=!(EeT}H$*nc>L}G&|9_99XwUwUOpDIWSt%p{4^Re}WdCt~f15mX{ zi!EMz6)#X#eh&aOIN5 zd>Is>h$vACvuq!D^U4-tYiQ$!4q!d5!N8aEAC$u&{Is_;cXV2XRu5lf9+NY zF05U%i+V3>VmLb+fmUn^p1aKS4PpM31EyQK=?fL9Ex@ZXlMAE@ic^GxUC+*J=x$JN zcH=>c_i~Y*QGU>9AeNHoXDN0Hm;X>{fS`LoWZ-rraXCZ$B0fK!-}QvrrIeJk~WQ);GSNN@*xt+qLoQB%OYIHP0YY~Gq;72?r;Y-^|-s!aZghJq9AKzKyZbnnhHz))pR5a zQuct0?%xt*5lDYgQafZ!*D%)82`NfgizS!Eb_a_STgZiR+r1|DyriN;HbT+yc5aX% zyl|h2Ky;p~*-a5#pd2%F_$u-}6Q*-}0p-aJOGB^@l2EoYCkxc&hZTHgTQ3dsyvn)B z{hES|+S4o817cW`30m?HzSKK$)!SP|Mz}ygb|&XFL<2WChCTC#Xn}!Erm?|!>=*sC zrcwfx!WK!%!dq^bDB>k$4Pj|8QYs9jd)b+{E)p)JSN32*uhbj^A+OMjD3L>jRrp$xdNoqil&fL{ zJm9vHf5dHdeXpYUZa<3zh%bm8UnDG$RcTV7dV}(^0jdwr@Cxr}Yn%0^ zAG$_?NeiCQQVZ<%tCBJ9JyR3RrPZLUNTL6+9rp8l33!oQ^*_WQG!aI|_LH$9(W)T4 zq=}>7w>Dk+@q#pknTZK*bRsu8mz&EEao*IP!xW7i@zHi*b>6iC;`Ir{eqCsLHN zACw)`aRDXvqT(ZB95#tT@COLUDq>S zxZVxRspLxR=b>78A_m&!hN~3rWCkPn=I}R2K$<%mnVSW(Vi8SFkV2ttKbz6S*0?}) z&t%tH&Jq#(nFlhou;8_kQ{%W!ST4nc$GrsH$pKt7^&@=iJGy)>+s!%XmNPOhV~r)b zwg`=K-u&1?m*{4)q-O%bYjOS1$kSi)u&41wTRex+=xj!~7E{MKmgJCoNKdfVAd6>l zpPSI11PMbnWpYJdpuGOT(0O@esY#j0b0BaGxYgZmhVCvovmwr+){UVEbCx*4&VG--&1HYl8cqb3!lZqgSujP(FPEK7JTGlv+IjM^i-M%UYDn@#bHSR zgjXiJ&bz;S^sJ#0z(^b`XXMR9qBU=+X;ga=CSgKwe;X-=KaLOmi_&E$_YZPBq9^g% zGsNgk>My{z+z8mTTmgsL#|1dG2S3OT zQ==EB?yY?(1#qqea)~{=2NPQNgq5cKhdV1G0YOB4cAH@i-$eKRL9c}jyMZDsow>{; zQf4%MM)Gja27w%l5i9mWdGcN@5vP)p1KWFDJ$MFH5aUqODwHdeXFUvSDCfraho9J3 zI6Ug~L_GWjJFZ_?aN`OrS;~MDB(lN!-m+7CD8xZ}9Xj0g!SLT?b?Cn|E?NuJMnbO~ zCXOJLjarMFp-#N7v1`GiA~}zxfW-g9>)#*+%o0mm=o&Lp1@_KJEV``(deqSj0~Fc% zZQM37LekGjwP_aw7{9r8;a%j*{yR zExUPi@-niO?90#oE)LmtI~tj+pV-fO;pdc{&At=ESOm@EM547)i2zVal2JLScwOk} z0;f23<8F?Q{ob$Nn9{~0=42JqDMvIngG?Y_i=&@|n7kE0DWIH#R$A70m&v`!++&;Y z&A&0+DYD9Qt_<*2M%-4z)Yw20*MAcpv|T^@*7x)}%a`e=!&EVbnYQ>Hh_E`r6Np2h zm2=5>r$ydqpy0NC>$x~isNY6I*#a+EkOGP9Y{L02`LHZECJu>6K4mlF08iIN1axn> zNuyS!QMU2|&Ouu(?8%93gS@|fhsQM)RwDEHm_bIodu_zRst1ANq6G=EZEk)OBO?^* zmd8jxdW|!RZzTt}lqz3+9V##@LOPIi#W`rXWo^>?kxD{hBtS|-YqxVbtPj7%IcEJp zEneERViYXAKlLAJO_E$3JUwXM!LHF~QNJ(a;hR5O*y9uI8&3GPs2c4Ry`=3{^2<0< z8Owv%^ho>)x8=k9tNLT0U>BBj0c+X0O8o)PaG4s*DFD(USz#NZSAo2~BQA|HZACe!ZsUya6=)hhH z9+Y;K*ZYIZh;(T?D*)t&F3)O%aO^K%9|0#AyCXGF(DjPaPeyZUv*gD1R!0wY@My^fDlv~QOdb(cBmZ3#yT%X-7b!52TlV51#6b7b z=_VdhW!MNY;^2k^;TV3)y*ao=!5Cs8E;X4vb)>~j0?;KhLvwCRY~v-y9)rMJu~=O^ z=qQP+H=k0T4Fd@BEed-L<>u0J_9!UA*%=v?MYs52xM{VnYW%p=2Rmg<)8+QY@PLK+ z%>)W^>Q7M$9)C*SF^f&0C>DveGdD$4xA*U)z|-rwsHog8E&f069fSn)*5RN0v>rxB z%TXvI9Nj-C7?qbSs{-%kjBk9amv<0`Nt(AeT{9-h8Y@_I?#Ng@a`L50R{N{TKbBf|QY|dl36rx>PJLl7vD}Wxe3pw(xejB*}6? zy5VP$5x5D#D%6?roebVW!OEm8H#XeSWvB`P(e&_h#&$R8WwevrXY^bnpepxYWtUn^ zOPTS8)1yx?!u^eSpJR|P8q||}FO|V^nE!&v0%&{YD%+C5F;Zci zHFN5|;~pfMn*!#NSC~EQ<+%6jSEz)sRQi%(lE@G%IO4}Co@gFas*|H+h2WW@OFJ4H zgPEwJ;&-cx!)|=Xo15*WTFLw3*rt=Pf=J&b$Ln*vBj-k(uy+)IqTd~O$iW}=OYS%J zWC2t@uXojl-FBmeifHQ2(ay z5xNM}$iuj8>P=qTRKf#l*JvL5lTzbPpaOs;Nwgcow+{V+g6ad$0_wz1YQ7AfjR(Bn z!pI(6>m81x>$fo}rrzG&OatSx>$7&k8^ifkykq0X3wq_4wDZfTZnm1vh8g;ODGH6A z99cuj0~L@cNZGK8>+P&sJDLP{4!Sc#4?H!$@GLc493v9_URkGzvcgrU=0X#(gA76< z87o7^?p?%+OrAduGk`Q*)cGs0E(?J6(CsC9ppCzu0?+o$zieeswW$On^@G{3bRnN5 zdk9kraB5ebM!6x`2g!lKP=)iogY-MG2$Z-^jW(dBIf9&l367PMZ?SSUchIlgr$gjx z7UCoT+-+F1PT6UP(D4Y3YVKF1$Eb^l+?=i6z)t{Ecek+BW9q`;HA;&(AUlqKo7#ph zaUc86k3^56B)Ygt#x#p%6!r~oX|>Ed3qr(R!L{6!g`?UJ z5~Eweh>wBW!N;2Kpe)*$8-l}F5YsR?n929|URh*{{V9$}u3R~CQXABSo2I`_q{X_9 z#`PP|a4s)cv>?t<{~Efz1m{u)nA=W2zZk}W*0t9!7(;K)5~SOR@v{V{Srb6R3lj&q zHh6NCw4wgkUI|M+3ny4|@1GVQm9_<B(YaE{L3P@e$d^PrFxKqH&qY^9!`sZkQa z0kxE-u)dLcm9uL;cJCrdhRoa12D~OiUT%F8{pgAwhAw^;5NAi`d+XPMP4@mtn!R1A z#Vl2qpJR4{$@h{NJU83I)|Adi-8ABD$MD3|s--TA9lfe-Ok8$F7M3P|is9V3=g>6a zN7_8u+H!xRJ_hNo8d; zSP>(=(7^}UlbHpvT8oUM=k98goDD~ht0>VlP;58esFjO2zKoWvps=kXSn12bY;*}C zkUGYGH}qkjj}s=#Y1^Z$s1T?)cIpQ+Ts3WZ9Z=80^25EM1$ZH^?u0w2HgX0(C$-(n zVDESv;wIWK1B^=1MSb)V3>Hn%<*EHg$hE5woXR471-1={=ufp&;Tx00@I#3c*?|0- z5h>V^9ftOPMvd){{#gJpu@hU~e3qsuj=gXLsec{0<8OMj0UnnJqui|W+eHeI?Rm`Z z39k|1WVz8OCO29PwNC)Q9WIjtfx$*M=;L9;PjZnqRojd$USo^#NrtGw=~ zM5p$kemqDQ`GcF(QY*m=7T+P#RuxUdd3i(FF(Ut(`i|IvIuXJA?8&vYtH7Y@f*Za4 zEvV?ywR>H_q?6dXx*j~o9z~Xz6jnpRt5VyEu`jyzZ}PM@QRp7*C~9+?c?|%&z+av) z(_Mp&?)LyCP)c1oy^Tyfu@VXF7Bq&h<5iOh7%Ia z;Hbz*P7r*&%x&M%vrV7~o3l-PxAFTKq5J@0;D>^hgEs~sfqf8_Ul0)UmJttT&{R24 z`nVh61v=_%&9EQ2YCr^uZVV{w2+8a_JPMQctNk~h1^Rs+Z*^rWcaXW_bQ-^pv2lzc zSdgGFQz;xl5F{GJ`JtDx8|&#IO3I^n0gOm4D3#Yq_2@%M0TcjKV7-X);N+56$(wYn zu3?iL2!HV^3vw1|1rT_n;RBRH(xE&!5}U&?Fs{8prZhElI7Vz{r+QOV;1q-s9R%_5no;Dg0eUg>Q8N;`bmE$;FK`lJtO_M7SW2u`M zm?;BWk4&vc)_L>cy&j`-W?%rJXdAMa>`P1B6jFP!KnL}F2NfVT>;q#aE=MZ_*gkOh zm+QAFjN;MA^yO$X8JZddXVEPXOZtr&4SO7Zc1Hxmn%THO>)y9gK$+M~eh~GwM<*jY z4C0I~?HMgeAhu5vkhDRhfDNAEfP=h3N~MD~q3dAdUJ8k{FvzGCYcCt6dX7_l41vUt zY(SbOVrxfHd8Se;ZS2zpkqX;op%tjnBv61MVCaPW3`&ey+)t=IffLD9&4(yOzzcXz z0-JAJxGRq9R5|AT5a9R$2#n(LY6lykzhQ!2P0fPj$@(73=j~&HUdzoB)w6iYt-PPW zX;!iYaG*ruX^)Bsvp~$?A3REy_OL?R$czcvB3*>X>BpXwiru;-TqedIT=~I)Hw2=_ z;~W)$38>Kbc~DVf5}1)i%cruF|4KCf{|x*`dz7z8J^>4m?R50AUVsGQo}3X^eS0T0j`IRVP-y`tyhLbzZDd*;>k5y&mOc)d zGUFX}IqH}ICXg57=%21R#`Zw~po5s!&d3!4l40VFzL7^D8^p0AGQ+*#Oqwa+vR*-E z*;~{pE)~rKMLhh$EAQj&&PKMV7*j3Ky<&GpBw{&@fIi#p&ie zUSphM0oC(tIckUsrAVGLz)2QJ#I2QVe0=(Xcn}yu<@zj9ag%kZ3S|KZ!d?ZYpV2Zh zj=K-o5&6V1M)|MRMXr~}N3Z=pB5GW;#T zDF8MTxs@edyCoFAo&jTk)xEYkj8u2w9cAX8cYDnIIRC5~)k7KP_r`#MJ2~4EH zFb!0HbB3`oHE-uc{GhDaM4fJW1q*xbsxf>66cI4PSZ~^f2=Ow*k?wl}$Y#tl#$~G{ zINZ89*)S{{pAphRj)>z-oD)a!j1Qa0H-VVf-=a2=qk{IRl^$J1 zW0t}?>B4qznHsPA2Ow0R3ijekE;Ya|qig{Vo@?PE(8{C9{n>&PYIZ;Cu}-NJ&90S9`*e}gMu2{T5U$Rf?C2P0Bb4hh zMdCRLh!8 zowbL<-=7S?l0;Q&BhHgy@kn$}mI!LXoehWE`a1{VTG)-pHU^Al+XZK#==ZAvVlC_< zudl+YyjJpX9J?W5vT9AZNZX;%rp^uPgWU2^H801@P%rgQu`xz~C;t5t6 z94_zgyxAMA&*e+wISddYdd?fynxc7w8!IH)HtMr(sRijunedYUJddQJXlsy9rHH}Y z7J5|XS`lrQK)w>UHfG_d;2ag*LyzyT6(j|MmbuTn+ks5-;Ace}pnR@yx0_?7+KD0@ z`Bc2pOO(n$)0jI9-Sny*5Bf~}xfYA$Q#PiWjS{mBOCuo;>l~eKJ;K`2ghqv=0d5?_ zO_kCnmTI3vdIYFL}$}zZfK-Hl|@{Um}59$fVt7+Ii9A{sLdvtiXAeB$D(@tsEsb zL6iVu!ksz4Ce~6r@yQ+d)W3g10Uc7w0wasIDCg-kt+kvydMkNv9KF%JLAM{ZizDLn z@^?`VuScdVDyN-WjRgVmf1rU<@mvutl} zmAv@=8z%@R8N=OeccBw5wN7iqD-YI5`54BK%e=&MZK3UGkh4Wse?fGi+w9KE2s9s zc4uE6P3|8#v0z90?yJ28@Y5~%!m8Sz;I zKg-J*V%&S3&J+2b$SJMhOsz-6amB8)N8a;%Ws^X<_CI*m+`=hhxIRJ3E8yt5d{0>$ z*#wNxE0Yt$uz7pUe6hC@@swUAQS!C}303TC_CNp(1&8k@F*TDVzs%3X~hBT`2KdpxqGMYIK6(dV2lC z(pEay!TPLhk;!v^h*$Qx!8gkQ64N$qS4F-YboQ7P0d68;wJNbW@IKdf>MugyhD>Y(>OkKkw&Y>bJF>J?)kyy)xS_L_k z-Ulg*p|fxeP1I%xTcN%-^)7MwW|T9{V1m=fjDAzE#=io47I>gGFi*~yXeJKZs^Ju^ zf$ZP%AUlFLO#wIwOVj10MxZ>FXnwrOWC2SK%>;|jO5SRAo~6mmhN3Of+NnqS0L6a| zU^J5~y(P-9omGp5O|!@~-uv4s%3&%=BS3pN9pOWX6vd z#&OM7P+JX01E-r4098K%e5>>IcAIi|v%-+F zTP$^$!ZK}ZtKq-!S}~mn#Sy4;5I|cJ?QHc&;(EEr`2InbI^;gv=Mh&E;HuA8xdWQ^ z!kl6vBccDwi4Ef1CiUTOVzej?)IvTSN1+xm7P7DMmg*kS>aOb_=}m4W4`D}or6_5c zSL*&V6dI|62bHyKNSGl|ER5q`)MLsfuvdD^F)2strx}hv1CFTFPmp*v;}E44)U#~@ zIdpL7nZLm@@_LfR4M_rdDvk@uWrrB)$~z3H!=K=%lKcrbr}Gg-70R! zu?hXe6M)WFNrmP7scq}CLsyD$&aWYt)yMFX&o~^w^(Jbxp~Pgq>=C^<;$C2nx)R4> zjkoXwo%Kb*ppT)QLu0%b491DM~P#q!(9e2mB1Yk>{K?! z?AFr@zNRKV;a|h}BJ-usocA+cVVuj}bHVQ9mGjsAWnxOt@fU?w%^i4R7jxwD?vaep z^eUf*ce1i_KJ`s$s1z0F3*YfRrtk09oxQBwHk-3=VSyL|x_qVs@kz)~=;)zqd*-ba z&e1Y%#eBM$oM|NeVB%fXv1)-=CqI>5zj?*5#--^%+`DJGMomAT7M+o^dgf=;C#+uB z`s|uijS^4Js&W_Y*NZIO44|3nXjjuCdT7)_dUqVIq{!->`$5(%hbf`>vWs@px>5bo`5&C^ z3^5KBySjveUj)a`e6mn0JVN)kxKZ@^?Ea~l+XqY^L}>AMw`EqEnSORm{pIa_Vp#q` zLGi|)*Oqx!bMddfOucGo-TLF`aRQ3F>~a6*jm8hS#KX~whF={{T+lU3tX8f~O8XVV z7Q1VC4C>Hif`8@ouIY}3t&vslDF^7lVt5BFPfyzQiPJgbXD)ZWzWJs8E_bQ9WO?#S z@!Rt*0e{M*S7W!2-n(&WT;up$f$@=7;a-=7AqOvf^ZvIi&A=qDIv$OH6*f=I}z-yGte)Zw#b3Eb6JgKX?8vYu!R^ zB;#WB?lLuH_``5p(|UB6{f*C;PINxA&U$0h-4dH-npnmBT6i!`q_a4|j2l;Wu{ZNE z^J=+mm$py%T+_$=J93vw+qt6N2DY9WCQ3r>32UZFjX&_&W=ZzN>s;&SX6;#yf z#@eYi&8{DxFn?BMop_uhJTS?Py_ zK`_PNs!!lasTAdGa96E#(e8|7&sP4>7buJD!~8FBJy&Ohhw*k| z%sl^+*UJ3DC9N}}{TT~S=04x@Q{nF@{CfRc%t@0gsaVDExm;^^!rF<$g8obFOsnEY zDuOk+ca18J%~f9VQv0xeFb49c8FR1WuFC6ziTIYjWX1e0lctCJ>#GibKUp)|>|F?c zeN*ym;vRnAPQ1OT5xVuJgR-oYT#&-Y`a0Ru&wi$)r1D($9z+J-IN)S=^7Zg3h~o*3L&_SL%FxbP$(Y(Lk@;Y7@w zspRRuuFeMBMcOf;)Ar~3WL>!D70Q$t#_39~`PIkj&&a=P(Ui@8<@a`6%xrP^<;&T9 zuX&Y{w}(du6(lGq|mmMVI`99n#H|6*2Qqs0N(yCbaN_fn6s`#oB3=uqJTG%ld=9(0j zfm3N!qVD1Mq})hRw3Br@bwPV5^3Tkf%U6^Rg^LRd962xKmAODZ`=hM4 z=>fh+59j#wyQgVBc;#^R^0m7;7Tr*RD|lbu`PN=N%Zo}X;$0;J3sKs#vjGS0PWFZR z=va0iIZt`>FzQ`Xa@`rZi#bPbSo_Vq!mr!p|Ae2H4V*JIq=1fiy^5)tyBL{vu==lw zi2OG@yBJl$YPG=q6KCa4Dtt%rchtlvyHRfPJ3a4PKc8=Q{H~^45WkTZE=Jkdz4=w& zwF5qqf|e~M!Jhdw>l&rHK8%kOXMGPc^Edu%n#g@N8hZHR?VQsQnA7c%4@NJN)9XJJ z323^<+&Z;`Y0;(13Z1;N^HGYYr57^ywMD%yl9k<+F8=eb$CH?nOX~OXgj~OCnmuUG zkCES9ed}&=<$2Ua+h-{&vq#3or&?m?dR0%IJAd$2;?I5`VVSvBQ=_OLxGi}eXIuW< zcUUq;Tl>d+#*!R1`9ZFY#&=uYta>@K_+K3f7d%4;KYo@rg8$0GZT6H zT;;=bi)qQ0FOKsoRV^G>bcht(?)dTEeIjpOBZf4ow`=_S2Cite(DGc`A8<$U62iS!u)&*Sbj#u*h z&6r9rW_(57xPDHt&ZFzPx=MuT#Pb6pAH(X(mR=1PU@IGy3i{vvy!+~17S1hPKi*#Q z+RNLdx6M96p4~_I=dZcXO$p8ffG+F!JV{R9=VIZId>ky&&vD_S!p)E z9;EW|@K1X9F4w!BwjFN{d1)}LN@t6eK9bAVgH(cE<8TolH!2l%r>u24QrqJ4@}?JQ zc~jKIr+LVkMO7$dYf~Kxp=}<5;x{*yp!n@gF(`g(QxB?lQpB_Y2anKwjEl&w?@Uh8 z*z|wVX_ch$Jd9a|>kVUm!u5tTzv5KFbiY~U-mw<#u#zY)a$H>8yXr+c1BGpFhCr(` ztm`@lGJlV>N#xyIVW_aEp%D>@3-}p4ac;3XudF(;Q`+S8NI2Jv+pvvN9Es#ofX=>9 zzrSp4HZ4-Wv44ZONnCmG=5Zb`V}ZD^Xr2ej$Av$!!jZ0}pEqzC9+)#2x{dApnKy3c zk-0|9To3YqR%=);ZU%v%!s}IdTxEprGhAq-ZY|C$ETa6Wm*c`>S)Qi?ZvAs+Lrb)e z;4jTD!FG|S#u%e&duP}mD?mf$LsWhFgXrJHHiwRB0AgJBerZ)_g zgjnNAlbEcZ3oLYFGa3r{Yb{)0ZMbQzz-Mi^ZC%WtZlmw?a{y|< z`7xkkklQsdWWX67I3#hC#K()afTA`x6`&0Uxvc|OgP}s{beMi_^T3!v^r(%tGYhY;!gWQ| zV{m~UahI|utR`RByee#~^Z*e9y{Jx#u^OkHkasCPc4AY{j0~bw>ypF?IY)GHp!CoWOmKk__7ZhGx#f+U|GW1kgGkH`ws zFB^ExS0Egfq|E3JWC`itsdEyXtVuaeSgxlp{?7OUr@*X0I>M0L|Lpqt`|w&@i5)f@ zQ0+zVMUJ+Pn;mYuWd(;aZ=J2LB$N;Qp?p+%qgj{47SD1awa#KDujNE3dS(6QSv1|W z&pH~CF4ifWsGhz!X1IwsxJGfmxerD%CwT`L;+@+67QP4!-IfNGe}mBYLZ#Aw-U538rkvJ}$F^m6dVBi`t!ULHJ$Ejn-$3dbQobH+5l*A@tSYxs zbLBp6ob-ozv+5gH7ofG;Z~afN4uv+m%h)0S=`ILFOhuSsOaF zU;hP|F=4hgP<=cW&NDBSffQXB3j?gj4{@)}XrumoVvOWAnu-A(ayy;9uf&JsIGS7m zS+QS*Zmcs>jh?F%(vMtdrDn@#R{--jIRW#BII)Kr!g0izXO;7?&~0%aYv66gt_lOk zs)zb_y)-9w5Q6Io;8g&{0SC0qt2ExEp$P zxWTiyCJfXtIrfaMbv7*G-c?|AVLkITGJQ!X^cyDwkD3O~fl&@NiHQ2!X#nT+ zr!Gvrm?ffSXk|k9r^fz{OScaL!_Ga<5l9k$j3~-vqucf0Dd@_Isr(E{mfYP?e<=Fu z^3wNX9c^ZnPK~o4?*RxE%~(E~;C%X?2{$V49!AsSY-sEcU)4i&7gytBB-&I6ZsPhYw4j-yfrO^J6j z;lAtZ>4;kFku5Mu{n~NLIYciYJJ)y@R4qdC$Atv1W}*DLqQ{Dg zN)L|?h2P_9b_H=(BM$}H%ksQKoFvI0X2lC9);WT!pSPkGDeQX(KU3?Ol%!wLpD|)l zZ0@4P^9=?Yba`Fzm`W(m-JCMHlG3PgV82e!=)vNz%2OEX<*MSqVs@m%6_K9{@1MR} zzV{OKQ?1%3J3t7lqSWNzSbw>z;^#DsObL?kRu5Y(?x+i9x&Ezvn3hm6X3Vj|wzR{+g*N%8z6~K8NXu z%vJYPTYQksoZ}WXhB!gb);}}Vm=2x|^Xxi(EjP`d_p`K1X|myblT%KmSMToLt&;Kl zid2Fl?wi(EPf73*7IiLzDc_r(@D=IqmLSf+Nlu-vS+`jEO1v5{K2(Gp{Q0Hx{8rlB zq@@lqra{-Q6B6Q9f3)spxj|zC-FKzEVkmAhUIoC6m9a-ylw*_Wut{Umg#2 z_rCuWr4W^nY?UPYzB8WkNM)-OS%+-NGRe-EDP@UJ$-Y$*g&F%gizQo@QI@gJ*au_G zjKK^BzjvSC_b={w&FlR-=RWs+-Pe7c^FH&&0wycD9^Ld9cxGDbP;iFn*h0nx`f`n( ze^`i2*lKDAVAnR=Aq=rgMYWmh*6+Yby(5R%(xLtwHw_I_M3-maq5_ofi&Gu~(xg6} z;<~@ITlKpEd778vGNx6>WNR9Z{yFxoXCJ?@DTb8X_{ke-u(4_89ui%?V;a8k`prU3 z>Cj?f?@(3v!^P=kdDg|5HE?%r)M(h9(CIFF<_Hj`{5tHed zu6Qi{In4uH%(kzg{a%>ZU}m-qc)CTN7g@y5I~V6N%~LvHt^pwI%f7a|GOP44NpD48 zvdzv`@r|1woRf9nN5TE*0t;9a@2R5Fp^l*ryGCzD%YtH<)#4qcIQWHD*2=VEt5E1` zVX%S{J$MWiqf$Y;hV}TlotDg_)gO?kyrshLauh!w)QR+8I=)n?!kuL)q`(B(Kc_at z{8b;R+x$rI7lMDU!4>RPIrl3oiA!%#G z3*$Nny;vIV^PoiFR2X&8i;IWna4};^5!iA8O40jj zjXRB}m4QF2<>{!Z$lzD-w>%ZY59fCd{-BDwgv2njwVI%#W{W0db63_0-MSS1}Dnw#5rYUBo4e-9qsaJDG=*EDfFIDE_1%sDBi%O>F} zDIY33Hf-LP0Rh6S7ay;ojjOMGzr!mMx%BC+HVESl-85a&pZyp6v_lGs>C_$@k7W1m zZ;WjqTBMN2TWte1t$LK3t#pM8#s4=IBX7pAevCz&_L*HhsiOVC*xg5RsSCl6A2~WY z=l$a)24-Fi-|~Lx4TQ*c3&NRrS=8)F>|)C_J(L8J#Q@Se^HFZ=h|9dV(6(2 z-K1@LUSCXG$4Vx=U1|+=pm&!RL^-2x<+1-5oX=jMe6ZEtLH#k1#xA{#{WG%iH?T(K zwX9ZD*Q%y?8}la*eb35mSi$8~%F)wV6Q3CaJbQZm>X37pSMk5^>IV^a0#@CP8GU_c zP~dmE;;8T6BYCnSdxr3r!|cJQ{|( zpB$liTb$w7AKG?I2?P+Xu89vij3U=6d z`sRxjZ%Qz561$F6pn)@ZFs9X5cQX!GI$1JQ?V9bSCl$7cir^G61WsegJDWN8Ae*_f z?nm~N^1P|cE)Bl}8)v9|xbNtA(15yd(k`di|7okkRpv`v} znFgx*8rI8TC9YD9Padp@C2g!;hxpK!*(7&Zs!PrJ{7L@Ryb2H1$eW6+Ec2>*OJIR9z?Q&iP*+!z)?Z{SH21d20DT`wY?MUL5ZJ{vAF&@;kv6m!x_LO5wp* z!+y#4TW|OzwtY(t+?n6F;{(qrR`PCj(8mY*%=#7C%aMgLfoZJCUkK1un*@T22QU0L zs4`z1ha{ws?#YN|3y-GE$XX$3T98ehh>SG1V+M;WS7+WxvNsZhgqP$ON75>`3|wiY z4+jjr3J)5JDm>J_c;Xk+U?sXhpS76g{EuV$5YKN%)yCD`rw;C$kE=Wzm$uRfsZ4%% zt(2J+ant7zuT{iw+MVkE*{ocyz~xO8Nhr#Q;y$Lx~2larK$v_f}A~Y9O;`f z;~f<&KC1P3{qi%+%Y4b!q1`+9tWB8Sj;8-5DcgSkP_1)^LFFs*?h6_Hr60JT`z3v+ zLpW%iOr31o&>LNX?SXiXUlc=O5p?Dky8$QuitY6meSF<(XImq?_Ues-NtX-5$$cjX zo2+`J191}|tx>f;oYX*?e@j;Dl~+5#_Q#M?a7Lkf24vh;yM8{0O?V}aHm4D9$FOQi zq<5QTtEIjhhna2KJt4vQ*?Thsy=0v}1kbtyYiZ#in;h(wYRnb?P%iRZ=4T_&7A5L_ z54HCsK(>MxsNX)WMb}b-8Lb1(ojYyeyYbVmF5l70kD2ZeYD2sey5oLTgv1{<&oDbM zBy>Y!Di;mvoj0dvY4prJ0U_aNmA)4+Fy(k73A2UrjA;wGBR);P7 z9ZYT3_;5=<2Y$>@tn%1+l(esH8G8Ld%qi98{h?RS`!AV}TTKY(SC8V~+s2Vteo6J8 z^(1(L7pd5R-*PAi4&}<8_{=@Zhmmjw$49f8s;es(XJVCw*ct2^75sz32aFoUKn$`4xq>> zz4GGBi35-6t9wp)q=ks-@#sNx-`ir_bD5sny##5J`1)rmkN<)9;c_~vZ>(ic(;(|YA>3f zr%uLD@(kAffjL47K3?apUG5hrN=k<-X}2{;9nGIqHduM95weN#d%$`E%+>Wek*~Md zXSe~CncH5yXY$dCB4z~{kE z%dP{tbTFaMrFuBQ(A=(mrUCCo#(n-A6xrgKvpM!d0bpdb7()KxqEL1(E_Q7xvpOgYuen@Mo7NuKNh3@G&k@C>d_|ZpP zhufSGU9h%HK>=b$RXMttEc*(YHvs~3T2b~z&&#v)YNMWUQuSz-$LBr3p)x@`C-MpP zhqfx7h3iW0HqnG34ub5Aq49J=_Y|K~9Ty7wLR&d_!$)vA^$e<+Mtwlb2N+b|2`824 z`m+b8jzRpv_4=E?PY^EBz8%N?TIp7}(CTmomC~x-c%<9l9Kcz!tuMNhB12@r=_NC# za6u`{rroPy`$wK_=Dv5$=qehGx4!>*A1qUqBB&)jJ+jhSAezDPy?&o~ImSYUG;t6N zLwNb81b_w7Qv=Jk*%E)eUA-k9T_`Kgc5l`b$5fXxZfNl<3_fPQal|=E4eIL2%g}fB z=bDokkd06Su^Tzk#n4^Ru%W-agfM8&RB%7Xzc|EmEM22nFHds7NPOPGU`e4OH&@hp zikgHO4VDWHEA!$pug>wvNLBW_%s3J(|Eeg!zzT?Lzoh=|3@2K^Q-ImbvjETKH% zq^vajYZ1An(b@(>JT9TfA&)oygDF~fce_!ey~vgRGK@ zl?6iIR#Uabr@vqg5zbr!2kM&#?E?5Rbsx_YJ3@`(*O1bY6v*(7Y{}{DGJ#oG zI>wsN2-iKYg=O58!47ai{&43}bxNWtAEAO)wx z^+BJv^}#Y|I=6W$`ALa*LhsmcPb@;6GYrsF5&zx{7#GSq`EI9mUJsCG5!yPR#J5*Yh}{!2s@z!T#BNcjC1j8A+$g zhK8LWGk5G))uqF;F5107&_oycbTp;(v*9P=asc(WfRegq3o15zC*xVKODzXe@-i;L z-a;yZh>V51TcyBp%sY{j7ff4*qHvPNBgkLyNLx=4s_$wLe^bI1S^Muuy`X?BJIWUd zG7o&W5PkT~<2eQ3N))rPY|`T4M~gA1Jb$qUdce6TPX;?K2GX{+ntKsX9^m_@YrR0j zM?f&s6F^g{dCL%v$2>J~zJ0wbL@QH2qNRGT63gjj?+&6I!L4_tgQ=I*?fAo*GE7Zi z{V)4u3}=$A^GeHLo&WPpI6;u01t~WW!2S1&{@7Nj%<~D`Aa!T-?jO1fH#g> zgx~+2ja$H<{a=_KHo){VVbwcppM_B01JUbi&vq%xK%lOIU9z3<5NusH+SVmImt21j z>X@5EQyP6vAUEw(XDr^9^BWA938HAQK3sy{dVd)U=*Y$MmpBZSA20Ub=wg$*;o$pK z%EJR({t^=-WGfP-U#v1x45g}~b1Z~N-`Ks!Niwb|mE8PTw!WuzcvKVE-thT%#7^HU zX{=~6f$8-lZ+Gjv?PZ|IzM}H)7?r$xf2^8JVCvO9I=6%Mkxjlnuthc67eg56CT%M` zpey$lL_Y0eeI1syN`DEuH>TCR-Y8=zrP+s{=E*CL#^;G2frvpJzL(6S966~M!#<#^ zOL}t_4zs404)TWFCiJ6?BSj>Klj63I4+q^)V1IN?Id;l}zFqqHV< zO0mofw4z2$^+SZzA=u!7CUj1~`dVezN*O&a*ZO`$~w9aqDrJ_SW1CYIo zD4@j~2Y(m|bmc2&6M=miY`93TKxF;%@%1H_q{Qj{Prn2xU`fQ7c)rtds^|vwNeLT& zp!rCvnbH(vfMq_~)7-%-{cRn!C7Z&Z%g}tWAyGWeUWl%MYZ!5ne>SYlgn{VkPZhZA zpu`l+1SsThVVIb%Xl`i2%t|id=Zv?}=07?(W9pl~rWasd!7fEBNw%i?q=p?X;6uvF zkDJo2Y0!SZkuPl-TH3C-u7wFAmO{3;~*`%JLLRZgp_-53#&*1$!XQ6zx7k!`7K z7cl-x%e8_)-*u9PIY#vaGYx`9xbw*=0Ui|({1a!sqlqtMD$@)HR)H|3R<8d;I^*uY za)c_MB7+q&_Uu1F00ZB#u82^$MEuDee_?IpfgPrBARMjC(&5a z1G6peeWNf``vY5QeN8^1%#Yi=dNS|S3vEF)(d*QsKF-U>fNr5ybKnJ2gx>rMZ^$v- z5N&$UX030@*fZ+iv%N_hc+HdzYwE;aQp;v)C(V36nOgPTF{v-P+fkx5bxNf`d4nwG zt|0>m$j^2R8cEsUjO`a*c;P;zVr0wE)aS=AC&$*nu4&1L!)UOja^E~RGoXVo7UT@7;C6881cIR~RPuuE)1AD0!L7-U|!^(q;XBBx^EANDPL z+jVXIRN5(VqF&IxcH?%Ze7C}p{3V`p$>g}dk;4wAJUVNaqrC0gs(%e12sBjk1ER;S zFniXTw!SZ|SG^vs?SJlAA6+bF&{#5m(0Bs}phTl-l^)pd+RNeBs}t9;v;dj0_& z3sV69Nh*qmMi);WD_2kz%O)I-T7C%rey`M&3s>|))&s~D!VG`+K>A6j0p-_X^B zX{p(6VyOKxO2fV^a@z_9YNAgs>24lZz=yt*-HxYQ1$wt39}MFU#=b?{Qc~J|cISN{ zOrVX+j&}+v%u0?N_~akC)}Jzc>T-zg#sJY_+Y7AC*_`o!HU$G$*}!gkCZ5ROwIy*& zhn`U@lnM;zv{FbiODli(n^Bx|llJ0Q;Nb1&*)R5yQA!)fVrjnnj}O2jucl!V{~qu_ z3(r(c+H~I<-)I@HH8?@pJkAYl+4pkP2D($OB+Sv-tU+DQhq48*#M%sc z?CbkMnHeaTI6d{QoKdS?gTgP9}O!0a`nnNld9mK?zd9yNO-!}F~}jlHK@MLC_s zvuZz?-N-{;f+@E(a}jN5!4nx%4_gEAP8r5KabJ?>AxMFZ8b$1Ouy)vfNppKIpHfht z5-zCSK>~GbnV9w-?L?FcQ*IaKC0K7F+4eD1=6|#&Pu-5;8`_W_QehuN7xvoNO-L?O znn6C>p3^7;G1Iu;mnUHbGmI^8KJ}R52XQnhC_idSw%yr!>}vf7b*S7GLgsLqtluJw z{q0(IC#KC@8ihA*tH}Yij?3Z4?{kYoe0{jjnYsFw;nVf=SE2eDJ3Cnb1ol?F?Cv}I zVpPBHsFNav|0|MOnOF@xd}D%69g42=3dwmd~4>M$P2% za*3_&*#Fj^?$;}=Qe8stK_CY}f*oGbpFS~W*hY>EsoN#(x<%n^^iz`hab?599?GnP zL3TAigAte(@+?IZ)%boo8aBc%4Bng~q`c$u+X?O`wKV@^mX7{b{*RXYpQi*Z{j=qM z#1(p0HPEab_RM;{M`!2(m}U(vGn!y{DUyy^kzIGT>|F(}hOcf+E~3}T6cXA$Zyp`$q*SEuuZk{{gfG#M@S#URLeubSa)u{c;0pI*O+{9JSNx;YHeUYum zshAl_@`>rdlBK6nidc+-?;Sw4DHop7o6}zPi!wY?AU%7>mc#{s4)*cHnYRT{4bI;w z+>=7Wq14Q|dIQSC#$3MyU}J0Ig2118xmVuQyU(;185Jk;A9dz)=Z?^W|8P488^UTfqi%~>!bsn z9dR~Z%nFutue)22$hYBg*1bjouXi7o^jj_25#DUT%8zg`Js4I?#tcL)VvI`irLJW_ z7P}gx2GDVx+oZbsMi?dgKFQmP;)FoM;#fzt^SeakqnVm0 zWZwb9rSfvz}p*b@4nm3dM67IZLrGxE>4z5JK)5 zXotXW*u0xwf=drfkEeDoqnLu-K`u=9@uV8JOJjQeQ?KFWX=awY*&n_AqF(ooEArt$c}^L83-rn9<69H@!A|%S zfr-yQBrDVkfPk8QoMjwwDm zGr6;G&mC?lDcRm&2f>*EzQQ|t zkySNaP%XN%i?H_ZhA-l-2sW1mR!EIM-_dw%8~eBYa}E`E@Nw<2cr>Q2nCgQoh{2q! z8%0LI^9kS!cWjFtNR3;>oSE_6ElQjAZ3cnpn8Hkp4lGM4c)E$Whn5-^tnLMgWWige z#__dhur%jesXji-phds$`aF?U^y8rA>9q1NweXiD*xNFKF#GzfTTAMc76u8(yln@D zGfoTi1-z&)b?b!}_0?XB$jMyN0I$t-^!vhKVW zYgYmnv2$woO|!-hO|e6-IB#t=#g5B)k@Re@J8L~`+e`1q7F18qk|UN+YB*|T7>6JL z!N-R5)ID@FnEEFr!mIXKJ9H%72#3BDM!H+f{19k`5!MLwqVBjuuAi%xZ8lwL(-9rI?^@R- zALftpqtG|`4wfE=QIg8NNgWTK!ajm~HGtiUzdG!sz|Xd&u1KDo8$k4`$_R0~dTQ0W zN~9FkH9QV6E<2~*>sMQ3w@zZ`**N^++xfONwBZtLL(>`fY{@_;Z1}4wu~&ceIdY! z9SxjvC8Yv^f`7is5mY;>K} zAM!nQZl1);YauudnzahUE&gvsy)#$rF4sQPazX=V5koOo3~al%9;?`vk1g8CS1b_g zF#Z=a>jfKP@uP$4FXRqC`FkigM{rs(p|Z>xBQ(eOsZaF}Xt7>R-!65NfW{JkPVH&p zxF3#Kdr|#@(T0zDlq`@TWK%qrIfT`MDfzTo?~P#1=5hxL>_tcYTdft!O2k9@;BGwm zJ-3~3cC!B8giC7Mx8jn&m;3Xa!vkO`=5wLqH5v`v2#IoXaLI9WIC%SYciv!ibgN4A zCN0R%j525dH>{GW$4l<9gp@)QTK^IY$^k! zXGF{xFMWSp(*h0`rJ@(#-*fP=-kQvMe#R@*dC|XT*995fxARwILM4ovzfwh=QmYqM zyP?(0N0rbqdlh;_jV!3u`<#y|M_cEx(!^g9g^|=|R-#UdT4R4OA(pfOC12p|q?;;m z`vlFO1H$F*%z^_yXOw%TW4zOg-!6ToHJURt^yq7+DNRoN4Bw?kM_u1@^0ZFR4$hpO zsc3)Y@GNfT(ygPsas5no^J+Pw{5v6QKG}>lw(CbV4>jCE;r48TgM(||s_1i0#+C|G z^Jff4r|0x7GG$|QzeiJV(5Ekfg6QlXOA(B8%xu=!;)u{-?b|S`ZrZeT-?6qob%VjB zOoyDbJ5keZzGaGm@yOwaFD^UUQY_2qeX96Fg?hFI2#@XiG4?UMso+Zwe<)a$0=dkO zx&af*+x@)5v3vWr@3WL`#GIWzDQ=11Ce7lyPiVsCSc{unMDui{*3_OV@+1FLj%VXy z@j8!OO;cpfXspVeNX?ylkX)%qmTD|SS$JjdOe?0NsPuf?Y*)sgl%!Le`!9HjM3dNY zKKgzSLo9Q4-tZWzbe1{y=E^S86F<`B*p@EVRR669fq+LCX(cZO@O`h~+3tf)zSK`4 z9pqXDtck8=-5Tu8}88hi`+A>ueK9c&T0llxk2gp{*sX{>$r85MAsz@_`f{(*^#GMf4#&$^W z*kay)E~F>zO3bN*Dx2M&3q5mlOLq04qEbftu`d|-Gg12zOIrnl3vmcjv&kp+TBCdw zDVs=S#Q67~l;k;advGG8Vpo1OEsFY;muNC~!KwH4T%ogw_WHZo$-9nV@148Q{K72|rU(-!JHa`}bNE6d?jZYrK+Cod)(w_X(pen^B2?H8^jtbyuP(fpN$y8Aw3!uPXmC#y9LvmA!#Ha)SgI zep}4=Wh{)Jy+iCz8Mx4ux%1QXFbUDSW%rHXFKi`D5)kwvW8v>e-&~VvuT@%{(snA= zhDM+InF#pi*sfzyG}WKpUt$pC_Z26q29=3VBwclWDA9DDt8DnEc3EY0!}=e!@{K_g zeR((F2t%0#lCmbb=C#};KgKydNm=b0nLP7DdlCne@YS2LFlmf%gKYVvCMsLjb6QrH zdbzwFH}CBQK}@5-T7MTX%yhl+j}CgHBH#;#m_FOSu*9~ucOIhzL!I>6xfaAEd4lrF z=E)QhjDE~cTFYkra)fb#p$Nv`b>M9Jfsm8+3S)qmh-srIe_;ZX+3l6iVa00l2?$fK zWj_jE{(@D=l{>I=)SG5kv&L|PTk)XY;s1?Nl!+XNX~Ek}^o|wC%OOAx zOKSMJ;sva%KU_*_Cim2|%%j%&G?K#$HiQkjOcNVW@?>V}|)f9qf#;8HL z;>j9{II^BvQ}QS?P92J}e(DfF8vqT}{wqMNI8J?|_i#*HV_PBE?xTWIUdI-S^4i15 z7_Z%Wb&TL|YlI+d+oFNtTpJ5&=t_9LZg|of@R$|gG4kpuqdARGU@=Rz+5eDymm{oV zQzHHAm{3LnNqZOM6-#vq$XnYP+>(ic10EaU%f|)v=g)FH{{V~>=gDfYb&+{#YMsB5 zt+_aa`iC?w6HoP7OlzvCyaiIq7XDPerhusg(lbVv&U2f32=qHq$EKS1v+B2Abfz8o zwj1?%@W+AG{=!uPxEBs&e?+0}`A%t37UNu}3~+9FgEjdOC7&PAW3q~?Xk{&=@e-Zq z9y?aWusqK$dAfe(^XQeIGc>%XwHHV)Ka*?MDIx%18Upu+J~P1o~A=&adh$IP^!U18oAT)$akRXk!L z;;#Ou)9GiMoO`ChU*zNYd8(@_lzn7_XU}{euK%<_6-b{i?HvkEehXS(^kS=7!LJS-bH}1Ad#|*;l_#A1pXCnXb2>aj?GgcX z>a1npo~Sy_d$G>Xiz%=9+TU>!5=k^e2c&I;p4paDEJBw_-#wqo zzMnWf6j7pL^lRDeZ9C%%vKx1Jq8h2P#SO}r5wQpmwaw&+S@|(j*bh|%1&LqmtKcP` zu9cdYk^Jb@q^AyDOU{U=h62eAOSf^#_{fsWz)!eyC05j^AUn zdYg|!k1Y0CeQz+=fpi%a&6S~+dmJyQuU~@;=$yhooHxjdybQi=etx)|9X8R)OY9;CzOgA^uUm zS1vcGGxjUa5GNxDeS4}k3qeQEFI@ROv|sp|0mU;r97r!*ryPK zpa25xUM$rQ{`T43bSneyN3h)Gx<&x4!;9&n>@ZtDU13V z^{SF{-ZscW!uPD~{sE+wvMrULQbQ-}w|;B4xc{+KyCEelz%utLPp*f)OW)6CE{e!1 z)BSL|#ajoheFt<`=J2kB*41*_JcoCog%`JnR3svF%k52j^u!J!h1;wr)7JvAXd9OKu}EUYKEjyKkc{VGsnE!;gC0R^M_;+ z&@M-Esq!^`C$Yogep>lurR37UzZS%~pXQ_tSXRIqh(Y>_pBo{C-BglGt53W_SS>)Z z?!ZN)xNRZ_7;mNEUJpbvc#Ff2zicTdBh>@)$Q>?|&zw3ScUMm18y?IzuEcnsP!Ehv zajVI8@$;cbD)SicMS$A7RKf71p<4K-#BEKVScootcFuFoSh(xZOC4GtZ{GhS0KppU zpc8j~0Y}W7+0KfdqZ!!cD)MVSp9aKSy}7awsRPFT72Kw)zMGzgIaT8;8+9dF%If%} zG_ic{OMk9xR5ed~fcrXcK~-XCcKcQhDg1JKSJYAA1b)ZwiJBkA%Y~yRZvN?_=6-Av z`|&gQT+~GH+q@QR~_3Pv@$G8dUh>)I95V8uQQ`u^(asaTG_&ekOj>;hGy$ zCZRXGDzfeZ-fhm_IFpN`m^2i=tpC_+tuf{T$1ajDvl}sBTrV73NeX=GxD1vb3(^V2 ztPB`u2xRChkK}r_)jt7vOM^+%x58Od@5&bMgC?T!LZg70+mAjpP*~b8*xn(IZit9! zVcs2=x9&t%ccO>AuDzP?jG7xCsW*ozv>Vf4IQPunhi3 z?IWUn7Km~WnS%PFFbIG~miz@)cL`N(`LYB-b?7f8m;i@n{S%L~TMpWutYwUdb+j?w zXarK8J8LZJHVg(LjA2IH5&=PrQb1-*hSmNh#+-SPHFIJGl4pY-FS z)qZF3A7~OQjC%8XuNWOxLL7UPsrj=DCD^omLaTKEZY-1O3uG|MXd@ z5Qg_9r;8GVoB;pWl%}u;JUT(+k?N0>_k>AQ_T1i^&Cle8HP`~%0~|4#Vpf-dQ3P^C zSa@%VMF6k28>ttjuqweY1&reB#_O5o>QMfZ#(NGnuzX6mB@So`ctON3b>P+Kgw6v? zGPAe&XB^^H>U{c>k4;aJD@F{sk+7u0Ha@^-?=5JlDDyC9aL)`L^!%nI!x28T@tHks zbAGo_TphZZ+IRTgQZRPD{|$gNJ(0C9fb`DEQ-{`gAmS_)qn7P0Gv|RyBM6Z^{8fPF z8gW@x>zC0RHaPugsBQnYvhyk*)f~O(q9#v|YIcIVfSO1;c5GlP2VsTnyv8=)ns;vN zllcG7-SfR0Fr{-NlLNrrK$tGv>s*GoHlH~QX8SRadTv=?hBHOFn#}efQ~O0 zMjYFVjAb%!yYg|@ozgD*y|VA&4>59G;ys^v3U9~O5_>RAzSJfr;;RQ-)VtHWCs5|h zG-vTC{PI4qa7RY?sl4Ok%k`{x-h4Rhkh{&F8%zH2oB6&)S2Vl5d`7*RD=eS*kaqoK z!HS+-dsi(#dCmeaAp$}a4N}v^R27&cgZ0@0wQtF%DiM^1M#FHkvPT;fS>?oa?O81aFtRt>k3}nT( z$V-Aj_~6)ozy5J+^Of`!^?wwAyLyl;nsel{NtFJlgV1wJWq%(D9smi^4=rOH#O!EL@Ge;+xo>q-j^ z@-}eFe8_R!vpslJXyf2M(t#(?yJF?pfHFy$imixn(w@~XzE(`n2%?uo<__=x3j*9{ z_*ODtLgOzebcW?}4vd$K9Ji%qjrSYkIt8J3+q{~TdTFYB)v*4c^3+*3u~=nkuD zep@W-{_|ynq8>yix$SfYAB26?b=0S-l+?>9ceF5oVbZ1`sRA5=$*XPbFm-&=C3=Dp z0u1Hva%?CG`*a!IX63@Oi<4F}A{ta?jrHI3_fg)L#GR^j6sh=zB+N`}ejM+QE~ok& zn~WvP4HVLu=XW9-NsW3y^&^k+!DhopyJ-Q$rW@8ZukL4P3H7Y4Mya)B*4(#EApfu^ zvRGmn=K77ntz=fLJF8RZI6M^SXTJ#%xkWHdDnFV!e*?wD=x4D7D2*Oza#J<1^5CEA1=jQVd$fzq-c!CNY;gVL`B~J;x9?$V+sXlY&*p zLv(S~4`LyAUd9sxcfFd{yJ?0OL37MTp`nqyS%?3iKOqW=MM{j4&5ZDSedcme0CmPc z%rSw!UNBs#o{Ci41)Y&>5M+^t=0u|A6RiGRaD+GZGT4gk#Y4>%*!?L6TcN#6|JfVK zt7cBl|1Kj}lR~4|LLV{zbI$(Hz1|(vA}I5>jBE@xHry&RMr~JTTBv5G37mO5CS0do z`@dcHCRTr)$?I@%<}o#>JojsC>XYmEpGRJOsDdeP9)OVL%exoH-Uc|;CZVzFkx2q4 z_rhAzp#nYE9!7q^?cFM105Tl;N7S`weKN(Hw!fH^IZ8Yn>rvN`L z2KRAxUfVEUQYYx%dJ(TAR@1dhD#${X%`1ZOuE}Gy#wihkdqXq&QX*c>7iC??*SzHU zIy<$e_U#SFeAey;UF*fo`C#4qPw|>J)K9a1MV%@DZ|z8<$0>=`&^?8%+LY>c{$N)F z8zbq0-fHMX%Xv8+llUZj@lJ>e%Uq1`P7=J7{3;tF>5zOM@)lWq7T0j~b#y|aD5Npq zJe6EY--4gTgeE>(u}61*tBJk)ti);~KwYyHZ1$?Sr!PIFytzuG%h z#`kSwsh5d|hF?)VuPJAVDe6#BxsqW@^e}N9F#GyZ0=Y>w}OGktGs^Qs;*2^0V)bas6Z#@JjCUP+l>XPsZd~LFWPej;jSc zQ22YRgazuS1@Kwbs!GNnRyvr4ypl|ZibFNP%8;Myay;*uKWY@zfB%dTBJGTD4leTE zRQt6@S0;(sdsw7LJy5MfXWx8z!VISKewbDULgAz_JKxqhBMftfcwPhqYk$q^FEa=V zj;E4&C8^J(Vajs+PH*Q;duen&+d1vRjX@9UbG&EKA7aCye9$q(dD1SHe!@jdq=0;Q zAZ2=oG9YZ*_snCB*0@A2`-+=aAcD+{b~o%WQJp$I62mcz>RRMdtG(Aj?+?E{HWeMa z&GFUhhNwoAQ%B&oOYvra{&kMF%D!9YNF+cWhIWF#g1H&tu@Ip}x;bbbsT#ABsN&|u zvb?vru^0aqi#fd{+y+gboper0aWkA(4sw!E0ovH9J%JtZIwU|fwxat_6d&Y=Uj7m3 z|5gd}JErkUSMkAt`pTT}uhtYt!z1yiELmp*} z?m3^O)Z5hwRLX;biB{@I=0{ehRld0aZfWzoIO0QkZZX_{z)xy z|D`XE=rG(2uW!PivX|AH^XGO{zpqW~^xzh|ssa0zR|z3?x)K=D`VZQxI)f}$NgSy| zJ+$J@JA!{PekTA~VZ(352@J^euVS|6zunD+84%PlGaAT{6!@jY`0#ZxW+!q+VSnra z40^4(&+PI1w-=v3c6lF$-OqgU)6~#Fy6-699bNQ5N^?wYM3~NOPW`pwy(b+Vl}45f zu7N-N>s%71j|RMM_i{6C0S}rvn6q-vVA%OiomKfLxBrP>(iS@0?$)Mo0iaYvWOjq~ zqtdv&vzVBK=UX@H8-$9Ud=xqfxCFVPGbF1(+WA@((`fW89cErSKch0fXdo$Ce~h>2 zj**0brvm*RKR-8v@t0fx-lnwK8&0Ls6ajI=0NcfPe?odQUs-2MzmIe)8AVqMVl6b0h(hk7Wqm@8R-(r4>ga1}OK*nSIi zB_OH)U#&Z4g5ka@Myn>+-l=1ZrmuqTp-%>%0L||C{(aFt@?*F7HKo+q$a`D8`=YsB zQVDzG)2x9K4Jr^)!8 zt>gO_m=G0YB4Xr&j=rNQ-S=8>A4*9YDM-9yvAbzruQE(eyjKQ!@&|vf4-Ar3U<#GZ zgxmDcT;WPGU$lNQ*qZHJuidUrnB$*{V7$^G^Ou5>K8FPO{VJYc^}S#^7Iwl3{3EHA za(~>iAQjeW+{g9FhvXvg71%a;)*LVg?r>!s=>np)-t(U2Ud*Psct`S7Ek|)JHo{GG zydxzHLr-Y&Za_?|%(d|^iRPV}mdcu)oZS0egeo<_d5B=7es(n=5C%iF{;|~KMhG`d zTaZ)stb^S_0Qdq!ut*7YHA`~qIQ7XqrbhA&a(MBsG@>-jbaJf?cENWgpZFG&^Ker{ z9)S}UWbzn`R8Ky1aCWRY_KBPr$JF)BofZ88oe)}iOs8Sqw2EK^J32I7o-NNs2|z=8 z00~R`2?zeg?d6DvP!BbrCI|-n-d41b$Mmc34ha7<^$m8IZ?eCsD-xBHkP?)?O||G? z)u0)Pz1b__bK!Qo1HWkHQc4dYvr7FZ>0=}@2V#Wu=!oR5~F zXO?BpvV#SboqQ_O?qQ+U){zB}Dnxh-l6={~SAx2cxhF zjOmO<^9ABHs%XNl2Bt6F2&@31H>nOl9td|I_1-F z%=r%;Cd`amhs$&G;e0`P=K%mHm9&Kz=)2$o*8odwt6f2OE2Na=Xt+u+@*^5O%bu=+ zxYie~U7wTEs`$7&l`GZ%B2ti#zVoxQ=mRbUu336q>-NviDEWZR>yCx3w!R=62w2>Ylrek>7m^aAMy5}>j45PKimNi~p8&H1&wX5@VxuSr-KKzqfotQyizr^sXOcCIN zGjE{d2_?N=?1!TW8#2abGfhQMu=TCeGPfmj{@Cl_IMTgXYAnYt-#=T z@}CaMHNPt7JEjC)&%l3B9+flW8-$Ygth6t(V9 zE_wdw*(1#x+I{~rKpa}6r5*66z$NV5*a1&saNvE!WbDgO#A|FK%sR4}!_KeeKD4WA z{ljFVb6`K?8~0`dcPogHz|MyT(w6;k=Uz&m0z$v5`ysuMBhL7^b}tF!0lGM)>??g{ zZ`0Q02lp1NGNne2-l+Z{r_Ja4vh@>axnu)ThwapF@-b{T?Yzvx@Of(|?Dd{amH7ox z{gT!@8RR-Pa(BWMN)n$^DWZz?WMst_+t#;+0(pe}SxK{O2yp|e3eT4KG3xf&#LHIh zaFI6bl=#qVrh!*~!p>%gKSPOlEILH>G-5FRrg`wUHujd!VZH)=MA7b8rD_(4fAeZ*gr&kxGkiUqm35zLw-ZUbV67 zzb6djwqEaxfqdJzr)X`lGo{LBSL*Sig)Kv#1>Q-0&mPa-c5V512xGZerC>vk>bDEvvWZ(p@r;kwtS^WT~f#g3Oad)jVU($ z&$AtkTdNGNsc(a#JLeSt|Cg%MnL~JM21V_4-)Q-2efboOhuP}wS1tsJGue|{yr%fA zbwm50fQxty&GG}-y_mG7HbEoEr-{cCY%C%qI-9T%J1yCqGFI&sq3j*D+6?Lk^Ft?& zhwDD1kobZMHnC>7W5aKv6?E*`A`$8b0QJrYn>) z`TP_4*MZjA!l|w4%4N~#zYg@n{yEW~O)&bOVGbgn@K*T|xoE*o@bL=uyGn`5 zlTs&hT&Ot9`L-U?=#cF#^e>*B6dzQTWH(-Cd++>K%-iqlScri8Zf*_zQosJWZ+yecln9Bb zEI+aH%1PQmqJPJ(47&YATJh$9L&reI0>~Vy91MKBb$x(O80~~r%O$b(<6hFx&ejdI zptfZ5Q>#|a%UGQ~U2^X)hB1=IPVijDsY``4omfQZ>)1s`!?%>evlG4|GVaXprbp$; zvr`%SYq0x^p%Z)BvPk<xn#Sy+^)1YxZ&x-Yv`%?@F*nR)Z|( zHsS$tyM}WnLUiJ}iEZA6BwFByfPsjO?-bGEx7M{d)SpZ;kgb&p$_QfY_;ox{OXo6F z4gxW3jNtG0CQY*u`X3i`TV&fj`GifeWOnDBnI|KT06!7VK^<%aERH4H%##a6ejFPC zP_GX)I)kzscYs^`!G_6Q@rCzuy2E+Px+y6KyuQC~AG`6>5ENs$Vt z|8PwFV*)0B__O&RPO3`a&!D1PO6Bmo2O_=Vd5zF1XKOOeLPEU-I)gTC?fJ9SwIR1& zmRo*2S;rWVd*LJ?!sMzFK}}r?yH~f9>q5V2xcMX7lZ$dkj$UNX+l;Pbu@r{2+P<*{@Bn;>~4c$eOI39$KzE^m;f3fhrx=J^vS zwY!<{R4c8UBz`jt=(D&{!aDcPutL_y*n#IS@}w|uyYN<={h!Q_bRZj|W_+699==mR z@9y29C|&pDSY`YJMLE;!FQe+tzI|dbR(Mgccafb(QxdRoV}zeZatU240m}ea#I@N~ zs-f>cp^1O~h11%d%Rt;>#Pdqxh2}*~0If9F94?|#A4%lw8gX#}rXcA|hg58qutTjC z;j+kuicvpaKQzWO*=$Lp6$P4K{vhHwnZk^wmkSav!rtbyS6W(x+8lbs_I9Nl{tN{)8(r?gqNH?)#;@tTVna-9viA7fJ;9eENYf0H+{~wl8TlZIeQB{KokU zqx-w0M?V7JDk_Az_U}yXr6!i1+_!E}!8y}65Br10?7wYrJFNWNp&(^Sj@6=X+nMA; zo9&m+9LgJ9LY`I%D1P+?YWo&5C()N$D?%$yY6cinSIUXaOiMZ}7R^4<*u+`Zyj==m z&7E1TA%S;u=bqaHbDH@9{ltP5sJgf+u4JAA0=y?Kdeg<)>`41p`S z-9^yt&W2JAW1{Zj0!y3bLXYP|*%9>x$>esl(MsfzrLn*lOapZ!d9m4JVDzt){QUkm zsXtdU9zo{|3jGe>233LsTRbW_rK00f$F~JJ0ahKp)Nbd++>5T4iEZy>umR(9e3DeA z?OQSOg;r@vd~>uUEgaOWy~Cz~)xWBAA(-u{`;+;)!fat|)3Xclwvg1M*r~6viek&m zE^1IQ^EFhV)#=dyBeo1^R6RKr90w@H4;OVwN- z?WryzvIy=ou-alFbkt_YNTC7b-RSCtS)47kY!?LJ-RMKf-bZaupaq`eT*TUrd2;ol znjPMS{*o_(sqS;xzPSIIlV9=O0$z4ARnWdz9vd(=cO~Mml775;Cu85;xbS=@bP|_K zw;Rv%c^*y-e+ArBS_5hCN-y|7nV0q3hIVBYDqNl3ZpH3ynPZkLCWqV3 zRBJVwh>oZM+u_2g`4(^QZ8B=>jt-3~eb_;?T# zd<&nI7DoH8s&xg$vw35)+b=&&YvZz2am{fmt6$3;XZCC9zDu`#HiRkQq>;M_m3alQ zY?$)T)zAk}DPPejlJQ}SL4=RmGAK=%7w5xI+f!qsDWh!x=qe+3-M5BI@;D}^K6!Vz zE`2{MV_``Xxb-GZ?Z4Eid=o6RI;2z(bJg>zZfYB1>NGnYVFtHfTVcNok=#oWhQ-SI z#NYh4XPucY3=2zC-&T(BN?Fd3|FOo#(lEjM&Yf%8TYlJ(UcttL!Dg&%r zbNt}Wtn9$c4zvvVe;hu+vaOwpxLyZ#q$D>36vT+l9{AUMgYzulmIihWmLcJ$X+1e) z?WNKZg38}yxLW@9H7QD#-FQOQ8SfUNy*WpGa)G$d51qY0l;lNUk9i(%7YbsH4(u-h zSxO5vTP$|Pu#&Rd|Mo|^|E+Y^@9LSeTd%%}bJd1JMTMgJ|FKm#bC#8-mqRA~W6S97 zoH)Pe_+^!;`By5MQd#$|@wpTO&fS&o1MmX>tt1eQMxFIr6XgMkM#cW0w;Z0xD}{$- z27O%wXXaEu6Oem6Vz+dT2A|zU4barYTIo8mFTZsQ)*~jCwpE?_1SO1ijx6L~p#=~H zA+cAS93}eN+j*xQwJu2T?xvlJ51xd-6X@JgSg^A(L&nu!8u+8F+3l(SUa_mo_<7IM zd*tk9`=@)mww%%61?vV<72Q`{s-B;D#|AMsm3uU1C4y?!FsLd^)4u}77Rp7eSV!*f zaJ_zt<0r(Eob1+zO=T$82=86|fts3i}T)6SxP98M9%DC?l z>o!`YmlbF^R$O;!Jt?TRweVJz;<}>&&MDwtx`q?T&+b`a!gTdheXER$5_5x_i=W6& z^$Sev-7Ghv%^@%jf-ylOCL+j}4v(RtXxy&$UK_g=UQ6@^V=UYJQ9o$KbHNxeq2cF8 zUxim;Bv>;~?E>=}QH_Xs-ASwZ&CCMRhba3@3o^C^nXl=Mv)M8yx8fKD>QE9PB$@2% zUGj0s$ip)P1AB(phJDErRjYqFqTWYPb&-ZuRO?BilXv~Mro2XwI9`%{T~~+(ye$V@ zRb~mAWCV!T$6qGh0Z-cGN`m@I#Pg*EJJXL2?rVqKFbgd2n+!3XcEn7WrI!fFl?HxI z$y8(n)bp&5)LdJ1{+`(Vc}dr6L$HJ9wsCElNNlNQ00F$lm{oPnO)z-%L{L@rkXqb3+n0OTCom@%^hHikggWgYQ(h&anyI=rTo%0v%Ae z^G&zdC7Eds>gv&bTIh&Le!T{FcvWCyKH8eFJ`Q;~ZyP4$HCs+;^~#!yC!2 zlKeR#3!WsPKb93wS5gbSvL++SvTP<7j|o<)zvqZcgvvTkPEc!jU9#dFPv~3GdJP~I zuU_xnIgwsXEmZf~n(7cB%X=>4Q7#)h?B*y+ad}G`#PD3d`yhin(vs`EF|6*zs{g1s zmpqOtv#AJ0SaUnUDvYm?IxB41z7F~F zf8fi>ujd{BGzWdtR{Zx_7v4E)SGl?fGKsC}%_k6*TYZMUNQ0ctC63y-~H zuD;E8TRbZ+n|h(kEh~oZd+bJOvL&9|Q1doeGS3f=!v7s}Ey5$>3FQJ@wjxGm-?U?g zDVbydBSEl%yyS1BP#Z!0M+k6>nfN_$pP<)=#ZP4t ze&1y3KAI?O76z^Fy~e6`cLmrCWL@0zWFNjZZ$Hh$EDntJ%DmL$rlsl?y%x|DGp1Z) zK9(9UXsbLQYD11#@{juT&VXg}V)~*4tX!(+4FDesj}N!M7`dI)!_bYlcd}e--p9DS{vSUbXvVA#7y z{?d|jqA#gC(%;?IzG~{HHL%scw@R0AvQQYq-keR<_v4xhvZ?E=$ajA&s%p#N5a~3z z1NY|d^s9BUCqCk`K77}`Q>N~yk?#nBi>l7-bBO59o#0EvcegP$gs6oSonfKf0a&Tf zZY%2xxXZUf@-{!aGB~By=ICZJqeES0^2%xIwS{#?3Yhp1O*O$+?y$rg9uOopW;A+YXSR>M90T4 z60~QfNR#N`eMo^11vytoNn&7G6X(b>)$~`9(%5GbTp`@WlbG*H!!?*6*7d`>c1PE8 zWxPehl7u!3s6*OU3W6~)&5hT0J@FSM2$d8u`*tV)Ir2NY)tSh;D z2l<#s)zv_iaAm)C)apcv7h8JpNDD8#e2o#T7T@7IJ)!IO56v==oi zAD9#=Q^YK?WyVtXRjg5?HA(e?RB5D4+pGod+30nzexVSpNyFd{K$uUNy30rVTgwOH zYr%yb%KP^QcZ=Wa>zy@;JW$>#mVnAa_M5(^%sHR@Dp-VhM>IXjvACAT69q{u6js`X+P5mM*@B?%QQ&c=-NY4~yalDs#$U4961l*yEEQ>4G(P7a} zS1&6jj_}2w>i{Sy>Z*loKL7i1_PHm;uDjpSCAXCc=U2jSMpyzS-Cat>wYOe95anw$ z#C3HR7kb#kb#}#D6x=fd?kx~%c1s|CTu74}lmptTey_e`Dhi+kv_(t3zNokccW^rO z7M7>}STczrAxSLV?*co4ryR8F>MZgO<)%(25=2C>mAU{s;lWSBvPL--qA4R{h|>?h z%%-{(0;CKrg?29*SA^0O8^(cKnTcPAWym* zA~YIk^h_xt5b9fz6Hi`V;@p5-FdyV9!swy$+ov(OQ z_h(Xw!jL7r_rc}6UZ(b%pneEf{dQ5*LfMzHz;#be;lA8NK z%B;^#y5?C>?>r~D- zg}kOKV(7vE5wf63+zOEp+cr|p;D8%-df`ZqMkx>1==l2bWDFU*MJw{<1aX=jr5 zU=2|uAl2lRnFR8Q3MM2O*B0;2HRYNX{z1pssBf<)s?f0JwU|l8+*&bt-VF4K^CHMY zM+P!9CO{MYiY%!=-QZBNA9Z8L!r>twCC4cms zHjt`);OR`Uz<#DIRQO3;{lFw>|xLJjE%tNh8-E|FF$Ix}+AeDAeKaCknW0 zU@wBw(W{3`A^Gc&41RV3(^M~|iy6xP_w(oV=wKe}7F7V#Bk;)|q+kX1(YM$p1;^yV1; zE@!&6MN>;-L6K@hlOFtTqbNpxjsvl{#5~qSAJILu{`aruc@d6)56W@b47&@bm6E?T zq8B{_-}6(Okc77-q}iV|NzNW}c^4qb#aj}T$McbN*TD=~dQHNyGr>`T{Y?+it-F;U z$)LIgX8N^t^4wWd{`yAR-{XADm-&&TqXF6_Dh#IR4t*H|#XKh}k0%hmw(rg3Z}7vX z8sqORvnZ)IqpHemv&vDF{_f9{gvyST!EA?(Yf~aK5oJ$q)eBJJYq^j|0Z3zJuqmZd zh@bE&9ZF$s#rxM1MGgfs&lc_y6@)8i!?7xrt#A!aAi@q=|K(TMxv9ZMDJVGD>x>stT&9*P-;%}L8!cT_;1`_oZ&7gL3@jGgT#nhE`sH^hgP(Dg7&I(26Ylwv+D8y zAbt3(atL8{sMB_#tns#Z98v|lk zMkuHoyHB^xR3^9=N~`%1hovfS?rs)Z3XRT;f0ykv@Y=e=1z}#?a`` z$)cESHU~_WH&i?B0b7=0ePVMWSuEGXAzJNIS+}o;+89MXVzQk%oOQBd1S$uoY*H`I_V{H>pL~!C2wV)68 z)%Jp9A7z}uUBC6H)eK`5r@~oMuAyEC!0Y)%kowgjJ5}sQ{ZPZocCSBvq4z1;H0G*u zyu)^g%crYAF_an6i7W8AoN8M+uqiOvaoB8ir19z1fqKjP5k@s@#rt+4QIdX}COph8 zNQcGlO&(C$L68c-XfB4sR^C{PT2~omhIu$E6EW%WG5GfA$p?m6um)iyv-6XJgu(0G zQn?5*lQo_<=o)fP^pb2e*%Hv_(H}&Z%(nTZ;Uo#?#lNAA-g;0UVh0*J{214fa-b|~ zZ9(A0wReypH{u`CC7iqgcsX5Fl;%Yjf(O<`jK^WzZW)RW!yO48 z69un4ogH4ERVXeyv6?RW#n%(;dyhrKhmxM6U4sOumMQ== z-(Q!<#D2YuOCcD*i>1Mll-3ZfdP2L!xb-IfsZH-VUj55TqTKpMZ4tU;9X1_RSTbi4 z2O&^O#f`Pl{=lR??Fs1HkL1qMVDd!}1@7nkv20;hxdhr{EnudlDt38*HX?8wUqXMz zQRW2`3@ITz8XheTHWKa*Bp_IQw>>j`_4Gj6@`Th{9s-Yv3o%QXWzt1u3tX*VI}p{-yBso13%4BP*CC<=d#EM)mE6&dy)~lAe23 z4t8Hf|JRV_or7Noxli5|ifdngAAJY$r-|0rK`VWevV)>CAKEk`Y?spdm~%pe*8>%a z6@KSpRGXT%O~$rIh0v;*V01}by6cgr46rs%(BkHV@l=}r8_^n2ACj27cUiH2OMWsjOmgD48JE)*v`L3r0;Ub!5g+qL73c3-NG@N=M z`cB`z~=^N^k zMjKbMu<(1l;E@|An0m==PGct_+J#ya;uupWc{m_6AM=Tv&AN$D{n4D;5mXTwBwi43 znW4L^`cnK>%zo_*v2BGsEtCO4evbB^St+L3Ju=N4QF9Ot0ZQnFOe((#S)}l6`C6>G zH;5xkE*jIa8lR4|x`{3Yx7$d_>tE@l-Y*~dk?1k8vPgHqbGS>g#9Q3Vjva)Ff)oIw zs7*=>Gf0PH>iMqo_Lw7aCe$ufXN-^~_2oFXllDpM)=p4*^W!^`sAA6bQ)1ET70(a} zfj@nkLLQ~q zTLP{d;ZE_?*~5tQVe-K1)nN-JrSQ@xVTTD zL6p+*HYkX*vr4nfe4VhqZ@f&}?$6J3sP_mbDIiRy9}R@trCd>KRrPvN*v7C^n>wA! zknnOpj%0Qf46Tk7{3WRY(Kjg3#8#RVq-hL|g_bfp1Q=!#;Pu=>aW1Au7~m7hpO(~3 z#X@zlA8l|9e= zXzwAqI*66oS>>!JGyx}{wsnr%!@dxQv>VP+Our>KgQ@z2p@eSDv6kIq!Jbo12YjC1 zh2VeP$GbHmb6I(mt2YEXzc`lS#W^Zdx5IY?>uY%u=*abv0$>P(TG~LZiJ6h_pV2D^ z=hY978Jd)$Qz4G>RPDNt_Q`Cw)qjZk?D$~%v;FIZrXH)W)09%8M*sQ4GRDnX1Ug;Mu%nO1lP%N8ElATTD@~m~JEIt`|vyR@ET~ufs`2>>sao z|4fbNW|$5wsr=MEy_74up_R?^GwIUU&nK{Ml@weYsbToo6aIqu3q=MjWrPj|5pDvv zcA%1~T?pE_LQ3$hn5#Y0k#DOL92eaV%1#Vab1np^UK4uK(C|BYT8-!rKBh!P?hRSd zL{xR+w#O=V%B`1G$vs*i^8u$Xina5)G0}I-1qT8Og;u(3>fHD_DeV=up=iyHdFvrs zBM(Pn2I{0-r71Y?Bt>yZQ1kBNjce%0cZbIRb=BR{UbUd)q#Z6VF=tP>*r|P`Or;80 zvUHBT=!xYc7h1B^#JWdw$qMdVRJoK_oUA71KM?C8iZ3i&dU*k8-f2O_4Ri_>7^;!0 z)w#&YE(TyMGc;MTJEdC}^HnP~dLt)>gL|pCqbtDlW4g{_x-IdA83q}BdlX-lmzGsK zxIbKBoZPO`<|?%Rd*zGOCrHWdSoQ*Q+uD_ zHYLf#^9UVn@^soR!`G!4o!?H**c}qlq9#^KRcPZ&&`a*NF`49Kc$<9Dai6L3)ZeiD9GMe$wohCbPkk5yD!N`pf{AT zR+4q80Z3Yr0J_KhR$Va!HqZR$kMq}5{(ATBPp*fr{yuZ|vQX5I|NB$(*L)xFMscth zQ-STciXgx2TZS@+Xse0%y9#-QGQO|?hwIU2Z$$CXw3 zC*yP`!U#RrkNbo9m&*?hd!C;@IV?H>U~*>e08du)W}M(KU%e(z*fA>c4T4GKl&E>+M$>Feoq5>~>yQ6JqD&B8C-SiG?-&@;OnNf+rJ?O{-ZR7}k8ZvOsfH7&PbWf;7?9orPy#hFF@Vq4vl=FjK^Kx`&PyL!d4n;qiaedFqkaFr4-j4eFqT?{UoH!I9!qT+F1R_6Bx8`!V2jrgdy;Y^|J z6O%(;%pTw__uX*$om%A{pS*;KM#RGL$tUG13~3<t;+a~V0zrBPvXm+kKFr!2AC*sa_~s1*3UgIRtmssb2$$-eK5LZwEMzjBG~6i z=G?wKM<~osf{5Rz>n0pE@FMRfP{X7)WXXL7$8x<4jb27cZ%AK|P4(3_#Cm?-QSpW2 zS*epjXYF_Rm!4lxi z=p3}GVvRa8-Fic`U)%*U#jL)BAx|HXntB~b$I_D7`UUWQ9AW2!f#nW6VF z3nyO>I*d+Sq8ax#F9>+FJ2e(3>;_3K2bwVW<*li~1_`RL4jsK}v{T2)l2jO8N+-KQ z5xJVB_5vmUqG7kj(#t;2k-34Mm*mwxg1-n`yMsFH$;(V$xXZn`&x3jM`h8fZkB-6= z@TnPag`rL)8PZpbC*t<9V>B+Q|9jH<_X|}0d*yc@$KCm~viO(XOne{hl$^YQ@HSNO zAt?y~@;a?3pTjfyQU@iF0)w{=&8CpLKYUs}Exa0zPNWWL(i<64A(4!u!Gx{uRQM3G z%O_X8e|BTbYk@+_>*{43_J)*>a{zQO;w}#Cs3;69eRl+a!D5`TSnS zn88fqCfO^X-N!xXNWEV%VP4?LM5!34^-RM)^qML_ zNz4L0^oTm4i=XG_i|he6{aBXsvsh@ZSlN>quIO!-gg3b|8{IxAr`n%)XVSon1t$B? z4<-9Z)!^>pS%|Sp!ePng)5OWCra}0Ahg`?P4A99jY@_Qq4;Ti*us4AIjhaa%&ZS}? z8vS9`J8E)KxbKtR8E({LuX&bc|1BHn(3h^JbI?2&97UYQ8OusNsy-EfxW?R*Vq#l+ z8PMKlyVUxP?m+R$@(n_OP0O|i-gK*ZReY|!<*3k(ShEov$QmlgPf;~nB;4@C&5*Bl zIyD=vfo%ijiTU`R&5#s3MD@n~z}cR1@??N`3(yH~y~&8OBUWzk1;X0Pc_xq0gScsE z^B`)vwP_GE4W(+J?JCxFz!HQN6c{7+q1s?fC)mVT9IigB%3Fx51Ms zK;~fV6m&fEC1TKI3Ys*iGX;nlL`?#s2K^^n-wkq19-e5v#2+4y4%u(Djt%K=wf-8C z*#dNRm#PEnC`EC~V1WCQzNj*Rj_cM^AF5nJi1U26Z-9?8OgALUBpEuVPMtbAft*fC zdh(dx^h!^KYjLuD@&Tn5Nr-&*Y@}PF!g^^S!1aymw&x1)zRk?Fy1dVZvm*Cnzv*4x zzo7TrS+X|j=Ch)2f7(2ZwW%+S^S=E-eI&;kRUUnG%JF4^P0~y8&=RDCr)8K`C_f0YQLjHUXSGT>? zXT6sXWc3)Y;)$8(Gb&U(UJdj`+-f2vvu@O$Dat;6hwfx)&l)_l9kOcg`)5@A9G`R< zx2vIu)R2ETxAez1(mX7zR7Gx!Adm5D=>cwmA3IIe{^fNa7TcP>0Lv~LZ=#F(?G63V zmQUO8T46EQRi2(}IX7^e-s>dvCui2b?-Ht!g~ldn;(eD0A9v$U#ay8Ka;Ol z+ZbL7#z0P%`3BeICtVqazn#@(lCj#kMj(aU))@^Ny{vwC@xGx9PyQ~K`#pdevNE;C z>d)y${}QWCn+VyCQ%^qiN)c0;jW=L|8GT=3?&16 z&{@#ou)<667LGb!q&BQ9OKIe(EZs2W11%x8w^QXys$5zX7X-Xl_!4{YgFv8MIL)WZ z5E#Ij)P8*^T@tu8zG?{hCkX8sac$_@6?wP5JDYNwQ!>rPil%ebX>t9!vIt%U&i)FI z?nsB6RjR71pL?SO^y>b*y}PAIZ$JlK7n4SQ*S>ABPH#siy04-XRc>9H?A#m~-WE=a z>ZHNyQw{54KkFwv9`kNV={pzk`!wQO@|_u#nw0mSfEr&OIc++7$$zK{Ut{m=Vhb?- zB+>4Qf}tOaU@E10UvZ)V=VK~&C;6SY$mElkFRoti08xOHAikEeBFz-uI{|mMM2l<+E Ar2qf` literal 46370 zcmYiM2|QH)_Xm!*skgLRLiVy0p&<-nLQ%FUOOj>El06L}>y%cEJtWIiiV(7gn1~ts zlARbC%w!wP3}d$YzxsTC|KIQ7K4xBb?!D*rI?r>?^PJbY1b6M)Rl>I${M@z62mHGL ze&2Kt2=wy5FAdRFfvB99HVpFeb(7ZAIxl@*TUAX>RqZ@PTiV)G+T81*yYv+|uZQ5h z!?3;oMAVl5``Q)0|9{^*pQoz-H-5BxxsfN^>B=uI>HyzUpRYXp(G4oS`$GO(t%p82 z_w}3G0|(h}%B%Z$OPiyWC4W0b@6XxS!9igLoeKII3rG*Ab3&q)n}C(R?85Nk;@qOr z($zr|%A@MretT*T+c|~|3~Rl81~1-p2pMP-o_>`4T-Z4@=2PSf|K!Rj>c_e%VQWRyEJZY!pNXZ%iIGV#CUL%`kCUYYTVOyX_h0 zeE)Rg@`HT@a%XR_n=TSa?x{zA{q;?q5*>33k*|pv6O{6sJ*%H`BfP4EvOS*fs(Wew zS>@{64dgSL)$`a%DY3ou=bgY!*uxjYqA1^$U|X2G2}7|b0ODL}Zr2o|6=fH(R8%@~ zZ$1|3T^-04?nxduzaBmkc)_erdl+iD|I@^{y;I2o^lb=+n*B~AX5ZPjQ{olK3kS5_ z1`k3#+=H&nk@OU##qeH`@ZsKbUX9m(saf{x-Ud21R5*39q4qbm(cbY>H_%#VlLOG+W9n zJ0?w9P*`f-+b2fdD@NTfM*UjMVDg_6$tV@%=4Q5@x?hPUy3zzUAPwogFW0Lg*ITOX z5xbl^`LkibExSW4%TP1n=JD#=$pXfoIy`x1-Eh=)OJjX8e8*>|jw&%p$d(9Qx{}#Z z7^MCqZ(Mtau{mwo6&Qf{`h_^EFS+L%%3is@!KJbwj zuYJMk!AIyxwewK#3}iHTi$iTXvkNNYvLjLj6uH(9F2Qg5<{JLr8pGgaLSI0nJZm79 zKOhN}Dw#-AC=Pl1iYV!BGI8NdPhY;!M78nW3OBUC#S4~S!Ku5TyF=6WyG24QFKPbY z@d{TY=SJK&x7BD)R^3_uS)V$t)uF@MARdoAv->xP%|Hdln5|vVgr@AieEy306ZlsT zqSHH`rI#)xhr3TOD{@KuM2Y(_7D^8eX+P-xd1nf`dmLQi?UNJk0}pPb1>$&bXjuNR z@2NdCBcgD5`1Wx&WM?^QmSlIMBU}*$MqtC1!sVaP-P;K%Xk>J^;-_Fy1%|75j%a|= z1tJvnx>zag0h(APTiKMsyZ-OlnfHHa>Fd5h-r3HgChu^(+%JwBcxZDv(l9$-0L1cg zlRxh`R7Su!G_&6dbcr3cYLr}Fh*ueBB*hCnKwIN@l{MV7V8VXS(@Sr87a|Qu^qe;1D&SA{8b`7!KY9M2YvqumnlcJ0ky4)+(P8+ zT_ZH>J7P3RQmUQ}?c-H5O9xFHp=tT55^0Dz2_o#vb2OefA@_6PE_pCC;zD#fvQte) z|HY0Qcorg~U!H(uh=Fh!+^c!PXxIKX|843{@PF_Yf0>6?vmA2}#mjUtuP2I6xMx51 z%|1rD(wJ^El2I6uy|?#cPJkie4Z2be6HoMwaczGOI=LS73J3$}wa-A)Rdprp_1NIA zK<=qPM#FGOX!O@t&)c_@u1xPZ#%?^c@yElwNzmM}UrHZw$DySVHQ(&>VqyiTeC2DP zFDmH;komyxuJ7jU`-o77iu*gR>+WFC<*TjyM+EN`6BzoGzJ4%!=6%P$lH!w9vR*rp zHIukA8*h7G=ULPC2gGOM;k{kYUWqEWMI#M2!65uHe#b0VOo5?Znt^Oj*$Em;RqrWo z3-pM|?XuS(erw~<9sY0-2+jVHIraQv19wU7H}r0VDBkN@^Mh#6H9_%65a&J~Z#6lF zYj*!Z;y!WWzHB}Tb5JYrXf`75+li())Ak(;{y$;HH36M*M>KfNjRihiopV%F~a*LKZa5P>3bk~dQuNSP)0$)IyVSfGyYWf}- zJ%V>uk`_~FkGO59`HyWtLsj17{kIJF5@&nk|61G(Ya*P%t6;GI;|@2;f^H<#lrI&j zcWaK;t9K#OSY-e&5(Jrw*069cm?%(NmbI<3XHaoc?+c~oa zL{NIvEb~rw|5MOW#tTi>c1(I(S#1nN0Gzq=cJl~S4m9cij%=jZgCXDl|JnM<2eh^w zGw&Q82`>g@|DQWwBY%It-HL2H*Sn8t0vZ*BJoEAIpFYo>|3Saoqh-Ic#xJOQ<{h6+ zs|)BIhMEy60OPIPyF+S6{%d5*)y&V&z(s&L3k;l%PR?qwqQE2~d|L=P7PU_09?R(a*LVWi5q{1ACWA9KC){r6s&ZRK+ zHvfGF{r_G4L`u+3653aCIAZeYPS{S7UCG9u1kptE6WV{WpLWpts^q-HU!LowO_M+d zxTdZw1KKdc@1|Y016qJxS8rep#hvW}X&<-kICOB}JQ$ukEXS+dSlTR=vjVXM^As5F z&7gj$(yext7yt9b|I0j0&8H7o`X8|Wh8Tjr$D#!)dZF(R9MEEXfr7L6X5ZnQEE57z z0<(~(({goo(6y5a?T)`5pA#jTrwq4)VOC;RspF7(X5(K(0_Hb&Je5y-i_b^wU$VbE z43#P3)0$~d|L0CS9(C&fW7tm@Et5c0?JwQ85;r;c&ksl9)$isj{Re`lvQ%;aga(8g zm9FIVzeSYHR2$ZaDBRKl6WL^~UOUL+A9hjy-{!^pm=KtLPpYt4-7_k;Nc^8)sjSEfqncSVih)5VZQwpQ~wddqP6Xwu^ zZ`X&fH@uui%DQgN>MCc3sidmRf|m51%R2$aikqfaQZl&4%*vC#9Zc$B@ttMnj7#T@ zuRPzMuoFzZo=M3gasRt;*c%+L{qJ{6e{gK}e-DgEpDxJ|gYMLZ6)d_F;%e9Gr(m^T zVIOy!NT`2#lGmPi23fkLC-R`lGwBBXuw169nc7n`HAI@*{c{}=PAPSTvQ&#}3kxaT zwQ`vbrfR3n)Qn8k2x)H1`n|_66f?EjvE&~On`U+w`Gx^$Y)gjtk}Vm7&v7~NzSuzR>av@@??SZV86=y#))?tH=YPo zIr}6H#5RKu(*H4t*gta6G6SngHUBg)dAd!jbbz7s-FhdKLThDr=rGF2raF52i-8%) z`27=KWgK3+g0~0f{6r2F1pCQ9(D(YPBHGY7>-PH3l4g7RNXB7tdZE+ZfZLt*iDGW~ z&!~QTP1J%ly1WWM1(y<#@-JLT1PPOomF#cCGcLhe?}?v<^2EUW=~0`5{sNnpKE2eZ z`QW2F{!YZl&q7-FFuw&_R^QelPqcf3KXx~#Pnii`ta5caP>?=xe1@$Jdh~{c<;8IQ zaeFPxr1DCjH~rK-kGZGx#ES{HS8|_eCZyhwzIoI7jKPvCey#HINLQ{vRla9`3cW)N z%5=diT7oIZ#GrX3@NndNd!Nny;-U9R6MK4JKCpFcke^8f%Y{i30s;KTQgRDF)RcqloVY0NHv9!AQ)boE#lHvv|z{zASE z3Vuz7#uiEJ)=8LfClyMVjJx116VwI7b?f<{!I4AAq0*ycHjX2OLO7(F_eZD1hvM{^ zI$y;EbumnCXOo!6!N^pipu*|7^!*99bu9OqtW@|MwKM}(6r+h(alMaq6E0%j?KVLy zJ7QCl`+~W8p5yDeM4By~tI){)3fFu10hI1YP&V(MvGP)4yNB+`VetmZcibQ+ zeOcDrwC$f&zxwLdx{}tq#@4#L*787FZ@L<_G^IOFuGdx05?*Mvrxz;Mds43VoLp~_ zT!J2oKgmw1W32PHgkN!3TZ%b>-(#NNBaPqV6Te3+zsGlej|G0x>N%Y@hPic$HdZ#! zEG7^h6X+ikh=>V9#ZWKBs8_Xyer*l?+#33=wY=e*A*#p8`!6|V#7$1r!DD|m-Bc~O z%si=FcX1D?B}KX6sdBryjbV-MjcByQI8VYKw|h!|x)HN973A_6>6tOx z@*j2I-8et~1)#veJc3(>Opj@xI zT(7lU!pi#Iij{`F_|4oWflj<6CO>JGA3WJj`jyhX=hG|Ygl;R}u5!A&!*jpGH9=#{ za{KY$`huQQX-|@#gqaN5-1oSh|=B*4)uv0$rQ&ZH^Td`SKd^p-Vtn9XyuM5Y8@LJ6^{M zY>ZN%UPs5;(F(Q$z1hEVf74J8SRQw|6Hm1l#TUv%gv#oA+9-vai61$x zWB^G9M5glMR^UB|LN+3L)Bm!V|3?l)(Yd^_2V=cLz^tRr6M;uK6guix+d5&GGwNG~ z5}tUpdnNJ4`rAoIcCI(jmt7&EQQ?e93cY9?a!T{c_l3SGJ+4PSC;S(#(hG%-9bL9w z4=>_Km7}uW=yPMLEz#5OQ`Lp$|HI*zu)|A%>Ioo%2k8@ZogUj833~wd^9u)H#%;yd z;iZI!wo8XcR0IE*prbO!0LruV)HhF$-ib;Wh`V+5=61o-)xmdw5EG)~VF(1#!ao2! z;5ft(aG1UA!S%VzjT<;Cu+G`VN_7DaEaS;vcv-Atz|R<9pcQ5eH){p_$x_i=BpFX8 z2r#J$g`+PaFVbBj+Q`M-iMH`&!Zh@;cUQ;aH5j4Yc_4OnYd&QE&R{*pzpwm=?-5CFhil^9MrSgUo4cZAh; zUggg&NYhJ5lk3CAR>p{EVe;IV;2Z)pp%7uURLosLRR?n6kArLd9D-#vEbt?`4_)Zb z@M(+^V2y*K1V+_@VVje+=lAR86&3%29ps!&`im|qH3h;qT+}x5)QjpBIUOBwl=dgR zpBIa0)`l-G!aZ3tsu4{zk8#aDX!iYT01i zpUF)nW8ewPrrcJt;ZR7v5?Avh=_46<9EHx!=qJFEF}5|fA-uuGo%4=g!;`35N&#GX zW39U@&Yw^^OVL`%nW^+hbZL5fStb7p3!03;enn&+7New)AQQUCh|ohs>I1ig1-2c! z^z9fd{t_zE?Zu1<+Btg+W%+E%XAQ;2-a&g7rW@*H8)o^FqlOt>>M|EDh>LQHhxwm^ zS#!#=KX0gNpu}72-MnU5`_|(J1o+n*(QHh#cCai*Fi%Tiq-=1ItC0y?J=F_gUOL6) zd)FW_>E7OUX39YnGsJ$c{YkN@kbNtTTI3O7Uq-RWZ6&|)FJ5oZg)tQt%7)m<-oSym z(XwSDya!AyPgr)ACDSZ*^@t>|CEBuU-NY7n7{s=@Tdbndq~D4qjXxC9FkV^B=v{W~ z3GIQY2N^CS^CJoFp(F zvI~h?p1?SxR)O0_wvXZbWOQd?lL^FR0z~KBKvTmQAlbpzI0kd2EfvjJWt_wmvM;{* z?s$*|cYzt#T6SYbe_`VWaUQQ+(OmU%fV{{sr&AKU{a?-ykPP9x0}2U8C0(b!if=>E z>{kQp&=Bk4D<*dVOP8-Fkg)^f{Oc>;z+(MR^Er~joCkW-g4UeZ$1kHyEHLviGmsqZL@c*4uSqhf!hI90dMM=ZPh8U|EJgH29e2=r=F zJE0(^&zVNaoM|PCP5s7t^kXZ3VWs-9ka|-W_98oi&+m(Rf-CL!{Z+ycqwzSf{}{ob zRm*tGk`cl~3~|^X25g)*CYhrNpJL2%L~4?xAoU(veSM?>ta?8dGXTnoaN+74140%U zD~1nTXrq^-LV}_!;|cF+OUjJVqkzkWYSbX7DLh5W?stHmb;u86(;N7T#zR@c< z+A@Po@GA%8H5X*{A@#RUVXdfvMW~}c0l786i=8;2T&$B(-=hs6FL0$20Emu})|S6F zz>=p@?5oOPpl(n3sg7|i7$0e)N1xS=Vb@yA8t{G2-F(I8O{V%To&cl!gxI<@wa*8gwcgASV*g)4 zC~%L^?-g;}|1a31ydxIh8v9Q9V1&07$Cl~A2$|i_(f(6;?6PSr+s)%g zE+9zs*|jcpneA%xUGbF-mtf#X`goM!mUAL6QEsGQ5CSV{V?R`&TBDnQ1ATDnV3TX6 z>ruI*F0}equ8%1#Hy@QDjdHmV#4)A_vUphnpt~2#E@L{G4M$z)B>44=w=BpQG&h@! zjfp~+rrjbmnFMeW0OBkPJt0t$Ge4tcvy5l{5yV|X=Vp%qQ> z3LwUtciF9E@fc!3X>Zw-9?Ji6l&w&BK%;tQX^m<%FtQFjq7C?i>Cbr}(=`{+rrlwZ zA8jZYE5PSac9R)zF$H-}jb4QCoc>|{l_fZ57w(7j#sy=0eY{X?0g8%zb`aD@d}n+0l7WUd6SI@gR zd-Up?H!z)k-6VbeWGMdgBU?^}4lGiBJLnWAM4BURoIz{;!n0s zbMOMP7+O2YWQ!L#fyYj+-<4Qy1)tt*2*LnT%G?#LK`T zY1O5<2YjP{z;dpLk&oND*^M}=Zc+t7?aat1*2U8C~!pvNv9CJ2NFOQ}Y zK_JY(_)DI`dbHpa=Iqgn+>9c_+atj(xGM}WecJvln5`6|E)CQEq=WnxYxf**vy}@H z7HoIXjU5K}4#q)j&P=TNrs+a7VK$$rimP_Asom)Nnr7h4!#=Dr-2cbMJAN4q8=ia)0d6P?&S#N?G>O>w#j9! zCq2(lAArjp#ujc9O>id5O_mJ=0czT(Vxq1Fs<-F6IuEt4-I5#}!^x8*=)KX`&wbHK z=5rE9n91VsC()F=aujqE4C$g>laplK)XX#GQKGPcCWHW$=$|9H$zJE*1j_ngh2WXg z#VqXr_=c=8y|key;54WuC#XMhpmGebO$%*rID&&K5fzN#e;4SHY5qlK5{Q*c+)Y>X zZ$n+sR*GVU)X}4P7X?Hxk9Y9?Q@{j7nEvYLOZS4<5yQP{qej3@+77t@R!a@m9T;^e z_M6tyj7W}dc@ue&jhJs(wAwD$+b-V?`35=z`BTicpKvd%tcTvC`>jbdF9dl%uM@x9 zHf`u{?YMfY~ z52lQvp#Mbp=Gjg`+V-(6OPF%TEULpNY{_ib)y)6=| zm$MCFicy-10`6*TY}syvIB#ef)4Q*xMJ;j`_|~RhXEbA^*r3d#whRY_g~T-IeWoZo z=11aygaG4!+(-yPox9+EcuO&qKaVQA@KQ@8B=9sK+hCvkRJywhfsn=_=r4yJ8y*-@2U>L~oMsiXnqS4KNa{6Bu zp{;Ar6TNvBl1y$%wUK>ew(laCoUoBMS!(b$au6@a=nW>pWZ}-g`s8iWZA^|?6s}Zv zoc>u(fR(YDODK@L?{I#9+1;qbfq8+Ykj9Yva3;l<3DWzLDLeNaYU}+`%b%9$BWBqs zQzt@$7<(+xe)Idy#qBSvO;Ks}`qU%TK}dJ=Z9Jar5JT(&um~w}%il$vK{1@k7rdM< z0p?4H|IM^Pfu$@iFGql%86wXnptsMa+ok(E^^}!5OH~qL7SFvn*QiLs0JNpa!le*L z?iXL+Yz!BGC-!B;tPe~PeXgJ47H)Gc@P|WL-+1f`TFDo4Ca6}d8*tH;Fc(00|aex*J+mlGCOp+5xv=jyX^vO$y0yU%;D$f zOwjqgQk0JRhmIrPu$A2Sfj<5%44HE{QKs@7DaQ5TtyyNPc@<#I#vBJ+Y5A8~qd$P; zG0YwoxbGPjOs$WCYT#?j2^N(E>q!-4#P2Ceh^Q&ig>!%VyvM1idi@H>x|I1&DO1F- zz_e51p{httDv&#OZHM{^Q`GRq?VmN5S?Ti(^-X7|aKh@t7$TgLUY;v6iVQ}trh~qH zf#mN(Ib5^Fn|Li7wH=GBJfc5ssp~>(Y2AM6Jl7{39KDxJ5}AVi0Yb<Df|gliOHDohuK!pw zyLJ1$NRDPQg8H?ocmf8?xCI1-M5Le6KQQ=$7z0OhPanthb=-B@+aDAyk|UE0@Es>K zFYndbDc`FFSOohRf@wD@EYS_!#65u53gV~*MFK{%TYT#|j~O`fml%em8B0q}e-sQ} z&e`|ire3HYwT~kbxqUQ&;xb1$K1aC$HkO=o+X+gZsO84UO?~VTh1hMzJtBh|RY18` zAx@#}+<=j|Z6I<15NT8&fKBPa9%`V*HHNVAsC;>p%fq5p?n=l6pyKm=90XJEVlt}h z7@_V}S!rM!c`xcgL}DA4&Dc`ows~Top{yaQ>{K?Oz72B4Qfd}5GFZowKVgRHi{`%l zrmuShuciL015*Jc4v6wo6s|g<8qXj(eulF(=hwsE3)Ejbge@FvL9G#c;xx>I zNkWvfHkPCGS{&@_STa+$F_^V(Xc{yf1Z~ZuHN}Q!95noueKj9ssXcaR@LMYMg z_C!RnQKEpW4HjWM93fVLE6g~^|9(8=mC=den6eakXV#l#rU$HV^ zm4J`1YRqNMqA?Qsrv?}L5e!LY0pOwm^9-l0de;CBc(g7GU9G%_TG``T2dBSqc z+G6e}9Nd4lNrmf`n>cWVpF4H+!GV4}ut@RweT7^0oTCfo18X@ZW%tJFb=+9_oB`VM z?HfdzSU3?oE0`xHKO+3IKXIzoZ!6G0{T3p^fE|<&ybmOMirfSsvF;!txXw zhTMq^mg1Jh0+2BOQ>Zd`ppu6<`c5jZQGhzS%D7S8H1Xtnkz$zY2(%mFDq;d*dYuC3 z4TRM5C{8`D4 z?(bpJoAA~s^!+pusrn|48k3qQm8UAlhBpEVbe2?DX_U+|c8oVi=MQX{K0Xd3>p4P- zsDrk|B~#p}=G=@Bx=bYJG^AKnrRG;YI6P}Kq74ZP*DCX`Uj!@|FcmHUb|=E3v{;yvgnC%xB9}Q; z9~uE`tN*abez{o0luiTqj%~4SNtJanp~hO|1x5ibWRYRHrCO5$lc+jvtYGd)V5QAi z{1D&ZLnaK6_^D=giIgKV+dpn}!vxfTR?h>G*2CC_U;e`HuzXC&+uInLD^`Qgr|PKv z0UQ|`!(KG_T`(`9iBL<#kuSt7ScE6pKnXNxUpa8Jds8j2&x;;rb;kVLAN?Bu=J85Qfr+=JY9#CF-E}W0CBQKeD`Qh ze=$ELV!5r4=iMi7+kA}y((%PSKhS*($TtI!f?=eS24_Y1- z@t7;sqWzYxjS|T7P+(%ZOwuR>j8eHiAOtAfNnk&xo1yhH-oUI$wLz;5iYQ=^gxM-O zX)<*YU1t0DC##(*;v|<$cxxx=5W=- z3I{*hddGVqStJsY49oh8c(jM}X&`X`57v?rQVExgv8h6NM*N%BEJ7bY(LVr35bKr- z1ozP7$F1!0eM@C>{iu^1u+5|hv%=#Ahy>j`wB0b{t)+W_74;{Hu_cH{nW-h>!F}a6 zwt-lCh&y$ettlG?sqd5$$11dARM*PDhJa_d7AvC@8y`ckXN*dLh)u)BuUH8A-K5ya7wC7FQ_h3J7j098gQOtXgnQi8X0}9LrECIx z^AdKEQ@I?aWM;ROSV)XhD3=VsKblLLI#Ujm9v?k1YptLUGOr5&Js!q)O8vV4^STR= zPtrQ@6(!lq)i$=?qJ;EwwZ8%ytRY$@ z4T}9h5O(4b+aiM7o$NL2QDnFA(&5T(ayUF#eGjodF=c7k`R^^4R(ETsuxeds zs^Vg{+kIclEc&?ffeTMWB4OoCSYaUH4qA$5=Z%{?jLxMFQ561iD7JDM+|ir66gxY+ z39MiEf?vHNdbNgjwsG8$2-{8U0=B5a6Kq}RV6ElU3|!dkEzT|50b*`iD?{q_D?m!G z2`HmrxPyemO|_*|>o) zM?JvT2XVi+^S6jciHy_6;c_D|Dw565nzCi-jU>kqGnSy-vFyO#qZLQc1I{tTM5k}q zN6;lak39_cd3xMo7(2z`POL^XscS@$n>siBorS~~YmBgq+hLqibK7erhz4E#LJpsG zh1CAEh$I;5lk&PLWJF?j{xZzsT&i|&3*>3ZjlenWSu(Ajkzg%!pmJA9CzddPIFX4bzZ7wjA3zm+sFm6d zJP6*}CC{Wtj-dA1=Sf_XYyu|Y8Yy?CWcN4hrSaJ%Lvsm_J_BU9GN7Ijc~~gU1N$_ zH*8W(|6$^iDfljRZ_GMGiAXeJhMZu6TmP(UwrADEIZjD+k2mq;&zD&RCMfGogV9P9 zdSHmVB0G!P&!xnJFA~m_qrN9I?3@UI^(pRN5h*wXs~jT*33GLc3QrGpkEGFcuR-da zU80=-Yy8uSG5}2@EIR=xQ(N9L9tlUag4<~}B7MDD1QM2h5tL2obE%&e<7|O-qI1l8 zF+qWwAdblnZv8w>xSoa`400J|izfG@j&St8mQiIP^`3@+@`i^P6FA6(fG^W%KtmPw z=q8~#3VnMrWcFusyZAG^IooS{Oq=b~qmCeWP(*kVmi+j#5%{hQ-B#Jz zSEPT^`iZvXl`r8obOg`B4WT!-QIfX9wL))*H;2Y$#p66|2{+^OiZmHtFH;Ajtd$qc zh8?fFQ?_EGpsR?U=GZ8PovV{j#<~)d@+ubTkk()u>7cPyWmnaxSjM>^wX#*DUF@Ck zrE@Aq(PhN>xOyNW zB$(3A_l<6KhuQ`RX4^4OXhUoR4t}PZCWvvLDr)FC95Y>E`^yb%`yb=ZOFuZ6mrn>B zcyqTSO(9KQmvLA0KSOnv8_;}}GmREZaITq_@?oXzMlOCuT z9Ip6wR-)Q{eOBD5R9fb&zs1UxGnsqN*$En*z4{>VS*gl@g&|e$|3%w9J8ZCfG(9M- z%CF(Ow5*(;MsN5%sku0jE~-C1`s}UJtJjNF{P-QSQMzsWp3CCP(^;=|&k6Frf&0BX zr2OtbdxsOM&o8yqT=Tl-Ev0himQ(JV7ZEPa5t97Z_=3JfIPA0T6EvT1;x#~YzdrHz zMC4d0JJGyn@9!>G*TprJti|}kT0Cy(iIb+r-h6#YF>BVt@uAmmnBKnTE936gC2yEW zaP-^VTKNsr&)3{<)ZIF-V{~04KOKK7cyGD(crCf2kaAw5W9-eunR}fJQt_&XFAaDw zLd<0>HP2VtUp~nHEB|I;fCwUC$^1Rk!tC0?t#t#+%c`{>0awD$uN;%T^_$j`k*Z@o z<6+?1@d-P zjS}LBzg54^X}hFPA7&TMh!1>BvcLZGk%fg*%f$42<#U@?qD6|_W_cU>S5IVky6OSJ z{(0{c5Z=I4xJozQlZssKk>}2rOq8!xzH(->6%kB9LFF^{3Yk9jrC#liY)6AS&nd|{ zUDhp-esh}lirtv3r+K7vlB&mvlU|p$-&$(REzo%YL47~bUpdUnXPNRqMd#CsqU*d# zN*jNCYd++c1sw4fG*J?2Us}6rsfWit=S#5fs^HqZFl&F~So_87E^pbLhz|GDn_`Nu z1+9Js^YH&Xc>2W61uJ=9!w+x8N(~t0@^{a=r47p1+Khdi36%ecT0EuEtMgls+x#-# z)#+pDwz#aukA%aYXeSO2bHkm>KE5dWtU_%(ilMdD1Tx;4&5t~f)%|vVrj38=kl+c` zGa}a)!jT8OgbLOSv`RC1LQ{lzVb7GeJtxK9Xd2XgNRcVqA1f1UYLKxzUq#v>@@8n- zZ3D=K_)Op5XK=dG-trbpcl62oeXWziC)Aqxiu;-27bZCek*eIk$BF!JUA(*Y^6K+c z@OHeaIVXJXrJRlUlZc=zd*mO&ck?{{;+Cd${r$dy!bo)@-HEEX7a{Mfv>JWx^7txN zThu1>B$+_{(>MM7(H{PuXuCr(ibuRQQp@P#PPbp&S@r$#GV~zwLgu;4ng)KalA;m^ zPqyFs;?wo47yqJv)i|gr8lo>Mk!gO@6BXu~n~_UD$-h0mGIFId9Uo816g8H=zOe03ET_=FjG@1( zSU9dK>pmfftCmrH+W&P=%B2b`8uIKj$wXe;?K7V|4w}{_ZhR`pet&CkmH&;O75mYb z_ssh)*&gGMt~n=|X!YLZzdb|gwkicDV{J{(Dp`#N+C<}P9WUv7b#X0n|GqHg_3lz^ zB-Z7>uK4hKKqe6oyY#vx##Z>OUHPapc z;TW^@>eVFqD(l@HaZu}?-D#?`NTPe>o~q%&h3H+j85+F_2|X=)ov-hTZT#K&v8Uy^ z&ACf_hb#;y)L@tb!!=m*`Q1(Rr=GQaPAlXaqZO~*kQq!srR7OmdIZ?)&c7I&+`)%?%SqUul2XAU&J_ES7|f< ztoq2t=v%>K(`qIDp=?>3$rr)$-%tiuTkt{hkDx-q#_$vRiM&PB>TpOUpWrjbo3wK> z%6;ZZ=NFVUosA4*>omQ*@2=m8=Uce@pT(_LPAYE2d!E)Xl;gkZV}4-g`C=C#8ft;f zo7b$IOQl;)wA!EFKkTjlRN>Qm-#FouXW~-&@{i`kUZ{Qh*J-H4=K5>Pn{ET?KdyY@ zi41?(`=IB|hu0_83$5;ioqz4fc{$@PI>;b#O{(Pi_eO(eqFTU>pW zE}Z@ETwIHo%^Rh*IE$jb>+^wB8;hrKM& zaj_k+vT%2Yv%=~>6m*5xR~1x->R=1h!*zxRujs9i{t6vw3QjEu{`see%OX0jngW~v zc-aQc9#KY}QZx%=elN%hD;m72NYS1J74uI9t#4R@NTAF38i%=^I2`td?5m^q>&!gFJeXzlpHFe+6>A zKY;(#db+wmFA_IcaB-@Y=%y6@Na_*yW$ry|2nM!AfUQ?usXXs44#(4Jr}3qc%YO@U z6G%&>wN3doLii({_XU-#utrC_D+jz3QyCPa-=h;Hxzh`OS8}KS{LRUop8xyN8C#3T z{6=9~2G8o{bPg8k<=_Ur^oB*<(!?YR|C%V;lm>mwuYT7_PZ+wtR#lrJwv6pt#UfU) z2;$$1xu|j=DyASKtUjp>F*bPRqEqJ}&v#T8lhPGhA6?+XVm5JEvALyle>-za7ro*# zM*kWLO+ETl@wq_fT%Q@?Y-QV%CLhvooBbo+D}F~xPdmguB0K6uoUa=>gwHxMyseNL zctD~e!*1PR31MemdfJS7D!25Wo5F;eL8?#B#QXW=vD*^sDv$TnbOa3{@;OCz16Jda z6@dKc+Z;xc@Ao&^J};ePos_o#`KZA;%Qq+q`aso<^}$~j?(&+s$u#a;N1tHXv*XLB zMAa~Bp{8fu+U6W}WLeKcKhNawSGLhN~f%y7U7ht1Z_KHkoV#7w5F`le=zD>-OuafS zl)BXJe8T^3Xsv;9$_^kR!*TOOP(SufmR1abU01n)Fmdv;VKW)^ZSPe7t>BCEy7hEV zTz6$1TF|02FG>MY{`LEWwDoJBo?cNiO=l1W{~S~*LpfL1hYKQ}7axn+uynVt@z@B? za`dr)ShHV;#BFSsJHAkT&X}@#MF>2scBO7)`C+{qv2D4Y;m7dj$Ib_M^k5U1e4r() zrwhMyYo7D3?Wi6(@uZA#mXiL5x);>`;Ce&TF)UupEjFNJJZ*mmE^a(%eUeR(jVhk& zeGA&Lz%y^Q;Cp2NYWjYvPl@uCPvDtD$G$-C013Jh-@4da;+uCJ)%S$&%8IGVlV)pI zZneUFrpoOpMI{rnZOg$!s?D|K&4biaDe=NT12qA)6Dth-t%)h#a~(Ldyr~>~%PJ7e z=Em7Ai!LROu)BTAH6t{&L&P;Sx3y}v*#z!?H;zy_V_Wz?uG%U=>{H{9%DF+*=5kkv z%25fkhOiGt73;q|w;1JLi-oyp3+~_MWB&vTfP$Y)ulnCG|LN0{tD3z0=!SV}AW~mj z@pK{xc@wtQVJcx{86pI#{71WiIq=xKE@2tZgOl$Ko45kId`vYy7%s-wz(Tu+)BDkG z#7_gO@5;ZjOnQteCNaTPCSootBKDY9VS4Qoy%V3#`2+~u^O1R)@;=1`#o;U zr`a$22`}s}nk?X^?zZ2{SX7fp6|)_!J3lx|a{XH3abCUr_x(K7OBORP=NNFfk8o~g z+a$CoD3|3KKxaxmkI-%zJ$eoV7k+Rhw>u-D-i>x9MQi+W_kADv%E??~%y%Zi^0 zN%iRnI2w$r^{Mw*FqIcx&9h3AL`LRlt_<_$&eyTuW^H05nkSD$<_HW2sZ-7RDs^sD zPFf8nrvJ_Ue1GCRcKNnNdpHS`gH1;~wZFRJ+#;6K*4K;ZQq?2;@m<7@uOyc&Enh5V z*K7SJG}lSewd?ZJ`R-InQO;Ct&=?ZhJvph;-Lyg6+b@-}J-cx!aX|RS^2w{7CXG?M zG}G)-!<(=0G85{gni?ZbM&bFA!A@H5mL~2JyZRe{8wp(a5)zd7(di{}?F2T!@nJ?n z$nIa$HIbW*pXAZFz(E7kfD8}BQc$(uCl?`1SvNLoDuF5Adf$g(BJA=l=sp<6K2Kw& z($qH+p_93}}#=4_a4MowYmG>i?yFta&rnAvmtJUcec!h*#{V@SZ0Nb^u7`9<&R zTe`Ku2y?dI*bP$abm|D!;P`d*+P`ZUf>pM1mjeFR*q6tur1O}Wys9*mWk(4q^R<9V znVIQ&@0NaE*SVtBM-D9Vm!m_{m4!hpt3!PePl`Zkhtk7TEdw}PYoNgo`uXkr?&Z~x z68Yudhv7y5Fmm#bEM6)$3i|V}#t3C*`R}x=@jQg$gMZiRKgsk=aFP#Hx>~8%0>Sdp z{x!5upXV?@l-4D#l_z~0rEN$i`=T*QBE|Jx(Jy@D%~2N(Tg42UWTHA3LPC2#EgStH zk=b#DS{QjZeWy<)Wl}K+^~2@7>bfoUs}S+GE(Ja!7pa-4QvK!q9{BmJxX6j4ijV#G2RWQ`@rtVQ;fL z5MunlPvJ)dTA{RN_UI}5J)MB)Q^UH~jjj$SESSg{+qoS{shc;n=N|N%xevE-Qwz`2 z&?k$uz1&{^&3NNqLv}8ftvIK-=gXI`7X7?dqwla&knE*tl3#7?1?=gSk0@GUZ909L zWcib52G7WVjv9U6AkJ*O&tQYQ{YJN+10I4{2fF4oyymLOk>(>>w9f}e0WZ!+uwkf0j}q3jRsEd+QXzaU(k+L22FS;Fnv#s%YBNpSRMlrY3$*Jzs(hFPU+}E8rJG z9dF$tPA7C+=}M@!=M}r+=G&$iYZE=9<=qq1*{$3v()2(gJB$r0(Ks4B1y0ZGC<da|`GP3TLAk>86K@%Fm$Xk~o;uA(%XlGh#o+E`jJojP+(F&6+}_p&AGa}hV# z9T&_|Rh*N7jv3Z}-Ug~0rCLLEr$3LaNNzc1hUa}sAEkeuQBiq$8aGkZ58iDyZ8-m+ zFsNgZuQGXJ<>y|hG43{8)6UASy(HfDW(pRvJb!OEJU8fes5z7W>C=?$c1?ZnP<7C4 zO9wqEMcr%pbdHKlG;nZ?+$o>t5%Rt41G%kDnG}*MQtGoK0QQ(xlRj7d*V09YdyE{p zMs%h_=*Hgd0}iv>%l01;Sw?*Qhyv~3*V^K9EJC}?k&VkcNWq1GmjLOm4=9tK@@B(6 zT5DeE`TN`-Vuu+0WX*}a_EL>6oO0cT+s%lPvkG8Gk?!+a=%10$FLw@BA};^^m1au| zWy76Z{=He^==#z9&y|feSJm^k5=`yJVq~?gS3Yf(^H`$YJKA6>dLo0-2f9J6_e$LH z)nBZL0!E%H>an50e4pd$aYwkpxmGOzDDI#9)|!1`(t}M&+>f+t47jYZa+iBiFC7hz z8IKc&+OzF)Eka!>%QI)4Nn;{ESBk98oySuySemHo2gv`JDT0ECnSYI7Jc8?q*_S&y zvDcm+__aR%pWdYsdGJK+3j8Tl`gC04y1gkf6bP6P~O^yE~{Wpr|!vK%FJSF0TOBx^s`Qv-rW`j~)2pb=b20G%>mn!8)_tr}mCfis1 zOHYm8Je4$k-D%A>Wvkcd)NMA@*5KbDSOPjPs8pH0?6y_bSwu}={)3!5$W+Nr?Okz5 zn5piJ$R(W34Ps9?8!fw?8##mt6%kCO&Jgay+l$OT z-t*PAY%f{+|0~fxQm$hu>e^_d)Mv75nkn=T$My5+zLANUBC{U@9X1ar3Sx`hfKq@Q zT>Uiw-PW=&MQ{^0f-UAr9qaCapT>H%l}5?HK(L>*;out*=7%mp@dKKoP4}+y@t<=umpc1R!$!Q}w-z2wZH}EzYOX)LLHu3`E^;P&>=9v=WZp)xN!1p~f z$bLSmVYYUzD$iH?r_BQwYn9O_w__e0dXam&Z<2IR5Ove`Z6^_DvC%eU#4+^8+S&77{+diA6K343%IalYh+~NaC)5?LFxeZQbYm&D@t?D z(`DKHgYC_eonEH=^ILsY`M}W)_MEL>-y>|zJWpz+1F=8q{iPfCB97 zTA%qt*k2Xu@y@}r!`>cYg(v@n>gNwn*Q;+UNVC9PhM9O6M2z~zU?VT61+!Zn11jga$i1%6)mUcOzP!Zr z^cux%{L>ol6*`VAQK(PWz{Y!k@X%dt;H)IabO=$tH=g%n%ue!7$gtW@a#$$-k%ay9 zHoASUn~zs0r6a+NeuxHo&ebmMr|=358^}EO-zYm3<>B{{WsL$dMoWZ2Pjn^^0x70`9BnGk3u^e@YrpVVI+nYOGq~H|owyjq{;qj&6LBBf)Zb zF%K_E&ZIe$x0 zPP!a~3rAKPm^MB9nWg++~wFj^9)E2jI_@;G(%<-8lp**Yo!O8Pve_IyK2FG5$C zifm$%eprEB!?4~5pnh0+^}mQSD|Z#~mH6txsG8Nb!J%%eoDG{$&>qn|Y**YBU5X#L zVTN@go$WEVb`;aKz<0406BpLEhIJhmDG;rbC=aSgXt z^?uJ?#K7?``$qTTu83GCu@x9TTo(}2J^U9vGmf3T;=*3DK$R-d_Z2AXUo(u86Dxfe zjTX=EwIp3xLkpvV_OKZ^yjBYg*|!a0*fNK>VYwv zb%>lM144$B(Ur)LPf!x|mJOP8a5)z~Na{+g7zrj-U+3^s!)w zvA3V92FnVq^H{nyW;#uQbf28QMb7eH{br$~6`!3jKBt>P6oMWO`sQ5(8$Wlk{_oma z16j1*yG>%F>bC0ngf6dy1*8?k{%%-%iSADLuc9`;xVkoI@2fpgTicPQt!l+n6gzH@mzw;wX7MaY)L1iQ3gU%nTC8`C@14Z#UDk>mwpqu~iGBs>;%CUuy>tL318DA*O;* z#oJH8;AADObVc+?Nzs}q>`}P!17|QkvBLTfP!`6s_8@0=GgF-xg;}0#&Pu2&{&=I4_r$jMR-eJrL3V__f-AuJ ztz1hQFv~C2xtr|E(5|`$8??_(9hulP=lT@>z~6ipwmE9r3+Qw|89IP zwa?F(`f|SC{waD*c_I!a_^ihW#mNEYT1lk+EHR`O+7m#Bh$TyY zwHSX*R>NvqqgO+pQWPFLVtDLJ`wq#eGF;`E`Dxnvu@-u#uAR=L5d76&-K` zw&hNkRn1OdZ)_!_xn{o?-#cK%(kNzn>Kv^Si@W9I`-b~5>6WG@)A*SI>bbz@i1Dms zL9qQ~;6T!InZi7^Q0KkKht5NR4ia!j{!d3F8v+H2P*-tkv?f?|0Xi4@R@OUk4h53=ci^lOXgPXqi z$oPQ<2!&nP?B#$dZD`zwA<%tTCC&857OB4K+G0_2Gt)&u*pkcqBG9d11%Lq@#Hm1x zC?aNk4Jxl?-$ALfitQC|be~A3)m{s%V+Gy(vH5UAU{WZnQsp>4hof8O%v(?6u_l^B z#iZ`sMKfsgCd}zTi8fD49$;2C=)~x`;hXJy1?C-7!TrtzbjdS!WU3&{t-%ZGOKXTr zpv?+p(2a=*31@f)T;O8Lzx!%o`&NaHXS}Qb*m@75yLtIVysM8_$Pj;s6aRP4fKb6J z!|yX?iOK#wfE-Iu!Bb3}qb%5dY6%~e64aCHEr*2z>V&8P$5wGWu&)L1gx;zL~ z5*RB1wwis=k{e;X@3Z}%uxFU(-gAj#W+l8_?d*0n{`_6QOHpCAc-d?C;SkPC35qh{ zrVu(OK@7+jb^w-w@i{ihqdWjd)rQJ+w>A$uU}Xt?r{sm~Ea$C4vyd8(BdXP|WhelOl)uZGZUhY+L=yj)q4 z{OYF#8OLX6JPGYjlqoYqPqVro7_QlkSfBU5$jxPmZ5V5%=A6qGj0TOj|Nhn{XbB)Z z-m(>J-?qDD5%evfNBPNe0=1yYSuEDlGHdy}+G^ow^+c6(cYztl7kKQ(FY%b2DgRVp zvZHTgJ?ar098r+1`FWu$D9fnoxxWlA;95d$V7#YKtXQDcH=OJPJml_E;oq*T!$&b1)Z$pLqGwr2?=Tcu5i#--{ySnGE0V7MjLv?Q?&| z+W86doA}~?z~sOXqgJ5zvJgFgp@^<6dJ%{>{#6Q(vZmX8#4+TCj6E0;lh2AH_#;;U z42eHR`EQvO2pH*hl}GC5efruL14l~Q1#4e-O2v(yu4GKO3$My1gFOPkw9O3%S(#ns zmRA5!Z#T#p%G&pYsr$eWu}av9C~lhfxhMRqs2}4l=7hzJBSa{b<6S0WO>MJ~TVZMw zRfDVb*-rK=uwYXwJRly9iDpt2_kmh?r^?0pl=R6W{Y|@~rsx5)z)lIa7Rzpu4gt0L zB+N|(QSTe>rd*o$Z&1T(+HBN03yW!Pz{6N3Kt(cof{<)068N#RB=xI%K!gkF&NRum zEX-6f&^X9wqv|;G30k85){9T)@JL}+^)aNO#Rh@47oTaDCKlWudQL>E#MM|8UrqG9 zU5)LU&h6;){8+`WX$jA{MO@Qv4HTYn+8bS7-a4YwTDe6F+($Xw=5YYA>(|?_sq~$! zX(&XouB5ry7szi7*Sw(*iu5@@YQhu5jcPf02^~>#E`1j4{FS@9;VWk}NC6SLjkNZX z6N$s;BG9@|!qJ!!JQBxX2pI?7J*h4EXWLx> zdl>KOEeA1{N21h18onkA;&^JwG{nKF*C@4@;A8>sx``{)H)vw{28rbX?%OQCME7Zg zh@e9bth~LI4)F1)p)aDGBX_$bV|0dLN~HUk1~ly$l%+o#U;Arf33V~ht@TAHrDuEX zd5Og2=zYvlBr4gXRgWwu#kA*s7)Qj!qLP1I8_R1u-EwX5%fo(2Hp>qyj%1`N@`k64Qn@qz3QQA;s4TV~#PK|~N^h)p&%iZA^_;1vtUR-p| z{*7nr!Ct>nQ(CGQFAGwm7l#knSsu7I#W=Sfid^C*pHgG0>miH7GWsXjY;}aa#6Ha0!(?MzA?d@!8Kv zyBRvSKDcZ+9*1(@5))$W`mxo!w56Cv_|8T?}-%;7)+_aX4#`9WD*Xn+

      >wk8Ci# zIy7Y=u`TliLBfo#`|EHcY5QXRGQV1A*|)4$3$uuOW+<=TMmAJ@ZtYnL+gD4>-HcTIX%1cHFwJES?ytcMFxZ#Gl-ceC!teIe9KY)+}&( zdkFu{xKi#IHsSsb%4!+0u|Wj;n6vN?gVFkDE-CIC3=<&O5r*9Nz_L)ieGE{O!wzYMb9wQre31{5QZj&72{h}rKCf*C7 zc9PHh21-pyReL|R?;Y~U;V$y{l&yuI6RAeU-ec4*)$ys^D|u0)<{*0oGZ}Qo|1f-? z_qgtQ;AKKt{Z7L1RWV3d)p`&VVC0v$pW?`_+_q^X$sU%KCSbCvFRRjj1mS)?Xarie ztw{@VIM#(==z)@4)QT9Rw>@C9uIp>jXZF)_UoXpus+5vGobP{tRX8@-NZU}SV50&_ zg3Mml0d{@_W#I+11Ex&$lC6$~()Y=^jO|A*uX1vJ zt>BNLxGNFpqxB~~K9M`U0h6GTc5tm&GqXdg4Jb8(C^vpF(``AYA9=(YNoOHXq~=YqxS&G%0p>WORUt@8o+KLFjz zvRCWJ8}APH)b-{t@a?r54py*(H#YqKYXT2Wjc#s$4Len1yG8N)kU=pb4Rc2KPN`h_oMsavswDk!Q(_@G3CK=dj ziv__GOcyTO5B@V_wZK_h?)VoNTri|P9s>PkMEmRT=$noz-H!~r|I%W$L9Tl4Z73FiVMs1otc?`!gf*Hd|kvQENo=ujxba;ur7>QGWCA* zA)~)}hhBj;_8HYCrd^I&t9Vmeoak93G752)gO!UX9l@Yt@Yp7IjN|rVp*?H zf1E*PS9@fT4=C9;=!S2F4sH*zYKkBuUOzlh_&&@LoYhV19Efc-n3N6N8W0deq_=#) zQ`=?nX@{h=tr_MUYfrqafYR3sJ3c60*W$(Kk^*YWMdqCZ_k68t?&B6q@NM!Rc&%ql z42FJd$tH{Q)3$lgkfaIph!-*UYoj?hA>yNu?W+-rDP_FZE0Q5ud2g)kvbQ6bF7Qxk zkbwGz;~xjU2;?)u^NqeTD$WV;rZbioF{)x$KTos^+COeoN*LK>{}Cj%bq>YSNy%?6 zG$q?xO=1tKvV|gECqY8PHUb+(I;LO46LsC;p{m^vW&}$lY_D`{Gdn z>m;xl#M*E1nulf}d<1W?Q_^ms&hX)T$Sy<4qD*^y{J6Oo%i-eT7X}HMFkz^0Jq>^{ zY%}TufbfKH56L%HD{m;`z1lrbPCqS&Yx5+UTK8AGZJw2(L^=g7%62}5hD>^&+{^7S zic+9cB6Ez=+IicjYaD&ZK&vrJqNiuQjil0<>RoT~($w9*>o#4?nFCXM&9xGSx@C)q zY@UiY!{0eg;O)yW02?Qs+TKNERX%$lY^iJr&OUw`EBUfpEdh+|S^uE%1%&oQWPXT3Uz_8j@U9gU@@R+Yz&~Q@D z4kaQ0&hM#=M$(unx*3ruUVq?Y;z9yWRQ`+vr9grmdSm99lj3gZX(#9A8DVjwxHw$f z_CCrfC-C)~tfYt=2Lh#K#LgPZ0fEQaX*K>lu*)hJmHAYBrhB}-XmG=Ev+7GXP?qRdnhg#m^)8wWcUD>s&-Z z{nKG3(&~0Gw4u*%Hht*=ch}>|j*`NLK8z4V9U}{4ez$&Gt8Hk$!eE?2&b)FeIUPgW zmDQA#HIA>4-fW7?9RS&EixtS`1PZo7VJ6ggXc^u?S!}2zo`AR6)l=sNocxuAe)t3M z8o?Z==qZL==QdwoY+=C?@85jTy4z*eF{d-lF>2jaB~*vJhO=OJVllmiUw}fwwh6gj zqXa9@S@RE6``*5^tx!t5N52Q=>IIX&)6!1!R7x+%EWU>wi}P6wyxVms z4@>I%p#k-`@lumOXB$!Ck1VkE>aM(lGBro!aOGzM7Z3|7{b$IOnRuJgrB1VTuU1F3 z8Qg(n7(Blf9#7CO8>gOQ(~0U`s-)7yzazn6_60n!9njlBU4&P^xbhsX0W2glOE*F> z*}CJzpNzKoF-FNv_62kv3+T86S+Rn5D012lcaU}H9D+Il`lCP}?9PA#Rf1jyW$knm zhT=P&N?8MC7T+Ug;i>)qLyt&nBfMq(YN)(y*q@Szz8OiLP+vZ6lj-{0xiyW((ljoGw`Ap4S`nq%yRQ*WO= zNj3k>mRmhj;3AUnJR{s(C-vV)tfYX8ZBl02DumR6j{_i!E}u6SYy^lK&3!mKuAX+s zmoQLbs`-gA+7$T9*gY6XXydR(z%Jzs{zphPKp`8Sj#voAEneKbhdrVS@#j*07A--_}-iLXEYg z1&c~R@7g&UuYHPTGToQFPC~ztL}5V(Z_2Ed-%8(jzT`_YUkU%y)b_`D9dac3f1@cU zsA%=WAzO9*=zuu-e1PntGbS4lWgJ??h;my$-dZ^pt@4r%E7dmsQ?e%g|4=yd+4E;B zwBlOxXVvK1Gz?G3PtMA-hh_EShYHXnzW(dDrXlK{jr8=*fxJ2?=11sL8?RlC%wuw_ z>FC*H zk8juMh8GNJbLZWDuwC8_#P6O}N7u5vm{;d9!UxXGY(20V% zVb`Kz>CUd({$mxn%h1;)m}8v`AKNDPc8Ya```WdB&&d~PfZlt2t+s$aC)&2SADjP1 z*TC>m19tN&Kt4Cu#v18hKyLh_Nm6n08&w&&DF92a%BXwIhIs3Bz75z5 z06mbh@WgSg)wSP~{z7n!&<9F%i=Nr&_y|gs?KeIbSeJU2@2vt`X1sV_>nm)@6L#z< zsTfv`9d}*aeJii1hPAO4sVrly^+rcG}pqBQe4CoC|a&r)+ zGrKon&%IUzjx6PICnXfin02;e(rb4F2E&>>c_#1-VQlQc;gh407z_qH3fUu^y6bF> zikk3@00e;*xx4=im?1Q(ZB?udk04P7h{am;&myc%LvSiX5{0*o{zpc{Ura~Vf|f+{D6O?`qevM%O$TAULh}6jFavV?>Wi%HCM}eJApacL=LZ2cKGe#FH05r z^lLYD$w6noj$cQIqSdDO=H~+0!K`4 z&3Np5j-OiS>9kG4hEQB`&Arj{IV@MT^p(gJ5wl+V*Mo~utK$t;cUMX%)0B=$N?5RZ zH6~ZR=WgS`p<-KnxQDFx&AHbK#(~h|oT*k}9DY9zS_<`^z}}PY|4;BQzJkE#OW~5w zCO;Wlc^pj-31y{EkPm`~DF-ZuZAq4E7!P}rTsg$2$3A_bE+C^VK^u0irvRkkPk+l$ zf33?M78~`hU(Dbg3llrSi5;Hoy;r|tIxvDIr&H(??H^M zvVOK?RmKS8>l;h(<-*!Q)9lb9Ea$AeY-xT;K_E1Tg4Rxg+C%6=N;?uaXXbD{5ixkv z#$4{V(-{-ID;@UpHx~9JR1X_EtyjO;sA}s~gw%NjgzU|xP_;ESzcb83q1J=~L_f4g z5wZk+GHgG(G1P$t&q)vPRAes_nJ$7>hEg}1#r0To4S$$r zMX6QQGwW8QPtIze;qkccyKh-_pF{KY0zx+8pb7Y3K3!{r0M>q!n-q`(L0`kSkVMnB zPCckMT)eU#zsd}jdD`84~&J!H;(#4&QRv-(W zY7hC<#KcSoOB;@7FQz8+<%RdP2ocA=x_G@RfiF}!3?9skl6jDku-QtOrsmg=0A z0)wa^v5lMagZnha`?NJec#SKkg7(gTXCU&eo!2X~zNChLV7;&-cx(5ao2gN-fArm= zPG>w|4zuz1-f59G$vA2+%)L~}58DB7A{&<`J!o7FLVgp(N||J3WKw%6#Jf)QRXPNx z@91+EOo;0!}OYMr%V4WQr8_xS3r70H#(AA z0qLb2I(4IA$AhliW<(Ea&INyP{W1?hA#5?S|6qoLbxa$%4rR8Mj>aujOXD$pP2qhD z<<$7<;s#eEt4-a$4WWXGeFG``e2+bjb17Fp*Jr93BJvt&0q%tziWttMt~jrAA{qZK z&jMF2+zJIOTeAadf-2*GREgGq#UGKWBCm|5o`;w&^QI4HqjZ0c`H2qsnUj9&R@NvK`jg`k-S<=bFF&z0_z>{c zQzRP@nRLeXLj~0NlcT6H|GY5|5bq5?`4rbJr>Y=Oby1hyJhv7rAF+@&p6{{TR7F-_ zKMMwQ*)4@@TC!riJCahsF_O?(f}P}LHXdn|>|6JjkY^#9W)^ovt-w;nQ`{Xk zuHy<8%}d>nr3Pq*gzc^n2|0gPSAWQTJmW$WS~tyv5Nev`$Ctx#HA3n*)rvzFfY%&Z zS0J*PA~Q!zL4fp=ZeeN_UU5MSdmr7ZYl)3F`LjJaV!{nMP~gvxT^esvK-kJ8gWF7V zh$FBq1w^DlG#^n=7)^ZPLZ~j>V1JQT_K1Oi(Y2- z*Xe^#%{>LracRd#7jcI{q_rG0%<354@=)=jp_oh%f_RdJdAXchFq=C<9qVtk<{3JE z4}FD3uDXVC{U)!-j8Hc;nhMHp^WKvibx)?5HpHe(7)q%!6_LBL{kkNt-m|UAg(}um zX4jkr!c#!06wM%}#_j-hI27I^TCM2d8RE^#vysKcVeun^g~QdNq$hobi>Nc%2dE^6 zN`bysQvo7hdmNr^^npIt#&)H$d`cw}%^-ss&gcT~lWXn~1KU-8T}QJN5Axq~hEBzD z#4E#8QY57c@ZGaEyE8fBGi<)AO=;7M)iGg`=TyP0C6(a2hY?eFg}Iz*Y}@hC{jPc!U6-$1OgUh)Ll(i>hkZc zaYRbL`)Ey+?R@!u>3FW?{Sy9Fh*-r4F&4ZA^6aKB!A!+7kPetBtF1~M-Y&!PEU4k98o#dMccuO>FSn?q&_?(0#QGFATf{N}J*?*= ziIC1|h97ddsll}dFuirQ%d!MOC=snJ(k6JCwjzm=Ul-3`<#vqw#&5=3r@S;y}fx%UhP}qE4^g%&C%_aZKV6LZq1;*)NLdS(!JumH#@%8smIU! z%LG{>cEp-$brn+LvVLT5E@yyy{0^yK3fD|1M2I;yU-1hM(r(ffR;^+!dWal?RJK-1 z;i@L?^Ss2e{jw~1+t~Nem$YLw{kT?wB81^gM(1)=8BrtFJVCFvZ)xFw1DMgx$-!J| zcoknj2hu`D4v-cCqpau$Xj)d|$~?klhkmb$jXHTY?JXdqoH%#(H74gUtX#dOF#-KI z-w_%oq!t0uAM)GGw4+BO2dccsM;!VloK;eMyDNV(C$-??S_n{cz=MFj=#M3RoXxo% zQBTTbJWZ7YQeY((soA7!Xp0HLbVqE6c?W4UaSz*$EShEeiCWsu5ZQB?AF6o}AY@nT zCb+Eo#or{4!+#{JdO~kgyAqI5>y@H*!m)nCunW=J0G6VEd_AzZVpJEeW!$ma;*CA| z@zs?Lz8XX^L~lqH*mP3lC(E;6i3pPKjF18|B{e^hLdB@L4t}yLgu~gKm>WSm@Pm*}YgK9d$T+ zu|iK2JaHS6Zl!?%#X$(Or_*q159fV;9Mk>bf8kWzlTF;G0oAeZ2{fx!*TY6Oad$?J zc6vUOsxbV)(T7Pkq0h#ZUr4JUD5p+HbQw^nh7FkqW@Z#{GjxBQBc}@4{utvcs9|@i zRbF0bmr~H_)*OSdVnlbsoNX`OwP)tlVql+a^t|*pL)B?Y#_vTIkk~%BymMizE8SUw z<~6u_Pi&?=ciENSRM80ou!~8|%C}9qim&BM@>-u_q)@qmBD4ArUShn3j4-^=+0r#t zU0j`a09elhHg18;^xi+hee6_a34gz{WVLyc5+Egb1YJfKRq&A#d}J;|mMFH;Ez3dEg>h?g zUqp@klS^Z(M97EM`&}sC`!a<%4p&{ihh*Y|PdZ8xboCKW>Nq<}3W=35u;8B$>4;23 znM9aJ`_dw1be*F*;?5h%WUxK$lw0*({Fp-anbn6gXG|@Zj%YQ%kOycayu}d!aF7wr z(`V+LOt@j5SrazP>;OnG8<|(XaKjcBYLQZH1N~&UMt-thC#X zRK7xP(iHQo@r{CBt2Dok{IDH*+K65*C;NE zrJp;}&ITP$-K6qnlTj-|H_vq@AX{cbvGo#&Uf6^3vBu+t6`YHL>5gNwR_#O&^mgW7 zUCBdjl4c{6)2BQ##)u=yudp{xdO@#_P!>`rY!0H@+pWe~1VA!#+fq2g@!;gGecQKF z7uCj$n+j+jl-eYKQey-R{I<`#S!OD%ac7if>AjWm#{G7AlAkO5aegn=aH6;Np4o`p z2rH?3j8x#8`$Cp$u-Ae{%iP0MsEb34<=)}$6dNOfB8PigzVyoqJ5ydK?rmDaDtr8l zaTB=9Uo{P~%X#BV%a^fSyMtqfF*Dh+kCf?@;jc7Ihz5p8wK*1+aJWM%-k0Mr#gYmI z1&ej65~?SnbXtTjgsmA(O*kkVIi;j-Yq}(Q?Vc;9OeRfY$7n+J!xZ0iRLhVRLRyb^ z)COqGrd`VJM6Fo!9;+{|mu5~phGOxp@G#?D6_8TTnw(~C|1``0rP0aGH@nXtieg;C ztzEoa#W>Wh%EraQWB<%X4kriqh2S70u$zZg3>k%6sWepnOld&U&u&KpSU zOB1$+b({gihri@YlG*x#QQm`Jh=C&oiXpwI??bM!kM0|Kq_b-;OQypA&VF1JybbT$ z8Xp^8|M|ioB)9(1Ou|n5k`e66tvUPx0|%$w+H-R>it(dshW2e6r7`E*uKj5Z?)lqh- zDMwJ3w!xy#(+=cUFL)Lo@Ya!EKmd262RtLP^$>&FGlK$hYNkEW9xM1g0$X~+ih8b3 zgj~xHaQi)%-{9&Wq;`&(;~&$v46HG$8T8dncOp}iqMtI+7n=NqpGAM7(^SA$*ggpE zg9QMpKqB6`=NB0^afO|h^QPW`G>mO|;3L&j<0ChdA&c49GA5VBpj)@DnrRKoj;tS# zom`d~;rd_o-50w6JR~_;`%m)?KJc&|b#KNI`pDlZme{K&#&TyTe7D7Q{hsiC%6gft ze}~*!c42!zGE_FlsX3V2Tbi(vd%1j0nZpV^5m;uHHWuT2d;Q3D8VE@bKb(!EhX@_X zQ|+#}8)ez;JHjlA1xwJ)Pb1cJp_97|Et{8G|5N_@g2Snni)6iz1vlEv3Q70c zN+C4PBldu1f{=gMa~bx%0V1%KhKdV^h=~(22X8W_lYkONb{4MCq^ofX_Sqf4s{`X1 zDorGzDAd6E4lD5D#+HKcc}?2&%Mh!FzgZ?%KTu7D-`!$ruiLfF!liN>&2z)RU7!By zg02z#XeTm5i7WMK6Br3_Gs|XK8R-&rn40wZxN$St51Tmw-vw?ikwE0T*Bz!dvXw$X zA5-e;P5y2!37`4$YAogKG3o9O+R=`Mv}HF5Xu$_i6H##DcJllq%IH)PZL zw&a~ir;HRhy)efSn&;ZEwafVfP*Ix1?t7#+Cw+LP_%QX$Y#(>s?xGp#-7L>D3M#Q0 zcaYleG`AUWLjd24E1Bp8J?_=6`6ieH81wfi{MADKE~>G{CN9se=1|C38=J3?YspNg zY{~us7g^9{W3wk@_Q>bEo8Hw`8u~ktaS4c`$G^rw3X@T4<2;urOD^w+Ko&sAz-5G` zz+)_vm(pY_MTq^w-%#Oorx}gyTcny3OFTL7_6OdTFa4Boo}_Y;&5w<73W*o6 z5}ui{V35#(8#J?)$S}gn0laY+Thz36Qg>enjgSj>ZvnJt6aIlpX9Foto^RAtz|2T} zG%LLqct3H-2u>;Vj$7~A!}0sK=1M3c4i9^^^M0CW*t&RL|I=dS5VCodEO)<^`zhF! zj+56sx{yLXvf(juJGg=@S6CoXdy?PKo`kb)4GsIZBpR9PCX*`j9jLS(>?{$4jgyWQZ$T5jUG)gR9$TtC;-` zw;^^fXGK7wAjeC(l&F&a&yxo3hZ+=(6%LKmW~=8~&ioqty=-%p`eOC(xwrVn!y+>( zS7oJeCOwK_)PJd5q|3`Fs2Ynkwf_?AJ*0iIw@j1%}9s z9tUTsC8I=yZeG5PFlY_ichP`)2?8NF$1;?O?M1*D!nC4S2`7MwZ+<$&#j$vT*DHNH z{@+~X`ZezT4NOmeITK z7J$?HHSq^#0=AsxKN#gTKEaxs83(TbAC8%CA9y}n2M~%8q?)JecIy>{BoJu(o9AezjZE zWL%lQt_vGGu-Lqlf}e_jN8`G``RM4`6^{1>y~s-ibsstrGLm|N=+~7r(TDc0R4cjw zA&b-L8X=o0rKqxlijY?NWarA!k|vi{jovB~)YwqD`QGl_-%mnrw>IjUCWBFZO}g@B zgBxCXPbT1(2TYB7D)bT>3RcD{2rC{I^89hvXXAzvTbk@nNskX$%9;}a(;l~PVLRqvp`&{TH=03#KoV8CtK16nuURGL>8TvoGc%5FNtkPx z*K6q&3a?l-=}y7MLS$R@WTFQ9X)hC633tS@M<&je#@wiH)W;GN3>%&r9zLKWOa0dD z18Rm}DEMFwyh`p>O6ctHYo#*awJ&A?BE()XS$uswM3$-#OjEgPf(W|2-hYG}0Wp|7 zLEO2SeS;$t)ee12D)*FI`PQ$xPGwAT@9$im{#bEu(Mo=bmsn<=ynzevh(C7#xEiWLM zKiSOTsel_$@zg9)6ZfZ^IqD(jfIC6I<|BSz$?Rin)g1U$)uc_xr`ePNwR+he+m+V* zb*v9y6Fu<6mfbS)srE9!l+MnE>+1f---yHS+Rcm?MRI*%ZqW<^O5DQ$VNtR|+gCbx zBvmBi2>K`2@kUMEbE_>o5Fity>+skkk4QGk5OH9VnF0{50fj>E$QBR^H)k&M^~l8K zz!bCULpzfg0F&q{(x^`<37;p@|M)v$+p9D~ZNud?bC;mvoXLK%YE$>uL2?VRmDv>p z*zd#gr6bClrgi-*wrLX*Q~K*~Gyzs(9ho1h)2#?`oFHu|$&=CgLr3Q1B$jTG3V#2G zhg_!FhS={1%RSR(FkdZ2da}yk6bTb`{)IMG0m5!3bQ^VXDHb zztb|303pL|XnhWTVjCJ{ps=`(Z+j5$+_tOaPZ}} z&Px{!ysWcH1|#hg%?)B@13Jwyrzzi|FHJ~i{o)=n=2Y26@gI}Ot4lbob-ynE7nA-M zhJ+%_a~P256QhgUOTO&2r&JWM=jI671t8~_;=8(X*S605;U39!PUWke>{E}+^X>_L zHLf-Kb!6-J|7q+!V)*|Z_!x>Q-Vvq1Eljq`+aE*r{O9bOuN&)D64snsHAZ>^;ccW>=4v7f0uZ_ zbJB!v!lluj<%rP11JEVc>-CZS#gjr=y7cUP^^7#(?P7I~WP)fwVGHF4;4#+zl z-Al*T(%TBykZIq6ih7k8rtim+3vNnu`3}8xZ909g5MBSl?*+DNiL$KP9TXg^TKNG< z60P-FR{j(@n`xIL4&DpzNL@_XZ~(r|`YjFkwb=Eazf576v z`_YnkkCIR><%cK9^zXx*=w}S*vvjMN7WNybYZ15MAT|5S;bA69T?z5(ZmfgCs2-}X zyZk@CN4+gz)jhf;0K7|gaW;G%7~|RmBbf$8V{e;A<(%EGiriDE$kyE9)o*s{g!LeF zOee$Z=s$$7l0EAT^aM~nw~*01#y;Z|dS9LJy=nAtD3yG|@h?e~7;FgCp@2dTRScqi zZ=zJ!r=~Wu;n)y;bNO(CQ%Xe&@o#qr#)EjqU7M93d7(q{~n5^gJ$Z)gI1l%SPiGu2!ZA z7}5Evea8-y_hL(tX2J`WPUKKXxfo| zPYV6tn^mVzAhz5}zao^Rr)_{%qZdw`AIHC-htJxgc517}JH@Nw*Su8<=Cmn(eg!od z68){FU?4pSUwbKT-@IdTAfo6bf^X*r(oE;8EE)nT|21)oEj3n_&a~MJ86F?)-6e_U z*Dg`{M)4Y5dV`(zt{28U^y%2{8ygNBM+QJ`sypszGNQJ<54e+A=O~= zc}Auj%8>_~r%7r`_id|RlcM7HuMqDO==zX&u7_N-*AGHDO4wHQLNa^4;9mGMWD1=r zEbnr1QHHy*puHeQGoTNcZ8}pJQ|7z%035kb&g>4Qk3sXgNVw(lY_eiBoe00rz1Y;w z8e$p+8O$ffE2=Y=L@BZs*G>wR>C&tArawSDx;<}xtY!UgV2FUUt|9_JCO38_WdP3c#5X1l8 z@2&fu&Un>L-ob5ghrc!jHm8b=UX(pxIR7)+wk=JhIS_odapIRNj`4rKr8cq(Xvf>~ z%}L%SL$KB+gqQW-_N~B%5}Rv^xXWVsx<5PUCTNaHf92(05mq59SqoA+;5Ap34d9XN z?I$WHJSp_1uMr5pEs0K;;r4xDfFWg3wH9yHmweRzb#Q&fUn9rRI>vx1*(0pMu6jSN zcI@v~#b47CQ5{syzpwPWPx{y>%JIM8$di-0lK;b6tr?<&y7E7_jFPg6nLXp?t=1_+ z_ltd|U4Qj^H*dB(70Zj7_Vo)T6(uzcO%hsmEa?tJ^Dv7<7a4{1BrD~e*)C-ykWueya2pY z4V`eXp(eKfikO;EH;>cFS!$BiiBHqwBZR9@;C<;NS6c^w9<#nnQKp)JDjIOGl&wf@ z)A4<+j`Bdsj&Grd$#99vNd*qQ4g~FYGTgMj^CL=$2f#HpW9mu_rcJ#)2r(uo0#1r? zc)Co3vAzbU>rS=j|2zzdH$o3Z{@Tu{E&Lm$&=V#a%@j^YF2Vo8X6wSG#G_fG)HmlC z;IdW)5%i-Ds%wb$PbJVZ^!S-ziqBbl=r*SmUDdr>v^N&!;| z*r0WBJ=-ur`!-LEWhVc6X>~Xw)ziK^HaY|2HE_dP>#0M8OBNE!UQ=04kPIjNbdiX| zM)%zB3&`Y|B8eU)N$wQQCONzBXOK4>AarQL9A7UFas5t@JKZCnmVpc(`@c%vQm{38 zMNA}2{e-$r8K7)<;O5Jw6EPQyHY4w>t%8%PFDJrkBJG+c``&0B2DC@@&K*y#dKwU{ zGCKgtp+P9WMGB|bqnQ)+q#H_pU#CDNt5R1SGS~g+a(lofe58_2fq)_9@56*HcIRl$ z(b>NzS9suB6-7NbwJT|`yR5Fny@Y)cI@+I0&E)-tIFes4_cx>;79Ab_2e^grfL3_& z!zJ^^S_MMNjoR}6b}G@OyV0~G3FfpVtJ%WkiQ}H5Mb@+>t{^&SFz zDQaijk*6oX{vJ0zCt?E{76F-;jShQl921d@Z=8H}MOVG0t|cM33*v)*taU9&swV3U7=lXWV86|qPoX8x(^i(-b zWj6fX?uaN4++dlH4?b1dDX??yz_xH%^*r3@Z|578&BzKT)wT=Kt3T*6dA>F_^8(raH>9`Sh_0`V_LWRKu8rtA&~<>W3q?zQ_X~n; z8C`pr(QhWVDXzNXAr}zH(F3&$MUdY&3_FgfCX~?1--Pvp<8Ky{D5>)R5~u>L5!^irGv3ckg`=F$?@w)+B&WE^ z=05N1Nm@C*0&&f8EOhzG(JpHdq^WhTMviR3V9F@%F}ZIzveC(_&%dL3;IkP4`+aad zwV%55cMyVk$6Um@$olO|xz`CZy2Ih>896z!J}Q6*&h%r4={VvjtE0Eptl!T{n$bj7 zEV``r9Q$%Ot4PomBk~zm&TOPLdBAE>NO6Xp!8PZ^zFtgSFXlZAC4+7}s?E#-dcNrldWC@MR6$P$p?9x|e06Omdnl{7 zslhN8$^hf0=IlL+^N+M!Rkm6KTNlwCYLc0wqnYmiSxP^dBp5&h|J0yCiGw1yX{zY z^3Hm540NMmU)-YUB*;Z?-+OqLEZta!IajxC{Zb5A9k?vq(o%vk&fg+idNOVOQJO6G z8!K<*pEm)DuS9$^5O!#vu~^{rG_~!}^C|P0vj^FQW;&~laO&&|p@qGA2w_-Tq;Jb1 zrPaS5Mx6)I4EW%PwEY;r9>OO072IeheqV5b= zXu(bvv_=mhYW~1>e!||gGi@w>KT>edhu+C++Z=9cKA{%P>%1DGy=F>2>|R`Oep3jP zg)M#2AD&Zu^$=`1JI)QijNep@D|XPEuWS1I{nO3uu}}=lkP{H$+z$8Nos6$>UjAOo z0u&=SCRNQD|FdC+V%OewMnITU>C-~Hbgg!BAUqX^^m88n3M5jtMFkgjmuA03y`A8u zsx_2Ra^c>#`k>M5JvUk4_Kygy{_MS1H~Pu_yb|7vFC4wfe`PO;g?ZOf65M zD`Wdjat)LXxZP-D4_ZCH6$D#9{O=|?Z;aw(VGw=q8l)^}mOK|!4*tD5%orB5Z~^m> z2bd-dQ*`+Z_h#v@EU=#gS4I0P4X`d~ln01Tm&oYOJ34+t`i<=C0z(LtjD>J+@5SFi zb~7qnEWrGhdIia!*0bYXRnTTfuVGGDu%D9{u*2`LSJB&N;^#E8&rBo_aG=%E>x2`= z>Dx2?c1ER~1vsaUpHfov>6!jKqteI%?1a^~=<&f)`==d!X68zyfRnrN64bo@ia(gn zh|7rHObZz!3y8em6Yjf`;EU6b2rlaEIS@Y&P-$fwNZ86t={lrb_@NS( zakxSCUY!+y)X4!lESDTTTMCIX*6{ah0JIxmGwj%<06Y)xHee788WdEmpynLdYW8JFq zz5ZT|PP2wl2v(q+ThsWrHwY#e|9nLsf5{E3lN8ADEKlj3Ftq*P!>cmV&GN`~p=ma+ z@{X7EJ(+t4!ryt6VW3WLYC5*}EA3a(1}=2@JsK{>Hpo22T6Nt~SD{WcCL*))(#eTN zS^KSx1>u<+ds>G03y6xkmCMfT+@OT#!@ZHYHM`Fgfn?4iFcfw*?Z|BQMh>?5ZRO!` zzkXlD<()*a>2D#zsW{uo^Cvn1*)_h(r6MgtMVV9O1Xl&7rZze%JnYSU~fN zM;y=OE<8fi=B6M%qNxl_yogU|p0TSC+yXVpuxiC(xONj}C_>K4S9j+{D_X$AD_u zb<4aj&&^?G9=Qy}8r*A-7>Mdmz&Yq>XIb8E9@C%flNlBD#m=8~q%H}5uAA1&mdad= zX-k;AB;{L3Oa6T^Lf?A`Y-3jp65pAa4W)3Q^o(yzgPC!j3yN%V%Z#OnDp zvP@f(%mHZh17uhnJYox9s{VT!rTbU) zoIpT1Si%*SyJy!e*XteoNpWp5EV00~eD^42?Uq$i!PaGGWk72&CNR)*xZi*F+qj%Y zh!*q7kLdAu`xW=T^QHFEUj>i9Ml3isn@@2HYQcwV19>swi_Y-OWD zC?CL4z-Zd8+~5mt9LWb~U85^0ebzyaR{W_T4;fDB=^GSg@Yn?+tgT z#N2Y_&tH~ab)w84v$&Sg;$#^V&NEG;j z3trI`yeIEAoQjyVQ{#Xg*`)Qg^8-EW3TlMD3(R&j-iZ%;2Ai{zn(lv5+clEylKE>?8=0D+ee#hxo=3~)%K7b7=uU?v}R1aTj>=@eTs7zy#!Wx$zn@6 zSm#1n@{Wo=et z)r6V4WhC1&-3H!cZubk=P8i@fs4s9`wgSs1E0vy1S@|_p%1tT^YE1R74?raRC2-4l ziSh<$R0O&739?!rCHoM+?J!|lH>G%{2#9DdG9mVn%P^*ak#Ge8Ve&twh)hCxkz?ZbRC zBHX`v#`3w(CfpK7VFWYxhgUsZ^5YR;Ji0TVDNJwiTn#7(V5$AB8jdmNJyCWcVQIzD zdOm~TWiHA=b)xcl5$QQ4$ZK?B)R1#t3&L|AI~g{weFK@v0T?!sR9lIteqz*SKOFSj z$TO+pkCC-mpyAARr0f~oV`sG zz7NpYuWV;*^i$`>!cv_1+s3)6a)-8rc#X3jBbvs$1eb|#Q6reaqX;!QH}1Y?4_iWj z?>-p~iS(0mqfssA9G%oE_ubAZr`>c8gx8^ehRqrq;=k#CCbc|7DBT-?<<@iwkmws+ zB88v;(>HPueqtB1oCwnEdK%#7PYK{F+gs50~9Js+} zp8FDMsC?hYBl4rQPTEG~B^2{i)+~qi-$AA#z1ouzy zxig>%`Tl?XBssb5Lyk}TY(Lvgerg)~MEU6%F#&g`smrICmOY49cBIW^kswh&G3TmbqD(spkD5i> z%{%Q`EO`Yxm+k@iIbiAsd9Sw7GgfdGAQ|lMsYj`Le-{>CS6{ZO=;*Q?wX^ZvUknk5 zGTH@MyqH=NMrfr*n59eo~JQ*el$+?_JOFOehn0!#F#Mflu`^%*ahqnU;qNvI>A zRx!EA+LY*oJF2jXg=jyXA{AuY*-?@?q$CurGfd(b4T+LyEF>F#nlK&MPvqWXmrm(7 z=a2!YU_tuXIzBqiJ5hU|t!|yg0l|K0<;@1GxaEBZLa=-pYz4Q~q3!peEmIpgmn%@H zvG1b3HWmWtaTl!PNZZXI^p%9>zAM=J`e360KF0NooMj5Udkl@*9 zEVaV0nKIMyk?~V8yUKNryCbK~S;vDWknIxXB<=Yo3xH=1Je-}8-xA90b+<}%KxN9R zvs&Vx5*G5cV3_WER^dyt46;KzNQ)7{fkzF-%m&)eSR?Q2_rLH`F zl3`DGU&m&vk4M95I>$?QE7QT2*cVgT`&-TfA19QD;l!-qnkcSAqek;E&_hg)H#_Vl z!W&UN&I!wGR5am(IT2u_Sxg>%wd5s*uwCqB`lqSNzdNsvwO8wqF zFe8<{qDdVUB#$u-ZjxJcOWnLIU?GDZF>sYcM^&(o@t9q{Hq5Zvz0UM5(0muJ)oVJn z2Ym|IZMIa+4UI-OvY?H8dI+LwVo%|gj<1iR1oN}uB~h?(D$au)W4Wm+^@@yqd%YY% z_Yn;AJ#Y!4zY))Xhguz3Ri`G4QgNh*M`rkxzm{DVz)L-ig~u3{-(klN1r&x zv{-VaMH}m9f^`tV3((c(W`nZ6qm2Rs)dAvoAxxD%v@pkF)2C<`FS^kD~t~Q9-gZ+7!Mm_G*#UZa_XcvKB)26DCs5q~)JAMyDI5j+W`m&X$ zkSo}P*F)Zd!R{#g*L9qhF(m|KQ$(qbU@JYJRm{hti1bUZjWCgMmIJ2hrb&dM!funKKXho zP|c!NM0*lhMRvSdBsx;xuT6>Q(a-OPP0}~zX!h`AdO3VduH?qM?Vf)xysJ^JO|c^A zHE$u!Wta(|$1me#fO%AQeN{r*2m9TxN2cB$B~hcu=!&=eenveszPTHU0nBG|sTk%I#3iDGsGq0N9Tg zWAuO?z5{jYtH~@=ty>A>vXbp4av|qWKG)2Pp*X)Te)zf-#GRN=epwC2I!DB7rHz)k z7i82_!5uLsy(d8)@g3;Z61?rhDS$ZkQ*F_B`FR+7H&wOhk0H>VhL~!%NeQ8$Fo7Ig zc-Ase1bC2om%m*5gWVP6Fml{^;tX+CD@R$`h@ z82Qi^S-%c(E(9bRsR9tsl2=-96$+&wamLIczMA_0BN?pRrXsAA+x>|>MTFZ>xb@$M zlO`~R{2da}s$RGHeF49htBqGN$|Q5xJ5NO@b~P#V0r+RrIqi!6u=mVl&ppAIm_S~M zDE;0&k|E*w0*8WtrP|=NXfDL8C)b4M{5{Bm`Xf)Vu%-Kb%{>#T_BGy{r@^(0n52~w zP{^A6D3)@=e3uSJ)jhXrH}1I5+VN;ntS5QEZ_Ui;JKVCxawn(Xe2tEkLoKn- zlQt`V_JY1$VY3IKI<+%R)sEp_Rf(V!`eZiPNah$ zm`;@k6toB!JvPKIaBP0gk4#w=S-&+jVxbx-fBbKBcZY3u9Cj<=17-a96>ngb8{?3^ z(G-y_X5uLv)8DZ7UK@0)m7*duZu3fP8gLn4`qA|F)@s8#W#(FWZZnb==K#$;fSe^Z z^Z)W;%1-k(Z?TLv@U%P_s+35fl}EUN1wVB!-00JmnI>l+_F_F4O9H~gRQ&7#<3-?! zl;V}PDfw1sJ#L?Ba-)#iaPyy%hJZ+m-c0T7H=CdH(4MR8Y<^;4P;e8o>yx2msAn=g zSitBsKws{|3QI#7Yo*`WDO~~oF4ILOm)@-ZCW(?g6BQBM8P>*{R@+S@!|tzTkVs?c zhh?YVm!z%Fkg~-{mp-re0{6ckq4rY!vJz_`8dZeuNLz zfaYBHZlA#(-YSLYK`ql z;KB39cmP>(J55LGB<>go2s`DzkxlBfuicB-JN*QxBd#420AZBp5KBrRV>sltMmk0T zu@DQv>I>R@Q+jafLhW{W2pU$;0YAS|XSiOcyN)ziPY4M;bWv4%EQ@e%ghNl+?h|>^NhHxz z{fKeWaK;-Cwxz*zk`G%UK`1oLa4Ut1zPzU~_exFUh?oqH6P%6VG& z&eQHI=UFW?HO!2uprr5un}&rFjf^kB)`ogU0EVaT**ncXlv8mxM;-(-t>E|-0*1jkcQC5+oBzHRp86}HonYFpH>Efxyut@WG1U+#oEpcwa#!Aq;qP{`tF(R>7M40JL}+R8fpURVUf zjf8?{N5$qz=BiSj7=>Lxd0}fa?gJ)@Kh*BeDC1njk04N2p<5HqH55KHN)HzJS<(Yl znhVBuCpxK6sR4HIGvn@ff}$&{XTq3J_Ue*ZCJoM?d+K|G+OxC%uIvl9LDSeb*`0J_F2c+ zX2@K^ix*@40(F+FBO$JVu6thV>W{4#?zEJC)LrC#ob*NO`q5>rmo9?M?;pIV_;Shm zX_7UpI>lH1o#I$=5PeB`lcZus!s6$s7)$|84FmCT)DpKEnMuPzzu)QS1~isQmrj+R zlT=em@AKvpx2fRy{Q9zgKd-|r2bK0OZ-G@A`6ll?8n1IA#U0!OLl2`+Pi}E_yHgXi zM6(pU?SAUMp3q2sw-2JcWuj@HYxRc2evyc{T=ut^x!?ZYM=iT2B3fjJRCK|`{5ok* zhmoOp*>+48<$m+Iim%jIcn?KwQRjuts73eCqX~WnHldoUuDZPUMuXm76^aWKVx{!m zt1Ic`V%2vS8oA2(}?Q^_uJYJMfBOd))xIxnUPdH74<{v>`($!wB{B zpfmR+roz{;>5UMmzELj!5X)TLVal1r>lTfkGaA8b+x6?%=fCztgp>=;Tgoshib=6R z#{Hd{`5r1)h`f0oAJ6yep~ckBnZGSSjWmzywFdKFS$7+)by*@1;j}fj-hLpS_U z7~CuV&gdO>F}ERw9nqax;f_iPW2|U0yu<6C8^-@G`Ce9&G~Aw~u0R zO4Sfwz)zwkB6mNwd(Ui(*bUF{*eH^amSvgg*%|w@$CLZMhX8`*=(Z$%)J}gs>D!q- z#1Q}QY}%bHg$3!R>^I5k%AcM&@3?r2y=!>8$y-}u1JF+v=yojv!JqRY>hBFYFu?&A z6YCFW*et$$f^(zPTU^)oFTPm1zqL?Pt-Z9lI5z`ZytHu3UQ?C5-5cjuT6_DWf1lge z?M?SCXYCkwXh(*Oi)b8;q#l&~ie1&RfbPk%%L00000002z@0000000000004>t00000004Layj49*13?ho z#Gry7_ydGQEd2+9m6ZXpP(f4O575qDu+~oPEUdIhr54)T*=uK^*x8y7FgbVMPG;cY zv5|lWSu*!#-prew-K#j~PW*4u|D2m}t~`f-C9Hlau;+pAlz#^JM;@N5{=nV^-p!q> z;NLayapkMx?U-L$_ni;&rRvSV?-$Y2MSQ0)-+%jGqMm$cJt@71&>Q+2 z`+xMuer+SZto>>tzNhu2@O#AD{$C*8Pnq<8RK7Lv**tN+QE{Hv)c$b(RQv<=NB2|q zt4{iQu($NQb$?(t^}IcTudVaE0^ItY!Zp9_&oub@y5C>m^In2y!2KdN_h$)sV2$Vd z8S%!K0r!iP1&uL?f9PgIZavCa1f>zf6i)!RY=rhkU;Pv9F` z?-cNx!g?FPi_Zt^Yg2y47r(SAw0~3aHF#S->+kRJHV+YBMZDc7 zXQXc*xb-@YHI{H%xlYv8lih1&0NYPk%uI00000002z@0000000000004&q00000004Layj49*13?g- z#Gry7_ydF}mi`05Mk^JuP(iKk4_I0Y_I6rYSZNU(74!$#*=uJZ*x8y7Fn8|0-J5|2 z$0h^}+;WpQZ)V=?>|R4e&fPQV9+3%=`W)VBSlv=#&jUZGm4EnG;eR)IX&(ab6(SA1 z-2xxicuo8}=GKsJ1$KL2|4+pGEy{eUdNag#OVrZ?zgwB_zx}UKPcg8bl-^V5_5BU~ zKO3@N`{38LUoG(aTHmPnGveEPTp_-j!ni-2kM%Nt1ALpWVR4>M-j7tg40_xW>re4r zXX7vIkLrv2#eaJG(6^`OtqZ%Q=S}%B{|lmbbiP-qzbSkg{9O0@2Yi<$#?NB)rOkSm zf%~e$`F;c6;xYdfxF-ewci5Y%7iRIGdbz%)r;6Pt+K(8IZN5KP-z?%;y=@d=`ez9L z2EL>9P65BKtoI0b_58EG4&`Tj5%KK2bHCZ&`W5Dn=YKK9U!Z)}-w==aHV*+`2jA|K zOVW1?-1@KaK5D3k=YjKazgSq_21=X{p`OD zf9vlf{Ovwx`~$en&l33deNEx2FYZq&Ukc}ZYp7>S^uG0001Zob8=aZ`)Q9h2Q%t2)%E_p+r#xoB+1vv~H7aR>C#~g2Ip^ zCKX~)E=6}6py+R3l5#D@R(W_vEbqNQ-&)BUT@LS=nLG1QIr(&(UoEb^biPWS_ok<> zgRf`LR`c7d>+7CZzV~aAZI+Wp5=F&-K+oEzTmydmaD}3Vf(Tt@iTem zduMmcn}s)ue9w>jLC_C;iM`pk-m7Jvco&OhUi@wE#aEtp@+tXzb-P}s`Q~bqtL|#>kPUvuwZ^6u*JRfU<~mQ(ZQ9Zv<&)dMZ9; z5b5UabVABTkZ#Hi6mTYyZZ2o~X7d$g7Kx|0KSCKq+DWHxFDQdZ zIYl%-<-$2qPPv7+`yC+ZOs40rzN0Kc;hde4At*r7Ii(lbKslr%k#JsJOfLRSSwzA) zUo8slTx9c2LfJ*iIi1daUVg|an@Bw8GP}E8E%Q8CPe0?)ZZYZ-zO4YRwxobyaDia%*&j+x2dwapT6Um58 zlmn!p@}jxGIY9EM3M1~`43U6}3V~bYuu=KOIdh2AQ>IEzkVB-O$#im=QWhIYhrDnk zog%(XlV9kpF>H{Hcn2U2Rd=4eO-M%No#zgILnNc~vnh2pMG`8M&aE(n35ZMDX6l^#rP0O z=#nkCM-4=Xrel}jGAO2^0woC!j$VLL`Xu4fD|DO6?1#(9XFM$)^m$+*u%Qlz=!-HtHmh4gDCNgNob3NiuHG zkE;#qd;ePj0o7|?zI6Wuc{WcsTaaK668OERu<~J@t&+u4GfyuMp2#$CfcTBlAvx#t zk(?EPfcQ|+JR%@|gQAigMEgyWBI{5jYXvAEJ`%P96~I$omKE?DF%s-O!juF_3qVRj zfeS!RLct3_PJ#ypASt0F1|Tj$BLk3@;0N*oc?mi<3S=ed`ME$^f*zm?j1Nc9<@ZprEq||K$?P| z*$bp8ltX)gOhwtS;g#P6tspljW-E9aKpvEY#a zfq;dA2@ptF@KAt2!h)s(1R@qHEI=S;LDxGFvQSR(1)>)G7+)Z4q0v2LEy_p7_;3n& z3+*&tAb7!!^93Ro^gLf6a>4h_0fG1hjSNT=`hsKz1o9UeXh0x=p`Zo?LKq5c zKp=-fa{~f73{__rf*3S8Adth@a*(`6A&kKz1Ojmko*@uOWAG4xKpsOw5eS4bwhu4z zw+f;eJf9$t%|L*{0h35m)ibN;@(&^l4|Kx3i(;*}dsg~?ntAx<{`RX6uVf#&px3fjU8@#z z(m&*^zuSYmj*tZ&+%*p!^5E_OXn_ZJXMBe|IJC)wyUBn<9vs``!Lf^ba97dV;KAe4 znxQyoQ!d{1c^&fL@VL;^axOkDq!{wxaRo%nndG?A%8-hW6Hd$3OyHmghc?B*!EtHL zj0bJng1(DkFg~sVYq^+l@mM^v=~z5+@mPFhI%|YMAA&E`3jPGI;v`NCFBU^*jdslhMi{IP%b(!UN^P8TR-mR|QuWvTx1wVZH z!EJlrQT)-}D&1SC?7n{c-tNnveEwwb`s-}|tH$UP6DR$>>ndM5v{4Rj6SPTc@5@8; zxaOWbz9WzB2izKs7O?l@9OM$ZbyRH%@5WO>T?DenQ?YqZ)ebi8@l`-HZsc>(rik`DCE9|%V^5inQ{ssF%*QEpLEo*X zYG>{pozS$QvRh9@<|BG7?_!UqY9DXts7i3-)E}5X^{We&jw?^&j`AG|=-QJ+i$#JP z;#1c$E$%5dO7wyGhIimb>I=<#D%57*j*A5IC3@|%Q1*B#GViI{C%EnLlsZVX7^mE* z5@Pe7Qg>ZD&VA>gwMdss_y6@9*oHE~@3e>~i zZsU~s8eJVKJ3h^rKOqm@*i(`D{#5Pr1NL~T_E$4H@{}9>Df6k%ccbtO&8NQFALz2j zQ|b)eVv*oR>KmA!VFhkb34wV}slkYjkA3FVH*}*tH8vm7BR57fwU4@X)W}npQ`PJL zFuq5`Ueh-}c0(n#zi!iwO2&>vUgKLz)IGnBwP$`$sY|bp>mKvXk)a!&s{JXwZafvb zp+0qa)?%D;<9w!m44}o_=f?T0_U95h@{}9HCN*Q!VnlaiPpRSd_B^G2z^3DfZa(+b z{;aM&o>DgkTijD_R0(PlxkXR85zzuG0001Zob6p(Z`(#1eebUz^xlY{B;EigfNeQlZ<98a(9HtD!jK~- z6=G2?MW+q0*xz1~axKMH=gb*$$r+$;i7uapXXbp@L;B>?ZE>}{_Oit~eLk3-z8-xy zf3{xSUR_@gyz0HrX}(=;vgZSNCIj!+yG35yZTGMKw0psOldsmP_pjZ{o+QuYneUz5 zt!|cH82O%`3`e8k$d|;M|I>T5DpK!axhl%f4qklYc_*LJFITslRaR`TwrSxNUvA6Q z=&gU#5+Wh?T^_zV2F<-1Hvxq$9{s?6daVML-y`T&t=9J$2 zlym2ZIn@#3_Ire=Go78k`kt}~iF0;Jx}XuF&MCb}4d#$QBI3Ndm|pxqSwzG+UoT7U zT;z*wO4&usIi1aaS$!xdn}|H;GQYcCuZkjFQg#uC%6;N|<`{9Pg!ISldv2@7h(&d_ z5pfGeJSv?>P8mcj%F0!qZ*J!44P_QlslN6JckPHwRbb=d`50zzZ!b7F5slbDIYu0+ zE}C`iG2-@Sf(TS*2;3?sTIm}H<^-{)3Y8ooCx}1O+4M4_ENW4Qyl_OF(!b5p zU+JhZ(TGMo0Ek2N&Xe1OXjJVySNKg3jn2R6B zX4R0GZZhg*1{%2>cZ341=0VKa)ZkB6H95GnTxExV| zJ<{tcyvaXO?YIc>s5zD3-pvV{5b|)k_5DENuU|{9LCSRw^r)HjB9<0br!~x=Kg+p@A=_5KD2n583jOHZ* z;%g+8fN}|1G62;Q{6JoyUV@H|0<{wK{9K?~f*zm?)JxDwwLrmy;Rs!zY{FoM zE>JmPI7AnypP;Ac0tFN%V|0Nc3WGViU>yZH8xg3WFq@~lu#JV(*+7B=z+RG{e;0pU7&)3AE^rzQB9Bf1qv(3fxSRg1wFABD5zjZ_5#%u{LEgU zn!<2sFHloaHEek1>qsle1B$g3yc$5DzQRlnAW&pspa&4BurLq=2ozb+iU5Hc3tkc+ zP+(!82@t5T;6(uf6&AEAK%m6JNERSaWM(XXNS>omjKNC?1j;dZ4S_&41}`EIsK+o- z5eO7z>~3Dr`0-D- zM<1#1=ll1cC>BNPt+HkM`}2W+@MisXeTDnZ=xx6F{mbA*xz^hQE5kp{JpA%-_tVE$ zawxf=*K*LBH(Jce@EBPCZv^+mvjD+~iwN$=aTXxBpA9>N;9kgJ0fKu$i9-nPJLDE1 zIChc6HU$#DnNRKqz?7XpiL}JnnksK5R7d)gRzTeaAcDo zlxBqJ=?vPG4(@xr4k0+UsU#UWS(4auDFk$VC>9ZK_E|F6M(1n^-({k;S1+2nH@@GqFvvICe1> z2R0!XIEkQ5!_L6PsxE5Ql507eaq$c`oQ}1Opo?d)q3dZE!HJ7K>V|T&mh(XuYZ9^P z4Eipr2Q30HaS^}JrbyhdJnE?;u?fN0MK2iH6h|T#1*~J6W}OX3Ha(p|ivo!>bjm&D zGB&Ze;mGEse($QN9?5ZU=kqEr?iM!#FS}b`z2Dqy%U^l;?UM)G4t}Hj(A_#aSg7oO ze)rz~$De%vMHosLEePZHdcyL|SOUF*i(Q|@MiE>{ayp-x#Ki-l@8v@UU)(S*9 z1W+xZW298A*^ZD>IYfJqN>m9?H%P@Q$7c~zsvMysq*Pwn9;B3mk#3L*R5_GINSV6R z_K=#mai-$_&y?~GBYTh%(+zD8Ddjx~_8>Jf4bkl(WgLDxW?%0>`KpynXWSv{IPvWNOer6YX%AAy5xPC3 zl(*zqgjDZ9`EKN$%7?#olq0wy-{@bx;X9Ic_FwcFj~hFVeEs|Lu^W-kc+%El~S32q>zeB4M!Ri7K9cI89TI;#5I@aV>qwiZ3Q zadWDEUH9&Ur}rlO<(&y%-$L-@u7qRvB>eRq36G6E`tqZD5jxI%`X3A^A5UoyPn3_m z>nNN4nsS!$LaB=G^GF8n+QzWS<*(ukt}$9c6QF zAfXZlr diff --git a/CPLD/MAXII/output_files/RAM2GS.asm.rpt b/CPLD/MAXII/output_files/RAM2GS.asm.rpt index 8878de3..ddbf78b 100644 --- a/CPLD/MAXII/output_files/RAM2GS.asm.rpt +++ b/CPLD/MAXII/output_files/RAM2GS.asm.rpt @@ -1,5 +1,5 @@ Assembler report for RAM2GS -Sun Aug 13 04:50:42 2023 +Sun Aug 13 06:36:33 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Sun Aug 13 04:50:42 2023 ; +; Assembler Status ; Successful - Sun Aug 13 06:36:33 2023 ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; ; Family ; MAX II ; @@ -67,8 +67,8 @@ https://fpgasoftware.intel.com/eula. +----------------+---------------------------------------------------------------------------------+ ; Option ; Setting ; +----------------+---------------------------------------------------------------------------------+ -; JTAG usercode ; 0x00171C35 ; -; Checksum ; 0x00172025 ; +; JTAG usercode ; 0x00173373 ; +; Checksum ; 0x001735EB ; +----------------+---------------------------------------------------------------------------------+ @@ -78,15 +78,15 @@ https://fpgasoftware.intel.com/eula. Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Sun Aug 13 04:50:42 2023 + Info: Processing started: Sun Aug 13 06:36:32 2023 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 1 warning Info: Peak virtual memory: 4663 megabytes - Info: Processing ended: Sun Aug 13 04:50:42 2023 - Info: Elapsed time: 00:00:00 + Info: Processing ended: Sun Aug 13 06:36:33 2023 + Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:00 diff --git a/CPLD/MAXII/output_files/RAM2GS.done b/CPLD/MAXII/output_files/RAM2GS.done index 15ad0a9..d4305d5 100644 --- a/CPLD/MAXII/output_files/RAM2GS.done +++ b/CPLD/MAXII/output_files/RAM2GS.done @@ -1 +1 @@ -Sun Aug 13 04:50:45 2023 +Sun Aug 13 06:36:35 2023 diff --git a/CPLD/MAXII/output_files/RAM2GS.fit.rpt b/CPLD/MAXII/output_files/RAM2GS.fit.rpt index e04858d..e60bbb4 100644 --- a/CPLD/MAXII/output_files/RAM2GS.fit.rpt +++ b/CPLD/MAXII/output_files/RAM2GS.fit.rpt @@ -1,5 +1,5 @@ Fitter report for RAM2GS -Sun Aug 13 04:50:41 2023 +Sun Aug 13 06:36:31 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -59,7 +59,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------+ ; Fitter Summary ; +-----------------------+---------------------------------------------+ -; Fitter Status ; Successful - Sun Aug 13 04:50:41 2023 ; +; Fitter Status ; Successful - Sun Aug 13 06:36:31 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; @@ -135,8 +135,8 @@ https://fpgasoftware.intel.com/eula. ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 1.8% ; -; Processors 3-4 ; 1.5% ; +; Processor 2 ; 2.0% ; +; Processors 3-4 ; 1.3% ; +----------------------------+-------------+ @@ -157,9 +157,9 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/ ; -- Combinational with a register ; 77 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 56 ; -; -- 3 input functions ; 48 ; -; -- 2 input functions ; 41 ; +; -- 4 input functions ; 57 ; +; -- 3 input functions ; 46 ; +; -- 2 input functions ; 42 ; ; -- 1 input functions ; 8 ; ; -- 0 input functions ; 1 ; ; ; ; @@ -168,11 +168,11 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/ ; -- arithmetic mode ; 16 ; ; -- qfbk mode ; 7 ; ; -- register cascade mode ; 0 ; -; -- synchronous clear/load mode ; 29 ; +; -- synchronous clear/load mode ; 25 ; ; -- asynchronous clear/load mode ; 0 ; ; ; ; ; Total registers ; 98 / 240 ( 41 % ) ; -; Total LABs ; 23 / 24 ( 96 % ) ; +; Total LABs ; 21 / 24 ( 88 % ) ; ; Logic elements in carry chains ; 17 ; ; Virtual pins ; 0 ; ; I/O pins ; 63 / 80 ( 79 % ) ; @@ -186,8 +186,8 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/ ; Global signals ; 4 ; ; -- Global clocks ; 4 / 4 ( 100 % ) ; ; JTAGs ; 0 / 1 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 26.5% / 24.7% / 28.5% ; -; Peak interconnect usage (total/H/V) ; 26.5% / 24.7% / 28.5% ; +; Average interconnect usage (total/H/V) ; 23.8% / 26.2% / 21.3% ; +; Peak interconnect usage (total/H/V) ; 23.8% / 26.2% / 21.3% ; ; Maximum fan-out ; 55 ; ; Highest non-global fan-out ; 41 ; ; Total fan-out ; 661 ; @@ -204,20 +204,20 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/ ; CROW[1] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; Din[0] ; 42 ; 1 ; 5 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; Din[1] ; 36 ; 1 ; 4 ; 0 ; 2 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[2] ; 35 ; 1 ; 3 ; 0 ; 0 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[3] ; 37 ; 1 ; 4 ; 0 ; 1 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[4] ; 39 ; 1 ; 5 ; 0 ; 3 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[5] ; 38 ; 1 ; 4 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[2] ; 35 ; 1 ; 3 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[3] ; 37 ; 1 ; 4 ; 0 ; 1 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[4] ; 39 ; 1 ; 5 ; 0 ; 3 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[5] ; 38 ; 1 ; 4 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; Din[6] ; 41 ; 1 ; 5 ; 0 ; 1 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; Din[7] ; 40 ; 1 ; 5 ; 0 ; 2 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; MAin[0] ; 49 ; 1 ; 7 ; 0 ; 2 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; MAin[1] ; 51 ; 1 ; 7 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[0] ; 49 ; 1 ; 7 ; 0 ; 2 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[1] ; 51 ; 1 ; 7 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[2] ; 50 ; 1 ; 7 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[3] ; 71 ; 2 ; 8 ; 4 ; 3 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[4] ; 70 ; 2 ; 8 ; 4 ; 4 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[5] ; 69 ; 2 ; 8 ; 3 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; MAin[6] ; 72 ; 2 ; 8 ; 4 ; 2 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; MAin[7] ; 68 ; 2 ; 8 ; 3 ; 1 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[6] ; 72 ; 2 ; 8 ; 4 ; 2 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[7] ; 68 ; 2 ; 8 ; 3 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[8] ; 73 ; 2 ; 8 ; 4 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[9] ; 74 ; 2 ; 8 ; 4 ; 0 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; PHI2 ; 52 ; 2 ; 8 ; 1 ; 4 ; 22 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; @@ -245,18 +245,18 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/ ; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; -; RA[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; +; RA[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; - ; - ; ; RA[2] ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; -; RA[4] ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; +; RA[4] ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; - ; - ; ; RA[5] ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[6] ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; -; RBA[0] ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; RBA[0] ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; ; RBA[1] ; 14 ; 1 ; 1 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; RCKE ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +; RCKE ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; RDQMH ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RDQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; nRCAS ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; @@ -272,12 +272,12 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ ; RD[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; -; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; -; RD[2] ; 89 ; 2 ; 4 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; +; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; comb~0 ; - ; +; RD[2] ; 89 ; 2 ; 4 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; comb~0 ; - ; ; RD[3] ; 99 ; 2 ; 2 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; ; RD[4] ; 92 ; 2 ; 3 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; -; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; -; RD[6] ; 95 ; 2 ; 3 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; +; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; comb~0 ; - ; +; RD[6] ; 95 ; 2 ; 3 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; comb~0 ; - ; ; RD[7] ; 97 ; 2 ; 3 ; 5 ; 3 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ @@ -491,8 +491,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Din[6] ; Input ; (1) ; ; nFWE ; Input ; (1) ; ; Din[0] ; Input ; (1) ; -; Din[1] ; Input ; (1) ; ; Din[7] ; Input ; (1) ; +; Din[1] ; Input ; (1) ; ; Din[4] ; Input ; (1) ; ; Din[2] ; Input ; (1) ; ; Din[3] ; Input ; (1) ; @@ -505,14 +505,14 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +------------+-------------+---------+-------------------------+--------+----------------------+------------------+ ; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; +------------+-------------+---------+-------------------------+--------+----------------------+------------------+ -; CmdDRDIn~2 ; LC_X5_Y3_N9 ; 4 ; Clock enable ; no ; -- ; -- ; -; CmdLEDEN~1 ; LC_X5_Y3_N3 ; 3 ; Clock enable ; no ; -- ; -- ; -; DRDIn~1 ; LC_X6_Y4_N1 ; 2 ; Clock enable ; no ; -- ; -- ; +; CmdDRDIn~1 ; LC_X6_Y1_N6 ; 4 ; Clock enable ; no ; -- ; -- ; +; CmdLEDEN~1 ; LC_X5_Y1_N9 ; 3 ; Clock enable ; no ; -- ; -- ; +; DRDIn~1 ; LC_X5_Y1_N0 ; 2 ; Clock enable ; no ; -- ; -- ; ; PHI2 ; PIN_52 ; 22 ; Clock ; yes ; Global Clock ; GCLK3 ; ; RCLK ; PIN_12 ; 55 ; Clock ; yes ; Global Clock ; GCLK0 ; -; Ready ; LC_X6_Y2_N8 ; 40 ; Sync. clear, Sync. load ; no ; -- ; -- ; -; always8~7 ; LC_X7_Y3_N8 ; 3 ; Clock enable ; no ; -- ; -- ; -; comb~0 ; LC_X7_Y1_N6 ; 8 ; Output enable ; no ; -- ; -- ; +; Ready ; LC_X3_Y2_N5 ; 40 ; Sync. clear, Sync. load ; no ; -- ; -- ; +; always8~6 ; LC_X6_Y3_N1 ; 3 ; Clock enable ; no ; -- ; -- ; +; comb~0 ; LC_X3_Y4_N5 ; 8 ; Output enable ; no ; -- ; -- ; ; nCCAS ; PIN_53 ; 11 ; Clock ; yes ; Global Clock ; GCLK2 ; ; nCRAS ; PIN_67 ; 16 ; Clock ; yes ; Global Clock ; GCLK1 ; +------------+-------------+---------+-------------------------+--------+----------------------+------------------+ @@ -535,112 +535,115 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------------+--------------------+ ; Routing Resource Type ; Usage ; +-----------------------+--------------------+ -; C4s ; 175 / 784 ( 22 % ) ; -; Direct links ; 36 / 888 ( 4 % ) ; +; C4s ; 146 / 784 ( 19 % ) ; +; Direct links ; 45 / 888 ( 5 % ) ; ; Global clocks ; 4 / 4 ( 100 % ) ; ; LAB clocks ; 14 / 32 ( 44 % ) ; -; LUT chains ; 20 / 216 ( 9 % ) ; -; Local interconnects ; 274 / 888 ( 31 % ) ; -; R4s ; 148 / 704 ( 21 % ) ; +; LUT chains ; 27 / 216 ( 13 % ) ; +; Local interconnects ; 266 / 888 ( 30 % ) ; +; R4s ; 149 / 704 ( 21 % ) ; +-----------------------+--------------------+ +---------------------------------------------------------------------------+ ; LAB Logic Elements ; +--------------------------------------------+------------------------------+ -; Number of Logic Elements (Average = 7.61) ; Number of LABs (Total = 23) ; +; Number of Logic Elements (Average = 8.33) ; Number of LABs (Total = 21) ; +--------------------------------------------+------------------------------+ -; 1 ; 2 ; -; 2 ; 2 ; -; 3 ; 0 ; -; 4 ; 0 ; +; 1 ; 0 ; +; 2 ; 1 ; +; 3 ; 1 ; +; 4 ; 1 ; ; 5 ; 1 ; ; 6 ; 1 ; ; 7 ; 1 ; -; 8 ; 2 ; -; 9 ; 5 ; -; 10 ; 9 ; +; 8 ; 0 ; +; 9 ; 2 ; +; 10 ; 13 ; +--------------------------------------------+------------------------------+ +-------------------------------------------------------------------+ ; LAB-wide Signals ; +------------------------------------+------------------------------+ -; LAB-wide Signals (Average = 1.43) ; Number of LABs (Total = 23) ; +; LAB-wide Signals (Average = 1.33) ; Number of LABs (Total = 21) ; +------------------------------------+------------------------------+ -; 1 Clock ; 17 ; -; 1 Clock enable ; 2 ; -; 1 Sync. clear ; 5 ; -; 1 Sync. load ; 3 ; -; 2 Clocks ; 6 ; +; 1 Clock ; 10 ; +; 1 Clock enable ; 3 ; +; 1 Sync. clear ; 3 ; +; 1 Sync. load ; 2 ; +; 2 Clocks ; 10 ; +------------------------------------+------------------------------+ +----------------------------------------------------------------------------+ ; LAB Signals Sourced ; +---------------------------------------------+------------------------------+ -; Number of Signals Sourced (Average = 7.87) ; Number of LABs (Total = 23) ; +; Number of Signals Sourced (Average = 8.62) ; Number of LABs (Total = 21) ; +---------------------------------------------+------------------------------+ ; 0 ; 0 ; -; 1 ; 2 ; +; 1 ; 0 ; ; 2 ; 1 ; ; 3 ; 1 ; -; 4 ; 0 ; +; 4 ; 1 ; ; 5 ; 1 ; ; 6 ; 1 ; ; 7 ; 1 ; -; 8 ; 1 ; -; 9 ; 5 ; -; 10 ; 8 ; -; 11 ; 1 ; -; 12 ; 1 ; +; 8 ; 0 ; +; 9 ; 2 ; +; 10 ; 9 ; +; 11 ; 2 ; +; 12 ; 2 ; +---------------------------------------------+------------------------------+ +--------------------------------------------------------------------------------+ ; LAB Signals Sourced Out ; +-------------------------------------------------+------------------------------+ -; Number of Signals Sourced Out (Average = 5.57) ; Number of LABs (Total = 23) ; +; Number of Signals Sourced Out (Average = 5.57) ; Number of LABs (Total = 21) ; +-------------------------------------------------+------------------------------+ ; 0 ; 0 ; -; 1 ; 3 ; -; 2 ; 2 ; -; 3 ; 1 ; -; 4 ; 2 ; -; 5 ; 5 ; -; 6 ; 1 ; -; 7 ; 1 ; -; 8 ; 3 ; -; 9 ; 2 ; -; 10 ; 3 ; +; 1 ; 0 ; +; 2 ; 3 ; +; 3 ; 2 ; +; 4 ; 1 ; +; 5 ; 3 ; +; 6 ; 5 ; +; 7 ; 3 ; +; 8 ; 2 ; +; 9 ; 1 ; +; 10 ; 1 ; +-------------------------------------------------+------------------------------+ -+----------------------------------------------------------------------------+ -; LAB Distinct Inputs ; -+---------------------------------------------+------------------------------+ -; Number of Distinct Inputs (Average = 9.74) ; Number of LABs (Total = 23) ; -+---------------------------------------------+------------------------------+ -; 0 ; 0 ; -; 1 ; 1 ; -; 2 ; 0 ; -; 3 ; 1 ; -; 4 ; 0 ; -; 5 ; 1 ; -; 6 ; 3 ; -; 7 ; 3 ; -; 8 ; 2 ; -; 9 ; 0 ; -; 10 ; 3 ; -; 11 ; 2 ; -; 12 ; 1 ; -; 13 ; 0 ; -; 14 ; 1 ; -; 15 ; 1 ; -; 16 ; 2 ; -; 17 ; 1 ; -; 18 ; 1 ; -+---------------------------------------------+------------------------------+ ++-----------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++----------------------------------------------+------------------------------+ +; Number of Distinct Inputs (Average = 10.71) ; Number of LABs (Total = 21) ; ++----------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 1 ; +; 3 ; 1 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 1 ; +; 7 ; 1 ; +; 8 ; 3 ; +; 9 ; 3 ; +; 10 ; 3 ; +; 11 ; 0 ; +; 12 ; 1 ; +; 13 ; 1 ; +; 14 ; 1 ; +; 15 ; 0 ; +; 16 ; 2 ; +; 17 ; 2 ; +; 18 ; 0 ; +; 19 ; 0 ; +; 20 ; 0 ; +; 21 ; 1 ; ++----------------------------------------------+------------------------------+ +-------------------------------------------------------------------------+ @@ -662,8 +665,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------+----------------------+-------------------+ ; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; +-----------------+----------------------+-------------------+ -; I/O ; nCRAS ; 4.0 ; -; I/O ; RCLK ; 3.7 ; +; I/O ; RCLK ; 4.0 ; +; I/O ; nCRAS ; 2.5 ; +-----------------+----------------------+-------------------+ Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. This will disable optimization of problematic paths and expose them for further analysis using the Timing Analyzer. @@ -674,9 +677,9 @@ This will disable optimization of problematic paths and expose them for further +-----------------+----------------------+-------------------+ ; Source Register ; Destination Register ; Delay Added in ns ; +-----------------+----------------------+-------------------+ -; nCCAS ; CBR ; 4.013 ; +; nCCAS ; CBR ; 2.469 ; ; PHI2 ; PHI2r ; 1.523 ; -; nCRAS ; RASr ; 0.916 ; +; nCRAS ; RASr ; 1.214 ; +-----------------+----------------------+-------------------+ Note: This table only shows the top 3 path(s) that have the largest delay added for hold. @@ -737,8 +740,8 @@ Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 Info (170193): Fitter routing operations beginning -Info (170195): Router estimated average interconnect usage is 22% of the available device resources - Info (170196): Router estimated peak interconnect usage is 22% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 +Info (170195): Router estimated average interconnect usage is 19% of the available device resources + Info (170196): Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 @@ -748,8 +751,8 @@ Warning (169174): The Reserve All Unused Pins setting has not been specified, an Info (144001): Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg Info: Quartus Prime Fitter was successful. 0 errors, 4 warnings Info: Peak virtual memory: 5345 megabytes - Info: Processing ended: Sun Aug 13 04:50:41 2023 - Info: Elapsed time: 00:00:02 + Info: Processing ended: Sun Aug 13 06:36:31 2023 + Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:03 diff --git a/CPLD/MAXII/output_files/RAM2GS.fit.summary b/CPLD/MAXII/output_files/RAM2GS.fit.summary index 9858dbb..952fe86 100644 --- a/CPLD/MAXII/output_files/RAM2GS.fit.summary +++ b/CPLD/MAXII/output_files/RAM2GS.fit.summary @@ -1,4 +1,4 @@ -Fitter Status : Successful - Sun Aug 13 04:50:41 2023 +Fitter Status : Successful - Sun Aug 13 06:36:31 2023 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition Revision Name : RAM2GS Top-level Entity Name : RAM2GS diff --git a/CPLD/MAXII/output_files/RAM2GS.flow.rpt b/CPLD/MAXII/output_files/RAM2GS.flow.rpt index 0c4d2e3..fc55790 100644 --- a/CPLD/MAXII/output_files/RAM2GS.flow.rpt +++ b/CPLD/MAXII/output_files/RAM2GS.flow.rpt @@ -1,5 +1,5 @@ Flow report for RAM2GS -Sun Aug 13 04:50:44 2023 +Sun Aug 13 06:36:35 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------+ ; Flow Summary ; +-----------------------+---------------------------------------------+ -; Flow Status ; Successful - Sun Aug 13 04:50:42 2023 ; +; Flow Status ; Successful - Sun Aug 13 06:36:33 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; @@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 08/13/2023 04:50:29 ; +; Start date & time ; 08/13/2023 06:36:18 ; ; Main task ; Compilation ; ; Revision Name ; RAM2GS ; +-------------------+---------------------+ @@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------+---------------------------------+---------------+-------------+------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +---------------------------------------+---------------------------------+---------------+-------------+------------+ -; COMPILER_SIGNATURE_ID ; 207120313862967.169191662914016 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 207120313862967.169192297814284 ; -- ; -- ; -- ; ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; ; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ; @@ -85,11 +85,11 @@ https://fpgasoftware.intel.com/eula. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:09 ; 1.0 ; 4700 MB ; 00:00:23 ; -; Fitter ; 00:00:02 ; 1.0 ; 5345 MB ; 00:00:03 ; -; Assembler ; 00:00:00 ; 1.0 ; 4662 MB ; 00:00:00 ; -; Timing Analyzer ; 00:00:01 ; 1.0 ; 4677 MB ; 00:00:01 ; -; Total ; 00:00:12 ; -- ; -- ; 00:00:27 ; +; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 4702 MB ; 00:00:26 ; +; Fitter ; 00:00:01 ; 1.0 ; 5345 MB ; 00:00:03 ; +; Assembler ; 00:00:01 ; 1.0 ; 4662 MB ; 00:00:00 ; +; Timing Analyzer ; 00:00:01 ; 1.0 ; 4676 MB ; 00:00:01 ; +; Total ; 00:00:14 ; -- ; -- ; 00:00:30 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/CPLD/MAXII/output_files/RAM2GS.map.rpt b/CPLD/MAXII/output_files/RAM2GS.map.rpt index c5bf80d..5cba882 100644 --- a/CPLD/MAXII/output_files/RAM2GS.map.rpt +++ b/CPLD/MAXII/output_files/RAM2GS.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for RAM2GS -Sun Aug 13 04:50:38 2023 +Sun Aug 13 06:36:29 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -46,7 +46,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+---------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Sun Aug 13 04:50:38 2023 ; +; Analysis & Synthesis Status ; Successful - Sun Aug 13 06:36:29 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; @@ -167,9 +167,9 @@ https://fpgasoftware.intel.com/eula. ; -- Combinational with a register ; 68 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 56 ; -; -- 3 input functions ; 48 ; -; -- 2 input functions ; 41 ; +; -- 4 input functions ; 57 ; +; -- 3 input functions ; 46 ; +; -- 2 input functions ; 42 ; ; -- 1 input functions ; 8 ; ; -- 0 input functions ; 1 ; ; ; ; @@ -270,7 +270,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Sun Aug 13 04:50:29 2023 + Info: Processing started: Sun Aug 13 06:36:18 2023 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected @@ -301,10 +301,10 @@ Info (21057): Implemented 248 device resources after synthesis - the final resou Info (21070): Implemented 1 User Flash Memory blocks Info (144001): Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings - Info: Peak virtual memory: 4700 megabytes - Info: Processing ended: Sun Aug 13 04:50:38 2023 - Info: Elapsed time: 00:00:09 - Info: Total CPU time (on all processors): 00:00:23 + Info: Peak virtual memory: 4702 megabytes + Info: Processing ended: Sun Aug 13 06:36:29 2023 + Info: Elapsed time: 00:00:11 + Info: Total CPU time (on all processors): 00:00:26 +------------------------------------------+ diff --git a/CPLD/MAXII/output_files/RAM2GS.map.summary b/CPLD/MAXII/output_files/RAM2GS.map.summary index add9d2e..061e4cf 100644 --- a/CPLD/MAXII/output_files/RAM2GS.map.summary +++ b/CPLD/MAXII/output_files/RAM2GS.map.summary @@ -1,4 +1,4 @@ -Analysis & Synthesis Status : Successful - Sun Aug 13 04:50:38 2023 +Analysis & Synthesis Status : Successful - Sun Aug 13 06:36:29 2023 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition Revision Name : RAM2GS Top-level Entity Name : RAM2GS diff --git a/CPLD/MAXII/output_files/RAM2GS.pof b/CPLD/MAXII/output_files/RAM2GS.pof index 69bb0b30a72691c50e1c0ece72a7f1321f243e4c..5f10bb4f0b6539bdb824529ff76b21ec08671baf 100644 GIT binary patch literal 7861 zcmeHMeQX@ZbzjN0q#_cD!V#Jevu68;{|Hct66?x}Bwt|Hij!KA8&@>~L}gq^q?Lv| zSYMP)?Tu5^k`34vY@`kpg<_3XDguGJI)+79m%TNbltyBHxQJ;*q4&nEtYa$rcBL?P z%e%dq*Wa7nJCZJtfBQ##z~0=vkKcRq=Djzw`YzhIJk7_Z-^ytv&63wyC4NWAplr8`p2_ z*s!_%p)a>Tu5T=B&F9>pq*F#!| zE{_!nyn&{D$h%U(C-8-eSYL!ng|R;C;ZY&eC5;1D(=0sX5p=_^lOqDs@&b885%3Z^ z^Hr!3V=s<#VB{s!If{!$m+k1FL}5SZ@Lwc+-~~16mB4oeIgBrXFJixJDzZIka1kGm zXi`%EeuOv^m4qOl>SQC{j9ZF;8)e8V@1z3w%B@8ea1ge{o^qidDa!h+zni*1cO>jG zKN=DXont-YpA=X($#i=$}dVMrBoIyNF-@p7{%(T~Sn>?}a+-verEM z$vyWosq?w&keWELHL`zMTW|c2n1AHD`YiL);D6g29qNeeRqqGPcj!s~-TtsR{@&nZ zclX`>&fMjb{)Pir+FrSA{IhB7!?SQub`D5o@X zL%C$~NzI@@XF}vDM&KilYn6}=p>CxPB3VMLGZ_hbIo2nFT#B5uCXmU~;YB|jQEJ*X ze1r*n_mGWb!am6<5>ksa^c|BQQ!zf~C5iZAjG_!SiTek~&%=Z4C3VhYef%ODby_w1 z2_EKbC$RBDQyO_PM+FcR<(Q5>!|RghJ6r|1=@PwV=pMOLXzE9y^Dx&B=O;x)6;u=| znf2|FC!jByeTmJWj!9htWTIc8$W_qI!*)_ zvH$P~^^N_J6cltX?Sdbbe4v%a2Yj2}`~y^Q->|F&l^}!uQ4Nbh6l@D#kJnp^0)6T4 zymDVC`&{K?UoU3tuh-QRU6R)imukhditKXWp0>}?S~WuYhgni?j6Y1N)jD_V+|>I& zUa7ya${PHio2`nqW`4)A73)qz-z(qrj=zohbDubNBx$~eZ7$?7u(u(yxkR<9qIyDt>UfbNpXk zJUQ|DtM@*)r88cCRYv-NS!b9rc&H<6MF~AN#vkhQ1Bx8*wCj%8Ya~ zLf(EC^(e@kKN)2!6*y%4CvmBQ+(8`K-X$J^PqvFZV0$viAn%nez?VYUl)F}8dVF7i zo^#2_p{MgXrzp{bjG+?=En!~w7(3xE2y5i7!EtduO(RIa$74u!< zzQuM?M=TG%GXp-~Lokm77Bjig7J;=HJF8YI8V11tB zDV34shcQR9$P>*vtjF|({~F&fl*{s=mXLGZSRcl<;J&7TD`UK92;-la{P)mT5cfds zmTCCmnL2f$kFLu2#{M*Ql?42NTnX_&s}61On7u2E2IOaT)us^kht4S)iPv9~ zlI8aHmjgW|C(%wQ(*u8g?LC~-AL%VB<&76yok86Jui~adXZ?V|AEwqZ{ptG5t~cKK z;tH$fpX~Yl2P>;@yS}D<)%kaUrI>HmY1iBD`~~=LKlS)rxn=e0>uv3;jQ!#A4OM z?L9rC-sQpPi`{=X;LLfR-8H29+IjDA z?$tye_lyYZou)8v{N=c6DtR*D_mht-DdlkAP$YY?9~G&T7sc^)w01Q~au7sL6m-IZ zAEKXT&Y|D(`pcZ>$eR#yB+IN%RjpLk;Ctj^R5W}M`ZdVIxRw-cL;lD93zmx072hT&<|&Ii8fKi z#RaUXAM=;aC9l)y0f+O>opO=K@IZl}d)Obg$LlxxsZuVWLSr7GKGp1Eek_+t)b6Z70DAGW`i3XB6U;<@|aL53f71gZL?t7w`^PiM|=9B;FTX$#Uqck#Y{XMt`l* z2d>7|1%1NcK+&UcA^#!c0p$W|FTVFEp=z?>7vsYs_2*r#_e-SDQbnOBv3<}X$Nnj| zAT`-E9co`^wq=TjzZ)_vS1!>GeO4krN|f28Zg@1f*uEHt-)DtFctfgG;pZ#D=$)yh z>iOt6O>Gso9=3jU)t>*x!OHUb+iUiH$J9@mQgyAEPc6)U>hVW@(=u89x3>F_8~=x) zujx2lwWw9E{MuKaq8FZNxn939*!M#dACL9HFN5!Y@oQggoB#H{(aHMtw!X8*KI(6L zwC8YfeEiuH-91P7{^|J}2mX7|xorIR$p7%dwW2@1XWdly#JWFT`|^uVZ-1rpq2ZIK z5`CBZI^vgFs6R~=tT*8!-${~#80rki5%;E?t}WzaK9&nfB97>P$U}-~8(qp4IIhs( z_}ZXnggGC59oD#!8al2uF5}}oz?|_hx>N>RupVn;6gUTX#2oLJG=LF)$Mg7{7T~LX z*h}PiZuorunR5VrJ~aHe?vnl=%L`>gJ`x6BQ-8y5GAFE`@hUvem_Ffh%EtbfQBshn zG|QpC<07c|y>NjKzi=t@k;ll#0Pm3>sc%~n<;mDj>zX7bsaAmg8T6#49XH0y5cttZ z_AK~~^#T|5p#;whImBB;z+0prkjz)O(=px%IjJCf9=~^)Io=2JcwbQ}4gbLpB72VU zVtZ`Ail4d=+si-#{^8ru%{b^rr0rO~KoL~~Y3Q*%+@l@5x76q92hh>c2&rRm=;@uN&MEJ{MXyWP1JA@KB5~;GgKzeIYQB|k zwJnzQ^DljJ+4=8*Z{nj!Y}oq7MBiQWt^X*9`EzS6OY{1Eki_?~FT797kJfMZKzrW0 zXRf;ZA58u>{J+zBgEB|vZ+`*&7Hj!jb=i}24Zr#P8|~>X{&eiwLSH&{>&Y7@PyVd) zg)8dh_ssrR$@gEn=KDV_uKSN~_T_WqXD;Rnov%Oi%&AU7IL-QM$OW8e;bHXGD*X3- zfw!@OSzp7x3VeyWK$L<&hfe6gauR=&-&MRM{u&gUTzpR}^&XE4`Jwy*@*nsbFFv>< zdSE8}xPBn3CF5f>=#JsTzQJ$$!F+a?NV0yD?lN7Nco)PXdMr;K^CkZN!*dt+MAQSH z9~c+xL!a+!g&3dhH1W+oqW7A7kg`c{*tcEu4Ux!)B3{QLedQXz8+y18ESU@2%#-?< z%{Jtg)L+~;peJC*B^Q3i`GxT#c!csd{x|Cv@6$S4Ys#SXhd?^_KI!!G z{jXt1 z4d-LSUSnK}v%rt(siEfo2kNo?-!8wP-@yNPT)J=n-|_gAwfg4fe}vlkKSCdWes?24 T0xk99&+l{uR+;}5m(Tn!^4wb` literal 7861 zcmeHMYiwM{bza#b=^~aGqo@%VkVqIs`m3U3#xVp#-k^q+rj{Q?D!V{HGj6OEgob3G z2RD+kJ8}vs4jQSb4a*@Ma_zWuP{b082r?mU?~V*xmfP?V{ZLqizB`c=lZ}|&OOx2W ziw?DOG_nuvSz3rPeZ`ib9WBZ@)+x7M5+CTrm#`cYyJMO!$ z_^p1#jZE#2P?8^5kRpeQx7lZ`!!=;rkP}C;k9S+k5x! z+WYk#&n23`!#{T=?)+o>z<++mCK)2q$=vJ^k*Mr9WN31Be3r<3YiLq~X6XS&1-{VE zRbw48GvL8|5BQ7@quk>wL={S2vvOZspsJ+{Y3G8d3XlvvKqf5eOjHt%PQuc`YXGJx zfL?_$boxn#mM)31SgQaAbFKAFa#l}BWzaK_Wlu6;O;|b5tR4|y48x2TL4hdrGf~|> z*5hf4q=7v9SEUkZFva!(m!uY!3q7;~HR85Nbnt z%+(FLBG?UjNW%F~+CPXn<3{m_=i)f)vGY(z>}5QcRr2h*5hV&23>`Ec$(U~AII07U zx%00s7yGBnv<X2mb{yEJ+CXO?386}Dr<>i;OGL0^LWO?1t4D&phO z*u?wknVInqzZaxZ$vuM~4-8CnK5%VtU;w)Wf5Yl zC-QllAD)jqae09{<+!o^CV>4;9^`UR9nD~#m1Tu|N*BP@g?w}S!2D!NM)9aM3Dilt z-f!TiQPsdqd60Mf1U(w{5>f$ch$Hf&k4kVTtBQ*v41GEQ{-Emi ziS;$?M&p`7XNlu7mCsmQRi_8QLtSWDz#6v2J z>(???o&)4?Lgznei$9`Aj$?fgA4@M+0#nhWr>Qjcc5cpWiQ`*}dRGDYKTWeGqo+^Gvyqn;b-V1iFAaJ~fltz{%j7Ne zmk)yO(}iLEm^w~gR8k7jXyA*C_d$36&Pc$yYh`i4bajxrC4Oa!$~BYsDeq-R4pzK{ zuUY&q_76Sp{Nmz|Qr}))Y+73S)mlo-53gOnf$i^M`;nA8R?Yu7l`ywAee+6UYx2vD1tr+BVebvbZRAcDum^S!fId+7Ahi60G=?qb} z2oHQkR{n;6N@khgBjlx=^1`s_;@eF|aa>s*?S(uta|->i$aAc7r^8>t_0nBId=NP3 z8;xSRCyi24OEfi9wmzezSronw8~q#h0;jCnVBhE#A)tSP29N#ZsfK=vBJO)x8d=iD zJ5U@tQ_YAji{EqqsfT8MdU1bKVyq?A{5Rpc|C(9V{Jr@F+-gt$95R{Yo_A-)r&^lM zO@1oX{LRX`|7=M#A4<&s(QOGApZovy9h3ZQGvr%S&EIbwT$)YZo!GmuF7e$FmiIco z(K;hve-`o`OkcOu0{W-t2Uj1m@|r&MC(`L~eC+74RO+El@8bclcxwNJ!I$pow)TsO z7mnO}?+?evwp{}KrNQABHxHe8@Zmq}%v<|Cg}9=BcoFhW&KW&xlu3tX95HqA1s%_v zEzf8neL`G?h_FqLZb%xXP>)y-_}rGJh|7S^OX>15=A&iE@qY2X@O@HRd7nripEbv~ zuporb@**Gk(|jH=e=LuOf~~)&MbWK?j*dE10r`^c4ImG`0)<{(jP0m8m0UT?%Ri(zLb(l{H%I-I??7%ku0Qm#Dn)vxs>;gZ<%ViT>(-B~{P5XV zk~7yXE^m3^3oXs_t)#!Tetq-e{CsKWFI{}(EAOUeFMems9p~0s`hKx~Yvs=Q%05?r zCk}k+9kcVZN4C86vt;vY|46#l265OeBp&7e|zr_OJk{*ds9Ps|MjyE4xP$> z<;0nRdVI*_QRle9RU^cAmit;dEZK^){#ri7wHp!l5Kk(manG8o#qv3f3f$bENR{Y` zAdA-ljo{;#?^AXJU0^O*-sJ5$7SkP{N2H9vCgS|+1)5%{x&C3#yHMy#5&03@!{-2` z8Q<_TxIr=GpkRxu6_bSVWerxfkBF+;rn^ z{cj3%B^vZ9lgyPQGZxq3p7c_ z!#==3d~Cl&;a$YDQF6}p3v4jY@mVHiM>|K%{W&pifUz9Y9iP3ADD#T^@tL{EH|Q;O z`7XK!c_pqOI_0dGg7XslcNuiW@v`_(k1o*pbMLk^;~Sap zmY43SQpd`#5uXe1D1Y1ajvx)^fTu9=h5ev*}s~le}MaEf9kUTgP{7kw$6cT1O9(>c245` zPxALW%k+Nv?dvn;f8X}_`K!+r2F721aiEybKm2+=uizHw(^SLx=SO(2lRUTg7IsxI zJ>C!UrM>4EpJ>r=9~brbGoP=PgHY8p<@8Eu`e|8bf+@-J?5D-a8OD>BF)xIuzc{~d zs!w!OFoF;Kg2%eNtq0PwK37>Ip}!yB z2Y|=>+AMZxl z$+|w&r?~ZgdpgJXwlAfP7;4}T*HocOznSRSPu(X`<6Yd3LPc9t#rBIve4#s={typo@RF^uXv!EDg_Ylqk~NZgy(nUSfukS$6Y31P{D&O+mFJZT=pRp0 z(9j2L#s|HA-`82p@M5VJ><9-fT@9MByz&=`-|ux;dKcWjN>h`A zIuxJp)e`5vG&u0I7d>^|%A;?p{i7M|ni;Jr-0aK0m$hOTVC;_Bx_jovdCp4fW0 z{WpCx=c(-|HfpH%_T??NyZbBrdvE58f6?4@E@(Y+m|EAY+;wQ^s~Yrk#`*W5|9(34 ztMQeS6RG}(I*)#Qd9b``&o%FZ`uR4o?fBKPiPFT{OT9CNSN(r}ar4B3o4>r~pE~RD z{u=lVKCD}L#0~MdA^+Prbv!q^IR9_>oj-Nl`si@rfAV+XBj4f84f{o^ zI*Ip+oikjossyka<(9WJ-p_B?^}Fp%<{JMWSoy#CRrlkQ@z(wO|BAAzO$UxaLnnG%KECVcJ)Iob=1IX^R23g zpa6NI1?CHFYDF8$XWb)*3kbh zV&#ys_Lyb8RE0m04sOqCz=A(414QTMAyZQFExOouuZQ_aPxVf9H96VFfZ+zq*niu@ z@DtqXT?fa;iEXFe4(W~vnT{oePW594Ek4s>|m2;4yt`KRO0@DI?KjLKRx#vfa_jm$AFDj z#qBuYdD_t;%-Zq!?im+?)8D`RAj{z+amdMMLyw9^edA^byYh(XkXy-U2|ow+Avd!z zH%l-z11m?lnI}36YY&E;2#(1I8UC^l)5=cF^sS?Tu`A7sYV)$b@V>0vDmrxC@E2Fd rtAU~G{j$Am`f$av>DRIUFj!_4PRz3VqfYV-UAFh@gUh`zF(;u*ms#0v diff --git a/CPLD/MAXV/db/RAM2GS.(0).cnf.cdb b/CPLD/MAXV/db/RAM2GS.(0).cnf.cdb index 44fdc4e098e89bfffae00dac42c3ef2776f17a76..98161d863c17ca104905b411496478fe12dd269f 100644 GIT binary patch literal 21188 zcmaHSWl$VZ(=G%8!GpWIyIT@0K!D)R;_d{8#ob*40fKvQUEJN>-CdT2{dnK+R^9vS z)>L)R^mO%9pEK3x%+t@{z`(#%qQJgO7#N%PgXdjqm^r&xIoMNh3bJvsaZr47wX!v( z;N$0@;1Fcz;$r9G;1r}#m81A!^~;Px%GB!DyRRnOhyR91`T1W3(+l^%`aiNy<$upT zV9z@IYSJ`;o9?v2Bhn4?4Ys?fd}?O4W!>odTC6iF7}{+3?ccBxtLrU;uu3VqtLkU^ zqi94%O`n3qzsrl5hPn-@CFP-!GBd{Pmx`E?6c%ywOf%HeqBYJ3n=dhDl+@ZL!4F0T z*-by5X5T*NOuFQdZ(iQ6MbRu>wzzaozFVFlZ`qTAlW{LTAU|{S14K1w#YvnGhGwZ4 zlf^}PMvH`BZdMET-SO!dsCeXB995K?dowN8@7o}KC-|!M4!7R=_}g1{s9581e~3lr z6~6TMpsPhTEWdTCYf$rd2qIntv`}iN8bI?F6xHWvneYT4iv@YUT^HkH`@#AdLSAL1 zUe~U!`0u2g$q66>zJ_PS;I1kDyMP3TBRIItDdOF?7YR1vw8w*oj@9BPjNCC+E>tpTcQvgXQ937y9o4RG!ap`GcL zS#?$eIH%m>fd?*=EU}NqRK6D({gU7{?x={n77IM=<99RN%wY~8!7*jtq=UVV{6MuN z#iRr94zozL_HzsXjp~NliSd}&Qu%DamEjY1exn^Lr5yf27+V15YAT@lK9^GbWl6Ij z9j=y~)M&Pgzzxq=;v>@ZZ#nHEFgBD>WrmyoWz8h3^KESx;C&KNEqcF(9XBa{zozPU z5y7h0`MKmwqng=PKT`D~aTyd35S@*jR{#g84zw~?CpZ`T5#gZ(PW@x=f=hEmz@IP_DYt=v*y@fUa2mVXK!sKn6; zzl@xg8?E?6;H+@I$kbfhVi+FS&DL{{y^JuiMp+_B>ReT ztKPqkje+cHt??Cu=PSATuklJ&TgUC6XmYDgk4KoPz1i5k~QIb)#^2$3ukey$XLQId^}C2)M}Y7LUN5e__A^yR?zyLU1{|eBk7% zIdl@I7=+e-zN#U2vvc%|b(zq6wezt1i)njYPtD!+W3eZvcD{9!KE}V(SI+rgo%dG{ zBgYFEGT*0(W!Fh!`Du7n4=QStT z+E{9Fdpq;^aGpD#oNKSh9Kq?^X7zSX_oA`0^5xi=QmGdLbl3ZO4@V1s zqXX`Gi#K=^2P1B5jARb)G+={N;#bMO41(+3dYLw-g7xX^5ufNUy>*|W$4&!q zTeQ;EgAkWg*^WB@T=HSH`kjh)^4>;yBmg4td9ljm2!|5PgHr;|%m^c!^#A%&6r5{2U28J`s1ap!<6g$17 zV2B+;9^=6=<{}64=;_NWWDaOc4C2*b`hh*R>;R9jAd%d)4c#Z34Gm;{+O^#v7+EvgLD~u!~r*f;$VUy;#hKt?BE8o zA-HWv>hG@Mv5K(OLEU~1cjY1E1BBUF?OCO4cQ%oV-hMO-9OP98sM&Vlj>N>>C0OVM z2bf&%ymqSYUc+7c`_bRG0phxtU6_6G*v06xHe)u&2Z)&t!xA@F_svJOR|>7xdAz~* z4mR83Ap0GM%dp@51|z47_3Ru#TGV#zNYHC!9fQRf`(9y3S-F~v!3;hwsOk%U6*E=- zx3e5I{a*Z(^i!^J>Yd&Qi6X*lxlCnHc-ZE)$^7Y6z$xN|(UG}8E^m6=*Q$)0?5J@o z@xck2n5yIEAG@swce%f8p4u2wtB@U9R^FoT|A5EX2In6jsBvq(5us_=lZAS| z?usqn^k4CjM7xLG(zrJ)3@zS?t|&gZheYf7g_EBxnhmk|U%2-^_^9nKo>5=w9?Zi! zs>=&blLG6?#(d+Nv|h`cBLn2>^r=umtkU97%Hj&7OQUGhux;^aS;qOx=JQ(C|LzC5 z7&`4D*HKOY(b-qJc{(dZz^CgIhSY)4W$w=EGx`Qc_p3FImvcYb zYs*ZqCI;hGpO9?NN5IR&`0BT!o`5mB z{8)I-5kw%N!v{?Nw9mk6M)CRUHMS}H6^`JF+1{(tq#?_E=N6NXZNO=9;By8+=H}yV z@HupL%Sxgl-2pA>iN)yv{SwR5<^!=q5d^X}DfUp3-rJQXYZ})1#;d-hz(-!}Iq+ta ze>=!FBr6+wZYQ1f?aA-;`ZfGia6OO=QxDOy{TATad9V|vBj2gE{h1~Mzk%AvLfqi_{pyNIqYC- zZs3I&ByE`qIF%-^rskv%O9+U9E>qSSvklb!2o(w5Ow`#mmmmJJX2+{SNoH-I9FVj| zhRviuNu2qlUvP6nJ6DpM-K^_azJ4r&r$WV?akNrJUTcWz(r@~-#?JQPF+geyXocB) ziXZSo(LB0ez!iTL_gsof@v?#Q{j8zqrumZi#l0h+9kmSa!ua{ascU4^V~SMFui4rN zQmPxk1iU@%#D^fLI=0nXM&j?&WvpE12Yk~s5L=tiSqT*ksvsHbPUbvMho4OP8Md?( zHEBY)y{Q10iwc{rYiBsPrN)EHNQWioM>=H`JvQCwyUDZe-Gr<@be1Z^TD!AWbQ@Dt zqdUcnk0U~kcRho>&Q%&RzjvhMfa$J~Ay=;$sMv#XsrVTvxJf^_*uxG%l%$x5Z2#TH z1g0r1sxb7u;w{L$PGHt+8ir<9=IFh}ebeN^yxVg4l@+Vd-le|d4Vgb|vem5P=^aDW zP2nQ+G|#c5CG6+k@?+C}&5&LUA%0k%qg(dPwXk}zzX6E&oou*K8*k1Q$LkgdC05~? zhf9ChJCd@g8Nku!lM5kS=>0{`qqR|CpL$qC*Uv)k{>$rY1RaBk59b4))quwZzG&4- z(x1B0DWvl?$XYK-qG9;049%T6QNj~_zVbv--A+&8)NWwqOah@K-`>zVGtOn1fm4-7Z7Xgv|47yyWMt))c`5_C|G{zCVV4bkOC`XbqjZqyasdl+Y zM94?{Q6GY-qWFnBgKzuDBd^=sejM{%=4#k{d~U@j*HV}#@`dzZ_mEI4NC@@r#^R5u zTIL|@%+}9w`wm*vq+ba}P`QI=>s+nXJ_vkJ`rPyD=83`6{O78x=rp3` zi%KN-Ztu2qMyyu&E z6D+YeWdc~8sNF+CigyT=qm)Eaqq=c3Ch$JQ(uz+Gj=|+N1I3r@ayRF?oH;2P+Dmn~ zZZ<_{Go4upg*p`!f>mp^M5g}C(X=-YF1XnclY@=h9sd^VH%_0T4Z~F(ORe3uYUr;n zfewiQFlx*q18d1e+lO{iS>GV7k}sp+$Z#=QiWQojRExOq@*jer!_{rR$WB64Ue)Kp zh3|u62aL}#iTn6c6=XA@)Cwz-n3T=7G=r_Srp(8_qLvHPyQBdI(wN-wCprT=NV+uT zNY9SmB5NxPH;+M5bIgxVMT@MRIL)FXZ?W-QP5ovrrl^dHgI@kVokv{bLuht*Xa9^_ zn@&T>8=zw)xWrNWxFQSASYK=2v!J`yB77=18gf9n`)dI-Lh4ANyYEF|@8oN8Fp7J^ zL06gF&bQ%gHNxnqwDr41uw*>sQ8}S$5ygS3qFwdR5hZ?+X0y@uYsuYQg!P3`KJE2xV*(RNYbW{)1{4diq284UI*;FLA1frZwvfP?vCWL^ahOLds(^F z?ayJiUKKR1niv-N-6eYI+AQlql3)#fN(&W(K(WXa2!~Pg&?!>v3aB&Kb0d2`+j|k$ zI#W?XVSbYn4jB6oNX{j2V)Xq{hkFq4sQ8~D;Q zdPTkkpOn*vJ1@|2c<1+By;X9KG&q`woXx0D#=SwL_ufS6r%o3}1d1cyGrwHyT%MEP z{^|}F8*sDiv#mB5)DfKXt@K&6&EQFq5(x3CIMR=P{!yAbf1S%(tAZiE?6x2FLf6R> zqQdIV{{|}5EZb*;DPH)m;jsW{bDUz`!bb}2U@dRJk!x6+dO3f03BeW@-5yn8m^TI$ zW!b=w#Geg1gZ`klpS*_n1L^awYnDS94{vqg$) znrqlW2w|7cQ`f3I(RnSGg3n{!>^I1ans)sy;C^eyDP-i#sp)wh;>wG!;Sk9YyU~(b*vnN{_an@fs^%hvR1iqC>ADuQ`>j+ z*@Jx9S`U}ur@LLX0YkMPnnjk?EYkU8 z*0!z$(hr3gO?VykgO)R=@=@tVbcKsiYD>VN?RHJMbK0qLv#e`kd5>6sP&3y?=j`h+ z)o+#n1J+ZJpAd=(8*FiE68SBY9)o;WsaZkZ=ZfG1EJy3*!~9vc>Ty2&w+8Qaw9iJLx zzkuT5s#|fGu}twLKA)nSww4__ZGGSNJ{V|1^SWxzVrq^aQ}fh#ewDHbir?B{nFrc?vQN4+4=6SSAK_4pH(g1Qixa)AN3BDT zDwmbU96X&zRmUZ%h)$mW@wWeBKN!Hmi@}uP@69(HuVHI9*Ye@iP5zj+$`>@f7}%Zp zEG5A+3t>6N2mDIAuZsxUEAQPIyw#<)DB1-2IFA2ZjTsVcaji4bM%=}T`#wdI_7)Ow)YPjGZ8`YkmbIJT`naux^D@jd@f_3!cbR;} zS7Kn(wQI#5@Qv}ARF!@4GV?0dZHx4*tFE}kQ0vCK6z6P6BF;Y66 zb3RwY^~88^A`BiQGVh5{tqC}AlR;ymNs^!P*GbyM_@%S@ou-5LRI-@n=^NA1kbh?kApT%8aZ(fG?!rC?=1*xksMIx zD;3b{Hp!ja(8qnxUt?bH2+W~L)|wpZjhf)8wFpLd)<1QmB8g@#oNMQtX5=p+QM_c; zYc|Oq?#DhK4QR!$E^ut#E}aWkXmc8aw$GApe-9}Isl87;0a$sMc8X;m{;}-ncxnh^ zy$S^=d?xPjXd|=Vf-2UalEZzOri6j?9X0jPFBCgYQfayDaZfpyj%8w1B~{D~Hm${3 z`Qg|*)_yS%ytCZ!r+-_jEv@B`NSG9;a2wxleT@C^`xEKx^C>0oz+uH1Xue06Ql!dL zs%`HzxK+AvE^aLxnps6TjY!1_*!ivDyibHxGZdG=*(65XZ{6pu>XDu6fP1lXpu8aJ z+^EDtAa6hKor;(GYLP84;QO_1(;=nf_`Ig6h4dH0B%DvSrxvt1XTaX7ZgS?ea+T7} z0g)6!VuEI&)U_fLQ`5eo=oJfW%f(MS#25{%+!;J~+}J$Keomb0)QpqHVxM*CC4kG_ zZ`YkTW~lWwA9gui2uwNj5VJ_}_HCp0(c+JG2z#Hd7Ed;^IvJNy>AjpaB8)cD1rS%- z3se$B>g-vX+b^=wL3+o0n~{6T??8@qh~N@J9@mjCgTMRg?UgwxoS!Z4Z4UsumA6$n z2|qQ?O};$1&0UV~iRYib>nppe&2zF`ehG2Qn`(r<_DvAarG&lxn+R6Or`)Dp$nM(4 z$a%@;Out1v7Uxqf(_v%rFW=2eUa^>``rMD-T1%ldfs+K+-kvcoEhMhROp`ys)48G0 z1$e^z?4|-Jr0$}r04SdZXq~_`_VFRQ9!5zyTe+O`8wWDnqVNe9d+l?_0~Xc~o*SANbBb|C9}X?Gtqo@t_Fx<8x5xy|mP`@&nzFT+b*&}61ADUBAP}=g-OOcO zO=mS|{4m#Vz(NRW9G%7qsKVfrADN~#$j;(-fBQ}L+d^rQe2l%2Tx|5MjqqhMg{!M{ za_DW}{Kx|M#xe$KM z6Y)A2Oz-l&GzM-ghq>0ShBRiQo@*y>eL!U9ip5VZpJ7&vwtGkz+2LMqFLhg$MBYs1ax zoS!Q6`7Eh2K^I|Cv<25_7P6dOU3}Oy3sIR!IR?kO3#Mw1Wd8YLn2c7EuIssX}&dBKVF~1(#b*R1Fa!%9!_aP~@ zr<>cppt0Vz5eE8uZ|gUGxGoQJ!kQ;>Ey&-WEL|RrAr@Jld_y4N=-jr|O1bT2d8jVJ z79|F+m}+wF1pL6usAfag6D$W%lJ*Maa%vGD_o_KfLVOPLGU>l8T-;QCes6N7KJQ)s z+iE7@Q4d)JZt`)n{KQ_U;%C8L)1PaRRg`hzwN=)H5cg(ShnWEP<_um)+d-f{4K>GA z4l>9$FBG{^EX(6s902Tu;}-0W66$lIu*`oEktsdcM8w!wO>}7hhANI{URcZ{ik{(J zQ;n;i?D}>5N{_fq4e(}}g8aO%H?RV}Vi3TwTu{pkQnSp!H-5zhiYV>Bei1qQq9{sD zc1NtuKG0{seZ?kfIPH~(xf3G5?VZYTL^KAnNqGz(IBcMnKBkW1b`;H7Ua?HQ?rCGW z#6)-I>yO$_ah`Di^Y#aKF@jGT`7$?hhFVnlq|x^x#5M4Uy3Ogcvo|gesHMLx&h80| zaRCc2o`wtyFOtAR^*E&zhc7!}=u1WQD4ZDLk!jfL*FnQ7;8ahWnje%m1t8=or*RTP z`^>nJbPnC1RnyZSNo&}La4q5PMg-$3iVl-1k7c3}5n8cFTPB@ji{?sujIRFXSuEyt zL$ubi#JacRUisOA_=enuPc?T5O&I_ekHf2oJ?cE#cFVfmlR@)=>QQqAFk#N2%vjd= z*5T%65OBjBI1YR8`q?a^70v`L+@;#yrrNtN3LN0B1=dDy*#>$eEHSBP&FcT_BN+Sl znUXIq^C=_lAN_7y`nC-0hPl#F<24-nK|~qwPF0Q+y?oNRCdxe6Ec0kFWKgenP{Cv9 z+pF*MsTakw%ytrhanD_2${~emq5f4I>Hiq&WU}DCgsSr_8JO6xL)eYxxqDo+WM^;*8)JDj+c$x5dZpzl87%Z^q zXXzsTT}_$j0_l!!U5NHjBss!b8fD3MI8_Z1by|ZlZPY~h?BqTn1BD(sVa%8POL1q7 zK|%&tR!TkfPuYejw-EFjUv2+;**sEUlc4R+!xX%7Q&+g2p;`H>aTyKxBG$Z7w ze7F>KwNfFWO9N+}1cYFv5;wVj&(ktA!vO26kHQEv*GKh?1mbV`E%C>uFQ2-Qle&BI zB4A=S?r$b9!4u^eksm@f+oYYDi$a#?R5|@L`kqLQQm^NNZG}uRJF_JX?*uS4XrF(; z(@CfQdFib6!*{tWCi;P7wB$*8Vw_I9VN+w4MrChIK_cPHsQTN?7W!I>!!W8P zj8k<;MnHy9>4h;R$nzf~8LHoo+M?9ooRgeXtGbTL!%jfc# zPeqbxysVRByj#S#d=RS1?;#_5Jk03?3h3{U6VeWQq@-X=<`iqmm4z8G%pW}uFnvUv z)W_q>bUO3T%}d0tW5kyEgx2Mo4mKg&zhV_=-2TE!2Lckz#tl!BHLfZ~OQjgp>((}v zl}i0Tnq=|6u7P8a^sHKz{*v=F$x+?6G^m$78Hd^;qhJ>bH9geB<0kw5(D^w(9${T5 z$Vq*lT@vIenPSWp&(?s{l^X~D<;_wh0Gmac0BmX8$E!Cr;CQ3)N1-$!+~t%QQwYq% z`13=Ga{gM}bGqRq-#3lk-CiQdxs`u}A?EA)oC9KSLpuCo{)(gMB{_b3Hs%#iXDAA( zoEv2nTL)APA-Ehj2?p7Y`va4pR8kgdR)I3i>fTm;@{X%kdM<`=HKs7#d)mgwz3xmzeOwzYGbg9EFr|Uq~R`9oC&I zjjA~oY!EmDKej$Hfh3&jW=Un}Rx&svju$fX`JkVVw=7g(#`qKaVC~-${@~y05Ob7H z*?_Y`N~SlTP3;8pBwB^<*f6*U2f2`gC~v^*U*m6{RML6!@Ry^|HrP!^dhQ*7%^#Q| z{+$4t{NvAcH?!I6uNVei4GOSvZ_>s_M?kSRdlYZg{9(imm`&^MF!3S;zb2;sr!di{ zq6R?xlOOdr>0E`KTzeexqM%J1Lx+6o9)WAnv_D1;Ke@X!109eS-jB2A-3Pg*+3UlS z*(?J*6ar7>xEo|lHRl!$^$m^_%j&C9MWYTR<}a*o_5MKlIcw+IZuh*}!1?1tkN}Sl zxIF%8AkCvtT=A=0Gv7L)>dx{%^s!A!m`QxU24Y~?eYrHkqozf`xdIGClpEWC6Gx{@ ztil$zjH6D9KyRy(>PXEP@|6)!XNbsCy*fPe;xO1->*3a2rmVfJ)#4-}3^ZcRL)};P zcfeswRQK9b9mI`PI+s`PdR*Wsb8B;PK?9l4jK9S2n6q3cJ2CH!^_o1h zFqn<*1ea;&%leGh&QvN5D6A$l{eQrdwbTyqj_x&~6H3@S_ajkJe$dTi@6HRj;x_)Q(|#nj)0i zc+ul6v72zKB7vIY%sJhMAyRfI^TwmgJvq|QYxrS)fyDGruF8#YS?4Iy#dF?j9(p@< zphVL!TVHxtUb6E@GPPEQdk6YH3AY!?sFu*7Wh(e<-FVI^$+YZs4a!5D`waNmNM=O7 zhV_|LCe)Qy-_`lKjeFjsndX)-APo0VanBs41RNOI`U7G}g z6o=!)mIJem9k9Zb?&nn#8 zMGM~7Vfj9r2S9Y15)r#xST;TN>6G%xq3hK{JHWrmbTTM1qodnR+r)5GZMj(QQ++u{ z=;&X5zLSE#p4EnHh~dBw?8u1Y+LT0NlZb|G*yvB3e$pa2;mf7jyw$tHJA}Dw5kQ#9 zhx&@q>kCWE;NpPzBqFozAHsMZj->v;71|Abq3w?gQc1-(J~=WIDF5*1v=B$=qczIN zGapM*Js#y!hvd5`I0v6_=)A=qIG%=k|Ck(xK9%jcWA&@I{$e=CI%CY%Xrs}>S1@Hg zkBF)M4uoj-toZDi9q$YZ9i2bp`fg@IV3Zu{>;jGWk$L2^I#`Xul_HBHqARlQu&05q z5))yH+C-mG(IDj=uRCaW5SGOwD z#v4xv9;3ApJt|e8((?rDU1csS(oN%5TVnJMQ;!x&arq9n_kp83VWQmuxq!G0tg!>T zy^KR1p`~`aKz&^CBPponwMGP`3&Tm8(G;g(rlnWOT}dBp0*0Y?EkAh>W-+JBo`>t(f%; zEO|eW^Ow>w`2s&Up#Z5G#axX2-UMA=_QllDK)kM@mH63H*ITf=mrvnguN}!dvw~K< z&3wHCFhZ%o5%o;BWWAge2rSH|lflkeMopijJiS}DMW~oF@|CILZi8?Coa=ec-xhAV zf2@1G}#`t&al+ZW`e<&3ku|Xr-YZB-u zxI8Gy6%x*9J1a@Ik%BTQ2MOOUEXdOxfqV4|VoE9Y?_@UEXWiia*8UghsC4q_RkHYv zhtnS_i+iDwNyGSCzU#>R_WuCa0mX*1XWUc;ZPCJgJ9Z&R**Ya-m(Pu&3iZ~(Gg#sBRbh=3DoYc{;b zt?n^kD3<5aE_F`o*-y8G0ztb@76;V`!$5R4AdW`isYFG4#v^|gUo~XQ7G9a*HDtp@Bo!0t1VE|DHWD3c(jPGXn@{w@iHqTgS?!dhL0Soc^m~^@Dz1~<1wNs@Z z?!u{EmM%9GHs`Em;~;${Yr+92>PCu}V}{%Hmm7BKeg9Gyg#CvZE2EVo6t#cK*C2xi z9e-u#ie0+3V3KY*E1x0@8Ya_RyUkcHI2E;t6DFyoNun6J*}rK%Gj*k%juD5k^BvF* zK7bVT)4rw-A?Xs;gskWIC8AlKvh<+mLNsj)%b+ zoSU<{54zmWmb}VG=-rf*YP_)YO$Mm!5?REbzUju&MFfsY;dnqmEIRtK;kXfr-+5^A z#Hkrnbgzlh$u(&IJi{W{68*q}x5c0^dSZ)sO_5wdS2&ZW_j-`fJGu@N<`7E}Pk=+Y zFMy+d^DXia;yZTm)^_MjM(CujpMiRerz&&nw?T809CslOYGogSPg#?WpujwFfn$K~ zh3ae?-Tf#H&Nx0)R3mwC0#tM)e+GDLpAYTGsOHII1Z?64)!IOB+5J$gWuAVv^je;; zKzpK$a4iV-(X#{4+|K>(v%CQXHt<}3@uSz|tzgL#yt{{xKC5AT9_rwr8sz?zj5$O0 zR-BoGOdbEw0fyv+=<|N&du#C^gSV|t3+y<$SOn1CecSG1NoMFnc`?8cn(jYC{^n@S zs9}^YHlYP4_5yejRGN^)fmf_`?04l`SC1AYMCgf>BT+N*-qm)@R|~n$iGrWXL)I;J zu?%`Q$4(Oui{M#%2Kc???cHFlOYDpogVC zR_@ZI1+E)McX%O|+f4UJy4E`9rlv4(KYPGFLDN^!kHoYF148EdD27OMp5Y3pd=klj z`(0K@9y;L;1O=Uxn9oBJuEAmS|j(D%4h^mmvw-2ZPJSE}tJ zdi&g~ArIh7jK_E_&NUUvoj1Ul3bA4D@Lc=mwg$_=CV$Y|Pp%z|T|DkQP?5NgBdZxN zf~Qkq_OQMw*tbAl2tjJEzYh)IJDpkI+tQkF&rKQ?bZe%Q|C?;#2r*bm60s|c+nmI> z6Be8~_(cvBV^6tuElEHD+j#h2{4yZza;5Pn);&D(Tsa=W|kHRCUS*{WU0WR?@x5+9sl zBPOZoTRn1i7A&qV^z@eW85LZ|y(J&Q200m`7I(m+EmFS=fZ#-sfWZ+l|q8Z=c1tz8x<&VYJ!v*9em8Ne$~b;+c?I zSf0mz=URleXBool7#k;aj~?R^|1A6LpMuk5gqaT)!vK~N!g}S>{s5)NbPi`~*RC7# zYlZw9h|W)Lb6a-Y1DyY1LwUMjJZIyw(7%IqNrSW?`AS#v*%;z z&2aH=6^jP1?%S6@3i*))J^E`QJ$&|RiD#Os;ZNcqjDUldWcokaH*NB6?|{@bBsy(* zOgtn6=++rnIa=IwmC)Mj85{R($bH|7q3aFQTjb2?dKLWerdw_8IWrpgiox`_B-Rq0 z=FUqV&xt3{=Mg}6{VhOxI48|A@Gso>kKrl8-+$g1M zqL#-_W7Y1cO$gZ$Y7VNRl)$;~xygN`iJuJ9s>&_q6ZHP(!1Q>A!uPBr@hs1~RLZE!>9Y2*p z?Q7F=DYJ~1zfXVr>G8=dCD!F*h7q>4TaMdq~~=DXi^_7c=%229DnJWUi$I1mE9H5*9T`*EuwTTeaa@Z z5wojINjJVvz%xKJ1nn>Wiu2b1%ai>{~q_z~Oi)96xq`#OQ~Z}Q*# z+O8sKKYZUJ{ytXJ#f3$acSkW*jj}!&lKXk6*)LP(#{W=BQFn_dIaY%CfWr0{K?{?D zf5Tn>3@@y?-A^H)luTek=|SNu&5BkZyH+mzBpsQU^yzyC;Sv7nUorzd3>%kpPP3E) zCoGWGQ!V+MRVK{iKl2iTh!yOj;Er4b!1QBE8A1Aq8P~G?V?mSedM)70?MysjT5d42 zn}u~fNyNgSRHQ6&(5*BS-fhs=y8Z7q^DmmKQcd-7@!US;v!2ppdz&?--+>egTXamHn4+RKd3YAMEopZtR%0t*WbK~~Z zI_j=}!Dpd3=vK}TNcXB`c;UBGw`bt|M!gKH30_9D+7~wxa>F%a+rz45!INtn% zEA;M?KJ+gVrD=igdgClgw{m>;O4yMcQLu+l|5<3s!@Kc#C*QB|uXl z2upw^glZiE(*HElia6?!25n>3xI8X~D;aIA>j>ax(`#C~ICZI;P;X5jLIMI0MpPnP`4AMPD@(CvZ zmL5Yzldg9Np3T-TOX1xYBJqSZnG1pBk()%dTWqPI>_^Ho zd+IcY1#*Grc~;%r@&+Nb!__@h2_kYsc~jWuGpM5l#-n1lM{8xh@!eIdGL~e&_isJ) zol|i{Hg*ih|FOiHFZ?>*%bwxUbsk$7VhuXXSNeO6}K z`*a9z^&AS;MmSa(VHs&D()7H3EfI+N~_Lo1(bzCM<_$ml>P zPW2`?UEo4H#t-(zug^dG^SZ`ZKVwwOU@2U0fk;p?)mKTi&?Gkt>JYI$B@ zA#~zX05I(Gcn&S<>ky@guR+g`0lLhmp)FbiBVy9Lk9jxA=Ub}?Di#I?^0xr@F%Z|=D~FID#iYEbJ6I%BOir8+3+7jXudyY^!LqKTQ z=-VCscschJP!RHbR(?GM(fAQM$R3%1!Af?7RazO4D3A^u7vm8}eyuHl<7l zNoF+jJ?3KjgyWcB((5{GRd>Zaqr1_Ex*P?QF~O2X4syV0E8u*l%9MBR!Fr-BPDRsY z460Gsj$3<=f4^ zC$j$Z!5lHS(I*=F@l!KB-9}i09YXX$tjS(E5%y7)wS4Q?G?Dj>*Yv_PhOcpFJ-se2 zvogp$bDC`#Bed7a$&Ijjb7rM5BX@F<7Ni1lR{=^s7JA@R@8SEdvK&4ME}V&9KEBXC zDp$%h^0KnCCsi{#*_9e>cu^m}HExNe-FAMrbk2xWF;EdoU+^bzP|w5zbpf^SM$g3# z6BKkUgkiz3+s~r{(;vQL%FnhOzrouSOg{+64F!Oxe8`F)%Ak|h=Mu*GKi(8fO z)32EVx08cDY1IT__zz_&W14IWty8QUV@9AoH{wA%?6O zgrj*>ZVUUu#YeMBqtacq@_|Drl&`mmYiWdaw z@23#2A=qPQMeuwzjwdJaw`JS)kez7O9CRWxwoA`lS3^T9T#;?JX%^!WSj>S>JL3nK zd7FM~M4ES@{qF5ZiWL)a8n5-EM1qPl4?UtcScnE0`y`&=M+pYnr_ErnS(s2MK!V2J z%e+#_u^bn?mJ0e?qvBCdC(wI;{VPA**cUg(3m81YGn9PthsZN+N@W@3mRH|yx(~jl ziIQGT<%#K`f=GE+KO%VK!cb-Ixh2>4tlZP#Di!|zxL)4yC;4~@Gw(uy81xk@lM zhmud)wWxIeZ57qpb({aK>NcD~|4*CN+T6T!6v?QNrA^?oMlT9T)Ij56)Hdfge@~5e zL0my8TrV#YvhZuBRmgfp(UM!o89}s%kUBngI<6{Ov1)##D~X4lua|ttqRfhw<1A8p zqgv922Uzk=L0-CArGtr1_&J}7DqrO=l1Itse%lqdvCbZ$p%zVT7Ex01NV9rSDtZv< zgW_j1GDNZL!mG&7-~u7nLb+^V+VtTC^Kh)g6Mt0qNq7O4HX~eJ-7LQHCCyklebz27 zSznKqI<#IIhvUw-L8~X4C<1}Y(?OImnxxkBPh!^i41qANgc9yx|H;VB5g+46kL+F| z%YO=yE+^PMgjA~|u>VLkvL9+;iIZHgg8}sxkUsHK95vr3|6ZLL{II1Ki?KwD(Z$x4 zF@GDj`%heB><f>%QF`oY*r^tv zbnw{n$LX*&iFv&Q#Plr7ULm5x^_0W@*2G0gbK&^W_0dqf&r;#ZNVldjQl@V?b9I2j zZ0@R#JVMHG-PKG@@rB{~CqCY6aEgmQK@mpZ<_o*STC;zeI-S1tM#>Xk?uw&yfNCzu zAy(T^J)33oOJXi@OmBXDaSC`mK{-&UHRfmg{e1Id)kn|Zf16IvUtJ8H;eDz~ObT?r^)K;nTvSY7Kwuyj8k3xUbu;y~Y= z$z-El_X~uX%2u-~Teoef;^rGO<1+3-i3&?6$x(Uvp?my*wb3~KkU-rk2F_RsGm=GY zCKrohAe~crqtVYu_!E)deDDa$LzWS0A;pFM2wV9Qb$NZrN1wxkLo$O;1$SQuWjX80 z8}0D;0+@|_^oJg@v=R*Uw{Qlqp8oR_5^Zdx?IZ)1M&aHjUtsBdtjrs)QU^!6&@=@y;JwXS|(=5`PswU%pPK~th( zT_s7>(g?cL)^;;7UN$G2{Wr9nR99h7{t&qjM$*HRz`%1%H24Yl&EgP1?II3-dZqck;_Za9Z45D$AWFVvFGnGKzULw$2=%fj&|)6 z`B)_-m4DEJv?J}r)7Mq=+a$+G6!TUj11G`h%-u%zDEv*|!ok^GvnM%cJ{*w80m5l_ zn0#%}X(WP&6w`~>#5nQT5cSeO{}WQ(z=M+@FC|+06qr?_~+;V|Lh;Y=lB3VoY(Y?gOdaJ>>R-7^Z-6v2k_zCr>_lG4&cKhw|)8C zIe-t37WL)Bp06*C*!0F(BOEHYxyUdb<$cZVWrFv?86w*!h4ZW~e;m{Gsy_N~abl-7 zlznjS5zam0)dz>Q9$tNL7=NxO4t%&{--i!4yA>*ZaZc%Eu`fCO_lL{(5WxZ-kx&-*%k)Og~Jl8uWX#7a?Y8xA8!MmhA=*p+WOv} z>jF05PLuILzDfLZu4h~`7v36x!`$p6+X0!iZw{Fkk2AtMs3Y3Tgeu+s3D=07Y%<~4 zxu8(Hv09Y-=)<-3YeHBq21wO*ZJmBS$nf~IjXWSELJfL9Qi> zPZ|yDrOa%yThydmpKIblM%a*;PqORb-r)sRvzwY@qYk@q<=1c`yKdRA8)vs?1O4`> zi?re=I7d~v6GG2KHqhAjd&UlDjyzn^N1u!0LoD~fIi>M^ahR=_rTA*;q~=8P=VOia zagC47deCSpFRAlh)js+V1AX-&hxEl+BR+l4?#~S1gIwNj`l`|$*YAr@U%SnVYF|DZ z#iuXM2Lt%rEk4^61byNFyKNI*9~^YS4t;Ro!>*?fPS`QKd>|4k-9Cj6wJ#rb+5GQg zF5P^Ho0S80i+$sO@n?JbXNV2J*{0gZZs4pOfb;H6(ub#acEA2=Zhe5Be;Z%6)K{weR%ggFeRx;PgFbMV~iR`{*-7Hdf;y*BJZm8j-E9 z4Zt}vzy>FK`UhLD?8%4Nxz>}>E4i)EB3(Y{+#`m49#7VWKku?DmeT z$tJTmW^U+NK^N{18cyu*&WY^MnG5zvE__YG&}{g?)(71+l1X;xj9DqXKCsVW3Cu$#kR%^WHqpvF6vR#oZeeK2^?aPOl?u)}& zXWuhV))C^TkKK-Id|w=F*4IDSZOGgvm-f+zvo3ImZ%T}S?l|BXGXIY)kzY3sJXY&M z*hS$6M&V;T&IwIc(`Sy{0iyImd?%dvTfwd8JHg2T6z$YDGm{Bts3O!hzW&n$-+6RX?K%cD@ z*H^v>S}pMD>(e1PCL6f9EWK<)_zb}z-mb~1%ftLMKXvN^A7a6LI?3E-%wC71rpkCe zeb+|(vRc(-gUdKR>=B>Us6IHXrQQZ`8OI0Nuw56Q4Uln#`F}x`Jtpyu#TL?Y?e^*< z{uN{NHo`;q&3vfuepQ6uA>qRxeB`FYJ0$Uy7J8@L=*^|2SHNGRYW$%?Dey;cFKxnS zA36qq^h(?&e0Yw*AH5g13IEb~{-c-UHsMdefAogjCj52dJjke86{-ss_ z8z0`SrYX5cLz{jc;DGwQOU?C&_WZtAb_QB}E`34^NkN;E0a#k^x#R|M~T4Zm2IeAmBs*pExAs+lvWm?ta z!6?iH`7;IPSt&nriBih{_taO)5BJICj}H(#O=EaV~z4>`}Aln4jGJ&jX&#zqomRM=|@RD!oS%T^o_-_(N%q`<0Ku z%#q!y%rvmrno*i5&kqg;mtB+;mlGZ2j-Q*=2ZUrk|ke%wWcuK;5T5*V%%y?BRURU=g;lnl_ zCRIHaw+U3Y;>YUcLiE8;Np6$(Rbb|i_S6$! zd+NC@+c(WVx<#)c50LG21@KdU?ujiC8!b$}b>X5+=88_hZSVTXgIVVt>R+vzONO15 ze70YV@C@T(9eYD7-d2|jy-HhoogZ_u>=iK&i&94paLyXd%y@qI#^ZUKI}4f~??eaQ ze&Lz!hcwR1!a9LG%y%7BvR#nF{18A6_O8Zz9X#Gf4Q_*#x_dliF}xVNRax5PWR8$u zDD0~}%}YtY1EIePTd%LCUx{ar2xnhpS&)-QRCCEN#-o2O8HSCoWPn;3hQ1#p*t*c2 zVIL(OxbeY|zx7_03jNHt!2ECSL187GseH}FC;T#%D$TQ^X?6kC|280V%)|U|1HL6Z zPjhC5hs$EYCLZQxSyjM1&G!qM9&dGl=k1BjJU{wlaShL-G$@qZlUq|*S1e6oW#oJ>#Y^5NbM5npRKIgN z$1DI`2DYx8RdQZrA!4zfIS_{t0xwoBX~>mnIH3^#3yaim)KSN!LI9m zPW~5!YueF5c68vM=%I@|^qc0`B>v}uJqP;>VMNx5XCA!7v-%DelsQr7L zA*DjkPd8M+Vm7iJ-%Q1R(Ld!p&}|Q-+@%^6zJs^*T$MTS$U0SI$18B7 zkEgzL2)gaIM!>oznXp}3wZZl02(dm|J^$hYgF-Ipfd*FUk^a=%HD<+=_7j{RwqN z&H?syeM0I#PSw5>4OG5U|Fr5a8J-;#2B8QRsc?kSJNl<~s4it)<><}2b`uY8aI~=N zrA=e$W1VV)Ek!@_G|^FaC_EoFFRSu0dtUw6mN)1>q{@8l8Uvh+bwzbS?Kic!p42*X zTJ1M9xsNDk>{t6P8HXPdepcg-tN()j_2+8pTOs&6>f;*oPPKU^44%+jrsD@Xw#fkh zdsGi;%tg^-+(r8I{Vvg4qvJ{)FN!|x)7m4vrQ)lJ~Is=7o4weY{kFR{`<^ zT>B;O3E^D@E*xH_%UREVTe=JzwtFg#M@`C1qzF$yXp*H%xt2QEUadT zuFA8oD^*viE>pcHRs2ppCjxJ(u2AeU{%zH*in|Z>eVy9G(4Eq6zmCMfSsjsQh1wT& zgg!cLR9&qKedt2xl!RwK&P!G`Z}1%BIUU!iu2y@MD&tQnZh>D^8+~}e^hq@?sqU7J z(5D|A7{~u{5VQ1C7EIzsnSYQyKcDo1p}r&QXEFZF@mOR5Lc80-(dS=IAuzojEG zAJYeU89Q81oAU^4xI=ZNVgcH1b$O99uq|ULG7=JI52^aZ1Ods>IJ49Xkr>HBe2aG7%l)OTFYI4}4i^<%3m zf-P73s@i8oV}si8=Ot{&a7pbQs;gCroy+RO7TZ-%=sW&-SI4(i@e}Y%s%KRVhTYBx zezF+zw)&07VYRXUVbv>Y8=W`QUZMJ-`p@Wioa4vxk!0Pd@As;Lr>+pkt5O^IYW1NP zvhGy9p2pylYpVF-{|5j7|NnRaY*I^T6HyesZBpBs{u?z^(JuTJEfEyE2-W$#Nv2F@ z(l--nC^)59(^3eEwkTN8jVNxqbmP_^-Ke-Kb!AuX#Jz$-1$CjTmTo+Em~=Xlz~xNt zJ@4N0?mHQ3qA4OeIz2q!1Z+n1A>6#}+rqO<*Ykz#$x1V|A^rT-jT|7LrGQ#q@f~$c zXkLOQ@PFvc>IZJak>nniMLdGq^E^!SB{lN=_sQ4*x}r@8xp zU{(uo+^rPb=^noHjbrbp!%7!0x{_`fdxOhVAJ0Ge*pN~zPo(GtO6!vsl7k_o9~gCU zN?45N$c|vz;%IhhION6mqB%vib7ves2JeO6D(dA)(^t!G7d=FJ;oOo{r}f5YYS}P^ z?4|;;%H`Let^uovff$R0`6Wk&2I!$5C{J!}rg$z#{DGmbf0CG`%C)HpT=TM2UjxsX#|bl9{jxm2&UJ!xMM6|Ra}v#Sx8$v{OtiNth+hd zQ0VD>ltp=9?eCR(yW{v6_bkk^wSv%nc7ATxIkD+dQF2OB&82NjtQa#pTpAHJDdx&G@rPxtD-Q)npumm&3|{15*R z4OjY~wkPsw7hbf1hWjROGNo7HN~HX-OeJxZKwT+^UE`P*bFmq=ItA`gih99b!hoJE z4pFS+c_br_2YqBHW;&{-s=QhdvSzX+YLIkzCXQyBou#UDNU|k{#?O@C^5sza^x*GS zs`7Ke_WPRdmO7{RE*F9qIUbw2n-^VVGN11~&^n>n~3%Kh7d;#zFx3)e;S3~H{ zi#`kM7JF;GWT~mBRNmZ&ly`{diYUM0zE``2I75EsP0R%59XU^d6d zZNE-HJ;@u}FE_pBz4|M6x7AxAiSbhCEYvwm0tP!YYm$|Ar9IhN>8rNvczthg0zSq~ z6Qgmm)};;mY?(58;$>T--t|PN8{%b~|7-kEH{?}d545;>mjpt$XL_@N(n9och8I)^ z+^SiaN+Yy`@=T-~`;}--`M!kgU+F6pfkAcI(z*Ud{0Sn6KIcz<|HP6{Ff0^m;m|h2Uso!P2P`QjFLAMj{{FW4Q%u~oRQX&59w8c+d@~O2de}Q~=zN%S0gJ%b8d*i) zbAA8lGnS&m{&mP#uNH4Tqm#tn&X94S#;ZAbj^Z(7RBIVrerwZYo!R`7@u~OR#UUGI z^mI4h8@Qrs$jf8=KN;J0qa-4p*IFaAj|fM*U8_2qCU^S9u8 zhGEs?X;TXWD?e_zEY<{ZL30EKPtFGEQ#MteW3Q=_-hT?F20@+&*IxU+X^e zKyHbmHEE9G;vQXc5P;KzxijyMUcdN4t5I26|%vEGRqx*F5uWFc0;9Ok3I z1F5JN5UAPa>^*Woad>V{N$k|jsUdP7+GxJ;;(JSWR>)TMa1WBZHa3c=Sa%m5uek@8 z6GL?3>}s>^;g-RsT?uo-y(RUOh+#^uv*Wcqi&t4os8~hU?=M{Z;ZmwZK5-$Ou*V6o zJ@Bgjj9H09JZ+@m8Jdu~UL2?7A=sCL-N>e!sa>BzSlv<4Z@!JIu;n4R!X*6L$>wQY zy|UZceS7^!T}^si{d>h9FyFYRMac6+o$NR>tQN|-bg{nmbd{^b%(;|Gm$P!+lnNu7 z0_q~{+@hT&sB8ZAXwu2&iW1diywrKiJbjd~w>N)FcN0W@P9{W>6y;r70@R-8e5l=w zqbu!czf{K?2wHp#Boq?j;C7SNsZ#6By8V!DgButg&dI)0I!JXk6yq*6%m`(Fg#-S? z#!-u|zGrNtjzeV#ZqIuz5LuNze0h5IwLT!Z`UIk2wf?M{A{0+OfiZ@%JjU_Pp+oxl zD+`CJVLJHmQzNS8q=Rm!4<}Ino~2`t&_Wl;zfpc)sbxiLNys^i*A|^_QI(FryS2um z=ec3t25iIKz{6)98j~;<)EFVdi;hN3A2d8|6E>X2Q!+mFQnV#zd@T}5b1$LG|0(*h z4n*2w@VJFF=^t0NX*pz~efBG3V(04a7u-m;CQ2Y4UFAF>>^u~E33TPWLh#{uZL zx5C>KI6Z=_opvaflb9D*$etH(9G;OnJ%U@U3 zJKJt`cXP7YJnj!%AK2W$16%me*BZ=r_dM*gUB)uL+%ZlTWV3_f)9%V9%St+n@ECx4 z0rt8Yl9C}y!ujp7cns`|G?@;OcyzcC<^y9^-{GIAfMIcJwf$i=fYz}5tnD>xHb9Ur z=RQA4)+{i#OU3f0KK9;9cQN|~xg`{&F)+iuy3UJT3N=pc$A2L&^tTs`q zyzGavi693`{JufoGhaj|sYu#KN2Z?x(&;uLd<^Zb68pmm3m-j0ThzI(nAtt`o1#kY zH`TVs-?_SEO%QP%#Wj4+f_qL&`NyJHky~ti%R*kQ)NX1LP*ty7xO!z7srxIg0+#8w z=Qq|VfKg-3Lf78!ppepbag|zWpr*k7)2dlEc)Ml)5MA^bQjX%&_EEr)AIrkr3JOkLsi!*Vj8X01Vm-Lu}_>99HVQ7ZSa)NI*+$+endhgDuf@zUpe zLiYV+;mZb!rJ=AFTKy^&9ep3KlbM=94G$6%S4ULlny@`mP;{@Gc$9nLlP7zQh5Q#? z8=WQJhk#3@uf9Nm8%1~>ZkB58n4A|})34b!wi2zB@*UOF`qMhEd)HHO&!?M@hv0UG zYa{;WZezjm4@2>(F#uX|ei?Z(49TA`yap1_K#DVEZv>Q+RJMt=^$kF0>#5ujNE=Fg z2mfUBjQ3v1u8bI3ZA6euqp-I9o7#b~XDEvv#D;(>ihMj^yELO%&abU4dDAg^P{^gY z1Y!{I-wDi4HeK2<|3e>);LXwY+#9VHrQ5i9iDw|tA(QfUOb$-{(CF5Ik?!w>2^E?YiP=L*>-fy+ch7*8XQ^?ERyPo|E54(J*uNVuWH(CsZ9&z@B&E1k zP*6AKvYO-Tjo>v%((|-lE1kU{`6T%D5Buo9pDG#8LpDP6StbJMI;Uu@-GA|&;+7|miD?Uc zy1hmUxnMPVT*K0s&&?X}zbkTKEvg-Q-FJ79{ke%pYKbaUV=_8jO|NRkqfltS+yH5q zNYe-rgK`QMFJ@Ib_t;a0)^Z)XD*0u{__*w!(f-CrVRpfaXtn8@E0`j>h5Ug-Xhod% z?UWAFXgsMDbQ$)Wi|Nd--zu=4`PkKCly)71`!W0dD~|X7uIBs+A#^?-W1k2`H2-SL z)-?}i8xX;m^|L-UP{|@#RIp2>Df^o8HTa`AIg6c4Xa|t2wQ;NmKEvS%&_+8?OAF{Q zB5TD9@&WlKqZ7Qai|!+v=4QQ$=u+3Dy7zNI)GXcvh|TxuF&P*NSGKkmFp2RY)#?A!roYvBzG$@g?Kj)knlf8HH;ag=!v+g;v1T2nPm1))T#AP6vALiysso%#n*D=TS$MJ zdh-_*6)dIIc_Y~(XKlnS^0e3z*-;`#qdhD}w;kp|hasAKvAb)tP4c1`@im*sO3*|8 z=7+MpR`1i6&3EoyYK>O=r0(qM9Mu{?`9lfcclyAi7IF6F=vfRk&tl zH?OgL3iAxs2Q!gPGz^Ez5_ogQNW)B~M=WOfowk(^*?Y}hP0@chBuKH`5v!SPy-!0|}#lrI_zW~Nq%Z9JB_!O<0`RfF`q~WvLq!#LqrG)vj zwCn3&d&!TtYA-Ct6H^`eQRG~!CV}}@v)=bq+-QxNMGBGRFBn~Yq6n*)Z&&~%G+ifY zYC6`Bhaua&Ig-1eQLV`nB7G_Km*cJ@n-7kOSugkYRSJHJoFRlKPO-&+98K4rGcg6+ z&3?+OknGgMG#0+Ze!w;hCF?s{t|CuC!W}@g`*Q5TY^^@pszpdsY)y#2f_O_BG$tox zZVVBASrxU^&f0aZx(@2wYn0ZjHt-YZ8X^W9v=YeyeW?>~?(W?IIZ0 ziHLI|EhL#m+R|CkG|U8aF!&B&LI6%Y-<_wf{8bT9aloVTS8M*_OwQ|E;n_@QW-@_p zdHLWd<9g3Jv2rI*r?~2~1s;)`LCTEV9@! zi+uLfgn>tHQLL!;aSfaAly{mtZDXT94jyUZ#REp#2>Ps zb@h8qnCb9eSF#S-P{i#A7<`xV*2$w2zRj)9Yl-{;Uz%Y=Ke%T;BhDQcJAN##vf*zx z!t1KG^@pNa(m=SBk3Y8wze7;sTn^5WCw`SlYpMdRDP9kHGBXOz_t_H`j4mpOK7Z3OChqVtoyJ-Y#jGf={ zYD}3Na)U0%TlAM*zEM(+3=*YD7(b19RLQNK5%yv41{<=(?6^ zT0`BMTlud5I47#-RjgejzX{=1_Mu6(Zp$ah-BEz0_DAv;U)pRBC@MZQP$=+}YM(B; zy2N}XON48lr@3yMj&*C~F2gHCREeYV-Y$0fX<<%?w_5zr6G_fa`(}N8Mk~5p z^u!J-|vd? zT1pzFCfLr{GjCS@M3b2-dv{5Pobi&rq-w~V5lvN^WnIN-Tv8zWJDGL*l?whYPWq1! zey?a@G)}ZN=X`CVAA)6u%GYGe^)4`FN*7sy`B~R>C4}R_hG^L&u7+c4vzg&%dP~#- zh9=-poB61sdS%P+lD_uj+DN;JWzeWCC9FZ+1|v~d$;^HFuCa4w+5=Utk!aG2X@_u7`49}}#r1S$01Ow)g5-|Rz&Ki6NnvAQGnbsBT^m!8HK zEV3dbx#pl|I-W=R<1ze9K=@nzhJSn*r64Q;-c9ckl;+qLDgqi zyAN58EC|s@7efc*AT2T$#31;?_yS$Cz15Xf!?2eT%NK6lc+LfZT;pNu9~&~v?-RV0 zPt5xhafj%s67u+2;8-Zr4q;iO)3Ff;WWBsrM;&GCY2q9|?hHo0hg_NG?f|s~%TU|7rR`YRO2NxYA zB#^5|6(g$8AcKVml{X=#iug*%wX&0hfi5&hdA_;Ndh2GRXFujBA-OUJ{Bco>V%y(4 zNrMV+f{2{E>DTxiwkd9RS4Xa9=aT)WS-AY{qj{pJ^F6dvs{h4FnNi1uxyMi+7K`9w zuXmwoh^<6lRrfHox_r+Bf_D{Wq!VlAf>;HIIjhkc&ug_f8?^P2JT`Z^Em|xVdn9Lp z!d^0&GXoc$57UTP*vtLeO6v2ryVh!_o-?HoQ;SycZCtT|PcDus6F+Em-n`S2eR8b4 zTu=-Yfve|4Y0}~);<^uJ=`>#&z-!3?z%~H2>-zkR)lNXb4pfN$(LMMvEeIm8h6%~@ z5N8n(lsdtKnoN#`*oWP&RLlnU5Qu3kL(-=3%`}BzIUqh?ZSMs9MgE?63-JF;lqLTMe1D^W=5m_ zLlGuxBwWvM_vNe&OrI=4u`rlW&u~WAZQRL^(*vH4lyir5%z7WX!z~D@4WG}e1rh7u z;#>DMmm5KNC!eT)E9(-&O9$cP^K&+*LF!87t>xz{4u0Nfc1K3Yy03y%#F>AhP?J5Y zCNLJ_qTapO;?pPP+W(*szAluO1=(Tu;%c&$JpNHVT_5MSXQ#Ijs(u>X6S>Fx(ecff3=e3sAHMbbS-j+7tMvF%Qu=EWA zU+*86I(LMh-#m1ZJ&7gNlD~xl5i^~5ZEcUxi7%25{&bU~lV{ay5l_{+zTX+~gK{gJ z?R}IN@8SBp&~U|Ptq(<64|t3Z(fFc}MZSx)!gJ+)G8xe)=;dbn2Z>~;!cDIK0$gG4 zU&>QAcOgvUcjY~A&5kD22Q%r7oseVo$jv{z)z36KcVT+AUC z(^I|koeAY_%(|Mj!rsBMsV@i`mU6S6xg>4;JFRRGh)&&Q=0aU_lXq2y*`L=0!Ox76-TCc~l~+O(3aw^CoKM4| zz-n>_xsPUZu#TF50f_5}o|UV$mkckj|Hjc3|1|56a;}9YGj1)K>hoSL*ZRg)#CHwu zdj*AqTqgEWR{B0a-C=j!XQoMnT%>NGZYtQ=UwAZk8q4n*GT?8H{OQhplvT<6^G1&S6-FdaMWZz#uIyk&c-|1$@>ZB6l-pa&-5Xl@K8hgET5Oe77bOx-C)< zmcO=e>CVaCRJfKE(V#t%SlQP!AN6t0lD{7N4BBJA>T*Z;t+jECvU>5bj}>FcRAY=m zql_GN%OPnnZbXgCbOfT{)&=0U%yggIax3!)9+pgF`j3*d;Tr$2`ydXy3x>k%2l#tl zSO?m#D-jOED?v?I(NCrx&*l(|EH9oBkYIFfhmLCTrFJs`_quO{P{Fbn8g9Il z3uOsVof*%ZvycOZdv{sWZA$x|EY~ecdvhE_O`9RfC8CZ3Z5=QlH>v{JS+=^2V zU^$uJjT=pIr~5B5T;RumZKR^tq=+rHyoDN@rpI?fJhV0#DfVn5N&3h3i#Bg;A~6G^ z4l7qzEWLd`L7)xn&L0$E^$k-PJc8$YH$YwhJ3)I6ZSGaV)tK9`6q*l9)Ja9$)W=k6 z0Z+jG<9^~pK1%cGnfQ2r+|ItF2h6ZxuiI>cT)*J$ZuAQS(-8Nav3+LTbvm1l)S5LA zIqikCqi4tW1IZN&c45ZY(OCwR(q9 zPgUMSM5?n)5PnE?Mx(hb16{Xu?}xv<>He+M)Ou%w#MX#)Db4wWmku6nJJ$~jC)s~} z5x&Q@zG^DAz@oJSlWkx_VXDb`$T$}vul<4RT8adAyKHZ{LSda;tpMJrI8&zQ5)

    1. ?x%bNTH0B#4hoBil{__5fiBnDv&=albuhh34$tE{uR^KTLJDmH`0#Af);B z!=PyR*I(XhufFa{s72yqiW+u$!M*bl-oeQTVF3=F(H?M-o!8mE#fGNuSqcieJBW!x zlwQG~AUQmF9R7Vr1)hu*Px?U#PS-q%mE{?d%iTasEJ{k61SNkT38zp-+!240%a%4hdC{xAAWngy zJH`Cvj~UnxcdpqoU3pi)Bz(QMkc;)?D;wk+fN{XK$a5qiMEl17JCk!7oAK|8;SzaF zv0lYCk+(fXPU+h0%y*S0wbDKWC4(fdb+orUA^_=66(5O*o!%jd!geYyA@47lX(zE3 z20-Bvk0Fo4sgj=%$ObCN9G%0Z5t0(NChi8&*zjSstdZnITdy6P#64E-hd?5VA3_3l zZ-(MPY%Hb%%ah1;eWrDemY;qVdUQQSbpVfU!@dO+K#Si?+YkO>%kpM807sI7sKpQq)_LmucNHb*lLEfx@*P}BHw@B@J7^Co>e?)R|}K9&HrvZ9+J zk?pBrfou6ICbM$UT>kzqT>JxjWty%*S1hq_*=X9Uth~%+QM%cAeSIFwFn>;-r&|<> zn>lCV(xTxO%a`alqD!ke?eMlG(_!BLfCG`WsF#4^jpcK0=R9X4*+7cNqWz3 zd>;$bKam<+8GSrOY*6>5;O#mf5=Y4*hN&j$wqN$Mf_n@xvaUiwU~GScgd%+tZ?ogS=9^WK5iUqc>4 zEV^(1=Ag)+fjGau7XA1lhSD7&nuG6O9UyK$aA14qreOZ^mz361kQ4chCeJg3`BXlF z7T}3OVc9E%Du?q@z%Z!$Gds^;X(u;4{@OnYU6D5ukaTpxUB^4UdU`R4P(T6N!$ZUc z2tfpaAni!1_wsMD!S8xlvc}%735R0ndX%PP?9Kf}J32#BKx7WIrbh%&@~}z@0)4PQ zzRfZg|K;#3=U;y=F@22{13Cu;?He+VdpIj(*t@^6Y-Vnz$4!0L-&{ zzBpe9qax)h%7^f-1rvJ$)QDFY#%=M@EIc^}I%T3kMeNL`U79^`)UUIY0O8tW)=3R7 z_TmbzZL{Ktl3pSCFQ=||<8J_8`elF1oTmT5&`LHzDl&qpA5D~J#Z`ynnu4lXgn6nzYUSAmoceRbKN3B~brPr&%6 zJJsjczOy%FyYIWJL-czrn}YYqC2y^XS5~0XLVwOO%gjvDvAK6 z@Ur8$XyZ6*4OmLU{wdUCp<|1B%+CF4cGQ27Jj)8Pc#(CFz$EIZYbo@P3lv?U8DcrV z64?9K6Tr_8=0T;_PaX`BK!QNSh3se+9eyK)Md`LGJ3o0I&9K%uDRG>7$$1?)=bKPj zlw#4;yRks5ZT<^$Jj$suHQUy!&g_R)hL)6ttXw|?b{y4GtvM!O7q(8T$Bz7kqp ztPdTkl*q@YI`2K3`+{YWRlio*kBNL3W)K@T*VAqZ{M5P$y6l-UTb2u}WBm)j%}^KR z+Wx(ZpC&c$&o#hGFx;mph~9U=KVdRB#lr8h9yB3olMHmQicW(n`EBSN-kZ}xstiYD z#8Pz?Y`Y}jfY+US=%!+*4A-8(8#{&tc36UF&+e5k%de8^!I2#oziYg$pwPToPXM}|9%Mfp8bzh8vyK9r<*06{R6hZ^mEL~7NoNHR+e0=W5N z2gPdzCtPYVz^HCzAs1Dv56Bd@$BSW{fy)$8LX|w6*|bY;S3&yGzKg9J9p&TIK6P4!i?wM6Dk+6?2Eluvw9PM zCBhDY4O7BHer~ZbGkD(rBEKc><&_hNOTgp$r8A`*h}Op&?%dfy#I_W|p9&GHSx%q0 zzO@XEYG;sd@5j?jVj99rzh`b+c|acX^C1dk7&)>F)$2h)+wdl@S!#kb&Oi&EuBzad zZF+(%IqY>lnbVIEp$SVLcpOMR7pxpzb1wGWT55YQ6~v4rhO^-XKqSej!k<#axnpn# zO+TtS;+USg4$V2Wq#Jo5mhN%=(YaGfm>11wf4KIi;|#(IzoS zK`)sMYt>vo5*Y()-5T%ei#2e^FLZXiK*oJ!319K`cp?W;y+{?9Rf*mG7jv@G>90)s zP1_3MPTmybMv?z)eDghpN$C4BZ7}cgaELs1SIytt+3>ZBoWSw`nPkUY1`*DYVTZEV z2D;~Ok(j-aa8gCe?DxITKRrGhYIf}gtT>mac< z%Q;U(!%o7y`MdKr(+sij=*OL$(=nV9(hvh3jLFQ8QH5S+ z3c1U_c$XV%{%+d84WV(H%hW8om>^$C_GGqO*832gKLtnvD8hbHB_M^{56<<(+Tlks zpLw0tgw>3bpkwVEV7aI5oBTC3Fpxt^Pf~rmt^kZdvM!R6?_M?RU;C|_L!itr`geb~ zoJLjDu5t%A|CW*DZmkl}um4R8-!@M2SucksiZ}LoWZ!^G%8d<1!owJHELA zNrMmDH5|GDV zw_yY6Nr%IHbK{LgZXTrOHvgoPIjEz^h!q&IKa+_$Wv9^6O}_ie8bAYe(zSg4((gfU z8BWOls~)f;9w)jMaJ9VZMB!PCL7*Zkz_uf5=*}7|f6#I=7kWW^x@;TN z??8ZPw!c4amZ_p*;MK(yB8ue@U;MxNf8}_ZDH0L1k94}fV*OjqSVvP|a>z&p^5<4& zLG*8or)5noE%Fu_o~|HfDmOzXKOt1r$*T394S;45RG~`h+t{{sHi(nW6_;N%1g6rg z@7qkip|Om1+3vl@s6fZq(`OmgT3}6Zhx(0@Q^((Rz08~!>v6y3c~KC`dZnHaNaTAJ zv*?eBG}v4rMi9$qyv3zaby(O*iKn7+x$M6sn3KIM{+4gB&)&VfHHFBB z06UmFg|Doygxy-JqE72~<@UZz6s3J(OI--YRoUC!^qUv;XB@p?Yi7hy_2a8;H*`{2c*Kw`kjos7hGAvzmb!PJ1r%m9#1zTC!(#2-Ch1d zS;0S%54~gRBOd&>)I3bqNYL%8Q{jnvq$$u^%f0(v)$U)}fiK-7E~#CGXzgvn%&EWj z+gHyLgBK~F_^gpJxPURK5wVF!FQ0$-Ak*-w`jn5<-RKpIfR0qBIlsw*v~y$;qcjy3 z^J@FluEUSsW0oIN#L)NDHdAlbv&=^A7K(j7sKfq6^b}}dJ99XNi_pSnMm?UfeVAjO zLyMJt=ET!w$4vev`9zqBvT><(O|HK!SIe0Dwo}@6HJT9O_Lqn=?(JqYzu2(uq>rf$ z3gpR-AkP}im-x_Gl4sf9p}GqCEY!c94(;HWy0FnxI5$ze?iig#2cLrivQ}pgoyKoh zw|?<&C|H1f4Gawmy=1Qs9#?8F_~q^IT|NQ;2Mv5m)&dWFV^`|+GkrdF+P)+O@e8EkGzAxF zsdUd1w^}7E-xFw&t^Q|(+hBN{g*{FcV8UN6B(|1|Z~bC9uDu@^G=tq~3FcD+%vnTP zEs!AQD{~hhb?(RMmpA`1LkDTVg=5lvIS7A`0!C;~4@~3)=+_KIzw7+> z84CVka!_UU1cF{q%zmpu0iQVPb#~%Dnxw40`FAAS;Y_Fub|Yo-gRGXx_%*SFM0W@A zTm9dm!!=dtmsT#Qy?ikN$XRN)>;T&mkwd4LDJV4_sp8g4Cki5gI$!Fl!4LtV!8&21 ziA%%d2E?-y^9^_g&|ZlLe4mU{WK%2Qc__`gSrW=GV@4#uf<3VZN@F6IT zCe7u&G(#J%^GVFTYQQ(Gd;(b#`AfMLKEP0af6hZZ>6l&Ud79+X;ZvKjyI9E@%K(Nu zdzROFLL|`ibuH#Xu!Zw?A2kz9En*^B+R}S`-}u4H%!e41-M@4*+D7CbMcv{I<>n;@ z*BYYy4Swc!xo?Xq`FJhr`>W}`K`S7t?a#VRc!gcjk3rj_5!GM=j*ny-2do3rut-|05rb~v1RyTM6HfqXZI0Cj|x#t{NfbytGTx569c z+sDc5*XA1^h;MZRd`gb+dunAJ zCwTT^j)Ez{OJ9O@P5Z5r31H9s;)&dVLa-NLrDH3>iqhE0rfV2vyOJdJcJrY08< zVrcwI_b<`HH!)E&Sg^{5Fx+AQ2NnxgS?(B!SRhuC9^wCS&sV?yy+Kfa6FQ}M7PY%h zc&+DWqI0Ehri}85+2*YPVDliHGJl)kFrf*XC0f5`?)%dXZY(X8pJ80ar91_m|%;W+3IX zhB&cfF=N8;YY5JaBI~S>Oop6g$`BN@Z z>qxrS4sqA=>xUS2+MeO%*JZ+7KbD@YF3Us|D~$~+(nd`?X5%*Q+=hYWtMv%!?_-oU zXpMjVlw4->H(x){*zB>)$M>iU=MCxOK%9vK6uU~SUmlrajY-tczu8oIf2{^6KRu-MAV-I7j(U8NbE6~f#PHTQr4;{5XyVeO`a#;`LTY= zQ=q0MRiVRMsu)n77PDD7zg+N!7);6{Vo1L8YXrOL>MNG z-9koKPks7xMm?RPVTtF9J9Wm=Gm*rC8jNkg`*6I)Pi;~A4m^P#`I`5=6ZhD#k-U`b zgRX*zi7D#RQNmk5azhE(53HOY*9_6}KqBIZA|-L$kQ~c2b4_w0ojcJOg=zt8veOmk z;F9SdB5{i}77D$)%yLQ0G;eq`^ngKv5Mo?$oo86@Gh z5JbD6ylL@q7ERB-O8*o<3_;$a(R3}_Mv5wqwCEyS8ekdt+7S5d`+qigT*um&Bnmxt zl)T*R^50GpE`!)_+%l!dXDI1?NB8YZ!;% z=ce$iarP+U|7Y}oIXfCHyOB$P$^T*~3)OFI^egQ{fiGG_lf%U0p9Kz1mT1wTi-Am9qj|c>tLelC=VJ z?6d84P#PYF<<7JD|I7{ zsOOgZH{i`E$uKQFpREl`7OX|u71;3N8|)GzhEelB_C%yl`8r9!f%8`2$Su@UUPK(B znF&V%CIJq?@L#9qV2V)S-rF1zuo0~Zp}eo@B?W8P{?p)QV7%%XSbO>@T7xDx&@j zKyxPhO-ue@4~20$Fm>Pk4M6EIAWlJawK~&%{i07$CN`+wZe`?1>C3k@ zPON~*)<|2e3!=xk;_wC;ugIY^8>PI;%<`4kF9@Z2NqpjW$#@1^lvip)h=|^r58x{6 zBq0b5FWk;qQ}lYASjqM}*&sj5uk|^K_7R*Bl#XQ*eR^n8Ht9IvarYAYhx~RTRjEFq zq^d}bjIR4w>;=@`YFU`*A3!SF;X(L3wbQHHnB6kxZdp0U%)QgGasFfTE7GD|r8Nyx z8n=n*u>E561JCj%(vGJslI0mf35X4vCLN! z_APTb*U~M%kIxb87|y+~3rL5tjfU-mY!A&xVC%)?Tn4Cu_V0JMn*SQs5m)2aiA}y{Y+bm~fXCpX_02y8$&nNwsJtX-16|24ohH0Rk=Ftzxh_0&7i#{% zI$1~xU78)Xr^+3u_7aY>8RO}3`H!=^>!leBG1H3BQJuI-Jm^THSrK^3R~(1jnN}Lp z952douFyR8I`XlASqg7;v^uz;&_@AC+R43r0$|#YhH7x^@!KZP7{7Nc_cQnzE;j0? zeUe}&4;>rZvysu&sYq+tU~v^?Yz6OkM!n6{Eh*SbOU_|k_(kfVmPriic?ms)tolt- zXEjf{zq$$PgQhtZpvHenE#X{)qgKTXIYg9hyVw>O@ef+IM)AE5nYoFi*NyQkjdaLP zFDs+kY`+=VMxXmvRh}F4QJfQIL(roie2)4>p)N#N85kuf0nzPK_`Ivw^8Ly-8#C!b z;+%OSDDnd8H{#Y@_3bFhz}J2PlKan!fI&W=$C||NeHG$lISo)YQgH_W#j>feJ6tE6 z4X*HIMTzJ1i)*6Y%RVaUvh-TrDz|){&I~MJZ+!Y`lhIkUT zBL>>I*Aio5FW1iTyiDki+sGpa9I{1$A4k^88%=T@HF!4lKCfS=jZUP zP58hBYt=obeRU#X%RVb()jO(c%t=Q-Axdz8Cg59P&Ssv?e(=L3!8jxJ!?I`WK-F+W zoxKQQ_SM+|i@emVf?lH2aJ{GI)$BzOR+eVb3SOra>%1S4SLl5=vC!juh+T#6V`fdW zrSYq!)p#sbWj=>{j=3d03v#7hy@*#S>%FaISWr>Kp2qCPR`l!Jqd&5SKXawaX30;K zI$r0jHr?1U3x#y52&MI-ov(nbgegwicY?294}|t5@s2vL#}iy+&m~ZEy@b8RZabEX z@L*|oGUqy{W_B)g7YQ)DitD1pJq-#H5j2bM<_jCFV#ReoiE30@ed*>~dYS_1lhRPM z+r{8CAEh;iUGjsithLlb@i?DPu%N6$s-a8-1!@NNSOTNXtCmxiZ(Mfo_Q_k~yvmDZ z)(~+EXCgQhW)i!1j=y#GuR;ZQ`{f9is|dKG8hETQjEb2$_};4bFZ=Uot1CFSj5CuO zEmh5m+Q0t!wk+m1kmgUHy_kw^hrT=ZQ0u|KwyKP3z5P4Y)qmIdi1bOCW(~=ZYMJNX zISBa)z|}t&TBvT~CqW+bK7A@shD35H`rp}%;4SB^iHg`F>-dWQx@?TJJ<9)*|5}kS zcS#s67VVB3J_^Qwj39~3qBzEWQFvbZ6*KzC-ly3AH_*R?NY(G*SN}l~D{ejXJREf) zHDq~Z{Fe>GEe6Lp>+KLzsfk|*)gTwlFfco4T3A?u9NPn}T9}&2=%?>*% znjCmnXo#=tAy4L(ozz_CJn21-^|zAbvf*#5>;zSW1GF5c6g&HAk58j6O727*$HQR8 zrO-(eds;;XelYSyjB@>7$qbYGx>k5)@N8?PVO7c&Y!mQ%LI&p~>0!fI{afO0gr#-U zcJgWHL}`d0Xrx%Wc5fBLsr}=XTO*dEVD3O!a+!{vgl}1~ztO#iO?`Wvc9Jac_3tBV zN%6)9DgSUapvtFr*v?0-2xLHIZyJk%oktO7U`&EFaG|)K|IFv3nxbtRG?;l+Dl{ zWC0wSCM>%!8Fg#J=NdLc#fU^+S&F`bcF@C!9Y|`Wyxn%wz!@w0wstawtI(C*fjZu~ zKW>1eW_Hp1bMuFpCRi-83H=sSk54~9aoS6#uv%tOy@eOh$|y?RRDEDV3+Gc}|KIxK z57MRn7@b7}d~Z^mbQR0Se`6_wsnBhqHkzsiKFdJP@rO_6>zSO3Q4_lF1$-eS2LO|b z5bWKXA^)kIXN-@n#Z+mcTrS`9VO$8v-h1~JMG)!8+(N41Q$&chsA z9(+~vnzcx9u{u1ubYFf_Pzt)PyV}(!q%S~dwPMWN5_9Hk*-|yMl~E|Dd}voW^fYGt zgz7k;3&O@smGt|OTtfPm&b2*k+I`Dqc}}_(j+rC z{s+%I4!^L{4ZfQ$y}s9rg@{`DL$K^Ny?N01Z6RKE=xzfj=EjWo8JtC*m~5FQuPu}K6YbjRa7$TNQ$oNbVBI*v z!q56teQY`{zq@RtwQ8_0!Gb8Zbsu8=>?R7A|B;|1KRZ9*FA+|Z(@+*aGeH3)3k1@# z0`^w_+IeMMjrYxvk^cR@#LHoni}x?vD3pg&Ks;Wojs5++g%winJ=*1V^@N|94rk8- z0Jo0&vAxz7f_}No`3s!K&)Xx4j{Xn^jp=q56#50uNA}$y@A)?h090zK#mNEmKyHvk zR{zaFQCa)XWIs5jwXy>4eEpox$$vE}@ToegB=k`3Cm!&4tUhmHC!96*@fVB%INSB- zr2s4nOjZ)h=wT-itetuEuqG;fKSxsk5;|Ppg~%TOku6(|vYWxSnxw&QK0mu(wmw9q zevjD{hP-!B{^aXqbjd&VcA zjKD#*aqgr?TJb-&=DevdpCuvm#bMufSk8p=xVD~kaWIapvD=3|=K?sVbi<{uKIeMc z4L;nq=)(t`6V3+usL~xf!~xet`tTtR`sx$rX-__j5`A?~oOK${UVcGGv~Rmt1k4Ki z(d~|pOgM6$P77zPY9G6CE&8kw_zinCTh||!8r}GR>W%Vojamp*+g|A%J7zw?r5uc}$1?TIOm%9l)uR>O&~$jy)QZLUc7 z#lZ%1B73qR)OIV_^9j+Qjva*!#=*I$v3!|zTR~`?T>|&o{LItGkx_>YxKi53Zs@}| zVcrY$+oP@!JsiL}qRJH&I-+N~{qwQL@-=vqZJapZOlw-zaNuR!V!QqyTa&f=;GER> zzBtTQ&Z6xWC-|deyIZpP7;U?s8b}rY7Ij>$+D9K^pszmozb_6MuJ76Ky94+jm$#cf zs&vQOW%222x9y_Zm(SywPlIS9WV;__L7@Ey zzT-KLi)utUVv#+nh8r2x*)i4%I72MILwLp~((2{|4|W%QaFC7K7l(7nzBoq);CwV- z1|A&1r>_mL^+!GVkWu}vL?2bUeTrPi2l%w_`6v1uRqgB3w|mNl4cN`}<^21F z@BkZ}>ZuQ_e&5v>n;&W9vob&52 zmaRY1*cr!1A4l36J5l@SvsU9hAAMBm_Rm$x()a9+Jk^&E^Q|w=CgE&Q?PG&ul8yN3 zg`@F(ai)dS*FV^;Z{A^Uvj+9i=aTqXg@pJ{>Vv~t>TLj*QGAdM+ja5T2pLzH|CdzRV-nw3>}c`aw7r^#Tc_pQ z?hZdN^?&NKUlrkZNcivvAGs;>p4b7_V*m18tbbjT zEzU^|R(Vtv+kG!r>}GM#c_D@Sj^StSM*O1Gw=^z)1^yxRVPlI)qiu7NuT1K@*Wuk= znv%OUwCVNpOX~M7HP<8BOZ#416e=a&{|wFWj~TgE)wo+kw4nc04UHR#fF0UL3v?rq zD?qSSe+up2YtVtqEIEZ1A%3kv2+k5f&q4mG-UkJt}09Ms4>y1j&8a`}j2fyL6r&-4AJj`_TNOMUB9 z!OJHW(!_Z9N)ZownS$aW6(Xu>v8&5(6rLPIekKAXm;Z07FP9(g6Z0 z^DkzYcNMcIROx*)z*7!NbKEkF&n^sRj_g$>PeFmr9mRN5DbNeXE*rAy0kw{)vVk~U z9BF@+RcwP)i`H26fLfoZewI??yu?08RsW^HgT;fTRVz-*YGf-Oq0MQ17N1St+r^4J z;8TyqlTzdJibK5AY{l#9{w#dh#>1ql$KvAx)vfrcdbyNsrv`0wZ&ts_TaCqA*NWux z_-j#d14Ul{Sd$q&V!_6-kYUNHsU+Aob*@POwG!-#{NeF_-Cuxgrz?P;{e`Eu zf*G~2ed}zv)vj<=b|!v}3Jr6AWRf-EA?FpXHK`;RgSonW67vT)0VA;129k_!FI z@4)=8$w6V7&Z0c$VwX9Vs8ng56HT)VsQy>)n13GTfA#LP@H|a>=@B$Gsd|`~Wo-uY zG%sc}JziHVVKdLq|3c&$!R*)h__dp46Ja zCN_&PFo_A93mlU*Qp@0}C$%Q9?+u&9t!N*=`!$@k_;Iao+jQg$X#Ursf!X>_+uM`R zRO9RSQgJNfWAVSR%Xrp(Zl|+%%K3rIwP}u#W?XNZX(rv%UczWbJin(CNfndWw<5&% zq)`*t#4a%gCNW`ifn%~pY8gEBq}BvBv003PNle&W;FzqDS`i-4-{Ts`d8)0&K)Zgc zJzsAPZ#rAwp?R=aYk4J-zh1z4Yj}P6y)6V@Z$a_vJN)*F-!btz7~n}`_-)hq_x9{Ie*^DY5=R_ps*WcCC-`(`5bYZ|mH$@$)2hznATj<{$TSHY%tt zOy-zPjLG^}T7pK(IH_d=Qcr44V9{o2j+sT`5leNgV-YVr*Q2$MXEUb5<2T8|_lpAa z_9LAio=Dx1y#DhX!5PhGex`;JpWZ1x#ID+Zt{2;NW`O!ALAr4`f8}LxCIU1@;jpd; zJea6N4&8j9i%!Nz%^IKALLdFH{ICvlvca^Dmj#2yjM^XQ$Y-8681;-UQf=pJN^+@muhhMD!x4Tq0F&X$5~Zm zzak0XMjuwvA?UVfjezxuWWsiB)dts}Kg9ZI_0lU#3V3DAPaY_=zs2j@99FXWjsf%CYoN#D?7iEby^w1<-YDKvJ z{It3v=K%YL{zK~DDyn@Z8mN4x{+Q~o8J-;#2B8QRsc?kSWqq9#8c>Lp-F# z^#iRlr`0~F$$eTmW53#0)jq8DPL12I_BDNF=mQyyzBPg$S06tt|Ge7#bOSu0d7q9S z>ewa&{O?sgtTAUrk8wQ9My{C=y|u;hjOedZ`-1ieXLMX6{h|GdBKDN}7KC_BeQ)dd zrjEQ+@R(#nhkHfmapCOI*hRJ95#Bu-!*jX|s#jEL^Ga>_Vt?eiqzcU?eSTNL+!am7PD1+qJKW;wv7M^rsed~rk-KYXGiw4nc+KQJC!&LYt|}(%`yhX6rHQ0eL}RJmm)zIje+i3(VS6b{7Kmd*hRH9{01+!J)y>B)kVcL z^yx^Z9=ye}7R_*_@zh)(7=+KkWjf!1-&_a{y^p_BME_q8rE6s&mR?r*(W>eaMO~r*vGS0ox_xqCUT= zSf3W1W9q+4pO2~XQexsCz0b-SrvyK&e(VK|7`v=Cv9eKZ;`6%tk>R}B3#v1!#NSo* zVTO1P+spDxK8SlrORlo5#s`g32k&!Xbpq^BnRlTJC zcXb4Q<RaklSBT%WMf<39nW0agk#UczR1dL^%|BMXri#3mRgo83=(buo zRQ&S)0{{U3|9AmxQcY_UQ53yxQrnt-H)^P&U1-&!C4yoXp*kOLk|~p!^vy&X3Qj53 zv=oA(EeaNNBZ{D1x^e9X-Ke-Kb)((6@((Dqpc@yus<`R7!=%%Z1TJTC?|J9mci+iS z6HOD*@tKi@CSWt758>u*-xi)_x}Gm=Pga_#4e6I}Zsq_1Ed|u_itni7Lh}+diT}fA z*FLihN1E%p>brTx6Mn%IQjuDrlB7E*{8Of11LzBw-7%u==%R&IkbA7W8@~i(vCbIB zboS9@WLB-Udr#Ymo*{bT3{S{nE6pLfzOucw35_j8oa8X6jgla3yvRKO1ie~-6K^~u8XPYo%>@??r$p|mk|F*z7g`hk&(Q^I0AM|K3= zmd3KnBOx!o7tJZEoxAP$F?cWhR*{w`O7`RBewaOdgCC7o7T0Cs9^Jm+ z-rv%9e>Wc1bZ{l3pGG0{{_w9=K+wIu#a(0hs^W??&0(~qqni(T!n&KI4TYXQKv|Rr z*8g0s%MIaU!n4rJ)(S%R+4;FW=itiWGv~6|v4b?4Ao|{sJK2gOJoEoY*})Bu9ty0+ z9r?!t@`e^`x8|$0*=vLIwc8oWa3*o#2q0h_14d);?i9~dE#XU%$B06@I{*Lx|NkC7 BAWZ-O diff --git a/CPLD/MAXV/db/RAM2GS.(0).cnf.hdb b/CPLD/MAXV/db/RAM2GS.(0).cnf.hdb index 4e17e94270981c4e801cc56f2bb481b617190bbb..a550f3d96b199a82c646e7e7cb369c11226055bd 100644 GIT binary patch delta 3211 zcmZ{mc{CIZ*TBa<(-;Pm-5^Vzh`|t9vu7uSkS)7xVMNW8X&779>>@l_#y+H&WF5*f zB(#W0*$G4Q7)x*O`=0Zi^PTT}_x#Sizd!H2=iGDdbFmDuOdE73C*VIZ&HUf`@0`K) zUq>-*x>|)uU*~}*z1e#TJjWx+O5%MtWZ!B@Pa`ks+|t$=&zR9GhWnGeTL>-_1f7)m zwn8EQTi8VmR8KSFk%$0RLox!xBC5{>iZGBfko%(lQUWT<{4K1uY5k;Qp?q!=ZIk?E zsb%tb&%)oAK>uhcm36<VZAzr6k~RZ}YVO!F)I z2rL}Q87UdjaP$9$E3Tesbenpuy}ieCJC;bIcP~e}?aYWBu)ieVsPJlwR&j3{~_KG%qH$pD6;Q zU5o3~?WwgJE7we{V|U~<=S+cI2z$-P8@l6tnjSw%0!kTa z7)7mJDaSh2$%AYrJ&RZ>GTeA$^sIGMABSfy2gW`5AjQ3;7B zpIwtMt5B#I^AD@s$U16)sJYU1&F#+0GHQl7i`x32zV}8%@C+a)vJekTy2lZY|J|W= z0pDq8vRq?|O9&)|Q|9GGVD%1@g+6H3goKtzw#SJR(gpSh0;g-vD(jBe+0}!&))19J zeEPVkMnNaNIlYrzuOtAc7G^tN&Sup6VDJ{$2h8_FqeVgUK`rox(}zAya4`S)4d)l( zR~quay2?7Hn|oK9hdAKVWov85{YU*7Z9FpS&#IR5IqGjOS*&lL_HPEhsHUJT=k1N+ z`6l;pk0`a*+`7_u>Rf{A>)mh6O$`e35WvS0R1>kJW-3ffJp>1gQ68k6P->u_*I4jP-uWy0_pMD=_wm;B)%{$R1_BQmH7@7o#she>`1%IR z6HKC6XK0h)07-+EDGP8G**@8}hzEt4-f+Xxe^dUU!TbF|Oz699b{*7J+c3o5W;B0I zg4~_MZ^I65wj8 zjDL?PgEEjo4dchQq%fwOkPQnjuE@W0#RB&qd94~Dx4u@BD5BE=_pVHB2dpct{}4lN zdfB@!GqP&~&>(c9Ew-qhpR_HQTNsQF=4!O6=9Mr%;J?dH_&omHvZecdEqcIPMV&tN4~si- zL0z|-Q^-ivsU0Na^1)#zJH&8Yv%zJ2gT;9}4)O`D)z*uVI_fyX?wEch-4}du-@FB_xvYu>gdKlqG9* zpG69#V*LDB9T*rFih~r^)>Xpx?2~rkd?2)Be*Gi(^=L=)N;S^F;@S@@!-$K~e`WQu zb0N`Yh?{pA80R8&4o>1g@+EF;P#Yi;Nc@O25n?t05CdycSq4k7-K{~{SX3e#eq^s$ z94I)jQ9gt+X2o5J`@r@{G69~5Nd}c+D=uV4B;2WCp*?%X5e}*}mJcIhTr6;8WfM={ zFZrXiXTq(^IZ?VU2O}vqvbsVd**BWm&`$|RRglEIP(jO2hytP)BCy|c3fJo^$yqEH z0BwOe`*eT23M|S7B4wBY%#VZ3zXY3i2b-7pPIaRc{UJ2Y622H;HsbQ z@sOZ)?myhW-Y4i=clUr9#CQCJgIVR^*Ym4!6=k&Hf%8jsO1F4p#+2E**7Nx4P$k5r zYo3;7uVqmVVlZ5bg4a~d_>qAub)v-4q-{A^1!Q$v^nK(T+f(1i*|B>tON8=~sv_#5 zZ$}+eWDF}Vlt$rz_5>xPt$eVh{lFlIfMoLbD7?5pF%s^Le%OH=@lkaIi+gHofl@t9 z?=e4gFb*3C?)qD<^a+#!M zf=OIS#MuKzQ}^FnDYf+;!-u8@IggoWbVWl|Qbo~W1c2TbK7oc~J-_+xH`W&Y2F4|I z#9E1+Hc@sw&3eFr_orzFtfD8{RflZ6sMJVllY+}|T3)79!LH)mvCQ8_`8=3I)qEyU zfjA&s36b^aE8B8#1r-fZCdKu0;q=%SJv^rZM5M5u@Ru3nJ2yk;U^tFM?#p-UhD+B^ zCMp(NCQdmxYYbD(Xj{tVSKf73~Vx)+2?i`0z=*LoMgRwWi+4`kEdr}7L; zYxIb|&1~W)+lYBMlx(k}rw0zV-GLyEo>-lKG)UoS{cbhGKC@MN3h*w0g~@VBs&oiFo`YePU^momqca0Lt8%E1*H zXxLN<_FIBx)!`D9Hv4A}X9CxM_o=8@w(+FUl1z-50u+;wJ#cSD*ma@)r<{SOvICsU zD~0IHWs3@pB+2EVOAdo)1ijfJ9zP#1`q2XZjQr_)`rqGM+vp03n8;@_=S)_kfIcY`< z`R$lY4R^&SE%j*2Gh z?{xJ?>*=H7m4E4hfD$ zviN(n`;?gkiV4ocM2{{Jk8LcWcR=;vrR+>OOz`_Tez-@Kqi~oLPX84``Fv%&{0uG5FDeDP?o1a2-YfD# zK5M04@x>%hqDC;d42pX|7p5S}fbRKv2h~Dc4Zy`dittjr0vk^8uBC-+?f1MOl39!m zDjw`li3NYv?DC^W@z@nvvBm`BLnh=$tCWu@B!l#NcDc>+kgxO@`TarNkA|-eR}6cp zx4D#NCBmJKQ-3Y{q$l|_b#1n+%BL?yH*8fYeN^3Q%2dHkx7_?SWwOO^_aIs{v@0+E zyh`N<7Ej%_tNS+GByhrCoqJVa1JraPa8*3)%-jD>Cem#xPeu%bRQwfhh(%7pl5*9Z zqJP&O*rqOaa99<#&9{cn2vK{5xQkvXtVdjQDeb6<++Vp^Hux6xn-|mIQ+yMn=0__g zM(~6JE55`!`b-ynlIdts(@%_0z z!Ll$u4x;zEJ&xR9@3(f-xt0DGGD#nfVDBdZrUO&l>w*V0V?@cOA^T@Lsj%560viE; zu!9JOA{5%mn1xLNia2Di^we$3=DH3-`4+2CiVIBsGDUYLm-0pSy>4uB6NR&4)XYbR1BWzB;XqDu! z_pYPn%pXtSqEsW@dvm&ep2X~an5X-SW{dwZGrL{Cw{_T}W+fn;$U)_x6ak~a4@)cI zNSzp0;)Z+MozaZ1qk_Vdc$E{2D&58uY7?)Qx22mD7adCQPx<^NY*&*`qe4psG4H6x zme8GCh6BPw0RM#s+BYNey9~`I5N#?iJzS0n?ZlBhC@7eT(vXdbwD5F;(H3ZF_%pp! zGVL$LV|>M0j&uXMlz#BGn!4ucwm{MRs-6@+yL(b{DT_7R0I9wCz&j$GK_5Tz*E@bp zpJ0vq)>4D2*5}Sq#_6_CLd4ChU}1=kmt}1`#*?Y0?}VFm-}Mofldl`O`#W`Xbhl6x z7nP5w+H&P2R6xuMCj*ctT{2P9@a0l>&3DFPVRuV2R%glV+A1geZ=E6awtrkQA1K_2 ze{rMQR78>Vrr>?ta2(9}n!daCr|d@p<&7_-OPf~NYssI9nmD-t1J0bg+5Q)ywPkp~qGanr7n+R^QN(Rj(e>-uf?F(SNP*!r+JH1^qXm6%-;LD}Th2*qW4 zM%TLc`9cn@=w70%CBUXxI3;U}|F7SIS%n^#nv~Cr1v9|*&+*rlQd-tGHl4k+u?Evw_sjD?b*q)SebZR239S8NW$jjJp+74G8~ zmBY;{HiF~am7*?3$x>@aXN_9o?FRX*92e-0G_AL+Hg9-ZtJf{yWF>%Jf=E!C^`DXM zcAR+b(#QWdA?n)%b9 zxBw?|>i1Omi*@}PTVLLwwSl#t_fwW)$4ZnZp-$r>kcRJdiTSATq`=m##Rg(nKhnL|pgbPQ!@En3GJ)}E7{PD5^A&<#}ClKMv-{(2I72 z>%Abv2(5jxAAp zsviwg5b(5d^VsqhVK|2ln*VvS%w-`{G0kX`*zP&MXB4e@3R10%2l>%9+Sd! zLAMu7|7QM`3}a@QZHq=HecN(Wq+!dM>pj~NXI0tVPal35WX9Uu$Jv{=_-b;`=pob? zdSky&(i6&JI%S9=hJ52B>Br!6Lrz7KU#n=^$oEHSNK52)+J@<#QD6r>SFQR|^rWWK zTTe(~<_@ug=?t)lGiR%IO|0^RqAIAu^eLy-i+w$!FXENKb_VFh7J?4?=l{wz1Kd6&VItOc+fXFQ|SAUZJmZA^qjv|!Qj>e`a3Mam=7thhcV z@7=H|6P8HkzB#&;+}Zr(=;H>C`@aWF7J($f4fodegU%=%{UB!eQ--I~K(P!G8a6VT zrn9BJjbo<3u25B>=OF~GZtbjj)~^ytE7UeN*NBo5mOHs@H`T!ow(#PH5a>CbJ6P2T zkn!$s5W4*U|6~P0GYcfWR%PnYzVls`OW}fd?~=!M=B-o8$c`Nv2Xc+*+}EV%KfC?r zm>V3N;ER*c&A83G|0?-f#;(BBDO<5Nfip7x;$TNWMpY7xkj1S}e_uFYHZ_5DY6SyB&5^<>FsJDOhCI3Qg$p zkq#N2kvEdo<=|R64HeUBwd7a#2{!eqDQqZ-#}#*BIlxj8+kap9gi<4eo$;}cRGWdH zku1w&lSl>Ot~FBc`K`xt!THV5u`tQU`zraH!Gd*yeYT`3 z{m(*oq~kKwSwpt*8Ex!OA0$3w?+i*v5)i^dq{2kqBoM|yudO|;TfF^pEzJLPbl)=82Q-V`Tn&mX^_WLy0i z&M3TZiGaQry0m-G72m2<`8dJ6ftXq$UQymM-q=X2zn$~zNB>0VuMPd$YTTTD!-RPQ z&&*Hh3o2!@EuYBu$l#zu(U^KzmlE_lNjJvyptQvAB_Ze}mYf{%=;e4JWrX5yG|MF& zy7?tRU~+rCOkKCO(2Vf2$MGFS8@{-zJx~dxo^%gvfz)&=5&Pr!rLl*vD;xU{%i7kS ysgD_WKjJyF-?J@IHZF}Uh8T%=WuEYaH4_ZHLvwRNCrntuU}EDA3G diff --git a/CPLD/MAXV/db/RAM2GS.ace_cmp.cdb b/CPLD/MAXV/db/RAM2GS.ace_cmp.cdb new file mode 100644 index 0000000000000000000000000000000000000000..ab4f43a54186a081cbf380e268399ceea201c3fa GIT binary patch literal 44062 zcmeFZhf`DE6E^;_ASx;%0wN_M0wPU7Iwm3@B27VhQ>0hvEd(n?dJ&{I>Am+vq=X)N z3lMtf5D1Wde}3Qh&-lG_XU?9P=ggkDch2tYKD+na{_ns4${Ei68~^*y>EH9@pER)X z@N{r)mJ^eZ5R-T;E_YAw)jdrIFPnR+)(&3(*8ZBj z_c`2T9KktDuFK_4H+}yu^fB*g+Ang3>LFXk7+uTcPuqECgLC&GW; zwlr3u!R5oJ^+W!QO}CXNG4xRk^XUd~&#5aQAbR1$udcB9u0Ha4M3il9 z<({nlI{MGRdm=2saFLDd@+2h6iGvy6(!gkatpK8+t_fX6amxDx? zIcvwSQT>2HPjvr>`NMspka>E*ms?>yC*@+Afu|>zU7CDYTrz#e>V@e?fa)|Ex8eS1 z@2Jx0^N|0}90fo+h!70t1VBrorDOiyDHFkOF{H#Dm`TGmxO4IwUSc%xeaK+HZ@6Yf zLrF@3;>=l|G32PrXpf(`%=LH;RDk(;sXewmVlj%9a_1|wBMqkogn~bRr2t}i(|EB} zta7huGSxExboUt}k(<4%j*A~et(BxKfk@w*S^yPB!j-f76D_P$c7=<{`)6X zxrdlPNZZjF)anVCOC#NaN;}U*ud`P`Tx&ND9tV#MtbWJEObXz6xWSL#L5DSp1T%}0 ziG-NJchD~SI{PjGV)8f#ADCUkDKGTjYZ57Abvk+o=>X!LQ%Kwv$Ld!QZE%%^46pp0 zMdl@R`)xK3xt%XOr6Xld2p|E!uQ0rLwmOK&UBD<68v@1F;+iY)lHlYsFc$;W_V68a z=2@!)+}}GbN@ak z1G$k9ii@$$ZY*e5V+R^jphLLj$}pv9W492-4iuG(AUfO?G{;0t4NBcf$?pCoO%kPU!d4y#b8-+WpjYv>Biv9~2U{~q? zLK=PHV7EDiH5Bgn#D)zv6H0@^uLlr9rXmdwj{_90Wzmq&dQB6!slC~^@lE<(arTu(=UC9iDmRR!XU*dM<S<-sko! zcvN5mWFaZ+S$`t*=%ujf$2)1JLluIp;Z|?lWhH; z7$?|LXvMw3w~!TqO3+9k>c8M?BLak!M8jhxtFon?w)X`^}*#`g9=wo6CE?tKXLMoOax=UhQ^SPy{EI4+` zCg=&EO1TI|Hn)$o8>0@jmXw1Np@TS2|K}EQ>emB5r>!!U1oI%GTw}15fT72*&4B=E ztWMh+a?QT(&89p2?rKgJnvE<~=_^e>4v0nGmx#;_21CTbXVd=cR9AMO)U0{qC@KPb0;@Sv%#UcR=uS()|R}cCd%g3CQ2BCA0Y_ zkt^^CR%QcR#ZK+ItYwoseNE!{pzYKNKfQTu2L=VHzy5lK+&g-z)FAD5;{&uzt_ZOk zoD*EPRWAqk^J`Fke!%@4soguXdr3QpShH?5)_=YV7-{ZD7{B-P*i|84pIKJ5QHKL5{1{{QI;7@+d#=YcDd z{BYAisC_LzTnz)YEw*FI4oBf64y|1n2X(UX^(SBd1-fI4M{1gF=l=w{X=~0m`Rie( zHXM}!MvKaKE>wExVCOgV6d)c}v{0$D7&92ihZ2KcYG;n0W*U#%%e%5?wSuc0F4nMn z3_?y{tQoIRPt#lvcd0nGEu6?d1~m<5ZC3T^1ob;h=qP$*{I%6V-f?u1KZtv#CF zm4E?RB?Qa-;YZsf6h=BHs6}xKfcC2TxEuRwLuaf{V&@5bKl#6H{rHM)(Ke@|?!HSX zujy0fwko+1lMw8o6*Ao$+Io_DVwHtn3k;dDM#uUupMc>S*kGTuy7eB`ElPxI!m@k} zSgfmTcETUA)8-I1EXIC|-tBHY#{u^(dIkEfjso`ekXXGmv?-`dKF5V&dv|e;XX<8k zP}s`c#;?l9xy%A}=G$cFB9V{KrfGuOLyn3j5w^=PEpicTg*QoH&Lu+zl69kgqwTKK zcb%3C2U;dd)x}zO!D~A?#gHl1&(PxyWdS%37gSeIUcvCB-8fZsBKwLYg|0I8Ww`C! zgYY<;tii*%%tZXi^H;uzbD>bk6Jp-=Et@NTS-#@FE`z^S9uX)?YFf{el;e-Sb32{M zb0tVP&t14NyOrc&TBF&O<1f4$>lXU><-#6!-VTbHjj=Tx6(^D;+aWlsvX#2B-?+~I z2Q(pIS;>RE67IJpxs~y&==a(~=W_;&smRf3k@cf*&-3$m_;kyXzP${b&4<=$_$yVJ zy|Rjq4JZ!0#+a8PEy!)G%DaR3^&hi}3U^~y7SwUSIl$2()7Si2KA8SEInKD=d$&w-%#C7KpTa(F;sCsc>4B zJllgTujd1`Oxo-$lE1SwW_t;UuvY6Gu#Dnm))CH zZq;yKw}^P^TKdXEy++mTzW86mMm3mh6zt1*5ji84^S5b&y9}GKfw|DqX1Z55$DjPy zHCwO5q}aUX2j3iRjArJ|O;X-OMZK!~a-+UNf0O|Vt<9=^VI5%dA~?eOIC0mQ9Q*AH zY~fWc80%x)XW)%Bua!?mVx>Xr1E*5xu}v$sHKkOs)?QpXug5Y_iVztds?+wE=?9DCPP97syX>zl#Djd6(_SUT;tPuF@vMAZ+b~E8I z?^i#)I`~8L?|6UE&04oWTRnXNF?{H(y1<%8R(#QMP2Fu_1@!W$+j~_(-?U4`;F+(9 zjk`hxK73UPy{}2=c_M6u=XRgp`>}n) zj97H9n$W%6Des`rSt?t?Q?NrAGYI}>Xz^3SBkg-f>A}@A4i)jr@rHxq=Uw78HR4fs zm$y@m2lkaUAE*!W&qf}Blh=04;t{t4TqV80540TU3xd9dY}EL>Rke3kXal-!b5 z9}|aJom!js`uZTor1SYX5%`1Fnj|Nt8mO99f6=+oKqp-ZlHILvG56=T5wW;a_iBA} zYyO?4lk2884}!<5qm`rce$)uGzB`$e2rjhSo?*iU3D zqmX{OO3yjxR?u!^{r;l{aU3+oGh{VDph{0#fnT=D&3A^*S1+WD$9QO8%L8G^YyXCRuc)P@8@F;X(vx%F;J#g51aPpS z6@AvsWi-2W%lYW}gwRBgF|yzF^P}5-!CUuVU#R||ayQftt*uQE>!n0EwLRg zthbyUW5+3-B9`{r&Osk~e{wJUnnAR{trKd6TxovQHLjQE5p=T)Es7FNNlJjUVHzRR z%jCSyU_uBUgWb7vn!~==q_*f5ux9pJO&fCGiQ~d#%l(}{vAu!cOo_13-mMSF=9;7F z=$rmA+5sZU*Xjpdr}NThL2ci{%XHbiwxC9@{8<$>>p2j!YPB|X!Nt@JZ}9Gi7Kzclvj-*ef??Il@%eu zF9E&-w_}QTAK`AJ)%5HGDJ(kvx^L*MvncUPPinl2FVBp2b+JaN!UeOUW>B>!p9X-t zs0Puj_6e88pXE3&T|>ZFf-#79zC?%@Tr}^XZAZ5lUHvIsC#wElb7mPWo7& zb@}`Tfx#WKjZJWoe-D6$oUL{^2150ZX6ttSg_+%9KA7cf@}O2G)aSuKCw0FT)DKO< z&i=Lx4?y0`dWu=^yyikOKG~`GgBrj)aR5;jmT5YS8pzP-rE$dF*+PvsA6ELdS}}zj zYQ4%6{vXunEbeEO-})MJ2!;6rty$}$p(<013c$v-Ta&wcnNepE2AM-M9%*Hi37*;hGU8s}3*3{r?A|J= z$#L_(jaL~z&!1AY8i{0^sJ1WK>f96lni~mQg916@P9cOfJ9+5y?-oLVqWw^h`^Q&w zBp>5-Lv?&wbgZHRl$x5gl;K9JKE$<*3(y*EX~Gx}mPj3rQPEg53%Yz6?5|d{Y^rt`o-yFF-Y0jazNU`$r}F^f z3`Z&^*A0EkM0FlAh7Dn&tqQ3&HJ+TJy12A>rc43Z>sg;cd)ee&8!m9`hX0X(GW7KR z8M~KfTBy!OGhge`CUV!qZ|C5ZpZ2;sFJX5tTx~6Gp|1;D_seZ%CVK(1XNXO4f=gUC zStWhMMhjJrinby!+h+r!#d$;AXfsR7!W6&)_t>hL*0?m|)NxsS*z6FIa3gp#*U%T{ zY5Kk0iX%X}v2*t%Y0x5Jb}7QO((;tBQ*x!V!XwD*r4}I;X=kdn6wrsg9$wjR@g}I0 z;8<%|V70UVI8bE2%5Wk9bVP8>Tvmf$Z;@!P`-aRh9i}W1u5$t{t{8YGrHFlWW1+6{8GFN{C~uwslu}mWC9jW`ar&Fsose@# z`<(j=I}9SL(O!BHhuboYy#aO5-OCn1`YYtKu$o9{$v?VplW z6)M+_oXVZ$`X_};yR9Ynv}f{CTfqZ+9rIES*T!XbJlk5QJj?ftW1_~eSkU{gEyK@B zO^C2UnB9qg+s^R;2Wi(c$Rb~Za(S$P5vv7}uK@>RNq-y+eO%rzheFq%{(jZol~5=Y zPqXP2K79|uusWpu?rY;A#t?e$uO!}?$#AHdks_X$rpF+h!U_aO9%!ZUr_1aer*HqL zew84%TVfnJ3)7$N>u8gT$#a{5QUuwr&2I!8#3E;seFl+gET+G#k|X5IUOh-pN$j<; z2x4t@eA}XDQ7;>F`G8Huw0_X7ExA7^14l%@DzCNw#Xg?2>iACJ=>3ayfKz z(H6>gXitpvo|pLQw}0{7WJSM+woplbRRDNlCzQBRyNp?BJ>xZhF8W&?tI zSn&W0!|Y8AGI`ET9j=ZzuS$u}^4lqgLjGY7|-VWZ!FkL{gIAkN`$bDirStElmAEwWy8u z_TLQhsJcPU+`Y_I(b88MhOG#~-x#}AGTOqs2usM;h*7_~8n36eXo|J+%o2Mtew;XS zOF`UI#Z2_1$+=>7`jK$7Mwh2+gkThp*wjr?$3Xq(TR(&}*18pE<+nNQXDDj5ZTAc> zzB07W=_bVZu60A1vH`Y*oyjU>Vx;tX^h(bJx6gBMdb(H zpL%OOt-aOqKxt0~=?5^w;HoO!%q=Pl=kkS^sym-P_o*CZ%#BTOPmR_s0Q7u-OTSul zqprpT|HYQtc2&I1e=)6`!HsQBe^WlXhns$oVwLg53v2Ve>hxCkUgBfe5MN<%DE~#_ zXUcl__aO40ZRah<{e%O$JL8DX_0cH|^(ixzsH;JzHrN$`3`1}h^_wZryU6_VTTAJO znAP*E-5UFJo0Tn-aM{J63+VH+%@bM>UYxJO?mlzeMVznaH%DI6}7Qf$K2|Z#~|Hy zh(9t*f3zK{JAeKcTboc`#RFi0Kbnt4M4tDrf643Ka^{bH*JpUGBL)vdI(0O)0l)sk z17)a-<9C~lE}zeTp_K!uYa>$Y%Q5h@ROy%tjS2@pAFL2n)Sx-1h6$XD+C{$QV9RuK z7y0F&vbrTTipoOK2CsFY3>a*`RAAaq9&aid9Rc$d=LWnpeFt=RH~ps0Pc26n1}r{t z+7+~ctgdpsHVZdSG=3lc`RU!L@q_Os07Ln}(D;{7yuW}!DL^}xeYFQbAa&l11` zfC9??b4mcU*}G8P;yCd#C#yjW&Cs98U+$tCX09Bp2YHKCFGfinVEAb60GH6w+PS?S z67&%~-5=(Em|Kv(nHCq*NgO(p2b}yFy^BJAbH@xGMji4T(BTp%-CG_smGL%Re|XAKet1XU-!th#St5awVrcW*`uioix~~9C zofr!bP|cz&z%?xwTuy~Ee^ZJga4B($_W_Q(kmEf+btMi_CAM-gpm6k??2#J|huAo(HZi)8JI6Z8 z;~Tg2b$>@=4uw<(rN+32IM{3+<$!9&yxn|Q;|4$!-*12ZE+q6J#@EU2g~j{fd&WQ_ zY1#AV4XNE$6SVi=Wku)E7@&C&o}QAOCf#0}UR*XNbD|8KwFagBgpF+h*y=AgS1 zS8XY~BYwL$de6=J207DNHy;vYKWMXY^i1Y*j8kYBZQ#Pn1$J=CtWMF>*_H6UJy*!f zW0lJilF?X(BzyAFAkeD@5^?;aGxOen2?xaoU`MphcB_S>>L)EMeB+K!-HAzEs>y!w zL1F9bbC!HTTe7=wKMNPSOK1N=i!FvL$6(Kw=&R0#E1>Dir7a3qlQ~1FuA)}=%U7a7 zO+t$F(~o@O5>rGyx^3mF>{ZMvG|t~3Y@Z4x-p){G&C~FzINjypXqF&+E0h0b{;8J# z+h6q4mU?u;ub|vS8nBEnj?Q_r2=G)!|Cu9U)I&{b6-W=15EKD2vvm9uDanzs?9(cokHL32#+LfMF% zqOglqbinSXyWfPr4%=@br2jA&ZJ|zbmcP%xGUGB9o;k2JkpF2M-dOe=Q&%PD7<%6^ zOO4&>V})Ljp-81vHtVVj?uIaUX}lydVqV&BKGZMG^hUTr;IxJMElK@0GA^DpXXRe$ zG@E|K--0`psM+h5=+m4uXn+s)2ulXfDP^4rh||=d1=;c|EOQd(K~as;`@^=Ry=~JH z@W=a8&3al+!{18NX=zv^NVA7<>nUe5g?X0!xhshB48B!AU98U{r1%Y=*RcP?roJmv zyxy)tx3-8g8%KFcFUDrQq+^?N#?ex=Gdr~dDBZKPU(J$8*LI>vUjUPyRA!@1p9g40{f zpqB0F#~W_;zV?!QY5rZ06Nu{CpN(eoWMllg91mNPCMV4X26R8u^1=5!U)*J%R`x5H z9R53eSv&9>n0{WGvy4y%oYh2Jq;4%J}dL^tfUd?_~l z^dl5W&i=_}i;19__uK94u+Q4HDX z9&pgSUC;M^ql_!_f})I1#_S3PGM2~6o;CjEgWg8F9;8`D8mdU-dBkAJO4Zk=hPpS9 zvW(w)9L(p8a`z;Hk~U>}>FcBBvKPW5~C1vgnPn5|eM#y$<} z`7`JAD9(ISx5}XXmobyZz1ah@|8)aLg%5u9rdO<7Okk2+j*%$xS-BWO-;l+Z6(JZdajewr(7H_EO~Wir+|s zf>W6^Go%c*EL z%0KkXbJDtapg}1HgsgAJS{r_!BLJxiwGPD#7M;LX)2pNin_G)Fkk>fype=lwq4$)d zVs%4zrPwyzFaV&~e^N_~&h>`UTNDNJK759l1^u zLiBfk3f?wYv$#8*GAs|iQMj{XBk#g5x;1Xw-RYWNkgN@!@6l=b8Rz!&rQ@_0e~adH zc@>f$chSIjE8ba)@gITQ`t!~Z^ShQ0JKsh&TMT3kADp`fg%qP|+as3-j$QeL|G0@B z5~uBa(~s>wNxhl3mM0YK$_qaJe9Ohl=-#)=qZKa!gQth2&aUIibjf-igQqXqm^gH9 z$pqEEC|Uf)3p72}@GLY50q*y>Br$SZ+>R+osCc>|updTJH(*iRp zU#FRvO}q-F5$I(66}CnPY75_g7X#_CojzA7H)bo!)|fm?Dia+{w#5E8wOX#d(K+Nc zynS9V=lcyqGdOe2lk3zCbz{b;MJY1UhP1vaCUmKo8<)=FgkF!rh0#WZS&t(#_;@zL zd$^OcA{BWlexk{~F|}ZeJ@(>-@C@VYmOSR!fI=; zDAr;Y*_U^(j6&~KBvtM=QckFJRsA^C%2M4UdVuQHaW;SiL8~rg&Md#NGPt^v&Z2*+ z=CWWwYF7cwq8Q$O9p78FVm3(UxEZH$dt>75U6NI3?@UD))gGC;8^5pin8r3gr82LM z!90K*xAorVf!5nSXc}14gvnJbycLgKM$=n!c0gl4I}+q8AEMI%wt%h#@m4SSbi)TB z6=T_VvXEnUqwIX3Ap?;#at&@K99Jt9hI2XnJY6bDUORGm{jZP5F67x9{73C6fHNJEA%5LnUYouPd zs?xGV5q0uldgs=G<}MNKjn4ywm}b_pH%B;nsKu;+(@53d^HEtIw9RHqMR=}3~;K^`M+{-y#B|yxZD0*dz-*U~)^VDRy84tc(y8PWq zdnZ@1`dNpsRt-dGVEwy9zyF!;VT_q;fPd>+mIx!D)2HbvIs18KC$J6~D)iH!61)+V zj!=3!$L%nPvuyf(prqUQcJPvyw?#3&brFSE%yl#y3y`moSfPHHoy!@DNATQ}kP=}} zlHED-J_-IyZmq~!z%$IaOph3ZyTPvSHSOqhuS|zqtDFFOvMb6FR9R{Jv&Qd2nSC6F zkES2|F-@;E=j$s*!oU>~r8YJR47@BBH8uTjYEIgjkFAHZ)7{*nB2+(cC#-QYbx^8Y zqj8b`_{DHR8;!;1@&9wJu5YUJul`;SG&8(c`hX5>UVxIfxd(kDD4R=nHgk6ZenB9# z8Y9v@{a~W;RG9m18k)bmVbxW%QUmWTA3JA1J!4xDvHmArVX(X3dLpbvl*iMV={uD& z)2)%_8Zqk)Grh2OHg$(}!iuAcA{%#B=_)#vH-;rn{r=<5oTN8=*4n)JR#oJY>w*=2 zo?CPyxpzBIz##1X>*2Gq5<>(+9U(yR|; zjHWN{21SA+ZU2}LPVTcR!ar0r49cboH74Dpau^Andk16mBz>ow&FbXcbB^&7gsk zQ!v+tronFCl_FeBh9qIp(*^i69*Ee}!nxac%Ux-gIlHgp!BOK#njPObd!W0-SOK$8N$ys zE=0@aU(brWgF3RjNdFlMC4He;U4KVm6mV9kY=2}1d(UW}aRx*q>6;G2d~_LI&XcXC z5kjyP^VA_i$|-?DA6E1p2ol|4H&4kBA`9!axbwWSmc)PqX_M$<6(4T3n}85?~qr6jY!oHrQJK#?WCf5m=UxM;8;6uyX*Sv@WqI9o^w3RANm7xf3!6d_?c*3k_H z@J|5XL&ZVPR&s|7Ge_&kTs)M>TI5kc0)$Bv+pR6g3yzyk4#vZFYv(*!*lz?|%1$?J~JjpU!C{GeD>l&uOd$UB7b|LpV zl}&@uMHhX5ZZFYNlX4jcTpPt`a-wvnMT~WNivadtHdNcYB{rRwUQK6S`s5OYfwV>n zrMMm8%xV6HYQU>48N+H2jR!dWLGKo4tM9MLAR6L2d=x_j&DL!V0g4^ZcH$4bxe?|^ zRMZXPX)pLN(1;airtKs$Tw6#UVzjFvY%~tw0kPytAz(vQiN#eLvdi&!+jN)VUs1nQ zQ6LTH-E(|Astp+us}Nc}v#(fs3=6#~OpBO=b@$qUK*}@w6Vu?Btk?tb3QNx*arCOp zqUtrk-*tdP-Y``R*iX2IYZcgZyIsCB>wh~JBAS;qjnWeZd0N%k7*ihvHw6=Txq(B= z?fTPHtIZH3P|Jby)(?8GVf`cBe%n|1B_60Fr;{WsYo2rXXDb03A@e_h)^oUUn$8f( zlbYNd1X`y)FQ3ekjqy6pKj~JzcqDDu0I965j2-$NtFm9mu?y@1yeeLm%pFr~+pgzFVq+uzCOQ5qb_M`*PORo?U znn$Cc(+?o@7|4)$#!j=2B@=;3>$Vgf@MUoSKKw>IfFhVa@o6lZm3-y#S}9q0t6iOj z7|iv96)^q0WdZUO`^%p!QS;=>#reruf=kQl)m?KglZs>g4Qd77KTc0!&SCE{c(Ifl zT84ntKX;ZQO@i^{I@K0?Ht*;E*xcdbJ%srvpbY1BEDaqYSCn!0KyN@RvUFTe0v?WZ z>EqU7VKfd_JhsW(C`RN=s_svFK;Y!Gkr7WL-nd(IHJINt#{D2t+OS$>cNBPR>1H+p z19P+gGb6ATDZ#`|rv&&a3OU*M*5;!uf0J&+>YpV+CkBz~vp;FU!-{=!5;a#8t5up+ z0m*g?Z~t3nhxkDE#@m^Sm5#TgelGmJu~LrmJ8D}MWlb+U>#M{3RKKGO4zFi(mO?n_!`LF`9DB_S3p^fiSYvrv!9b9io)K8LW z*|^y`Wgo^mU_M}D4AF^Fy}q)S+IxFiE$l2}Z05T*LO*nh(bnlG>}=#0&Yh*OnYMi0 z5g+_R%uRsLas;wXym_omMnXFY@uO=XOOLVe_S~35h#rh^@FZ=!)5K zFC}kKV5nDR9OMfl2wE$Ri*PfGT@kq4ATXZjYxuq^c}JO7a;gOt%V2Vix>)vN9q(Hz zEe`weBDnPC%3;wN_F&7n0_K(HJ{+t&3_I>k>PfD%)jZsPTnC&PYi_E%AkCC;6mJE5 z_4!njjy{EUy6?Mu zCZ^1Jxzk=!!kjFy9)XXTuJJRo$#~CUHs2%!{M_RBjUAr&V0i2P{r_+w3_Y-{%EUCu z0bBNj5^vByhHkK~*IjP0gq;uPGsD-BYODm9W;oR9W@LSMLvG$@*!<_%Sc0I$6L#u+ zGLuGW&}&2C1q_ph6JP90422t{GsQK&#wKx7qZb$l*UGFTg_n91q&C&~UB*hj$Sg>} zqIc*i_Ai3#cMuUbqzuMnte+{wJ6ruB)WR*%M1G(732o1|I#Mw1vGtD?h$+apn~PEQsa%J#ZuBgu20w> zaZI0S>QO1-lm8BpI%=6ZsUz{@?A6k_)b+HzH0yVfb1k)`zVI%$7S^v6clqVEKgPOz z%7)MAfBJ8>bqKttC_NaX=QjTK)DnAY|6=i6L+G}(k%=Gi6SO$^k&!RAy|e&V^ULe13(glIFOMVJnr^6aX>UiHM2cW%h`7u{(X z^!??XuC(e@!;F zY88iTjCPW~u6+(?YyHACh64%Wl9u>Vo7M&JL@&iLkP?g)AZ^p)k5yPr{5%lj2PJVj z`@OroaFfWN3{sD*zk>a{?J}l|Xeq9|pPyLm3@Z-o`ZlwWnyoiD`b#qyI)xEW1@$g* zdbN%y$S}SSxMvC8XSGn9EsuFYHonDd%5-zG@QsHRaU5mb>b}%P3ilv8iUr z=(=S$;PDAk&F=E5OKzA5>c^Yzkf`;?hbIme8$Rrth@FFZ4wtM1!fHiLT^?fv| z6zbLe(|1o>I1#u^PcnQZO7hHzak!KngVH`gb!E+z&<;nFdi-dNyEje(oAM|5@r7+k z-dkrG!~YRIjalWXc7A~IC?swa*)tN{K3yY9%Gz2*lSU;Me_aELPX35R$l|k*$&JJm zs&-&-QarQ91j=YmA{j!06cC!z%|Xjo#eZk*;}$5GT!9Q4GUys0?xoE7FZ!S;#vm#P zmOD2b#z8c9yH(g8_LPyjGJFGvsQ3;<3Db^oGv`PG1l^q#gw;!cVLn)kIBd_U9NaZ=|w`mZGo(jo*m1?^*E*f8g0V|H^jkIw0x#Upu8?ycKl5{HH%?{7fO-(*xpv zEMt?9h9U3DDN|nh>Y5i2+Vsel7dub zQDFMG8W`F$(|(u3_%^NefnORG7S#L5xzVog?FY&wcE2cR$pJFa(%g;(r(g~l7L5fe zLk7RZc#wUF2WRpGu@hmc;IASag$_Y26w&>T=4~B05raX}sV6J-uY;CUpk3?^~XL(xU;b0?n{voK6`P7D}X$ZNTQP-{y1)8McAE*Nn?m4-OP?ds9lr>T66 zT>Y3fO|re6LvQF0pQ@eseP!=XAFZg|RHK$+sK8T~Uf3$NV?Gd6v93|e?xNa*Pj~$; zauY5T7jQ)Tux$y>4vrzo*itvWXIv}!Owesf-C}QAtppeM<|BW))ZBXl`I~%~w8sWH zwNpnrRbcE|*pxJI`^}(cny}&F7ZTdad*;V3APW>gIn3Y(XB3{~T-K_Ru!qD?1JkU0 zn*`(fhf1xAy0YB)-fH3b+k!DRzt_ypVhx?I#Fjx_UiKipNd+v?uWYW}mXyG+ZdK}= z41_!P|Mase6S}%`BWOC3s*ac%EwjhDZnFid-hb7w&6!*nU4?c>xE?necSn1s+o;41 zoaOSoIif^A40{-8rv}`Oi7)5o>uofAqqt=pFqJ1;sjBcaLi?7gE5^44fT_y6yRCd9 zi)B8Hcxa$TdCf{hcGJNjX&%JYD>v3G*G`{4T8 zeeI4CnCa7l2{LPlYt#83mJ|mTZ!)LgmM*|!p*+6rJ<*{+` zNoFt*Ti$yt5Ku^I85VdNoQjtr|G;_H5X{$_dYjNEKs=M7^AO=O&`s`Z*?j>6C*SGHz&s@eH8DR01dXRrKG*Oib|FzJJ zE)6095y%O;y~Zs-;9jwJH_9m^xHhZs13QV%6|{YDDy-xy2e7~vnj(OmkVByA_}~YI z5^UeN)!4b^8wEs1OOkfRqH;`wfX#NVQVgcPKOl9e1 z@}Bjx*Qu`ZTl|mQp2+KdO{;0sqkFR#c0R#0gm)kVX5ZfPx9eV^li4-6nVI&)QjeQ{ zltL8@Z0!oEiwMk!a1Uj0`&^Rhj@4`#qxyV=7_3@Rrosjq?#?$Iuzyx4O&|5f_CK#J zXHM3aYI29Tqni&(-Noe^!UpF4Eji}Td7qS(vft`t7O60uhn-sL$*{b8Z53Qwgf?Ea zn)m%NU{jD}A-T`sy)PR{9`u65XD~TQ{VZ8Z+(=}WYGOg^f5~$AEXLd>U_W;b$b8E- ze71~9Hxi}{1bv*m+QCR@v&Kgr@DEvVaCs6`2B47Dsrcf|0}W8S+zoiPw*s; z%l{6(O&uKa-ll(|Z2CQALVgvBYR%G=PNjZMlkwlrb$nSOgfc;9ly_*I<$uZgp!?SJ z?_W%oLrOmV8`+XMVPsbh(yT*^glJmI|ugxZT-M3h_pyeaDfF)pchBQ{SO&yMj2r+ z#lD6W>SXP3&%o_>-of48;!S;nX^7#b6AyyK?3yM67xO38GkWE`fOvT1)Y1V zEDAnll3YQN;N4MFM*PI?Iq6HD7A9`tx)3L`&#{SF!G?sN4?-Qi1|2z6uw~8`vmc|% zOp-^g#XTtNbwp8yk3EGPKh`b_cEnt9O{_+}&DsySvff$WOME*Pl(Ax+Q<)X@dD${4 zx{$ib2_kpOn3| zK`OCFTB=wX!kYh_$+cHWEowFL5ocvH_0n~=%?cc^!s;X7qLoX@w=!NeZdTi!em>TI zoA;yMaLTL0qv|@!LPKgf>(&q*O#i^~i_-M&HA&d)%wCKdRnpdP3*{eKs;LFBYek-r0?|! zDfXo~jcqhg88$nbJ0QCC7k!iesQ_=u)Q{m;kh3S-g%6I0O@vdT6>I?64`zw|C0nwB z3u57q5bXc%ei$|^z}##*IyB2rSVmpFbr&sr#5hULVWn4V|H6K@(|0uR_LH+06fLf3 zdxpW2kgsFCNW5E*s z@JXW6g@;HeC_fwZP}zNy-D62YqkUJzmGpJnHz3 z-9=Tcw$^NOe}2T(7{LKE<0;W#u1PtHefSZsy*fKNl7TtjCGQ#2bg4Yyf~-dre8q2+ z8n&o$Z|SE?*27(oy5_zW=~7o_wf&PjGKWD1Tz}jfH{Wvl_Rd)&3oaqebE`VN*BZHV zR?oYq-%^{~egfebO9Dqr$NX#k)Iw&A#r4jJmI%~e=Ncbe`I4a}p9;c;ubQ|&aXplZ zHl_b)W;Tw?^)lN@^tCg7R#3^buDt_wqDVWE_xj^rB>c4(T~)Je{fXy>(Ojw^8UCPRR)+#z4Ced z|B-Z!VVX3(dUwb6%#Lm28QZpP+qP}nwr$(CjUDUE`<*}ir<1Bqs*>F4)Roeq9I&9q zYI87iz0eaQcYZufwZyVoX`zWCv_^R)EVp?o2z5`u~FtK@$+=jahxY@C4IKNS3tZf9{$x0M2(bC4A1 zZcehtF0^iqjfwgc-2caAyv$Llmy8w_gdn7qP@zCt8q!Z4UN zRk7+JpVt{I2;l!vC@19S!l}dbJIjBJj(o}W{#w&U%2L=6#a-++ykA~VA1rw1bWPex zwX>GA2ffZX(XC?n5<}!BDBAge-Dh;tYpo3s%}Ly&7&|oYu7o&9W`lBM1Q>U=6@FPw zXm~FQOB0)E*LRCzNPP*lV9#I}-v~lyvzW&?qRtP`n&W6;r0-qRF(Rfrhz^pgZF})krxJ$AejUCvvmAmaCDW+FcGBl|Oy+rUdqBVv# z3u3*lumgTbjcJOKQw^Yb+f}nC;|wy1IXyLxsTb>!ON@ciKKm2&NL?=#alqck@{jEA zd?J};>6o)>>YD@xKA&bCAI`MDnKB2oNyX-X8pMr9J!y<&I<>!zgD0jD*0ZTH7o{ul z!+Cdwe6u|x)T*j6P6LE2=7fuuyzS@(`{ML7`p7$Ex$%8rM=b%uuh*|O`2hepn(M3aP(P|%pVvGVNgXd(ecHXlQe z<<#^D%uc0B%U)@mk4IB?*P<~h^@Z0GS62B_PoX-K#3Ru%+s1+u=|neW`+7r#F88YSwfLQKA!nQoL?`y0q%Yd5p$r=g84OWLzU^N=>s zv%qx4n>n?=+m7cFl}Sw*qH=|zJIr*=5T)i*Ibc;?;Lchj;0|X|uU%6DdBaH!@7*S4 z>XK(AgN8%NCpvV6U>+aPz(bi&P2GN(Fv+2@`*BhTM13m-Nay6w9iTi&MD%F*k1>6v+$R7{AB{s0)d(8>>5GZ1=du|qiF82Z2x(x(iVqa zfNr7j`u&b=s5zyVZ6}4cN#U{ORDlR$@su5h;dd9n1EZ~~Uq>#&gkzTl70Ub%#z(ll zXVOBQ16sh%ie%R6WB2(Ji-m6l={Y;>_?^LgkV9n|QT5O~y4s7n6!U^nwqb_W!kl3T zJ~r*jEzC4W|3P?~6Xr+w;6+)S^SUE`^4ljsG{p>NjX+DfqyoKoqHvm61#<)9>q6y& z1xz`t!yJdD5c~e+3{@*xBBhGD{U+&JENFYB>Y~3Xz8x&eRjLvg13RHE!zc%)%Ymt3 zMtq3+M1-lpM%>;R$E;JLB+wqFbbNt3E#r$a({b;lag#GuXN`$#(XNI-oS#Wp>;O>JFBb*cnPdL0R(Z80S&{Cudke+b7Inb5j zhr%_mQSQNGlniY<%AAE8>}Riqu3I9(AOb9lf`>~<8D?G3pQ zzdHFntqvA*X@tn0yc6$`jG1lDt-Na>4WUH4b-H8?SayrwRxkAE5(s0+EG^;Wo}pU5utCmb>w?(9Yn2PT5f`aORDAZA8gc5caSU`m zb7HXY45)bFv2=#%cTA)Gh+S@8@(Ofb zo8;eJZ*t_EPFfoO3L)CSSo7(aH?$51DHz*WlfSQV+z;d`z!k=KwaPCjkzEun`>);?CtPLtZCO1T z$|^+o+S;kpXO!x_Y(VAdYqoK*2R=yZIejXSINuxuAvFkCP^y=B)X1%1?%LUV{`o(e-iJ+t-j{K-H#a4Ykf5cNYJo=cNn`;9sd%i~0iTpIN{ z@s*|hVlO0n#UT(lp%Df{(4BhRU;9l z5mqTkgCip7yMEK&{c09qpcTDCAo1-F;Q$-|aNv(8Sx&H$Uzo@Kk5VZfGr`+MZoFM`40 z4Dju)A3CF+PL3ieS=ta(@RxsWZ@456b{4`p53 z>5lA96m8j&n?Jo`&Z(BfRwz^-pE3dN@6!(YZbEjv$!Zu5gb=$o3G0K zZZeU-iicL|G!=U$ABmpt!$aw>(t`;r$Z^# zawf`G0!mZAL|#&z2;?-5`YNkUo46E4(ONt~A{X77CGG{gu@CdxbAI?auhC~#0}$CX*-TV7*G zDHkHG(pt5jYIM%x_02WU(o>%HC&(1$+$zMEpr<>MS(!-bqOf#Dyx+O!G)C%3M!gou&s`MQt?YCe1UZeH+0!$vN zA>}`#C-(JP$gs-KObwVtM`*?u`bA_cbhDReX4*4l@HE=wqE^maO=LtK`sM8!GsL2*|k6E&$F;bRQi{FEAfye70 z5$%)0Ec)=|@|j7kD^N>50k&EqCK7j1k9-JeGGUg;Q#WN-50Nbml1_YYTbB3xC}y<7 zIwWipk`WC1V69>zdX5TTKWjg{i=H~MIvtnio;x)G88Tz~D@4Zpi{Bf@6YFNhkA5ua z6Mp8aK+zw`2JC#TH63Dr66>fP(azXdN)#0jlVf8TZ-s$|CQ5gcAY+qll98J4NsLsB zh8!Lege)o89O;$)$OFKZ8M}N#`Q7mrEDFq1xjL{{ z1h6SDx|t)mK= zMhFv$0vxg{#U)EV8BBKVSoa#T5wzu9;ctdE+Bb1_n+8F*w*GT_empQ*2~ajltrGTx z+RAwvRL`19y&mww0m%kYThikU@e3_}`l_;u4a1g-d{1cM>EM~e!fp1KXf z7f#D}dE#DhPiKsQQd#V*Icp+w1V11~60*NNox}T>`}B8QfsJ;uqNY=%=&@B1SQba) zKIFXcT;st@wde1s@-$jh{vJ>kYE*DouLwiqOqhI6#Z(f^`D&EuI-Ec|1%E-UT`at5 z>la%2%*R>RFV;dX+Lu2ew4(BVA07OEa207d^%Kn5r0-wjZl;amS2=z7fy}W?nG+FV zJ^7^DQsolu%@8GmE7SN**lI}Y*_Y~l^B~#M_2pI!-a&0; ztQyhBL9*LPh^7cQ0N86_ z{vPqsCdR9N&Y z!H}Dj`htGY=|IEJ^!6tjEB+<8#quC}Bw3W15Am<%!w$npYPMQ)u3gC>BoCY2RHcT) z7??s6hjeK%Vcd>XZ^z{p&197*#bQCkF_0$ZV0_MaCxT|(_lJ$uFGG@b$`9B!;uYz0 zT-z)=N^(<59TCRxFpOoP6-W67V|Qf$Brih5cgOBk z5;D2@Eayv_3JdroSC33cAgCMS>!0;WFnko*q?g3D7`ilhZ^s7?kd?QT#TSKWnlSxj zL{-D}`X*TlA?ac0BVBFfY3MO#Ac!~b4C9+^P>>D^Rt*oV*!Bhh^j%FGP zS4`0%O2E(G9-$IPkvHP+4e{?hxLMF>eFx#4?O-VgamdSK*c+;LWl~6Yb$2*8N zxW}4=#D^N-1C*ybERdbU`Be?X;s*=~aZ>G;p9~qPV<5VVj7<{Ubkxs+h*y=DcegB) zCMgXeEBh+jh+ycVON89i6Jyp0__&^kHu}0vOszm`$Vdp@%9TM90N8D?F(z|1cKpnc zq=R;GMMHzdgG-KUYa?~@MczR<-vy$cHONN~>%;0P;f>?uv{Pgc$kw738{rH#FXfKx zl;d|_v;&O~vt0~YS^c&al@)T_1mk~LX-j{~<}_-cHIQIsZ*~MoEC0$z!4eEdoUUA= z;_huanr$VY*5t`cxgR*bJKPeY%PUTT9R(d=D@k8dk|w=joV6mH}T%j9Sy;?U?IL7XtsZ z6P#styX(6O`VG0uF7P#^ut@chT|o`%L8j4ZWMCDwQnKumXmiA$PF5;kH}>@>(a-9U z`#h$MP(9tGE+*2JIWOR!4!OylImkS;rTkNAA{yDZs8}t6+svAo$0t_=|E&CKJwc79 zE3lfABc9}@A_AurunnAz;tg6r@y$0*)FMO8Qqr{Qdy*lQ=Q(1Lp|?AID|v0lqE zSI+30q!n(d!G!Q*jCu&GnA&)a=q{!}nO#_I() z$Ydo{mI%f>hqZ=dr<#*iVA@1WW)}saZ^2-hb1<*kAAoFdwrYWYb^_u?<(i9Fny>BXwUxmD&VP&7E;1^)`Od*8V9Yn?W&}{b7a#B*!VrewamEADJ`5+zLzm_ zW$sXIRAc}3mvG>f5g3_r$$vj=(iJ%$KA$)P4s_F`obVqbeB2#?Mjygcqqd^n-$C^Q9 zjLZx*ZD~EDuY%RKBDsi-I`V-2Mbl?8@tdX)bTVEy#i@11pAY^3oTP%P!BptAwz6IF z)~SC)A&+qRVB1J2tqp=Bz=24v#mjrIUec7*Fi)Y(em(W)*E_Pc(4MgHZ;Cp8JpW1> z(%kM#=%dWmM}HD0F+9M1^tt+D7Ai0WI&BKFXTeA)B-rFEDD=SIW<4z6;t0{6i>$Iy z-N^tZq|4ZwljNEMTVX zB*AvlLv1M$%mJjOCEAct)$v8&u#w$W|5XpKxds2WNOCRL9|p}qGb(R~Ll{Ps1INyC zT-VJgm;b{6If)|3xmaa2Uo72c7|?G%QWqu1N&{)C0tm=K$h54Y8bU&I8do9;v`kq@ zU>vrq4vbKp$SF-jxf7_?9PvHseE7opveEM) zuvm=nC=Dr>G3#5pXc*90yz451@7%WIq~&Yi zdd_G~-4O`ZDkt1m-N!DKlD01WD+0zeAD$)m?%)Pne#fVhAT0Iom_FP3#Mi4N}UinMTf8X6ulm z;E$jd+y!rMu(iXd1%YeWx?JY=Tfdi|R2Ou04$3)t(}`LoKye?-`>|);7ZrRpjItQq z`4OzbhP+B_4tr~gCKIqi`;9U~q*fipZ*pQmWEwcA4*%7{8Hlcrz8)ugV|ndt3|@iU zxLyt#XPNJSH8%QGptimigx9HjXe@P~MuDgrNP2CxPp#l+;BD0^iDxt4X=j69P$)*T*dqNLibJC|o8>BFpH9%c;ROYhA1QgYZirtU zC@9Hdy8;R8M2EPWJm%fFlspywz;gEt^;0L@iR z20R0GS#iu_F#n2!j|wKSyJ7l`h5B9xG6VBBcRN0&+k|JMSM?xj;Z6Pme;t-8r)VZ* zLGL^Nh>)F)aq_>b9kOEKcmUeoNU})3c^<|vqal;*TW=PEd}qYu(JwX;;GSD9eXB)` zaMAR}=&9jk0-(Q#5v1rb3#?Bg|8c$jn#S%6qrlaj0;RGx2g6}y!y<)mZX9-{s*~OA zDy!H*g!va%E69jEK;ZR4?Tf&F?_;`()&?{exN&QWw%AVPx8uMm3O~L3eJFD-0b|km zFXUg5aqKqBsUYC_iWG;}pP!5>P6OOk1+xz$^l(@-eKQ=8-x*~JL%cnRMzo#t1ia(} z+V<*z9epZ3OXuDl^+^K;>9oEOAb;1ooRpLW0(Kq?IyWOR#w(Xo>!qtYg? z($zGHsfy2y7ow!EK?)!93P+_DiY%WmhLdc%X$14*0mwB>|MfFu2=cu81V?f z2+2}+?a?COV>XG(Zld{eIObZ*tuXj))L~vK{P$9D)v=xtRCZ_r@k`T^0*E_8tirA& zKCrJC_(VN<2=S93ajupf{PDF@cd@{m=!#=EdXf_ZA}%kS0Y;OCw{1OHqGhybxUr;56Bl;;* zBz>%b{f!sJn*O_lKp1#PA2%g%zrbmi5y%KN2Br@&90?y^fr%dm5akX|s0=`48UgYN zR=V%_>)=v;Si{-Me_vHEfD`|hdp);|0_zuz>#O?xaig5Ba(9V`+>H9YU!WloiKMWU zwC#`hCQSScIgFrc2h5V2wETk|Nb$6uzWA@aSbDIyuEU=r^#Y7U21}QZ!q5hX4J3$ghjnEDh_E4u70>O*fVWYmgB#*oLeLC&E!6F(^`AJu7eJ1HoIay z&w#+kJl)4DjOO)wSHP9-U$$VzKKRBzisf_UqZTmVO!OgcMN(T;06#i#b$<{S?Br0g z{|=xe+9BaMREjU7SkGNruu_-cjt%308{$+GxU9Yc$A5KlAtmaOu;#F4U5NQ$?iZQb5YM{as z(evtc=K61qk!glHZU7H$B+T&%;17T&FBD7&dJ_Z`9IxtQ3f`#`d}%KUxPix1B^a5gx|3N54h7&Wc`<(h>!tPJ zFfH>I76WR5W!#`6qOfRNhAU4Lms{^P2>yRC&d69EJC1S05^4!+gJPzfm|Sakq&<)Q z+%;dlu>Z&nK96Vzhj$*PF`7VOW`FZ=_Te(s`H6-K3rq~X2?iN%7)7yq!ESD1=%jN^ zKca2LI9MT6=**L%dKC-`^RK83iekmo6H|t8Dm;$JpV0pE!%824p18|x_e1H;^Aj=n z2vxbI+XiAo@SVc02QGYQ-Axrn&9zd|BqH+C3#t{b2Zl2*kHddHC1*?LbKj{w5FTJD zsZKKzg@>@Hozi$2@KQhgQI29nLlN?7KJRm#7TLp7P$`^gAQdD#%b|C zOz^OjgUut8F8{xls`+`QVv}?ounoeyN6V?+t#>kYeMnB`G;)@_CkBVOOv~VP@JMsD zpx!-6PQz0+sK1*Og}yaP0H@no@IP-w5lQ1FF*t970s9Lmn1*t@wNnNMtBnYOPv_U| za&_Lb>Hz?_upj84%g zxacd{J)nB5f6MTB{8gE^2apJS(pvtV!~DOk9=Xc9V5+s8JAUli2B_Aon?nwMjaf{= zh}EV`1Jb62r>ssh6z5-Ap_>At-O-Q2KOwzI2zYo%XdMSi<4fbmMTOvOR=uuTtHH{i z`=kuPU7Uq0+GCtRTs@@TC(xZb@Qr~-s~qi_1S+5e_1CoAxW(hkoJCt2B!NE5P>h~4 zn^40LW|8t33d0mWNAS_!>;3-CX{ESA$Su}3-Jfq*u?nq zVY0#=2V_Ez2mya;fN*EGgK7vMUuU_l4~95cu%gqK^} z(w|5n!Ttvpk|(PT$AQ$`f&ki|4FtKuTdJ{Bq3+g3gBqp141paLc9Gjx6 zdQrcVeW9HWXqBYbW~%stqS*YqJN-m>YI_ZET@`hy_&n!M2iCV&xoYg*LW~Pk^J!`9 zp$^|;XQ~pP0SA970*&S~M6Xm7fED#akEEgd$k~Mm?13HfYgu3hfu!QM+A-!h_)YvpX<@kR4c&q4`4-P4$mM%iizk_CpNQq3wZr42E!zYJ&H5W7@?C)R6 zQ+{jdX>LLExTq1<6WqdsZI-f3sR5ACBs#@G-#&pGpkHCG9PDq!y{>O#T3cbij<73{ zSl`>HZpvQF_W7;ykNDanE!MH)0K<}Dna=5gm#H+|Eon{!(pb=XQ;grZa;ZVfuU_?f zGVG){Z{v)3x>_3u=Dm!>_S!(B7oAQ*T=?lMOgi~+FNB>WL3<;IL2~B24{w3NPnENc zKL-q{&3P;FF=i_9} z_f=d&Kf&#u;6YGW{=yG0;!08h%*rJrm^XXQN_o-C~~jTJBA7_?IE*)@3qi@UzN zTIN9vXb~c&ygZ0yUP|sp8jHbB_#dy~{oZ0lRd;9A2`(^&*JU${TT`K`;~P$wRo+#=);S z8K)^D$lMefQTu1zS&g9Ok85mbI=z<~*v~4p&n%_<7fpyxS1uUG)l?e%kCj6|@h0t5 zF!THg=68(j_&}mY;jYpT>tr)i{GooL@Vler0LG0}^JxR<=}tZkG!Oj%B;;8wzoj3H zg@8T~7=C=0>FB;M6+Hr_4$GP@jIBNAVuWgX^Uk2E5wK+94|KQDU5d*E~9a%TA>nv@K~bYC9KXKz%LU%Cs6U_mSRdd)f@atgNpQ>z4sdyj#L?wfRU&jEo38O{(IdM zVf0lKaF61)``Db5-RfHPvUTH!keo{pPaHr&_DC=iAh;_NlT2*09NTh%gz}H2Q3Tzi zh#T%!lL=;?~ET3GFxxEkY#k z2O~U=?w##ThxscECsI3wO~3C%;cep3IDjFQjHHeGhkGH`a1%V~z6M3drvmOYj}0~K z1MctV+#gWs-8rz$Vj(E8YVbMzOdEQvobQ~jhnObHj_Wr}Ai^ag0S5Sm_OdHCvCYwZ z>w|Js)!WdWNmg{0J7^nYsv#I0x>56w5RhUwL1EVAMh2t#_I_kar&6=6K~dUr5SqV- z{qR(WkU-Y-;TmdD8S0C&U|8lDBJ=@M&kfJ&C)Eu%YtPy5+YO8qYV&OGnO@71=YTZM8n^5+wHc_E*W9n{?Tv5 zYJn71%^J#5j1;u6q7m_pxV%e(SYHYmkG6lPYfa0Og9%~}f6xy>33y45hI|T_@Au!q zOal*ny@WSv&d&=?@z%!>ZXe`~;F##fdPTDjbzuUR@BK5w1EJle`3Vn)Lv1GU_VwfG zJ6~j$?9l83&i{V9Vr3+baLx7>h6dMAYcA@~p5C>AQ}`%vOa`|3sb#}y%ddnCN1}(m zn4G_`G}=X;d|hU=1=8mQgLe6A+HzwTKj|Ft4xYX`Tgg_NJ>m6@j`1`|Mx{w0N~n5q z{LwDH;Bw}Q4`;6(;r!(&r6+5e6qnNUn9TLe>5en3MJuLm z-@|Cd1q0btUVevNaJGTK2iBdOK5Jmw{!oJJejlN_neMEIvUfFjM>IwFM7V98AN=k)>Vcc7IE60cBVKcu30$Ul zVQzOjp*_CTU@?$)Af^lq0h~zHgEzASmV=Y9$xC@p-=?cV?a9B|L4;g8qN`BTZmlEz zTeQ7f%lN1Br)y_d;k3$n!MW*;+g;nt*`Vp*yDM$QR0rb5X(znIg;(dP*}r9_<#9PT zy_{~; z5Xl%Uu(;=S`0xf1JDN{A1EI(jn8|A?*sr2aKYc6M4`S~>_1c>CR}FI6Q*Je{ z<0PA4Z0IOhdLh6y9IlhH@vVTle;beU2Ql-&3I@iN0Qckeixn)NDI^qZ9597Lj^{@<>3<7+^CJ-Zxae&k(rc@<*UWRhY+D>N5&?po>!|1;$D_ToWU@ub z2=|C=KbYK2X*`nj*}g6qluY}VeEB(#d2%)f1<+W)Hqr&_HNCQD%%%JMN!^RQn7>v-WZ_imBQbjyEsltH<|PC;$-;*2sL$ZCAL$C9T*$4Jed8M#WM8Xu|3 zgVFv*PdiWsYTtqH9p2T10!CuP1jZ%q{4Q!F3e)rLR$BfV_PY}{; znY;rlg4&6g?cu@~Kbht9sM}tbu$%hI4Vw;^{@eyCd0GM{i zG}M%i^_?!D1i-}U0uS?_l2gh`KU~Vz4u3u|8nS#u4vq+3jsT&-2O06lm)|mc@g4%Z z0Uf0q$F$$bKT4LL#Rv-G;js8S$qJ0b{hbpiHd?XA^Mm&B=W$}iWXTWtwR&SZ(fcR@ z)Q1q1esY_1Xqx!AmuVv+%yb)SL``p0aRjnLfJ?CV>E5j&>UL+X3{;d_3 znyxFR;eK5TJhvne>nnUXWT)lb!RJSchfo$A_zZj^1YAJ=!Ih)(4b#-djE_+rZI4K_ zdlQHDZa95IE?RpKMtjT}Vs0Ay69J5;C*PlLap`rczC|X@ntUjlE_MX;wO{H|Lc>R_ z<5Rfq{c~bnHAbOq&W&IodajKop=u-!f^r%qR@YjAe2^XyS)dATGtmL^Fj3Xo{Mo%b z4Jpuyv@|Sq37UVC;BHwTN2C12){uk;Md8q+u*FtdW=FY>&`7cP3~+uX`Gpx{Aj_sL zXq`x4-X?b+XRxjCp&nyL_zks`!OVhlXQGK-%R-G2W4pOqb;N=6gghU;4bLJoWM>r9 zGz>SM`Qlvele+ti-ITrWVmAE)Ro*lOX4PVNgVG$!T}t0(ir>cW`$vMr=1%F2E0eVD zs*GZFk3jasU?8f6xHlgFr$8NMAWY@g&M54K#DGK;^ zhI-x(XuN|lr<5RCS?(m9zdgqeR%e~~r)cw(Uxo$#j^nhm!+F3!oJK?NbMgPlA|BLS z_Cs4yM;-QeN+c4F0#Et`&avr9J-==z zYmNd7c0FCwV_7r3q(wauvC2gc>AmcUus}qJDY3eA1aEX=y+4B#adTZg zka|CP@k#bGF>~56brwcH28AE1t6*Q90W>dOz4~IxU}(9eqi%==cF+=&jjo7)h`Zsv zM95=YIqzg5SW8G{RS=!(LV8a)LwuzNUGKsi6KnjE5kf{5i%)J2n(qG~)R_z#^ay9! zEbQU~8L()SxnE15&keGE%ow5mekE9XiQ zL6`94bN@hg@4d<|qeo)PS{YNjkLjI#(vn*Z9}gFt6Y~%`Y=d_NX5Mz#a{}eXmlm)H zai65+%!oioh4B18{(A9Ipg@>oq)qoRmXxwQ>B3)Lik|2^-F*)!e`zto@*OGU)P zb$6#jg`>dC+AxH?{K`+*0vP+GtKg`}0yhZsDKuZrwLX!4;Ng7SM>>n}G5Q70Gp{4} ziL^?(+=nGz3EfG5R)12WAM7uDBxow*i>E(TGEqrB8Y0Km z*ECwPu=vFdMsOU5vYz_`o8?9vrZvvySJ9owNa2AI6J%wGE>SuU!=7ChW6^RI5S{S$ zfN@6_8_Gj?{Q=bf1N^p7jjKAo_nx=)2$caC{70qe8>{r+JWntj!$`P*J4el%+_Z;1 zoY%lekLJTaQ6oLcy{G&EIle+eiakyyjLM<{6)CpcA?}AD-}7zr`XQv9Ek}047iSh1ud`Of2bTBtu?;}S-hYwF&I}j#$sNbk{ zHzq`-e(mle-Sb^HVSzQc4zcxQ!_b^jPSr%qacI%tk4T=$Zx<1#*wMZz*7L3Pq=@vS zyuO;Z4DMIwr33GyBY<-s&L5JnxtyZz2xg>cq#r^t!I&+A*ju|lv_CHBr-8gJcja#g zktBqLFbh9jw~Fd238&8yh|Z8ss+fhLaaf|;x?rM1`lp6S#`sMKW^hqvH$ z{db9De-puDMDHOrntne!G4Hr5%!z@>6wyNzan4}HAd@#d#&^;@ab$Q4l$}admR#Ak_dC_LHmxE!vUH zKmbem|M}o@*w+bqX6>3;z$(Yzb4zTy$Jx$qAT#}tHE&`iGG&Lr;EEGPH47o#J~7C` z^?=x6!0U5m2kfygNTmXUtapaRk|B_gr+6fe=&*a5lj=MBSa@Jxv)h`1UNA-9iNWh} zzvvndNz{Q{}7&=f0CaK*W_G5uNp z(95vlR^O5(;<4c-=zOhi%rW!W?9knkMQU_XY}EW9Y{TL5*!+-rx%nd1;Gki{K|3*> zG+}vi;7)hLW#h=RzPd4;QJ(;Y5<5}cQ^6jqb4O7vE`$-&Ik|Fr6REhZ-bb+NLZHsEo`Rb&~cR@$Z?RuM9u8eBp6-uojRM zFy&+105}sg3aAh-P{$vY`{^0PN!WU~H1jbPNZQ;md}b=AX?Ez?Nt45s4rtiV|Ec~| zi@n;CZq+JIQC%i!Z8md&75OR|Hh19w^X@pDmp-{%o>r$c7ZLX$DKutCV591WvxYulwv=zZ04aB*N}yE>oNu_q}#xkzG+PON91H=nvVE7*@v@tXS2Zt^3Gm z-Z&L2_M@v%*wju(Ny>gB*fq_G9OD?>TQo=7r}31%G1~?4Earh6 zGJI=GFskgfQm57cUoG~KP47LPxY-e4{_(e2S*H5T`I=o;$=+sXc}B4Q)m>xX0H{K> zFjVsx3YVm!U%N3mQ%(8o4!4|rYhyMfc~0$g1I)k01G~iG_Io4|i550sH>BxXIfA zwcF+Fb*=ebdgsNX8Ob~q@C5OHEV*su;oL3c?-ViOcShTpJW9KQT;RD{G9M3kqV@gS z+EUPdP-Dm$Gm5Jc_28FPwkdfe&YOV~4lr#KoU6ons~6`Qaq{pRa@&yU$LT^Imy{u1 z>m{7SS+`lWN5{%U#zsNRQ%SUV&U0r4QI`pi)=Q0RrG(?8m6?k@oaD@{5O-``FYY!{ z2_?nIWmz} zjUfk%k%51RZ~KqdX~sI5h#1@XhVo!7?(6W%Qd#kR@KRg5nj`H(xDi5)gQe&dPBFlg z?r&*vsd_h2*bFPwjc$T@?Ba^q3-4id{-ZlzO z(xR=I8aOY?8`p|V=+m%@@)>(LwQ6WZlX`E-aV9v+xO1f~j~Y04YjYWtaBXh86F793 z$bCP7B9Yf;nfUH9-6Q^fuq_ttY$a!#3(0Vib^SPbc<7vz*tcm&sB?%Rk$dzXIz3{V z+g@ZHFNd`=xs-`g&&%P7=A`V}Zvtq^wxG?_=m^611qFVKdEh$uM=(E5jE&FvETiq( z$sDiGGB@hT55YH7b6Wa1UtmlC6Wl6kj~iCjws9YKy?K5OUF@DlWNffB8`4a3#}Vf8L; z8-sSP!qw)a{pBFj`};aVDWX*-WU?T4dnw`gZM!}w;AD%OTy1Nn1}tmWy!kXB5LS;ohPRa^Lx*hIWsG>#`cV?~W&bWH8+0`j6g! z@Hpp`o6})b1aW?hdN@Wah23<*eXzQChq$fE3Xo@;H|RY^U+(0*q+o1-UF5ME{LpW% z&+^V_0NN2`at#}?*ZDH%DUI_tEFD}XoWmY%QhvroHFCOTl8P?N%WlpS^2j;7Y->gf zE|bO1;rTh!^2Ry0i~T$&A~>OsinA>jS+hYqxjL=whs7r5fD)WoVA|8ea%6q9Ezr2a ziscKm_)W?BoB+{bAmpvqZreqC9rbS$9){* zr&~mQ#`AlRK2?JH75l)x3=oGI?0wczWOb zWN+WMcKUurk=&n+YJC4fr|(C_#RC|~edh<4+G6qON`VqB;8Jx!3QshA4teyc-X6WL zty=QXPVbmjDf$9-eo5!gc4qSBa0l&p{=^cs&kpW(8$5qaC?$KEU5dMqzr%sZql!aq zr(k#@jLDHxjs>}J-VCywv%RhnLqchV*qy_p$&Y<-eL%>ZRgj#M60Q6YMw{Sdi=1!_ zF($5S>TM;bpVKN+mv*jn%VZpK8D4gC?vf1WaNqf&de-WDv~LKUw7~bTIYU#zd8)&s zZtZ+H;@Z8ea7yl7(-Jv{$B;eBy5m~?!|a@t*lPk*VCOY$k%OyfSLh4Q(_uyJExrPK zi;&6Y9A0*N6#ILfbGtk_r@k2#@glXo<@;Rv0#|zJ`?($V$nm)yt#5Ym$PvFDdo0<3 zfpqXl2rTITFE)Qd;2<=B2r^3s53aLNHf)3NjAR?Mh0P~AuWh7xMb0LkHbnXsTSP<0 zO9O;RM5;(zD%)TTh#7Jtue1g(^h~5~Y3{~Da-pYfZbi=CH9oXib%$+mIJ{SFG0nG6 z`0QJspyVM=?=Uf{J-dUiOmq))g{FwJDNi`JNB1;XQ^j!XT@CFW(z=Gt4rxg0Aq^#w zK&C?)Q+W?*Zn{gXNaJ6zdPwUUnmTM_dD%mn-AlP?wJ31o(?gnn80g|Ep7Oy2(wwal z)0|A)LWq1w}|9vIlXm^)5*wzrCm;AOv`D>9PRWV4qfuFujRDlP2}|Y_EIr@ zd#ok!g}LWHFt_!?y-|$W1)Ovm(x(aYvvXTttc+Cy>}c5;Wrn|&efr8A<6kfP82t8F zYWw4Q-r#K6_wAQ4NgyY$*bKT8@SZMO>-p*d=V>B#kNC*w8h&7W^UVd(_FF5=XwuX zB|~mY%0=1d(y+~eQZ+jKlw&6nsROtDs-6)jr;M+$&D&*Zo9uMXL^rmz+1zw5W4;+D z0stjagxBhOx&YfA^ZKrhhot8_v^B&3iyztX^anNPReLo~hlKCay;d9qs1cgR?2*f0 z(oww(*$_QwjhUJ%v;)RG>Na_aa#$h%x1{83+GeZ{K#C}Finl!H zy)YV(Ye*6TTTB|^?*POv12dczKrZRhb+I`6(g4{aNjJ3lw{KC}F|gxlq?jRQE`T6u zfABPBh&4wNY~bcDL_or9vfY}D$&mA6BUmo2Vw(wT3I-^m&{X71m}^(1)lNr-U_Nnm zrK=^T=~G!GfNanPtG^)^gB7|A34S!-76Hk^Qu^((<9lM~5KlX1x&>87+hP=~Ws%GX zo2rc1KHMc9?eNqy#OjcSO~lo|b{wM+VtPp|eB;@BR)=k#A$-o{@J2v_w0&lPcbN(x zC&X5E84s3}AY=kS_NfV;`WKhu7!qv5jY#0uq4caI@x>4KG-il3p8$}9*2FUerDSih z7J5xpF+*ao#sJdMWnQ%=rh8n5_?Ka#(tz87q+KomDR7$r5Ilv(00M5y2gtF>0P$~Z zR{%L7X?Fz3=Hy7eAE^MsP~(YI=`trwiVvz}Z@Nhv421NBecIxnN?Q7Tw0So{mpN4c z61$89Lr5c$h=O|xAcYoA2^O}gNEF8qOC&Oceu|f~W_JX{S|V-1j(s^-0c4lhP#OoW z#REdGH@&H-0CGTV#Po{su2$)xw<=s9$!ElN!Rq1|Vt_CRT-3%BA9@&^4InzUDx~>J z%ikPr0HIAL*gS!FZI;?fu(nAuaXpkCut0`&CNK5S0Q-;_LvI?Ar*`Z`#Z%AT-S)k^il>Yt(42idQSsD!l$T5M z^n!wQMZM}+)?M@Tq+Rx+;^{rPdPowz16DkJU1I2`F0JCJ56%AVsik>}UH28!Q>M5Q z(}QM|zhzkQ)YI~+eQaLwRDCabxvAqJl_?^Trp2~GQP^m8OY@X|%7PY~po*vTQ-)}V zx#FqMS+_7$RPofMoX%XW@y)6b;A~d4gz=3C@O2ShTsUXqu+8rm!ZPomJl(F1yn|xC zshTRJF}2;bbLx<$({#O%2KyNUq#})1-;S#F8XNG50#7@OC*DNixGs5GA}!r#sWd{5 zKgjmF#b*f8FdsUbi>b9L%^RypEIVZz&vvg`B`&C{bm5}6u@V`k$H}sJtGgrHzU-pt%@VGw^=D0GSa~?@7 zE(we$1TJDJTN$Z}KQEru3 z&fAcW-q`m!7XdHBYNVz0*7L%R_06n_9He@q!&0m{=K$QYTSK^A5+E*Z1a824$^fb0 zR(e{&?Ur1?ri~q|U+P5(Hw)bz^Ji(e@tc6V6fF1jk>GYjnBmS7yyz&Z;5KKT-qVBw zTLm|V*ZXND-@H3}xis8Z^~MZoaBDhNIa%PrAm6e_RCzx|+CC~om3(84VGiVnG@uG@ z=PZ%TAJ?$QM%KVZnn>bo0zt3 zyP>)HmVRwy&hC#0mJI+pO2p}DtDCp+HwG&#&#XmL#Px%ji=boL4oR_p?`W;g3#Gs~ zD^E}Bvqk^HZxaPwGosaTN#3Mwm1$_A;7mip(*->3n4Py2hT!Q#UnyNuW}KFy&B?O7 zQd<1%j0cB=-33bl0O|NNkZ&EM?=Cx0rJt@bDVeFWpAxJ~cHIXFf<^WgY3WkDBtyjY zpy)FDOeu3dG$KRx+A|E;Dj9N?Yk``+FsK8wn_#B2+z@apoQG|u$dF1RUAEr7!Pu8K zk=Dr&6bB*-d$k>u;+xhN0EA;3vEjy?1-rb93Q+}+d~vWRSjAenz#{Puf|c@%I@q|4 zx+=wP+f%AzjvajToqj~4_8uOJSLE?cjgmxe-8pue)QEw;!TL}DGAgHLQeBM*w$oHM6jg?bKW#KvFfN$s*PcGwh^*z8)N z*l3JcBb4DKHXVTTWTO$K18nRGU$6vpr@Zd)Y^{^pLEw!|pR zNesB{G;x&6{EF;ldaY4e8^FA3>TsSF^kg`_>QFg#cR~s|TaeE9u#sxl*p*gk{#xOMVZwXIoBDiJ2YDP<88E*MJf&69zX=%<% zvUM^fJk>={4N^S1Ev2t25(n&aIFyo>#Y8!sWGIU*W$~2eZ&c2%>2YS{M z+P0fibC6&J233dbbvROVhn zz5xdLc1)h0F=>^2!^0ye9sOb0tR!91;>U#5rnbu~oFSJLPm63=qNil2zHO42ZDKuQ z;+nqT;xoJ`J*aJqRaactNhksVZ^s(xv_QHlk`@6-Jl!jCJG5O6X=#VKUB>OM>InUa*CNTaLsGaB`>bsxSci1^wAfrjC0HwqC{$cH z$M_~`r>#3zf>p+Jd4sh^zThn*uMyU-lx=7xy?Fr57aWy0%vlB|<6c3~j1#;W$YoZ#jnu z7R}$#79N}EtVPTV8tzgvD`-V;=ex!GjF}9fJ`hSbs>yC^#-&PzT+^j#ZN8KuLmI?% zEJE6o+VFG(6(Vpe*sy`=gL^IiBn8{#c;mTFT^gUNZnia2#kM)&#ybK2XImB9SPmSx zr(7hLZ9}OPl(sn#x|*n>^rl*3o3m8_;g;exZN7qNdc6z`%auzeW|P_d zZk>0$7Rj$Ibbq!8(CLd_SpXoHL^@$L^;UGTt!O|z}i>-nMFePZ*;7rVk7NMmApT`YLJhYC>zUP8Sfw%v)T`fO^AE}s(H zS!1ifOW03n+iPstCUcvd)T!HsG*>#tHWOA`z%xzmmKJBL*v5?yL*WLyudCR0S1gyc z64-;GA_fOLOy_pWXt^MzzM88joe|qXNxW+!DuV;JQQU3KjUF5rcMm8n{hPfN+*pll zlphkBs4~9s9@RzbF7S1@P&l5XRqmiq%D6p28t@ha2GaNdo$>5`=+1?f#3mLV4zDyo zI&4EYUr{`+Hx!d$+5re4`MFA@-B1;OZROu9%><4E3-dXed@u5tLLHLoX%H zHmeqMIzO72;$&nMITJ1kB(R&d+Ge@Zw#`2_SY>QWvu%rnUo%?~xK>-?8i|B$ltZ?u zu9z2gO4{a((bT(jnM8j>n=R1`;ao_+_<-jeThYa~PL~OPAZ*&8CJgwD!4SA1jf4rd zfg7G)gGbch#!0rfOKC?;QMy8swrSf;YY|EjQYa;n7|Cy{gqEgsC6Z+1>$Y&LC_R~V zHG3k!?Fdl_&l`(@pf&^22abe+iwO9FHry~?mTkJy5T5#i)-H{M*V=Zmt<$xR(C?Sz zO#&lEp(FGwEgfGq4NHr{Jpnf_#SA%6B?>Ie&S|u~NV93V^`eq*hJ$m}@{L&fy*Rv;d}I1(MCst6=i5ptA*TE%^LCqz z@YJ8_g}&fpnXV?n1LK*^K z+oSB5vuoH^Vbhi7*Rg=NU?ZLvWylJ9hY0p)8|NaF609>JU=`b*6zh807*%Y8%{w2Q z726oNc5>Z_CUQJx4YqACSe-2@HEuY3c6PR?)S>_&C)H%Pw)i%e2g{lwjhIdgxA-AW zVF#y2ta^IQ3cN_$BQ_6x1zyjPi%C`|yx2yDT#;=DjIEL(w{+P91!pBg zHk%YLDlVWnQpJVSvMt$Yyb)fjDuR+~M`Q@^BObT)TO~ty$uQc6r=B4}=^fb?*(#no zX8w=v6;EB71JmItm$;4HsE^~%b2}u8!3smoYNg|L**9$qN2E13P^n>=%&9WsX5OKc zesENyD18FL1=An941Hj80HxvrkAyEu0(e2ugyIR=R5&GS-iQAqt zX4}#LIW0-owar^1k#8Mcj9x#RvR3|GOtKn0R>TOaLB_g=93}NIk8h#CL`i`M)!cQK-gwTr*k{? zIo|6!Y%5wN&Ny0HQ(&ZL9njjzzq=ISH8!NptH<;81ZSfonpZIjx8(wC)-t)^Y*Cs- zZq&KoxkVQYBWydaZNC&-%Op*gn{(A;n`Z+rD??FQu1PF-x<}Hs8yhaDDoG28bWzoO zJ@gIHpdCRs5G_95x6T!=XAcsKFh8sB}1-C>n3B1fS5D@*`RH; z*sQ9SNY^E8K|DK5TE(`NVwn%pDz+UfQndmIVC>Z9wpEnQi0`Z<9=Ggi1_y7K^JS*fvA-pfToLHD&ZL2ta@krAB78 zpQaL}F=KSv#kRJoZ!m&wi#D+1vl$)MzCq?oP*|X8ZHxZ~S^ECCv>yl$VLCoPoe>}# zih-+ejnnlqe?3MSRYH#o`^3M^*eapFX;JV&B8J{t7B-~X82S-xl_+4-PHo(h(fTQE z#I*P}I$b8xv`!Wu1>PZIdLsoO0Qrp0!;K1_dLNj9NAySl!KRbJwhAB@#FC7%-O>PA zrH;@8ko%S)42RGo>8H%hXU79_d07EjX@G1`epWMNrF96u0evKZ5bA5e+e(H+7Q9$m zhA^7*xXuYrI|i;>vg=Z?jV@zJ<1K-V*_rzTuZs%|tAmZ!^arQP`1ZJh1?vvutBh}} z5GnF0U3dHRa=J$k46&Q72NJ<7=+cw zw+e3l6@XQy7~8P9$L#D&0&8gju(MpORgvo(lQ}&h!}zMT^LF3{8+S&|LOHE%@$&*6 zZj);fkdAp_W45SQj zE!Y^Up-Lk0QVN7}2x;lTS~^QR;}}%vsB){w$2TnB2|0vPhMHm$pEZ&0ZKc(sAk*ZlAK`S0`t}d(}D{+E#I}?VVV!>5}XwmOh{8KZF$^?v4cUrHCHgp$2YH> z*1_UmFGO0L$Sbo9!2&<0O0bx(;+$1U^6iQO&sBF?yemo0`$+4;854o0cwfBQJ*$@d z-k+`{ic!!d>JY$7=O;`dbse4-roz=VaKQ$&F+UlC(S;Dx*QGQrL1SMCN?FRk~9}^ zi?#)&Tf_>N5B$+K(*V5JB$I<3~X#(R2O2B6$2M#1Xv zbhjNpZgH(d;e@2E2sT%2qsMcj;&&l2LtK$c6pO1#q>62O#5S$fnYB!PRv1M>(h7;X z^lgLMif#AoV?t-F*v1EZ+~7G|v@L`l+V9}lD1i0#;UqLtw^}R>O3kd(j@3XeB^{}s%oU`^#1_>0RR7Z z0eqBONEA^R$B(ztysr1`qGqYsYQ31UZt7mn&K{l1Iy0*-5kq8%5KG=5lqmDfAc}e_ zf*y=6AVJ_my@XI0L{AY!_8`6VQYH~Bfkof>cFwY!i_3nT*)zZM|GxSD-)tkvASHy5 zj6e0c8L(zT6hrv@UJJfdHFZXfOi~Sdx9@amf+@8bUyy|a7|BAZrVn3!3#`hK`&NLow@$vGq!bWY8>T!L*%m)>HkNp;mDTLF*4CGiBpdQv?|yVcoOPzno9-+Yo{It}m7}#g3#2O?1@f@^hfl`ckQmL$ z=M_jEOY` z^rZn*%}=Y*toIYK%K}Jp!pqD6qq2W5LL7*J1<5rg9Bru~$Kn3m!gx!S?Ut|t7~2SV z0r#O54S$>3yFiCaC1G0JFTnPr5A(yn-tnv)D~GTj3}@V@sVa=^0dgO1TwVR%4-46Z z5JM6lTX@8S!J3 zawlp5XAInTwx8&3z}BDncz&w`THgsFMhNT1<{!pMab9}t;C**Pq%hd|BRDLf>ev-g giI^riY$_h3zY*u~^*#5T0CM1Bz=$aS00030{~ZEP1^@s6 literal 0 HcmV?d00001 diff --git a/CPLD/MAXV/db/RAM2GS.ace_cmp.hdb b/CPLD/MAXV/db/RAM2GS.ace_cmp.hdb new file mode 100644 index 0000000000000000000000000000000000000000..7204d1514fe21b26d3ec8eeebeb7567ef98c1d2d GIT binary patch literal 18555 zcmXVX18`-}({^mz$;R2(wm00^wv7#Lu(3C`wXtp6*x1&Mag%)cz5lOHJ=0S?bGpv- z^mO&aK*q|;#LC1%CgyH!XGX@w%|gb)%gn~c z%*MjXOQ!mROy1hfoJ`Wp+U=_^^7#Km_b(Y+%|jA5Sv@>%sV7b{Rb5Tu_Ottp?)B#? zyF2OT`+-XNz5hY5z{|h7N0)Kd)5(73Vx^CtIJn0Y`U|wWY^O;xl`pH+td)tw@&+l^ z+IKeT1@ugsq^d`*ruFXp=LZoBwuzB*jz@;={Iz7Ocj4d+I#b!OpT6bC0*eq(Qkji+-i$pQ|@6HQJAr@QCXp)d?( zj0&9p?db&+u^zyyX1=5zfxnh*@+xSuw@-wsf*UdY(Yy6+OckBmr(5v6h)arF>Mo8U z+z+ysSNWlDiWK}_dJ1ee$^@Qsm8-@MmZyw)@GiU0?~U}A%1u$Y>(@_H;_2fO$gPz$ zI83OPg3=G30v_Ev&V;H8!h9>)Wy{aS7O2kuj8&)-=-J0O|T*FRod1t1$wL!gFTaqAYOIL)* ztjZusRBWTjQzebm@4WPaW~)MWuYc%ACYZt=Z{Hq#P0&q58f zGT!N|w8#zh7Jw^OCClw!4=;dE8 zD`|1Pl15hQGaH+;iVc2$jWv_dCX+iU>ALPzf!u|i27+UX%Efp;y}%-)yXKh3xH+Mm zJ-xLHgVrsaV-`-SoX_%~`u#TiW_;##y;TlA?|(-&xEVG2X0>KI(eCCNg*w&TKkh#1 z|4!q3y>$Cr4BXm|9(42Mo$?pJJr036n@}8y;kcRkeHl7L?@Gn z9sH_PKpDHcDVQfYE*Nw$S^1UZZYFCd{Y&eq&_N~!V7CqXlA`+q)j2CC8U#KnYW({B zSdF(Ni}}-Gh3WQV>sB^1D%BncJbuaP)T_~AlQn#j5S(_z!lg&Y~RxTd>79rqi zUixjD}yeY$7tn*C|_tMgXobC5fFqMhnPHYTjG&^oHo z)ss=S3D&DOSj(;HT+6*F$}Xj&aMN=8YFU^<_`dfFZ(I5GDk7JL4to5<$lqxy{=g=c zE9I|XnlSV_D`3^66CIeIM?XdcVw zq6hQ#Yu!=|p9cwJoowJaSb}6lyDnm6vY0u<%TLifbI?B9w=SvBPfjrOFu(t8jlv^} zHYBcb#BXrlkyiK z;e6CuplJVNis|;mmX|0)f)~g3NP(T#2>D0@lK7*PC^qn3e_~hQz-#;+icXZxkLsEb z#crb_sJzer&!xNxMYSB}Yr|+t7mhcTd0#?HY~_0jY-%y{n$qIP;0GJ~Qo@4QiDL<0 zeQY5ESEN#ST&cwej=^pMQ1SfS08EBRE>{9ZPMp6^?NGf~!r?_$FV$sQxUf~g?twe&bzf%P!yPjV6!%(V&HD^4DGALaJX9Qwt zcE5GSf|P#{{Xj|_Nu~`m{Z{vFzrb5Eb+vH4h{?rEPkNfIWN=Uwo!6Qxm1QNa3E?EH zUB$xP5uM@Ey%F{1>uqG2*0vS zo&DUVnP@=!M|LWL|2HF9-+|Ah%h(<%kPz}JUFnC^=Sk)h?;-aQb4E<=pI5@mi-}LZ zL+-VOw_|(mk9@#O)^fh^O)h^o!M@yE&rvgTuXv|;wfqyUq=6TAy)fy2_}bT#|@Ae zS(6_)=_{199D9`X&=yz>@Ko{*ySrmld?Nr#Zd=U515b7{7Z9%n+?K^ox!&Y$I(yp+H0AFnbo5W{kb5JkLn>e zh>2A%j6@cr1tYg;r5L@q(e+w1N1g6*&i~4=M0q)ZN*ja|2Vy+f-wIf1{PN@kGjBf| z3%};hoqudm)pCe>oyoU2w`ldcZf2AU_5Y>{^TjUsL|?j~k~?D(U~M@jI9s#v8UuJn zQHp%m^#^A-yvuPU*8Ve!yUqi9HXqKm^}#Uv=aQdWV8ukEWTz>MQfN`U+v1Y$J!ft=XR!iMV!ypZM8uPr46MGQ?VRi`~8f0td z@(5Xe`|_T$ds4%enUbW8R~ znRaM7X3wi{+?l7C-j4OaF$yVR-82=U@FlD0k7LVS+HUyY?Pb|?puxoj=fTp3KW*)D z)Cy+|6I`|gGIc@;Vkjl72jFIB*>skmo8$1{YqCd&{)-Om^f&%=$TApf^pcsMkKuK1 zT5;O>!};2muxxd>m;Hp>qIf(JJXQi%AAa=AJnzb3NwQw zbugbO0iR>)5Eyj%=tL)K*6quN_%qRY2xRq;1mA7i)EQ>B5Z5?rcR>p2{GytR(Yik) zs8dss-b5@;FP!anl6H&R(8bfyFI)ijZr&DP_^`_gmPe&QyFX9@@Q*(P@)t!8Vxxz6 zDNOB7jWnwrR$jvt6`?_^(*vXf!t$NmzfmuhsxpO`F#vqAzn^$hxE~`v%GC*{g6;oMO?AhW5(0M!ZwBcZbB}&wlaXN#$@L+5q z`P5T(Wf!Gzu}QfaEKvE;gx{f9ISnN;k;o{NTO$}uF4&=2E0t9YGE;V@R6Z!aQB*I4 zLW~(qrMFt8!=IuW(u-Lg(fn->D01M>(>X>lUpy?CSON8SJ@c>qpAY2+qq2-(FH`v@ zk2|(7IFr_Jn8!QWg(ZBDyie0j#=v%CjRw5Loz7uSbioj@&QP$|JOVm(1R@^wDgcVF ztR9tb6&WR@h&UFF{RkOK8D_!_=1$^(3JV_*roEwgw||yo%~=K}|DxvO=Aa72$J&}_ zt?>h6vLhX8!Yyi%R`}+WZX-9+cXq-y|%Z>HN!sm%O<2W_axImXWfeCxA%4 z8#hQLtZW}@n}q&TQo`MP)L5riX=$GK0g9{-AiClw7<{SE zZ~rRtE>_!3p`eQ3F_{QG*o`dbo<#Oc?y>Z#%!A1z1s97uYTgF##4HELJw3ciLOm^S z2Ssg|rc4Np9%)F89=R_leL?jLnqSa`)Mzoxp1!T23{)G@3F?C0E=p9-VU3B&wyiax zk?&q#-r4AMo=PX?LHP48TBMds6N*2SOVa81)S*u!Mr(399kWH8Eu#?`+_pK7Riyzs z#&`;cBa~Bj7H`>3)KrUDH2CL^SyKM)2Y3V5yF9w7{F8Mw>t-SAup3|)Z=nnSi(&r7 zNMw}?BSkMpgoi|ANIAEWcp&1?w-^^q$?&gGTYc(-|okE@D*1N+JvB zEppIbhno>G4xEuN!XX#ANDfr}K@tmDU{rlF95S^UE=?^?`NL+oRV_`6K&qn)?KP)t zr~CB>uf-|GXtC9=T_<;0_rZ~I1I-yhz|iXf)2LW6KRC@c1M(j^!4^#~UlyJ&hXpVa zaH!6**45L}kKMpSPEv{v!wR=w4}^iqz!+CQ2;TU2KZ7pOnPVC#6JjF_QhY>UWxc39 zh+9AQ67$6cX;W3V!NmR6Iar)FSCRU+P7tkS%ap4UDMeLQHRF?xwFT6#{W$W!!_hbF zw?{`DOy#fKm86CZLdI5=$1x-3FM~ zcvv+ndz^-bjv28q;VV{%%?g`u*t-?R6RYXp2YOB8H1 z-Xs#c*y7W(1qIw2hlfUJ(km@aPY<31V8;%l;yiN%;`}$T5+&id1{HO2WaG zpwDjMV@DgOdV(Ljg;KysAj+jSab2*#t?+mbq!Vg-y%Q3g$0#tVBs1)bq$jUE(=S&& z2<4Vc%A3liLwcK8go9TL2ncfM&zWW0F`Rgblf!c3+{$x(p%d zBf4^XKHMwIr*!;#%N!VVWX`M1^ zX3b39vM(4_#9}i_Sr>%@4_v3^7zkf8qFqNfwAL;*gn6`_eP-H1d9^wew=dihg59r9 zGqd?MV9z@jxbKkn$Yeo$TF1HFylwW-vwdrRuSZuRl;0JKn0WjeT#X028Cu7B6Gpr_ zPnYU7g4*%R#*a|^!pM!#DImn)P9_mg#u3vpaaov|jrfHhV-yZMd9JG4l%4#zWtW#DOMpeVMhQ@PyM zZ}ye9Y9aGvhuT=Y+O-eAtKO<%XJR!DBk9Ejb5E&V%RrUz?dxR{IPoc|$tqrOC;H9X zm2tPvOj)2T7pa=&6f6c3a1CEYRNGtC?qy8agDIK)xu6`7?OHgc_eM?u<*ydik3OkFhcDAaof{1bEyNt!azcIfQR({tUQW#%@U`oWM_pul zIomC%5Bznh-r0uqh=2lVlJA3B5ra}W>Ykx>B4lXOw}#+Y1hm1zeK`_J14y(=06p4s z6QwvD)Xnj%d}vDRio9^YGp_MdYPjt;o*r7vX8NRkpoCWP7V!<(lhP&+b~_sm3MSo= z|E^(zXYX-?Hl!=85O{<&tghSqs6hqdtJSo z{CcW|69Eh5+heEEUiNgyKTT;)Ij}rn zLg#fKHR`uDrY<;BCm-p8-_{JDVkRF${kYf(&W*<5Y{!T=h49N`pP}gu9G|diTm>4D z6Pi}(wfU#LX(XbWpPmR&tw4ess9J-?ZJJ%)k-1*zYE^rSQ2Y z91D5ZPT`?Pg=G{fXj9^n+kden?pWPUtw?B@lsMzOuW+a$)Tc)D-Zap(Zix43Ts(IY z#^xS(l#?Jw7vCi4yip2Db0U0a9Y)dcDg9GnJvHSQpR|CiJq^L^>KNyDVI4>ASzL4f z=H^KMp;?g(qvINuruV#AQ=R`v)Xr%@K)C#>FA_5;<+SSr&YSy!?M1n zxht3oD#cFNcvL=c>?d;FMhX8OR1sh@&MMzkI3-8h=%r)9;X@ceUW|4~KN z%xX{l)VwCiLfos?85!&;#B<;ZoP1JS$6KAkP~ED1(mH_981=f5rFaO~6z`0^HZe*r z{z`rL)5C_EXatXR+v?ulOJeUjpaWpIbK1U#rCk7o=tF%kM**ghwr~FlOC|r+8i@eN=n3!=1N9VVr1W}NUl1G zOq(<9X){Usc711~{0+d#k`Khf$VTsH)TK;dCy%S5+-pe}_ZHJbv!tSNrNl2lWa9pS zaBvxxB=DYQ3`=CMi;+z(7hW@FAUkf@7n21ENKHG93S%@70y5-|eDv7pxc|t67siNZ zWhJnd61g}-;-e=7Aka+6{5TW{&WQgKB?V_E8)A8kge60jOD+mcwL9I=%-#!;rUp0D z{BM7c+j1H{CKrRxzt!c8$e)`m2@pp zo!59jW}-*cxyh&EcKpFD;xnL zU#tn~(iT2!L-T4b$&z=j(cRUdnuo>~1lY;8N3i8#Cm>~j$ zJlfN~SbW|kNNx?}2}8m@L&W`%nuybO{Y~8 zUR-8-VnNq=KyEQ_R)5s9(u7dGmQFNl7ErzKvbV+&k4qhNrYy?@Wiz`w#hoRjmwdOd zrT1X2_9w;WXAE8h`A29bd4%b6eo+0|=5adfBv%+Yq!lV2B5=@s$9wdR!u8!}OJQ3( zrhjs&v@rUz0w>wxvMDV6ISce>ysR>dER3?p*0{JXzVsR^>Bm#NKAUTj z#WcZQc1T*o&LbJI-uj!a{F;-xa}74?o|;OUo}Md_-un8sIMdnNnD1C6cq8i?8^5az zthuXPHL5zTrX?+F4Aou*uYSHQF#Ou~P;kAoBZuI*BhWRe9upo$*Ja+QO<34P-Brvb#?TC z>I=G9Z5l;lhwof>p5(KhL{cx8OAp~fCbCCw1Kz%AC}oidAMLX!5JnQ8a~X^+G&gp3 z!D~#kZQKGK0!l{CHy(zqr()Y4)dP%)I^n!YSw0D1$)HbH$}WSsFj@%=BRb(nk_Z81 zH{P?|LCv;5Z?C{j_p)idIlHkR@5pvocP!CYUK`i|57O~>wRJ~l5S9;vsTY(L z`IA!F0!&U4Z;e5yFEZPLuBh#z$K_sxdg)4DOfw6B2stYLXSOT}>PDysKCI?T+|7Q% z4*E71eVfKlsko7+nwDE82-4i?yU2Z$q?#6U9(4FXMYKjjxFvONVP&iNWit$bg*VcQ{T=&>zdk(KYeqI3Y zep*(#TqzZNC?stJUP@4tvR@Z4iqhFKTYm;ma*BCe%p3dcm-SYy4YmaQmvV`^Xch1$c?{b}B@in3qFojf?!kESW?f3ODghP|E2 zi>h3322mXJKm?u-qsGq({QoWFI#_?`b+4+y2l(R z4r$%oM=9%y?34Jo0Zl-j)PeKGd|f!O-gytR851sI$!il);@iqZ7=9L zioWa-xgR{&{g#?K!`albD|s$>E}A1j)77zU*{-;IkIGL$yxE(At<1|y4MzUbN|sMz z#&N0b%>2L~0gV8>-1$V2IP#9x6kXLlk#r#*+4HB+A<5lnGCwL~Z=@%h zrE5LHCLUGidXq_%HYX-HL{=z_mTbE#cW;yXrSc;EVF*_Dhlv%J(8{G|Z4Q0f3|Xg& zf|PniOkEslUkd;2l{RFfavhrlrdH0ZhC-Lds zWfh{fcVO3j3Z4RA)7p4`>PVUO_03dx3N~q*ef%Q74E%(nyxxt8 zUJj)fKm3^6t?SDlA2fQMjc8<&msxiI#RZphDmJR$ia5{cgv}jh9=u(?`@`=aYH2Q9 zDK;N4pTqielbTHn!$kOU@{_a3HGFCZZb~2G)uSB*B~!impJ%_Yk;) zUn&E@_81onlk)Z%NT1JRhE1yQGIt3|J(|Yqdkkfu4=BbZbS9WDY=YC_tYX;OR>xW6 zEft54R$FMSWj!|1^VbI#9@dQy&I4V{&GG~Uc-VLZ zc=dAd2(6UG{TEmHGv`51F<8M^SVYteu?b^TY(KZsAv76&f1=${1kfw_H-PCyeBkV0 z<#rcPCehym3g)=gGj^}*pFe(7omxa?ml9=nLqgz&RibYb2K6A)4sl*{90T)X!8-_N zLB|ETg@}P1oc^EY9lLENR9V!izg}t*x>MKV8__=exhR4#qqG8UbM|I^z!|%>KJr@k za=~9YR;RK3@jAjk#%E{c)N;v}IC9@RiN*ZEzp3pAGG2cREE79c@<$CQY{Y$3;|zQX z^{X&`^qQ{z?I?W!eS@Y?@HFs`y`N616kd1{4`nhOulgqO-wuD?KWM{c0$*?28`XEG z_L$+3O)h9!>(dDhoyu;uOqCUoPzBGuuZVX~&_ZRWmy;N>aZ!fF19Y$HvmEiEwUD%P z3CBf9@9PRqM7>dJjhmiX6Zbj{MsD*|4-aI{a>wIKDp*txc?+wdI??M{mU0u8{WQF~ z{}uwR;Y67_y?F4xRW?3(D+Z^R?Tehk(62TqjRjv05)36+A= zIJ*+!T{k|$43<)u0^ok`_mw#;#syEONlMN%K%&)8yVOX4V1hscgqWNTc4{3OZjCdn zu6$(8Zq;^dkHV|N07z#|z?}t11kibfpLVj05?oy=_z@@!q0IUM)4xWq;Cx~}luycl z@~$KT)I7V$VE;T}=`Cn#l)S9g=-q~C)gtqU9i{2(M>k+T0(`vc_aaISqjqvNNDG|a zsD!y^`=4mak0$fXweJYu4)7}f9^w4NQvPMPM`hX>Qyeq@(CGY;-m-2znyYJee>_ls z0+KX7U=EyQ?>+;*euBL+XoZdH=v2ukjlfDPGBJ~8Y3U489nUJav1u(dpZ^+!9RGa6 zy&9q1qg4`4;+$Y;r1*5rDbLdJ5pSXgJG8CytuwZ9D(cZ7u8x&g3oT(22#;xH#?sbF zUm$WX(M`tu+h_nzJHoPGUC#Zxn~9VSDy7*%Yy4)~L$Gt#%> zy1s<+mpf(Fh#acY_cl_0k770=i{hD;rGxar8K}3KMkNOTSI*i|Ps&X4)GDO)myG&_AX0E!8~w z#k)_Xxu~nDqz`4#;(H>%ks}xp_dQvE#+=Dzv zo!|3Q{a*2WWn_iA{J$!6-_brA;}&;ueI)9($Z;}EX%f8rcGCEFe^D0GHf+>E=KHL2 zwkXtPLVqV_wC#QLPfQle42{6+7Z@CFWsqR+k?LbnG`*N*?dpvx#D!DUp5V}}X^1w` zHPUpTIa#Z4z|FLVXXP;X>J+SH??AHCwvMZ()K~7X;Q>yj#UBViL%_Vt*h3+{d#N+r zPl_u19c!yvvXUNeuJAure}68UF!dJ;ngKNQZ2BLoyMMbH;6U4{AEo*H&Nzb@(qemh zhQu_+js$DRMro1~?W|?Ys7MOD?5EJ$qn9Us<{v`3E6j#rH!9GHcjr0|=l# zgIqEXeqW*!K+7syE*bv*PNSKkMt3I(r@5t_#$yh|i_@p`KYtTp8G`Dc{+JsZCceWB z&gCvi-gPc_j_6d0`9VZlp#fWxviKcxcv4bi_FEMFKIRfIqE&!5c0!N<*)JJ*hDFTF z$14h}Rw^Z3GE6_PH1ynR;r=&21!6jIKtL&Jlp5&7a~2cVs;CevA3LzNR<8Q)wdZuZ zcssW?mP`O*6#?sk=MB>{NQ+(iyT7zn|5rw+37~EN7hr8}R%An>bUTqKNWNdq17Q*d zyQ}QKgBr}qCiJr+&A39nG|$1Ue%X+?v}-2B%!BQ1pLjfn2%kvz^-nqQj4n~#x3-;& z(`lS%iGf6q4ci~X3)bwIm1uWj)oL`oahUo1nv^J;;4hOc&%O`ZD4N6LALk81tadLf z!DebHiNdP;_pDHeemQ?WcaxjNzP`S4VL zE$i#x45nPE)ZdASe~6gLaaK2*ut$YyDRBz&*k%sI&j*z+wWMIxT(lR#c-6$5hDnF& zmclj!=Z4IKEY>SSkgMl>EmoQwcbPNmJ4OClc3B5rm4!Yo!q01Yu@f|^5{+wu?2lcF zE+eTIKbx#_vR$+<9|0*Z*G+4Td=nytIakl-WBK=uzm*vz+HT{DXxgRI`=dScLw2PQk7G$BgKr zQ-Vrv_0hlIvf>YDTsn1BiehhenW0y(8D0hOjVsXV19MPkx&xd^DZf{Qs_|wg>ZFD{ z4|E+eMW~>fQtw^XzFL_wMf@g=G0Pm=Y$4nkEi;!~hSOutyMXY%3sBYCw5Kdy8O-OC z+3Zix=7;&_?*oNL^U3z1;Kd%q=NLx3L(cG~^LuWcM_9)hyc;99jj{A(iOp9(IH_E8 zJgvla)bxP)C$8bPeV$!R&O`j?I+)F3l70C*bfL1SLsUb4$GV;_v6YUD<8;$aLQOmT z+o!Ch?%l3tiq6%ThYB|9S*lr%fzx!;Emp@^$GW4gk%>cHtlR|aGxW~AoHfi0DdhRml}e6EN`H-c4mLfT0fY6@XjU1aovR{$(B_7x9S? z-CiUAc<8;WM9MOmkj^|pH^9HqsR)PxwnoLP0+KJfDPEvuJjLcxS7^4^I- z>mxMr&QXuNsnF@|E{DEYVl>*`fOus5B5M#HgthkRzK*u3dA4g*CzqEPZj4aC>U}(6 zhPFzb;dO-I7h&Fa6q(&K4xXUWWQrsHh?njFKRjkq^()Y>+ejGemc*amnUd|*N%rgZzbKL&K5?MtrZ+PZm}PIsu%!!VgR%U z4QTV)WE2(B;tC=fNpUCm0<&=c-MCfK)>`#}0_|t*2q^nSV0LSk{6o!;#44P@uaoB< zGk^r@=jsUO)(kD`B220?Y%`^oq`Wo4U-a$r@@Lc`g%`@aXL>ZoT!>1>2OJHwnLH{mu0`Ced75!(*Xsrp#_I z(aVmVcKrDpO{0E)^x7a>{Vtw+xsc1Qrq=lytgtPO)va|ziXNSfjT&r?*N6U5T{KDQ z4&1_F&rgOL4MnE7T{-*MTq4L^cFAe;$o)7plnI2vC-IO300ai$)g8t>p}Zvh&B>V- zu-Tfotles?jMi@Hd?GZIulZm2{{djn8-mzlzT|^CSNKI)jF&0%10yTocJho=s&ho4v>QXIsio$jc`n z&+hF+RqL{bdxI7glu89_Q;-lDQ1fK@EauCGP%ngL`J3$=ETuKQ8#Ss?JUv2lFK|1G zqgR4si- zctqEv`WjW~aoZBZn~BrJ&gR2_B!2D)V?q04h=8y&%D9^X-bZk1KNle$ z7rg7bc6aP&qSR@+05DunvZ|*a^5~uOpa008YtM^`C2z(*X25fg7faOuB(o;E70g(g zzg(S9aHGV}dGl=odZ4WGIgfF`PPag~(S|U$T4agbs`M0xW9Ys%tpF#WkvrJ7LI)IT z(qg>S--MxBZo78QQg$)3(`~z4wyTsR!q2YO`OmL)kEz_SxxjoMW99oSTz zGCi~Xcsa+t<0)uw7BNzsc@kdTpdD`3#Gsw0ROPT(6MXzS1DV92tXYP$9*@4lFk7Gd zy8C1?y=DMmO&yQ7g{6L*{0@K&ax%`Q2uY}5tY?2J9wvyI1lV_y$b`zK5|qoRo6wTL zIYPzbE*)1H3O+>MX-cu2iR@%i^65kKw9L{^Z#RBJ6sqn<4U+Yl8~wUEacj|~VRUA_ zR>1>_CC%&r-&I6)Kc6xi%$Toa1MlbJ@8-ypC;l>L(?>WR!c`YKgB#)D;30c{k)HT) z>zY2Mq-)pa_Z8xm5LD)`qo_@)6x{yz}QI2{e?3-#y zB0MQ?I$y5gouLC843F0B9|LJLI`iFjT~dh``gw7?bn>wVwuBC|N2tit812OM1E0r& zO+hwkXEMp#KRN2n5JrNdN>fmf6p-Uk(k3jRqtqxY{-*4+BI6N5<7DyT{1sBKhRU?b zSeC2BI|#R+dQ=zrRgfOk7Ol8%>!h`Ey5!Ge-;L4%)4=x>y5qp%#Zl_+35Og_vw=fG zM4->Mv^1CSro9Vi<|M|rZ{_)TZ>AfZ{Ju@+@cD@oCIm$*Xx)82(ec7QP`u0p18?nm zFi=w_jX6m80`rfs`4UnrXHMk@u2%8ObtwZBMq&X+cPoI6gGxt^y_Kf4@5dQpy|{vM zMRzxe$!)8wwcocRxZGdA4Q09c{(QUvS>~b_pnGh6&(+Jhv6jGdXYHqiR762sb_Wrb z`kxp!xHmb9lsj0)m_4YJEx*7E1sVcgx6nQjdaVt9wQ{oi>&u;J;;;xdcDmv0+;8{_ z+^8MMG^GR2t6r<`bM@?Cg!uv6>L*Ia(iO4xR`7l(vu)zl+-f~_RF}tx()2y{5Pa8m zswKI(hTf~!^U%;q^y|zFV47>pHpu?Ywl{J*!955!8?2>#pEf&DHL5k%Q_pg`!H(8r zk1Nf;yDO>g53Afk2#6z|v48WU)iSGUYap`-HGR+AjOs~i>NIUTr*`D04(#lwqE}jA zJ~Nkh9IcS2neTRqW%R%`ZkpO56^{c~CjpLj!O<0KWcv#C@y_l)@w@VmxAfFP`EWa- z*=j==)33`>B&BVqU=FJ!W0b!)i-u|^*)BzrOaGm+^U{rawvF8J5x?647r30L^HvwX znFgIGyPxt!q4Z1{aAw%B&*(eOxvDb%$jskf!g$?$VZ26u^9Yt?9_>EX5CSOqyOp)y z8{`2~Kk!P^7q%?b!+NNSDKl-@?_)F`I(cMbF?S5C`?y z$Ky2Gg|qPe()G0H?@QV9TlOxF#2g*r-)9)}g(2NirW^)6IOT+Np=zY;rTx#7A7>!5 zcQNQqI#oVGK;uh!+j=5x_3u&8JL8XzM=knvpBmtYf6uqSJpB9e&Ql{yPYdU>BBJAM zCaIng1#79^lU(n=E#E)|@lQkB=1*#Vkd5}yFY*1)cw~S0Yyv;xoe~b_rlPy zaXBCG9P{!Y1H%9QJ|XErRr7snYII$b7(mth67GOAI0Zy<_Kc}gIwg^xB|qipNObiJ zPyL~Pe0uS!R2cCT-LXI_1>gvjA{`6Ygi>Y(ucO>(hfOBm4$WPY>h&UP-g zE;j?7q{JRt0U4aA;P^w{bZ?Uuo;CdHbBZsJQkiD{m1Je9l39B}HG~E^c&(Tx}Ks*~nY4Gn-6K z=AHZNtI75y2++ln1l4#blA~tf8E|^|0IXW9ZQr`6JRk8(XSw`P)8lkdfR1;>5O+E?$ZMEf5;uB#57KP@{GRv-$)RKY$vOLcH{=7gMYsph1*^8( zh9sV;5L7c*yR*T!jv*n}jJ z3Qa#tUANa`YYZ!@H#)}rTm+7N1;G0XsDv$*&^_z z7I8ex>kzL*MpuTbiK}_4K*LwhV!G{odQRsNBq&@Izr40%w?!ZmrS*1vTD*>JzBuBP=CUWbb;%~RW26p8MmJzQNJTm~ zggwMwOK@(7EfYolA+Lcu>wy%5f}4YRRw1#?I~$1NICTys_BXLWx}?C-*L4m~ z!KEo!eU3inLSmw$q`ynAny@)wE|1N`Db!|-rg#`)qytc&F2K&`QL2((1#c19+~_O< zGt&Kiq@?iq5!lqm(%@p`LI|Tb;usYk5H9W;q8rGP0$eyW&k9PTEH#E_5m~GJlrV3j ztvasX3d|{ARRWZaoaKK9Z<9hJ$vvB@Z+yuC?O2%|AmDj;=}C!2eVYv3ZdJE98%W_U zSVp#XK6tKxsj`uc-uN)ckAS9{Ya0}y;z2+P{uDUIJVYit24AS0ap-5;24SZBays?{otCCo*O{ITLi_MMQvd8WyTt}Qw;bbN zS~=Tc9@Dm*>c|Z{zbJ2z(yKqk;7sjaUE({3H&dXqd~~PLc@(luUR*XRn`-r|OeL(! z(#Qk6L7k4jxBf1YoFB~UfCh|sta>E!ee`0LnGUA*=M8MeST$pOXk+Vldxg<6Y6q?l zpeRLUycoW&@X}l;2fy2uDz$-yCq}*QD^nF-EV={`=zjh&?c6Hf8_?_8Dpus7QJo+k zGA3)Gj~#?|G@-@3<8r?4ADz{apS5QEl;`)L<$o;A7=&sU$A82ZdsJP&BaNSZpRLx< z)E50EoMV{ev9lW=V_t>)25O3X-{&jU01hlSyrX~iF)s-@v;l5*kWaO>$huvRt)HyeT9!gTNj zbZTrMvfh|ld?}i{-WXPVS!{)Bs!rk2Tp(y=?L)r?nbMqFu<2+GOS|Tmrw`-T@_mhb zmdD?dR)^aPwAuKEZ7)3W6i{$!Z;kqW%}&loYwoeWQ4r0sxr3@(PpZp@jsP$p(fBX& zF|YWt$_h208QuS%(%e;x?|%YQJi-g!H|9~)8*{bR&?6tk<@lxMuId_(>DM+>xTNQ< z>KmCPI~L}7jt5~q1DcWFy#fn19bRzg)~ZsLORYe3EUz|o1)Fx(G<0hya)dt{FHWBOkxbru3yGM|x0LWgXaJU&2KB6&L7RS}#O;R2AE+HQJ|m z1QzJqTc^^lC8soN&o%3;nMZo07u%~hPUUUJ09#e&nCg5r>DQq1Hc`6mBb(715ofn; zvF!;OFC)1w^g=Og#~IV^h;&NMYkzmnN48BzPSYM)gr_gWn+!4prP(_BR$vD=n3j)z z=Oq;6E>-=C@wg9i0$+)Bn6NXUF^YX2h<_4=-i6gUcxtzKHq$6hT!!1*A7``ZZ)5_w;5zHrQ1ovf$x-3vd~fnQ1zN*QzTxlM zm_MAm;XHxlj52iR9@h{vqy>8` z>(zfF-gcjpX&lq#-1}%tPb5_n9xVgaice*VJzDzmxV8i5mi9-`ZV~#(48vn5aLw|r z=l&yO`fuX_(-SAOW1td!NrY75CiLdrVMjaqG9#n?E6gL~(?k?LGHM??S`xF;Z+hZR ze**Go@j9<*AC;S{gvSzubQj82^3(Y@tbB_-;t#X=)n}lD9S6iA369{=p%`{pDnvN8 z$9KVh!7yxUM?&rHC5WZF;+Fc=nhSs37u?SDbS|+GNN7ns3rKJz2nEyzLusPVS{)ge z8>mKi?%_BgVaHJRu@$fH_(SX}DG`N<>2YP;$%$9m6Yo?d9F&+ItvrvEz6{6jUGO(* zjSGe2xA7QDbZ+K-sA$k7V(gJ2B*x{DQTqhflGvdoYoRT6LutIBp~f@P(o;eV9pWzXVjrga3lx?T$t!fLPo+te!~*;HgS4Q zTu3DBcsY99Jl3mmj^pEmgoFI1Cm;zz!qNoCgiUae$LB9Etu)|N7`7lCsR{Cc{VlnVLdAD#RVvN6sUHbn300960cmaHuYitx% z6o7A^yvw_kcX<@sr7EvJSZdqZ*}J>b?#!$+v!xpnM*@mlW2FxQsTyniQw<3kNTVo* zgjlJK1hC={qQ+3g9|nzykAFxLG}TC=q$(JS=bW88yW8D%lF8l9{qA|+b8nkj4x7ms zd++^@IvCjRxr{A^G358zdc;z6%~mvv8v#k?x$HE|la-0Lf!- zz^6AqzSld?LFPJ$$z_z5&uZbr;I+|HFp!Kz4&Z3BBqPYJ0#**6*Eb!yj97mjV{_85 zLbe6|K78WCkuk6XO(}8a{oGJmxZg3pZfoV1`WY_#3_#Ps+W?;F!o$bVp5;7fJ1(N5o1pqx=duu-o1TTaU6XQhPv}HX!k3{~v_s()m z+kAL&RSJbr5zB{<&+a*Q5C#%e<3K^K*<6dNb|5ST>r$3^z4(RZDi5`H#SgSUvA;Cl z-d#VR6pS|=$J~&t#f~h=3~HcFvm{01#saFq+@gt>1-B%XGr45QA-kE!7P7BkB5pso z@k@xxRd~@0G(|E^C8()fvlg)u2<^`C3&rRNMp=}zsYeZ&gIYDBYd|h$KSN!;GhF{S zKxyW=a+%gzZtEL+&Y!B0tG!TrdmJ<6<=+8EhW8rdACjKgB zkAsXWYs=@q?Z_;4WSTMDaVa8~kx2E%AGw%a6uaC(Rj&HDkxrLT{s5o{Y21jZX<1Iu z-gbW91)Rm|54rsa*nZy%N?z;HfnMQ>*vVEb!U0%GcKy;e@EwR?GvJ*CFNOty zRqQqR>-M{&j}^j*BHUCNh7==aH7kYh;z0&gban6ddb_$iFYC#2F)pb-5Wc=V1%L?EbGmv(S1hV6nq@D`CGZ8Gc)pG%3i9%^3zZ0-fE! z$rUwaSF234(I5U=hsnb5h*&3^kexWi9%QXBeRcQQ3K+aLbNboVhdp(OsY5K5LczG z6#bK)OK$;4z6n~DBDNk#@|e$UbV#>NoN>43Dp-Z?Wut9b+3qe7Wjy@?a|d;iGnMh5 zHiKleeubkUXz0-l^Q$N|pA7vsfrW^;I7py&B)ZHbZW+~dlPNfTc@IMPiv8s0EsD%* z*b(^l&2Kj^!H_1%jc_7hwG^<@n|H7b*$H@2qiP0iS7QR)Nv_9!eX;vE0H_foi=f3@ zt;w`Eqj0N%&R)0)i>EBtUG7Cf#9TC^NjIhKaFM8^=8)6Tosa(D0_@sor2_54QUVG$ z9wFP{Gd<`DR-YsX>=wyTBp>t}IwA0`P*3u{I92x&?h|CiZl=DZXaT(;!_{4YWp_2D z_e|+;BNhC)S6;Y_reoIKW=8C^(g7=AYkhF(&YdHRyh_d**xlf9Q&R|M z>uPjsJj2@j-+>`{Gqa@L%G8-BR|*KmDWty2PDv6FP0C1kki!JD_y2#Oed!4)0tpET z8NV_XpXOLHvtfpGM{~@aN6j(Jf0~^dlpH$$T#|p~kjR#%QdzIAAO2h*jg51`pT+6# zXFL3IjNs^S{B`$FZA?t_BgIn@5<(3{l`{JsRvkR0vhY-sb8W3`v(jT{nYlGF3s*%- zDm9$iR{Uosdk9OIE=OqZnyy|)CXHG9{@)Irpf%xgLYQ;N&R;uz?fTWa!B~S~X^PXQ a{-zrCO>$|bE|CQu6PC}fwh1u>I~xEDSCKma literal 0 HcmV?d00001 diff --git a/CPLD/MAXV/db/RAM2GS.asm.qmsg b/CPLD/MAXV/db/RAM2GS.asm.qmsg index 2e98dfa..00602f4 100644 --- a/CPLD/MAXV/db/RAM2GS.asm.qmsg +++ b/CPLD/MAXV/db/RAM2GS.asm.qmsg @@ -1,7 +1,7 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691916603004 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691916603004 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:50:02 2023 " "Processing started: Sun Aug 13 04:50:02 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691916603004 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1691916603004 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1691916603004 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1691916603223 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1691916603254 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1691916603254 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4662 " "Peak virtual memory: 4662 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691916603363 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:50:03 2023 " "Processing ended: Sun Aug 13 04:50:03 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691916603363 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691916603363 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691916603363 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1691916603363 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691922990269 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691922990269 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 06:36:30 2023 " "Processing started: Sun Aug 13 06:36:30 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691922990269 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1691922990269 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1691922990269 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1691922990566 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1691922990582 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1691922990582 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4663 " "Peak virtual memory: 4663 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691922990707 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 06:36:30 2023 " "Processing ended: Sun Aug 13 06:36:30 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691922990707 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691922990707 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691922990707 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1691922990707 ""} diff --git a/CPLD/MAXV/db/RAM2GS.asm.rdb b/CPLD/MAXV/db/RAM2GS.asm.rdb index 2e6801ee76bf4121d326c742f34935a2675953b2..d29d87aa5f0315357a67721249f293570099c228 100644 GIT binary patch delta 481 zcmV<70UrLT2B`*+fPW_a*pT`bHA@j943?@wyiB*u?ILnXm%FRjUq5{DZELGhA%s=O zx!>78`_4|cTCLU-()*-VJg>D)CR7ULNr80(-tzFgdxX9q-C5E%^nQnwSYDF3W`Wd5 zDe4QtZk2}2vytHRUlvVX$A3w3UCS#1muf++^Kz!P2>lkOiGPb&F?0Z8yGsvPQhHqx zcht88-q4S*#9C-Pg*Y!zS&ly?aq*m_NeL_byl`H}mguT25aA-v5Dw=$uSzw5Xy6}~ z7}fa#{iw=}#8NANlxqBf3vTR|#K)M1~(&xVbrAza}%T=DP(huz-V7=lWuUyA6+p z%nLX5_6wuShY7RUZEhm3pOV>2y8YnCxDy1!{*4#+m{!*h$)r5L4A|NuoC;HDn25r- z+TRgu$FHdm)`TNt8~Hz`hUx5iHdbnT`Dq-Ez$mP<>J)(kACn1w1wrRSKaO2T9uYP? X!|bOr(z)3`DR$fI9Q5EflT!lL-qH2^ delta 481 zcmV<70UrLT2B`*+fPd!Fc0=l0)T~8_Fj%Sz@iJwZ+ePG(E_YY4zkc}Q+tya2LI_Ka zs#$ zGOaHNyHy%8&qjjNe{q^~9secCbuO<6T*?Kt&dZtFBJ^9B#D6Yg#ZUpnc9$Nor1ZKX zuGF^#-q4S*#5&b@3d6iWWjX$Ih>Pb#nj>L_pB=aB*b-f}1tMJJ8N%UQ=T)it5cU1T z5~Dg_pdVG4kyvWwk8=IdocKp!+!-bQ;OpnekHha1zcPAm^zqat=vLeFYPu;`yY`n& zS+Btru-b(fm48ZSxVa0@iHehNr%JZZrJC8XV_BOpoob_a~Zv z83bJrz5br)i!O9Tr_0-)kvXFKRCJZ_C6&nV0}D4d$Np%f6kQ2Hn zQrb=3oQxG=C~6M973iS{0xgOnm#Re&!f4qO)XlzGJWcEyMcu?{F=?IeyT8hd-rwa*wcv=Agjk z0`zDg8e*^>yT}ZO`X~@;OzvU<;nUZ+;9L^ z*rhfa%0qJn_YPL@3gopsUGlJ`8qPtx2~2socdUlxENC;?B=pXqXUrpIxr1~gH%Xko+0nQpw8~V#C3&c4V%SwV@GxRy|Kbgc z!U(Q$vgHD{UIe~53mtD7eWpzm4v#HpHg2!BM)_HC4Wpu?1$Xut*q2a7dp2^PMFoxRbBDa) zliV^kM}H#@mJo*{=&9;cpC3c;Wrq#4O|PIm2@{nRPEjP$0nKs}=$Ga&p6e2wY9idM zY5Z;$Y7*h48-C)Uu}JL@QB%W^<6b5{OOBHAQzK4tt=KQm?fVMzBKKKd>-$P}#(&oJ zvfyqi#c!^ttBlA_D3*r1xhpqd-ww?-R8q(E6S{r%pTHIF&~k*I7#&r!JP(ya?uf`Y z7nrYHokM6$4I`P9jTVm&T|>uW^Jq67KLuO8-mT=gce?ZLJST7uVsjX19fz$~(Bwin za_Dy{<9pEbwNgz}V;nkWbE1T+n1B52%T)qsjv1$P2=W;j#zO$}Jf46zXH4uHJTA}s z3$#*2{2MuckmkB0l|HEHN^^XWs*A>wm^>nRK}a z!FCl3V{XV~=ee6aSu%L7>RBP@H&BR*qERR@t|I0Ymb@|rE_M7jt={zX=Bt7?Uu=Il z8+-xAkd%E>cEI;2Xf8-4ejB3Y*>0AT33m)*ev^UWNt4t?mlFHB+)e9s;k95hb7n2? z*_I~_MZz6a1LO%~zPuv(Wq%*v7ik~;;AA|sxU&sfq2K||VSZBP>L_$W7p#=%)&C%!%o<^P{j?X=%B*KJZ6j1TmtUa zb$Gv?l4cnj?SBims`kbzkIT&5 z{xJ`EeyE6sXfz~ft0rO(vs+=vh;WGgA?@>EV=v9jQd3HdvW;$r5sV>PHo6PIuyRwe z5V>Y0X1c2fklT*X4=h^G3VSWJIpHfYOmy{mgg*M~!0Xe@PGI|RY9;lGmQkX)$7TzA z-b0JGwTCD8?z|Uh9MO`|cUYY>!V7 zrl~$-2 zyF8^^P#+(N(L95#x+=7|e->bv;89V!CzX8_xF6!PvH6e#Y=1uOyEu%|$ohtM>12vr zvrhfEn`Un+@$+e3+hxX;^Zg9*KZ?e*Zis%};tvzzbG~w0=nl|IZm$z<9?e{ViT{%4 zJbp+K%buINk}ta32sY{nm#n6SVTo9rrVq1NV9bYbp4)^C4mn9=m)x2@x~NjbrGekb0#3V$P+d1$hp3MPkL4N91z5 zl9Y3J*%O_*8hv>LNpZ+sI*hZSjfjjx?k*Jx{i4KW&)?0KHqw6+(pSO!dMBu zDN~C0b!KWXHG|}6fIqtbHhdikB)l%uDLme&*mxeAS?>nSu#jlY6~;U%o0$1(c^#1Y zM|p$2g()FJ?V(@x;_){0y6Zxp8a^e>^I79ldhEv0%0}kQV~|tboh^oV2#OKf%LuZh zgn{8B0DsUoc(yE}OCLEoEc@;}4|kqNWT{}X%CSV=4?MMmTFgVW8R~x7;KWt&=c0#g z<3caElloak3{G&4CN&bOEN8s?I=}Zl&oh;Xm3;J{F_T=6VToAidnb?3^4Ro4z6B_! zF^@eHFJ&r(>&R6Zazl?o}8sLBE5TmbjP27V|tC$H9-ybJrEI400-yVoEkI<~WIsgCw delta 2582 zcmV+x3hDK>6|xnOPk%}Z000000055w0000000000006QI00000004La)K^_-T*npu zW;A>E-c7B&tJq#uxMH-nwc9{V$wLXI4YO;)mGxv zMXl?J!~D==UNfx#GRF=MH2g{N_=e<97rBYJq~U~rIc$|6?IaSqZdS39HF(v#qWE~( zm2P_z5!TTVo~0ldN{ur)Bx9nrP=eb7G&bt?2Sd?2WPc=xCoJ}E6|t|$6L>2$36SVR zm@TB+sdZiZrC5mklX7(*H|NS+I5r%{muD=#?tA(o_dM8?S3_PezFFbAD*08+T`SLP1M(1r4rE5{jbr1K9fW!56lVZW z1W57~9DfB2fG;6Wgn46zaS+ps#+HD1Vflm`3voFl(G&H6vGs1)t_%E;TRmICTJFs7 zx1uS1GU@0BwF)@Dm12wKWQCq=YIE+W*f@?u=*Oj51>xGx-u| zV+$v``M@v5LgcTsO&B2lWfr0Vla!|GM}JV42DK$J^>WyrmzG{E=O!=v>z-MY7_J1d z*FHB;yxp{=(v6S@+nY>WZ{QT~=CB1gd|eDDAMI^IKLj> zj3cbj$Al1DaIb_0@2|A11AH2#@K>`C`L%-B7+pe}$JyWs9Mbqx9hLZPy#}0)1%ECW zERV&e5r@wYR&X^C|oZqx4?kdMszO2dnd41ldJoW z%Y{NUDHgC;4H-s;p+%O>PN<@?66eTdc@B#a?3f~bjI7Wj_d?`zgQ_r?GvX$UBd?E4 zx88GbGtyt~IJ?$rO4%u1o^C{@C4XYxN#)8_pAoK=<*8Y=#o}*Snr+i}ldt&K&7OV4BEN5f)D#9eoXjum1iWwZY%GAgc{Ix6i`G0+pd#Wt) zTnYo?S<6B*1t%PT-~^*ZWhx|80sDc+9) zI6#mT&p8Jl6Icn9IxAxyl59v^%h%Cd=Xc5Y&rp(|J~Lm7#bDhDjlE0-&E>f(c{$WT z@Il$3`IPLGV*=Tm^4&L|=ju7_P$~-di)y;&ZD8gZtgdLR`funSynhlxl}!B6o2T6} z`56aBAM+#SZ8-a^#)?*kaBD0~Vjek#(K5$yrbZV0(SP=C$e7EyDYSkTA^DBQ(GrxH zKnvodqH)bhA+xdh%&3Y)94x~mQ zA$-+Ds}evDN8W}}K&NqT+KdXuc_k3~GH@kp;#sc8Aw9Bv#eYK1JFhFryL0ugSe+9{ zUIZA@2=K!hF2Xn;fsgaeUYrx7Q%ZaYmvDunL_46|SI0TmDY)b{$U88rSs}iFv4Ow= ziB3Ox5U9d-PU1TSEe^s}CUIrR=p%;-p%3zzLAdJ`tQACTxsSX;Gl$MU zP(Q;L*E3R%NPoEToOQsbm+IpACD$&G+eLxDzjesnqQgL?SC=e4Sk?)@5l5z4H;v(<)tKt-b}r{#M7gT#S5}$wY)Yd)|T&>Wuex}I>zMKAAgFBB!`tpp^rKw2c`TjP8bfU z5go6h)NH5G;szkzafXiv*~sBqQDf&gV_D+dQjXDr`4Su}W^m2i@@p5mDUDW$&SVQm zO7s*$_aOI0o?d))5364_vP|$Pau}-A(tQLie6IB;WufmFtUW6$4H4g(Qn=G4l*qlv zZXxF#f`4odsm)@hHYZ{BJK3BTS0k)}&*d(!9DI@=s?L6avr7^4=O+IvT+fDPUex(* zIm}(9(jR$hvIM8nO?Z`>$GS>J)DYkQtUMr(%2?L4`MC173;brubV54fLF9%bdFtJq z#3N~~QtQTJ)U$Df7sEmu@ht)FYEe|1HPg=2@qaNb9(CV*&VGtz>9YKQmfdxeR{K6{x+(-f$Iy|82bVN1mE2f4k%uwtAY&$~LLgT%Nqr z$A$a0UJO_mKhIC-u8~%3avzLfkDO+oAk00DPtskDEuRDo3r7;4Z?R;kJt+Sx^6uQa sW!>GC_jg}2_ch-sS$Y+lL~f|vN6^!Hc?-9vb=~$K$=Rv=2a`$)Y@i?dMgRZ+ diff --git a/CPLD/MAXV/db/RAM2GS.cmp.cdb b/CPLD/MAXV/db/RAM2GS.cmp.cdb index 4458df81301bd5e5e0795cbfd7be4ab35e216fff..ab4f43a54186a081cbf380e268399ceea201c3fa 100644 GIT binary patch literal 44062 zcmeFZhf`DE6E^;_ASx;%0wN_M0wPU7Iwm3@B27VhQ>0hvEd(n?dJ&{I>Am+vq=X)N z3lMtf5D1Wde}3Qh&-lG_XU?9P=ggkDch2tYKD+na{_ns4${Ei68~^*y>EH9@pER)X z@N{r)mJ^eZ5R-T;E_YAw)jdrIFPnR+)(&3(*8ZBj z_c`2T9KktDuFK_4H+}yu^fB*g+Ang3>LFXk7+uTcPuqECgLC&GW; zwlr3u!R5oJ^+W!QO}CXNG4xRk^XUd~&#5aQAbR1$udcB9u0Ha4M3il9 z<({nlI{MGRdm=2saFLDd@+2h6iGvy6(!gkatpK8+t_fX6amxDx? zIcvwSQT>2HPjvr>`NMspka>E*ms?>yC*@+Afu|>zU7CDYTrz#e>V@e?fa)|Ex8eS1 z@2Jx0^N|0}90fo+h!70t1VBrorDOiyDHFkOF{H#Dm`TGmxO4IwUSc%xeaK+HZ@6Yf zLrF@3;>=l|G32PrXpf(`%=LH;RDk(;sXewmVlj%9a_1|wBMqkogn~bRr2t}i(|EB} zta7huGSxExboUt}k(<4%j*A~et(BxKfk@w*S^yPB!j-f76D_P$c7=<{`)6X zxrdlPNZZjF)anVCOC#NaN;}U*ud`P`Tx&ND9tV#MtbWJEObXz6xWSL#L5DSp1T%}0 ziG-NJchD~SI{PjGV)8f#ADCUkDKGTjYZ57Abvk+o=>X!LQ%Kwv$Ld!QZE%%^46pp0 zMdl@R`)xK3xt%XOr6Xld2p|E!uQ0rLwmOK&UBD<68v@1F;+iY)lHlYsFc$;W_V68a z=2@!)+}}GbN@ak z1G$k9ii@$$ZY*e5V+R^jphLLj$}pv9W492-4iuG(AUfO?G{;0t4NBcf$?pCoO%kPU!d4y#b8-+WpjYv>Biv9~2U{~q? zLK=PHV7EDiH5Bgn#D)zv6H0@^uLlr9rXmdwj{_90Wzmq&dQB6!slC~^@lE<(arTu(=UC9iDmRR!XU*dM<S<-sko! zcvN5mWFaZ+S$`t*=%ujf$2)1JLluIp;Z|?lWhH; z7$?|LXvMw3w~!TqO3+9k>c8M?BLak!M8jhxtFon?w)X`^}*#`g9=wo6CE?tKXLMoOax=UhQ^SPy{EI4+` zCg=&EO1TI|Hn)$o8>0@jmXw1Np@TS2|K}EQ>emB5r>!!U1oI%GTw}15fT72*&4B=E ztWMh+a?QT(&89p2?rKgJnvE<~=_^e>4v0nGmx#;_21CTbXVd=cR9AMO)U0{qC@KPb0;@Sv%#UcR=uS()|R}cCd%g3CQ2BCA0Y_ zkt^^CR%QcR#ZK+ItYwoseNE!{pzYKNKfQTu2L=VHzy5lK+&g-z)FAD5;{&uzt_ZOk zoD*EPRWAqk^J`Fke!%@4soguXdr3QpShH?5)_=YV7-{ZD7{B-P*i|84pIKJ5QHKL5{1{{QI;7@+d#=YcDd z{BYAisC_LzTnz)YEw*FI4oBf64y|1n2X(UX^(SBd1-fI4M{1gF=l=w{X=~0m`Rie( zHXM}!MvKaKE>wExVCOgV6d)c}v{0$D7&92ihZ2KcYG;n0W*U#%%e%5?wSuc0F4nMn z3_?y{tQoIRPt#lvcd0nGEu6?d1~m<5ZC3T^1ob;h=qP$*{I%6V-f?u1KZtv#CF zm4E?RB?Qa-;YZsf6h=BHs6}xKfcC2TxEuRwLuaf{V&@5bKl#6H{rHM)(Ke@|?!HSX zujy0fwko+1lMw8o6*Ao$+Io_DVwHtn3k;dDM#uUupMc>S*kGTuy7eB`ElPxI!m@k} zSgfmTcETUA)8-I1EXIC|-tBHY#{u^(dIkEfjso`ekXXGmv?-`dKF5V&dv|e;XX<8k zP}s`c#;?l9xy%A}=G$cFB9V{KrfGuOLyn3j5w^=PEpicTg*QoH&Lu+zl69kgqwTKK zcb%3C2U;dd)x}zO!D~A?#gHl1&(PxyWdS%37gSeIUcvCB-8fZsBKwLYg|0I8Ww`C! zgYY<;tii*%%tZXi^H;uzbD>bk6Jp-=Et@NTS-#@FE`z^S9uX)?YFf{el;e-Sb32{M zb0tVP&t14NyOrc&TBF&O<1f4$>lXU><-#6!-VTbHjj=Tx6(^D;+aWlsvX#2B-?+~I z2Q(pIS;>RE67IJpxs~y&==a(~=W_;&smRf3k@cf*&-3$m_;kyXzP${b&4<=$_$yVJ zy|Rjq4JZ!0#+a8PEy!)G%DaR3^&hi}3U^~y7SwUSIl$2()7Si2KA8SEInKD=d$&w-%#C7KpTa(F;sCsc>4B zJllgTujd1`Oxo-$lE1SwW_t;UuvY6Gu#Dnm))CH zZq;yKw}^P^TKdXEy++mTzW86mMm3mh6zt1*5ji84^S5b&y9}GKfw|DqX1Z55$DjPy zHCwO5q}aUX2j3iRjArJ|O;X-OMZK!~a-+UNf0O|Vt<9=^VI5%dA~?eOIC0mQ9Q*AH zY~fWc80%x)XW)%Bua!?mVx>Xr1E*5xu}v$sHKkOs)?QpXug5Y_iVztds?+wE=?9DCPP97syX>zl#Djd6(_SUT;tPuF@vMAZ+b~E8I z?^i#)I`~8L?|6UE&04oWTRnXNF?{H(y1<%8R(#QMP2Fu_1@!W$+j~_(-?U4`;F+(9 zjk`hxK73UPy{}2=c_M6u=XRgp`>}n) zj97H9n$W%6Des`rSt?t?Q?NrAGYI}>Xz^3SBkg-f>A}@A4i)jr@rHxq=Uw78HR4fs zm$y@m2lkaUAE*!W&qf}Blh=04;t{t4TqV80540TU3xd9dY}EL>Rke3kXal-!b5 z9}|aJom!js`uZTor1SYX5%`1Fnj|Nt8mO99f6=+oKqp-ZlHILvG56=T5wW;a_iBA} zYyO?4lk2884}!<5qm`rce$)uGzB`$e2rjhSo?*iU3D zqmX{OO3yjxR?u!^{r;l{aU3+oGh{VDph{0#fnT=D&3A^*S1+WD$9QO8%L8G^YyXCRuc)P@8@F;X(vx%F;J#g51aPpS z6@AvsWi-2W%lYW}gwRBgF|yzF^P}5-!CUuVU#R||ayQftt*uQE>!n0EwLRg zthbyUW5+3-B9`{r&Osk~e{wJUnnAR{trKd6TxovQHLjQE5p=T)Es7FNNlJjUVHzRR z%jCSyU_uBUgWb7vn!~==q_*f5ux9pJO&fCGiQ~d#%l(}{vAu!cOo_13-mMSF=9;7F z=$rmA+5sZU*Xjpdr}NThL2ci{%XHbiwxC9@{8<$>>p2j!YPB|X!Nt@JZ}9Gi7Kzclvj-*ef??Il@%eu zF9E&-w_}QTAK`AJ)%5HGDJ(kvx^L*MvncUPPinl2FVBp2b+JaN!UeOUW>B>!p9X-t zs0Puj_6e88pXE3&T|>ZFf-#79zC?%@Tr}^XZAZ5lUHvIsC#wElb7mPWo7& zb@}`Tfx#WKjZJWoe-D6$oUL{^2150ZX6ttSg_+%9KA7cf@}O2G)aSuKCw0FT)DKO< z&i=Lx4?y0`dWu=^yyikOKG~`GgBrj)aR5;jmT5YS8pzP-rE$dF*+PvsA6ELdS}}zj zYQ4%6{vXunEbeEO-})MJ2!;6rty$}$p(<013c$v-Ta&wcnNepE2AM-M9%*Hi37*;hGU8s}3*3{r?A|J= z$#L_(jaL~z&!1AY8i{0^sJ1WK>f96lni~mQg916@P9cOfJ9+5y?-oLVqWw^h`^Q&w zBp>5-Lv?&wbgZHRl$x5gl;K9JKE$<*3(y*EX~Gx}mPj3rQPEg53%Yz6?5|d{Y^rt`o-yFF-Y0jazNU`$r}F^f z3`Z&^*A0EkM0FlAh7Dn&tqQ3&HJ+TJy12A>rc43Z>sg;cd)ee&8!m9`hX0X(GW7KR z8M~KfTBy!OGhge`CUV!qZ|C5ZpZ2;sFJX5tTx~6Gp|1;D_seZ%CVK(1XNXO4f=gUC zStWhMMhjJrinby!+h+r!#d$;AXfsR7!W6&)_t>hL*0?m|)NxsS*z6FIa3gp#*U%T{ zY5Kk0iX%X}v2*t%Y0x5Jb}7QO((;tBQ*x!V!XwD*r4}I;X=kdn6wrsg9$wjR@g}I0 z;8<%|V70UVI8bE2%5Wk9bVP8>Tvmf$Z;@!P`-aRh9i}W1u5$t{t{8YGrHFlWW1+6{8GFN{C~uwslu}mWC9jW`ar&Fsose@# z`<(j=I}9SL(O!BHhuboYy#aO5-OCn1`YYtKu$o9{$v?VplW z6)M+_oXVZ$`X_};yR9Ynv}f{CTfqZ+9rIES*T!XbJlk5QJj?ftW1_~eSkU{gEyK@B zO^C2UnB9qg+s^R;2Wi(c$Rb~Za(S$P5vv7}uK@>RNq-y+eO%rzheFq%{(jZol~5=Y zPqXP2K79|uusWpu?rY;A#t?e$uO!}?$#AHdks_X$rpF+h!U_aO9%!ZUr_1aer*HqL zew84%TVfnJ3)7$N>u8gT$#a{5QUuwr&2I!8#3E;seFl+gET+G#k|X5IUOh-pN$j<; z2x4t@eA}XDQ7;>F`G8Huw0_X7ExA7^14l%@DzCNw#Xg?2>iACJ=>3ayfKz z(H6>gXitpvo|pLQw}0{7WJSM+woplbRRDNlCzQBRyNp?BJ>xZhF8W&?tI zSn&W0!|Y8AGI`ET9j=ZzuS$u}^4lqgLjGY7|-VWZ!FkL{gIAkN`$bDirStElmAEwWy8u z_TLQhsJcPU+`Y_I(b88MhOG#~-x#}AGTOqs2usM;h*7_~8n36eXo|J+%o2Mtew;XS zOF`UI#Z2_1$+=>7`jK$7Mwh2+gkThp*wjr?$3Xq(TR(&}*18pE<+nNQXDDj5ZTAc> zzB07W=_bVZu60A1vH`Y*oyjU>Vx;tX^h(bJx6gBMdb(H zpL%OOt-aOqKxt0~=?5^w;HoO!%q=Pl=kkS^sym-P_o*CZ%#BTOPmR_s0Q7u-OTSul zqprpT|HYQtc2&I1e=)6`!HsQBe^WlXhns$oVwLg53v2Ve>hxCkUgBfe5MN<%DE~#_ zXUcl__aO40ZRah<{e%O$JL8DX_0cH|^(ixzsH;JzHrN$`3`1}h^_wZryU6_VTTAJO znAP*E-5UFJo0Tn-aM{J63+VH+%@bM>UYxJO?mlzeMVznaH%DI6}7Qf$K2|Z#~|Hy zh(9t*f3zK{JAeKcTboc`#RFi0Kbnt4M4tDrf643Ka^{bH*JpUGBL)vdI(0O)0l)sk z17)a-<9C~lE}zeTp_K!uYa>$Y%Q5h@ROy%tjS2@pAFL2n)Sx-1h6$XD+C{$QV9RuK z7y0F&vbrTTipoOK2CsFY3>a*`RAAaq9&aid9Rc$d=LWnpeFt=RH~ps0Pc26n1}r{t z+7+~ctgdpsHVZdSG=3lc`RU!L@q_Os07Ln}(D;{7yuW}!DL^}xeYFQbAa&l11` zfC9??b4mcU*}G8P;yCd#C#yjW&Cs98U+$tCX09Bp2YHKCFGfinVEAb60GH6w+PS?S z67&%~-5=(Em|Kv(nHCq*NgO(p2b}yFy^BJAbH@xGMji4T(BTp%-CG_smGL%Re|XAKet1XU-!th#St5awVrcW*`uioix~~9C zofr!bP|cz&z%?xwTuy~Ee^ZJga4B($_W_Q(kmEf+btMi_CAM-gpm6k??2#J|huAo(HZi)8JI6Z8 z;~Tg2b$>@=4uw<(rN+32IM{3+<$!9&yxn|Q;|4$!-*12ZE+q6J#@EU2g~j{fd&WQ_ zY1#AV4XNE$6SVi=Wku)E7@&C&o}QAOCf#0}UR*XNbD|8KwFagBgpF+h*y=AgS1 zS8XY~BYwL$de6=J207DNHy;vYKWMXY^i1Y*j8kYBZQ#Pn1$J=CtWMF>*_H6UJy*!f zW0lJilF?X(BzyAFAkeD@5^?;aGxOen2?xaoU`MphcB_S>>L)EMeB+K!-HAzEs>y!w zL1F9bbC!HTTe7=wKMNPSOK1N=i!FvL$6(Kw=&R0#E1>Dir7a3qlQ~1FuA)}=%U7a7 zO+t$F(~o@O5>rGyx^3mF>{ZMvG|t~3Y@Z4x-p){G&C~FzINjypXqF&+E0h0b{;8J# z+h6q4mU?u;ub|vS8nBEnj?Q_r2=G)!|Cu9U)I&{b6-W=15EKD2vvm9uDanzs?9(cokHL32#+LfMF% zqOglqbinSXyWfPr4%=@br2jA&ZJ|zbmcP%xGUGB9o;k2JkpF2M-dOe=Q&%PD7<%6^ zOO4&>V})Ljp-81vHtVVj?uIaUX}lydVqV&BKGZMG^hUTr;IxJMElK@0GA^DpXXRe$ zG@E|K--0`psM+h5=+m4uXn+s)2ulXfDP^4rh||=d1=;c|EOQd(K~as;`@^=Ry=~JH z@W=a8&3al+!{18NX=zv^NVA7<>nUe5g?X0!xhshB48B!AU98U{r1%Y=*RcP?roJmv zyxy)tx3-8g8%KFcFUDrQq+^?N#?ex=Gdr~dDBZKPU(J$8*LI>vUjUPyRA!@1p9g40{f zpqB0F#~W_;zV?!QY5rZ06Nu{CpN(eoWMllg91mNPCMV4X26R8u^1=5!U)*J%R`x5H z9R53eSv&9>n0{WGvy4y%oYh2Jq;4%J}dL^tfUd?_~l z^dl5W&i=_}i;19__uK94u+Q4HDX z9&pgSUC;M^ql_!_f})I1#_S3PGM2~6o;CjEgWg8F9;8`D8mdU-dBkAJO4Zk=hPpS9 zvW(w)9L(p8a`z;Hk~U>}>FcBBvKPW5~C1vgnPn5|eM#y$<} z`7`JAD9(ISx5}XXmobyZz1ah@|8)aLg%5u9rdO<7Okk2+j*%$xS-BWO-;l+Z6(JZdajewr(7H_EO~Wir+|s zf>W6^Go%c*EL z%0KkXbJDtapg}1HgsgAJS{r_!BLJxiwGPD#7M;LX)2pNin_G)Fkk>fype=lwq4$)d zVs%4zrPwyzFaV&~e^N_~&h>`UTNDNJK759l1^u zLiBfk3f?wYv$#8*GAs|iQMj{XBk#g5x;1Xw-RYWNkgN@!@6l=b8Rz!&rQ@_0e~adH zc@>f$chSIjE8ba)@gITQ`t!~Z^ShQ0JKsh&TMT3kADp`fg%qP|+as3-j$QeL|G0@B z5~uBa(~s>wNxhl3mM0YK$_qaJe9Ohl=-#)=qZKa!gQth2&aUIibjf-igQqXqm^gH9 z$pqEEC|Uf)3p72}@GLY50q*y>Br$SZ+>R+osCc>|updTJH(*iRp zU#FRvO}q-F5$I(66}CnPY75_g7X#_CojzA7H)bo!)|fm?Dia+{w#5E8wOX#d(K+Nc zynS9V=lcyqGdOe2lk3zCbz{b;MJY1UhP1vaCUmKo8<)=FgkF!rh0#WZS&t(#_;@zL zd$^OcA{BWlexk{~F|}ZeJ@(>-@C@VYmOSR!fI=; zDAr;Y*_U^(j6&~KBvtM=QckFJRsA^C%2M4UdVuQHaW;SiL8~rg&Md#NGPt^v&Z2*+ z=CWWwYF7cwq8Q$O9p78FVm3(UxEZH$dt>75U6NI3?@UD))gGC;8^5pin8r3gr82LM z!90K*xAorVf!5nSXc}14gvnJbycLgKM$=n!c0gl4I}+q8AEMI%wt%h#@m4SSbi)TB z6=T_VvXEnUqwIX3Ap?;#at&@K99Jt9hI2XnJY6bDUORGm{jZP5F67x9{73C6fHNJEA%5LnUYouPd zs?xGV5q0uldgs=G<}MNKjn4ywm}b_pH%B;nsKu;+(@53d^HEtIw9RHqMR=}3~;K^`M+{-y#B|yxZD0*dz-*U~)^VDRy84tc(y8PWq zdnZ@1`dNpsRt-dGVEwy9zyF!;VT_q;fPd>+mIx!D)2HbvIs18KC$J6~D)iH!61)+V zj!=3!$L%nPvuyf(prqUQcJPvyw?#3&brFSE%yl#y3y`moSfPHHoy!@DNATQ}kP=}} zlHED-J_-IyZmq~!z%$IaOph3ZyTPvSHSOqhuS|zqtDFFOvMb6FR9R{Jv&Qd2nSC6F zkES2|F-@;E=j$s*!oU>~r8YJR47@BBH8uTjYEIgjkFAHZ)7{*nB2+(cC#-QYbx^8Y zqj8b`_{DHR8;!;1@&9wJu5YUJul`;SG&8(c`hX5>UVxIfxd(kDD4R=nHgk6ZenB9# z8Y9v@{a~W;RG9m18k)bmVbxW%QUmWTA3JA1J!4xDvHmArVX(X3dLpbvl*iMV={uD& z)2)%_8Zqk)Grh2OHg$(}!iuAcA{%#B=_)#vH-;rn{r=<5oTN8=*4n)JR#oJY>w*=2 zo?CPyxpzBIz##1X>*2Gq5<>(+9U(yR|; zjHWN{21SA+ZU2}LPVTcR!ar0r49cboH74Dpau^Andk16mBz>ow&FbXcbB^&7gsk zQ!v+tronFCl_FeBh9qIp(*^i69*Ee}!nxac%Ux-gIlHgp!BOK#njPObd!W0-SOK$8N$ys zE=0@aU(brWgF3RjNdFlMC4He;U4KVm6mV9kY=2}1d(UW}aRx*q>6;G2d~_LI&XcXC z5kjyP^VA_i$|-?DA6E1p2ol|4H&4kBA`9!axbwWSmc)PqX_M$<6(4T3n}85?~qr6jY!oHrQJK#?WCf5m=UxM;8;6uyX*Sv@WqI9o^w3RANm7xf3!6d_?c*3k_H z@J|5XL&ZVPR&s|7Ge_&kTs)M>TI5kc0)$Bv+pR6g3yzyk4#vZFYv(*!*lz?|%1$?J~JjpU!C{GeD>l&uOd$UB7b|LpV zl}&@uMHhX5ZZFYNlX4jcTpPt`a-wvnMT~WNivadtHdNcYB{rRwUQK6S`s5OYfwV>n zrMMm8%xV6HYQU>48N+H2jR!dWLGKo4tM9MLAR6L2d=x_j&DL!V0g4^ZcH$4bxe?|^ zRMZXPX)pLN(1;airtKs$Tw6#UVzjFvY%~tw0kPytAz(vQiN#eLvdi&!+jN)VUs1nQ zQ6LTH-E(|Astp+us}Nc}v#(fs3=6#~OpBO=b@$qUK*}@w6Vu?Btk?tb3QNx*arCOp zqUtrk-*tdP-Y``R*iX2IYZcgZyIsCB>wh~JBAS;qjnWeZd0N%k7*ihvHw6=Txq(B= z?fTPHtIZH3P|Jby)(?8GVf`cBe%n|1B_60Fr;{WsYo2rXXDb03A@e_h)^oUUn$8f( zlbYNd1X`y)FQ3ekjqy6pKj~JzcqDDu0I965j2-$NtFm9mu?y@1yeeLm%pFr~+pgzFVq+uzCOQ5qb_M`*PORo?U znn$Cc(+?o@7|4)$#!j=2B@=;3>$Vgf@MUoSKKw>IfFhVa@o6lZm3-y#S}9q0t6iOj z7|iv96)^q0WdZUO`^%p!QS;=>#reruf=kQl)m?KglZs>g4Qd77KTc0!&SCE{c(Ifl zT84ntKX;ZQO@i^{I@K0?Ht*;E*xcdbJ%srvpbY1BEDaqYSCn!0KyN@RvUFTe0v?WZ z>EqU7VKfd_JhsW(C`RN=s_svFK;Y!Gkr7WL-nd(IHJINt#{D2t+OS$>cNBPR>1H+p z19P+gGb6ATDZ#`|rv&&a3OU*M*5;!uf0J&+>YpV+CkBz~vp;FU!-{=!5;a#8t5up+ z0m*g?Z~t3nhxkDE#@m^Sm5#TgelGmJu~LrmJ8D}MWlb+U>#M{3RKKGO4zFi(mO?n_!`LF`9DB_S3p^fiSYvrv!9b9io)K8LW z*|^y`Wgo^mU_M}D4AF^Fy}q)S+IxFiE$l2}Z05T*LO*nh(bnlG>}=#0&Yh*OnYMi0 z5g+_R%uRsLas;wXym_omMnXFY@uO=XOOLVe_S~35h#rh^@FZ=!)5K zFC}kKV5nDR9OMfl2wE$Ri*PfGT@kq4ATXZjYxuq^c}JO7a;gOt%V2Vix>)vN9q(Hz zEe`weBDnPC%3;wN_F&7n0_K(HJ{+t&3_I>k>PfD%)jZsPTnC&PYi_E%AkCC;6mJE5 z_4!njjy{EUy6?Mu zCZ^1Jxzk=!!kjFy9)XXTuJJRo$#~CUHs2%!{M_RBjUAr&V0i2P{r_+w3_Y-{%EUCu z0bBNj5^vByhHkK~*IjP0gq;uPGsD-BYODm9W;oR9W@LSMLvG$@*!<_%Sc0I$6L#u+ zGLuGW&}&2C1q_ph6JP90422t{GsQK&#wKx7qZb$l*UGFTg_n91q&C&~UB*hj$Sg>} zqIc*i_Ai3#cMuUbqzuMnte+{wJ6ruB)WR*%M1G(732o1|I#Mw1vGtD?h$+apn~PEQsa%J#ZuBgu20w> zaZI0S>QO1-lm8BpI%=6ZsUz{@?A6k_)b+HzH0yVfb1k)`zVI%$7S^v6clqVEKgPOz z%7)MAfBJ8>bqKttC_NaX=QjTK)DnAY|6=i6L+G}(k%=Gi6SO$^k&!RAy|e&V^ULe13(glIFOMVJnr^6aX>UiHM2cW%h`7u{(X z^!??XuC(e@!;F zY88iTjCPW~u6+(?YyHACh64%Wl9u>Vo7M&JL@&iLkP?g)AZ^p)k5yPr{5%lj2PJVj z`@OroaFfWN3{sD*zk>a{?J}l|Xeq9|pPyLm3@Z-o`ZlwWnyoiD`b#qyI)xEW1@$g* zdbN%y$S}SSxMvC8XSGn9EsuFYHonDd%5-zG@QsHRaU5mb>b}%P3ilv8iUr z=(=S$;PDAk&F=E5OKzA5>c^Yzkf`;?hbIme8$Rrth@FFZ4wtM1!fHiLT^?fv| z6zbLe(|1o>I1#u^PcnQZO7hHzak!KngVH`gb!E+z&<;nFdi-dNyEje(oAM|5@r7+k z-dkrG!~YRIjalWXc7A~IC?swa*)tN{K3yY9%Gz2*lSU;Me_aELPX35R$l|k*$&JJm zs&-&-QarQ91j=YmA{j!06cC!z%|Xjo#eZk*;}$5GT!9Q4GUys0?xoE7FZ!S;#vm#P zmOD2b#z8c9yH(g8_LPyjGJFGvsQ3;<3Db^oGv`PG1l^q#gw;!cVLn)kIBd_U9NaZ=|w`mZGo(jo*m1?^*E*f8g0V|H^jkIw0x#Upu8?ycKl5{HH%?{7fO-(*xpv zEMt?9h9U3DDN|nh>Y5i2+Vsel7dub zQDFMG8W`F$(|(u3_%^NefnORG7S#L5xzVog?FY&wcE2cR$pJFa(%g;(r(g~l7L5fe zLk7RZc#wUF2WRpGu@hmc;IASag$_Y26w&>T=4~B05raX}sV6J-uY;CUpk3?^~XL(xU;b0?n{voK6`P7D}X$ZNTQP-{y1)8McAE*Nn?m4-OP?ds9lr>T66 zT>Y3fO|re6LvQF0pQ@eseP!=XAFZg|RHK$+sK8T~Uf3$NV?Gd6v93|e?xNa*Pj~$; zauY5T7jQ)Tux$y>4vrzo*itvWXIv}!Owesf-C}QAtppeM<|BW))ZBXl`I~%~w8sWH zwNpnrRbcE|*pxJI`^}(cny}&F7ZTdad*;V3APW>gIn3Y(XB3{~T-K_Ru!qD?1JkU0 zn*`(fhf1xAy0YB)-fH3b+k!DRzt_ypVhx?I#Fjx_UiKipNd+v?uWYW}mXyG+ZdK}= z41_!P|Mase6S}%`BWOC3s*ac%EwjhDZnFid-hb7w&6!*nU4?c>xE?necSn1s+o;41 zoaOSoIif^A40{-8rv}`Oi7)5o>uofAqqt=pFqJ1;sjBcaLi?7gE5^44fT_y6yRCd9 zi)B8Hcxa$TdCf{hcGJNjX&%JYD>v3G*G`{4T8 zeeI4CnCa7l2{LPlYt#83mJ|mTZ!)LgmM*|!p*+6rJ<*{+` zNoFt*Ti$yt5Ku^I85VdNoQjtr|G;_H5X{$_dYjNEKs=M7^AO=O&`s`Z*?j>6C*SGHz&s@eH8DR01dXRrKG*Oib|FzJJ zE)6095y%O;y~Zs-;9jwJH_9m^xHhZs13QV%6|{YDDy-xy2e7~vnj(OmkVByA_}~YI z5^UeN)!4b^8wEs1OOkfRqH;`wfX#NVQVgcPKOl9e1 z@}Bjx*Qu`ZTl|mQp2+KdO{;0sqkFR#c0R#0gm)kVX5ZfPx9eV^li4-6nVI&)QjeQ{ zltL8@Z0!oEiwMk!a1Uj0`&^Rhj@4`#qxyV=7_3@Rrosjq?#?$Iuzyx4O&|5f_CK#J zXHM3aYI29Tqni&(-Noe^!UpF4Eji}Td7qS(vft`t7O60uhn-sL$*{b8Z53Qwgf?Ea zn)m%NU{jD}A-T`sy)PR{9`u65XD~TQ{VZ8Z+(=}WYGOg^f5~$AEXLd>U_W;b$b8E- ze71~9Hxi}{1bv*m+QCR@v&Kgr@DEvVaCs6`2B47Dsrcf|0}W8S+zoiPw*s; z%l{6(O&uKa-ll(|Z2CQALVgvBYR%G=PNjZMlkwlrb$nSOgfc;9ly_*I<$uZgp!?SJ z?_W%oLrOmV8`+XMVPsbh(yT*^glJmI|ugxZT-M3h_pyeaDfF)pchBQ{SO&yMj2r+ z#lD6W>SXP3&%o_>-of48;!S;nX^7#b6AyyK?3yM67xO38GkWE`fOvT1)Y1V zEDAnll3YQN;N4MFM*PI?Iq6HD7A9`tx)3L`&#{SF!G?sN4?-Qi1|2z6uw~8`vmc|% zOp-^g#XTtNbwp8yk3EGPKh`b_cEnt9O{_+}&DsySvff$WOME*Pl(Ax+Q<)X@dD${4 zx{$ib2_kpOn3| zK`OCFTB=wX!kYh_$+cHWEowFL5ocvH_0n~=%?cc^!s;X7qLoX@w=!NeZdTi!em>TI zoA;yMaLTL0qv|@!LPKgf>(&q*O#i^~i_-M&HA&d)%wCKdRnpdP3*{eKs;LFBYek-r0?|! zDfXo~jcqhg88$nbJ0QCC7k!iesQ_=u)Q{m;kh3S-g%6I0O@vdT6>I?64`zw|C0nwB z3u57q5bXc%ei$|^z}##*IyB2rSVmpFbr&sr#5hULVWn4V|H6K@(|0uR_LH+06fLf3 zdxpW2kgsFCNW5E*s z@JXW6g@;HeC_fwZP}zNy-D62YqkUJzmGpJnHz3 z-9=Tcw$^NOe}2T(7{LKE<0;W#u1PtHefSZsy*fKNl7TtjCGQ#2bg4Yyf~-dre8q2+ z8n&o$Z|SE?*27(oy5_zW=~7o_wf&PjGKWD1Tz}jfH{Wvl_Rd)&3oaqebE`VN*BZHV zR?oYq-%^{~egfebO9Dqr$NX#k)Iw&A#r4jJmI%~e=Ncbe`I4a}p9;c;ubQ|&aXplZ zHl_b)W;Tw?^)lN@^tCg7R#3^buDt_wqDVWE_xj^rB>c4(T~)Je{fXy>(Ojw^8UCPRR)+#z4Ced z|B-Z!VVX3(dUwb6%#Lm28QZpP+qP}nwr$(CjUDUE`<*}ir<1Bqs*>F4)Roeq9I&9q zYI87iz0eaQcYZufwZyVoX`zWCv_^R)EVp?o2z5`u~FtK@$+=jahxY@C4IKNS3tZf9{$x0M2(bC4A1 zZcehtF0^iqjfwgc-2caAyv$Llmy8w_gdn7qP@zCt8q!Z4UN zRk7+JpVt{I2;l!vC@19S!l}dbJIjBJj(o}W{#w&U%2L=6#a-++ykA~VA1rw1bWPex zwX>GA2ffZX(XC?n5<}!BDBAge-Dh;tYpo3s%}Ly&7&|oYu7o&9W`lBM1Q>U=6@FPw zXm~FQOB0)E*LRCzNPP*lV9#I}-v~lyvzW&?qRtP`n&W6;r0-qRF(Rfrhz^pgZF})krxJ$AejUCvvmAmaCDW+FcGBl|Oy+rUdqBVv# z3u3*lumgTbjcJOKQw^Yb+f}nC;|wy1IXyLxsTb>!ON@ciKKm2&NL?=#alqck@{jEA zd?J};>6o)>>YD@xKA&bCAI`MDnKB2oNyX-X8pMr9J!y<&I<>!zgD0jD*0ZTH7o{ul z!+Cdwe6u|x)T*j6P6LE2=7fuuyzS@(`{ML7`p7$Ex$%8rM=b%uuh*|O`2hepn(M3aP(P|%pVvGVNgXd(ecHXlQe z<<#^D%uc0B%U)@mk4IB?*P<~h^@Z0GS62B_PoX-K#3Ru%+s1+u=|neW`+7r#F88YSwfLQKA!nQoL?`y0q%Yd5p$r=g84OWLzU^N=>s zv%qx4n>n?=+m7cFl}Sw*qH=|zJIr*=5T)i*Ibc;?;Lchj;0|X|uU%6DdBaH!@7*S4 z>XK(AgN8%NCpvV6U>+aPz(bi&P2GN(Fv+2@`*BhTM13m-Nay6w9iTi&MD%F*k1>6v+$R7{AB{s0)d(8>>5GZ1=du|qiF82Z2x(x(iVqa zfNr7j`u&b=s5zyVZ6}4cN#U{ORDlR$@su5h;dd9n1EZ~~Uq>#&gkzTl70Ub%#z(ll zXVOBQ16sh%ie%R6WB2(Ji-m6l={Y;>_?^LgkV9n|QT5O~y4s7n6!U^nwqb_W!kl3T zJ~r*jEzC4W|3P?~6Xr+w;6+)S^SUE`^4ljsG{p>NjX+DfqyoKoqHvm61#<)9>q6y& z1xz`t!yJdD5c~e+3{@*xBBhGD{U+&JENFYB>Y~3Xz8x&eRjLvg13RHE!zc%)%Ymt3 zMtq3+M1-lpM%>;R$E;JLB+wqFbbNt3E#r$a({b;lag#GuXN`$#(XNI-oS#Wp>;O>JFBb*cnPdL0R(Z80S&{Cudke+b7Inb5j zhr%_mQSQNGlniY<%AAE8>}Riqu3I9(AOb9lf`>~<8D?G3pQ zzdHFntqvA*X@tn0yc6$`jG1lDt-Na>4WUH4b-H8?SayrwRxkAE5(s0+EG^;Wo}pU5utCmb>w?(9Yn2PT5f`aORDAZA8gc5caSU`m zb7HXY45)bFv2=#%cTA)Gh+S@8@(Ofb zo8;eJZ*t_EPFfoO3L)CSSo7(aH?$51DHz*WlfSQV+z;d`z!k=KwaPCjkzEun`>);?CtPLtZCO1T z$|^+o+S;kpXO!x_Y(VAdYqoK*2R=yZIejXSINuxuAvFkCP^y=B)X1%1?%LUV{`o(e-iJ+t-j{K-H#a4Ykf5cNYJo=cNn`;9sd%i~0iTpIN{ z@s*|hVlO0n#UT(lp%Df{(4BhRU;9l z5mqTkgCip7yMEK&{c09qpcTDCAo1-F;Q$-|aNv(8Sx&H$Uzo@Kk5VZfGr`+MZoFM`40 z4Dju)A3CF+PL3ieS=ta(@RxsWZ@456b{4`p53 z>5lA96m8j&n?Jo`&Z(BfRwz^-pE3dN@6!(YZbEjv$!Zu5gb=$o3G0K zZZeU-iicL|G!=U$ABmpt!$aw>(t`;r$Z^# zawf`G0!mZAL|#&z2;?-5`YNkUo46E4(ONt~A{X77CGG{gu@CdxbAI?auhC~#0}$CX*-TV7*G zDHkHG(pt5jYIM%x_02WU(o>%HC&(1$+$zMEpr<>MS(!-bqOf#Dyx+O!G)C%3M!gou&s`MQt?YCe1UZeH+0!$vN zA>}`#C-(JP$gs-KObwVtM`*?u`bA_cbhDReX4*4l@HE=wqE^maO=LtK`sM8!GsL2*|k6E&$F;bRQi{FEAfye70 z5$%)0Ec)=|@|j7kD^N>50k&EqCK7j1k9-JeGGUg;Q#WN-50Nbml1_YYTbB3xC}y<7 zIwWipk`WC1V69>zdX5TTKWjg{i=H~MIvtnio;x)G88Tz~D@4Zpi{Bf@6YFNhkA5ua z6Mp8aK+zw`2JC#TH63Dr66>fP(azXdN)#0jlVf8TZ-s$|CQ5gcAY+qll98J4NsLsB zh8!Lege)o89O;$)$OFKZ8M}N#`Q7mrEDFq1xjL{{ z1h6SDx|t)mK= zMhFv$0vxg{#U)EV8BBKVSoa#T5wzu9;ctdE+Bb1_n+8F*w*GT_empQ*2~ajltrGTx z+RAwvRL`19y&mww0m%kYThikU@e3_}`l_;u4a1g-d{1cM>EM~e!fp1KXf z7f#D}dE#DhPiKsQQd#V*Icp+w1V11~60*NNox}T>`}B8QfsJ;uqNY=%=&@B1SQba) zKIFXcT;st@wde1s@-$jh{vJ>kYE*DouLwiqOqhI6#Z(f^`D&EuI-Ec|1%E-UT`at5 z>la%2%*R>RFV;dX+Lu2ew4(BVA07OEa207d^%Kn5r0-wjZl;amS2=z7fy}W?nG+FV zJ^7^DQsolu%@8GmE7SN**lI}Y*_Y~l^B~#M_2pI!-a&0; ztQyhBL9*LPh^7cQ0N86_ z{vPqsCdR9N&Y z!H}Dj`htGY=|IEJ^!6tjEB+<8#quC}Bw3W15Am<%!w$npYPMQ)u3gC>BoCY2RHcT) z7??s6hjeK%Vcd>XZ^z{p&197*#bQCkF_0$ZV0_MaCxT|(_lJ$uFGG@b$`9B!;uYz0 zT-z)=N^(<59TCRxFpOoP6-W67V|Qf$Brih5cgOBk z5;D2@Eayv_3JdroSC33cAgCMS>!0;WFnko*q?g3D7`ilhZ^s7?kd?QT#TSKWnlSxj zL{-D}`X*TlA?ac0BVBFfY3MO#Ac!~b4C9+^P>>D^Rt*oV*!Bhh^j%FGP zS4`0%O2E(G9-$IPkvHP+4e{?hxLMF>eFx#4?O-VgamdSK*c+;LWl~6Yb$2*8N zxW}4=#D^N-1C*ybERdbU`Be?X;s*=~aZ>G;p9~qPV<5VVj7<{Ubkxs+h*y=DcegB) zCMgXeEBh+jh+ycVON89i6Jyp0__&^kHu}0vOszm`$Vdp@%9TM90N8D?F(z|1cKpnc zq=R;GMMHzdgG-KUYa?~@MczR<-vy$cHONN~>%;0P;f>?uv{Pgc$kw738{rH#FXfKx zl;d|_v;&O~vt0~YS^c&al@)T_1mk~LX-j{~<}_-cHIQIsZ*~MoEC0$z!4eEdoUUA= z;_huanr$VY*5t`cxgR*bJKPeY%PUTT9R(d=D@k8dk|w=joV6mH}T%j9Sy;?U?IL7XtsZ z6P#styX(6O`VG0uF7P#^ut@chT|o`%L8j4ZWMCDwQnKumXmiA$PF5;kH}>@>(a-9U z`#h$MP(9tGE+*2JIWOR!4!OylImkS;rTkNAA{yDZs8}t6+svAo$0t_=|E&CKJwc79 zE3lfABc9}@A_AurunnAz;tg6r@y$0*)FMO8Qqr{Qdy*lQ=Q(1Lp|?AID|v0lqE zSI+30q!n(d!G!Q*jCu&GnA&)a=q{!}nO#_I() z$Ydo{mI%f>hqZ=dr<#*iVA@1WW)}saZ^2-hb1<*kAAoFdwrYWYb^_u?<(i9Fny>BXwUxmD&VP&7E;1^)`Od*8V9Yn?W&}{b7a#B*!VrewamEADJ`5+zLzm_ zW$sXIRAc}3mvG>f5g3_r$$vj=(iJ%$KA$)P4s_F`obVqbeB2#?Mjygcqqd^n-$C^Q9 zjLZx*ZD~EDuY%RKBDsi-I`V-2Mbl?8@tdX)bTVEy#i@11pAY^3oTP%P!BptAwz6IF z)~SC)A&+qRVB1J2tqp=Bz=24v#mjrIUec7*Fi)Y(em(W)*E_Pc(4MgHZ;Cp8JpW1> z(%kM#=%dWmM}HD0F+9M1^tt+D7Ai0WI&BKFXTeA)B-rFEDD=SIW<4z6;t0{6i>$Iy z-N^tZq|4ZwljNEMTVX zB*AvlLv1M$%mJjOCEAct)$v8&u#w$W|5XpKxds2WNOCRL9|p}qGb(R~Ll{Ps1INyC zT-VJgm;b{6If)|3xmaa2Uo72c7|?G%QWqu1N&{)C0tm=K$h54Y8bU&I8do9;v`kq@ zU>vrq4vbKp$SF-jxf7_?9PvHseE7opveEM) zuvm=nC=Dr>G3#5pXc*90yz451@7%WIq~&Yi zdd_G~-4O`ZDkt1m-N!DKlD01WD+0zeAD$)m?%)Pne#fVhAT0Iom_FP3#Mi4N}UinMTf8X6ulm z;E$jd+y!rMu(iXd1%YeWx?JY=Tfdi|R2Ou04$3)t(}`LoKye?-`>|);7ZrRpjItQq z`4OzbhP+B_4tr~gCKIqi`;9U~q*fipZ*pQmWEwcA4*%7{8Hlcrz8)ugV|ndt3|@iU zxLyt#XPNJSH8%QGptimigx9HjXe@P~MuDgrNP2CxPp#l+;BD0^iDxt4X=j69P$)*T*dqNLibJC|o8>BFpH9%c;ROYhA1QgYZirtU zC@9Hdy8;R8M2EPWJm%fFlspywz;gEt^;0L@iR z20R0GS#iu_F#n2!j|wKSyJ7l`h5B9xG6VBBcRN0&+k|JMSM?xj;Z6Pme;t-8r)VZ* zLGL^Nh>)F)aq_>b9kOEKcmUeoNU})3c^<|vqal;*TW=PEd}qYu(JwX;;GSD9eXB)` zaMAR}=&9jk0-(Q#5v1rb3#?Bg|8c$jn#S%6qrlaj0;RGx2g6}y!y<)mZX9-{s*~OA zDy!H*g!va%E69jEK;ZR4?Tf&F?_;`()&?{exN&QWw%AVPx8uMm3O~L3eJFD-0b|km zFXUg5aqKqBsUYC_iWG;}pP!5>P6OOk1+xz$^l(@-eKQ=8-x*~JL%cnRMzo#t1ia(} z+V<*z9epZ3OXuDl^+^K;>9oEOAb;1ooRpLW0(Kq?IyWOR#w(Xo>!qtYg? z($zGHsfy2y7ow!EK?)!93P+_DiY%WmhLdc%X$14*0mwB>|MfFu2=cu81V?f z2+2}+?a?COV>XG(Zld{eIObZ*tuXj))L~vK{P$9D)v=xtRCZ_r@k`T^0*E_8tirA& zKCrJC_(VN<2=S93ajupf{PDF@cd@{m=!#=EdXf_ZA}%kS0Y;OCw{1OHqGhybxUr;56Bl;;* zBz>%b{f!sJn*O_lKp1#PA2%g%zrbmi5y%KN2Br@&90?y^fr%dm5akX|s0=`48UgYN zR=V%_>)=v;Si{-Me_vHEfD`|hdp);|0_zuz>#O?xaig5Ba(9V`+>H9YU!WloiKMWU zwC#`hCQSScIgFrc2h5V2wETk|Nb$6uzWA@aSbDIyuEU=r^#Y7U21}QZ!q5hX4J3$ghjnEDh_E4u70>O*fVWYmgB#*oLeLC&E!6F(^`AJu7eJ1HoIay z&w#+kJl)4DjOO)wSHP9-U$$VzKKRBzisf_UqZTmVO!OgcMN(T;06#i#b$<{S?Br0g z{|=xe+9BaMREjU7SkGNruu_-cjt%308{$+GxU9Yc$A5KlAtmaOu;#F4U5NQ$?iZQb5YM{as z(evtc=K61qk!glHZU7H$B+T&%;17T&FBD7&dJ_Z`9IxtQ3f`#`d}%KUxPix1B^a5gx|3N54h7&Wc`<(h>!tPJ zFfH>I76WR5W!#`6qOfRNhAU4Lms{^P2>yRC&d69EJC1S05^4!+gJPzfm|Sakq&<)Q z+%;dlu>Z&nK96Vzhj$*PF`7VOW`FZ=_Te(s`H6-K3rq~X2?iN%7)7yq!ESD1=%jN^ zKca2LI9MT6=**L%dKC-`^RK83iekmo6H|t8Dm;$JpV0pE!%824p18|x_e1H;^Aj=n z2vxbI+XiAo@SVc02QGYQ-Axrn&9zd|BqH+C3#t{b2Zl2*kHddHC1*?LbKj{w5FTJD zsZKKzg@>@Hozi$2@KQhgQI29nLlN?7KJRm#7TLp7P$`^gAQdD#%b|C zOz^OjgUut8F8{xls`+`QVv}?ounoeyN6V?+t#>kYeMnB`G;)@_CkBVOOv~VP@JMsD zpx!-6PQz0+sK1*Og}yaP0H@no@IP-w5lQ1FF*t970s9Lmn1*t@wNnNMtBnYOPv_U| za&_Lb>Hz?_upj84%g zxacd{J)nB5f6MTB{8gE^2apJS(pvtV!~DOk9=Xc9V5+s8JAUli2B_Aon?nwMjaf{= zh}EV`1Jb62r>ssh6z5-Ap_>At-O-Q2KOwzI2zYo%XdMSi<4fbmMTOvOR=uuTtHH{i z`=kuPU7Uq0+GCtRTs@@TC(xZb@Qr~-s~qi_1S+5e_1CoAxW(hkoJCt2B!NE5P>h~4 zn^40LW|8t33d0mWNAS_!>;3-CX{ESA$Su}3-Jfq*u?nq zVY0#=2V_Ez2mya;fN*EGgK7vMUuU_l4~95cu%gqK^} z(w|5n!Ttvpk|(PT$AQ$`f&ki|4FtKuTdJ{Bq3+g3gBqp141paLc9Gjx6 zdQrcVeW9HWXqBYbW~%stqS*YqJN-m>YI_ZET@`hy_&n!M2iCV&xoYg*LW~Pk^J!`9 zp$^|;XQ~pP0SA970*&S~M6Xm7fED#akEEgd$k~Mm?13HfYgu3hfu!QM+A-!h_)YvpX<@kR4c&q4`4-P4$mM%iizk_CpNQq3wZr42E!zYJ&H5W7@?C)R6 zQ+{jdX>LLExTq1<6WqdsZI-f3sR5ACBs#@G-#&pGpkHCG9PDq!y{>O#T3cbij<73{ zSl`>HZpvQF_W7;ykNDanE!MH)0K<}Dna=5gm#H+|Eon{!(pb=XQ;grZa;ZVfuU_?f zGVG){Z{v)3x>_3u=Dm!>_S!(B7oAQ*T=?lMOgi~+FNB>WL3<;IL2~B24{w3NPnENc zKL-q{&3P;FF=i_9} z_f=d&Kf&#u;6YGW{=yG0;!08h%*rJrm^XXQN_o-C~~jTJBA7_?IE*)@3qi@UzN zTIN9vXb~c&ygZ0yUP|sp8jHbB_#dy~{oZ0lRd;9A2`(^&*JU${TT`K`;~P$wRo+#=);S z8K)^D$lMefQTu1zS&g9Ok85mbI=z<~*v~4p&n%_<7fpyxS1uUG)l?e%kCj6|@h0t5 zF!THg=68(j_&}mY;jYpT>tr)i{GooL@Vler0LG0}^JxR<=}tZkG!Oj%B;;8wzoj3H zg@8T~7=C=0>FB;M6+Hr_4$GP@jIBNAVuWgX^Uk2E5wK+94|KQDU5d*E~9a%TA>nv@K~bYC9KXKz%LU%Cs6U_mSRdd)f@atgNpQ>z4sdyj#L?wfRU&jEo38O{(IdM zVf0lKaF61)``Db5-RfHPvUTH!keo{pPaHr&_DC=iAh;_NlT2*09NTh%gz}H2Q3Tzi zh#T%!lL=;?~ET3GFxxEkY#k z2O~U=?w##ThxscECsI3wO~3C%;cep3IDjFQjHHeGhkGH`a1%V~z6M3drvmOYj}0~K z1MctV+#gWs-8rz$Vj(E8YVbMzOdEQvobQ~jhnObHj_Wr}Ai^ag0S5Sm_OdHCvCYwZ z>w|Js)!WdWNmg{0J7^nYsv#I0x>56w5RhUwL1EVAMh2t#_I_kar&6=6K~dUr5SqV- z{qR(WkU-Y-;TmdD8S0C&U|8lDBJ=@M&kfJ&C)Eu%YtPy5+YO8qYV&OGnO@71=YTZM8n^5+wHc_E*W9n{?Tv5 zYJn71%^J#5j1;u6q7m_pxV%e(SYHYmkG6lPYfa0Og9%~}f6xy>33y45hI|T_@Au!q zOal*ny@WSv&d&=?@z%!>ZXe`~;F##fdPTDjbzuUR@BK5w1EJle`3Vn)Lv1GU_VwfG zJ6~j$?9l83&i{V9Vr3+baLx7>h6dMAYcA@~p5C>AQ}`%vOa`|3sb#}y%ddnCN1}(m zn4G_`G}=X;d|hU=1=8mQgLe6A+HzwTKj|Ft4xYX`Tgg_NJ>m6@j`1`|Mx{w0N~n5q z{LwDH;Bw}Q4`;6(;r!(&r6+5e6qnNUn9TLe>5en3MJuLm z-@|Cd1q0btUVevNaJGTK2iBdOK5Jmw{!oJJejlN_neMEIvUfFjM>IwFM7V98AN=k)>Vcc7IE60cBVKcu30$Ul zVQzOjp*_CTU@?$)Af^lq0h~zHgEzASmV=Y9$xC@p-=?cV?a9B|L4;g8qN`BTZmlEz zTeQ7f%lN1Br)y_d;k3$n!MW*;+g;nt*`Vp*yDM$QR0rb5X(znIg;(dP*}r9_<#9PT zy_{~; z5Xl%Uu(;=S`0xf1JDN{A1EI(jn8|A?*sr2aKYc6M4`S~>_1c>CR}FI6Q*Je{ z<0PA4Z0IOhdLh6y9IlhH@vVTle;beU2Ql-&3I@iN0Qckeixn)NDI^qZ9597Lj^{@<>3<7+^CJ-Zxae&k(rc@<*UWRhY+D>N5&?po>!|1;$D_ToWU@ub z2=|C=KbYK2X*`nj*}g6qluY}VeEB(#d2%)f1<+W)Hqr&_HNCQD%%%JMN!^RQn7>v-WZ_imBQbjyEsltH<|PC;$-;*2sL$ZCAL$C9T*$4Jed8M#WM8Xu|3 zgVFv*PdiWsYTtqH9p2T10!CuP1jZ%q{4Q!F3e)rLR$BfV_PY}{; znY;rlg4&6g?cu@~Kbht9sM}tbu$%hI4Vw;^{@eyCd0GM{i zG}M%i^_?!D1i-}U0uS?_l2gh`KU~Vz4u3u|8nS#u4vq+3jsT&-2O06lm)|mc@g4%Z z0Uf0q$F$$bKT4LL#Rv-G;js8S$qJ0b{hbpiHd?XA^Mm&B=W$}iWXTWtwR&SZ(fcR@ z)Q1q1esY_1Xqx!AmuVv+%yb)SL``p0aRjnLfJ?CV>E5j&>UL+X3{;d_3 znyxFR;eK5TJhvne>nnUXWT)lb!RJSchfo$A_zZj^1YAJ=!Ih)(4b#-djE_+rZI4K_ zdlQHDZa95IE?RpKMtjT}Vs0Ay69J5;C*PlLap`rczC|X@ntUjlE_MX;wO{H|Lc>R_ z<5Rfq{c~bnHAbOq&W&IodajKop=u-!f^r%qR@YjAe2^XyS)dATGtmL^Fj3Xo{Mo%b z4Jpuyv@|Sq37UVC;BHwTN2C12){uk;Md8q+u*FtdW=FY>&`7cP3~+uX`Gpx{Aj_sL zXq`x4-X?b+XRxjCp&nyL_zks`!OVhlXQGK-%R-G2W4pOqb;N=6gghU;4bLJoWM>r9 zGz>SM`Qlvele+ti-ITrWVmAE)Ro*lOX4PVNgVG$!T}t0(ir>cW`$vMr=1%F2E0eVD zs*GZFk3jasU?8f6xHlgFr$8NMAWY@g&M54K#DGK;^ zhI-x(XuN|lr<5RCS?(m9zdgqeR%e~~r)cw(Uxo$#j^nhm!+F3!oJK?NbMgPlA|BLS z_Cs4yM;-QeN+c4F0#Et`&avr9J-==z zYmNd7c0FCwV_7r3q(wauvC2gc>AmcUus}qJDY3eA1aEX=y+4B#adTZg zka|CP@k#bGF>~56brwcH28AE1t6*Q90W>dOz4~IxU}(9eqi%==cF+=&jjo7)h`Zsv zM95=YIqzg5SW8G{RS=!(LV8a)LwuzNUGKsi6KnjE5kf{5i%)J2n(qG~)R_z#^ay9! zEbQU~8L()SxnE15&keGE%ow5mekE9XiQ zL6`94bN@hg@4d<|qeo)PS{YNjkLjI#(vn*Z9}gFt6Y~%`Y=d_NX5Mz#a{}eXmlm)H zai65+%!oioh4B18{(A9Ipg@>oq)qoRmXxwQ>B3)Lik|2^-F*)!e`zto@*OGU)P zb$6#jg`>dC+AxH?{K`+*0vP+GtKg`}0yhZsDKuZrwLX!4;Ng7SM>>n}G5Q70Gp{4} ziL^?(+=nGz3EfG5R)12WAM7uDBxow*i>E(TGEqrB8Y0Km z*ECwPu=vFdMsOU5vYz_`o8?9vrZvvySJ9owNa2AI6J%wGE>SuU!=7ChW6^RI5S{S$ zfN@6_8_Gj?{Q=bf1N^p7jjKAo_nx=)2$caC{70qe8>{r+JWntj!$`P*J4el%+_Z;1 zoY%lekLJTaQ6oLcy{G&EIle+eiakyyjLM<{6)CpcA?}AD-}7zr`XQv9Ek}047iSh1ud`Of2bTBtu?;}S-hYwF&I}j#$sNbk{ zHzq`-e(mle-Sb^HVSzQc4zcxQ!_b^jPSr%qacI%tk4T=$Zx<1#*wMZz*7L3Pq=@vS zyuO;Z4DMIwr33GyBY<-s&L5JnxtyZz2xg>cq#r^t!I&+A*ju|lv_CHBr-8gJcja#g zktBqLFbh9jw~Fd238&8yh|Z8ss+fhLaaf|;x?rM1`lp6S#`sMKW^hqvH$ z{db9De-puDMDHOrntne!G4Hr5%!z@>6wyNzan4}HAd@#d#&^;@ab$Q4l$}admR#Ak_dC_LHmxE!vUH zKmbem|M}o@*w+bqX6>3;z$(Yzb4zTy$Jx$qAT#}tHE&`iGG&Lr;EEGPH47o#J~7C` z^?=x6!0U5m2kfygNTmXUtapaRk|B_gr+6fe=&*a5lj=MBSa@Jxv)h`1UNA-9iNWh} zzvvndNz{Q{}7&=f0CaK*W_G5uNp z(95vlR^O5(;<4c-=zOhi%rW!W?9knkMQU_XY}EW9Y{TL5*!+-rx%nd1;Gki{K|3*> zG+}vi;7)hLW#h=RzPd4;QJ(;Y5<5}cQ^6jqb4O7vE`$-&Ik|Fr6REhZ-bb+NLZHsEo`Rb&~cR@$Z?RuM9u8eBp6-uojRM zFy&+105}sg3aAh-P{$vY`{^0PN!WU~H1jbPNZQ;md}b=AX?Ez?Nt45s4rtiV|Ec~| zi@n;CZq+JIQC%i!Z8md&75OR|Hh19w^X@pDmp-{%o>r$c7ZLX$DKutCV591WvxYulwv=zZ04aB*N}yE>oNu_q}#xkzG+PON91H=nvVE7*@v@tXS2Zt^3Gm z-Z&L2_M@v%*wju(Ny>gB*fq_G9OD?>TQo=7r}31%G1~?4Earh6 zGJI=GFskgfQm57cUoG~KP47LPxY-e4{_(e2S*H5T`I=o;$=+sXc}B4Q)m>xX0H{K> zFjVsx3YVm!U%N3mQ%(8o4!4|rYhyMfc~0$g1I)k01G~iG_Io4|i550sH>BxXIfA zwcF+Fb*=ebdgsNX8Ob~q@C5OHEV*su;oL3c?-ViOcShTpJW9KQT;RD{G9M3kqV@gS z+EUPdP-Dm$Gm5Jc_28FPwkdfe&YOV~4lr#KoU6ons~6`Qaq{pRa@&yU$LT^Imy{u1 z>m{7SS+`lWN5{%U#zsNRQ%SUV&U0r4QI`pi)=Q0RrG(?8m6?k@oaD@{5O-``FYY!{ z2_?nIWmz} zjUfk%k%51RZ~KqdX~sI5h#1@XhVo!7?(6W%Qd#kR@KRg5nj`H(xDi5)gQe&dPBFlg z?r&*vsd_h2*bFPwjc$T@?Ba^q3-4id{-ZlzO z(xR=I8aOY?8`p|V=+m%@@)>(LwQ6WZlX`E-aV9v+xO1f~j~Y04YjYWtaBXh86F793 z$bCP7B9Yf;nfUH9-6Q^fuq_ttY$a!#3(0Vib^SPbc<7vz*tcm&sB?%Rk$dzXIz3{V z+g@ZHFNd`=xs-`g&&%P7=A`V}Zvtq^wxG?_=m^611qFVKdEh$uM=(E5jE&FvETiq( z$sDiGGB@hT55YH7b6Wa1UtmlC6Wl6kj~iCjws9YKy?K5OUF@DlWNffB8`4a3#}Vf8L; z8-sSP!qw)a{pBFj`};aVDWX*-WU?T4dnw`gZM!}w;AD%OTy1Nn1}tmWy!kXB5LS;ohPRa^Lx*hIWsG>#`cV?~W&bWH8+0`j6g! z@Hpp`o6})b1aW?hdN@Wah23<*eXzQChq$fE3Xo@;H|RY^U+(0*q+o1-UF5ME{LpW% z&+^V_0NN2`at#}?*ZDH%DUI_tEFD}XoWmY%QhvroHFCOTl8P?N%WlpS^2j;7Y->gf zE|bO1;rTh!^2Ry0i~T$&A~>OsinA>jS+hYqxjL=whs7r5fD)WoVA|8ea%6q9Ezr2a ziscKm_)W?BoB+{bAmpvqZreqC9rbS$9){* zr&~mQ#`AlRK2?JH75l)x3=oGI?0wczWOb zWN+WMcKUurk=&n+YJC4fr|(C_#RC|~edh<4+G6qON`VqB;8Jx!3QshA4teyc-X6WL zty=QXPVbmjDf$9-eo5!gc4qSBa0l&p{=^cs&kpW(8$5qaC?$KEU5dMqzr%sZql!aq zr(k#@jLDHxjs>}J-VCywv%RhnLqchV*qy_p$&Y<-eL%>ZRgj#M60Q6YMw{Sdi=1!_ zF($5S>TM;bpVKN+mv*jn%VZpK8D4gC?vf1WaNqf&de-WDv~LKUw7~bTIYU#zd8)&s zZtZ+H;@Z8ea7yl7(-Jv{$B;eBy5m~?!|a@t*lPk*VCOY$k%OyfSLh4Q(_uyJExrPK zi;&6Y9A0*N6#ILfbGtk_r@k2#@glXo<@;Rv0#|zJ`?($V$nm)yt#5Ym$PvFDdo0<3 zfpqXl2rTITFE)Qd;2<=B2r^3s53aLNHf)3NjAR?Mh0P~AuWh7xMb0LkHbnXsTSP<0 zO9O;RM5;(zD%)TTh#7Jtue1g(^h~5~Y3{~Da-pYfZbi=CH9oXib%$+mIJ{SFG0nG6 z`0QJspyVM=?=Uf{J-dUiOmq))g{FwJDNi`JNB1;XQ^j!XT@CFW(z=Gt4rxg0Aq^#w zK&C?)Q+W?*Zn{gXNaJ6zdPwUUnmTM_dD%mn-AlP?wJ31o(?gnn80g|Ep7Oy2(wwal z)0|A)LWq1w}|9vIlXm^)5*wzrCm;AOv`D>9PRWV4qfuFujRDlP2}|Y_EIr@ zd#ok!g}LWHFt_!?y-|$W1)Ovm(x(aYvvXTttc+Cy>}c5;Wrn|&efr8A<6kfP82t8F zYWw4Q-r#K6_wAQ4NgyY$*bKT8@SZMO>-p*d=V>B#kNC*w8h&7W^UVd(_FF5=XwuX zB|~mY%0=1d(y+~eQZ+jKlw&6nsROtDs-6)jr;M+$&D&*Zo9uMXL^rmz+1zw5W4;+D z0stjagxBhOx&YfA^ZKrhhot8_v^B&3iyztX^anNPReLo~hlKCay;d9qs1cgR?2*f0 z(oww(*$_QwjhUJ%v;)RG>Na_aa#$h%x1{83+GeZ{K#C}Finl!H zy)YV(Ye*6TTTB|^?*POv12dczKrZRhb+I`6(g4{aNjJ3lw{KC}F|gxlq?jRQE`T6u zfABPBh&4wNY~bcDL_or9vfY}D$&mA6BUmo2Vw(wT3I-^m&{X71m}^(1)lNr-U_Nnm zrK=^T=~G!GfNanPtG^)^gB7|A34S!-76Hk^Qu^((<9lM~5KlX1x&>87+hP=~Ws%GX zo2rc1KHMc9?eNqy#OjcSO~lo|b{wM+VtPp|eB;@BR)=k#A$-o{@J2v_w0&lPcbN(x zC&X5E84s3}AY=kS_NfV;`WKhu7!qv5jY#0uq4caI@x>4KG-il3p8$}9*2FUerDSih z7J5xpF+*ao#sJdMWnQ%=rh8n5_?Ka#(tz87q+KomDR7$r5Ilv(00M5y2gtF>0P$~Z zR{%L7X?Fz3=Hy7eAE^MsP~(YI=`trwiVvz}Z@Nhv421NBecIxnN?Q7Tw0So{mpN4c z61$89Lr5c$h=O|xAcYoA2^O}gNEF8qOC&Oceu|f~W_JX{S|V-1j(s^-0c4lhP#OoW z#REdGH@&H-0CGTV#Po{su2$)xw<=s9$!ElN!Rq1|Vt_CRT-3%BA9@&^4InzUDx~>J z%ikPr0HIAL*gS!FZI;?fu(nAuaXpkCut0`&CNK5S0Q-;_LvI?Ar*`Z`#Z%AT-S)k^il>Yt(42idQSsD!l$T5M z^n!wQMZM}+)?M@Tq+Rx+;^{rPdPowz16DkJU1I2`F0JCJ56%AVsik>}UH28!Q>M5Q z(}QM|zhzkQ)YI~+eQaLwRDCabxvAqJl_?^Trp2~GQP^m8OY@X|%7PY~po*vTQ-)}V zx#FqMS+_7$RPofMoX%XW@y)6b;A~d4gz=3C@O2ShTsUXqu+8rm!ZPomJl(F1yn|xC zshTRJF}2;bbLx<$({#O%2KyNUq#})1-;S#F8XNG50#7@OC*DNixGs5GA}!r#sWd{5 zKgjmF#b*f8FdsUbi>b9L%^RypEIVZz&vvg`B`&C{bm5}6u@V`k$H}sJtGgrHzU-pt%@VGw^=D0GSa~?@7 zE(we$1TJDJTN$Z}KQEru3 z&fAcW-q`m!7XdHBYNVz0*7L%R_06n_9He@q!&0m{=K$QYTSK^A5+E*Z1a824$^fb0 zR(e{&?Ur1?ri~q|U+P5(Hw)bz^Ji(e@tc6V6fF1jk>GYjnBmS7yyz&Z;5KKT-qVBw zTLm|V*ZXND-@H3}xis8Z^~MZoaBDhNIa%PrAm6e_RCzx|+CC~om3(84VGiVnG@uG@ z=PZ%TAJ?$QM%KVZnn>bo0zt3 zyP>)HmVRwy&hC#0mJI+pO2p}DtDCp+HwG&#&#XmL#Px%ji=boL4oR_p?`W;g3#Gs~ zD^E}Bvqk^HZxaPwGosaTN#3Mwm1$_A;7mip(*->3n4Py2hT!Q#UnyNuW}KFy&B?O7 zQd<1%j0cB=-33bl0O|NNkZ&EM?=Cx0rJt@bDVeFWpAxJ~cHIXFf<^WgY3WkDBtyjY zpy)FDOeu3dG$KRx+A|E;Dj9N?Yk``+FsK8wn_#B2+z@apoQG|u$dF1RUAEr7!Pu8K zk=Dr&6bB*-d$k>u;+xhN0EA;3vEjy?1-rb93Q+}+d~vWRSjAenz#{Puf|c@%I@q|4 zx+=wP+f%AzjvajToqj~4_8uOJSLE?cjgmxe-8pue)QEw;!TL}DGAgHLQeBM*w$oHM6jg?bKW#KvFfN$s*PcGwh^*z8)N z*l3JcBb4DKHXVTTWTO$K18nRGU$6vpr@Zd)Y^{^pLEw!|pR zNesB{G;x&6{EF;ldaY4e8^FA3>TsSF^kg`_>QFg#cR~s|TaeE9u#sxl*p*gk{#xOMVZwXIoBDiJ2YDP<88E*MJf&69zX=%<% zvUM^fJk>={4N^S1Ev2t25(n&aIFyo>#Y8!sWGIU*W$~2eZ&c2%>2YS{M z+P0fibC6&J233dbbvROVhn zz5xdLc1)h0F=>^2!^0ye9sOb0tR!91;>U#5rnbu~oFSJLPm63=qNil2zHO42ZDKuQ z;+nqT;xoJ`J*aJqRaactNhksVZ^s(xv_QHlk`@6-Jl!jCJG5O6X=#VKUB>OM>InUa*CNTaLsGaB`>bsxSci1^wAfrjC0HwqC{$cH z$M_~`r>#3zf>p+Jd4sh^zThn*uMyU-lx=7xy?Fr57aWy0%vlB|<6c3~j1#;W$YoZ#jnu z7R}$#79N}EtVPTV8tzgvD`-V;=ex!GjF}9fJ`hSbs>yC^#-&PzT+^j#ZN8KuLmI?% zEJE6o+VFG(6(Vpe*sy`=gL^IiBn8{#c;mTFT^gUNZnia2#kM)&#ybK2XImB9SPmSx zr(7hLZ9}OPl(sn#x|*n>^rl*3o3m8_;g;exZN7qNdc6z`%auzeW|P_d zZk>0$7Rj$Ibbq!8(CLd_SpXoHL^@$L^;UGTt!O|z}i>-nMFePZ*;7rVk7NMmApT`YLJhYC>zUP8Sfw%v)T`fO^AE}s(H zS!1ifOW03n+iPstCUcvd)T!HsG*>#tHWOA`z%xzmmKJBL*v5?yL*WLyudCR0S1gyc z64-;GA_fOLOy_pWXt^MzzM88joe|qXNxW+!DuV;JQQU3KjUF5rcMm8n{hPfN+*pll zlphkBs4~9s9@RzbF7S1@P&l5XRqmiq%D6p28t@ha2GaNdo$>5`=+1?f#3mLV4zDyo zI&4EYUr{`+Hx!d$+5re4`MFA@-B1;OZROu9%><4E3-dXed@u5tLLHLoX%H zHmeqMIzO72;$&nMITJ1kB(R&d+Ge@Zw#`2_SY>QWvu%rnUo%?~xK>-?8i|B$ltZ?u zu9z2gO4{a((bT(jnM8j>n=R1`;ao_+_<-jeThYa~PL~OPAZ*&8CJgwD!4SA1jf4rd zfg7G)gGbch#!0rfOKC?;QMy8swrSf;YY|EjQYa;n7|Cy{gqEgsC6Z+1>$Y&LC_R~V zHG3k!?Fdl_&l`(@pf&^22abe+iwO9FHry~?mTkJy5T5#i)-H{M*V=Zmt<$xR(C?Sz zO#&lEp(FGwEgfGq4NHr{Jpnf_#SA%6B?>Ie&S|u~NV93V^`eq*hJ$m}@{L&fy*Rv;d}I1(MCst6=i5ptA*TE%^LCqz z@YJ8_g}&fpnXV?n1LK*^K z+oSB5vuoH^Vbhi7*Rg=NU?ZLvWylJ9hY0p)8|NaF609>JU=`b*6zh807*%Y8%{w2Q z726oNc5>Z_CUQJx4YqACSe-2@HEuY3c6PR?)S>_&C)H%Pw)i%e2g{lwjhIdgxA-AW zVF#y2ta^IQ3cN_$BQ_6x1zyjPi%C`|yx2yDT#;=DjIEL(w{+P91!pBg zHk%YLDlVWnQpJVSvMt$Yyb)fjDuR+~M`Q@^BObT)TO~ty$uQc6r=B4}=^fb?*(#no zX8w=v6;EB71JmItm$;4HsE^~%b2}u8!3smoYNg|L**9$qN2E13P^n>=%&9WsX5OKc zesENyD18FL1=An941Hj80HxvrkAyEu0(e2ugyIR=R5&GS-iQAqt zX4}#LIW0-owar^1k#8Mcj9x#RvR3|GOtKn0R>TOaLB_g=93}NIk8h#CL`i`M)!cQK-gwTr*k{? zIo|6!Y%5wN&Ny0HQ(&ZL9njjzzq=ISH8!NptH<;81ZSfonpZIjx8(wC)-t)^Y*Cs- zZq&KoxkVQYBWydaZNC&-%Op*gn{(A;n`Z+rD??FQu1PF-x<}Hs8yhaDDoG28bWzoO zJ@gIHpdCRs5G_95x6T!=XAcsKFh8sB}1-C>n3B1fS5D@*`RH; z*sQ9SNY^E8K|DK5TE(`NVwn%pDz+UfQndmIVC>Z9wpEnQi0`Z<9=Ggi1_y7K^JS*fvA-pfToLHD&ZL2ta@krAB78 zpQaL}F=KSv#kRJoZ!m&wi#D+1vl$)MzCq?oP*|X8ZHxZ~S^ECCv>yl$VLCoPoe>}# zih-+ejnnlqe?3MSRYH#o`^3M^*eapFX;JV&B8J{t7B-~X82S-xl_+4-PHo(h(fTQE z#I*P}I$b8xv`!Wu1>PZIdLsoO0Qrp0!;K1_dLNj9NAySl!KRbJwhAB@#FC7%-O>PA zrH;@8ko%S)42RGo>8H%hXU79_d07EjX@G1`epWMNrF96u0evKZ5bA5e+e(H+7Q9$m zhA^7*xXuYrI|i;>vg=Z?jV@zJ<1K-V*_rzTuZs%|tAmZ!^arQP`1ZJh1?vvutBh}} z5GnF0U3dHRa=J$k46&Q72NJ<7=+cw zw+e3l6@XQy7~8P9$L#D&0&8gju(MpORgvo(lQ}&h!}zMT^LF3{8+S&|LOHE%@$&*6 zZj);fkdAp_W45SQj zE!Y^Up-Lk0QVN7}2x;lTS~^QR;}}%vsB){w$2TnB2|0vPhMHm$pEZ&0ZKc(sAk*ZlAK`S0`t}d(}D{+E#I}?VVV!>5}XwmOh{8KZF$^?v4cUrHCHgp$2YH> z*1_UmFGO0L$Sbo9!2&<0O0bx(;+$1U^6iQO&sBF?yemo0`$+4;854o0cwfBQJ*$@d z-k+`{ic!!d>JY$7=O;`dbse4-roz=VaKQ$&F+UlC(S;Dx*QGQrL1SMCN?FRk~9}^ zi?#)&Tf_>N5B$+K(*V5JB$I<3~X#(R2O2B6$2M#1Xv zbhjNpZgH(d;e@2E2sT%2qsMcj;&&l2LtK$c6pO1#q>62O#5S$fnYB!PRv1M>(h7;X z^lgLMif#AoV?t-F*v1EZ+~7G|v@L`l+V9}lD1i0#;UqLtw^}R>O3kd(j@3XeB^{}s%oU`^#1_>0RR7Z z0eqBONEA^R$B(ztysr1`qGqYsYQ31UZt7mn&K{l1Iy0*-5kq8%5KG=5lqmDfAc}e_ zf*y=6AVJ_my@XI0L{AY!_8`6VQYH~Bfkof>cFwY!i_3nT*)zZM|GxSD-)tkvASHy5 zj6e0c8L(zT6hrv@UJJfdHFZXfOi~Sdx9@amf+@8bUyy|a7|BAZrVn3!3#`hK`&NLow@$vGq!bWY8>T!L*%m)>HkNp;mDTLF*4CGiBpdQv?|yVcoOPzno9-+Yo{It}m7}#g3#2O?1@f@^hfl`ckQmL$ z=M_jEOY` z^rZn*%}=Y*toIYK%K}Jp!pqD6qq2W5LL7*J1<5rg9Bru~$Kn3m!gx!S?Ut|t7~2SV z0r#O54S$>3yFiCaC1G0JFTnPr5A(yn-tnv)D~GTj3}@V@sVa=^0dgO1TwVR%4-46Z z5JM6lTX@8S!J3 zawlp5XAInTwx8&3z}BDncz&w`THgsFMhNT1<{!pMab9}t;C**Pq%hd|BRDLf>ev-g giI^riY$_h3zY*u~^*#5T0CM1Bz=$aS00030{~ZEP1^@s6 literal 43929 zcmeEs_g7O*)b48o5d{HhQX(RtQ~~LbC`Ck?fb=H4Hv#F19TX%YAe|^xy7W#&O6a|} z009Do7D#}EB>L06_g@*~xqt0{|9Sl@5B^y* zmzRMae!jP)l_aGl@841n_V9MTC9iP*)_o-@85t>=`_f9cOrGA-^9XXerRD4q^lxs+ z^u_<{!uQwzHUCjB{XhFZZCc6ydk#If)5=US^)ki6Bt@5=85#Au|HYjM-{fH5R&cqR ze3d=6vO?z?J25xM`DVfWUV#ptdpDJ4;GaJW3m5%r|I4E7+4C&zQNyzl6>e%cz-qV}$fQQSsF-dxK}2tlZr>+m?NK&9tRRMkw2>Ag|s|s>+QNC3ChDvzOa;+ z((!Jn;rEaE51<3#MJ~>HVY_AKc^TKt0L=0OQk~GNTdux7eJIE~K(IDw+#d?)N%!MU0imEgt(#8syb3#tV{nEE|J z+AkEAfh;1=S9oP$)@u%_T=VbOQI*5;;JE&icLq%GfWbD!c)U;Oo4}HKfeVp`RAICv zck}Y23LOy$zq~w((Mmru{=#>^i~~jf+H2WLc7M{X{nLM!WBv?oZJfo$V&rd1x0O{e z@X*(PVnbE>jPag?F5v&gAz%v|I#@Y~;SI^8ZpG0n95}%;F}w=L&CZPBx#V|4cPWy} zm%vbdw6AqAsey4x*e^a~zkcQX1vlOnE(p_}qT-_puX!!Oe{X9WbRNtksfby=Gzj}N zFMn3k?wjoM(vC!nS_!G%T;SwxyWYKoH*ZQMY6_kEf^&cyL>v?E`!r0k`;@;LtCgZ3 z0sNy}Nzxc#i%i5pXD&duk_&{gm5c;+>aA2OIQl>C5Z;cpoP&Q)ifh=&ajgVZA4>f zgfpyMep3t7@fOxYPs_iGfRY{c646nUDfm-WEAz*KGIsLP-l?x~3s zT40*m(;k(@$PPPceiERR$Q(XexCo`uU8O{z{=}9mmW+lF~#a&v8gK!ZN4}M-93N_s;Rcn}lU{${)X}X=azx zkRnJ57O!mg!!QoCKK#{C!`MlcC=NnQmlz!jrDRY5<;0MQ(-`=jxV9fB7o%Q=fnS2Q zNU~<_JdyAA2^gk$|q}fK-^>~<>Bm@cA$!@RDy6s+QKVmml-ZQ?b{&B z$?T^+Ctc)=`lsvo1pqjU> zn$Mhy`=^Q5tqD^0Qo+5P$8>;f8d$**o{4V2Xha)Pv}fs|%%dW6zd}FS+o4g(3iakY z9Y>G5WrgRy#35Nofe|q1RT%bk=7Cj8ivt@Ok~s=mXFhnxsd^r=84$_Ix0FtNO*3?+ zq*E2P_rHF^cWigrZfj3{<)m}&NZ2DCcLpTfTe;HK#y{CKtT7x1%q+^-0pWUv%~w}<*$IC3dVqj z{ppuLS|$cdYneP`fvKvoUyH!fazH$q8rerx_G>e?%C3<;!>0=(yb2g42xu_iL;9ig zG$7gDxflLNaf6{E6Lb^-rEKkR%|@@w9$xaDA=!JhMs!yiZpKC;2G_1d+*u(`)}RMRq$)rOkVaM5^sj$tC)17ybwqGrcHN)Z5xmOx ze`&QdhfgFb(jmjtZXuyCLE0Vum*h$*GwP`mf}@F!iSiQRPidoTMahg+bSF<6bB`MacczY?r; zn-0t-thrl|`9xL&Asj`1Gx~nYk1mZC!mo0ZsuxA8pU$ng;(6Zz(KLDdXi7em$tiLs zf!sq&In&O7Hjhiiw{;3QM1$2)20b%7bVK3mULpv5?eOVbZ*K)@PFO1*X^ya;jE;JI z(O|akmS-1J7n2Z^s{y}enHV@r2`nMkG_m<@_#Mf{bMc4%)3Up@ITN4LQaJOc22~N? zt!zDmizeTN+5Yd~{|4cIcf$W3hyTTd|4+bp8dUe;)&99w&;&ndu5^icD`QxkD1LDw zA}Qrfp?id<-TC|qc2Fxc>ie-UXsVh14}JMb_;k7bbbYPT+z9ZuguS#3NP>s`_MayM z47WW)aET{^M*+P@N6bI!MZ)-``DVfCBa(Oc5rGD_%I`>uZQ(rz&9{AIk|V@yv0n^| zbg{smGOVCO7(xxJ?zO@91YgNe<8=B}yA`Q-UTr=~#tMt#`Dp+d_fbX!W~D1vyv$00 zkC1vUXVu4#ka(guBcCh7Ff+d&#B`%r9c!iIeF!f<{S z1MsXvVz6&wO5E?>K9)v2qp1GnadvvxmU1u=Iej+2>WuV0{6U{yoQqi#EbraCNqSaq zS8eC*pFtV9oY8{DT$J&V^PgxrplYnXKmA z;S|Rb@H;9-|5#5<;eF;@CXIY+iowVFncK-UQ{~5)-3#o~@~FrxmR-K-SD*H)f7adS z1W$NTI+CuXEPj7-yE?zNyAtM$P)OK%e;t{0(J12d^#m7FX~5h&R^w7W$4(-Sd0P#_ z7iqTAH{=o}mAJ;j{^SY*iSO|p+H+`B123;!*O3SxdOw@%)N}l(cgg2+h2Ec35`E+Q z79XdK-@cMkhBW+ZugcKPiM*Lt3%&vO0mT6P?@hI*9EhOvY*mz2eont8M}DP>Hdl#9 z^F55J>f(>y)=nwS^1!nc&V>(P7-iwz;X7_Bhpc>3vE4EX?`Ch_{UR}e@>#5tKNQOv z5fl=#8cN7xd)tn+)4{*X<})S8{>Sj=a?$J2bQImBO~R}6QRahtMOYtS$fhHV@{qpn zQeAIWu+f>m{Rj*mZ67G9kv$9FCfbF?`jF`GqkZ?HwDXs5)oZuy$CPFGTC2%gZn67{ zsk*wERDCM2*gOh*HR$v^Rgh8BPg1Lm*=|YPcTTlV`DYi!OiM)avZPYJ!`b2}smp__ zEx%F-C8=u|f6t?{+euAw$O~CkhkzUB(CQkLgcYw@g+Z_y2R3^Fmxd0-qcw&R z@H8U9AG{@w)SUk{{5t+F-NCfAn&OgJ(R?HjfhhNUvS;mG_n4myJ}EPmzpL`-RpN*7 zp_qze@2H3SKU+ah1ksyhnF>(S8p|`y`?BrmhNS0``ii|5SibZe-B5U5UA0TNOcmOX zrhOMz|Ji=(7HlEl`ja#LeCs}|uW$Y)5La=C79|hT7`}v6y8YKO7j+c7wJMPLB;nl}okZyK(SV*@!8;6BJN~)n z;}h=MYAb)FmLd>+4KqI2CEEWY=;C@tk?wQp*!bnII9a{uP2AKv?Nd8apP#$Nq9-I! z{P?YAJo!oWlX|M?`9Q|U_Vab~jz~n1k$+)ilLi{qDx-l-x^jb+k}9bj5NU+y@sH1) zgADP_XZqv-qrRohJeUOF^Gj@6x$88M#Wkel+fmf|ai!N}%bPo5dFM5=0ft0E%klgj zszJ(~ji=pX>SH2lMOGEB?7!t5p&G(nZqEhN?3i_&K7Jg}(weak{5;MB zqB}l_VCdEv(pmZxQxh;b7vm&eflJtGo{mUA7*(8e?CtDZtzS4<&|QxFOe2wRL8hV_ zzdQU%hsMVsf>?@!cQ1Lcw#M-m)>bH5^6ct$z@~&s8vgsJJCX8Uezhcv@!d%Ibga_H zqk~ITh9lkln#1>!VF#Oj*4mPInrof_*2QvtU-cVZ?Sb>_)1Ilat_|mWY;&0fc5txf z&-?)?{KVa)Pce~XG)!Oq>NT6h9yrRqXOd|XiB9%-thY9gQ6>-fss~XYLUMldNaWnB zJExn)XTL}^+(>YhItp-CS~<&bDZ8+(^;soKZov%rUJS7L3ONdtvj^@4JjOK6ZA))vRx6hcCUu^Vhln^SyZfao>awUoGbs;eDi?Irw` z6Mpx*eHM*pCV&5O47TlU%joFZ#8v%@)Y=dos%ly8yUgDx>agi|bor)VMcAD?9qN_C zn?_~x93aC(HEF@Gx(x8fCKtj>#5G)9QcHYmBBB*Oxzc$8oMMWDKysZ6rUGbdtyGyV|>|RXKGhEw&X;aQ?y-6=MA5` z_oouWP@y0E^0Itz-|cA?fjhH)y_splfgGZ#dT9x>#8;KQ} zjHV$O$Jl$!4q9@ZfgzzbS<}!?)3%#owewfz<;|bKJH#Wj{7<8ty(oo+?V7}-zrBG;W1>M|KP2#sh3BjqF z(xVWOCcmc?3+hH$TY+s-(=YX!jdTt%fpJ)He~lWbT9Yc(KUEV@uCM9Pto1DnDk11s z?qWH9SmRc4VpZ>I=fuf4y148L)kk8t|rcT&5lq~`F`UPWJAdF6&zP42aqp9ZRFE9gZVaZIGAKJJV<#_l!# zOYg}6o8`jVY?v`Ikp_RCI)|vByijFP=|AHPgB>=IQ+~m_#UD-ErlA7K=KLPijHpXv zHfh7jC0xL8cI@-v$jA}k*U`RJ+WsN*njatN*drdYOs2NNwZWl}t@mqJ`ya5M^D1HQ zXP5Bf&oztG`CPAW5N=TxYWz1W-AUf-QprsUdETKrweFAip28Q71aF7{rJq76CN;~q=LHUK~I@7V| zf%_#56b%CgTsH;+(wLqYJ)3j23{qCS6L`7L%`L$T7glo9ZBZD>U36>Vlelc?)Ag88 zWH%`=Bx4g^XI%FY0Fl`Bj%AHob&!7>XQEyjQGLL%p7R9DPR-}d|M0I@tbAipsXMsi z=kNFA3Wul^ATbZu@P&UodYypKD?#@yCTCYx}-nNP9uV zWXX`fv@h~4wGtoVBI~?29&AV7rfd>`cnP8WO`JG@iwUi@3!GH^X{FkU@UI^tI7^E_ z7)WQzzsRJ7*_$8_w$6jlJJ?=>rq!Z0*X-`ZR1jWu_j3{A*b|)xqC~6d^zs!($FZ2~ z^Q#nmzvHFavBi6@$I0`jcay#`jZ;ee9hOnSZSsgsr$41xP0=F7v|1uO>5V7;#lGL;p*>iY z=b1qThwbDJ(DbvYyb;S0x<*l%W+k`9-fivYSF(QmJeTwIN4e=>;9}p%07=`Kn){j{ zw;oGFANP32w%pTN8e^G^^SXde_deyF`E@O}C7%J)xE105QMI5)W2j+u@apU=w%bft=S*2n+iuwN7QJ(^`D?Gy<{eiR23W;cIXd!`O&UkTs; zuoW@l#@S-k(tEGA%=32#cEQcIdfV#jMAND&6c{1&Lf7#wU(P_j)db%B{`0Mj)@dMhJ2Fl$(Jh#O??iSPYe`fBw;H*CnuFlCrVjF}_cny%Rz_c^>b?FWM#Z6#r@ zEU4r$Q$PzV^zfeQA{KBI z<(N@4-Kf%MXSn@)+Pi)l-rNcnWeQXKRNJi>`QmLgsHA5BDbhzcGyeddIZ8$L(bDnUJKj*YC1-1P; zI{f5LF$&w_ zS`Y0O*%}DXy!vBTnUqHeqjH&_l}<%<7NM=8_{V+@2TWrD?wn!Kts@}5Y&d$KGb(%J zr{Tg;h5B#^j%x>;l!g!bFR~wN7pGzh-h^(XmQaeP4Nf2d5;3 zEL>w1WieMexe>gW%u?G;slKDOK1s1uXQw3LJ z^_0n(kme-fqzTk6=_CAf+fI$@d2@@2r}AcFfGtu=E2)6b!^6jD$DOCCScQldwLKBe zW>2vJ9b*zdO*PJEX+XZ#gjVCuzX=uTeW|r1J$T*X?CVLj;Wg_5un(Cip53M@Wnmp3 zrK27Hvx5O23WK12q}Lw=GvVg;<9Vvr4VyVM_f2617p=4}Mi1jCbB|3cHm|8vfBC*o zFJ8A;M{DmymkV+qa|{c3UmK*RU#Csv*ECp(zw}|fSYPf_FJYJQ@dSGMar(JK^sD$Cer(7}&Npp_pHsP@oHYk-G?aazWnW!OmRqoSs*x@km z1?n}cI9OIc=fBC9J^KonA5j$FAh|o;FP?ZVuzm%6Tr| zf+ATb$*gWX-trSh%!P@&owP0`mF^g9Lc;3QS94xje2lW{IXvONB)tBpH|u0>baQ{t zhP?5BYwtm1rGfF`0w+G`QTuC`whC7<=Un}}olfXm9mwYV(|l(!+f)6zKbSzFF4lzH zDH{__Z*y$g04DZEfV1=$Z}mA5H-5MnJ%R5yrjgUMrEKi9hs%F6{L6`)AS+)b#p}%M z^8SN*gFlCYOgF6q-H*b>pTKofjb$v~G-=ruR*hAfg7R$ACd)STYOScSEo0V`=q!## z?qG>>saji@h%%<$V2&@;m?zdJFuhaH*CpE}(-;jqjB%l`3|k*}d`7H19Nf73V7tmu z9e282mop$3p(eniz4W1?@jU(TZ=3OH#w2$Fq_^zUIw$z)cxX>o7k9F`P zL|Cl_%a0HXmL#t$-p_GUV=vcBvL4EzvAi>&!r;J4CGi$-xyzp&1_PAt7pR;mjM<)j z;Wt#1VD(l9HDD5=U1s@~*cy;;Bbu#Swni^p+3xxq!KyiNaQ8?kkp1ZS2xJpiRG^)! z+-c2`PDuF#&I1A;!KQjH^9exQ=O5U{AEb{D|5~1?)HYG%z91mB`H9T+_#C-j&;=4N_V)g=Z z>t5ZenIGzo;3$z7e)rGwYWHR#Y1Iz}2@WM$*ZhKX*q=MjORO(42u)SKhxfUxKA|^! zeEy8Z9Mf`~5n#wqOF-FH^Y5Fq{=^|)uYGA$V@ktpRd~%#6o*|Ec!6I@HJko+8p~B< zKU4Bvc(9?nQtiuck*(n?@i#K41M4}*8CKukRNHzlq*i=SaB9m=jCuiyxcFr3QSCjU zs1B=;FIB+{=w^=64M}H14X22_$QrC7O8*|`)4qS_+f+#F@7L$ePPM-Gkhi~_e2AL! zqqSXzLe{NPZ#+Cz8y>7q#>4jiOIiN&YGJCZB+XdQ*v7Q!KW2lItk|+{)rK)sK~Y|0 z^*eb(cT8(^IAKmz&#>I7%@8DUXW*g59r{1_jcF1h~m7x^qVRbX=9mPD>Yt}Xx1b3C=X@jT6eB*qH?;~NP)SjXvU zC%R%BD~s~ya6$;~FhVDG`LC(KRH5~H8N)R@%qZzO+@N&$YMjDP{jMBi>hlew?r~JH zklAB=(v4b$6GaY{|KL`;?7u;a{=D_UULJ;p;8_M1bFch2(U!0%VoN+xz?eTN39^_X zbMk<-8?X3nD)0g5O&4K^mEKfo`?Y~&dzMd)ucVd5Qwll__&08`@J*ty5) zlOS$*^+mmkYI(XjL7{K1b98>M=27Rm_)b5Hg+)?+xX*m@S* zU|ZCtrM#iX;f3tR9Jd@ht!qYV#7g_cR+UjzeVw!bRqSjWZWE5)dvI3Ic9g@74K1as zdr}wEW3dj6LVbp8?!S+*N~DR7Y9kE8A;;)Ds@@mC@;`756*;3weWc&!4-lmyn4rBl zvvKUi4r<~{xH=!T-Y{lGsXd(>J)@ZD1CwVQtI zzlzZZW3KGZi{W}pO42++NSL5T|j<9OYPF~ zi016l3|RXoWN?f z1};Xo-1%8xC3QG#fi=aUJ}Jenezi{_px!!2FfK;9l|kN=uniKgI@>#I8HWXi1lhRcQAq%jUeUkJ^OMX+v?A>#gAOPaJ@X@zfb}vh3<14Sdq|tqe zWV-7MB_xjC)V$e0fuG#ao}`q93&(y7eS^ehE02c&3zD0TdM&4R%n1`$8v0yop9w;j zGLygi?0R=tk8CC_tbHZzI^mL}(-Owc(+Zz?eG`JQ>(-@r87<3^@CU9s_7R)!TJTT} zU5vh+U}E{k0#c4DT%#9sci`j27JiOA!^uoT>c(HU>%&!<{i-K2-Fbigjh*%_S2&4Z_NF3k46vy$p%csI39XS$)_l~~Y+Lenx-HE#Du-k-UF5Z&59^|w>` z?%VUKOi%SyOga4KFh0FgA!mP@x&l2bA>P&j=fv!FqfBmcu$Tw*7U|ok2y-&}p2_!d zx)_xQ98Hv&^Zo+Hh+C>(+Y##<}UWg2!XQpRUBb-|4_2=>(5rZ1*LMw2mkue zTq#Xjs1u${3|nS%um|SvFB@7U{;WGB5Tub52}$`*-Anhg zv_H{J?6}{jROlO<#$klzs(vUI-!*5j9cWN}7ynNgXl_j`em2lj<#`zoq6@`B;HqYqmNAaYSOIKl!~}f=UZ8@ zpb#BP(%0KFmt>(j)LQ>!tQo#bR}}Cd)Z1jjl%rKH?F9k7&oMY=N5K&ReFiK8Sjj}` zFmFa=HsJuht&vNsH~kn0?aH?d%aMu7D48{#<;NwLDZzF|N(V-!Ep8Kr6B6&I3G+_p z#sCgM=Z=?{8inoGyEns~h6-zbJ3UFsL*SwQRuTfYqV)A&H44L4()~?^yZ4{zSZ&IY zd!eQm%cgbncefd>{_wA4d)g7x2zU^ZZSNJQYqI~(LFor$p(oD+DM{Ud>sa)esbGeV zpok-5et^|kt(5DSdBF<&xM$7IeBefkoM37 zvEH(l?Adx=SS>~8r?ho*GIxu@=*cr(%{iy zU37C8Mj{s#SC~jl@Mm!^Ug9#<6&Iv)a`p~e)GDYOws&^UUe;&7Iul#|tzx^MqapF) zRopL>d8tSCBx1)JbvAoiI(_ZXzKfJZ-#!rdiL*|`o=4yn3NBPtAme(KL50u2F z=4}`gZ-;Y;ssG`s57u=MqDf^kw#A18`6hu1*SzlZ$$lQLq#JRf0 zLX^Qi!Q)NxclnyrEf%ZJ@XE3CTN-SN@bM-mDpF+FODV-WmSZ4$WT7N`;BhtjjV@$0sk~N!M1;h$hrpEZirsj*_Ll4w1`i2iOw?5iK&^}Emy`z zYUc&6IUWFb0Ykq(dl@Qgu|$I3Y0DcRo*@LGJ$v)RU{WeI_e?6oPO}zT;DOD9i7W0J zgx$btF&a|e*^e#jRS%ljn%@j7;1|lq7CU`P{QUd3X6UxbY;yO)xI+=-m2Qyf;Ju3U z!6%>ac)Ol*FL&mHC*dV)UWbTp6p~zx#-7LR%+fU{!0&T$wNBfx^@|4%q=21_>yR7K zZDo7sfu=xy3i{KJzxVtGF`Hgk^@{w!1&wo6i@Dz?AG$lTyen5}*?4T|&8<`%tcwrP z=|3R`4-#XjGk;yUrhO&NENep(QKLe)W$tdw&kQ%7kDVIq3SZs3bn4||blXiG;S!Qg zNY)Cpbwu{ohFvwas=p!ilv+q`qWh4k@rQN$YlW{QNRQC^tS3jsG(Uqk-6kE?KI2;M zDm>za^!_3neCx>Bs8p%Q@SsFIT&N$l%whc)d&Y|`vo=4w61E`aOdPp5ns9WTy_V{ad=p3AQ1*LEC%*VI6@#^>` z(fW^!?4ozE^Is!U?G{PSO{wLNw_=7`zblW*J$3WGNeZH-i>A`Ay_#wk&21^$f{03R zpWjpZFjm(ceuC!CSPCO*UwsWa3be`hEbq(#)HY_`M0m&Aww(^2PY@gNEe~2s+#WZ= zZ3hU2v#quIBukePQ=M^eIU%t$_Sy97{Dl3a zqFRsEu`dnw>(rj~ip~S@NiZ72mNw}3(0rQ>pR-tLb(VHPEWz(72C@Eq<%RaEu8Uxb zJ%2MypKk1}%DhEjVLXfduJQdRx=$>(E=YFW;#B-H-_*F7U??Z8!{2CXBkn5Lp*S6b zWAaCCO24ec*f_U;Y>p~YhivcpY2GC)Ky25P}RxOX@q5CW=w!yg*zmj(1f00k}N?E>DwB?Q82kX6G1 z@JmT+X_`Bj9kk)Y zE1~~HkK;4DLUieCo=iYp%I5&G&9>k&>z_?ZK@^SlKMtI25%2oXMO? zoQO@{oT?ZB#&@Ta{F3`a>ie}RI{|ia_Qkh9>q8Y|(Kf&`fXIU2D^WfHdYmH$p9L^z z9KL_QwC>&%yqKBH*ahVHXRp#Ogw*bj!)!u3*PN=jf0dO3&*X#G4nF|d=cH?0BliPI zb~`ffstu|hUp=x>kZFC(Bu8l8scgp!;q!q@4*OkLLWy^wy|gBSJ4uW1*yN+VJl$W^1ce6&l*i1i6@=x&i`} z&XZPQ=2sT11+56MzZJD#?HeOewn+OSLTrelG_(YFBFJ~VlBGK`d?e@?i^oM#7<`n3 zq4FwH@r|yi)BU*ge5y^`!G5$Fw5j|zCGRYc8;Df}Ft*Jz*r(qC^XIWEEc?b?U>|(M zl1sK{PyNCcasd;oP#bU}>U|x5R^kg3MEM^T_twH=C+V3e zwWYYIX1G#Cl>UB^6f(MId^dN`40!zH0fvV>bJ#Rq2pLASN&;fCWL#|%^O<22)ox41 z$UfeM_UJJo;`KD=Ze8CAlk&venp30=qi?LCb1$r8QW(H$yja;dlzMrF`kYJ(&cNNC zSbEx}M!|$E?NnTL@<0$u$EIiA%#eNA)pBB>9*H ze}s&ROoW~S?R?bI;i1nckTb>dNSq*caYA0NUMK@{L{Zx~M77>HL`1yx-J_8S9(?5e z?^T;89&HmNptM}0j-N!OX=EdK2}=R3V$I{MQ}FOp5<>-d>Hdh+oSd!HYhq&cQ3g?x zQSm4;ioz;%4K+yAD6O#Dmy4z>d|+$YHL;PLqVcss|7%gkVb$yiSaYJA8!;B#85U)B z z5&iSEZ~b1XTLfqn1X!$``Rrev5auJC#hOVb^EvGc-TQ};S5hAq z;Z-ciXby&7)N9J9)$0qPemX4*AHw^BFOuDR`c5UXnQe({2wR#faPu4&VC#EZwQCIS@u~W+}EHbAZx(*AmUqvw`u%ye9h&l zhpz$QKrh*^MEbl-RM1U9e(`D;gN$cqhw9{lJ5H6q&F_io^+h-#^x_IL{Srw!D}~VoQBU4Rm?%NkL12+Bk^Wimv{O-osz~q6p0Pzp0;G1xdqEr_7e- zt;3YCf!h2K<+4`jvLRy%B5+W~L90yyV!!Q;*X{)0T5>p7w$HW79CRjUFXdG6Tjb!2 z75#lMFxlg~@(o5nW$-{}g}UrpLWFj@z7PN8Aop;S01NZVEvf8rOToNCSK(!aLnEf| zjgWl~iJM2eeODERwC%<7H~q~1hVBmuKGp;~4T`jL>q^n>NGL}6zt3l`vpCOKc92fl z)+6U0+F69dhXzs@q+FrmgDTeCx=yk0hY17!eGHx*+l-##W}5ijrl~_EEQ*nxXW*y* zNYd7lAp}+5cWZN~^SK{;;&M8}!u6uZHqw~Uv?a?1tj?1BdHtK#U|m^VtpThwH5={dZRK z8?DkyJ+DTGJRolTQa_}Z&1CF$4zs>Ur}!N$+0EgX`bXQ^=zC#r(`jtwZ%rf4ja9!R z9B|hMn@5};hoe``ZdH$}rm#kYvgT1ueA zHJewj`d}wlbOi)4Xe_N09j1E6z61!}*sr5m@Vyvm0UE5yq;mTL*Hzx{Q;+(k5` z=hZz1SI}nx*4H#k+}ys)qb)ln6NFrLmI`IkQB^mCY_bB^KOtU{2Vyf8|B<*VKuUiU zFJf9``hj?Gx2bpd+dy>-*q4m#o6)MHw-wqtab{7A&FV_fKpE^%=lusIfsbm=hAz?R zvZWlzhX?8_o+GkPPt=DdZ&$h4jC;@hOPcA5RxPev_e9bJ)7%}ID% z7?0kg0Jpg=x0zBjz&lSNGB(orClfa7EI+jckO4 zPNma08=@dWz)&xxxsMtV5Ch`|INB!WDB9D*UpCqX#=)9YYINI9{jTfN<}(354b5w`2w9rB8nB9d_zDjPTxYrf2VX!K;2VO_ z#9U>8zmVp~n*dRe0IV|6nloV&^ruq&1ZG+VcRP%9nT8x|hry3vCayrf1O-#nDtQKk zp(rePd^I2CLXJ;H(9QuJxositnl8?6HoBZnkgDdHa|JSSI9v_dTefk(r#LVm4WtFr@QU z1N_5EOZxLtM)l`#STWpQApC(DcMEU$o)Cx~WXy*B^wn6P+N%np#A^^ji4?1Ks>QZtOA7jgZoxn=$p) zZ5NCtL!pkQ@_sg^r6WX^6JppdwpRY-N)*3Wr|A;xIn-H_a_vOOEIWDBe#I**vCV8N z2QW9V&+{a_170dmq*JE*`%3cvEOG+}=TE(Ck!5@9v2WK8>8UVYBgRw{4-@hl2FuuH z-FW?^BCO4^3N$HIN@9?b|reTMY;3UuV$=l+uc>W(sFuz&PYcNF0Nlp=x~BYmzYR5sr0H zA=`f~bNN(=@vRtv&|r@^fk=t8Gm&mUNN*y&_Pgpr0T(p6|GCS(3!DGL7!4VJ`1t@} zgI_K69}{Gq^Xj|`wcj%P@0IFzzd3W(e87xwRe7TLGdF9u-=#9xX-IvNYvU*HQ?`qpI4cWT~FZ z58cyWUg94nqJ#Rg{o>#jidR@_UBxwlKsAnZs);1vy^o6ZqPC6EZ9U|BP1q3s-b)`8 zZ9l?HZCb;TZJp!b!C@wCr&2C>1K3Un*PO>Jo%LgwNAgl72Sz(PP zT-GsscJX*=OmJCz=%GN;K<;49m$fg+kQB0$6{SKmfYrt0!Ba~t1%vGA z0E$mRK{R|P8SP5pB&UI8c+HM)0~c(Ol0av(R64Ek4!tb+gc)3@ALDk4txzr=czWVT zD>%4N)q6fAq+;zYlveOQ(bp@KmxG@QT6tKu1uTMTwQ0cg&-eAMpIy3vqN59{oUawK zpJ1Os&U9$bT?Gew^%^-^5OW>(iNaW4-FVKP|AM+;{LU04U^7w7huCzW;4}ddtNm{+0xB^VMUxpZUTZKpDyoBTg3O$ZzAV0ty{nd zkieg0@^^3x!Fn$F&yvZlobJzAA+)h|o3PQ#0PwMYIMoI@0svQ@*jGcJEI1<- z1z*rU$p#!KC<39@mg8;aQ4}v#5pJXaW_FK71x5T@@`kkSoOH$LHm zvAxHxDk6JsRzX;uWuqoT_!)&`@8t6tjbjh5O1t0xuVaT}Z@M$fUiSImsSmHl$(EL_ zT2mZov^M|4S-EtBq2Y%=r$Y4fF%yM$p%mpAmi3dk_P;tU^ z86h%W>`FMf0`0?I!pWZIZNLR34kq7%yxvsYX!&eNOVn3m{^7ZFm4QwmM&U{{bfZm~ zs9^U_lrmjXus^Yg^6_Xr-Ez*2BA;loy+yEQ0?Vv^s}_aRw)h7&lX@qKV=h{Zl!j$? z$%x0GG>(|I!34i=;tOs}42|X`_J#P#j0x_KSD{&6>0uYz>{gF7XR~X@a^k(@L{ASn zbPO8ayGrDpuQIq%=e}3xT6MUFuH!)N-{OC7KO2DCDjRuimhJhw#&z`7gh`7rPJa+)2tF|1b0H7(~5DvA{U=D=-?XE4hNnJ99&c; zz#H#aU#wR-d5rt9e00ModC&ZY(!AVTw*!mXxr}Q;kY~dtU4HRwGs6P%r?qVFOi!O_ z-i&2%79P{sxRm2NT~fm_ogUprVxU{NdEjM?OA>!6oK<13-{d{Q7=4=TKG}9>*Vl<} zANLY>R`?#`_3&@s9Q(E79mu)>>HO%U@Vz20VrE%^#PO!J0Phm6H|y1s|9|pTgXO(1 zzPAcr$?%l1=GaLXP@z(~LU%dtl-7t^b~>)VFMZU>bJcDt)YaoDZ^bb>!>M-l7xZC( zx_`N}jN~CMRWi`V2wX0M{T!ncs(u=M_U&PYy+1w(Jox*|p^n3RW+(o_*>&f ze2u@21f_blA-A0+qrttcs5Gjko8^k=;&gos#?q(b>Dq>=gV|BTR)d~gVqdK}Z&{i} z#7F-YGmN4(FQ>U^Y>dl-C5c*dS60VcZ^Fk_3H<)hc(mxrqeq>I8_~u|sooh{j~IXA zrdbENrd;EfRSS*f5}i{v#a(=jt@!jx#5GoX$yZWZ`-&<2wYM)_y6py6l+@AC`(~Qs zuj4-1G+x^0_tHXk-@_uf>w3JoColGsV8Xklu(bog64T1pJf_?qWFryl^av!!tNLiI@p7UPWg;|(49ZXi1HrAmouhs2@&Pt^i~6hXtT$QZx2m?&Z=yO@ zQ$=4>9EVNQO*v!!&dr4nl=jURj8=Mngqf8Wz1T5@W{wyY^&KS|)$(`x}}Xx9)U!U<;bgER*c1`ab}{Kt8{*9wWcVnsW&T+^7JL zXWI@XGuhm_TB`1G#rcg`;7Uf5u(J`2GEbybT|nw{fl;86Zx-6VzRWh}ia6G5{+>)`<7f888cR&k-i}lc zjq;RaTk3GbH`#d0@uc9DY-a=sYcwgxJ8>-5jpJbj)0G-!qcvAVnA0oD^9Lxq-Na@? zje;HQ6TV%|F*%|h9u}PcI$TlSKZNpu8fBAto$zn2WL}iTGwUI07vH<(>uv1xn~m8a{B?a8JEp(^!ME$EqP#n!JdrAb zQNE;VK*g)7gpmVIeA4(OPtZC`^{CB>_i9cg!p|fuFsc*FjZ?rk>Z%UoE3Fp_Qs-!sF&wLgC4lg;v3%FZ zfirlHW7nn_x4JeLoBZiMZmqT(e2yyio|ZE*{x=4?vi>wlz^uzrS?ruD>Sdju${3RE zv&pJ!RDrp(y{KPpO;fHj9BGkowN?wfJ+f*h;n^Xph@E~dg|}XYz2=DTQPHU^ze*HN z^dV4PDM;wT?_1+a#SzIy1oFQH@&^1&O*V_zC8D!g*5iEJn#sIR_}e6t$$(9E>Z&sL z*=Sc%yjbj=5oTOBxRj_Eg+qdG?^9sZ5m5-4IgT?0v#LQXM}hDe7C(#BU#Dj0!i+ni zPt{D*<+94E3aCAk^Qhp=>{Tnl^OSbvG-n)`kIiE-odsV9l=K3?530a-SJ%ua4`yLP*kF&$N${oKJ02=uc zPdOWm?`oY18H-ZZK7;2Ynv&FN%+fj<$dMY@WL_;9E(^X-q@WgK*Q-pQtl?XPEEE3R zmbvUoxOaPf8Cx&0m{TPzm}ZJWLv3olX-4` zyJ}`KU(u_jkK0gZYw#5*ZbK5bUG|r8rV&d!rOOKGGL?9mE|=tMEMGMf2>UNHand!W zurqJUI#9Rw*>`hm4OqWfHf%?62(}jEGYg`x0b2}g! z546a@wMhw<6h_NzFcMr0+o^@6m2bu2HN` zwCHtC2zAiEBQg2Uz1^~r>6cPNj_V3@^p=(NxoDZchuk}$u_}Hw7{1OzR-fuOz3mO zMO{;JfNv_BZ?1Ki~zzcc7bSIx+Kd~I?%<&`P6 zPjIML&2$NiR`5z@@NEpZgR4Gc1I9$n{yg!2QtsfX-FuV$?aIt{-TMZ6kL22-RZag4 zLQyJk*6iW~9_6Xss#)ck%AVY{zDj1KteRCG?t{U1d+IqfotZLGI)-Gt4!FaA4oepQ9RePUfkeb#cE7eyxAb0cC^FmMb}`S|#Bc(YLc+dJoBNA>rAi zwpE5n*@}2DSVf0O!#fiqu{GJ;u8&cfuS&wR>3j}+qq9_SexEg0RoA$hgcE{SRN1Q} zyaIl|bGE!d{BT#~c(RRA*rOHx93Asym)#*TFRzhJ;_T9%Z#8`8CMeVRt!~(A3dyA@ z_r%TGhQD@*gzz<7=v`Abb{YVCbx^bZo!9t6OZSCxo zhBi-H_VNC)b0(&fwgd3>m!1STlGa*g=RK+eXKOKR*|%8XM-)`^vgxwy26VwDGOrq5 z&>}tET{Q?&0NEg)uF`3~J;7zVoYeD&X;}Zujv0AKGS8FO`K@SBKO%hM!YBi$=;86L z{gqM*;q*p_OJaRNQJvo%AnJA-N{|0!8*zptCn45vX1!&Ks1q&lE{xhd)X(GCf27n7o?qKxQ3+^YaLt4;{MQ8eTK@mL;j5hOCp2EH+IhtiooC3Z}D&ZLgi;6{D5 z;9d7F*GfRkuJ?)d0kNxdG|F(adKBah&K=tW0ZLorxK14R$+V2Kwvo(oE3Zn4ZB^og zbfhL5EU=X!f}f}kwPzfc3wM!ZUStU+xN$rx{KJk<)r(4aK=6x_#IS%*NRpH6sM!;B zHg_KuCb_&s(wW@mJMKKj|BRTIQ9dpB978c;K2KehnrlU%;&@2w3UskMs~{W4lcEsU zZH$DC;hCa?0+@947#lcVs#$fR1m3OA6>{O>gyic_;?PL?w`nx#9;mwPd;z{273W(N z<3`8ge2eH4=kt}(`O^s@AvO7cP!}h31cD>~mDMzx5M+;NZtg?C0kSViuQTLi z;a^E{J_pMuO7Ue{SZxUy+e(Y6FE;p*EL*RM{&CM@>oqM_Xk~Ju1~(y=3l1ma{eH=E zPFlqO`Z7582himxb-@!?n}<1 zvo|I9S$UspOM0iHXwR4T&!waIvbb6#Zj%nOJD#Q&)sG0@*@$qSPm8xht~mu2EwogGB2vvVG^6;GA3p4r~86*Cvl zu~*GF9v00DE%1pUHY74CFK^aSc$v3h$C`Y%I1<~eobv`e?ll z6TVh4e3N{+@b?MdB!LEgH{S+7%RUu`>&I#ojPgoR;2k7YGs^P>zbd$4(F^3bwp7^D z3B9W7t987mucLWkLOLe2{#Uhn*{d2wJy@3dEKcSMzq~w3VywBAq zqf9m4AxKc(k#sY!Y?qu7C)CHVDl3x-9T^4Sj3&O13(Kx_nct5nq)zppIsp@DHMb5t z$5_pStC*WaFCpqb$g({uj%)i?2V#CdC^#8kHS;?X!q>O~TPlwHFV%wymHWEKRdYgX z8~^Kx7h|^7qTTGdL$N)}!q(6|#%2jVM{u(S1}8)7luarqFVbg=&NAjFbh8rIb?cdH zY{=Y0HA##PZ#6kwv#P+GGGptyyl4zIQ0@tDN&YY{mvnFL ztnK!;q_Zs(g(rVBBx_a8=e;1tix^y|YY0@lg}Rz^G3jUI_^s;-?OyIjt=ZwUYIWC> zjr01rFt!qKS@AsIB{XsDT=ib5W5@AbNf;2@R=>d7B!RJ%t#PY+Sgu zd8EeOEVg=pdu6eUwW?wkTPXUMYH*{!Kyb8UJz@16%GAP2+7-e%(T6Z@r6Bm1^M=!j zklFC8?0?QK*Cl#k!$s*Tjf2vrlJ>CdzhK*dpl4 z#L6OSo#3--S!}+THINroL`_Hwe)YdT(J^04iVk+GnrX2^@a;9YX|Y{!VxY>4+2Y7= z>@FlVsE2EWqrdCuwmcCwnO6!puO_ou{_>E@gEiKRmdR%_Q`w+nGR#pIzvZ7L%*v9p zgfqJjL3SXz=$+O*wu(0HOC%M)sjr&RJuo0uWyuAyFwvJ` zLYNnXv#1Y&01&Q&a94CPiC|JK5S(Wcj*62tgU=UyhjZSP`b_6}f-}oAE1+epPUi|9 z6l`0~uonebnt(`qS>^YfMqZXAYg9dh!Ue6zmWuLeQMT)=CdpD!-Y$4`Mrx8^&v}BM z>`Sf#wZ%guL2_FugUPQ&&Po#g3)2eiha^0Q7QaI=yO<9${2A=qzALop!|cxq)k3b_M|jewSS}dy;BG6e<{d=4+#v z_f+x28%3-is~^lbnm>%fCD~lTd3}BT@>1`B;0J4xSRsq|g;qSPNS@p0NH5p%@cu$k zUX;+y`zJ+tjl5o6yEf}B8hB2%I;$FdR|%^K^q9yf9~0#XQMP-4bePPu1}IlD@2JVV zT{06ZD;ks!i!ygB)+o)HGlTM=%oXL`HOl-yMMh4Evei1X#uZUsAvYZs+?vTeZ-~tM zYLqu3bInsuP!g^7t$Fs>Mq#n=JRL!DskK9_p*qcr?f`339p>FXB zwK{*Yj4L7)4w!>DTqRno5ATdToYc1Wa^SD}FBVNBez9211{&zs7MRzdzFJd0F&psX zs-<)K^#K_cs=|P2PbEXa+D@JOOltRnD(kHDq=eb%UQytA4>YlMSu%tsb_QKhv&ns8GMIyf#Z?BBqrqw;j>Z-X;fDwFMKL3;N!%!K?AZcptjPtioHwJ$Rf_8 z@&^1sZPjG8j_Xu8UVeY%m@9iWiDuGl5*^OK?FfPg75S%Xlx^7L0Oe{T8ZxS-UyxH}myo(OBvD2NS-*=L>(k z>uy5~&J5Kjk#?%8zDviZ2OV2Q887US7mSc|l!V;9if6^_zuM_|;H+eHRp0LtE=_S} zPi3=uXU$wmazsILRfk*pbBR6kc_SQ|`}hTiHRHHS9FNvGt`$eTQ$6=)R*N_G@HVew z!U;M@RAYIw#F~B#nW#r)lcSX)Lbn5ctxvVD-WX`MT|4C3EMB&^e8JV|Y!p6kMXOls zmw)lvlp=GExWql*!>Zx4`}Tu^nV$F6Pe}45oUEp1lAuxkR@9i$)(nXsuDVx}%+~s0 zR&8Bj9A|NkQ-d4FE39%uh)j~h(q?7fu5=jwv4PyIBAK|dr{2IfnRxzip7`1kmbomB z{5sDdP(_BQNVdu~A756jW>(wVUu8j8s~f@3R4NN%D;(~_CWQXi=v-JPIu)r?qJSS4 zh~wf!#VD})-Qm`_mQEV226C^t&n)d!))=JRwff!Ql;@>c&?xVk7Ufv|65Zh`?mn|J zshS1i8R=+um!ro#ds^^AHGDfe=G=d>2Dh_gY!wu2Tj^ehS7$esO&EK!Mgb{^)mU%a z>}~enC0)2nLOYqnGLP>bu+nIcvu>}{IUyNTh^}vu#}_5~Mq#@+uF&z;e(afFRtcWa z`d^jSgOpjJ?i7VR+J;|diQOd^;B*#C)1!5 zY*Nu?uhOv&uRL4n&e-_RqlS$Xtc;M-*ntxnZ#b+>CbS#S$z=DBBsosweGTM46k0R+ zxJOxEnHY6eCZ}xI@y!mC(u?|JU3{;~D$l;Yr*)N8lw(%m>@n7>YX#>W6jd|IXT))~ z!_TI*ufZ4Tiqks5D`9y17VnZe*k2*rs&bAnsXRL*#TK1?M6}FP{X}=#>{K6&@)}8U z+TnKQZ15?;xAb*n)NbjxS{#>356(V9m$~9dMY^hU4tw{fQMjfxHvj93rxdIioT`ge zx#PAv(J}Z!(K%4#xI(?*$DqL$|1Ze_eim>>Qe?&#hABoRU_IPl?xl0^DvBUg=hIx@ zf)SQvTzxHP=OC=*)+N07GQBvn*c70&H8{C^P{+_SN!JT9N~%S|4OwjsXMW$zN+3~+ zm6qwgNpNN$JL3D?7+kP!B?+T~r*_kkRk=|(D}_4>XF;N;nK-R~p>A2p+iO?p=vW_a zcDtrHVT`Sp!8iB{;qTHB{7m0%H&N5j-+mk55_+!j9)P^@{6Csk&3trB^7NHSohCW6 zF7Zh_l4zN?cv=z*RKA142|IK>E%ufvQ@Sb@^I!GUjt!=sko8VV7*kR(bkw1m$&57@ zrDM&QNqEzJzN|ed__}`mFEn7A$Nk7mcdLpgHtbtr`1jm|TLX|nMYUUSK1Y~K|44)c^UqYH*@1Jz^iZ9U5 zD<#)G{z1mrXFKdT@4FTIxg581AKmiLbY%(K#CE#lZ#90%6*|H%-w*x)3;clpOW4XJ z{YJgGgBqeN&q{@$cKGw!dw41Y_q;>d^p0QGF_qxe`aB@3Hh1ax1JANIl)qm4(V`yx zYyf-<4KA=-jcIfm7>S;odMehCgLSjr0@k`PFN53`)~fNhi?#XVwrH(4tKBZG?F{<1 zX#Lm}%J)0#4PvVkzMF3F2Z}Dsl_7ckXJX66vs;l|l$9Z@DIYq8y&bHdAlA3S;A0e0 z3}SWoeh)KP+Xb=P!djQxZ;7u*%v@+~QFvRl)~Va=(pq<|Zx?Gj*SReQCkJmuH5(($ zZll(>F~W7x@OBuSUwSgZ-3niin7Q!tt;*{WtkKwhvUKy4YXoc7Ww&ZEJc2b-2Pn6} z*SgH@SI%y}!AF!7alU^4E{0PT;p;tOZCApEYkik+-}$WSOf$|lS>bS&*>$FAD+4&<8l#UBX19R#xXE=3Sld&Y!+njbZUJkO;5He2+^Y(=KY?!Zt2I-cfCX0zW>j@ zthZ68+IImh?O&<|uD?n#cF(_5?Tg-6fHlU{bG~`$^Ip8<-@kN2DpO_{>ehaJ?#iZP zCaEY^5AsXmhOJWa?A`}>a3@T+Cp@knOkFlj=ho;W#!hApK(Q=q z?gx6?cBnOM03sn84NdyDbQ7f88g4+xs+N4vc*#o)j5XebzG{6$+kxea^x>iAUdv5^ zf7ZzvJ+w#YPRPfe75}W&V0+#RWMObni zPKXc%HcrD4tsz+rzNYwluRcI>M-Y~LfHfO1TjJZTY4E_w;W&Yt*|f%ZEU`e~??_#P zmS~{&!V+Nx`oj`AY+zgl7$YR#CG;n`1JQ&BhC(wabyvK~ED6aR4;nmiGRzUdM`-MRr#?^9=SIRZw?tT|xlN?A zuQ8GokwQu|AuO34p%P)ne%`>NFUNyM;J+@LMPHH4qFJVbzDJ+`)Dau%syClS0p?oA zejT~}XpG{`8&&x2G6c|)=YgUWu?5y_z$o519yq}NG_%B0GfU9#4NH8bNPk80!fi>= z$96d3HYMoq$s$iq)-WU9mjs>Wym48q-_>Ca_gA&Ke?syF5+@HyG|EHm7KWrv-nS(r zAJgH4+Z2+&FQebakkoUU(^|?9qg2NDa6E1sqe?!%B_#8?perPsa|R+!vr0bd_EpKx zD(l)N?%NcS|3k*hLz1Nk29DO{1Zqc)he2mYn}TsFJzi!x_VjAAMtlwlh%wW= zvlrS=*BWEQ#iLcU^SFrX32f1Hm?cmo@TmP^x$AGH$ImfdBqC}Yr}=>$+trWDuj@ra zt;<`(%D#O;*Jgh|acZ1#y`2@K z8pr929ka$tZExhRZypn|pNNk58p9fhlv^WiD4}WGJZy5wtr2*+HD00@jnS~ioA|ZA znnC*Cp!56m{4v&Xrm@hzx$P4kvNMJ?5Gl7t#71a2EK|S*oVai{W)H4jalC&0%};}+HdPi%^>}6&^gt~e*^Xf5F5?s zBY0^8n&R_ebt5bhc)2ycOs{OFVU53|GN>7({|!3ehbGAQvuiUZ;I~x9tHAXyB^>(TB z=lVbh&8ZvF(6-AO#6~pm*avsaD|i^shK(N=u%LwnVr$Uh-(y$;0(o2nLHv%kU6u$u z)CsF3OYoqk8X0njo|2;(r2h@OHwesKzv;w8t~vYh=@WKXejNK_WC;IQ=WE;)Xc86( z5?z+aEdVYgqS|&nUFK{89TG3(V47>tG(=xviLg-fIPhXShBXi=q(t*PLm<;-4XSS5 zpb>F&@Syb&8*92}R)&0Q!W=(Ka*gwS$TW`=>FjF^Yami?4XP*cLE{<9E^DB9j+a}* z-+-PnCB4~8bP~bp3v_;q_?pyp^Q-{}tkTxTum&RK)>tGuM10H4$b$HE#RgdvIBauk9L?&+%I>-WYua?HXkH&;9}U>2#nz6h?=do^X$`7q zo&jCf7?vsbUNaG(J@1aBamth|T`-PFz@nbP%mXzwkI^tL8jz*xi#*+*G8vId8824fHX4YjRHMA zVUAx#6S}@eX&!j_7Hf<+KlzXXAU{9JV*_owtU=sF424y|{e$dR4&T`QD~BJ|aP!sp zmT1d>CaifJ))*r$Sdo9N2S%6HK`yp!c#sIoSrqu}noiaO5){%eeJD>BGQ+K*pYea- z)6de|+k~ITL%tt`yDUL}#6?GJ;8#Ry#zpvfoOLKTu*$9B|7*wAq1>j*aKKdq{lx-v zZE#ct6@`cQp56OcZjD65znT`vt(5mQV*{&%W%M3B&NC3{DUuEG@OjK9%&;_Iq46*n z<6}Pg&EI6CweSBvF;I(R--6CRY59tDJUliMN@fj?b1n1z=*umV#_MaCH5><#5G||` zPbLl1yv;(4k1;QLkrUVEK_P?oGn0T0)`?`Ok=A&GV&j(nnDe>`he(JU z7b>Uhqj_B02;X;E1I=lH$3D1Gfw2S@qtS=8ys>*uEREIl<07{}z7P4_N_k&1F0e{i zCcTN&eud2pi+E@f@eo^J%@}BdF+OJ3wQF_YEw32?(-w55Gd{iXu6a#+KFQdn-C@>n zT*N`Nu*S`(pr0jJ)L=2h8oXyKf7jNC`zO=3M#KnW(8jO^;^fwdD8G@|h%qZyChqAg zpIwuAtP7U>PH4=#&;vCCDot&Ta`*SJn&I=wcgctER)9c+42XtiQ4s?c+Z>PBiuytS zgS=2sGd`{lEynpajIWoct7~M<=>H0v;bDQ;Hb{3K4zoly2+?S0NL-*9fsQqDt#z0h zu&A1WM@PcFhdo=3_wK+76#CS}^a$?vIny;#$FUKefx zYmAw~HtjU!w`02a++@~?I9V}*^-G2FQN>AUozIfvJbVwI=|uh*HQ;#?Ij;e+W`Gr~ zE9yCa%^R98)(8ACUX#M`qw)fibelC2*uR?BCjf^PVjK7zceSViv4(8mk-vy^HaW;N zi5dVZb-&9Rk?Y`qi#32vqYmuR(3dlI#7wEG*?)6Ou6^tevp^#6Un61z2O(1az7noa zU?nJocI@X3jls$Butv-$2eT`AYr3!G@dDLxVk5C`oRI^&$<}}*BB2QlE%T?70>(CP z;GsF6JT}4_zx~^W%^dOV-=;4$gY>^)$y4xePF>@#9UzcfVcfW2Tx1IS9c@bD{B@Qo z#74d*K=Wn`Yvg#~0RP;Z4I4{5Fnhk!py?Y+JWbs%PDkTgqG^RV&PaFej>r~QO^C%l znv)%T5HqyXVXc8je~wqP#$H2D*7$yG(P<5ajhbB(%I&d6%qL_3zVC{SuvXyJtg$gE zV6pKF$rx?1@m!5D^5e$_gl{A+7#DSe{f$)_?Bo|A&!IYu1o=+53~+7M8!Redd!_>vMySNcJDY5zi5epZ~&g#8*qCB)+!P0oIx~QX6td zjCq~vs8}8Au!g$o&F75(PB$bOH%6u8{Pg|$fF4yb<_@e9F#4kf4FB^1k3QhGWU}=H zSA=NvWevl{r!7G-7-IBkrWfJ|Dv`gyfYgkO= zc;JKE^$ZsM-Xb$Bsm5PNFg#)*wn1~$_6A~t>_9}cjCDbi4H^>%IUYE`Pclf2n3!zO z4yGucIXS1#sF=7P&q<#z59Qer=N)K+rd=_CrQ*B;Txc-&fPZkYzSOYBns@6<%^>}6 z(D&(MtcS-%eohL3h=fwk3mo+OQY*K{gkV@9{N81auteY?4!GA2{(tP9f2>{E zb=MsiS!77u#3ZJ5f<5!vIF$uXYs$T0iGfu{xc!oDKR%40>46=wTjAU99`47jj zs-bdPw~WA~4mGVwT=Xgo7;40$nA9K_OmV@e20a?n8f1!7Ibafpx`WO4v-eu(uCwpi z_n!B|W`J4Jx%-@b)?PopYwaKB$Gw-mjKs=U5)cUq*P&DFZq%8L@Qt~@nOJ&UfjKgi zT?7(P zIRbt>s_cOVCK(vXlN_vp&{|%QQ<0ECjwCcfZjAWG3?lwnk}{4g`9_bX{H_mX$#P7*puItdaiO>?aJ=LL-&0WYcRLp_i{jIWsS1h2>q<_fkN5}b>C zYLbxnUw@0ejKnu^Q(cs6nop2m`?u-T!jVAGBSHeRAiVZ#5ROO9s-82>M@joTVXRma z<`K>tp^jgE!J8EeoJUdb>mZLj)+sbIc>&rYK=& zIdZi}UOdLt7AE~x7%R5um~lWwGcT|o36B|5ARjYuk2=mhd{Q4G(0JQ_)Q2e7G@r14 zUfX|2r$+aZac-KS@q#(z?+FP^gYX1&AjShW>Pn){(QrO^Vm(NJ6vR2# zVY}zlj#OGPzL&J#;Vr%II_^R$_L6eNW$$YKbs6(bG80SjB%7B9D{uAkVbPq`^#Y&4hN5M<4i^r+0eZ;(o^$2qB$obY&>U~$MqM8ol^53jnsOrMg^!*- zYew%}C3T$lk&}Ih`kv20KqD{Y-!w?z0cJsXLJtu*Y1E{wArV(u@Ok?MAhFP2ftcWQ1{t$mh zMUSz9_bm8zF$hoajClL~iy9J~k9>$={(-;8yB4tjs=+IKNIf z=plHDO2&X18k~!K@WcC~?1<7FA~{g5X+A;1w-w{p7Oi)>5#sqk*_V2Znux+I2v5ih zw%Gr5*dq8iANgRQzUO;csLU6G3(JX!!Xrk)M?)|1t|UhSG@K6}>K#>b!l`Hv3wOGH zKGpX}qV(KRiQ-EhKi6Zd_`|YmjhT-pcowOKM4ko*oQP<~irHKb8YAv!0o3nmTSyOy zp8CF*ZcKUX^*zwQBm*PG)mPsxVj*bw*wW+oaOfSMm1^GiUQRS>NZ?KnG%zXN#c>q8 ztfArOy#!H5!|TSZIZ3aDjv1x59G7*jzASs7fk`npCJGrfG`f0%_r<+_%EfJjK<&4KArbR zw8fX_xFN92Uu&C{$X8`~*N|2Ff|r^!opK=^ly(HYyxmH@5ng|n%mEb$fc-WK$AIjh zbL>PNpy%;sP*UIXB9W(s`9<~7L3r1SW&aOsyv>8@uxg!Z(K5$>y>$Q8CC0yH-eCTO^qHKKtp77eFekW| zqjG|riF}y603?1xXun7sThP}g=0`9l5QMi^RHy3jvCLxvld!U@855${L2KGwX4Onb zym#k-$4)qIITAZ!X=d$s5yO#pLOLQtPOTGi-Z!7Z;5}-#j2VueQuD?9LUlyJ_f2Ce zYD1JG@sp9cz0Y@iNJ|J$=vZ;ktsy}NjeN-1Ycd>;wEU?LNxv!f4{Phni&Pyy!jMF@ zqfqlaHuZf+!;d>kzR?iTATNCSfxU)?Ph-ABao(dx*|TZtQ-VyCYno5gu`Tp&90J^X zM}xXP)B_2`L?nncnNK}AQbWRfhx1Xw+jGH=%Fib?dDRrh3PiQ&@#F+5BN80PDX4}7 ze4yb|702-AKW!(cKN6k?Wf?>_ITP#H_na6pR!qpQhy)WhNcbJL z8WQkCK4j1~@gLQWXvA2-)OAbSVtYtL166&<(HOzY_e4uHh&7&$TE2KrI3FrN;_KwP z2qfOFyNOV)X+BYRLha9{Qwz(BMu>JCkyuyT2MK6IUYykFcNr9TvXrMfKDP9{bN@q9 zyC3t$+?`D<9peS{pwX9lQE-xm8fhP()^({2rkk`ED{7k(~{7kro z-uk|mZ4JXmJVEBuK9P$MIp1p)7*OwWMQOGO;4O!Tt8X7Go9Yi$z zT#ww?n0Oc0Q)r6!qYy~q?PC#W`1`poriR8c<%UvY(LDtdA2Aw!rS%pX%OJYC+hYXXAiLgciGe2|!I}ZW6Y5H$j&qR@5x&-VXcw)Z z@wWP}#NAPo4<_0D(SY3%@G^<$@zEnM`0cCsPG-E1v6#F#YG#3i-O%aE3&8skvAl_T z2!>l)qzvcUgw+!<9+el~i=0pF3+W-K`~YnhcwOST;AIlg&gZ;GkFuAMIQl7Ys3HMaZ{ps;3`y@`W50%k^Ee;g!+Vq+ zQI8RmI4uSVT6tcu--i~F6U4Y21xr&ebTR zK5~Wif_m&~daVdg$b(4Kl|-G7jD8Lg6WTaeyJ9yrG-3A#gvLMD)*~;L{hO26z`E1d zp7za2Ou{s_h=!v=9iyX)2C1$(+LKe9`@$FWVKm~KlRv07m-?YG^vy}6FJ~{YZ%*>n z@UJT65sxRVH|YT!Q&LwFb+LyyKYT}kPQ-Ze$+VYcftC@wKdCm~m5#^GA+5ZiN$eSM z-_JQp@m$$UI`ZPI+P_n_VICg(-QUIJ1#OYh^WRTU$+n{3Dy#Xw4_ZVopdA zxk<}`h9g+}zmKeONbN$==<+^@ZhDU+;^#)?hVeWKG;05*X$J@+{?dPKlCIK_l?;7jM_2C_Q;FY2pVIJxUS=}4!)Qd z9CwVMv#RFzyD<+BJ+@v_*LP;64g9qcw8)E3O6SdfXteS|8d~E5$9#m zDeF&6dg`fc7(tKMB%p1??lGw(trnUWh=_5I`+kl(->8FPUX(q>R$QMK+bY?Hc}vZU zMa--lF!K@3tVwkEh-gq9dx^1uf^VR)lywH<3sjp~i(Ya}dVi~5Zal7D^2cP(gV0Op z_kLB5XCPD(bv}AhMmlsTACZ1!GKNrgqjdm|d#<^LP-b)m-CZRnC z#?{fD9D#q|K7ANXa3MQPQEd-27B#bu8bPrrqJcf4XcnGul?E+#W~J>l^4}1R|3%n9 zoYnq>bYD+wZ<-a?UYWxWZQzCH1~F!1eL-DG)H#pyInPr+t45+UX5`%fLgMlOFV>1xN7^pbK$?Py~ul92GHMf3_r(NReF6?|SSWF(K8{2oXw^mqP|>FbMeNH`zv@oWYD`y`48G**2rfzgEqw_9_^TG&{D=o%87t5J`<;QvbBVX<>G z$OlB?R1FPyA|L$l{-f|z`PuqYWx&g^S{M=@cSi%YeW(W#h`}rfPw<{O0U~HMBz*pG zK1z5Eh?EoYo+syxP{%@TG2at-#7Ox15l>i8fQHArh6Lv$pPD2jZr^4v_l~vi6_Y5} zG@l^xPF4TGRMS5vA_^|d>-@M@_82RklU;YMy(1CD)sS%XoEP`Tt-hUCCG20*_UQyv ze>7Z#_l~|u(5^=h`3DN{yDWC@Il19+_c}L&((B-HKCkzmhhfxw8y}+BR{J2qwwO^f zqOiZJSgqz@q`0=>1NAEyH%!#g%uvFu@0}AmR^*N-2{TJ14F}(xPj}QsW zLPbP^W4xuVBMBx$S1ZF`I3HP*ygwHR|=k338Cy7cU=DY3Z z?Q>1@iMB6mdp^}Hym!!SAt=D#bDa1^eKihtM}mE)8WP^4oR1RT+TFas2NG<5WRc^9 zi&_X8J&|zHc;c(=Sm*m*!nX`a{7RDdrpk%v;iE#LluJ@DV?Q(f>I*NvF!S=OFMjmn zFFp74w&!1caoaQRu@kSn{NgJ*!|9hl{^GOTMfl6w+SDZ(4rcJTI30l+O8cClDQlen zsyCj)y`(1d1C3VSsd17oZF-AyfQO^w<>1Vl6D9s_y-hVcnSJ|l4$odSnZLI!P)9Y+ zulLse<=&iP?C@yg|9JS&`wb;4*Jf;d`h|~an0)2s%D4zWKhN8azDv`IM4Sc9KZF4y zt5$*cY~F&B?bo!uB~u_Ia&-LoEj(+vG@-7z);bwKF7RG$O)ft(^XfC(Ufwn$op%aZ z?nL+xI%L30`04H}(Hp_jue|i}N(UiSZ2T;Q3ZqgY>&AC#Yb3t#($ixEx~N>10_jsN z-(Q*@=Q}o(Vuov22(<=?>5shl>KOmqT^@r=Jw)tVv<>{9e(BknUE8LgfA-aF&pb2p z>`O1bI`iyDMvp_K&^)r7{OZGpul+uh<{xU}tM`o>$sCalKd&*1R}tF7JJ6n%&{ILE zs`LwxgJG28tbVtuCut(WK(KgGrC;DuKa7WWaL)ZVwV=#|sC)l&pb435+(Dw%fZ$|v zSooDHIM%h~sbXjl&cA0hXbDdy z8uo~3WRC^J?d1Qo-=S?l$ULljjV{yeJgIu()aIO$n%x#nZ^2ZBlmYn}uZbT0&XCMG zsqq%rS@&p8E;%QqL_NIgN}3W|__pdPd!Fenu+#T5bNeXA9Mm}59)*y3DCE*;JJ0sE z^MLF;yv%lt|K|`yrVJ)v-5O=SC(z|B$$becz)@KF)=O$YuU`J`A6n;SY6uP3$uNQcE)p zu=9>!z817o|B^V{t8`?}iIWmS_BUy3mi|vazwOnhx6RCaoC|<&uUu?Rs0F`un*Vc0 z2Z@l0B_{iOSvuBbf4CwWw0@=ynaO=!-qz<`?pDE zKji;Pr*^JRHfNX{?c1e&IJ0+&%Mo$yAC%1Yl~v96pX$^;D?Be`pZB5Ec1qtcbRVIPm6O{<|!c*IZj zlPlt3PG)~z$cNm{U($ZtBhK(1ekt>hdImd<9niABR@*>kG!i2u0izi1iu=#1LmFhAWRP+y8ihh*!t+3hm< zS1R@gga&S3L{84O{iX&^7JCOQaa<0ZZEiSEDn=))+BttiUi!XRMD3$?j3l6lI}eJE z2br|yus`y{GOtSJ*+M3AmxBC*;3u-!x^syUY~xrwX+IzG)BF3ALI~1nBdornn&}`D zj^9+hIT<+1B@?IMqJ^=kKqlKwtHK%x&S9A>db&JHO_~p6TQ7k+m^sCs!x5?H5}cPdKr_w5QwZ$lBc&Xk1}! z^F>wJgyKfesxw-(yDp*^gfRYd7KBbcfKrf_t{sO~!$iW=XiI3(*{H_%OP#*6>gQGsR-8np({1^u3 z2ZYQ`8g87E60O{zY7?Al-r|H~h%sx|nJ5!ZKW0A@GIwh8Gj1ne#5WczlAVFm?fhDs zO-FE^QD1kNUUu8LzwjM#6;7SG$7xZNIo#iQh;vHoo5<<*rsnAbJGtI+SzhvOO>k~= z9#VcghnN0s#y00E4cE@$<(CI6wug2$=kT)I_c$NbId{nCIrX@xj2EfxE#K$T7r4?( z-_Px|TaM4|Y<;tfTaMuWwznlaFpyy|5&{eQ|BKDXT?e57M37n9cyOJCvSAy9XC&L8 zEo?r0d2J)jD{?lm4vh2`TSP5#^SLJw(fx=XA`W9isKTG!CjVH=Ca9@4n> ziBz$T%b6b1{9&L=tVrX*1k#+X64RSn12_xiH)^wobT+rzcdBaB>x+ZFNc)(~97BA0 zgsn+teNXG@=fAHzi`(Klq~j|9aWS;J4RO+i&0T24~B@r=Ne}=}H#Jznp$p@_FL9FqS9cS8ny^PI-;;rO_;YPjJXm8 zzK9j6V%w2I+Tv{kGq-JrX|CAjbG-+xV%r@_;Zd$jTfA+=^nkW0fpVs_&5l)&A)D=R zh67QPz4?$&&Ugy?h>Qyb;*pJJP;?>JG+Angsptqj()J1r&fmAY5~L?{N;CYw^zoff ze^hf`wO136V5j*=WkVaZM}QikY0MtE3??0Q(dr_=X2MMMA(w8ONB0ILlzRqvQ(!EN z;t-TCYP)au$Rdn32#|g(4p*t4?lN()+gcUUHrc)_ucY6+*ybeBrA4KxMo3|5lG_nG z2jrTX`JLG~j-_^4TDhnm0SI?*Z;l3JUM%Yc$fRkg0OF^|0CGiAQ0nYU17uo~%&b&Y z0J$l)h}$|bHz}0c69uZV&A#KYBKF6SAy>q*uK4L*{hqhFF#d zkR6hQw}&mJ5s)y`5z`}bVJn7-Vut7xRk*N)oj@^IR!x^VuO>03F++mV-PXi21l!UA zYY;+|&T5O&Q0g~UgKes9(TFY+r4eJp#+##b+7GOZp|>j77(n`MnEFqtD!PDDjDaMS!VlSZssM7(nmAj`5UWEPG40W1NOElRuR%xL z0wAZva;X5MqstsN1MZoPl`eB!Y|GbW4oewb#$AXR60(<=&IK2ur)Dm=?KKy?h#6va zPpCYmCcrysb(JoIr_dNcz-{>eIWD^ZWc}zdgqY43fOsD26lQaHkexskKuF6TfSfW( zW4g?Ku`OShIb-g)7coPu4o`_`>I+sEGbFGPEIhTU)^aX%nf+qHOMk~JW=N1WYx{R? zIae7}cZ+Ra(tN-t3X309&j<6-UjgL4*tnl{86HstB=jsg;1+FHGgk``Ra48TxKq|POm!8iX zg0EW}Twu|_qSpS1iZiRVLEDWDc+ z%{DF{a3idz>Fs>F1iTJBb$ z)>&gbZscfRgtR+pZ}1Uuvs&0Z3eLEA-0&1H_b6iLv>`Eu-ZY@}luUmbUxdBRy@5gAHdGLb0wyCP0m`w zt>WobN#g4nu61dig4=5ng>A#RoZG`)%XXlXSol@0sa|UU5g}h zc2fJNbjs6`zJLpFXfs0T+5*ePX9&_fxzCw~4JxS*1j{bj#=YI^R*ws+DsS53X(U{r z+Y~N1l+KC^Uy(FFR$17P&UDPqU2N;cjD4~&ed+_Y>(a^%W$x`#|D?9oQ>c6c?fDnB zRc^B9j@zJ*OlB;fQFXWi^!`iR5l4@o|M7RAE9hNAgve*G%7Amft)MoEWLbkxV!`eH zK)B!u;4yhDvA7~_YvslRGv-N^9q`)OrWnB6L>BW8Xyab-c4HjC+X~j4o%Xq=0`FR} z#aE!{`;D9|!f|7W*kMvDGndEGxRx-=p_JdYW6d>f;s&Yi@;f^YxTRIxphq}vSAw(( zZZ{j*d8dNgT}fh|_ODP@aPx_6!lYJkyDLxOSl#j5#99JKNtGc2yLL$8W5ta}KiId% zUazg-He<7CB z^6j|ccFCS0R&e9G@}@A`ZA-@yxbY5gR#{z3gO_6l>(X%}(cROf;dWV)==F!KPc*pc z70Yn>>EA@XZ0jB}B&{FhyZxa!!CGZf&RFCY?!-9C$JbRpcJ5NC_x;9%w^X=36&fq$Eb>@AdH z^^|ZsE>9iiCJF-`v^putTePh;4UMO5w!u-}!&6oxfsi&;7=ovde5G_*WA0fg@)i1% z+F$(aj0b%E;-ZZi^wazvVl#-qB95ky>acdrd&{zSr8SPBrM{pR8cPFcM26VcG!k1SL(Zp@gO5sv;OQl$od3;l&Byqyr;24_F)_SRQ@Dq8@ z?fmxcH*Y?nHohpIQcq(wGCxBgmsK2dMf7@>eQ~<#a z0PwM(lB}$AFzT?CmEP;!5mty!RM-Y?-ZT86LdU4r1#g`2kS@Y>#`lBrG!Bj^Ekb|U zOh0D^p_C=I;{Qys?3s4$FReLsjS1PyIJ_=`uwJM8Jf$C&c!^dVQrkZxS1{ zCl_5;hSz}H$~!-eI$X>&;S|#*%q~MgK`Fq<^7_;kLp*k-56EcL6ROm!$YSsnW9!lSmRfZAwQB4s&v0%Ghwhys?_pW$uZEW54X^ zhyodMLu{9^&)QbTx65L?DYnfvs8--TWK#V5P!$)BNE%O){mV2J7Y-W6bEdSzg#|?6 zhBEh}dc5DW8j(mWfbN?s6;Geg>2-2r(x9(+x>szo>I){UHaMJ=q}B2=-u`&xg9ANl zwYD8*TxD>;wq4pT8XKOHId9mp3Zih{4h3EEwh~i~e(7QJh;M5wAf}`x&1PXUyhG6fWsB&oDOIv|Dk3c8RiZbz^$aXMzV8Y zHYt2r5}dQTO1`n^zirDXI7fJTS|g?ZKy}5__{<$?6;FMLfdyKcr?-{8llLAzykk*l zJe9rSp7LHB=zZX7JXJpnk6|vzIF`rRvg%{MT_(*RPEc;#WT1*f z6{W1*_Q_lSBO#&Z!i)rbX-7jZ;%&#oD~-y`5K9#aE-t?Xj<{K_#8)bBW^9#U?UTeK3f76yJ?n^|W&P%ZL?u{9ByCn~DiYO#RYalU!knTo zA!!%G;Ls7QnL^s~25Y?>!COXNBlPi7$$DMwUb4C;Ri;aad?SI{!Yrx=Z+8taB6AOD z17c5d6zWjd&KA8aZCceVFpjH)@N{vv(@}a!l336lLzD=ms57*w!iAGcqO0K6*KbzZ86EI4}{V++HR=XCabSx2t(jLlMZJk$*=3wlr~_7z^wr` z)g+IwYb#HMVcnamQ>1mopkc1nBOtVDfSO<1vWzV$fu+oQbOmsU|8cq@u!QN zxh&hbsXl9Lm2Nm8R&LSzE76s#n-tr$B;HgBHCdMr`9#m0w*8v9{Fm=5a}Df~NF=Zf zb!K&_iSK7LoLy{BnY3_@T}HV`6FSIGK$;V<6$4-TzwL%0w}*vv+^=n2$hV&vc7e6@ zU1f+zp^|U6v)~nzVOA}ax@{*|7#MpcSZAbkt2UR~1WO{r5OGaXE=ijI4-!MfBk%S5 zWWy@icFSC-^!jPw726hL!>%v~QVSqVN33o3P$8Tm(J(VbVRxr#)UemXA&o<#6fY@-+P&yPF8111fgjdZodHq!EfRsy>? z5LJ|>VNka1HMWXU;5{UXYpgFc`Icm-4+Jo1@t>`JU0E3%F!zwsa(i&0qc1Rh`0u=- zqT<3OnLk+!(H+u|5UJy?2w|VswlQ2XlW*Y=33$q#av=79nyT0aytm}3vsK{bvXg(K z8gm6bA-31`G*CsNiqiG6>#7j&e+#Mvsg!E#-jKZmN= zc1&Wv39HfixC*1dM8Egl*V3WSi;&Zr60UOVZ-f zk?_BvEqhQp&WRO^Ukzf@7Aa)FU!P><1qL`W=m*=t4Nq?vTN6``7Zg*Ju9PHJHCs&@ z!9qx(ltg0sxNB@nQ~HD?agW8*Qv<&wfaU)Wt1JVcli+iw>Z@!=n7mRd1 zPCMbLFKF!)`BqZwGIp+u?Mad!$e%i1v2ZLcLl_2+Xgg#cS2D!=fL}l@P3cA{d`%m(4OCHj zE}v~aD`_d%T8UIi%PGmZ)5xl(B{vZRS6ci$(zJX++KB0c`|WEPzx5Zoj5u1hkwl*S zc8bG01slP#@MPJRO!R6;E%f$t7!sanUx8MYzCqeS|pL zmY6czg!bJos-tbjhHZNgDLQFuyJ(x)0>@st@F2W@6>STE91`oSW^G^4R&2wC_*dZ_ zwylvQmh3ykdR6;Sv@O>pKuF7#+E!VFqHP5m6OvDD72DQ|1*O-lX@_m#Mk2*zVhl-- z4=^I97`Sn_{JwCz7vN3zYGBFs!uC2JqWN63LN7(s!r?=+an&vaZdj9@R(7~x`dm;d zD^nYNfKKSNK|4ir06C#)?R8TKD^ajpkMTb3W;KoDNQ^@8loz}iB%GoPmTxHamkfEu z4T>2Or0t*s%DxAgE8*rYgzTkP@tqaps&yHzO&M-Z8y}vkRnts|2q%O0sM@nPda6?p zY=AMT?Odv<_EQp^cXbXLTP5EntPdF1;Bl3#>sU%{GWJTB;o0JKZCx$|+-^!6UB;Eh zU|BVumNX*Y_`g~I^NI~>S2Rx@P1Jz&IFwf4CG1Fnq6@huwIbh;<_{y9mFgfih49oE7Z$%#<(>l*k`IU2hP2}MZTa@X zso*IwZ7w{M8KvW?65EOkPvA{!5S3A>6qG+7Jfpfe3_cb>&I3qcTL&OqSr){UPRmL|~GpsGQ8(U?3W1gqW956OqFmJ3T zjc@D4vR{$7ZRc8pL+<(XdS9}i7CX(c4Ht^$1*+J#rZA+#w%Smm1z00p z3b28z@MBt^Y!54k4tQCZF%cawwg|5YMd^NRM>Ha-NK|oQznX9fd&Z=7xPT4YwH*x7 z;;NN`IY}m%@JoiJAqcj4fL!`lqG!=;|N?~JjswgFB{qSf_2hUI7Gi zuSwjbu~lqi{c$m{Rcynq*Yx2oRBSt0^m>#6R3HwqZMQbBt|*-p-#JM8)u*Ej5W>s}WinkhbGkpviqi5bcJ!#bd0@5fo zGIRVel_&+vP}#+{LFaRQ!^z>KHn8LWSds9QHl!6_3}4N;Kois6ip~r>Sq;$KnRzmMn+FoOep|>gt8KM~a5p0zxVAG7Y zy%xtx6zI;8CUmg)C|pq#n0iS82tYok<8Tp$r}r!^efoGTfMC<RU17wE*T*;8t)**ZpdMp`2sILWYD;Y8$Sny(L z8G?tb9t@9kcco+Cf`#h^X9E!HMP3DDRFmjVmHG6BB%KS=D&yNa1&c9cr-`eKZ|jO+ zJ(leC%$PAZI)cSS$?`M83qbsg(gSlz1=de%n;lfu7G}bui2&Rc-0o-?gw@Bl3T~SW zH&!42ok7=dXyG>q#8`1)q^`R!e4zai-N6|%a zlWk{BCNAi(eEEFFG@sHbI4drgkfvDL^0*OWJA-^{&R~}J0k53U&f?#<^so`i~Db|@p3Fr|DA1vc8cbBdQB|r>?sPY;AXcU zID}~BKc|u^^ic^Gzm>Atu5@9o1nV`~#@ygkN%EWW`eKNE#Lb#w+i`tt9k29~(&3Jz z?X%t$m4+x_7dM)nDoXbWx2e&=!tz6sG_PkOr_8>}oQ2XeVM-wiG=D=|uuVrTiWkL} zA+)0Pl0oHNHIeyfUtCr5~FQqFQ=c7 zw2fhK=!hw7Y#Xf^MMWCD>Y}*>TZgp&4FCZD|9Am>lv_v?Q5eUMx6-_>*Uc_!mWr*` zi)HJk?&a+4(YdTMv+5EtM1}~lP3hVoF%f zBl)0nV%F^zY;&gc7E?{Ct6td(dKD%|twBbIw&B_6%JWxSpQXc_&u%BVkmqXmgKOff zD`VbFXR+{n6gaLNtlL^3Q{gC3fYslBH12`KXig!oK=N9euaEl89i#=6YeS1Cc>*2| zejl9knwny%)RdWF7Lpd&eHwT+EGS{IP6bnxmMOP@kP=%7m_)K-(hFN%1z(GPz{;ig zGI7Jhg ztAdLGNp`z~nobSVGZve2L3BH?u(h)G8S#9zK=Q)EL%L-$nOX)lO{PjPB0;U3)N@7q z!;kQKCZ|T+?#Zc%vDjz@+Lj6w!;k6MIH$OT=x87qhISYc z*{s^6!lwxiSCdY-Sh{ig6D)X`=ePUFTTp|IU1;m+%K)fafI88v_Y?7p0!VSf$IKw3 za$qMy9EgJjsWm1YZLKAT;r`shc&pQPOIQJnZ3Mi4yU>cpzs((8pu?q7FfHL1V7t+W z`Qcyhcvg;8Lf8+6Gw#<^6~=ZCxeGTgFMsccg{(t}AxVraJmOyR2DUqvHm>);nyQ6} zX+%_b$t|YUkyQW=yaK*q|;#LC1%CgyH!XGX@w%|gb)%gn~c z%*MjXOQ!mROy1hfoJ`Wp+U=_^^7#Km_b(Y+%|jA5Sv@>%sV7b{Rb5Tu_Ottp?)B#? zyF2OT`+-XNz5hY5z{|h7N0)Kd)5(73Vx^CtIJn0Y`U|wWY^O;xl`pH+td)tw@&+l^ z+IKeT1@ugsq^d`*ruFXp=LZoBwuzB*jz@;={Iz7Ocj4d+I#b!OpT6bC0*eq(Qkji+-i$pQ|@6HQJAr@QCXp)d?( zj0&9p?db&+u^zyyX1=5zfxnh*@+xSuw@-wsf*UdY(Yy6+OckBmr(5v6h)arF>Mo8U z+z+ysSNWlDiWK}_dJ1ee$^@Qsm8-@MmZyw)@GiU0?~U}A%1u$Y>(@_H;_2fO$gPz$ zI83OPg3=G30v_Ev&V;H8!h9>)Wy{aS7O2kuj8&)-=-J0O|T*FRod1t1$wL!gFTaqAYOIL)* ztjZusRBWTjQzebm@4WPaW~)MWuYc%ACYZt=Z{Hq#P0&q58f zGT!N|w8#zh7Jw^OCClw!4=;dE8 zD`|1Pl15hQGaH+;iVc2$jWv_dCX+iU>ALPzf!u|i27+UX%Efp;y}%-)yXKh3xH+Mm zJ-xLHgVrsaV-`-SoX_%~`u#TiW_;##y;TlA?|(-&xEVG2X0>KI(eCCNg*w&TKkh#1 z|4!q3y>$Cr4BXm|9(42Mo$?pJJr036n@}8y;kcRkeHl7L?@Gn z9sH_PKpDHcDVQfYE*Nw$S^1UZZYFCd{Y&eq&_N~!V7CqXlA`+q)j2CC8U#KnYW({B zSdF(Ni}}-Gh3WQV>sB^1D%BncJbuaP)T_~AlQn#j5S(_z!lg&Y~RxTd>79rqi zUixjD}yeY$7tn*C|_tMgXobC5fFqMhnPHYTjG&^oHo z)ss=S3D&DOSj(;HT+6*F$}Xj&aMN=8YFU^<_`dfFZ(I5GDk7JL4to5<$lqxy{=g=c zE9I|XnlSV_D`3^66CIeIM?XdcVw zq6hQ#Yu!=|p9cwJoowJaSb}6lyDnm6vY0u<%TLifbI?B9w=SvBPfjrOFu(t8jlv^} zHYBcb#BXrlkyiK z;e6CuplJVNis|;mmX|0)f)~g3NP(T#2>D0@lK7*PC^qn3e_~hQz-#;+icXZxkLsEb z#crb_sJzer&!xNxMYSB}Yr|+t7mhcTd0#?HY~_0jY-%y{n$qIP;0GJ~Qo@4QiDL<0 zeQY5ESEN#ST&cwej=^pMQ1SfS08EBRE>{9ZPMp6^?NGf~!r?_$FV$sQxUf~g?twe&bzf%P!yPjV6!%(V&HD^4DGALaJX9Qwt zcE5GSf|P#{{Xj|_Nu~`m{Z{vFzrb5Eb+vH4h{?rEPkNfIWN=Uwo!6Qxm1QNa3E?EH zUB$xP5uM@Ey%F{1>uqG2*0vS zo&DUVnP@=!M|LWL|2HF9-+|Ah%h(<%kPz}JUFnC^=Sk)h?;-aQb4E<=pI5@mi-}LZ zL+-VOw_|(mk9@#O)^fh^O)h^o!M@yE&rvgTuXv|;wfqyUq=6TAy)fy2_}bT#|@Ae zS(6_)=_{199D9`X&=yz>@Ko{*ySrmld?Nr#Zd=U515b7{7Z9%n+?K^ox!&Y$I(yp+H0AFnbo5W{kb5JkLn>e zh>2A%j6@cr1tYg;r5L@q(e+w1N1g6*&i~4=M0q)ZN*ja|2Vy+f-wIf1{PN@kGjBf| z3%};hoqudm)pCe>oyoU2w`ldcZf2AU_5Y>{^TjUsL|?j~k~?D(U~M@jI9s#v8UuJn zQHp%m^#^A-yvuPU*8Ve!yUqi9HXqKm^}#Uv=aQdWV8ukEWTz>MQfN`U+v1Y$J!ft=XR!iMV!ypZM8uPr46MGQ?VRi`~8f0td z@(5Xe`|_T$ds4%enUbW8R~ znRaM7X3wi{+?l7C-j4OaF$yVR-82=U@FlD0k7LVS+HUyY?Pb|?puxoj=fTp3KW*)D z)Cy+|6I`|gGIc@;Vkjl72jFIB*>skmo8$1{YqCd&{)-Om^f&%=$TApf^pcsMkKuK1 zT5;O>!};2muxxd>m;Hp>qIf(JJXQi%AAa=AJnzb3NwQw zbugbO0iR>)5Eyj%=tL)K*6quN_%qRY2xRq;1mA7i)EQ>B5Z5?rcR>p2{GytR(Yik) zs8dss-b5@;FP!anl6H&R(8bfyFI)ijZr&DP_^`_gmPe&QyFX9@@Q*(P@)t!8Vxxz6 zDNOB7jWnwrR$jvt6`?_^(*vXf!t$NmzfmuhsxpO`F#vqAzn^$hxE~`v%GC*{g6;oMO?AhW5(0M!ZwBcZbB}&wlaXN#$@L+5q z`P5T(Wf!Gzu}QfaEKvE;gx{f9ISnN;k;o{NTO$}uF4&=2E0t9YGE;V@R6Z!aQB*I4 zLW~(qrMFt8!=IuW(u-Lg(fn->D01M>(>X>lUpy?CSON8SJ@c>qpAY2+qq2-(FH`v@ zk2|(7IFr_Jn8!QWg(ZBDyie0j#=v%CjRw5Loz7uSbioj@&QP$|JOVm(1R@^wDgcVF ztR9tb6&WR@h&UFF{RkOK8D_!_=1$^(3JV_*roEwgw||yo%~=K}|DxvO=Aa72$J&}_ zt?>h6vLhX8!Yyi%R`}+WZX-9+cXq-y|%Z>HN!sm%O<2W_axImXWfeCxA%4 z8#hQLtZW}@n}q&TQo`MP)L5riX=$GK0g9{-AiClw7<{SE zZ~rRtE>_!3p`eQ3F_{QG*o`dbo<#Oc?y>Z#%!A1z1s97uYTgF##4HELJw3ciLOm^S z2Ssg|rc4Np9%)F89=R_leL?jLnqSa`)Mzoxp1!T23{)G@3F?C0E=p9-VU3B&wyiax zk?&q#-r4AMo=PX?LHP48TBMds6N*2SOVa81)S*u!Mr(399kWH8Eu#?`+_pK7Riyzs z#&`;cBa~Bj7H`>3)KrUDH2CL^SyKM)2Y3V5yF9w7{F8Mw>t-SAup3|)Z=nnSi(&r7 zNMw}?BSkMpgoi|ANIAEWcp&1?w-^^q$?&gGTYc(-|okE@D*1N+JvB zEppIbhno>G4xEuN!XX#ANDfr}K@tmDU{rlF95S^UE=?^?`NL+oRV_`6K&qn)?KP)t zr~CB>uf-|GXtC9=T_<;0_rZ~I1I-yhz|iXf)2LW6KRC@c1M(j^!4^#~UlyJ&hXpVa zaH!6**45L}kKMpSPEv{v!wR=w4}^iqz!+CQ2;TU2KZ7pOnPVC#6JjF_QhY>UWxc39 zh+9AQ67$6cX;W3V!NmR6Iar)FSCRU+P7tkS%ap4UDMeLQHRF?xwFT6#{W$W!!_hbF zw?{`DOy#fKm86CZLdI5=$1x-3FM~ zcvv+ndz^-bjv28q;VV{%%?g`u*t-?R6RYXp2YOB8H1 z-Xs#c*y7W(1qIw2hlfUJ(km@aPY<31V8;%l;yiN%;`}$T5+&id1{HO2WaG zpwDjMV@DgOdV(Ljg;KysAj+jSab2*#t?+mbq!Vg-y%Q3g$0#tVBs1)bq$jUE(=S&& z2<4Vc%A3liLwcK8go9TL2ncfM&zWW0F`Rgblf!c3+{$x(p%d zBf4^XKHMwIr*!;#%N!VVWX`M1^ zX3b39vM(4_#9}i_Sr>%@4_v3^7zkf8qFqNfwAL;*gn6`_eP-H1d9^wew=dihg59r9 zGqd?MV9z@jxbKkn$Yeo$TF1HFylwW-vwdrRuSZuRl;0JKn0WjeT#X028Cu7B6Gpr_ zPnYU7g4*%R#*a|^!pM!#DImn)P9_mg#u3vpaaov|jrfHhV-yZMd9JG4l%4#zWtW#DOMpeVMhQ@PyM zZ}ye9Y9aGvhuT=Y+O-eAtKO<%XJR!DBk9Ejb5E&V%RrUz?dxR{IPoc|$tqrOC;H9X zm2tPvOj)2T7pa=&6f6c3a1CEYRNGtC?qy8agDIK)xu6`7?OHgc_eM?u<*ydik3OkFhcDAaof{1bEyNt!azcIfQR({tUQW#%@U`oWM_pul zIomC%5Bznh-r0uqh=2lVlJA3B5ra}W>Ykx>B4lXOw}#+Y1hm1zeK`_J14y(=06p4s z6QwvD)Xnj%d}vDRio9^YGp_MdYPjt;o*r7vX8NRkpoCWP7V!<(lhP&+b~_sm3MSo= z|E^(zXYX-?Hl!=85O{<&tghSqs6hqdtJSo z{CcW|69Eh5+heEEUiNgyKTT;)Ij}rn zLg#fKHR`uDrY<;BCm-p8-_{JDVkRF${kYf(&W*<5Y{!T=h49N`pP}gu9G|diTm>4D z6Pi}(wfU#LX(XbWpPmR&tw4ess9J-?ZJJ%)k-1*zYE^rSQ2Y z91D5ZPT`?Pg=G{fXj9^n+kden?pWPUtw?B@lsMzOuW+a$)Tc)D-Zap(Zix43Ts(IY z#^xS(l#?Jw7vCi4yip2Db0U0a9Y)dcDg9GnJvHSQpR|CiJq^L^>KNyDVI4>ASzL4f z=H^KMp;?g(qvINuruV#AQ=R`v)Xr%@K)C#>FA_5;<+SSr&YSy!?M1n zxht3oD#cFNcvL=c>?d;FMhX8OR1sh@&MMzkI3-8h=%r)9;X@ceUW|4~KN z%xX{l)VwCiLfos?85!&;#B<;ZoP1JS$6KAkP~ED1(mH_981=f5rFaO~6z`0^HZe*r z{z`rL)5C_EXatXR+v?ulOJeUjpaWpIbK1U#rCk7o=tF%kM**ghwr~FlOC|r+8i@eN=n3!=1N9VVr1W}NUl1G zOq(<9X){Usc711~{0+d#k`Khf$VTsH)TK;dCy%S5+-pe}_ZHJbv!tSNrNl2lWa9pS zaBvxxB=DYQ3`=CMi;+z(7hW@FAUkf@7n21ENKHG93S%@70y5-|eDv7pxc|t67siNZ zWhJnd61g}-;-e=7Aka+6{5TW{&WQgKB?V_E8)A8kge60jOD+mcwL9I=%-#!;rUp0D z{BM7c+j1H{CKrRxzt!c8$e)`m2@pp zo!59jW}-*cxyh&EcKpFD;xnL zU#tn~(iT2!L-T4b$&z=j(cRUdnuo>~1lY;8N3i8#Cm>~j$ zJlfN~SbW|kNNx?}2}8m@L&W`%nuybO{Y~8 zUR-8-VnNq=KyEQ_R)5s9(u7dGmQFNl7ErzKvbV+&k4qhNrYy?@Wiz`w#hoRjmwdOd zrT1X2_9w;WXAE8h`A29bd4%b6eo+0|=5adfBv%+Yq!lV2B5=@s$9wdR!u8!}OJQ3( zrhjs&v@rUz0w>wxvMDV6ISce>ysR>dER3?p*0{JXzVsR^>Bm#NKAUTj z#WcZQc1T*o&LbJI-uj!a{F;-xa}74?o|;OUo}Md_-un8sIMdnNnD1C6cq8i?8^5az zthuXPHL5zTrX?+F4Aou*uYSHQF#Ou~P;kAoBZuI*BhWRe9upo$*Ja+QO<34P-Brvb#?TC z>I=G9Z5l;lhwof>p5(KhL{cx8OAp~fCbCCw1Kz%AC}oidAMLX!5JnQ8a~X^+G&gp3 z!D~#kZQKGK0!l{CHy(zqr()Y4)dP%)I^n!YSw0D1$)HbH$}WSsFj@%=BRb(nk_Z81 zH{P?|LCv;5Z?C{j_p)idIlHkR@5pvocP!CYUK`i|57O~>wRJ~l5S9;vsTY(L z`IA!F0!&U4Z;e5yFEZPLuBh#z$K_sxdg)4DOfw6B2stYLXSOT}>PDysKCI?T+|7Q% z4*E71eVfKlsko7+nwDE82-4i?yU2Z$q?#6U9(4FXMYKjjxFvONVP&iNWit$bg*VcQ{T=&>zdk(KYeqI3Y zep*(#TqzZNC?stJUP@4tvR@Z4iqhFKTYm;ma*BCe%p3dcm-SYy4YmaQmvV`^Xch1$c?{b}B@in3qFojf?!kESW?f3ODghP|E2 zi>h3322mXJKm?u-qsGq({QoWFI#_?`b+4+y2l(R z4r$%oM=9%y?34Jo0Zl-j)PeKGd|f!O-gytR851sI$!il);@iqZ7=9L zioWa-xgR{&{g#?K!`albD|s$>E}A1j)77zU*{-;IkIGL$yxE(At<1|y4MzUbN|sMz z#&N0b%>2L~0gV8>-1$V2IP#9x6kXLlk#r#*+4HB+A<5lnGCwL~Z=@%h zrE5LHCLUGidXq_%HYX-HL{=z_mTbE#cW;yXrSc;EVF*_Dhlv%J(8{G|Z4Q0f3|Xg& zf|PniOkEslUkd;2l{RFfavhrlrdH0ZhC-Lds zWfh{fcVO3j3Z4RA)7p4`>PVUO_03dx3N~q*ef%Q74E%(nyxxt8 zUJj)fKm3^6t?SDlA2fQMjc8<&msxiI#RZphDmJR$ia5{cgv}jh9=u(?`@`=aYH2Q9 zDK;N4pTqielbTHn!$kOU@{_a3HGFCZZb~2G)uSB*B~!impJ%_Yk;) zUn&E@_81onlk)Z%NT1JRhE1yQGIt3|J(|Yqdkkfu4=BbZbS9WDY=YC_tYX;OR>xW6 zEft54R$FMSWj!|1^VbI#9@dQy&I4V{&GG~Uc-VLZ zc=dAd2(6UG{TEmHGv`51F<8M^SVYteu?b^TY(KZsAv76&f1=${1kfw_H-PCyeBkV0 z<#rcPCehym3g)=gGj^}*pFe(7omxa?ml9=nLqgz&RibYb2K6A)4sl*{90T)X!8-_N zLB|ETg@}P1oc^EY9lLENR9V!izg}t*x>MKV8__=exhR4#qqG8UbM|I^z!|%>KJr@k za=~9YR;RK3@jAjk#%E{c)N;v}IC9@RiN*ZEzp3pAGG2cREE79c@<$CQY{Y$3;|zQX z^{X&`^qQ{z?I?W!eS@Y?@HFs`y`N616kd1{4`nhOulgqO-wuD?KWM{c0$*?28`XEG z_L$+3O)h9!>(dDhoyu;uOqCUoPzBGuuZVX~&_ZRWmy;N>aZ!fF19Y$HvmEiEwUD%P z3CBf9@9PRqM7>dJjhmiX6Zbj{MsD*|4-aI{a>wIKDp*txc?+wdI??M{mU0u8{WQF~ z{}uwR;Y67_y?F4xRW?3(D+Z^R?Tehk(62TqjRjv05)36+A= zIJ*+!T{k|$43<)u0^ok`_mw#;#syEONlMN%K%&)8yVOX4V1hscgqWNTc4{3OZjCdn zu6$(8Zq;^dkHV|N07z#|z?}t11kibfpLVj05?oy=_z@@!q0IUM)4xWq;Cx~}luycl z@~$KT)I7V$VE;T}=`Cn#l)S9g=-q~C)gtqU9i{2(M>k+T0(`vc_aaISqjqvNNDG|a zsD!y^`=4mak0$fXweJYu4)7}f9^w4NQvPMPM`hX>Qyeq@(CGY;-m-2znyYJee>_ls z0+KX7U=EyQ?>+;*euBL+XoZdH=v2ukjlfDPGBJ~8Y3U489nUJav1u(dpZ^+!9RGa6 zy&9q1qg4`4;+$Y;r1*5rDbLdJ5pSXgJG8CytuwZ9D(cZ7u8x&g3oT(22#;xH#?sbF zUm$WX(M`tu+h_nzJHoPGUC#Zxn~9VSDy7*%Yy4)~L$Gt#%> zy1s<+mpf(Fh#acY_cl_0k770=i{hD;rGxar8K}3KMkNOTSI*i|Ps&X4)GDO)myG&_AX0E!8~w z#k)_Xxu~nDqz`4#;(H>%ks}xp_dQvE#+=Dzv zo!|3Q{a*2WWn_iA{J$!6-_brA;}&;ueI)9($Z;}EX%f8rcGCEFe^D0GHf+>E=KHL2 zwkXtPLVqV_wC#QLPfQle42{6+7Z@CFWsqR+k?LbnG`*N*?dpvx#D!DUp5V}}X^1w` zHPUpTIa#Z4z|FLVXXP;X>J+SH??AHCwvMZ()K~7X;Q>yj#UBViL%_Vt*h3+{d#N+r zPl_u19c!yvvXUNeuJAure}68UF!dJ;ngKNQZ2BLoyMMbH;6U4{AEo*H&Nzb@(qemh zhQu_+js$DRMro1~?W|?Ys7MOD?5EJ$qn9Us<{v`3E6j#rH!9GHcjr0|=l# zgIqEXeqW*!K+7syE*bv*PNSKkMt3I(r@5t_#$yh|i_@p`KYtTp8G`Dc{+JsZCceWB z&gCvi-gPc_j_6d0`9VZlp#fWxviKcxcv4bi_FEMFKIRfIqE&!5c0!N<*)JJ*hDFTF z$14h}Rw^Z3GE6_PH1ynR;r=&21!6jIKtL&Jlp5&7a~2cVs;CevA3LzNR<8Q)wdZuZ zcssW?mP`O*6#?sk=MB>{NQ+(iyT7zn|5rw+37~EN7hr8}R%An>bUTqKNWNdq17Q*d zyQ}QKgBr}qCiJr+&A39nG|$1Ue%X+?v}-2B%!BQ1pLjfn2%kvz^-nqQj4n~#x3-;& z(`lS%iGf6q4ci~X3)bwIm1uWj)oL`oahUo1nv^J;;4hOc&%O`ZD4N6LALk81tadLf z!DebHiNdP;_pDHeemQ?WcaxjNzP`S4VL zE$i#x45nPE)ZdASe~6gLaaK2*ut$YyDRBz&*k%sI&j*z+wWMIxT(lR#c-6$5hDnF& zmclj!=Z4IKEY>SSkgMl>EmoQwcbPNmJ4OClc3B5rm4!Yo!q01Yu@f|^5{+wu?2lcF zE+eTIKbx#_vR$+<9|0*Z*G+4Td=nytIakl-WBK=uzm*vz+HT{DXxgRI`=dScLw2PQk7G$BgKr zQ-Vrv_0hlIvf>YDTsn1BiehhenW0y(8D0hOjVsXV19MPkx&xd^DZf{Qs_|wg>ZFD{ z4|E+eMW~>fQtw^XzFL_wMf@g=G0Pm=Y$4nkEi;!~hSOutyMXY%3sBYCw5Kdy8O-OC z+3Zix=7;&_?*oNL^U3z1;Kd%q=NLx3L(cG~^LuWcM_9)hyc;99jj{A(iOp9(IH_E8 zJgvla)bxP)C$8bPeV$!R&O`j?I+)F3l70C*bfL1SLsUb4$GV;_v6YUD<8;$aLQOmT z+o!Ch?%l3tiq6%ThYB|9S*lr%fzx!;Emp@^$GW4gk%>cHtlR|aGxW~AoHfi0DdhRml}e6EN`H-c4mLfT0fY6@XjU1aovR{$(B_7x9S? z-CiUAc<8;WM9MOmkj^|pH^9HqsR)PxwnoLP0+KJfDPEvuJjLcxS7^4^I- z>mxMr&QXuNsnF@|E{DEYVl>*`fOus5B5M#HgthkRzK*u3dA4g*CzqEPZj4aC>U}(6 zhPFzb;dO-I7h&Fa6q(&K4xXUWWQrsHh?njFKRjkq^()Y>+ejGemc*amnUd|*N%rgZzbKL&K5?MtrZ+PZm}PIsu%!!VgR%U z4QTV)WE2(B;tC=fNpUCm0<&=c-MCfK)>`#}0_|t*2q^nSV0LSk{6o!;#44P@uaoB< zGk^r@=jsUO)(kD`B220?Y%`^oq`Wo4U-a$r@@Lc`g%`@aXL>ZoT!>1>2OJHwnLH{mu0`Ced75!(*Xsrp#_I z(aVmVcKrDpO{0E)^x7a>{Vtw+xsc1Qrq=lytgtPO)va|ziXNSfjT&r?*N6U5T{KDQ z4&1_F&rgOL4MnE7T{-*MTq4L^cFAe;$o)7plnI2vC-IO300ai$)g8t>p}Zvh&B>V- zu-Tfotles?jMi@Hd?GZIulZm2{{djn8-mzlzT|^CSNKI)jF&0%10yTocJho=s&ho4v>QXIsio$jc`n z&+hF+RqL{bdxI7glu89_Q;-lDQ1fK@EauCGP%ngL`J3$=ETuKQ8#Ss?JUv2lFK|1G zqgR4si- zctqEv`WjW~aoZBZn~BrJ&gR2_B!2D)V?q04h=8y&%D9^X-bZk1KNle$ z7rg7bc6aP&qSR@+05DunvZ|*a^5~uOpa008YtM^`C2z(*X25fg7faOuB(o;E70g(g zzg(S9aHGV}dGl=odZ4WGIgfF`PPag~(S|U$T4agbs`M0xW9Ys%tpF#WkvrJ7LI)IT z(qg>S--MxBZo78QQg$)3(`~z4wyTsR!q2YO`OmL)kEz_SxxjoMW99oSTz zGCi~Xcsa+t<0)uw7BNzsc@kdTpdD`3#Gsw0ROPT(6MXzS1DV92tXYP$9*@4lFk7Gd zy8C1?y=DMmO&yQ7g{6L*{0@K&ax%`Q2uY}5tY?2J9wvyI1lV_y$b`zK5|qoRo6wTL zIYPzbE*)1H3O+>MX-cu2iR@%i^65kKw9L{^Z#RBJ6sqn<4U+Yl8~wUEacj|~VRUA_ zR>1>_CC%&r-&I6)Kc6xi%$Toa1MlbJ@8-ypC;l>L(?>WR!c`YKgB#)D;30c{k)HT) z>zY2Mq-)pa_Z8xm5LD)`qo_@)6x{yz}QI2{e?3-#y zB0MQ?I$y5gouLC843F0B9|LJLI`iFjT~dh``gw7?bn>wVwuBC|N2tit812OM1E0r& zO+hwkXEMp#KRN2n5JrNdN>fmf6p-Uk(k3jRqtqxY{-*4+BI6N5<7DyT{1sBKhRU?b zSeC2BI|#R+dQ=zrRgfOk7Ol8%>!h`Ey5!Ge-;L4%)4=x>y5qp%#Zl_+35Og_vw=fG zM4->Mv^1CSro9Vi<|M|rZ{_)TZ>AfZ{Ju@+@cD@oCIm$*Xx)82(ec7QP`u0p18?nm zFi=w_jX6m80`rfs`4UnrXHMk@u2%8ObtwZBMq&X+cPoI6gGxt^y_Kf4@5dQpy|{vM zMRzxe$!)8wwcocRxZGdA4Q09c{(QUvS>~b_pnGh6&(+Jhv6jGdXYHqiR762sb_Wrb z`kxp!xHmb9lsj0)m_4YJEx*7E1sVcgx6nQjdaVt9wQ{oi>&u;J;;;xdcDmv0+;8{_ z+^8MMG^GR2t6r<`bM@?Cg!uv6>L*Ia(iO4xR`7l(vu)zl+-f~_RF}tx()2y{5Pa8m zswKI(hTf~!^U%;q^y|zFV47>pHpu?Ywl{J*!955!8?2>#pEf&DHL5k%Q_pg`!H(8r zk1Nf;yDO>g53Afk2#6z|v48WU)iSGUYap`-HGR+AjOs~i>NIUTr*`D04(#lwqE}jA zJ~Nkh9IcS2neTRqW%R%`ZkpO56^{c~CjpLj!O<0KWcv#C@y_l)@w@VmxAfFP`EWa- z*=j==)33`>B&BVqU=FJ!W0b!)i-u|^*)BzrOaGm+^U{rawvF8J5x?647r30L^HvwX znFgIGyPxt!q4Z1{aAw%B&*(eOxvDb%$jskf!g$?$VZ26u^9Yt?9_>EX5CSOqyOp)y z8{`2~Kk!P^7q%?b!+NNSDKl-@?_)F`I(cMbF?S5C`?y z$Ky2Gg|qPe()G0H?@QV9TlOxF#2g*r-)9)}g(2NirW^)6IOT+Np=zY;rTx#7A7>!5 zcQNQqI#oVGK;uh!+j=5x_3u&8JL8XzM=knvpBmtYf6uqSJpB9e&Ql{yPYdU>BBJAM zCaIng1#79^lU(n=E#E)|@lQkB=1*#Vkd5}yFY*1)cw~S0Yyv;xoe~b_rlPy zaXBCG9P{!Y1H%9QJ|XErRr7snYII$b7(mth67GOAI0Zy<_Kc}gIwg^xB|qipNObiJ zPyL~Pe0uS!R2cCT-LXI_1>gvjA{`6Ygi>Y(ucO>(hfOBm4$WPY>h&UP-g zE;j?7q{JRt0U4aA;P^w{bZ?Uuo;CdHbBZsJQkiD{m1Je9l39B}HG~E^c&(Tx}Ks*~nY4Gn-6K z=AHZNtI75y2++ln1l4#blA~tf8E|^|0IXW9ZQr`6JRk8(XSw`P)8lkdfR1;>5O+E?$ZMEf5;uB#57KP@{GRv-$)RKY$vOLcH{=7gMYsph1*^8( zh9sV;5L7c*yR*T!jv*n}jJ z3Qa#tUANa`YYZ!@H#)}rTm+7N1;G0XsDv$*&^_z z7I8ex>kzL*MpuTbiK}_4K*LwhV!G{odQRsNBq&@Izr40%w?!ZmrS*1vTD*>JzBuBP=CUWbb;%~RW26p8MmJzQNJTm~ zggwMwOK@(7EfYolA+Lcu>wy%5f}4YRRw1#?I~$1NICTys_BXLWx}?C-*L4m~ z!KEo!eU3inLSmw$q`ynAny@)wE|1N`Db!|-rg#`)qytc&F2K&`QL2((1#c19+~_O< zGt&Kiq@?iq5!lqm(%@p`LI|Tb;usYk5H9W;q8rGP0$eyW&k9PTEH#E_5m~GJlrV3j ztvasX3d|{ARRWZaoaKK9Z<9hJ$vvB@Z+yuC?O2%|AmDj;=}C!2eVYv3ZdJE98%W_U zSVp#XK6tKxsj`uc-uN)ckAS9{Ya0}y;z2+P{uDUIJVYit24AS0ap-5;24SZBays?{otCCo*O{ITLi_MMQvd8WyTt}Qw;bbN zS~=Tc9@Dm*>c|Z{zbJ2z(yKqk;7sjaUE({3H&dXqd~~PLc@(luUR*XRn`-r|OeL(! z(#Qk6L7k4jxBf1YoFB~UfCh|sta>E!ee`0LnGUA*=M8MeST$pOXk+Vldxg<6Y6q?l zpeRLUycoW&@X}l;2fy2uDz$-yCq}*QD^nF-EV={`=zjh&?c6Hf8_?_8Dpus7QJo+k zGA3)Gj~#?|G@-@3<8r?4ADz{apS5QEl;`)L<$o;A7=&sU$A82ZdsJP&BaNSZpRLx< z)E50EoMV{ev9lW=V_t>)25O3X-{&jU01hlSyrX~iF)s-@v;l5*kWaO>$huvRt)HyeT9!gTNj zbZTrMvfh|ld?}i{-WXPVS!{)Bs!rk2Tp(y=?L)r?nbMqFu<2+GOS|Tmrw`-T@_mhb zmdD?dR)^aPwAuKEZ7)3W6i{$!Z;kqW%}&loYwoeWQ4r0sxr3@(PpZp@jsP$p(fBX& zF|YWt$_h208QuS%(%e;x?|%YQJi-g!H|9~)8*{bR&?6tk<@lxMuId_(>DM+>xTNQ< z>KmCPI~L}7jt5~q1DcWFy#fn19bRzg)~ZsLORYe3EUz|o1)Fx(G<0hya)dt{FHWBOkxbru3yGM|x0LWgXaJU&2KB6&L7RS}#O;R2AE+HQJ|m z1QzJqTc^^lC8soN&o%3;nMZo07u%~hPUUUJ09#e&nCg5r>DQq1Hc`6mBb(715ofn; zvF!;OFC)1w^g=Og#~IV^h;&NMYkzmnN48BzPSYM)gr_gWn+!4prP(_BR$vD=n3j)z z=Oq;6E>-=C@wg9i0$+)Bn6NXUF^YX2h<_4=-i6gUcxtzKHq$6hT!!1*A7``ZZ)5_w;5zHrQ1ovf$x-3vd~fnQ1zN*QzTxlM zm_MAm;XHxlj52iR9@h{vqy>8` z>(zfF-gcjpX&lq#-1}%tPb5_n9xVgaice*VJzDzmxV8i5mi9-`ZV~#(48vn5aLw|r z=l&yO`fuX_(-SAOW1td!NrY75CiLdrVMjaqG9#n?E6gL~(?k?LGHM??S`xF;Z+hZR ze**Go@j9<*AC;S{gvSzubQj82^3(Y@tbB_-;t#X=)n}lD9S6iA369{=p%`{pDnvN8 z$9KVh!7yxUM?&rHC5WZF;+Fc=nhSs37u?SDbS|+GNN7ns3rKJz2nEyzLusPVS{)ge z8>mKi?%_BgVaHJRu@$fH_(SX}DG`N<>2YP;$%$9m6Yo?d9F&+ItvrvEz6{6jUGO(* zjSGe2xA7QDbZ+K-sA$k7V(gJ2B*x{DQTqhflGvdoYoRT6LutIBp~f@P(o;eV9pWzXVjrga3lx?T$t!fLPo+te!~*;HgS4Q zTu3DBcsY99Jl3mmj^pEmgoFI1Cm;zz!qNoCgiUae$LB9Etu)|N7`7lCsR{Cc{VlnVLdAD#RVvN6sUHbn300960cmaHuYitx% z6o7A^yvw_kcX<@sr7EvJSZdqZ*}J>b?#!$+v!xpnM*@mlW2FxQsTyniQw<3kNTVo* zgjlJK1hC={qQ+3g9|nzykAFxLG}TC=q$(JS=bW88yW8D%lF8l9{qA|+b8nkj4x7ms zd++^@IvCjRxr{A^G358zdc;z6%~mvv8v#k?x$HE|la-0Lf!- zz^6AqzSld?LFPJ$$z_z5&uZbr;I+|HFp!Kz4&Z3BBqPYJ0#**6*Eb!yj97mjV{_85 zLbe6|K78WCkuk6XO(}8a{oGJmxZg3pZfoV1`WY_#3_#Ps+W?;F!o$bVp5;7fJ1(N5o1pqx=duu-o1TTaU6XQhPv}HX!k3{~v_s()m z+kAL&RSJbr5zB{<&+a*Q5C#%e<3K^K*<6dNb|5ST>r$3^z4(RZDi5`H#SgSUvA;Cl z-d#VR6pS|=$J~&t#f~h=3~HcFvm{01#saFq+@gt>1-B%XGr45QA-kE!7P7BkB5pso z@k@xxRd~@0G(|E^C8()fvlg)u2<^`C3&rRNMp=}zsYeZ&gIYDBYd|h$KSN!;GhF{S zKxyW=a+%gzZtEL+&Y!B0tG!TrdmJ<6<=+8EhW8rdACjKgB zkAsXWYs=@q?Z_;4WSTMDaVa8~kx2E%AGw%a6uaC(Rj&HDkxrLT{s5o{Y21jZX<1Iu z-gbW91)Rm|54rsa*nZy%N?z;HfnMQ>*vVEb!U0%GcKy;e@EwR?GvJ*CFNOty zRqQqR>-M{&j}^j*BHUCNh7==aH7kYh;z0&gban6ddb_$iFYC#2F)pb-5Wc=V1%L?EbGmv(S1hV6nq@D`CGZ8Gc)pG%3i9%^3zZ0-fE! z$rUwaSF234(I5U=hsnb5h*&3^kexWi9%QXBeRcQQ3K+aLbNboVhdp(OsY5K5LczG z6#bK)OK$;4z6n~DBDNk#@|e$UbV#>NoN>43Dp-Z?Wut9b+3qe7Wjy@?a|d;iGnMh5 zHiKleeubkUXz0-l^Q$N|pA7vsfrW^;I7py&B)ZHbZW+~dlPNfTc@IMPiv8s0EsD%* z*b(^l&2Kj^!H_1%jc_7hwG^<@n|H7b*$H@2qiP0iS7QR)Nv_9!eX;vE0H_foi=f3@ zt;w`Eqj0N%&R)0)i>EBtUG7Cf#9TC^NjIhKaFM8^=8)6Tosa(D0_@sor2_54QUVG$ z9wFP{Gd<`DR-YsX>=wyTBp>t}IwA0`P*3u{I92x&?h|CiZl=DZXaT(;!_{4YWp_2D z_e|+;BNhC)S6;Y_reoIsD2myjy@Zjz)!Gk*l3GQx-ySux4fWx^scIPD23CgvMADAJmN~pm|q1;yC;Xi+3740C8 z(F>)yYMU)pOARu-rY)48MMjQQN-VlAwT#o#Q#|__uJf&zbyRhS$CnkHQEv-Q1}LX26Sp|P8r5sr!!hdK1MUDD9XpnJ8bTlbzVm_rJORf;dQNPm#l zxXM{`KcJ+t%Fuhpu%bTXl@8wqPVOw3C6*B#m+4TC@9W$q4w0EzRvaXBDrT5tc21$h z(Am!YOv4#fg}7XKi@dh0dgf`&iVGd!e_QY@I8OGA*jpfvsrCF;=Sg)b%h@xPq#3y7 z!T79Lrqevtad+f2T2?Y3moYVL>BLyED3{3)E|7}Uvqy!~el^B9Ue*spC>6XKdGL?c z#P5kyvmWdYqg)XBN9=jNE9lVIN^q_0JU;}weZnAD^3vMB8p~yLyY;hw!@z+4u@ggY zuS$c9cAFTYWUa4QtL4`hVm+Ocy~5J;+vy=N<~wyu>f=nUen;Vr-E&lUry0iCN(y=0 z8Y-nxqqeFEC`NCl0%Mekgx?@S##%h*dzVN5kaMkQW}!^ua^=vEAD+b?dkIw3ao?J? z%t9^5VCaAls&Lea(|pg3piegmVVCQWCS+wN+M8+WY z`%H|G1Z3YYu=ZQejgHAX#pA!#gzO+;rl;HSmG`zl-3SS#wh&6DEoY=4+vlpCjrB7K%rkmwjya8) z;j7v*eE3%D2GKqnw@l7+Be`Lh6(wtMoDGjFM$sU(Z7k$~0S{juUva3Dtth32OSj_r zohs!J(dQiCeKvkq6~6cGE`d~xL1Fi@p9d&8R+&l`&`^TqpPakt1^Vd#JX&9-Q3YOX zR;FmcD+W?8l~)c}=9_6E6GGuxRSPhgskGo#19&Gd27YEd61pU{m994Hw6w7FQYe#( z5%M;Ch9tQg0T*MlI8CxaJL4sJiQM?{TJ z=&dXDRHyL#TCDLr{p_EMCkDqGJYJoNpo1QX(J3E>CXNu?6YmrFe#v)1ov9(?BGxI-w?p?G_%;L6QRFLr+)?)aR-&@ikmnodTRO>o0P0WdSs_+022s*AN;)^jpg!UmYMjV+TL2zZxD`Pz;&PEEz)7XkpSsjqpv= zArcgISrf~>)Vx0!6+SK6YAKhBC$|Tj;I>CQm$0*&RP($L9hkXZ5>llRJaccDi zl2`YH2}zU$dVYF)*WSmKwKuk9HBV*;=()a|guTgolQLzID!v1YP#!6=vcCBD!kk&Y zf7L9$U?ib~JO`~vUjY&ytzU8zn`E*cwKd?yiGoJDo_a2ywda%*--FAvYr2C3I%5&G zkJmk?c_%#zx~SufMvImJ9{cBO4I-10J}|F5F5uqG)Pkb)dS(++}cO;E6iZCFxaVpccWtjm*Ub`N-oe~Mjb;?1^ z_^gTY(@6iaw^Eh;h)29rX#mmJjRDtGqHA{6YqEA3dkP^$8n!wZ&wl5!bfT4e6~1Fl11qU-Rjc$xM}Rn*2V5UEu4*v5q3o3TLp;fFZbKB ze~Q?dW9T_l2cSWIcgM+Je(jU9X(Q8Y5elDe$Z|!;(z$;8*`EDr!1>_3=?i;i7kMqC z`!Kyc;l<9;sC*)3n%vOWTJ38 zqnq-4sUM9-V|<$$KjyzSR7FnEdCroYUR}RIBlXM;UY1Cn`Kvxj5_-Ci`-P(f)3VCv zkf~JQU1*vz&wGyg=^OBhk$1v5)9$j``e4Da1%TD$w!sTL17 z*`?8RSN7_D$RxyFa>1zhTyqVVI#z}Gu|4unl|G*?1I^@%_0DK&KDO+U(@7bz0-Z$V z_>TkEBz!^_-di3Rm!rq~It?%gtom=lZC{8^L3kWrE39<138MWf|5`S_>Dji02bDU| za#m#H{=VwTdoKXz2&(8=fZR>K=G^FlF$NDNI4XM76^Y+ZlQ-#=>hfCFp28se>{?-v zUcU=S)7-McYmd%Yw^c~<>si?)hWlz7iqh)^lbPXBPf^Z`?!8h=kGgOkV3E1TPnGKs z_aZ4X{Id?2KM#t1{+y-@ubW(wAM0xP>EVQ=2B`^u0~U7x46oV_Bs2E}_k7X*AR_wO`egVO=ERah z_K%xA1Rt@QblN#fC0y-9k_hJ2VQx?7eP@3fidVbax!?KwZ!=_r@gF}uNrEYJ(FJq6}q?h}2=B|Bj z&aq{FHupf%NcKYv!?srllZ~O_`yRm-!8@p@6=7-LyP&%UL+a-Z5n+PF-*LrTSO!^mN-#ANb(*@*MIvj(JtbL7KYHyd84i6mI0JxU2|d z>iH7H&_heYVZ!J6a}-~r8aHDvk6U6$q0jmQ1db#B7GlcH#DEO2TvW+ z$#M3oov4`NVL4JqvxfxC>lP*kKCym}g8j^cWkq2RMc~UxJ#bWL`(-R2Q=^r3{Dp49$oW^OrvLunx|aVA)|Cu8l!dlOtL;Ap$-v4fR#T?zq~~ zWNUt#Dg;Zs4XfJ8&&0*k4hkP(QDOg}EO1)~+TZdJLZM#~Lc7L}i*trAmxlWArP8g) z?mhK1g-CsBkj}VOX-)a#d{E*l1058h5;IkFloS?Hyep)HIpN=Rsr=z~EVXO2NzZ zvxJfy3K9B-)3yDkF2n*(DSWBEZ2(4X1;s~bde3QX_8twi{$W`NMag-bLOQb8)at6Q zUgTD*Lqp{_F)@jGF%GM)#G#mMrm20^kk6sC?niaYtkL4MmmC|M!#Q?G;@&!U8nrIS zhW=DgJ;=zDSirJQCq-oBWZfMWJsSTC{%Y3=++2`U+qOzMEGT+OSrjek+TH!9DJ@er49a=Sf7#~N_>jCOXI zR9fZql<{D-Jx&BE^^MUX%Y3AFKm5XYF+)%CH%TL$MO3fXE)Xo8A4IPdjII%+K)$UZ zjmLg~2CM9r+UT54L&5#iw3>Y;Ck72K>|rJr#u?Gf_a1@Lo#(8i-it~SCX~c(0{((A8g)r)ZL>j-|iDCVj8lUFl z7Cy~>t8Tn)eAqKTpPF7tF^zF0=ZjLkmLsYjYTWi2`Yqmguw~jqG~PFiHf=;e`I;Ba zKYmo(7BqXVfKb#C;vrO|&OByK`Stc6;*bwl;H<4lC!3MWqx?r>3;)-3%8|Y!k`(kI zxKWY_H#ZihJGKU4(Dp@cl_YXmk8SYWCePnvd*bao?l^~+RcRhD+PCZr+?S@4qR z4_JD{s8X_f0$T^suQ}Pzoj<00Holn)*(b8+agSz9XYILoV_W}Xv3D@uU&&@ev*L!U z2E@Tv1JXW__kpqx)P0}@zS^#bFK0jR$ES+eHdt?z?jJOb0}!EF1oi1D>?kebY>_}TXzOl8lj4I@j!;g+GS=#6 zzL;N=OO~irMRWN$JYP#JTm5>=6%6T&qmPARSWCS*hSD#lznZjjn?xUXM}G*|hK{Z% zU&(K zf>(F^PrELP7)(X>tb~`Q=+2G{n)gG+f*5@D}(Q$nt-t2;As zT$62=N0;s!hHL>s{7MWNRn`=C)Ps=8<#1_g@o%yt#(EU;@@Pft28g~&rVh2;DzzEy zuuk-uIxKpIdZgF&4U6}hdacI3PI#sTDmng1_ObANCAq5%0zzN2b=>=)NT6XmM_QMU z%OKkU`)H(;Rh#9m-uHw7P4zL2zMuZZgMAIUL?;iaVU05j%5$a?ipZyGEU$4P7F;%^}b~y+&1UedhM1j|l za?^%n-%4wLinf6dYipHiwAuhMaT$RAa6&=9lpZ7=zSoXnCOyxKb`&P9#ub{(v!;Nx zv+8ZjA~Z!Ip;1##Ri&0Cd^ah}YEMbu-N;+#Hkj`5b;`ah=XQ=Mes@lvoN-JycSM9& zP>gxbsWYN3)*6hDMpl-)QGDJvl)x&6YdYjTuT|yX;I4Uo`9Q9->!~rKB8LHgi(e-V zix2y25YDM}hs7ZrgZI#(8@c|VEw(^*B}OHF<=-`|4>zvXT^KoZ?3$}82O?M*yf08? z*i+9LbIJ068f}6)!7p1w-*cim%w+t8em~%M64Yb;zyxKY9N3*9wZ=QLs*vIP`q(hc zkMx9K4(Vmm&6Z_EF>PL4RiX2AwObY^9IGlm#?KB*2dMfmQJ?E606!c$~$&Iim zKZzk8F(Dt(A*btqVJV|EvisTFS?K>P35^o@3Agl5La%ArjLihfX?)Ov z-7%b)Mq_~UALKX%ag9T$0|B~#YLAWZ>s{0R2gOg1BPx0C( zOAL?};YVC!xxkP}v%!h2wTNqodLSpB$+B-yH3I7-C;w%xT}vB9az$;{oMmPPe2dN` zuc(#Ag>1jBXb&+fpp5SNdAc)w3%91DrEPZbyeKHiPCX#I6VKg&p6NG?Vp&0EhESH3 z!+Ww`rEyT;VtS~vYa@qh7b8~s$=Tt`y#HLAG8J$Aru^cMM)J){A?_?Vtt7=5&qx&n zg5|Fr2<^=UgOT1$Ezo)+-nWy7iHzO)FPlYgPp^+`btcb% zJPHjh0osDjVae0R8FroB`FhR-M`?r&xbZr@W+-pe!4UneON+iER|SrC@_5b8jWJ6~ zWcBG)%48gaK4|*_PO|{->8h@Rs>8K=tKS>#I}*Lw!OvN7xA++I;B1b+BpS~d=k-d~ zkn1TctP8Q2^R?ySu7ISx#mF<9$!pUo0Wc@3Hj0d^TY+y%mkV2q-dZlNZe|@Hl5kHk z93!I={u=KSX>Hb;-ou2)oIix#ODENRbBQA=9R=$bY) zCeJw2CLSg>m@~TfZ)0C%$PMbSWNYWFl?j7KqL24~-=B%&JrZk@;o*DtZhD>V)NMoj z^B>duPZW~g^rkC0Pm`vbfbe^al}$4HQp7W$CYK`Kv#G^WX>@a~sY)VV@RO<17@w z*mgEtlLOW$M>mcdbKz5q#$K&>XRQvA-v#w#hX<>0Y$&mCyk$Q6RIJn07`S`qh@aTx z8sK=n1G%R8ripU2q8k~GD8Dcr9>{oNbDQGlZNuat9SA_t3`stDI%TKzm|@zFv!jBV zew#PfS>c4{-?Iac%=~rEPQA6`TYteP)(j$vVvMs)AoUHE(!%OD(83abz**`i;z4vF zrcF|$7|Xb+$empX>FQ3D_doU7I&Y`+s|3YVc;5kXf(G56k20dB?l^c99m4I^V|K2B zs}bt|7>{mj-OT5u1qxxXyNkeE9@x#>8KXbB{Jw&qB`&B)ndx*xa=rL=`Z~zPOfjF( zh}ZO4l{bq9hu^5tW7Uu*rim{y=3HMq+%+}*OvUp(m*aSl*cEPTuGsZq-vuT=kKOgf zER)VPpJMI4ROXjRK5vj|W`>T+ExBP9)nzPk97GMYR##is&_pSXjW9zn2~-OPRVRy{ zf!RD#wYOJ@b&9)u`mIM65zBjn|Ji}Vr}6c`lZLe<~845H(e;S zJi2(NX`7U6I^=XAo-$6?-RbeF>a#Or{Ug(h;Z1bkMjeQnaGM)Hdzlu@sm7is-=;rG zVfG|f(jz?uBC&Y{(s&rsH)Pla_~d4=DNE@AI+iq-Ux*R^S-KrJ$G=VYO$(?FRmKcc z;E?MBqit+Ctc%WKll2s2x_X zB#l~^Y6H9DpKbp@5!Vs!CSco$zM(H1iEsbGhiw+^lrvN|PQ~oB&zIZKxlYSAI909Y zF{e^bRkJ1;_bTN_&d91YG1@U?`h z&*3y75I*lYhOi69f(`;|v>IEdNFuZ(=bd#EI?rNE6@Q=f4|~!DaUK1^y(K5@WSJQP zdI=aDFBO2F0_VY6g2U6i(N4|gdOUGAv z=m=lvsL6Pb4!HwkyhCy(3SliQq+~kjCQ;~!2<7M}KPLXwWL`8)5*b@`@P2k^UiMUN zd2v%i1)DpUJdX0gtd62WbY&l@;fHlYIy`d5-nQ`4-9>Ka#XD zj$iSnrS{&g@CPKXl+Y65gyW>Y)iLD4zp#e8&`5K8E`v$c-ZTrdy1pzeiOy=%nzp0S zdHNYWKRxVV^tyiu7nXW4(bJ?G9)lfSzCoHfF2mB>jJ{JVehOUWkhQVv+%8;t+G0X($YP6S_mjCwBp3VmCe8TbPkJ%J;`DZ*-75MWWkR z&?ET+r7-sKeYo!kY0%wzIOiTWr7xO8ov2r0iLC@*_j8-#GRkhm{SQMO2kQr6B!RU^%iX>|^5iqJEzdz$Xj)fL!8m=|Ts@imOgM{CZBMcC=*ypG~QC+yM{I z;NGlS5=2b=%|;*T-YFQPL$72%^aSwktqg|Li$d{miaayy1z<~Zb8yDJx*fNjVISj0 z2)`47yqo0u5&2Of8BCI2*Y~?t)qD5FPkBn{<=as!>G9=HE(DhccM@cW=1>3d4WVBG zXgl$ib5g@h!ru~aLVUZ^?ij9YB*#t<$s;GiM1-O6dPG*jlJA1@-({X2NS4{Kj~^32 zOG^}8OU7wIhf(31%}a%GPiX-V&H+F1T;Z8fZ@Ve=vZT;uiCiB{OBKMJ;H_T5ztn7t zzTclF*aG%ZZ!ueTwE~y+UY$#&AsP3=YxkSsskFQHt#qH4LrIzFs^(mC?fQL8XhHrD zfxhG#~C(1!>W{=Uu zSkpSnq03}WW2yI4HjZ_NMy=i-D}y}~5+m*ac*lB{4j^_y1{O}tk22(w$mjJcjoOSx zF92TgeYF;^JtPy3VR0g_#cAOrx6QhURBE;UA^lXBUHLQxJ`yn4eoOY&hcH<;F&W$o zBugpN&z`tG*Az6*5k6gWwN|PYz>=_oxRmb{S}QDN=Xy4FXijL?JK&tO{W0I@%*Ao` z@>=|!F6jR2jxxcRNU5y#S*HtRr)6HF<2hO_H>K}qy#L4(`4EPG*Iko&uz`(7;ZIrD zM0}9_MyXeSw}VF5R)Z4g;A{^QkW^2aU5H7VtdFS7#~71h7LnvQmK*XFX-|MbEJELb z{Bx0sWUDD%Rn~X%kdlaw1pkzhS6Iz!RJnTuv!ea)X1;%C>{DG{LhUQrQT9_ z0Yp~8FB+^IMy|5`(Lu*x_4G9g1%DS_RjoB+n{KNMO$KjChQ9_rS?l?K z2{t5eAsv(1vU!t|*!YJ@>gU$08pT|2rZ3}Z)hl$pB;$z(;oCEe_!5ECse4fDPPd~Y zndVg5$*_fGRmUhywB$}9gtL@9S*D9R(oC>;;JI|~v-eL^n|oy}@9Fm#KVCCuBH0@( z??%nrr{g)bfA$VwQ*XxeN1GW5CM7Kk7(BDssx-20?1XKC8J#x$j@CaXe~`?8Aqms0 zN@5ajd>#T_^4HT9%~YU&r?q-|fO8mep9L~A zwu7|cxBMoW`tEmjf7>_Q{X#t8xYrYs%>Tz5Q*z3_uLE((P&8u(U^i}PYFUjpzOy9Y zxPow9L96F~Hy1t)>=YLFqOEQDXT1|QbRQyP7}3gnvu4&sNO#Cq3nwt>#SglT2VftY zV{ucwqZQ|g>P5Vv$!Jo7SyiSgMl_@_pTp18iZ7*-y@-s)MI(d99q$Qrn@Q70-{qcu z!LxP5-zT!0go>@>4dU+hW!g6R5a=GsRb^Tz1WAu|;|+rE=!?@R zd<9j$Q9BsydO5LinZEdzP38+iJGx+L!kA;y>R0w#JN$%QL9J;kBvY&Kwe_TZY?4IP z(5Vy4y(itz+(orCXeU^sO0k3E=mF8k)!TR=fcmk#+Yj6yT_!JbyP$@}Zx5zVa$Ej* z|9b3fL+NP8{eG4~d3LR~WJZ(wCig5IKWZPJpAPs^UyPTFWF0BuT~UXVi$QA-|6(QH zlmL10pV_Ubtz+WHh1);z*0bEJ2FVDmx$q*JB275q8kM;46aYbZP(LE>u^>CGsTH@D zUWBw;Q!cXuGw}yY&xp7k9CW)KxY@_o16^apZR`@gm5V;hCpRgdKL^miWY8ML=+b0Y zk|oCEFHAhL^%!UVfaC5LF>$h|eJ=I6nsc-!=@oa`zm)Awxh93l#xmy zL`65>?3~8HiCe$C`bwJedvyW?{^jh?h1&uF*D`XDZXe8n{k3XcgrPVf^n#I#g<78^ zFJb!iw}d~n36Duj5%xC~SiK)zf%*zoo{YTaB7h{QG6$|6)QGv;Vk7!Ia2YfX3-;*K z2tBI(DKC|zio#fm3@%&ZmLO1-f+-8tL+El5lnFkDP)>j`(wVc`lSG|Pp?z2%w9YZl zXjJJh3Drn+UowvsIu*l^9NY=t8*HFY}Zc}aO?_J9$W#odH zQTgh#V>kEuW(Dhw?a93|TneWrH#406DmFqnR){(J-KDB<1ziQ$5aOAB2VNc>eH}tW zHjSDXRJAY!Y4|Xj(5hWI1fBVKQr^X>P>y$B!9g-OxUgef>G7@488Vmh0Svf*F9)9x zx5kn-X`wX>KQcyxWz)1s`^aF%FE638xDckO%Q{XrZry5u{i7>lOdj67^Xo41rw)G= zJ+~6xSPW;5<#m5t!ze%`JuFD=6&zL*dKjDHkg0dP-=pzl@Jk%je)V{ZkM;e#F*JxY zIcx*Q;(7EYY#-+xcBZV?ZR)CjS@LcvG}J@o0@YIJ)siOo4OOhXx8wUIIq^@|9N}j{ zsMs-sWmQht4Z_9xfZ1JbeWcCMT)dAJU^anaK8aZNm3RoOY{J7rY25l(X)nk=>^Gi| zw)fTkd7sj4|1lQbsq7|1w81u zgE|-WG7pj?RLkY4fct4i(0HJJH^?z!A-4(bn~-gmpC!6Ljr;j6GYqbuSuCreHpxq6 zpfV?pEj^+-VB-_5;kd=TwRn(8dbGOsx2(naI_A1pwEY76?-*T`0(S}@9217GoafQP z2giufRVr|2yI-I?F1~pYHl~L|6n7U|v`g&&stHe08(&oje?jvWIXAS<2v;z+@qV?! z(9|{UWR>OaHOuiVQc(kX?bjPI!dC;lz{Ec>uv0ptF?>>g5E{h5k%k-g9XkqobMT5R z3n?|EokW0<6-He`fTsyfa151MQjYBKA2NhcexdSJ6e#unngD@+o26?E-g^ zH!~P1VE`26H}!V!-;;v$XGXJnE5&Y_{9E=gdbN}Q1Q`H@N$_LTU|tUZ?YCU*|PbMMsyH+7Fu`F^Cs>$)&sc|E?DZ|AF zGu8?4`DqY5JCj8L>%2N4C?e1G#&^|J_bVQ*HV%8qCpUf9RO)L^=xFNJL1?xeQ_=$Y zZ+?cyUh?^*I2By%iZAeeW+5Ix#ZDf@3>F;?-Q<9W=vxd>aiX} zC>R(}GK)0Y)!_z zJDwkNX_Yvr-w-{B9p*Tv!PjkzfGcTvV~%e1P`n(;#xg;uLluOlvn|yilQ&0q{Pyq( zd-<2d%NqKRJnXfk>ulxX>C@ypqth{r!SK6hl4Bn_^~J#I?Jt1x)ZMUbn5SzN`>8zVR#3h|bemjyk>Z+SN#M#7l zdGT%XFs%E~a5Dk}J~UPjafHpeKDwI!3vl)U0}#@0?_S{ooS(1+riPwUHqWT`BC~w~ ziYzI_MvN`OJZX%%jaDS%hwzPPJwxHK^}>ovy=2vGb+ zy?@hoswQbE%@j(9{N?8i3F%<~xO|APwVrOzhl4*vz9GWj-m{fG%BbtEUUhQ`kuT@x z7l_x=9hFxB7g?=OSdi*#W=f8Du+Iorf6ugV+a9sRdS9`3b>anKVYfnhI*EMLuqaQ& zo7vqNojXHoL+9Vf>o0};=~L!#4PlC-sa(aF3`w>8H-#8|+WpPZ_sUhCUvRlTaGiI$BPU=evTbeFX{Tp0_ zU4wm#7m$ZA_oQx;#sS*->{&*T!qW^iAWhd>D@Xgvt^^y1uB}E$SQi(g8p<%RPXbrk zy`trt7)zA%wG8GYsfaSkq-pzw!bh)B=%0$*ufu{8L8asoYVbDVo-V0lPWIP~uR%>Q zbJVZb1KY`?`$aLTR%lNq{!joIC+N0LR{fRoxCO%T6N+ab#4KhMLe-Rz(C#TP%KY;o zJi22?CY+cgSo}Fam}7Bd*`w%pX3fvM;P%-FDL>!n2O)$+?a{Y5cUo^_Q-|Y3Jf+wL zrJVBJpoN&x0M+60-?LjgqgP42tK=Qw+eh7Jgp9n{i%(`?a8OZ__`MmUxevyte<6(q zY_Z-!Vt6ryLyH697Rl<}hBL|{9^*=7u^72rJUl$S(HC&X{ZGmBMw?qRTTfARkACDW z{>}mU6|!eD10FT@PN;dKgkSZA#1eeEF#IG9s&*M6i8?0velEvRzfM52`xY!NQ7@K% zNX3oIe@BBqujwe?G?MfFack%Xn%fv?`r3RZMaS3Qa2g#*&++Qk)8pfAEVxUZ2|yAM z*XLXLn#a+$h{!R8!EsJo8&SkEzh^gI_XTfUyas~TKa{}NF_NvCD7aS@e{w;t2fo%P zJ{Zr49m40t%iP#lOuKe8-a~EqlB8GE{gpXjiIBE-E%a*&ygxouOt+5HC)(sJj_6qjhtd*z2NGz{n-%29TZ7V<}#LiTy3^42iwkkvg%o9^OIW$(^QWHeCXGq?sV(MOSG z9^7slH@|6bjoAXo^7@lR-A|gV)FO*BVY{8X((0olnQu`u){9Vm*(I;07I$O=fmn{1|DcIGtMKm@SFTMc{4M z)vaW{05ATe0?S)(6lM=GmqIVS^moQI7ddHc0wNO?`lv!hxd+YmeGjwTk(;aSndm?I z3pZ`^Z{BFl@NE)kD`#65?4_ZmozZq9wdcEb|LDl)*_1F)&X&KZsh?c|7=)lqc`Dos zCgvdoKv3}vL}ela?38z03%KPddz1-0buIULlBFO$pb_R&sSN{y=em*vL;9FEC(Au_ zGLtOsV}ry}*Pgm$jh6+`NL`B5#?S7;cMYB6B{|B=?=f#umV4X*6aVm9=TEPWL9#7r zQh-v9o5p7bf;?woO%g9_JMX@)NSs;;jlXst>^|Nw(el4&`uu7y>;x@+8taD>(5PM< zs^po;`&!9a8B~N7RvrcXcPxvz6VrwR1hPib`1e1xcMqxyd{+NN@sGo@E{LOhzS4e> zLc}{EbQ44kx$nJg#vm2Y6Hu!|M_;A+A!*|QW14&>sR=!HJ`LLLj;KFbR<_MpBceu? zx$Vs&3q&xM%vF!P;%*7>l_OlPTJ7y_LObKMHQHQ+cVqZNjPGNAnVj$LB0Iy+Pj#e& zxKpvK0?=~O?uu-|fsgWYdeM*n`_Iw=R*6A+!u|8DFZ3&m!Hche0->%Snxzu7bB$kT z=a0(^nZYOVRog5lUr$vp@w~3G&M)_t+mCLAVsE3D5B!sxE)rv}d=&d&;shtk;$*$V zCx+7}hI;;Od%raC8@!E4y55m39-$E-A-+XYw-yT~+j77c3faXcdlWHm@u(;4d#Wag zujkREKM5-3pE&ETyr0Ats7$-)HjY=3S{5ehQBR6!gMPI3W5dvch7lV#NWFXw)Egi= z(f8#K%+rbHoh9enV%`BY;_!+3Py`pQhqfG-o#XJ{+Y*&r73a(N)w|AfKHp_bsb4ha zG#oo)&bJZP>XM`RQNf=bLNo9#agK}kD6ed+jx&H&Jde`kRy&F~ZW#6_!B&%DJs#|w6ai!t47xb zE;lS?U4LPls!W>fgaQrhmamQ5nO4L?O$c2Xv&9ef{jkdYlXio&zOK%3hyQ?~8J1XQ zq!V$4Rh{znZ75VjNVplITwxocLEFi?*_G^_tL;u5LaqX*aNfS`t@q0Oo55BThpT=0 zE4;PKb<$-IT{*|Rwr8F$9pPdqkP9IE5#YE2y-Wy~F`zn_@0j$tIy$P#_*Tjn!#X

      PVzLDN+>9sr?L5}3a??00Bk^qQ) zgtYM=f`@F>RGxf3v$D;G8=VqgM5qv~y5+iXkUAn@9rQp$yqdsGBra%WiQ zMd233dHhsg~1D*-mfIlUGh5X}vYmj}RZbi9Kv#hl9A%IhOds>4?FqNw$ za569w)7Fn>+#g_%A<1*V(n&} z%dja4a1ru%`HpL1h_W|^IIfSDu`LxLnO)S*7ae%}F}atSfFsgkaN({dAtu15f{_*d zp@}lXdf*`PWkI~1WMyyE^sA89ikA5)Z3=eSMW*;uTS*DFfk3ZwQNYuspgII*la3iA zf?1nUVWlfmDhwg1WG3BGO@;jlXfilVsIK@&I~KbdNqqFg({ukEU?@#?z5Z9Ouq`U- zr-9cwrbe@gZJytKN`a{W^H}n5y%PC2CzR%77nW%_URgj7 z(aXe0G6Q?UK0=32+Lv%(*{MREYv2rF6O8lC3h`C$|XR#180h9^_Q)Fo318xQSK=l4DWi;auv<#UK zn{5eQpt_$^3My!FyNA# z_cUAYeZ@IraQxkThGfP|7t?k;0M0}u^pfR{?Gh?Hk=irU{q~c1d|WdCU-n}xG-`-- z>(T(esLkjbR|tTU@h*dXogiSqG&HoY1}h2btCk#L?Vq=D!7Mg^m{^SL<(11IA%=mn zSHiv^h9l%+7ilQ5^n+1Jvi)qg-Nt5Gu5BgQ5tO#bb zm&Afz{#6AWku}HKl4q{pmz4v63j&mb*=;)=^A66F0jx**0vuRNLXX37FMG#D%{8Zq z$~basz7;D;3o&zkZLODxb}rMX361P~fsO0p(Zbr=l`9!+#Pp8E@>-0Ca0Yh5)pXha0N2!e8l4Q7y=T0>4o;W%X?N+|*GI~>j z9bR|C*1H-N6h@f~s@0{PrW}|rH)u{RL}@iyU<>PA2u2}cHf%v7?IF{f|$Q7as-G%_*D#=CV*G;5#un4j9nuC^7otD2tsD= zN*j7dgu#GQfxc#-f4mLR$lW&h_YqU4KbYx}B%#n!5@-R}dyQS~{v~_;fngKdiBe&G z+bfDEV>`ws?(XC0`y!tlSpe33TYT3ragO84L?)`@J+%fo<6LK~Qc|#8{M^$?z`Of~ zW+a>`d7yG;jr=s^ZU}V4is{ZkxHN*sj(#HcQ_m4chsD}QB*Hla|JTPEhtprVD2!gQ zuWeCJzi$R6MD=fPqNXX3*m|(wAHr zo>2vGka5gH(Mts;=fSMe#+@SKIX|PCb*8-O0Zl1seLIA0yn9eFAou+q2eeWW4E#b` zsT~YQ{IK_7X z##PRCKs`az(A;x~;3l-fyqVEKIQ8PSC*=2r?C1gSTzN0o?{{{@ zPilM;%3~&`VA({bvILT9l;$9Amvlrc@aJ4VL95r8x;&F01W(qO%gm{ zv^dygn~10`2)qMK@6m4SkDW6U%xlcjIr0QMl9R`;WM|{t6TmL023Dq*MGq`XOlfa6 zY#9Tw%!-ab1^JYSRf%l#7C^_s-#-cgij^)%rx*vb(j+p{px~iBSNJ_5oT_M`gLX!+ z!9>h?%PHFkk{eLbR+=p*(wKB>293ZH6KxB_ZA|F5&NYQfL`S+(ApXBTJ`97m*gMR= z{S+9G_N^k)v29#XG$Q%%T=0$>`@%GJ)a)sNC(JF-`+E*!TP$>je->?6M6`i++_3M# z@ohHvxXb$)cTxfY4k?zp8<%^ITUpOl4$PK?A zWae~mzVWs-U}M$`rt&B03HfK=6Dn{HS9w#xj3jo=gH`~O@opZyH6#%$<&?B}b-mjD z`eJ6g^zENt(*R(yu)!KAFF$GyC1l=BYB1{&dJRjbk_&G&*e( z$>VQsM{qT6lICfxIrVHV$ACjGKaz*_<3Dw&Q-v;mA)=x&KR5N@&KR_7Cm8QW9Uts! zu0-7Xf{{@>af>jGcJBk90V_52iDq!T0AA>?!$K$|GL-yX@ERgEM68@vBj<;RQuRYG zF+G=UD^?=5VyBzz1!3dW`lHg*j8mUnKRn<)aw{0Wz981P_$KW16y5P1D}pa1H@FuB zm?U75h8N-J{Aoz9W~S*glt!VKOd}ld?npoe{HZyr@utZ<8L$Yx zAi!;I4(47n;`sI3nt8vMgg9PG#Mmv_nk~5s^6?BY`^8HMk!)3Z$7p==`Rz*Sp@)yy zM)q}pyEUUYioBhWX$u8qaB>(!v3R7zu3n8dCl}UlLmG0)ylA_cOg_$zl!2`X+I~A; zqVq-^59>uYbdKWdzi^V9;_fAOrleztB}M&_xA^BE1U%&e`r=)Nd%~4nrDGS75Bp^{ z&(GY@Pi~OJAB$!Si5Z{|VwQ>;zEK!ig;*CK;=o)cIq&k%9w=E$f|6P%Ne#qP?-S)n z2YF4lj6CJX5PdEbs>Nq3ld>lG8fec_tNINi+JdHgGpyJqP+gznF)wiCu^jeHBI9oA z-Fe7ibc_P8Pvt>eOz&NG@gY~Ufgb9VNvA|pAdx?=4}ujd6! zRI@hTFVubFpAy;fEWGzXB1Wuxqn<^b3%hO6yGcY_IQ3|TU9dGcbxC;pP3+WgD$PF| zCqrJ;B#OCx=2xl4@?e`*JKWlv>rVss({9VOqt%X-JyBLcrciZx=}Z78$(5gznW0%F z^RR;D?O?2^SQc?stJHtUf{n9dHI-k7UZzJBZ9J^?7_;(TBaSYKVLq(QxY@)V`*S$l zO5W!5C)Z||{O9viE$zY?ZEH@*F7Or#y}7Um0S|8Ty@+9brbpVLEUGDY>6@n%_wyfX z*|E<~$&e0Cn#Xuhg1%1o=7Y#m)|v7Zs6u(<_EZ53+?kUQg$WRw*z(4Py7`aJc3ytz1mKj$o8!6qu~@bn(U8M zmwWrh=D~JrF}i8sj1KRBi;x-|i5q+SQvp2pwV9oo%XY#viB=r9W|%74!u?CK{muPw zAk4=>RRH44PV;D)4DscodFVJEkMQH2kMWS{3fGZH0Ee#bVSx`h;DTY+FP~8_dd-&F=sLNX~wjk zQ+`SsgdPvJq=kjT+Nfr5(mjsS@PVu?Xf=k>L*sj)E!ys226JRA;VTgEXlAVDQt(6Q zJaK#`w9d5_rlrCw5aro$fiKmXN9tM++aHiU9^cuidt5xt{S7ieCjAP%@ih36V_SDD zDagK@o?`$=7Q8+`fo&-g4e(d^?YYd=#&+sHHsQaG_igh1+~u{xgLNymw_$-R_a~$F zNnjD0$Dp_ASxVeQyy+?~5SIL=tLit_s(15@wovKX412_@F+6r&kioApJbGhzHA*@Q z(C2Rg`j8Rx zNgom#FS0aOHGUGHaZ```X2b>zeYQsq)<;tj9D;`@tRdgL2(u!wsXdF2H7+MFzQhoq ztyw2|92mXkc1vGlWpP!e4957eMoHp^U7yW6v0gd=^>k%^P~U>lL6zjl-gxDSFVaTQ z^rgl72eC2p4aMCx)2h=jd7S=(*v&?IRpxW^iQQ?y_b!gMH5mNKaFBZ^T5DxjN`#m9n)d?(9mvV(1J9W#AJcp3z;z#0ACKT}(ZV&eG~;va9flF|iw zUof3L-l`DIpeJ#2IRC#6F|&6G*>Gi8lehLqigw}Mwc$!Fe(F~k{;hb7$gbA;!Lkg< z67S$Fvo|d;Is>!)3*7RSMU@exOs@=#_)^#FtkiL~QfA6z7~s)(9MKkk z3phJ}ZhmwG6L(0uf1XHxeZL3Xu3+j0y#=!-TZ@JNFBA&v^$_Rg1Wx)F-?zLm!sp2Z z&MgU?jBWdYb9n?O<3kyroCDGn%07sKGMr};I0>gI#7P;-aGp)z+@%Py4{=ieWjL=` zoC8>-6xxV7(-h+5^{|$O@8r#V6S@v@-u32EL!37eqb~vP6nr?uc@+6q(9UAMG@HPA zJ%MvPf%9GhC+B?0C*LU(@;QP0=@LHgCvfuq0dd}p;AGppSc3CG0w?c95$9wCC)?)L z5}XecIC)=_IL}9Lo<#nw5}c0`IJwTd3@6(qanjeq@8S_geJ~u;5N0F3jmot)-O#Vg zdqYHA#`zoQk8b1oZ3P$22H)*~I_H*S;{GYF+dJ{T5z-rmKG}au%D>xX((4<2UI@o= z*KN!pJj!?x3>+7b&(+}bK}p$KlszmdTazmj=OWI0YW2=3sa+q=*`fmWv>0TXWO{lQ$AssGVOUtNcW9`pHRM)QqBH5 z|D-Q*O~netIw^Ez;kN)sy@WU!AE?X6EDOFpIfXp^ z24mPa(s#L`3Q{Zo6y`$P3Y?&zUY-IW*YfR(;2iUS#g_!9Yd;34pw9{59Q`iVhJ3Op z`vt2r+BmfPL(ILOgnZK|3+=wbBO2-xU7rz%^EV+*jumM?>NUiv-xHz~AzIN7WDC&!W0=NZrp^~u;l zKXN#QF}fdP9p{m5p-yO{lz)=PGG7|Ba&s5rywCe^fSpBI$mcBLXBp0237mHzLm5tf z-?a?qPy**Uw1+aBo8V9^+YI>7?xO{q)%^1U@DUW#w1xIQ(Gcf(;L7`wAfnxm7jQ}j z+sY99f&JJ`9EUdA1#!ysN&mWSp7&=z-5C**TFf%9|%C%=(dhVyp9=g%Z?9)-`B;aqKf zp5UR+pDp05=JONK2|;Q55a)%4ILCpr%;zr_a7qS!o^vylJ?8UUAx>HRWPhnie5so3 zM-qHqR)p9W{4)`ku7h-0+q{y%c_!hXcN6}3HG%U|0w?FT%lN#Oz{&L+W&U|9;q#LT zoVyY}&+jFXPlAX3IhDZ4>*pN~IaE@93q#Z+j-iCipf?f>godnJk z7AJiw#L0OEeycTx^KJs?QS0;PBYg5+;++ycIlj^q`qFyq^EXf-o_@NKF9Me<*)H3s4H6@Ufa)Letk7$WC~^23SH{`f>4HYbQ+{1 zfDPN&M%ak9o&46^T!?cB^@lzwupv(R*f7dt_8Wx^(|1Mo5a%kOTlw>GoR@)`J{H`Bc$<0wMpQuGtsUuUQ(}ZwfeX0_X9XIF|#C38)L>Ys#o8wBK6P=e))MDujIA zL*D%oK9?i^i7g9puC%<6W{8uvW&S2?q3jz_ru0Ib4+&&bi1QKP`fZuu6b5{`Su8lE z-NKEs>ui<@PJv_D8sNPCeLN$D_m78svc9GeXOT~bb2V^Me%Bs^7xKyZEKQ;8>MJY{ z`Rq^NTwlQHcu`sor{qv}-t#Ww(}xTBeC!p5e6F&5@_XF>9{>RV|9Amxlut+$aTLd& zu9oKCRZ~;5P3WIkt)wKhNHeoDvm-O}TW4m~MQAFrRRSqWDafcx6ka@fscR)(GU|}% zDNo%xbr1>^`U3@dQX=TRpEHhAyYP6szxVllfA9C+`)w-}KpX(h&0N|jKwpT~f+i(J z*H#5bb}d^466iQzM!YJx zOze{-rwE4dcl*i3cce#2)KPpVfs`g&f+eN0#n6L+SIs}>(Q&ZW19uQt6l{49jH1e9 z>)Jyii8}R0#S~@BE`!_1{1z_0pgmhCTNT6F6^u00kO`m*T#lLK9iRlt3WO!mg7 zPI*LF1y2?$;St6rx~6pMDyc-#0u?c%D6&<>^T|zLn|<$5RHT41GDFqy6_2G4^zBeU%Wh2DBji!K|$fW>q(14jB7+cAx6*{K{VsjiI7a59d)~USGWX ztrXxpT6IWK!zLOHFp7&yGn?y&u_SG1VTcjb2*(k6J#ylD6MA}i{eT6jm<;{0j9 zjP;09s=FyyGt&A&jz*{7uKI$V9;(WwD{3nK^<)fJ(FK*iDqld<9GizaI=j1iTlw2s Ud6IbGs}$pxemiUY1pom5|3m;vC;$Ke literal 19071 zcmX_m1yEeUvNj0;g1gJ&1b2tUAp{NX?(VL^gS$I{;O_43?i$>d1s3P$-uJ&(r>eWF z&(zdRpPsKz_cRt16jUYRrw8nW;Pa9UQ*>Bq_UPSrlb-kmM$M-kz_vqcZwdV|1zkfFaN{;L;ZjJkL>a3+}Az| zThmQHXn7@)*k~WGx^`1$t(`Gl!=u=J@-pEoGV&&W|I}^VuuXNeF^k~LnW0(6Y7V{` zu4b?SjEsh;lRv4F%r3N2oCGBh4PM5F6eB^~P3jU=qZeb#c725!eyhQDX^5-#@1GJdzGZ*Dy|Wcr;;#Y$kc!kfqC`$><6& zQt+;?BcQJ?Vn{R)kNjsV(V;q&&GS&P35@lfy|;&|u8Y5vS-Cgx#?QO~#bO^GS@PbH zcOWPXf=)sofKkI^3J}(uBn41|j;vXTBjAS7y9=ge;|;2DkFQDK-RjLPX>osLtE9GB zdKIthFx!@VoYF#H6#o)?c)R=eO98S$;z}RZU{zm(fHq)qzO!!yqciw|PYXpqg>6`( zj!yQm21a>H!kbZ_l3lyqc12~#k4Om0H^+Xc$t0G0H_a!#8+{#UBMXV=j`3afKpeN! zajw?Z2t5iOym=K^g8p-K)a-P=EcOTU=CAU*irSw+XCdY#rf=_T&y0D^*o2stcTG=R z9?jY47L!WuD3WNIg&0!Z zNtO_wj)V$c^@6r(5;3JUz4%R{Q@+ zeqev#+`sZh>-Rnl>n>;>=`_2hhh)@NA9IT7&ss}%6)Yq9NI>@9_N5W2;XE(4)}iX- zv)4Mkm*2jW{3xeciOyKDsVR}{W=p7f3p_YBKK!O|UA;bQZyc+Jdyk?D1LrpB@Mo>3 z3cnJk-K<9IJfqgC);hFounNBvXB|=HWd7vTU+2(2r+XS|$iVX4?@oqc8S-Vl8STsA zz|{0VvThS^h~Ti$i*SF4>3AsO%;a&;&hpnZEWhYD>D}e886QH;e}t?LVMcn_yO%;P zSRCpd{2~O8H{Qk9_o=w3uIpWp#TcpBrwCL?5FwH zTlYBanlq&Cw>~58`e)&89{V5dZ<4>?wcohc)SThwl zYrnuYScJ&xI|WVrngmUN z>m+QsmZ<6Z_i>)Jf+l+52_S8RDOk&iP*A_wA%8evUh7=+ICypr3IBl&?SgC`iw&Y? zVw>W*Rq@K?Vm58CwnQK@l&A8N%J?S4NHJer;FjES9=0v;cKJmyopNZkVmv(Ex9+O0 z!#L#-tGs)+;Y#1|nT`%UbCWr?s|k8NzqxqpT^NrQl4@lmER6wuShzoLKmRr9ZC_82 zkzNqw@+%ECb5PPtIoIFzAda&q$0I2D`uo#e$_`mCKpyPXI_Lt|M~iw zpZS)Goy5j7#)EJ`0|y@DuT|v|Ni?0qf9f$K5RF{=HT&H1Ue~*8&Opli z*yM1NR1b6csnG~=EpYu3S5SN8dy^J&!TSr|!6U?2EZWobv=a56D3|Ydy^RqsW>|?S zUejI^fX>+atE-lYuA?VVSu)3|_8L+-_<3{6@$_yyIej+AqU6s{d?KT#A71{7CN}|*+gR*(|w!80KW~+_&)a>66ZdXjk7xdUg z{E_|0B_$xuC zY6*Q$KiyRZ^69jHZT8Qd(IB0FdVCN>AAg!ej`e+Hr^uR4u^eS&KVP{Bz4erDKjy&- z^BoKO=T6Lf^BGLZdi33dA}PTyb-9VdT6Kl`=l(0FcF|(MddyM|`Y7xr{iPq_loBmc zk^(e=^TGVoz85cYks5>p3L3=2MHtS^rl3?Wyx_D^{Sa_!o~bV89KX0%v%{@u_!r`5 z*^GyELTUI*fWOYPb19BgHjGKY4>j{d&E4N}K&>av0G+SK*Chui=;Cx}RzIerFvSZBS5_+0(BUW8TJw5Y_E zFg!V)b^JXSE&9hU6_G`rV72$tcltE9yoT2F-z!_`IKS9xWcoU~(}Q~r<23pJP94GE zqebH~_xvN^@`khDy!wJ!0%~ST|CNu+1L2iF%3XLws~=rKPid-(1Z4r*v8tpi4J2P? z)s{LL1io;leKE94U38}vT+vc&kPjpqPXAXr1d4S7_?y4ay4w)yQ*qHsj*F9oeUgVS z`w?G8_9MVItJv(7xV;I-%eqb3%X*`^DMe*zgWGue{*m_no&(Tmf9?eeA((S66Ci+7 z(N$*06yFz)Z?%`qJL*$C>eClh<=|eEkE8(ewEsHO++D`@E=!bSsApV{=L0ZQqew66hlw~Zq=W60Ya~a1{C8*v0 z4JmsK>mbOs0H13M4qyLX=gGc)HgLl7r}UIl*2Fj}e#$3O>!f0FFI_ z)M~6OpqIcjg`*UK?@!PvPCbG3so-m`cf>JepDLSdhwqT{ed^nF<2ftnbfP|<2AALk z{Q(@v#Kgw)G6e^a@A9@lXqH3uJp|92?TW;?e?24Fg7!IuZl#jA?^ZE}{*iF3rW@UZ zOBU|SzbElkpP2qh@gpg5}z6B~6 zCUy8iazz3!o>e;6-8cX(exKyn7;@D8!va7cuK}azDO6@ zLG24jPi_oX0STZx+eaQ9r`tz37_>>8aUT&c+8qbEO=~rOZ?>Fn{+O_iI7Sa;gWDLQ zV8#(J4q!{?ElZ6%!t^JJeJ$3-{lOEI;-wf^oP3MnHeHDBn;nU)wRaLkSI))jN-LIM zGK((w*?kBB)~M00a!%zUdF!fYMdB%Dl>e~N&%-yGp?)LY8EvEHGKIaK>%YL1#-|F} z(WfHu!C5Y7gU!Di7`CPtn3Kz;YMJ}O3ROgia$6E0K$v|^I> zXZYULg#JzgmNQARePRD6TKPbK0oE4hTCNlnJ8SBlymCF?$jx@FEu>vavKU37!?{6H zf)ttSt;PKP>Dj(Gbw5`UI5(!z$sMGj*G3UIn+P9eR%MqLR~G!r-;PTjH3Nb4d>(LUl+OKzxn+ zITCPGHBR^3A{`NW2S6h~xes@W&z3GRRbMFh$)NPmx=iR(9l3l0Z|97_5MM0(Mjn)D zR<)nnu=+!Aj%@Fy+clJ`c<)~)AJQjJHddtI72d|V<3e+fDXW;NF2`GIiqgi+5qXSp zRbP_$psz^c6ZJ-%nQmKipWvUD0J$TU!f_d#rAg}zfGd)~-;zSPzw>{_{Kke+xtH_5 z+sqKJkiNf`YpG0F0spYF%&)95MY@^J=c*vMU{#2e&WPW=m`lE^Uf42oa%igfPCQ#| zndSg>?Gr359dyk{w^>C3W5!?g?}3(Rj@7m2N8(oP)Klqs1vluW37Iaf^+h-OwfiNd z8E?B}Q(kYuO8q9rIu|i^eK4Z_tl=x2gSo6ld8_S%Xyb%uyG!Bld7iTN8TP;7uKA`j zY2%gxB;Kfodl&nS!P8QOEWcU+9e$r7ojwwgi^% zC~JceE(|nR*-P+*L={jpSGH&L6Qkbj&p#ZVzKXA^w5q!DXx{Ut@4KbPLI2odO29V2 z=bEs z4BkR_Gm>GT({QxgZ;B`2j8@?~T|eXGQrcO_mqf_oTlgM0kHD>jBx)^qrHtw4(Ok~t zoz*d|RKY@Xg^BaAr00!61m_!IbZy^<+M)uB=3b+sb&G~uEkhMf3x2T-dNR1~RG2@% zf^SCgTRBPt)>s*|T*!w?yLVSpickD>0AiG(m3(ouzUuw)ev!^x2O*aCaLvP@>EKh0 z#MC4HI|N^ivalb#jG%s?GU0B(l6~CR*KfHMeYnx>Q||bW8RYBd!MXTbf%fnAg!eB0 zf*QUau~j)zHAqWE_tDv33|`NJO~ZB-a^kY!RaI~_&ag?>_;bIUe*XpO*2nhHu=2b z)EHGx7w+>X#L|(mlOq|Qcun7Dd2qF-s+s0}m_}P2TuedZ1jV_VuT?q^dCYuGw8D^6 zgpxpv2X4pWk3q=^rZrl@ZiUq`GdHZo*aK|;Zw`M4>giRtltKQ65=>8_IZx+7wlzMSnaH|++dpTk z`3Yd6gBuqYegZ`4ZFo8%UfW-loBF|3O8Gd>;FH@rSQp(yXMM7MP zKJOnC{x!5$nqem|ox=X^^H@gYrO%U`N;$GPbKZ_*Tivqgoz^!(g!0bu=MvMeR?4%B zc-5(U>c+n(ebHh1_OVtJEUcEyedbXL*$Vw-^6=l@EnBBOVY0MN+$<@2-RHASJA01E z=ebNW$0rpQJMyr~JOXEX%n>#houg-=Y0A#2JT}djJd>9=on}5EMU}Wm_bFPqTLhUT zWT?u235LIVqL@2N5q-7By5DXP*@QhT320aPxf#<=PE=q2lp$3<`+1iovkxca>+ZSv zd6oxX#JF1c=X$sU0baM&1tv+pWkU*@@vpoWdlGyq6C2gPoeECF;00+G%w;1 zMVtRw3Doh5Z-y3y_gQZm$2mw&`DJc=t(--e-;j$s`Q%ANwF2LT?=uviCaW1kHVMzz z6l!|cSeB9QV4{d`bxUAs)aZwq`d=6P0>K%@-aPnA+23Dh>m!-;5)zffra!Zr}97U^U>h>_n!F zZCw90BEp?Vt4Qau^t(W>GaS^IRjmFh{G^gw@9-{7)GQN9=hAbZUPrE-Yr}9;*|G3s zIcU7`JGMea^<{Rdj!u;eXBEz*(u0s9-0i0Nhs?k1nIKMWhudI6pXUayn(5NnBSrUm zHJz}H5-R$~vX1HB*!!GMNDCfXjlA2x%bVRtW0;zIewo)=PCKF0I(|ONj*_ck=cFW# zEN|8=!Zz+-)>ipq$;h?rUvDDBwOzo2%wb0BM;#C(!C3kyAqC$y)PdyoN3F}K;Vw?z z6=DY&;#WI#}Uoet*2Jc$2RH^urV_K22%HEf_~Mx1BFRb*COaSZS%J>vw1%60EbK)9{r8> zny4qT&XVYAOqNcAi1BN_n`{!*NrJHSS)6Y_Rw+2uSd`dAsd4i}L%tp0g`feeu*PR_*^7?W^y% zKhw2LXiwy|e*}qk;H4Kf1Po%3Dorn+??UHo515q`1w zDdlf=l&tYmqte80^3Xi$%7aQYKeIY}T65@9_#*a@ppVSTG(HB^L-U-c>i)>4T+NVa zNB(3k!Y&)JAdO{C?_joaPB!{~0n@o8mS*4;~l7UhD!DKC!vr!>wW+&G*O8ez{N`v`bv- zQFZXE4)y2gD!YDkL0;wHE4x0~ZCSeWY$8leWL2&G6iS!8PIqEm4%)?rQN~`K=#Rs8 zd@BeARyK9Y_#ZskmPQ`xm;aeve=kI43M_4+{Tzv#dv}{(J+||W>gHs(q5`>V|FPtg zcPc3MLHkrx^ZnLg;dA-C-IW$dB&u_D@)O-GjDQ0-n??j+wnBd z*SF{E_^?e3D3Pyg>foYk ze4({?Q*NSp@D^BQ62nbKUbRh@s|u88;`i9^S;eR;{ngORu*Jp!vyL8pWBgQ@mef1g{IZ$;x6-CxXuRcf>O<~p9>9%nRL?|F zrC#RhwVB;c7hsy;a6wJ|Y=t2=HR-&9XQnGp9zs?$b>J2cYjZC-V5?Y- zh%8xqBOs!`l5R>;06_;j= ztwc^1gQjZH*GFW*8g&hw!&Dr6dYgI_^yB`%x z7QMNB&mTU5x&+ha7I@DJ?SMQ3NZak1mpZ)N@XbDBK8E$^*h1aUP$+MNAFT)YZi(PG zq=j&Ma$TEdhJur0-F*qnVPhHyxd&NA4@Rh2XuFYVZs`+uhBUwF-n1b5-gb<@hJJes zXOEF{q!gNx8nXQ5Jio6TOu^Di%TGhYO3uT(eD{NEwVnv`4s@0^I#JswRHBO`#i$$- z>o2FB68lh<0qpW0y8+qyLX9Oy1m#rTW&FwTKa|Zh*(Zp^Exu?SNRmtuuXro`KBuQI zTpTkSxwkgl8vYA2MN%_s{F_G}`3J5X3n*yr6 zcnbm)@+{$DYyDuIl$zFPvWdF?II(jm6-k@lA+M-3D89E#x3joORK%{xQ@S-%Q_fYf zSw2CbBORE3MnpLX@quhoQ`CzhZ?dW;DgN8!toN<)te6~2OtM{UZ9m&`AzUPp zDr!p{lq*n3w+N_X|2#cb@qHCv!C$TDJdx(DVgxHH6=g3fJvzF5a>;L8pUVx;Tvl~2 zy4)AboV{3ixWcoOe>DB4m=za}E}S`w?(gN0?wbeM0!O^YuUqF%p|NvCz|_Eg>L6)? zR1c!>@U@@zqqW(yuIh_M%+WH3GKXpUE2b(6#zcYrBmg3EQ;j002xTsm(~*1IX(3)8 zr&lrWe>-@@M*j5CV8`haZN~~Awk8sbvBTtFqcc7p*B3A+;jpTSa(lHTk^kT@%rOoq z_IK|2D_1a|gu@4bHLLQnmNCgbJd|_C3_ent-UXB!d&st~;Kt)7qD|La8?4^1S-Z>f zzAMnGf-K8HZWzs_6ixSoKZuo^1`~j)1Ia_X=Yp7zHba|}Y)=nBTc}#37$Fo|YiR!o zb)4bYpgJBuqNG94Fqx^Ng>f+*@XnO5Um9QgnQP@mYJ42i4ZeEk1BnD5>S?NSF0a*? zNC{1o3r4EnU%4`$7z_y;pjxfCdXNgt(2lCqaerU-JoE6{CjUEk^FKdf{|Ac42sIjl z?E=F6bl^Op@QYh%h4vlW2!vd?P1lRWD=hxHMZIIjw0~oe)+EyBig_Qq2C1tibxz$p zCPfqL=hpe;iOx+YFAjI-5W>x~ab4eOGFWo|k;zRNEbW(4GmwswH(Gq>^&$NQI?!bY zaU|c$eNDQ+LMo{9qSs)%Q-Mbd%iR0k^`q*K$5h0yT~b>)ap~V>)IC3dfap|c|(scNt4vMQWpCPn!6^r z!?QYjIz8)HDu9!BB$Y^wQeAtItU6cu2(%KLY_Q|$^$FJ0MZ(=eE@p<5Pg&()O_{Bc znR8yNs?CMatnw19-?}zVNsLW)A80tGq~`QbRAu8dr|WL-%?)+?o}vlYd%73GGL7qV zFMto2P`y^{d%B<0NzrEyibF7M4}~yf_bC66-O`X{>+sK=#$UK7#~Gd*>S_Ooo>K1KA}8&`8=LbZIn9awHj?^? z&kWbtQi|AC@T=K}RUA`NDS*cfNhw#D?)jt7&_02)V(t?F>%my4FTS@){-hhauBJ5K{CdMu~jNm}S%A4qXYMG5A8>Il>vhlS#kFkTQS|F*?Gq zS=zanpe)6b4&|NE8FRzNrOxh4uc?c-*CTqU(+#$%$B{bi5Je6=P;i!Z$Kb)GTiel) z%aXxIx;+9464qLw@CfuZjBMY%DV{dHMqt!FsiC&bEf)!HsRF%+oJb5!9!7Bi~Q zBlKH&$*%bwZyB)(M0b`eyns7UL+UfJ|Fs0x)Hg?~!H=)5^$8`H%{qLXcQpX(f zpsnwQwf9w_ue$bl8g)!z>w&UcPC?kdSLC7v_Z`0}e?;1hGd%5GPS#0x3K&}(n zb~a0mG=_D)`mEN(gm`vjx>vf7%rW~+in9Z=4?S-=kY46vtIYFqpZwK#H zlnoHTG*&rgPRuk?c7snhDs|{cS@rlL5v;Ig!Sf8rLBxBZvQJv=ksi^iTJrYKLJ-ws?_ zlusq+ov6=j4*1>42Vl6I&C7v1+FM%FdB;MYxfgSvv1w)Yp8$WKi`BKB*Y3=mO3mi+ zl{RI!{RCg?Q)dc0ZfMB+!Z%ePx_fk>sjXs|0&&*%%?tZiiSdVFd++g~yZLKN&DGPD zN@bpx8NvPPA03-zf%9NXuk-GN+IeuPfOoN@Z>>rDd@0`%cy~c0oog0CJ6vt*@ZvT0 z;fWuNFZ?W*jmK~Od530v^e|Rz%6QifANZDbqL+UrT7J zOf(w1|M0fk7(Vv9U#ESSjkcEXwU9@`=bS_14{-cQx#?|TcVB;g%BWHb-*+KHbuSMk z<|B4$gSgBEnd=%KrUpguv(9o9QZG~LKj~dsVwmy=O8!O4&AoAe-Lt=FpxT&%oM4-z z?j~A!vq}?b_L~^3IHG%lvYuqgA8tKicdNI+tWQrbXSq}=e94s-x+O~FximH2?c+b@r1`v0r>hEJ8Yb-BGVMyc)R<|?OpyR_Ifb?7lb_KS_5vQ50YlmMO|C(BOq{5Q@f96} z>tLU4H6&h}PELsk_X%>{!LR~RUU+j1&w0KIwUuq=d1D=5wq2+DKaQ=1X_wM<2jZc9 z*r>+hSjbtucxYs}gAQkfSuaS9{ibf8{6y;f$QKgZ!B_Vj&BN%3Z5d7Rd1!YeTLbD^ zC|Yf5eb{E)5d}s5Z z)P$WosO5m&=|_cVpTf@eav3y?lf9Hc{6!^^5@BazXd-DNz0;sc45+t1 zTdir`0b7p|l^cc=iPU#H>KXlBNoW)Ko&b*3C;Q}|3A9tELWmh~4x1}IZ9_FM=Ia9u zBmyvpr?~2iU=GMOm`z_G={mB{pLRjYiwsd#3>;0EGe{iHJkM z6-mSE=*P6fMD`WXZ*UYfKUc>BHT6qSNEz*h;#|Oh#@WE-)&=F9++f(r;AP-N9OazO z0PaIH5fI`AjA>3XNpNZVvT$+etn4bS`Rk}S;A&G?S`<-&HXKqsPk6L{5!;iyGxR!x z*un(d3eJ$WIfU{Ut94Cl?s%PUFuz+kMf{lk|j)?wG=lB~% zDdGaSL6E@V7uS|JRM1dG7K%a)Uaqz6>%MvJ+u7C3xDpQ|g)^`A?n5QJvW}<}Q|Lh& z$MA*3klet1bIQCjUuyn3wTuqzE{Z)oTU37H%9nI4>+0+*QQh}!z@F>;qX?_XHj=`R z5RSo|&(>zs)-{ngNEe=nBXI9nzW4|ugQmQIi(o;p#Z(~mvktekGG$56-))o`pYTYf zy-=qca2(;!ky!?sBe$6YlP|5o9Js=Xn2M^FD4H2y^o(W^FphZn59iE3p7f$%6pN`6 z3#H7ODr-Ruyo=VwxsKlb1FkY1n=KeQ`F^$J#9Zb=!Di@Q;h(RQ&v}n|uyS1*DQ(k|7C@-UFis1*Iu3Jkj#ObVtHr%>D22_LWFR*fEm0^S z#FiMhK0s$%j-z~YW+^0*aew9l=aMz6SHkEozpU9D#uM7C?vy6rWx+>>X;M4<2;%RE zM-++`7V%}#kQ~u9Q|g^NB%<}F80DtBP0&;`TCTHXFo!J9nLlsZno?~aD0uwnCwsnH_ZgCYqSp~ zI2K)7kR0kfBL&viLP>l1Er(x9!0MY_jM!S=Q>bpd2rpJhIdy~ zc*gyCVm9Cb$U#uU18iKb97jCz1C0_kT><+Z9InMRGcF#$ZifyTUUa4{qTrva1`k9dBlXwq3^`iJc8!MTq2;i*1`3(wbKC2hgLzS;#8CSZSCBeP(OXIfdv4=6FsLjgNVz_eq{nom5&jWz6Gg7gtZ zdEh!u3iNx~9uC1f*P+Em093D^-S-@U2I!A)m;%ZRx4bqqu)>h8UYbcg{@Kpjvlk|* zr>nh+lJ>RW=Nw&&5Ixx$gbXiM5g8XIY8^lcNt`dc(08Gsw=1ZpZqNB;j6{!^L$P&x zr_1%L{)lGW*FBcQztb7!sB<1V&PNG}As!n#PAqHZ1W#^N(z_Yh-M(ZoRk=q``uaF~ zy1`koEY015fe|PJ`z--@yJ>+QK5s)*V|(XLFm(p45oieKY%vKwO;UQnmoB72Yo`1t zL%%pj4!FbQls!;Q+tb4a1kq=ZuiQ84-d4j+2XEC}4v+wf0;aDJ~dWRl9h4V(qff;;eVjU`!gObgzh3^58@p`Do4@Q_`*^@S51 z>+l_g0-kW6EQDctfkmFU9@?P0(&rt*HB8l!uai%>b3|h^Nl2$hB{MnAB9W{F^Sny&RxRtRlLiTPGg$v8O|^qVacTTsuo*xdAwS}iFMz2 zZqZ*WFTQ&)J2Cze1-)>kx5d`qP|7N6gNv3ti z8t_q`4)X@nTb=GKvIO%J7UfRUBGy;ivJuVkOgJ?a+Y?t`2G@2Lo7v>vxZn~FTqwZ| z)s4jpi1{JvX&?1}03IqZ3V6CZn<8rosQlc1yTonD?a5!fuf3up)w=ukWkO17beS7waFzmit zVC}Y(v`gOl>47dGNxuEZ$pGwb{&HLetGE(hprUE^!_UAZc~T`^8ol_EzvtE+Z-YZs z%X`(jB8HT71L*a|oQJ9frRvR59Bvl?OG&Y+sgSXZE`=RZs?oD&cK`uCy$_0N#rJvfD69#H#Y|z>cYx;HIzwW8L0>dIukSE zhD9EPJb^yhctP3)U8L~JZsX+jeTbOxcEH@ z)EDX>&!Q^WWcyZduq%LS1CHtkki~nbz3q z_PV-iLU%smGPkFdL(q_EG1-*!Qx zFAyl?IquuEeNX@gcc#l-g|f}}{*lI%yq2`qUG-XoEnW$!+k;<*&xE!%J)_!q?XZ44 zr#M&gUy}}Je_1MTF5kY|yU5A%TPWFI3u|!mJv+ran>AfX)(|w>_F#lLTP)P`dHUI+ z1fmsC>#o!lys0F2t+&&Sm`@7(5={M(YM-0ZoYFjoLJWO1`<~Y-=7a0E#$S!3l#f(X z6(uc(OyRH66R1xd$=p0pGk_{NlmEmGDFHNY`uxvzN?|loH-NEGN0F^pqp_;e-&q~Z z_CtiiD7dopf~)ma3(@fTik(27cTgACJQp~(s`(U9Yb~hpfEHKD#3@@B+L z7GvJ%9kW$tjonSgJG>q##ZA!}HK4flekDwrwJA2synAA3s>nu{w={3(4SEFzlJ_UC z$@K`zog@F7(%lmimY0VS+@r$tNLT|`=;dk~uDKt_-Coqv@t`=3k!ag*`Spy~T)zmF z2HD{bJs~ul7`SQCmCOg6ds-y6e#gL>gm(uW2UsvFLNy!70iFa%G$ZpOZI^FMCBKz& zvyO~#ZsSXar!jYO(6geuUx0-2cV}a{j93HQ@**-R(4isy1+t zCGzGuu!4`rROGo7c{Xz;69CFEMe;E8v1>}sFho*=p;KGZLh#M^H3x-k@)^cS4|FXGh>tCfJNzW$j5G}w0`ScEv9x0*f?-h_*s(hg)ZYL`g&plE$VT64Za$83OuWikJCJU zQFGWF8E(Jab&Qik7nsX}vtfYag8t9h#4+)}PdwpuKX2?Al-*~WzT@UtF z{-h2dw-`P_k6f0B;7P=&^c(f*9{e*;_mTx0&>aE(`PyC!5`@=nfv^u|g38k83-Vpm zAeUPch*B71m(f=#8ue)XZTt1(>uiZ^J0h|K#LYc9+GRKg1P4EXs78n5{E0J*_y?6@_A0IaTwewFWXHW;#M%_;K_?4p|&v1I~tE4oIh8HwWG{kTVKD>dAji zhSO}kIYK};GdJV{Hq$B)kseX+Ey=Cqq^u%RFbqF}MIG`k4^MHskPu+ZGJL&TajKxz z`({>UQ0ly2Qz4x2RDRnM;opJ>sX$WwNY46ygZ5lb61$l~j38$S2WRfH;#BMB41R$D zy8EnV4&?6X)~0|9lhi<(=uK|4j3xVn7$`$8 zLB|jp(A=9L@aU@dSjZ14sr4M-g9l1Mc(84-<$aDov!`%^%@cb53Xt?;n6|#9{qfhK?n!VV(AKj8h(<$**%!jHR|GmeRWB0DD(>hQ z9b9z<8%f7AzI^>6l;j2v2y6*M^=NdHJ8{XCtRWT`uzkh?Tb!Np1^c0$K3%=wKB*0H z$wS7QfcgRKeO&3xFhs+Rhk{=mSE#pZf~#L#-E7zm2l4vuEWU%QDy4>ZGU5&ehQ#4m zp~CNoKN7v5l`sx_VYgq^y;Wo%3Eu4|AH2fStL1M6p46gXbc>t*W!8*nYA0Y|=h08< zq>p5;t~zFxsKIzJEemq}Yh*a@@tV0F5bpmuWBHmO9Zzn~NQ)2@FMJ@B1ZFewF*yX( z?Z*{3ZfZSb8@H#$S|}9P*I4p28LpSno^J#Cud)DCItMOy;r9n&ea3C5bRy^d8aKlD z07fMU5x|k;KRCq&fx_;TdF;#4sG5a>-K8 zc>#xB19mxCS@kq>1z~>XxjaF@tQtjmy=RtO+6EfYz8)@-S%*u9diP1}Cb0KoEubUq z9iG39DUH8kZa7-ReTZwnfzY*EZKj*M;&PdVW;MDEES8r+dAOMt?z;kg&wtD>?oMmj z?j~_o&Zgf5?`i?}L^Njulyt14oR|=Kd-xM>h6ipA>Bz@B-9p{8FEP@iv`}@|E3YHL z9;K~GUi8fuh6FM#`*sOKdYP89trkq0O{zgCoRm(E}YLgKobd8?eiTU0~79 zKW98riD1`eR=6fiXWcn7X=ltPnQXje-8wLF64SyfnTtX*806OMshzqcC|K<4)uzud z^ZGOO45*#=ypO%0OCEUldh+O7B@BT%&biz^8}f3=Tv{)ExX3H^yVgU< z+nkAgxX)rNHRjP6N#pv{j_MIUESRdol3?6s>?y8(7DL53ZhloL|L(DLrC~R>*j7k5 ze#f7h%6^EOc(flEcx%%PE`W9|v`;fhiO8JdC$ooF5e*xDc7y?E);g}f<&_lxuN=-RVjG| z+u=_uS5^vz+Pmyzqwl`9c=lZG635G=b({{hj%7RiYar&+D~?O|{9s$G)@HSoOE>&xu1oD@l=;xhWB6rOJ7D1XdmHEBaK$Ai`ewBl zL=yLG${lU?il4kqKj@OCT?4{q9UVH`;cg7z9+&3N>~nkjbg3$52<3nXUfwKh|0dIT zMOwveh?2ou&^}>Yhq@hVOR}G1XL|-~5a8;eJ_oari1<2nL?y{ue5SSum;X$8$Xgl?MzU@FZ?-j=e?bHwUeg(dJo@sM_SUS6S{Po$s~$@*atU4YJv)OdnzhuhC@`zu@g3JpmBvFAkXUZUwouWN*l zo%i%EJm3?C{nzQ;-hpwQGqk-;+Mac_0QY7nd+Sd*?|wUqQ@x)%ykTBo5w0(BckXa^ zK*ZJ=qP*PN0)2q=>Wv@LPllCYxLweWc-QS7s7Ib1){H)Id!7&GXwJO#EltSVY-~U8=aRq;7|ue?zDuqXtb*ma1~7yGm`}~ zxk{8#_yg@Z?l9mFFIK)MI!E=vj0t}^ZIQJ0qij8tJ~U>J3^?nnH8M9vk+K=jC^ zw#4A}flyr(aP+$+^1P@aF0;9awV!kshTI*KZzcD;M{Er@Dm>`Hx=@Wn`~L>A2M!*+ zi3&9SIp2JC7_mpVH+lX>`+6B=dDSThlvCdRe*we^JN6;VLtLZXPGk`ZaJhMx_IAiQ zp99+o*g_6$M+(-Oev~DhobGX$>%TS$Ym1)7V_o4kZ=eoFyDY*<53yYcVB|;mG1%== z1jc@fu!|8G{Z80S0xPnM=n&Vh2+t7Dtc42Wv%kPDj3ch4or0|4cS%Mq9>)b?JFyPq zKyn`gUf4g(BL*=wWZ>a9QXauD8vwgwXgfcst+xX1U?M==F3oLbe22Pn7i1>UcKLQ8 z>Mek$1jPBk}o8VQtRC_G~+@gSP_y1n+C=#`cVD$OgQVe!*y;_7P)#7+Vas0p+&= zb~^`eJ7BKTXLXbW!ReY}sLjID;orJWG-QO*Ug{)O$tJaE`n7=a?+wV>T%F#33k`uRe zbDFgEHWWLTBPZKqO<}tI?bb;+so9iFrp-#PRhIcc^w?%ly zsmWiu4N0=i!LtDi#}hlPO%5W!!|{Z#UpSsvZz~#xu9@#Q>_vw}+%arbXx>09U9s|n z*RXycP=zMPpKP}dVlOnMvNFCnUShvVS%s!+UpPJ+$AceN(Wr&G--Ddjffu_jegIyi z#}vx>2yOU0@MxEiCfjk^@)2Rdx2gCpJpG1I*f%nExshK8lRW)re2VVzHd08?F8!d# zwNj%7H67Oj9YKk2{gC>Q$3pU(>Ad;pyD*kXQP3;h-VyBML_@7XM*iN{NF zX>PUpa2LvX&hnc8ETqYPopBbEa}edZ_QlZ@<9i|!WNAuF5Vi=MAp_BRBqxlQ9X6jk zk+U34`hYl;DfCf;0Gq1NYPs*4VOT(U^A>}PR@Dc(Ht$Hxe4_lkLDH3N9NJoTR?LGZB`!5 zCD@9v?Z6NH&T*2aDt^BJdc;GMovH8BN)Y=hG&%p7jwK;Pzn{p^lnmCDV~7X#W4CY| z#?qkGJr+yMyKVId{VvqyKcvZaX%L_oO|}Ia0cU$2(!35im2OBApxpR8sYuv|G`Z#= z&+nHC;`3Ai&9#Vm`rK==Ej-~S2PxhCZs>nH6 zAm=3|hV7W{Arw8Q$&@jTNEf-dwCV^34)cg^QMq{(Z5yqKT! z5Ua%J&H|eAHEHfBpt+EtDH$+RAKL=PQp}zlyU>=gn7>^>^OB8E`Z2WU4C3<|_{C`6 zDWG}7(j1NW{RC(Z;2J4L^KJo6exH}R&qU-rgP6aQBPYjKn!;F`urYrV1w!5D5TES( zi5p(W(I!eWoXcAW0PjN!oY!1($b9zUE~T%>W+02kQ+RE^g!%PN(2*(Bp&z#7`?LuQ zb(mt%AWZ@{tYgREBkFPcTiI`i^8M9Y`vo_oISra)fXDoI0y^CPLy;wv6PMq84?Y>E zc?LAeGe&a)D2q8XS=S%t(7Xy5X)=ZWV_SC%HalkEX+O|U=OZxYlO{LP46o70k;C}_ zrqF-a;CI?(^ix^?35NWKwq{?Dukas^v&b7!#)ipYVG}n9eA*4y)QkHGlLfr=eQ+^@MB_i1r(tHTKjTR;}MF3xK zf`z8I8KIe6XA>qg1&^@Jpn3P(mVwEaIXMQ?6zZEnfRKJtK}oEr+{++3i$#sf)*G}jf-)Nu&$ zLOB^P%x4N|J}JKGV zRmf-%TK`$(CSA>0BxF zV&HY_j|FrbZ1BKc#1#cw-Unl-GS$BR$WO4|<92Rj%8stt&VGLJ*z(pzU+x%w8E|x0 z%$ibKPPs%SgG5Z0k~=!P5{bSt=tb$TmC55(xTPBH->t+J+*-~nKqu0NZc7rA6Sv0m z6Qft-;}f?JKr^jGdZ-VaIE+3>Lt;ioa5Pb;-l&+OY}plX2btf(rI)m46J={cdnlbs zn8mdx!eW08y?=6`tFbD0fRU-b#Pn&82&>@9Vl_O**kt##PF*FHIWpp5KrEquqNkzd;tG;<^rZaZC*nK*HEJgd~VqwlYHU|1`qDE06HLn|Za zO5z^kPsUEiSq4YQVOGO#T9h=M8J-Ns(y;k<6y`AYY<^>n5V9t;Ap4=5tqtW=H){?W z2YGg1qIWk7*F$5ds5HU_R9MiL?tLl;SVgN1DQeh6qY1`vad~!oqXkP6LkmNUpk_FM z(3{bdH)81N<&h6^qq4afW_gdb1=1K624AgSL!bW-r^@WXW4w^fpEnkfEKnft=B@lm zM~
      0|y7_@yy$;M#ac+0w!pzl@EDQ>uF@S2HsDA&%C~yj$}HyF65tO;^-Z{OidY puA&Pne^tJKs5v$db$0c1_qFr4wemFi&{rwNF9UYY_zM64|Np=4C+GkG diff --git a/CPLD/MAXV/db/RAM2GS.rtlv_sg_swap.cdb b/CPLD/MAXV/db/RAM2GS.rtlv_sg_swap.cdb index 025235457cffe16618eaceb52c5f989d6aa45213..72e739284001ad724fd9070ac085d6464e2f3b23 100644 GIT binary patch delta 485 zcmV?|!#5t7+NmsH@e1jt-j@ZA0BPKx*?1NDAf`9Vm4Yq{TA$>{QPv{6a zi=TRy`13HJPU5}7m!jHBUpd&u`+9-xZ+$JmKHk?e?BmZ9YG0%;&WN>eZgH8zVQm1= zcU=LF+7@sPFn;+ozYpkj%WZ2Jc1m{R4}eQTI62<7I5~{US>raqs*OgwQ)}v$ZJGMc zp5u3-aC*gVwtt|v+Cd@1Y>yY(a4L;^hUTFwfu>rw$Rso~APmR7tNHaLR8vshbleB} zP`XNPs;POZPFfyl>`vHsEF4Ry_Ah~%Ovi9dtWka*c$sXs!Y!p+8-sy2Eh9nmz#GtV z>|4iZ_SHGG{J;y-+R{%O$;7xG3qR ztKtd&W1&)MuqmSacZF8Wk}jk2>GuSZpTOQ4M^)P(d5m3JtpMS)&dw9VS_(7@8}!5v bRj`xaC}Xr6PhIcaqmHB9`1Jk*lS~5r!L{}v delta 485 zcmVhb zyRHC7Z40;t7{7d)-v{)%<$79%os!-71K^SnPL8)NP7b4T*0>F@YNO$`YfastIRg>AmwtDILSo%K;OoVY$XfA{oR(n=IWPqR*m^c4^E}Z|}-q^$b@BZ()$MwIq7tE3WeIm_*mhnv1 z=V=mDO5|Ydx*%+SZgeAoMz$^)MWySSd^JxMNRf;wznlDm-oy-KV32uxawRYS73R@2 z%7M9}@>A6WQpNdq`(EZ=67RKJ{FZW4Qa^rRXa3#V<7zARX=Hc_xX34Y>J#{5!7ox` z?6v0G70*-uC4VP9Jw5NBfK_RcCp{yhd-(^qoc1+}6ZpgKll3#Mjd{O>b36Cz6;J}O zDkEZ|AYzhvhaA2`(KgEegxin#`Wk(8N%V}x8mH6Udh)(OIOWEdGB!DLX6CwFS8o9z zA}5P^^sO)G)F34cvTdA14r1!I;YZ??-U^;*5IX)InrG_Ijx_8LXG*5rb)N2A4?4Mx z`m$xpiyS;rdc{SN0@u8e+s=oUpEF_V%0U!$^U%6JYd^oGqa5V6vf;>{vWn5yX$i9P zsTaa{+eTA=*}k%2<~&ZW5(fJ2|6~YUJxRH7t#PC%VSbrf*9NeZgABGN+Pq^1B~LLN zqkA`2!|^K-KJt0M!3mNRTP0v-<%D{ zH574q+q^cLNIb*53v{`f-8w5ix>lFhuczp2(Fmn*M z48|(Sj!F~xM4H|iE(|v?ycf3r48p`fcs9P>d5^ZoM!0Fn7aDEp#nG^oxk|e*W%TIJ zgvP4nNkUd+d<7Afwg?s>o_GW>zT~QFn;1?k71g?PBHuK3FO)hu36jQ@IK9iL{$S;v z<#~p`5dtsr!ECe;Z|lXX!Tcd^zX5RLC6A`ddp}S1&4}@dzeVbR8h@RgkfY}_O)D9x z)-rm*ig2-=r_ad^$cO#@Y)WNKaQ?6e{Oe(vU%qwXWr~tPVV|s)#l{OTk$9yg@vHc> zw00VUxq{F?(#(e;m*A1FX_lE061P7JcWU6D=BU4YYaE{mkJD?5g$5WGsQkeq%^5jq z5F#RSs{qF9OS_ko&+QUIDm#L9{M@T7)j!#%@FC=^4&mO0ehqh#4Rvgq;xa+7LtHWA zpC|T!aBMsmI~Anrw1a^Fo6@vxr}ONs?Ypyqa7GGYC(5F)^Q4!LJHPX zFXInf;xxr1G5h#eQ4I9W4J$6M%KVlV!y!q|1{~w|9wU(uujXe1OYZ@_h4TJ<=~3!= z)PVw0C);-xz6wrx)`82{tcgO58zas>d^Ck+XT9*2&1)1tlW70qu}LdRKe_MQF=e;_ zT`w6FO;R3Fub6=6Exod7gIu}Ldm9iUb<^d=u6m)=pL-a-f7|JU zkV;VLZkk{slApF}nhA}OWP2ZtF3_*K(MmA)+E`}@6C$3jPyV!h|47}ra{NwNaoN%? zQXJ;O;Hd%~orabKA*vZq|IlZ_?K)H(Ev-VKLtmg`Eh}Lxdmf_UBVRJq21uWq$(5}T2X4ANMI=Njr*dth8q*X#1yJ-- zldOym{V9wI-9|D@6U7x$SAcn}?K7RW*m?zoUWakGB z@w9*S$_8E*V#Z|Bt10}7324U)BUSZwv zz80m&bbG)Hw$k4Wi>hGnXmc?XQPB_kb$dXy?eOA5?SV|aLYz(g)&BFqJKtxV=aRCr zw#XMEw)>5Bi9-WY9g&;gdvXuEk9#unzsndARVovYztaiP7QscQOucV^Y{vd8R>4cY zfT43{#~+PuO4Pk@(x^sq zmzTP|a1HW{aB*w~JSzH{ENi3?7W!ec4Q!Nx!fG@rL)Aa<|Mzk>-V2|bb~Z49?MXD5L1jjeKsK5s=%u6Mvr-+jD9N$h2C9%m(0%)77}sFAaPW1sH)ecxnip>MAqY< z-AE`bKSD);bvHjYzaG7lSYy;}e~4HmPSLp5d7)^WV0Y&+Rt$E z3p8Z_E2zFW$#biiMjn7i7Y_+ne*#iG>_EAD)q{wkup8-1(;Osp=LRpKM;s7VXi@FI6xzeA`^F?8Y;GBMnJIHL zDPpzDpH-hb#xc4H}XiJ5GQ-z6l|Mcg;p5%fE69toxGP_v|!N2zU z1wH}Dd76wa<(7-B%@Q_yA4Kk)=9-V!CvNi4g(pKtQI}dJL$OZt&^G<(N1h*d`HUNy zG=yK*J5Te|w!#q2Oj$KYfp6Bn$}z3#JUS;Hr{B1hYboY;4|b0eqc1VdIwwr%_T>4kvMPrMa^ zD#ukCx=SP`e8xzIsMZ!PPP$?K=N$M`Dn%^3jS zsEY)Ph8A8%M})~qbaOywC&&m97w{^?+Jn1nAHDbj?FX=tX+1wdrcbl&B8(i=NPJQk zUOXqs*~rFSB+jgzAu3^T$M9n@C;mZ>rb?-|Br+S>miKC`kCF@b9VwUw8@P!r1q*2+ zRDCgO-kI#%d6yF6#RMkgYgJ0YrJn%dv`&ytBYCpMhriM~r`2$s{*3GEx@`hy!<~Hl z7r|RaYu|CuA)_tfvRyy{X_`xvh)?E#Nn|%yZ9Eeh*15 z_0!#07<2NcPP=2;fI3#6OMdz!3VeUvRW-iB86Cjw)c0_)h;S>$mWXvp!r%c+g|XBY ziOJh9l_VQ`KWq{AP5PmrD)l)Xk)2VB3VDuDir#K4qjC6R8k-}WTtN5(1q8cm6NsHT zn2roW@ORNLh1V@#`0V@m_B46i6iJeBuZR4O^3MbPexxwW>VG%-kz79!w{q9~$t{hH zT$M8;rF(I&pIgu&=DXyhKU@%S`io08h{tWV*nRr1;k_)j&532mQT?XU@h2W%OvBpsqAd(4YGVj|(mu+_0Gvpx1$yrE0^Ovm2b0yg5$%77I9`6QogM48Jn!!AzIy1mqojRE&5&&kvb z@~KK;5XnX$1G`SerSSwXotondsye0LJDD_#2#oM#DeL+&J15whUK@AF93agY!;16w zTyRjCNv%-!Fc&9c$f99&%c@xJUyvA`~o$ynd!L80sc@zUY^$q9u? zi9}gmU3b4ro={tGUkjCqym3NtE}r*KNJ2hLE!D4lFWFunux=A@>x!-Lh{menpZQs^@R5^AbNqZF-Z;?dh+?+RH zZj_cTaYBM7UBJo*{C)DFxl8=;K~`^G?aw%o_=bHFFmcMaQWZlL%4)v1`d*P$3*gt5 zh4!x)mvJ!A-j!gKXJYN6a3H<8-nZuw2O zDlOf1_X(sH*0yzQv_@Yq=-X3s=aD#bV%@Hg+9e>O{$P{#zQRCgi>JB9WZXVq?ucd6 z!9f$qD0f*+nr{M$q2QbJjzp+=Ja(_E^Y6V=zt;^PI*C*2n}WtCjo&r+-{vHH%Yq#1S6dSnhd{Qwr@+hGY6_VwfN$`MkquwXxEB~zWv zbN={&JgG{P|1ny=r=mqd=;G?p=@()ta~c~^m3PG=(|UMk{^giQ@Lv0zg+bCB>|tJC zR&DpkA*JZASAy2c!i-@6MXUP|t@Kyv{!NAVJr3ujdkUV1u1~qu7WcTit9SeKxLr0w zhPu&M9xaQaGKU6yRP!mUB?yY#6{>9|CB1!>_y;65sYB~E=*}+ETT;wrcHE=dmL`or z$e?-$KPI-`RE{gE8trf9$5&Ol%nhWd=b{leh)b_;i2DVe5neXf4zP0 z*ei7S4{ySDKQczNmy5K%JNrIj-ic|AK+S2(_Q}+gHHJog`l5oMD2yVREV54Yqm=At zv?Ct+SVMETxq@aDg##*$4C+D6@V)IVKvHr>lwuY9a!&mDBI~I!bxZj3#)Bk(#+6K3 zWtcEo*-%K4!FJZNcay$~-@v zm-?2si!5OlqQyG^bB25j@ge(Kz99j9ua#c2r{A_tjERQn8{1pAORvJXzdA7c-@Wtq z^ur9+xwpG@KaX5fm@`Q`vtwX0_*2rj(trJtNs_3A$cz&a#y{IP7~Gl)e2~!6Va%)t zJxDVktP#PTM>Bs}qK=pe6lfN^-#IG2ix_cUra)fX4R8C1A@T_|?9&8Cz}Mng;SRjH z$~>ZVoIDUJFNO{GlJS;~At&;FxQlOud&kj976>#UHM^pu{Pg8?<7bQMWSd@!$tBr# zQBE&!@}ff27gh(i6hYr(fc$EA@W;V-*O&#Sr))b~DpvC2=>Rvj79wvu@n#O#}OzL8No_ItyIHPG-!tt&y!0`USYn-={<14k4!+ zgg^8yd1jP~2f|>-!$O+1A=>iC(j$iKwpf>ad4@T6^;E25%O(yw3enPit79KHWkU2O zKdQ3K48odX8(f9X9=@hJ3Dl;gk<_y}{30P|kUW6Rp@BEBQ3Y0b9XO8Pj>5;sZDbo3 z)f(J*{5~v=`3#%zwUaSVekm3S(k_jR46~4G;2t5Kthjt66m?C=HG)HSF>+S4b`k^gbX`3jCH{&sgq>3iu|rAA z-TH;?;m}zT{mZLt&faFbUdM4L&jUViFqNCs$*U8hKv7XMKT%e=`|a-w$FkJr~K znH9*&gAWF`s0I5c1KW5^wPnF1NC!iAsD-`u*>Y~8{>d-)UHnu;ay5rJD*%})l zj6$}@AL#nWvXsVem7jT&rO^e_-yYNt+3 zbHW5EV(rHH*%p@h%E+3&x=06eLz*d*(LyBC<%x2E2OU_UOcYln0-D^jTFTX8nTGV% z&8&-0I)v6_gNp{Z%DZ15crfI~wKbUW0204;rTh|V<}MqB-CyH34{&)N3$e zNjp2c1t|SBpZc7AMYQ)S=-UyA|&~H-$S;E1`XsSGS)?`nNfI5@e z87a?xvW3t!+M;Xo>#@3oOijhWT@->`3%X~8BWvN9H9I;9Iw%YG_VBYaD9@;fFT@S* z+RoSDGu|ngYI_|Yvi=l|o;_y(KIC^!i#gfO*9Wa!yh0CfWxCG}o?y?hIt%GER{`>P z5$h&24tB8zO|mivH6;`8gC6h!Cmw9{QJ8C{RlGusp6ui6LzQAB?z?S!)%F)WF@rp1 zCN9@AQfe(GSaUoZ*1|O+24s?vpIO9L1_k_bli-3cSkq4F`J(Qla3fh($_6Jy!Y(Q3 z2gy@3g%3JcS#+fE?gXo6)(O>%U^#HaK^ZO`G#)Cm&ms)g8jrjtL2bbB0DpRWS%^TM zhn|O!YUw1|c$|xm`gkZtK~Ca1q?P4hs3ComfCY?CBIa-FL{d|B$z9k=7wP+5BUirJ zj7Qqu$tdi2y!M{^E|*`>#D}|3B{&nIbpI<2Z*pA3E&s7YA%Dn}tw9ug(8H1Tk2>uM zsu38eS|27z=RQHJ-WKo!cIFJ;DAh#D)|$M?t6J=tQ5~g*vJB%HVxoN5lqN1Pf^a=# zgHppNQCTQRcc@L~5Zgb*y>h;)4Jj!`t{g~1yK3;zpW=z4TCEDr?cX1G;Oui*oHT39 zf!diUKx`dH^`tnrqvM;S6&yO%m=#dVhrH+*Vg8#cy+rxD29OIb>mq>8$cz$Y6_myC z4bb#zT#sxYgSwW4GBl_52F!EGvM^t7FsZSuoMtjZlAeqp#A9AM1VS50=6yajqSh{% z4=`^RS!>;s?)nIk7E9L0C5u_f@4mx2ox*?{U2fv?^xSKf*(FG0Z8>N9#&{Jct!rILP&j&vvELmtl_WOVAH{t3f8?;awI1O|o;eMt7( zFy;+}($AjMeIAgaDTeR|=8B9MG8J&qs5Yn}+rqEhIw7Uq#@HgQhL?QB**Zq?P)*Fe z=&iwF2wt%jjKd+09SjSfRHJacsPa;i(fC*OuX#p*@btPu$G)Bc({Tr!(Po1(HwpX` z_SYUCNpK{{u(ZxJ1U9h9_P4;5LGg$r*_>l!gsAd_Jf)ND_C^h)vSHfR0MY8@3RVm9 z`{q3?zRVfjn=8IR@zo!L-8NO2E0f|+^c{EjPUJgYHqO!oE~>FlwoWxWx__3YX}`7H z&#d|Y<~3Om;~N+2}OSlgmf z^@8YMc$?qf7Ov51OkG2;3-6L~rZ>4nD@Dh!K21Y#T$njXc%C&nicCa|mC$G8DaSD$ z5}ay&7;YCk?4Wi)Os-357ZoLPPITVX#1>5h)soCw{qdp}kxfz<)Z%L?xy@)=ZHw4m zBJ8`3>h4)`V(w!bR$^@d=w@2m3|ZGPNr=5qW<5-QFxSG@W~|K)#5uqjygh2tv@si3 zS1W%AfxlQ(_L>2gq4e5H=>+W9I&=U#xbiExO!&fxB@Yg~$A2!u`z^C>?7v2cCP;yM zoUhp5ly;8Ss%I;Fc95Q@?)%1!6s*ZQE;+6~n}yZ4(u$EWqmb~2UsUh<7Qaw469(=& z6!*bE+aO%cY%wtt0>q{n>_cle&`zPQ?surUGXzJJ+mPbn7b(Fv!v51r7l4+p=~bfW z%!XOs1DXMn=15@BL4X9B!BgEd?GYc1axL~VQDM1>a%xkWjKItZCy98wLq777K!gVQ zubw+fhj*jdvJ-d_&Wnx%IIKrgUS(6@X5|t++ruKXwCgKda$D}K(@`V#qA2fm_WHHE z-|x5zaAx!7_6B1YxSB8M7XY1aj8uJrx@hmm?>FEtj-F1rm= z+KmLKG8ZZK;`RoNKxFn~5WYx*W)N~iHNo#!Ja-~hL#-rMo8AVS_7IJH7~!!v{rsyO zw$NltRcG|uRQ~AC9It0-`H6m0I7Z6bISG~rbbZ^!WK~u2q~|W!9)qc5bNCse9YN;< zKH8E_=9`jNrPkR_SrkNlR@R{Rx(VQ4z3_kNg$Wpnz9 zM{&|v=eUK0r=VMk+h%9M6n9FXud8laHRsoJ_O?Pm0n;+_2d*R~X1;=Ce50)Q!?U)W zy`hC7$GEl93)3s!Px6rb35@KQ607N|k{TUjz+LTq_6z)4p`)J$gH%4L8ZgRc%cWMX zMgA-^op~0`*lkO-Q8dey{gUgX>3IuV%Voq8Rw!~xSPLV8AH}$p6#k&mrnZ9oMjD?) z4d~@#JUAnp7HK!tOkbBa1_ronx6}kq^TY#d^9wpBaMOOt2_ai;M7iTQH}vV7mqrNy zFMm+(T^_1?Wz_b^c`+F8dU*O;=l8xH%S{c)2a3va$RH!&=3Zu_-K1ow(N$8^Ze!oyPbe5d`2lNnk~+WD-!QaXmJVg$*=;azV$r9p3rdZI*AfNq%V@16Gv zomSbuvBR4*I;V|Q-%LuPsQnlWCf?4hOCpc%kFBn;w=j|#F1h(>UQ>pP1zU93061^) zt0M(ZpGQq@fSNvjbIPZDD4IS+B&1yyEOq$VwiKHre6MIGeW=zZY2TMg7ibqxt1iG; zqr4QC=dCN9lgEby&Xy+1bq$h78_q)4XQDJB|2tyk_M5$!*&j^J;Xi8)Tdl`<$Sm|F zM7&HbO?Dg0F*v^>jpVZ`F@>mVIlwcRr5w#`bKA&Gq3E)eJXJTk?UukBg{;Yf6XZj{rb~m600>H*Zx(rS z`^j$OIC007r+o?f<>#YeocG3Ee?ls-Q1D)0yNb@d0&XFDL`k_&Je9kOq)$+iQ6~CgV8eXPA$k->$rEb~>nvZ)-RzTViiqYwAB0z7$VMaBQ8VXhb3`Lg z&9#!6<5J-kFNtLZGp0-F76=~G%uzew9kNy+AGM2gTd!$W-}S`TJc0}Iscl9>`SrV0 z?X7fBq2@em>|kE=L_^SaO(|l|d&L*Q?Kv8IOJ?(>s-eVw$ zebTX!5LzCDfNU#z*0J7bQ>ix=amyEWWgUBEz-`%=n0^yuB(&B@Gy`!bWqNP#~v>oL}3B9yYn7!lz_TeH#O0ozDNx&8((%GJ)$w_suOgOV$zB#n}x3vUSn8aASCg zVOrM}YaVzS9jD*sC5eyF8k82ZU6T_jG=b)$of}GPFMtEx|4_kL7ii8l5~IQUyA?IV zB|-PdZ30SP51eskA-lA=4paEb*MxTmtJW8iqWnftezG-CviyvAIX0<9IH5b$48O(r$5&k-=Q5UXQ{{qVG}Uwnzj zHsnF3JF!_nMt1_7b$l3Z&tao-PMi))fqQhUs_!S#u)Sqdm>Ku!!d7Fkh0^}QSa=8P zI5DoI_OV~xXgKt|$pTsTLJrVKkWrM2i7eZhN;6#Z5P!#a(y0FZ`^KkiYA?$Rby1xz zhO$tHZR$7D8u8(=s`z_iQ)$(5V_Nj0ty`pnnHvwlI>m&!C0yqg*WV=;tT_c|23sWe zGC}3-Sim##21HZ1>yZLC;|QN3wwBhkf-<>kuez2-Wi5kftmfO=REKe#1Nss!#BKM! z*vF$ zT*i*U%YL7LIz=8utLU!WFhIc|DaMHTMM|gda^xE%00!6MeF(kmb{EJW+XB2H8b8*n zrSM9LqTa~PbDO?ho&Q)4yixrjj+c93I?H`tWqP2#P64Nwiv^vTNsg#_4j)OrivXCs zr0(zsK*{ zd*o0vn|z^V1f6<#kmftZ`A-r)#i#)soE_hsp#oM#EzJ#$#Au6If`3-}CFy1!D7$o1 z{p-xCNbXhP=fPdd>!Dc|Ed8H0GiE42em>(puW08}M0n8jc~Z@H6=DU`GT3~T%=F%A zMc>Tex*$B)P)%0hnR(>Qlxrfl&y@cR?*`5G>g?O2abPFCBZP+KfH^5io#bDGJ1K?i zxGzgM7V39bGh1!Wwq(oVfprdCl7CtVD_Zeqa^wjExOe|E5Qq@Wm556U!TA?kiZ9)+ zG*vUL%p$P=b4NEw+F7=)$?M6&G|cZNwjZN0vWHj$e3k=sKtHj1;~mH|mOcNQ<=X%2 zA1{UqQ6cY_S$K%rlB+x67f$ulg9%N_gqNeXlHJ~%I=&QiMDT4C?qf&#bG;yWKo4*| zsAT$!$tV5}9%jbt#Ut-}q5JhFFGBO(g7$JFZ`X7wSGac-&5wvtzaUFtav{w~D-Di= z3p*z}TeuQ?yMr(6O@4$m+R%@(x23@xoL>+`@Z0QY`Rc4%Shjs%cmxZg0CcyV>4>Hs zS#M&73ICs&w0o*biQE>L+x`K-p$1p<{6op1>rb7IMaqyg%7jQ2PqZBEqGFTIdxUm> z#QC5(*i-UE)(7a4xXgHx;Mc9(AYrdVddp zpvpbL=64WFQVyGMLJme)hu3iUcu>0bBCo(TgOtA`CE0o{6gn~aRh!*?4f}!fNG@wz z3~Um|?t%OhBr7yaz%>XAg$n+y7tX;`2!im!_?i>NQbGf@Q60_uJFg(34aMhBCv4Gn zIz%NMrvbtEfjA4An6Bshj_7~C4Vym-Bl=}){WsByvh{_RQZA88o7UPa|uEYYkR;4!DTgoBQG;ryTb`uCNhi!K^{Xy zFntb*HOTXOj`o&0>+s{bXWy$orF;ui`f=?gD$DL(_Lkc7f5|mUM4idQU?gGBBz*nr zK3>dxTLb*np~p&5DXA&jn0*E>yYFhDo=!0x$x`u)fo0_Ckd;WP=oPzX=k&eGv_U3s z;3%#tAVZZT=o#|Q2TZop@EQvNupjfs+CH5_3h?xX<&DJc4du4nj!KmW=F)EDq*Pmb z?q;1HOR`r-JFg5f@7X8BvuY*4#q?&TxHJR2gqejs&^(5)=lN8gel5lSw+2BX-%2{U z`%{=dL_NyZHL{!h)(49~lZS5Sa>MunSW%zp=D0EehlsuAeOM>Ey6|W+V{s`_+RRNP zNiU||AddXb`E*$FA^RoDN%NE3i|jNm8CmT2IhrEL_5MQ@@7Rh;crS;=E!fb^;s zj~b1LLXpGdxjNGCI`ZTz_aV@Fg;c8^oxQw;Q?S|?m|!Y$yGf8LJ$&$4Mz|!BjP)z7 zM(_POfq+ko`@84Kt&Q0hdYs^uF>)>@+Uu1FQtkJ z-tLF**x$ByU&#kB2|p-A9#voET~^|}`4I0krOv@2_Dl3wAtMX%xV~MiCsHa^S&4*@ z2AKkLESid-^1Wh@)02DCP+PQ=`PvP>n!t+_h(%54PTo&+K1}4M2f1-m0Z{#RnP+K& zQ@iiY=I#0CPq|dkI@JiSU5gYOtE?d|VAAFNYNk&&YPAhP6LTf|-UZ-1UCsJYB-bu-`Bi|vd4l{jMB^b$ z*brO!Pmj`R?}k{vNomR1$kNmah?a9BH64jg?4o+igYJU)@kexnIuM?XDYEhB12ShH z>fNvThysYk*?pjQ855#lA|F15Ly6PW=ZC)mV$(&(k5te;^G>}*wx&Ao3PebAo}ZoR z-5=PF-0z>Mo?C@c9;7=xyTxwL%q!L?gj?5I35i@?IT~ij6}xKRf{TLBjM+XW-9UC& z5prBQJe7l49xrQa0p%RZ0F-?w3sCN%EJAsJ(hFq=$}E%{D5FqLa4MaV0xHix<^!MgnP)vd zZpuy?G81^pq&wD?wrY;;V@i|;1koP|MBAS(`_AoSvfv(Jvf>^+{zAS%gwi?$_xKDY z<8#pS183(;H<~-gr`5k2b-M+behh$ny?eyoD!mil0QL3m;hAN zW5Pb)_&KH6lNt92s*CTgdS^ctVO(V|DT~M1PGaX43&EkzuW&8J-VA>jaSmc%4`PD2 zN~=V(|KFtam?t=7ss!5WbeWIJSO`#k?IL@+MiW^?X9xYi>%TIU<9~H8s1v`3RI_1C!_-N3 zo9N)UAKi%hu>n#ulgZgnl)inl8p^gr?srLL-moDY#W(!N?(Su-^t;n*MW8pRC*v+| zJmaMlJ8Rg*i;t1oHI;;I=TGqK+BK-cB(6Zs;GI-oH2#JUE2EL7)tm2`=u@1A2D^fe9C_jy($*e?jT{dXK8Q0%{ZR5L;{eK z#P~cl6?e~M?g!cYo<<5}?6san=a$|Mn&Qp6mFiWinL0;cSfV13PPFpnS!T?B5h_^X zO;gM_c4K@QN1*98N@3JM6Y2T0H_6$U4~y5|!MQC?t70*>c9* zN`FDJ%soSGeOV%V>%?E99)?BOo_ggaDd8tlW%CZwHDasa5Fj_rLZwYqZNgV7Xg7A8 z%|^}N)F>{z^A;B)v`Y9Lc19i-NAuEa%-;GCULt@xt|VQ?Ib$W5Rubqb-3zqm;QgR4 zO?gaVQFBTj;h~z!SxaBbavN-iQ6jcGi7g2G#aeQ5!$_VTA7+tgY`aP7YnVdig`92IiTIj*wSH&U<6PlAGYiws;ei z%k^2zN426gdd)>z%PF%Kfo?ZjWtDuc@w>nWUCN&o@ZA^tT#q^-iv;$;+cg{7d&W+a zGnL{+qxTI1Jvt_$t`^x$>7``cW0^0icjJAE7#M6ZLz9Z0tw(>1Up|mXy{vteiAI{K zZjZ*Q_QQQi(Bm81pe*PITzqfLB$Cl{d9XE=o_R?xcSXHETf?%<-0?Uh+G|8ez0lik zP&ND7Z?`7VN1RD*_lj75bY~u!JkGg+E?Pq$^qHMdY@RT0Ra!gu@^is(_i6Grg9hs( zOf~Z?n-Z6>QZ@K zog=;W6<$f}`nJmo)_N4^jxrD#)$xl+<5N3DxV2dJ7Tll0UDm?t2Csp3q`SN4Y35qf zXP~}G*&n)BvE?g}TZnlpeUs+Hkvs!;)X>@#&U!SQ_Pc#4Ny2ln=rvL>OvH1u&yXN4 ztrW-#d766oZYGFW>X=7vVO*emC|1VGfDK;o!OkWJN5Ois3TDxD$}ZsjhMsl2{IksU zNm%vs$@;I6Zmxmx*~bGsiaG(lLq$1vHNge1({)Ps#12>hWeG+blRN^xx;^++-xODg zsMcIiu#Tqrku`DE&CON!$^PbCi8Gs&YUO>ge~AB1NRCd`~GBL+YYX(o#Hrg)Ms)I!sPrt$LF$<)pR7ulhm`ix2l zOVIhB$cH^3rN|IrJu!XYxw<{{s!f>PBDPI*%|Wj42Z++Et&tQ}%F}u$NfjjjZKQBR z2?wcGP%3>TTbw8vC9qOAmt_C^_*cD5)0 z=37t)Jh1}kOK~lYY}1sE>7djf5oIh4XH>ds?GY=l9KRORDlqk+)U^LuWnXt}CfID^n*kDzV;;c`L-8mhJQp z^n$a%u5eC^6h|4TDxwYRsOSO7Q_q>$b)>!h8WX;jym)ncI9oKw#T8HKcN0A;!<`f7 zm(Kczc$UwEp6qJDX13?Z0Mk6K_7h z5h(7&o4S1e7VRtQA|gUfpZ-!oU)Shd`M8-4Oq&s<2=k?#xKn~U}B>X3bV{_sNJVO26RuD<%`b|BGUS2Iv*%sOu4sU7j^lTL2T&3DH8oR^`P zcCr$7L0@_ua+|k$H5P!l&M{pCLBKYc@@o9i7P}IJhTPn&haApW=glyqccA`LIi`p)Lu0D2zD`Rg zdFG)a_$xDt?N=QG)|LbPh>oHI{SwJ6poKz(?1FDkM39TL_D4W-PnrP6zGGwn?;OPh z9ZrrIMWERGh!B;nt#|5FIo`a{vv`nsU>twkgCj-5u6>R=i5 z%%h{Sd(u^PjPv2`D>64~Cpa)1S1Y<5mBvsO>ukkle)?&R5nteb;g7iv$jYxsPPcln zgG$ZF&)AwIq54)qm*#DjgNStPJYznjR$;&0F9uf9Z_O&UN=a2Wq&KKNB(jxyBVSa4 z?{0>?l_fV`?{7~f*KpnUQQ*mV7V1?t#QffasU7RA5Q7nsndyjnOobHkkAfz)!a)mJ z;h-C)iaXgD6SPL1MH*DVkCce8{yilg4=OQHz@D+X09?DW3hooE5ke7NR!7evW0r7j zh@?23go>5u6h?&bJ@`WL{jt8zM$aSO{9Ux8Uun#y>nvSXCx`Q>`-gsw=eh~?i2V>8 z*K}x`+ulq}=^5XMEju+{ZnTY?Bs2jckJbW0NyKe}6oxJ8et$h+;V0{MJ^#(F6Q`zQ z)ka~Q1A|%daD+*^gG$2p!053@oR^GkarG==sh>5VB!SQkK@`iMYoactbbL41a=sQ@kir_dO@c0Xrn^5a0eGyur^+C)1yc z_j&WaOy3b*u+V6sffYsjR0WLi15_ltXfea?j}PQ$Q}A!1IptOGg$vY6{-oOXzT+~} z%p>QXvMAA7WF}@fb!WqgB{&eYXUqQfwaIYbe-~3dl^V}7hsK}T?~-IK2*j$F&$z!s zlcZMKSCC-s1vsYmOlIEy?KDt39xlk1&-5)qUBhqm3`d~=6(Mf<(vJlp>~kA6x9AJs zU2L9%(zZhpRP)F*#{I&q{FGz-)ijmQf;~TG6cfQdwmxxb;AHOCu9iy!zwHo08mR z50n89Y&CqUx0~#w|Ha9{>mVJJ?Q)wPNpM~Fl|9pw#L`1g2D;5AcB(H(ckQ!D6=}hh zaOsHrU8sZ}a|gdtt$1RkK}VJ-s`hWvQhjO#Kur6*4z}Br;jb~p#);S7-%PiM&HSUg z0ts=3NfXVia*4uQw;7D1gbrUsF8=^2Qlq#*wGYy+d$_z>A39hDI1Rbn)2)af`Z_)& zz8)5`SjwEj`JmUz9U1HizU7L4`WB4X+SZX(TLt8LqM0}rSeeGJtIR2X5#316mwc# z3Vtsmxfr{a_e~>(Ys~xBnW3@Fb`R}OXR$!yOe9E}fY7FrIXG-^WDrqi#;#aZLQ9Gv z8&UQ%HNDVIN1|`w-&(zO(|*L96e5zCgZ$jH-K+hm@+wF!RdHIT?U@WuS_*akIlpTpAS-JkerGz6l96=h>b7?&t_pRw zihi!rpF3GPbw62nElO6|NNptRHG*NQ$ng_(%Yc9J?^G4oV#Yue^xdJwhAPI{6kr}6aOKHW)nzfi0KYrFJnW9wY03~ohP7itx~s&f zN>}azq0kPfuohdnUz#n zGaa1FQsGvs&0JA`D#g(Xs;6M7;8ZNZ?cjV6x2P(K|lXtVy(TL@ZJ6{n?k;7=XVDc_If*0Syu#p4so$vHrT{50zBWcr(^dm4>%V_0m1 z>bH)8VK!&C!!~*i;F$oOLu@!FJ$GVj3+}jWsc>XaOM~90_pjP4I(n%ulf-7)MDW?= zwIe6ep=ci2;J1Qr8opVu;F1z=fs3e^v9@|q%v`;T z7Y$Q)roiMqpi1?V>FG@dA@?hK)RQLZzS?ut9l?C*;L@oxtioD90?jXPGyZSFWWp#n z*fA|H-F(#E*uZye|qRFC~a<5owc#0w8A3lR3jc`4wC0Cq$#U7H4kB6`5TtOO6Ec}>v$ z77cjN1LcY}=#zsiErpO9*6fmlT=q>GynpFcxdmpQBUaslRJ$&_PyVddDA=Ll2HdJo zrCkfUh8W!bJ7f_;Vej0xGFh2gBTN0*tTdKtH2pKaiKj~Qb6bJ6l1F%gJN-LJ-UBc? z*fgdZ@Ph1Yp>LfIdY#i1%6J)X&xsbwz*n9dd6SHpqcncJ;_7*}Zm%t$Rh2cn2L7~v z9lCToDBz%?6;=tq>Ghn;<_!K#(ZZ-vwLCrn_cIdVO`D>BGPUAW*hK(1!q#*2q+d+ znI_}wIEy+k$M{wPvW#@pv2+E@ksCsAK^?lTXA|#5rcy8UH_>3f8BWVfNxkjN#5U{rd`4ZN}3)7u;@z(S$w?>Zr?E0wSOFmHWeTlWEMd44j7FdOF@qB20$+JxSt{p zY3E06>KEZbiJ;tzKO;C)Miw*Ljw#F8i)5C9Sni|VtusuT`u84Nn4M!L@*QKrYHQ`M zfwH(ODv2jwg`_!(^hsD)nw|Xs%V-~(Iej|$N_A()`t`%UHR&VKK=ABcDZ)_2W5y9^ zno|kmy=S|cb?QiV1`Ev9V9}TJB%9NeSFNJz#+4$aF~Lo&()X?I&|tBKS%-9CwW&(A zqIuubH>U{f$l+3_G0D1FD?(3J@ORY&m&(casN2L#_&ZP$vbZf@Y_v##T-)|9M{YK3 z*k}_`S}b$NQh^!uhS11KofSz8YF83^H0^Y%4ZTVTyHe!+cD+*!QnC@(L-_24>dcxe zq{;19a|@6S3^y_x4;Q|ad%#jUwb8vq;B_yW zwQC~l9U)Lz+D2C!O`ZA9KD4bRRjFak$+Zfv0S{fw_)!%FL7M?67`W@443(F4hb-hw zlk;rsw(8{j{IZg|PRZWN60)8j@!~KR;97q?>KE$F+bkA$&QjG&i(62Dj@l270Ur|)Pe|eb==gd`dp@cZzF2;;bXX^c7MSB0!4gz9Z82ec^z)_#Pv&T z25fquuEg+9d0a3i%Qoup#)yyp6L}UNoz%kO-KxN^PR1zqk2hHItM6dON_STU@MyxTl;~W)oN!e%_-j56%Y~yL_S$& zB2dZ0F8V@*V0#-SnE`XOz*{H^=}EJ_z{`m}@RMZ#3ep%#Wu=KC?2YE%&=mjaeh!o# zE~e7CY+KwKMX70T(I#KB{R5l9UU|KpG*}GodwPY^}?ym#$1lI%>k6_*WosCVd!wWYV&vvars{?eh`RSb~vp0OQzZSh(rqWva@7K>zZ4YWj2E|;uXxJ);&#Ljlu)YN%@gpDC zZ3fqVh-S$--bntPt)|rc`QC2kCsV;#E}RM^Wir@oTa`%r0Er0j!jP~wLz(CDZbuoW z#8PSZIrRHT%P~2mTULs>sHli}Sa{Z>W+8jj;!06Q#qd`FuLk=`%m8~fxI z`o7p8Uq2fx@G@`;Tf9^iWI6fc*m$DNIP;Qmz42yQDshBzohRU|jhIdgVgJUnC0Djg ztwH0k-p%i_bxe)#R}<(9M{mw&q=usztZAu$l-Bl4E%idrUY5CHYK1eUya%gv)JOWi zH|&T6)Dg2={#hcMR;WQ4DUaXYfy+CYKgq!|yzshs4>JPA^K+Vy@*KX3+ugNl4mIfkO0aC848(jKr-B z3^p~|)ZEB?A6IscMoRJC+gKnABW!`o+uc=3ppu>0GhiTpm37YBjlc|9=UKx}$XE2w zE_^+G_9U>t`fGTWnk5R3t3a|sy|Z0`^p?EIN^gq57pK}NQX_~BCtzgi??mA3qdhy9 zlMcab82�Gf`+pRJuYocb{f2KX}EgEWZ+OmXq+reEoe(R0p)$H^I=dW?EU56XlnA zYh;c23ulJX&D5D6&Q?Q)#3bTEiO@p*1Z7H9LDoQ;REK*!&*O>}!tX7mZATtCRKA{% zHSBJ^-#8|)LVoI(Youxgkw$NTY!HZgN~4(KW^N{V$xz5U=QNDXM6)6opCxO4KqrBq;Y|*H-B`$850Z|xzHCe7sK=6=}f^`_@G~uVK;XFN#_S`0KcDn zWrHFB(6o)9@bo;A#?7q8G`GSxGGs;yH%XwfMDEk)Vd0!9L(yftx678!Bdq&Fl2M~Y%7nPUqn@jT(M28o$V`NUji^el zI1zMmjJ^o9$-ZS5ua_28xQvBpbZdy>fNM65Z;u=Y_H5lPjc7lg_#KZyaj^?fj-@KT zv+@c1G%SNmCL0TvINBhzH+-YM9B|2vqk-EL5rF%ioLzU2^D|g1=(`5l^<+xWFDanI ze97fS(uz~~iEv9J#1@(%V8|(ap!iNckA2BlbZqCfI6ysj<|oQg)rWdHH>eOPaTSvG zugsLm#Y+0MSFBkhB4FC@>YWj@W!oT4;ucJSruuKZiiy_YM%BDU2FdI&fo&AQ(2@+P zUj2-|g~$6_e9-aMS>!j@mdwHLu6c~~2G3y;rw8z5L-Jk115 zeljeXg`?8POZGG)6HRU}V<6-x3J= zh<)pMq2;(8>JOVyW^~DIj2R$euJn%ir_n|QRJkfFg8>{HcV>YZki}yoMtqb56GeJx?L-2M0cNs$4!0~?1*+D!AvE<(DV9UA2-aJ zmnp!0;ev&XPJO<6Z-C04Nv2lp(IjRd^ z7jB^6;1!@vPnxWHLYV)`*ICjmo3GGnKUyUr@dDRb!c7&j)j;A%BRLCvKE`g4BW_x~ z&fQH|i;FG+)_KZSSlP-h^)bP$_fqbuVuW0EhHv?fvvPL5h#Dl?X5jtjKrM6PWCwFi z-9VAa+*=feL~MACaoZ0E6OZs*Wv)~Qxw`BnY*Ryr6Zi1$+|r+?c}_0cm1}E5KGt?a z$5WkYIgj6@ljTu={89xtxDSSpUm`u$8U7UauMHxht$x`m6EJWq*fZhEHlf5&`?3QY zgfu-YQ(l)1XG(G>M)CR>zW}9M-J@H?hAZ@1==Y;9TRuiX0>O->>qx}I-~)!*vkf$z zD1URTvjJT^-(A_J43!@WuI2jHFm_@r>cc3dY}UeubH(xJ%vlehlWhE=DE1)-xna-H zO`CqH3kESmxWx~7l1R~;Z%wI4Be4T**9SfXy5vZq|4Ok$C&cTxC}dRYx+z)B;P&0u z>TUcPB|DqZm@Fo=?;M439EI%n3Y_%}aM>>WEku&{+}O?M2nvN5aHaieTvv_Rk5r=} zOZd??K{)vzlHaQXXd}*BL}N&VcQ~rkU_x6|6N`qaA5P&@DbDSL^-9D&W2@chn1nzM zwCYC`H9nDJje>E46i|`bCDd2ndAhOaKNVpXvt;Qa3b`5bX|<@zrXFV5S93bGH{>br z`olF?HUkww>@wAnTM|WL1cl8fNDZ=as2Rad^(CU7(HTp?yV?Bbct#gC8<<-cBx244 zc8e|fKS>VqXff84AxvDR$=Ng|SeDge7nUs|JR=VJreq8+6QN8@D0|I^fbBU1{H&$iMduLu03I%`$o!h+QSA|c zk|!V_s#?-l4#4R}F3`y3RcR~d)sn)s43VEnU9PFqp{dxexX* z8$wHC4e%0jU5+y-9Hl?)N$mctCo+-6&99^^x5C#?+lNNeX_Q;8WUs(KRw}gmBk!TT z%Qp`T*pLa*>R0aeIMQviUr_ytt-3Nfk;W#~~%!*A44E-mqnS*zd9wL#+zmwS~)hfP?E1gp=k zKli4QK#U%Zk2~i{aQuqOdl+P+g-*7{#i`bo+zL5VD90$q%6QN$QLi2d5a~Zl=Lg2% z!8RmndEB>{^VYAAYdbKC1~Ll?ZtTWj9-H8?)9;Z8dPjBOd)8 z?oyyKQnA#-@J7qYL>a9Zg#)jey-RZZz?GHXy7gP>t3$9zf3LL4g!{6akS{#fM`_NW z93Mg-b0S;FK5e310lJ>DH6dPo!UC8yv@hYyhB;b7*@FSw!DHuXE;&ZVr0>(1R+rCi zHDron&blW4a(?10$)1(sIDnWgN(yWxc`Dw45tE*TxHp}fDO^EtS-l)z-538y@~+wcg2BnXJgyH zqjze?Kzg8vO7#E*D#ICaptl3NyPLM%h3P+QR{@Y)Sru#cgH4}?cG6`6EAHw;nwfEU zNE;I!dec2S3g7LzD@&?;c z=+#nEwOIfK-rSgcszNJ>kt1W^sg;>(0Z$hFbcYe%Q&Ie?32-0bVBfD!o3=V-m9aov z2RGpX(fq6u)EzEtFad42Qix5;SlmMHJT*t>h8VEDcFaVz|HWKMV{qZGHy2g@YnG#i zVDfytd^aYTVE^3Za@mFShCSGUpZ|Juw0x;7 zxMYx5JOg`9_qcMhQG6TtaK!30N3&eOn)yYiCs|Ei?1JKmZ5)38Zv&pR%0kJhU8Gl( z>*Q}0`$Ai(%6|3qVu73NMFQ@($tJ0Wr#_{ajQ*3Unpl_6p~1h=dj&F8UAI~(>rOLd zkASlNxrETHOlr1;g8rj{NswpLyFIu(0=T>Jud%-{W=Nx_OBvDyH{g@XMXaTo zs9U<72^C2g^JcP(Qyfw{n6awYlKj;!_h2L+mfveAF>R2PAVJN@GXAE#rj^y-LRZs? zmT``z<)jzI3LAZKHlZx?yjMVxd7}uXlL2;nk_ukn)$>W75shEzRKfx^$VMaFMBvrM zx_yaM;>2(YUB1elFbC0-;pQ9HlS_y);Db)cXVSQqc<(T4;QZO_<7|THFHtbCe@l(W zjr3Y7o_%6ZbBP?j?%FrcgG@VuY3_WId2E?j&M%>&q5l+K87~h-23ijYg#|JL2&!=- zq1KOz(bkpZBOWv5b}J?)oEG|&=O!gI|7NqRi=`B@QR9g4d+1qOHHdpG3U?py`>7NB zln7+7=^_4*Tgbao`DT0zoPf!dp+HtE?(S>e_*bFrPV%!OSVsBR3Eu)?IfB&LxPgo`poiO(0vkD4v#$}X1S=41%=l=}e5`EIWp+H9ho`77EvD|&jlfVhUWi);{w@G z2p9Eorn$fq`LO=${Uz-T(`rk73wMhS|G%7rX0)1ZIcg=7l!FQ}|FvV0q+?@)(u_zf z3l_dZV(hMH_T&CK(nm19{qdi7J#Of3SRj;ij9srgA8MKoEGoD^3B!cINB#7Cv56Pi z8o41twcqz{mNBJ>?2(bK{R{0TT5HbS%ri2hH{=M4lE{4G4CuL&+B+zvg1+-+SF;!N#SJxnk0gLvA06Qikpfa!kbm36Z=#;08F8XI znrlC+(+eg3BpS8fX2;{eohqi;IDsX|Z=810CSL*3TKKqjADvZM{Hs*jguH#XK!`+Usle1 z+v-H3{gy7z-pRTdBGqcu-eKAb6JudOSt`H8Xn!CBpm9YV>K~wQ7+GP0rzIF-?J{ed zzux1hn)*F{VJ*np-#VcFG<9`Pxsi>nx2j|5j3)vT-=abJ;u;*c4T?^TkG_Hjx2y zzRT{SS*Ujc%4;6I_K9Had_o>_0c z_2+^fzt4_msu7FeqV9u! z5~mz?sbKBtPzY=gy{+2;;eEDzFc*J9rSTTLRQ-?tyPrl0($llTXv++KAleZ5f0-r#2XCkUc<{ju{*7x9U%eP8HH`uOSJ-z7%wv7c~rU+slDc=SGvwIMa) zc6#f_E6SaJ5N3^)4l=I$e6$Wsxj%b6x|$~W*0z({1<$M`@{aA!CZ7H&<-GX8r|{)z zGw#H^1H6{?W_z>QIXvO`iu_r&d>V;;GoQ*K$ayFczkhf~5%%Z910a3XE9rb&ZkyoY ze(ZTDzh6Mz)i3Wqt)?29R0~_i@h!n+a^saBmlcos%*2v`MFvaw_DBjykz_(tcaG_l zDs^*U!pdIJUUYdjdSX%)NTcqEOM;o<-~RE14I5|Emwst^lJ}bZ8@^v9$AczgSThyf zk8j`laC=Oqz0#z83*TMe!teYHbL=Sd&MUU}b2;NUMQ;vChTRC`$c4{LB6c5QCog{h5@Oj#a zLlH0m_dOKa_4JUL^mrs%55X+h;d5bPrP0>aP`iO-F&w{p)InC+I6n5jRL-c!uTjD?OV#SOa!7dZ$xP(BR&d>e$FiD{y>z$|B`z2>)AX0 z^|vsxw_NvKzQ30jKtXU5f{(EIA`+kYzPqyKbND>^P&r!u)7pXYazREbM$`aQamH%+ z8QiAX^a?rq5LGi*2CAa|i#Bw@D+~UyQ8mVKs#X~I4`bgW4}>NNo)GRJphI|qfB+#B zf;5Cd2(%E2Ay`5H_8|p6gkuQA5Hca?Ls)?z0HGCv4`W{s#>YS4Uu?+zF26jszM&-S zx%~3tJwmB-KP{3{0uXJ$rV>*_)`imh>!C`3Q?fB&oNWBLS+0g$hkEg@8tddAPg+Q~ zw&k!-u@ICYOh5owAw@L=M+oQTu-%OK@-&`TsLezE2)pXX& z)iedT{x-9J-YDNWSNNXAvcXD-f^ZKJVZK5{VV!0* zb>*Dejz-jrJ`f*bk^|!@Sny0W9qU(t;Y=gQDfe%k&Ni_M6SmtMVvLCX#hE`fI#ELH zD3SlS>fF`1+JQA_`=`HWbJ^vWQ+?wXCXxzf{P%-45Yf+nqQb^6|Eb_E(}{9NAe7J1 zrNc9Aw{wG-Y7hIR69uLmFkzdIB#7+SVKrg;C%oL}GpIIRdVkPwQjyBf_)ml>eJ6h# Z=KTK%12SH|z;Mdscf{X(_>!R3r_<`~tls&ugeis%R;zsw%6hz_cW7%p@=Sg?dX~^zsV@pB;to z{yoK7&F`RS|LEWG-z@J*-v3th!NpMWpATyclx0MoeuU-V&lqY8^II%om5eQoE-%k7 ztEyTXHVJ;?RC!)*`rq>47J8F&_`-0lsPatn_?ENcX!-c_R-vti)(EY)RD(o|j~b?- zUv7-ruiBTNGxDjL2rpUlINxK@d46wh;G5SLJu+_HVw+QsS)yejZ*(o#y^+! z%{L1^alXMh_t#wTI=d{!?Vg4Hr8jjJymFUX9ntBzz@)VE>&GRS#aq4^q=Q(?&v$m;T{Yf`(pHzLDEgJ#6Yo6rYTN` z9cc_LN0(zvzd`=)E`EKS%jc-#LT~JgFniPG$@DD5gRvax$^|p0E`BGUr}g>De!{Z8 zd9I(MUhX`!>0%mi4Nbd^rkSE?erTE_nih$sT}0Eo(KI_WEeuVwK&v%%FdI9BZD#9V zN82FQucn^M*0g!5Ih?7Pk*(>e_T|(DL)y}9P)l-nY^g(&?IU(bfU@E|yW%ptk`Yqe zum4W3Mbx4zN3~AQi$XtxXv)@fy8jlT{lp~PX=75;V1855817C6qk7FQC?%f}JD0`M8yjVBQNh+yz(q5E3bAF<_ zwr)__`VmdA)3@l-$U&!FOzkwW3Q^hmkD4d-BW^zGw1>)mgUU{b%muv*BneUWICt?k zuE|fTTE6zi-dJW?H)9}y!m<-h)6;iUm&E_{@5`P7^|aHUztgX)ZuvUQsMH12=FVV6 zaPSZ~KFo9H*6Plcn_R-5&Rg;geVQMPz-buSJJW)l=L)^RTcAxU`OIMImffHj&KlVs zzStY!?XfuNoehC|IJ7hEqXh7=pRM*e;F>uqgQ7&o@h=6t;hFb5#S(3vB6!EOZl!+a z1UkKRSyq=c@6y~gxzlzuGdC&vc(e0=Z-DnsiUedmPJuioudBYaN&!VIsrWHl0TsCe z?)<;=mcMSVrYCkG8f}BH_c-^*52y;ADiL6DWr&Y%KgjCYb3}vQt)~_gJJ}tA-8>~r zf8n<`^(0?vBox%_H4V$5+N^|dNA(9;2y7P1Ly;OXq?%gi`jr1_gZ&;a%2V&&ZiBwS zhxT8rlU^bW)o&^GKxMltuKH&q44W}{HKSWlQQ3|XD}JJ;rTO~gL|=Tku&mbu#C7#T zZ_SXtyNy#Y%R$WPE0jGbdu664_GlzU6ZJ=jhI0-ICq-p1tnevAocysjW;DGkhr*2x zgLct>v!ifH(Gtwcyidc-V=HJKq0ki(y^SAVwZJlz8h6YisXVNQ-x$)gGzL;29GK-V;^R0B zqF42U&vM?0cVRmlo6)Qy{{ZDARIjkry^;}zM?^p;u0=dh{Nqen%9BnN_wmYI2sQK= ze;0p{2KKRNa`tTuj_;U5Pf7So%=i5BxEtZJaKWF)CNYgzHWRtU4w(gxrbqGV-6v*swUx1cZY|dvN z!`HX4_rA3EJ=NMZSr1wa;?)$5{RXauDf`qu^x2|i5OnbPZqXg@wo;jSq-ObFn|yhQ zLkkvzz~WT{u_{I)CBemtrl41r>($b(v<71D#S~?OPyunfyt5sfM#1|2tYLvvPykKt zge^8KuXM4b`sp`!!b)?q$l~lUIRu*}l>({9{L#AR2VBYAap}1%We(gUr+}0ZY4=k(8q`; z6+F6j_^CVlH^@Mo{b|$Y-Cc-o&|m%lb5|tK8k`&)1I`cLI_$`6S$-0i1%d(tiDI_y zF!c^uvt1RsL5RdGdOsNK;y)qsd(8@mk1)&kFiXdBpRtSwDmh1M(!kkwRs|oJSXx8$ zg2wy`6BbH2<+Jw1DC4K&Y&>W31qc*_`MMq20y%6*i4t!gGkNbc4wMIUIIy*CXc~Zz zfGxnZT5#-A7ymjeHGti5_iYVG1K=-a;|GZy5(E7Q)y8l-2@VBky61_#S9f8D@bpDx zw{;sqxBt+zn9o7h> zV-OGe@zTPegVI_rLrZ?o2`V^0rxD~AN%;3Cd0Aed+ZjLI`OH7NLm#>zj6u6NxnqY8 zQ0V>jAmW~@r8d#V6ZA7NJD8J|1nfVnf&kS7F|ez|^^fvE{k`w`7rnh!KXQPw2i#L- z@#UehC6>nyy}vkj)f5yIWKVFX*huprjU9c1O_=zp{LX;ab>-yY%DFnk-?fOpH>9M& z(MSHMabB)r^U3o#Z3_&molmvnlH5Z%oj9;xvfq1#R8` z$yEmQsP2D$lj0ZabeQGiccXpu{#PKoJbw47Zx0HT`IhpI%$Hr0Kx|?`YzAU)#45cr zl>3K3$pn#0-u3zmfd)s9)+VC=WSd;5eVeX+Hd ze@%K}2QOA0Jya(M+8HF?q0a%LoS$79po{#*3b^->1lc3iwC))-c`!2ne`_u{rWvBy z{V^w;5)VGLXh4ZS(bD$8r{Uvo#V_w}wFd+7jxoY=#_x zQV0^KrK8L>jhr4;7Xzs5g|NtAJ>Q*BA-mmT*aKRB$1O5jvNCqkgPhDAknJE$)$+Y# z(f`j^*OnFohL1frLj2e_STGM5=T~g zAgqmV_dv-Z)v^<|>C6hLkXX}sT6+Jt^nM}f98oh>w=Az)XM1Ao(%+Rz(ZWn`UNW7} zO~=d-g=f{8q}1x;X+fqpFYh*qCCxT`-1b*O6rVv9D=D+n zM~HoIIW3qp{5;+YOt_S93drEIL`o!whm>Bnj=VS*c^^{mdh0Q%w;d$G%-=jy{+nmU z%|L2Xt?qCuE=6*sk6 z_@4RVLzCA^@8gWC3BePRcq9PEb4+cyho!kA0~yz^e!I>8Tena1-$I<4Wk{;pIo0q_ z?-7OGjKkWN5t`vQ;os^tCajxRFfAER65B<+Myg6cv(?rCmgc0_l%;!WggtT}SdzqF zKqf7YyU?jBzn5}0KV;usVUxnJyoKNX2`U~GAYAZ6n6|HUS99un%lrBj*)<*kqZ;a*LLb1KQZS}s(7?cDr+P)OuU3o zOlK@ij2TF5y6@?r|J0=_F3}73rCI(dFf;6=Irf}6wgGHr*tV~@$~qBlfMQRD{cMHnY{k`Cx*VeTEJ8*eaZ>@Y zcIIN>RC@nI>6~0Mtd2Rh*$mrkj*T|MMw?^VW>~g4md^~!XO1-o*OO3~GmbXxvd=WQ ziMNgctFCaA)lk#h_&`S2Ug73;<=Zj}C#PrB47yS&e-qbsAI3_XX*y(c-j#LKaHHQd zi=;w~&>^1ay1*XRi*$@$*wH{m`_E1-9gc51YMKXk58O*v%&m#LJSZ@5N;=iW@gJw~ z<3}~a!xV3`GApJJNOez$*WdRHNPk~L$$Kw+-LS2#!;vtO^j$iKXofX07ju@~vuyPg zjO&_KS(<6tnvKLG-Hp`4V$;$4Qdbpr6H_(+UZ_o11b+%U+wB`DD0;NH&u4F=-304( zWoP4wY2(1$8b@YE?3tk^1rwvxF`egM#}79ZaL^Cmdy>bN6>45TB7Gu`EekF+4BxCO z`%zjJytFymRy{6p^Bn}QFlbwe>M_}5Ay+q955;0SUfs3ZU%G|5$j&a{4u0lATaS>- zf7z^38FsC0AC7FY#LxPBgnmmK-8Mf;Zh!PauCD9n1)SZo1U(>(8#p}f?-t`)J*Z-Y zJ;4fV;F0Ick}NCFdmMlF@JL$C`{b+ZWk;>K3@Pp#L2krut`HtCa~r5Ezj)`OR!*A^ zR!r|cC*|t8{743caZ4t>brEl_<%=PaI*Jd#GYP>+$7-vGY2;ZHCR|pzyti#`p@=-X z9356Y>S5a=&$R`p7uXU7+{${mv4)6E3eF$puux6ZuN-%f=96&efvY!t=4JQ+d+SlC zDG7W?L=Cr;sgMZ_s`8@Mx=d7gp0+Jj^{D7B;P#yu!7dc$7E6apP$~u(C27hpfIq#5 zSb!o6rO$#JGk$si5$Ax!Azq~~_<+d+yQe*0IhE$ThRQ1`sGr^BB?(eu9n2Ec_W_3g!2*W1YTngRyPvoL zPOM5usE=)!9V?F+#CZxR-$3yPh8o*Bc*E`9oS+nx#q{&O?>(OvoN~4K%?mXQ*O4JM zAQt*J%?6Wdfl2e0nIF)feEj(!Io`&3@E#! zgIMi@jYNw1bSzTP+`b!1o7@hq_onamL-FL{MtQbIoznEaoMk^0#`TG28xw-0nqgQq z$VZ?mRtB>kS+PSKrpCo6m-{07p~Z`- znfYpJcbbVXK|u}aS$_`JhIC)k&eWQ}vQ-E3A5YNc2SrI0)wfd{g8C#u;&(XY914611K^TMt@^1z;dxdQBnb7KIf~hhJ zESnuq=FKFWceT>-pi?1lQ8pBZaiFo2V6ZKOeO(^i8RwyBu zl)!`%U{S#yz&k1SC)f(A*b9K*-DFrk{&b|Ieg*^w)sv|~UEU1#=lVT;tk#hVA`ZTYvhq_y{8{w&v-M>c_}1Q2#toXr@Bmy?+7c3rnK|xA!S1W zUh;bMUoxoIWC#U* z4rxQ9rDMoCP=crm=u!?INMssM{1TG-A1KXT58h9Ipty^A58+v`(Xj$Itc}|HZeY=A*Hp+8(%4<#3zm^DY^(&euei>*pWiOO)VXR^5 z7XqpT75w6mGl>A3!Y-20i#T3=uQf(_dOzr<&21FU=0;Zg;#I5DxR^Vwc=z0Os-Y zSw)~ODHnhfy-Xl(f{^!#r)WHQX@x8k3aquWwhv9c{)?hvOtq}QHLLM%-T;_;*@Mu$ zq_*-UoO?%@_-x3Lbu>v$fC*1%xr<@v+RyTep|Q&DfF5?aOXRyyD$OIbs$;XE1U=Y~ z-OYT8Oa<{g1s6h8%e&|iGJB~3ehl^P?L)uWo>w%c;Y41wlyLokum?f&5T^~-!g8XY zMZa>OXggtUVHbfMKa`zTJdcZ^06D%UnBp;IH8myU+lNt+12p2IJtj|{UAk#fhH8%D zMmTTG{xe{}P2pb0SZ2LN>WFX;Ldk5kHqTJsQ-s4FJiVt}cIgVA2c2^Pj3Vna7;XIE z_M1JtPB8Ltb4B2^^oS$FU87L=ABN{(BmpX)r^PRjd*wNkzpBeZeYgy5cJ|(!h2Jrj z9E}X5u=)?INaRae!kWB2fVaDtC^?Fca+ek67EV*Y^$=$mP5RKG43dA6+tT)BD@pMq zUB|xdgt~1VsjW1|u{RSfezc!_=yihfdh-LO!#HziYB1UWXDE!5YjEEmyf|pALQUJs zMRsrrN}~`oU(p4Q44tEXnzlCDZ=j$~k> zNri+89;RBU@KwI&9LL+p(%%q)yq|G9A*fZR2AC4z>J1UZKvIxL#5C_)rKY9nkW!(s zlE(;P9|(W5n?2#ieA4r2?-l_E&BTWN%Z1RHv&RU2iwr`>=@OWw2fZa8=|GD%90W{; z2zEtq8p`gcKiirOjCSJ!(CguIRv3M3H||q6j@Eb)TVAU2m-W8>6bUifX4rHDHbvX;;Ss4QwU4((U9f4^_ z9FCEZbAwgj{7DX@ou!+^nlo0x#fGS(tmy&?kky&E=WgS>-4>oPz>FxA*s(nk$0h1?+&(d;0b>Pt z#Dszi(FWJ%fb*D_%fhlSZ6h#C5~lzj^W(A4+&t-4XfClD)7JnsV!%+Hi!JC)V0B_O znHRaZ<04$#6yO^hbvTyp!@+(IcIiV&L`J4AqjHa`D^Ao>`Wo$eX^!~`}a`;wp< zrI+LR)tiSVja>jN7T0G+Y0-S2d8nhf3_l-?5)Mk%QN5*qir{ma0K#B^WzQMm1)rQB zorpz*6R=BVzalQtsg84_|I`Bq!8FoF8njPxzKJLs%$D<1Ymhl;CPi}U_IaitsICU( zFkX--i+XvA;Q-QGE*K^DFG)!6Qy3luA(x3N-PWi9#QzhGDCGWuAX1`zol3tE!;jpd z2QqFm#BMT&rM;XeGj;@~y+GB4b8?swyYKuuyrF9x23)seKXtQ8C-*%e!?YiLDf^5| zTz6R5t};a=4TV7{6p3vzUyl2>1YSpqBXK{Z4iB7U!J>9;+j&cGAWwtQYc=iaYDO8| zL}l&f0*jb9=MFAg1b@jOm#&wNM;tEX>I{KmDUgujs3Y#F6Ijiz#eVd*+q3R!n-7)p zi8AxDdJeXB^!}@M-1s%z2xsdQ8|S@PiH@Dl4_^N%S4 zlp>oh3-hNkm(M1EVZ#RxdL(R0hXf}uc+GX;!tk(|BJT2D42~-dl3Bicr|%M{8{H8s zq*C=an3^Yl7f~JsqLkSC#%?%2+5hJWe{QoBg?c#V%U_@?H+QUmxK$yF{4QpvF;)uG zcJ=^9Mk$1AxydcI$bJj9QX!X3;z7kT-|`wn7sMNX@X8FnxC!E^vTM~fjHg1eO31cj zz<_7U7YE|iV^IO82-b}8#r)iY)>NDg6D7cuXujn;4zU?OqCD4D_%1R5b)0$?LlS)y zWP(c~H;WJyAuZy~@KkpPXAt^wBkc}4TYBd^Ig*lP%~YjHQ4>l_Xo4O#T> zuRdb3I9DNldM2yRdLcVOW`6Lh7`);GY+$z-0G595YPu6g*3nhwgJ#Y8#j&7A?m6#M zG&bIJOGGEwcL74Z)Q{7E;JkaPOS-F}7M04I`8j(R@fz32#6>AIH?7J__dS9kvf|?z z`nhA9ozErTraKtGjZLKKn>XnXA4eX-LR+<;5RxAQItB2*Ky;pcg5sjx&Qi}xM3{?7 zgoOclz11hT35u(t7uX(j=7pH7)B3qDQEH&m{&z}0v1b+sAA<9S5(T(4G1|DBmXc-$B@ViJksOx( zTsWG4?9FgZ8#ie)2$O1B5v=SUlOGQN9RPGDms!`#`*NL7DMu9MgRyK*0YbBHm&L~j zv=>?95Nv#pRUro+M2+!^joJ?q8+Ki4A_NNxOjZ3CA(;O7XaM@YyrL7Sp(%&_`aGSA>| z1qYbOGi#7h`r6Hlz_qN0LpNXTDma4GM=PEL+H%% z< z5uvf?NIWJq;>a<;e)cF{LAHzPG52X}(Jc;%DgKHg;g}JJ=o0_IjU&v#Qf*nNlo=7g zncgj-*%ZO%K3q*?Q?=cHE9#sx~U{*$TCIYm0LEiH5aT9Mws9E z#ohE!p#tk9>PW}pD4IfJJhED8y|mRgK))YgG&&^j8@ zblK3DaY|bPL8WcLBc^lF54|Ajc1nL(#RS=|dkkM9JnS7!2utA@Ic11&hzp&OMR0Ez z&?R1=#$JGj2diW)lnsMXh?H1#9Ftbt_-A(Ei!2oHBfS9+L()1g0R1MM6COOf6U4>l z4&3p@`p`|5<VIfwGi;@EKEmrJ1%RKz7n`Ii*Ba0W8}&qWD3n z72G4PIf;Cb3+3)2mvP2JaJU!ngDe=!)g!i;UE(pQI8Ey}f^ee`E>BatKb)w*d(z80 zSSAFVaC7zhHH}LyqU4n5~K8d z5g6GVt^;HF3>v6iam)7r1n|SMTgpT^q!?voKo^1+l3s&fViHU}kfxi|gbKH6AKr8V z^LK_n7_SfiB}p^3V?JSR_I%LMLMD+O3Q%aatOY}s4;&<8qSQQ4*K>rM@IHGYjU)$I zAh>!VuO)Dh&vh}Rb_m5&l!c0*he=pr+A_P-s=lI1Xlf3_#@qojOjYhRiGSRYP4}7J z3iH{}Ry73j+qsR1!*}SrH#CeLOfl8`t!=yqk!-)IH~)Y&s4|4+J=cG-KMo8-9-O>;K=yYaA9TM}G?RK`KD#If zmH#0P>QYh8Ug+S!_j8h86O^|+>ro$h^Vm1S@40?DcTi3kr5sIEh^yTloAJ@j$R!T% z_Izv6U4T-j>mz{Am7X808c;5!F`}im;MHoV3L=z{%sg$(mK}45hOMzxfFq|5!Z09X>g6QC`q&ru_gvu2yxN=6%yY(XF0YUW3f*pYbS=!8Vl4ACk+IJ=NlBPAqOb&v<>?WtE=q~mwL-WL2K0n4 zrM=b2m2ugZT=*~#S}8kUk~5)<0$&J$g^3z^eG@z{OIcsHpM~PbrN_og83eyiSHQ!9 zXA)JN#MSONsKt!i>-`8ET8xR|B$FfrXzei*+{|r@%N!4|c;Mvj0z3(QeuVKz|5Lov z-2}THg2|urN@OXQJkpPnfDu1+@pO!vYtC1Eq%Lu;KCEm4*@gY6PkEbs2u$=E;ctPs zUnu!1RIE9?V^IJy0gP~3H7J0^d^a?2wwYm|&KsOG<;gAXp2+8+bbUH9X6dG*Mw8o1wNEu)q__dB0kol(%Hf z!*y?8d%nK@59PG62JSrtU(O?>0Kuy8PgdaiR_M(z2b#jUHijpstqbb(Xk8E=A=Aa+ z?K!jc^+YsoaHwNDKaERcuf#3PvHshs{P;@OXR=$g9&Sq*b3Exy{9?e!w&e`&oCdK- zPnbYeMS9Y2PuUCN9_GN)Zg3-Y!PB}C?hhBeHqlF8lqt++JuOQ#h&_fx)hE`1;*_R@ zCafvOgBv2ufH&SCh_hkZ>pr9F&R9;QIQyUn+*sMHA5MHc-hPd;^_R5*yH-n6HP! z?bs*-)Ey208b9>HN5C%!p5?{6n-9XH4S*+9TmN}6#)F>Q z!FTtcyfq~ZIHX1h%nyLhi&R7sA!L7DyR<%%9vgZ26At(|0{YO(4&N( zQOyP4JcQo%;8gc+OMKXNJAsAjX~B5Gr}ze?35TT!9`s-|=QGW%TotAJ5u7DifE7>! zkW*k~3;R7n6FYb)b*9E?77o9Ys~q|O{G^~Roob7^HE*<4T~~)nA&qrxf4Rq9K8&H> z$55d&+6eC2_0-(MG6YLmaB^%s0Eyy#rgbVDjg$5D!3@Mx?U-tMG}IBVHt=AAVIf9# z>0(m<^_l_;D{aIqrz>~D?Kn4^ltzk!tj9j4P!atSpZXlGnKyN(kYs6{D87$Kz2u)$a;fVVj}P`-Dcprqsdd^2pJ7+}SovTJquo z)J5YvZp=-h7MYv3>5OUoyj8{wh9a2zxs%}glB?)V^3()szi1_x*_+RDtQ@GpR;`4f z`yK0~`W2k(9H%VbCiUt^H(>&3#<#f5pX(K<)EgifMoW#AB)=H9l&DuZ>=Al!?4}*_ zB_mw_5pM}(v>7z5u60*+6v1YRm(hm?{$iOh);oRmYV=7|Gu;lYXFEj4kQsBRe%(gx z6ya%&)xcO5vn+c!hj1Xr^UozGD2l+ zR+ybwQo_gXt|9COV@lRFiNiNyr#e`*mhi5{!4bQ6w@-ynFH+8r5n*O_MLfnLt{v8e z(<1Dojth*YD8O-vD}L}Ofe%ex+7`wiJO-Z1;}{XP7ZW2y1g7QDRc!>L@lWNw0{uF} zFcVa#t{5I=DF!StcF{#us4%2QXjTX3C0QJvX>jKZWhb-UfN$~w^?o|7AKq3E~ch3UA<+u0M%_b5EhS^m2cJFULwZFD@~zHeL$- z1<)yRw%~cxroj@Y^RKSXAJ@rW0#3WK0gj-FHbxYlXo3cIWD;I!e7I*JiRmKAE z9#l^O5qp_Yjd{=808_b)9CrD}f)ic&Bx*|r#vJPz3S8h-y=PYL_KREdOafUs7uC*DgT!tNM?&${QnPplYH$F`eT;zO z6Q##c${xVpfvd_NKp#Ghwy*;hn@BfSf>XHAJarhVbs+5Llk4QQPn)aI*t3Y(=2&A^ z3R{8jgVzgC3Q6MQ9IG(#;QL%7h` z(d=J`23sbXJn61UI(X9j<$Soo3IC*Y!=P5 zSdaaOn+fusJ9<;r~riWaR> z`;TlN!_Np%7A&SDnuEvIO7vg|PKy|e?-)>rMq$>ne*v1D)KlVhY8E%B zR#hQ-1AsPWI3~K)r&BCiU*HGxdf6Ii{93SX4(;Uf>zSo8e+Z3v*W*Ryf{b@7t_HQI z3DydUUGWSf-czW*CjQtFJ=$ZHdCf(G>`+HZFJpb5NV;p^z`$`p6eC8{GSB#HsciUcs|?u=Wa#Sy8?;Ssz+gVaN8d@ymb|( zBCbDFwnN%amVYi!3LBlM_+0+nt*q6?Ir2OpFDl9l;hbRSSx%=w5^R)bwL*_WquKuMwU-?Ew z8IW52+Ci|ctWn~}Zjt3_`Brf1Pdh7b2HEMB&u>8FJ?tMkHlV7LlC6sV_6tyqF^$3W zsXm;O-gV`bz4|#*v(5d3iiz^kqRYGz=_5?l;8V7Me6B>eoF zpu5qP_YK}I(m~TzO8ZSsol|JWlYHkcVCLQp8-j<(8AijmbkDsXc8j*%qle_dqe&n8XJNd^rH)=p0?lqPSQiMGFO zd%R#72UyQW`Hv}8rTGMXXT=yV82+4pmL7%hJMZ}9q1LuandGyGED?G4zA!o8;c|QZ zGiRXiY5cNw8+4u>I|C>@j=6$*=>a)ldI(zq(!wT0jQtzpCo)63ww8=_lwTJ_$YcI~U zR%E>WFZ&|#ESmQa#R{_vXz^+o=sx~-DnF-TF5|)3`migHt;bZ9#7CtoR)h3K%Z{qq z+F^+@fZ|`Q!0Emi&H8&v$&MXT6)L%s8W67_VLs2BFYsA~eh0*V>ZsgQIMbWnSdr1+ zaPDBx`*Q8U?b2SCtA36Z zy?*PU(l%FnY})c+x}n)rm9fWN_l}Rf*L&kFF4=~}A?;^Lhd)|(%a>dzd-dAp!@}iD zz{o{^Y}i}5f9BflYm}_tEZzz^_d;`pT<|iDGVsyW^pM@L8}san7}Zb`lH=TX!vMiI zeyHWztSjcD_1?X^`(obY;rpE)B9BM@eDFZGCn+BHJ}W*bT5vc^<<3QEBiBR6PyYL4 zQopqC7k|rE;Y>m?EF(p<^R7-uf1#gvJD=WPK?m+wIm^5fcIlKC9onM%CP>Yp zHoWJdPQ+VddYcLIr>APKzZUyh z@BZ}(akX{#r#*@nCeIGRgl!|`K6-Ayj&~5Sk}MEzs=U$KM7x!@sCwQM7Xt*#Jl^j6cj)n;*}o^2^+}5Nrsd{wPLb8Y@iC4<203lQ`68PE2Bw>T z_w@&_?3Kn`UXzWw^?dA#<}+o1*Y+C+vROhZsb^j|#m>_l_b0nge>0@qX!f&yDQ|p3 zuaKc2=^>?X=&DMG^MOZQeS4@SA34W=*r`Y2y|finopl$#<+ok$7M6yMYy?eQXn>wq z)4ShV^R2|OPlSdr_*MEKEe3OB+QVol?BdHBq(&W1a0s(txVt`n^u-Uve8Pj^NYD6g z7oVILVy=m(xPuQsDSe&ZXQL~(BU&{S4r)D*?}z`GJG7Vl>Q2#_dSOG2&iJQq6QnXW zENr7a>B=;&kw3w1=UczM0=O13AXk zw*J#TXKva@?>Toi;JwME7ucY5wUZ}(`wZ7r1m*4J41yegSeCuKR`j&?)O2rjrtc5Y zs;cXy>Lg{c9M6KzpXT2OoBn$+r41?U6*Lvvn{2V^`u6Unp`j$h6U0sNbNW%`T8 zvnP6k1VHiqoUDvma|Fv||Ut zjSQ6%Uf@MpRfOXjXp`WeY74}!2TH1SEZN?Y8)>n?R zGK43f0*J?p>g$C-rI(PfNAfKzu3PVi*||U55-_|N5L|HOA2qi=z6Z+fPahr&WEuP@ zc<{dVOv~km@9sG9;nZxIUs~fL{i=;tdA|B~za0NtY6)yOe`F*ENp8M#y5-5kU%*U%v7x{t=gRUi+`Fjr*Zx+d0+#H;8y#a*IO7 z=K^t^Go~*x#sdkvx~o>>^fp-FzyYaLVa|bzbA;At%3&7Y%y6 zE*i?bRmO##813)f8Qkto=MKt-9*f zuH3j_89GuBGV5uts=nH8afyDk?DEidj$BUGb34_=k0KUr#}$}MN%Gp2BazoKL&Qt- zC_g9jm+sp9xNPF@b2qA~gdC~eKb)w??HIPwTy2~E9-H4hpY9tUBje&Sl2tW>xr*0ou*%Xpy$Sf2A`hz(vK2`y7}#; z(3V%K%_RX*O^qemOE&L1hn@9Y+K2V?tJX@hjO8oyt5$w)W`l? z`K~|80yOTjl1rv~O8;TpacHh?K;~~T=yGoG&%@q&qe=f=L+k74@W=FfnYd8%rE_TOurXyA{nmnKH>=`tFe#p%*(i%+MR{ zJd=4uZ?tDuW}4opzu`q$b-VK$bTumiovvV&O%L_73iGr0VP@h_W>d}YYL5*|=ms%D z-K|h`+w2Fn$c<2hl@KlTZF!a6{7-!TQu?D_NUGPeLTt=u6za>cqF(CE1-)Jxe2ea4 z1^-3YP{t|JJBKe{_S>NAF&ehoN+hDRpHz>(tTxjCVg;-g);Tu;?%%TZ0qf+%ZK_7J z_QZ@%?r0U+V z)RB6+4XNlx=CXK?QpQipUqI}O5?b`TJ`ST#ul1vi%MW|U{^3r&)zzN`U*UOUHl%j0 zyh3DCZAtmvrnYRiPpII{`m~brXn(l%+bp21FpKZ0YyOgPMa!=X4T+z&zDz|6^^zK# za&co*bw65q=2=X>jDVioEk9e%$Edt}ExAAJ)`yk0-0RUp$a)+KKW@}`-0?s!H(^>R_PVq0ni z{`l(-^>nir}QkSNnIgA3Qux< zIq&!2u!9e0OImCkbAr6S-pU9lmAjdQ+qmVY4}aeGtLP{p_uzVTu|e?}aOL1^aAg-E zf+9HBSvq2j6HpB|5e3)E>wO;BP7BYyZXP7Jy)#-`pN#uGdKnyD@q4sO(&Im);ar2+ zH}-24%yHN8&V8L$kv>1#ehck<-wgcqCV_u`1l;s)P-ICWY{xgMK3_WTdU>ETcwzk! zZmfw?_tnn1p)+|hsM-x3Oo=O5xF{v6oUjnM20O9(Hb!@KX&utjWsaX|?P^~`MR0g= z4lBaTX<26(U9tcVLV(+IQpE-lr6w?NSQg(ceNA`Wt{>kiehyZl;6fs+`RXUa0j>P- z%^Q!rC`F_-If^?&C73}wQ~bTbYcTs#c-NWYo_CtKe>0yDWyW2B<~PnWsaY#9!Je+< z?^?|zX^AeabFnd7YEe@cYu7*fGWyqFmuK%zO>+@XGylDS-idHjb)-c&`*UieuTh0K zemTRYn$L0iTJuwHi(9pUie6XJM;GuZPZlzr)r8q+fRi0FzmgWZuM@=XS165Z31+Zs zszTh0s|SgvJ(d0UGrug7pPX3GLlUlpOg%lqc2Mt`&%dp7Fu z%AUcE>&VJZq2@+`4fQV!DVvRD)AyUY)@W2nsKIguj^I6u`8I&ii!Jc5AqkhoxqTF4N1_jK>vcKA9D6`Lx?3J5r zRcH71<-R04zDPbb=~K77@n0HA=;F$hi7y}g-$aWaA8cK3+go0s=Ci-AvoPg2W4)E8 zHLtgr!4&1)j63ZzLD#5j=s;B3@*}20YM*8IK2qbDOC8nXoV$8{?qO?x;^^dfluM8^ z{#xh4E@nhsdE)f;ed}!pmbMGu^s#)l|D9Vi`hW3m1=iMRjZ|4Y+-?|uQ=lAP;2MyT zr#G;bzwcevR0{nfYTF62mw+9W9CsxfYQBcMbGntAZ!JiDA{0*@y}i#m7=GX_9LFbm zU7tL@?EIi)Ybs0+z4))Ztp8ob$=#3BXQZk_1XAuORfkfGx5I-5s`L`W--i6-pV*7j zo&Q%W{PjTv9f|K!Iy}amSYsbmZVS@4r00KF`u2FH-}nD_N69IvB&T;&l2gceCV7|2 zsiGWb$tmX0oS8!rDmj!w4wDoL8_99D<$N~hIc^Ry4BHGd8-A}o-`~R@b35F-@B6y0 z=k>gv_x-wu&{?+tE`nIu^YWxz73p|tU%Yc)Ywk+nkVRT>gc^>wx>B$QTt(D?mbiOa z(7N#Uddr)Mucwsht9t?vw1Yz1wc3Jl?`Cu6@KKz3aN$_x@DuK}OL9G{HA3RI=oj3H z6F!^k!3$w-qKNH6_FdL%FaD%;r`=XDYOx#OTj?dhzZk9S5=jD zI1e;6lAo$YOy@3oDxV#1xLUkA&&~=f8TL0#RUlaFSZy_Qu|e2TYCK5QL&X>w8QYC3 z)7ZakaVz8YtqD5_xDGV+HY~jw82dMVK|;1`P$it8y>7L4NFufDozw_UA zSH#ASh$R#Rd4lb}x&%Ay%9s5@Wu=xlpQKH=_K{jbV8c59DO zrkt04u(=Up+zv_znA~%3av(>9sPFp(O;EcAlJJypmeby(F#yeu1OAy5J@FZ-@;+%n z+P%lP$Ahv5Ze&-B)LYIFexKpK|MdodX=+|U(=@2}5*|79Pj^B`_EB=6|<82g7v-_XnSREhqkc6tKQ{uI2^ zPCcv>JWJ_uN$Ndxa9-{GhF`Z)T~gtKCo&!C{4ggSa3^w2=xt_B z57RQ>H|N?QoReVY7r~lgaxpF6uqe(OK>~ZN>8(xyFf62;vRnwRq9NjPEwZDMD0+x? zY#U$J^OkGhwK2S^*ZdQ!>wq?r22tMXANtP279=NBQM`k%Y}!2WA|^t@Btax}@Y%J|nIX#qS>mRE@(es?8sJt&1I%yHF* z;LFfX4LSG6&eONg-8eLo-t|w94>YL_q(ELY7)x5Bt7+0Ni zL}x5O8`7^;v9djiW1Bb0}_-npP{@AdV5E=g|eq zmFbZOO;&VD1$FC&NCo3WFnVKj<-_}L*sX5E#pKrA>9a2Gx3;KBA(HENffFcQMNa3@ zYYj=6#i4g2$09o4zt8THPPZPn7zb^d^VEy|Q8$O-%S*v$I!$eJ&Yr< za(mIsk%8=Qp$Z?S$<+X|EdLymezp0g$1;o`^GXX^Kp8a4{FyVUD=314IlLC>UEjLJ7F~Q)K(`6U&*M#CuaycE8 zk5bB3*oB6l*VF}Dsvh-u7<(yzaoSczjn3-{AunL13Y?~JT@(He=WbG z(p?2#b68B@nt4szBBfAPCL|NRb(9vm{D*ivr`sB@$_sf@f;4^)&8)tmiczY3y>z0- zIv8QE>8oQ47(=5YWMNoEa@})yvTCLr)mk*V#Z6r(HNLy*{iAZbzAi^sU%Vi+SR)#k zi1E9A=2M}-=D$&Hf|EX$o*h79L#I0(8Y5~{08=1|z;p3i=Xu>_L0Q(#gOO#@YQ;{}1JB}8t;0ShY(zVl z1SPpyyGR$9N0tuUaZLP1M%}O^H2jT{yu<>#Pk;ggdFp%A^{da2WY2bjy+1kI z>5W$~G|OTp6aQkb%bYh)u66HGqK8ZfRG0$$JrPrPe)=g=OrjwRsqHI7ng_x=%RO7c zjaWK?j{Q#Ije#zdb<|S4J}6f&RGHoy`s3gzZw-`Ye_s;(^rmAJF15kq3B?iNISWeI zjFS7P@0wYJ;)L&mi1ll}tEU=LGirmC)DY+MiGMVv0bpYXdML}@p-G1Z))5o{kfP2^ z7Nq(E_P9$8%PM?CeO?VKXsa;k!{(^7_ow_#6Zj~S9?jE#%^?GrqgQX>F@%=-vZ6s@ zLN-J?I{1)U{&y-*(!!@MnGpZyg;Y~ZOF6t35-ybiNw=;W`6a8iPK7JyqwE&{}rBg&_@jQYxxqVhQRRJqBIKg@)y=U6#$EayuV?+6Mo%8W2Z)gQ5#z=ug>gI(Z@>$RW#j(CYL4A#x!>0;Z8ms~U1Q>9EOtw_kRzf>;~p(VYj-Pa>jzwq-A>H8-~ z1f-28itnGXLSO+a?9upJdTZadUeqV02P|X&1wD4w`X@k50-$ESJv=;W%IQ2!?8Xp6 zxmgnD{O<>d`1`>{)vWYa5UkO|pAqYIUk=4lR<<^oFDjXnucoYjhn;w(uk+4#6?C;t zvp#J_sq8)WEuZeqgtdwe9SlzhW~7%-CJ1_zdS1w7b<*HTu+Xg z-@$J9kRuSbwd~Ks$Ui?#|1W8NdCSn*uir>@(B;}ecVLXaXq<@mTTH~sA! z084y1X(dQ?|G<|0OO)1k^A+=hn|_x7I7n8H(Kt!!8IsTa6*YB<)&D2cGwTGN^vhX& z`Gdtco^+x?gzDk`)s6k@A+N7P70SM~?c(rB+j z5h`ONJ^~ma{(h;_o#MK8{!t!(k7_A)bLYhDm!R+k>M!Uxuw+0Hb*A~|YQ}5bvA)Qq z5g>qrqPiE_-{$3NB~9PyT}yrkwHzRz|D$iL*HcpTk-F?njgW*7bURP~^Ri>I;Zwh+ zu~v;RH2FWoMMN&zvRhOEfa9vK*gD7ZG_?I2f<-!gSqzD?o}8lwOoe96rcFHe5`7{z2`xtK&||0er{_IR5uJK$J||2z;=4uf{qM9Wh`^MiakX^Oup zbq%tkwC?*dY-HN}{CrFSW0m|uTGb9Z>t{Je{MHYIV5J zd+(uWie^qW44;tDJ7*iEG1Hk#6Ru51&n zCSrrSW0EWW&1c&)`(Zk$%BIq$TRQVzds1fMXF4MQ$`zF*4tnjmhpbD5554I|v|qNk z78Uhw;)9!gG4MuRl|%N(?v#lDKVP@7)y>ts_=Ja-eJL3WP-i{U0FuPupUJR+@fojY zl2s!0EKnbJI^5J@VePQ5va~2$Ljlgd7R^#tlYXxCT$ddv7NVa1*YRX!$0WZGW{mjL zrPJs&m$+BpRgF~!_1u(uF1PO;wdew99+`Bv1GH!KA?Ubtq~ki;k*HF* z6p4cmeaHV2%vJ@e;JM|f0~Rc%hGpU2fNt3e)IZ3A;coRbyci!D8#e$z)W|&3b!cK6 zS#yYF{Rye35@GdEJ2)cMIWr0r|H3!-9wr?vekkV>5PfOmTkV&X(;vu*TP~X@^qOH{Y3S?{VrfJ#KUX9EnPe}fceYT2R6^b1$;k%x%Ih9#0cW7t_~py*M=uk5}wuPPm$FYTiE7gdL{ zvjjuN4hRufg$@?ZMcmp_ZhK7ZA<%f@e_DiDqsNZK%`Q-MBJ{EaW^ZRf%7acQxPV`> z)!&$brJPLwg-L(seNJ=Nu{M&J7$E9OCnVk}s$l7Q?rrNt2VVo38xG;)&EF<1BzN2e z)Mk~~Huk_O_#ZzvUs%HD1FR#m%Hn68N^i`mS7YAY2r5x(vG$4ITjP*ATIi#qormmw$akz+<=o5? zj*^_WY(2j})Rz<@+E9V8DTNvXuK6>U@ea_Dqt?PRdc+!{2Gwd8#^ai)u3r(i5_&e_!PsgDb;UDd2NQ3xY# zuX*ddx+ReH4YsVMC>7@Px5r5}q<(z2mvDW|%#!0X zthH672XNm|qqw!fA>`VTs8d()*VfeJeny>1Us!Pro02YNn?{x%|H}wAld0ADi&|L( zsio&y?gd0ggQQ43`F~t;!xl2!h?`k!uxCLy-F9niu{=970MwkArGZXC871$ zSeYP;Sfb>ou`*6ldX&-=YlB63+bNd!-Vx6|9SjE%0i(zWV*>2=NamIP0xpiPM?X%U z%`IHtf8lUzqz8o{Q-_}1|Fi!hR{N+95pTfJaR~KOUbX%CN17Nit>GN*@l4SIN$}2^ zN?YL}T;Q0xI!toIU!~i2PuR;pu_mZjJ`Q#Ra%#Mxbi(K`)AarB5HaUqW$@wnEj4go z`ifnx5-VTyjb#ep5Vs!wWX)G)zvTF?2JTJ}yAR;obvp3!~EMlg!Zf5yQkBi*79yV6giKEZFrg(DvtazrG||4TfwVsMiah zQtt~i2|-~c(Xk}S2Fu&6(SJDzvV*-083dhy49_ z=Ifh3xC7ca{piA7TJ>~9YoIwB$Xs_0(`fW-7J@OE(CQEL5d0}n$5sb*NJatJh zr1S0te}JJPEKsI=_8bHoFMI9O+J4tn2QW4J%_>d9@r@s#ezhHz^vfhzB7)hyIt6SZ za`%0I$v<8?CK=oCR+J33gf9{qh# zU&H=OKHGcZ7&7y7=!2UE=WBV?Vq`+z4_2_>r$UpBs;P%9n7MDbVMjPbV0N*;3o><^Z{k7+frX}QrI?;{}hnL^r!6<*s^c1yZ$*nF5-=P+o>q+CI5oGfv+fg>z7zoa>|X|!-c(2t-r1JAvp_I@~d zoT-Yq^Z-}$WUtbF@6MKoq@v}cg}A4cJrU})Y25}(Dn{61g*`2uYO+BWmG+wJJiR7b zUaUPH9wxTl#Mo?n1?dz+HMStCI@SC49KYM_!<69?ss16p2oQB29~7;Hx9sKYcb`Ox`}&5} zPp4ZezOB|0GvaF;30J@i61?vM`5{q3i!}1z$ijq(UzU0A>cm6^RaNfQ&GOBrJe`6{ zVvFldt)lhKrtg2bd<`fGGBdVg$O*AFP2x0oP&=oWLLPAn-1Fp&>5q&V_vry31$d_q5)2?FITsClPo+%CB_!DAjypVlU`N#KgijrpO3}!HR`~_^OaNFP z5$Cf1p7`lk5m3rhPE}yBK;1Tcbi!BiC060x7(O3@ z^iRoNt^Tv`Q)}9wOwjR)Gh3}rx^B29)a$KVyQ_xnfcf^j*F`OaXbyW#9U!#S>tiAd zah5uR&QpMhil{X>id?stM?YS&iRc1YVdhU~Nj(eMvHX-;nP|DR)u@ZX7k0}Lyy!{k zwuc+>Bdd*dLlYSAlk}W<$D(=h;p*H`a>ch6OH zZ7;@jOI(J&db_?f^`)YDEb)*QIAC`?QFJY#d*Vu$cc~9Q9ie!5yfwbZ(#X#g7O$6- zA=ZOeB~O4VL;uqIN@03{1N}KphzmsN;7}qFsbMY@qoW zr&Im?v88-In_Fv1qmVPCql>thsYEO`P&UZ8F?9tr=VZ;{uN4{pq|;`=B+M_}LY4+0 zPj*>G>2G+?%Jt`s8oUKX6buQD5dV<4?b%IL->ZFD{)aIRv`hOJIPS^vlRPFNt796s zI&ibpUr5N*+!;pX3!-%W&Ce{^{LPj2W29($0Gia)r}3_TuSUyi>yV@6sz6Bf?1U$7 zO>thL4f5=spK%@~v$~?Tht;`NANFV(-lJ@O^1Dg=mc5 zVGF-7R`h@K#JOoOiI=n>Mc~?%i`1V7Ue5_Pa1J!tM{C9DGGS~$A*ox_sS&Q1|IQZ~ zYP`;cp&+r@B#ZnxUiRh_AIqPBZ6FIHFs1f!M)Pc~nH*(je5&d5q$Mx=4=#Q$Fce=M zefvImb*ikjf-#dsMzY}jTz_6p7sXE+&_giqY>$^T6%BIzCFW|Z0pV7|m6f8Oup&R? z!IkLHjyxZ&rB(l}VL}*xE%H|{^vg>v)E?^DZ}I6}PX|iY)WV8wm+SArFq=qh+QiE{ z*$@yU8zby)FQoDTsGfYxeFC-wH$j?dz6X7ui+|I#+HShYz!I^mi|45-t%2}F>SqYgPt7ta!tp|zY>=Qh0beU1jL#VJ|9Vj!e$i?nM8R1 z>|5#Pt|?&(s>%v!wE&-sE<$31T4rZQ9=B|JAKxkgwzWPIbBq*52u1Ee2J|g(;^?q` zxM%BlbEx1c)I75rs7BWIF4Na8_O3_ifup1vEX5ahO4|3?zjIWh<#Zef+*GLV3y!N? zNR?DN)ZkzB2xAZ)d03_?6`D#>^J{5K24(PyNy@<_5{qLl5C@R z_=een0uyA#S`zK5w$0HV0Vv;8SLmrM66Wid-5smH8?6rpBZk_3CblBIp5pf)hiTqr zNpALW+vYLdBJCTmrh9lsRJ|-jB!D!jEUVJ(g9wtg6A!u4pu*B`*BHK)k7iZcBtA8f zGHUW?Jza`Wf`*Vq8!WKJ9ZR3G5f<;(A0MR=6}EMh2S{@74txpvh}KK^>fJkWlAdN9 zC;tt{7r5HKcXKZP4-~O0@AAR=P>P4DM1Cl+W6%X?F_KK(q=zzlOHxuDQVY%@2lmXe zsfYJlW%8@CZ{%|Md-wVo)Fh+fGav8#t~HIhrgA{2C~mG=KR;w|SGfInnRbeX3zOU^L#<5#QmXG&0k4^y5h=VixI71VWPaEn>Z+OF2 zkxPt~W7=C%Diwvnh}x60L;)QP&a*PC%|0L4Pau4CY0^)+q~sa0rftExzbIu);bY!! zUQ2kJFgUhzzmOH+0ogEXMj?&0GrX;r|KLY%hP8cGaI4nG5O??uM*c+ch16+P{5^>z z_tib4IUO3V$l|dk#ogOSy}Z0`!dAEJP^L<(+^(|O5Hw&-ah-)?&I6}vI%=saSxzQ? zgOn}Pu0NR-?s@TzBRdaigsf^qfaR1jCwDB`9I7HC^jKyY^(-wwvP>eIGZ>bMB#j@z zFYBHJjmgRS>zM8$lkSQz_-L_!D3`frNs6iCE0+`3P0Ch}mP@sExm^;IvKrgXsZBm$ z;fLYi-a~aM!xbX+kwERY6j4eGimomOxGG=yQcfu<15%xY9rvFn!n|l7=#%WJ9DPT6 zv8<#2>OZq;|5S}o*I_M_1unqpgZ-LF#Jh~Kuw6j$fd^jJXGRRSreIIN{0e{yChx3!8t%S-wA zh>S4ExdR`|{=(9tBIA-m)-9SAk5pMlVAnjJeOrO5{BgCs$+}i!af#);d-&{lE|jm# z3l+Qa{vrsOCv$-3JSG_}e$xO9ZG?3q@uV~Le>X-xlaE@{YJ*!=>Nt1N@!x~d%Q@5H zhSKsgv7EaG^uW5d$MYv05evD!qUh3p9z-@8V5y`Cb&T1V`VGAoPOJd=wy<=1W929J z2AjCBF{?>&h6Czy?nC6QN1C~BM~Ank0Od9n`*8HpWB(See+V%IMZ$oyS6~0-uvO4u zy>0P?84Y5Ptl&7>Gx7rzcC8&a{Q;kE&FY;R=Z-(gst}~J3h80a$mW$W&TuHrs zy7#6z-3R{6mNX?mit$Qv4avqwm%nZUa#l+?p6oF3Nt=A!9$>HI7yego{Exm;o-)Uj zfRt6pC}av_k4<)ZZ7FXCPAg~v+Z!{PAJ+m?*Yv05H6`Z*daQJcLRZ01^k~gVdVpfl zmryg!ho{6@^6efOOSUqV4>cj!T`iqp+y#(z`=385o*7p6JbE**!Ng#+wB7az;$$^CREOn5C1kGGVz za`n=mA%o6zjbo%buQPLy8QOd2%&DuiA4&tOJV3O3c!Im!x(uEFxbvv;O`^g9f=#B7 zi{;I7w!z~i{J|EtfVm6aX+KS2z2M?S4%m4oI`I@fTHQeZ| z^xE2q$q1X32nzXObzOnuW_|UFGH=I_Z`e*Camk;6eF&KXzE&eYYOg3=f|YR>Tf^L8F8C)vH;MwzeA6gaq0(rxAWl=j^#T zT~(Nb?y21QH2*pORTDN2XS6aj9gkT1w4?P-uGT720=bj7cWC_1 z9Yv%n={~5K!o9cO@aBq;A?$5JsLM3t&pI)&Vy3mN-V{vt$^^R67qxmCNKiuyI(-O& z(en$>QjZvnhesTUyj|uCUn<(Q+j?_hw>NG_K|MU?X55%+GfRk(oloYtZEK#EcGlq9 zejRln6WEY6w1SXVxuCsVCoA@5`~=|1YZ$bIXx>A zvD%{T;o=X{zc(s^aKh+85R2m-OxMArLi;1$&pf&KCweRiEL9_#l3T0;;8(y;xK1MVrjjPlTNEt%8cI4iQK%`LrRJ? zJniGm#El7|^_@PAq{w~!rr;k{29|@AP9ssu{it5LH)>VKSkgFj@ri_B;g@>@-+MlU zy$Qb4>&F+1LPz(UrSw*;?i%{Fo}}GB0E2%gCf~zy&DmQ2aRvm%BJ_9<1uYdhN{;+4 zgx7x+Sm~8;h#0@vRQ;TLh(kC7+yhP56k=>8wU1(<4w!aQ>Q78oHLL9{r1ioJ{EaFa zcbfdk6MdQ3Fc9VtM+3nV^E_@a?xWC4ENQiH>T9aFnKa;8_#v8zT6nq#M^(dH5gfqi zULFw$Z(7cV!V{zFw)+C%R=!V#{>vM3d>h-uNz9JQqjo<|4UgEbo(@{=dOcglL?=d@ z#p~6M_F|#^^X(m%2fn`;T=_w}HSQ+7b~+h*JEP}d;mo*ag~Gm=Q{nK-L^7Ycc2gS| zTwK8Sp*r>|WtnwJ3_Sj}P@}XI6d=q}R|}7SifCo&01KUYooV=YFc=sj+!h+TxTF2} z*%bGwN|NvP4NfA;rxPcNF=Lt z)BC{$^pfX%9`#xeu@h(+eD=6Gp9iz-QR$`YD|R28)w>zGSZBu65Z{g)e%-O#=z{_U z1RmuVuB`bb>a3u2S&?(34n?dtJ-3e@?fp0*d_`+QCCzMGS)q#ho%Yqw-YOhkC-W>5 zB1wsDNEQv3YHNP@zon{YzLr+MEF?ZeD^?57XcijqM7n?Dmrmg{ALtE$q|P{lnqxJv z1)zX(a%sv8C#Ghtf5T)xFJX7Bj-RYLJFEXL{X;y8c@2ts;cF9tfHRQo0i8y~x&tv! z5=;=@x=y18qlCV|_yyPHwSf7#&eanivsT^lCfh!jtEloMJkkLem^?5rNZWDs+k+f% z@|JVQZx8Ln;`0%pL5`YFC&+W9;N}HqpxJvWzyO1RYlbve ze1TP)41L)$Hr5yHd1d>Rx`!~K;@%Ny_)+(|H3D7r=qdONvUJJr-=?;0^TK0Y+k*wv z27Yp6qj#RiB?#d&)nZ2%BSG9zlFQ#|S5UPY-j~1u0s@+b_SgXqW46w4@cUkv8{BFC zbXlCG-UXEFwNmQte7O7a;>Kq<=B+rInp4_oX^Ph1F{Z+5o2A?K zBhiI0Cmp;Yv8$G15&-F{9rtU*ef>V<`c8fmj%sCO&lS((Qu~b&jg0UI&|Im0T8G+> zpomZ#Gx%XH=_FxN*jJ2#oW&SP5JKBlL}$lHZ$+68$T!FLw9WR{HO*n=IG6m|yB{u>W5;jkk%-Fct%Q{mg}yE>RlaDv)^9!$(~Vp!Y@Uz#=p`F>q4x z3dI7Z2AOl;)<*rzCHw%!)lgouaf*x?GqgeZnn2`H`BgvGbyRF^Q|BY!^&4}w9nI(F zSXxezX+R^x@ndc-FH_VhOf5WHy+J2)yY;ji)Jaz@-2Dx#tbo=WkBWFHmNp~)#gDR$ z_`GgvjfhL0dN)Ty0+9hdC`z*D;(iDX4g8vw&7=Be;`nTuzN=h6TLwR;N) zUEfjxA_Dy?LQ;WSz*3kyDdj7Lqiuma;~C*hJsOSS+!K4!GQg<~IB zFeIZ5U^5rY7Bdw_FOa$3#k+=VW`96eRz?rNw1f8=8CvF0%|(BTig6gK97NDQ z9iHu+f?EgWTGQc40JhqJSzb;(IFK-1$3zci&xqPY5`bY0SEa{T`in27X`rT-Xtun8}Al_)`hb_v`I z?biq`yYqEpmmEE@YD|4<@RLcbjxmepgqA}raws+wQE2uhzHC?h(cc^=+Oc{i4(+gc zlR$Cq+-`_%=x9cLW3tdU0fVPJB$1$Zj|Z3h!*Zlyys*{Z5C9F#?t4*4>QWiost>2H zMd)vyjvccbTmi6?yZPIrCTSM)Os+j$?qj^bI1}o&y{J&mi)TEjz?nu617R=84- z)GNw^K#ZJ_<}7RgEvoT!2DYEd;c~s=jWoAI*v+x}GCSy+F6&vvjxb&BK zk^1Q~`MZPAU4BMh!j6VXoG+Xq?^3A|h_x#-QCBxr3$Hi-Y;#$ngvUCB4XC+tO%S7 zL88h)E+$_vF4$C+H(et89x814=1AFDJaySG=ENp%V#+2E= zqNVXmN8G-LECvPSIP@b2SZ@<1!XVVcS#}~l~8n`^(H(eE#C@@EI%+7 zz`l+QQcAzEWDCXeL-p4(q1VA<{L-A(bD1MnB(p}Ji#V!!_zLXTcTs@m$i4Ap^Gg#! zzxwTgR@Q6UIMBK$3ez!aTN6z}ly;kZQx| z$6Ym#`=%hiQ8^5@z64e`Z+#<$@f>Yk`LWVs%n!BxR%2Ee{(&2=bQ)VR_N$-Xi=rYws!DN%(}9093@Y=XgYr~$x^B=M9OoD zU%Cz2nMlbs1@?!)Nt6%b1cQ%t-3Vq=1Tn^MqJe4$8a)iFNjleNwI(Yy?=3JK-t=6< z!Q#H#r17tfqS?qtx10RTu8`l&lPX_m9}frjUXc4*E{DCQ>zC9bc2Dc@KcdJ7)c=uCHa z(PDt?UAEIsB&|zAcaA2w%R8C((gjY7&U0P^G^+Kv;Y(oNxns0+p}W#`dubBYE_c7@ zZ)NXA{flFNP1cC&hr_afz9#QnGh3RFM!JK*qna4Wo8o)8ZBh!Z^kuDihPQh7hX3y5 z>!O^?{B3Awpp}I!;h-L8y?OQycLqhWSAV)2W|B z*-H%#5MiM%mzt#U)3dXg4JX@-IFPh>g!1YQTKqgsLOao7SLlk?V#t100Cr)YKRZtR z5hdcRA+>&g*Vrjd;B1we1A>t#^W!oFYJ9AskaFZmZ)FxrKgTxkcQ0PhbUR3?YA{0f z-ABrB(l@SeP!3*#+zHw|bYvpVGAiZjHsS+0SxRK#Ge9iDR1E*+P8psH7IEu+-Vi;r zA*sqRY=O_6aN6S4lK(-T)XW(EjEN+?2c^cs4_T=ol_8c%^gmA16V9|Lf3|dsu-85y3?ytPY_S zep=USp1sZCF|U}glwdMs%@I82O@XJ{WVruOyq?xC^Gkbw|1{Oc$gGGe_rXU891;9lF}u9Km~$^_s@GbyMl9rD;F>tqmqwujn2-l ze_j_n>DKbR0S7!kqjV{&IX0|5{;F}P}YQDks5|+;Pz(W1Z=K+FCOeYOa-7`&&9Cg-bu5YXAg5-Zj;G?`gvbZ8+K+@D*qF zG);J&b&}wJGcK7GQYuw46Z)uwuKK8EIOak6qca^Vb(9e^yYC7uz~5faq@^LuZjqG+ zc-9{0YSp4dAGI%vU*_LiL)90*jIby25nZNpKL!w;UPNpJq#{S;Fvu#?L zrbKTsFo|<1GTS%{)ypsK4BP^!@}J%EmF!{s0CeZ3YLohhZ>Uqm`&qW(FaLNmY}X)S z5xEIMlMlE|k9Tiz@D{nyP4SlCcnTZOpQ}u3+}qM4FtdP;rcWA}rq$IyZzl(bb3+!Y zhCa^fdgAGO0|t+4S?(JQA0gDZ)=Bbdw-;}5fmnRF$(EzjrPB*QRd<5HYsa}hc%!ji zr8`^<=X#`({8}Rq_Wn6=sR*u_FfJMpan`F7_()b1(5%X#`cExh^ABneD&?x7s7 z5}@q7aIM4P*QL(59qf@N(5IBa+$l&X^BD8{0=}0X*m-$Rssx~8h3r%y1EkPd#{dfK z-{Vf8_s4&|N8JBQ)kLns9m1C95`@&-mZa-&F6X}vkO|Gk4tvv~+h^J<04hu*#Z+9Y zq^ko#MZMg5=)}$YEaVviEE7qfw{Y4@X4&5g#MHwXdoNJd8rX~(gr#OF?lVk{HwWCL z^=(ANfO}oknX*1{k!dt%{}lVlP}F%Ut>c+wrAMV-=H;u0qRsl^oUi?ZEzVbyuhfHH z|ENu@Dg*Xv--zBD5Qq9^&rj69A*_2#&8^UlY;C}s6BmJJXccpHuf}O+%WSW}_d@T7 zyK#u~ZCbT+pLZtOwli1@K6t6sgaBv+{DOjpCL_a8U*S3*mF08OgD?VxJak}9( z8cUh8*(s(8a<*vTToz(%H*`6EN3Qze3A(f4ywjY_*e+0nhbT8w56qig^1^Ii>ZO;; zop9B|ulH#vGMZYd3VYe-d_WiY>vZ4OXlJ)lMdHZJFnj%3&V~GB*sW(9tds%~^0rt6 zsNyw#gB5;Z#blPF*wnVG#Emcw6*;a~vEAB3hYKX*{jUf?2ybW!0HX=n?h4eYTM#A_ z)WSi`&b_}aDby=+@Ij|Is$+nXjWAyI&tZ5umBiDc|5hNuWfNDp_hBRk(Ljli!>o!$ zRPf0@jW{~Lc}(wm5Wa)XNIW-dynJE{NN(?DoE1T{Jc1DKS&nj(F`x6W6eN(5m^R~F zFFeZw%~KFhN9sDyKUuiAYm^>=h+pm8Ey_Qu5DYrvrt3>h@CvQjqN(dV@C?RnEKsLV z!}Xf8B+=e=Z^vb7k2_m48GhzyXXCog)<#uv#0~iQeSwx(-Ljk=j)4%^K4R%Ise(uE zTXL7G?sTH-twy*ZnPBNeHwRNpzG}Q=UumkYywVjvI~VR@>ZB~}w!%-YXf#!n>P^R; zano?Zb<=xf_}jvI)B6H#e}8V|KAV#>|Dr)o5Q4yXvV_f7^_^vYgrfYp;*bnJzi>|) z{saErGwg2ZRRy_l6eM_c*IDKlbyYzG$4FQWz~A@?mZbPJ{j_aBPYRd;l6Kh+DNJV_`uz!&>%I-PTnRCF{t_i=g(h{;6AQV< zAb>_az+Tb3viC_^f77~IE16^bx0p6VimLdRe4LwAqJ%V4Ur ziR5f+p#IDHF^Ve0J+E2e1pG;f6w~g3vew#uHTpple${Y8l%9oUb3c1Q-%YvB^JvCB z+Gb>5#h)afYOGgAibb1^V)SwxDQyvry7&MIfQ_tKw*={L#x}QPfZ&}njU#);C&-VO54OB z>Ko?xYiMV`_SyIWVx50ZijzpN^R^G1(?Agm0M$JqY%#{f~!pc^f%Q56sN(< zJ>tNB9_>noyQEVs22M7DPW|mkbk=`ten&*S8ekY7Bm3f#6@WnrJDmZh)4LQHIjLOo zu}Pnoe6S_xoPn_eUxmkqGsl6MpqI4=l}jKjWu!NWZV~I@i8&Le6oS%E^V~anS4jzt@>-Zni^eM>FwI5z}!Oa&Z}M@g++u0@cO$0 z?F`5~1H0m9a7euR=-a_UuTqJM5W&P?VflDWtnE#X{U<;Sc%nyXQ<|;ttC1Na>++SJ z6T0KzJn_0j&aS@Qxq;hPqrX0#EE>#KZl(mfugup^gyiX1^2c{pp2GR)PZWH)(R*-VoI1$HJ8lFgZ1R}kU2 z7#PK)BOPYws@2SNNS&DrOJSZzKD-K1aNVv!yHSi5&lzpb{`g?g_Hb=*jD4aGcVE(| z*aRn4gaj)fvW5DkpQBb|%u)bRdOC>mn)s?|=TOpLZySE1my>*(Fmy*BqW{cpm-=1k z9hkd#EOZC>{HJT#9F%b6#%01-pMScOc+--86pd&1Kso}MpdKE7TbvTO!IOci1mHEf zAyjg=vVhviFHN)8R|N0COd!ggjL1+NH^(~MAhq;?^&4tYY4O7fUU4Y7G`&AK|Cz      hp8!e5Rb#MM^5lu@^72HjQfMC#ybaD4k=`#2zXax^I+T0S~ap@mePd%q!_;>VOWH z;8};Cj0bYE&Qvq~n? z{Z+D2f9pUzYRUH4_qXKMSv$zfLKEpRmAm8-u?TAg0?zr6&kaUSN`LkH?G=u@{Tqrb zWA}Vhp;?0O*6+ag6dmQJHhmj$R{c=RqYKRZLU7_X>fVdVlA4co5U!e<4UlSg&fCFwWGWlX4Q z7!mg}1$*hIwSlsb^K`r-+V}c_pt`No#1{hLz{kqb=J^&(Ad2r4mBVoV?TCrKW$E+< zdX+6bL;b(TzWc9<<^S5NSGfwxRip{Rwa~kuv_Nc#AVqo!y_WzY(nDfFIz;KsM5T%J z-XxI{kRkyBglZrWLJuJXLLl&spXVQVe#vWRcC&TnJ!j52yKjhH3l)rN$JY3;!ep4Yp>O~=I{isUpd!O&n=P$7mcjPl5jR$46<28EM z?`&Gdr+vFZ2@i1pM(Vq%oTOHgO z#g~_kyZ5T|S9SrB?u=iTmsC543Z6>^e@bD%f0aX5>NucjRy zdHkcQs=ar}>DmK265L*xXRB*R(k~@_;mmLMww?Fb%9;-?AyFl3`@+s-8k>{+!QGz) z#b~{4znd*5#8!gw{gRVBm-$st@|z?fM#O48$w`hXOSy9%;@802z|tmajs=xV&H{xP zot2;&3*lHP(Y)p0K4OXIh3*FAdS%hM#>DE$L)V_o)XqbTNzMiZXUgA(y59QxVe&38 zO79Sn%_?3HMCC+Jfvg*W_W=?<8pW?EC$O=V6)JxC@2ce&2o8v+F(pb z!-3wlQG2o#e;#;Xqvwz1HP4yz7+tVwer_)jzz6U+JgqOI9jZ{x@bb{J^-yn6JwFx@Upm|58r(uewffO9V?`6I5}edtsqLL zf!jov+vHb7=YHv(H~3H5U^lFSS}u)O*ChyE1ZXuZt|V+Tx0M zAt8eg@d>$>0rNtZ5MP7wqIsF%@N3RM9|crStl;!tf5edvwloy6v?}VFWUW~p_P=IM zhf`&DN8OZA`fF8O`IaK?pd&yzJu9f{Vev>9Hi}d3^E{F(f8C%r)&Hc(&?N ztX7Y5uNAlzauA?qbu1t{_uQX{Og|rTdm{D3a^x&II3Z~2&viApck3`4wkzqALbo8a z17!-Rth$hZ4)$0pDY{C~{`yb8u5}V+m^pK* zWNO3ycyc$Cc;ilWAsxQ^lBqkD`UGqzy-#Gu8eXaiM04#~M9F7VS>mx-3X?aFH@T1> z%DzWtVM`D#Zjd6;c{##Tjc5;Eb+b%^p3t3L)l>KMjpznORaTVe<*tkKB2Wn8H@iZMwoCRPv_vw%d5Jy2xQ^o25^bH}U8>pb6y(Ust`xPl{lcCf+|%56h4la%q5a%rc*p$v735G_Jv37iY9%FK$L5ZF%g$dS zC?hCmsq5vpAmUwnPn`%izw@3m?}S z*tgS;6-ZA&o$%#=3bMmA4HMGpVBS7$&7=L!;W6X$)5~~{5C@e9o#bbm2f9f@w+pZ^ zdx!#u5$yrxpnpQ};y!7VS;kfq8b2d0YzIP300X4}ho4(NWe0QEFyAc#t8Dm3#|-KO z-(0`dFB8mLxrUtbQ$Q(1W>&8^Ek~$M{yj6dLR?{Y<{7A_H@l%SjN1;lG1;N#w_fc$ z>g0d>*($%pfWam4by_R8cr}Atx$p2Tx>^-C5YQIBjUx$gI8hAeEWs3xnVOH)ta!L z5fv!=>NFr

      $`WOt5#?^_;ogD}>CVq|(s0@>RHJe-4S}HTbN*DK;U(+6vfnq>gbgRJX#UnT zw?(RMUFo~}u^EDMvLeBytA;m8yX{1+NAtJa{2G#E0W^swkq@N*F zh{U0np!OZHkon=;F^mKrHOpvLtwSt)TkO-C5Vhg<)_Ivb78a5WeS815RAbWFgm-gq zSX}mH;pnTTq`&!QD^Xzi@(s_dzRH>oT|nvSq(~rIT1DwvawWaHM=TMUsI>Ow0DMrv zh%-z`Zv~GD z$i)5aZ$LHp?^lg71VWoufy#+Y4=5-@KnVk@f35B7kLzM#XshAPzbbLVYS;+Xzv@V3lZD*sfLO$_ibIT9l&@u@m zQ5MfFLy9L~=AC~ih`O2%Yat()17_kWU0kB1@0F|j!@)@m@xCo@9Fv!=bGIWG*i(C6 ztkvp$IX1jf=ngGnST6s+VR^%^;y&T_sC!GA=gvaa%BiMr(%2cnD26XnoEO_5y)JbN zqM2|isxTB&_x=ScXF*dRA`=N42`+wN#P;%l06RSLg@6}Il_P6{s8ii+c(!RF(kg)e z@~_FE45{fu<_hKJC$<|X;}3P>is@wm1~ly?TBbQ)oWH!pj_6sP!x!2sc2C-?awO@6p1X;T+9l zMduTLlRlFzLQJ#`1+k^+tpJ0?rAXY=1$Zjhcg&YWDXBm1-6Td3&m zFlg7Mjnx~aq7iWSFAyhTv1gMX?LVk?g~o0B2^aMOunz=La~MyOWJasO+wm*}v(px% zrhoHA)bxNvSMb;-uj4m#a!Htc_DEA{*d#%AP9Ak|i>+qBS?6aDi8clhPEUqc)g<9D zcU&y>?PlNBh{GIde;C8K?=N$dC#n_9M1~J-3^}xN{ZU9oBs^MR0WFDa=JAI1Gn`Iu zpXQs5RLbpFH*1bkS6Kn4;7UT3CE7U*$=5lU(9n6kz^e_Rm{4>z_E9gj@;hi-5Bee0 zl=Q-P{>SafNd6B5;8D_GAP25kaH#Uv%XcNELRu z?XCbZwCvD+nkI`}$kP`fHbpc1w*Yt##;<>47<23laSbjp0k+O@gjAxky_F}!ftOu< z6J?qe&Nj=H1{A9Oi!Q=gt?CE*HPl_UVs;V9fmVLQC9bGxQ)U;GA4Azb6V$v<0Zm(Hn<+EH0^XAoJN&K> zu1pSXu^#R3La0v8DVO*91W}RQo>=|@U){ifjD@^=5Ws-peSVTAlFgZ#K;V&4%PtVl zCf?%#MqmKp7eP8$aP*l!;H6e{gYeRf$4-T09)}FvlPPyq2%H7M|KJ!3Mwx0&_0Yh` z1=7)fWFyxvcJMubt|z0J(41HOjoYs^WN<4Gw(!)Mo#Aao;})BFOt60&<;XVaRLK6( z%^VG~VP12E?BOZgI<9WlvEuXOFJ8694FhqjLcpJ$)x| zU%o6uX|w1YO6U@5MVg_(gL-ob^&r7I#Xj=M#+*StNqgh{))W&(UPb#z(Mj9RtMDf< zySTeBt>r2X7X3d*4kl?-lt1ww)MyjN(1K>Y%Od(%gyr2zw+?1C~J6pp4q42S* z`@o-?!BvGhA_$?lD7;6*`0b82ay=%4QxOWan8*wX_^;WC%vRXDX|`kZY4KHFcc0)l zx2_i7in5yNhMMrr*4?YikaE4!+eobaXdu?)os&|o;b>8u`m|e+&x>Q2e;NTrE7mEMhPzQ_zsk_}<_HDwl5wS9FcStZc!v7aFs&%HdV zEM6NF)iW_*%P(q{iMwOb=+&ia1+CQ1lUt>E6Tdw&D~~1N*=uKPYvL~ALcmLF9dr#I&`F5G>Mnl1) z0?#3Fe$=Cfj*UZR(4mQPD0@|M;(tSl%8dv;Fw0?P$9>HQE9g7%^$J!z$1!Op*tv%f zD~5qqRQNG#gY(D+ek_gJaWSKwxxD*fmd2^^vxlu$9>^IrXM~VI@H&Kq6hWt5jJExQp;(el0_tvNGiU0g?R$S<< zd?mQ$IN#P9$BUI#y?g*nz_prw*Tt8|50_Q(*K=tyf3NWb`&#L55PP3L==%i_9Z>K@RNM>z=4rilLMg^?i$rmr)cr^C9 z0@gp#!QNGY0;qq+uyF@J>>sT`D5@!NOH?A}W$=@_ta_e?N2=6VtW8X6*Jj{c{i?hY zd>2A~x@wh6)c94*v>V^-JCCP`J)&@&9lY^b3f_>jm2^Xk;1L$a@qOyKYwlLIXTNgQ z1iOLj6$MD7aNCw|VD<`57gNL+Ye=Uf!o>Fyxv*XD5g#zh{xQ8Nfm_1Y5XQ;?_#;4) z-y^iaS5N;68TMC?W^P}gr<=vgxk=S$vMS4cUqP&Y*|)Wb(E`G4q3amMQ_)5&0f!2DB9> zEBkH@!n&?Dkrl9MU?aet?Gf?lG7mVojfr5MhRuq9(bN!n;L9V4yDdZPq9ZZnODw)} ztG3*plK#DG4sRqA1V&Sef@K*+-=q=4kIr_f?SOf*viN+3tE`QQGopt^epj!ol-6Q) zdvNE@AfH2R^7QgK`sM9vJa#{*4K+zRR$oj|Zfxy-g&5=0R;oe%s@xw*a7~IIs9)CP zjR}zK6{wI_n|B6|%fDw^;Io@9brom(hn7EP-C~=5SHe12C!r;a{%T7P+_(%@@!Pgm zTV6u~8tMpNEnx4xq5Y8$+tGLIA_OGVdR_gl0vzLS^tx_H_ul)ZHAJ=Zi~w)|qV|mr zvrV~X4Q{ICQdPR@gIDGhyif7>#%csKeu-6(IX0FX>*_i(Tm7_il&zHC{8j)eX$XI8 zE=-<90pLS_xg_1;bf*?<4gjBX=>}YjA?V?*%5^`hIUW(%miz5-u&p*-Q{{IpM&=OS zv-OkDMXkss>=CEZECZ$zlXQ$P7rC`d@Miy^?#~}mAaw%U(8Evcaud6J!TVawfOHIL zrTLO*P*AUXC60ZxeWaSa zU9j})>vI(XL56wLwUJ_W1Lbl`-ZPy&A=tORIf*ir6`TA`Q>Hi^IrtpD1Y|L3YdzE1 zrM@A>+j!qGKWw66-e#EgaliANNLwgwqA0+_e9UvLU@0ONwJ34W{Of(+btnX+k*rMO zv4O-XnI$+!DlV&kybsSf9kI*Ds1=WpOuT(7;(m+FG3C;mx%#6muD9O5%C5&W=|DHE zJ07r9M0zAhp{tRz$d<3$`v{w_p6}zx`csSc2kGR>$J|OD`bxIEJ1S*m>->{%CB|L% zQc7JdCCotZJQ3>C5OoBm0Tl-iDTtwNDL0r2MHhbzWfFto>Z{+ZFA^U}dWPRdnEjq^;0PeoWq_~X)< z?i=6!%RniV0}jP3R`wOQ%g&wBRTcp!aT$COit<9ZsrgxC;1AwYCf)T(!g#W@$Vjw? zBkuzfZY#)Fu;JKAc*D$O{^Qrh!|4-Bnj9x+HLLiU91T8ELfKAtuxs#?vwA~A^MuV@ zvt0<|Lr=KZFw%M$wI;&?Yg_18surX2Xq_$%ivezECx`Ttg zKkNsWfukxkvL?C~v^bo=PHJZ8%s8;U;{smJQ?54mzcE1|)oH!N6}$c*@5e zooz1cEgEMzo;l{0t1b_zlxhezbMyW9_ZwppICnvK`t_1`^o&ub8KS8E*UsUS5IF9Y zf8S-CZ^$=MZT_STWwPM6lYrac!yF}U#hNfdld8jHUeI~H12cAE+* zI}|ongO(089at9usDbZ%b6RxLS8K>T>Gny^%ouXuo?b)_i~p#qk|yHx^90$cGz`Vqm>`B`Fcrb>1`7}ifU?C_w>#D4w6P>7 zRdLtF2;Km!cP*AnUXUnoLT5j6DaMW^I~2XZG z@*Cr|NzsO(uub#44oZ6L-f6C`rjw07x3&yEvqAY$n4uJwa04Oz^K&3zj(O(`^v#po zLFMw`QiEjW28{B{;*zgd-^?f;LXFJ&3y5a{P96h{qVZQ`GP51YRh%1|tSB1inrzS_ zdSxotL^#MteKCGuO(z4-Lo~eIyErb*9k`rWA{|o>cYT~>D$+6{6QiDVXAM)A6K967 z=fYKl`lQ2R4vk4XVdko5WMCvNMmmUzci+nU)kc!yF5|p`{u=lrG`Vlex=CkKI<%x{;{s&r9Yhl|v-o205;9 zpv`_#Te>HCd#fym#2#Kf?CjNEb8d=!baAd!M1?QcqF0T=4m4SoyaGd361V_x5nwl; zms}PiY#hF>E)(WaI$y*1PJ_Hf{3}W=H}6n>y7p5c(nxkZsE*8Ezg3DAXnegg5o#Un z%jbzhu8tHN4vZ1m5t01Y_-3(thq8V8#XktR?b1m*$$Np}n7#GCWgw2A1Mjco50ctE zoT?8C*AZ4oS4%5+o1JP_+ey0qO-By)1 zGypf(6)jf&s(W=JQM}O_{YIRmZk0`KWQ%+Z^X( zSG+M*7dxCvaw-_i7Z1UG^vr>>iYJRUCNKehj-O+q(v!7%HosS~?+k2)Dbs_Y_i|mz zlU-nrmJx9#cE|-qu7iW*ZO%4tdv{G-T`ga;gHibJz_^8R;zESlqPj+>`MA;qe`D+1 z-s9)F14kBn8yWda!^Se&YT2e*w!DX5M|l+I#&FZ>pYZTsW>@JWJ`ZH|( zuuwsSsGL!34!1n5Wmz2MJd91BCVtSzadG1>Nj)lybY3pdQwn+{pn|i?cBz-%0^D@% zmKp!%5}o7dj;T>!Y|%(i1`z7Mzkx?l|K<24Wu#>JsNct%a4n|gAOjo_D6TDxG$pul z0Sq#-{jCt99*|xm=O^TabIy&G=PvEkf1cVYq@D%L$wRx9#)a3Mk@F}AG5B`%I2gv! z)%N>m*!SCA^`;J-36k_DW9=?+6&?Zz9({T=!z)tFb|k+mNmfM9YfEMvERa%C&!JA3 z3LWXDrgu}MMcf;HYaT4W${kg66@^~fYuFoAxzE0{2TSVcYLm&)BX=@aMq_s!dP`ko zGf)WrrIs3wui~$d3#!~G(o!PSbeWg-lHvMXwz(@)gNk!kaHjKikagzU$T*fakXxol@ zq9*>qPYCea{h;+onF!ksb1nQ;3cm$5xc5LOgTm;4=%a&;bAl!`Zte9ZaJvr=PJ9_Q zvrv7F@TdFrD>mXnz-G8|TJ#f{-9+5ysFwZ-xQ*&-N9HSI1MeB3wW-G^GR+98I1QPq zIvEJ?_I4EJ9K!HA!dE8jj4r?;SBGaONp|pubd|Ko3tKMT%q7dP<{@IMq?}oOwg~gF zZA)>FgDs5Rn(9A$K2)q(y13x2L))74SsPU@I(I#ns1{V^CM}9&4o5^m?LQ_fJWcAO z2gANb-AJabjX+H-dSi5zl|K3ds*+u_%HiQRi?n^0@_#-X)Mfjq;NqiS8s8>+G!hv} zvRXIF40JOQ(jrWOTuey@JE9Bn23Bsb_15!3D3zO{oKch)N0Ofu{CG~nq2~L%igT6N zgb2$P^zmiCK2c^;3*KTSYg-K!7~m1@B8jjh+KrP-f6k$lFOdeLgw~5t1$C3gx}W7% zf5UuP3xZUYn83WdtOaO4%!2hEn}5nKm#Q@;x)^w&dIG-ChOaYtWbDPA(YwEz3`|87 zAGF~Q%`|((5xQgu6R@x&TxH%cr1o5ORS4J5 zw)$t<3f4F^xMa-1o7sX_6659L80x?#w<(Y*y(gFfd)l-276A8X;CClu1qqb#h*hn4 z(#lPCoL+%;C=;Vryo=_%PCv-mcCc}bki=o3H?=B!ekq&r1#*o*z{Rq^eX7HDi3K2s%S9|Po=4pZ&kDXC0si}7i7cy>sR_uI{<)+{Gf9qLdnD8N zDAUmbaN~(Fkh`JRUiII#`k~`CHVV2bbkSfPKWOWu?g#Q1(U?d>Sb=^}RJ5@V54Pi$ zJ7T7;*aSn}R!WKS*oLo)HI5ZdUx(J>k}+i9#<$A;D(fI#k1&!MM)_Og7uOr4Df=Cj z$jksvXSF*e2mJ1S?h#+NgRqOWADr(5ydtZ>jrVZb9Bl?t9$~K57JQ#WpuuZx9?bLd zbgfC#V{UA`p`5{2-Lm_T`7pC)4}smj%RId~&jTzSCht4;7g)6K)W2rGD=WAve@{+PQ_!`T zS{Cs=WuTyK_$N zC-eRAA#yC>jiWl@L4FkULP7b&+Uh^shw1cT{6kG$uCmoS`t1eJI_4ooo>Px&@d)|M zK#({16k4sfLR!J)Zrfrzaid+B17fkMLZK4y*H`8w%obi5m z=yI^I@KHb|Hzh4Xpj9OA9hm?vSH0w05!Jc&oEx&Qt%a3)5?5!4CcL!Wah zvP-^3rO;)iK?dGjD?&;j#*cItfvhpbSps{$$jy$FsNTk}D$3B>DdK+jta1YN$iY1^ z=m}}TP9;>1r>V>$!j}4^_;rP}R=r+viS&?{3YXtivn%9{>s<73CRfbnZPGn%!gHf= zTkkdYmJjy-2GzIMdF;$ya`v!<`aAw|Tyy=oY;-#eppdUbNkrlYNC=0t`?Oe~E9$A$eQoo^mw#~n{a z(iJe#fdc8q;OA5uqqU!WfR^oqHQH{cVo{@bLYP3}`Y@OH(H+&`*buqJcoObh45}af z_5E@p2g`H$zcd%3fJ@@y<+N4rn0r{J;m+_Kqrw>J28_}~zl$wv2*ZZ?gRhwFvBl}0 z+y8ViObn#Ncgt3-|8-ru$ib$>j$9(*oc)j4{myvPTF}*lCx#X?#^-l%HKD?zA?rmo z%$f&HQps60|2BKv20Y2SxD3Aw`Xq51L%eL~=71m8IA1HfivkpggVL zuzZ`EIbQAKe`da8MR#d+(v5ASWKjfoFV0cB&84jjas*7<5TOr{&B37!SfK3GrV<+B zj|ssu4zZ~lLo@~`jo!4sIFm*XWh^$O(#esCrZhS~gHE}*rm(X{Fr0AwjYnsdqbI9i zKpR-RiDJ&kiCU>?JxiAPzGecVOpU{ zVy$F*0Qh8rduM=0Vl8WXz?J>GGvJtg4~QPEItJLlG90lqk-`sivWFA{2LF>xe&fun z$C+)1+hKjoywpXGw8gwMcb@uUM|4?$#2NE>%e}SzOm`XY{%EoedSuhE5vl0SUj}af zt-Sk~A+oo&x3gANaeZq|LjQ#}LRJ(BhI!Y{f~jY@=WT9`2K(QcJx1<;4ly)4;4GK_ zo07wj$Z*6p;5)K6dhQp393%RJmPFXBLXdmdOXUQAQEU*7`*-+I0DdFf|L7F}d$6%f z2Q(etMerYn9E2l20pCf?trry{kohMMx0B9RN_4a@WbN%SQ`e`zLJv-*9;)*E!ly05 z#0I1&=k$&e`nJ{jwzvCgsqH2;M-NXi_VxO<6Z=9|f~?NKBs!)d^3c;a3C{{5j%?qi zaHrC%ZVnXtmM73Nf!}B?(hTiN>*H`tL|xnSRA6W=xLI9h0+v&LeBEYKFEbgt)Fr)* zRe6a-zLzEBfJ0%m0JV-8V$*IHR>3G!K`#@Bsk)@;eRQ)gFrvq8YKv24L21^!Z4TlnLw8u~&EDw`<_mu;sU-;J`^b=(zd9Y>gH82n0k~G4oYLW z-A#iO2v_LL?!<4t>I*5580ZP0Ddqka@*m_2#EC_K4~}>DQ{{R*!$^u9l0?H`gS5#h zl-_~&4AK|)=$ZBd7g%EVQK2?W27UBxp zSntdcH|@wvWbv){nOX;u{`}B`fbD^kWBWIz*q_f-STf2a>t$}B>gQA&559*u;x}>A zQC4kmpFN!b+J#>Wn|V{LTW!XfzeMW}Y(jwj zn;cV7qHSo`z2Nnuq&df$gBu~Ru1(`f*6B8&6YF3C7{FSYfcdkQCIZ?&S7Awv7P>JA zT}M|1p=;??w&*W(Pg`Iy9fVjRL1K`gTi{3fvCVNlJ-`71b26Zu8&x+E6f|ZL7I+eB#832+qyU_YyzqT--UUW9=qdA1C?r%g29gA12y1 zmL>bEMBf?t95j@7V4C=uV{a}e5=PEH)*>Ukopoew1}E7`6uw>W5dhQ{DHe_wpOn{9 zO~rtPWbM8P=Da-ntmlf;e@+@LAK!q!rsbJNd)Hp%!^%2&JrCKA#NYpqzr*V&R!2JH zHrSz4|0NEX6ita@z2Q98J=p|Cy!t2?ezs`-Ggpt}&38Hu_oZ~0PAP=^GkH~tK2C%E zF}GUC87%SolV3g^y+U=dwC41l+6`HD^xwr@J>O;QPMSQX5p+5KU}vd9Pi;#@eVa1CIKEC<~)@ye2H+hN98ww$p=0Ieo4I z|8RbI`6{&*QDR`6eYOAm^xN&^6A2eBYkekxFBaFTm#B|_P=dwO@=sYQaomwnIFA^8 z=E^0cuJ%Rh_2ZZrp&#m&pm=)>i*~I6CZjk>}@%%%lfX|F_#6 zi42TZ!4r^d!M9npJw`?2F!7$g1b5Lkm$wGM6j7a3XZg=ebI@1IF54KX&J#vgJl#&K z&mo&Zg)O&h?09Nj9xurB#tA3mFF`#bu|XfdR5RuE@S&$b`@^yhSKBxmo*}fNDn7`M z7)deoGo$xX6Z^Up-)Bi@*KmdT(MlXJyWgj$sb~MGdgz)>1i>U$xoE0}rI&mt;8ys(gB4oj)(rl{^Byn?)ekc3#m` z%Mkv6PR0XtHsw{vruizP1C{2zjFeNnb$+sIePno3FgvbmFRC$1zajCRZtCMP|F+Ej z(=osQf?v1eVY-ZUi#zi?O^G1zaQyiUQi}e*4}a0Uov>}G>oVm3y4wE%?KBNX literal 46379 zcmXte2|SeF_kVp_wNNC4kgW&}$ylcpD$5kIWXqPF5VFlwcE+CUrl=;_vTreEnXzTb zPE3qt?3uC6`urb#fB%>JnrFMuJ@=k--tTknd7L|N;6TaAgW&Ih18(5ob?|87=;Q0+ z$37nzEd{yqx?sh_bNJePKP9=Z?Z!4ld8ZzQeFX|AzQp z{_k)g_~`$R`@hoF|2uziaJA`3hLsk17kP~TD95^3UE@`iy4KnCt9e!q-rcLR>tE}R zr2p~!kt=-b{OG$^hokP9bp*l)gI1Wn+(BOzAYhuhw!VR7sx6K*4L>4$DJ@+e)Y*6u zuWkQdjlRkFlg;WIx#3>A9$)uT;yf$I?c!t`CQ>NW3Go1iFA&PXhqg%}HT-ZbhFTX4 zoXBl{IvLS$a!gD~d9uyDVhVSIFZ)HI#|b%6t4@RN8-kN{?k$`(jGSLyMz_T$6ZIQX zEAHuh)5zcol-19l9os8F_K~8Du9D_(vtx?2usz zwehQfbuxic*?DZqzqS+2H|7u^Q4=#Zr0p?#MI+^5a8>8Vk@0h7VU9_^emOsnPOvkw zU^Oz`?B6v%pdyDkrfmK2LKcnc!|?I5&G${~dCQ9Q;E3HD2zba!Vd=!v`7ZAZ@s&)D zpUG6ce%@K-tdGBQTm>Y<42c_oRs}QAtN`?G&O62A!&kC?2vm4qmsEBbJOOo@_j8=% zQIizrm)r|^sBpefsiD;>$Bcmv?su%mm6*cS2icA2Do&1}_Sn<|M9~&#YR{tUi1u(T%NF z|HiM6%e-29#et~zct$V9_pq(}<5$-&{JMY_Rh6N-3rH3$yEUO&9~#FKi_;w?Fe5(? zBrXtooH}_W_uK`XbUPAFtDdGvi3{`NsRbsy7#rCuM~LAjygq-&p+9I-_08jk*TMCn zxRNmLvO;^Da!H6PL~;$b9;Yt|Q@VCEU&{TftI$%=H%zn9#n zEXo~o-Z|zxaeL7I*4r|~*dynquMK$mMgGUgX>JQphd8#i2CQ8-^t~L4%YBOE5n;kB zIVNxLb^9jR?Y{(Yv}~z0P_y7IjXJR3qs%8O3-=rUjX$yd1nl%rq{aX5w7oA$6P&dB z)MJ-)@7FTK!xkK-?tGGSk>FU9QsB(Mi?OT;w@1nbx|Q*r;naTUj|O&zF(?ddmTlqg z0!lhAh#Lkstt;8g<#B8s|JqrFgxhboGqaPnTcHQX_nXKC@Ild|B*JdapG5EfD!gC& z5$is8Io)OlUxMP;Kv8Oz1+(w>AMH0X{vzIG3IEewN`$M|7j<0Hxn$9swopMUZ(fA1 zI2v@E9y}pX$*p$XAPK?|=0`jX&RxdM#W`I|w4-=E6dcvNW+)8D_E6E_tLNGmAISjye6ZL{d)@KMv>3`n)D>`V2*^603Zb&gP+H5S`)u zIx2Dyj-#YuKrZPobzN~7q9z3v&tKgZdJ}dbJ+V7 zD?{u+rf1^DB^RT;a#-93!zLXK{Ju-%KsHd?sHp>r=&HdS9#c+DBgJaZNZ1D5W~* zKFK+Ax|QwmNkx&BDDVGzrAiCPlqp%zNpT4-k38yYP6jr|mVl_fgD8we{hKSO(daMU znx}r6e1{lxI8pjLKaW%PYN9|yNO9%cLVw&QhQGZa`NFx0%K^pZ(+a&+Ic`*7PQn5vefFqF5Zr`}@_Gf%pq>^dhvFFId-hI%^m)a^DDF)6}6=TD_K z&2UA#78EfbnA_N}0IKeSXe*A50zO!rNV#rsv$;hys`;A1&5I;Q%|=j1oeldSF!nei zQ#oH1ZZCil?{##S>TT#XxB7&B^Jm79>J>0Q(7t%T&-*d>J_xkG{}yr>8QF0qwmaUN z`V`c6UofAO6%1T^4^+f7p6l5N87i`Z;$paL%8TGpT+dL0JaEh3D6XKz;aJf48X#f1 zgRpOrKyTao^N@cHa}mQgLBBL?WdofQB$74|KN^dR9>{Si8(QHgFMGk!0NZjqb;)8T+}gSp zoXlr`(y35oMe3{&32y@-&IGCo^XQ^K|jY=TLm|r{$`Q{ zF^KL9u$I^Yc@GAvi9xE?1XXzlWE?#7pwrAg?}dPCrD9@1dRW1+jl^>mC%U>eB6ua8 z`6Qj=OZR`l#x&dnSNlJqIg)=3KYFnWL0*aOGYZUIJ0@2*`2a3jbl? z;suOXsSG$~N8gJ%;r$-P>E0bJ5QC(^(o6f7Rq1Rc*9@E^z!jkel}6wC5vvvi{1&~^ zG!#LkgV6w@|5)>eL4Vgi4QcRWzHqx!kJQ;@cK_q?eVrQUmbyxZC_Cl6wEx!>47d`& znS+MfZ#@rVKox=C?lf`X06p39cmk?&E!*+Yh)B&J`cEFZ^5T zPwSY-e}w-GWz^0#U{*5wZ8lo;N@FZpMy zaI4W%1SPMS(#%J*ebNATb=uzYo)cP9lp4mnM*P z4gUe}j^B)g02PGZ|BP69_Xy~l|7%VziTmbpIG>b#4xjvbAF!G>yiP5arf0ygWmRK0 z^$&&Uc_}au?Tdf>KL1~W@UA++D>xdYOKFoYAZYiIT;J3w#Jpzk)$yO8N*}I----qx zJ@2|gfqxX84aU(!tJ-+l8tQQPMvMfpB^~Y z?)||frzWS2cU*ldL6onNhv3pVM5%wyw+}6Qw9vlAo(@XzjmsM(DHnCVEynh@CGY2Z znfme*W#7jBcfqGG|0}34Mih+AC4<=x9~7(p?>x)l!?q8X&cD3yM(5p?G>L?LPhCZX zj`IAf2rkS;Rb8|-@|IuDz>^8MhjXy9XQdQ%-e=9uDG#@|xie?DGjDNc%1O&B89Ow8 z>G*Ay%=a+4zVMPl#U)=~t%a4?9vSXTFDZF{A*blRTJFqADJbEQL$lZHXSs=QCcHK! z+`Vnwy~fwGv^5Ps52Gw?1@|swBQ^;%7yt1s~La!)Rw^a`PH^uIx@z>K#sLHok1&7SaqdN>i3@1`4E*d!Gue zG=od-x#e?$G*fU-Tly%7kx}XW)WgddjE)Y|#T~qo9p4@$?^8$PKk6{}$2C*`Kt2iZ@CqGa(|e>C)qLP$Buu9o~X|JPOa-~csAlTt9Jxn+IYBR22^*2w4Q-> zj;+3Yg+@h;s6%5GchZ_AmZ&`@wlvNXVF@t6~a-{EKI+=E4Mz9I@zA z+KzZyGM@eHgX7{v&RgxSD0it+EArpl%nye-)>s$u$x;4F@UN_UrS{NeK`;>XWjTcJ z^Qw0$>cW#8VTHhtR{rc0ou9e)rLSu6Iz6%La9np|tv0ASdgdhYr~k{7&OKMv^bh>J z&p?&~;i4cxOZtRQEFLT`65Ad#b0a*%Jsdx;12%m zXTgImP_^OrUgaQrqDE)Ttr;C$= zR4?M^kN#=xoyV2kV#n%!Imc$?+m2q$d8@H@;uY~OuJ@&Cf|^hnn+|N%5}TUb=g(4i z9^cF(ZfW6q;UCNx#PT69+oV==Dx8(FE_*+|vg0#H4cHd%b8r zF#08xQ&da2yDqD01mr0H8G}?3NrMS~f;yB)!4;K+kQ)1`@8!~mmu*IKYv%~R8>N2d zI@Ov$Yac;tO`!qCQ2&JKaYOm3N6CRzErH)!GA9;ozq=Si-AtegrqH5C&>hCTo7PR2 z1_|`aK%FPIcx|YDNErFj~0_$4J8|yTYKdoF`oV2<}GH#%%qt0s8$ z_1mc*=b>CC&sGiI2;1YmU)k?29PMr4&ashZ{WhEVZ9HT7aK_Sl=2Y>sw_nV#&6n)q zf``#O#m+LuGd-p=V}i>E7r(^HWS58O5l-|nxD%{8Pd@fPcLwVJ=;|}sBD30Itt9gz zyY3PGTet+z|L`V5uM|Gpx#gZ9b8%;4q;e#s1uPC7w&*i<$SZl4SM)5e^qG62P?85h z5L&Z)N?_9TXo6ta;of#`3-D6D#_m+k5vj8loH>N@lJ7P0lgsXIl_h;OXS35vR&`^Z zmY#Zfs$VrL(&dOf#9+z(Obi8V?ZRysQjac!Km6zkOWdm{?r}`?YksTGm zk|I%}#@{~YJAI;U7|^`DXd9L^Ic?VV3A`Xcv&CL)B zRs|M6GB^5h_0C9C>}cwaoGyU85A@vu@Fax#Dv*}|)H?(8DsTV)6Hrze^tdsVc@lHZ zZtMJcO}{-ApYfAIy{%YqbOR*E>PQ+Fva{mK*fC@`Tf+W5m?9v!*LRiwFz);xJn4#x z@*|@iE#Ul?k~U1cPmi?mk|j!7VLU-uC-=knn^L1Uf3(50>5{VrqWS4dfEFo=x5-{F zGz6TH@fLtWpw_ed(f>7dW+0oLSTO@$KT6q<#M={C&NU=z2k%U{Lx(4%#ET~F1q!d=^C~)N3+XMTWZH348^|=t%ihn50 zL9b}HuduPIQNRZBXGJGeL=e>NVc^u?N$1;=Ox}MNmVfa_h)RF$jlbpn5jw=W{v_lG z0u^f-h3-N_dSIc-NB5Gt&q7q#DW-x5X{wSSt#u&r;pXyIaHHo?j@}bR$Cd!xRtGkL zFif=BVq~lu(Vj`no&)`$ZnQ3Cdvd3sqFD7yg9>wiRC{Sq@R3z6A^^b;n+L+iY)X7;4ZPt64w>7Ob!zM($k(*1 zWj{-&hG8{m0r^4&bg=}$kP@}+byMO`6wH z+M+K_QafEwz$V_7fiy_y`_AAg;1a_j;drfbTRF zZJn<-idKYjdCVeq)b;3g*A=k_QPVCtNZ3n6!T=v9br>8C#mdcNF<*nDiE}dPXNdL} zLqg)z5(gByR*2IVv58-Sy_2ld-?6-*N)T*u%yh!m#{8BM$}^W28C(H0zu8;Y46%RS z+(xUwFtY`)+Zd+{i{1#k+p__x-q8cF9UlOZWM;!&fSephYIGsQwB_`A4!oYPb=ALMsTpoI1@v5|D1WFdUAP}E=_g!V8W$r`3mmQYwKuf5k-1JuAU*BUat zt{Q?+?HuII-L+9enBuUBys%0L!tQxQ8{^x_wa4+Bbm2gO0%-}{#_c)$MB5+hS^k1D ziP_1)&0ua~fU7&|2?IyE6hny<;=+292#_`rZThwk@M*-fLAFkrHT4n+33AIv_Gx+f z&~{a6O4^g0%tkJHqT3i~&>Z{c<<`@Hb>!62514YSltB-^Z?c!07u#b6%`W|*nCN2@C=$)J>z##92}0{ zxH+MIh)Gvw@)zhzkXH`ScKh~_QY<{loDB$WL?&K(VLE`F9O&i!$+?I&$hUFI4@LiK z=FOETZ?21EwiwLe9sjhE{9^XpyBT%r_H*}l07#It9m4W8vt^Cs6}?Y<={5?R za5}1+p>OtZB=#7_(h{{~h>BM>N9O3GXk1ZXI4BJ*q)c)Rz&84$d?6hBY_L~INu?>w z66;{pXY25U0gbt*f~>6=VxmGJGEZ?XrAkyAd%su+CtgNa6kx69EG7;#bud+cAQfb& zHmj-S)1rsnbBEczzlVE;-213Y(&iXEi9d!hm4UE{rC8jCVz~?W#c`uI{-9CJu&+V| zVa^s-jG$nK-W_0CFTtY)1pn+XHT?q2A~gVWO`BaTVIS5AS4PfDGOy1IfrWB#-t1r) zo4U=q+Ov%{HIu~c&$|-hHIg>HPLRnE3b1AW_J#`4rbB8+sR1I?U>SLf!T&|SYK=jz zAbglN@7_PMsM&&BjVIH_{7f4!7J>9`vn*9eKZT{sH^Ur4@Fa4~HlFgN=R0I*v1brM z+ihdi93i?sT)@2VfkPUs?GTSMSWU-((H{VBDAPs__7lhOKIkzPwylqv&K$!M?l-=* zL$TX}UMLeo91V*`3N0jgW!Ts~|Ix-GUM0)<6JAcipZVG$RM@dj_5kxNh(2{rN?*em zz@>~hA9$f4K$7gMwUu}iFx#@<`h5psd7ELkqHO^$&5i~*s)7X)e)#38X(#Hnd9l-w zrn3QTPzY@_906ZkoX!IhKOmR8zPHhyNz*orK`-0#LQQ9MY~Wez6^|&GEem?^b_uyaniO0hlc$${=+Nd0Nv;6^DO>O60ZDfM`4} zhl%dM4oPZn>)o|tc-{1}Sha~~@;1r8M=I0G>C0;f`Ve!wkm@ar_i~fhSa%9(1EI&5 zPGREHt85>S@IfZt@}kv$qK6p1*C}+Ly}#!IFBa_h*RIq4UMB!xp`Zb#Ln@3RYISolIzY0S zhm*jYD_zdg$o$sCFErA=pCk5ShZuppM8i?Dn*U(hsiQWW%vv?JDkUOdx!Oh&;-mw+ zyhutp5EvGCUE8$GP0g>&ww7aY3~LM9&ysI_Shs1838b2gaPXHSq6gABN0owu5ieeQ zQ$;t?;m|fxQCm$ZGe~FLd-aea2aXgML*3mNL&s?#qSO)w(ztfeI94$VZHofw5e7lv zuCeUsev<^7%zm4r%xo7x;$NN}XXCYjG@@X7f%f&d3i?ND2M_B-U<*Dl-@pePXSPT&@6QGLAnRNyEz@TAA@3~*vwF${z4 zzK%N~*msok?-GF@3;}RK+Z!1T_m^?^iu+clqNaW@?uIlJaUs9m2|?(S0Ixp6&?aT6 zhr^;DA4URr1+z%lLm8v?8);v6^{=LkVSA3SM8|CS=#U05tZY05LS^V1CF4ju$*AcY zP};3O{4t?y%X7n*4+vH;*f$P;A!~R$oB17ji19z$X&_#1|2Q-9SGSyfKR^9zG>Yc2 zWlYB>uFN9A_-%$=ZVr?CYa7If8yKP=3TkLBa%)^Rq(Y9ZsYdN=+@{-ajkGat9N8Ua z5Phfn+JkxRpG&UGlu^7p?}XIaG7!Ccxv!vj(%~4Ys2?(Zy}pnlmj)b51%i&HO#7ZI z*cDsAP%=zuXA3y$01a&~z28E=2KP#`{(5=g2;|~Ew1XgLfv$M3mzq9MQ>lS`6R4&g z@cE>MpZXf;Nb(sw>i9jYtWEv`ql%p`zME=W^s{J=XgCUykpc9IB9Dnw9-(p-5F}}f z!mDMG%wy$31*+Hlml?1~);M40D^wY8s3fF$!3i;zz-o#GQ;pl4#9)^#`xQfrvgVAh zgh47uMbBmE0A!VjpV1iN6-{WTv zx8tKFIu6w40mIGA%)Okur`UfO{M#I;u*^B<$3kQLv9mN(c0&rI=B~Q%U3m2$<4+@A+1}G+4%AE>9|1zspWT~7wJ|7?BT7+c&|EQaR9+es zvFv~)E7C`=jAL;m{TK?+0CQCv;l=voLA4j}q6m3A@MXqc@M?f5CN#{&2F0$I0~?mB2D9pIRSifhAki-9ujviAW8Na~ccK|Zs4PYG=_4}}qCEs+p876XzVebJb% z=-G!s?tDPnJ@38)6zc=1PsqnhXx>nT0T>S_Ky)G4R)Kl7_$*R9h?9 z@t-9$mSbh1kcp_8;g9{ywl(R}_wZH~No|-uYD4^BnFW?aO>U5n^~0--VUN)vDqgdD zZh{L@N&{#fCa=}&-=8Z1Vb&7t=qG$4uRasF=^Bbzl=pJ5s^+7|@Cv4kA$Ol6ki2xi z`Qtl@@N&R{y&lAo0jwJ659S!P1-v=vU}ZUg@wbMZ-JR{!A=(SiiQQ|P<`JMHeT&)FU8doI9SS}5n(Rs!D~2)3!j!J2_7fx_ zFzdWAq(@pm7W$s>))|PK8*Qqx^_bu*U0u?qngnOGjMHsT~f)>)~I>nEJvkLI!n zE=e-|OoChD!roGu0IYpK7i&_-V)BHlka6q1cySltL(eAcD?4i7Yz##=N&!*o$RMd7 zgs2$UF>-FP;9<>q3ef|dTvX%%CgKKb7Y`;=O3AReR2cq!*-9OxfuCNsZYRk)xrgOb zekMvi3)1uwrWC1u&r-tyvC_>r58jx;^d{;VAOdFX`N2f`O$#o7%Sv0pK(c5+XPz}o_b0Yt17SjT;{_vcw*+o9oP@BLAJh+?&G4l{GJxzPL|m#(M(-O!>rsgS*( zR36Y8TTy4xW5I)~p{^W~v-DuxRJ~=vSoVq>B*=7@rt7un1xL#TXE1WJS%KMLiKd%# zlTSaye&f;CT^Y;te%NbjsMjhwj>)TD?)mrO?#4wMD`#qcFFo&8P5$_6Y6$?tQT z>|aW3CuzoP|BNIxb#2#1Kzm~bBDh8g2^hexZ+ncQF(|py$3bD$R{sSw7|{bdTq{^3 z6453)Ij=JDVb&vygchuNr(Bbcuy$hE@H&;5ShxaL55*EWs-$0EbgHy_>qIWti5=Dy)^|UT%8||Jm1!Ku5tSJ;RXFF?S`h1#XWe1f66HE>-78>kqtim|Pt6D&#;)waUkS_o=c7TtIS$mH4 z^Cx6=vPS{ZU^dGbj3fQL4PdpvT3}Yp-tG=fZx{W$oo1&#!ULf_whJ9H0t|^deO5b8 zz_T0lD6mZWyObXpoV>f6kG%md@ligIaK}qyAwwwxB=UqdmWK{a-GBO5uhV)S3E*)C zUhN@IAlgWuVsN@D5lc2ZyrHTWcM{$>Kie_>Bqdl4=GL+Ac2 z!|b9zmU+G%HDQC z2h!pWOd}AimJAseu1o3!h5C)zDb(NQ&7OU7!Vx9^m#-E*vQBuWSBPa zHrfV`C&d1)4VD{K8eO10MKveaAsaA6>1w29T;LK9&FMd|07bZuDjTAEvbSDuYDo(RZbs925F`94)EJ93j;Q@H_|y*A)F|TU&TcCLmG`CtJHCX4_oMmtX}1(G zq+@H9kvw$589FR^o^ww<7q%Q?YPC$8O&1XQb{8RQfWVPD+Gs?ZHL&6f)4(eM4lvFF z-yI)@5oPy4?}i$V*CHnHnzkG~2T%^zK&c0K^x50APgKett8rr0U8Gys?N?$4;q$;Z zBVX%O%A)SGd}VE&ekH%X{k;@zBcqL`I^2AvvnY{IsPdYIoiX4tlD$^cYGUOY!hzpN zC!yO(XkKPRIvs;yp>cb8LP9neA-m_f)(J@05TPG?@#+EgeMHM#UPAEMcVnSce=KV) zX0wTpNcYG6jYMtiFOTxPgSj2>2+WkgnvJ57><=t_IC5w}U2eT8PRC2w1S96ShX{$HA;T$Yw z8$VnOt8rwW1^36BGqro6Je0+t9yBCK*N&O}7)hEs>Bj;veK6@!#e@dRI4tKbyHE?` zVgXugha>$LwglBTFn14CBSs65!{NnIudF&Lyn;Dkbs!gJgiojRH;;wR`(vr3JM`({ zK>LNdV;NC)TNQ0Aqdqw5DXRJx974No2jYcEAa|(U11C)2q{5=TmH0LuQ1giWyjGXJ z8RY+%s*04p<2djAN?d*+kvK}V`8}R-NW(6dyFgle#8iD-ZkyEysRDc_poi8H2iQ3A za^O8~?2+h6-<~pEuqdjcR*qaML>5x3(^yTX0YoAaqOxVPN-*uQC})0I^U@JZfCs4} zC}**QF$7kdoVF1l_j{7HmSB^84g0$XEKtyQ$&8dPY@P=8uXyStEE9`&VkJCm5^5|J z&~{v{Hwd2g{n5sl8f4lp@7dY!$lW#OD0=>IeZ0SW~w9Yl77e+ z%hb=0Vvv!{^Q(9g9b~&NRluPw`gPCI@q_n-@mO>*mgvP|)QSi%+uh?w*V>D)(Koi|mJt+j-0r#&r>@0YI zylLP~5E6G4)#t3fGvyjqqm9ulMF~c+wg{}UT!P_-)5_Xz@W*LbA>dRZo&5{&+ZI5K zj;sLVD_dYu#~>H2&Q9k@!n!44Awjk+SS*p@LRwM316tmjkq?x`Gt1JLgtTeC2Rvv| zv)bJMl}ks(aD<*MLM2Hq41to(>xY*hpB}0$-Ks(w5u;j1C-wx*76tsuxX>0cecE8L z76xyVtVXV^?S0shyIST(OjQ9=RDd)ZvaXSHCpb$eX5Hh%h*BX?8zMUZnD#dh-)%Xj zY!EYG#Yu63Poggf-R9a^gjd0Ld4}7eX)twlp!{C0_cCiRk;9NVI=K=CR>b{b@o5=C zLiQljm~#^8&$sM1m{q&467*JKHa}jOX11N5WjLXllb}c{bP;X`xIF~|ZW!1BjfZ#r z^l;mY8}$iX1)^MiwWq#sNJD|TLyJQ8TeWS}?BTyio?gJRi;Cu*l6{X>L1qOZysz(! zev04qVJT@Z-WwaGIUQyyDS~y=YR*kqc%2N2X$lsVDH6TtwP@=piauU^T}~y35-@6q zbep+DnrEZakVL+YfxdCre!1Jo(iLbtzNwzP8F<{^ZtF`MLmjo!NA!u`Qd&P0J7CVW zM$hwS-n5hu*MNKppbu5cZ3DM}Wx(kdAYXc)elb53k`)BZ$#3caguBAAqabKVi+ z_nu~`t|w;X&_(T@GuxQnqV))YV9&8U$>vtU7z^LVxRfnZ)$KdK)mODHBWs28T44(}nTdjJk&xv`;t?$SiS z?|pTEyC*sL01G$*ezd$gfGphZ^Z;w<^~dPJ3b4Fx25$jef`+Z#fd5YTT}(lWG5Le# zQk%+LVpJTLr=PNhE-Y(|bV7o(E+LPWBcrDR>~;$nZ#n>{B{X+(pa2~bglJ(kki5DD zd=)`{2wHTtI&SR*)Lmx6-hjo^R4yj={7%4k7WY`bkqCY(F?(T9$ueQFPHBOw^PQlG%jF{`o2`)sou4S zpFXU}{9Bt3Lg_?H3A*_K7_6=U z76uY5`ZWIjl5^SD2FEr>zICl7lWN2F2K@)#EGIXcU@5l>@0$QxAB74H^wI>f0&F@r zTagbwn#`OJzpn~d+!-R!GTR@VN1-&Fk*n0)1kn?`?g}ua?P4 z+PT-wp9IK>y#b&iib$Co?FHYKtX?kqG;5x&sJkLqJ-<2o*zUcs$Q3W063^M|N6bnu zM;a!*V@2#`r6dLESR@F)&>A~)?wLoR>AlGs>HC_7zefHr>{(jP(dCzf8sF&s@X>nx z*v}>PPf7?wMB=iTazb?rrp5OC-R~i;$L8O2#wLL>43CSsXTN#-erF)%^)PpgONZp! z9v+e8st5S4+V*SPA)UrE*=M#|^<0uY2cp)x07)at!QF|m43#hVPc+;6K$a7Gz~q

      G$xjGDek0YLu_0%&pIW4gyiCn{ zdEv%2#m=#eiR(|h7KGyEJT8RyQRXuYbKIXSR7RiE%XqPH0{$IZsv0qNy=3KC5H>pE zn1E^3u|f79S9zPloqk(x##%Xq>Qp{<75rL#g7swvTI+$9i559NF_h++#ay z`l0GT_F)f&w$o2eNzK;}{xQ05snjzm-c|WCF!%$M=YB2j%~06Mpj+lyVTrZ(Uu!uP z{@|>!O#fQLM}1ND;Rz!o5ux6A7t#~ZWV*3n7`C+aZ7#SkH%a~n@j=xa56%>7=2)a? zy-ugQ$cM{4JtjAbHiBP&)|F`t6hG)PXsxtyPw~M*$w9}LyM_J8icH;K$?m1l1Cun{ zC1I^~nGXJDNf`T5{^h1`sdcv`c;t2S>16L`JV#0te2$otmh-O)OlaLYN{;kqyOEkw zBe&mh4LOS^7z@f!!e&771cuf)!&*Nfe-M{uyirBz^rIKyXG7D!SI7(PGQrzR%Q1o6W4P((%c;@n|BSCu>R*|l%L9U z(~bCKMeKd1)KXgvt$*yLbnC3{8sEKj+iFWnEbnT(nOVJV{nwDnoHu_RkHZGE%uXmz zT)%s_qvofs#-b+e0Z*a#$c#h?n@vr$Uvk5OZqm?!ZXLyCLCfGQIZB}Trt#qn`gEdK zq-@Ydp}4nKKYRRXc*UdpTj8PEhYwGl)Nh>E$gGYvqE?vQyOlSm)xu$`+fvgM=Zc0hI`Q##-xTbg{;FapcApZzUXPLC`SzK; z1gldy1%9OJh+?r1^zb;x7Rqpl?H%rr5EGpsTYeRI+y5@*49qI|C0p8&10A~7feKkF zfq$j0DiF7=C^rt-NVrRHyuNyes!`)6|JhJU?9^iSuW8ukVX>@ZWdfX!1gu@7bLN~( z-syIq>B-gKlSf`jkVuW{koX*b_VGKhHnX0pdCg^&_fuiZuf;{oNTt0pTY~$G&ta3B zL1mnmw8_8D9l1SZPdaZzoPWJ*Xp4wtKh}EKQAJL^J5(y--T6ZjZzktN(S|j*9-N#Z ze^BN4s+7jK?iOgTE$Yr9m4%;9E8DcS@I2m7dinauM&u5H?dOZYxNYqNY`XUXcBjqA zCC(_RVLP@i+o{Na+xO1Al|B)_mU#XB^xDt+@xbvNeb&q%@Z|LfEp#}h=hj5~8W=X?`I zLi)bMtjINp&N}X$XZ}@tGd|%{q^M563wB(;^JTiS=C!D8sIEO}Zg&&pP zy?ep&M~wZad1@;8tFd{{>=$E1k#Ua6{C)R<`{Q1%FUAp7T914EJd%^Dm)aPogi+sN z3UY|)WLK*|na}LkMMBf7)eg^JdlS(gp!MJD>ox&0B7tX}zM#Zxsh9F3R2(CNCM?gq zTPEXNtUO5hk3;S~I1n3}7m{-0B+q83$m1u@oWI`Eshr%e7xQ{FU!qHo+p@VjE@;*` z>RvW@4QK1D3738124~An?7wj3J>|?}Iq~PRn*5mX=SdZg_wP2guGwqe$B5i164)fO z>&lG2mFrHw)ukyCkv{hLK~0CQteobseKe+_H`8cXz(_Bfu34Y*W^rDyp`?hKB0xtL;C z_^RSEHH6lG<*sj$bW>ErBi-0vopDzuIO~e5lE4q1*UAm_9^Ma1&$axz_UO#hh=2nq zimu38@oT@Sk+o-~ENBOgoD2`&GgtRv9MdxoO!4?Ad*Z+Dg1_gv7h*jX<&B3IKa&Gn zWEVa*$yYN61Rj&kZ!UieaZyqo3c0voRey21Tl|RmgHEgQ=DDuZ*Q857kCtwiTK?QE z(bd#^*r`7`ra;M0FZYOh`93zC{^h8@x@E&yqx{jr+=k2dAaMA{&xkRTi&`lUiTSN1 zIV+q!as5~0PkZwT_t?lSdfB34fWv$!;iy8!PK&goW_|QgXrIVA&wY+addDMqX zZ5%&~#;2=?wi|u?(&ccG;E5Q`&5RuQ}w3F!7EL_{qmX@s1sA4Nq366 zU;-|`R|+rsJPe#l#)alh|Dk&A5q5*Wq`MYg9I^_$n!d;D#)W+lw!vMro7kO|9T}Z(~PCxasC| zarmUV)wGe!k})mFRW2%{6S%m#l%MBGTADW~@h-q%gMv~q@E7&cjE!!!reA|1&8$Fp zI(h2|+^+?$CHd2M+V{g|GsZ0t5r@gTY3%9$;eEvGSbv<pYE_O*DDy9^9|$JsBk$@1!2u zJBU%A8X}IJ?htyxipp~>c}LC^jZakn$-%c}r2zTZKA8Bs4|fd?+k7ry1B=4*_W>6P zgKTQKQ=@Paa;5*i<0XK8ez(%Q2vZvv)QH*nGn&iVwaPPC-FBkvrP2tgfhzSFqZbqS z!7J*yU4w*RCcoNxRUR@P2ra>k27al2-{o%YnM5D&?+!FB_4(jkjZty@>{BipudCKH zG#C-WY{^@$$nN@;C;NwKF#=fk4sxqm;YZ8nkhQ@L6_}zIu1NNDhe%tT`H-dFvHSm=am0Mh~S3PW!o4R9}nsk*-l(sr*h*I_Ve#KmJ``=p=JDuY5n_< z0jN=C*jj4-l*H&r#?fY6Hf|ghf-Fm#(K(ymy9%+hv!xc_`*d~mEt;9?{w>3b2b-2n zt17nj0Tec~E3XNzy8gb5xZosp@@tbt)#Tg+xzX<&tg|lx{I{mN)7+p!j;7D3}qZ^iJ{~H+_V;(X~iRW>Pa$E7Vx7`K&7_2zcb-tCv8ns=V1i<3Q zBFpv!72gsK@p53l?n6qliGp$7h3QWce}=r1R1xEs`{|!3bh5GGWT^Y<@{co}INi#r zb(=aTpWJbg>GiUQdZ1sT<&sxl4Af-g#8EmQ@&&qs&u&e7hN@1G@y6f?k&CN&D(C$H zwYUD;RdEi)kK^l0_O<~)c~w!=(|;2B1Wq;rUjp_0>4OOg&bNyN2~W8mmK`%!HET3> z)c0%&k#TsCGQ4{bcbVK(l8Fkf0yuGLGiiOv_1*zu71WOnmiResM-`r@G#cVm&GxCM zvL<65I~$j6042#b%nUXAh#F9q=bF3NoMriT&8jQCAe8ws*3yFYq2IbQWT{82KqvWI zr)=A5&AfbY!jU|OEj42vVL;)}y{C!g-&0X}f9}uRd%C-Sdhzf6X{}gZ_rdNksZZ4b z#t4m?qA7)wM^aDjs&hXI8Tg4?ukEa!t3Rf?IH@>|<+(4h__vrZsLk(8Tpr9n%qdV7 zyTu5%vS16$a#a2AlW)EX;DuNUG;x|(t+`$*j8KvM(x}!W*C=6vGg^HPM8-0LxEM`R zFA6Ao<5V}QqL-0S*3?LdmD8g6{3uhoA~eHtI|O6>$;puHmB@Ev|E=uym2OG^M0E<4EB7%HPv~n#f27U4JE-34!f}oNx9Qe zrH@Nz>5tmI;^I6sb_eHvH!!94R4Y4ixCf0AkE+tMVK)loYA`Ih zenGX~8+k|TYjFBo?P-6H-3+tobxm67xp9_#HSu@?LuK-gk1MPCy63^g|3}lC$3ywO z|KpWV32g|WU6LjHKCd<^TSciDBSf-{b!@|ks0c+NYb9Hlv2U}HkUi^IXD}FyF~eYt zG3I;s{``Lb-RE&X9_K#iI@h_b=ks~p_qks#xjO9>{sfVrmz>R&JGJ;NY1P!=W22{@ z$iD=F5#NWT$+AMfW8J>WD1Z0-Etq)^((nze4);*sx@Ijc789sQts6$~Rd2X^pm-JeH4BCl@xuhe8wQ35Y z;z+{@SH>eoXa`6uq`v_jLqdSxyG`6#)_{~!sWq?1G>3e5I+&lo*s4Uz>t>)<7?G^B z$aquZ@rJDe_FdLHk39)%*8=7A`ld*RTLn~Q_sVvax#lp7x0cDB6#`TH+j}!p!qZqK^$UXILaKvqCCNLggZ* zwch^GgOt#pThDx-)Tlk~XhLl1%@KT~6E6~y@NN5HHG9U7|G9+EUe&v`^T#T`($VPg zD?0rgQ@`-|M$mF%m3U1+@lHDS!^a<~=X!FQZT#e(B|~zq-B^4Pxa#lo$ZO0%)ky+# zraq~2I;Tx7JS5Pxti`Bu>zU6xRI|8>M}{3!Z#g)T>AN3#3!WUx>Q`vUd2%++nlZK} z?|1>Nb?u5ntP0@hP3Lej^E`L4`YX13uapv2+K_C#!|#=3hdZ$D@-j|YtvjtMbS!rF z0whJCSPb1fGHB6l!n9dV=!uEQqf#m>+7aC*M<6BG()ijb_w2zCi(THGcJQYJm^P^{ z_%`!(DW&J-OG^`uZGFNxuf%2ntwKM6@Ah&fCPYn%sw@S8u21K-S8EO?Bu`tm&3n8K z{e9g|PaRva;E<@9*!JaIBx_%gd~i6UGgB3vCCM}VAhVC-rp4aC2{_z0Lzeal%9^IO zR>=CnV6f=4cvF?i6Gp9Z)AhhR4DUL81dCb>FTV4G9JFFSAo2prVFLGBhuo z5A(ykeg;K;C6aXuN#2x@7T;d!Oa(TxscX#<z*c$+`B|8{<~=>>eK8j=hl2ZJtL&`kv?qclKc;WUCW z^P#J9Z%)B~+CBI;iG3|Lz-+WsjCl_jlc~eMOn}smx%FN!2v^x;x+P=?K!f=`bQEKp zffo+$jv|{dh=TMNTOsR@!rf%AOkGi)Et=oP-(Tg+*a@l3VBht_uDyJas1EIh=h?jl zl51yiAbR%mWU=kK^c^+z$4fuk!w_!7{z^U(662{p19$uBv{ z+O@U8Ciutzf5;O5 z0{Jjxu;sU(?l%L!6cpn5W~blaZJ~-wt$KzS=D4Bu*3d&_>FU*>j^d!J2C1Qym;Uzs zTNk6nBpa*Q^3UJf`z#&a85R#+!;hifCRQs zlWf+gmDlrU<$?o1utB^3&BQY0({jU(PjDXhN4FI{uxTJ_&G#uMUTLG+I=_?pyR6RN z#maHrT8Fu%*R9_CFQB@^Z`iGGC1(dE3wNuBU`GA{zI;BqMlbNW5nQ&3a}2}RnEZm# zshF}e0MBC&Ucb=7htldcRQXH;7sfl*B>>zL#~vHTjKcn96rJ@YV|-FL$_!oj>u3T8{uF zMM%yZsh)8JQ~B{pdP87SA7;a4KU5=#+Z39h$Ic7xTu$X$*=OCj1#zAwxWB_}|0Q2} zoNUwWUge-U5)hoHZIa?ndlG-TZ57q4h&8)@i#e=#%l3-0>SxsxSkvphFJBNVT>UzN z<}e|`UoLzcIzB2gN&Yv9JlFGC?~Smhf&*lV4O2=V zsn17yFHzw>^&{&4MT7Bjm_27gMO;pD^C?4F*)1(JL002R=U{tl$$Ez2xOMA5&%*Uj z8>fbZ{=AfhYei~{?46Lo2o@$o(gmYX|J*3ztKF<(B;+Cx9pVv5d`@V&Q;=5);>~`+ z8}6x?r$<5HtGYeU9IZVOc%q8Web&s_9(#-?*x~TQbhYeFVU;N*O zki7zYXkBY+FMPiBC30SY{k*s7_TB$2MSN6Aw^eOGldUF8Y;P4T>19z#HsRefS^%~9 zmG`5y0J$WaD8P&Sg7e(vLYm?{)-Rxj-%oMPGFA92drJ*pm&_|+y#&NBOqrYQ3EW3F zUYbpvSCY3%p?0-K1lFStgnw~vl$OAhcNdcy#54?2Z9?Qro*b)o9lWkzu`FHYjW3Tk zx|CkKa%IdhNGV?7-*PzL?!~wf$No}3t)6#TS&RnRp7smq&lx})7P$5SCx=y+v>t>r+vmb%4gN8lw zg()C_R!=5c)mM;rR@Ps=+_&j`B_qhrC3e=FZ>3AkBZdAxP?DB9noob=#v zRl>1=mKn9nsZZpdtd?e(++4=RW}!dm#^_aBF{jG^jX1izQZ~rsfjm!BR4-#&1HH0) z3Y`4tBac$_?AF!#r2sHip!^6Q9jY5{N;X_To7Y5sS{C^;KKP}Zf3nuDg@vCDa7+hl z_jH4f%iWvG$dsnQx+g|oXzUIPXCtvccUs7&hW=g6`^r*A4iJyb1c0s+tmN?;35jo~ zl*}>1`=O@5R%u;bJ!()c`{91~o^uM6RLxX*&)PRWTPL^gN_C*11zdKSMw2Knt}Va2c}QfZIA6GT zlt!lqS9(x}AGClh|vx3wYeht|c0A9Ej zjpO*5zjA|BF7x^B-v7zEw4~E|N!1)#dR1R73H!CsY4ZNUKcVE%)sM@DdE8;;=mbE| zQHe`g)-%%TxxvxU4eWBFj>KWGoxp$v+${z-N+!IB#Dt^hkm73R+LJbUn@8N4Ht8-ysnNV*F{YeuJ(I8ZTqCBn+%hS^L2XU zj8b$K?xjg&GlN1;s~>Np*ghPaW~5vcJ^vHF{fW%HcGQ5Y{bog?K3Q)rc@t%OlcDva zv;pEA2CVHSO52$6JLH&GB=GC%=ndW~t1vtOy+*4hR4euI_I$6Gyvb^3mINO(jOa@LOF0|F3gX2) zs1;C?zmb|SRVqY$Go`dd6^S$wYeI`+!na)KJe*VFrb>m01yf(_5YDoRQ=SoBT?a|WAAc%};~(QTQbx~|tAaquwb9A%G=WPms9PSg#uCC7P6 zwt(G`G?H@&?@Lc*vBAXa3l?R?)w7x28lolphK0;4WN0F!(V=msr|jeJag(lohATpm zNb6rZ(R4WpeD_MBhq8xAV-4oMk<0<2H&1`7jlE}^X6I~w&6xd(XK@lhvKoHk89xa6;l*7rF!9+M(13>NRX#NtAMX zWz}xww*IOc1isb}^6sxTj;O_*NV`brA4!8Pgf!~RzVj%F?J7Qs>1-Oo@-@^d`E_&Jw%9Gx%SSMb|5K z)?7#IP4uxmo|5cW(zC2KR(_;pT6K7D=lr=l{5)e<{ecABmX3^CI^NUhWs19J)j8%- zvyI|;I_h74`UtQ-GLN_&AcaevBerkosb`t!p0%DO5fxQSNfUZAQOdr4z`!Y+P%h*C z_Z|Uirx(L$Ey(W`Qz&=Roo*p=4?;4JCfH8XZo3yz|(baD;He2zm za;%C@x{U@A|8~j^p&=NQ8l@fA_Qfc&fcw!oaKGrPa?5siX`6(}qkTjWCR%129kuQys(_~B?(dw>h! zbS~#q;4PQS&f)8IK&JJK_hf4xuSgBbyz>=wqGB)Ie}{8;)aqSjY>%Mj(-AE|o!Prp z5X#s!%f#Pk?Ge;hN+x5a{uE+KXVrsWk$*%Yl-SkIlLY-+cU-JnK((ZP?E2hyf;XDv zlFIU*%GvY*c;3oRQ=gFuVr?`0-H74Q64AZx(H8FwOI_s)M?BkkN@mQ(7t5W9QddO$ z)Vqz3ffl<|!?)yzjEU7YkEuJ>;qiM3#n(z?O4-;Mx#m9175uVcv_(zs0l(puTo^mpZ5IN0`!kNPxZ1ROXX*-4CwkCep6Ih0{1jizf!1Zz%aW3+Pi~~ zc9Nn1LckniTz>SKQNa!A_3qhpCUJX+7$!LzB)|W013lQdaQh*fcOy?mDc)&n5qKl` z>yphJ@5DWuF0YgSF)E^m4hnh zfmBh?CG-8aTM7lzC>Xz(z3Iy?15yP6N@myTNSE}U3pzaHaoAzNO8anT)K^~NR6Xb6 zc}_G+U-BnUBA{g%<|5xrJ`v(H^gST}x}WY4loVE2sD9;svmbK|XWvS^rVoAP324uE z7#gCUqG6;?{1XR2O5eq2CSfZIsl=5Wj2V#erR-hvx%8W5+L19Z*k|`n7Cs4EJ&erY ziL5hYHh5|a^^UN5qy^-C@8g_wJu1&t$RpXWSLhDx=KVIbw_;G%=qh8|!C4oNOTvDO zwrCvSMc&;k8VjD-7|*sR5%*$l{$BB6?uwYJQCPB3&Pthq(M1;^(ol!czOX8+() zkN*RZ#ZzIX`U!735Htv|PSsJL1*_-Zb2)-Bp6d)si=4|%VXgDoFIfzzo?+V-d zxJ@8pCu6s&MXZvVy*Ec{G%qZR==q}_`$W0Ry_c#TQbMSa9$z{o?@7k z9hK)M{qvz=lc9e#F9&(a=8T0Zt({gAy~%iSeHG`3C5LD_4=)KopC+=tw$%eMSS8FT z146yYI5Du;L^a8sOPyzio((E!=Iq0WKEBeS(oLb7Fizkl8_`E!hEG0eA{$yW&ZD2) zr$~Q3PKDIs#(F#V^UQ~V^yYfsC9;%TxkD0=x@&^&R8K|de?ZhAaQW@wK=UB+>a{nS zr54{xX3A?6RRNiSN|LO&8ymez^BVgBH3AgeBlVa7dN{nosK`(#3x2X3KQqw=@cVoY$Zw?#&5yJOzv_je- zOU~vh9!VFlq_kad4fmWBCYBugo(3U2VodlH?hK9h%ZltXoW`1>$7qYvXD8`%Eb$TX9xW@yTfOy!MoaWFL zauE+9m_2{YrVH6@JLosW>y0R=FM84wU;9l~Wou5%luR>h{X0{pN$NnIJCu<`dl5+P zh}Q%mhKr%pA6zOPXhvIi}FdSiK`Ix)#U7*oxpx-tBB6!0n0vQkX|#S7+jp^l#oIu_i) zaSfM|Z5l}T=YJhwb`I|k548i3&*oW-eB*#m>Q4Wv(na{cg|#agH940GQ zUL5?ysw3c@JLMTatgJW;>0Emmxa-cj?@oDl6g^h3XfWMW!Yj#ob7I7$HqS@jAWPoh zohTF1wt-B`wB;>q?HDc1;uBOvegd%8zYEFjdU}tYM;5vvL@w1tWSem$yA{`{UjO2T zvK%;D`A+s2rou}CGvI3&C<9L^?;5bpP)+L<8vllU%BN^qdU%Q@8=c)=t+5hGSfp6B zFJY*o0FCs|Zt7^?8pB80U`d-_XY5Kex{+w;mI>5`5N_QQKk`u8160UV1$Gp=7@Y0* zA(JLJ$LooH{{cH`a`A=7Yjc`l;>~Nj5HJ9yL+3({&-J=2J*8ds_&Hi5lpPoBx+&_t zEE_XmI9v@#E2*I`rWJVBn}Sr-4zU5Cn<+bwDVzt0Q}JDSz*syG%3bPK!S5AJh4mU zsKExRwSHFlhD*hD<5SGuX*au{%dfkBhi5J6*!NK4vTW|d5suht=k>+8KdGAKMa;{T zGr3zh;eTL!F1j;yv|TI}G*LX#0!lre#n$xdl#s4f0V+2lfkrky;VF9Y<4)g9|KaeY z9O=H*bv4||frY69MA}w9EK@8KT4LYi?!J@#pXsKh(eN>RZDd;*ig7-)0A(xD0OLnp z02OQ;cueIqpug2xGlF(c5igHyHx!bM&jhOj)f$rVoU!5%yMJ)C$2OjB$E{S zbRC7?-TVM8W(SyP2Nj1Ju&WPo@`M|jq?dtR-F%(~K8m?DU3!ohJM~8;EA=rdQd=)n zlE|Gh6iL{5X{7Ru=IJ?cH>Z?8d)Rc%{eT8gJEwzk1G#_*%DG3_z1lmT%PY zuN{NDxI3>BnHy6wZ98ix2E~%eMwguDBkJ`6Y(p|S#cIqGc$U|UE284`hUsFM9*?U* zNrq_u%pv=Q{g`iz^W*qMoz7s1wO(4TW?S+687TeTTku?G{vUYEKi`8{t1N+7Otzp+hv_ZV2YnWQZ0HnW@b-|BUP0j1WQ}>gaVX{#z|QPi*rrQWq&m@t+x&^FEByj3!A}9IKa73(O3|fO6Or=3 zXBcx9KfjzLh~z3OH$a=`KhFnV2&lrx;4C_*4G2%^bqy8182PijgMB17xNTEx$U4d*@mdl;AOLWiI8G&9Q7r5`Km*lNJdp15Z zlf7Y;QM!BxM!McR`;*#k`f@nAkOCtyH)C!sFYU@}Iw@^?ikv{saZ1F{N^GoynZjt; zdd3bZot|@(F({CcK8J|u>N;xBJ{_`>v-9%We5Dt|BkVFBcgv*}8Du2tt<;tbu{xo4 zvclkksLM5Ds#WQ^IYJe<^&=IUDwtbT8}Ngue*V0T-q;%o&KI@En$?urX%n2KGYrid zJs<_YltDDj|IXde0P3G@e!pgk2R%Y0K6|`C7^+2T8)BMI-0bj|b^Qs@^q{sV`TD8U z@S?QIo}K#i<|f;0gAWjG39U}Rh=%V%RC<#4+iGTb%_|HYbS>()cvLn=P+2Uk5M@H?&2g8rJWFGz* zD+h>$DK1tYc_D3`TSpDPYMhAs&T2gYYN#ShIzN=y(Z1u3;vm|e8`|#HZew6ql8aj{ z=?~SakgJ^Gac+Vg zY04+E$v_p6^>U$MSfn~ zUu_%+%G~<|o7?p{qCnvfQs3PmJff>N+B4aYXX!!68bWaoNuEguR6A9z0PONzkDn0y zWsj7(F{$D;tBP?aE6st^`cKYCGmtJjw;!=air#-k;Qy7OZFh08ZyGaVJ&$?kU%VH> zN>jW@873D8BZ>G8%^;F7<3y@pQ&Qnh`Y{8n{$JqXw|b;hYn=+*!sFjhyNQ@={>2)yR02zwiadQD^Dyx=+ifxv`i-B>~@kp z>fTiUaG*t8DCGM~Ff8ejXm$CG%*OX^kfe(^`+`fE8x|c%*hbfVL``>LGVdv+SG;LJ zU4ZgO=hklRD}W8k$XAg?7wCN1TWdl`Rn8@}$9JsErA{U)<9FX>6ZcYqr6KQWPw5Oj ziq^~jd-Vq9WHwr*xre!~wEQKdy;^Hf0L%NYEl|#}ceh~jPDM{on0K2xY6dMs!rET4?LKp{_^B(W?&_f3??+dGGrN@HXUvv>MAe>M`lY)WK$ z@QQ{u;fr8WNT7dZral6XZ4(L)ZuyQiz+2iOV@k=E>}um@R)7SDMA+el&$z&L*#A8n zXfHzepZXa-P;W*^Jf+wS!8BIEUh}4gG%kR#HsJE3cmHtUsTq*CzgL@0arWgt7p6w9 z9%?p7Hvi0!T|XVDvk@W-^U)f$6LfGjdQ2t<{&?{ZAu=>NtLF$MRjnb-ghk?y>dQe{ z^@!N%gm93C6lkS*s#;_IHD2cA8l)z>3IACUAZ|8XvO|@XN=7VNQ5>Xg^r`o9;#tKE z(Q@5{_IhU4xT6hx)HcI2K+DFgXL|AE(_1{Mx61g`p=@cWZ7AlU(5V86H9-HY@6!f=LlBBujxwM_N{j?pSf8}bmGPZ2|xaGH`3ob86?_K=GdXV$ zqaMi47PeV&Lxk{Ep#MXa0@ylHY(IN{z#6sxy0L7=lcwk$P!v<+{fXS1&Vv8oFGWyE6*Q}5=i|T#~`iVweC*SpmsUs6n z!s3y(-nLijVy4RK^!G=i1yTt^c>@U*;hF@PM#$8HA7QCCAmo)M`e#N%I!dcI- zxu9Gy_Uy&}YMFtQM^~#*}#_9-0rwzyH+cl=~8(C<#;Z=JS4{U`3f0u9pQqq#=yOB{ir_X6|@b*Q$U02QW85M5 zIc#<@0-{C*aA(%}7oSQHLC#w%`~8lMj4#^u2b8liJd)Ub<93I;YG%7cAw|V|ZUO!3 z`-aH;9vBmAg@PjTSRLRj6$CI)SZ>ziBS(gI*6}6$KG`(rftT!u4c+* zf*wm{{3jiFJ>)jP!MCWy+!-PwxlEcptm&oP}el-peVA1mL8ucw zGJGW4OIxq{iQ`I>Tl!SNXC%Y{?%SSa;&(0X{3lR8|!De&sR$pa%|vXcenPBE4g?R8`!>TQny zqT$6h*DZgMJ9N6#aihh44!EY5;b{^E_z&OznzLxrc|iht(K7YdxAR~p#d~KYduXoI z%q+36z4Rwa+Y{V3}5Whc_{t;`$_cFm`s=H$Yd*(bcOt;RqR;->KV%jTDv}=enK70yRUHB)Jn2kU`g;W6}mONrf8itzqwf$i|2Uj)LA*v7`G*^hwd ziQUI5aIU#JiK~(u3%Dwa4QEHJ57+ZhQ!sL;kN3zfL8>Xg8T@$AulM;Vmoj_z9nyRZi+b(!*O=;*8{h#kc{@R|7L`H7B|p%@VgNI=8?Vyrq!2L6nur zt*dg+E6T<31eYxhB9$FIu3#(NbzukjX?h?CAu({I`a{G z{S|x24=ze~GWD-C%O`Kj);~AsJtk>1eZqB79USPql^{@9x6@4R4ckFR|V!x&UUet99bOW?MYO6TLJc6!psUyX_wmAdwCz{?c; zEopBRSs|CvoO=kE6Rb-+;QQrg9>Q?CZRx#QiVQ{25`@R!@2eA;@D^Q6E%3qoA{X>4VKew!pAO9>hu6ME0%d@L=&uD%h(WO z1!nJoNpBjOf*%zBFO!JX7{Z_S{&3&7ed9}A!ed|s$Kzp@8_VZ5EgdJ~qKAny^>sPF zBnnd1!w-BnI$6-96kZ3@7XZEX)2c&eP6JnguTXInk_NrbN^p#zuLvfoGgBx%%gvrUKu z*ofN5g2h;V8(57@@;7e`(!3R8S$A&wxJ84}QZ3IboRKY~swc9r{~WmXJoi5Xy>n%9 zJYIxKn8P5_G?&g54>L%$jK8|V=cyu~M0rO``f5bPoan;`$8zHGeHy#YuXb%OMU2+`;qe{x0E| zWx$8~qchU4m4FOKy4x4NnX;=xKch+xUiq3R-=bNwpi8iFQyG1{r;7qiDBym+`Lwj$ zd*Bq(c196zvf2M4yg!dCKk#IX=DBh>b<(;Uq-)25dQ ztA_07cHQjau=apPT$lBdnsbpQ$E?4As_|&s+?W(Q^#f`|%BkTqcxp@vVB991TQ5K~ z`9(rZWNJrgo?Zu2*Simq5~qVR*=mx=;;q)6X@()0Q_%Ae_S(o(hm~zV>7q!>#eog-;T-tiIv<&2 z|3&*X#PhA$sMdI~v>(*Z5g+CA@DwYg5BYNbgVbApy)lTSwaP|ht8*S$GVJBJ`In2E z&)be<5FOC7Ry*q}J$S3(gD`nV^+z#K^Exf3^tcM6vbHAH^BDS}x^?>jc_32BOi9Z( zvn0|@>6Z-8^ym3~?kRYX^T-67>#vWZ-eWvho3LrAv>j+HI1dheC5LZOrhnbXG!+!$ zfqF(Jr89obCyxeDo>2G{C+eEAht%v`$;Vsg=h}yN=UqoK>g8$*#%Tq0TnR&4Cr(B$ zzvs;IVs>F+TRne*gv;G^^J6;QUeMLa-%*W9Q=R@qCb!WIKqy~Y!dA&=I-GA%4COl+ zN}_}&v$zMFd(-$Bl*z*+VQ*TqzbFt$K(wp3VxV$$BG0z@pZ5nGfkT0~^2*fHR|2@H z0vDePGVI3{jnS@OTzqMZV(?i>P_(kDip!S&dyL$GtcRcwxT?)e(kQ-Q384?9Q_5dlFAz;MHI0gSGJ-k& zo}WBPJ*^of(o2XjUMg}l%KX;Pg7H!nFT;NI${HTeziiRF^2A0+oU17%TE(K0zo$a3 zWS*PWmKqi(hY-$;p(^62@*vq2YX z7z(a2w8r{QEL_HcE>{Ky*^bF7XZ96@J)W-F%_*Am;2C793F4So9N2<6SuK;dP4hf8*Kl`)rsJnQC^hp^k zk(X{cEE*CARqg1y%(!F23v4=xEcUq!A6tQtSrF1*{qwn&luy-@q~SKp@x1XUT9PH@ zZ}lYTC_+Lom)4&IER36NV*!27m? z15KBa)<7Q1J~Ld|=JWJ|_fwEJ$y!$GRrt*;_k9J^+p%;Xs96dB=Xg}#y+`VHu0C>G zx+h+seUuDBx55|73@5$d0pykI-Xk#JIO}I!lLfbf7 zCJ@0-AAfJ-UcEIwKCwr+k2{=7+fRC~v{f^QI?OSCuu}ODRhnBgYl0{ zPNB~Op;PmI_RTN;GWV}$69sQ8uS^4{tav23aihszS^9skGM;5qf`SO5kK;_Ceqe7s z0i(aEv_143wQc2BRJ(lcC5{{rc{s&~NowAnzpKQaOT3!o$1&C6wT%HH0}23uy3gS1 zHJemwYsXmLX~=gxWuV<$z^RM*C7UmZ|6VVQ!TmZ&|(4I;u?GClF4UK43D%GwFu7RuA(6@`>+U6LqH z$5Te9JCT?VP;e-X-02S*Z3i$0xTU%xL3nK^V{uaDWvy(-4^tL!q{j3B+Ii5+@Y9{tNf2d68x(|>Jz1TxVxk!EjK8QmG6>%)M!yp1uYw(`MY2MYLmKAbiH%j6OvtI%wFh zK$^5mkN4^9e_x|5Xw6X2>c0pcBc1~AGw7kmryr){&0KZ(5(^as@TkqdL;bu8d?85G zC0ziK=ZaI$tMc>sHXAr8CM@}V^x&hk$CZf=PsvevTBso2xD9`2%O?m$Fh*}f!v_t-ZlmAkk z(^WdEMj9QZduGI6hmy(+RIBqqmxF%=n%(ckCSPmwU^~OI@Y)x4W#yJ66PQ9ok~#)Y zj~q1`(Xxa1U8ke6c?RNL&U?u__qzP$de0Ie)zk!s9udF^*>gKXp|T}l?K@i*SC;An zE#XtuVi&gpeWx_SRxl9*4wn*q00uP?ytg{zUXQ?d^C2U3bSY)DB2qL}$Y>zIfkFU0GED0)9;K9l}%INGhU9NUco&p z-2J|bJCoKKY5vA<7hU)MmR$)R^_c;-9`vJ6T`^hsj=rr)ed=A#2ZR=!L$ zQT&JWgP?$Lz=}&B{cOFq%f|^jd*08e>C!^g)7X5*o4|`Et9D;!zK3HDry=+= zL?~l@)%05LC!k%QUzDA5UJDhQ5A`QLF#vEr+dD%pfjv%HL`G6Ycj;CmZIRtO zDv_Se0h;S8=}ioo_pSN{y@mkM?qwf3b$2q`weN6FHl>RGCZ!?v<&HWUU?g((8>4y1 z6NI6^wW?i#ieaa7p(nRr53sN0)$7_nzLX2S(-EN+5Y8|vOO&V7XDSh$Zsa`REWsPk zI!F}i>@IwdTw11i8tx~ZlMHhT4XfR%$eYek$)%g3pl%(q`$C1_iO;t#DX;H^UYQD> zZ)Yrew+)*PY}|~or0;!TQy;6g`1E*~-}9|?+0zY={4{}Zx)!@-E@13(G19srzxXYQ z<8T5mx`5cxuzy8INrv@4v#xux-dixLw(TE&Y@plKXIr6{=@CP>-x|baF}kONUD_E+ zhiM^-t+2KUr~dfXBuKD3$0O9 z&-EvZrjlW|-NIe=aQkHkT-S^6?}Z+Hkoe6v|M@WK$pRHo#jzMaI~BH2oYVMmUyz#&>%aFB3~ryZGlG~xrG!90gXaQEQ?)!=$Hzx~MvI`a4F zE5nlkWy(nUg`YNHBK0jIka2YExpW;swJ_Vd*v(MDz0R-ad)~hxx>Y!z%NO#QPoEm7X97uR^`>eM@ z!MY8duk7riRLRVT!-R)$cUMRL)&f=~?M%P~V$@Qf#Z7zVKxnbBUK_3YyzWv9>gk}> zuIC!{G`t!66*Oq1`~_^|G6!}j_&&4XmdOpp%vLTTqI00LGr!m{-Jh_5-Hnrst{2x2 zH3L8h(MfxQy)9S9rAi#bL1P~`1j={6koh)sT0qHXUe}wH0}*~+B3LAsnUmSfqPQve zX*Kf4i%Zmkegt6;kX~dLNNPv{WKJMu3?`tOr>vr}9z~qzTS%5hHQOxR^#RA{eC7lAIk+IAIp&(o^$7Y_D(17D`~#lqHDeCuI+E+ML6lDN`6?WA`{ zPJ>nW-&;Sn3(3HUXH1ewpvz-vIe zdwPIfs;tV2l$37(HGDCAP+|1FnloIv|l6VG6F8zv=~Pb?Qr`+poimmRAaPw^&fAM|Z7O@^OI(OSPR};8S~HFE<$`xg_)c8K%6^u|l*TFgot8KH zZ@(303Mbg8!NWd@uEKkRv+*ultr2usuWQ5n9|m@x1*Pco5BJcS9qSmV>Rhuyj=xM! zoH{{pqdVh*VU9m7&0X8rh~{c^JM+2C;^VD(x4yQ3kS+1E!+NAr4S9HC-u8kZK6iQV zmOn03IVihpF;~t&`7m56Hz&gNn}gM|;bfxtgp)X@wl-?=1m|+_X@L5%<3h0A7p5NI z69*z+4U7@0Tb3Q<*2Awv$%zVBBsPmyw+xI71!#}f)&EK~Y3kZb!Z^srxRyIu-3@8T zvZu6pI%Gj6q9i=@Ce8xl>HGul(Ln9))LVS6i*K?&XG)eNI9-`Mu44*XKTPr)8S;5w z`RoNZ

      dHH7%#909GfueC#O7+XBTTi4DLzk*74=2RsJgk7QF78l z?| zpbudOo4BB8zmP0B!mDan-Q^K~xT3^HNQUCCYHyEN_Cw&|ZIIC(vjbX2%6L7%MY?)m z)Emp;|9z=Enw%OwA#6-p8WceYpkZZ;>$=#UME9nr`gT%)d8LSnpQo1+%&+1fO#hFkSCKGh=~uU z)3Z;ux?$hT{c-O?BJMY+ZbZ>Op0*@cI`jw-j;h1;cGHeCNM&K=l={=n1!U1l>0R~h zsKqhWW|q#TKdL^-KRyvc$%A`H%s(PvWE?M77CLSK5f_5pPji4N!l*34#u6on+(hzQjet3Pc762cRi@r&mX{d zZA-zYRzEjX{jlCHX3lIA$HVrQ56<1YfXrPz^rWG+;r1XM2JLHOx{eHL+Ul>Q<><%~ zzXMf)lUf1s52=ethC$|g1hRMa|26iW0ZF!R*m&c4vT{}K-BNRB=15U1pE4)q%)M9c z+=^ORYR+;`s2n%~H?9N~(Hu!m+^A%xsHiwVME>;qzn|Vu?j;LvK!1om0*igDjVLYwC|Ssg9jyiU+|kU9~m!thHAcwTi1PGTw>)et9*`>}eT7S?YOA#?*ixC%2>$+3+z~2%U+c`ZB_5khflm(WO z!|Ur-A5C({p7xeCN1Vz_=sJNz{sPuNr^)B1QHR9BYjZUi%)FQ)iliXj&M%hcy>nLV zR$Tqg8wDFau~5&Ql9IZsw)#pYp(%Y}CIfa(dmL%A?Jrqt8AlCab+9Dxrd*5?3_NY$ zxHSEjq;FP#+jLikVq{HGPa^FfbcVfIeST(6PY$%A5~87ITxzRQh7(VQXjr~H6&kC< zGRynb$1l51Ke*@v^KYYI8ujxiDSSlMmWhS2QyQcwLtL-%k7wai_+?3y{v|iuki9;2quKhtJCG`5Q zwQ2otCSc~962O}EJ5f}}v8BcZZ()YqW}RdvtUWiQhAEc!S`q3qh6k&*W|$fOBln+u z5ze5e8s}>ibyk>{C=P)aN_z?C8i`|ie`Kriu)Ac`)UOR}qL$`b5T)r5egD#BbGgt~ z;Hx`pQIom!E5j3KYIZ{I=ENI#@eaVZr@WaYh(txYC~#WPk+c|=%|x6R?ibFQO4uch zH8ItMxZk%jg5?GqP2z!tGHnkpbFQ_$TWh#-~&m*L_nyo7}BvA3BC>Gius9WJodo6hnA>dsU6f$(bs<4{F0VRzl~fXAYW8DNEHvY zI0Ay2C?i%Ntl43__qV*lUECYas`;_anZBl3aARRA-`GF$2~lkot4NPp*n6|fYx$jC zCvEiqG$lQ}`17ooqy{BMRdF)NrMtiPisMPnQu~`-F93eS5&jRkfel}}zj8J_e7j?vT1qrrmh;Q~%YGrf?iR0R!d>EwuCe1rp0glx0TBI3 z*T{R0?7FBMvGKQJB1uP!ywM`;#bS{oKM8qwzuEi;ny19O%{YX7x5=BlpI_F^C5yqiqOrJ5880QO#N6vzZUjZ|7n ze)vpSY$|3X>jDJbN@88p6fvdlaxO+m1{8=1YdCp({&&J=Ey>A@lD8I`QFZBLn{C-N z2FZ<5el~~$G$Tf>T+MG}s>oF7ywuK6Q;T(J+f~T)rcX**aZuNbj%+ygjgeDSn;pQe zs9Coi)=W58$iXb?-V!xP33JQf)EAQgJ-c;;iRgZd4S1@&tj^DQ0m!sTSxAhca_kv8Jes^2z73i0sJXi0hx56s!$it&m4+PECB?1NH zdU`2pv3mJF#v6kt4{VVa>J)8t39127^x}GsS{FsS8d^6o`9!wRsMg^QT?Q?w&8@Li z>MdM8d{L{ZCL=g{cpTS_vwWLnUb!d}(i-Vz%Z!(#7yCaWCG2F*6?Pv4x5q3U4fd+J z5U2kFPgB4I>+pX?!yjcN^j*l+Q!TDLL5ddOBjkF_X^3;?a=_G7!RDh9&Wnb zhYcx6x6^+j7ak%FadIa)BVkIQHt^voH>KAjA*_V7eGwhuU`>*YMcXRP>8rpioM*xJ`DYSg@1^J}E6H*0DM4Aes0fv1F}40o{BK z^x_D(sAQL33eq_$u)M3FiCd{=0tC>q}g6aPq_1r$aV+$xD;j;4oqC>`T z3X*(1I=QRFo33*QbTnDK)-EL4k-l=khS%Gk4!>%5pvCKzNH0#!^8~b%L*x^rnG}gf z=O5(N`5R7U1|EB<@9pOKN@;d-^BE&JgU?&6qjb1Io4Sn{_z}AuwN&$TB1mFLL8~#(6YqAuxGKh#L zjiw;`7ERS5^~zmfHhh}^(rBsvwgbn(VGn(o$r=VM`7Mm&co$=SI?@!60MaPv1m_;C|zd~nJ%-n-L}zg8SyWJdGi_MB&g z*gwXbZm&gq)z_cqpJy~Zi}zO?*o^k#do^;HJlwxMe-_fAVAK{GAC<|5$1aZ1Mw!A3 zDM*uPy~3bKhk}67vcuLF3uU7YcGXSfPA2QSie%PWm7Vedk2FiDyrX>=d`BIN^KF=& zXgPDKypXHb-e)}mF|-Xk3pv6E?`0}!Vk-rZ21{pWK<{Eq)}>u{u^R^}s80@6jJ11h zCYDJ=X)tQ@wL(mq-)ss}xl{Q5e&u3Au=8VlHuo0i0sEfsW&~nz`*Pav*Wf>{*r12; zK=Z@1G8Jnx*U(UJf0ozzBGKi<7B&ccWs~*5YcIR42X59&vUKE-@Gz$6+x>g1dq>nH zXPgtf(Y#QuwpD$oCKJJ|+PIG12vzp$g;QjI2>I5yL=T=$48)pk&u49~X$cV0sBK(G z?VF$kzB=KC9S(L?uINFv14D{zECr=`$MOdI;_d^%#KHTv+^=89-2TaV?&txMldZ?? zsyy%O*MXzgM;KvO<>>?`gR_BkPxcrhi3W`DsnPqkvRCM_EX$+XqKLbf_>%u);9s}w zr6Ei>>Eb(vKi=HNccLp7u4D4@boYBcOCicY;ybtWz{aQg00YfIYX!K5fVPCID^?J| z&T(l%)B`nD$P0^k*1We=AO6GbAbWdUjI+(IcOcefXN2ro2b-!Hi4TYsSgC~F)#?b4 z#vq(UZ@s`krQ?5FvPAB&xfo+tehnV}zP)vADeN*lyK$_9cGDSOX#wE8Dmr~s(LG7~ zD5uF6E{^M-nYNB2vQ)x~0qHYlIFt$M6Gya;?~$Od^lY766Gj1$-n3Rap6rY9{j4%k z);?}AQ(jVqwQQ2Ql7y7TL*YxbLJHiYd4{UR{!RNPKGqt27`9EP3L>$`XUWm^f=E<4 z2{^eO4HwHJapAV@NCZ%AJc*Uw34(lzCqWiz#mXSu!CpcmGTjn=h~1%=3nGa#k=Z0} z`xY`ieBHVaw(|UldBJ-+6D?e$?^+=s_Hq|@y;U5NQTlWl*GX#hN4cymCsJ)e{){xh6>2LU$rf$0`6 zO-GIgl_MJE>JJJyjXN}?dMmKrg%T++2cgEg{fF=5=KVbo?r+G)DX=~+8zDs9zTZ0- z^}0YBXSZFF6TwStHPVX)jlXdiDZ+76Z0nX{lc??)e{mC3j~nFjm%C`X1Lu-V+xR5^HP zD$E+TD@1&T%ve{6JSN}vOxv$`((k0^j~?=rg#uLElRSL(K*dWVN&>w>B1%PVo=bH! zB&OjCK)pG0y{^s@2|1NMJYO2=6Lk$NvPivyE{WbD7KNw1TWw&&a$Qbe zC@Ul1sRXz7%lPa>-2xN<6~#GS%2y4eq1KDjA0FK3YY2GT`ie`qyA*I(=svK=4(rc1 z(cICjz@o{brUNC>FUSTidF9+X7C%A!r#iR*O-;|=PP1yD|J;|t&M)K)Tlr$X`CtGu zF_Eip~mrE(N%e<26)hSNs3QrY5hq4M`35?m@LN_ zAS)ueP-~LQyS(K&!~J{XyPfklGzv!ftG>eBovOp%z(jHQcgf1tegKI8b#);fAueu6 zlk{>4K|2|{GIW-Rv-bj3-NpY=zW=P}gWuE@$ReMcIlw99ObO{yrSUp#>z9;+9{ykq zG{c*q8(HO3iQF0Q`VK8}P;r+YHgK}Et#gNI1Qz+12v0r1SRvv&uW44wQA_oRYsJU% z2Es0ebLG~+CRj_pS}%Y7MUEX$O}Fgtz0(0lFfKGAPqZ2KgnmckQB+;W&;2t$pqqYb z^o2M@Cli##)tbenLq4?}LhCTuTZ3}r)M)YURCvW^?g2FjfYSv;viPS-`mippRc#OU z8Z!Ns)y`N}udbl7RFiMAU|!m_twLy}!#dgBfWFPsvWI-D7T+3Eafs~Yulg5EY7%ok zq@^sqZH#K?k9k{uc$ue9k`JvnjqJ-~mZ1xF%MjJ4hN?4%O5ab z{{7rNXEpiR?C`?ES$U$GT<>wSPp(4cWpv2<&qxyQ-?RTXVRfm9`BL|EZ2Mp}_5t;9hrSp8x(?|~ZPnS(`P1={$qopF2528(&r2MF%hxkv&cV`~@^3gEPfxs_K zYZg4dfx5qN4|o8{U2XuH<@Qvo{xoc?&*E&@xlS|kmya;-pNM}CMiD=coFlo#jHDi~ z{9B%I*rKRlR4LaU`c=z4`p!zkfKOM@#hdp;=c|`}cI>l~C~wu!B?kjLZ12Mn@Wocm z(UPG3dtmYFV5p|nzIWcvD_^pnCJ~Y9Xr=3fhVa{_hLt4NOn;=MlUCZY>ATZcoS(n@m==l%?kE>=|00+- zWno?zbIGf`oe%ePjPets`@KfmX1B7~q3*Z3;@5iR7LZChV+W-|F z`P(vEu3eSQ6Nac*ent;Pm@RN9T?fpl+H*Y^&Fbwt;A->-nLomxr(GDYA>heq(5^TV_oxmo21S()29FWLHQPi)1=f=4wllIbe3$=vHssYb#dqpb7I) zy2R0z^*~TiDb%hAV=Addw4}J<-eH2Cy>r-U+LzY6HmsQ%zlGwF-`Ct={DeRbwaSqR z^jqP<(Mo+>2eFH-m2V_Bbh}FE2g2$55ip0)jm-6t2J1$%gp7W@2 zqa2{|2+(}n{e0%`ALMXoLFMn`^`+vJq1B^2MBTrfM2r+zscGNbwOV?3*$>K6a8$5V zn78(Xt$b%%xqkmzQM*U)#Ely^HIbkJuI4qzbYOHkUC6K;e?@&aDu z7J~ogiGtQhMzr@`s7%+5NZM`fTyX#u4zeaBd+ZDTziY zw_QEcB&!_2bOwpp3z2U4saZ(73GhyZXVR9ah99IeJ zT1@fK{hjM^Z6!i#`5rjJj%*y^!>|oyI=Q|x-DcFLn{MUMi)7bQ=*6=)_aM?K!Fh5b ztS_|oqifEWxIAz&!S8>4zvCHIO(K;6q8_8ENNv<1^&xmn=b8lU1mx@ zg!g38$F}*%DwpO^#Ig&siRKNww6CK3@LQ3<@||ZL-4>kqscxz;=bd8raQm;G3W0gQ zJ@RAUNKM4OU8MO8VbNLZ0=!P8k4%%U$xKznRlXRTeOxE!%c3zN5miaz74v10@j5nd6UDVEN(nH!TOn>cIHG2vd# z{!@sn_Z1~n;~`+HTm_-7g96d^>YIq~FE$qUJx_SlYJN$x_!LpF29ATPQQp7&ik0zPVI%=bOrJQ4rTTd~PIY#%os zCc>CZP2UT)_!FTtN(MH5wbV%;<}8ma--~o5>hd5Kl6<1$iXA3vLri-o&6Gi6Bi^A; zsK&IZ^cz1E6l*pg%x%f4oCi+v4t@WIVDTy@?v^@lx5Y=Cs zJtho?)<)x0zr8F#x7t$Hd#pm0%aEBod!DrHv4)_|?ctOpeo>L8_KoAWQcdF8ccuD` zxALvB1>6OHhn>npc!h7J@2b{DMY?OIVlQCN!Z~dRN<5H5lU!M0bww{uJeXTAo}Jy9 zilJ?Xb3>$<$kX*-%_JaP&N*ezTi+K$Y*%ZPFJq>R{Kc#WibuVf7~O&pV-?H?p4*%c zOT)`zV8Twk<*-Iz&hGKOq=xXj@d(04#L~_!4t2P(;^brQ3F|O!F>3a1MU1dms&3_P z{u`o3*?FQku$UVtx44_v<;=CA1M{m7fFeK2p`!|Ww_=i9s_speggiWqvD|$sVY4|I z=Ct=UT0?Yc#%a9~_w7JvD{y)N|N6aewa$|G(y}Y0vO6a}q6p2M!&_;{-YN}+-RI^kK zJ#d~sLzwfL>=8KJ&yAjmxT{t7+u{C~mBw@{8`JR?=$lp9hJPPh-z{U#Tp`G1Oa-T> zzAwG~=y5h!Z5ZzXTAva$FKF(14rlm?G|{AZ=&Qd-pBQG;vb-nI(flFX;j9Ddgp|_I z@2{u4mCB+w21xhG-y1DAa7+kQ=k^Qd#Y9pse&PIO!VyW~##M{=#Fr}xmLi75D)Vg* zgEnZDJOwWJ>bOztz&!^|mWG2TNN=|Iuh_nr% zE(P~rndQMzmx)$_uX0TBu{z-0Y`^Ml`q%GaB9N7Em2%_`z`jfA?(#=_qe}PsGuVpm zl&XWO<&VbXXfrQ3x`d!LpPq-PY|IlaZlD&e(Gr71ewgPy58^r3{Knx%oWNxp5uI?q zO+A6mKlTK3 z39KGCseawIDnYh+E2UeFsGhM=hHyna2kL%?F|c%xZbLSL;sd%a_RBG9T^mWNV3fwZ zJJGS4)pFn}snf;17(-Saf2r9uNK6hBhDP4Hn5Q1u=wCw2MK_eu?Th31t!zT}#=D-7 zZ3TV=YG=96V~-$TS_f+W-X%-j3M1mSnFy(eCdcsV(-;MvKW#vJA*|yy*&a31q)|%} zE+MA0P2R9!-u`5jCSuBrI~$NJn?)2MN&&-jGIv*NnG5!yfTjGWw`Vwpzh~|CD2~?+ z4H`;uPCSm#&cbh|wU@2pqvu5Wpu4?lX6NSsi_6yzW zz?oRX^rMEYTu&UNdYNmBJ+Ahm3t~^>P98~fxxHo4#{UW%bPoI zz&!F?__)sF`Fqt>2T3$?=|6UXK-@}xzbSGQFA#MX;>X$uQ#34&dCp>5X64dffheo9 zJX|S74yH|yPE`}~$HT6kHtnln*4lcX02|6wM0gGd25LeNhkZF7GnGW6iOET3hZ1l* zr^P;7gB3ft0id-hq?o?(LSM1uTSw$vlofZ$_@QGmS*T6H;P4O{`TgR~<-Xa)8K;+h z-GN0DTbnZmh|-#3m^weK8ci69@!t|1Zt2Kj$s}qo#mEi#_ZY(&Z)wO*SM8}C;9^5jb{=az0htg}o{S#YgDgN$ zSQT?ySD+s4e5-HS%*gGTP~vPjW0?P>efdUvUtsN>Z(0&V#=_g|3R>O5rg0v*f&kr# z#c3Ejb|=77pB|YPnqwg@0`byUoQdau+*eg#k}?qcogc>6N?%Pap-eqj1>pDDytnR6 zdX-Sdm#EjAxl!-dWW7M(H0O#SA?)qW(mYCj@P6}L4C~#`HEC?|ro+Aw%O_u{wh){W zX>v8B2{x;5?rCijk;F zrz%8ToBzmd^I6tSjV840mFdy;S9i-Imk<5TFaoAs7CaJZ!0g}rrWmfipKy)R0)nD# zG!t<~sEmFM6jw#~=pr#sSCrht57NU+t!UMiu$AjzX;j6eO8mDf3CD4Wa(p?$FZnjv z1n%;IJ1Br%b9a`>gx(DE^MHKM+53}E9k&=N*)))k*U0ckR85XiG;WyZUAvqPa(E>* z5#(HIwJLtMEblovD+>te@?><~O?Gh*lw8rHkx5?1+$DJe>B~j4p*5GBs*ZplqZg{% z1tvCv{zH@U%r+cdbC)o>xQt&q16+Mjj>oI#njJABqUn23eDICxTK@vK>iLuS+cOsI z*qpuN`c%=>)P_4x%K$UI1z>?Z?Apg@^hVdQg`pJI_3~qq?r4_tvYMr@g7Xl7Ic*{u zk$IvRUDKrZ5lr#`jULi(JrFWU={;yql+#Z2n3}@(l~UD=9*QOBvixSbe*4nv*XP;( zbG&-y>}CGM&intI`+t7xG~a7&iPz!Z6(GKR$H(=^&w|j*9~@j{?NhX;s=G#@2-N3ASfvdN{ahIZkU(&{nTJeCvSx^ktz5d0bJtkQqY-^6Z~14{8I~?f&dEOH#uqD;k-{ z?Z>+sdMA&-tMfM*&Jc!uM(lfRtad+Ye3hZuj~ZHy{qT!O|E(|92H9p@gfO0c4^*-| zI!@0#t_Gb*>LHOVWqXyh3k=C!D&(E8Hi6uJT*IS4%w_(v6n*!(-ib*}MEA{D0TjSJ z1J&qoGRk&@_XeHt>778Lkz3{_Gt>09jQIOe`mg>Azeizu zC)P0$s@leE`U9yh>=0Dc9q{vrBih(oUA(U8OoF!Uas@bOTq&3<9+KGu-DevN8p94ln5EV$lV`BQz1p?=yvN7ex>JGPBU==^gtM#FySL18jio~`t;Fm$8M4;*&>)orwL&=$djR_}pu)G$l_mgegWa1tmw z*CTwbC#jnzvny8dJ+}5bgQ#*qs;;oiru+Wu&~P2~&VzgZ@PTr~)I^$>TzHbY|pkR^l-2Xpcqui-!_z#N5F|*zE$KztDI#h&n z>>USW85R}r&!*85(SMWZaQDqVN`@l9)8k?B%jV$g0%ZT2wujY&Lj1i9wdU99^~=*I zXdH3t8F%i-=%+#OQarX;7Mm$M8{*aO=YxB_*#@_RHWA^WA`|fBg(Vw`Ji{AzD2VLX zI4ZWQX&?rLY7WCu)BAVZW885+HX`%wBn@iPr}t&sMcr_58*S-!_&TC`Xml^UW@`U( zJJJa!xpDNyPOO$p3yoPAuAZd^Y54oC!uk$QW+T?KkL!yQ5M*rV!t^k7CgPb!jn}H; z=C`t9U?Vv(^kmysj1hEPQ_N@}hlHLC4O{-$+Ml9IX(+g@LN<<*i^J;35~21zX|&Cj zg*1FZByE-IpmEYj(ANMr5*})ZHWL1sg*4K2XB`^p+Ozluy2dP|fvz;GT}MAPi<}Dg zCm>P_Rg7mS9)uyrnNz12jPTQ0Sw>HIo^kipxL0O7WFPD_f@cz*J{{>5t+6Bwg}A?T z-}3&g^}u@WdQ<5K{dvI$$)6rw-n;PVxvN-X;;p9@pUzwVmu!uwPW8L{R%PT%&~PEm zB>4-=;e38n>}nB1a~166^hnlfXeyly{dT>VA5dR*yL6)bjJ&352F6E7*0w?*|J8+n zUO~sJj_R$S;%uri3r*g7)nDet$~t_&cqu*>s7 zA_MF*?{-s9C0(|te=(&Uyh5z~z4PQdDMVbY=&Yq8i;9c_J9sp}g-z(5T7}e`C-Lz@ z-|tyWY@Awbve8cWs$Qux|DJuL-ddkM0u|0!;rg*AGv$7y|I1ZHG8>~=Vqha%@@-D- zkOD*eTz;T0$yv6`=A{lW0oUd>Se&12397O{TgOXvpE4HoaQ*k*Jfy{@v{kvzmaE?R z$&yT8qHrqiN{o9HHt17D?UB45F6^ug^{1@8NIOeY09Z2`RxCeaEJe}Jd3%_V+>gHf zF;_aTjxF4m47JA`bk5A|TsY08c*Hw|1vVD^Ctel0Iq^q7{C*hHJO29cb#57t0p$(p zjcLiYO1WnX^?9j-I#TIZWLXDmUi2n7efhJm=pN|RA_}^;_nNF)4fX?cQ*=;yq}N?r zX6uwLWTw|2h}`Wv>{IBCk)K-vd5P%5Xhg1lQ}PGhj3?uM?KuPg#{W85IP}>tljRQ)$ExEOu86ie1&RfbPk%%L00000002z@0000000000004>t00000004Layj49*13?ho z#Gry7_ydGQEd2+9m6ZXpP(f4O575qDu+~oPEUdIhr54)T*=uK^*x8y7FgbVMPG;cY zv5|lWSu*!#-prew-K#j~PW*4u|D2m}t~`f-C9Hlau;+pAlz#^JM;@N5{=nV^-p!q> z;NLayapkMx?U-L$_ni;&rRvSV?-$Y2MSQ0)-+%jGqMm$cJt@71&>Q+2 z`+xMuer+SZto>>tzNhu2@O#AD{$C*8Pnq<8RK7Lv**tN+QE{Hv)c$b(RQv<=NB2|q zt4{iQu($NQb$?(t^}IcTudVaE0^ItY!Zp9_&oub@y5C>m^In2y!2KdN_h$)sV2$Vd z8S%!K0r!iP1&uL?f9PgIZavCa1f>zf6i)!RY=rhkU;Pv9F` z?-cNx!g?FPi_Zt^Yg2y47r(SAw0~3aHF#S->+kRJHV+YBMZDc7 zXQXc*xb-@YHI{H%xlYv8lih1&0NYPk%uI00000002z@0000000000004&q00000004Layj49*13?g- z#Gry7_ydF}mi`05Mk^JuP(iKk4_I0Y_I6rYSZNU(74!$#*=uJZ*x8y7Fn8|0-J5|2 z$0h^}+;WpQZ)V=?>|R4e&fPQV9+3%=`W)VBSlv=#&jUZGm4EnG;eR)IX&(ab6(SA1 z-2xxicuo8}=GKsJ1$KL2|4+pGEy{eUdNag#OVrZ?zgwB_zx}UKPcg8bl-^V5_5BU~ zKO3@N`{38LUoG(aTHmPnGveEPTp_-j!ni-2kM%Nt1ALpWVR4>M-j7tg40_xW>re4r zXX7vIkLrv2#eaJG(6^`OtqZ%Q=S}%B{|lmbbiP-qzbSkg{9O0@2Yi<$#?NB)rOkSm zf%~e$`F;c6;xYdfxF-ewci5Y%7iRIGdbz%)r;6Pt+K(8IZN5KP-z?%;y=@d=`ez9L z2EL>9P65BKtoI0b_58EG4&`Tj5%KK2bHCZ&`W5Dn=YKK9U!Z)}-w==aHV*+`2jA|K zOVW1?-1@KaK5D3k=YjKazgSq_21=X{p`OD zf9vlf{Ovwx`~$en&l33deNEx2FYZq&Ukc}ZYp7>S^QE%JE5{2LUD+s;ch(n2_1ULa~%W2&vx49B- zQy?e|Ibu>F7UfcOZvzzl?U$rnOR-fRo)Npt1^Sjq;%GU$XLfexqkQt|Hosb2d+B_Y zJnv0UUk6{$o~`D$SJ&4)uYB*GPgElb-j>-8{>G?>4(v|FeC;dy_3!iTA_y zWlzS>$?ekv0x?ukjZ@DN&*L%3=<8qTH+5N|g50QG zWY}bs18S5JF!^%!E~E^`*r0HZ907}G^Yqg@p-hgEBTr}9fH5e31B(G=5$UG7ZEkJ^ zX=i#WK4lQ;=IwMs%0`fG$^{f~CXsF~XYYK@B9hI2e_y_SldV5y^A%+liKmz!p$sDJ zq|>(-ltHANBATCa;T$QaTteJ@2S_@T>G`YgD2q@yXQyNc3XpV8=|MJ74(UiFoL3i< zi+@uVk#Npei$XgW*?f~wc9C*Ur?a1zA9Bhj63@BJ?ygtMJWm#sU8JF6p17DfKpHAs z`u*mAJvUVYq@pU@h`E6x9TmYNqYNSyrNt=E*Eh4|hBAw!RNecKyLTj}a%1E6^8w7> z-d=F-L^5JG$^p_)dDC3r93c5ri4iw9LnNRgL*Pa^Y?Qun&Kx53lv^by$RX0tWIDM_ zDT|GyL*6)&P7&Xx$uIP-F>J6K@eV*5s%D;loF*ira^|^%-w?^@{A@~{O_78OrE?<; z;RZx*7GV?pa4R!J`YBdsS&*2lQ)*>~4RSed35AV{2P4jA1O23Bk%P-TLU;@+hstf0 zAyQCflZ){olF%iaa7PV9B-{#(8f`>m(Fh5t945B|M@UF7+0-LK5-JwwMLNH}p@bQK zK^dK~yIX`*#O59mJPb`#2bZYHE<{c{t|v^ndP0mOqzFhc(onIKR343ykc#bNLK$oz zBQD0rFrQ;>QsU(ntY@i^z*f(l)5+a*HNI(<5 z&^LldA+~ulZcvb;Ppf0N3$b0RF)VAJe@C?k#z;L?Xy;ss9{Jl4;x2rqc6)|tK^>3eh zFN(3=?pf*oY3AXZ``fQRJd%Cnf*#9W8C^A)ll~!R{oNkit>g}PaO|Q7cXfZd4tQ`^ z({;#$$BnsF2ktN`hy1szx!ZT(UbDs}4|Zq?%8{Fz9S_FG38!5T#>Z`Hc04%hl8TR< zPCFiqx}@UJ#W)ysX$^)huEF7PDQwF-iIZ_K?2rd{#Y2ZY7`zl{Lv{DYP6SPWd=j9W;`WzS!;JZRaa{@<0xM{SBAxBKTHiA@l;*fX~VwoPY(NrD^dtIcuEc&hf))E!Sn_S316HdGp3Q*~8fLvc!*sF?NC*uJMm+5liUMc3xX zEoPo>c*=g5^4$pNL;HV;XDy1u>0I?ndlY zlX&fUDsbZ{71+;v#f>!;+gD%hlSke0)X={AhHiLD4K219r`+fZ#rCrVHRxm5Q}#2@ z*p0of_NgmF`ILVf9kkGXmN0Z9OR&H7`EEE$O>VTf^|^8Ev!5gQZbT`u-)a;`@=p8l zJaD6Ztu76S|+)o^m5jsSl?u?tN~Q@dAJQ>QiHOhD*ctBf1)LHJqZ` zUsJIgYf4RHwdbjk8+APOFk4(xZm3WFJbR0A%8e|c_6JlA<>+n{ht*H@wU~Lj;VJc_ z4J}4=NA^DZr#r2D?{tpFd6|k?y*zo`W delta 2577 zcmV+s3hwpQ6xS4gtPcSI00000c%1E>Z*SX162{;6QxJOJh$B*>2si<3%jx-=w5fz% z4hRm095Ja7OL8eXZGgjl_L7ooDYnXIpAnC{3-n#0KcnUBKC`nkKhh_kZi}ngb+DW+ zvge)g>FeHilV^+R?bY>lC#c^0oaO8JYWch)&!iLldN<8~i@Wvi)t|O61aI>BA`AYt zeL0ZynLG=Fv%C4tEEptV5T@N;uiFbH4JQ8#Ud@XvxR}k0^0S>6-vq(Qr|iqs?P|U( z)>rGS2#PPa)#OU-~#-7g>J)vGRk} zrM*~=&nG8;-OWF@U++GA|De4duy?tf7vpR?`@$HFfYI^lx6^ln|1c(FVDjHTj)$)= zzGF=GO-30}qZ|N}FDLK%l)(fW6wZ-DVDW6a{Pa#JlPPlK=_HRBgAy88>`@kxZZ?&3h%vKeI;X{ekhE@nnZ zL#0c9e_X%krYb@z+GHCEH&CRbGI->aL8PK(Im+|Z%_O^_%pxgmu07_i9f_&h*tq>X zg4x^K3(lQLM(jozAq`a*%>~W~$!C)oadQ(R0hJj7H_F&3edC-NBlT2UB`3%j>1Q+^ zT`nn$M$#cK97(5)Z{zG&de?{zb|c;aNJE={nJ1?S$*7un?%)?A8J(Yvsk14PP^olo zgnhUHk())|L_gfh>?8e@E3+y{j8;o(W%dnnIc^E{jfw|D&ZdEWmQ|61%RKt<7*q|F z+ba7=K^vP~jPD}}U9t)Hz(7R8tP2Ff>vfTm~k)5IOC*o-pR>2?>&rA|NG5L*-IZc{D*nDz}dj zWzaxIT#Qd(KF8MD6C|NG|G4Z?8+&3_Rd|zsq{?v#(owbEIcX+F+Yq;DBnI^a;gW?R zEN554OgWoKMCCBK;4wt%*=%i`GlxijK$mP9J2WY1a~4f13FIIR6hs&MhDIkLvKfQ~ zG~x?=LwFQon>VRJL5@DHrf?TxyH+VIYoC8lwFgq9o=s@yT#4jU1!3+ikQ!}3oF|Pc z31mS(h3BAhdN@g@2KBhwu)g=-4G^$-?dzBBf1t>x%k>r{*n~n@l&I&+4La1mS5s=UzsU#cGp~^5 z1wtc6f}JBwNszPvq$Cu$0OTYTya41RcwhjM5=vqK;u1760BH%nAuo`Zp!Y_BtOVUZ z7f4Ic4RnFL1f5h11SXU%bb;7^grbKokepC9(FO7obQfJ9K%r@)3xp^XeRRPb1=$-B zNKoiH=>jPVMJruQ5DK!FE)b$%o9O}x3VIiT`~=@l7l=?O`so4z3c8^#ke^U=)CCe0 zd`n#*L{UL^|0~}kQA=F;AUo9pQ3^$`ULZ@MY}N}zDm2}Cfl!5_T`v%StKj?f0>KKh zVK0!XpgZ;gfeN-|FOa6-d-eip3T4w?AX8BlYM%1_Bfgm_(Y|+_Q=<{~)sP zKqpKq&SA?f9Do$Q{@BBhf4V*RNQFP&zyCxrEwW&~oMpd1?}U4AZr)un_fInqzueva^x={0BNy~o_Rd$T!JKptIqU!K!M;Nt+=W(;Jb2`Ppd0q! zae}bq!Q+I}tOt|h1YyU6kxMGxwJ1IE;E{uF*n^RW9^92{9q{0;An%a}kDT^qJ-DNc zJn~@T(i+?q@;vfj>{1+zeavRkvb>9n*L zyR?%eKJFyqQZ^$#syJ~;#RDIIReWRu(Qr27;~Gp|+KW>kt6MHPF!a%ZiAy3*d@RlM zT`I8leJm`bE+sRmk83b;$%B!P$KruY9vt|nVmVGY4e!N1Hku-r_TtFPHRw`d;mB?6 zWb@utQBn8zc0SMZ;%<7=36^(@tM{v$b@?khZ0Esmd%sbB=x(vx8>sAmet!Gj?#G{e z|77p_>ui2oWAurMlkVPiRWBV{DF@dHS|zpf@(}0imi6N)c{Cw#Z5WMU??w}H2<>_* zsykb?r%s()>K`&*Bws{?XRiYj=4LY>S=>SbDm1; zijVGis&7A{_dQXcc9_k7d8(FtbjMS%{Ww)iIJ)Dh+Adi;o)SOSl=Xm~)*U0=@l$QN zyqy&_@Z&7gvmehzyZN@9BiQ#;-;XGzUiuBH&yVx*P#aDg%%=Rv5o+%+Y3bDGhx%gs z>WlqQUoGF(Qk?Q5pX%AKPKh6JN_~)M&QqZunWwtg-(WuFM|H}7{_!~UWb3o9zlv8&v^(S}`x$yI>_7hKaM%QvF!F~~4JOLN& zt8eH@M7N(M)IJW%9Z%KX&)HH$_e6d6vxLNx6y3h3)C5V(_=f!)z4lQ#4tdIc!=d&r za(6tXrc4^lr~JqgBKtXd&yP5z?jSW7(LFi$+28xrcY?Klyr%4zJR?6&$ZBf0!M)Fq z99=!34X!Ca@+mdn+@PoY$fwkNbAvg$I!oBRZu*#!rwhH*FEArMpfWM_~ zhaUk&T|{V5&Qof}yyaZZene3>hFgxk_8q0B0sjuY#~!2Y&%XLrjFykl_Djg>NBOlJ ndaXMu^ds`7_ILBzKg7g&>hUZ0e@VFdQgJoAe(}v8dr&a22Co0N diff --git a/CPLD/MAXV/output_files/RAM2GS.asm.rpt b/CPLD/MAXV/output_files/RAM2GS.asm.rpt index 820df5d..37465bc 100644 --- a/CPLD/MAXV/output_files/RAM2GS.asm.rpt +++ b/CPLD/MAXV/output_files/RAM2GS.asm.rpt @@ -1,5 +1,5 @@ Assembler report for RAM2GS -Sun Aug 13 04:50:03 2023 +Sun Aug 13 06:36:30 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Sun Aug 13 04:50:03 2023 ; +; Assembler Status ; Successful - Sun Aug 13 06:36:30 2023 ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; ; Family ; MAX V ; @@ -67,8 +67,8 @@ https://fpgasoftware.intel.com/eula. +----------------+--------------------------------------------------------------------------------+ ; Option ; Setting ; +----------------+--------------------------------------------------------------------------------+ -; JTAG usercode ; 0x0017116A ; -; Checksum ; 0x001714EA ; +; JTAG usercode ; 0x00174FF3 ; +; Checksum ; 0x001751E3 ; +----------------+--------------------------------------------------------------------------------+ @@ -78,15 +78,15 @@ https://fpgasoftware.intel.com/eula. Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Sun Aug 13 04:50:02 2023 + Info: Processing started: Sun Aug 13 06:36:30 2023 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 1 warning - Info: Peak virtual memory: 4662 megabytes - Info: Processing ended: Sun Aug 13 04:50:03 2023 - Info: Elapsed time: 00:00:01 - Info: Total CPU time (on all processors): 00:00:00 + Info: Peak virtual memory: 4663 megabytes + Info: Processing ended: Sun Aug 13 06:36:30 2023 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:01 diff --git a/CPLD/MAXV/output_files/RAM2GS.done b/CPLD/MAXV/output_files/RAM2GS.done index a58a91f..096fda1 100644 --- a/CPLD/MAXV/output_files/RAM2GS.done +++ b/CPLD/MAXV/output_files/RAM2GS.done @@ -1 +1 @@ -Sun Aug 13 04:50:06 2023 +Sun Aug 13 06:36:33 2023 diff --git a/CPLD/MAXV/output_files/RAM2GS.fit.rpt b/CPLD/MAXV/output_files/RAM2GS.fit.rpt index bcc8b06..675e69b 100644 --- a/CPLD/MAXV/output_files/RAM2GS.fit.rpt +++ b/CPLD/MAXV/output_files/RAM2GS.fit.rpt @@ -1,5 +1,5 @@ Fitter report for RAM2GS -Sun Aug 13 04:50:01 2023 +Sun Aug 13 06:36:29 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -59,7 +59,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------+ ; Fitter Summary ; +-----------------------+---------------------------------------------+ -; Fitter Status ; Successful - Sun Aug 13 04:50:01 2023 ; +; Fitter Status ; Successful - Sun Aug 13 06:36:29 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; @@ -135,8 +135,8 @@ https://fpgasoftware.intel.com/eula. ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 1.5% ; -; Processors 3-4 ; 1.4% ; +; Processor 2 ; 1.6% ; +; Processors 3-4 ; 1.3% ; +----------------------------+-------------+ @@ -157,9 +157,9 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/o ; -- Combinational with a register ; 77 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 56 ; -; -- 3 input functions ; 48 ; -; -- 2 input functions ; 41 ; +; -- 4 input functions ; 57 ; +; -- 3 input functions ; 46 ; +; -- 2 input functions ; 42 ; ; -- 1 input functions ; 8 ; ; -- 0 input functions ; 1 ; ; ; ; @@ -168,11 +168,11 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/o ; -- arithmetic mode ; 16 ; ; -- qfbk mode ; 7 ; ; -- register cascade mode ; 0 ; -; -- synchronous clear/load mode ; 23 ; +; -- synchronous clear/load mode ; 22 ; ; -- asynchronous clear/load mode ; 0 ; ; ; ; ; Total registers ; 98 / 240 ( 41 % ) ; -; Total LABs ; 23 / 24 ( 96 % ) ; +; Total LABs ; 24 / 24 ( 100 % ) ; ; Logic elements in carry chains ; 17 ; ; Virtual pins ; 0 ; ; I/O pins ; 63 / 79 ( 80 % ) ; @@ -186,8 +186,8 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/o ; Global signals ; 4 ; ; -- Global clocks ; 4 / 4 ( 100 % ) ; ; JTAGs ; 0 / 1 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 26.0% / 29.1% / 22.8% ; -; Peak interconnect usage (total/H/V) ; 26.0% / 29.1% / 22.8% ; +; Average interconnect usage (total/H/V) ; 23.8% / 26.3% / 21.1% ; +; Peak interconnect usage (total/H/V) ; 23.8% / 26.3% / 21.1% ; ; Maximum fan-out ; 55 ; ; Highest non-global fan-out ; 41 ; ; Total fan-out ; 661 ; @@ -204,20 +204,20 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/o ; CROW[1] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; Din[0] ; 42 ; 1 ; 5 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; Din[1] ; 36 ; 1 ; 4 ; 0 ; 2 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[2] ; 35 ; 1 ; 3 ; 0 ; 0 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[3] ; 37 ; 1 ; 4 ; 0 ; 1 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[4] ; 39 ; 1 ; 5 ; 0 ; 3 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[5] ; 38 ; 1 ; 4 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[2] ; 35 ; 1 ; 3 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[3] ; 37 ; 1 ; 4 ; 0 ; 1 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[4] ; 39 ; 1 ; 5 ; 0 ; 3 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[5] ; 38 ; 1 ; 4 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; Din[6] ; 41 ; 1 ; 5 ; 0 ; 1 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; Din[7] ; 40 ; 1 ; 5 ; 0 ; 2 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; MAin[0] ; 49 ; 1 ; 7 ; 0 ; 2 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; MAin[1] ; 51 ; 1 ; 7 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[0] ; 49 ; 1 ; 7 ; 0 ; 2 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[1] ; 51 ; 1 ; 7 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[2] ; 50 ; 1 ; 7 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[3] ; 71 ; 2 ; 8 ; 4 ; 3 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[4] ; 70 ; 2 ; 8 ; 4 ; 4 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[5] ; 69 ; 2 ; 8 ; 3 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; MAin[6] ; 72 ; 2 ; 8 ; 4 ; 2 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; MAin[7] ; 68 ; 2 ; 8 ; 3 ; 1 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[6] ; 72 ; 2 ; 8 ; 4 ; 2 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[7] ; 68 ; 2 ; 8 ; 3 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[8] ; 73 ; 2 ; 8 ; 4 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[9] ; 74 ; 2 ; 8 ; 4 ; 0 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; PHI2 ; 52 ; 2 ; 8 ; 1 ; 4 ; 22 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; @@ -242,11 +242,11 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/o ; Dout[6] ; 34 ; 1 ; 3 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; Dout[7] ; 43 ; 1 ; 6 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; LED ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; - ; - ; +; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; -; RA[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; - ; - ; -; RA[2] ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; - ; - ; +; RA[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; +; RA[2] ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[4] ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[5] ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; @@ -256,13 +256,13 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/o ; RA[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RBA[0] ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; ; RBA[1] ; 14 ; 1 ; 1 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; RCKE ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; RCKE ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; ; RDQMH ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RDQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; nRCAS ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; nRCS ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; ; nRRAS ; 6 ; 1 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; nRWE ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; nRWE ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ @@ -272,11 +272,11 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/o ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ ; RD[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; -; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; +; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; comb~0 ; - ; ; RD[2] ; 89 ; 2 ; 4 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; ; RD[3] ; 99 ; 2 ; 2 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; ; RD[4] ; 92 ; 2 ; 3 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; -; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; +; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; comb~0 ; - ; ; RD[6] ; 95 ; 2 ; 3 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; ; RD[7] ; 97 ; 2 ; 3 ; 5 ; 3 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ @@ -494,8 +494,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Din[6] ; Input ; (1) ; ; nFWE ; Input ; (1) ; ; Din[0] ; Input ; (1) ; -; Din[1] ; Input ; (1) ; ; Din[7] ; Input ; (1) ; +; Din[1] ; Input ; (1) ; ; Din[4] ; Input ; (1) ; ; Din[2] ; Input ; (1) ; ; Din[3] ; Input ; (1) ; @@ -508,14 +508,14 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +------------+-------------+---------+-------------------------+--------+----------------------+------------------+ ; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; +------------+-------------+---------+-------------------------+--------+----------------------+------------------+ -; CmdDRDIn~2 ; LC_X6_Y2_N0 ; 4 ; Clock enable ; no ; -- ; -- ; -; CmdLEDEN~1 ; LC_X6_Y2_N9 ; 3 ; Clock enable ; no ; -- ; -- ; +; CmdDRDIn~1 ; LC_X5_Y4_N7 ; 4 ; Clock enable ; no ; -- ; -- ; +; CmdLEDEN~1 ; LC_X5_Y4_N5 ; 3 ; Clock enable ; no ; -- ; -- ; ; DRDIn~1 ; LC_X5_Y1_N3 ; 2 ; Clock enable ; no ; -- ; -- ; ; PHI2 ; PIN_52 ; 22 ; Clock ; yes ; Global Clock ; GCLK1 ; ; RCLK ; PIN_12 ; 55 ; Clock ; yes ; Global Clock ; GCLK0 ; -; Ready ; LC_X3_Y3_N8 ; 40 ; Sync. clear, Sync. load ; no ; -- ; -- ; -; always8~7 ; LC_X5_Y2_N6 ; 3 ; Clock enable ; no ; -- ; -- ; -; comb~0 ; LC_X5_Y4_N1 ; 8 ; Output enable ; no ; -- ; -- ; +; Ready ; LC_X5_Y2_N1 ; 40 ; Sync. clear, Sync. load ; no ; -- ; -- ; +; always8~6 ; LC_X6_Y4_N7 ; 3 ; Clock enable ; no ; -- ; -- ; +; comb~0 ; LC_X3_Y4_N9 ; 8 ; Output enable ; no ; -- ; -- ; ; nCCAS ; PIN_53 ; 11 ; Clock ; yes ; Global Clock ; GCLK2 ; ; nCRAS ; PIN_67 ; 16 ; Clock ; yes ; Global Clock ; GCLK3 ; +------------+-------------+---------+-------------------------+--------+----------------------+------------------+ @@ -538,113 +538,111 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------------+--------------------+ ; Routing Resource Type ; Usage ; +-----------------------+--------------------+ -; C4s ; 144 / 784 ( 18 % ) ; -; Direct links ; 51 / 888 ( 6 % ) ; +; C4s ; 145 / 784 ( 18 % ) ; +; Direct links ; 52 / 888 ( 6 % ) ; ; Global clocks ; 4 / 4 ( 100 % ) ; -; LAB clocks ; 17 / 32 ( 53 % ) ; -; LUT chains ; 18 / 216 ( 8 % ) ; -; Local interconnects ; 286 / 888 ( 32 % ) ; -; R4s ; 167 / 704 ( 24 % ) ; +; LAB clocks ; 15 / 32 ( 47 % ) ; +; LUT chains ; 17 / 216 ( 8 % ) ; +; Local interconnects ; 281 / 888 ( 32 % ) ; +; R4s ; 153 / 704 ( 22 % ) ; +-----------------------+--------------------+ +---------------------------------------------------------------------------+ ; LAB Logic Elements ; +--------------------------------------------+------------------------------+ -; Number of Logic Elements (Average = 7.61) ; Number of LABs (Total = 23) ; +; Number of Logic Elements (Average = 7.29) ; Number of LABs (Total = 24) ; +--------------------------------------------+------------------------------+ -; 1 ; 2 ; -; 2 ; 1 ; -; 3 ; 1 ; -; 4 ; 2 ; -; 5 ; 0 ; -; 6 ; 2 ; -; 7 ; 0 ; +; 1 ; 1 ; +; 2 ; 2 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 2 ; +; 6 ; 3 ; +; 7 ; 4 ; ; 8 ; 1 ; -; 9 ; 0 ; -; 10 ; 14 ; +; 9 ; 4 ; +; 10 ; 7 ; +--------------------------------------------+------------------------------+ +-------------------------------------------------------------------+ ; LAB-wide Signals ; +------------------------------------+------------------------------+ -; LAB-wide Signals (Average = 1.39) ; Number of LABs (Total = 23) ; +; LAB-wide Signals (Average = 1.50) ; Number of LABs (Total = 24) ; +------------------------------------+------------------------------+ -; 1 Clock ; 13 ; -; 1 Clock enable ; 4 ; -; 1 Sync. clear ; 4 ; -; 1 Sync. load ; 2 ; -; 2 Clocks ; 9 ; +; 1 Clock ; 17 ; +; 1 Clock enable ; 6 ; +; 1 Sync. clear ; 3 ; +; 1 Sync. load ; 3 ; +; 2 Clocks ; 7 ; +------------------------------------+------------------------------+ +----------------------------------------------------------------------------+ ; LAB Signals Sourced ; +---------------------------------------------+------------------------------+ -; Number of Signals Sourced (Average = 7.87) ; Number of LABs (Total = 23) ; +; Number of Signals Sourced (Average = 7.54) ; Number of LABs (Total = 24) ; +---------------------------------------------+------------------------------+ ; 0 ; 0 ; -; 1 ; 2 ; -; 2 ; 1 ; -; 3 ; 1 ; -; 4 ; 2 ; -; 5 ; 0 ; -; 6 ; 2 ; -; 7 ; 0 ; +; 1 ; 1 ; +; 2 ; 2 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 2 ; +; 6 ; 3 ; +; 7 ; 3 ; ; 8 ; 1 ; -; 9 ; 0 ; -; 10 ; 10 ; +; 9 ; 3 ; +; 10 ; 7 ; ; 11 ; 2 ; -; 12 ; 2 ; +---------------------------------------------+------------------------------+ +--------------------------------------------------------------------------------+ ; LAB Signals Sourced Out ; +-------------------------------------------------+------------------------------+ -; Number of Signals Sourced Out (Average = 5.57) ; Number of LABs (Total = 23) ; +; Number of Signals Sourced Out (Average = 4.96) ; Number of LABs (Total = 24) ; +-------------------------------------------------+------------------------------+ ; 0 ; 0 ; -; 1 ; 2 ; -; 2 ; 2 ; -; 3 ; 3 ; -; 4 ; 3 ; -; 5 ; 1 ; +; 1 ; 1 ; +; 2 ; 3 ; +; 3 ; 6 ; +; 4 ; 1 ; +; 5 ; 2 ; ; 6 ; 3 ; -; 7 ; 2 ; -; 8 ; 2 ; -; 9 ; 2 ; -; 10 ; 3 ; +; 7 ; 5 ; +; 8 ; 1 ; +; 9 ; 1 ; +; 10 ; 1 ; +-------------------------------------------------+------------------------------+ -+-----------------------------------------------------------------------------+ -; LAB Distinct Inputs ; -+----------------------------------------------+------------------------------+ -; Number of Distinct Inputs (Average = 10.52) ; Number of LABs (Total = 23) ; -+----------------------------------------------+------------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 2 ; -; 3 ; 1 ; -; 4 ; 0 ; -; 5 ; 3 ; -; 6 ; 0 ; -; 7 ; 1 ; -; 8 ; 1 ; -; 9 ; 2 ; -; 10 ; 0 ; -; 11 ; 1 ; -; 12 ; 1 ; -; 13 ; 4 ; -; 14 ; 3 ; -; 15 ; 0 ; -; 16 ; 1 ; -; 17 ; 1 ; -; 18 ; 1 ; -; 19 ; 1 ; -+----------------------------------------------+------------------------------+ ++----------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+------------------------------+ +; Number of Distinct Inputs (Average = 9.42) ; Number of LABs (Total = 24) ; ++---------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 1 ; +; 3 ; 2 ; +; 4 ; 0 ; +; 5 ; 1 ; +; 6 ; 1 ; +; 7 ; 2 ; +; 8 ; 2 ; +; 9 ; 1 ; +; 10 ; 3 ; +; 11 ; 2 ; +; 12 ; 2 ; +; 13 ; 2 ; +; 14 ; 1 ; +; 15 ; 0 ; +; 16 ; 1 ; +; 17 ; 1 ; +; 18 ; 1 ; ++---------------------------------------------+------------------------------+ +-------------------------------------------------------------------------+ @@ -666,7 +664,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------+----------------------+-------------------+ ; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; +-----------------+----------------------+-------------------+ -; I/O ; nCRAS ; 2.2 ; +; I/O ; nCRAS ; 2.6 ; ; I/O ; RCLK ; 1.9 ; +-----------------+----------------------+-------------------+ Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. @@ -678,7 +676,7 @@ This will disable optimization of problematic paths and expose them for further +-----------------+----------------------+-------------------+ ; Source Register ; Destination Register ; Delay Added in ns ; +-----------------+----------------------+-------------------+ -; nCCAS ; CBR ; 2.167 ; +; nCCAS ; CBR ; 2.632 ; ; PHI2 ; PHI2r ; 0.871 ; ; nCRAS ; RASr ; 0.519 ; +-----------------+----------------------+-------------------+ @@ -731,7 +729,7 @@ Info (176234): Starting register packing Info (186468): Started processing fast register assignments Info (186469): Finished processing fast register assignments Info (176235): Finished register packing -Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. Info (170189): Fitter placement preparation operations beginning Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 @@ -739,20 +737,20 @@ Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 Info (170193): Fitter routing operations beginning -Info (170195): Router estimated average interconnect usage is 20% of the available device resources - Info (170196): Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 +Info (170195): Router estimated average interconnect usage is 18% of the available device resources + Info (170196): Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 -Info (11888): Total time spent on timing analysis during the Fitter is 0.22 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 0.26 seconds. Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. Info (144001): Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg Info: Quartus Prime Fitter was successful. 0 errors, 4 warnings - Info: Peak virtual memory: 5345 megabytes - Info: Processing ended: Sun Aug 13 04:50:01 2023 - Info: Elapsed time: 00:00:01 - Info: Total CPU time (on all processors): 00:00:02 + Info: Peak virtual memory: 5346 megabytes + Info: Processing ended: Sun Aug 13 06:36:29 2023 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:03 +----------------------------+ diff --git a/CPLD/MAXV/output_files/RAM2GS.fit.summary b/CPLD/MAXV/output_files/RAM2GS.fit.summary index 256cb2c..f3260e4 100644 --- a/CPLD/MAXV/output_files/RAM2GS.fit.summary +++ b/CPLD/MAXV/output_files/RAM2GS.fit.summary @@ -1,4 +1,4 @@ -Fitter Status : Successful - Sun Aug 13 04:50:01 2023 +Fitter Status : Successful - Sun Aug 13 06:36:29 2023 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition Revision Name : RAM2GS Top-level Entity Name : RAM2GS diff --git a/CPLD/MAXV/output_files/RAM2GS.flow.rpt b/CPLD/MAXV/output_files/RAM2GS.flow.rpt index ecfb508..f7a0da0 100644 --- a/CPLD/MAXV/output_files/RAM2GS.flow.rpt +++ b/CPLD/MAXV/output_files/RAM2GS.flow.rpt @@ -1,5 +1,5 @@ Flow report for RAM2GS -Sun Aug 13 04:50:05 2023 +Sun Aug 13 06:36:32 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------+ ; Flow Summary ; +-----------------------+---------------------------------------------+ -; Flow Status ; Successful - Sun Aug 13 04:50:03 2023 ; +; Flow Status ; Successful - Sun Aug 13 06:36:30 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; @@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 08/13/2023 04:49:50 ; +; Start date & time ; 08/13/2023 06:36:15 ; ; Main task ; Compilation ; ; Revision Name ; RAM2GS ; +-------------------+---------------------+ @@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula. +-------------------------------+---------------------------------+---------------+-------------+------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +-------------------------------+---------------------------------+---------------+-------------+------------+ -; COMPILER_SIGNATURE_ID ; 207120313862967.169191659008924 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 207120313862967.169192297509168 ; -- ; -- ; -- ; ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; ; POWER_PRESET_COOLING_SOLUTION ; No Heat Sink With Still Air ; -- ; -- ; -- ; @@ -84,11 +84,11 @@ https://fpgasoftware.intel.com/eula. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:09 ; 1.0 ; 4702 MB ; 00:00:22 ; -; Fitter ; 00:00:01 ; 1.0 ; 5345 MB ; 00:00:02 ; -; Assembler ; 00:00:01 ; 1.0 ; 4662 MB ; 00:00:00 ; +; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 4702 MB ; 00:00:26 ; +; Fitter ; 00:00:02 ; 1.0 ; 5346 MB ; 00:00:03 ; +; Assembler ; 00:00:00 ; 1.0 ; 4662 MB ; 00:00:00 ; ; Timing Analyzer ; 00:00:01 ; 1.0 ; 4676 MB ; 00:00:01 ; -; Total ; 00:00:12 ; -- ; -- ; 00:00:25 ; +; Total ; 00:00:14 ; -- ; -- ; 00:00:30 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/CPLD/MAXV/output_files/RAM2GS.map.rpt b/CPLD/MAXV/output_files/RAM2GS.map.rpt index 3f94942..1b86fa9 100644 --- a/CPLD/MAXV/output_files/RAM2GS.map.rpt +++ b/CPLD/MAXV/output_files/RAM2GS.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for RAM2GS -Sun Aug 13 04:49:59 2023 +Sun Aug 13 06:36:26 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -46,7 +46,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+---------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Sun Aug 13 04:49:59 2023 ; +; Analysis & Synthesis Status ; Successful - Sun Aug 13 06:36:26 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; @@ -167,9 +167,9 @@ https://fpgasoftware.intel.com/eula. ; -- Combinational with a register ; 68 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 56 ; -; -- 3 input functions ; 48 ; -; -- 2 input functions ; 41 ; +; -- 4 input functions ; 57 ; +; -- 3 input functions ; 46 ; +; -- 2 input functions ; 42 ; ; -- 1 input functions ; 8 ; ; -- 0 input functions ; 1 ; ; ; ; @@ -270,7 +270,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Sun Aug 13 04:49:50 2023 + Info: Processing started: Sun Aug 13 06:36:15 2023 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected @@ -302,9 +302,9 @@ Info (21057): Implemented 248 device resources after synthesis - the final resou Info (144001): Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings Info: Peak virtual memory: 4702 megabytes - Info: Processing ended: Sun Aug 13 04:49:59 2023 - Info: Elapsed time: 00:00:09 - Info: Total CPU time (on all processors): 00:00:22 + Info: Processing ended: Sun Aug 13 06:36:26 2023 + Info: Elapsed time: 00:00:11 + Info: Total CPU time (on all processors): 00:00:27 +------------------------------------------+ diff --git a/CPLD/MAXV/output_files/RAM2GS.map.summary b/CPLD/MAXV/output_files/RAM2GS.map.summary index 27c7401..6ae3a75 100644 --- a/CPLD/MAXV/output_files/RAM2GS.map.summary +++ b/CPLD/MAXV/output_files/RAM2GS.map.summary @@ -1,4 +1,4 @@ -Analysis & Synthesis Status : Successful - Sun Aug 13 04:49:59 2023 +Analysis & Synthesis Status : Successful - Sun Aug 13 06:36:26 2023 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition Revision Name : RAM2GS Top-level Entity Name : RAM2GS diff --git a/CPLD/MAXV/output_files/RAM2GS.pof b/CPLD/MAXV/output_files/RAM2GS.pof index e4b2cb7fe430708264dd379380ba6480bd258059..795da91680f2f4c66c6b54ce468739ac2874237a 100644 GIT binary patch literal 7861 zcmeHMZ*W}Ibzfr>!vxzfj6*0R(DVb752>+nVh1$xk~+Yobs$X(q-j*w4wm8sOF{ml zcwqOE$=E=fkZBp1C?IR-jNCAZyzO{w#cXz;6UH_Wtv3IRLhRk^6ub+FeNRN$_q2O; z@9FQ{`&P1treFIZNV9wQo&i2pt zZ{M*E?|nV}TXyW&*57{bw*H;l`+D2g+_GxTs@3g(xqJHq_qVTGzq)<(EjQhK^G!Fe zUUN(P-~LtmrtQ17wcmdK_Fa%oT#{G@$d7;K=8vuZ!r!e~y?W!v5{na;gLF^tuI;-X z*mi&7QpoV%Rf#M9%zogvpR-AZh;(wedVomO_Zl)(tQM+7=HUZH4W8u(BDBxu%B5k73P#HMBn8ziey3nA8q;*l{DT;E^IDJ8ustNW{ z6u2?aI*JzXp|1t(6^@^WY!3cA|5zXR(9W}*9@B=T(!ifzzb_T(hoEm@A4T9pjs!G# zWV`K{xqz;L-=g#A*FA#$b(S}nM;GXk3Fb&gs*f3(0>(Gc=P9MK4P{`j#=j}@`e4X_ zTK3f_sF{H=(kh78gB+29obn;7si|6inxJKG0KNe(QCBwb4gC`OpvaidqesN~G1B}; z*da|9bj#Q&XE&rZWsZW+egUUN$9gDI~(>!u4oD?)EB=Kp6yQ^VS?=@I|cfoi36_Ss^0cXH>@ zyMu!hYu8Q<4GzH)_J91HgIjz3!o>2^6TSJ4(#Q+hayGkh^w=?{FSFXHNNAmm>y+(} z{8~V<{$w)@D6O?5lf=F@DcF-nym{9wz6p$ss08UW`-_*My;PDl%SXL4j?e%!o}!ZC zexx`*t^cR#ZQu*o$@_u*H58kN{wu3*qzt+OmB~Z4tI1J=Jk>K{BshK|txSaNq=Vq^*e!vN^=iPyg20bV zCPR8|%<8*-sf3n+@NFC*hc>05^EC9aE0XO@p?6}ObaBs-_ADIuXB093`)+6hdSZ?H zqKHE5Gbqp(r70sCq&L?CpG1K8N9iYrqm=2l{2J!vs-(66eIm-b^FfE`zr)h)>)Tl0 z(0TJpa>Ek_>yrulcDyt6Jnt7#?ntqif984WyyB;)%vCS_Fg4r1D@-hjmYus{)dBEJ zFUU#L_I>JH@zbA~MK7J*w|Az#Jdvn>{Es7P#s92VKshFN!akg!?@5?6_wX3$-#V+sE`1t;wJ(a@AZv}hy zTtASTDV6*+>rV|04hOb=$)9-orHa3;_r?>IHx8^_`P^fV-Er*6jepT`%<893my~%3 zagwDdEo{6IzckfKa=^xqJVaM_XfHw>_+0G+7uDjq_~z8xSwk60QJMBkvOehdMwC;B zLE-s-^kDy`t1dFgQ|q^tW4?{7rrepVjW7BPBy`%!OPo{CxfgppukQ)r z>|}dnP{&)V|1*7*@}Qrgl%$~SvE>6f*oE$^GgePTJUV=IksYYDJY^T~h4Zt9e9E)E zc$vO4oKL`YbDwbjA(|nduMj}~DjqD~!-pV4yCIvOv}`g{DWxNqKP^9Ms1l#Jjv=3$ z0)EQkqimobuZugB<)@>J4un?*PlIVB(Qa9$GFHX?MdSmDayjUMkACDczl2FIf`EF9 z4EMVz>+~TLQV{4q^ef0%d=GvAp7WpU3S@(Go{ZEbTYq6-bdz^9mS?+;7z*#>e#aVQ zN_ne?yukV%i2@F+a0~L8ijjGC%+Fof8SB@`KP4jl3JlFlS*Ld?-ABi|sCloeKlTIp zlzf#o$XO0Ah0$xI18Ma~>xtu)Z}xPb*!XhPz3k2Nso8%*{XH`M?Z&l-US<26;GgK} zzVx=2)dwzp^ZdTOTmG>8l1HZ7ese9mOF07n(Vj|SJf!rcpa0xG`q#&oU%BL5+jXC? z`YB`i&<|<?%Q*iw zJNw7S5B_&|<@`IFPIsSN_2(;}`?tsL7(DjZt@AHsvdUyR&ghFtjwj+KL{yMP>mU5B z`y@f1#Epsh6op?!et9mw+STWooQM2^L+%{-g2^@A`Q!McQr=WcKM3zboIn$f2+Ey&iOw^(YcF zA8~yyI>j)FtYJs1eI) zz7Jxa;ryy&+ju8157M^(O?d_((8zR_Kacwg0_L&ZK7`=5J#Vp}R(~b&`Pc_K?*EeQ z_9!$y_ow?@{BaJ)@x)xC?xmpt$P0@Pd1Z+4(Zpt)9igg$-}1i-{@wgMros}huTB{X zvcR|cU337?Q>>>cjROOC9i~2uu_LZO74D%i5AiEcbWmLfcj7tfn$Y$EtTA%ylElF; z-S)Jmhoc(>&V4$xGMsJyd5s>o^;1tK5|y6Beob?9<5KX&2>8>}nl88TAH6kkrLp|u zEA|VcG%c-$dJ*`6jgL+y7K8tUCh$LG`B#T}dPXB=Za+TV{c6vh6NT}8eE(cO^poLd zCU&;JJ~Wt%?G*BiGB&P#9IY1rEATp~*9M5n*|!=%h+k-@|b+fA4cRVxc~eXI#H@6j6%xFq+60tvZsZODA7~oXuYk zb;CCZ%#nBSOKRTu1$};Ev3&@9fpdm}qu?^XjMs>LuEKLSqtpU=eUIysnq}-bo+Iq@(LG?9vC&Wm%1aYHgZk75`1w^$U35=r z01IxDmdF1!T#5)lJ9T8$C3V8q$Tf*@=~4br&bMQ5bGm8bCnM+s%X0N(KHUL##>iZ zmecgFFMs2@L*D}*`!!ctmZ&sdJoPUhNX>pE^_ykP|HH~RuCo3;&-&NgR%zUQ@;h7C znS^d!d+vH_s9RKLt3O-52ETjVY@$Jbe{Q+uuhDM!rch?EW{%e`o(Iy_L7Rm!EiLQ~p@#xgQ-aXAgh+@xxE*vhxq$5ZE}`zSyWv zSictPPuV&yA--iJ0^9$weh#|qzugyD(TE~M-=J>Q9z#+i?jG~uzs;{2Nomq8`PRPJ z{yk>TFUaP}lel>rLv>Y(@lkIP?nj*0c0J&Nzo3sf8HojXL~Ys;x#8w^R8HR3l>pt? zx`@vY^jq@1z;pTZzvJ%I@1FpZt^b7D>^~?3tTF=!r@U8wmRCV_U z*LSjYmCcq(a;eEUP9iPW<6Lq2DGCPC_}rSK&V55U%$@%Qh@oX%!1q)rgAm`xAwS6L zjPs$T-$gUMO*4#qvHGeu7d>^z>EGw_yExe z7yJx%#fhyH41>>kaD3UuWkYepj{oWZ~?$aQ{$Gs$$LPu7`QHa{MlRt0G5Pn>TkE_( qUc7(*U-9^G;)*5nzX-MSFGBDC{pm&k&HeqqKk*1$W`8SQHSjj!-YK8gSiqAhd@W9^v2llmZ z-@9w~PJ9jy?0sPO?wxzv|8VEteY*ztw6EWI^ZJ`R+JEQ3u7@9N|6*51d&kCgx7@Ps zmX7rs+wcDU_B(g&-`Rf0gS+-aHuX!Xl~B21>n*o-{P9=UcXVvIHFaI;S3tUF&;DKe zAKv+3Y8hnswK{eEP38-KoMo3Z5vlZ8d6Y=h9@V62x_qWgq#qldR^S=FPr{5rz;idE zE5)P7c#=b)Yc)<|Qwuy#U)1E2+IKO+5d~T@o#>znsG_@A4_UPZsvA7OZp1hGv~T!I z_%U8abI9rtcyfImu)Ip>q47_G4~8NEx=+?z>^Di)BURwT-b|=e=xVaakt7!F8*PlQ zQ4PY{h5jlf{zZ7g+~^Obu@@$Iwg>r;{dU7z2t3)WKca&NzEU|JYp{fTuzW<1Mo=n& z9@H9g@SXYgQa-*{cy8>QyaXS>4^pTGbWT&K6aCHy@S#vH@Izsw*SBCdRFNMuH67F| zN{|n5sK^Qmgb_K8_`}G9_Kjbz20zpppXCz1-_SH?nfR(kzt8zqfimlItQiJ%`l(Vu zgNncaC$-D#L^;?&MqC$mBK<(H-t&ds(>>%!zekVquG0=`3YQq$}k7KL#<&?Ai>@mvewN%^1))Cs=BVlx_9uGXe$ve^56 zCAWu^0A1A6Rf^V`*JU=;uB_JRO?sso`CoLG>i7IQyZbu&M?imw_!Vz88X$wkk@T*nTpq%Nafcf9}``X#dM-IPZ_~{!M*PvO$_s*O- zA9znVlTZ2m1Dp0`e=;&M)!BJ5n;nVsGkN*Buk9&qox1*Cww3;=+j;S1_f+@9?;W4W zOM`z8afBj|aN@ewg!=HYTycFN@4oCoyguSbzN(?_qtKC2{EF0@S_~qybvi#ii+poj zfl_l(f7gs2>4Hvrkn1G~F^1}8B98wYg@N|{VeCjQ>L2)Moo(=#?+^{MpYX@mF4vi| zG`VDlZXBQ4*FYuVL9wD~#Bo&**M*)zUurHi8)4*p56&pcC-`yJ??@W+qz^yCuugMi zLk1A4Oz>zUKHgtRfV{6rE~%N{W|h!GkjEI1UxzIf3M%M)7}YWGni^UN^n1K7QrO%< z4YDP+1ICTBeuorR0C?6P)YTZN%B0b6*X}KQz9keQ&#-*xN=-uBj>?(-kP3P{_|1Ay zzXEaQ5x?it3D7D{lb>lP*_RQY_H=-J=AH%Lrrh&7_<=@Zc)tuSs_OdC06DIt0{BKB zeCp-=W9}#^;fGS*CBbv7vZ*7hZwKw@64HWL(KU2HO=oYwDA}cT-ZY#u4r1A0;K{jeh5w zE35i9HkDSM+R~M||F+Jyh199TD^}CWzc{pR6!t5$d7qa}pI>?E)$aZj_}_T^)ZwAk zS3a3~!o+87XuaY+IacnOoK9!@H+8nnUpMNldiwpgHHX#}*?)TMZEwZVyY9GtI^DmV z`7NU!J^g<6R}UHcww~N}c%Z+&^{r1&_Yb8zvu9Udm|ESL%l`F9)L)iYdiF<`-+d4L z*AM;KV<$&OCnmOhq5E$o;v@?ubahB76mwI%VoL?lT1d>dwdDdlJh_ zBy|9NFC_IUT}^?Db&o+7T+%8R7H8Gmyh>#P!1q-He!31ezI3RE>zG#ricq6m)2k*e{~>sc76A z;F;m$$g?0;WvQrM?2*52W|l}<_C5? zS2^z}+&d=ZnzB}nmPpM^dYT4YDZ?DPT)zP+aW6SAO$Ca&XpEz-z{o9afDJ=uP zYw~EuYVBxy>{F@J*L7U!ZFxd7KAYaYslN8zQ!8&=5dB{Re;)jguYX&$r6PR#>E)#r z;J<%LthwoiTMfUXqiU~D8N3QFJEsThr=7{an(pu4_K1C@_bqSzBd=yR9_=&!i_+w? zuaz!u{Z{K8pZo0X-Pz;c8JU{s{>oDm-BEsU=lIren)8Tr1NUC+j&)HEDlY1j{l^>Y zrEH0D*37@|VX2)w(=pc>#|s9rzc-QpJnaTe(+4T_5%gU zIDfoOHDi~AYlo8QA-1T5kCE{__kp6B0?sN$|7q6uy(ZIL_-puM$R8CjQI^bceH|cS zX+h^e!u`N*+On6tpbY$+(GR@u`7;Xl5DprC4?1-r#+4+4|D>36wF|n*0~MkFrA)|k z5!b(dRQrzwR)GDN81Itj@7C%}RR2&Jcvu78AL}H^hK!a9_ithBD{|AgfAV^{NPa;r zbe-ElX;OCH@Oy>4P;!UAUmGXLJruUlZ2m;G5~|m&*nX{~2gY&Z4}2}<8RRXa*Sz_% z3OtjaV<+1e^lxrYS&i3MtjVrQSw9c44IYa93(7yQQ`HTD(#(3u+AUv-@9k%L2P!|WSJN2ab&Ntk*koN+iQA63q9f#*n$#|^0?*$U;5l9{S@*F9t^ITt1 z-_$5CwH!wOy1-kYOQ4%%<1mc&KddL$E9@3wgzd22t0T@gVa^TE7f>JY5A3UaJaDnR zAbHTmeFPW92=7wS=s}!<`y=4ufL;@KT<@_R5z=mngUP2k#KXrgnR~6l8-HBTU4Fji zeH!{XA9{)ZvA+U*H)HJMt{VA)QG|W0-s50C46=uxu#Tz4@ZmY8Nyry2))fv!W z*DV=6hA)*k;{ykJcX|mO`H@r)=}DE|yrQ(Cl^*w(Z)Uwe@6)-z!&oEm6_p$5Qy*jg zviW73Z(#abZQ}bb@bK@+hWO!;*Vf(!e#`xc&u^r4F0vQ#l{mF(YQ=5TGT-u_?kq6Iv_L4XC^F4c>xwNg2&%XHm zkzzjomG2(Sn|0v)HO+qK;QSk=|Dd8-C*Hj|4&*^5JXbb87;oyM59_Pmlf|A;USPT;vRRMeOM&OLrTs$MC9*`shkYZ*V-fG@ zoZ*pN#$%t3`b)x3A($S^%LJG3<2j#G2JiFv0emu-#cSgeKE^WQHT%pGJBhvM{If%z z3+}%qIAf3LW@E@i_OHQr61(JO3p{ze~a>J*cF8(`WNxWFXKnj-v)nA zr1vTw&)Wr@l$>9#pC$GZfB!dn#CK6o*TSK|^G9=lnDw3_jPvD&^9rPJ?gg;2j4DbV}|c*8JLe zJhJmW$>0+^OZb0uKH|sun4IMPJM$LbKk@s^m67aJXID8pG7|Gm|9O?Eo6mV(q1!oj z`^Z%Or7g$v`Iry;>_7G(lLtKi9fUvdf05q=R}EqR426#S3;Sh~w?Jre$wF?E`yp

      gWheuud-Hx-u1n&;-IHg zS#MD=V1i7*MdK%Ex7S%R9jj5mgLiM4Um2b0Nxh}e_Dm>mVGX@;FyTEaF!!lkf8Lkj zAM#du0S&ax+%}!IlJ!=zujWQ5%$c%}Wn)_@5T&%fF!eec<{-@nKlmpKxjYrHw#c|` zjgY3nam{`~9y5k5Zg3?$O7Mh2YQ)9$FRSHn$6LLw90d}+W?ol;3c88u6Zub&@wCg?OmYwoG{D`~?1zb!-%L(`o zVRVcNH4NJG^FcE`DJbLO%=8#ttz>GR$Dc*UJ&!?wvMFf>NVGlHTpk_;V-){JOslH_ z>VS0t-`Ro=tq>ew8HbabrD=~O?mNNLHi%DJmQqvK)O}kwh7(u&ZNoz_{)}3%vV=nW zSo}KniWJ=#pvQ{u?}ZldB1SVq}B3E)={#-a@`G9FHCtp5Zmjj<&RE{!uQ;- zgmrF@M7rn4CmF;Eg-jsWZd3uHfw}>ALbbFm9dezr2h zgH-XVwGH)wE{-*PUwy44>9~rK^n#o?Qm#|3GC9zyN>dv9w49vX6h$rS>PO!?VBb+} zpw#j@zl*D?t>8X6cprf58lYbxw?uuXMbebVC>FZM1U z1uJYF=#DYo?X9?;E@fYSfijjDvfVZU5RUN>J#Reh6wC^B67p)0k`C*No3u&LmF~`7 zu{#R7jcus_IOTndr!Hv;v;`tg`y`X(;6tgyq!A`;8v`X9u-Mf{9lye#5mQlTYvWc5 zsn^10*<>z`v*3R@nv^|b2)MiZjeNkt7gE>v5odpV@de#tL7z!+ZO$kMo~~cmDnJ_syFb1n3f)Nq1jQZoksD z`L#hsv6b)7R}43^P}fr3q7R{FuYtWH=FHWwjyPd!^t~31>@q=I<7N z61~I#<;U}twRK_X6m}{)hW@O7%Sg60K{2t#?*IXLj&qmUOPx(G^5o z@Xg2=f$ND=L$Pz{4b=$PYzmvL$AB*y%tpoLDaxCKJBH{ylX91K+Cz2LD86n;bK>I+ zhfs>slY=lylCh?Z(T4U5kHznM#<*{5JFc4gew92r>NeuKN4Ne=Yx`c}_k^n;0KgG= zvkE7IM{GNGhZ4nrajM@|9_(cHI!Lu8`$~1*$83uM_((x%ellpCt{Ce^nj9(U4ChGRjCGT_Onx{!y%kJKH~JFVe7Md_&EG*a=EG0 zhY1f~?<;N~f}e@E10VxKiOdl}tAFVPohJvuIQ4yF9va{N!ausjMPz8f%zTcFaw4gA^@}E_uKFSd5oK0_DH&gc}>w5Mr~dt^&`?Pq_~` z%bk_f9`24VyQ<=#+{dR@6P74K;Q4YSHyZ+TKBttt=s)MdVYRf8$0w< zB_gh@?ZmKnD-j+Vby|6?Ik{>nPBu-N6x*~=pN2l&Ior>6g` z>mQtzeUx@8s*5MI4uP05-QiZ-G2Jyc&%CeUzNm^E{yUSh(Jb1VGrOu>XvS+X zuzdeM!)sShF~qQ+$55-s`BFob%&;nK_^HC@ z**wFWYV`}nhU!%rwBl_;hwp&Leg{nTO`@wG-&TmXqP+!}{JcUK811G0Y7Q0GL)6`& zD5Y=Vy|3+mV>#sDYve$2t89!6b19WDLm0_JQ3kf=6bjaioig)-t+Dd6aRh>ViDq~Y zvcsL=F2^u>eh8Fpbv)c&kPO+s%flI;W)MF(IWlAbqlGqx1%IH<`c`(HjeGFZRqc0GU(2TXi0LUY? zR=zkx4_CpY><7U-^`%Y_Udn*g;c_+qeuDE8+VZ4+4S(5C?yWbw8iN^zHvDrfzMrCP zTM*}7RBxLUzi|3ra&d79&a|&%HRxj&^43Xw6uqz7&if9bbL*zx=2`!BapAqNOt?bp z+%GXi6?vC%tJBww$3RN7NCFuip>oWtNsw1Bu{#^Unr%SR@>$u}x`3g)x*qARE^B(t|G=e%@r}fCdRuZ|EXCx5dHsKH`<>zP@>U7^oHQz-35`l(q6bI4rom?=~mlmmD(9;o&8+#I++EWw}1Yss=#5h z;|sJ|c9bA-n|)e;{YL9lyZyVvlHL?}#}~8M$-#Rb`@cg4Y%0UtZA;SdU%uz&^l_t1 zgz3i%jqne%NQ{X!jJp1@fp6N`WotC3zYwS~o8G(?N46|soH_%E=nSj~D>1G&$Bzj) zG6QzQgmb3^gz5dt$8N8bkCfD(%a#R%(wm|#g%ZMq%g5bwsFapu0fs4u2tvVAzTaTD z!a^7Q<1@IXNssuEpF7@Lt(TgXc`0-~(cWii-9+J$>1D_S2m`^6$&{ijCr!lFYR$^G z(1d6O!j0rq^wQG5QTC@-q6?sF*BTRr_nT(C00fdk}3h00ICL|HJ1`4GCj_ zHY-&Bw3};6%|5@`ZWY$3JRxMv?AKpq-^H|*F6@6gH4a^l8DnW|nG=iog(Sx*ZA_EH z0yevL-9+rtuMiv>Eogem>T{R@9EV)E@v5}NhYhE6%_o~&5IiaqsrLu?QE>bU+Z;ub z35>te3f!GlT&^W}%}~s9`h-c7c0c?}R%)SQUu2;fLO1NuC4GCFiH@UZ*eRc0a(Uf@>k-nqH@Tt_#O{_HAR2+&a`T9e*J#;XS0;C=2o2^ zZf7j4zK&RrJuViw6{{%-f$`1MQpMuJQ37WWv6gES{6mB|?IF{@2bh4-O z9`gNcm-|5vD!?$7pagq+N$+0J!%yHVqphE0$216C4QQydQV{u|I#cV9#{cCUc4isi zPOtOvSX~Fc;@FaoKl&G*+gf7Ktr(;>BfO;6*o81B{v0-l9Llq&u>Jps!vMxyEd)e9 z$c?*~7lP+O=&C?c-Iat$x4IJI8Vlh+z(cx~^;9mo*^34siDbtdh^Ko1!Ch+wDY6*` zSW`Y65$V>kf2zs>Im7d9l9{z@0w&?uc9g`>u5ig&)2=Y4Hp|c2H3R2x&Z*`2RcD24 zEE#alrDjt5x|<^1U@VCC%o$c(arsLumULF6Bv-90@#t0-Qr$8N_024^zSu^U=oeUM zYOUZ(u9{kE(yf@~ug5&J>dZ1V_~_!;Qd;o$y4Msc1h`?Hc;^)6psjF861pjhNAT`* zO~BaLg`Tp6R5uyh{V8;gY{N1B-BkRQl}2QusdeMmppk2Jat76-)a0ZSGSB2`z#4l( zkLq}dF}o;*>vT6|WWU1(Vb#NThR0g2{SCaNR{@5{3$A^TLB{cMn0U=vUNfCLrtMdMUbv{0TzWXtVB1QYtZj@borqss5`6`Wm+ah2F8;iv2u3Clm3iy zag%mMgcDdTk0hyc3~F2!0hD{Lx$Lf~>qXcerl|?GPpq#*FOrD5blTXl(b%*Uf46&d zdl=AvjEwwvf`+wa*ZnISLYf`3oS+(7yJkXQoC!3wHS2z1zH3=OG$k0m(zyr&me3?r zBE=<#S`C-64Uo{eddjZ`G?m;6TC^bgdSq_T&N*VczhT53_r$oThd7GS5YYcjlSq># z60=_+c5^9Y`kw$+2dVheGCDuQJUl*4^umWn?W0FaVpRG~Pn`58AdeKU^Pct*xw%Ss zEI~+jp=>2TS$xCFx7Z{8Fq_}Z-RFUENW#+K(V-Z2cq&9Vw#9eBPhdC9v?HN*_Y%a? zU2#kOYR!$mt_zMhJ(Wvr1QJ>j&jJ!02|@|AK~tLEXRVI3%MDbcEB8>Gkg#JYf7^=J zxBnq_mz3y*iQ#co+{uYo+7s_oB^;C(9_>7jl)4PZ&o1~IwZ?_Q@!NPGOH^+9eW+-s zOZ2gahmdHOhez$>TuWky@;Gk>K01j^!Mmk@bi&F0!mza}FR4#E}nON2mLKAi* zWF#P+a8N>Mf?(DN{xj;3CO8s=5-v>CB_Si>AirUWahq6P6E_kGJ6?twXZQ7boa4AS zA>kmu=?O@Jkgznt@mL}ZdwrUy?dfqyqV*GyL?26RdJ`|vd``5OHpPW`2cg(_N!Z~h zOn(?5Ix796Au$>FoxEE(5`B!nhh6#q00030|9Am>muqYkRTO|PeetG+LU}`Z6x(Ih zQlONjZaX`BcX!&InRR9sx*>5SRBQN|D29Yssf`2>@dr_3sNxTU z#>B@zED4&LNTQ@F7{GJR&YgXBCz;&s-0zYgO<oT3!{F8HCtx5MvmC(DW=TevTji`CJ}>XsdkL}rQpTocVHK{0gFS1zz+5O_5Af32Q3X ztXXUxgm&ZDxf*l?qb$nV)Z>QCL9H6oH6W|mFHl$SUhw}7P?mXaIopaFi_T_G!F<=X zp~Xpun+qdq)pSFJ?O|Gy27+)iN9*t;~?Ym()!AG9GNwaOf!Ky zE<@y85~+^-QG(e;vGW~N;MBZdl}o z9Skg>2sc%R zAti`e%xdAgc#uIAy?xz2UvJ-@WY3NzWNQCwrw<4lgzLGv#L`_#F+DUiP%Y>sAdU(( zC-X?#0X>+gW$l272bZmYmn_(|ExD&P!xnGGZ~roO7P#G`9}Wmr!go2M#FmrP3q50( zQ8E&uIYHGaR>F=d0Yfqpc1%)?6=d~+SL;U*#+ntoGRU!}?YO2`E2*u1@!8<pg;R??K>^qn_bnT9> z97ar`u*!)%QuTSgq76U{cz&;N%irgd)tC+SZN<$3J)?mXJ>SrL1VoW};*61_y4;DG z^ROx~yZ@WdEwmmBSnTjEN;D`-M$lFzO$u{kb)JFkKo>SJx1z@FYTi^E{qe75m@EvB zh;_ON*{M_PLDmJ+SGJsPfPtJ@2qWr;-X|N};@O+`Ar^u8pAN0RFL<#vvpT}V zJm#~B4(XluPPyB25v)S@3emQ#taTTNGA_QrTt{8xlsEbFYLJZ9FK{%34LzP`{(4Hy zr$hhU!$L${93)UX5?y9ew~S`G$&{bGv=t$I#eNF%&5F!7u>J7u+uv_ogdt0i8{t&I zS}0((H*RAYvSaX~M%4`4uErF&kz7yw_F~`b0H8*UEP@vAvT|u(Ug0(aUAS;l7LQx5 zo7{_ph`DG+IX9)XaFJ-G<}hJ*Um5y?3$SaWl?t>EO9?65c!X?&&-9=tSbdTlvNubH zA_bt|&D$2OSfO(vD?cbOLm64ejxGKpnX`1xED2khCzDDFyN2L26hc zVmO_3;?iX!NOdxNbu=bKiN@=k9T+p7*TY2%%I#vF5V=`Vap10yC(dC7w=itzkRHwp zh0ifRzmKPT+_)Kt&|!7>$&sK?DRyCcG3ixEFII;Du}U5_6KY4EgLsRfh^79G@N`m4 YZ?>K96>CLh#Uuk9gMV562LJ&7{|V>22mk;8 diff --git a/CPLD/MAXV/db/RAM2GS.cmp.idb b/CPLD/MAXV/db/RAM2GS.cmp.idb index 26da0c3929a4d72898c620ba6ad8d8d01615db8d..775899adecbf8fd3a778405348a3d10b27fa0c88 100644 GIT binary patch delta 2268 zcmV<22qX8p6`vK5Pk$2$00000006530000000000005r~00000004La0kz=ShV__7Ns`!V;Hk*;CsS;}qjR98- zB8>|$7#hgPCTil|plDohAwk7)nAiJzeUCi82TAfr+Vu3EbAS2$KKJ*%zx#W4?t8P~ z$QX0u-A?YV+$xQH2f4d*>&SZ_-f5il)X1mtzOql2SQ#g)`2AHrt*MMVtNeZ{-$ms= zA^XF*6?h-b`*Xbe@GkI9e3y4@8(?5P@O!|y!0UkD1zrpM4)AxtCg7vM-vD0&z7Bi? z_$F{G@Gaomz<+muaZlSI{w;7nq55V-5XE6c{z{SA(fun%6z>&Zaz#8Ci;0eG2uov(!;3L5Pz|(<0g#F(QYz5u}Tm|{^A-)ax zZ@|Z3el2haa2;?G@C@J!u---Bsi3z5{xj(J0-pfAGw?LvO)!5ma31hQnEwI9<01Y4 z;#YvjfPemL;AY@Uz?XqrfL{c@3hWB}D_|Y)b>LRuTflz6F9Ej!{}uM99pdAG?*ZQj zegOPDa0l>1U<un%w*)c-l~KY%v^*8qP3YzD3dPK0_of&U5mtH56aUk0{8J`tGN zcb{Mf+}u6PE&;ay+r#`(u%08t`v7}_-U;IG!+(1HAYKIVeZZdp7X$AHE&)CO>;mgQ z3-ybjcLjZaU^n0a!0y0L0>2FF?}GIQg8pNO7XTLm?*JYF`F28FfcQrc-wr$m^jjeQ z7vQbH-Z0+>*cUh$*cmc*hXIEJzW^Ku`6D2%0oDRX0!IVK0Q=Dwa8>gM4gjX_ zYkzk1C430)$ysTcg3gedVoW#ag=m95%b1yxt~X}UH|G~pva-?_=oh8wjY8_HX{ig- z^$P?)VM?@+VMrCymMu=vXYpwf?p&LYwje#r$dkpVNV;XcCHD~`mlzGg)C|MClnfz} zufa`xreTqR%J30V^z((7wE5}0thD*E%zuwoFp$uYDa58^8HKKaXkN}jAx^(|iBX78 z*Jsf$1aW>Zhv}meA`_iuNQl;{KWR+m!?ZD-qA1j)+%dw z8b(?=23@tR{o`^g<4PSr)_*F8 zRk6x-DOMRLOF5NsvQ&>cPBp0G$T*)^J)f95wVo{Pkvjhm&F`r`^?LMLsMn#R_=u0u z`ef-WsP#0iZgd{i=Z|8&F|9>sh;)y$>h*il{ZL$;x2O8m*Gu{F`g)7=(!1@46QAGP z^-})c;!G#r{!_;(pPH#2^?&u!e07}8i~4?}xLQy7kfjZA1d`Ohpg&YU--K=tC*@#CTlHVARjEZ?#(%OdIz!4qRDaj-|LoJ5 zmTs#a?i^`f=up)i-6j2eBHe^RlatKqJAnkh#C}%36UOoS&TyYTsws7Tsk%$N`S>ZB zeYk&8_IVzyHX40f0bGkTLT(d z`m>lxuzuA~TzfK~{~4bX!GG=1pE&ntxgbcY;ath<(sHZpFWEAvHAWSuGfhv2p58;) zAqsE-d#*|PVfNpje@^?B(_pow@cUnDC-wPt&x7>-^S{uZv^GTDaqutO?KM!7bn2$b z)WH0~);A+YR9d*7w12O{TI{#flq;B{ zCf9vv4SZ^YY1~M2)H|yWSama3ndsWrZojC>oHu5|uMRIZyvUnPdu2G=TDL}g_}k55%#^&Y`S#7VQFq!WbblJw^kvD1Pm0w$s>S=) z*Rb%{x7+KkWwEcC4V@EnQ^k&zEfrge_iJwL87w|C+1YXKJnyn$i>619yBKIKFIj0C z+mxeejol#jWeqGOG?a$q-t zY@%+^Gi9r*9DlXvv$xq+B-z*~!)&Rxxo-xMFg>zG*e z;QM`;R@$TqNZlhgXU}HI`LS$z?fHs+50*w&FQ3)v|F&=Cjf~oe)*OrY#TtvK+kQdZ zJS>2{UOj|Oe|09?8=TGNFErWZPc5$LyG{)JrTKBDjXnf?! zZoe_7Gk4a)J|7(r#oy`HcP5&X#jCrV9g3Hqx32U1jVUj_P*c-B$j%rNEYAD=DTjF> zp|-H~e^3-XE(F@{^3Tr)PtBJ8G0vX^BHMX3H2sZ@%Oa-ysWCa*maS>C*s7KevYHAy qTv^)I>lO4^7~ZE`dMrrKjTTF!^jJ^^sXC?%Do+&}`xmn*36TN7@Pu&y delta 2295 zcmVKR02^c{s=;l9}ClWCo^>T9wf;hX@Aqxch2M9&%NLG-krB^ zhGB8!IBp>8DyjEpR&L}wNPQ5qj;uSePI1yxBcI~Vl24Xcj+2%B0Sceil;bW6zpuh~ zRrviR-M5}%ept~JnO_?v5svE1l|Hp2YwTHGw>$hH-I++Hv(IMPXpfuz5`qb z{7>L|;Jd*0fPe1;KLEx(ZGikk;J)&~km7xS`vDIHb_M<#=5GT26u20;1o#5*Mc`84 zOTcBo$-o1lel_p{;Qhe)Fy9&A%fLCnLtwrSfUki5IB*8&uR{Lsz?q;ghx`fP1EBv5 z@+W~m1bqeMKL$Ps`fHH?1o#l>uR}f;_%P@zA%6-u3xD)CAfE?(1oXpzyB@sKxNyk3 z1BU|70uBSt20jX`0}cib0S*Gz0tWy;2h0Oc1bzzm6JQ_Up8@|B_Wwg*JMcl^0+{b_ zklzFR9`L6yz8H8aa0&1t;GYA34(n9`&j!5;cpK;s0bd5a3-CPP?J#}^@Y}#uFn%ZG zqaptY@_%0fj|crt;A-G6fNOwjf#(3<0`3ny7dR5Q4)`wcJzx#+eBcJ)-LOARke>|v zHE=WVBj5?ZEx@h7ZNQU&y@3m${zBlhz*~XO0~Z0?fX@LhgnBxF{{i}&z@4DK1^F6a z0rZ@@yFdk8-962H0bC2LhVf%zJx9np0XqYafq(HXkpBy;?+W?Dkk0}>0-Oze6!;kM zN5K7HeGjOA0OSV(y8#aZ9t=DLcqnibtbYLNeFF6FLw-N-2f!J?9xz`f_u6h6`vueT(bjC`ocXtt#2lZ+NK{pB2}H=C0Zj4v9D7Ct`F z5WgbHn80iJS)qKgDV{g1S*bUg*|4BNOuN94kYu*7$)fe5ZcT5Kd-EZyEhc_;vgrkV zGQW_m!Ax|D=|vNj;mzxf%lI(EvLsfPVSkw<)6fbg5}H!@aJ|{WcLhROIV<=G&;=n2T_ji#8mWBKn9ahpF&%;+ZZKK;=Aunv*|thdwv%-^-jlUU z8a53_S~?iY`Ds1nI40@#;nH~d!;-ChxMWLnKd#ZiP_9SwQyrxLE|&C*7WI8X(`;GL<@uWuMpLpz%e@?P z$H%GAAo}8GlUjS^0>1Ky>L1Y$s-JB_w}+E_u*9wUFV`y9qAcS-Sr?rl`F|iPYxsZm z=}e2aRS$QLxG!|5N=_dTzdjLf!YMNs*_3wz34VnvB?C0;Ck zRbp@EUy=Mt%)c!8lbK&8`5NY5l6)WLmrA}b^Dj!iAM-Cr{uJhyNIrAL_EYv#u0^)z zK_f|j5HkbTFZiBo&t&7zuzxW@%%1+9V}Fnff=RWE^I2WN%+mhmF<&S7xr%zjq!?-F zOw-e$r{5vmNlGvQS9(YMV)mQ&AD<^rQLrH;=ilGfx^0Z;IY_^M{ukO{`$gRY2cO(X zk73$lH|wp>ZhBo;vC@)z=_fW_OjxeHd8waJ8yKFy!o#KuIX=R^Xn(@!d`I48ux|8{>3GdmHf0u6c^|a}t*5=sL^r_bVuinre-L4fvs%xyY4>eWmw4*)OS__%R zZT)7u*Dv;2e?7*gdu30eou64EY684$+N7!oA-1_*WE!Vz2Ja2p3_gH+m_6NUTfzm0 z54|rGlw1%3v*Wn(H-D1Uqf*!8R(F&UH(?{l<`YRfXrq<3b)VUT+gd6bo#-uZY904{D^h_$l*oNoBu zxQ_j0qqt4}=TtRk>NS0000000000007H300000004La z?0wyH9LbR%VV~? zva+hO{^Z`hd*8+1hxp?&Gjs3z_^Ed;E~8e^i#ly{5MFlT-k%`$*PFlDWTN~tGxN_7 z^%wa2m-sWezn|j$WBGf4U;eSW`}q5ZZ@>K(RsM4X52K5yeP(Lypmp_!Ft+tI4r}-_ z@E`}Ce}cb*+J8>3}oT;^1#wP2UIP8Y;%kX6G{@0y;Z2H~MbWR8JeBL!D zVK+K!n_j2W>V9cjowKNEPW$a9(b_flgZ7E(^v=WBbbmXiy;ngT8b(QS27~sMxeVf7 z8);nj`$_&UZDOYA^m~{6o;i(LVb`3-oeP@}FrjR7+KI!n4l#TGLDX)x`X>yZgfD>^ za~XHe;^4v}z5_6#i@tQaE$oZ5j{8Bk+i6BYFFY|Poo4?cZ1)^_AYar*Ef?;Utq8xl z1d_U~D}U4NAOHKX*)#Wh9Scn_j4!$t@Mfod5;;T&qz>!*4kWV;_}W12{YL+|+l-@2 zON+I$I1E|$m$o>U<=1_nsNXgFadZ(T8PlZqi3gYT(f;F_+1f8iWY7-R8NuacD{2PE zt?~Y7-oOXsECZT;O2%De1?q#V6y)Vr>A zebO}-LA!q%G<*FRxIVtR?;s~RpbW-HTZs4`kl6qmK0CIUJ#L7gWmn~UhlH|)%^VFm`WF{Ld{xMGh@AN|{>My9@^|+yR&oFuK9EV@{<#f7nlNw}c6;QS$3g!r z?Ak8{|IN(&2gLrH++RV$Y1Dg+0pSG>h>jP+9%-kXYBD@-3U*E zeye95w>rld4;!Ok;gCA>9sK7RQ~%!S2f&nhq<^*FL!?FXW-GYtLIgsKC?D|Ox#m$X zvd!CTj1;Quwzsj1{?xZ&yK{zM;WIPy8C1I8yK(&JBDgfOvvC-l9Cd|akE}lOb7-Tp zv#;W)7Y=+mJvB}loZYGY=9!so%Ike!>S@#~D;0TfTx`(2coW4!oh@k(5Gce?rP`{? zU4Q5qpP9y08zVTvPIdlzw+PiUcJQT|&fH%X{4t(?UR9UM$UBds9uzoR{G+WyL<~GL zGan$1#rvXJjIXMo*hEh5Kw%7qjjr=3$nt_uX{c(pJ3Rwc5;{v8+#j_~V1B*Rcx;v7 zIkJR+&&i3C$NfvIoFcU^2%id{nHy9|YJZn1iHTab8(u(@bV#c;c8V%0n$Cc%h%I~~ zGK+e7q(ET(HyK!NohRSMsV0GCjXlhkOxN^Km-)?K4zGhzdy25{sWAZL-E3olTZyxTJf{8Rvd&~*ME+u z6#ZVH4Qp?=JaGhz7R@ZC_o`#s{fpx;?!w;Eg&E3OfP5TAei+J-1sV|YL@+Kj zVXU%NBA13nI#{JF!FBmUtI%2WGB1RI?&>n69nTt97~Q=Lo6#w(btn*!nxNHbhjZo- zpL~T52-@Dd(TTMHme$|v^poucEq~t4%o+&{3z>e3U?G{p9tc}6&?$B+O_=$zthkx^ zr-&Yg%#jK5#R`aDl!3Sh^XG-_o z*7J>r5ApxNGh8zWi&0&r=_xp?PnNra?Qz$IEF@LDCU$+{n z5O((O40>)N^Bc0}+ns+L^?#o9kLTSuK40J8-k7Jwb>6K)J43B}ox6jwzRD8J#>x~W28*?m}rgf%P6Seln~xBh~%GLL{t zy>t@`j95U&3}hp01y`naa)L0|WuI`(*X@nSWL7UT7BY_{DOCyfjDK!c*5OJwgQYyL zoBaz^mncmG2GpS=MnS>U#`r+HLeu09f z1DT@k>8O-&IyrujHl_%gA}Hk-kVxjCgoHff9Qz#>AEKNc z%<`klR`^Y(s7$TuC4Zf(i+tpKdLKLYVB8p(^M7T2^7PTpSNJ=M+TGqyNZVyL08Y`Z zEy)jr{`XBpss`EMzhdPx_bBUS{7E#3jL~@5ux{rpuXQB9wJIWpj8YXnF`)$fmQ;wQ))OERLSo;6Z zISRy-d6d27VRRD3Bke7Ae>?4@!;pNNZ!^=vi_kYkOCiO*yJ*RINjRrLnhEh{_XHMkMOoZ5 zLz93BRDY*fD#MJ9pJGX4qb&SBU`boq7#0I0H!!DrQ*biIIWybt1Si%_fOAX=Gu~l+ zPnjnFBeFSz;8WW1;J6Y_IO#Kzt^|0H{$&`)JhP9Z^YF!Z;);dCL>}+Araw9UkCI;o ztv(Kh)6oFPiQ2wn0JhC4@BKZj#5f6iY~VLs!`FA($Y@Z%KHES*g8 zF~tWM*o%uhB8R+C5oyGo{5XQui#zbZ3RNU%4LwF;RfVw}%=|(%**D$)S`ReS1ouYb z0e?8mJkn`@g-G$5`!ocl1J&ATsPv`C*p2M-Koio6*y7fuMOo<;Rc;wQsT?V~# zHyMEcdwO{XKo=R`>H+UIptII~*8}WM_8aT>2)7<&XAM+XZXnA9v&oP2|M*?B;eUL< z`vTG(78W7SJ6oqs_x|UdS6z$vUgy#*!UbFJ{6QB;q!;}2;HC4w)(T=ccI{!NMb`#F z;@W_{k!>&?3EZH;16e%e{`b#W?(}Ae>CF)KN{Q*s5RlpK%az43fi!z`QG6fw?L`1&;W*XKj)yXjY(^Y+fWzu-^a#H}`U;zLx^XRt!2ww`? zZeY_M*8cAzTLST0*#1m=39E+}#OS+wgYH;x0hh5Z9fq>o$3D9kXGz=N!tQ>9uoa?} z$T_rbjosZSH$E^E37f(C9atxK-n{-!ik9cDGHfe`YF+W`AMjt3~`!jtj|^E7RVjEVpRZQu?TvYjU*bkJc-!7| zSGu`OoOB&vcRh>ch_EY%6>TFa4X&;dXg)W`7i1L@l{qjKc=} z51MDLG=6pt|J*x;_J8tDb!p+Zhn0neI(ZonL6e#H4z~HX1ZgbmQG`i4)7-PFMJbV6 zky2S*HuDChn+Ilf(R^w|jp9(9Bm8^3s%T{q$ye8rdTk+1{ZW#7fEDbD#sa?MVWBy0 zu!C#`WmZrm+Lx9|Jkadnd+<;3E|w02@R0i9p9=1wPUt87Gk=;zc)$S^>vE{X$#x-im3j@kS6a7VI2tH^|X@roo5SVgny0g@r2 z#H?kuPF#LcS$%J3e`|a5;Ha_nc(-==^kDO7izY2R27lFs)k<|?v9h?fQe9tJovW;@ zSJtc5_0{Et^?%CB8k60-#{qJdmJ~c?VUDjL$)oxnYWU^T-TL9y-tN)i=FYy&X7jBH zI?Kw?@wU9J-O}=?`3a5aY-M4()Y{*B4m|81Y&JFzQSRRM*6!n@#@_Z*g6g2;q-VEd zo`f*vG$I@UdQLz54J_}rOf8CCqOv-4JnfGA2YbKVtbZRK?L9r*e|mVdv2}pAy#rd7 z@Q_Jij>Ksl=RVX%mZDde&He`m_i?vkDl%By;C*2999hF0&K@C(JCuyLCJ_glLLm{7 z{eBp{FwbN_+6iHf6fyG&K01!B?>{w=9ie#uu|~)IumMV8!u_0*Sc6{fUM582;jzVq zg|G0hQh%`#_h|KkXmu}S)TPyhs@ZwyBGUBL6&GVgp!M0DPq9#SF#{zoFD|VVl(-<` zpMz9#Rnb790@*;JODiiyU@l1d4^dFgyg5*GDF#+n3*nXY6b`mG@zz-t=O;S`yR z0%aiuQC9B+&2wBT1qZC%UOO4R*gd$6EhRPz8-GM(hD)ya?0c%Pw@V-b&v3$ExBfP0 zhx>J#*vk9oxX6Mg)`~#OWrfOurxoV-W^LtYMOvLFjN6x3Kp3|#w3IMzUv&9pS=Z8y zsw?lKZbb4c*JmtyuL&iQs`CmA`DjH1#+y)CSZBgDUA*8SMeN#ZU+n8W8WP<*Rug(S z>3_+knl`S?wY=)ma5$9Fnv}K^e1mI^aVK&MSJQe~?~Nt+&KZS!(hx@wKUQEz*opgY znQzXEH>UArr)gNQ2&uHVG(@~PD;2K6NgC^lrzHB+4K3-Q#10e1cEcX`wYd*uc3Z?D?!$3W&hKWX z)Y>twA?`zEOiQFt+>VZM2aSxDtYU6XynypU#<`cSJQCSeD4k2ahA>iiMwmyMCmY*X z!9#5>F^9XceUPV@Kl-{-taG@4=IlRYfS|;%Ks?9wD)GteV{4`+T`5S&6=OqUy?>#r z>QXpJ;ka(Qde)u0h)(f>Cj-pqh^XQE=GjM`KGtZR0s>nFF3Jv)3zQUG>qvh+xboGf zz;S5wzEu&#W6{Q&x!mhD#K&jIL8_gdh4a~qV@#CvSBIn)-A|>i6sJ}KQYBs}Pdr4Rk%u#A z>k?x;JMUVWVu+$ox~t9G;#(>enIM^Bu}Dc6;Hua2i;ye-X_2IsilByynt!DI{ps-w zm5PmAz#kq8F-hd<&NPE=Gk{?_EmmdtB+byhYB$g0PP>Eq<(s%qJ)UoI`*E7hLL(LZ zG|d-`%&6*1k(7ogLfr`LVHTQWh3hiD{Uk}`%y7-H)v~vOHG??5GEMG&RM{#*eq?oe zc1SF4cCO{ec1o$doq@m#6@QRH{kV4;v}ZAK!!4}7zrTa82lee=;Rg>JkxOgiZGFqj zE^Li4)|M#6xoFY^CK&F81^EFvlZy3K=T@X)R1cIT!aVU8qnX_VLJqTzV(Y{f-tcfR z->xTXdlKt0@i4VN-eZMuG@0&k(qGEQBdnC5&lJ@(^=|x)Z6MxAV8Rq@xG!q+M zx1H&>vL>YwHhRRsK$XOOjJQXAOi5L{lbH+KJzy%a?RF!#n$vJR|D(3iQ8TElEtv=S z?+b+SXfjmP!DvrNio#jq+KPFwwj$XX0Sn}V#RV0yvSuEvtf`2~Dym$S2o6Wcp)+KF zq(-EHW>3B9#4qrJhkw|I5cne~J8^sdNBhN&bE;qkwrW@|cA+q94#aD{lCPva86aIn z zGh6#E$#?KWL%n+=(d^FG3SNd28|fCcczu}y+F$;1y=nCN`#6new@jB9+}wQV5(DX` zz-B)Rf27)b_kVtZzn!RUr|!I+)BLiJbz3ea9flXySyMk2K2f4M)t_vBnfi~&&oRr} zzKxi=n~O*RGowu^YFj7@jt}>m`41y-eXjXANN5_7$-tQg`Xyy zu6Yt*WA1Om7>hg7gwSA-$L?=;6}XZ$@#rvFYah0>*l(=11a3AQJ#wVLrZZQ>NBD81 zFvttTzHv-Un(oN$b_J4Xas}G0*_-vfk-a{TynoQl#V};7hE2)f&Y${rqa+$T!0+M6 z5`U(l+1g7d9wy}rUjC+AK8mYIE!*J79t9Qd?Smp=JHiVve8y8wEnF6~i{Aw0xlp-}x!&y4OAsPf8hc)MEw6(Lq=>zT{qC&g{(2NQ`%%wZ zZp$-s0>vIS>SU$Rgcc4uJX@5--D((}oqt2%z^o!$v8-1|B*#+@LLFaa$Ew*s$4QDN ztVoS3d+9q)Rgh!Afy&(I=J|}5Y^l~=UJIf2wImbrjs9heH_B51xn_BPQ&ipoj9T^> z$~6o7ToqQ+HYT@`5oo*&TTq+404{H)((2tXijwhsfIr*KU|Sne5M%J60RJ)?Uw=ar z;LJX?#b82%)c}j)S>vJ=+8r>Q;1Il`H#z)4jaTyh$n_33yQVzt}EdAZQ0yvOl#pPoCQEi}LceoG$fz-Sl7i09s$ zew(zS4B6E4YF+R1_XKwr^8mzI%=I)^^vF)Q;k4D2&apY&%?Jw{b)0nj2rJh%%JiMc zk-eODccaQgbBx;JNMmgM3V(zE9q-xuKI^oTz2q=U=%TPd_21h3vk-3 zR;P0*r4f(I3x1bL_J3`@q&yh=XNQ$ZpsLFY_#aQ^!EDxAz{_ zw#UtAyWg?P!QOLoz09he+x5-uu`6YV3bc*AM~7KhbtmdDrHZqY)F=}uoX;?raPq%c zH4h`dw$RCjTIf{=pZnu4I`VPyqD)U0|BIZ_(6xb33 z9n5>~z&AV^1|3#e-62mdt3=`vaClZHyDv-bP#>Q66MPml_-QTdU9)>Icn#E_X=>($ zoapHS`xC7ik#NzVruRBW`7E%n^^2AoG4E(VB_V!IeVN7ad@cA zTBDGFmVYOMH!#zMhTTnNL`K45ksV~j9g(*5k%DI(Man*5aF!c?)1&*Wg}sUbArBJ- zNG!7A$tqsiw?%wUOK-diFMBepxLvtlWy&4!I4};_q#kSw#{YOSFLuIhtp__#e?z+l zw|`G3rU=b3I?N%~ZhyiAid@6p5QzvFCSbXxDaEX|Fb>Q0bLJ`?D{zd_3Ef(^L{=g@ z9^C*P{siA@-UrWTs^f*MOwM$<6P`r<3tOZmV*SpQ4V)&n3$_VI`VpyigAs{n*#}X& z>iCxK9ijfvzyd3_LteS>TrSAC>7kJT`+t`sS@`9vUD|ZXSsb);F`IIF*y!~k@3HLn zcy}XBbKLJr1!PhPE9`YmzosP|A`)Xo+wH)I>IAj;40h);)1rr|IX{JbEWH)P9#Uk-(nligYV|RoXZPxa6q}JXvMCNmIu<2%PE5v0$Q|i(&ZqCHr z;|9s`&|F^y*w`U#menbAqRrqBj|#Ho*j}jJI+TAOWLNoAP<5We;iKpqXmk4=%v{Vy zW8dg4+sr4O_c?;n2+4=-{MHZR$gHY%6=cuL;vdx``1Ul2!NW95He`=|N~Mz2uHs0a zvjlcIahEy5PXYhS!`fp>$7P8Hq~lS4g<`g-2F-vvHyR(tumf^fmg6fAdfZt*|78Bz z7f64Ihm*zX;@sM&q_UN{Mf+Qst587WA!6+z=+{sdTju9JnN9oD$^7nr&as|gHvk<3 z(u{f5>KwzyI*@)zX9}q+!J#Cz(`KgQ|0WWZ_$SkeBF&X~a-T#N%0m zw_my#a?@{My6sTQ!fYgs{dyqwyZFfC1#*9O$R#D}vxDCwHzRbPKf;e6MM2A%Z`6Vu z?YOjTq3jkB+r^3dK(Mj5!|v>IF$6o=En=Qtrm^IFn8abyj3qb6bJzjgJd?|BXY_@6 zEGi+nyl7Jk^`ttie!pAzcdl^Tze4=vgQ|;WP!6szD4mr{pkfzXHkQ^F&9yAd?oWTV z?6Jj*bBnXj%=WYT&R)Y6!`_CmBX)1PpalMkhJV>5%z;-7zXDnXCj~!=VL+meU@I^Pxfv@^R5s!cB6V>WT6VI{+zgWf;V_&sIWt%kkD++u+P>+Ru zMLc&1{;CFFVN^j^Ogwihc{pzE)bfJAnD_^2oBgBUA8eo=BFnt z{Hm|+K=vf~*P`FAvggRZ7=G12C5I-(y$SqU_OB|K6nQA_RDwtWt%4JWUkiVKzi^r( z?_&6in=*0uwe(+6{9BCwK}@r)gRx~itK(k}|7!8Ss(@C(V*INFcL~3i|K3MLIsGU| z6|bn+iPO)T8oyQ*APT+3_*d|&v=fJaUBj<nrePd^un`(KR;?_c}%^mR$KbR_-1+w!06w!OLG#zpe& znxcJ0@XE5Of^V|zT>bS6kcWrc4nmIbm6g{t_ESMPsAV*tifX;;`QqTaJ@RqE6Rof4 z^=9u8lDblHn-xjC+k)RW-|KyBa`At#uMjaP7j84u>AVvj_Js6(;|WQ1P^OP01Kon# zgzu*HTIKcraC1#o9j?&xCdFRyz6&DgbxnDs@3q2PEv9_M?5g$eHs4F@wYuxCgvj-M zaqHiUzRxJTYOO?xy5iQq+e4o8y;gPo*6Li}D@3T^d(rn=(XABsy=wAc@HT&PUgy0V znXgxQyeH@KzE@1}Ui7_QBl34qjn#S~1KoeO2~W81t*-Yl)%4k9HH#UfaVAi6;JfMj zrPnmg@vYa&p1-cV<&)Blp z71JwHSDZdb_2dvGAV!FS46ACwEenq+2(PaIP{(b;Ywh0(#B7Hw_6ugT_Pef9Da@$h zQDH`*Lj~^|Ga1wml@p^;qwSz;$|5ilH42Sy5o$E?-4Zj}M!H^%8HJ>`o@ibpX0-iu zUEx3liv`VlPcz!Kx~_lNLSd#@(5M6|+xsMFwBdDKaf@nsG0`Y|sNh|r<~6dDHp;H6 z#h8(pQTTe#Ff({|oFln%*1`>&&+2tt7V@mq>LoX9aslnx!RDiEtWs>gj|7W!CxQQR z-U2vWV9&ub{NQ2#`fKXd)Zu%Gt}fHr0KEvTC~p+y+1VJsn-hOQJlul1k4q4p3oIK| za9o}{TX~+ID*e1_J8RmA;yIU(O&&al&aI6Z%y^8ZE|ES&5^k7O-qc))<7&$at*IlA zG(;^WagD^6Gw(n;O_PQ+zKdgZ3e_VF4vs51+ZXj9Y;;Y0F%>Vgru7ni2k@7e+$F(U zzQ!LO&G{LfmT7;ASyH%@9hcfACI*ulag<0An20E4DVi8iY6KX>8KF2(Hv5S|rDjbE zYZ+7}rj>~SrG^BBH37<^3OjlH6lY>kDLcBtnxgd7>^?D=L`zTkm@KIfWk(Fvo0s%u zj3ju{JmrEsO`~N|K3oxLl%`HYZ&D@_4u1|OtuYO~@w$JNa8V?ip$LDiEv1gV2AZgM zS6BG$eyP8a6!aU3V~Y=wEoo6{h*U{}*gdo`*h@@H38FH$R-hQ9h2@FBs}2?jB}x?6 zD7vJqn@B$yg-i)%eK=i!q()1rgQHYJ(Kl5#ZX*Z$ zp*4RC+u%@@z;@Fy^j5Gb0q*5hj&|sK&=d7Fr$)DeOw0Ab!HrZ+$hRwtEK<0<(2|~6c^Eh&+mtX~u`RTwUArq-?Asd{h zcslc9W0H_5<=acQ0-SkaJ4witQeNPuGm(F_zB`G;>)76JBhmcfb=#jq#sSX+6NOF2 zfpo;q_2)!1h$X>F3Pl=v(;9?#tzdg+a5|Szju-0_?Hw)G2ggFYbd&h%nIyMqsXjOo z5@#6?mJ&(}FfQFHAtY1J%ZRIJ2NBi=6~XXsJuIYxaL8 z+jZ?_O9Ha2WV&{MAV3iexocLlPk;+5mqfwj97oVMpe9dB`ue=dBa~mymE(&mj2QS!nCA@xCwT` ziqvI0M6Eha5(E*!X@8|5PX=#%sd7b0Tt9{?a^&FjrukuIKuu2Z@TL{i6(vCZI6dj+ zD^cl3Wd(v8iIY7jlN#~7PhZO)$}TJXLD^@uP(SCJ7+gv_);?78aNW=xGay0J*%M#m z4-ZjMD%8CXZHq5856#2n=b@9rm-kI>;ZifOJY0STHZiya01KCzedXc0p&{nx{iyU} ze_@;A#)R(ulkO`W0!l}d4J;iL)2@8egZkQlYOC7sHLE?5G-Q-FlRhjN0kM-+)62n=0!$0-!2wJF(}sab0jA`**8vqtIlvMJ zL3v63MkS`8iA3i0!U4#Br{~}kKpFWvah75s6Dg%2qfXR5@a|P6g)(-<;0Z^*E5H4basX#p0_4iTz_Op$~(dN;15h{w(IE3?} zyV1#g`W`+Z!@U2TX8I6c>OmY|nfiHvW5-Epgl#`)zQ9G+N!-VXd(_AE+^XF;ri@rT zWVX$AFX{mqNhH~5J30oEbSy1se>|w|R3A4G!ov=!tS*}e`0ooFV=aHJ+IO2$>$F`( zrui&!b=5prU6t&NsN%GCwW1;hQdE$o;n zh(ycqFyB$o>h(`Aj&OhJe0a3D7Td<=;*Q{$=MvxBZx;q0qaj5YxPG%7n#c|X7;zu7 zIOJQ(6(8V@XZ+J+`5cAl8=%)Q^-dfbMb??Snn;7rV-^B}OqLCDz*l zMwaZgld($nQ<pRGoQNR88%5h zj6{;u1Ub8RHeYZe2`Eu`wrNw&~$VZwtkjGhNd z9>!P$iHGskK;mJHk|bvDWfkMB(=5`$qo6&DK?@-~>Kq3xesmY3x_4TG zI{mmA8h`k^I&oh)506HR?Kzy&xh2bRx1`AC^xU??^268ic;;V9PLWsghZ@;H?LxM%5Mg{c~vs+`m0P; z3VYR~U1f;y=O6w8bvLfs%{kL-g+ctKaWAdpx?Tb|iZbejl(CYhz*|$s2Zi-4+Io~F zU+n0dm^y{=+NA#L3=$L4kOmMX-f_{*`%CEeps*^x%fMD8D=9axO5nb>z@pvdCK73U z&VPE%+%vp5;gIn=cX)Bv?!e*2Nhf^>oVyFLjg==4x?+1{XKaMso?kJ@ex(g>BWwj% zrgm}y!zWBM-VjT1mG}iD5h?AM->P#$V3~wjb&8)VbHZZ^L~oVFXFPcjvtNgR=%7j_ zWvs3K@W7U7M@@j}&*2X0Ow^#_H0{FNnt$Jmk!!4NQmv6myX71qsO}`tp&#Z7gk2~#7zl+|5ymbXo ztVtjIZ0!8$S`xF%=sr6%d#wveUsAs?$8h*F1!Mt`{GSg6z|yR7*S;em9xY3MjDPoX z-0jC(b3k>YRBfs&mi$*}0YKHn_<%0&fh zVi@)r6kPn7XmPaD?q3{Z!3x9?d8iX|GCw!cj~^lZPQTTQE?eO@etk>Gjc`5$0X>gS zdgln^;ZXN5=!Pw7hP5~hY^>!+zJHnMlqzK}?l*h=*lUzrf@}mYNtcD+*FZFEQhIt5cq1{1T(`1n zS~@{dubIlerz)#ooM8Xd<}RY}Fxk@UZ{5cz*0-)+Y4ne|yy>z2Lwq~{6@Rm9x;mWiETZAXW z?)d~iXzuK*=p;0a=&T*IvPi1TE&D~p@sLE}U2!UqtAb+BJ@hjzpE8>L|4JYyrB-Ar zW9Kz4W7;&5zE6=KvhL{X;m*&=2uFZCW z+$_+;kjs|3haus`lW zX!^{h6{bszwP~eQxmamdt^{dUE_Q%6Y`N01T)9FWjQx}RH5`9akSNTWYb-Of+`St# z2Jw|hs3eM2Q1BBJLZy(1Mj}epwp4xqg+vshAR-Fq+&woaPHr;qGw*rNxi=0)5Cwp} zx1qiwJd3fau%wd=rI<`hgo%96Lmd*y?Dx{+xb=Py~IyI08NISNQc zi=@Gom@$)7LJuk{hnLxMhRn#qPYTBo4)?9neXp(WlU9EQ%`AU=Rzm{S)tirdJRn#5 zyO;tcJmHH#)j&JSZE7>$j|fFGBNwoYlBvKAnXUy3k;>EF1G6BrZP(7aBEt#mU;vFG zi_d4(c-CN17Mhna$5yuSjOqmWqlbMApc5FlkRTP@YfZpK&{+Xk=@nOIt(1?UWvWsF`XHFvWqCk}MW`QxEogHVF0%&h+d H009609J66s delta 13865 zcmV+^HrC0@Z^mzsM}HSm0RR910006u00000000>S00000000000071}00000004La z?0wyH9LbR%VV~?1Pd@KzS0Cr|*(I%ZmwQ@#%;0;&a%eaJNl5q-1|&r(9EirC0kk=o zfqHt##f9R+5q|Ki{}Ma=bkF{ad~f!Hee2(^Dyuttrh8@pkbeU%Z#oE0b#;AYWo2e% zWmRSU$-R5`zK6dL@W*Fn=HB=5Q}0|{My();I&E_hUUuT-PZ0Z?&EIY^QU5bD^Dhwf zWBmPV{F%PLpW*#u`Fnt0{;|6I`1^-%zWD}K{!0W8ql>70W@_!Ab@ex4Z0l@t-%j|ZNs2Sq5@R^yZA!EIBc@;-z=ZSex z|H4!kD(l8YW%3w>X$HwN}g6WL*=7-7tO?p3L2U(dose*9}eQbTH57U2_t4 zqqDY2I-OScOVjF{MNM-gE%ydlH?2q?JIK`#7P@z zT=x5E{x5A}rs(vN%U)tmqgL28r*Y@P<^xP9+njdd@T^13-hU9ao2}jn!zbY@V8&d= zowGQ&u!!#fjOd~#oo);JBCF$m(Cv1bQILcu=A_f?U4-q#kq7ccZPaq%UfGK9>q{W1 z+qyE{-hc6b44a9$pL8rVNf=*rE#S>g`y_IR5J(-?_Z>)P8}PM(+WU>(akm*qmzEZ5 zXK@&^?k{a|F3WFvKvA!2_T%UxOfzOl?-LI$>7)I}HM6x}kjS7Nt}}wm%U0A3j$5I@ zFM+rpWYwlP{L;LRl5^l5sV*Xi3_=wo=E~DWgk=8c#J2u!2jyM%KvIrgH0oW~x<2We zi=f>*4Vp$*xeY;@FmM=l6LQVt zpm!E_?U#c8W@i2qV*g#=UqQlY)O(Bp;ROzeju*m&v{Ozs9O!OB|NS_WijA*$x6_{8 z2v37vD>08-onwrLjZv_0NS*l({_~8ffA91IV9Gtx+7A(F(Y)CTF1rwc&?3qQ{BK?J zs2ADh?KMUURd#>dyVym4>f5m0IYY4UnVIRv-BV zw9(nw*Kw4D17A*0jZ+3^cWS?VW@el6df%6N8YN|=BJYih4Z0U^qgbf3CG7zMh4`sd zTXne$J>xUexN2hrN7$*(FLsMiJ!1!7s_D%AWx*fg`R9LCb*YTJ^C(K7z}ey-Z5<+F z;F+2EF5+0cFPg>pstSrt<>U?&#$ed!I*)=ZFZh&(s%E>B7^sraS=!+KsBHrCo1MmE zs|?SPB?Np z<0(bI7idG9@>gsMv9lz9)0fF11SrovLZyp{ETn(ZtbdcJ75$Af5W#-2*-oP5O84^y zI2YEs@GJ8OwurEVMdrKE)C}#okaTxhwC_@%#K*$rp zxYUHP%36tB8XD{gmE`^&Q8 zX6BzGdKfZCCg?9#K>VT%#66flFFXfTHZ5w;?qSW6Ge^>48J}@5b@@`u_IDJT0#CZWY=YYUS(PWz?psB=vLA zAG(X1@-?W1blSsUm?6MaKF0lH-$`9RKu|{c4Y$@!6$;Dl!zv`Kd0EENyrjGJ7nGHI z1XSv!n^<7P0y<_O8(}NBGPRQvgt;#JgloQTZ$vJ$dYQ41c_c}xO0egDbhEM!SGpN2 z<^8(Zze07X(llT|9XetZ6ijW5541}zA43;BitQ#78(Z+7YautL(2gsLT&XTPmaXWQ zC}=v6De9h%N-3w4;|FPDil8ZiGJXMx8v}Fxugp)MKHB*Te@9WfoBWitU1kH| z6y4gA{6Oe`-$tZrkPZGDRz7o&vR=lYRD;MFjfV~EcFyufNAg>%0@DJ}t?yQs^i!Vb zQB+X2+T33W)p@A)Xe9u(9nT*(`JI^-aBqqOFvpY*rZ|8snbN_36bBqfZcPU$BlpPg zM(Y*qLF0^X{}xGSKE{7H8P|s8nHD<5=^G}iDM?L9YD!YWgzj~}O*v}HQB#h(F4qi8 z|BsxbKuozu*;^h)Cs91o-eUK+(@r`J$+!77GcCLbeN(g)Qrx!}Ejc#Ci*O>hmTk@N znTJ99rLo5LVMca;e!Jy@KnWb&Ho)We`$6+1w~6=JVPD|0+d7O7I07BJjRjqUQnsz#^_F zi<@RB!;FrfVo778EIh?h8D@0+6iXT#W#K87$}pqjr&!XHiwQx0-v=ydD;vXNfaC_| zY;Ouq#yDqY+nwOVx(RTONnyr2tnVq)* z-HqR#BL)CG_eckS@#NCLuIwUL52|;jo*v4*OiVpJfS@#oj0)$75-&oRJcQxS(bdo4 z7|fsZS5(-aapsqZ`S$SR6w*AMOz|9ki#sBRexV}Lh&%al1S^R<@W2XHBxnsi zMq*Wku^i0&QZ?B(-Tzt-G}8q4M&bcD%stX+e~C!(n){i5*@LDSn@2%68K(p7c{%>) z`$GR(H*CKw`1l4tp!D1$P5KK&!Urq7TG5yI0nY2wr}a4J@Ohw+=My&y{&+qL2lQs~ zGu9z?KNusuef})x`Rf9Hm~!squ|f||>F}UQ_wr4X#6i0YcjoX<4zHi|ycL_c*KV^V z^n@kaXmG}VVc$6pL#%jDf}<=Rrl%(*B=0zn@(=uJakv9*_r5T2yG~D{ozv5~`-kUn ztZL^B@T_iqk}*^2hY23JG;Ehaa_%Mr@PAJ)?*Ql`=UYAC-3D~l+Ut6N-N}Aq{T|`g zgZ!+43d;>-nP4{kk^UdQi#D7Ocwa!a!@?rOd1vc?wCUdeyz{zi5ubD}%_3Z|CFc*i zKq9^1p9im;|Fu>S!?A0EnHF6e1gUES_C~(JbR=+t1`lNMko(_1XSvgxA*MG&*efNb zH$zP3W(Y`j86E6s8sZic_(8nx>3BK|nbc8XFE9MBNKU$7-fF{aLY}`6TY~4iP)Xr+x^`gZ!8MFou(vi|~Y=2MZtPMRF{C z)Hkr`cce$ekqP>tTR{Y5IvxFZU1n^L0Pg@z(V5M5?V)iR*(MYmS}2E^D9Rm8Js~PQ ziB0ka_2wQ@sRaZb!)=>r;OuLfTF038l=I1dOrf0|WOkWPA_VQc&JOWaQdQSUtR;OyBn#^v#0XxQzAh zFqHQwW!~lHrm)?VS8h^3A&x&r?4fmd>~6IRMY7q%e~oVrv5pG?7 z`mgx2_s_X+uOi&*1(hL9^FQ$Ye=-g8!+DK4Zgt?n*5kolXxW2yoO82w*Z zI%RVS1Wa=~2>usJ_-`zx0D>db{zh=X^4-OL?$Qe=06mAMd!OM$qt|TWzKzpf%gkaz z-Zr(~nW-$Ag{7~S7rt6p#65V`MO(ywJ)VKdU$FKJ({FgvbDwDzsI1Rb<`&GuUWD28 z%IbnySf8&}=j~m3jbGueHTdD)beFxkOq8St*muuj%x>Us?4gq3+zPs6topEXIok?f z!GHgzbH!broY@}*7g0+t9^-%l&xGcgD~+F>D?s6p8j_WfBiGi1;4-Q@o1}1R*@6et52e z0$E zM_V*@;W7BDF059n3yYP-wUz4n%IaKYWxcXqSy^6RSXf)H3gvLLoTZI_1y5O+gDpt% zsJ@39e)V*>ez>)_dvv(Dvv0H6d~3^Dc&zfac1z2nwj#Y#29l1av#tHT=fK1M!DeIg z5asS|Z|y!lYV2)4C8!QEPKS0o=1B-6Pb0$Npy%|^-@w9e%haOSCDP@Vg=vx8KiK=# zX8rJJ@9E+G)5D{UtpmJ&?H$nOgojKDLnY4fILD$kvJ}0#9`-*txQAO8Gm*jK25$K}egCO}>Xt0x{bI;dl*Ekdm*DPtu9o5&CWv?k)^LzU5pih z)|+#GiiL`c87OgiacQ}r#04plgH(En(b$D9t*jJ*xgah100s3KKCe;q>Piv3(mo0Y z+Z+7_R-{3iMs!#qQy8$2f+(wZg627{n}TcBZqiOiFLn>EY0HR>!Uhq!;gV}X`<^Q7 zy%UJQGn_Ekt-lL@+TniPCbshaIj*>%@wFm2<$^I>=ly%!ZP2S7jI1C%g)lUU=dPTaao9XbM`A-kdrnRk$5PHK6OJ&HYl+L z22YySNa@53G`_ioPZ7ZL6a3NLw-rrpQ4FQTv(S!0UNO9nMH`#Y>Wr*__sZ;s33t4? z4`g;*#362f%5hQ7BWJGE+A%ID?m=bDN~BQSj*f9Vjf|FrdTvhqgY&A!xmT_{64_NK zol8B5Fj9C%m`9o?8{1ghLv1ec3Vz1+PM%#0>Fdg{&fx-@v;U9-f)c|5@f;Vg#3!?l ztpS^Kr63_!j17tPldh`E;2?$LBJS#0ckUuO#S5N)95A0FqK1o|XCHNXSiN-$2n-jv zLOV#WR#I?Lfw&%A{ncl{acJ~jR}sWx(Z)Nw-0L;O$7jevs-2yMTiT0bOsO~%!5rT% z*0wviCdoO^btO}>tg*N8uolUh+TghgX+K(>aB;zfN%)eoppu}VjujCLS);Simnh9y zX~mX*f#qAOir~}iW+~{$;2P+uLcv+~zsP`Da!Il~;2pSZRqcd3{mt+ceQzsd`qPw6I6Wfut-T5 z;1byLi;#N)vLcDdiXigCEbSjok6)@(Y@`r>3Wb;y=;_WhgKjf`$vP`mW%wk^(7kFm z&*M(JgPZ4@xM@9}Z*gOCmd!#V75yyB7mUoP>dTOng(yPZ2<%}Nnq!6Q(tSTo6FDN~wN31A!GPAcOjG?=)!7V&aB> z`&oT|e+OR=>f67@4<0t6FRhKY^(`;EurTakuQ zJy4bi^Tc17W_D8uIm|jnuM=B%!^6RRyPmH4Nvy}j!_5A8j}^iNh05ori}_fHirGEx zp4hHS+V3N$7ioQ;NXE!8?>}dm*zmf4?M%1HH7$*>(N_irsxw;Q?DoQC81AGM8+nn7i4$vnV+Um%P}lcAyxMtee16wVUYR?LI770J$sMVQSN z7gWT`nt8CYrXnhzI2<8|&X5C=8j%K?J@vX1zr+t7Vjn`_kD%<-A^IPG?H4=F zse%>Qs$qSx3x!$xK)lu~`AXW81JYGQZUE@+CEv2I5J~ao8g~@5lHTdXQ5$y|9xblL zwy}M2N6pT~CBC{AFXY0&KEB9J z^qK4c10USXm<^awv&`F3)9yll$y8}_vhd#)obdfIZOW_P|;@G_j(NVllP>&q0- z{#uyvr_o$usJxHUXm-nViQ(Qo;$i3#1L>x~Wpn6kF5>$v|Wl6_0UPhOQ#-r*a zyqJgoUmO2J{Ez9R>0WSYg>p7(*~yRnYG-?Ur>6xk43+yBWr8o?>rOVq{+v6gHQMfTTw8+zTf-0?4)Vvg%svb#T=+ zf(m!*!^7Sw_Zw$b7vq35A+4rixbMy`y3XF(vvv`;L)g>r;r@nyi*@CXn~w9Av^I;M zSx_?e*GUJs(#m^`O7Y_!hza9FXsGbhWYaZI0&Lm+T^M6=N16~CEb`c$@2&z@vL+rK zCTs1(mKK{F1#CEa-I3ev3MA3=6=*kYZ`Sul_WC^X zLNgb`kg*yzC4)PEnQElnD2c`n@OwD2#Gh+uw)V1#hspSY*TU(RkK!s)%QpBip`gNz zeo!QAM|c5-&v?qIh0B6=@ms;5`&Sx8p-vN(-Kh^Tb;VNMih4mbttx~Av{E}ei?Qa0 zYX#pT>P=OS&_psNUwcKBi;$|;Oyydn$Gbd2&VWZAm3QcI?pu@98S=@bx(b+i!4$LaD zFU$ISL~=ZTZg-ws_Y(6_9I|_t!<`9l)q%52#$Tu+LRtHEm;ZTO5JL%diEt$qV4}W-6`T4WlR- z&v)@>yBTb2BMM>+J`~_zM&oN}0-V`rwirxkuo_^0Q9Ns0v_iWBh7%luSM+A*N2JiA zUMtFwFDxZ+IT2Q;)yHMiM6JW03N%Ktq!ss_1RP$4a-Gv{ z%rT*xo7fWeHjDEAILp7ayM;|Yv{AU+_<|>Y2Pai&aLH+O)}u>ah}CWrC+R|)@*c;} zefso(w$K0*_$_&?1EXCSBc6M2dTr8*GGtTFt989M;1k?x%%c%!G1t>v(IY$IhSOG8 zI>+X0HzO=;)N!)yBdlE8D6@AWNA_~s-Hj>}%`s|=BaN~3D-Z&7yl3zGtkX{R(qk@v zp`Rx5woH*}-vK(xMg%fLJ;n|;nCHUd-q{(6flC2SSr7}K6qF;++zSVmeR2@V?lk1g zhbtboizKri6?B-|Y0ge(HtB7~QT$H2C_y@KyoUgu{&$Kaze+w}fs_wN)dj!*i^8-d zmTT;}5=c(Z5PMWvUtdHRPeBy>fft>Bq6cJOlt{)@(-_tdA2D}u3SQPlu&O?(kV8A? z$(vu}Ffc3?(wck$BXDmG9zH+YovVFBW=?Xq&ahGmCX?+6P^-8OZ_gy#b5~MC4(Qwq z=XqN+;93FKva>TPd_2_*3vkw~R;P0*r4f(I3x1bL{%yXbJQ(|Dhm}d7s(uH5Z|>y* zzTg^iSO&V?*+Z;!_Mn(M-3waCRvT6k?jC{68i6nJh)r(On$sA^P!EFFt}J}RqxnLI zKfwKEz_!@H`*09@;H9XWHnrKgXrHfj1&*fOMGC z>H};9<+L?C!6?FR%XHR}B)}zqNy+b(S(fCsKa9XB$4H^UdhOug1vcN0Wv1c^dYZ3M zuWf9Oo0G$rd#ze18~!v^dv1K@iVi z3~3(32cv_m>xS(!zd?)8t}Za2;~5`LCnzf87!+h@b9heAoA*p#DLY|o2lSwS8F#ucYszAO49%}Gz>bdvby7+Tvmz1SK#ohPIh0G+^#-6?yXzX?4Bo&@7aDdqlMy)yi$!*j5qCt|(nkuObrdQ4guz*E z{LK#avljL$3WPjN5g@V1iYKpl<=+zsi+6;EP}!ut`1G7L5P# zle&b zI#%EqqZ7KdZi%c!c09TPI{XQ~)x39}&s4_?S(!f58j&fws(a3Ljwz}*baH+zH_-C=fHuc4^ZkXK~QZ z#cayyVI%2ULEdB8@A2+NmgczEl?uqD5LVdhntjbmI7B4IiniN<57h~3@fqySXQsu? zpmTl-K@UOJhtMe&Vz4NhrL$7idR;mWu?|fI+q(%O*><{3SMMFdK^(`)&UFVS%}Q%=3vv!+E$3mfXG2#5S}3`3vuF-LtFR8 zlWZRte@$-I_D9}-mQ@t!;iPbvHxVm?YKG1%^Z`B>Zq}w&w7!;}5nrlgC$zafp|!pWs0sA4I)qNF8T{c&%UQyb z;4XK9pYr`zhqcF&j;j(2NXL`@3dL+u4T=F(ZZtlOVFu)=ET>l9?@lcBo`wGLpr<7>NBIKJs*d9365=e~J41*!Rdy2;Jw8@Z$$j&~ok@l^{nuE-hOq zn?=NQapFD@Y;5hY8@pT#!A>`en5UOnEIA(*aac5C$<5&$W&k(M`xfKSbv-%RK*oCaLwkWPFxhTx;Pj~FGlY=1< zf2|{SZ@Qoq{)&cw*(K})uNZy>vDn{rO_{G>)3GNX5B@Mo) zrhVWKLdOKEPwtR-mNodrGNu^&iVf}%fBY2%z8|Q^!oDIN)#^#p{;CFFVN^j^Ogwih zc{pzE)cOT~G4U&oRt;3}50aN2BFnt{HiH~3CdvB@oxrxE&BZ; zdms4^g4dTo$)QP+e@Z`E_OB|WEAmj>sVGGOt%4JWUkiV~R!a1agul2c6Ng_*fBzN5 zzs2wmVw!CojMa2r7Jf7Iuf_kW0$K%&=|?3{T`_U|Yx(b;5R}u8!nER*yM%vDjbEz@ zJcZt3{44lX+KJiwH`MhH{ zHbkH&XQqyF-U|B?{LE7WtMJa#e+Y&GR0S1rNzgWXP&<12;L~2yuGeb~{Nk~2DDXz2 zU%_8dEu0wo9sCCxe(%L%EZL*T&O1YyIQg_6J>SgG@7>k(ka|I-?j%ir zAE23TF%^3ZwCAHTn;J6|8u(~D=Uy&j_j2I{kF|*&Y-L-tT=ea1fghrfe|is_KVeaC zB=||Ur~L?D>{(H1k*ou!TM2%E@8woRiXGnVi61;nE5*nbEVoC;ezcBg^IsohgX*RG zNcDB2(@S!8uSG>nimO$ukQfP1u~3mwu}tcg#gCy(G0ECR%{4%mL#$-hNy>)Gg1LO; z5)#(gfneJH-1JFJG>S!_5sFnJ@Y~$}-1JLH8`aX{5m=KNBqo2qC;YFckJVyISFG^< z^}n8eE*AHHvHX8e=wDA?msCqf(*L(x{!`p+Z*I78k#cBF(Y_*hH91kix7l{C{`v*T z!^3R{AxHSi${QN{sURHGa+*&?wO;jnaqx~uK6YI?xxInv!xc|7zoHkM^(3gc(TXO% z-ICuo-z$F94~u`teT9fY!Jxe68_Tm2N*sORI-h){pQ_oDB$u3IVYd)4H@;BER_ z=e?W0*9$$~mvedFD*^ak^u1mtswh={u$PGw)p|*w`|md43HQC#_8w-+J{vc(^=cY? zH+{eKhGsgx^;+GlsMd|_{JRnQY4dNZ?@&oNsQ-EsKX};pBjIf=V!a`&-{W zNSAlnOx3fhzg18rxEnS9jS)V{1+8!32M-&sm|C@11y$oER@2{Y!q??`UDplizI~7` zjI;5@QykTJg`K-0`#0S4ep#KUPfv6AvAU9kitB&h1Hzx=!u$_`;5T?CM;5E!!W#d3 zzL@Vu`kX;~U2(mlb;as~WKR}RVqt_V$mwQUYL$h@l!VvU0I20Q;kov21!A^CR{RAs zTK`>FsT5|^2%s>d(4m6w5oWX{bWNEAMq)-`@%_Y%Hj=IvV@4tA9}~@J1M0fMfeIGO znfHI5X0&m2U9pA2OtG9%2~@WCNX}@(>$+kV)$n4PQRq;?_XsoED7&r}V@6^|;p;ua z%;52Hj^oN*3-@e3tJiT|$g@r>N$=R?3fi-S%}4oIrPh2O2^Q&40{=ZQIfnt9Yhl~L zGyLG84&yJDS2KqX5nWxTzX3WDSW*5c%Cmp7F@8fQf_S(KbsyItIwx2*s^G*tH@EUg zJr(+S)ppjj5yf*ZADcXQ6rH;pbC~fM&72~AfF#^Asr;$A635k*6J+L+7#ti{`b=L`5V6-a^~O}Z(wfyv^c}!sVtShdYk7e`JX(Ld z&1tkuQ_PaWo$R>GEHN>d)PSQzioirfDMQi3fKnsCAkGNIfwI|83@SBeQdrBODz&Uk z3@9}uD69!k7FF2G<0m*1gG$-a71k7`XJ+?_!6Zt0#>Zqyg(y2>sNTG!H)ABhljSKF ztW&egZu? zYzaMCu!_g{PY!n)ne>SRAWUFzkH|S_q2Alur&fw%#TLLM0Z0LE%kZ z;giGquiqvFLJ$^$K{@Rp*w}w_5cJbVhUP59g09&ON+x?28kBwBDA*6fsJRv=!}U(9 zchSDybc^lqdsl6^R4RKz?nEI|f?1zW7a*z8*wdHZU^r3OlyvqiHrStc0h!;5ZTquS zK>H<&N#bl#IxgcQg)ss$k-5d9h~x~4EcCYZdw(|A_RZiZl~VLgm5qPf$N_(D&B8V~ zRHd-pbPT-}Y)XK8dDTZdbU)~c`kGUtTS2Df`rzP3swQM!ADSd&O53gu4tgFkFW4su znUd>XS{3xB7oL-ZOi6VwtqLIX!}J6pTatMkxzkIq0?7PyV3LrDRJV`~&Qm;{d9g7` z$dvN!rCR~cys(`lWP*Pui?bo)fbUKs@jABm+ekEje%-=0WE}8JFj3e9SJ{Z&*Pj#7 zAeICx85CLQZEFzTyMpbV!RcH&N_(+B(caN=eQ+$aOE;;zo=I|>mg<8eA#s*-VmU$3 zyst)frx)>xq*KuDK(p~~FfC|<^THIgJ5X)BlQRpNve-$GgqDAKMZ0EivR&6+wj?0S zN~UWc2m%zrP|m_829+|tc*#xz6R6nQoa6L~!KF0%B{c%}!*xUIx_K`uecsFYK73i5 zgJ;O=%Ga9%rqp>q2owS45jHu%l+@S$*Az2i3j=TV#*+<{MWF%YWQoXO-a{0}*wod& zWjztB97 z?%ilxe5rY8Kfe4tbW-^8?#V4&Y6jL1m!E-63@!n{!lhRC=+$vaN`| z{JQ_d@TKImAG(X+^4m8i2A9%|{jjd!y3Y7fWCqGclMyT(F0-zD+k^VrfNHDS?=`DE zku+qKx1wOLDND0gaTFXA;*2#VXT7p>2T&-fTHv&kTr4MlbsQ8|so%_gLq(zM%1qQ1 z^$;64j!NmzW^&{!xTS)E>tG|dihLZML@}cAyv;p0{y41#Y;bNMfO*pnUnd2a61l5` zW;y{(PYoson3BS)gR=txOwSD_1=tW9#M>UG*M)R4Zc(g1v0>VuOti#2I6;!G(bJGg zb&ZzLgQJyy0H&9NCk2=m+Jgg_0HzHClLAc1ajyd^l5&8h{(<@>`CFBkf+iA~*9!+A z`@NonPXJ})@6=a{g-oQBf{Z#*`@nlwnH0*{6@w=n2}^bn#*grJ7{(X8S{OHJ;F^$b z)Wzkz%@7~(6b{TJ0d-FV&y?tB>M6KYsC0UDqDPg?4OjVs*HqY>jXZ%b!Z*r4N z*Q|-RM|0J{G@9oZQIeR$I66DSk~wm`IXu2oG7B(wwKQHGV3m(a;n&NJ-x?9 zVyPK_@=|ww@j59S=YLhcXL1{TK6d-*;p|?!b!E2elJ@(^>7D5GefkiekYV0`&N6*~ zFZCdfuT1?sz_H`BG{UwYG+*K_>oo3T#69ZahHlkv98*Rt9x~fzJBbn?BaI{*ZAZsI zl8&Wi?vDqxo$BKTLU`CAmDOeQ0RMeqW2~irRl9CeYMr*L$TXiNuCAH~tE-Zo5mlVl zu2xjUK#B^oRD2fF4vSD3azIk@X`tCtuRHNe{NN$>jWK^je}09(BXnW%NBhMR<$`&z zAO%yjs?{cGSYNCpAWSOjZC-zXqNF`JARUYx2mrQw$+zq)M51MQnC~cPCB4&&BiuWG zA092P#kR41aYt~=bBXWmcMAiL(U2kxT)$ZkO=O1xjJS_^9P%yWitpl$XZ*8c`5cAl z8zAYJdM6HzBJ13BO{78RFAD)Y9J2lDE=k@d_Oq_B66QLS3{?fRYR(fMEfg42`^+L)(kAVW!a?!0R<9=B^OGmrP79q{##MCK_ z*CzGfhBSaE@s5jb-d{q$2ZdGnT?V!)LE+7-61cA|uzzTGxrsy?pR?XD_Y5yi zIAr|J9bVkEJ8*b$(n%ix=k88yW97+%uGrq#85?0Y@hb-Tue9N9gstGp)J{%d_=JhZ z8)7N0Qon#CBBdSkTXjxal1rFZr}(KdCsJO4=&iE&jHe&O{MR8MI;he~8EdOQJg{Zj zQL{Q%@fpqZ4y}kEKgq@d6(>cu&nqD_*pIPC09(UTEUKhO!dFu+GSQ94y`Plih zwIpVj(S3Gk_F5N`zNCI(j^Xg<3djQ>`9B{DfTdaEZhwA9LOfcQ{siykxZ97zZYY`* zTPziRAHl8mt1wPL^?8C51(b3k>YRBfs&mi$4kk#8nCrAnE^y=Kyjy++9;$VTvrbXoYFE%pfYdAN$S`E_ssu#ARJ z8)nG8i(d&+Id)dfag+$~WXUD7y;=UckbPxIFG5L5>FG`2jnpJ^-O8$2=>$c+<|_M8 zRaU<^!TzbuT}0twvZXiQx{pz;Z(Y68=pA!;(|=?Ahxm8^DrQ%uQ-jO`&xWXZ1tF|2 z3D!QsOJ!*Z4uDtJmgqrv&3tNPL?K4ump5!C288ocaaAdkD=kOU%--bOnFLRTRFw*q8e0p=ok4Pr(9+=S{V;g5(Nz z;(v?NtrplQ3FBs`-9|ek+ei3VU0X@pfV$E~6FUbv?5q%+)dhlIUCI*XC9zu;-E4&y zSQ_dY^PmQi12@iK+10rfzf$*CC_Iy3XggCnzW;@(E~-^DVGoKQ_b^m-!Ef+nk&7;v z{m+ylCNkZTk;^X4KjgA2{o8$JO4$OFPk$+DbG}R&@-vXEz!u?2f^g3#_(5}LUq>gQ zX+&r3pp{2bWo~g@nm-ty)&F1}Y??Lt!&WbVlik-o7`XFKVmj5WU`J6@yNH-g)&F^qgK$b|!!d-SOPe}B?m zv$4VhKBdD)##8<1#=w(9`SRTIjZvO;|0tAa&@rWOXr6I|L-Q%G&7m35vm)Wpe3`03#_NKyN1{))#hZ%GaLxRJ6dj*I2 zNWmdn=^kbmDVMKZq+EsrrW}UDEHI_UVMZ1qw?Eu-@w9={!RvSCeEE_BB%9>zf zrD1)wNy`KQ__1jRnr34aef*OFHXMHy358j6jb&z*yLW@eAifd_l|(^;f}fxeDuqNe z5>cwQrSbzPB%%-n5m7kj?zus6a+7(VdCz;!y>TdjC;;re4fGV?S%_7EC7om_#dumO z{DQ*z#%CvfhCwW&r<0>%NJSul`pfNB2mMdgfJOfYVlo^~dybG{9xZ|?)bD?`=iaFe zp>amNR4^9Gam8S<_I!ML-J@Ov)-w3duLPo~-9y`|@rxNh;o2UXmBK7iYt~mH!e&iO zWwO3+%jr5Nygw)P^X>zSr;{*q<7dzoCEp@3AhNE%#;DKkkqbfL0zc$qC_ z$c!xfq;MSJaNi2u_uBeCX=Z=W%<{KqB_vQ?zWKPv19qx^7n7%iCwvj8DriNyMXl$0 z5us>i0Py?b=yaWH@0B^r2B?{`ssD&nhg+Lh~}_*vdAZ zQJo-n^stWsbOHnC6Qly$7Y2^$8(P`gyeMY4k)4M|Y^nZjy;d8SoWC(F_cLprn=w|# rwhk;r#uk=n0XhR^8KIX+&E0Iui38no?s#C=Ae3MtGwuHX00960t`4R5Ha9RJ zFgY(WGA}YPF*zVpN+3*WbY&n#WNCD1Z*J`33jhEB002)i0RR91008C%0000000000 z001jB0RR91004La%w2VS6vx}&g%Dg5iWUfdn>NoP#i2m4;_mJq+#!br_aenz10jOD zCxqZ$iWPzshhhQteZDi9z0392|KIJW!{wfx$De1Ok=;w7X_}sfo5xAH(VRcy|3dr; z-~E66|0P%zm(H!u|KUPwS+39W8}~MexJTYE+pli-|5smk{O;J?KTFK=8~OR08)o@g z;`esr)*ZuteRk*e-=AeK_wVBcT}efL_7W5&S5jVizl5d`(9dqYB=nQ`MnWa$@|%C- zkcqC4FkL=|xwS>xVBo&GOqo5^uODXWkdn9JrCKcaHS>!kF8k3miJzv~pk(ebm z$)UVQ%931z(@SpMbts_{kNiHBpzeOpdqG9=Bkz}(Q;R!a3#dDX->f7|E0cgqt`rZ_ zhXIw^cqjTwu0Dv*l5=Sz$%C}7)R^Q`awzrSt_^RNPsu3nbk~x^;I3_nM_NJBl9Ecf zo(g`l2r1r*&+hj~{v~zE^FQJq`F&EMZHZs%NA}GqIF#Q=dFB1`PD#bxXWX?aKTCg* zwvgY*&r)OV_e+RW+L=a?r(M}|WwxnqUMy}L7o&WVIL8)zlw;J&&>NeV;qCS=z6o89wuru|~PW zpG@1j1qQTK=P2#R0Q0Fn(8#R736|l1b}wB|Lo?{YnM&HeX2buEoJdI@A4+VJ8mv#9 zBg3g>cpDf{_=a?*49X-i(C0g_rUZjYZY#l_gEemsJYAWj=Ye;|RVCOV$bA`d&s?0` zbgpe^YCnV<+ZE?Y!DDhDkBbVUww?UU=o6`poC;j|3#;WL>qcwav06itYd;z}@I z?rar>bZM?lq&3eyeC;t57Ksu<2Xq*L1o$;?PE;z7kA0-7)q& zJ?WeCROM2Du$Y&ZK&@#J&`4^a_&d#5Y8Mxt*ka9b+Z;4CP6P%lH2MiJDZ$pmNoSx@ z7DM71l1MOgw!=T^xh%#iki=C9GChP^LRU|rTz;|is7ez5*GjNMUl?x=kwGr_m<4lo z5S;&}1QRGkvotb@`h}iJ%()BvXMA8l{wdNV4#l|(tT>0S4OW~x;H0hKuFBWmO(x%O<%%jzrN$9mFZK19ee9c}n;*4>M^CK*iwuwDe zYyHyO)LzyRg4w<%SbM}uwf6O0NZqGwPb^p-u$Bo;n*#j)%`&nI7&p6E0Tw4#OY358CG9~nGu5)= zM!XvB-a_tJ+#FW%G)=8)n%lfb8Z-Z~g0^6=SjqoeS0Uz|OgpIDB406DHed@k!C(Qf zcAP2bigtnBCyXTu`9qNHi6;AuziDg7V&?AB&5h!Wd>fFTL*hd6x3pawDcka70=YA} z=4=S$!&v!NF8-i@EA=xl zkZ))6T8~3QD9v#;3tyvIPmO>)5~*h|lsY_F7?th+hIXDR;)qL$oA^4$5^6hOl0#h@ z(5j-{srRQ*#*udk$h{y_2IfRxRB}5t$|;dISIGB)wfbmQ-;Sg^ojy>=#fgq#iu0N* zvNptvrMp$9H#N#LokryT-FS;ZA6EhXU%v`xI`nZn-OHHS3?JRy$gWJXf@xcGfFfUx z6BIToy%4N@iUgBz>{|MHZnWXKPEf!;Z}VfZNW&k@;JU~ETi?U23y;1;Yx)#04<`#Z z1}TeGXWaTN1V#Nik@V2vXVwV)#Ym+r_C0#PMel)kH&EnEUC{o(Y7`c00tut}fBk6d z6Lj-vdh=+NAqHcU_D%+-n}YrQ$@mdKH z-{1^lg%&D7dzy`)=>^9c9~En3SY&GzR~~v~fpE%_Uz#L9G2JI!>Sc#j_R}WyIIq9EO`EW7^im)7z+DfVX*f)Fz{g>Rpj})E=O* z#-64QpMA`m1)duf6v|s8ZGn;&CXkKjovyoASfeZZPWhiy}Lt1Qp%7icoXA!ji zX!`cuMk7D^nx_M&8edfJeUSTiG&{0I(7s$U{Gn-q_ddL;GyV#z5<#gA2`IcFx8>NyrK#xM0`?{j18rc}>Qr!9aq~m@>_%thiZ6i|<(J;>P)}-6Ery)g z%Nw0I1ck*!h5d!2#JZ+$pubkW7D;n3Yq>Gv`#4Ap0}6$FX6wU7K83s}Am^Ds{bIw5 zv`zOjOBZNp1k2>y*Vo;rmd8wErb`gMdRN4 zCmw-YLg%MZ_jhA&PQ=D(H(5F_C4-f>j{3QdN&0m(35jG zm$-zJF7pI)_)FUN_=E1xcP3Ix2PN1Z+{gbXR!dDK7-t>L8tSR@aMfElvhYWD!P2VU zYk^nP$nN0m35;tw;TN?%Y1?YK1%r0M&F;Nlb3{v%pyEo+YOr%^+L#Uw-L@z?ZsNpc z6)sbpQpSv;Z#|sGT$Ni8Ou{=czXmmESC(79UnGda!WR&xiV#Iy zgpOP@X_o(;6_op=NBN$YA$kVf*>6)|z|8Biq~gw!_V4Ie6G~OIi=_^AtV)Xxe0>Mn zTt^3KPt9NH+VVvrx72@=FoVv@RV0=RochageaJD>$)k*>HB*J?LUw8GJbXf>y$sQ@ zj=}gAmq-Jz*xB{(*R-VWMe3VHhg(JorSoKvun7NeJ-O>+HhI(D++47)!PTD3Ow}>e zqy%feMg#?q^ARI3`-oV((-y*5OTgOI-Qo1Piv;)K;y{do4B>?eP*AkzHcs!~TG2iW zxqn1`K5BP9bIH2VW{uKLqchVM#o%8U!oopeMY|4*i|4?WrjS3nxx*-?T=6_)N&^Nyl#irBlk%FCi+3};)kp-!<<+%SI1ROA zt(c#g5krlG-9a*g@tQ(Bpj*==D z!yNWRQ_x+`tXVy-{z?_2htayH9}Jnw5}49PVP^5ms=w(<)_P`{6RnJbN-%N91jNFn zArolH-A7cv)*d5Pm68g9re!SpoC?NN6b6k4!??KWacVz7x>U>mrnS9)5nx;Am7%p5 zu(tW#-}G*p1S@;GaBC^5Kc}7-ByttMnt>oHjHXBG=k)r|;sSYZF2IFSCjn1x=EN54 ze4g{hY~*QN^O#Akp%;5D4=x+yS#DAM zrw4c^kk8KLWsXSMCb3`{02X07Je`;M=38q4hMxnVvA0+jF^;Sr=F+wgZqqMDOq#kE!~VVuJI2Y$y?eW6<$6=E=%ay*~D1LugJ> zd9(!W{ZR2(M-cg}la*!z9$AH_dPDA6XjI~g9@)XsPg!&tceY*u{Oq4%wCd3)>Nn}2 zv0k~$La=rj&78WY=~nhU=7LMQe+uO;m>g-t(bPVX-1PaQwOHdS?gf_kI)nQ*0{O$p zadf=NIT1wmy5cV|^%{W7dG!l;_o=r4w@_J;mpf!>V;6(IEgw5Z!iR8GMAj(_Z{AR` zJzcom#vIa3_rIW6%Y&4A4#Ux+dOqfZ`5n!J&Z$OS6-0MAyu?Q z3w*J!$#joDB(6yij6=}UD{K#@$r(I~gOj)^9h0&?9SsavabK<@ zH&>o|8!|mdqsDJ6fsKJSaBT{7cOC@O%|9X%ryfDJElg58Q~!YLE9J^y zQ)N&AUJVq=pw2MohWKpz$nGyBcNa(W$|CMN{!J?eF=0kngKwAZH zhKOjxUh+J_3bV>W&di(7&}v>t!s7fNs<%H9_IhNmD^o^z&SpS|t?rZ2)`U99ZX?&pl=)#0WQq*yD+ z1-g!fE^X1CK-%RWOLy~qHufr491TDE1KFWpU2n5)>PBYp;NHeC6-0uy^DyYOfm`WB zb-8k&rvBPkEQYjZl?3|=IhNl>Fmh2dWrH6@gZAfpv&oSu ziEt(kdRbcVs=iZ?hd-)>y}MF%gK5jsA`qUC3@Bo|_oVpH5Iep_@;Hm$U(wq=VRu$) z;T4l0D=B&_dq)^y26H5%M9AI3n^Dk}Fd8$}&z#|GV6<1gw*c>Di1&TQ2~@6R99@0C z&G=O*wF&TEf?&V;T%teE$}Np#UIMG86-4j$P-?)sg;e{pNBAG$+w_%C>T6y<|7*2J z_=hnQmM@g5+##~&BgdBb1kQhflfH%=N#9kXh8f7bc;%o`U9pC_zy3SGUyD4WvcDBG zLw7DPCMbLNL)p*~?ANOrOEH~Em<09~g{TmK7kr$0OzpFjBUFOfVp40RAd?p~`}9yO z-Iyf7Ja7ex5R8IM0>%F{sDOxOM%tdVZM!sRG~*Nob%FnI2jV9qEITZ>0i-lbiIzMx%z(8gwdF{;fw-VyMF6 zJYwa*Qs8t@*hqwbuW!TY?Dnw#k!4}X5`HdX3g)a7=u-eErQ5mf4;!b^`s4v z>x$Jmn}~Yt1StF@ngrx)A7nSCDnCDp-Y3ws@$N$7-o{dmLGO(0iZOnDmz4{@YvbzN+OIt_16imGvcjvsNN7fHJii zO5HDAFk(Or*Kce~s|y0S{hf2~|_n4CP{kdEZ9Y*zcJoY7S&^#?@g72H#=^;Wt$_Mt#tgbga9 zWIoDcf83*bFK<=Yn4#qEg$)Nm=F@_{G~oC->RsWCkxLoW#oFJGUQ*S&6@@|L6m1vy zYr|7Cx`Q0vQ96hK;Ux#Bz7__ZVx1zdIJuz0SyGPQE8!?TfWzIO+*{`JNvQkZLg!&u zdyw~GY0yRgZP3Z{IymeCdga^>)w5fr$ju;g2dKua4SlY?7Kv=xf0rn{suEg&|3n7qe)K!@d0JUQZ$up6DhSqYu$WfE&C#^8N?!B+ zoNmT$6-2x`XK8KUI@-};BVEsa0;pZF9gChVnH77( z(=YBPgISfn<_ogdP%w^I)`XTN-6)iLg3-we8%gN}D7d>r59JOip%Gzx6l9-*^S7X$QTFVzy-C4=JP>4rh)mz+h6Ra7HM$?TXl5^XU1^6PYTCVyy zO1{%0^;Ck3i+egg3JjQ&L8hKo{H@@;4nW;uP{nzk8?{^uXd#^TES~#Y+NAXX)atvT zgk_0;BtlJV4^wY}&Vyqj>GCT-vvrzh#!F=}aa%7S|HH@2yt=ND2tnTYl~)(U?tCb9 zMAAuAINBowJKLNei3kiBkZ?$>jMDj1h%68(&J*pI)I#qdIFtK+Nm@nQ4?V|%^Z&VD z0?w^&;M{$`B#)w95Kf1cB3o;nPlh=*s~8k=r)4eZDbm%X@CC!DOhk(yxH*`Pfa2AB-R zm`8mLD(dw^gXwyg^>k)=1EaR0y^MQX^`P_fg~rnQw~s{_e6Q3}8zR?->Mm|rMg!)1 zguw%dTm+m?jtmT_{Yr+xOx`^g&Qt`3UkkYv?Q-5Njh(!{CUOfeAzNAtzD0Xm=>#TYo1^x}#shCxsP2F6kBvsh#n8F?{uu8NORe!Lo>Q-j-U|8c(rX<-3i(?^NjQ49 zjUPkT#xD?@+na9?Ltf5oHKSX%YegY$R5n+l_OBVI6lGgNxZTh^uE zJPnlU2jq%#WTs%XlM8^x$8&-#_ssOi2P-JqX#rD>duIBXNycNIl|_sbxJ4m{S}H2J zyTo&t^g=DG)N-KWVq=pEq6zS$tbB`p`PfNHcG+84>^jr-2JIoNe0?-n%eZnZ4X$xc z_}U|u=QC)}WWTVQ@+h5%_8djK6e2Vkf?Uyl)xW&4MbWMTaCS5``vgSF zgEkLvmUaU=Z`5!yE%TE)U&6FMfi}k?S4NOd$vv*yImaZW)WHyJI+~JIT2QC{V+Hct zj67vxr3M^dLTAUwyvDmTK_A5A70AVB7umIMkiiiwYGko!xd`zy44fY>9!!tENY;=B#fr%mWCyHaXxh4oR5@CL*$}d3 zYJ%)g61`Oc{`^IIgQ?0n(OejGKisv|?jF?Zw^PEPKrTYOFL$)qE1#4J*i@ns__~8r}=YN8$@6o&LkxBG4RL+4#%@4fn!$DdWG}Vesq0B*& z^H@H|B}QNj3piuq)Gl0~Ok0{t@DF?(;&2rA{tbd1L9={UN;>=`lUM>9#Bx`}si0P< zQ#Y~+?D6}0OMl~`lKU0HD*)D++ITKG>Tadl?K>F@RE+(~5UlN4)`8dvDxXtU_m!CT z0nnZR(|%zS=y?LX=;j`|UowJs_I?3v-jfW{y0eljg*;F86-IEPc?sX9X#v-xY4}h- zGwtNPhL4(;@aCISE6Z~0qw_>k=O{n(&GbITEM*c=N@fP50YxHce?wWf^yP_%Fv%Az zZ}9=tAWI=%I)A!xpJz2946Z|;f1F5e!vETLg{qCW0PDErx|8 z?F*-GJu>$W>hxZM7w`tRaO8hr%lB|sMZ4v$#zr~jTuf6rJ#xN;bXylj(8$zsPqGGE zLd;8=!D7BZp|m!1z%!!&ER3rFm_Cl)t#ZDkjjbz*GotyqoD)^gO@x0r^xofeJ*6rs zPaJ+>lL)n7Th8i^AU_`bobI2hXL@D0YP?bQ?g9#1`4%hnkeAeJS!G^gA7}Js&czDZ zYkA$upkr_LW-HT%l+?DQj1qpnM0)DqNF!o6KGxy|rFK*@2j~6M_^3R! zAwWkEz&z`qJ{jwoaWlplBJw~sm?3%(fDhLEjVA5%7E55CmDV_6YgS{3c`hP^3hjR+ zlE-j$9O4v{)+#VmSIF;_t7j|`-0-*Cfww#&bnM9mWEGd*l0}7oUYMGv=RuY=DHWAp zlu>wUaYin}KN-{=$=;%O?frtNL0vO%z23%Q<%)1B{U2_u=+ZmrU_rU2>BV1&izic> z6@rhQ$Dg1fohA4ub=Y|t;(H4k<*890Um0T*=Mo3ngTuYeY)2ZJrM)*9$2kN&=l&h} zRL+R05TY$wUueSFxBd&;JHLNQAu_!duF1Z#H@1|Q&B%Xx3E z|FPocqqWlvFZOeh9e57Rr!XMhwngV?-ZZ&rse(jX0kW@9Ztm@So|YVw;JTdlMDpl> zwD*BY>q_SXvXwPnsO~?boXZAp8NPEa4csQPLs6B_alF7f0}9!nr=$fz-wBf_rD+Sf zqgEUg+`%ZJMY`urI;VyWOuJqy*WAmPsFYd_j`9Qlr5F8k5EWXqhC1hJW86^b9{SQM zfVI{7TnZ>3N8?srGn~p>KEfS%N7Jc&TjgaI+a%8v*_~5BVJD!v2{oS4+p`kP1GF@W zKrWhoTfNNrp%SdBIgQ6Mr*;W)r}_RFZ95{tf2zdQ+l#xlhZ+>;X$~(jrYXVBz?ov9 zn=QE_s6%N#v;E=`#!o8z*Io`yP|l74ngxCk;HcC9WTUJOpCSoDoM&3z3=b>Kx-Ib|x{*<-$$XVAVJLP+Y;2 z0m7i(oHWHiwG&KFh3X2-K20U|NN4(}l4fT{E{)%=bOuUNP`U$@AufBg)ZD?0SNd=i4l{d&O;AbOt$S0%u?D!^wqb&3-U zqW1?N{{`N1*)fi$7P03B64`skE7;RUwH`;;DoZe9lgLwXa9a7`Q40CPV(rAdM3fd? zq0a@NJta>sdeS{g43bzX6k%|Z9Yse0ZmDIc;64o;6I2+CWPmjr_l#TCi~=k6r>6gW zHD0SA!?a1PVO!O1CNrzfYiOn%-@quMB6JqqfeRB&Z}M_8WyvFlSgh6y+Csb@5ME8! z*8hFWA&zGP#3vS<+GMcbHFqbfnq&f*M|v68ltD2K&}%`kkr zjo#}eeJfwgta97atEUMJ?;qG&-dvypqA;+gQ&>Bg;es+aATAT!5Qo-R$<)P zY5oQZn~>ZzKLi`2m0GSs1mR7c2F6g{zoeh1RVHCy=q>hvcken#i-*0Y6n7RG4^;14;86#Py|=egk-gsL+`qdRV-#z{ zur|I3c*cisrEABfw|J{^j$KyMIHW8s<&qHERMp!IT(!ZtsCwsz)-r>@>#64`=%n1? zQjV(CVTI`j;A?ulbF^ZY1S>b!A^-tt?Vr(SY3+Ck=6Q+q7CuYr#9YvI1f@ZPYM33EI7aE z9-&Y7UUW29te*hqFuGo0d?T9DdNl<^95X)Kf&*VWjQ-Vb|4mtE7Bewr>d0CXoUedP z{Nw{~r+nH-D@V(^rHe|rk=$873H}uF;5}OmFXd}EN@@9`H;ukPJsamSqic0H#xZg+ zNHz!Uzxfue&FwI%b4{lEAU3ENB*y`7F;Gywf34^=g1NWIiU#C;Qx5Ob zRYn#(JjGC>dROt;X^c{8*@cenfuii>XxhC|vUXmv)}J}on!_&9gSXPl@8nPuuAU#; z0%xiQrIx%LO)rk+5pzL5HD%%ja;Ii8*xK;pd}_H*YK?6z2aA>9EjfZhW#l&nYq(Y| zK0+fn(yU$B(~>gh2oV_>#&3%+FEeZU6BSbUMqRi?>x9IR%Zpi4U*lgS58*AC?P_h= z744jgXEav}ZSj5Cf%hQ(QqO1>Z@vev{{G76B5 zK#?v_2*vi4IhB#gDCq*H<6B&EBTAT<+(q8O*!2)p9u5BLNp;f7ktjR+xftG)BVjWF z*D23SO(!@ess$CU%$!o>6Qz1mu|lH=tW8j?eP&OPy&tbUMW1KMYVR6r!z10R-kCDS z80`J>8V!S1hU#uDd`bgv{%98eHcBjsh$vYF&fjoZrWM-}PPK+gN5=aL1n1dUBUTTV z(_RWXJ8**|hjPW6&`4A0rFQ<|bfe;YI$Cytksj#+*Gq&!TBzl2o^UD{?PLDd_L?z9 z_2#20{IC+5ykW64CrNR!T7$GFqGS?!KS7iI^HzF%RVK|aH7CL&&3ZQU9+TrN74znyjK&X1r=RS&cgCk(0LW18<95zlZv$>sm2;kMO#2b^EPuNO`Rdf66n-* zNQ__i;nbV^M$oK-GJsPnZxJ0aSlCh0xkeWeB|F0ivtS}|@ljKrHLz9n zRpTQm`m=N&&;p}RF#&fY1RLTv4J|BRBdM>tV#|=gjWl+!;PyK4u=0{QA zRX&1tF=Y}ydF<51`ro6-NUA+U($2(bPbAG&jNB@K^yFTMmgaAT)_fpxaywK6Eq;H2 z(%N&d_6eb)wDvM|i6hdUuO-~CY29v(rr4-p%ARMraZjnmhH4K_ouP(lJ!a6!L3<~f z1~Z5>YX{#7@_R_jeBcHkQLXhkEMHA1H`lE!3y zXuMPzIX9A~xTi|~q-NNgie}dC^^8lZ*F8Hce(XAlynl?N2{q3cg%icMxOd9nSSps) zG)L5S8sq=%=R>!gq>Cq{uc_RjXz;%k-k+p*k0dyoatF>L39Ko>R)_p77SMzv^A3`w zg}@{qb8e$LKg)a`&hiLHJ_XJj!z8MAl0HX`uK(6r$q$dH1|RzMYVEeLAb3jwyQ~|t zonoHLQSdvpLdFkqI5koFEN8hN7dOq;g&T`Wk1*&wbT5poSf$|xvPS8`Q}?q;+5j>T zT$#32@m0blEYS@zZMA(O0R(pt&V&iJmY*9tui@a1J#EPZveo$(T^-!%Un1Ceuk0-> zE0zX^7TZF_jwLgLm;7R2rY5dxXtSXCkaZY+zv?kn4tiqnLm%=&lF<(#l4ezYP2KX; zGf%&rZJ^Q=8JQo@u&lgbe{$b3ACbA^eA#XXyP08KLXh-X6nTmhDN+ zfphAKw}FiMw=<2NzlFxe$fSvlUNKlS1lhlN=&+Xt-hLiwaQ!J+WBK`1FI;B!&2h9g zMsC%DHE~ER99-3hN#5NYOH&(4Ff`o`l9xrf#4A5e{E_Gq7CQlrOvQqV`;|>u3}>!1 zJ`?6z)9jxm#4%SXRg{v8z~7Z@PWmCuBD%i)kZb(rr8P^hi=gTC$20nLq?jm*E-0PP z1Jhw(pv4a%bYzb7R9^6~dD=W@dvdB8Wm&7$aAD3*YV~6slj_l{wVo=C5W+d&JJ&EvQnkS02n&`-f*eq)* z@2(B5ELmHsW>kDOmQQGdHPyT5gawB6Z?%Ni2&dzVz0Cq`dK;zGoXDjXuU8Rt?UO{# zPrkY7{5b|_rE{-KVUE~DO63QBEp7ZmCuMy-pZ3?CXjBKo_EiJf>qEKClrF7q)}8Rk zz^=3FItS#hH@=|grl#k3MA@% z6*W^SE@OM8m0Q%DY-CR57bNh~pSvUD^)6-9wBrbe-Jr#0=3@LdQVvrfXv8%X0~?$Rs^xHEI;BlJ}Bhr*a1&m}m~QX-b`5kE7XR zx*3mIFp-gKBY^WW=laN(CnycC-{anNtVWSMHo+Q4+2JhJJIR0}Mt~aTLg9+LVW7?j zqA6=D5_5k)g}gP?-4P*}r9c?HIx5|vD<72>$X%?tm$9}tEP_6tfHilpEmwDFEekjH zlW)M6^=-n-Le|41q1+_uZ95C^c<>|INK)>|5jp^997I9d5>8x+kR#W)E(r zu*7o%ao7(K>>Fr5!s!2#Hp)?}0NR>dAWma9Tj3M#V4JlxaMD4Zy~W51+8coUxu?Z!SF8iP!Hg`C&Jq6TEU#?%$DOv# zc{s>MGOhm&t^+0;bCXDG|0v}AZp9$22FsasFgRwK}d_d+b~4>azy;}z#sKsLQ6ZQCS1z_yxc?L^3DefDgB5qqZF>s^oc~XI zixr7@Sm=NDP6_0K!v6+?Y$|RNY0cJoOO`?V9_+jKw*CAjq9iLk${lQb3-?R7+`-$G zw}eC8{ASO@AvjfeOI@g&E2G57ZM6u@cy~Y|&JzdG8s;w%=Qel%EGAI6vnFaRd|Lu? z=l4vSwzu?W5v|`m4Qku_5!R<`cyc~p$t}n(XSow`epbmXz#X}FBF@DY2tYUBW_&U_ zvDTOunLO?yVPEp}mKlmRZ!2h)ScO({*XnW8v6%HD$nuf{ANT{Va$U;MxZ45do5(^& zeKq=b!n7p^nsr>Chs-%mcsOkeA1V;b5(0&2Ccl|acPhze?#J-?7LU3`A@BV@sef|t zn)vE7F1dNIO$T%4ox=vFXwPe5hiE#)TUZ(1_cV5Z;lx+Qa%(6}M}8AZlXI@woa>hT z8Td3*p`Xm#x3e199Tt$vu*NX<2`$raUFl17EERfj$rz(DHax}J$v5kJN1Ubl3yO(J z?sir62!%Cgu=VGg&6FWwJ4Ivn5miqtJfSsuU#`4^?qBgUyJx&^OjCkY0NFfXBPQ*6 zn%nXxb6d%1qc*<4brj+C4UW8b#53yowV0W@$5CUj?Thj*Zc90y(`A17GF~hf&a8Qu zqeUH8 z{4a2%^78|z*Pg+f-Fqvoh_@8#chKD(Y^R=|_BJsmdeAVGUZ(dpd(ItYBv*^nqW5{s ziDnl*O^$bRmCEEZCjU|0<3Y$JDz~_3s|O*=lrL!DB%uo;KE=%*Pw&I|0L|uY22ZKw zl>;Jgfy?C06iemC<~1LjcxPZ#7Z(;cwI*CEYR!@*GwarABX&FrB;s7$m@@TxY7#5M zpeUpB;9Sk9YK6UYtgsE9Kt$7e`1GL}@2Atw1_z7=iL@qeNpE|^x#l?Sac7$~(1sWq)l?qF(FTY^t-qCPm5esVNAWKzWW1G_XON`(A5J!*|(s3$%e_;cCUX{c@ud*0# zjqw3gMy?Ot$|nW_+lzPgey3I~8Zi{l^jOxOTw5qRzr+GO)K{xDIC3Q4(5lqZF{X{{ z)f3`;_dTGvOL&S}Kz)gNrW!ieptTP*m4zm_`Etz5mz&rJ;zNq(lKqs+wL z?-b&iguzywyphy)mki*MtYwir3Ndp19b47jlbk$eqGPTK&$pQGWQ5MG&BZ9=!?84c z{AFXe3Zl+nn$KN2b)A>Da}O$Ro-aM$(3MG+!qkJImcW;1Y3D$>NDV7UO9+*qxp?&~ zmF^?K|3hnQC&p5jJ<^~d%=v$$T(8ng9Y;@1uHiF`Oy-1Lz&{=z)MyJI3*Eh2dc z2K*tWPr6VFd?<5jFV?w89&zA&1RB+QVU>9vr(=3T?jP#%Big%s%V{26$+VZ7ON`7CwlCc!m1*$CRrz%)PT;nWmz46!qn&Ut+;NZW;` zV3YYY>5R8|wUyJb6m8y}c4|X0))gKo z#Fd9z{T1AGwYHgFZj-%jSLn~kt+YtF+y2=^!&XZ$9xrx{28bDZs7Z3RjB5p4P>4sp z7I305ZN9xp)TtQnMeo(9k^6%`H5yc&AM2Q|{Jbq{;vu>yaE zO#PtQ{W*3}8b30t{4&yrL)hTrcXqQ6vu*V{rM8fN^f}s*+5OC8<~u;#glON-sXe&1;VdtTi7LW`wGg%exc& z8g2{;uO7!znKu0LWu8%WVdNq!zJsw|L+3STZlb*zC2~gQS-z`*szm-}uA?`6U&8f6 zli9TWvowiaLJQa`45UZD&ZMvqSrpmlTYiSR`Iw69Oi{!0DUIKhQh8sU-x`JH(!K$E)k7P`VO`aV8)xA8?ORlM1GDegSH=SN`g);to$6qAX|*4lXV{+_jKJ=jlY81luR?9)h-sMzMCk@Fe3O_z?5ucV$n@f3b%G`pr zUk`(-_@0^lj$^g*wZhN{p#-?~xe@)EW(s}LqKy11h^~XR3n&3TJUUI@Sxiy4*amem zkh;t!S~x+m-lWFTafIR)WbCkCmnJJ>@i8+z* zwL-wob*EEXJntNxzv)q!e1XDlgTJ~l=P7F*=`CK0C4PQ`ch5OJ={|YRQ=!kYxBYn8 zeIy2KxmZf>!>NM|eoja#l`Ae@=Z@#UCf(XVqkO#05Hel>ApqFw%iwZ8MZQ0Zo!)Pv|{Abq7?)4kEt!jYLkYzB~1h98alHpahp@KNrP6 z-hhBdu{8UT_w|>(91B$Oe+uD(2LiP=fyJonfx)ym%P6A-b1pK|c8~=IeM9ze@-}1v zew&pl962X^cnsfTpX)KMgo_`n5WNpU#6}RT@Qf|gbe4SZRh8#j0U+OsX71w6G`Wv1 z1cTf{uzBdn4<9+TJ0rKys`0Y73KEU@MxFQXG_4$Mp@NMhxP*%D3S975_m}~DlG`g+ zQO6}kydiUrH=XeVE|2O`Mx!T{T)x3Ltgvt6=+g?o9r`?qp+!IVnn?Fe|Lw??=WnHq z=cQVBg639vFk`NwsN$75uA)dlMDymw6l&H`a?U~JwiheF&QVk8j|d57sApcQwPGsO zh>~Eok+k;!xWgT2O@)DzW*S}$7ABbqnf##hg9WEhxnE^(`?!;fHRb1>3)gm>RBCa7 z5B(iLSw0S-w$a0lhr&%6HW`C&PSB2zIY>1Jy`~4VyBkTlx)-#EVRYq%Bz`k(>`C(5 zAfH9%$AI0kVmfzcvhGZ99TKYtyqnp)dfTfLC}o6vIt3Ple`;ZnsVR)!`r`yT6E4AR z_Iyb8T}4Liu*J;z&)_OZRioQUgRK30R?QzEv~>6tS1z+%Fm znnS6>(ECu6ZIt7z1ZU?}Dpw&29_{tDXFaaDR=@>BG&ydRCQC0Ue#fJ_%Bcc!9SM7& z>7>i6!^8^s+(awjeB3F>`f2qts<~Gtt}bi|5&kWaP7@*Dxag*_hSes%T#s}rKGi62 zj%LReH@{03Y+O|a6%f(nTey+Rh3ICL6WRPfDexnx1vyfi_pXRp<-jPhmTP$>bmMwR z(`JME_DhqfdVqXikNra(`w(MUp*nZ4{X-oINIZJqR_m$!vLyb+IQE@Hz3nKOihSM> zBau6Dd*UIGS3~x42dm_uMF8(LD9Ih1Pc4|fg9320*K!B1QmnOrCw%8A*uP^a5%LU5 z-ZKcI5H#+{?PccT2%^Sl+`;`6ZGnZKYfda!V%oh~H;Fjsqtb4dzo%MMkZAwFnGPW2 z+-c))(LFVsi66Ss5-BykLY)j23-r{Qn4sa7v8XY`7P>ofI||;xIQTibM6_*-ea`^h z7kJ!z+sJ!>wVz=ZcQ9V4Ck_?th9mPcwuyD#TPd{^@SgHS4oUEx_A8nyo__9yZ*ffo z~()Gle*!ab^ZQHhO+sVY4*tTukb|$uM zzPWeZKjQuHeC_IW>h$SaUA?OI-lf)=p1i$hPg%qlyo?{{+Pq8t#_h@*!s}yog9+_H zBYdDHSUSmjXwn>6ZM7%XeW7Q%bA0L%G0Aqm*_=~IV}_hvVUQIWH95gLi8_waq#l{` z3VDc34b1h&@-J(4-qVaXwcP1pkI>vxpgzc}Y{f;#q-lYzk4VvLNJD;UTu<*188pg= zwC!niedB7Ws+D_qMou62`Wm&kTbnUIQN!~J(XdRC<4{Al zPk6syvYEk!ZNd`W!JM`do&qc0dN&AOL()(zKsXTH#ynl;6N4L`r5%<;F}4@# zaR)-L8;14N8mg4l@*(Qz?r7k>p22l7zd)P&!fhdF&dYT@=^Vw?6b9a_bG?!i-%#|( z#Gv>h%A6a3Lr97pyu^o64V}hsd}{F>=63oQj7ug z4?+P3R#eB}eBbkY7K|!Tam%lT~0+1|TBD4P3X zyM_AQlSv1f91E$dmoYuT=pc1ILn=73W$SeL%oe6tUP)Z5@>S2n2$mk2)tZF{(>lm9 z4st9 zZ1|v1IhWmU>=HKqIRtBVJ~1+|`A-jR>@eK;irlB=c*7jy-GbOmhdAc11!pOb2(_>t zC!EV7_Y@J#e=^Ma1`MJy(xiH3$5V+!FgZ)L7FVSUcb$z&%vi)A?H-p2Ji)Mq%Z{x6 z3++ThEA$8m><{!~DkXRDDbrTCA2V)jx$lDQsqsEydy*pUfIwPbu&fw8rVi zu>1J2Ne5x7tS%XGq->`F>6`s*Ss@Kks zZ~Tbtu4K-cv1|D?grQ)(0QN1Nq85xNid-Fi+qk%q`ed!0L&PF_EB0SM^@U=a6>Pjj zt`Ez1k8902=M1Z2q`D&5cl6MhVW-y3Um)1iHo3$W2YcMQPbB6>gY(b=WytNMB|S4^ zWdr)I5CYhlV^VD(y4cabo-n|)o_-2}OyX{>efqo70@fPQdWy$bU|qhH6R{@dvU&F% zQDXZUG&FAW#fw$rrVP+`_fU+NQ1m^EvQo_It20A)C*!f3_M7qMwc=&ePrv^jMNQ}? zd2be_fSh0Mc>-At8ra$wc*CTxIHSmPH}|#{_ol6`G#1E9z3pk4pXus3`Mn0vn$73U zaEsd-iQ3^86t{SMUuoa&L}9>U1vYhzS}j}+&)?rU8u?p{fi*r%2B7}loYcjZ67o&d z-)f8(XiRKKW>2;=8xpoF77wIf{hgCKo1urpVc9XODR3ly^1%eUPfsR(|e%K%F&uYS#R2Q`u*Cd)sN)5-Oj}dOFnv zQGx~Ym8F%BC#G;T?Wl?j4@1^%>9Q(NMkP*F%~ z3g+-k_e{lVb>zyaz?RZ>FsE;4%d2nPhW^EkRi|&=hP|QlA<&9HyJ9-K5p)Yh^cCDT zHl|P*=F)qK)V`N_4AFl_;>f@hS@aA2wD>!<}1w<~wqXBTy#%)0xC4TqaT=f%xpu<=L~9 zoF*1YUt6k^0#2j9Vn?pR{_`5318}U3hk|T;V8p)gsy@`(K%kp{g4VfQRQYx5> z6E5g+E<5PvF`5WF3PJYZi@3)ec8G@giosqpfpeBZo*Z@H>T-QV)5BzAHC>>tsizp| z5hq1>3`|M@oT!OZgv;$`bV~q)JHq*tt23nI2(vuiOZF@%BxzguA*U8ZY=;PDvHMqx zhwYCMQ0U%9(UPOW$muM;2Fj9Q5%d9VEp)!3PcyrF{DH?1Dy~SR+GI&u4I2g@)eUbV z^+(6DY*&VB^4EIS$e^6bE2X_kBDG$edJ3G3Evv2&aTAw)o+wv=DgKriN1n=ie$GG zzJ;PpqxleHCgh&UQJPqQ9xX%Icf2MF?7zNZjOLm;{%HmYHP-}$cc+#`hG zRi~6FpyRWsYkk?(Hymp%AImYfTY$)1o9k`t7BLRjwfe_|nWD|f7!s{bL^=I>$Es`h zc#TV@u=)9rHUZ#Uu_M-#cUtRAsMGqzUpkaM)UK{H+JSyS1UJ)K&f_qX`DRqwZ@Z#d z{Zdahnr%vBUIHDPH$i~pok2s&i2VIR-@^p4#!n!pynIt0<9zThpT2E; zG9ID+Z~p+_>5N~C=3bPocnAuW^`DmK#P2Jc!+-&b^;AX&nvted$;b!bLqo>MIL!R1DI>;y{(rc zEg~C7Dy}=p!iTe1>}eU1vn5xCsEZtxl`I#f>xa9EHTDCg7eocv%GpA(wp9O4qkyG> zUe3#5&;9Gb4(__9XW2deXeTOhMJrb-GxM6ai1C)J6}h>mIr-`{`{nY+8hzvc%+_?k z0sLh9>(9G0Y4FoEDPyQ2wCf_5gt>wr`P?*QN{2tmd<;_6s3$I&P88a zm+5i#N%(kEd|hvjA<(MY}ocKV1ZjaE^3=YpR8K{9SSok?4iI zYL=KFUVO%Nk9GG)is4u_7U$!AqFg3+dC#}v&sNi+N~Z+%X9__;-=4+e(ng+tl-AIY zv=!@?K{Sz5u);I~^kDQCG$Q-f^W8|0qb!cGk zAA_Pbz3yb0c~Ur-F$NaQ=Y@MN!(CB$MBw&Ht%zY99S`0z4$dHcHL z)+@_$;IlWmvc91XY4#8)0|;NYCXW(&yN`5hWJKAuq@%tJaKM%=o>+XwkHs3b>1Z3l z6+%t|=*^*6OP9{yh}xfvQ-A&Qa-v5Go{%|n@U&jtEQ00pOHvs`sOsnI2xhAmpjHr&Cknlt@7y!i72 zX&~S0rwXK!xB-5=Keu5x{a$j9`rbR1)N+G~<2%H+u+sdACZREagyy79)2}6KA8h%E zAe<9KWMQnLw`=vTPD9HV8!{Km3sqE2Vw|Y&H*|PBv?C3VcCat>D0?puA1x|2q)90o zyY73CoR61(>K!uqlY8ly9OJIGg{~-bef(4*FJ;{`T*0c z+b5bo%Y1V|m74K-YnOHLQ58hi!(EMBy zfjxpc1fK*&?UpifsE!HHP@tIsa%S#Lrlv>XqGl#_ec~2D{02fD0Oqdp2ec>f8T!cTh>Byp%ZRpe$LSHsT@~W)*!x$O_k?!^y^1y{! zqR92UMw;iBvAlx}ADFn)R=lebUO9{ z*U{y-yoR(pWin|~R2O3gLl9@`b~k{v))}9cH?uzt3gxNGS9nP(ZI5G2yAmxfj*5`q za3>aK*)G2gs$d5+DGuJKwzPk@nyoWsZPKABR)fwm|D55sz%I+(Oatv);6QgNcOmov53>#{dOftyc@89O=LeVL496J_&Zy_>-$zA9Q=DPb& z{s_s<)t50|)~OcOs08sQ^qTU~LRKJ!u+mt!Zx- znLoH6N>^dT4>s+5VA(EKHyfk~iW&6L{%yH_B4N--l~i-8W7m#2z=_^uNK^~H`(WZX zINQuSZ-`-eu`Buxsh82f7HaF7xZ{4LZG4bo|0i*$#xR=cAeEqRVa+hV{doP~d^W$d z3B#beh)G>!SiG}7|B(7XdH0t#hgW&g{%xmefj9Eh8&fjYVdAt$Qv!TTPyq1N(qL9vT1)oo+gK>OwSWbj16 zlh8}cSe>$G9;j1zGDRKl5zm(v<4QVgB1P;X$m=iA(+Za!#PA_FQ15D2mvwF3O~amV zz86Gwiq0vpB;y?Djx7B9G6CLO0=jK$u?HCCTPW%5bDLjSCP*LpLyjg$0cy-=5LB|LVUC}_6bMEyBT4_=l{gos zeVBx@QvSBZmwY)6YSU#(QM%`8wt2?9Gde3$|1{3ypL`C<^EPhvW7 zAk#XA`znkLy0O}lEi`N+dEta11&{o6ZC48fjCPIGEha6d()alNQKPAk%A>7Pl|LUz z`R&Iw+PmzUYwj8t+aiL-B-V9l+Gy4{NKT%L7Ja|Z3SB`B0rMr8%<`Ofg?}_iD~*ql zp~0IK4|9eaS!cX^8Sczkc7U^W+5b+Z{_Zd$T>jajt?O6ZsEUqtE0(V~9SmaGvN*rZ z^P-?N7{!_UWLA$;E!KED8${xpvcJ<&wy5^b_tecP8L$wGP(bakx~Xp<*+z%0!?L$+MT+#4Td&aKQgD%QiRWCx>Be!s!`^eS}L%{=>fbby7ZgV)n!43hh(p zeD8)D;fEWLXb_6a*+@I8qjU$?f!=t*a{4Fd+D4YQ>28iB;SN8Pg?`BkEB8tMjE*3y zXN>UCdL={;yDfknesN|S&DwV(egNW}MC13nz-<6k4Nl9NgytsLx1dzq+-ZsAwwA5G zWUY8Q$NI3-C02o|WE5tnkjkJpnv|&O)r{5NucQ6Eqy5tur`2e4Tksh_3T$ax4o?O; zx+2&w+JOGoQopoSWld-y!p$Or$Pudpi>oXd)w|(wNn}RZ7wy>@t^&UK&=#Ob=+;Ey zX~j8qm&{E`=Pr=?hmXA!BkYPj>^}`ffQfgw1t-i}aF?KSbtEsf{femZjMm;;tACQ- z_<0?&5yYc)elkzqM^ec357##}VT7@2FVUXh;*|80adK&Ed5b+`m6?rGnpF5lFN)RbxK>zOE$XJ0VkV}UOZz@MqfaZNC5N6* zdD2Pp{%G~#mW+z4%kKM#<`@IT@-&hDpig){>>y2B|zV!nl9A zdf6rHMlL+K!@gJEXaW@3&?lzH7&a!no|z0Y`P6(ca=F(iC9m((%2qmak8unofDwNN zXJtJio3XG;QvG{pJgZW&L(&EowWor#0VQgVGmg~b*hc`+-3C`5Sl(*nu;E;mOMj; zeuM}!+LJL&eCp>pdhg=kE_K_TR=W{V+YG7?+Yk}3e<}AI>LgjHLWUpHP?>mi6ZE(P z+EMHm>J#$!mSLBP-Z*p8G@wI#R$6^9XZ04-B3Bc;#fyLn)9QadRuFgZL+oWZcNrq znPl>tg^<;wYrp;1Vn~k%=LK9&uFn1mdX<){;|84&YPJ;IiCWDENq0W}VL>FzPoNJO z3cXSZO3^r$wY* zeX7rk5O%|3iLpa3qScfS-72H{hvJ4t3@VAptKaTX-E2wjgm~vAMhiYUBFqX8EUB%f zeIgRlpyivbl)d%7jgf|c)0vW660l(*#YgDBkI)IY2acHs-+a}Vxdh1|t z{+1o+)%~JOZWZC{kJNjK&KpG(JlQVxq^d-&%G%8l$|`&sl~L=2#NOU`4bdxF9|h*7 zD1yfFy@RgLgy+%&$-Xa@+9VpV0GF9cB8+db|8xDFpOEA*q;KVV`7Nj>#%O~l4C*wD zC;`EW#Nnn455NR8|Jhel5BhfMUMdf+_hvAZV&g}z*uSqWmQcE9OzKW%?k#2!w8jLn zRyHozDYYV(y%bw3#7%L_ebm!4BYo5KID=YITEZAO#dx+ly&F)n+rj-l#qib)cm_}= zSRAPYA2P|oYYiQ-ml&0<#gy2RE?hW5YL7Qw<3&Aor}dx5>ne$A5=dpq4evxYc77^% zi^1mO9*Q32>w!B#1LC7GjGP$1%xyN%8%_B*FE2};hzl;PonswLR+P?J0s4dXDscX@V`m|cApt?2^ld~UG zgTq`xa8(m*4@UXaDp^{)0%lM|8(hIt-S8-N2T$h_WKPHY`=UK228Gj0n>}DS`whpj zPUotBe(WvTz(5{Zz*a*UjH$8Nlf*UVuwY7Nb}?(`3$>q!C3EX0WM2Qkm>7EPl>w(a zHR8&_rDStC?GN91aZMvEmR9cWwX6Wu5o?Lm#>imHj%iYE-dRG7YP7FzY@Nk>ulV-J z9iKE6kSHfRpo+bCsrR?^3=NOEC*bTFpr<2tgDHp5MR|#5e3*ObGYS;-5yYH5Tk#66 z!G_Lh%-=ul{9>fa0ACO~XM$HaEC#m3P{mG77a^-Qy?Ambza+h-Ee*?XjW(O;f z=^qZDvH2f3+kpKq?>I5lZ9qc)>|gmWO4!(7HIeg+257celI9r8iJtaxql-W*&Dal! zD&PC86MioFX^efQ9jjAZw_wo-IFSGk8RgGVmwH@)^EA;4{zQTCD&>Y66&u62W3-L8 z>Ydp62ejFzkG6>M%o{6Nton6=8Pam8XVH7^YD_3`2vZu0*sp_Y$F8(rC*ywt$UA;E9`6;Z66A@UP$)5ed58OMFj=g z*bWVgLRE+sK=2{r(KE~Cla7o-Ja13au(S%)OtG{JlWWPVHV0GaM$bIe)~yiTDs)1@qF^IzH(Sk^l^oVH z){e7}EE{2dyqZ>84xC(By7;0?f$fF3w%}7c2)_&;o*9-IN88iC>KQP7cNOk_s2hIe z)H*;iLe?}VRw@-knnH)K>yz29M)iGt>vM8Yul<4}n~2olYG*YSa;kcIzArQ*LWbAY zIsCS#i}Uqc4ZT(UAf6{v)oE=%EYFTCcq@umQq_*r5D=Rd&M=Y!B|Nr*aunwaxuP^n zD=S1LqhJ>PTiv~UEwsDvCtz-(w80)s&Pqr3psLu0)r01vx6z5E3u3MvbDSH7zud!0 zu$~*rvMs()RRplmw-#8gv%}OL{6{dsA1D@c5d*E2Vf&mIN)GeA2PuRYI=_VO{0gnf zD#n`nmOqPqgdoT#ZDqD2dWJiZu4^fxs z_-Pc6;&}b8fJ4XKX1udSy_&;K@*g^Doy zf0f-vXHt|wYvXDhO8)>+qNrmT|FHUYEx%b5+|MHRb8KXY=OO1RmJ)RMRmclvL^;am z)q8o5&+{ArV6JM>V6iP}8Kp4KiyXh z@*wizcaC~!nlz&$iN?8MJ-u+j{&ts$HJQICRselkV)M?k3Bc~`i*H}&VlhADqFU8~ zz;w@NmT&+K8=u6Nh8S?b4v#1pyk>ew|IwGEFBU1%mr%)zU<3UI+UHSzT547;rkcJX z6Zxic_vZ>8}%DwYy7MxUfib9BxLT=j}qu`R=`x@y29G+|KJ$HdsFH zegG#==IF!cah!})wRC}Vkg)ij_@{ z6Yw@zg|e!xkq}mQKDXU9t+!k73hi@gL+`zjyhcu!{s*fl|6PpYwTxl3SY2i061&A4 z-;p5ShwwZ8-wRKXVj4txTl+P>g(4D*`*iSdmG$+-4oC492Q;16^cX%GqkR7FF;;^k z!0se#Sj`Uj=1&(86|+twE9AOdm}->lr-)H@hh;AZ*fh)qF?BJ1i%p?D8hNUX3Q7_~ z(KS#drN`a?e~5`@PM1n$Je;d_;V(QQ=7*@?Ji=tRZ8*i<3}(4fp@~%%RmFJGy@&ah zepQfpCB@eO$(DGzU7kwUi7kSJ- zk$l!5RbD6Rgxe&Vgj3`qL*^+6ONjaPXhoZ94!O^j2iZyw)sn?FM7|?FkpD@lv!Rk1 zUrFBWAN=|L=je@|>V>wx@7e=XX+1HkX-T$9r1yT{zjXVi1n$D&vuT=Wq+7*_TU%f4 zm`u}@uciChv0{+I$eCJ^IhtVeGS(CKEY`PymquB>du{aGH7R&$YDXbrYxGb&KDBc5 z2;YHv)R=%qAF6cd`zh2^c`RgBcl6izuoSRp+u$qD51|DYvpdyOi=Ey}84TkDQ<4SWKcpdYE1y-2qGn2tVrx z=hLLSf~~vqsUvu>a9#+_E}_egNRqhF{lHK34c~;q&A!F79Ym8+Q$f#(-oWAHhk70@ z)52*=-Z6cePRbG~wwkkzCb(Xd_@V5H%dz8}}K8&)@3&omSpPHB+++L=39%HR6NQS*y~ zoW>UE_mgo&oUJu?v(FNMCjwr>K`-If0gYTIrKM`|-3tFR zW>KAyB>18HTr9}n#(S6-paXb+{m;fDaV9a(2HnVI?lyass}}D`a*7AWNqJU!@(j`C zJSzo}!}njyroew4L<9fNK~kZv#G6<^Oav$8+vm@M5A%J;@c(iBb9X{vHnC3u|9|#% z3Fk>trWXIDkXw)+6XEOkvtXC=&FgwpL1GBSy6@*l_lc?w;Lv!ufR+vfkB=Klw= z`R&&(1f8??;Ar;Bd*{*or)0RYd6k_Oy zMV}2MrQMB96yu(PU~J{BcNwI6dp2~7MSz8}mwrt!38}U(j}nCh?b4Ks@jb=$4ALCL z3HHk4sGNc*9Y)JM8e1`bMa!t@Hts>KSrq1|%Uo^Xs67?IEMg73pwV;+5#P^NKinz& zNyvxj%Hs-8l4dU6A+=yhWMd>vaRve%z-O{9V7Zd2y^VM8*gr0pW$A!hy4&vgRzI%E%ZeCMC;cCc-+`4sg zP(16wI*Oa?-0Br%bAkl0^yJ++$v`R{D#uLRf`ZqLq<%^Bs=n9qt)L&@XG0P4VbbSv0->s%hG@Jhn`*WP@TI0oPJ8X~X!D#LL+3=k01@;QfC7)HV)Ts20{I zH+*ZQq+rSpGJrv$)JX`Z$|J;47mj-?hm8~rrRJz)INs5ge@4$|FV zK5yV?&9v5EX1E!R7D&rE07MtXWZbD!rOxzvTDx)4<(*WaSZm*(UVJCgxxrY_{zXyU z?{=|imOegr>f|+7%vr5kINqtXg!nSg&`+PcWL%JIrQfoFL>&48p-zvD;abHl`lZ|% zV^BX$}Y{2vCW0yo}?34wyUL|EApJjxI8zZ=Kw3j^DIg6nNxH& z0dI7rEZ-FBjw_39jN;Z3AK=z+6i~4{W2^UiZFFQ~s0|q!V`qY_7IHWn&1_qcaMTq}tRrbAaNKXFXBvDEAf?oy!vi%Cthg|TgW!j%3&ga5VfM>b=SGpQcYA#rr07eFyG95P@<7U3|a1?f0^(A+w- zQm9n5nu4asCSCf7Bw%BLzLx@-@+rPRm=``8jKAQQ^V0RUl96^IVOTl|zj9h4qp;TKUWNWAbiFqjVkuZtJ{gij3msUm0-(a#jKY zgA76rN+qUeWD}K?q$%@7_N`imlSk5WZ7qqFJ}lulGTPR|OpwNkMRT7A$C%KyA>Q}q z>ZwpmDRn`2bJt)bSNmUQa4@#Hk{LGb>X{c_4w7lNunei&0p|f}qOR><>eK|ZPq5Or ztodPS#6HxotiuGi$Xy19xAGt|9qX^Uj@E$PG@w`}is^r%H7uXTR}k||Ak%g@p_oaO zvgrK#pqnFEf*MM~9rP&Gyk6wc^Ie%f0b>*vmDzWffghCXG@kJ-LwvJAM^O?V3W)gpxpluQLw8<)1i2iy* zlxT_KV!vQxQJ@_VKbsmPSv1NFu_RE=Jliu&(|ezx)=qP6Lo zLo^UNY?(iUp@a%1ou6lo&SrQYwSQ;J_80VBZ|x#C@=~BO79$Fdc`L?fP25mF`?4Cs zZb;~;e$f>x-zHQS3z&IL$w|Ps!{(Og)y9SF{0Cf zod4R&+bPd*EKg-`=;jCSAK1mOy3bt8Q(EH_J{GVVVvc|OJ=~Ma$Aouq9la89U%Flk zQh1EvIg~d$sVa|ai=@^r!KFYXxuOR%T4BW-R|v!n%1Lb=d={l4kLL3jUWjoe{ZPVR zGHRCkPwFVy;`xs_mNo02L>PG`WOIGAv+n`2`rAoO}|FKGIYE+MTpj!OSR z_2Wc1=U9pT8P+>HORAbma{P)}Y+FZ*MpxSPPnS!>dbh4Z>c4B`h7fV$5YY!jkz{)nL(EV&%gIE^n^ z!d13e;tmpS+v9&vcZ*Ac*_b!31(bDZLj9bh6cR8EAUBEc=)o=^R{P$9rZ(t%V1H)j z3M)!c!X5cCvZ85rDE;0)7+2=l@$O5nhmTVp@rL4Nasfr0{-q(34qZxxkLH(H%Bdl} zO>r3R2uVZssbSEV;}sDE@uAT~wZOV40!^nX7}#3NmSF@RhTC#~ zH-<|uZ8#`&vQ+~Y2%RL_)TL;?6!4(yl}YiZt;U>uJ8|u{Pl5YyVc7oN8>e=7)Zn^J z{dtSx1CtrGH{yo^jRzls)TBsKo#K`kPhlq{$0czyZ`{bt4x%)-fgC2grn@+k31XzO z9n2E6GxMptKA>@QyIJV^QUxt}jH(Pmy7KKvxe{%&t=;GqW6m;+_Kp*GqsW27w90bH zK1BblM-Lv+t)_xHYB4yt_!8K{rUe;I5$)!T^1>%%v1qsh2%U@HD2k$b^!P0R=T*{;{jZaKV#&ASV zlf&-nRbgI@Rp7P;^{cn%3dw2@V?${U71D%oRod@*ZQ}crjco2(Zy2$j`}lQGm<>_K z2iDNRsof+k>1PWi3CK>R;|fn>fwL#t&4uC>$%QkbCzvK?;MVuR9qLR@Oo;gU`5WBR z4#WMfB9WW}6r`fOH2teZO(45WyBp>2=_V)B?;1-Nj6zaUcYRB|l@1y)7>z>oONNSM zYTpS|OuHoi2sgOPJ`G)t1HJK(f1H|ldR#3+1eoBXrz3!fVyHZIC}NsyMl*EA<=f_s znwlhbpbhWD^_#mB7Y-C@4JX=(b7K2JnoILPwpy8L*cMXssJbzo`?;qWXqv9sB#l|A z7uVMufyrAEL8`67!}PC>4@mnN{I<&-JC-jCoPY`NA*I*9V^u0r?+wQ!N$9?#Nar^B zmTW7vvTN&O;0f%Ejbgk1s#DC)TGs;B9lk+krogt1dOfNX&-9|=Vr`ghcIp)e379$y zxm^t1q_@3f!eE2zRv;{5IyWHQLkYma*LM~zeL%Nep|LLtz>EkMXoS2JOr&>}H)-Kv zmUQ*j8T%JB#5l_?NNsvMRA4;+m~_z73a_0v`v`Dck|Gitb2mUe#1pnJ3W`$%MBFbx zG#*#RF9fyL?l4*lsD@MIQf)3LUKfo|$Etnx1KWW_!_f=H>CVl!p;KuNpq0h6?ilscW%W>4XNe`-0*ds(8 zFzgdlE;4UMsB{WTNF`Uy_=!d^!0uUuFuDbHFzOTF7dpG4?Vi0oVpHI1(2iD(TTgAI9&;O z$Y^U_-*5SQjH_)6lS^;cf!5wOB{lm^D(S5AGe`N>>9!r{_t;7KEttlkqX9yI;2I|8 zHrBpW)5O$d+H?|O+a)Jl2cN9twL`#OA{g6(Gm?EHWdN!=xC$ANC%iDWh$D|1)RjcA zWSllC28AeOG)jvOEd`u7-i@jQ!S#qp0Ux0nY^M@2dMUU#xdqbw-;ztL66e945{qTz zu+9(*W*1Cw8*X=C9VWCr${wY5ZFC)|oa}H)tW!32exDw^cHq1@?W<#G1MJdu!S)OP z?Sd1mZ%P}RgAWM<2{)w>WDN;^A&K4B5Q&hDW!wj^W=Nv7mR^9t89#qAD!Ynr$X}bkkmWv3FvI zUqCe|Vj=nvrPycPB`Yec|ElG>t83OoqTqADUqgqvsjU5L(2t@-;-_i91=TYDbF^w*{ro$ z_gdcwuYfL79|nZvfw@)&mgn+8qTA_s<&6ct}69WMDMj}?B}%)d(ABwf@A zB`&&EXdScshAOe7Oo*oGUb*&99W$@~0oZK5!zxE3_4%tg#hFsv)qWVTv&Pg^wR@{V zY@QUVM72D4cV&}HH__x0+EL(_W}@6=mQ51lV=IOdh1=5kfEE8bC>h$fM*j~UH=NUS zAO+brtp@+fS~gZXgVYKfYW?*qg5#GqTv3#g7|7)(wA@>t%bA0eI@qn2UGa8sOUk_d zYTtW0>i~<$Hg#1m@va9Am$niw(d#yj1X7@QC7$w$r8PzgVFfm3rnO#G&vExI4kowi zR+i@05tCD*ZWT4jf!6g=AVz5|a&ssm)p-8mdB1|VAtP; zbY@|mCLIwh_vJ_$5!H0jcJ9S<0d?>ypMS2!7>CvP&NuO(J?!Z18tqkEIfKmsS$KYm8g z7a!(~TRW3TCO8m=;bwWx4Vy4lqo-0NU!Txol}n|~sWfh)Gh5^A;2pb&K54xL(s4z*|Z-KeM{aix-^2+#wPhPl4@;2XWE^XOa)D0$SzN3GMk z->1|y*zadh##l4`^A>%WWt4VE=s94H;}3>iR{#9@PhEF9UL?8Dt8FZ&_r#LlUN zN{wQFyZ41bU&hh7&RnJK&oOpaFFjDD=rEs1*)A9NNU`ub>t1|hx=hcvlCySOP#Z=x z$KOYue#bQlwltWoNi^3#y(Xp8A8ty-Hf=(!i2BT}wP9>>*Byc}T@u!T&@J}$D0Hpb z&UhUBt;mE45V>PLdYY8rOP3?2?%i`K&S}FZYx(2tyxF&tEGXJA6Vqr9-pY&lQVPR& z|JY9tRw3wka;`x;yz(VijAKe)OvvnXIBPaaX&V3nX`k z95z6N;s^k9w6uXR&7u%-A3=NMi^H!$%`40gL?u9SL_DB8x0wKeQpQ^eioR&T_V7!y zO*$jXA`!b zt*FV5(#QjEo~A#?Y37@ui~)pm0;oW5sN$&*z6SV3$bcBQAeYUxb;AB1d*{$4O0X^A zwr$(CZQHg^+qP}nI&ItbY1_8lukX5l;SKM!2Dw&dRb}n0_#*b?(64Xj6AYV70G5M~RJ@!wKPG)~3*7?`TVp zYmJuF92AUMUfa;F#_}(34U@P1NENIXQi02*0!s$3-fQ1!{Y;QM5~y~YKCy1b;8SVP zYH+C;sFYxf+5XIOlYDuu%HWgC69d&GlY-M!O!|7)d>VzltI;$D@ZtwOwY=)NpVski z@z&TpWN5_`BTl5e#d{|rQ>7Q<+e*gL2&S%zYXz-6M?Uab5F2IXdeJtl=yd=h-{YxQw(?aYeD(ttgQ_A)uuHbF!+@%%y5y$n8#7{_VgHCg$<@|ZZpIw z+>NqBk}PTMs{_ppzMz#pBMgGzLhkZ$E+N2-??uz|ilZRKX*^YS}4Q7RR1OCE)?yoh3UAc*cB z{t?D}(={B`E4l;sLJ_qoq8I%rkyru+cQ6e%0B>`$Yq z@7j3{?2DusLJn0w*U%O8#1+-=Q30$s_7M!wg`h*Xj86|^P)ZKb9e2m`{MF650js4F ztLwY87?Y|6YTI?mh}d|)Auu?yxSTD_^r9J7D95mZ06#oN$Ge1_6Y`tEbEJm+MU7J5 zFD|!>&{{&O#!s-MFI&LJqWuCsu{0zah3C3Qb8s1MM8MXUR3SRH2ZU605<7OkMtNTN zrRbS}qbSO<$(UtO+3m-3VqgS2E(c}BCaNj_*sC|pl7kIuV(^oz`!VwP0{Ui8+CIR* z7}muHR=KnGaGWS^GxP#3n>am3dM=qoI2K1qN)rAd-2QEQqkyxcG!&&MPe2XeuKbKi zD91xfc*_#c4O+@&dL4mlq_Z7@1DH*X;Et>s*VQSq+!V!YP8~IlG!Qs%|_keOk)!VVtmOIpsRVZ>TFxUsqiU&74TugC5JsK=n__kkI$TPm{ zdKKD;8+^y?1cOw79~o{#65lS>|60hP$H|660ELBpagEw6bj)~viLXw0!B*L`f);6% z)5#DaI|HSOsbB~zJt~P=PN5gl^L}ll9e06dG98k^>BLRqcIpGB2`lN3xxD3(3d?J~ zr@y=ZmHu{D7IA>B)v&=3nHNZntNOgzi2RywhO@s<_5)nwrjp^3$YCq|mU945brzxs zZTEnZN8!5ll?&Q%$1gxo5)9~FDcWRra%vO+zX}7fsrMLo`hFocYoioE%{irTJK(;} z8-8*O(0pv0;Fp_8bElI8Jl~ss>QKa3{Ew|&LMGwDP~-5PaFX+F>9VB3=y1~g<>v1r zlfyH2SF)Lv9takf8ahj6wj}+^RvRr8MU5B9+9&Yfp74^7k>U^Nz*dLfVP-+}sP&BT z8#;>z%zG5aVSQ_m>94h28Gs!4ktbj#{fbLa(5@huZltb6$%@98QGENHK_Qf4flGbm zJ`?)z4K#?eHG*l&yTv-HI5uH5_h?YJhUZ{9xV=Gkj3B}~!{-2%raCG=-C}@;lXe6l zBli0EJ2FnL;3~;~ibN1A`=!#;+*&Zx*^vqpP9p_j)vmnYpO{I^%raZT}{>*EJNvfdEoVT`L9x$^vCnpn*+0zC!yi8lAEXOeoIbO|Qh@Xm@{y&kWo-?Nm zb}WFHHLPAF*Gvm=emn(lq}x8s{Y{?Qm6(R*Bf7U#Y?V09lbvU}^m~W81Ppdw@r;}l z>9HO5)l##_%aYd4fG(_}m#>E;DqMflmOHMLBStr^_ZU`l5NP|*Cf~V3hINS?>`#F^ z_5EE|lWCdM&&QdlH?S)PUI*6qh_^Ss9&zv}Zw2kJliIV&wuq>&vM+tmMv~sX4yF^2 z8Tg`xM}8n#jDTP{?K`diSw(INp*6H#7O#856ErSnk=8!p>}sxVhPaufv^NFtC~T9^ z$;0+$E;!XhKN#c>C2)xm!}^Z}Qtf><-oIs#A~|GCzhVnG7q}g(|C^cMf=?TBf*LF~ zkPx`Jl-rn{P;5=JCor-hE-+`UytkR1z=x+xTS>vp+Z7d48SmgEvDT}vArtT=>Xbdu zKYB`0<_BBsfa{$|>6JN(6B4o1%p2Sw!EL{F?guC<)@qdH^J5p?R_H(pfE!%ipklAi zq^ZAtzNaYdUEQMr)<;rLZXWC$B|Tb!Me;KDx(A5)w6D5235|$xk&gP58olYe1z9hV zAeSH@md}b7929ctI>uxqe!!a8A<}Y*(NhSNz8PV|5$bdz?P|a0^n9Z!?$JrmI^KDV zV<)7_2~8m7(3%T_Smcqc zm*EmRY|Hs8aorKXjw5ZDPL1@)glie3?*{dF%`r&qI?mFT`NE%P)8W znqA+6ge|GjOBBjbROJr31_jcwjoPiCnOhOC`1?Z2V=ZmJRGxTKhEhGp`;}2C8U*$z z6&bTT%neVy0sL3PRL%2=M!9g-O!$pzjf1pyYl-w;VA&dNyUn1<{@fJj8Xyh>_g*0J zIZ|ohZl;!cmGUjEI(;xDoLAIjOWwq7!xqa7Lw*A`^^e^f+>X_SoMEe16I)w!Cr3!d zq_}SDo%2e{CC!)T)jx_3@1#Nm8@DtlXCeaW4)-PduCULF+$%DTXjV1x>e#g?Ll?u| zZ@Alyjr{}7zV5%DT+B~~`Z~zXM!e7URmJAYZkKNIOjn_v*XkgFI~GnMU?>ivjeo6I zvQNk#O#mp|!v*9}fHQa6%vzPLvWw|goGdOy&+?|u;&Jp+G!)&he|O!wLU)|U=nhYh za2qPh7TRY=U_TShNc6AJ(TL^Ds74f_4GZXwu}5Px_uf|}c`Q^;bMfhKEA;|m16P4o zV>c@QL0>4zMJ9mefgs z2HLJxq|1ykSSS#CMxGn-O{0TR zmqo%e&WVRNZD@^Tc_>=O1PO$(JHIe}YiP#zK!8{LA*BD8#{NBr^wNIPvkd#v6mkTi^Cs^x_EZR^8(4cc@C@uB>6@I!lHU0 zfi9r~vuOKlSRF-~H(O`r?`SHW)#J;3}#IGlPS_*MLz0QZA(%-kSdnzBs(bD>f35XYuV`h2Oo>>(%ao{||QU`C%7 z7mqWj1P%@>YMzdj{zt;i$#2QuA!d#)8%^A8h9Dpt&mAabV^=C!FPGV)isPRr+i$+9 z4?tYi=$7IAhG`1rS*$x+9T?i&HhN4%xXl!r$o_YsE>&i5dBZ3>6a$u1VJozJZ+#rB z_#Us5JUXAnYn=sHu6K9Ur&K~+^6@?LlthHwMiO(#)WYBkFRHG=2>&UIXr(BPV(5Eb ziEDU~n;8^O5>yQ7oj8` zn$si-EDC%aELePub@opK3l(gWIRkk3J0mZm!GY+yTc+cZ*Q86+ zPeB!tK3zFEaGHX0KvMncrMT+%xAwkGwsY>CPXHk+lf~sPrMZajyvdYurwkxseJjqs zO%_nASfM0{na6}S{_bzJKNY3cVs$d8MsW}olGNAIb|)5QMA`QrN|mO9O#5DP#3gLKrgCkhkDIl2qU-G6fZfAK-0epJ5{Ae0UQy zN%pFHXxB@crNEVhB^;_*uP)_qr;C!P zl{jo`alntwGnPq*xOv^C%3l{P1R6mfvXtwg7%oY;>vFBf1UDdCU#fgpq>iythXbhR zIyC-rfduL$M0fqD>T+a58%sH_rDT9P0)k|r9wn);+jc`_7Ar=HNeKZhmwcAo?Sj;nN%LNbpYRg-y+Mv;P19;g#|Ps5M{><2$0 zI6asn*EH7O^CJMxl~!9edR|R{F)RHBHn>I}qXe5CXhSU@^IHT^dFhMweQ?%nj;5zG zy2qim`4L2q64uNVfvrQI&93s7G*Eba@Ka|O5hw8F>yq0mA9TeGeGQHe$=6=?&8FiX z|I72imR;NM26K2qW*wir=!+J8G_NMFC|zKchU|i7{j1PCxueoo1r^`Nir|ierwTgr z>^%k(Ac!4p4Dv_Nz`w7FzX<(!y+l?dkLgb2Pskp0+Xpfcrr(YApuiDXKoy}qFbG`% zUBilMF8R4F4#~UnM{hu%s{K4Hz`0>RG1~X_a0m<)dj;xxKZpf7fCgI!& z!MH%?wDu8M`16%k=kx+2bhRB+ALixQe@Sy?8rFa>BW)mrNWU=8~6tTqL8tYblr zKDEYFjI^Vi6t#ZtxTzNNfTxv(>}#l z2C>w3^Q|~i_ID)s!TG?Hl<99s-)OEDBLwX6IsofafkFY}333OfDg0N)M?Bsk?3==?^2k)9 zNo!GTUzQEBLJZJMb|!N@aSdW&1JnIQ-~v{Klr9Q66;`zZ$;RB@(p4yZp0;ehXoB|2 z>{0dx0ECFc7IRM3vf$khBwjeace~Bzs%J>+Yq_L&@P`Y8Ei|Yarj|^uM~ccK&_RlZ z#f7*7qJsE%!ppRZg~ErIC{@`Ay1QhG1UZto#T zqB4q55Q7k58Pp|l zjYIIcrO2De^4xg?V|R9<9SPxSmLJ3|+RqHz+THC06!y#6jpPQ3=TKRdL2nweSZ54L z395zO*MC${s1&-0HWug57{arm5%Fu|-D{iefUHbXQz9l^%vo*&yFZXAk%fY&qNBuj zR$^C7C(Si~jwo}dBJuYnnWAaj8ws71a&b37b)^$cfdJ%AEPmIAPG|*2hZZKkM_A-DOU!+C0|r)=K;^=c#MwJ)Lt?zjN8X$8kY9IWL~3!= zKRn>K9XN@L1b^=zwDStVxmI;+9Ws!)yBjijt6JmoaD@PGhy1vJvA%S#1 zv4M%Krf{}=s`!wa10EQcsd-FDGTtMirX(Xd!|+^+j50D2q}v=tfL=BTbQV1w6@+jV zWA~l{C(xHe)as_knl5sE_57mkM$ZfFO9T3tKvs+^`i-I<&n%L*iTVh$y0po$PY(^r zH&&WLw!%14Qd@_wV~|FtZ8}7lA%(bsj%ZWcB~?0BcwDJ_d=XqM*9{CBuBIk~o+Z&@1A$&cWzlw*rt!{5(@I&$-bqw;tGU zgi|J{C+A~X#@~Di8l>?4MLId$Imodd0r4?B7;Je4EbU@=tk3*qYIg;gPVPq1hF z*I#ZC5KeaLp93W2& zNOZI*Q@n$_hi9_JP9tPc!#o7yT_m0!^&MdDzqcC}(%IlU(5w4b^C$43d^qJ>@Ulg% zmV(%d-fV*1Y|%Cjb(Rc@8Z$+Et$~OQBbuVB!?P;M4I0xCr5k&AQ3%o*R%Y9>;iq!zWiROC4(>P+2M>=-4Da|Ykb8fs? ztcW>BI<~Y=tQjd!m@B~{Fzm|SZU;l@T}rPaRj&wj-U4-rNCYQhJ?`*;GDFEFcU_#y z6(Lxg1ERB`#e*!X&#ylJX2H>!(RKXHQTQkDvYLnD)_GrbJsSRLHmtk4Zs#B<}x(C-Z^& ztps%`rsfj%Q6x{~43%&^Pv}Z20tCrh4Y4YlI)lUKcXL@&P@I66p#{95B^Ku{N~W-( z2xf%SuspBnmOX$5=l}s2Qn_W_#6K(YU>5<78k|XU$Vf5RIA^$Ib)XDryW`a3`=QCB z*t(4roun&c2_3}|R5#wKk}iELOv8fn9<+H>uS9_snPwXViExnO$S^b`p!50__p%XT z3u+GK1aTUuf%Qo1;2{saiTO5-n4L}i_(IelS!8l3vl^1~B{vwhlVv-yDYIHufu4JJ z3vJNm9maj2ixR`$OzjmH_FPP*mkuv?Jt66qQZ9un0mbYtn~e9rx|W2iGWOR+fMS9y zg!VT@Mb1(gMM*(bP%(PJf&Q@kAZIZ&6HFMPLfZX+2Z&TOMab4&D9b7t4sbK6xETLzspJ8-mLxI)mtBQiUQa0Z z|ASlzyxOl1ekeZHrQq?1Lg18ixshW$7Y)dHb$+r}H%X!Mj8qHVSo2^FGW5!IaC}I? z^G}8P0Lc_-IK*Gga3<7#mA5dz5PP6veuLKpUeSO;v#0qjv2%J-OqA_GAHZk1Lrm2t!5nHeT zs1KaH4ZSq;KXfFv>;jE2iRA*(lmvh{XssBwRj~=ZOyCrR+@k<5~^-7 zTFf`u&s{i5ux-jCXY0l$VW4g7+#zO}V)YL$1;DFAnaFNW6pA!_fGa)JaB}NbbaXLLQx|YEB~NZL@&r zY=pbb^^Cq~-w?9UKe-v8eq0ghfJ<+cc`!xkHUmru6;o~ZA%aX;@Kr!Mo{^zXRTAxh{8X85QUygdFE+6zfUm!w60 z?|+cGRE5-mSRV-8C5V>lGfo8+ymUbW)IQBfrZtAhmz;5Fxv7*JMupA--ByFi^Qfc@ z5%ipIEHE~n38y@|1j*Qqq0mg)u|_(TghKtaUK$>RJ-yuE_&faKO1*EzCr72G)DP7s zMZRn*7PE#;NAm1YTk8X@D#L{0Pjo_gpkQD~O4S#n#b z=>Ou3_x{yL_~tg~@_&XJFuE0)8yFUc#QmNi5&8i!d9+_yNuEW^D4@4|vOrP7FSWzP ztmHgOKwL!BX_YWyHGhUY3*%3;!2}GdjdMgcp)^I#5n9$6Dh(}Q17D0Z189NViXVgT zytA+zh=svP5qN@ z)lwFkm14kK=pdUHR6Yth5Qj;TEt;GguQLDMLtbu?e6bs``2oH*6dD`n<;?_9z^zRM zm1FI0fDKVSmxVoKqn<#n<&LYsdt!*P?(%683z`{7~-$$1j z^S2;}FE->ntK%M=4GHz}!4afjA}{`nWQr1p5}aMY3D9IDJG;dT>}Lu^5AB_;;Y zCZfS1tcq7Np5jYx+X3xiLV)K=k$ItF6a{s*vovH>;TRB!4XGqn+eM9zJ1E$3QSD|7 zJiP>8>q77WJjv`U@Xmf;0lOEbHKI9<)t6ToJ|gOVZ|ck1a9YgXr26Z=>;`d~yZfyt|) zddFVf=2!zz)^IIK9b@wH8E7E#EpX3l(m$)6Q$Q(csh(JFvCblabv5*{Um!diMHgoF zr`%A7X%?Q)I$qlc%Paz{R_s9+-57e=HG-bxFDmkG0P{us3IKAdl14eYYFG5 zr3_3CGiu^{1%M6&3D9W7^ks^mJgh8t^?wU#8+PWzkn4dk9pW))uq0sb2*nIk9V&hjS~;^GkQ~SG?E-30o2`SfNM>?x zX_#kp6BIIihoa#>Rg_z!+ziST2%J5LvIIGoFsmtot!gSL=4Cz26mO23zF3RNkY%pC zG#ZjHl^=N_1Oo+*!0*n`sh!?BIs(|XbJfbetHQ7bIgeOWF9?6Ek76QvVEMTKgxrW{fHk;9 zAg=e$?6NGLM+3JPLn9c-f^(wiQLCQtt@U#;_OyYuAfvIOW8~uNPZ#xOYQ#X!tE`2L zNIBxazhb(Ea?0$1P8w$pP19W;$jle&**c)E&pfX@gp!k85ipvKua?j0xCG|uL=aB} zB%lFxz#!34w{w)CK^YLUr(?}!?NwDHC3U9RhFSihwv=!#Y z2Y?kkDH+K<{hV zNWw@txHm)Fnm=ZE04nHs9O<08D@DG^FYBrT8|KX+!}5% z8hGIxG6B6Y=&)h~Jp1mUAI{CD9O4ccK`6J3ENzlu7uMNc&y01iJVL5qvbblIA+<;Q zQ%YS$ctIVV{0ojo@TZxfRxHg)N7rzL=D+@0lP~%bdei`s#)Ro%cezEntrx-%mriYu z*y3IYp3fOhH`UaZaBa9*cLlS~6Ne*0N=sP#8K2Y3;mV=TrM!m>VKa1;M ztY*z+~`PKx-g3!5{#Pdyn^xZBLO}iU;1{{ zctcw#s12TY85JwMPybmhnHWG+7-a7+^4|j#3i9D2rn>>q3d*EKD_|V;gx|O8$Mf7Z z!}xXO(qNh4Q`aa-O_}KgMJ@38+X$?*tgeYdyb;DtV4fy>SoCjjG`go#pRlqCOp~Xd zhPmXDZa3kRR4PjB0cyh%9`RN%p@znxYAa)*n{lj%2xF1ro1(s{@Jz|{81DG1aP+NJ zbiWA@(~LxbPJ|PvCdAJ;loyZw6AWr$>GC!%2Z}7M@(&OVg*0sPvC~y5NGvf6Y|NQZ z4Mm>GKR2b(h_)(cO4%lun8EDlHk-OdvzR+u_eaFp!wJZjoH#QrHqYk^sgo5iwFtQApQ9+AU8>tNhwifC{#Ib6LpoOX|Xa&ws8>+@2N8|;dU6iJ9 zj212hG|;y_#xt(4DGym$OF^ z9;m+TMf-R}zTaVp1J%nC)gbHf zj$rWmTbcImmyWr7@zu=*P2nwMZE`%05E)=!vqYKmVH7N5g>(({k2|Ffzea2 z*p!Fx3#~{hTf*l(hv#2BCDgtGPQ#lZcb;+z4a$HtEjm3APKbKViF!euCf7ZL@?U*% z9-(~a5a+elbM%437GqK3&ZoFrnd~!gvfb2u%yy)=(oLyUeA^!Z93iHf_fL_ku4^T? zYND%@1tVoi!oOG>|2h)9{ZF7v{_q51*_eSxPXM1NbgoAM9s=ajsg;8mb&^T-3!-~t zSWy=jdBZX<7oD53pjCAqqSl1;=Ibsg?lp1nkp}G6L2DlEoEjkW2GNxKIw$t=2!Bu; zq@fYO0*$-e@zUw}MJs61Bfju$np;FS8jeCif~yZgZCOS>NE(C-CNI za-HPp3j*13(lTmxasN914SX;sZ0IDGwe0wJc)wdX`-;KFC!=P6$$AmH-vRHXr$qmd zV8+vhoj+v}`_+FY!iI;IBTTn0JET?t!8bT4?f_#AdJw&+IV>t}0{qGmVd(4Xneobh zsSBQsD!Oo^$!I>DttNxuL>1`|0$g}mfg#^toj#axJ>_Z6H<)q9 zypSK zh!VY_SeBdY3djPGZeTfFI1Wyo1JcQ^Sa%vxTF@;LPT|Du;zt39S`XQ~Pw%(OsWIn5 z@RfmorrL#{`w3k;EkZRJub&=*L3jYMjbESLip|bIBAVHdCjoUOn2unKf+ySUWRH6m z)3GC>6d$sd`zQwEWpf?`jS5G^(pL0CetHcF#^HAT0L>sC8vfpqg(T`0fHqzibPLvE zKlI0eO3S+Yt^of+t{A5M;54j(uWaRVJ-}rMa*<-wAzDDsJ~*OIBub@BfohpeSE1If zAHau8XWZmdlLb5Njb^c-7>i!@8yzWHY$0j(W)e6LJtVqcgz#o8JkIL_YhBh}XHRa; zLZFCA>k?4mwD(!d>TICW$k#56%0{Gi|7fKxy~RD6MnPK>)C>Bw9B}ac?-X#bzQP8x zq8%2{y_m{GKaM}ZxhcsdB z$*nZo3Jz7`z#9*=R_fQk?L!X4m2OE3hL8h9sVat{esjH%N&Mu1qwT>yl1Hw;=%%*q zFN70}T=-kCYATE$-8^@MZZ`PJUK$PveAyI1M)xUyTU85l5--o38{+Rur9tIooS$nI zWt}ROlyoVdGNZ-T(Blo5V6A^+jhyH`CNfT?nP}Y^0#WT{QkX+Vm1y_${ z7hCAhyGCq%F2>9&Y!%Pac7URMK|z13vyb|;8OX%*Sps9+O*#z=1iO5HDZ^{rAeAP> zB)0B_@~ilySn5qewr7RMkPAZ9JZUggwQh%YA#%og_uWss;=qy6>E}X;36n9Z<|qe~ zMQKf(iB@90&P1Q$0Oj*y2a*(2!)f&Ay}*TuYyc>>!EPCz-gUej3^v69heCM6v17pA z{jA%)(FKZGK|Ajt&+*SajKkOqho(`LI)Kd#hO@=EaPuPpIn8>(Ns*6iPgHDalQ_*I zf!MkF3~Y~Z*jsT${XzeEzl17lg~|jmL676SHpBCS<)Wg25ulrHfWVfYAx4~}y2DnG z3KTUFZpF|$Bn4nc8$rTfb029H`=5Z2VU0q?D$xVk_&YES4YK$f*Os2c!6=<35=C~| z%FFHaFZ!NvH0?N<&a5NFW#%?RY%DMrbx2_E;0B9=shUhe;c}@FhH3lz#l~^`-TVQh zz`eq9re5@lY`Uu_+9Omy(HOLO6IQzkZ1SsS4vKtQ0*B~ntoT~v3Yyf~TETw6w&_bB z#2b(7C<>D|qC9p-%@J9pFL9;*3}&Mg;1NF8fC$SJcA#Ih7RJu=+>yJQz_Y!;@;v%D zHNkMF$kqtG2pcqJP~bB}g49$HN2Ae2EN~?OMH{T{#DNO~65S4(1Ut$4F{;K89pX~L z(8h^8d7T)cK_J6Psb}04=&*0X+cen)%l3QNzZZNzwqKUcs0*@sij)AAw{VW_C?Y>= z2j6l1nrFTvm*oiZcVbBM#1WJFO@1}8%iMc<&nm+qwQ8VsKk9k>Pn_pQaR9 zv4@%_wdUC^{UhGiR;Sqs^s%5~A15nOC~{D52sKakizpr`-e*6k*gqlWQ>jU%mxrF< zgm_69Q`UzVg3@*VFWWnD^afJPM+4qh|gYzlKq@1 z0Ao3Zy&g+_g2`NO&)ckC1KsyY=sF*Zo-g3vjmCK*g=b>O7>;_0fWnNdROY!Mz?WkMr#zr88j zjT~^UuhSw-doVl|xaNbq0+Uo6G)!@90$GQqhezb9c&>UK_>$(S*zE;=B2{*@e0pm@l6wqUNPBlX6jm2pd zQ#FC-7^$O4Q3vQLGDPftTP+?C-N4uCvmjzUxfbg7?J#gOoK1rt=49~rqlxixvyd#q zvlH%h5ngr9SJ0r*2pftpUr+ipkMHgJq3{7!Ed{0(%$r*frw7YN7SOmmXdE++S!O(*d?m4|xqW*I05hjlSJA)5tqB=F zaTaOIXzj7%@@3rh-~-^s*x9&1ytF34ub zTJSN~nmp*%_>HfKS9Qz_QhN}Ovyfh#vdCy^Y_#Xl+Nzhaj^lGn_Hk7$JPF>h==8G% zOS_I{I)C&^zQON2n~(SeO2p_F=*36u7Ad-B-6UZ+Eid^3QXwyGudhJ#C<(uAn0Uag z($vxxs5(n=06S&{YZ7M^CFqt}tOjN2p4kWBGcDQYpL|nvX>SqmVZah56CAita|54~ zCll(S(jzw6E{7b>aKt~Q?DI{6E3HBZ=J+vxJb4Y z5gD^XrI#4+B+@|VdTD_o6z9)B1aUBrynh~)kL##nYpW-teciqO(1(tHX#mfDHcC=P z2mLXlvLG%o7beID&A5@-+i^m0{2$15BvR{VgW-}?u2D0@EP;F{TYz$3g9HEih#uyX zb*>C`<%lpjUp=8%br$SQpi6XfT=NcLCoEq46zhFjsY@ME6fZ%2e3Gv2tK}7)#`rv8 zC2u49Qs<>4t2VM4qU3?*1Hm6k23s!z;zsExL%{j!rCz%-)2rb*cq`DKA-o9cK_7&+ zzulyIm0de)2_Mdvn+SuOZ@NqFWwL{z$mN%uY=WejaMa4z$VN;nq!SxmFi*qCfBDt@ zv3XIDZM2iw8E!E|Un_IkdwdAv3vz$sL&|>#e2l87c)P8tFPp6{iV1uMY8~<`3s;=x z18>~&>U4hmE%C0#?(lDV63N?O9Dv;(e*}PU!c@{_hv|BmLmJ@)7@Nm%Qi0{FE&}k| zY6vI$=X$as>nm_IPFZY@1~f*M*ub_Dp#I>vAz^a5GvWqN=Jc@4rUtofqJg7weY=GK zJ}OT|p5ffzmZ90vTz z0b57G+)YRx!C^YAB3Vdi5*Jr{2<-9u%xB4II03StOOm7B8#_872;oe*DM@#^ge)K- z(l)o{Jr0_VMUA<=Rq!DadV>D#qO_%^>3I!(6)tTvqXUDIj9Pw>-yCC|S8^x)3isH* z9^7_I@>>+fo-3^Gws6e~T|g+L4*RR@ez8G+KBhWQDrGdszZ%M6by6s!oJg=NzMAg$ z3{Q=AoN~q|=fX|%;MeQG+h`G>7TI5@L^2E!&X3*UqL}w8EeaeB$N)hWkN)P73sh~@vn?9BVK5~^EW(H75Ce0Eb5wn)VFpwNS+ruVp6$EOf)2Wbj!VbWpV4d`FOK zuSmR%Y$+kcuGUh-y9>y4430;mQAaDZbuRH3NQijEn|{;S!n~Un`WxU_aiV`ZQbEzx z!CM%B5mu5BvUg}$-%xTZ5*R-AHtOU=U*qedV_SrWx_c#l&xkv z8y*-w<+%fUOh3#s4xc|_?AS3@ z9l=|ELV`p$9_%yp147p(sE7gE&|Zb;WfAZq&K&mDu)JHYGp-kHpcY&ktY<*p^Qoh* z;rKN#0Lz8Cqn zcnTcNK0Y)wjrCp}aTZB>;aI7_s?@}6%jF?wRe<0cq z0s&3lPi-riplQ(C04s%%bwFv%@#HWX`g$Oszz@hOAn`z?U`Vl+eZ63l) zs@dc7@xJ;7zDnzW&z<)MTO;O9@#dggxj4oXL`|~prJ3ytuKsQ~Q4kt%D8h?vl4Tj;s@mm!Pj0f__o@buAO7QZujl}6U-Lebi`WRdb zR{9adP5O2w?&l zqc_;Wo5r(qm_}xmPus0-Hb}cU=2la35XUDbLDLkV;y${nbN$Q}LofRTjD(4J(>Qsa zKr8rxdVlPLi8FEK6u|XhdjAzeWod5nVeLS^*xmsxzX2RV4R0RL{d$Gi6dWkbE0EgA zcZ_r8%QIUaMX4!<^i!i`)7~tp2BtujKBCNzFCD*tg_{)2TAE<$=Rjy>BsEHtR&b{; zX}F-20QkqmcYGUVxw2YMi6u^;N?vLDc#ezy?|r4d!k9Lx9;CZWaw}?8N^qm(q3{#0 zrcJtsh08@VBcQ>xPd41m*nQnYTwESdF+0HfY1#>O206b5Sm9LM9>8ob>>C=b2OSJR zTZG&nX6%0UhpVtIi2gMcI1%o+a%U=a;%n!zNEwBP!1cP0uQ$!MR zhTjFzgTqy054J?Iv>HY{=;Dhzbue)ST8>{)eF|j4agf^W&IobL{xG67=HN63L>svz zU}aA|i4PE7CJ3E_r|fQ)hOCU+42!fWdLE^2x2JXE{q!R~mIYpsTEBQ9gGulxqU;NK zLZ9sz@!)lmMwJ(3R1?HBYJoCg7->%r(S+{pRfq6{xdu?Na1mV^+#MinZ9rQlJhP$* z+}3%pSZosl2nTQ%C-49Xj1Z6tNS5z{2Bgg^b$yNS0Ef~i+k*8-NTb|h(-(FvvlYzq zPVRFwxS(EIYXUy4j0yF|yScRo3XVGfI4D4vv!Y>Vz-a&pX*6b%4WA!+0QTci92jf# z#)Z2zZkS9p5aAbJOB)WqwmVcmdkpjLbZw3v+5d(DRRXKZSnIHhvgQ*mv<#rE0HY*E zY|9}^dId8H1S}R{U8(!9FRbF z`fFCae+%v+cJ`LrxzR%jRY({G4LdU5Ru4nmDSbn2euhw~JNAh-Xrd^<(m} zv^cP+ZG=NnK8vUM$`vhk<0hcjF&(ImR?(t8Yx8PSceg;a(sK>cZoUg_!7gDBtif>mdG+@W-PRwhb8RRQ{>L^V?lQ8d-zp z1-#>l7d?N|YhE_>%~HqE=I51xau+==+f^jMTSZ6{NKt>tGJYDj%FD*(u0yJ+c>#Vi zs|0};bK|>2E{>Y*kDviA6)~aCL?U=ugoadhb;0*jxD!{Ul}!_86W6nPaqSqq(L3Oq z{D(wXmMa7C)V)PNifpa9!jCqHW@K~j(Ph^_oHl6|Dg zkMJQb=E^>IoL!NhO$*5(sfRq-3iKroJ|urJ*AcqgudX%~zw&$2Md}obf=4SvP=7BW z$3(LbwzsE%opix_`eiCcnTmshJDpDphmjK=`1i9j)W>uLz7gdXD>oLW99(m%26f4I z2Z|9LM%T-j_b88SibP*Id2RTWLqxYj3RaB2^|R9bfU?sbgTw7Xhf@Dg+<-)LHwl0VyXqL-hEddTuf6sMjQ_OWJ8jngVW1ju^@Uki?o3PwmpRxAP8U35H0 zAhZxHK%z7`2e?g7Hwge%th{Rpn+ZcrA;4?%L=r6+3Rp03)_?1GTI5_(5H$~eBE^cz z9>Ts0I^)5NB3d-|I==f_$$BPSENF#O%ZD+)5t%GWsS~NEiGLd#Pbo=6$nK%;c@bh3 z?4Au&h59*`)QmbZ_{M+G-HYGe@cYA+1NkAYh$c{1E0MJ1btXbxij>njem7V^H2#5h zA(IKb)==8kV(bO+iXq~m-x%d!e31&Fy{fhkzlSWDeZNukZ6}GOqSofh5qTmI@)I0kWCbDYy7p)^gC2M_T}BbU~dXW+fdn(K$!3g1p^~ehyk2K==APDpYU>T zfJ+e7?2N|JJz!vz+>`ukI*V(6h*e=6;(!e^`?aotL*Y3tOKKrsF+_dEFy>D;dymkY zO6TBTxt+At&Ys~1yo`7WGZ)vsYp4XWtY&lhQwiB4(hL^Os!PSv%9CcK*{Z{=+Q73? z4E!ppYMoBH%q!3DX0~t4x_Sdj`?o~00CQ@`9MfLvd=D=3^)I(5^}zm(DWdIknq@t@ z5`iaYo+r=}lhMCan!qo+UH=Lzs<{nhc)~qwG#V&TO{T%q4C%9(;z~kBPPJUM>bFQd zq1pzKgFwzI9wfwf8;KzUVjKSO#DWVDm3+haWL_F_p)|NxmBFk+YFi2h+m+Vb=7(~$ zbfpA__FMcg+U_F|6a_HlrUC1a3hm6=(7R^TFxp|wzj7i=-iTtzQg_9^leqVrR-Sz$ zOZJ0NszlM~aNKvCq5cb2W>q&?r0kZUkwtp0-uDbp-@G&c?iVqwm3m0Tb}(XG8^M_OrXrl^v^P5jpRbu_B;v(z^<(N?Iq=-Xmkf zHyY>Z#z_1pV-t(1@p>+7htEg_yLGSbEBr`2f?rAr!O;^6kYMcbg5(s8bSAPcXtP={6+i~N*KbV&jam$!kHN)!O|1ZjQ=Fvh_#Mv%8!Wk?|Eq{ zS;lj<92sGAM^5RIE^J-bBbpO=w&}0g*=d>J+4FG|;=ksV0|692)D`s2YJcu6X{{j# zPn4b?tQfY=?R67UB)-o`Npzg}JJUDA#rnGK8u4_TG{c+YztS{RuIak-7YE!D;l;Fu z9NBTS<)zrnn5xQ*i3Q#a{eV49%6bE4syo=)0b*Ria{`fGqx-M`a2IzdJg0U9WQjmO z&_qa;JPr}8%ZPrhg8J9MK;k|} zu1xFaBYzF)a7~lha*)do8%Nb@qoQl8-FHO@SQ6Al0z;wdK#esGyPsG8G|0>IM3S%P zuxA4&Zj=tLm`Cpq3cA-u^=PhH`C4%!An0!W{G(r|S-B;lU?ytiOdUQs0%T*Rpd$ov z>BXlC0xls!z)tcOg=!&g$tv8p$&tj|p3Cjb3gX%L(S!-(GL_oGqkAYxYyUV5_voM5KLc@y32a;HoMyiTD!c zGZ#aha;~2JH3&dzX}~S14X*#vCv(1>2ATL4R(5)&^I|vRy{NblEU6+y>{vtKwAvRk zF?9OSd!sR;_Vbx6J9~aVw$`fU2eTxQ2E&nQ#wj+2Zi6=VNx+YW zU2TgU08QQ&yLWaxMXry~8_@kyvVKsYuToa?nTYu{3u5CEx8!wZ4wAFH}qYZClS zl}xaSPQc8)FLswU(DNP5g-?SM%s!bi%@W5j^$hY|{{Bhai%%8QAEUk$)Ec%Lp0s*Q zV#jZHMdsm(`zO|JrXhH_to^1EGxxol0e5E8XuVILsvxbkJcU0hMB@_WrV6|yF_x`W z7>z`h&|N9Zo!WqD89QWXT^L?3sW4oi#-o;fLF(@Wk?@voMg({D*0R;g&i#}QXa zc;89ijPn;UeB60*%#!R+?EjS(hPUvgVn>7LZ}2XO7^U`BJ$`8gJrw&zW@=~RClCer z_G&UZRe?c}WXsIyIvDiz-0+BwhpJGv)HUOvmH*IcdPO4;q-0OJ!85WB+tJRi9b#mW z|EYX24#qA`H320pKCXej69-Pb5ovlf;fQuApDtM7$;tZ)ix7wmFp7a7q-tFRgWH=W zYv*6<_- zOh^||6|{%%On+9Fop>@6=@LR{rj(*ysu1Qq z-baBVE=@xraHv~Rnw=_dZubPo%*&o1^IFDeQ}75vVO|3oW-PjaznziXj+#knv6h$pU8PRYydOvON$JQ|_W-x6sQL#C$zGfB~-B$mnq-~1K!%LEP9 zX~gIX(kcgiCntiVgZ!ZlcA%fD>l7GXivETmoFR6~0SkhB6Ok};aIQG0QZaRE@zgvu z*7m+sQ9?3+iKH)AO#Phfr$##(0Y<%?KJkmZy-JL{G-ERWp>S`+@;z^rN7-z5;fm&j z$XJxUxCtYo%tNjR*L7+n+ukBO@uxZom##ldGV{OSy3huhVjHe#zyX^89jl~yK9p;E z^g6C9@YxNk z7S~a#r+N!iiL(3o-gD8RJunoWvEUGJ^5~d#*DYa{2vKJZUoAyg27W-UGw+| zA%?=d)@5S)uXb$e)1U$Os9B=ePnKv*=nmD7qFQvS-v4m?`l@;U-i)N%`7SlPoLm;E zb?YiOCA#Wuk1GFxrvvVYzQ9Rg8rNRZ_2Wkcf=d%GNNt{Z3Hs#$lkXXD^3X^8D><`j zC{dM;ihh@TqsD{B0{@MUqIhZ`Go}Puj3|o#RP9ECLlg4s(kDwx zHI|;`Ia)UMyGW6|cR3$APqpr1v0~xII&^SIe3~EaQg7O031>(=`%8)QPCvim!4V`i zFs`U}n4ti|a}LB$OJ^OMk+0eZ2{%*(gHQpHTQ zCw4)udq&zQ#7Q|_ck=8@h#7qsUrGh!fWM2YM|Hf$Egi*>8x$mUpAhc5N=yJm+b;s$ zwz#k!I}?Wlh{ZF3V7v3iv#Qk3ik)dFCvw z7{%d+BSIwG24bgwQp*k*Sk0z665EX7|3aE+qO#QBa7~JUR$W(!)&%nBZuY)gCs4V< z04@hoW6leJhReN|%@ze9ZYLdb*KWF6NWMF;J2Ng+yk8 zfW2pq`rjje^N|MACyh}Q{G8qAvMw?N@vR7uD(f4j%`N=dz~reuEwNLB@b}Rnm$%E} zH$=R%Ota?~@Myk2Cxjv_h96e~5eh_<^~Yj8PvQzLw!|{t+5X(7CbR9ETxZHlx7GjP zrcgU=q->F*l>%U`yK!95n2eX*N7chHS{GkCfVeAnFm}A)8ksquRKV2;__7^}1Kf(p8 zuU*d*F3Wmy4irdRF&?|n`Jpdg^M~D>r;6FTZgTF=}(E&1`mCdMw zg>15p_>g;Q-H$g$@JUI-jQl&VCM4_Hn)qM7gMoNR@AW31>-DIgB6LY@9=A@$JKgEV{>Q{+pB?& zpGbVN`d#Ap#_V=dtFxxAyr7p(gyKFekQ@qYx+NhshUm#SxgkpQEf%+(Vou=hLkBj- zR`aRdSApK6L{yIp4wRjP)sTi0(hpYdc{E`Y;x)((I!OJ=D0`=pi~IiDC;z-*l zQLG{2t?68A)Ea_Pd+P?J{O!5tSd)mR!5)h}5x;oDLuh81AY-=6&VMVxvO+zkjH3!b zm^CANXsJi8A8>f&4+8j^)xSwqKe-TkVlAJN%)LXtb)0`Go*T!%W*{(`6+~@amTs+L z4x{2eShG?`{WMjK^Dgk2e0YKHXn7~0amhjF`)Tv1^ZH}^7WQxLy(A%FO={15T$+vNLHTYZJ zX(W|vBgWiW{9$P+nTlV^wX1!~A{9Qu;BRwZWV65yaMNk5t?#5Er3Ey4aQyrtr1GRc zi^E4>3XUU>3E`P1q2W5&O3;rMcd!rYxA|JTI(hNOU7+ELYV|N{bQ}{fVoU-Xwjc)0 z&SM%Fp>k!tCzx>UV6g}TSG$q#N+#XS^2dBri zdh&(nTW$v1bjETP0#4>&oPR8pLm+=|J=(;5>V`FA96u;>Lip`XFcQz?DL`vVlF${5 z;3PL&DNi&mf_LEOM3de`JmeM(Yr+HS!cuVMz79{_zg!KFMj;vyu?%bu_bG}qv5LU33uHZtPdBajKf*$|S z3I)*GLb3hA+ouL`>IBs13L^&F8k#iLL!z%&MKmySzrby9xbY_c!$S45y+SAe`jGWK zpKKzKc;$EHaUHolcJLL`N9O7-!SOttrJh1ZNHpQD`0^#Wp6;l6@coEruf|3?V}_BF zeRH?w@=;#UFKeh;&l15nkOXIK+*_NPsTzzMaaCa#QXCKl4y?JogR3`+tnQFCnt$WG znGXIzxbEe*=n4-p;MMh5lD(;^$}B&&gC07{an0HnPk{PoLs#?8p?(}$Jo!u1Jv^C20i6am zSmw?_zU0h3yxl{t36XvBpg}e6V6~syTJ_I16 zkI>zkl01jQdEZ>en^?u@*aBKjN7}GtSm*+$EV79D!42qNUKI1Al%Bv$p8>+(SS=^> zV?+O-r$wKWjtwZ;gYd6dCng|wo}iYL1wsnDT?iqF z(MM2aTvZT;hu?mUInDhNm+VAM3W^tj2Kb7i>0}-Y$MtWBN=9}Xj!Z(pmYDFPUlgGV z;A7fVoLG{PY~*a<%m3Q0M5%-gc?A!Lfz@}O55xwcUPxgdOkVM0f8~;l0s)G9&5+Dk zw}$psz`ya>(Cny!Vekx*_RUuqeex9{eXSx-g-iEzgcGYyo{?KpKQvLlYF~2U{DPgf{O>|-FL6rSMATnS<~*S>t~|#+QE=%E7XA5pM7;AA`?N|jRSWA-2*JvA z5TKyD#4<>~+Zgr3Y&IZ|2Ut0LL@Ym3)NNU`joyE2W+lebgV{?RQosRw$8MZpt)ba( zw=58sI*z-TSD z!+VS86p{SdXb|D_By#t4!!!8%QaAk9^-(|QYiAKUYG$Hfol*kcOXRVfeg+$B`2D&p+s<2l(@z07Y|1f3Vx>{1Mzo2 z<6_|+VZfgS{qYg(;l9$xBj-^i8gswkPS}oPI{EvjZALpB?aLpRq1b zP?y)hViMGez*8bdutgV$eAHH>Al~x^&3V!Y#NC2H(#h?H9#Ku%GvKl-PEs8PM|0}j}GL{&#O$w zkpy=)XC%yvSCUGMkpJu!3{w#!aBtUO925|yY9n5T(dHc=OEu)?rYCY1epZcHwYJ0(yyzJr>W%K#p1KRkr=MR-|`wgG^){mA^$an>* z)^|i+hV=_ce%J?yqQd0F{~NP|jM9RT8NNFo{r&8+E!H42^4tdD2oFuJ`oR*ZC}>o; zgPE6bZ1ny6SeT0;Np?6SXz*I(=swT8onzAtM<%Q-6a`u3jH0u?jT**NUfnO_0{7v>N5IR2-Ie(m;wUXI|NQZBOdJ({A2MlCx&I52(i zn692S7d8YocVIvxW(}tWMt)eqA;=Ho=ZKJ0@R40wtm?8aVBrG4*v$8pB_TWBkUVeO zKzH9eVe9jawpO&WZ|4f;#}ZnrFhP!3AeAG;%@UY2?je-Aiff*R4WwHsj59-9>zM6d zCxZwYLabZAK<`mvzH`E(M)ha8p)q{rWapcZ>Lc#L^PVI{Ui|}vV1(gYtClF_3zf3v z!@>?l8caFa7g-ga9Yv{6b|@|av*3Ii^Q9@cBSK>xdCu)F2uBhb(Nr19`{GI{ z8lr+wb>Ly09yKu;K>)^&lKiRNn2r!RHXMvWc@)>z*`b^@whp-oDYV~$7NK2q3x@~q zt|Vd9bo+S3w=RMC_UR8z1m@U>Hyj(qs6|r9)pLhnFQ2v6OvynJN5}M)hJO|npKtAO zr>-+0O;Qju1Unc=r#_$@NxdRPl)T~p+}*2A_ohkhTqZ9s8`^kb1+v)-HeuQ;uQhI~ zDKd<+9J`qH^K>9z&6raQLK@1YZ|12!jBub{^>?AK##jnlu*jp$3VFJM@Bdl#qLDOo zgAV-zly!8kCrE*WGMT2nx&P%v+kj0tAxR5iX|#v~pykAZ`-5|b%*M=JG!?_$udyV) z0v0lf%cMYIVSJZ>+jxiRQ`cIzQ2vT#R}_@#L<@B>Zk?^FdW5bLKA&R?ojXWg&d%hU zsNo{0mm?YxVL!fqmmj|I`>WJDj8EA)6aDz$pqmI4;gVvZUxovHEoDY7osPo$Ls2lG zbG)m9UG@d51^Ug<;EgAzZn_b}7ZvljC0a(T2!*@InbJVy6!IQe2>JbSua`q4Gnmif zgg$Z}P1p{lwaR9&siFMc)-@qqPh>CUS4B?t`Y=^ZF3DGXo;e*_$oU0HJV(OuYO6D< zN*9OXL6R6{6S6AgA9pD&&Mrya{1%(?e9Q6iM?yWxh%^&BFhA}>s~1=Ia7upQ__&Y{dgy5k za)tN>2qOVfVpmfkKrZ9vralt+&letUA|*!$r81|hd?j`a#9v5)$kcd|q1s5XFlqz@ z7M_lLLR=&Q@L?%>R)8MSOJ=Ci-7z zpZNdd&+q@^^mNdFk^e({bt9JlUuOYC|M92!|2X~srs@BRX_C-UMuJz8@Jf0L1J+9W zb!9vw?_>RaC=#B|)#te5M)sYI%k;(`ej2qW^X*4ew9>`S;@?uh!+v(_%?xoIGgxk8 zG??tnYE!Y}G|*^8yGd?C-Hk6b`VP0Xas@BNv?B{*93{JBPkp6$X6+VPi=o~SWwg5n zP=E#;3H)p`|COW(E%IaVvPr@h$h%7zRc-cbvhC8lBz20V)k*711eSz(&O>@iI5J}W zVlyCv+HWk)<1fcx$7ZWBI6qp{eMp*LBSn=s0;&>AfTJcYUK%|-ACPqTj{c+7&nI)G zM@uTrxq0Cc4Dm3|*o}ZHpZ^jmF%WuL&;5X&-ZXr<-L#eNDGYE~y`3g)hKa-Bv>616 zg%PXpxwxG7uCNTp67X7X)vff2g(C8&=*JQYwz&;nt*~JHDL};i#pkqD#?nlVbPz8x zAc?@+={8uyzqYGu?|BMu>{LkgKWIc+od+wJ090? zaS4KSoNOgN3t3!F8yOI|h5ji+NFhr2iiN3C21z0i3z|-+t$?JE3E7U6ARAZ~owrz| z5+pq4rbWa!%hpXs;#W3IM&XLYz2ob-i`=flMNHywSOMd`EM>U#z2uV71zV&h&`5-w zc(7^LZ4??BFPFS-xj=?D?8I*iT}>cCUr4V5c&+(a1MC;)o{^k5*1hKSO;G8qeFMp5-D}q? zH6G6sMS9Z$U=ZJbZGCWa6qg>^sRqn(0yv&TU*_+*ykMIKKvb*kj}Mwr0RmDoRo zA}hv0N^*H5wuL)DQK*nKh>n(dD>_V!k>+ghq{)UAFAUql6Z^uJrPBd(F|g#AnR~_r(sg*&hY_M+@$)U0w?p z(Vc`Q~5!XF=-MuobkG60?XVCIqobCQFuM!;a>T^ zWrts~Yh?cl`VPuS!w?7+c1u>sh3{UDrz7<(Dm2l?r3W?dN??Fp;OKTiE7@Vlc${um z@t|g@XhKf&qY)!^Wg&;@G*otI0=5FTJL!ywT0#z&J?VxO7(@b&6U~P8VFKU)GqLLs z>bW?@^74lk?#n+C6?%|yTL!EgA-ts{Rj!36NWT^532{qmI*HWR zNx@b>yDuy`*))iI}qmy~?UUuOP%_f+$t`B38h{K239P`r{_{HzdY;^NcTbg$6nnn1NP zg4%>?`_8f_7ZK+22}~2)E;+5?v>GjRJEQJE6POmvA;4OYLGRAOr6!=_9!1OJeR!9dZg%jI{FwUbwenVi~hpmIq1EN9(IziqBcF{;tOBD@Z zUj;h_JBddSfJiEBCy2A(^7FAXIqwQgO**~BcrXadR89YiU?R5xXmtw4q04RR z^eI%Ax1O4KR%$6u=F!Yre$hv8cbNTIFIFsu5a+KV+E9aK!x(p(ZCgw zO)T4B%E=CqP`h~Gg`kVs@htS|G6@UjnU!{dK7+Ek&c6og+a#uThJ+an@#b!Jkp;(R zRQ2Lb5?1GAMUDn#1ql+!v;&P+e>G+Efv6T*y^8Ybjy74WL}*X(`X*`Gl#)J2d$}uV zxuo)!2B(HRP1=<2-&P)B>0C--EM^GF^Y08^uS4UlB7E~GfM5Tm9p=M^Y4v*g3h6Oo zvsQ6gznQ#+R8K1(q5g`0WJ!t~k<{t!cyr(q`1uiycJcZ6MGb$E^~}68pd&!figf{# z(Eh6YVpJ6tZ^aoe`BR80@mzhiy@^J?zTOxmIwc=UgkYtcb8 zuRU_Bv#~NrpR~s&I?{DK?;JPiB_GjSHbQ`Ky^WuZ1;V<%ND@M`CsNceEG$C()Ii4+ ziRc`?;J(HvC2B0vI7bj+LQ>t+9z1nu=9&H-wvwWeTR{Q3zzB?NW&*k_KjoY~)PC@t zs(s@@u%xexTTApz9;1lV9;3nTFD1{EH9a>fS%TcxL3U}uO3M6AMG%@9r?goR6W))W zfBLXg93S+-H>w5icm~@gtogy2S3NvHOTa`Xuf#KhmalBy`jZ!j)GNCbZcMGGYAJOO z#h79_KiJt5uO!itpDGteB(1jOe_8^eBhvSy4&p%v)PZUq#A)S0TP^04!r@>M%UO)u>5Kk50lG52(ikzi)$It$-c824``y=BOJC;HsvFgBe}@(;ImY0B(`$U4 zzzhwROP{h?AdSuE!OEer-ndwk4)j)WB zgW8hc#8l{a(-~t|F;OKIVJYBt%CD(rLl)4@s^6s5pdqAP#?gffI)3-!u8e8=BfUnQR9PAaeC_MyGWPkU;cd_h3C&92 z{-by`otbmJgY%W1bCPnBRtEea9Ogy`cN5@uW~ElrrN7Hpcq3MZ)>}~H6{RCi@xx~1 zR@L!+ngjnbkvoVw6YcPm*W6m$BxRKz zU)2AMg=t*{aOAjuTpt(5GG@<5j?T)q@#kmj)vox#?Xe@}Pg5cVCrmYb+5J?abg4i! zOTwNiyhgL>K-+Ypo{QqbigNLdvBU9$!Mc^AJf71Uvt~wp+xCZ!e5saA(sG&=KamWF z{NcD=_rGSZwIc*eq`6ZUrUFm*k-HQZpOn~6i=0tTHQ`}d*5ey4kE#>VTnbh3>_0a) z!gnRg#_m;dozK?Ki>vHb4_E-4VE`+fhit02ZOO+y7Mn`5^EO4IfnlKur_1rD$bad- z(x>QayYE~%e-iX`>0%9x0Nh^4a3_EK_1LtJ(w^s}aEcvgs+3As8**LraGVYXkjiFx7%|d8oexFAvSbv9g+QgO^M0Gw@B?xm`i8Y!pY5^ zAUAt=1FzAbri$B_7Mm(|Ghd|D;PIq%IgOAQVUKP)Yzj@qw@dcVerE{ru=k-ujW3`{ z;oXfYXDVi;Ng)84ah}0egt$f0QzPRSboGZ7K4-*@^X*mRiZ9P<3F6W%E#Cw=Uu5G> zl~2uN>yv=APByuUUTH@Ssh$PG0lyf26M@Zsnl^jn$00xMGx`Z!_33C+7#=> za>8PtKPMe6ER-|d!moim$M8vhNq#G6pLZVue8XvzDWd?n7#jP_-g0D9cM6=@7&nS1 z^1mf?bgb)wS~LdgxX#f-YUVXg=KRlo%k8ozjHDtrAm)RxwFZ=1r%u5-&T39vOKv{@rU0b zd?#z|qz;OsZbuF^BzKD!g@Zx7%$bnlsIWggm;WSzW3lHHc=NM^Ls#G5jDS`{}THu zo?`e1NR35W08=i=rHy4maH=uYDkEl$8j|~g*rq~A;G`Gs9G16P_9G-Rv}&G<%buO; zMmyz6y$Pu+|9rk=@2spBeX;P>p}j5}g} z#YULE3JK?%(3z}Bd-h@kCsiu0)eBbiaAEwLs~anNe5Z%MTJI*~nk(et@IJ^p;w5hF z#H`K=4|^jv1aFD(Lh9vNqh3=Jo&T==0-x() z0^=P7Pl|g}z<|CCJ065HZ@$u|>aYtx7AMY)i_~N$g*RJ{`Pagr#nuQ|-Cx-H(ZpAQIz6GP!&m>9F$G)-`x`J!(HLRiij*tqP4|pS*9RXxC zCNw1n&^~p0&{gU_@%E)HTcagM(MwtRB>*+*yJfsJiHVzK0PJ&=*Pyhni}{U;`mSWM zl5nk6#bNb29f#%XkXT8d^~&8x48-i~k(2QU+iT?FR^nL1C=?VG14)f% z+!@bhf^oS6YnQH!Ah0W1N^fUL>mNt91Gb`!kqvigA zGcQBA`R%b7LmHwM*HWqHFX1V{0Q(a}5r&T>hkz@b^C!i(>0aWkTy9^I>#7tKlP%O3 zgEsoO7(`LK?<((^KcnlceqjE@zBFlg$9%0OYI;!}u6X3TVcM}@zwmEAidHy;m~GE+>98V}^jib>~NDn#AMdW>W_ zh}Nwb;m6gSyKm=q>{Oc$RG!r5IJltRyqN##Y+5rhuV(w*{3v)}_bDcCyF?)yf?^AI1e+X!$gcuiVl7-{)B7HBm#QvQ&v#q*0#_MDop!MeL! z#Z1Xe>3p7h;rUtZk+Z2JzB!`?_N{qO;0K)7c&6r0(HTtA!RC&dBy?0%9mY&JeG9G8 z_gR7GOTy9bG16A5`-+xH{IeYzq!X!4EgTIaYuA3u9IPe}Na_vUQ`It{!}B25%D2?* zn0$$U zu`WT2FnTLoeVVU;u+E~6kXTZ11d?*)+gJIrzXo`yUbx(aXbJGOe zHgv4T3Dpn(b>-i+FJ-wb^5}w|=fDknd>n!#x)wm2&fe6zp7b2$T1Yv$M`i#km8PyNgD0NUe#87X3r0QDlM1yG52mMuGW1b^k+Nd;#>OV(KbBT_Tqi? zapUd&y|v(j=^}lg8j80G`J60k`1NklB?XdkQEKs1OvnxCv3>b33NZj&%yPYVin$4v z&R7a1`yWJiNp-P*EZurksn!4d-&Mj`@mZgrHk~(4-Y;c`?>LbV-&s4R(pE=_`jb;O z7@jFe*>+Qd)INd#BF4$~P{ZX^5^^a1&W6h5x=YOj!ZzQzB*8N7Es*T>h*T_SMonPL z)0v<8o+E1kqOD@?XBMtKyYV?#e+U-|n@P11@e>c9Ye6(2%7C=XT*OkE{T?|oS!l6o zv6GYGn{iZQBjvf!xSFd>_bN^3Dt*qSWnJxQX?S<8Ud;#{pDd3Mf;NM23L7=MvCgTh zL_e$bZ7ZD}R}7j={SuP8VbJ*?YPB4!L4x=sX-pj3>&O9;f3zmfY&TadRBB ztQ~8!45MDxH>j>AnBtH2b@lnocN`wq5BaI!|#$tddB+VK!^a~5q5^f~%4CJLeBo_Vz5nkQ+|%&C9v zSuw}dsJfGMAXTjTPiPCbY32BK%z4pCjcB*ReV1$&7|6;1Klvu=@Hz~}l(F`qH?BiJ z^kHkIYr&Acfuw=>$%WAn@q-K9_1!jam6RmA@p1othveH0-3o4fA#4?dUz*}yOGjrs zot!6ml;Z1t%m|>3$Il6A!|A3MnnxjGQ= zSfYxnoMJuV9D8rW85<>r0?_!-nO?t#}^G=0=g0Hk^DoMo5NLnvpYzm%BRM09R= zGaujreiO|hER|HYk!Su!1ooMgRx#~N+!L3v{y7h^iZcY?LrbBajsSrYBR6T2R7F0j zzZWCuhp%}m{MJ0$(>~JUGlkd>HVhZ)dG2q?13EWzW(yRmbANq?Gkg`yblcIm3KDcs z%?rUCcma}Y=>;qNRP1O5%JU^x1sy`jmmUC;zF4)l#1Ov+#*pa9VjmaPGQ1R`JlZi;wSP=Gv-4$K?%bqu1;( z#r2(RKgMa%-35?ftSR3u+gHkSo~v?@n>p+IRm1tfA(VUGBa7?DK_zIN#QXv0?#90U z;zaXSc$0imW_)`a8MpH%wx{7mYM*XD#`xWv=B1ryzY^nJ*Y@4pd8hCpZfa_KQA4h; z)auopPxKGV3Z2mYJM#6$qH^`E_j2h4^?lNEPRf-DB%&KV|J0hN8aCX+yMS(gw~&(* zuz9j}!8W2Y>T91#b=50UCd8SG>z8pW6g|!mo}|l}Tl{Sbw{!9Uec^OdhIX*|IX>#t z=8=u)kB(}1^bQ0hLnxcczhNgLZrb}f#UF%tQ%X5$qK?m{( zXTo_;g$c0|P>9x`oW1y6A~FuB5gEra?{_g97~x9GQ1(C?kHYQ(*e=Z9g=Zl$w;-nd zG_=tN0C;nR2Z@=Z#~lgn*Bw{dPCH)m9pB#6bcHbB&+DzZglbs$6!4`yZF1q?%bh=E z;_lZ4&@<$vH+^*}=P-&%5hZkX8XlyHwNpoc!9LcPDNI*q!}XW4h$1#RDGC;sSk<#B z@&h(n*!JnjS~k@HX(JoKJ=zS>shJ?|<#>DjsVP$ePYpp+P3BTTlJsI>{gi(E+5SH$ zk%?dL!;s`wCk}}kXHF5<4aVzoLIOxMRInzhOvO%uvXafC;w9uAA3#bQSO33`GT#ku zFGo413%Ae;9t-YE@1;p%;2DLFtLgSxrzJtpm7Z@bOR=V9O8oME&|{m@EO&RzPr3wn z(uCvp${7f8jNBbS*_(-HAt_Hbp&*%UzsV4LX$#L?L?@-y%1omrzmtUv0}UnQcEiZosGpH8nD(L6L# zaV*X4+Bl7(qKdNHu`}^$5k#uer39pe-U&*Jfb`x=gdhkZgwP2IA@JvW@BL@a z?3uH7cXsaGxihnS&hAuge__{=Bj4`XyGP1=>7v_(|5$=x5g2EtDoP5Ds%25{auPL2 z*7PPm7Or<;LC0`e)*S=SyIK#B6A(U!0MfFO*x*48?(~NJ2{bd+I`v{+>i06EyFROI?gWUJ} zYw-fY`OVKTO|PwvbSKC4Bq~2Xa?dOej7&5rYUP~*PH4V5(O#3kccY3?c$W0%dq8nw zRGPme#ZB|OU@)Z|x{PgOJ$Y6kp^j;V!mlM4V>Fz%;RL7kQQ|7K>=Cnv!Unw^S+ zNPbJe2^Hb|Bn>OtZWI?VaOoAguVDLuog6(SRl@uV&C=n)QxvSA4gk6@JuA zgs(bXEyzFVowY9ugDj1m4Qi^9#evrw!ys+>RA<2<>Rw$&S#A0VC8$lEQ5Qj>WQ;ei z*waOH4ktYl-3ks={`Zg0N#&wtw0>av;Ckx{%f8hXhNo#wja!5V1AwpT0CSv@W%#xxwT3+FB^D?2S&%^PE9ffd~$bEK~^XDM$teImSqSZ`J^a6ao(_F zWMg<>fj!>dy8iGQW6z+#r6+e-A20zFQ5n-@fK{GJ4M;{dMu1o#m;GorrJk zDFp%vv)5gg#AE=khj#Odr5#*6Qdm@b)JS)ZR;s<~nT@oOK^ zq#d=$`T6oOEYpo)nxWD_zyZ~;a0uCWLhAkX&V>VdjCzWu!19WV2#cm(-2`K$9bE0( z?C&8-EyjEFXt2g59#rvw{>$uuV_(03*TMjU$Z=p2nc|20hVLRO9=%i3W|8JZ0G@f6AL@ zF-zJBj$f(w6WkyB=?HYrvC?;Z^tc;(R_|*n-;{mdN!Rz}a|5jQ?a}dK>Nj*rVeaUF zYtam&kQB>|^bs}0^(MBxJtAXYA-5mQK3h5#aJTv*_n7sKuAp?l(Wr%I4qJn(UhN=T z_$_Lc{ohURNp0-Xf8`Mz57%o{Ia+ITBu{D&tC=FRP2EPyPS#9NQ|Z-+ahO{cqD}f$ zOB24)wdh~NiDx0T%d|?ONvZTJj{fxHv_`N$WV1) z5PE%d#8RwDP5QA}`rEYG&F9vLZS*?ff;u(egH?m-3vDHxQ-`BDr=H;NWLAC+7A+k4 z{w1m+bL!c%l^;4^eLtTjIW*P%?l?cJlLM+tI%5qXA{w6)_YDRZgh1crDy&P+w1U-= z_SA$vj@IQ&{1M%UU!q3fZw-`3{yfMwf9L#`Wx%V$;$co3uZ{;6FscH!S}6q__yjP7 ze2*vNm5=_)pS73{TIV618in(6Jx4Vw{^3 z<7-wI;53+9O0JeN=6a24I2p}Y_%@O;@Mf+KLxaqCma#GIrg)(JsiCsfciXQxP1)UY zbUUlj_LZF8Ud-zL2+mYaPeQWTGkXukE7t;$`rs66pVPEwWznmrd{^E}8`G5)82XA- zQ%Zc>IxIULT5Y3HH+ZqSZQ@Qo@q>PaM6Z9Vf3NFm)nFul|IpvX(;rXle{cOj1!Ru( zRs8JzGn?D8_Qd8vYU6#gOk(g3*kB_$#$6ZAt`ZMDu1kOCBcMdE$DDxy{oP8QEA7>a z#Iq^uKk+_`(?|~OWXtDHW05k=oTweFt|&F(Wd+1w$GROF(B2w4+?zY}TT0#M)9T8` zixSXk-{~s+G&`ZSH!N1W@#EBXnvsK`H8tevlc~nwj<&f-Ns{qXhe6_f>#Z*y;SLQS z;UopkXU8ETNi1sJy_#wyDy~s2-BDCx)aG^I^=S^}yThe2UN~2s9;p6Se7)NN>5%w_ zAl<*Hla?%`$19nhZV+7B;1~OTEp7jihobtXp#G*}D1f;7;YVR-U?A=-)6k9vFS;8FR`KZ{FLp*GlVU_eN4}_YjBI zKgcpiB+-2^0bDxN<(K?dCkFsPh@k+Z%)DYa9cc>)G4#*B2UF1*KSZaAftWiOIqI~N zHoNlZfPkLVgG(+!>QZwN$MmJ`Ol}L(#NE|A+pbhVrg~X2ptm}Ezq+VKPV{?Y`zTH= z^&*NJA!@<_FK6s2ktPHe+%8vbtW7jOvZ5=Crx5B!>zND%clQiYbD9MUJudmuxtu{Z zup4o*eNqxKPN(v0dXe@GwNJ~Ia@Cp|#r)#dePa{GA(DPozcke_S0R#H2Nh}!Ai~~w z=)7jZ3E45HejlZS(T7TY^I}qIpl%yL|4~sgg^Hbxh29%hN77LhL~G89=Pt-C`?*~5 znpj5=$&X9?iSOLci(mLon|S1H5gF!^LQ=M-%7=!H{|TskxJSkDv0x71b+RHZ$t|nN z5Gso!Tt!JvMK_ntnO`f{yZUWpRbNv}*}FkwbQB@sUI;0HxM&)Q;tq$ir$ZrrQdC7U^Znm9AK-vX=FDbpc3Cu;%@yM{hyXGSc+@(?`I&= z9ob`}_VW{?2GSFI>chFSlzFQu?bz4G%U*JB-LF3eW-gyLUwE1=@FA&2bmZE;oUFNm zGS66p!llM5;JLrl9R_;R)}5E;rM`^d%W~k}AN(buY*TG1ulDIbn1o%i+-=R^6c|(qZA!8@%0Lg4^+F^qS7r67bOb&c zrZa9&z7#-&bSVDXW>IdpvTF0aA<)p(bue#wU1W2eN(EF;ZCbe`PSX=PnWt>sK1TdSTjl0@ zbDXtJd(UDO3&nTj0oa24gCwdErV@swP)@uvcU_9VMk5Bwt-xar6j{qcev9Eh$3WOlXU;_*+7=+na2mv`1) zYxcZ(iuIQEg{yqK5Bgyvk)IOO&iyUS)2+A67BV z_-&I?#R5nBmPrpwWv&c-IzSaM&9wRLetV0%xt_l>||rS*2gA5mEUn!?(x=3H#nV7i)kCd@tV&wC3_ zMyFpF%({pg#pZt`=?hsP?$*|kD|JOu#fyAZdg3WZR|#1jx3bNcw=F_>KlxfeVw!-6 zOvH!?Dqo9Mr#cSI^;Bwj{GY=pGlNQ+coSVD;Y$y_lx_oZ{_}Wd%D6tSG}Bs1C%b5W zjxVt&*B%3VblX-@HWxp^NDTcuz;kJ=Z@H!gfE9o2%dX26rps#aDjJA=R`c?RQtkLr&7LnJu9^rcPGOq({nGo!UbGE+a)UQ>~Gvy zKnZcJy)JPbSZ!PHth5Yj{kd7bW+I~^?M%L==cjPOg;l$|9q55P;l+|=5zv#-!^krZ zO-{80+d?b733RnVFb4fsbOoQ3qL7q39?RolF*4ikZ5@_yD?Sr8@qyrtMW!4GQZ$wx zYHq^U*gmv#B2rgO@g1bw5V)e4|bhvh?t-$K5y%OV-6SwC(XBYzkQy(!cWIvZoEvrR7=A-I>va zsxhT9=ZXYxbIm4GIiu!Oq)zSA6oV9lg~zaxoGS`1$TAn7_FB<|ifx<)Bch%-+SQT*s=@zn8=#wOWn3k}i_k^@Cq5j5tO;MT%rDi@LwLVwG|BNL(fI zY&X)`+9kbT>*p>Qn3wJO@h8!0O6cS$?kT_(N%b~;xdgIad2|DMHWbKNyzeB@ zx6MB8^KnkujWyki)!v4Kl4dj6fcshF>QLEIOJLY;u3o zIELc1;VmRreO>p`sCI=jFY?`Nr&Q&US&3w5`O7RCly(Jx2d4M+bb%JBx-@V!N@JR{ z5p`bQRW>CpbcbwoKo%R1Mcs%Wi_L4C^6!NxzCH@pfG?aO$~9HEO=YB4?eIn*`u8*7Ek8_noXyS!6Y2&TNaxT>x84(rtMx?>cMrCusHX+c67X z^WF=+rOv{MXJx3^W`_O{Xe!bJEw_3oT<}ie#YjVU)<_Q=MS{gteF{C3R0bkLZ=b6T zQF zI$uzpUR1_gs0e$T%6PkxUC5to$`FwfYlnN${0NyIfe1&^DzgG2(lep9fD6QSaMAyM z&GgNH`>E0AO@^FufExi}u6y_l7gz1XP*d(87)8~yQ5C3jc1+G6yT1_-4nUgDB#dMu`Ie#Ki&<|-wYkD}LgAY&Rh zqLcb@`%=`4SmzSo)20k_2ogR*ORUlk3;IB`!2;~kjUfzbzz=>K3Vao;D(t@CTchjl zlP8#hbJdU1o;D&*z#Ck8R{B<*L;Jto8B|_Xi@ru7u)!swjgni zXO0AKaNcve5=&~svH?z1dxPYAx~|<=R~2fS$wM?PEV+Tp@r$NgFQ%Q#MonO)%Er){ zIjI@Mlk_~O>QCq|@myHK5qq7zx2!Xd0rBny8%0)BZ`AGtL32UTOErQ|MGye_0Z8RN zbIM>=H76g))X!NB#m{rTyvg!@3tOm!IOyco?fj;&1kn0xDE<`}GIx|wr zS#kGz`;+Uox1gVDS`D6bI_#X@3%NXerKMr0p@jV6r0aa$E76FgiW2qk^^_?G4Wxql z;s&gIC>8s~`40=@|Vqh8@ zIzt#EjMZv{Ffo;i&#V$eXz(hLGG*$ZQl)wMS)Q@cjUPiM!#{M%Q2eoa6ONNNgi83w zRjvjdGETq2xdMxzChpq>EV?HtQ50N7HRjoEgOT^{#6Lql#58`KSp!qVo>3R3(BkYQ zPI_)+0Z=2q@rS>ozI4PgvfXvl-?pJQ^)UK;7`qd*FN6gZkcQ`Ft@qq1M3SRJIx+)VEwi<-1pe@_&et-k2r^5tw7Iniq9YEfc(qO9#v=61+%(Ho*@Wi_$@NnM)E zhd2&pA71cGt^Q_&F)2@Q@ldfT+ph3~3g>`Ik6hY=0{%2##d@%VR>5f-7dq0@Lq?5n zs@f_N`TINjNh`)1>>cJ!5i`GAnq&p+`2}`H;OMX0ZT}Y8)tCC&O?i_8G4JHbZNr{e zi}tqQCvBRg58b(Ug2(@{ANuJ}JnpxZRpIv+rp)JN`N}>}4TZnu@|gRVKMtwf zt2l9OlBFbEy~+B)X*sgll|z#C+=b)QwbE-%GL*@0{_u%}&}U>6;f?S^WYaZdIW&*( z6wC!H8F6LLDfl70J=W}oGCAi=7$_TX3$6=!@z^;g*rv8tNU1vZ=Vp8<=P4^R!g;7% zn{6rYx}$BNT1eWX?2plb^dWY$e0Fr=TitwHG)(o<2gVO0jd+f)w{Gcar=dhCR;Y4*7O;gGbS`)C*zL+aZ*~0oNO6*P@VW7T z=s@rji$vFEf8e0^>`S>$@Nr$u!Y(Q1GD8zi22pMGaNNqbUBm9EL(#JIEL+5x{d^O{a)ibW+rSg*qs@*7Ej<>>{M}I6>cbV=qW!)?;jGo zb!jk+!`R|`SjxGHID>eJtu~$+U!BKWp>Nz)NVv7tu)iL+UI;P)Gawol#`h~3_VkR~ zU$)nT(20fC$Q7nSdnPa|kc?hMMGADfKRtp7bMX{P~9 zz3Ef;jbsC3<@35P+8g3EMOX${lM;G%KTZqFqpJ?^^5~_Y`S5nb^T^^|gE61P1hC(q zf>my=Mh1MgPZ~!27?%l_1q)vpEVdL#ENW>LKVMXpZtS6$Q!<5D3zybWVxu zQab&hRcU_VRj9Oj8B_92yyo3pWDRE6lH2a44utn|k`Ln_KNzIh83kfR^UohQv)l1u zOcj%fN8bIamP0VzPQ+0sw{|DfUZpICr-=V+D(cZ32-E8gtG>;S`;JWWsZ$buLLMHHa*{anbSHH&0YYd^MGoM@Q%ucnCNv6MdN;w@x~;(q)OFE zk>@6BgSXT%u0SsF?jBhlulyl0{XHvB#*8v&Ygwz{=Y5 zF%oMks5adHtmtSyjG7yX3fRCkOB7LW&Fp`m$#sOOw(iyNnK)IH=jZcnyT~tL6_9d{ za)!siLw+SY+rE?6D7o+2VQ_AeSrun&w`GcRNuUQ)Mt)-f%fB-75@M64!ui;k-+WQ6`DWRn?Lx=sYCL;h(HJBwj(LEE${gpW zlR2`%BR1|kP{KS0dFGC98=Z%9crHWr=6fIFFqQv~Q={G^b-LA75luenGLeL?(CVcS zw$+}&id30POQVT+-9o)siYl*Z^H#&eh!6Sx<3^1)@Af&6|}&jQEJFeF=s#hJ0v+*0Gk1|`36uUBTH zV9`ZV6D24Sn`(44D{IB=zVtW|{VD-^oy*{yq`!?`_#uv)z}pba&7Qd%1RTAaPgFyc z_io>G-jRu844-{SN3^bo9Da=w!@F+oi4NSwgtkm+;*5=9GcK@L3EEIGs&(N%Vmo~gBw8$$ zN}aNvaVbXv{;Cm^&ORQ{K&}82VgblI==24*)l06RNjB8WisSf_LHXUpI*Eo_&P; zy;OfYyd-NCyWwCCC)N1j`z>M)A-(*Q&?gScO@D)>67yP-;#f&; z@p)$TfX)Q}?ZmmXH7rG>U)jXroN1o^^VU(4V@t`1o93F5bF+xSf$&$QiT=~GKX&KQ zfnlv)I>Uk`_>)H$1E$0hTIRbGdIR9{k!<4SS`~Ux%sX<3bLUnm#g-4O$!5#yvApt; zE5^yjW(b3itar#a#1R^;8_F3$|fM1}a^UrcinV{wv~=>n+K zxOuL0k12FWx)->~2H)aalj~6k0bO1S54@&N6bb6p=)QBHUktpq^GjiuX)nQ!W+^5R zkm0Q(a?Q6rUM_i@%>EiYH^7wrR`(=Y$|9$S_5*Pp%T zF8A4K7j&;;1LJ44VsoP6w{y9P@bNxa*#RwB2aDe7xDS?hs5i2$x^QIHvh9I1umoRm z?~UDh!b8^i0+n(=iq%=ENei#7h2ZNW(tS|$R2`5bTt2h3VnTmV*%bgCw~`*=1-O9k zRd(sm6w^R4dwgfC=fdP1)AK8*@xU`iToJtMiBAnmeEY;QYm@ zw-TOXPC2oTjP*;GiM&9#T`N?c0zJJ+DX`uF&-`Qyixhp$$cP>d2YfR4`&{;>ek3!6 z!)@*&;ytyVq^C}#QGQQ7{YiZNSE2sxciAt&*VmXw0`A zWxFf_&V$)|gJ?j=Ehpd}T%8|J@)W95;{oUOjSxi zasycL+uw=2vgrPCC)z7rxHjkf<|=(fmW%>!z4CcBq1$Qqsrzbs`fdktHilbXKiU@Q zW8a#nBioyL921?8o<9qyu#ubTnKdm(WglUy5`&I~XF805-rmP(f6%qXg)w~n`EV|q zVS92u%DHzSux6tnD$LAuV;$^wkUvSP8#4Z~D%p#1sF~!QwK1hT%^~f+`QSphF0(&A16^K$F$UuxfSx7)@@8^P&w!$L zqv5y2`QjA$Ge^1hc1~Q|d)h^B&)V?w}F5YK=clr~BC`w;|%nEuS~>F=_HM2f6Gz zPFv+GY1(1N=}WLLr!6+g`>k-{4o7cuu$EKGTw~TiSheR@N|Pp{=bwDm1Vwbe-F9N} z^}DsUX@oBPEXHBexX`1Xl0HP%vt6owMriyh=4kaRBB0mm{&cTSDu^vHx$~Or6qg&70}Lx*FDqU-`=gQY!&Xv4`b#iHetj%l5U2 zbik#=A~fKc+0x zQu#nMvI4JV0}h9LdM^2kRC0F#&vdVxjwjxsb`nE3@%=YEUPJVG>;D4$X3HxEV3s_e0;<1{A4xZy6YvA-|l zS3JL)#{~SGdh(DPH_UDkQ|;8@-2orTsk^?_HM?qg0)?LHp4{Gj_h9r=7d(b_Wpd_I z*Qc)A-qvR}7f*HfFNa=k?Q_zwLenU8CR|gTsSgiqyIxb^qwEVn7JB}L?@bb2F(39S zk+jHP;=jcQ&y_C*L~_|_&KbI!VaUR}gGQ&{gB{kBt?bV}kN`)C8v>IC#V}nJIm+6! z4d}}cJ{0@X$H2cfK{6zoB~MY*>vw3uZs3EnT}>kI>CLl;qw@~6tXYl3?N%4%vq;Yc?;5?<;#FQ# zGrWxU?Yb_W7I+`iM-S*1uIuxQ>V#)~(swM@+mL;^@qTJ0gS91tBCW?&;9*O>3ik(` zH3_VUdz>{r9EkUz*KJ*K=evwVy3>e*j*p0%=HX0atK11A2%%x5fXAJ+Y%fvMgEY4h zK;`9Q0U=bqt#NXifpK(}mIdw%f)QS7rOq)L`$k*4TR|N<0RgY#(+^tH9AHZc>?w78+3rA2RFIEUH@9L8gZyHYH~&-9sBN5ULbd zW_RVaal%`J_CqkhCXcK_Lql_Z9&{ltMNap&-R)lVyMAn4--GCjLTrgao>QGpa}*Z- zElyH~-G|>0OY^ZjKF+A$ms}g_pH+I!)bO)JNSIo(Cyue<8+Pw4xWq|IZ-Tv@FFTpV zCqqd4!{oMeh4up0`!5-2=8O87WuG!6SaK$KJyd(rc!5V}IrPr2(XW4=U%D>&#!eL* zl_U0Xk{Gzt-#;4r>A5h?7{k|ud|hF|fxJ6r>tA+OWotFKMsD+!>U?=CV!`C-u&@02 z8E!A8^z-*qx3OPUZ=M@`(%Zc`8_O8DM8v8qkvHC(XgLX4*h|SAUDe}k@3)WoUGh%k z_r$_O77w$hN|vThz!YXJLE?DfJ+RbPPuOhwtk+BU!#9jf1H~`3y4__rJPp5;rwA5 z0PpVogEiT1p4s*qE7{5<@7oXIv58({E59H3pGSKu$sEnJSN|KbopNxqY%k5Wj!Wzd z??tmfO7c!S-R|Zw_QNv`4*sd4o(UwF*k~Gfhd;H>fl_!(pnQJa9*(EJ_mpnjdeIw zuh|$H)dNr!6E{n;_phj|ntTq|_bQSjsD0;3^U>L@sEy?P_)=?l9MSRg)PKu*d+pLU zLG3P$=Q3P9h$n>8{cnO}x@>sv2VL5vlNZ&(eKAb?8cK?mxNd*?xd(uQqY~LglQi60 z2BizK_;5cYMeN?(je#+m{JHUhkDyJsn2e3 i0eCt(10f)6^W+2R1nX1G8Hv3s#4Ckj*_Zhr-Tr@y_=v;+ literal 79262 zcmV)GK)$~e000233jqKC0001M0BZm=00011WpZ4R5Ha9RJ zFgY(WGA}YPF*zVpN+3*WbY&n#WNCD1Z*JVX3jhEB006%-0RR91008C%0000000000 z005pf0RR91004La%zbry6iM^<3`B4Za=-z>cLJ%w;c$1i!`d{XNfcMza(;fM@lEZkz7e0Wcf{Sm_%UsDn9@F9d7~sx4$XfCp$+^TYX}LnbS#bE| z0*|ZS-U+#+?4QNwRR4NMYER;noXBtFn{PxdSDPl%5-}|aeJh~fMJY9@3up>K<)!#O zsrW44kuu89QZD(8BfUaO>gp%19xK0>oXhW}_FTW0d`dk? zi%5CX2`#z$r2PC)=*QK^vbntZTtFpn5@$vMm6nonNvY*K^0O=@pE6#QPa>B}sN_oO z%GFyWSF*0uSRySO*D4VI&*cB(@sj^@lxg_WdRBHi{y(S`<9~NK7{6JP2L8UopMS>x zU5fuMky5jFEXf~Q@IU5@YyJ}CM-^V=p{YXyZFRm{7695YuEPxhKX1MlrtF!Enuq6k z`o-c~JVRjPDyV*=ZF+NL_Wov;z}&_we2XXU2fufP`Oq`{K8zYPjG=6{y|%fcWn}Ot zMx*a#maW=b=8%;xoKUIUJ1Za}ia%TdmHa=g0B!0&1O2zIt0lmNQfT&i;Cv~QwazEj z?3yd*k&5#&pgr_E7mD+s0iJ%7@GYKXKz<(#yu6svJbbR7`Eue~qpG(6YFZ+I16dBs zuujvR@bqTvVlShjY!Ef=wZ&XD`@u!-H}mOz+tUd-FT;&K0@1D)T;AWmXxD}U%-sUX z`Ek@{YXn$|^O;^tZ95d_f`u(Cm|pQfN&1+il6kRvV!z>v^KYJvd=3j{J^18feq7wa zENJgzR8yRLer4oGKp|c3)l_KqD+1@$6z7Auwth@!6z2-eC(miI2|1t6wXL$y`JScy z{TDv$Bf#I1$8-K55m(Ft=@jSimiu4gm70fz(n_%4y3+an*1F$g#rbF8oek%>lq-XI zCRZmj>%(2f8s!c`?(E-~fxuCxsAer+^Qk`A$dCXm-g$R#4OOe@ZNiyK0$sxA)PO0p zGVoMF!CFIW90_*qYvqCdf!}Hfa2jQj&9L`-6iP6d~Sr=HwiI8oB~!U=gg$c;|cDb+q(v zPa#+_CD=DmDT3Oa#!aRrhuj2v3{#&$5nXH-BZ!L)hTCity?SZy9jK+YIX6#!NS1l5s(?wvz3wcfgAoeCAV^7P?vN`()#q z0?$ImIf8di)eWIxpNuHF@jt7{1v@RO9+uEz?HHmj!#kbh`ul%ttbXt)SHb>P7DGMxD8UkC|6w>1*DsKX&1To@J@YabjO%Cy-Op!qRVH}^yw4G# zhdT|Yymd~C#5Glc6>3d8Rcs;M&FjXw6P$8QfB(|oCFeH9xf857hp!DyU=s0;^0n2$ zd5o>f*IF^>GMESNA4%4SQ?&8&9OJ6e`4rZ!RRCdHaCHcMIg#G%J?)_}Msc1M+2JY@ zSMg+?=EuAB68f5xwShYWC}x_QU^x*#+{|$P`O)9M!&xa<9JeJRBXc7YpuI$)1Uu?` z$##Il%86HeTGOix<*1t1Jalx1kyRzG@yJY9V3!d)Lh066PjlDg-p1q)RzN6PgX*jR zs|Ttd-LaK|lO++&VI%hJ#%K-ZFj#Mf{G*UpU9-)YuiDB~p8QTp4=!3}J4fx-`kJBM ze;B_h3%mOoT{q53v@vfE1_S4z{CKqhba#JaEBD9=*~?#H|e+J8bLg~9piTak3T z^Cy}(r=!iG^NFafGi|-w!J^d97)3QBwivg;5uWOZu?gRp0g8yBrz3pK>cz_%MVPf< z$bAy=BXY&MvzsV<{c8~=?UHErrjR=dF=j&UB_3f^BE-jBQ%m>zO|c%uP^}xlOW75^ zXYC-A8u~t7shz=E7>d3>!f4t#DcBzVLI_q4ezXyS9cgo%t{+KlW~@=iU{(V{z}g_D zBE$c4cpoZ~H$<>DnBQ*#)*7KL`3ztC%QKwH417z?%WbjQl}QRC`i4Mtv5iO4*T8vn zwfQ$=q~d%$W3a-w(B?#Xnlq0yHaFY)8BvP!SsVj;B&2I=hLh)OA7QaS73VRiE#g&i z-gNI^gVUN+YD<`UKU`-0K|9U3DRZidA?+wWeFTb-Id-ZaBf(i%FrjndW)ol+CD@{S zM{Kth=PSWlC#0ttTN_a1mgO`laFua@(TS%8gRK^jdrR_DRK+`;>Dj2hQQn~zh_-^mhM-#wTCMZ4*S`Nk@C zCQ-X7$mVCct=alR%G1SH)aE~Bgr0!hYxti&$LArP?Ipo%ZwX!sKl%r6|9LB#YOIvt z%pCs0-ai4Z2(_s2Z@$a2?fe{HTeQ@9P~{=l13LL_X3#YB15$o6YLZ` z{2|%1lruWB+#(D*Gi&;CmQFJstfNt;F73_XFHGXeWUbGT&VhXGexs-|No$xS32N`l ze2!9V&S`ol4>T4k@DFGtHF^jgdv2k5!QQ5kp{cQ&X>Wm_XF%;Y$ea`3g;0b2lJ+u= z+h*|d-3-0MMr4Lk{=aj8cMaAbSHZx*}Iv z(IUWfxI5?j73Yhfu*L3L%b+;Vik!6w?%;~t!FdZX!T%BpraV!LWv28V?#La24Pef# z+o0fz9CLf(sR+Dv@zE8Gv5o-q(81E~x`Q35M=0Q)yWHFrk+s(XGRhs?i~U0w^d#^U zgl1Jsv>-@*OH-F>9vS{E{#dpl>`=D zbT=2C?(g6EbprwB%96G047Qr`pSsdo(d1igt5QmW+HX*PDo)GRQ?nLbS-w!zZumBS zn0g(rv0^Rl)tJ6yn{M~V7cEq8uK*wu*d&gum?rv+Z78&i=OKgjFW)%_{JN$U^(frX z3>lQzuY^*|9MoKjVnXie(vt)d+arH{M3y3&~axF(!=m7s@w4 zk$GJ>h5bw~l4fe|JBa3e9O8Qoz>0Q<6v_Pj(E#Duib7=M(QCcUtk3$IcbbP9_gPQk z`M@&kKk?C{=^3imK9^Z$MN6Z=$M~*AanN1^SIl;L8|}y?lV%1^vVwL`Xv_~NvTn{` zp3E@7eB30|7^3Wb4_tY0ZOf`0PE#}bnyn5uF}ACAtTnvl62GHIHkLKMwMN`+j zH@Yj6^aoi^_nI~_ZF;k2`L-q+XkxiV6I+Q{vj*{qN*g?R3q>@La$i%daWzfbg|4m& zgP^{RZ10rZzaZ1sM8|2&vKG|8;y_BX%G+;|GD#@3_5@AM<=?$cPydeQ!%c^bZUQM6 z7xAGx`18LMO&dH+Q`;9~R8`2gGDMrhD6}JopU~$5#m%x_t&AkfVqM^*Q$S(&=8a^V zBbEA~xF^Y4@rIkRJD%J0?l=;2CdH(kbMu>8Uv#edc z2WWr(V>9LI{zyb<6wg`+g)gLIfO+Qa5tNWU53N$r#sV>zMkZsOTT^qfDn)=Bu z728|ZuEGmgB5c(QoMrYX~LnEf7m5-sKgYe;-z=sQnkz9RSv1vd*WrBcwCk z_KL5ahw+L|u%&%CL$P=Anq@s#8U2)}W@L}H%At0>fv4!egPf-MDag2>SUZ8P`8NpG zBwqv_e=l8>tWGT3hTF>9hzq<|d$&9+hdo9TpL@E!q)M*Pf#+-2u(BkP$2 zU*&H_pXmZTp&S@h5qjYEUfVduc?WPVX1rc}Y(SYjhSS;wTZ}zQ=N@QkcEe@H{2D`p zw)>ikmyR?xtE`wG?$8#rJM&1=yQDOzgSBfA`5Tkg^FIlta+;L;zLI+|!Yc~ys%W>` z+0@v;S`%_7VLWE(9{FUrLseu>RXf#z=|(=TEyn&xT-H9e zi~cz(nlA3nC43Dg63>1hAA&y^G+l)gqdj#ISca^c@zC*+8~7lC@&&T_Wvq=i06xfUl{hCOFA>+Y2RkUZ@*N(|`8m zX^As|wDj2|W4Z!=Mi^k0-0ItTBV`!mZGN&28hBqkN#Noo!GQOf7j)>Izu7MOFXOSQ ztzOf#fFA4VWPaUDx3#-rQ;o$&$bAUK>+o%~(Nl8%p1%;Be?@g+Rh1oXm0oMxs)DE; zOfnX<+kG2NSH{j4A?WCk@mx1g^`fxB25kc>LdtrbPtuYLGBYjX{+durD~P-hVX9c` z*7l82OR**x5XIc>Ugoo)Cg$D#7mPP5LY-jS@fe!wQCv7vxbjpTiD4`__gb})N|cfj zdV{l~puHIS>4Q{qA!jTZqss|D4^^CZ1#4%xKPP3p*a@NC0`wxu`7M-b((yh-ZR!J+O_dsN*I0Q$ERe^THN$F zG0^Z+N=?jUt-D<4<^G;Y=c;>|jVJCl4ucsyqDPaF8L(2#Iz=l@GJl)?)ZivWJ}HpNWLGEZ3A<~J}W&!25vWvz*}Bqv9{&Yd>97BlY*Z7C%amoGCTQtlnpE(p!40PfUj zrmepUg8+U{FOJ&be*LImY+%ALzyy`$kIu`<>)mL?k`W>dnyWDQ3cSmZ6;&AQozU5~ z8D_?F2Y9Q1LWX-j)N0sMn*R4!qoPuam?`J^Udx)k-qYOix{X;bGRjz|d~GlKzuQ;~ zdfVm?X-rnr#AMD<)j$ghe#ohXXM|Af^;d%PBdP^{h}3h88PJF3K1~&xnr72ZeT*YY zYgv$b$};;_j|y8UW`Il{$UJV@=j+9-bas^lGt|Wu1p{hkFnCKBgLNgF8UYbS8V{-6)4g)!S;>QKj)aXVVU1_{?AnJCcG~xL0bS@2=gf+;;R%(Y_{`@Ln?G+< z60`3~Je)-1KTWgd(Zm97>!HrK5})et-)D}Teea+Q3b)ZX(>PapvRCVD`^pm!q9Tth zcu2=qx025Fq3DHA$=|wdlvSR3lP#h(9#<2tGAEx;?_n3=C^q0`N!L360Sg8{GQIUhn&wp6s1*yqq;u%%%!`-3^6SY3}@lzFW~1t zjy$G;XZ_9Gt(zFfnRC&+o8T%vE7kIh+eoKwz7ej7&aKF)Y!bU>pirFO8ac%_Ni{X? zp|Igx=)Ecppch`#sP&z8&b2vifi=A$7gpiN8)!+sM`Ergxd-^-2UES)Sp4-{o{4n+ zs@p=)SqA8nVDv;Q2Kv9>t+M+ei{4y_%5#XLM1NobKgX7YR^#SC~BrY#z( z6%ctc?6;xI2HKk{KBqD|p|xx<)&+2&TrqvnI$KXgyBI9CmMQ2z+6U0AYxC*Q>SYG& z+~s+Q)*wr*2=cCyPGm)~!O7(X{#f|faC#f+w*KvWtj;{@kD+tr zishqs+BQHGJbPd)UV9JF@-Hkx>38NZyMEF9YA9DM0fpU0ZJkZhV}A#8?zkvpg=*&7 zL1Da(#rtoVt^BQdzQtpSaY{9FeGnk8Vbze6XDQulUy&7=w49yeWt#Yv+^?C>(u+}C zn;(T+tHexLp)lLd6=$jBBU!sFr#&(7I10QxR1C06R69*^vrOTNy;br6D)|h{w1R>@ z$z{W4ERRSYym`j1SLMRdweW8=+ZLxx!c(c5whxW?60e?g^Y}OlDz(Vyt$1t2f=T^# z{1Ht5=o!pG2Lhd~fuQ>h6yg@~aIK!~#)dF$!Fd_vtl5xGb!!S9on)(}kRONE21B}& z?R!$LyLM`3Z8fSYlT<)6A}ILzKc*|`$fUdB#xr(M@ntatcxh;DZ`DXzkTaLLJXuL& zqjE)FlwiEjTHEJi=>F3fF^^mXc62;E4`$a(@+Oih&)ufD#Vec|1FVwY2lyZSA?K01 zs}|US!QpGmYiq_^)dCA}b*SZnPaUf0UChjKL}kvjjz$dSxko*b>BY4#uqF2|N| z_RqyjinYl>p~hBa5@+?n_81!TGN)PeY)@m48ag<^bx$0ps<9F|3?W3D2YaVQBxTBT zf)ag_;0|mAF$H#ptLv{|Z`C3Dn5Pl9YnolO-^(5IYrov@L(dv)6|G?@amV+?g{9tVJRy%3t>|dnamZUhH_m*sbLL z1Bk`SL^QYCo>YWWbx?L|Mtc;qEmlXGS}B}nUz#P?uZ7RraQ;dnIS8OidAIc z$S&YNPtv4iQmGKf2@#(bZs4(hxCFORYcaY zLf!yVOwSO9xp}^&cST>b!res%FGI+uCbB1Hz%@NAj0)E9GW&J48{R6n^n@oIgi_}n zjiSTplU6mdDll&g2(WlND$|}nfl|(nri!gT8aWi_PUJ^^OKd#% zit|s*ggydFEjM5yUF;!u4LCAWKU5zNvrX95-+yT>*+1{9IA6kYORsa~e7|DtC0e2t zK(08)`q(lB#tgWY7M#%8c~p)!&rGyFIXC?#gG>$4TD>{!Z7zK$BQ!JK$I}?mHw0#z zkUEf}0^B%9Z%UsE{=OgT@1Lo>7I2LydPRbe zJ4)odwMBBydxz~>3V5@!80L`!6!K@tE$`u}|2dEBMD99|Jcz}03xB1SH(h(%LX<)4 zGZXrBIMcOqEon~kkrev;pn=6>fp;6rZ4H8EYp;l*=*Rw|pPEPIwc%V_!%jMF*^i;r z|241f@hR%Z%J@={yT2H zV%w%TPYjLx1>|okHlj)^CQ#_J?S`)c^U|GNW2d)kTA>J9)-#v6IClxd;mEw(h`aAB zho0GQCN-WaCl(f{C=skpW_w$4<~+($%`Np%@?T zK|U{{~JB_pazIb>g*V6VfRC{_il6yVA zg7#&m?G4&}fIJq(*2hz+a&Ia3Ggj&s&>oCV<}}wRx%0Y?ZM>3OFwF-FcxQiqe@fSO z7#;r5%?MX=&xE&xqd0qKH5D8BkI?yTrkxbD7eVg!7_%)MwSc0+<>-AL)BXh7Vr{N5 z@|cnv2A!Y`>Ibrq_&v?lpbr>%G9Wh@jTHy2xf*l?fBO;0#bZNjrFtG?yn+mt%P!{E zeuA~!oUpCn592ArKhh*fS3eP>Tlj;{vo)HwVB&b%dRT(_%K$Ow!EK4A{lR}GKn}1# zzMVf=o#6F9rv=fBO#g_ih&lo}sOV#$wT|`1)1Sc-Ij`?ZBm4ualW)> zdxI%Toi~BHefXbNspeoZI!6i4d6#m47>71zh@J^rQng!`P2q=iZ7~hSyH6}D9}A{0 zn0B0+W+gFWq8wF=0a-iz^+lKCl0q_IIaCD!9XdVPSO<=0f&W)z#X{P5Erb&EQw8`i-{qQQ5;nB;eOxip?+HBBol z7QxF%Rj|9YD|}6CE3W$SIVHMW(ahb$Wes{DDqe@t6DQw7%X*|1wLMgy={SP(42s50 zx6t;5a@OL*n|Rt>E&lmHNvPdvxxXbPhpeEjfKH_r_f$Vhdc>s4%)0DCdzUa~2gb)`7XQhQgrAVto^7eiN0}oU{|q_cW&->R^5i zY~VbN>mrQSwpKY+zrR7pw=mgW#@*{hU#7FnkRdbtXD?Tl58UsQJJ z%=*+H!W{;#pHIo#$~BAZ-tnCCPDW1U$RMhA=EJ89yW)Hez}eAIjsNW_<+)$fEcR63d9TmB;x3q5+Uek?H66{EtYoP9v zDE5teO~gDn#=1uOmB z7Bp|^Kq}&?`8fuAs3)JF6<<)j{q@bTv;l@=>#PE5TE3oZDHET38&KheF&aj|(-vGM zgVCFAdQKgtR5q7-?=hw+Pvst|X7PL(53o0Kx{dHPuiKXyZ&_=?9fmSM&%uS}vHd)C zZy?h>d=1}e*yL^Tl#Qj8GB40?JtWxS4)uYzKmXG`!p>3l_%<{#?`IP8EoD%#7&2#R z`)O)3z*lS%tD&N#5hx6RdD~nq22nbm0uwp)0{rMKQcsdI&uP_?`sTh$ zb|alaz7%BF!E967ZJ-{PyiKnLQw=YrwM%fb`w0L1siSFZ{3bE@xo}prGFCrO_z@UQ z(;v!ZV(=pRYZ&n8EAeKPZPB#*y9B3U)`ZshCCe%g3d$Yk?h7+`$C`XhG$ZE_W7#^y z(Z*$Y%|XAEG5D08d}?Dl^D9_OJ$^I&Tp%5}zEVpK;B5|Em#4q*Z#qaiGWZqMVNZQN z)Zz+m%MmKH)(?$E7Bm)0YgmJJ9DV5rlk`C0o0QXD!F+2s2` z3M$4tKsy>QANbRQzO0KvTTani4FjqLT%Lf*xJ*9D#CHNQ{K^XKBYtlkkM^rJR*QV{Lw^H-EM4)&)N3X_se3CgpD-6{c^FwLbDB0t>s*;Bw@fE_W+V^Zdi~?NyAbNYwXULvV`aN29 z$Z9j^m5|S!kK+77;srLZe=lK0R~_zUA8sT6VsoSbHCjc_|HlL?v#U&V1B0?}8y=xlU5{IuH7(Q5x zLq&(|1i-sN;n}_c^jk{lO!%@r|I>o<-Usx~J zPBVXwW#Vq#gKT+~QfEMhaQ>&i-`|7Y)eN8qeNGy~5mk7OVLVm{?f09DPigRp!sha& z$Bj)Y$ar*Y$0Q)4T41dTidHM0 z(wK>E;06$^3W_wNp3=<#3GT_%+!k9^0Kd&wQz%t5?-#+^6%^-ox1tPLgGF{2%i0ho zDG0na6lye=y!3vXW8rT$WNHgf&3(8&ZM;2#PUej=5-EdEgiL;LhrwN6)9+b|iVoR0 zmRk(&9|Ersv*D}tH1nbCkR4UMJ&q<`(%^S2h5SLt1Y?py{?##aaJl#~^6%kgMlT&< zd{@iFzoWy$qZGS7y8Lz;@rMjxp4+o{uRiYzf*e#lci6q{fV%Lwtqs%)dMRyuPivva&=T#6D;_PXaLj!%NOE}g1BKOuX zLz0=#Yz=ArZUN!+K$GK8UaF8L;T^@6H5nFD23>Y$hV!s-J>ca7puCx4-6ZPSM5cQW zB?9*<_)tBXn(GZF(ayvYTt*?E4kmKpWrh6qh|a=WEQ(^+i_O&ZhIHg8{z9Z4 zUfhbmSI4zmQ<~8UwcLSB6_^u;Ccq|(Ew2Mu1iTNSbLEQ5x3(8O57CZw2Uq9dilx5} zp*d6KN^VV-$C>sDB7-QkJfFPFR$0jnO4{#8->IT&(Iagntu3<3NZ5XlWD1tiD2k5l z=970kE15&hI}C!aZGxvBux+LOwPZiFu^LI{h3)n*=ej~(CTzWNQ>DGv4AqwbdBK=C zTGptju(yLV%nDfCRj})`x}K$PV=TXQ zDu^nAHqUW!s0@vw0u$x9B(dsJ6@%QhVK$GkUgmFoI-1>2mN%}e+9ObL2a4}=XVT92 zbiauu6(Ptgn!NkOwRWp(3yg891?~lfZA9&zlf&t+Vd>2bmzRs2D&m_ZihrW>KcccP z^9rRZxfG25e__HSI+RIHd2UpkJK>6R9Pxsmi$*d#xZ;bf?ArJ%;q-8j97#H6E$)FU z%qnZ=eIjU7j09&>~i1FjFB;*s4N@nvRcR(Z>c1s7~{l(z^lpS{tv14-cUJJ?0ez_!^e)}Yd7;cV&qWx6$uwWh;1{wc(8K^I%PJj=O@ybx)|NBSHm= zwVi|M@AA4Cx$26+Ghgz#2Nxd!&ZA4dqJKJ95}tZi3Dyf$5AiEn+1e}V-1qqNCCXbO zpl+Vv<6d}tZJ&rq#zn3z@>&q^c0tiWi=xQuGD^_Iibj$T8U|=fQ7CtKe}BAaznyXm zF5jOCqE*G^c+7*pky8Uw04|T^7*9Xv%cUIf+ui~B&ksTyc5row3#ps<7uzdu;nj=) ztrV1`Mm3H1PO>Fa7AuU}w~=~Ib?HfCZ`dhK=2J!r)d}YN*SN0;gN|tXnkpTsWF~2I z!5FG)JGn|$;tU0UB(v_C$s#+r$=!Z&G~J1lLht`xJnunF|~ z$HvgheR4$;b6h{rM2~^o&)|xaZwHb`GYNK>yoqmu8QhSVbB5XJ(Y?W410dt|`t1UQt|If0~lF zmNAxJ#aK(=jmAW=im@)$=83gfVNfyP61VlePd|lzsr^U{dXN(YO5S?T!3nGSL`|lK z+@9d;M$E8KOAEwLX&6*R$;Eb!Y&&pD7tdv=`y^^#%F&7r6zoq4rX_BDV={lBcALE? zD90X|TduP%MJxCL6(^%moY&ki3kzU&(afC!Z9(RKn<-Q=z3jd-M#*^zt|&k0*{0CP z`!ac8r=_SfoJG)Xpt#q3D(#ylYgghg1nnRU9ro~>j@tsTP5TPuaXh_2L2c6>+HjF^ zS-GO)6|KwkU`laSo>r)!yu}Gl?z56AmXdv@^h{fL%O^PU8mL7zR0k$bv3*j=#R<8K zklZ)P0P1C%Mm|@b8q*bPJ@6qP#GKO5+Z}lVlL# zZ|AME!k{Ig?pVZ_Yd=-t){?REwQpd}6|Ba3+DC+eCs4S8v#HBr?n2$!kON%7h&iE= z-uUo{iv+Yil(r&alD-U0P#gOg#FHIbv*5U{$Q`qi+|02-S&#&^9fB1^l$3C%E!~UJ zUql$J0t#2;4sbjR{6AOl14btxr=d08#gb5K4%Ui8Ydlg&$eP6_5m(E2La<95DhZHR zP)hvP|;+2CjdKWA4J8oZ0`i%?aH7+f}PAj0((zMU{F34 z{Xf(a1$|a>SBt}-zc6-dxqE~nt(M2I1UY<_{&u-4zSQq zBJ^$k6U=uh#oy}d3U;tInCt1pv=h{JWG3G2Xla~S6S|_qQ+b>&uMSS2bJaJ{Hh?y- zG9@&LU>Fdwh|5Rx5*pNjya3d4+P$`8xCRUwuj?i>s6#CREEX_bcMQT;8;}~xHa~*gsdgxT)g92+hGy``4{*d!^M|XpfwEj6L9XZ_d0w+2Py$; zQx)fY3xTD#a`n`Y+jiR)tCJE~CbrH)u%^$5zWfhHXs8l8&u(j4MGt=G+n|9| zZ*3gm%FD?-Q7py=JPQ<{-NWQvs*1}g{|!3bl%2>H+M_~ZL#1fc9PKS z4YY2M>=bq88E`=xOLy8t1koQyqG{SCU(>7mbE74`#gm>T)MLQF(|R7J-`e_S_7VGy z8A_|X;vwJD-u#H6?+<;=gU5Fm`PH`_U}}M9MCl8(xCNPe&h;}wRBZtf#oNj&=m4MV zSzq&w(NhW51~TzwFLo^~x0gBN&j#k~XI-6}NciSB<_enq93Dag|B*9;qj+Q?1Pej* z^#_W5)6P(h)VahKQp+QrC_LPHgLdrq%~NP?(leq1-UMIZ0a#y&Kyw9W7BDV~!YR|k z;atI6l%M|sG`YFe(_O)}l&_s(1?Z>H%(;U7RP9m@t+|37X;1OMlZ!5#BY_JDuZ-BW zf7qE4&<4K(d>ds&{+EEZ1B{WHc9ZS*-?i7k6EI<#fOd=$j4jJoZhT{GuB@e1f;B;H zu_xFST$6Vsi4IvxSnQ!|>%U~xPTMVYyzHGrEmM0Hp|5*#nA^%+GJL~*~ZsxZ`8P@4{Vcx|LK3<=teWQj-g}uCK?`! zwT#dw-|55QRQD|99wX=Wa1hd|)X!+g)EKyW>YKK{Y7G1rXm4dk^+lKZ(&{8ZwC%}m zW2;Jgd|5~U3>v_rvZqvvcO-!jni}OW_?w^Ot)Eb{j1nxGWcjr!PyG3mV(k*Vn%!H- zt$+y|$ztr@V(f21BXyA-Tpx@>MQz^k6QD)HY)Y_CdZcZD5{&0k>>7_l?fQaefz+Yn zG{P3MH7uAw-Uc2W$RTK*NgGNFf06n8ib6gc!RZ0I3iXOUzMO(>Qt$ix$)C{XOsvOqPTD|g!&FlZ`Pf$)Yzz^qzX8% zh~oI9vy}RUoFH$cCeZc+?-j1DkM0;tb&D1=VX<%}n85o4_I`HtIjwnENmvZxIAKISHXiTYP4vh62 zI!`xx1nr#3+d!6YHfE|A%kIHs((}t!2d@}P&hrju4y-hOGUsB(1U%|GD74RihE`mc za-)uTW&$pr0+f?ukc;MdT|5g=Erg~rS_Iw+mj zK*dMME!X~vrq$s&h1Sr73iP{C@fYNlZ9K=d{DuVQW^rZf50QB(&Kdr{R$pT<=kZ6C znRBZ(80|537KPW7b3M+c2K-Ote|ot|GpI~<*{xB{x3(R$S8!pSTr`Vfn#tNYvgQ^< z$|O~DU9b&RCiw+T7zk(w+cu}pZ^qD@$d|@p@eLQ5z{M7rt?sVJ^tOK`bMKx##tCJy z9r#e03w>g`SX!Ol*Nm>y!)T(kRu4Mw$c6Q+$#ELiOfIMFRNGgtLS$aj(Db~Mo>0u* zO5&cu&sapfWicYKa(D#Vn5^!iM#?T9XUUGJ$#VWIa!NY=zU7z zVlHJ3I@D?w`oNAO22bfply5=SAFV+q^Ble9QyPu59Y%FEvJhlNF{k2VDsWQX{?b%A z(+6fktHxsLSq^Tbw{bEA{guU%!y0?h3T{1gmhSO63tTe_R}?$YzC&TmA5V~v-b8nv zOQkkubYcgZ2h`1dS?5IYl|y5BdxYzXhhXiteH<;~ixlvOj9KxuDzfw+N8V#47~wCX zgtrvh_1;`KGIHzuk8HzK_80)#{Ieari~D+S>hp0d1+Q;yAlbM*cYVgt+<6ZvSdK40^gImvJ=S#|_jK64ac z6>7YZ+V=AnOLy4h?Y0g)<;VuQwp4bhM)QVa;cFux6K|;Efk!;&dptH7U({HzBQv3U zL(Btj;%M<3x%Lio3x`<+{>OoVI@RJR^$rQfo+1FWvEWL4+F9W&O;0KJh^h{k#(T(k z_8tDX&Wfdl%VcdkyMsu%1A#X$T0zB{*>1AYhy`=&E2dd`j>7KA4w=KCYk{1P2imn> z_H)$hrUVycNkxAR+n{wGAXtvBWcg}qor{ix!TDw|FyZD}%AQ-c2Fl!8Z6N0%uU*^w zbtcVAB^`M>+fg9jfr`;6RJX=F{oTf!jNBjJUpvzC>CsakRHtYkViO zdYZjPcNL*oVXScwY(a@Q8W`Yf-l_D>c&)&E<%Xt>hHE{Z$9u3RH!(A92s2Wvof=UH zke`U+jy;}GqCaKNgI{;2?RVrURj?#DhJDkm6;zz(njCHHN5;mJ7aHNyaoo%`JWbuZ znC7k;>x^Kwn8-{wppnBU_K$f;f5z{2MAPVO4FsNmN{{HlK)G*E;T8Z{RN4EGZr6}t zNUKDTe`Ppt+!@tOf-fm&;;Yp704TK9sbZQ9OZ7JDE7n56Rbp-=wY`l(Y0^;X zE&JJ^LheA+UW_nR21Q2hr!sN?YV)$DrmKuRE>$1r&O5TG-wX-nO46BlDTg;BfpgUoVSC#*mDh&Cbd6x|T{|byA5CRj!o0|*CH(vr-Z?OM z5>@8g8Sy=L@?>7asTXZ2*jL>e?Av>%LbMMvxJ8uXgLsNd{3W!M+!pCz@E{EyXd=6z|l|GnH1xNzPdkODr;< z#(IPR@4G*RZY+~vhqt_Ag~{4K_fDlqU%6yCj^!3w^nR_5ea()w6;sAZp|#R=`y##pl*J?JYY7R=TkutgLjrmZbBZv-N?LlX2hY45w zkG5oUwVsqdP=cTF^qbqjLrp_H?|H>J>|IlrC_$4P+qP}np1EV&wr$(CZ5wxN+qUh! z`|bXRec9)%&djdUr>in6A}Z`UnftP3!T9`rO76H3gY_qe6+Fweb4#Xf=-@-if z*2_I3;GHY;knM^ECrx)>4bw#z_8^GaTkSTk(R(3*K2D_tB5oE!r|w zFi!yjcy$9WlJsN%iGMm9Alj>7*xM34o;F~>` z0ymw#I=5FLvjgNEXbzcG0#4)ZiNTt2jdk6$GJ;B#xG}% z2WMqWyV^sd)LI&10bY3V1~|KXMeRdycw6SitEl3Fg4VIJc5QC34ytlXA8$Jc4AceK z<6Mgy>?mByiMtt4Jb2q9OWtd_ovqKu%(}#iVTN-rrgT%H+A|aKvJH)|M@hb+4Jr!3 zOStYCsvti0m`a#yw=?-hVny^SQrHFRbwyMkwzr5xqbf2!U4FUO?j*}g3nT1p*a#|W zp&o)R&vm)QFtl#|OiNX|SYgG8d@1c|dpwW#9&HVf5yiF9`eJbN1l1Q}T*nzq4CM_q z*WUQ@nn0j@Yx+xg;(Am@&&Um<{m>t0k)(cHU7;q)!91n=B}ZuxhoSlq`tpS*=P^Lh zTK=-3^(`^wRgL!*&Ss3&r0#saQ0#PazV{hTk@2PESxV+zNm#yk+AWT@-}mSXkUw{I zS6PLlE}-{|SiUzKkLu+Mg|Ju};QVSnVR;=`k@)w>n!u#*JanxwOsq*YeqdtcSZ6{1 zs)dlsn4b+c)B(|sO1c|R)|)(HCtZc6+1QE^gOV0yf=$4MZ*}{`5582cysAKRn5g`| zU`>=$*h=XpTty+jK(JJTa4@jfQYE!h`2>f@n2ty`ZVP`l7~yr)s#bZz9luz}MG?yy zv4~-Q)pe$1zUbsGtwko*{YX?oB@!*xfdfwsI9da{2Adgh7>@fpTf^aZLyRhv19=Bu zk6XS?$>l-U70K=b!sThcYT2&quf19Vx?7HppC=?y`L?TnKTGH#(qsh z-_ZtocDdos)|tqbNw}4t$fvUQhe3+r@>eleabd95Mxf!Zh+NYfspsJ({8|C$nP=@F zQ7Q7wKWR*oa>{;AR9UX zSy=yS?2j7JG6xrdzQa5KBa~uDh8<8jsorj`^&s-LXl};Dsz; z$20#>DT32$1n(`pnOY9`u8o0KWrv?Y(UsZ;on|8Zs3bNg4#IFn(zyG{Nkc~UpK`%RFcF-oU5*rW0bqW^ND)Ku4{kKen#UV zak!o7-reZA>ovDRPbYA(PQC1)6#_Xgk2x2EWT$gw)w*68JHIzk{jOVLnP&ZjQSs@W zYW2CT=ua#9{*oSn(!TlVv(KPDBnZa9^hS<+W3o9zJx6#*cWs!wX1&^NpbI}_X8egm zKga9KChH~z*G4q7T-C!XlEF2e9c*CH!(3OoQdM!>m2I4PQ4AS?atHE){{1o7xp;cn zBpy*5iIvpz+ zevU~0!tMTtfoVSHz07>9Kl>n>45?KDk8+<@ZeZhr^6~r+(z*0^;up2Y5f6gQEBqKf zpwx$5&Gt@1!UNq4n$CFggi=l>|F;jZ0@*s2{p-@VKp#@|1>LoQ3GBX>squ8k<5b7fio3{{7H>*)k6^Jsxwh~GAyu_%y z--%3_xo+;lBTVOBf0f*P5Bhw|Spa<+t>yU=DUZy$6cq(W09bvN&MZ)0YB5Q<|Pa14;B;6xgR4^en+_Kgl|^BwW-fgV-7QdfW+ zIEp^SE;4i$eg@h+AUE*mat>`ayyuGKnI>Em@We5uYAMXQTS~E_Zb3IAs3*3)YbMWi zpDseJVdF15IZfj91}# z;mQ5(^A;-URP9GiQBfW@NKiI zVLlRaWPhRecA=MwtH#k3%Eql=j$t>jW${$WC|cf%%_pSzOdD?tLbF>cRJhwJSyEzEP?4_B# zxTGJRKhZknmnNgfTSh%7Zn4dbF$=zZdCG#&zov~g?J)V51QrFZGxxf`-^-HseMu1u z4plBXqBpww-_TyT_G*0c{X}nFY{@ zNyIjt4ycfG%*Js#&{gs0&M2oclU-TSS*`~Hrb)e;li+5ViCmkGWmhJ!kcn{kk@iRM zc>Cd8)7)BpBx9J7{InU{)P>F6o$eT(`9~d#gjJ(jk0VpLPM3)?sO%DCb=XyAc)i91 zh2Q4ckEGxJ&0y1okCy|X?*9lR&`j_|c;-YEVTGS&wWYFiXiN=hU3kCIJqT;Ht<*UC z$=^m6?J1rdzb%&bO2RBVLt(V|ljUD3Yyz%*G`lNhhp2<5n|HcvQ?V1=JcvD1Pl_K! zWckREeCiM{n5>8$tz$IEs(s)wSmF!&PQHdE*fcp+CK$Df36FB>4eagD3UDj!i7P|x zI7y8_&v-hM8ooAL6NEZwVdAs?2w}Xk^`-6L%dBIA2RNd~Oofp?;duFI_f&k@bR<6? z#);0U;vWXkaq#8d0^KST=>&*2{JA1Ssd1#6;}14S&sm zR#h94^m1C^utexX$NXmQX2izbxS4LgKZ7vwtGPfo!VE530)+zQ(G?j7;~*1<%*e+( zdugD0vD!b?%{OLV!nBAnmJD?`47prb{ugfj!%ZeO^1H z6+_D8Ho7RyCJ3g%1_Z&nYOayE!TSwKsE=%M+B63b(@W*rRNh~LyNk&qJw$4SogK`L zS*%`Abiw*D#_CY#`=^!x3yWNQ?!f0q(JFRtX@A;cC2YR-&8wofF{vGvC%Mkx=|(*Z z80@|Lo_*!S9=TkLnLWZzS7(;rBOuMLDR(Pda(M^&e&Ov3qim$;B&(C!Ju63#l}*p@ z%y3JIt8Q>6IEm5wb+aA8GgbJ4Cu-qcI922H&ujLhbX_Z51F4#m7qdaq2!qyZR?(TX zGQxfvjYC=J9op7%m5TTqy{A{EREXq^nu9QDHz`Q%8t|Bk&6j|=!;2HUUf1?L2x|>p zR!7`aRe27can*p<5(_g4?aZ0TgFE1n7vqD2k7J`gk;js-Faf~?iMm%_B^TYVKs_vk zW6O)Ju{o7*m+}aE{9`TH&5Ap2S?{2UY3IakSB8j5=|jkoay$YJK=!OCXKK^7QUYhylF(N5xMw`i~#g9n0amF7b$kjohB+oW6;6h-zHndslBQEF45C%|fn; z{D^hK&b5^C1>Mop9_y}@vQ!hMe~80BTAM8t%N4B3)`+u%xm3-r=(3rULF>DHEZL!3 z%f``^Eld3v9PDdq)%%SItqD5D;4^}**9?)Wr`Sq^yp0LL!y<3L7u7PsJ@TD&6#t?XiCcZOdigLK|gV}(*=Wvu)6RmZDo&0zTO9(dgS3)PcgU0 zl}Go31uaQAK@`9ENK^cm4}COXsgqU3=QDj@*!*t$#x-CV@-xYcMQzu4ATvvdE?6j( zQch&!7+n)KV)iacTS(-g%!OCwkwIiwK@|@E+YLzC^DP6 z`89uz>ZpuV6ku?(o5AgNC5{jMsvUXka$LF|6diVGElUu~xC*@|vvl|)7&sF6W4YFk zqRR*4L}z(HC1~mo&P2H(#WqJrbKEU3BdQSo>W>bpPuxX;$QeaJZX9sw^kPh|1IgiH znQM*fFesyyuDn%K{)Udd{!Qj}Qed`=iT3S2)aI+&hXmh4W*#|V$^wl;QBc&jsQJgo z4CQ`X(Uj#?Btt^GENn)L3;tzqQo>vO{N!M)3$HTSYIglO@#MOo=ibX^B|Y`Mn%88T zo9Ux2S{K5%fSYI;+cVO5Fc@er0J^>nYE{^`(LEW_@`^Tux+>;9yi&3}OqiWov8V*( zce`v0CXXmpF7XCEh0Ec#k~@Z61T7*-&myPA6>ym^T8Att)xwpj0+Y0tF}am^GPe}0 zNa7DwO3~02x)GM%l)0g;V@ulQZ^X?SJm~a@x_H(%(#-?`)J|S5tcvk?MT$XjYl}3! z!Te0{4P7?e-b4~3y%{6en7tv$?0_*h33jIP--pXe;pP#v0aU%QCrOFJpS>Oz&+a&d z9r}U}n03nX0ACw^@&scmm%l)DMf)bX=!4}J#Pl)lydAh90LGYE0!vrEPS*jB7M#e? zWl+wRTgBcEFWkQG1Bc~D-{hb#C~UuYWY)TRV~gMkH4<+I)A`3;+k=C8Uop6hnJiDf zgVe&8O5t7mA1ctroS3RVsPYnqu%p zZucl+%>y0MONqrPL;CV+ccB8tq2 zXq#UW;55D%$?keiP_dD&R!5mUFyuXrh#jq%b`^;rBGR>TfUFpr~dx4s2D)a zXI-tqPnK6wggP$Ga#ruO+OK6#8al?G`3U2#!h}C{WdLLFj}_z$n@QUe<2OPsLU!dm z)d5i$Ca+GzG-msagK8^zQj>!ngDiEbkza3mweqn%U{*dE;`rAPE(mJi2kgPR!_Xqo z%mdIAxQpE>YI0byC>bdlKM~1M+}~A2qO3D9PN3a${wU@z6Mk^qvB6MXKU~(2I$}pc;35G>8zi8q^LNob$~08EmR5K`!S@< zRPHJZQ!DFRq2&9PI5h)-4~%B2AEv`R3@3M6&^7G? z7TH*f{t;zJ_u#>PDE+3^65oVzOSHU>y*fxvCt*(rr;|Yq0tdVewj_LyvF&|cCtJ~=zKyiLKY(7!P&g{w*^Sd?LgcXJq(-&%D0r}|sh*`k$JjLNTWkYYkeTyj7w zs)Dv5-70N|BXyQ)`D?VHyL&6;hZa;!8z??u4wYr&pQb?e<#_1*_p<=q$u;`m%Ztf> zi ze0|9)j(|F%pI}pv_=H3AikZW5Iz)%u=)i44aJVDosP(wPbADmBuOPNXMwuq6-P8II zG!GNd;guNYlv}`)HBGh@X%mus`DrsR{G`ZVX7<4iaxCP!jauUJb4^IC$k%bVKH#Ki zt)550^v1|QKM(f4DD-l^nzewLt#5b+=fz(_qo9vQYa}-2M<#I^4tf-nD3`}I^VD`s ze}!yJ++mu9~N&Lh}=~0nmuNcmLjc#cNt2r`X_c7IR z0=sBu=;{|^{@6p*4g^`%@6mNZM}bKQ*}H}9-GI1-ZtQR>DJ?I%sj2+~V?RRi?y+SWp9hbw+%o3S1Bu}uc9IGtffPzA;(J)<$R5V; zr*k~qP0aY-B|HzxigTQRDS%0qVCez|)QDO%?5MD5hOKh9f~^kriKjq>7mKJitdLb5 z_Q7HDS51_+i0zL9R%K4R%p~)N_ffzn=K)~!LQGe`n8{FE*ppYS4E78>g~;?Sq1JdF zE(u=}_qZ|>Kkw;B|0rnBHXUBpaIxbW5v`Qp=*Ad1Bu?*vqMpz}ltdAC<+%qgb4&y4 zF4@PBGE-h>AIx|=cemW_@@GU_P^nq7rlz+F`>>{V-!jse*H7N4?wOAgtrTn=*4&m& zL-peKq)B%=%vs*6NCgmZsJjeM6{i?Q@|$Q`k#e1V2|%s~FM^)S$PfC0XUU^ZK8O?A z)s%tkTg;(TEW|nQRNAGScSp18iDWu?k%M$VKPhDz?fzyf(js4-;dn=Fy#79q-{?!k zCI0Zb&3LMEclCGRdAm`=E29RSl9jvCFN0kU@5&}=mo=_?7?Wd~vZhz{T|rk~RfOxG zy&>U_#PT@Jb?px5bAcR_d}IO+W`lfd>Uo*>%%ls$_|6k@Ag4^{gtzLzbn&2YV3^go zc$6`_yv1;lt$Kk5#_E_ehHSKPdhb%j+@`VS3OwREaclb6n5{R|THYR-$NeMkVKV7P z7pX1gJi#9M21Qn&AF`2KVB?hQM|em6r1&_GRVuGy(wr3mM~SOe)>vZPh-%|`c%Ru@ zjiR2W=!8Uyvwrw-Zc+8l5c-K{dKu907c-1fIg6KcjMl0a09wj|R*LVuJW^5rIm!;d z;Tl0X(5zg*@rmY1S`?lwxNQutK_yqewd3MjzTR1!Q)k?FqyJ&rf%@HhYUrs1_Jfw^ z&o82!f>zVOR30&LbNQ2LTd!ieVNBgV*ro5ux+v+cw_zTNG-XIBQoDN*4kO4NxOHo$ z2^@wi6qh+H6;q!Wr#;#;^lfs;Kj0I%v1x1W23?WfNR{NU6zNCs)CX|T?e8F2!DhDm zo$oWTZ5DijZcxE%$kwQ9hik+O&xZ>08I#z^!)F^3M@tclCykIzz}2A<19AC1n)Hv? zRuIfCl#@w7o#+()yvkkHGrEWkoMqn|g6#@FLdxGk9%HmzKfsG#Iln5q;MV3F+l7AQ zi>~61Kg^4_g`D7%>V<*v3CP9I$=EP9n z_-%Y$tj3{m+f=#Z6S2uy8ih)x;h@XOe}1u&m4FM5=<8@#;-OV8299ODDd*ZD$Z#gY z@%>UL=k7Kf!;9@ix%8T(bE7QMy7@iZc$;L8d_Q+a7SR|qGIlVXbDcMUUZsYX>KE@Y_^ zeeV;xlzQfUwMug?DcLp_7LR6y7voaih*6&r%11NWf$blm5qP)|L7OEpo1>;{I98gZ(bp+ z85jAgYURgvR7>Kn6-cTQ<;Sr>Q}*W0lyd{0hAZVe>5@!w+qt8Nl%|RztQ?Bi%oWs3 zOPSi<`$e#4JSL|n2+Fki23F6iDZv`vgFrw5nV5p`jI%JOoMhPg`-`YZEycbqG-PeSWVfA z6O;h$iqJYa*S@eR;;K5i*xy(BomFzLqY1lN^(;R)4vSO&F+UN|+mKtnCZ=9T)MHKQIsY`IoKTC8i+#F8M zPHS1W)vS-Lq;x*WXwhlSg;V8F!8i?$F7_)d%Ue6@VXa#+s^4W32A4iOVclW2_SNdp z>1o0oWy+WJzB+eUZPxaOMW?(vT zAGF{DEPM-bBScE|PqWB~OPZknbU|PIAXLqsFATTkc;i&le9&P^@jM`Ml65RkR9fA%v6gG&viDXHvu`u zB^-VfzpKqX;*78XuvgW|4@xJZ^%jw_CT+3%YTXen8*Y}HOb40YIwbD!+M!U?#^s`T zN9gZIsuY&C{>kqV*WoZRfu8*PX!mfcu!?F%R&c9Vbsf)7vBU$LY>C`^f#gisX}QVu zr)t0NyLt^a3p7npTZZAjzF^~qg^Q;(5nH$HiSA~3B$x8pZ zeh<1*@HQZ8i`|D^r=&==jVP9|OVkYD6%a#d+rMaKG#bu>FoS5;Fa<96u|M+c@Qhcv zCS11`7x613QC4qAOs^t{@kwwE@Dj8~Dnd`ib(Y#SjBvLwZ2Hn{MSUMQTSf89Q(VnQH1q!XX}?!SOf3 z82_bW@I-85{1WegAhoZ;D2fIDg2u-uYBam!md+^y zJnJANtLs`^KW%>vOPrs3Av=DRV2sh->QHX=#{7i`?_bSkd$&6eR2&o-|C^;sQ@g`r zRz`7Eg~!qPfr5z{@*-=`81AKi;mJ`JA0_b1ZP}1%76H;5-4UYne zWBiB0r@H4lK;hw;9BW)KBb#Gi5j#3?$9m*6U?T#?P-r+8F=Qnq`9v1!E&MKpCTfvVz#-+z}Gi1l**IWAK51a4qGR%-*8VvIum4`NJ zEFh{20VdCtSq8HPtNuD*A2Xe#1(4HHf5R^asH7suHnLbZ&4e=d4>{F0$O z##k^t1aN}!SnWm3emGjUcDesDX<5zI_Y!Z-fd5aO$lZ?{ByUy6i+=WHWh{Y&kIy+ z&DfJ?tihaPf{n9G$6VqQ6Yxvly^i0Nl2!rA$1yq7Zc=q?qR;8ol?joRL7pZ~%{>@# zy=8;k7nU)1h0JxVYO8dtUJ-qw%U33mC-74ubRXDqxNd`PgOz$rRj8H>{x{kc9jyD7 z4$+J{x?VC0Xjt5XFL8Kl*57D!<>dQr zu;~gz1t5DB#-WPO6h@EZN{(mcm-m4@NTbzgEP}~+M-YKH`93g%YMAjT>&za6QQCZ)JqSTAs9pT3= z`i6x#r&3xD=E3hQUzjUq-lglN_WIfH*_&S|UIG%!SGSIy#&5NofKakLT5R8#u3sb! zDCSB|`?#g5KsJ%O*WqRZ)t%tQ>XqqP5Vgm&BkjKNr#Mz7D~*KDm%4#_m8g<_0n&Mu zOyBpl&dgQ<{3G)!&v9Z7FweX(hDa7&tLv`I=pPg-4q|&FiBh#E>$Xq72jcEYz(0gf ziF6K`>K2jQBOvPTINSj@DF{#^GSS+C486e+et!>YS4Yzewc&vju!IV2^GtX}^my+_ zC_jH8L>f*6FHIGaG#}GZZaYr3JpUqH5Kv<WMY!p+9{8xtWiIr^h3I+PNc{C+b3+(51+j!p ztZiEX;l_JMTh1~XMyeNjGJB1d925!)Jn!1gUgw_N28+r}bxmKst7h)*5=2bm?0PIL zW98Z+JPe!GaQc7^Wgtc{p;j8Qoz$%-eim47n>Vya*Km= zWO3}&k7p_k(+4rHJ(=fSbTQ|1l0~i>Pg97F@Ll*|#>LQVV05r{0l4^760XF+Uc?=v zg?v^S7W>_z3fC=-$=tZ5)b~N>8PeReG`HVBa|+4`I~N_h@Y5tcVT0Q#oEjiM{47x& z9z)-(h$;MVG8x;q^Kk->`=@dpyOPx~LxoDU{Fm70Ch{@|*`B@sYctQV(lf7LRtib_ zJel&~b%#>OX#w4sZ3N~`=h^F)ymj}fQ_vUvv8Lv?p>u?Ka+Gj{^3(w;zcD{fG*zR@ zl4Bb{j}?j3Tg@a4Ht+g-C%f!+o9nx}r7TqIjc6eMEZ>*MW2E!9#p&sUigGGd6G|mF z>P0mlFI{ilYuEpH(|lPzbwFk^W5_uKt?>5xgAqkLmBPNrim}ODred zD@SO8;hddZH{Hr0He5Nq%DT5~6D}CE-}(&{rcV#5jgL5NMJ>f@6LQcnI|IkEFmRnJ z^hL3!IVb~N=s=7nlA%vhWge^DeC?igH4aYuI6=W34zVg_xi#GJR}U%P699vt<( zk)C)jY&WfLPkfA>Vb9Ng4Je|~`@Z(ut6B{2aI@0L z7BrUM`m&&uz3d_n$(E5}x$2-3Ij)iV2^g7S2TOm$r=QR9q;kO`Z(RQiqws{Jk=He% zI^}5XX8rp;pn2@4^VvT2%~0;qMJwv%l>wBbe&fV%q}hq?zxQyr2Hp}a3~ziP<8R|{ z9x$pkR2YW?@hU;ST9#OSWYffVrVJ}YjHa79ht(|mGfa<^T*y5wZtw0%MSCr^-&4P88}a_Q6a;PfwjjIyO3F7e+M3p+(8WluOwVS z{&7l6SoygmS8w?))&wd)De2aWZM|`J6blLgxhRgqi>XC}bN3ed_7Sq@qd@wxYK-y^ z70n8=g6TxIxZPt0vw_>dY34)#@{C^!Dy}0ocbYrNpBD5I_e*{moae<}6Zrqy1Qp>Edv*Ukk`=@T&YQHvEa^u-r>o#4+Q)lV5tPgIcJ&{N z4cz|(K>yzWvn0>b3%k(GYD>EFcJQ7T|Ge^f{U>x*5FW`h!TBZVf9LgYG_&NtR9=Cu zQCrlWHvc*N=XDnEKbDhxa7kW?56=L$|0MGytvE~a{r_qH|7`wWf16)^25^+#;S0yf zq(MhV#iGR(wu_?ah{zh*;`@$Q@rrokt=IC0z>Vw6gGXaiq&$i+3`1hBO?xmIXOd2F zPlzzL@h#;nIzK;dN^vMrQG%}gyDaOCw#ac$crbPeq+R^-w&7}P#Gw8KAdO2tWn<%B zSYvR-UtU>_L**l;$|jes%}h`Gf{YmW@tz4UVlvveJ4u42(%y+eu6g@pk*Z&C4VJK@2rVF@T8?;Nc^;ATwaMaNVtkN_B;h6(2 zpz}|o4oA77^3Smfe*q5|oPb&^ymA`vS2P@{tE}`Pr2GFwZ+VzT4li>>ExE&0pf{!? z+_A+9XUfbr^w;1+76FfOMc0zLmCR7|4G&5{`YT8pmsD;cZ>wG*$>0VWfXsztU;%Zy zc95TBZ;`gk64d2)y_n4H>UEPppsmxM2r}k3p#4%Q!A7%ZMNUS;8;xN`f(%7>yd@Wl ziev6@#|1xZQLGC>1@)VLij6OyPL7ec2RVbGZ=U^CC7~EO$J+2kz9^9p$Xz6;Ow2%h zjuhLF1-eGyL5+DLpYW8(s0yXN!<*m|%%}p(XiUm1NKd6;$n1AQcq8RKaqIw!n$u~b zEvBl?a>uBE`d$y7HcPGp23wdr{5zE$JJu8j%cP9R{F>4zaaMRikbH z+^U}hNJ)<2NX*^E*j9Z%_af03un*OEk!2ZKy;>EyJamV4u}TEigxdadsUxndnI<+; z&}Gdve*Ty4pJL!TAzVe-!W|J^>45bNKYUtF6?&TUH9}lrx>54FUv_vrd0uLAEpB4> zm~xw^@VcLsYep`g6DSCaJFt$XGd}SveI4<59|zEQp-{|Bd#|cX9Pu0oj*d+~s6nOe%33 zCkc<`l~~W5-4v*s_@wk`U+Vf99ePtVOusRAbOMXWj2_~mQwlL43u}vk^eh%p)J-&{ z(;O@H1I!h+0GGmPwYt4iQM$w|5FRldOL%~_`s7vNeYt>x|4nbe2V}WO7ag8wPGxDd z4`a+1_AFt{Us0b9cn7_dq>yvqqFoe{wNRhVeTt4g3sJd2>~bOg4`!5#Xe9Np zWOgl|d{4Ux7B#k+Iay!1I0p+q$Ke5&eIXsl!<(A+T%c(O^Jb|}@d+Y}2``gxK$!CZ zd19A2_4RrwQje5emoBcMgiq$i2rV7vDE&^~)1~NJrIq4U=MEkRV9Zk6ZjsebFq0TO zOhS4&YD(c0EXet1w4&+=LPW>6E_w}EJSCJigJjt^5lv#%@yVfM0(fK_xPa?R6C_xx zQuN7liyKcniPRndpfcENs?VJn`Y>elBEcZ#bi#xTovsN;WGG35c48Y4;CF_>YR0Ox z=&mVDF`Xxvi=qNH*!9BAgIJ*NJfywyL-p@0! zLv9^g>zw>F?yVUmjgk)GlMuzkG?HC-Jp4QkWf@9b2KdF& zl1=ZqJ2ngbus za-i^Lf8%MTA4na~>a#8|7k*XK$#<1K+nJ=-J3zflbXdN`Vv7t{sY?8bjQlovMY;o3B1d_qm25`QwWuGz*HlLKU zJWrjy1He|z1U)LVRxHwZa(OVpv1n@N2omG@2m}}v=~xP+WE0)en_a)*z4{X(`&ma{ z!3dNkm3R*6Z#BwwYaGH7%nWQMT!_I1nrSm;x6~F7zamI^Bb~qs^O`{)GPUS_1+n|j z@RHPCWi$-Xr8CxfLTi8(bz_8+T14WxScHI~Bus0CK19)!bc$i`mO}xyxSm{rg!mj~ zJX`dS7W%lB&Br)Er)(hh(Z^V+gF@-FH>BK$f3hD~Z7BkVP~H{o`NMdQFp#lO=cGxB zC^dWW6c1ao|CTmEZFfog$y~@ktyp0Ee+RQfl0|&eHI&@pT~E6VjksrIX3o@fR(IqR zU;stVV^nDubZxE_BmdfVd6^)8IoH50oC(bUBl@2pL0XFVn*c2tDy;O-!X?rg^g@0g z<%1sR^}>V7WTAu8w{SK63rLyN7u_Idpq8kmxIQ+W6q>g!0@9--l~vQ{0oSwOXGO#2 z`4*(dGGnb5*U*W)CYTT8hL0s--P1MLdM(G;oTFf48H!5-`#-f7Cf|qkBK0CJ>61eh zre~mbT6gJEF$T*oIV|Iw*rI*L#^6l4D)|;rFqCl04OX;ix_EC7Wj61-lVZCw=#S@f z9bqAjSs|tv+~*mJZod;8l&UM(V+y3I^60fPk?k zXX2bDWSysV=+Sl705;!>%#GfU6S5o0eIz2y7-`uVRWWvNs>sFbAfCPm6=1qp@f1lo z5MAMZ|Ly-IkbA4?!$!u4{>-xir@*Vw1=1*GrXnQ;E4gD(l1E#BFHe41$Ut}8sq=A0 z-YUIdW7OskO$*YJp1}K{tYR?mh!@30UPJH*t!kTy`6BGeY%o^z8mR~UyL2QjH_mWD zsvOfUk@Qb#6tM$&$fQCZRI^(RHHkQB1a+Of#+H(HBO^g-G6q=S85+S|N#2gzNrx`L zwh_u~zEoEN@7lIxZMA_z{SeL_5*SW9rt1h{&nRy3)7X#yFclpOC-QFKP^rD~u`wb; zLz6)ADv+BVVo<`U2TWeh5LPN!s9ZvYvOgVKe)F}wE&W_NLn$h@0PC}~sdjcTzg7Z; z7!dq9Ohe86`L1t`F*$c0k2HR|JDjEV-{;sYrQtl{4Ub8~^?psf^>8ObM~z-}B;4>0 z-yxlL(npz(>c-jhxGNh5ZpM?rHCu%flo+k#c3ts;SKlQ8Qtj!{Akn$V68U59J{=V1 zzI6gN&W{T6d;DS}VfJw3c}bN)Ty7C+hCfWsVRYf_`h{gpZifSDu-pLfEJ8iPzqxeg z34ch+u&oPG9yY+VL)I(R%fH4ci07f()l~f*k@Lx5@<$o|blwT&Cg}t8xwP@TmOv<5 z90Y<2d#v0;%;|HXp&f)BrxHFz+%^|Of3gF#(7qr+`=z0xTj*oYt#Y7yMXPIfHNQpO zFsP|cOpE4+olelKmU&Q29B>v7>HkwuWvJKom2GuK$`i_{K2v?l~IaU$sIpHj+&@uxvNxE(wO|<{8W}79v#06{Epv{`>ba{|) zx5fjan`1tKT*Eto9Y#AzMQP)h;X#-{7uTRYZB2`?JGqDP-)p)Ki{CK#5=!{8rU!(i zxx;K83xs(VItwqUL~BpLZ}~>g;CJY`5mc2jFPBjNW7wAfh{Z!j$L-Wb*XW5enKf8x zX5oCcDZ2B=$e{=0QwBj|F_HneEejno{thKtj1{6fkY>0gBM^-VM8VrPw}efCQ&ih; zMRd-4#KE&zE*%s9-#aar7!WPpNH*#m8(ctdi$(PJ2V}^kCDnm?N)@|M2ny(IxlaO; zM{&Rr&=pmy{hB6${`yiyR+{wze0uYwv@A#{bQ^03HbIsZ^WH%N-<|t2D#B=Jg}&mp zbN|ECkbymD#bzU%zf_|Jp`;;MW5i8a5ZTMZBd&Ip)b8oOvS01H@QN}-mmrtkM+Xt< z>@I*W#+kt+)1Lkinr|EnAjjr9BHvtV9>6#*b+ZHUhNM9>3gzLJ3uYD1iljPT_VoB) ziZCtaPecai2P$z)6{7tsrMw7E7mFpf-smjY8DhmWBf6j^LTe<}QN?|dS!eaoM1y4u zw<8&fpqPe-6OhBb6iNcx6^jA91u_H0#--6~v2Kim&okun4-Nnj+J1vVrPYcdeni#* zKAOYl@oAE!j%Cq zj{TR+ix>Aik4_6M(vr;gAXydPJIpnYi<$Q>F6-3%iE2urlhmGzQbc{0>%l*!L%DjD zjseSU{QOcbsRI5;a5}L-DFZQ6DB40)$H_$=wLWlAjgTDkUb=8A@Vk$!`?7N21*Mmb zF^IH-^)s_=4W}Du`U2b6xG{A@<~l6rhoFs|X$ctLd>IxM#e%s3F7 zC2cj_{1Gwz&8+Dv*!}(G(}}&?A9>) zICuq8C`uofAeWdrOY)lW@#80ig0xBIShEbJ2!7#-I-%<}r+dVe zHEeqdlhzD8+8j#S7rZ?;<^HnLZ-oH#Dvlw%@OT;Dod7W_64+o|#$QV>iHF`&6Kz&{ z4h#1r5_vVfz`vhOC~{`u9X=20KTQ-Oys5mBKCJiS>84Kr9$}BkldP^Wlr$bDz$hhX zZ&Cn&Sz>IelAyyv>B1f|Hkuc2J#|Om#+{LbH)_3iAQi_j6B8VPQkYGCk#F7AaAm!SgY;ctSWC>Mr@Y z>$e5W;ZcNL6N?`43y)idcVC3cOjPtD#Mb%fJ#%pDQ!h_0L&#yXO~|2t3NwFs1cW=4 zAj?q~@EQ^-74p%Q0*Fvmw@xBYlQ&SiSjPdb$Kn<2i&4dsFDmjzuH-J;Aa zgrNB5-7}*1e6PYL5_`NZ1lu-&oekRO;Wf48IUKv!%14i>?ODH4%)$l$Y3 zt;9%Km%)sFVBbZp-r&aUYk{PJ2LJEg1m9?wycsu|&Z*6T$$N&%FVvp~a~!^P$NWC~ zPc=#PQ!%Q^^ai_7h{?6MLyxh?vRktVODk}w;ELKH`?J354MK(-U1|Jv>oK;!(TL@% zYFb&7ZO@M5*F(dXZ2$UGIKiIZ8cccFI@^0SX1Z+_x3QDFO;ZOQz+X{%pq+HT4y724 zjZylmPm~V2ffbDx^B+ivh(+`8md@g#q*Iz6YEC^Ez|s{{_zK6Uw{naXO;q7CFTq@a zWz{^iNVZznG6-NrQeWE7GG!wA-OE6-;V#httB!Med_~6#&(z(vGce)eF!8eA^+I1& z7t0_MJ;JOFeDLnL_cSR-4`pOt=usJRpZA8}JPSOz!Eq1S!2Hd7rh@B*pJwb!bGW4`_H0W$gQj%x zx?!V-n7q4pOw~Bb-^>EF#f=ygaVP|JcRZw60}QD=oiuRWdZS7haaKfzAT1k*K+E_T z4~nWECo`7taWE8Nql&)vo+Gxjmz*x-l=8){VsG_lUXjPK%wW|aWS0UE# z`|CVbL7~=b#Qm&z8ox6$+VoIJ@j7QQ%mu;{Q%CB>ZSyEVd1XD68^1jobD_OPhFi%z z%?6Y7H;vN=v(Y;>HLyY63j!#k`Re1lr0wefBEE<^woDnfI;M+(a)NKk{WXsjd6q%4}hmTE@J zJZ%gCbF88xbu#XTEd==DS97o_{6Wq!-b@PI2m)1awYkgsg+GVBjyaoU1)gML?i5l^%y)>+>r$pNfS5X>0(wG@Pf$u1Ob1Y{LU!O`@At$f2;&Gln90#t3@x# zz}h0PmF^0OofWj93WM7-iS4WLB^ns3uV83IqX#0{zlNUo(9p7`9u#OgwXZzT^P7+& zJ3@98OC{1IiX8-#XZ-%qtbE~En(U+>#YMFQxNV3;QVpyYUEGSoQy)w!Sq8)!g}IDc5E2KM}CeU`&*ifZ`zW` zx9t>zV43RV$5<_&)n`=!D0Rxf8_|iphW`lH)vW?Gokuf>|52uF_>BEU_;ZcgfFX}2qMmKy zbuMo`i^k&TR=WxT9yc)ELMsk}Y|I?7@sV0vI2~~6r>C%AP*~yqUIo^d8!!_ zAt&EArJLI`37MZ9)u-c63}Tj(wfc+PheRQ=^zWaPK%pR-D>t7BM#Ej`c)E4U0heiv zwd!45OT-8@Z8@?Wim7 ze--?JU^Dv{4_)F$9oXO8-K2W>Kic-He^loDOYh@rv~{=FG=%WOOQPM#^fbKDX!ubu8O8Ot9` z%}s$8E*8Cr0LqF#nn9@N+Da`W-!x}?om3N14V9XDoG=gX&59E)5 zIt;PFELt6Hsn30YX0+z5_={2XfOhR8WjLD^9FGIXWwvdo;CJn%Uwo!M<_09aSm*h3fL89isx# zOo=XEMkaJT)o7;av->>f*K8hq)NJ~vu>G2|lA#oLA6j^2K^8?+{ReOTw9gFzc%t=n zDFy$?4|%~=8U!L>__?GPfl)-?$!JK;6Y>@)bE@aG{)xBDWPFO<#?oH3#fmXg8$&_W zUHizmu-Vxdi)&t`T)lZ2N^C>$#!QNbPr#@|zi0MZsu$PyS;(5p-L% zD8c&HhB3hkY|=vNFb%alt3a)Q*&(@c4nk3czhaJdCuvHh+WtE+^^9mCIncV-odA@7 z=jaa#>u8YA2btDBpejgSL(%>DXM=rpp@ zb_S+4b_cBL(ax`<3dr)L4$Va_1s(ZeCa7f|JQ)y`fbCVqhMoYTdOy{D50xu-m?j74 za8D4H>vbr;@#sUP=!2izm6mD(>7hF}?1Yjpi+RUwSTt<_@L;3eXOW$^dh9`}Vo;Za zXpv(qIN6izh^;Oo;Gpm)ciw#DKnVhF>w29Y#lcWoH5fRP;VuFvMm zRefC{%s3H6qCLc&F;KPzVjE4D(zUGen9(C3dqads1&UtW{t-pYiUv=kSbg7kanK90 zwPA?4<1C`AF@RTvnWIqbexbvP#AF+h5AYBj1^=25(F&h9kG0NGDr5-uOx0`vizt4p z!_*a=5WJHgXUaeuodMVQ3T6QIA1q)9PfsWteUY$X;nXb{nlu_Cp$Z>)&w zfbp5AN0}_vplU?IQWFUb2wHpuO&wCP2F@JY|KSc3`lflg-;gV~OP`NY^o+;dq~G=~ z2Mdvsf;!DhSzDt|g3{jrtq3t_xf9SCt7pejYkWJNDWMp0+RiauKt(Q$si9yJ3}SXF zcnjoq_Dz9lkA=9CTmr|*fGB3Rc=2sF^9miZha|*Q-VArT*hcWaBvDl_)lpjNQ(CB) z9w67n%FFSIF*fc4IeToQ3UQ(Tw-gy-EKt}NDTQU0QZY$xUc~on7Hp8*5N08?VbaSl zgxwN8+>lMWv_$6+3&TH6Au1+EpU-hvG_8G6-|1-HcDBwSSc)i}{BR zb?P7OIYsBekq}$H?S}kht$7 zl@lmkua`KSldSo~x^VU`w4-5n@P@w~{C|<&ZjZ?=q=oeaIZqo!g!JapQU>tL4gea$ zfWG7-M?Zj)^Bf=oIo*$NGd`2yIFOuJ&2GCXwS~7 zgEhb>QRkl_V=|5<@ym~C9HAR&C9Ht5R6OU;p%R=-An7RJGLi%mCxI-%h&m1 zc-C33He2k|k7?u>!Wdo(^NkKR!Wsn?tAynlAy#9hIsEak*Mnuu=}cXZZMnB@`|WAf z`A-!>m(XDN^yT~yqyg{B)z?Lx_e~h072?5jw=DhYJ#}*i@(lS>w>GkoRRh|(&chdx z()1qQ47(n9Kj*lRuASw7{Gq0M9cK;KOTW7=YAUPfi!c$MO{gLx$RV z>AF-&(;#3_lJdLpi{mt%B0}q-1ubc3lZuuzkm1IMEu+?uj%yc%)UwGNu6AOKlAwgYy~qkPN_+K5;j5{(n=|GLz9s8h6V4` zzKeGabQ_ZCHL(h=wPJ4NCIL=U*qwjDyAjmHJ{A=^Y_v}Vr9{3yX|()aIrbaRWA^>m zWBGX39GnroW2MTH@iR9=jG7&^p6Y;IxCc*kCam5PLQ;jK6#v*4?cq=AJ3Z}w^TC)O zd5SOKMe&uTRDXZ)bx3b54U?d&{9ta8R*Kc$8VRr*qs53LW+L7lJ@1vFEZ&=Tx|)bpTC1qj%I9t-Wm zyR@fTCOq`EFMXdjPS*$fa#|SC?>H&4xoHq0gFSaFt)qCu!*z};)RU(GLH|v}<2K%1 zvn&TFQ)p4OlxAHRQ;C=5p@xjrX)W+BEip!0=jY3nIO>tzqSK?>Lx&;c*B|84?ap6i zR8D@)t>TA{M5F!MbjJBuqV<3(hg}=;x#@O&6va=NGybMCwOhVLZ+#a-RHqGdr6rx5 zn+SJZGXW6}sH)GQiGM=CH)0jo)*?;xo?izG3%~iQBb6DC3^~8Ma;8R}e6?3O&Fz-< zo*RXw>|Fu?4Ta}MDtA(&9v8=%lW6W%%eDIvzVJhiG%?US>4}eM#ro3t6f9lThts}j z!s?uo)qW>L4h*8$Y(yM`5zPCqy=I|41bwvdqmnmZL@l_QapS77Mc)!!&y1vN*)U=$T?yULotN5%Lwhw_PshLKVYVz#7M-3|lraC1vDwb~U?#bCfb?qXu4kMcAGtbW3nyUn2Vwo$=dA5$)N)^j~`2g0;?-Ef@xL~7KCMt`U9 zAT0KtbKaR4AN~fCT<;3C^NV2=4j;E z8|wx)@PV2MzaCJ!>|agvXmJCs0N27Pd~_#f)PPhZ#JF%I1Up=RCN>-#0Dq|`N4{Q3 zL>Phiho&VP8xBv!!+M}QP=Lu5?+99?s9=6hsl)>OkD9mU3D-nInE3Zpk#ruwQsWd{ zWK`+DMex301{Q^DKs`gw&iYuZ4=9Q`Ir*O(7hpB)`PVpLi7hIZ0CQ z2k6E>Zu=BZer|BM#KEHgluJ=lBzb;&x8Pg57EBQ!%S2zlQlOI?tQFwKBi9q99z;N; zB`~I4|Fk}mu?$@fyt@WJ@s}^dmV0TumRxa2tXL2)@jd%7qzJDo{lZL00!)b0-Yl5v zO68H2^~@AfjYJzKL{Nqiu;o_PV_VM>Np)&siM69L7f5xOZ%@pqXUzHS>xC`?L}2xB zh^NE>@ET=Gzoa1l$U0n~PYr+zs{NR7P@ibzcr!`vi(;+O`=w|yvP>cmyh4@R5`s;)ggB2}p!So*a zmP6jVUU3~N9V29^?*8|ewr<-mmE!l%p$D2H+DJ5Bv}lrvwUHEOaX8f)U3i&T{Isdc z)txzd&NUX_NXn`si7K)Rr8LxWUqtUF@pjl4o@0kp-U|ICi-Fj*Km+y(5w+S>)#!Fq zq(c3bUkJuU%AZ8hUI^^^g!HuL-IH{(Vt?d0FRAl&CTU}S;tXLxs&)5-LiGyDEmbP- zAL@4#O%RnAaGX7A6cnlBsMYGu-GDVaKiKLfr$l8DF zphCo=ZBE5_m#H)qr@$rc(hTat574OrPMM8{PGJ<{P6kMkllC$#CVhU*m2OjT$`dMP zgRu*{(WQLL>`QCV48T`W2Xr&rUMiDwIQEPJ`Of$Kp;w<3jIj46kcKkU8{cKlW%Pe6 zBj|&v-^qn|i2nI>@`46RuTt)_YpQ$UPRHtr&wl?II173;TrpjVTBa_tmG;r&uI9g+ zn9^MOV_R{Yg&WBd_RPZhc`}i8-zn`3KqtAtuvQ?}kZgOr8OHgUMbz{o&tX+(!*pGq zPor4;dc<@)+3TQ!ui2_Fv$6u_Y7!c=Q_2GJ{lb)f3;#MeRB0CNDD$_}LWyIgo2BhPq~*XllLuPq1EJDPE#@=P#QGtoXijtFKn=hWj?+H*HM_{s zYS~uro&qBu7iHQi+Wi-OjMx}Iz#6EmHUo8ym2e`yN+8ybM*rKJIh=JqHFKWj=b;W! z>9>%RU^r$dG25*yCwr=2)ohv)+_0vUiUNOml0eBd+Vi0!D_>^RN>8vmZ7#37*YrU|GZDI2$@@{W99}WC@)k}v;Tt@`pOC?zzhX!Fs#0ruXs1fe z5i18vm!IeWdAK7q9W#Cxjmn>^vw1jo%H4)4LNjG93lud51vaBn;K0;a6vy~|i*c+| zuZ%eWf{#Xpyz>M{OnCgAc^bAjZvz#j9oqp*`cI$}Qv@E9Q62DTk*%N)Obc=g8$_Za zm*Y|~k^4u=(X|+CK65JZA^@rY9@7fo&>nLvu($x!q$#3#Y6eA#6;35xaIh#b8>6F) zE&bgW&C(NIcTrGT7sfubl1}neGS^tR?xfi6*<)3K1TyD%WS1oFHS{EICQx{}olP1~%-sZmPEC`p&3ofj`E))bm$_Uc z+!?{qP1e_;$`+InPTr$RRxt2RQ>q!jng$LyD*9E?z#*(I@{sDH0;S2_gV^9qJ7}(z z9fz+R&8tKs9%MgFtYr=Z(POJAN_LsCq;h~_C={m!kQI*{S0Y8*YTB5WPyyK8dv%p; zykx@j!&=G`<}6fv@HtzLxQiREi#MzvReekRv;bhnO=_Gso5O5#4n~ncKDKsKadXE>M_S2%f3=1af_Ye4FH!T>PbHzxW^`dD(|r z*0{y40!X2EoT+T6Z^X0!v=6A%)GY@M+MvZ3hH`DZy0+ZdRNj@P?>SWFU=LA*&a3D! zC>-VUL9ZHRekc#~w11=OVn0Ij-H)8Gb619Jm((xaLe9VAKb}oMU-%QEb>hOiV8^Q@ z3Fo8z3~{T|0{R>05#hESlwyZ|+e$&jRP|b*VlKx(mk%fw!IlO&^<)f+JgJpH@!S8< zC`-G7c@tiyWyG_z|KUH}IIJ0W3b#!zI2ektnQM>*-uOfp*>K)w3GF;o{7T}lX|E&% zt1IFWM;NtSw$;!+)<9PsS()e{ag({1i1Yf-mDnBu`P%Zv?6ABAoeZ`ADEjx=GOQ&+ zsF+{6X}x8gQ%3$vkO_!e-!hi+{gggkaymZ4c49}YuQ8EKQLdeDXKn7Yg&G61tQE{w zoULf<^}Bi=B}}E7$~O7X6am%wa1A%f`BBe4j9iJ9A!V}JKZx_l6uCBi9W_Ov6u>V| z)M36{CxX?OKa+bEa$&!q6<4120bW&AwVSI%(Z@N~Qu)`QKqvBXD%Sa7of=*-u`^irelIaqz&Yg8Ta~ zUlv6mwX?7FBjjcUyA45JRKlWZT_XlVWGsg(6r~?iVM>VOAj7wyNgV@(geLR$Hzqw4n8pi`;hoQ&|L{e4eTkAM*JKeuh6y zZ(?t#0m(5z+T?gfG&qWxoj%NhIOCfm{)=-r(Vs2L9vCSpju4JOQ=249%&VFDSaQS@;wAUD!ktf1@|0jQ4lsSZSbi zERCN8kkv*$o6MRI0b}(*0`46M(Fhj;v0vhW zF%c)xsBs5m>aTWN?KjI4vzs6`Y%mey59keorTXjL1*Rg)U3g!YVNjPA9A!Pb)IE%L z_Lq){lxZUNX+qno_?g&1-AUE$zO(Pdqt5u9&m~3Myq(HfaP9t-Ew<%j zk2RoHx4+@JUx z2~o9F99<%dmBQ_P^M2R;%rjAf@y`QXg5niwlSv3(yxE(S=|KrSQo>;~ZYO$g4mnk^ zp$DRRajR#*5|?nz0$!UXM{7EnZ$`}I{+J&38ukRYsG*cAi;>A990DWCh1xHmL{Swq zPDXRswvV}*dhzPb7_Fk&RKsy?B=rQ1CuQIe^@$;T~nG+N_4{sE1fBRNWH;`i{|iuv3A#U0Q@w zub9+^GQP^7hV4I!kB~H2)81CXSk|#&3BqcL>Rky#$BgJINRSjdOv4j|ZEVG{!bQ+D zo-q)A986SEm!^k}%{bua(>+jfIIwV>=)48vyy*mB`8Gy*RIDINBi3reTN0L}5VX5s zS*^%WE2EDv-!K%JnOwgYNjU^-aTmAnIRaxu_|{}m(U$LpE*f4HUI-%LVCsdzLX%Zu zc1i|l3VoiGy5p#4#>H=f2T7*N_=H=N00$W^Hm5H`+7Y8tn;hK+np-?Z`*7r82G*UK z`Y%*_$*%lQOnAVrLL##G75!_a6~zFb?xGj^$qE2Mijc^%z5xv{pE$r`Ax*4ID2OdA z{!7~p;}nT#@|`o-$Jxh7c28+`kx4J!YF}>E$T%72PljrkKxW7r5c#L6kA;%sz6_t9 z@V5%cmB2}po%|;g%F}me6VY2w{m`*0C<6+kR~v+CECvd_q9|v#$aqMNUAh#!4G9BvO8U5TwS(xBV^={&Bowq^FlzI`UjP~;K$gKRERrts19ye_=B}fL?RTvFeM0w;5lKdHDt^b zd^3z@Ud^T=>vl`S^>uj^!Kq7w*dw<1U& z*6g~1TcgaCeg_$W8I~<5FC8wr_Rfgg_>Jfh15?G+f(8FfAh7!9=mH0G+pT2_wt5tc z5O1@v(AZJernsKQGwx`$vA@$nVh6pVa9fOv!@!S(d1DR6&>YDVkdW7O+RYZ|QNM{! zEQ4gyePToYi3$WFn9wYiqeixE~UWJv*YFNJ)CjM*t#7zu&vd`7r7#H<&y^)NV zVLY_N_H2C3noA8Tb6&n#@8Vfat}{<}PF|DMPC|6^XeiS*;v+(I!?FM?O~b6NNzC7cL7mOJIa9L4yP*Y5v5>PYA+DaC-m7>3DyQ?rk~8Kun}NTwUpER3mMWGv+NJ0B&7zjexV|$GH#5pz*orOYQ=-b zhD|33hc`=$0-eeqsBR0QX`*P)P6TC2yT-$);5|dA388*Ljn^e?y7#ZqmYIYyuEa!M zYUc+X4{&eNafKWJcB?M{bg9a#nk02;a;>Bve9eVY8xY%wTu$6jf_js6R!-qhTa7>z zB=?^UmQg#*fuNB{0U%uyAZIiHXd$9>u}0f%?D0Yb5ZYFE5>bn_Iszcscbs&e0?vr- zm^Wy7WNQ7;<Q*|6~FlNEMIUM&8u1A-1$lf3^Jq?lH9iDKwx;MC&so_QC`tn6I01s+*)IK!^ z=sW4b_2|$XV^U=DQOkQsjdgy8XGSKPU?&jTS1ul)xYd}ov-!^!2)j5h9C;_82F}7$ zVu;aiOPuf|kH}<8=4q$8`N;|oe%LtbaE%pRn#p`LfRT6->n$XHNRuVuG_}po=3Zv_ zW>w27)v<#bsY!_z6z^K->1h|ORdgIABaUOGyD)gSm%x5jv4;M+AC~M@%2K;*d+Hb) zOMR@(N=UY*MDHU+VYA|hudJ(kXi!7n0@tV~15tPAZL$qXFu9WO&J1_7s_!00RjP?0 z&6dtrOEwf$9>}kGaA_mukAOdW@fV1ZX|vOl`_&Gz;$Ih_v?rMb4Qj7fhP36Vo&*j4 zf)_=BuTrp~nDRXJJ=J11levOo`Cc=F(dy03;PkO9n<{ttt7a0W1rXshL0Cpgt42!p zvDGas{6W?qb(Ct9(yJ=W8`jHIhq(h&FHC`&7Bq=C*TR;yLqfUcoUR1umKfYi+Oi!e zGNu~-CR|R~r2TH~ztG$LqlrJ64&+i0wu(+y(^R$dRs(H@KqvjzPN5H;D~}nB(CA- ztEpX$o&pzDspqRLmweY!%05`_6P>mFI?F7e7Y;=ZHWITr>KRyCq!Px5rw& zag=4`UKNyUMRiiDUfRGpMKge+*;YionXiIwMHTA<-tUi-N}Z?y+H9Zk5;u?yj*-7u{#fS>yrAPq@gbinR1yQzGay> zwy4Kvn4r8ClYJ#}j4RTCAP@B~8uAyWw^4P2ds7I8J<`_+=? zvwjFRGlka^IEX07n%}gYtX0lx{oecQq#?rUgN8wgw(ej!FvsQses=TQ^`wcI?{;t0 zZdfW-lCtuq`uGi31@rzJYQllBInIdqt%LvmmUgrWmZ-%ozz9P0)d4{_72{Yo0gp#{ zTF-3e6mW)ILmdg?QqUXy=ul9rQA@iGx!)2gBjw?07T~VoGsdoraDZ<(+9Qwf9Xg zeAN?QF{}9|)uFrPGJ!6WH3C8Tc+3^Qu*VMAV9f3S9Z~%civs#jaoS@L@t658@pSu9 z8Al?N{ybwg`&o-#;_yZ6icTlg7PR-4YE2&EIII}BihL!IdH{s+8#oO!7Pd-;6PWI| z*Xj7+YFJGLDzK8MEp@u{%^*o^p|{dxL>s+T%N}pI7@llUR8gsBoZaCoM#@!@b!mhF zfnwL!dJ#h%65rch5ArlL2`|VABZJJYzv&K~)XeH*oObcHmeXfK#BbiXn zvMsFOweQ};&NSjrseZR|Zx0r&Hvwa~1_h>8wA%%!Elmr>VWQH1?IYHIFmtE1o9|;+ za>%Y4N$cR*u~UT{B(2N6WQs|D%K-NXfbh-29=x`=bR~M-rWF4tlY8=i?85C1r zrt*l|AwY;x!TGEv+YZD@FA(R-K_3i%v@whDrFq7ht4EIo?!$gxn$)S4P}tEnsn$o* zH@LWgd;5P%yb!a*`zI&ZiJR8e9MzFVuP5>~a>Zz`hQMjGOG9Af3x(oW%8j0_**qv= zk`(5CW`~YaH2APglN#wqwUUJkTaf)}D@KF0Y2h8&SXXP=*gL_a`!4Y<&Q z&c+bCyAl!=o8o3XGcwQPE(`<(|G}L916e~%3RU*^6%G^h6nC~`cqgmHY@pWlbCwI@ z?_BPnJ;lFYep@Q6AEi438>8md{=J;M8;b?6=M`sXS7*7O?ka-`f`c4KN-(kNhD|`` ztd5BnN;BvaaKoXmA=;&dNrJ&)jY8j6HwQI6HMB z?v?yPeF)8cY$rF|?)9xLkgih5$rw~c`+hLcrUP2_`YOPd{K*D?(LmGpxa}pnsMEND z->DNS8&1E_!SljajXB@|JR%xfm~y#0(Wuqie3tGd4d$f(bLP2GuN-o;>|!9q}p zW3KJcc4-v>GSdeNU)p{4kK^i5e0l_*k95}!p%G!|$2z^Ic;%xQWJ-ZVFU3ZuU6Br3 znqZWi{^C1p1IcJH6QsL!UDdix1yMHT-{&gjxo4idXPNx)KbkQv%7EPVlX$&{c0)Vf znl05*%fuk#bZa#Ku2vYgF|k}pAoRBu_cwCa8D9SJLaI{%>cHZ8&643sM61H z3Y{pEEPw_*hppC0e2b9WqcWr^k%R6ytyJ@7mN8co-VTnZZPuTH4UOxl4L1?F5}Qdu z8a2QG5|1nJ{i4~~%^&dCKQ&xBMxLnOkX<*Z3hfllJk}w51~XwJg6bYB79nxsr>F64 zk9=nE^!fzi2WUv@)^ebC2!t0dM`Nlxce6<9I5uXrxTTtDl=-D;$vfLHf)Q&sLI(7g zBG$>#-BBlreZm0J%S??Gyl@+)wKFfyv5%xYT5I9)%Hj5Af0syW=%(7O^!9u$1ve%* zRkU{cvx;BUCU8U$j4U^*X;;#pXUFCcX}NseV&w!jtuE2vU5X}JM7oljyR#D?E;=Ig zCVZvFxDv4AcjG1@mLkSRnpZD<*J6Lje{d@SmGgKb-xWEMiuZ3;Py_Hc4iwGz6I3ql zNOE9uj{h9KaWv$zBCHYqY-DEb`lawWylPH$I)WZ_-hw?4w6_GfVS+`1s)=!;i@T!) zJ)`01*LyCoIai6xEqm2;=B|xuI%dvq{Ok^cr~EZAJ@D`&YBlpE(dNN+wi{ko)L(vA zFJ5XrZ#1jN2RQ{Z2-MG$;H7hETpN>rjpQFs)k-PxPn zLy>J(EgbN1{8irfgPr}smw{qy{nZf0sKC;bc=6)xZ)Jwt%Gw;K`jXq8@<3QOag#Ef zaoQ7iLANqFu%=g#w7+bX;gp$mWlyz2n58*372e-6(koQb z>nzsd7!oSx2=n_+cbCfY13X>HZ~?4APs@0Hb8r``68 zVN`I~8KWMnRH$D}`opdsqYExZ6SyI~uo_l)c2Omux^#El@=ymg}ZC)+& zkmiH()Sgsrt=oED-eSW>a5W+`?7tpvPG9U0?IWA*f~_4Grn+7fUf|m3ogo3;2sUo@|QeI%_;>mlR3#mH?a;_At#e*0W?u}l!GZv#V%AaZPufbsWs|;yR9mv?f zD#x4_^wXoYTOwHaCK}cT7rqkn|JY#3#}dl!877RTV8>%fX=Mq@3IeM;iP9|-Fh;f` z&2of^YIn|Pc=dC?bLDxj8yWYGPZCpD9b_s*G7Z5TM)5re%)!p#IEyIM@peCzvGA{c z2Sb;4K9M0~v0@y>j7lp?XuU`q?;@@LT`7{EitW2tR{QE)`9;DB8@5jS{kgK_jc=9` zQfOK2#?sSjv#NGl_nv?+Hbi9ysnosSZ5vpKv;gX-71S2lhObu&p>a|h>ZFMI|Agul z0^V}KKQL}EWfTXB2*9Vt$j`J)wt(6o(_0Bo(1GXsN;< z=Vb$HH#@gmVmoiRCc_rqgDm7sD=c0s){xsO2z*RELm7yuO@W*x56fmaf>@0aen*iF z7LSsfZJcdo@U@YlHIR6|I+RoHj#gE7(4Fau-@kmitR2ocNd@b~r3FSXfx4$zeBxg8 zHh62nai?xuT}FaKa9(~p`{JsnPPG=A12D4#8rZuN(Yu1PDmhgoX^}`Fb6%lu8|mR?_Yhx>XRpWT3cUw)@S8;lxSQY|Ck>F+*359 z71E+fsqNP?Ks*~u`I6%(%;rfZJU?aKGkmT*OYo%`8Iql8(fFdYOS`!#EA5JW2Wap? zB}oyVxE%&hi+*Z0qExN+j&tBW*C|Nt;g2JH2}{0DsvGiAYvLqWxxK=6aa^r{&|vZh zn^eylQH*!!DPhG#l#%;%Bgv4^7j_UWus32`MA`) z{82T4y_;3Z>I0%*T{#N+T}PwALl^8K=*yH=o!c=agRQ=FSXv}gXR+6f9Ms@TZC*|# zey-{2`^r$ses8j4yD}OLlw9Z&x4-a+4kfjsO7><$IF}L0z4rdTylh9;%c){nt5ldS zxH?e2FkfX>%XQ|uKqPQvC4)lZO`qDW!%)|}#NYJ~x>-2cr-}C^R%5RSrG*xRA1XUg z0xcfT8L;vDa_Dq_nr7TVuj}b#kSS%azCIFc)lJFC9Gjfc`%K7B=u8iC!IiBD3@cIG z=NE)(us-X}jAoe-r-Z5`6C(abgO}jQx3KAA8hLU;sDtWP>q-nv+ z)-JR4A984`=~nv_#_skeLa+Vrx{%3UG9@JY!Pscj-%oIOW5^G{7qiO!4QbX1da7)Z z@`Rsvozlt~wb?lC2cK`a?X9%P*7Y;AtJotBf7svs!*a$|7hz!uSedX-B zlu{}sLk?mHtM`-A2YjNK{4r8T(gsq3Pyc=@ubdmwheQ>2Jm^V}oS|!0Ntu}%dN0_~ zL}Zbcf|Lg7gIdFbp1CLow%7ha2Us08gCAoma~ zE#F3m`x+?Co^dR=F)WxfZ{!)1WtB}qBJFaUQmbhKa%YX4X1u;l0vL!oNNo{lG z%6SQ#(_{H{T-=Y#G6ma`V{Nx-fM*z5ATv5NH0(;~+1Nwho>ux4E7^|Sqw`y(Hb&!^ z7%nKOy&|%N z`=Bg!Pt5?Y^F77$+euv!YO)H68j@sBteZu_{o zlyMKs+(%z|Jp=b`N?o=fFHdTZ91fgsA#-9X1UAZ?S%# zJ@C(sX_r~%Doc-ck8rjgA?avWpSN7k_2-#HuWudi;hY{}W7QT97-}xP_}3Dv8Imw# z;Vs0mG6A8hm(hA26b51t%m(O|6+|~YwgJng;-9-8%3NXPpN*#Mh{rEI9a&wkA+S8G z)RatZv?dG>lPhEb@#vo^O^zQiJ`GSN$#ZFL*j}GxJ(OX5yOtm#o*0TTC!m;PeoTB$ zV2#sP4L+-vq_ZTux4M;)YqohU#@F5dsC}{Nwd&5Lqy`RWmu|DPCXFJIe+G}$NX4FR zOpa%|PXF_DU#~^2etGH`h(}I{aI%St$m3?iN^w35(T8vvEr#H*M>uAb&9H5%(G&g? z_jR*hd7?ZKiq~k85VlXN?eG`Nn2PSz!)RWNTKi;&rDa|I$D3RDXPk?7vNb?znO!Vo z{a(5`?rpUf+*5*>qkT0qQd?dBAkOCzR-|QM_G1#-%MG3OndA?#EPHPC*h|^NFS;QG zV>=0X5engVVPRi|Qtyr;jU&7IlUWg4JVL%f8pg&sVViqOZUuv=xCR6pqSdzyp_bWe zlsJX;)P^Kz-l;A2>`foYN7rCmI_lYsg0 zI2fhp{*K;yWAf>4)LO}*RA_p$=K#BH@+px-$3qT)dK`%sxc%YIy`Mlbx_d&M-JEhE z{3@r9FHy9|`U^T+@bAdpzp!=t0zf^ICfh!CGA(1b^By@dL1VP0>tROJn-TYMCj`Zn zbBHnG^a)KLIC=H_j8Mnvg!iN&1j}K#Oh7@gZ=bhICo>ZAfp#Q&Z+&o}73PY}Ups$f zQrw={@Z;0W$nD0P*Rm@rQ&|iB>-r!b{UeIRPNF>9&}U*^L~K()iqOh>Bw9{?1Hs3` z?pY5~jiz4~RUvcLrIIarw!PXeHs{j4en=hNYu{XYTUp)#{O_KV6hHoqm6b`zH;)d@ zb(9Z|;{2Z*Dy0_OH}&Pa>JjBW1B@Y6Ny6_&vX9(0efXVgtLpqh;+(uG#0o*k!`c1^ zLyNe{dqDK+cruYWPhA@JY^1DP3`%W>H9r&{gwF4;{8moWL%@q-C-YA;+bA$fQG|vz z{&xza3(#Umq;31>tLqgrGptOE_9U{k@UmZ_nCnXx2ezFRXK{e1&fDUt~l7lH?gn_kC;ocZ*d+K0Y)&-aEtZ|&# z{%sl~q|m7Jnj&lO<#Y0^0=F}PzL`~Z`BSnq(J9cdjS+21ti1dEA*LFajF*J=B*SUM z=|}33KlltSUE5dUfOJ{>r9FWWkfFhhoDw^DK=fe@(+8CDB6O$TQF9bAOf^$Sbw>DU zv)*RwSu3r(#!SmGyDW|zBMtX1mLAN;Vm{N>4yG4eG;N8{Wxf9;qhwp;dEG3Mo8wk;#r>A_k^nI~zU7C!?TFLN6DiypJtf z_#F(q?pU*+H$s1fyD(f1xDe&@H|E|C^=ziFGeaa>W z$r-x+%?aW(GW&WTfFIzfB$jujGlA>slmXJ0f05F+Zuwj9{fxO#5j52}>ai8m$uBb# zb$1cvaQ!h6?WstHwIt~C$Im1>OX?KmVeS^+uG<#Or_zijS86PdZ-+>PSE7l|#)p=q z*oT`D7(Ec1li$nj~HU$?`tovJgsB+mA+AnoF({!QBmZpws+wvwl+2bTRcq&Cr*2AYfMQ~trf4FLXcP>Kuw zqA}11GG!X&XDs?nv(~?Pc%@qA&9#%7-Ud2P0pr)Fb@+>R7dK1k4c?2vE=+SDIK|Gu z=WIKX{ZqGe>peIr+u2lM7Pw@>2rlf_lbTnH! zcOdrD!Q~s$yxujR#hz|c*z^q#MOzH#-b-ZwVJ+iab&p6%X$+w} z$^G6=C(h2I8y~M`92?7zqBfLhoq4Q8@;`55ZFx$`pPhdInrz&ZI(V}agUmExLY#Rz z83+Uunf$_ggN4VOW_BLOc58DXRe&3$c@TyAmVo29h)KPNZLSTe|6}i~pXvyjc7rq1EO@2M4;`F{hc|zqvW3(3Q zgG%z)NO+<92jK%uyx}C}fAkoSG@*=eUSr@03Ham<3J*p1lI#oDF5v~OPLw6e{cH3` zQ(l88i2Xf07h<_;mu&sVT%oe+zrx^3t50TDE3UR=6fx3RB^?L`4l;vR;NOVPf}^3SBYtu zditrvasUu!0ISNYKK$A8;g3e+8l|G%lTnxEItKLd#2n}8L`M4 zx}kK>_npqUFJm3Q{bsJvk1Eow!>4#}36FDD&JJznzSQB1v8?Z(J!}&{kD!jnZJ1Al zjFn|ed-Q#u*PtFG{;kVDohm1%B+1}tY%(4g>k8*|q;TS5@J*rvyV}nzRqAQ&)jat0 zj=YIY#T!FnMojlSq_$ZL!L}%MS2YuN6I3)389y8vQh;%F99zrjQnaY%`YbAR2 zINb;}cMQZdfNm;s2Mp3njAXgII)u3IcK2e$Tcs!RvHRl-E*Bo(&CGl!NDowVA4Dyj zI)k;LwfM|z@`|cYd^1=cOjmv0R|t9=XGleKZqw>KbOtrknF>xkgQ0o%K8*}v1QX;Xu}uD6-|K#%cyojL%g_0CC5ft)I)N{0#NQ{ z$|@-q^N5$?roZ!(azHg~Ik_goh((aD6z^UdFqO%y31D4*<7!7ODBQ#f?g_X%8&Ef9a}PXGS+xBO#kHwD*-`G zuBXzIYRbHU!A3Y>%Vkmx{i$W0k=#2(LuOwtc@`#mzC*tgBo^+D*-pljNg>ZVx3?b) zHT#CQNQ8rFyV~qE)cXQ+Hd26-b08g>(#xw|LKLyfzq%q3=3|55sB?!P=PK^q)G*xY zX#nZ=BY4#QhrvyShp2(?=%C*SW1*w$3UzaQmjVf^?{Klx>7sQZN?v~J?vz9Gwyb7B z-7qq4#+%rcCQ$t!S9XUuk*0O*fqZSpfbD}P&hnY#AZ?gRDZ(-Y_P}LB5iN2YzI0dC zv{H#Bv5LotZxQ?=fi-+cTO%e)6Et61`skgXGdb=nTkvRWMM-swnC}{dmIp&l0)L!+ zc=^;{RBT(>Sl^}xAzoQNOtZBIub{>^gnMEO)qg&L?Y$&G{|7yj+UO}-Ogf0aBQY^y zBi0xvuJ&Q`f5V~WFgPQa&33fi#O#s&(U3(rOoW3hdjL00EZ&44g^q8Am2Gi??H$*P zqgz!(-0)h7(eKXp(;*%9+zT@hQlgXq8@^qNS1a!Nw2L%n~+BX3buku zy^1CG^(wCH?#NH}(_ut2Dt>92dn6Ci-eA7j#* z#_+?I<3{V}%#?m$jdz6WS=93Fu(_;xWAOxd+lI;pUOq`5O@LA}BC}p?4g3Q{B=Hq> zN}A4mRSvmV)i}_wSlTy|t-(^)SXiD~5OP_jrg2-V#kCGaD{O~d;fLH-Cbr|jm=am| zR-5XT-#pp>M%&UpQs5Xi2vyt~5$`7?Bd+1K`>eyn$GT=D|DaG4fIt4U1~Eh zdwdSm)hn_QI*W?ps~}}7&v|;dWW^fzG;&?#yu^(Iz(xj@J z9mE4q#tl6n+Btfoc+|pZKe!saax0+$wTsk$){^G?xd`H2YvDkZX~Nj`&AdkQd@z)S zzjf<>pn5g?*B1(}^ht5+U)tX|!4=+uOLtnUSWd%fUYlmuhhy&DTeBsfjzl@OlxdNE zm(k(YR>Wb4+_Knpub26;*1J=`=(w{ZWddoOqevO!%zR3LM!$QgRx};gD8)tS zv8MiH&1OW`b03(}uD1k-vmR@z>QqMW@H(qV?U2R)1tqt4k?=}eF9b%DgV~kK=g)U>sW`4E&JHS>Zvy8{;fo>Vv7RQ9H8ASI3^TQ`RxtY4(62t@DZ*yQ zXG(kan=j8n4H})7`cf~zEM*&y3f#LRKcNKe_u;ywLdl<)yjSDU2Cg)3F$3w) zzTbo0xj-@8-H@t0VAz=mg-WbchdZ*#Skd44T3dB#S7ba7J~3W)6alPD-_#37)>qqK z$v;MhJ0l8G<#K(;<}AH@lqBBn?Fp2=*`qIm;d1ZU>z}~CX29WdU8342!Q&Fac9WLl zx8@U&<9b)K9X_ie#|fL_5SHQk3rZSO+ko}nXanvv)&Ag*c-gxhEIb5+tA3mQ#!z)B z+T#H2Daj(ouk$$wX>l##j*;8ETx6i3=A8}D8Y&HRSF!CL zml%RKeYn)wDSLFf9a)0+V?L0ilhHx6H%h68=$etLR3uy4g0%YX%5}^`g}qSCSIg> z&%%8)B7J*8Z6!hEH58=aj8#&DB{snpds`q?4OnY`hmCSHEJ%4dM@LwP+J>pP)n}{@rJ4 zPUPKc<$)x{LiLE4lkz^PP%bj~P!=3rj=CP&n(U=0T7hg7w+#gRk&)Am01`upRgKo5EmdWw;TS$F_vhkHys?&w`hB=#b|tHj!Kz>pUfzCg zEpGs3Tk?k_l^(bY@Q)V7o+fmA?;9@F6x&1L&X7l!?cWM6%D_QM-YpGz;B6>xt<+SlzG?Altc)jufOdUk~ljPopfw|4O~+$ z@@EdyAUw{{I#WONZx6u=vVZI2oTzDRO#wn6E<_c&A4eWsY z1)(^154iF#pIQ6?sMZXaSglSt)x^))lkU6Zm3;w}JCU!!J^N-waVrso z1>qOyM)4Os^?pO_qZChQ)d2s^lc|nT_aKU#>mJWK2a(^VKK($Y)=7~j$Kd*l z^V?rq-Z!(tg#t!;My@AG-K#$=ZM3GuK~klj_iO~!Hw-LK{fa`}JpVbNLnehNk!C~l zVH84kmrkuG9#;7wa`I7+$_K3q10AL{l{v2Pfa-cNM+Savtb(7F2<*_TOWEfSPOI{5 zh1Z7nEr#9?`8$}o9XMk)uB(LD{cLn3hOFCz7b)Bj>c8TKzB4=m)J?-xN*G(BI_!Q#zI==pV>=Hz)?TP%Pp?TA5e%y{seN2hb z24GpxPKKm(Co3j0?Zyz{r%B6w92(p6B{vRJ$kdiy$Cn#e-cFr2L_7~5?M!b|A@DAUpY8_~>->j`t_mU+ZZs`f7XG|ZEGE2B%g^dJky0Y7PUZ#G&cE{}|Yw6TC6xEOfI|+Ucx7 zzvFy?TrNLQWv-ek{-}`aA6~?;d5>hRE+nIo$ zzx~N~RcT_{{j+_JM=t>h%RE(d?OhNV@q)JVmo2TlCu-N{^zVWKQPPzY%7SXW9V)OU9HZ?Tm&1_N`3V}M-7#IMgL&9=e>tmL)YPzq~{!l%1fB)X^OzF}IJqI`C7#f=8yZSvfKA+9GKSYlGeJ^3SAK z7?L)GwD`Me9lJExy}}ed*5*eNgG{ds{CRnd;mV-98iJ{iF$FS8{gzYy-eCTpNKqK` za93xSwI{7v`l4kTKKg3~i%=~S7StYQ=9lU9$@yC*)`MpoJ)V;9TxbitC=dr#1SOyx zxxZfD5t0koSQOvx(&2&jz`4KPcdfLfN%?p5xNR&JUcSZ8W&G#sfVqV?<$f=f)RMg` zDyGCn%O*3@ioXeLN0&4@UY4J4y?E=Ow}}n?0E(5Ch%G7s2P2jZSxor2GW^mNFUZqf z-sQF`S?kCM_L#&#h}lz;T!yiC>Nl5!B@V`>i8Q&P97B$S)+p~egXO@Gpc3XsRduOQ z{W$}UCCJtl`)=Q!@ui2MYBe}&j8dXWldv&}mk)|lYsY@H9yv&G=>h77mOK7(dC(5? z;X|JKTBJ2dqE68x$`x2Xt&eSFD*3~nlb>(-MY0D9-dVptz2{Tqq~Y#YhTu27hO?>J zcJUvvpHch8~F6$rh1bvdNg$P7tupYtr>d3N*oEm#Ed1bqS z-{Gd7A8!|E`08$L0mi%fu>ihNFX_<9h^*MZdT%uHbe%V<|8fE!oFc3#v?ek};qx&>lWX%x+~?8JT_Vlj3&S_Z2s4kZ9r}qGJ6J&F$d?lD0G^>6BQPk4S$?(F z51NNeQmdD}#o`Y<83o!yn?;U|zMQ|F!Rt-j2tHmfos{Cq+y1skJ__Y0$Ad(*fm!yrI45RX&zW+>r} zByK4Trh#e7-JJAgB}6>#XUKydYV>O54SC(=h``DFwE*FxlY7_1xE)&=z7`{H`xtMX zw|GX89;a0hkfKz;!!&G6TE8GL&yyqJud&?kLmEV&Vd|6f7>B0TPwzgZ>0j+G7@RS!8~alk=cX{%-^UC=@9nYt$ElLP*R~2m(fJg` zhf6U1&NA|>+ZwxB&?L{4P^Go6@tsyO*r*gph$hyl9;Q33Dfz@G<5S;J47XoO=;9jb zOq1wMp5_*D{3>(9CVPP#A8Y3g>f&eXacC6E z;_9hq^|M&&=%u@DLdp|qD4DO1oA?zN9p;JRYA4ociGyMin`kOjEFq*~n#A6=VsaMn zkl|UgrX}K~{}PKBr^=;vJgeVjL+>oYgvo`UV}B#!lI4=23WjzN`YZk1(BVWnJFnsbSIX zc7lhS015*ew4k^-mgE-%9b)pHAxCC-RMHjl4m}-+_>Of!nt|ypr*=qm5FjmuL z$SFnys~!T{r8HHjpsfx`)mTs`hdYh4V^pTnSdKliEx-CK-P@yrD(i!e=kY;AUZ^+5GXo?}#y8fWRfiIV}XNk)I+zyik} zoDE~et=lhJ)$NN(-S}NI;ZTV9FV}^ViqYiv+&)pJ=7NV&QNs>KJd1B$npp6tX}Qn8 zB+j)QH7REt?1Xa5pm!*F7a;ggdXsX8kAvb$!DrC+*&37=;me{Ky!m(n91mKrd(NrR zxGT=Z+s`=-Zp)bITcN@!$s*vms^O%PbizBd&G?8&h){hv*h9q`59hYLwQL2jU%VO1 zNMH&l4>1IevRAK=5ycRSgdR3vf%!y^qNyzZG+|5Rgh!QBsdy2w!bj>yjDRj#J)2j7s+YlvBD&3$bu$w0Xktx&n z5Nf4Xo69{iOhO`*O~(E!=#U&xT;>L-3rxCc)I`_Hm2Pj0Pw3fm*J+ni0!JbyJ&d7C zalz+0p!7GUY~%mF>StK`ME=Tnd86 zb9V@0q`W=GtY;GWhx5^c+#rT%Qy6O-ie00{u8>^DI^tF9lvoOBMQ$RqvY|O_>wrOe z*({C2+0RJV)S-Aa?x)gls8b;YX1*}Jq6k?V6I+f`iH$#BIb%ggpgFyc0jWSnhmm&_;h^bV2IBptctoAaO|VFrP6X0r zo+i3oL%$#>_@|FAXcRX0n6eQN(O}c00rJ(7eFN( zAV64m%Th7U82F36hs^K|)%&ALNd-`8wchq1avs>5qxS6Q<%qo|3nWvk6(*1L_=X0$NfX^-MqZ ziW%Hr?86(Kf_(kvb7I-G%pF;oK1m_YC7|O+91o75D|29n>Dg#v|N21i@=wNbX_bTx z#h)Q66wM;0FXnFJ3*mWZW526B{e93BYi~Ud@Ajk+8?M9oqg}4?LtP?#-jRt|M5P`A{l+c)znWq8TC+%-^#+-ez)GMJ3!Js^%@HzNk!&)_>nISc_ub6F)hh3~v8ZTFh z@HT@|?eaUZRfOce6XQX}Jv(x~#Rw5dGXsm*&sQa0Dv9u}(OZ;Q@Sz5O2do35Jjx|4 z0#`2Q($DS|6_1IDTcIthxe~amtYFP}$!b0by4SOphu5R)en&3|$3)rc2|wZ+?7yp~ zz((VIGL}!@gZja1(k}FQ(t$Kt<^#Kh<1z-d6PUe=#XU;u&`l~y&V7vd+1{x$($@Dt z?pUY7Ht@51{xkBG<(~rk&sLaJV}i6cru)6a;3NK~JYJye+~YPKkB`w5BlM_(O{t%gp4)0f&)Fn-JQ|Uhi(U+omJP^Zx%znPCXyq7(50oQpS`CbC!Y$_N)v4w``olf{Ns=&3b*PD-K{2+2YcMVjGk0R z)6qt8{(QF#n6Z{5%EIZ)5{V}ZU@DSYqAW$uJzn^9)%tE(4tpgYIyT9Ld{uR^dX ztPSc&Mc4*J2k5G9Z0+_>ysWh=hK31^S%3LlAP;~*wJc2>piJSBB7HbGw_97695AI7 zI5DmG7ZilL*~JE73J217mOV;U)gE0*Wp)JOv2MB!c84U1e`Py1kV?}LSbMT;MOvcM zibW+o*|9+eH!#v9%IMOS+%9tRs9i-MUQq4GV+Q?#_DDA}gj&0USe#tvs7f@|kZfEO zP3#(EeeTTG>sKWEgU5PtV$1v>L8Oow`^J%75--V~nM)_TYMz*5D0=>`wM<6B*fhMU zYO}NwDpyZ#AGPg@91DhHsi@ObI_4}V#H0d$b8hoZc0jaPNuWE0rGI&BlA|q#loQY7 zB6vl*RL?umqw0>(!k{Wij+n5E{x*$`{Gs!R@$!a%>+t^cwV1jG_Gya>#RqKJ)Az)> zb#qnEMj5TQFHQS$ZW*DhVJTx5A9{j4Y!M+AwIL%-6ioSu33d~spkw;iqVb*X(ebqk zW{OR;{?XC-z}mdQ8Z86#T<)>ke)c~qvywd1F_i{71*zMn=#E&^br_3%yk!`SEpX%1 zq6edtOMrI-RMaWYf7FneznufK%=HLQ@O3s=f6{8g7qlGBCH8jxGo>cPj#~KV5Q{JzeB^s2P@In+9*Gp}3jP(|Tx`4-Nof!~p9;X$VSS*OsLAOVDf zU-54y`$^$xw6Z^C1@WoD)*jRo6TYy5MNT|5mw{?s5K@z$92eFx57a8D_u7>SThVJ} ztQdyM8+S+YFNd7sQ`;qh@2o6xoVPoy_?J2vaHGnJfN#iUYi}bstoWK*G5dy_E%>?} zl=gfxnLltgeQaS|R%;-72JmLziXZ2!%AM?_^(zr$uNPMeij_R}snxhyQ5Z-=L@+tA zkDrt(qp9u(5Y|BmR-4LWKR$m}-57UwqCf|z3qHm=%?=?~90Z+(#thcPXOC`bk9nlpEa;CSzrmif87IfA!VOf6 z-i!ITa>lm-@JAu564r{9m6DrM8I1#Tgrvptd%FZ`{Rls7S}7Y3a%N}*+wNa+K z82|v+_UD`9$_^+h0*&Ch{MB1aSe%NjF_oVB^;Ea|Pcc+`z|~Fii-}pmAl@c+QpDD{ zjf^m%%xG7vMbBz9Tk1)`ZqGg`iub;YL&Psk@DY9b&kyq2i(AIw5uC)QI|%!?#YNxQ z2YRDN^9%I$-Smrcp#8CY>By+`v252&cE7}KI0Qr5Qc}XM&(t+K1s5Fpx;>0D{sv5f zze(sCIgS%&NKfv!8NPf*T~0$Ck0O|pT?zZP#F4KwFB$hFv#|cT||9o8Oa7VP@zhxgnB{p=Vmj9*y|4MyH z@c&EdtFQe(=u`PA5uz5~m)oX@&gv2Ucscju%u+jFNaLF=G-3GM_WD5Asl8FAAJ*Gq z4-uRKW{wLx2fytb+o#${x2J%*A2hL9N7k%$WVOk<+4eeZEVn7`2_wXcLxZsOEe(t+ zUO1YO3Q1FOW!&?hWQI}p-`xp@&k{%JbLz;v$YS@e^qShyosTkM3J7cw8mI1F$Qhua z7M_i6t6H?8Sw=AhAfbGDPv80?UpOy;0a zL;`upDaUT|70joshXsKYyjMmtC>XMN35YjXk5;Uv%AqOJ#2=`{hG9)&3-a|LP?ej=O{GHHR6$4k^(%QV(M)n@Qk4VL9I>W zp~AW@C@qi(^BgoabZScd_=_#J3c3~fO10d)X|Aa?HIj22jq;0?8|C~DFU@NZw8L1* zbF5JgY89~0GlfW*1_wYd+vbIvTbsAh{S{Qf%#2_s#y88llxoI7dB(TG5{C_6ApeWH z?Sgw(&dPe}l>)EkMRqJN_GFuIHCRV_@d+p3x*U}?+!m>r&CTCBJ9VZDeT_WEPy*1S zCAjQ-bgzrqz_g05?mQMhhs~*uL^@|}CQ94QP-&vg#F{W-g2ngq(MzuVQhfu7h|lF* zn7ybfG=_l3d~B>B-JOWdV+uAJ3>aOG%a8WsOuZ;H8XvC8_c~v>DE9Y-z>yL!B1pN7 zt1(9@F{?W-p}-KHWF(P(v?`*0u^}Ny^Aht25U{Q@6`>NyZ2Gsn6XK$xvnad*&k&{R z@_WEvLqm7Atc;{plXl56z0H%F+U#hs-Ai06KTN=9|V(|nC$;ro&-xp}Z3 zTp}=XB$)DSYlXgX5BxO^S98C+VS8WCP!3$tlz^%fDz8Ep5Q>uJzTfPX^vUQNPU}F5 zZjJ``C8x4WX`2M`+&1OCYQF!*gZV0Z(fz4%{LyliUR5q+k2$3^$vkFb@PALMTF3nU zBqD0$$1+7OvHs=NB72t9(liq@xeMm4=%mF36nP=S6izVN<6jLiB6JJXI|cdN73$_~ z^?X;FUyFqKrR3~75Vw{6#@j^1YMT9p=_Kx$WUF*67lL`_@a zk9zrsl6raD?by|=c0KY(hYz`CE{JQ1AHDD4bav89*KH4?uIO(b4rod);W9!Gd)y$A z{PSOg;W!pviq}B;y%+Z6Wa2bEqikb$x6MIvZ<$YuApzgUWZWMN;^Lwcv_V`2_NHIy z$Ia;HZ3^QOmV4DJq94@XS;zp1w}O9^1zL^DZo;szd0+#euE9J zOCaxYGPuR-h7X29x|IB)iFB(;euKo-n?MD?d|kc?a}VAIc2P@GNdktjZiAhIoy0Qm zl^Lt55nxsEripT@4Y#9^PQ8^|nYXHX@nw(~QP*rM4QqH|29sMB&v3z!knYB z;+sgoFF)5PsT2T5uVvkQNoHitWR(qZMVchKY*?|$uTz4@R>-(!v5ZPaJVi`&*%20D zp;toV5Cab>`OYG8bpIBjI+Tpm6BwOBxurA`~$YTvh_$z{?c2zQAHe;8hkg0S)?Uwy?cnJKA5p1030{-U@inkKX0uM7ul3wak9Ca#R>P2ZyDR;Q z;xA2FtndB!?i6L~0Z_NM&Q#Cba)Kh`aU9R662w3pOlB{0ROC$UV37(~&uH1pJ<-AW zAJE0=wK?89SW0nBob3jvC_9i{4c$201ylRj?;1)9V*(ZIrV5rjKz@q}s{7N#Bc)uk zswV@1ytER(8mmIG>s!??vEB#jT}63~+c#hhN+WIe8G6dJ>JQOws!^aL`Bhh^h#{I#quppHq07TFqx>hG7@`@GF)jvr`-|*6zQop{nEP({lpT%AvR4bdxlP z5-h(sCe83K0$LtRE5lNSJ@EYcMVy-@hsY}{RMoa*)p8Rr7QQN?{u+6cE%dHiF&L5eS0y>@32ONl4RarJC0_CX zF*BwBF(4lpS*0wvlv)~Od^rQ$&kTB(h#Gc#KSSMCUb`VZGupP}4Go#?h+g9St4f1zuCfPo{K5}5a(`cbP0bg8(Pq_&zK6X32omBk+a`6G6-s6CG~prg%?ouj>u&))4of1I>}gf;AaTEWA+ zrwl!UT~Nbch4Oa-^W!?D41iMbwo% z#m&-Ji;q#lV!pH#IVsZo6(dClb<}ObO;5RW=P^_hsp`shmXAPTT%x}aCTbP;)XY?e&iVL7#1V1p z47zSw_v79uC0GT~@J^HRMmFtL`_|61J@HF<=a8!CukdxwV9yZUnt0lo-|lZ#n?8TQ z30O!_2!b#(vg+&+oCh&uA!E3D+a8I;S=&ZkWdEQIM{_fB!dOquc5u_0@*JB-3~@QW zDcIG{r~4nDi=yX%oE;W1Nd;l8Rl0*krYcBN5RwSRwq)_OjzI0$XlNNQez~5NP2ia= zmpHfUmjV_XFw_|Q?}P=wB*Wvms?wFvT>lPAEV8;GBkRV8Sy@pd|y+)iP^l;{xdJNf5D~g zR`0)>VtN*XlvLDgeO(Oa_TgVzmG@3HKY;Wbm=kyzu}<`-ZBBq>P8OeJP2Vl1(w6bq z`F*n0X^iF%Kcx-Xji_#&3jH#-SL+@>N`MW^MJ@-P@JZb0baq0&A(`5p)@FUyv#nkL}2bsWvW@ zS=Fg3n@itn#wXigKqu=cNjqqi4Ot*T8&*VplgAsf>lC??I+ef_8mh@B>Yb6OjK5j4 z6`59tM7z;_Vs%D2%(={wk7?)l&B_U2&`B5P<3~;so43IjM}zRNLCXRWgmLZAvKRSN zft+?^bWy}91l%HnQfO6BL2%Mrm@bN#II_Sio|C1xc_23Cqk9%An;EsLH?>X7QS{NHmYqj?bB$C{zbal(#j+3TUkxYbSY}>9 za_f4@%B@?Jz+QF}}8mYN4AFa3KTfH%+KR_jR5y1}}^^@NS1 zb;se;_08PKe&CpzK}X?m z8i6h<7JS|(Zi`RpnbGX;(ZULY4uxFmZJV$>c#Ia$a#H36jqzE|O|MTTdY7AwB^?+0 zd}MgNx_&d}G%N~Q>Xi|F2cFR2!Q(LXXOOG?qFKiiXFqxP=_JJM-l&p0OXO5I+~M?g|dg~#t(@J(7o z7_-{!8Z-6f&P~RSZ#qmC_p?9AvPr$DPqrf(4WqaW2r{=(BBoddcy@6+a(tvx4&?6i zv)m?1BB#K);rFp6iLp}5!CX*KVW6}q?~3ohuz;O zXAMh=+M*G~WSkjX)Znh`Qkz7kH@&;qh8vpgA_S%KrJ(x9VG#v&qW>5Q8DlaNyHx^CKAT+aW+Z521IrLsr}x~bSCBwe{7=^MGh+R_jU#csMM@?BR3U5 zc}u{A-OC0)@O{_&C17FnyPhjge=cx@*cy@-tPbG>=evi_7WU%aa4o+p zT3fRw!4m7*Yu+!imkccHEG5Yr^x}2KHi*HTh5{ZLHaG6~kk$~!GWreo*_en0Cv z6JB^$**L5XJjXY&I-l%k!f{|mG$S0kbwHA{n;O0#g1Rcc#c?))+0?VXI8g-K#narB z>*5y(k7~}XpFm1B#Blly;XWt4M*>CYRAk7kk4H!LS?ILIr*(9;?{IX-!S;wnin#d} z{>gbh=CHSfS&m3d1ZtfwVOB%VLZP-Hacl7?otuGdAHrt1wY;1~;tT|hoXL-#<5a`HC+ltx z0Q-X2^WWT?Vg|tV=OPQ3+aP<5_XD&05M?yISaLZfZf@o*FWy-B2^*ao9-^ku23}s< zx1PB^z1p?h_MSc%BSlF-rV7ye9?#j^MgW7UaU+0&#j*fskVA$>2GbnTH_D@nf3`1Yh_Z+%mONc|H2buV+)7Yc0nAo1TUW@81 z*DmqQ;|D05;665UAs?Sk#Aw_-pTY2bSb41Ul5xsPA-D$Wc~eC zA-uQW9!+Q-%Au(=LTy5e%0Ok5J*udkXEnFuMz_}crs zsSD=hN?{ay)lS_))rBiVZOy}%nyI_dwn}0(k#T@@IWwzX8=$S7mpew+=)lasu&?h> z8BSCd)Isk)s%o>?1cVnJ#qL zIQ&a#ROdYs#dTIMZ?CSuE2XtQ=8a+(0<=y)Zx7$Jbi|L*h2K*MPdh%D+%kUf&?{f+ zM3A{W>!nVvrGH5!6XfJUBXORya{!Akm985_chFs3Pf1gD7QM!(CAq;jS4cLf+-}5h zjC_=neJq3j2{-bJKKM!*My%j59wK&hsrPrkT~j4B*>37CV9>$$`a`dh%YYV31zvp} zO<;PoJDyh7vj{tHEsc`|^ei&6Iq%XM%uMQ>y~go;ebm3;)sjsS5q(N!#q&>CWP01c zHTgDlf#Telbb;$V?UagEhBdzQPppc7jgNpDZ{@0$3Lfu1^MC(%xAiYvB~y^x7T#p* zFGerXi?3l|{cW_IKGRWzI`4B7=SK@xPl2z@DE)dF`bPZW^{D(4O>`bjEDV%4$R#`R zX7#+7GnvySEW3JdTEMx!l9R=AMPTHLpx!+{`rd2_4`~69NAT)8@i|XvA=I?c=}Bqj zJKktmQ_>eqA+z^w=uA_EEh{a^#%g0K_dlOs!fPtzT--|Mzn9>C2z{WQz*A@o_N$-3 z`_IvNl%;JrYMGZUYsgl z8-3XZlYTSymaU48r&p{w4o29IN-o?w+70BIbl}e_PI~g-fY97%ClB}VKl^+HfY8s` z$s08`Q#u%PATc|vR%TGLG>W&6K{0nMh&3ren}6&Wurq`%H?CHz;wP}Mk9$6FXB#p0 zMp^!P2`4y9mB-N08a}m7$J2p7V+ixg|J<3LI}7gBnj&|-atP8H_aVz1I{stSR&g6A zI<{N%mXwBYNR&`F|MDkIbxH6b)x@{_t>|lTTmGO;Lh#XNtS4Xm7{8`Ai=+MoJW+i< z`9?BZ3BGpEq3tvNyNP)|QJm+PKXZL*DvI5m8TET#eOo{`2tB;b+Xhj>x9u6;0a&7O{LT27|hk|h;mj`HCjEC`MrHvq&&himV;+$UL_ zh!1mlDgWtJj%HGN3Sy(=;zpCiO%~t+7qTvcn~i3S!;1F?O-mF+*E#c#uR2Pdl^DW$fl)qvjhZZ1wTm%M)4?N_Ke>C<|H=T*4?t6S@592ud zGgU2TzgVdB&$b;mi-At_);He@_KIF4ZQyd^Ze3+NK)Z|lmHvw#)P%g{z9*9*|7pEW z;lEL=^*#%(G+cjb0oGATU|CbFVw#bksmDUj3tBYe;B$<(Q!kF=n|aiXJ(U1X9L|rK zPbz^(6bo;?&ysyrg1ngtuQvNI;LS6SU|#I9>{^)BC!n(pUBF6kmPcTEtuKxBb94QC z=qNkyQx)gIxxGsdc$I1 zY@(NjqQ_;?X?S(Ane7QcCn7mv$|j^0hy{%)XAouXi9)LN`fMq^i{^gsVYYtB=*&gK z0`6-Xa9k6F#3y%rbWaeZ7-dj8$mJXZUjg_t+Q;*qFf zx8|!0f;_A5oE>3LIHT1C3ZzB*tM#({ns|vqBuc46Br?_c?2rH*^|BQ|7(4nG>_FU_V#|o{eV-LCC?!MErrJnMYm#&u=?tzTPUO>19xgl(^uvE_-26W3 zX4c_ydHILOH-RpicvP=dS^zMheoGwE@Em`}6k;HUvX36-^J(r!u^--bODr11eGieS z4S#e<)lE&y2Pd4Y_YVm9Y;y{BcB`Eyi#UELG6v&BZf0y=!d1*Lrv1wemU|f8g6M1b z{l7kA)-pI_b;gMQPgUOm)N~U(s-FcB1Vsg@5kV0IB3)V#Q4tVO1d-l*lU@>nf`D|C zF1-fn9VsDFLk~!=K>~ypI)Nl4dHKHg-hbYkotxX4YkN2M+uOVS?QVNZI?iEurh|^h z-P2wC=2xKZpuPg~4ib2lnq4{YkoCuXYg@veB5+bN)~&OT)kBP5yydLu==zOrm?Ui( zY0*8jX+{!puhREE99C#@5p_)yB+Dxvy|nt1+5L#)n*rD3$4o(5Cp_Pbj=#Q!bs;69 z4sBddRNliFCn}fRd#L<+*3$ju?p^yV?VD<{@7w8`;CFj6GV+nBCB`Dr1`l!t@~gCU z0$%=&>P5n4QcpaHva$LaK55p3?H`Alk8R@$7Qfeu*<&z1p95hAW(x^~B zKidDM{Poq6e-Ptip2RoaK(XPElRRium8M};74OQpm*9FZAa}VtY2(ZJh(ZD0)fspR zm^*fO@yXo{-#bMJ) zQV9)qw>$ZVX&{c(LAw$Y{Sr6J)LCy$yD32$G<{2~SUBY{nsOCyvfsGfdB`o8wMsB> zofu5T?Bi}V83*M)3S(jxSZKCf*YK5X)@mBY0y1UyN8=4t*%>&;K1c}kdxM5)iKE|} zCT~9i$ySi9V_(7f&RBI(l4i}`l*gEBnM(Y2){`$}55qT^H#8ECk{HJbDw#@y1!_~F znHgU-b*O_+i-I_uyvAe&4LxE9tA5iJWu$Rs*84ndZsMNsPV?G|z0jZBo3h!QJmwu! zk9y&qxhV(3mU>WL6?&Oi4FQDyo6Sa6+hDSNAO%{o1>r7qx)0(If54*gYybVa7vmPD z%ov+L>Sa7dbCzNkp;6D)>6QG1W{oIZF*f?e!-SAePn%a$p&0l>O6A~L%N6O)Z4q?(;b}PDBYzd<KL26?;V>{q@zLcmRb;)&L-*Y%xCq!X42ZAKV<)0^Fa={#)Z7# z4lJSr91PYoSq-eN8*oxtv7V+Z9dCLf29s@8#;TL*Qx2GaFr_%zoNVuiJ|`emRgUA7 zDhr87>@^$$B3Va07=1%RPH{R?Pg_T8@FlZKP@`XVO3!fsK+L2Y^~@@!>{{j}dG`fK zZ@4d3MQcOh@W#mI6FVc(l*1a%0jj0a)O<3te{pn%68WJSaa}mQOB|tirRo06Kp$Hy z4^W*&{5OM#`_7eTZH&*}3#Qd7*-F}`Ea}d*ztZD^*|9^}{$@;kYv-A`_GmW0|AJK1 z20KS|iuM&-AyG}O`lPqzVj3$wyFK&l<42=+tx4uZmZ+t(ML@`pw#0ma*r_Y_i$XHY z=7W1VMb~5zGNl{p%9{0>5-r`S4WmW(hP4(`=+|b(7e8K+g?P0MtA?Pu;nfA}H{kYr0(1?K$n^)=FfDd*r4+005GS$zs;t zin;Kpkqg{*y!EAz=}iL)vCjbmzuXPCSsB-9D9g7$|Hun@HZM-T|OGsDgI} zGA2bQA7ou|B&xg_3-QbXyLh@hqt*9yd1tn0L_O7A9mkqZz(FU{YabqLFtGst$uz>d zPd2T-zPxov05((`&2d<6O&!KavAVv_d^2Ap=h|QJ`wq7Zfup8+jn^C6iLFk~M1SHm z9Bo|N*K9QYDz-XpRgTb<(TD~Zct&iWY~Ojv+mk5a`Xg|Sw_fSkKi_6m*SiwUx>|O= z9xCfnCR;jL3FdTys?ewkPClmnk$gOt7dZW@Ry&>Mj@Z+UR0ZZNRdONwxLNf%Y-OuD zmPzYz_NDl851bwvmIt|+Tg}4zBwy8BmK2n2d$;!VUad5~ljzyue%2932rT(+B#iV85?VgPEV8eqmWwcWmxkzQTm+ZtLr#dkP3pX|3b2FbvMWUcEQWzoKF#KU|xkj%8yu1&%R z@v-0ch|0MxZ0XIsnitvs~6&h)}JB|4Y^C%o$qfH_(j8*!c=gBdY)N z^uG#umW)RD!D%*$D>vb@94J+mdnS+EQsnz!g{b?Jo{P3+`g&RtkmX-BwV5=8F~$La zZO3a4`&$ha&n$nyx}3eAbWey2i%qYYNLb4>(*rpRffR;qGVBpD52Ck62{HN&<`09$ zBe?%ZIuX9A`8}-@Omv4Kqnp-ajc$j&EShum)cR$ffNhA^9gZ}%nAdNa59+9R;T~hK zAD4}U`b}sw{lY4OyeB?`Cs&rUK(4#`JVa{`(Vgbj9ggXQLN$?l62I^?g~#@>^IMVS zRDR(glxP#gcVTC<*)>kdz9J5-cF971LwjuIJ&q^{ek zeevSn=tEVv`AJmaQsDdTFP8e z?ed{v`eDejSFU3*x7M!oT!LBi3(T%XnHPL~8t<4c8wu}lMN?2cgK);{}5d&<2pOD*dD!+W-^I7{`G z8e0r6Io>V?F@hy0!rPKZWFOItl21)V3OBQqL+ zm}CcS>dt2kaq$Slo29Ah!dF%Zf5!)O)5IX?rt7~6SMi}VuE(G4fzz+%XHK8J_Nojk}oUl9$@ zCD+8gd?;`6%7$DMn-Z8YK^j%f-)IG-dt!g#2cYR;0ep<3wC-P%Yyj7ADS?vDX6RLf zwo<(HgX27%wo=&E)9Y&w)5^Am$9m*8><^6n1JXlCp99~@(1yx>v zVRN~rHN91C>K}JqaClmj; zIsou-n__0AsNsOuBw+Tl`ljr}d?e%yqq zp5ks}O{{jHmWx@Xj(s>-^xBG+xkQmhH`MGqjFn43S;pZtV{d2k;3Wr(KUPg} zatQD7io?<3L4-awAHwJj>Q_~vA(CD+BwvJh*tiYRmEF>GM3EGHo>gh-4mWD51bv^h zMaf`6v6GXC|1#jNrX6j{K5kk;-)EW@(p}FMiBsu@lWuzhg~sUamO~~S$s3w&%c`o52&Y<|Nl#yDGB&?mkgcKdO$nIV4wjw% zR&D-<*rGfPrX$$HxtwQB`@=y3#Sp@O%9zhUe4U;Bpl+bJ=N&BqH1>u-=Ww+}u@q(ZQzPVrI}0{PjrQmGcE`#c-T6SuVU|3>7^T-Tl6#fB72d?O@?>zA#9|HX>%?2^Hf;WN7le`-(Q_mI& zzK{XGIsR3q4hb-Sn25un_b%t8Ozm^4HRXUmlnWGfS+k{}wIPoJs9~(wc8Y_5plb}$ zt?R)2F{l4t)E7GTmnn>qQ#xvQviI%%kM$G|MLO55Y`RAnFnokY1p@5>IvCQgjj?t! z;5Xk84yt}G?Z6i)qNrs0Sex<+xb>ptyEpvuKEE?PY4Xl5gXzaVnK6M|p&}VwodDz5 zuu6{SAsU@xPv`RH_UF>GC<#QF3R92MD&;v=&}>CwHSxH%;gNUTCOZtXH8tv@7n|t1 zy6fS5ef8#Q0)9}yQQ!~LAIi16>wZypmptTx@OK0psYPTX@D4f=k%X923i9L$KXj|J zxu;;`DIZH6I8^=U?q<8(#X3#r-=|PJh-nP2bw zC<~U#`Nu`(ZEp9N)mj`wEfU9Gu(aB^L|7dDMG|lvXQy3urp_t*YE3M07S}X2h)P{? zL66#VZoThScNc8ekBk!Q2NsIGF}}sNxugSm<9dh8pNe!+L;S`{?UnLJ2lij>g?$Iv zyeIM%DPFl4wa^ZVvq+ldeoc~s#-yQB=tZaapVUV8PevLqoa(*!BO||}YI>%0cB+qy zvEBH@m%|JB5%Aul%}fyf_W#RWPXF5lWfrH#rnZL8fPe?4mwa)||TI%&$55 z@|;5;l_9_m6y=4m`Z?73)A6FmYey>!p{Lo^r#p`nv{ltXo{9!5AEgw;09+1V8!NVD z_l0eChl?Wy7o%acSd8hxKEm!#=JHmYDb;GzPrmGnptHk!gY)I#iyNTPaI%Y0^UQapV1_5esN%ai|11!`a7@d`=(?$N6s ztSZ=c&&BtF*Y^j1D!hGNW+rDdag$tUg{x18r`? zqH~1G&Gb~v<)2oon9DM2`9p(ZnYE-C|MUHs(vqE8&-~B8oXfrb9(BlpsNEi+C_Y6} zl;&PSb&o`Ehy~}|V`ODU!Z&v{Of>sKtCs3YzrTweLrYcYUXZl!?)n**g*r^^*s9V` zD5!y1Hm`z{(E`S_1iiRnD=JU*u3#GDNG8`v+ibhdKXT+dG#yuzz-MOF%%7q~GScj6?TW?XP+ zt-o9kpTNJLGjiF*TdJ0T-USvBUmvG!)`nG7H)JS2 zieCWOOmX-V8T*6k#p6m}uwRD&?Nr~i7tn#%{y2Nbe{dck@&Woz6z55O} zB$o7Wc$74o;Nr<0 zOpcBncwNe#;((|mx2^kRT3J`pkl1Q(E)+DkemY=Qbto%vyfs3!0u3A@yz)_2kfkf5 z)ZXM=PDm>wnUg>6hf+(Cm!Noc%qPYeh>QBS8z>ZIJNB`6ysU|bNvG}+{shi7ILt2?+myB z(pturv?OE2^VsL+0F7)K1m9kII?z`&5E_Ht#wtK}zeB&AO>F?Q^H1#`cGRn?@ zGo>fgohfa18YV7{@qKmrYz=T{lIY<3ggkupbCjBdyX8XNwI5MIb=RJU>4w?KkjIj} zVSk39&q#AK-S6K(-Pob}G^2r#8E;6Q9L&ZmcDdr$yR8zJF(US(?t3Gh_snW*yh zKI&Ge7>_nzlf+KMy#&bGe8HFfYwqz)qxJj377F1pyZDoi3hj=orqfYs(@^QbnM_pG z^#a=f-zJa69wkOAS#kZ6)$6?7<<*2whud_YW}eXPPCi?Z^R_$F_Wy91t6!j{C-ciF z^RtfiMx>txzXhZxKPjRp(J1-Qr>1Ds%Sj*>U7;%50X{LZ@cw)F=`y{q)7=Wh`uFv6 zgKVrXG3TbxfTe-mBH{H!J3_)x-XfjMRwprRe5#hdA4DnHOQ;&!@2Wz6_pzSEBvf5! ztuotxEtlM`{l}yHtA%U%;C{arzFf@L&jF>@@pA5Q_+P^-H@T;Ms=Vv;!NeBa$j+=P z;a;s^!H7FP~rx!uxIVI$%|4LZgGBBt@L`ob+h(3T#Xl_!ItIzP!di z#bASN!ZgpN+@}tLeR|fC2uuWKnC7N)x!A?ZPsF;D6E_(q*yI53hK*D3e6w-(N_mHk zv2?Z|nF`{w^te1MV&koVCUjmOJ_?tRzji(&1pgVm-u5xz1$NH6%>+Bg zDJnlMvza||i$X8AGwL1}3-+4N$MA5UJmD!GY}6&)z^T>&MxoFDH^R%jPPy7h4LK~@ znP*vLSY>Dgl-bL>bAfrWNc<~}==IVb0m$R9%cJHOHJ<`*0bbiP)B}pp#Sydc;K;?%NltC;rVx=pVGrvs5>Q@4{c(lA&By;g@P@Mx45*?8`4uLtfj z5@UmCv_y&RpPq>ShN|F~(ERv6PpKnHoH?(Zfow-WYi7#lpvV_k=wSgBuT1%L_WAMa zfX5L8y#u=2e0zY?IEN#^idhx<>*qeiYqPU(vL#}Acl)HX$mJ~TUmS=ByW_tWH%y>U z%r*^os57L@eN79SPQGlhK(t=vL0kJyPUS91Nc+f1{zyLY7-`Z5eAqO)xW3EDi}+Cr zUv!BlUr@I|e9;MORl4XW7X?e1B?|l{KbZo5hAsW{Vp6!@mcru|Ll=m|R_r!z;fZ$< zQ$L(9Y+bVfc#(8Z9Nh9scqejlg{^IX5SU z-4|HJ#SZz^)|lZrH!AYj)P3;*_GfncJG7U=9_N&u`TJ*nebW zC3JEV*eEp$o!0SKNf!XsgmsfSLOdpLr zZucMfXR%Ia6AoJ}ICBlKwp^s7}df*jrR4zN$tF*!e+vZ>Y zhT#qrzOeI2zDVm-_#?7rIno~~!F1X8H}}VIKcv^W`F&q zlHR}be;~Ezw>R!Sh#^}_=s})5ZK(Xz$djm^H2q8e_CPl;#(l@h^!7Zx|A~aJ8Z`WD zxEOl=KRP@@FtLKPDt5Z_KeuiH>NfkaT0XlWvnkN+&NtX9+Hp$;2_)c;M}k}@eUlGD zpM!fG&@|>Jhod|PcQ~jx0P*{T@CD!A-LVJE8?&R&TZSA^_hW6 zrk8?^Ew8hE(}Yw{8&*9Nvw7AQle~8biG3H??}p@VeLmadMP4~@%3rNzH;VRzOZ*r;T*Fq;`Y@CS8t|GnVa$*-CcCx#L_gdQongECH^n) z@&TW6l+J#iy6o+nt%%(SB`i;|f?Y z`Ju8-aEplst_)aIXOk? z4qSl?C)WlojNqeIpsHqZBAhRvz1lR6d~$09u?cJ^K{o(kwM;}xqVsXS&pORBD<=Ln zeiTSr^50YVa$)Qj!rrJ=o{5nYDMfTm!Ne<1P5Jd5(ru?mXORCiPx3Ao;T1Y1``H!N zp+QS+r1G{CHx8V=PU;gTgJTmj;v&Lbfv-YL30Ye+IGwuV5$B7ryr2-X?;}OkUu4T{ z?DucMQ7zrB7B9MEaSfgmbJ>2gajgym{v<;`QU+}6MY=%iA}X`7F|@I?a8a$YvAoc9 zFK-9}XM-;$CkM38ZMH&oXCJAbG&U734h)0m{Rshf87FTv(qB5R+(8QtP9?N@!%5`E zgZGlCzj9888OJYeKo;TZn`bf`X9r#tC++#s_*ZeB6A_26l@Jhe*x%uJWK9vU_3STfgEK zt{%?kr7d)ln34}HyqlsklA^O%&MheY0pr6T{q@wjF16fpxReJef`CWP$Xp zbr@+Gx&te1exx!-DGu8m5*yfO>NBkaAobmvIrV{OU(mt3s!9EMF#NEY&W@G-4{ z6H@b7#p_jFZB;m$=qy@GtC_kzxq|>BaU=PZ4b>Qf*rHUM?k>yZlG31* z{Zl_y6OmQZPUfn?FH22~Rg7jbN)PA}!g3$ptM{t7-*PvI>H9ihD|UykoL_x>hg)tO^j9$5KsCMSP3ug~QTP=n*;`J+>+P{2TNh;N{4*Cqu0Wc64 zjxLa&D%oOX(i)8+jKM*ItA8@5Y!|;9n+UF0vLcl|#AsP$<_I&b-d%mR{fkyEJ+lmd z&lCS`zGB&7wxTegGyLBe=ahakFK$&f(M>+A4lAc|5$L!t(V0eExlbku6dGv{u=i`zU?N2 zTgxe;Q{tb1O9R`}=adxX+U$AK2rD|N)VtXtN}8=NY49FXy3^+N;y=9Mj0~yf+rA>- z5i2?g&0JzQ{iluAIBHTbW|xFm68*)n6Wl_}=EC7wd#a~=XK&dkuMSI*+atS%5#zS0 zUeMmjjxFEJS6cGxb@DfHpT;KnXDwh0-|SIxE`fP37QiexLEuz)8`pjtqXl;W=6?`5B$vf+>=L27C!;{}Toeoza`L zJ!H7TZUAACDixPfdE$n3IoetcXt?d@$&7aU%U=37urk!HV9lQnXr{gUNnI3ujD{#~ zB>18C(T0^f65trI;hEdr`kX>PJ&(nPbNK*A=UdLvi8JXc1?KNM1txqh`uJ|TB<<^V zr~ZA@)1b>+d z-<~bSc@IUap?&wJtd#;xdvd^EBu{E5N$K3Vb5yF|`RGKo*SC~!g`unZgrb~l)<0dn ztU3QRVDHc1_|x!>`!8f}F1-oZd(3t*#PXHyGfRaZsX1A2^WR-j*D-20Z(>+PpSuNo z_2`UGZ>tU z>pur&6OK_Gd73ZH_;8^rA@n1MFLSgOv?ZeVrPw(+<$1A0hwc|QBr*L84c~eqq)I*( z-E}vKOttE>e0VS6*pxd zc;`0S^_Nq@_D%Fdc(wMp2bX3BER=T8&|lDSxfeImKfaM} zQZH!?&e!q{GJf%8Ci$_Gksxo9>jUBM71kS}Mr@{p&^j`MK76`k=8AFiseoqFt>tw_ z`HOl#O(_gQ(n~)==FVq5Hy1f3^LO)3?Nk{(DUWxPdZU$+y_kuN(AYd>Msv7s!b6mL z)8NH@<8`m!$u=2+?uBPjGY)ez4m?YLhCKWZd}n6Y_t`P$rfNw=zJTxVa}~pFBx9pk z2|dGIgG}D3aYmC3){x_Qd_+n2_eqi81?E+sF+MKem!g5HC$V?ft#bUGo<6RUV9t4`c{QS-P_}=R_}IG{Dsp}%r2S!5 zHtNCH)!JW5Uiq*Cq2aEP+xMkN#X~|apZkkdPuT@n80$PA4ON@5;HrWV7f~DRLa WRD[2].DATAIN Din[2] => Bank[2].DATAIN Din[2] => Equal14.IN6 Din[2] => Equal15.IN3 -Din[2] => Equal17.IN1 +Din[2] => Equal16.IN1 Din[3] => CmdUFMErase.DATAB Din[3] => WRD[3].DATAIN Din[3] => Bank[3].DATAIN Din[3] => Equal14.IN5 Din[3] => Equal15.IN2 -Din[3] => Equal17.IN0 +Din[3] => Equal16.IN0 Din[4] => WRD[4].DATAIN Din[4] => Bank[4].DATAIN Din[4] => Equal14.IN4 Din[4] => Equal15.IN6 -Din[4] => Equal16.IN3 +Din[4] => Equal17.IN3 Din[4] => Equal18.IN0 Din[4] => Equal19.IN3 Din[5] => WRD[5].DATAIN Din[5] => Bank[5].DATAIN Din[5] => Equal14.IN3 Din[5] => Equal15.IN1 -Din[5] => Equal16.IN2 +Din[5] => Equal17.IN2 Din[5] => Equal18.IN3 Din[5] => Equal19.IN0 Din[6] => RA11.IN1 @@ -114,14 +114,14 @@ Din[6] => WRD[6].DATAIN Din[6] => Bank[6].DATAIN Din[6] => Equal14.IN1 Din[6] => Equal15.IN5 -Din[6] => Equal16.IN1 +Din[6] => Equal17.IN1 Din[6] => Equal18.IN2 Din[6] => Equal19.IN2 Din[7] => WRD[7].DATAIN Din[7] => Bank[7].DATAIN Din[7] => Equal14.IN0 Din[7] => Equal15.IN0 -Din[7] => Equal16.IN0 +Din[7] => Equal17.IN0 Din[7] => Equal18.IN1 Din[7] => Equal19.IN1 Dout[0] << Dout[0].DB_MAX_OUTPUT_PORT_TYPE diff --git a/CPLD/MAXV/db/RAM2GS.hif b/CPLD/MAXV/db/RAM2GS.hif index 53614c0c3bd33d6a100f31f5df66c211c2af79f7..75bab6408d4c2f4667903f87ccabab791a6a59cd 100644 GIT binary patch literal 595 zcmV-Z0<8V44*>uG0001Zob6IgkDD+My<6&ku(X%_ptgth)C!Qzo3ZE3y!WN%MOByhu8=999TcU^GpyNTZA|dTS|$-T zErN-CP3biynvKKHcqJ>qP9!Upiwue;#59n(Fli?qN48J7rZ#(J6;`2JQ}qTCyNI0{>1L~)9M_S@cPJQ;0i-l$?Al*i?#YG ztGwU`K+(PlW^1|($M3ZdW0A!J$Q4fVgA^>kZ@b2iXtv$>OeL|vnfpu6-MD?%PbyXL z5?BdYsYdhwZKb>}1h7~pfa*9MKOk;tVh=`S5grrD_of9?4wktW5uL=kj;89E%ql1{ zp1f35Eitz(He0d9%=5P!wsP0*rWmSz z7Cfbga-7N-5g-ONb&VU`7Q&=9HBHJ5N@1!`Y|Z+GHJSn4Zw4?X^7LNqv)?jP?~Gyp zkPH8iKkc7J5seCkH&HI?RFNv1gRGAAzUe2|i2Ecu??);B*1FAz?5Uw!W@Ov3sS{1u hGzQJ4wrNa>5&ctcd+V3xr;@kENT34r?mOCG9_-#$E_(m~ literal 595 zcmV-Z0<8V44*>uG0001Zob8lLkDD+MfbW+2A1v*qJtS)!o_kBvBukaR7Lr^oV}`^M zk1dZ?SIhqQ8c26n3Tk_3Pp!bRnHhT?-{3C|FYBhlccsh#9iXgakz>u7YEyzgHZqN| zX%S4EYf7&v(HtCp#v54!UdFOkwn(SQAf}G|)#`P4{i{~11M8*@JU~hjIX{OW+%jcx zxE*GKCKDXiDin2gRPyo>-|_lX;mM@aEc19&KI}N$e%hSX65ejPR9s=mYgs>{{c5W| zs=6ro5l|ep!F)^C;q<-sVJh-uL~@1G;wS|x?z^n<6PoXLK2t_4ST6jv=kDAg>t|&u zcm=G2yiz54fX-9Vlmb{HQ$S6UO&<`qG!cOwTZAWs^2oHn=3tqTh^djxX2@3CWL`s= z^YqoLN{P9hv-yUt=AOUbv5mWRcYU#kkd~pp4;D)n-p&KpTffm<20O_83%R@Y{9wrr z%fQ|E>lcp;-wSuaez6PtQ-7#?@!V6P`2O8F9)l3_V&M7Ss1Y?tU$2t{1xcJbOivx0 z8#S2BtGZWbT$F{X=hp^u0jS3qzrq|yjq@ZIJjtKt*%mp(rINRCA(~7DRkcT1pPHyG zc}9;_EAG?yyq;wIo1z~Zre)fOuxukrG)E_f4w|m3R)`{7nDif}-~JBru042Kt6z!b zs{Cwbm*f2D1%LYgfBx%4Gsueau`iFxap?SMCKE(}=+vBPT<4BZeeO`xq+F*I?3v+c h)-P^@c7*%Qh>VFMyI1S{=l4fvl|l{Z-FMD#A3GGVSTQNa#zIkV=x;e?l4WV+KV`yG@Desmw9TLem1pdr_RV~? zDo;vl&}f)LP}h!J@mSaTLs6TGyG*M%a~fykDyObsOPMC2z!ifS(0v||=Qn-0?kALg z^A_0UZz_~?$baZ|A^5;M9sl5ycbMlVEZkL>k(ud}x>mJlWo1-#@7u&(5s$^ zx|rcAm5i;-tFwD?hF!Rya=PH`KMgXD?7rdb515>#Z{lA5kuXSA;W_XX1K;2zM^9r` z#fv$g=bv%mS##~nPv^IvP4?Y;7d5d>-(R8agv*A6$aBgZV57>nRa|IXSpLds|7V>4L(czs$Ny2s|35t<9oz;sb*uPY7_Jc|8!GGc zOKn;6AM*%!@!yN{pZ^H(M+O@>ey{fD*XBjyoH|1ec<7q>ap}JjRCh`*fTvg8Dfyh; zN@?f2T7eo=xn};+b|x}8%IoPJ>8LC19joLzQn6I1 z#ks3OsIGbzh1o-h03tGT@cXxk@;es=4=K+e-;QoFwCa8zzG@XJHKlorw+Fm!?9vl! z*KNb3l7ZEOw2f3R(#G9?3iPV|vDM**GpW7KTW9QXs1fuu1^M2}U#6FJ#^lnQju@0s z@mv!V{Xu5bJx`z$=MwUliQS`Ywf4c@&y}=6U>M#cHV!@|~nd;d{OVEP|)Z!%ybnAAPV=nB*o(3o%OKLoD z)YS(y9Gw@=vVi!-ZT@WZJHv;+UA@b2*jXv`alk95Y5ASWBLW{A7jrwx(C8dFi_3<^lM^Un!fWOg{b`z3+P3a?W27CYi^M%piVcB_PP$69;&p(LSGD44qph8g|^Yv1a;vR0KMCT}}X@ zf3Cke(VG8KwN}7?m8}0sn7}|%_?v-bm_o!`hMwY+O^!Ha_%O_8^;`dKR)rt_H6 zKgzt}g-AGo+aNZPT`)8S6fVh?B6;Kfru>XCfGlX(3Xs)(jSbKMMZ08y!|8s=dFR)+_e;ztk^?U}u|)H+QRaRO=j}mu8|;D?LH&SP zv5tapStrW8iD7&>R5yHTD4=q^8K$d4Vh@_AsdiaxCM&s zDTlRREtg#kbr&T1Ef2s^O>*PKb~oQAue3bHj;@%vYR?;n{r9SKpy3&X&FfVY1zt|e z_)JgnlhmGmXuR8-(es``yFJZq7BN0D?xh*WWo{g!hxxEgm-0W?^$S?%ako_W>&kz_ zT_sKf%2zznK?eYV{NPox5Ih?b;2Xi12o$Rmb{-F~>etj4vP&^641X1Mi60ER{XT_l zWj>M{(pl%P8Q*MjxX-jW>T8^L%`c`~(i~C@x6D+w5m_}zZ%y^?`+c0CX7dLpGz%X$Pqi$R{seTJ zy0|zsQD}r*Tv}J*SDwF@!S?A&+(^^JDmN=6N@_NbeBun60ueS7)y2(IDVg&7vd*Qi zit~amE8k@NSKN6p$q9!4XWHrn~-6v5P72U=$ zhrU)fTzrm(P4<7s{IQchX}w*>E@Gw}b*xl~=-5}`Z@wbhCoX>d$JHf=;%nMhEq;Z3 zqRzF)7aB81YEWtfXK1L&{_Y>0x)C)jnQx)OQ~628pl=u{w0+k!SER`2C=Y$qB%od> zzaoy8uMWVyk~~~(>wk?e?*4m84mUHwknrsnd0}scxo|EzPW4FlA{03mG}BabfPd6w zYL+p_iM=Kkwy2DTnn}>_@oY-GFe`&j0I_sgc0V!)%VzAQ=dK}O1HGD5K6@m zv5B-q8bNt-anf1T31)jfXDTk|9+KII*rTKpAvcH3{W0NBTh<8I268^#x31lZ3F*Z* z$3~PJ0t6mGp@01+t^simSywm0s9uV~E#$iFU1L7ic0-Pm{R+Jl0-4MlXfHZ1Sd*FB z&vE6#G)3k1twUA_#9D7650WoYWOQYgA@uyJ0;dp&e8=TEQjVDMTePCcw60u%w*n0 zE8gVhbYt--D_<5fRtI6lqkx25Tn#=3X@Pv@zr10dI?86Ew!AEnJBWx$L_0%xmc5NG zjM`r4{>kc&jv>j5EBkjHWjn%dbQy-l^=0h@tQ9Jm=oH5Rk))U;U_U>c&CF5%QU{NR z{z5*}5`TlW!D(YM=U>!do9t7e=Ex`f=G_X<6^bMb|8!89HUvk!&mafwC1`a!*Y1kHR`|k8bIMD%Fh~GP5i1ND{BLPQO zE>bE@Bi4Ps)ARML$w<#o!(G4$Uh8O7>_;hDe7AFqf;2_MkV9Q%NG{3M9*T$|h0~4p zFYBAMNr8{RQRTQxK8W(QT)fxosFq zUJF?;pt0~ESfN`Ja%uhUKb5IF5M2Cq!y|&~>wllJF-aQ!lK03rS26{Mat!yHc|jGl z=5ae9$N zn=7@NUvmaeyD<<8)uNCRHw>=OF@;)hfaj*$tZxAQN$aBKzm#lLI)4WJN0fINdgUK5 zFU$~UU4$&^r(2C*2Yq2qeq6j5bw(ZM9bnxzw{P-VjEd}a+H%LTHCj|Lyon>}3S6zY zNT}J=2YV7p!)$iH|6OBC@E$bxMVACY_3>w)U!}7)JPZwrP=6}hr)(t|ZrK1h5HO-_ z8u#rS32YqvpmlBwuT=K>PG@a?*jb|y#jQ+#HU>G4t`Fx@@B5zy0b-ON$c0kIUo9<0 z>*&OV*yDAt>3+wyJjT+|`R?uRd2Ka?>*qJ$Ss;A%;p8~XLRsaw*1Klsv`?kvx97>~ zz59wMNO0(DNhtH<(|bzd7!W4=tkLE=~&y3=B^)Ijxkd;0avuxm&ayd}BEr99xZ=zF)O z84yWj28_FkfsINw;PxkD%Qsx}y7rw_u~wMO<)elZ-Q$U5)6xzqPP!8gUBoi$x64G7 zfAlvLg%`iv)IM9xuh^y~wJ_|0^v@6OYH{f@0h6%SD}lP44avE2Wmq;R`v4Di2BD!) z=DG0!Lt9W%==RZ)#!!(yl7-ltLlMOB;3-H1oFk&2F$msRN|V2lyq`pnVKADn2=n!1 z-%kh)D5CiP zhInAGj(*`o+vN?uj&MK<5vXC1qi2Y(wGr~xWz~%kJhbgcA?}oCm#Fh<5gQ&sM7?Ub z2$4bzfCiq}9}^uP@|4CQ`!t>U#%3PjiZO@`47X&s2uVC5o-9xw)zp!KyJ{rKbqspC z3e0vb?`=55oBrEC>rat_llsfcORRMLm+E;16Gb`>gQ^jQy7AqFK)1$7wdCWWC-8?r zmEjA^#mFaC))@#rnXpTdm#c>Ssq&mHhW4(dUp;_YLeg0rK!D?F)ihb3uw{xaZ%|cY zc0Anwt6jUH(`WBnzqBUqT44`@=NSFUWq&X{vpwxV&U{05`O$rE6%P{%x3n@{fJ}k5 zXSIW%3kj^ks^IsCr%(8mCofFkY0+9g;UD%k=O?IdYiq8 zl8bf(9CGh3Y969uQ3GX|$%L)-MRc~@<0V5?S0BouTl{E>zSkxijyr~4&g}J-lqCGC z$|1tZOug|k7$!I#6fy7QG#fgNi$TJFPBJ5liO)oS)uP3vuzF)uFL|E444Oz$F1yC1O2XwuME zMV~$Eds+!yk6cC9Tt+K^{Liee2lss~8y_P~N^esM4g>!C?@Nj}gsGCG8H$RXoRv6Jss~cO|Qe@0TE~$Qj|XEv*F=Dz9Owx!_}sV ziQ#0~B`n1n9!-3e#hBYST9L)L{~&bV4FS&^Q;kmiSxc8lI0ke2#`E?4NDc-x=SG`zgMJVtd*6Zin3Jcnz~kaQ}h%&O;f~5to%*w!?oa zb&s4;(b!C*I|kr7|G%%F7+k4!!hEYJxLQO!V<^>@&l5Wliw@52pVcd}Zug z?TkWcsc8G*3`&WT$CdI&4Xsh}T-ViR2u0xq@TRDWE?3MMW)36rx&7jbL*(1lfA+tr zwmKzq%@($>=T@29)XaTOU@ZOmKcC8g8Su7IseQec?A|)AC&uu9zYGq1Bza~hE_(Dk z3XoYpkbR69(=uvHp2=y<^?Co!^J_5)$KWmiXpdC8wuO5REkJ$zg)KKt9w5;vEu2UI z2&fnYLkSrX4|oE3x}aqy2+GfJ)x$gYKlLMCT%4GmI4Xn-KMM^(qr|L_zCc^_P|zi~ z^Eu=?1eNwi(nI+Mul5Tf#{0&s&}YoRY09<3Grb(XDsZ1+y@<-;N0mzs+^WtSx=1hkFwOQz6@QBv?)fe{=MgSjY4MmZ_f{4I8F*TeK>e;#9v);*`K@SaN!$GPV-oteiWb zZg_#$*p+p>tWkI!Gwzk4HzI`d-dY@YIl(ZiTNr5)~_*2dA6i#F$_C&MeJ!Hhhrb(~l44#PGtukl(X6!X&RV95e~kFxz-bq^`J7 ztYC8>;*mn_yc5O&b^Y5RV{vw;-rAe2;Draz?NOHSi_W#xz0NbeY@HLe{48(YIOw#$8J-mdzK{BRC~N>No6eBGArX{u|jZ{qlc# z4>~T>LL1gIpKIX>CYjB!)~|!?jJe)}y8mC#WJsnap%A8#wZ)AUZcDWGDn1A? zc?PM3&4>EQ&=qBqKd2<2G-)Y1>_RgD9bdjKNMm6TtC>W-b~sXx{tU4QpOpByp%4XQ zRGJ_&6pqVTYUV381yVw$*vz&aTl>7hrzWHD4S=7eGTQBlZ1I(`Sk#-vjF{pV;a%y) zo$BP2zhJixEi6g8@8&9;n8(Y_yFUl^vEN|E{%9=q`)gnGZ6eAV$KmsH!l%wXb?%~a z{EGtuH!rZv=YrD}@KP!7JI%UMz8j`XQ0$f%^YeIKte_$YO=CRoxUHeOlN}F!sp{18 z-17<0_g~PkT8NE^iM9UQr#-H~Fetv1HDjvYn5p-R$6;hbE! zBUAdWtWi=Q=$d*rt5KBr%pCVXg;%ixpJq5P6o08UyR!1H<`*=u63hwpwsgu{92 zQ-|x?pm_6;9^E1$OULv&hG(R?69fi(p9S*NUUk5|=WhkLUR_vne!xP@J9`-fC!ine zxeN`#7L}fj;aQG`!2N8np{Obg$!;1QNxINZd%Y8|8r|IXa+LB9za75*4Wo>+JOAZF z%h$*jfN2#?o?D6YUJZUi+gW74I|)%FSiqel`U#Akvh&~eZ9;iC`Wb%|7KLOJ*>wEN zr=ogi5I=8ERR{fOp5SZ1+^;%R+_=5^F!XE_8xP9-evSR;&)VVxz%fNCJXyJ0Dd%!RYaP~av{!|gxfDBla>V|yrOqmv4lAZmi@PI(3 zQzUJZ+w=!DQ3MJhf{yg(Uhs?2F+^@=3N9dEm6eI=InO#Ie7w+%Pjad68ZWo1{pPp% zFUUU$a67$G0SUpL3)x-E40oK&pRETe4lTflHV`b9awxmlB2D^(!D@%ShOP! zw{~?9um{3*y|S0PUtXhVJtSdcVp2Iq>zE=@4`PW%_5}ErjI2|pO^DO?wkaIrV?GM?=R3PjNU9_2XK@(#$^cVAxNmC z)}xzBtj5eT%ZU9RUWkIG#ZkK+j)sZ+AMZSON2!VY)U0{l240B# z!VhVMOSlvQl6JP+GhI@bPZ(6R*w^8Q+|D_(a+;{@NurF z0HO*$3(_Sk3niAvUIr;RdfyvnDQOJo&b(3~qvf0Xqi%Hs~@7J7Po!9eKK zn0@q`UHdkOq08MRRg?JmZx0oS{;%-Zks%=m@A~ZuxaU9oLr0t^V{q47p zNOhtxbHS9sI&J&6t;a`l{bs?ItIl|Vx9xsZ=YajI;rz|#k#?!&0v#JeU9BU*tnB;k zbNZ4{Vp5w0nS&^s#|%4c;<0Z`7b3AUU%KS@$->2qQ?mQ1dVEATQ0vKe8FU0n&n}Aw zc3eFM9{)xX*PFR3M(N$B*HB5#c{_>aG{I0$TAEW6(Er%4C{hpKASXspRvg)b4m>>L zgZn~sHT1zEccsJ8E*->a0m+s>yErBNEBE!q-1W}yPp?L6?gh?6)uNu*fvTXgOQsXG z@MW(6iknkHRxB5(P^df>?rc*2Ro)Cak)d}G@X%K>D*oHqEN<^^jsxX!ny@=jTB{;m zv%c#M`pVG@=fmZ!3j>NasR~~avCS2F(V0M|M497#CRUeX09{ZncgeMXO=03>N4$|_gy*%$JWK{K zJG6~!Z3>^x?i^hoMPXrj#f#xFgmiLcCKBTZ&+Mgu_> zhZr-2DQ6XXYxb0*J;PFB_DZVdbL$-SG3bRIATKWD^0{6@XIrjIyTX>)DvKsj#W?TG z*JbG;J1>6yZo}^mWp4NOhjT=B(qosY33;od9b_S8j#&F^(YvNd39b6}+2n#b{~Qpe z%y-uTuJ5wUayW%|7~e0|CVJz@ZXkKvz)M_C)W+X~zKG+6CUe#l4PfgMFW#f_v!T*A z)Zx;zT|G$;EZzk~{E5sl%kg1n77xG2hjOmKLT(257-mYR5Vkwo9(cYd@H8}I>H8G- z^lFWqy;eWB(J#`^op(VmEthk0BcKYlc$~aQty5jrG6^Gr4VSLr4ip*CO(6=OKKwQ! z{{A5OyCZgh?`vr^mua6kaiOv0(hy+^v@k;ES>(K--*uPft?dtNz-FvM#)`ZJ&M_T) zQ&apmDnd2yCQF1ezW+}rUOGtsbfe_j(iY)t;3Kw^CKm-;`{x|Luj(2zt|?FNn{?7@ z?(++5j{XH(wF4`6+N7A8ta|o?_DIB)MNs}Bm!+Y^r?A5 z7dF;TfqMG9Sd+7FVw=uN8^4KhmiY%aK7mTa(N_Jjme{JZcF~M)BsI6c&v?Q{T4W(7 zVsRK#zRmJXJ-~VTLX&Cs)8g8uPrAN@)EOfaAB&?bjF)U)=oeScAd3T%S>C_ksgWTk zhML*TMJr6M-O;ipLJ%M`5|fk}J%cR1Wot=7S397v&ASGWmkzC@bSHfFGg0~lT++rb z-TwClK^|}UUCGs}YLe*h0hilaK#&afH{ z9U?)%`k3ifU1ffYqpi1rW4?W7B|0ND8#CfGC*<|SBy&_1zqHFam(oKN@h-v7ebqHs z+2Xer3nNa=D65C|g&!p*hpHvL=zH#G#M&P$y{(2h%y2m_EYkfjhgPm#34^VwIr0vh z8(bF8fsFW>WtgO!C;B|?S3XK*{gi?R{NV}lc9ufaDfcjIgYGAX$Me1PYhILpUS6Bo zS~=HoCivI1WtqTf2|f~Q8&vo#zeV44SSJu3*!t&raaU7YC0tq*KqGxcwF<9ac?UHl z5x{9P{!}}De^@;^z?BxSm1g&Px;w&=WClYyqq6#cF>CKLX+dbSeC;VmEHI^FBs@^ zsjYH*8-T5^eqn)s>NLXezw;c5;7?f|$MAxK zo?-;xmGmZ_CUXc1G0Wl|GSzeXx%yBKsW{Vnv1>j0(Qps%M#wYPf_lrtV$|07$&$O2 z$7F?uh?+jGCnu`^5UaM;qUe8zfWSCEZvTUt^B5}o6AD~Y#+}+@vbaq*4EfS9I>k;f$^h;=Vkeo4%H;mPeMQ-nrP!_}m=e~))|a1cc!b)k#!k@X;tp_;K%nr& zlLe!?w`0HiW&*>Qwsw?|JM_6`@r#ceEAr+a&2-0JjKx*MxORqYp3 zMX*_T?2OW%04=a7k_iuH&B^xm7M;i%XJ|5L^QR%z$9EH+_-($rhV$RxQRQo|8=C6; zKp;K{Jz^wBXzDEHAz8Er+BHziXC=sgi{exZDtzS1zklY{1#T(^{Of`DS%LWwQF4Tr z9$HBImCHf>V$Tups1Zesr?6a=UPMT3m1H*%SV+_rnaxe`+TuNH(uLB&?-IPtRdGg ziR~?K+)^#Qt?P#ORENq#wzBXM*?z=k-=`40c5Zeo-qNG#;_T|5v|p3+5}t!{f~!zb zKU?O5d{V2P{z&UuzD4DWeSRz7aM#7f;@9f}X_KpIUqRne>4QjLOCgfGlh7&7~v& zCy|K*Tg@Nlr&0beM6-IKrphYfVpFDDI~~;r1YLw(U&(Q&l4E!dUGTyAy1_`HHyIG0 zzGveY6biuvKh+XCD}0I~=t6|}C$f=u3nOPSX0R>ix3N{%y<*Z~3fsSQ52=y|ecsLx*zE4zo1{l>jZj_>iZxmJ7xbm)Ju zVcm-o_4-JPo)dJv8PHGMZx{1MI==`ay0K5T%B^~8YO-n!wTs?AjXh`>=T-20Cr@g_<{;*ja+Pa;*E_DP9pR2H{fq#{ewP9M z0Rcce4-8Nx5j9dKZ0o^1#o>QsSD&Ges%t#(N-{$hm?t-EihZOF)2KX1=Ru|=@*RJ4 zz2Y5RS{#{AuD?>}vmYpG2JjU#xjrlKX`UrA`s;Ld&q!vW9ho)hqpw9)`Ds=k6%zPW z7IaGM8Lyru{wPMaH7F97TN%2h6VJ*%#{kTE+vJee)N$N-k1>k;;4oH?ZvZwMuopiO zPJgpq&mx^%#c&%N#>kwKxAlvIVIrwH)`t&alF!B6jLj2$f@3x_co>f>OVV3ScfA**Qmk=Iqm^hDc3HN87AIlx)OMP&gyeqKPbkO4 zjmpMah3}TD(mVVX1pymNBNTTD0jQl1vym98kL+Wf4g8RV`HeT`pp?S`gj%fvgqu^o z!@b0Z#)_2+ET%VSwUaS$#$TpuZzmK-cEcd~7egOZ%W<%VEFg|5oo*@h!387$Sa#^r z@|$%RxZYk0boC_{7|2@{w7k5E_O@VaPc3n@2^mx3U$=Ayu-IdX)CjDY^|jD+wLTLj z&vmj{l|*3971}e*b&RL7V7mLE$ZVkGBd<_w8-(N zGoAwSzLVo(m@Xq$PLVKDL7>ku+BG>s^l7@3Tv1y=f?G&x*g)Zqe&jW7&A?GUGH^?& z6Om(f|Cku`RJh}^`*DsADC18nSjt_XWQaPgZd?k6tHo6X@VkBr)d9S+bl-oF*!B}z zwT}x`J`{m#cT&m)UNTaXSe=-X#KBK-j4iggPMw&uo%Z8%y>eXqVu_PEb1?&Vz$o8I zXb^=9I8$jAZve;s*Ow>E0lqA~D%RI^DlZ7q{B24M@I({8+-z}+m=qo`3?(AK=WxmZVXE4x zUR%>#An5ux_!5-=n-bz`-u(J1C&du4SP^c-R~8EGW0U+hirh)SIjy}a3k_bL)sz%PTC_&G#l3Fq~IF}Ue3B;2X2wq?3`psF}fSW`6oyVZ6cCk za*>RPox|a)VvX;9$HEm2;}BPMaY}ITsY%RDQ>Y{_bp6BFi~VNV-FS`D5LXwapOwqX z?ty>bK*Q&WncKm)OcIksq9lxK$x=h_mlt1gZahKmd&3Uvh>TP}LGQOfnzdEgzpdA? zeW5)2p+`kh6$&oFF$3%z{GrYp!T2VO)WIoU?9QOWj0;iZ&a$H}R&Sd=^b zIzl9?SLeA|Y^v{`D*6b=_?%`J`<*A-1O5vq>#=UGP$6jg8BgR?2Y)5+w>X6u`S~4B z=X_5e$m(h|`e%ivapC>$5U%2aksB(GZ!u$q#XqKg0mYW>C}&pN=#mt9erNPK=sEO2a(^Jc4;cByJtiQ2x}_%>DykJJ0wT!z}pDZI_NL2GB9>9O=pKINqQP$+}GIE4;H zJg0zhtETy(A8I#4zLl!=Yyjz1bXHxy>W(_TR!L3FJ_WDMw5!}f|9KF4 zHrXZhBcw)o9@*Fa{TkLX0@L}y?od$FY*4wJrHycFBq1SUK668M{pYE zFOM7)xB~mT&Fm(9fURHog^LyE6|F~&w$;{uLK3xuX|S2GLvh>mUfqsaZjEZseuprt zdfs!bdpRrEE4AT?3i85(c3*#ZDy{r*Wms;?@q`xrcQDTSlx|l7(I+F~k*+>vg2);9)Ncv$WO1iJw4l@ngU2J+#cayftz1B(>RjwMit7^dJ}zwacK7)`VeiC@`4TJUL8J-=Eekhy_+^E7qOT-p1kYSd@Qq@_5~|!_o*n=>fMa!zgGHt73_KYhM1k22+x=_(`U{4{Uovg}&>Q_uK`@CaBPBg9cl6i?F)}=% zNAcj;ReFA0;OPre0u(SRVNdO`gH~B$#1;ff}ssa8v2j>D?xImPB#AA=jq5 zc0eSk$--Z)8EHhN?yHL47rB|9MOAF7AhLb1{A`JR8qIr`*rk|aqx9SR;q*)Qh`J8M ze$;8vrF}D0@uAZREPp2g(d;@T>!BU%{hE{vK(@Yy$Sf<xjnoo} zm>^V?iQKNH!B3X|DW;N7+wv84)HKO1YsC#yYkRDpv};#`cD6u{3>MpIt6*G!W@fNo z)QKVbAr0dsNE&8mHoKgc#V{X6dm&^)ts;HCi?2f9!mRjE5`k?G^Y9l!>|C%?Hm-gjET;MvL9+x@ zR)SR+((E0kY}OQ=(%VmN);nsLbuD=z2`UG0NyQd31b08V+{%w#oZ^*L4D>!c1d$$8 zIf=1WxL{vMvCCxx8=%W@T zV`M8*bQ!ARRf@*EW+~?pnIN9b3}32~Vwanj9vCNy3pI+YH5exuq*Y&+u!sudlA%hp zPyH%=cDV5gh9Q}jnWOp?h&-2_aHXxfOdWy=TaM^iQ%Yu4f+;ytdBJIQgD5)kIe{-j z5*O-8Ff?Gg)KQp$h{Hk9=8Dt=)ID#9;BOWrWm!vs4I4Q?o>RkoOvwS+W^$PZ1>y;v zxw1l<^k~~`-ewd@{>1!XBO!Qw9-S5%+;zpIlIr=>6H+-o+A+T2t_5P;wt-~Q(Hy%l zbUFt^#6QKf)sO~2`&%>VzCw`MlZF*(0Nj69hn%MG^0^4M%bZDHwzbhIjGad2G^gKbvlT67wHsg7Hck*EJ-Vt@WGcDqx z&b%*MxR=kW+X~i>9MjL<=NsWJf2nUnwMU}du2BZnMH_glCe@Zd@xhb;+k83ZN5h;q z4c&c`Y5yKKD?64&i{rt=gsb&kCpox@V4#ah`pQj8Q-{7v=5AGUQH?b06&61&L)6zC zUW-Nx)fOIqXj7PiMRz>UrN-0h&%%3j3ha)QHvkANk|2VgbUyKpabIao@hdtE{l~-Z z^i$e`8>E0`zXB)i8oN*cQn~73d3D^5I$SqN`h|(0!SI(3&_zJTBcBP^*ozxFi57JZ zs%?v?n;ZnjZ%V4z3SowZNT_u^20B6+GCO6vW77zXkO6hCJfasoKnYhNo>k;TA5%ka zy<0SV0se&1pN2_`)dntjo*GZJtAp-T{s;G;3N;IVk{2fg9bU*2HVcJz$ny?hS`yi! zd{(yyL6q))!Z~!DM;N)#{~Mo){<&FkySfivTo`7ecvfB+-ZTrP~Nnd!n!x zlDS<(41svw_yW7MwflD|HWNFlQ@bLzNOiiZVIfc1gP=uU)vOWNV=$k&{Pqy%PRbhB z=Yf=t5Hl!wD6Qu#OXp`5t~MP`OCV7S{?w-dJ1AK5%^k$?m|P4aq*m^8Ql9-twoChm z;0f7~B;bWL&rh1e9mD_HN#5}dMg50oc3pJjYQKTM6Q1m;H_W9k1jxLZpP#fsT@%W< zYNynr*iOsuP%@z1t^DBC$8tW|7aJ@}Ct9DdJ1hqYdbR)KWn_55O~46r=Xw(&u=R)c zP*)iRFkLD!+%1=w>RTZ9)y*^7azmF0y0xh$8KF6uGwr5RI$ACv| zHtOfI9r<;4d`0?}zsLb1PO_}vz*<>q4)dn3gYslBh5I7Ot003pZymjHxj;5#aF27G zBmE?35tKW@Wwm3udT^md;nGeAW;&)57ZF8qx+ATdIO65pB)jsu!~>g@BYd(JlN3a+ z|G6gl6iG_f{9=Pqf~P9*baxF_vDCeZ;tano1>RJtZh?b^-G}$a;z@KcoudMogpbSP+{Rys2NBY9dqXyv9 zewR;}Rqw|txg4zdH%@pnBkn3SLFWrW3M%_<+PlitB24DYYM|P8BYm0zOs-n}bh^@g zh8~ci!!)jbyxK&YF~f8@Avu>~sd|ddw`atxd_faWMjk+We zzUMePlHxCuLI&lVH1^d%>JqaHU41Q4r#U7$UjJy13n6~P=s6_0FfdbFqNj{w1jREQ zUkJYF)XUU6jRV{I&k@k!t zJCvpPHswsrTT>pztii=5NRYVpPj$cRmojo>sxdVSq^xU?%2AQTA1PHja)KlzeO1eh z(ZE*b@*2f=e84|~LqqFX+)L_MA^2IaOQiCr1i`l&*N&dge{^v3Aog=&L5_V9B}v~o zz0H0&a*;BT@Kv_~;?bU-fOox-WA!yY==kx--J{&_D-fQ(j~WCjXeAK$R!556i_GBW*`xf zBJGAII8q^kHw#PsHH-l{6Mb@5xr7&eocOm8g%V!LNc8(qNWbrzY%6rVR}EZD&Z%%} zNBxhZd{lbD$-(aE=1S2pajU+SluzG&CzdHXEYL-v32h-+Wgpj$1?LGEI?#6gx?F;E z{9&66e;vyfwCwFIC~Rm1WhBD;Phjo72Wi}_pRw9m5Qp3tKSbyciK!1S%{`6cwp6tt zno|Li;N4`p3KHL4E%Hr4_@~5th%{PN?wpM>P{n<0{Y%Ms=CQ<3p9WX2974kW6jbk? zQyV(Vd|5CTa+4#}wH5lsA!mJC!&YLxi*hqv_2kw9LsD9`>M}mRXY01<>6=D>4%O=W z`B$81WLC!zdbP1R(`l6wqsrI>*``acfQ;t%4irkN?a3(a`jxT@W6F~Eu7JX%$lQ8rm8K{hE-UqT&`vxV(bh`paLfU}<4)!X^ zQvbZjhYCh2a*oMIN6Pp0u>EAEG1&74E_~v=EED2r!?H!C5zPzo5x+c>ZCYY@cTg!0 zhv1^c75r6P@OLf&*!y4}3Qfn*e>_j)^?%Zx7Kl|; z386&5_BJ0FlB$cg3#{QA&^U0f$WotXFnQty-daLdBj9+K;;HpTFpfQ*^;%GV4?#V> z7S7DY0M#TrO6N#}!yR$lV@|KVgaDu`28vgLz&_9&m1FeeCoLw&ppE@%p|@ij=U>xZ z!J!~wg8A9+;JfC!cH)yBIm*W*+kxXP=-q|^!%mjqsgm5JapXU_f|2(3^KcUqpg!yd;tf2}?fN=ah@?-J>(e0cZ32Tn4{t+<|MmViNVixTt)u8mQopFAxwPAKsAu$%-}rQOsfLw;7x6q`;wl6Tv1E zg-#7ipe^^P1-sRKQF}5dc7#MjP9!u7vshB4E|kVw4F)xacv})}Ar?L+)LOJWa#uIj zyCMRy3zviO4$>PePb2cJ=g{e=d;l||t8y`3%P^{)6;&1B5s$*JC#@90m(M#T@ zLfaTZd(AvRtm*O`?eq~zb{*D@Bp(pR9g@ls2h2&FC?}(J`-=IfS}Wd{65kmPi6!x9 z%fHwWUaIq%ZoK4}Zm8^14A5{%zx`%u!WWf`-NWb>VHK-1nA65$1FjSBLWsO|>9ply z|NcfQQeg{c>YeIeyulB}z^?ponA({!NNjXTj?EyXcqn?gbUEvfhhne+EFe95NqAzT z{)(^XeDXY5!mREKsz*09nhix7j24VqB4N3*eFFxE{}AzW84-_ozEcu(m9H|iCW1;f^6rct{aN9il|Z-cV*YstjAi9!{_I*RO6<67K`%v zFm-$}**_MGoTu+j^lLv=kc+>n7y+QPx7H(nLIS#9DRP2`s71iv^jTD&LiiJb^uc3F h0}PUidKRVUSZ3c5FD@wS=zal+tOT}Rk^Td>{|AP}sD%Ik literal 17966 zcmeFZg>xH0)Bl;6nIX1gW@ct)X0~GnnVFe6W_HZXmYL(2nVFenW}lz;`CZ-Jzi{=I zYIjCjX?E26?e0%ct%ULI+qY`??_c|G-)z1fY+tR0nUk}Xy&VxVHv=;R6Oo9km8~fe z2PYE|6E`CZ3nL2?GdGc{43V6biy4u)sg=vud$j_<|7VCE(f?__SwZ}_{m-63;=g^5 z@8>!GbyzFfM^{X+5^_v^A*Rg4uy#xh47hA+kn|Ns=2Ah48NbY@joeDyf0o1PMys0) z&c6vK2o7Pio7#+;VQRLBRGUP#YBkWdlO?%U46d#~AgccvTU60jb0c5Lf%(Xx#7F{xc+Lu05q6%KKpw1!ae1gd*wL^RD68h>$bJFKE+h4DXjfQX9=l8j56dhimd>BTfCyb-oA z)y}8gDo_>P_eH|*EP$1>BFdT%nVuzdjr#&tWM?$y__~4XIFOvi<+}v zNo^#~;)hWqS=bq86!vngnie&adK)=Q|9iUsHRk_H<$oRF|36U$(xhGOz+P<=C^bfU zbH+^jbo^=?jvsz>Ip}x%@7FTrP~G?f<-bv&b91B8#kyjAj^BXqn_u#y8nZM|Q6)&%)mii;QP0vAc>$QM_-CbNo?@)lYq=!|` zZh~s8r2JBP;aSUm4Spg*D{0@NY78KLy~C=dRKlc>a_PvrMEknN*D1udMJV~Er32dI z_ZvKt$K@(xCVa9v&Nadl7+u2U1e^E!#@_Xs`_-T4h7Rm|+Dn6_tyb>> z)@Y=w?QrKuN%`S!{~*|i8I8C|qRjK)>XDE4*t5Nc=a>Z>nINc*Q~ts?7^!T+sg{K4 z7WH7c&zt?_CnroVBQNmnI?P?L{ln1DA->v;>$`o9QEBq!%h7>qHwO*o=AR`-pGt!$ zDdl@9&o(O|1N^pH(|-pyXU=Zwo*6DR<<|;1*r%%^8}gv?vpVulS(@zE*xz1>Z(S|~ z-g=Bl6(xS+?>4Tk*s(hGD>y=h>y&r6W#$T4d6T zx#tY_>|Z@VMCYSfFS9n#2qhdb68CsDy$v^bJ2ZIV2=J&!%#x>{$Be zpBiTwxDb`i990#r^@C(ST5Km74OnjWX8O{7I+a;v+9pxy#1Qz$Qq$6$Bs;I=)5vDi zvVTtVdBWom(J!yN(J$hysXkPtMMEHl#{JR*5nl4EjkPRjXPM3S!z1qq*uvkR{#y*$;s;QX+a&W7fHs#?k?2EW$2sQ_5u>t1+RAR#~ zCt+gi##oQ-;qc@9$Z6gX|Bctmwq;58oJgbKwD&;yr>$?dCP_RPieZ8i*WODWlg#q% z*#!epfsTdE!K!=aX>)r|&;REq*HSkeTvy2vlsue)9Nd=lazCCT^3rP)!M}IM>lQvu zX>1E|!3X-z8NaB1+^6Vy+t1&|v0&SU;b_lGrNGeA9f1*pW*EWk1QGes$x_$C^02J? z0s`5T<<_T~?XOz;Il1VetDZA<)S&?1Ie~|l5StN==ld=w$ixJ60vvM@7cPl1c+`9( zbiHsc>{pizSJGIOF6qjZ!ob)dZ0Ro*Q$5$KFJ*mw^^q!g-)TQ%F{>zI%1ZK!hCDmS%5!-#l2nY?cv%N)if+ewN>dDM1j3K1X)XU{4wD7>1y z)|;Rr+Ke^10)TO-Z(6^*&f0%3`IUbC{!DXKDh%RlzU}#5!DhVc^8&L|VFDtYN^&hC zi=XYnJ;is#FVT&FFXH8Iv(RyhbTM(3lvXYt$a%){Bq+^gQWHK3nAdOSOB?@vTq%LE zZ_3Vp!!%zKD z|I@*_`(kb&q;~%8kG6j0XcLUepQfOfto2R08LCsa1%=mE*LDH9FJmIaIO(;uhs|Ph zySjU-6SQlEK#M-0Pk)OJqivXMelgc1*3*JMGTbxO%e6SL(b!Raemt|ISta zKDeS)koVPF*rMEWm`W6yyA9^~L!d6{eH3H(%HBl#99deJ4Wh64J%rI~sZ(qiSEUbd}+S(OHwx3)FJ2IJ2i&hDDArP27k<<;@C z-1k_*wQ6kG_Ud&Het?Yh6ykhz!^HVb5XJt`+#*MVr&_L`fRPf3h|ju-Wz&{>F=Bfz zA<_3OqU=i2TDMv{0VsZAMs3d>s~?f^oUV;#(;FQN!({siwR5SL5MgGc!=3pDB1}{a zJF7kgfm{BPvr@~1K|}A^jAk?WfwH%;LoEQTVve1K=D#=}2UieK)wPtdJI@CQ9l39; zu{(JX**hDty9i69z-)^$?>1D(Y>+zUpex{PTQgkRQ`ta!hEXT99YfkkaeNyWOppt# zySRpalC)+|D!Cn+7LbtM0BKptzu{X4MTH+Ja`EMclB0F(VeEdTZ`S^Plrc=0u>H4J zFg_2QG<*4=cfB$)dPC*U;&ujn#7vCExauq2g=u*agE#kLkJs0dWf!qumg5fa`rW#9p$8=jZA)3hgGmli&}Q~LhX7Z2;Mu`e8E8*04b z9!#c!f#93;T&q7(bYjeWw|-~3T1WWpP90_Eh$9W3_UdaM|3W1|SW*0vDW71(;8LQU zD~Dw--Z5o&)|=;5AtmRj>cnJkO44aR-0PP%BUpb8c3ejb_#2HShb*86BJGPC7c}1c zRz}&O-Ry2v)H9y`P`ym|LEPS3Z;2;Z3R8+-{{zUt?rXf%2U%=1K1UjBU*;>9p;3=6 z%`ko?WEJmJlwwI47Xa*x1HWzERGXsDAM3vM9Z7$&|HC+d&8wg0(ghC&O<82Hji#l1 z@2s-gB%pPNFVoZoxZz7eZ1j9ijIt(ptdM#oHu*q?xGydgGMcDdO+<@OQc))*VAm!X zZkd6zA)%$0S&ZC|a!)Vc^VA)S?*;ONtQ0D9E-3upCP0W`8Nj~Qx$(L1uN~MZ)mMbOtlw<7nnEP7f!A1%}f?w40<%KixAX&NC8TzGFhKn6H_97I}~U z>()dx@0-u=68nex)kclv1_QSBkJQo0>!pyuhIZ zMb~=0U4N@M@QI*pKL#>lPmj}w2rW-P7e7eCw_>IIYQCH%sNXS)tg40~y5U2!uD#!O zIJLe>Y-$O!h$-mu{lMTp11=YhMB@Oj_wjrBgjdi5BxBP5=pz8ae4U;IR3;&>q?BKM zRGZp=qCg;=w`}ijC2L##WHm`s>pcIP4TW zPZTjK$u?2}-fL&cnI-S#IhE-^wA*h}1Tu*OG4JMBK_ZX}6EDY*1$3Thg~+kNSA7w< z6lj6DlR?7wqX8Lhcy6KO>Yg9B0Qf^0B@$AlQe_G2^d;B3R)zlvE${Bb8o>DF)3jQ;WYZfe@=@kgcc5t+5&S9x2hI5U{%AZ5p;NutHS74}yY~O7AH*XA_4Mdsp0n)DMyeA!o+@np%{CvH(}am3v=A+`e6~ z`-x&S#zx6PyNaCuOffG2iUH?`+5Y&m(l5(9Q0P>dShuAd9qxZ{CK!Zh#$ZX-ZPN;~ zaw{0kT{}tY?YEL2!f&W5pJWu2O!@uu0~d7HnJ+y%G4O#KRElZzjd~szmffy%)6Qo=RiT zGHxGjI!-L7i!3ouRmg}LpVluw5nF%NOwl_)C!3!aP_XWI+cOFBeYXz({-wpu^Tb{y zV%*?s(u&@UQjTB;o{N zkny4QRH#Ubt!Taym~C~eSyFev=e_UzI$W~50iCznkY3*^Gwhz)FFwM?%egJV+Af2 zl8bFeA0|fV>}5d4azyAw=)4^*0_d7ImpDflgSYWg=0-jI+d7`{WT(V0jD?K$ZPzXl z+<38(a4dS6#^!rs@4cGzFs$6)gl#o2_e zqSl&iXU;bQQV}u-@pNovvQ_TDNUs!Eedw>b3|rWLl+DiC@Ho#F)$P98s(xAaLro9# z8DtYt82D_=I(XZEzZ|qKxssT?gi;Ww#(q!Ri}SIXg@+~%pa)QXhec@96+=6OIQr$e zBh_RfwR?2eIp&x^b7p~(VQ#`a(Pu zZS+8j2TO3yc~V2#n)7;&4Nm#{QBUvGLh4b`P>6ar^$>_8aO51KFB;mpl982khVxVA zsTeo0|Bqyxz|$_#a0Ok%odyc+?a`-ui#tM~2p!5y{Vbw%0sr#?3Sy6-tE#(03EOYL ze=@Q=ETY)~zOgdl@B;@ir^5+DLH*1tzR7}mlPG}`0(+@`-0y9><<(c1gs#J9;x zQP)Ppe*Z<`5ipiA_l^iB(n3`8Iejq`(VU+rnwon5C#z4#{%W_m9nM#Uru}C$O}sUG zlx30f3p~(+l`Rs6tq= zBoKJYK$PggJu1ayl)t@&-vyt|lqH;gWYcd;;63iVw5JybhnS9iK{2AA9s)g4kLteA zh~uw4?y|qP5gn2zw-T3u?$X!LNWX)&kXCxE^aH3=Q5&IzJaZccZlr#dENtEmF6WI{vmEKGL(`$^@%8*>R!Svf|>zq69j8G8_&u z993%TsXBE1Py92k28rsh`jlH#?>th~H%pvv4(6rQLz(dhHR(ZyEG;gaRMv=GbXvL_ z26`PIri9vk;B;j%s$;90I?f4a_Ct)?c$L7j?MDy5Np zl^a(mcfM}kHJ*;sZ(xzcc{$8)#hsQ3y^ikDoemH_-r?pE?iq=#&&k$!gCg9V;PvHY4qDAnAiYebG-|p%6BbF(C;|`GIC~IEcLXo8o;{c^F@Y>OU|^NS07qDZh0#kcm46@Iqlf z3sU+e^+Yr3%3Lo2`M!LskQb_A{0M$xNjJ|~)* ztkse$ss1xv-A${@BW+iBU5o*OrYQ~0AP1)H#DCd1o6 zt**3-V*f8g?ADg}O_0J@?A6q`p-cvLH}jA%_A3_7Cu;T*>iBqq2=|{<+9FHcc^JV4 zk88eLm>Nvq#C`O~w;kF|K;stHR8?y`m4%s*;VM5gQ6+J}HtzpRo&X*>rk*4F?NDZu z2lfP9&z&@eq{4$vg8fVVE`i_SEMVVBnY)iWWSt*k-s67dKrbLzAxR#JTd*4>PpUKS z2(Vw6oTA)-d9KQMD)l69UhjquM^c%Jow9|2=dm4E4nSRS0WIPUDW!Q$on||NZi5s>UaxzeTe$X24*Tbid7G&$FzynmV6#EV zorln#byE8=_F82&(OT>Q%$wb+r}m0Gsgm^XTmYCQ_QBC|zLbO8Q@1k5&5j8{09huljMwWFR2&@HmkBC2G@i=hE|(so*v@(sn~vkL8Qh8 zJ~SSh&jn8%qXN{}sAyulc7Y-BtoP2sB%sQw2@$}9p7JpJs4W>WCDV~zs8q<_`Xw6w z6zq~{_{-VSN@eS>gR{|*nSYqI6_oNkXrbdOBGmoC#IIi&)_{BvkyV&%64Nf_Yt{7V z_?i1=)E}C*<;6`Op#16On;jR%N!_&f_e=tSezWU7h*^u&3ig|5mz6vW%IjiX$o9|A6Xav15KcCwLS7I zl85{-0o^#Q{54XlwJl~)glGrh+&2+}R-It|Wq%-^uk*H^lF)PNmC*MJTzB(vpH!E? zr#i>utzME~2}eQj;X{&Om%5*^0zoFvjIA}uLSB+6Y?eT?49Gk&MZULk5S=~&TjxLlwud5#he=83ZMBW-(Rq_B~x zr~I?$&(FGd8%F@ERCEmy$!7y0AGJo|!KQ(@tSTNJ zG9%V$<~m6GkUBEV(h*l6EY`Wf?=v~wC^>jhi6mdwrXd)&(>24}@}Z~mjtXe`?kFfo zbfHznv&*v(G?aO`b!f<& z8ks`8JwIA770i=R&Zt!G5d15cq^syIa*x^*jt*;6CL2tBY_{j5*@BsgZ_V!C<}i#Eq1@24;YFc|@O> zDLJTtNcy%ChhOBUw|dwPcv0G&PfKD4BK|1C20oMUqV+iGC&@qR=bj3FKdFAtnlEeM*X-HM^+v zlgxQZ{vu|^;EC0l-gK6ITjW;VUcZD+HT)P?a)1dVR@nN9dY2DDIK#6>s-BD*LX;WU2!Np z26%FwO?4yohAseunT%rkEW!MC;Rf=zlm^dW{7BIk-Pt>#N>(a8O`d9YH7?rXjHOEV zmK3a7@*>>n#z6V7qbL&GrjePz+=!3*dCwknn-rtd3TqL;$WJFm8OmVs=)$`PgJh&( ziF5_aPsNpUq<8D@N1GiJSIHBX@}mH8mwB}n51Bw=QZW}TstXvEPqx{X`_lg-1ozN3OZNGZlr!gHper7cVLbDaG#xrm9%mK ztA?3G*h+F>YF?#oi0GMN!lKdnfUQiM*>6eo%^-S6@4e;qiXv|O7*y7aV4C2@AE6t< zldmznw1gdPO$MuH+_$qsT5SbFq{!;n?cIQ}riqXHCUW9~%vwn@Lu6sZ%{es-cTd8;f|veg3(c^K6@* zzvs?J)S$A}(u(G?%g4V1)fG26Se9#|2EDs#x^d-gyQ%nqki)DTJq*>CKMFi67I*~( zxzk4mys*itH*p@%7BLm-I>gPU;rs+@tsDl~_#YZ82r<~)Wp91*Bcalf;4;^WJsG5( zE7{UkT088Q@7_l_I236_I~ReLZnwAOIRcXCu=R!aO(-`S^O~&NO$q)K$NDm?Jvuo^ z2F%TzvmNpN#c>qCu-9P6(#Ph8u@+ReJk6`i-|XqDRbHJx=Eb~2cTO^!&R6v)xYj9j zZBdn%C>+BxRjm2xio$ZIBz_(FkXrWV+07+x@t`2SSc*hcawoLr_0+!GiPiN-8O2yK zmx&{C)LM2m322oSy2^l?_7+eS04alL!E!B$%n5$CC)J0(l>{(ao+w*!qIi`ynQXBc z#Y0(wqUP(DZIAW{iT=CIM!e7>hz z@@ZE)g^6HU>>-PKGkcc*a}+;>yo~PePktUMW_kM+%YSUpzG8$E02;esdL2AyVwMTK z>Ifz456D6!naKN1W}H}GJ^4cu-am(i-5FVCSCVY{{J*>Y#zQD;wEGR|?&euIJg(M@ zUOYl-GU()~)ms@!2w7z~eTXsfa{c`T!#lUXF3bGA*^#PTjRTa?yujq(09Gb5ir|uy?6$e}ikG*I4}Npsnf+xB0y^y&M4d)y4O3>7#Pu6Hz zFC}zm1g9gvBiY`f{ z4h|qq8pFdl5;e3+Tq0W@JjpH_M@QFHn)#F740}hH$ES?C}UA^o#iW)y_qe+tNQA@3==CI|(&;cbgCBNXo9Xzh~|` zSb@*AUVxj(iVTXOshnZZ*w{$hmKku`)j~`zn*>6|ikINIz2xrB-Vy@_w z((md_C}OGKtB+?&!tl{8fdgXe4Ta~X_z1N4cGSswb*d$m@6xOkBA~sBEb_3r|<(?ha9xv;Fs#_f<+q~>P zz3jb&&;^xBP+JBxQ|r3clO;$ph*GRB0a2;Rgm9 zS(-utT*)w;aW^2WP|&DJUH+t3d5vX-krsZBnmH8Qc;-tOVK(DI2?qZ+l<;$^@gKC+=5YHCAvt zKdyXkW*%+5=~nVrkzpngA-c@Ori*{amih|sZ3|5|aPu9T|9m-5+y)mO+pG%ep2?ia zXE(Y|%t7w)K1wB2kYFBXSfN2RwLCTUvphwYcHdl+0nVsYi^1c8>P3PD$+M8 z;|p$X`4*92r&Q?!j#3k3BPYlL_cR1)Rb4Lbv$l2WdfCma#mBav+3wqFk3N ze>N|xvSPe=c!{?H3W3YhdhmbL-7{ZoHpbxK_|n#eu4;Uy#i;}m8R`}vy)?!AFsDr) z@hlJB*^ie+2r)p9wzl!}gTzAL3j4d@%LhJkr{q%San;ZS(c{a@q3XJkDjq$z_c2R4 z@zNfJEh$8oiu(0mPwxuIm<4ZB*TXqaZ(m-pp@Ga0>jh}i)F+I8Rw??&QZR)Ut2MNW z8u3pn)#0si`9G7#cPYD)FmgeFwx?u&>m2DPGb7;@yb~*`p zuud(I1U#Lf-h#+o-N@@W2#B&wVTInjm&UvB*oy`t~336fV(6a|Y-eH?a-p5h4nSxP${t z>jWWDI3miYz=%fxAEV7!Gek}v0=Gs#Ga8Ed;@fwp@o)9rV>a*Wj2+>o7pXENL^i=| zMh6RWHV3Y=*}LFN=PX+MoH8Bih(vfZiB&2Yyy4l&)*jkd0yX z)s+ZCoHjE+JzXBjMuTt%CD>|%=@U|#DII;p2z;C1RchWr5|({~_&IL`I-g4HyzJvv zokj81G^R=G{0Ci+kZBWuwpHN^6H!MZ%1;o!IekO2lMObVsMj_-_#&YB1ok^S)M@*y zdvWv5LttDm*GrY7s6$R*(u+apL*kTK9W#VGieG8 zQChLnX$!+XM+t)OhW-M4P79%YJm;O5r#v#^q_$#Wfq(a@|EY?@*xW73X!vH6EkHp-x6f6Fpw@M_5v())N^ChKCs+)X3^ml!kdrL)W>^>aiMPRXsuPRlOGc@ZWx)XQ$Ke^S zB5Nj#%BC2pEnJLA_I4{k{&T~Y&H{4ED>2m zkIJdoc}g9DNTs4A-7Xm-RC(xGxEh6Dn=-CleQKn~Ihtom68T56`GXMOObH&LgLt39pHhE*+!(aKaqpZDgf&{)Mj8Gk4fpfcQvZV zQf8(-$@QjExMq;7O2`x_J|+8gQ53Z?0DIj)<)7|E8six=k7ILsRua9Rff zD0_;+I_^&vglEq~q)DF(W7l0(olI+89bR5B`0bhity6I&jdti?Y%M7Rm7OFa(BvU! z7RGL!kofg}Iu8KBX}HMZFr47C*OdBF+zfIEW^BuLcd(Hdm&g*ZDZj1034CGNddU1m zw)OS`^yRYS-5*d5!+|1gl^^r%)iR01=tK0-KFYH3O}puqB4zU+@cT_2-;`VG+>f~X z3nMp0{jJimqn0Dweyyng#7ZED_G?U}3bOFC#bXZ#!xbGca*5G&gCxbZkSpr5pIf6y z)=Q%bjJpYgX>q7q4`ZcW?I#%=sSz>d{%O9Y-$jyuK6d!2Ig(KDX=$_&pAYaWYt{-y zx(h34^lNVn%><#dZqFjL8jdl8GT=pVE=mCX%5bS7`9f<(Csg~&SfEOKm9mF01!v|8 zsAe*#T3SdOA|cluJTU!A`kK{G3L>GBW1mr7=YS6&tX)#9-DY`;pfRP&#j0Z8D}Qtq?9ANRKtNNGNv4O2MGDYjsKCaHC2p=`Hh?8 zlgRHPHF(h(=sKxjFDl96E=1Ql8q>vrqY{s8eFl|WQnFcPQo}d#dT~&j^jF|b6VabP zNo;JrvqWhUYUY8@gNHC%BRVv4F^_$gSfq)cxN0t0yZn5^SkscFl`;e#3k)KOvtmjB(zzC#W@H^@b(lyS$zU?$|RZ5cNuLu=C z#LST{8N2R08XldefU|-bU^`3E**Q$1e0PB3BgbPKz&${mFQf--7Wdi~Hw%W7of$Zm z>aDhrG2~cZOqH2IsBgSC=UcDQEwy7v+ShgcC=u}(y(5wKTd2b4Y=*>n8N2KNkP=_7 zBM^YjG|3>K_lHHo99RJuQWOpQkYnPrPS>16V|3)+c{6$&7S@SPon*3O#cl)hKj`pN zRdqXHEG)Yer2R%TR!}ASITw2@z_zR_mbfEzP5k*8lOpU7-eY+9^Rq?iSx(fT=@H~gikL@LB^WfWn|spe0;_d|+V`w_a-qf+UKo4k5gtq{ir z%6~Q}k;F8~R;+gcS~#7&e86Qk!@Xpr-HBVx@2eQ|>bWL$O4&P$OB?2l|2EWwCq`K6 znH*)V#)yz~c{YPJrrh5j{Nw@KA+yn1+5ZC*vH?~FK5qTHI z!%r8TyPtTzLAMZ#`wM{0^L> zAfzDec0_j-`er97`Gux&Q{^U_(WWp{qTe9i5~RYoUW^|es_5f~X91yo{D^3<-)T|0 zE5${YZ8aY7b{<2RqQ%KJ7xT#hd#R@r@a$^N-lJ<_}(Qs+^AzYnSWBM^(ZOCbx{#1t(Zsl{S#n@z&kY7+y6O zKkXJL*{~a$TE5{zqb3dHa-85-X#l>NC;Hq19j+%{O3_24ln>~CYU1s#xt2dGYTZAD z6)(_Gp1VnQ8~{SiJrENrj+4tf4KncDR&fWNFpAt{b1pemqFve*tV{1}tKI~oP=YFW zaw=Y$pvL{nS$|!G>D+vKYoA9A>!u80(J5C*lj)knNdeIK#fMTXdijVhgyT0$kyLBW z<@8^OyO1UJwO6S!!T@tp_Y$(ueT!d?!CL4sEvG3v7I2mcIi)UXlvLVCT{7n@^a^efAfi5x$( zAxL+VYKf!wj5CpUGHZ2e4-N*a(-Eb};%O3GV$zMvsZ`YFgTwrZ}su&s;yC^8eCY>#)|jsl7; zrNy>mw?^HHgO6GGHCDZ7WeRqgz&HgVO#q5rED-ZCp}9&W&=d|auP%rGai*?OrrKk^ z(AX`FuG3W%lwHFiud}!}%V9wCP(;4y)3&>}+WBaFSQ)ZXlIU3u83FpbVAxY>7qXiSi(vNRT3tLtAJES?d{0_I! zTVnts5Fi6s-l8RXUm?O}T1sNlu7O{LZ6^Si$XpD*eJ}%y7Wk;0vq~3@EmLgNrXs1- z@2y;F4-uV*yNMhBfRgq=a&4CaA{Q=2>^u~Q91>{j(YNNUPE{av{_eMCX^pzxN|CL$ zV)oUM8ke_y7OgDhGDcl?tacHRInv=(+K<0`4bI1FNZnf zix4Dk(J(#K1w9JTR}IG1A)?(iQ+2-`CL@h>I!Gv0qo#jmLCPdVa-sSj@#<9*AbUMkAn~M@-{62tAx4uTwZzZW%UDsh+C2gSYf-^`PCB#M>RXh~Uiuueh#F{;U(&k}mS7ixd z?lL$37wr;BccG?jvG|{&BTgn(Saj&@u9Z&RtwOWvyEjqqT16D9pDukrF`yYHoR55q zikOHW__;K`q~C&%oUm|u9Wol>qigQj;%~syRea)P=~6njuwtf<9fupRCq5b@SatI! z6lDZR>-NH3-oR^6N>@B?)TT}MJY*Jo=CcOOjppJCMQh7tk$812xby!hCerK?4=T!@ zyAB^*n4|vCPr|ivhOlwtXN4nZM@{`t)qH~-6t4E<`s@n=-y01&k)n4O4rOTY;EcR^rl4^Jp3g*{ahOADa3a!aGkIFW3Z}cu;2H} zE)p{>q)d-TP|!x8X~C}4wbzK*&sd?ZpakvLBJ2ggKA68~NfVP_QN;a+E(^)QXkVPG zR1xjPb-=SEjC0TH^(*A2)bE1ratz7h?QTK4h6)zZpe(Km&;@r2`_0tSej_ zsA0^J*H<{TrrfqJ15>)_KI$&B23{d}PaJNikzorjWSaH+lJr5-D3WS4)2w)opR)Cu zJbk~^nQP{2m3|49G1+BIi!|b>@VBDy5gf1mR<#w0Z`@ODLL|gh378+MK%3nx#0br1 zq_NXsaB1^5b>_~`evIz>-Z9Js=6lBeuPA>5ifBAnW<>SSlr?MQF|g)@MfLDRkJzeo zvUw^Qc+m1#q;GWCkLOlObYImcdU#;%?ME z&{lsvvc3k`*~iSDNNe*H#u00VD8%B7nRHE`kXNqRr#N5D2RZK@w0L^yK}W9+eJ?(C z=kpxq!(YGI#=|ZXs&ms0g)i2WggR^J^-!=r3r4VdMzGTx+(CUrT_3HC$*Oheux_Z@H%U5R^gL3lGIA3qSU~0)=Zws#iMwkowT#xAZRC`gxK;cwPM2>H{WS-$H44_ zh1RW-=*tmTsli}l_EX%_v%mrAAfU~eLz(CwcTl7AJI^2FgeoE?$yvUyS@YYD_}Es8 zr~71l18)Q@+L-1tG*fryUu!te?nF>Lo3-`0vvmpxZWurqn12v2&9p!ps67pRH?n0@ zcQ|YNQO)%ALmKUbCIrC)$x>9O-UHcc6t5@1!p0A;Db{sK65<5nspDdmitURGZG`1q zqNd?#V5ywxaqZf)w}^O{U-i!6$GGpYV;*y;=k~!zGA|h! z*ndjV1Gg&55xh|AT8p+_VkXV_ECJ$UrC?3yphv$#zb3wBAysp%X9*ZA;g}KGAeecQ zYl?lmfa@8N%TLWNL6Nb;@uh6nXiiNH1~A%=aS` za7mu{0QIavnRF_zgPPKusCe@8H#w9ok4HL648DB5o0MO*(t`nKb1sU~p4%_)ZCz8a zn<|N=>x^hDfT^6BrMa&WJs9KSBt+}iS~2O?WThrRCh}Y)nXI5#4(^{@F>vEG%GGEuB1osoP@!5I?J{~4_kLlhMmqQ0Bxi?I zCGM~%ZE!4Gq}t7iC8Jmr5chkietUXx}hsk;QJzK~d19Djs6o{l0St7M|#_DD3#%5~y3HG2v_O=08?Z_%`af=+VYYv(!^36a@l# zf6g+!vpn8oh9~GiPI`rd}?R15sRh^{U=kZA> z8Aj^B2^#(n9^f3MW7viG-uBN4K`weYm{9Sb6s4?d`&j159#!zM1DChw(VpVvs2y6& z8%drmZ1?a=Cu|UBF~aQh79GnbBPwmU(8XTUY+{R|k!A;2q3+6a8P43K7|zJ75_I5D zNsZn!R3QtBMJ~ZK3y|`aYK*C)(Y`kcxPb&7+BBLn(Fcw2g-R?T41JRW3%7VdXjm1W zwv#*4dWj7VzoXOf$sP+|uN^K1;=$-F(dXe`+{N6mkn`i~*q`0b7BQ;&{p(PT4Q7Ji z|3>mhED|w+tlnb-Lc)Yy86mN%wVh$)Mc*!Uc8|w!d8Q*?!p5wiRC)CBuI(c@n<*6> z#7K6|YJ0$lD+wyJah7+je)U@DuzALvN;GWBW-=*W{-ca9A~|L<&3<;Wqg{tNSM}GaZ>DQb_tbQs zGks2X4<;BGSOo(3R|^Ja`E{{<^{U1Wj^?&DB+T3l%nVEO!R-W8~C|5LWZ_jA`n)? z>9>ZcXehcSTuxMxd&oZb6zr#L_N8P<3(sX;zwR7zBIT?Mfqa|tDl5Cd@7!4>m+7(I z8hr_rD^YGmx3`t>GB0n>aFF57KbAh-&9=0&=O1l|SVyO(63kyTY#C&d$0K)6EfT9J z<1Vb^suG|)8Z%sP&2T^MH+GK>3MknRB4@zp8hn`D-~W>;y0cL7oKeeFm1K^*AyEY( zcV=#Li02|)t`gjq6eWn#0?kc6Fa1U$fDoJS2^Jf{dJ+LJ8SEM7OVNPEKkH^G{~J-) z+N?+xK`IB;lImkloD;oDGvt) ztT@?agdU_f|xx^E<)Ed`RsHt~ULMv>?m*mB(G*NbU z!{d~?Kc{F=D08&O!kwhN^edGf4lpLFcT}i7`h9_Cd@2wRW!!ChCH8bXq zb~qPrGjxAk{0j=HG*5B8p7~L*$F+~zyX|I1UMP-2yH}bv%eV-3XSF?7gT-D_#hH9s z+9q3vjRk0Tg086X(9`Sf@#1$Uw-4G*+vm>3n%4F2^c~%QsaDelqa&Vx{c@C%M-9m- zv4VyP9u1Gzq6sQpGpT80dZ`kvvY4sd#`Fd$d}D1YuljI))ierp8ik){deOt(?Z}!( zE}YB-7_5ckbJf;Fix$Wm)EG&`Gfbf#d`3WT$RN!Y7-ux~rf zwtp1XUYF$f3`5)`5%zr4WH`$o8@jisY)ud_QA z+W)JRTU2k%%A-~LmVrMBCsHwad4&dRgRW#bQB2KAy=mW?dTeBjrD#=kbYH!C9&MwU zjv@KBoVsPN2CFfVVa#fojoVqngcc{YOq(l(Wj)B)R+U_e3^*RIRyqN}vjWa-guz@=wLS<&> zSB9Y;1oOH?dxi39T~vbbpzGd0?nBR9Rh&O`iNLBonbTR)`hSyqA<2^h(0u=F-Ue|2 z*1~SuP5H#3_@C;Xyt|Q{Nt?Yu59D2{ab#a(2RSj0`<*6GwKuQxr`dhMc+ps`+vlB^ zyiTQ>3|_w}FF9Zd1v6oi4EI+iWPwm&uLznmFt$hB9K|*KXX1eP$~BruTOog(B5{+% zTLkV!NDCART(EZ!hg~ryN}l7tn}L8)ml-S~;&_Rr%%Zw*Op=3?msoD>%5rK8Vgz+npq5 zN}u4a6F;JvF4;#SR-l_KO^->JfZoa|^w@ogI)mDZyvkcP+~?XP0jJ^BZ_dOa?`AXe z5;lv`=Q!|(T|z=yPM?+$zdokw2tpaWl*LqLzailj&U80#Ipfrbwbq{F{Si&#C$wmv zocH%+uEvvUYiAJaPHMqj7Z>=VY@2(f4`oB35-Rq;tGas7lEVEk2F+JF4-&!G)2Q3c6J%mQqO#JXh6QcLu{FB<;n5ZS^(8l5wA+ zum{NsAwxGLJROCLeEt;yLfLOY(FYODR}S_>)NenC)h8|Abo+S>(vS}vKE?IMgbAT; z;TkJ%g>zqUmS&9Oijm)Pmg;r5G$!4LJ7eGA<7#D^w;n>owU`lm?YkXdW@eTOBjc>r zYnSqf&})}PH+b?MwTQKo8qEZ21YjDIV{@ZYibQ-^=g}UxMh)_x1E1Z@4s2(zGIi&+ z%&j+|!SIG=DR=bohjrCxhztW&3Y_CjdvEnKmYTBFC3IIKtZ@62T2s^cx`Kl!$$9w7 z2{ia}k;z4fm@8yw0rNFMT+zptIyJ>hJAyrn;7MK?A=(c1$e6iq*xV=kl*40c7{h%hUcTaqpb1+RoUo5)nZbTI@;7HZFi zD?MvWK5O^$S$*Gbmo`!YO+rdP^;v6>M~*l{*g;fKa(Boe_)*oAe-w9$6A2A?Z#bGtq%G> zsYW+_=T+s1FOeAJd+OQ~KlYE>BmknC5(y-aHCx=SYFOK!?g+resbK{a5GUx@N2S9h z|GzrQ0fE)2k1@F_xZg|-=%tIQF#2Rx8L>oU(d#wd!WANKSpCX@uq%kTg@&c zoL@r`>ToV0ESVom@XXn2{Fi-oU9j?LsXsF1+4&{gD^Cb{B*Z_=4jLHKgQ#KHf*y*z z;?F&Vz=##?rTxP*q4g=N)nmXG? zvcUDbBBgtgF-8Moo_hL^T$m2#U@qTb)u{qj;Im^yK(@j8#Nc^)$nZlfM}MDnihyHe zjNwy>fa(i)EZV+V;Dk-S> z;k{zo2(CrI&sY@*bkg7CY}5Z{ohrImvhaFne20!?osN zH)ExmRl8Fw0EWjWv6oi?DhMcOuSW@v`4_JT8=L*oeZ-> zGd1f@3gT~0mQUzC;^KuCAxW2sYU5QiYyR|M3jS{M*ehbEav3#&6^msTW?Fa1==^in zTEb;#adFs?!q)$*8gBvtkr()|s5FK7U5OwqnbYOINNK6L`#zbd{q;FsYk{GkQJiw~ z+~v@v|FfxM?klXp}{T@>914IB-f=DyLVm& zfrT0@A^jL@$Fa7#fwnOKh3CAWg7j%s6 znaYT*R3{EEEK1Vsf???}`|Z$>E=)5~G$d!wshImduzlt_H7N=X8%EJ3a8^r6`TNAE z`=H*UtC3aR*(H||KmKH;6<+wcLy{&09B@dCJ;1F6B-Hc>xh`^KZq|pmWL%IWayTAK zs+-p&CvkYDFJ3_$OBHy{(+$(oNy-&rHJB;6Lb&jAE9Tjpx^K4=@S7egDPSQ7jNHG9 zwYy`&qz&ZAW9C}8x-0~(sNfi>WoGL%(6(8ax-3K$SXjZ$XlRG&+5Sf2ThpFec0OK2 zOe0L*!@F33)x>N{zBCknu1GRx->HnbbtL+9n)PRW>@mu=xeh7l@HmHUz$)i=;vi3<7YAPz08qglqm> zsQo7#5}u}dKolF%f%R|I6QO{VR*h|)YeI-7%|&hlIOBu@_GQPeFFWe7ZFDfET~6Z2 zN^h+#Ql6#4MlH(iiYZKZP}b14W}4$}bh3rnsNst>QAOsh#fs1DN_duSunse=9z_e- z)}owT-_HeSM2O7^%)X3fnB8s;D>#FF_K`d>{XlK#7UyHZ`_>R+Uf4{RYu1QEwuOhc zuBJynBx4<@9ae;cqL!>Gp4hR)1c$l#txuYz!ch?U zDI9P3CfW%l`!v5;p_%Tru1|U}Hv(0HCV61xa=kuRC`nsvNt>Yx!wOMhA5EqjiMOM= zKQUpht@vQO%GGIO*gLI0MnK=&S089Fp6$0qo4GP%C+|N4SI>IUfuUric6;MAhSW7b z__xJk@1$&!&$%WvWz_`Q{Y_p|D^s_@V~;19S)J)cMY;K0y;%!2;OiFSg{!U<>H^Za6_;zs-Fyi8U=IxC9qv5B?@q+oVE z_D0+Y>Lg-}h_}_<4OI(aFLKBu7~srgkqCD`grirVz}agXLf6z4;g_Qjuc`9#hR!5( z#vEQ0Zj5HiYB_tKK%Ecdkqr;|S!AhqeL^P}n}tIR zU2&#R;%EJE#~SK@414^H3hUIA7h1oL^S_hwba9xB%Fz>In$~+st_d}>TIyA~M;L06 zD0cb$GM&Krx=Cp|g4eVN#~;l#^%Jc=)&F)Mvz(FY{<#n}O`MX2pT6%kYPgnTFF+4j z?-BI>iMg@-t>d=dxZj8+6mIckzt$=uWu#fnz+;o{{HMQ@u6?9CYsj7bWTCba>Ln+i zW{u~bC`>^t0uEYM$W&KIO}G2K-51&&9N`Y4^$r620Ge(R;rJKydL;UWePl^+6I^`2 z&oXAlQW0#Gx;Gp+l>np+F%>77Rpkab{mOXse_;~wDT1mhHdo*60KLU2DME{Q<5Ogz z4DuF{(!RuPE#+$dHQ?=wD@A(EOr`30<-E+gr&3IZ2FPnwg%970T6!ou%I0h;V^|if z>v&{o=eEVGG;ky{ZN@uJkWVS4%ygm>%|5PiT?GR~W>`Be#{c0)|lGSb0VoSuX z%Pm?^sF2B)U267`$|^O8_g{n}G9@rEFXHheV_V>vY$(YsdJs*V?+3E3P*wzc<-e?3 z9V*E3upd&_BF|SdH_AI%i-=$?X}dtWk;Us%;>n$6s_KncR?pkcQbuA4#5;tgB6V%R zR8$@1*I72yF6^?In8Mb%_h2b_A}7mmWD*4-hH5oft_FH=&_Nix`zn3DcX>KEpEziD; zMnoc=mphVTphdyl!ZaE8bkKaRWI`CQ-si+wU6K~Cz_acmQHZ|GaT(qmQmY$yy+HB% zFeGor^>)77rf$<2-V=7YVvXE8498fvRfAKK!&tXnu+R8uO&??&{G0uY@{zT?^cHfXeD(*Ah zgkP>>YV>3CnhgeF;uCXlz&Iv4$xKUT?B7xR1f419=Oxz?Ew(ezEe;(#p}UYE3s?xn9s_ zj?fJGkc3ERf84F8Ks)|h-h^NsxBzObULSk?>M;+WuVBR6@eX$dYX7U_O`8 z{pN#A6ll`CftK*68Ir@Xzgo8Zs$@1qLO*R*4Im!zR*a~jnP5v^U1*+C?qChe{F>rU zZzv!i;n={l_)tF^&vF_rC_1QYbfbJ`#y^2EG;EJeG_zpdF2`Mj%#9~TSt3hm-2Y2J znnv3kfkc&s1w^E&(aTS>plud zeJW;xRpofYGnX#q93LY$5}(Ov&dm@HW0|S-%&nVtaGi({C(?&20^W4)p?!ATr?Hl3 zujLyT5qFvTR+|9lM6`jT_LBPzZ97RP`%q$~)42SIe|^T+u(k*+(}Uom+3d$BVY~<* zLj-nLetM&!_xS~@pSzaybtfkdBW?HUx@=N92Bu}oPIHPi6cy`~rrsRfE%o&Cv4%6n z$ag%6?Z*X$75C~z`G=By0|yn?6j%%ce0v^!-8F2!T&zaZMp?P8l- zq{QL4@R&AXl6GK1Cv{#P{-{azv@UJf)q%aCNpKpd@R-L`62hdm8=Dq;^Nb46X@O^) zg+F)7Ns2+g;|1LT@R*wHE8~HO2xRDls9Db|KfW1vVM6?v&;Eh*?Z-KSicD~Cx>W;X zgZZT)#%<=5BuTNhKrl2W$EosI$Ps+pOx(Z4!3@5 zgE-&^8Q6@pLmRbGZp_p^nO`r0RYM&K`j2OQQGdv9Qw=@I%WPd1a}l&ft~Gq)h-l@R zTR`G(DY-Fv?!;fp>|BNZ+wn~sv+l*P#=4PBkW5AeVVSW6(qU>!z}d2kLa>v2(G{Y0 zwJq*r?Bq4mu;Y=FqONW`kkif=nPjkR*V%BFr~S2-p(zGluvPn}F-FEKKC|Cz=a7E> z7`J(^;h2nG;Tj=;$Lyc+6Dd!N6`(?CX!eUx_@0wD!iKKMu2xGKsF0q91}?3*v%=o@ z?R$I`nQ##G&SG7ovu_a72x^vf-OzyTX1fT1prhTe-NCVYv3+{6pY&j4;>){{(09J0-z zT1fC#loLk#cEOrp*t{GNqmbNI#P&0OfduJ?X~9(xMAz)3N%FA3H=WDH*n(h;-ykb6 zs5`3b%dmh1)+}|x9WfgBR-{ky z&NIJc6IrIvD|f;D%Z20-$p`doi{zE42h%KXjE#r~@@$u|2ghuDY$xD^T9Q$;74PIN zCM)b7qChLQ6ZRxM1_*Z&9s`0oF|OXRTONq?!K%fQToR75(gz3v-z*dAu1@quxm_-O z&yS`FI9O)nrJICMVwebn*F8zwpkqIH3Px8L&G|T9oV!=|?N{XWuXa-yuF|ii{vnL! zeX`~^p}JU!t}LOgxNZrxa?S!s`TJQnzO8>kFgj=cZPhJ|60?zh;nkQ5xC}?z`uiNy zdl6PE2yxFZQ{53OfHL&ycdJJ7sXc##IxCnLk?pakzOTZg_ARvH#%P#3iTm+V9B7(9 z^x&HU9qJ|bq?Mo-m|*+bf&TlMIOIKu%MHw&QE~K1cta6Hv46$>N*nWuy(>S?d=z=y zfp&XE3ZgZ7&m_{l-wb-MNg!Q}tXv*o95>D~6?`PZVgCmWUIgWLfVdI5wATq1UGj7! z^YqEO^eNip!|KsHv}LFCy&9$JcHhD^-Sm}djWEn9hkIK+6t)t)O27TF*ivH<^h(>m z+<9<4Tdw2sjgpV5Banrq47>b7qg@}AciF(tf7W*7>Qs4hqS;khS6o)?*|Qr34gQsr zlM-?J3Fq=Ngq)RD3Mqdyrc!gh#pIzC+7idPTytxt!NU0|&pBMJLTkRmV`8;3=q&%L z^V8^g8--IfYp~8&>dx;MR>+;sa9XgLKwhC(N4DLW*{^ex{2YL`il#4i@_ne7MT`$QhABt}b zNit0nqe5obM?G|A5{&W6MK#1P*6Kh|dl{aJ_?&8F;dTmkpb zBX81Z50_U|TqXou5#jyj+vd_nLS=irvi#-;WJi0HBdq+CF6Cox4fCUiXPWx#C_df^ zL+z`Jw{F1E-^5Ett7_oEd-|w18VYWRu&6;hIKvm=EZ>^@JF#vqxG2@$i#`N@K3XT} zge9n*5MpSv51~$pf-)szq5g2dHGj_v8qUlac77!yyxu&Bq0SE2^AYxfj~ba6l0s}x z+g(78BUz9B+~7J?H(oQN-D>|cD)!1y7~VIV844@pf-?J|yyCN)qUI^t3tR`d?|cy5 z*85QzPnL0#010Dvw1@FqF4o))7W@PX=p(X4dSXL|C!s=MJA-dk?@qF}hahvvJFOEP zD#&oIj7WbWndS!aUHKAUMZ7~QZlbj;Zxf4vG=>2I_ezpfu|OE=shkXeo@gtQ`8#~K zw2;)M-rymD=-+C*IBzt0@F^RZp?HC=fDp$(zKHf&amC$*PoFftE9II9*MI7Rv`$ef zlOOi`J`ql)1%jdl#N=02^kNA?ey5rn|6+DrU@nV?pG41(L)xcf`S@XF%ZX|bePc+;!$UJ7gifYnyAZc8RNF>vl zf6M3ggK>H|M8AH_P#ExN6uc+&Ic|H;J%Sv4jE>sQW*2QQU}F#xhz`I?a80jM;~C0$ zk+g%~1%~Pnh4ZxW9J)^GMQD+4gdaM)JZ)zws7>Vs5%Fhkc>UBzYNda=?GBVDov?|? zNde-|%prIoXTYwGz2fgwfgfDFc8)3-7j*HE+`5&nm5u3seNP^VcOx^BQA!T?a)nk2 zp=+Q_TE12PF4P5C2KL>m&@dHL!Nf%@pn=qjX+n+2A86t&e{5G;jqFb=K;c#PiuX)+ z6F|1IW|e;Oogi(6XZXlPeT`0?K?y$?T|{3jwEhc4#!0#kLMCs{}osjU||0s){ zS+z6%w=T%T$HAqXiYs%)^XIHL&`38V`6n2H)&)9T3z92XD|Dr1tscj71%72IW82O> z#!mgukQP*hq)jU_Yw2A--yMfuLD+;sPP z)^J;?6QS4rdF9PxfLBMM51cX2cUllu&Xfc}b1#Y^&Ws)&{%)qerR3ep#|6m?yQI3` zU447JF^Rz8BN&@ho4&kCUAJWle^edq&eEU#mF+znE-i5`bEgzL5y(D2yc%4AR3sq3 zMPpAgPC(TU7{OJf;x#j`b!#PG#iUNF!pH@TS`~}*Evi?MCWz5DtPGO_iU5pZO_8*P zV({ooM(2cL_pYrk>lQ1r7z1hsjo4B-_$s;&v`&NaT6nsm>3tOEA4!LQquf z*gl4I4ggvw03O6SUKF{i6^KYthRoud__Lbta-XfAi-1=KpW_$MwCkJ5)*gy?mEb*u z&+*%PF3zjS))h*}Fu;y z`ffvxO?Go^cGZ)G)VjDw5d5!THdg8pll<}BhJt;hMh;4E5hEMfvwO<$j)i^ z_C6EKVhjfxkMCgi5`6;nN<^dcY;VT&rb)gLtexbk9A8C6__umzd)@L@1b5u(^M?1f z9g%`+gXacNX%f8S*l_WNUAs+u zg8$&>uph^@H8jt65~#@b`AXE`-vR?7Kvv>OJU$nZ??^H3uWB7XZ}og{^Q&<+#!3_a z-ac;+#~xq>V2q76?-SzFsKHpSx@1PX3B7y@U%AK_5FVI^)S9&Tx$OH)vL@CoZkjZd zfgRB1de!`~uq)_NC8~^)Q4TI*;R}syuKJ~+nK?)3Y@r*EQEI`Dqwx4=P)ErY<2A}l z()iLnHKuL%{zD3py7O(a%|s;sV+ZoGY8&@^VNFkLNzgl#E$Xp`#p73jq`h;m`G`yl z4*<~S>79gU8}D+%sV~s`A=ye@aAk$@;eUN2NCl==>4!9D%?boI;i8xZpI_8^1CQ}t z;+HoUD5u8tzBkqt2YCbAmOTSA$9p?-bk29$TnU+aJF8{S5qd3IHmNWlFI{RvwA6qk zqRTkk%Tq&Rdkzd{?3rnR9|!jZhuuXLS{abUmO_-TK|47+#Z5mwmO`gw0FzV#3!r6(Pw1oFp{?Io9yRxvy3Sy zizL??F2{sR&0Wx=8iOCZ)7*?u{$NJY zD;o}@B7i5~OwU02oIv|nQzFI*Eg&r0$XY`LyAPYAO?*Jpf#8lyCv{mr^#Ul*!Erp%x@V+x@qB+6={ zgC~DTD+#ci)(%<6WC-?eYf3YoKL*3`zr~UTPwrwt6#yWeo3>h(?H%d~?d2 zVDLJ-Vr?8FGNr9cp6uHZ?Gv1-> zj%l)FzJlk(CcF+_Z%DcGgshXv3)+!O;FrEV0f9!{&VKbvztin+a!|t(=oXd9rRpyUeMk5zvg+j#l5_Jk}?b1X@>&*V*s32$?f=Ui#Bku ztDXqf*49f+F6lSlPWJZymL7DoLb%b|VhmP{Ky`VHmgBfg>B4?(XRbhut{cR2FT^({ z1eB@579}mxK>DSIKnjP@l|;xZ4^i!UIS?N4qe6Qp-kf3*ar1Bs!zvexOB4;#_AO96 zH=8(@{-%eQ3+^M7Pxwb^P!1T1&$d$<)Tt3P3xVBH0B)mXva<;ME`!=oEtAV_ zof*;ean5+`B$U%9XBF7=qims)fEh|6VrAFmx2O$6QC%wfs=Au8OT#3~u?xa`@i!9* zL=jBZ%xtH!4KiL`0SGhkOBrmr_Do6kQEeXLY9gIRerQ_BL?{H5Ihg`Q+(+b#P6x)5<5%my(n$38GARiV%0Wo9O4D<^0k#J)Taw)3F`+)}7PAc4)qh!D<98O;qhGM4#02~3t*WVj1-_*oqZw}f*)HVr3Oa9t zHQOCQ=h}7wP@Rx#Aijc$bfzL=UVhS_P(vQrzC9=aPXhyQ)`xZ-l&^4A2d(2Hp8F>!G6GC8cL_ zbhMdygx{V$o2JXiBj@oi350)^NJ|Quv+a*Hk>DMKmPX^!l?RQ`%E390ak_F^LONr{Uo6~K;Lh}} z^f`?OR_U6PTy^#xoC1EfY2EAysgD80FSV2J?sq5}y2P5Bf_(Vet+jLtLZv!G?TFPG zPTIY=Y?;JW+$UD7A#ZN-XUz~SW@nRXN@T^(j`&u;c|I$T>!z`;b*dsKyJ{NQcleZd zRU$weLhlLnZ7b((`sOe}N9^Yi z!HZ8v?AERL=6>Wmj_rO^M=Yl&xh*(LqkH@gh573BTa;_z)`K{3ir~fjGZ<9nS}1re zzIht?p38YFA!I^`FdY&2O|?2gVZ{gzWDS~bf|P1~mp)nnC1yeXVD!1!F4M+i+)KLK zS142^CQO7Gn5%zrWC(RTF$*2E$afQGk6=vD(i{|N;|eD%uIYfZ^14veqk|JKHh;eR zwz~z-$0&0>(_ARBaJyaYzLJ0;8u(VX|8^C z3+dZt?Z_RQtmKvw*xM$=GQv0gEj2LDKj7zY2>Of=jr8$XyDn%tvkZAC_2I{gsP^&P zgVA^NRY^B|-b|mSo`P`Lm2v^(Zdn}YUX~2mX6Zu%ESG!ctLv}4)%<|bL=e1Byuf@? zu+Ac~lE6B)lE5r>Qgma!aB|Z?LUcpW!PQ#t?M-8~HaPZ_(kvDDK=#n(K8@{uu`gn! zk^~IZ_3yL4GdG}T%*4I=l2>yDx5j6{dv5ka2yhbMft2IvsDaPOxk>T^WgaHk5w?-d z>+i4k!a26BkNhs`Y*y--d$>H|w@gP>GJ{=Q=|kV`KO+4{Ap>vjL36_2@76 zJPtRw$90SsABDZKi~Luqwlr7ow$RSi&Oz@A9S(0I(Tle2R&cB5yOioJuyMzriZ_w2 z6YDEkP$F;*;8EAq(d0(nwP$~VU7Tk$zmK0|Dpq{G5CmdZ+#H^ejAA$C!P6-V@rLI$J!&g05DBXyZL4(h}&Z%P-^8q*V*y2ZbO|#t zacv5=wre5?kf2|A5Enat9(DJ!xI2IMlZDjXLwJ|a+dcyC&t4MkXasxA{-*!g0`?dV zUA=_W4TN7NqncpE>Gvrl0loS^S3z94pT6Pe0JX}h-qbt-1n&tz)2)K{>AoHn+?)`S zPlsLl@7OW0ju(>aG8GXCR1()Mi=ZBgfCX?b&r?M{1*vj>@t8*3&HbwgA7<;(F0EI! zPpQwZ$c{G0E7buNpi&VblW@28A##QNIZW_k_zAOhi1P8bsYCFg>fS}D!(@rltGC;6 zgLehs5hmzVCwQ+c^nra!4@$Io2+2A`;okswz~lgRdFHxiIUz@FMUVix`#KR@aUC|B z-ZMM2sL$-r9=7{x9kF_lvyQ#MFLn_V&s<#iEAgRgsfYPU%i_&?XXgSLqJm7LEl94X z!m>u2l>}%&RVRj9*W|^m_~euLBY_dfHW%<%>DW)uvPi<~s3%d$I{eNlzyUE*Gg~+) z_nj7!8W-+)JOtChQ$oXZiZ41_od_mQUW4HHb~>2;Y;>W4pz-U(Gg1kAC@G;g&$Za7 zH!3dOyjxb_Qvdt^9TxUg2JQ zLv9@Y0?FzdDAVtg8yo&X=h+nE#QaJFG;QsBYt?cY5zlG8$kvF^S(?T6Zo$7{M3!p&8b3d!3$+I4#$?qLS%NH`aaUPa<*@C5DkP$-ST1Q!KM z!1^PIL5CZC#SuMhIqCe^8SXHp0w)9|=&pesAbKXC4&e_S+i!~n01)Eq z@GLCM#9sWazTJf5YW8P5nq6F(i?{B}J^w7}`uMy+@y1l}V0o@(K6+$SPgl-wAyed# z7w``EV)GT)Mv3W|sNEnPp3^Fw6)T#3ZyLjf{41=BuQw~W!bXuM&Du;=+!OY|#EFUT zmrm^U@1{bHVqw!ZKLS8=r1pA~FWDC_@(ga|HKeMtfHo3m&4?&o%Usnr!IeX|;aM@= zg!$8_81=O+XnG5Bm3do}{k_uQIvXcoO9v4s&;0yJ3-jeJK;)M@28mO>UJTP0yzbo# z2RC)#Lwc{|JE|g=+(NZp_Rm<|T%mzbX%HAL?8owt~ukJ!~CtT4qlah@p z2aFuo*lqW!*B#+KrZ@pz1-M?w+g2G{x9xgT2dL6!2Q3cYw5uhxdh|@1_ze%<(nqzt z%52I;QNS|T#U!)`TaU280dUpUe@E1xXqC3Hi}gN=_g~)omOE}#FD0?EI@P|J>tt;C6H4wI#&e`$OBoK+>>hvVmG$lx z6qnY#$7ms5*H>y03S}-mDOnCGBTFk3XEA{*PSz=dX2Y!X$^x{VK!a3Uu}yVg+qSwS zcO*f($AR@T8`0^KbZM;|=$N}IKM}18T!W~$?l9NHK|C7vRVlKa&}%Uen8V5}sVVCiy=ZRzDjpVwXap+LRxhLc{KV2o6f%W+C>fm25$=awR zfaCb3#5GeZS5Oh|W9B{SiDS*BMVN84^GH?TQyu73cRIWEm7%@oWY^@r*eg1nv>Cu1 zY5b}8r&JeJ_+J22bCZT!Vacj(29Qj!Rm1rt{$*zLw(K@vWg~ku0;tYVj`bRzI^DKY zyB^$GiTWxXG_422GiJhR(3VD_chgg*+a}QUQ2JN}p1FfgYtUZ$e)dAEmI(}yI2e7j zb?Z*N5FEE{D}9$BPAn_h(nSQCGC%7KYzs2Nbggw0JqeN<%C%f_`Z|K!baWTxeio-( ze5Mn1jseC$MA#2O2}qq7i!B>al`tE6IU9H;XMN3Za66-pZD3i(B~pEYL&{gj&2ZZ6 zAV%4TN>4Ymc8iZn0XLOT$H~E#>SX&u^fg-8V|SC4Fo zo{b-3zDLB|9kORn)T$p=*{3RJdJuddmS-E3RA<>W={JZ`PKn?$$bfiyTPeQ4znogQ z9_g5jV`iU__*;R=$fHI+P!*b=rSE1cPozSo>W*ZIv~ChE&!Amy=&K2sE|jRco@8SS z5B%3qgG48=nurTS zb%CvSRCG?db29S%KkXhA8W_Q5+;=SBJ+bB4upaRD@7iMsSM`rwwJFd(NN!030u`@n zSp5KqcAuju+CYK%sKG|rp9b^N;Iqg%Upd&bEX^L?@Se7?o+F$9#vd?x>WG_2ZjH=! ztF_CS@$lYQi#!Cc>pzcOjl`>()Ip9pb>j=P`fu>q@3yQ9K=*I2u0nfL?3;7jU5qeW z@JNgbZwR%0#b2s)5+F~F?|Of32dGE_4q7)6V{41Jh8t?Euq_89>JBr%N}4)jlRo>f z2D4HGX%*5UjiC)bS*oknxe1m}I?s^+kQ>k4JDL9q%~VCl@Tb&4w(Tw5QT(sdYgp$O zh_3w;&5^6h+jqOz;TQ3`{TG$N@h#ZA7Ro8W2`}mkFY!v}NAMP>K*7BWA?Fq)XBanh zeH%LzIag^cs@<N&yi3WMiP|p@OvGyZ$CH|S_{;+ghCcY(!-~dmr?~)j_GQG$s!UkS$cFm-JRd~T$ zNG?e(L&=BDd*HB(Y zLs4hZi+N7=RVNQ{qc=eL^Xd~fjUjq3--^RT5Ght4J-4BWS^m0T&yt(%_m4Bv&dW!~ zC*If=m}>d8;VAg$1Q`tqdAF7z#ma+uHt}yG)YTCtAro%_z0Its)_M$8#o$~Cy}TwB z6{7U`nyEf#M#biL>1Xnt8lh^W;;wEb^*`vQKY0tbzs*Gf?X&&RkCOW}#`Ep}BBg!s zHHkWl3@++cwURPfiP|sIcgP8^uiZtsV4iFBk{|tOJ84ad_+X*BjDAzO3(%|&?r3-# zAYF~>_qA`LNHM5O{L`~37Y`FmLAQYaH`A&2o>SA?qq+1^zbv?NU<1hy<^ttZ!s05q zED^ySvZY>j1x=ehtBP%O-pm{pLCdmPR^DwK$vw>6iJGcw{*<}n_x-~VA(Qk~az%r7 za)7B zP(BuBK@W}dgU72v+|Cp$O`Mu1?-2K9VHj!eOP~6;7|VQ{RoOQDu}YGN@O?t2Z*q;(_yH#a!GaHqM%(RyxsY zb(le^79--^fkMmHNbSdp1$mp)i0aQqJb@0)ktlYLr5`H}53V;x25Bo~ZHkuJSfNq&U`wi4|%)BF=>=*7}Bt6>B$0w2(VP60OvRxkdnL zwK|9{RFm=;E-bY=3Fr1Q^s7x}ar{tJc_;J*S6X{NQq_7a0(j_BK6{^BZ!vF*{c&}tHA$bsj&zgHY44p%L; zmp8Lth0emUT}86LvGjTV6yAh2Y){7DJn?U@S5x(P-QnwNt01}ZxUOx(^S>Ng$=vFi zf#x(%WV`?f z^9J7kJqa$J?3UFI7i2E_6cEt&*!6dDQqH6QOPbis-)=3jJQLM8ZddOU+c6(bHUnqVdRP~5 z)hZ$5x<#}_i~P%t&a3%H@WzLoRaK_%cc`9&dK&~Ab#Z!GA#|#nK=EB<&!6O^*Z(-I zfJ_cw^>C`YGdD8-p*{aVA`xxkdO>vjT%mR#MyDq`guAK>GBf}84N{1jd!|ji`N%!S zBN&Jox9`A)B;26C<{kn+$O`@@Z(`W$Q1I|F^M~=(Bs6Nr@Wig2?5E-!=XGS`0{-S+ z*h9$K)r-Wa4?WYS#;#oZJ$s~?t&bBp&urRCbh+7me;o)ggo$gS#lU#M+eGqu#^%Pj zj3He>rfRcorotZT=U)4Ad2fKf^xFPxeb=Ox8r?`sLUf$(g!>%);J@I|lPKA;%VSjVb0Gh^2SUW* z8vaFS@3&OfGo}9ofPsB}x`BHoTUueNVEWohYi(NRDy-hp$gdUBV7}^?Seu$&UCOnw z)=iEl*+>$?t5`)Q3ZN>o8@vYuLm?LYMl6D_Q6zxZ9{`9(=7tF(;$r|ltG}CBko}D- z)&G&@=yG{(({%AYzAf`@&MRq7}?b9tLuureU6l@3okM|9^4D`^G?1W1{+~<)qZFF=f^P-hZ#xm zqU@LYe*sMdvirG{uL*8hGG}thkVAGek1b(e!$iCN;>NEaD%apeFVGapG?k#Ha?M)G ziXgN*CoUGEBN$~-&ZZtUWDaW8h^_%yz zS~Ry5f3ig054f^U~hYOU6L&oNx$pYu?xU;jej^OR0-eZkP=x>Qb#%`uA*cl zM00|wQ>>UBR(ytJ#O#Qq7#qmyzBkIo5XPDnyVB3GrtPSvSR1LWe(~AR={W$PM9~i8 z5;u{M@bODOz!c4katbJ6NEVN9&CfMi;pS$FDPs7bD7RO{ql7Cw53%oH=ID)k-fS2# zg~BQ)@<^4X^@;`nG2rRF!YzNVS5_l7)VCEir|B8xr0Avc>f<1a%oAsf9M=gMIqXI8?9`l0v92DfoN=}g4_tl16E4` zE4_6W%aEOd7d5J8&~`P(!JXuK?6+5XPXd4%F|r6+yw#dYd(#TH8tCZ@H*WEa<+{tg zNQjt=W;Erdv>h%Ib<`X(x_YzFA6$T48?98JeOO9B;l^WR8+@h*J;CaeA0`3$W>3P3k=}`rAkafByBC@1g0~wZsWb zmkzjHM)8_pN@;qhzv!T2Vo}1e)QgUf4zA&Dj|bF|n+sq>9}Gzga+y*P9UY>EB_f8? zDJL#nHvCj4qu0kHLX>E{&e?%6<7quyw4kY7%o89tb8`Cb3wh!kR&Wc$h7Rb#v`}~* z^V9oyqQ}jcfe;;5$DSVZ3zcFQCKi)kh4f-|2oS5}aWkeir8$VV7>Zc@-w01L#q@T= Wr5>?XR8~YXz%lrj<$nMG0RR8Un&?CT literal 17606 zcmX_n19T=qvv!P)Z9Cc6Ha50x+qSu}jg4*Fwr!hlZod27|37n{?wacAo|>AOI^ES% zs6aqKRWQImB@mF+&%yFjtC~1ES=iYUGIG)}(lHPUxmZ{m6SA>05HfJmGcnOKF)(rx zDoGMbTR58#iW*xu|Hyi_|96N}zW*HwXan}Y^?%A?k^j=}z?VKSSvo2%05GazO4J01 za6~#He*`GzMB~4LLv74XiLjGV+|1B<4954f0%-#HJg7>dBBG)qBBI5Sktx(ojiQ1> zG~YeSw{wx`3FE?+7NSw;G}OdrFWDU{Z5LS$Gg~K@PC+5{6tvw|8m^AdoxQWx0pMTpAXV_ag2+lIZ){y^{dW%hsIK~*{u!!9=$wXzSO`z&H zw7sV>>7gc8O{7!EWu?5R8#5$#j)pG`);M&ta2?f37mP0bd(CQW)s|Uca>l`f&N^PG zPd8hItJB0k*XDcXIYd8-*0!;jzkI#HdJqCU+TVj+^V{V@cMFG}-gl6-gTd&AJjiZ`(tBfm}S!^$E!ubH7z$8uX z90r3u&Mg^v2(%flnIM(poR@2oPMN4XCW{dqpI4kB@yKSHA#~5iz*br>DWsc7Ed5O1 zefEELsko=BDhTtQWR@s@5L%#mKpv|Q#@2a|(0!2HPO#%tjF-r;$SR!bGXlcVRt zWBXW$6njJ3rsj4cx9es2c;*8Il1Cg*w~;uC$Dye^lr=fdVw&@~52o|EaJ>=wd=#RE zjWC7O%vR%D^n^6@dHx@&c2<}p&eiAo@*;&{7vebAx}kMb=n&YV*>^P}CWe}z<2Qz1 zqvH6-=}h%Un5Sf(*(Qs_NeKat*f~UMl3kRO>auit+VVC0A(av#d~iaRd0goC?dH3b zLw{1IEI+hwdj#2B*`Q)@!6$=+QDJC_JlG6%&|!Ll)P**8nDL=-54_QI>i0VbQxPK) zl_wB=Wg70z9LG9d)pc1S>FOFZs5>u6wVZsl7JZKx)wQca|rs*1+y^v6g#9W=A( zjx?0UV@FI^O*?-#7%ZF~nxt20n^!v~^d;>HN_#b&uPIjLKz#R9-{S_@`2y&?n7_!0 z-@d^WK+ZtJHwfOoW>|H`)Blc~M(CTlpW~<9$!#IXseGr0XgRVjycOwX4oK*s;nVG3 zejtbM@$JXh*nBLnz z<}5yyffv2=r`*K2UsTy()MmSie+I7s*Gexd8w(ToUafGu#=o$K%8grh{*G$lU-7zk z>^2-HO*q+MUZs56vsDl=sZ(I{9-OuP7gtm?ay7?C zBKBdx2MiTxpj8XMNi`I7i)-V3S5~j%9uhW^ROnKAcS#N|v1Zn77Av}Z)#G{3$tvu{ ztcZgUW%X&+Pe2p5DCa%ktHC_DQ}G<{i2jGuZ3Wr-$Un?yPPO`@yh_`cc?;`^?!&bi zfb|B4a2fqmdKU1fg5=?{}iF7BglxkIuva-~OFj zQtmhG2pj%#)vzBqPo_Hn14e&pG1Ka+;oo&-^J4Z}Y58@JRYI=CjgrZO(pfHXyE~m? zArP2uZ_b_EZscOu(83UZ&rn*KmL@;s(OU*zsj)_bOW0KohHyG8@yjN^&4xM*<(OZ8 z&^^uQz=1nrPEPZ&BbZhYP}g%5PYUyX`-GR3#G2S$uVc=}3*j>2g1bcO1^c@;{2`%y ztiBaB0cwVy1HKNq$9*lFr}UO6`2;8Y8k-}ppkhkIWy^QFu9|aDEkSLTp!=hTMHgwN z^_tZjJhX;2u^pVk2Q31flul!ASzN%AiE$ZG$=&P@EUU;?T>UB~9}ypZ#+#OVNa;wU zo2HH%sK9&O;vZuMIP)57EABBw8VM`%ncyQq{+cU}!cd+IbOb}Gsc0D=8NvTN>D>m1 zdj_UO#D#OxD?xm%JlOR~d0|vvd?`dPPh0>=?yFoa7aC{L5@O~Vat`qm^4p>bjDuJG zZFmifopvmKP`^0-a1P#6H_?IMczUR#zB}B=)M0pTLMDtIb|mh+Ww^$AQkwg10*Q~n#4lqbTmpmeM`0PpaNEB5ZPOzjH7iv> z8aTlu+;J9L6n~P30o!$4t$+z&)m@!njk_*Gk$+pRY)}2;uaS!T3CRrM=j6((TuAm* zt|_-n85Os4O4>teOILyw{Kr96O1Fq_%Ad*veULj?#obKHdUlIcsE$-^Ev$ajp7^&~yN-6Qb2*n*M{I z%&!E=wxS!Egc---6XIn=GN@Ri)Qh7b2`j~L+hhy&GK?apk!Gy;o z*J2u@;JD5^RjvV*VGI@uOHO^}Qx9)Ix^+Qr_Zz0Wr5IactM|HwQ2=y%*4wuQaZmcU z_LCXs*MwIss|d6vzemOseXpCh6UDmt4goBVr6KNotIzN9yWAi7=Pjk#?g63}^8N(N zH@feR#|Gb|RPtOWn3q2mM|5AEs#)ZE=MHKp-vTaL;*q|64{y;wH=Mt~mgbr>t(DQ#-zft5ThiB z^zSibGfM?!4lRyxw&i?haS@Xpk%6NRf$pH>zmg-K|1~?ownO>kEbDY4O4v@2$T&<- zkzQnpH*_Hm!F?R2G~_3?;{BPm>>~ASi(K283-fFS?G5-KfPP#vch%e< z<#N|1z*7hNWf{>4MUocPNgwkZbLy@zp}-7|;$osFAoi3^f|sppnIf;C$oA(08M~7C z?cAY(AQR;y;g%_HI5*Ysq+ki62^d2zswg{Es3&)!H~#ZmXs$}95mZwKZ6QX1W1|PZ z{7Nrw7+wOPgsL8j!J3NIj{7VnsH6iMU+yqur|13(9p?lRI z*DGx~7nB8NA_({I66AJz^1xw}zPDNX7n8Z1HAj?*hbnpu)@MKAa2+~zL4MFX)|9zo zIEzTpXUZanc=`IzMr#^_R0$`el*09~gw{%1|9t{J$8$qFh{dvvh1 zmSHIr=1X*xG>@dqDEWNc@kYORb4RZ#I!1+Ng0@~#ES#mUn&VoB*C(_Ru3^;zU;L#9 zoC;&6F}#4#*#LvigEom-fHJ8mEl3F)iQGTz*1Yr(+}bn2%B*)oZZvIDLwZMj+u5Uy6Q5vg5FR}vUZ>QYnK zG&7fPKu-TjcvNV_uV}{ON>`N6mGedT_TW3u;mf(G&<9LH&N`a%fS222!j`Df?hWNK z%>IVxk`J!bS<}EUGt)`Rb}?{Wp1!QaThrJ`tgNFGF>|2yO%7qbwKn22O3c?_wy)QV zHQ7A~H6x5k__`ShhYg+6b%H6}%0w6Qg1N&^Rqgs+5u-n8N`l$21|`-Jb2sikx6Mo& z{k&~!&=^MuQ|P0tiJ407MY_Jyzj|eC>{m2!#j6&DD(kiZRodYYys*X9e`brn=iCx! z-;N`}aYg$Gv$SwgxO`0lFNB4ZH0seijrGFK+2E0wwbuD(+IpMRjLq&Zb0+(k#S8gz zmHqba;CK_K3HGAxFO4mHIE^j3AMpJ^_6NE@u!YmO@@?Xp;7trxq;-ORM)yV*eX+2< zw2nd3VtBKb$aeZTcB!!#QNRqGf&#O0;#42CwOB{(!z*0{$6+;Oq`~;Ti9SX-&lX&{ z#wA0@s#OZD-r$nq|Nn`ld5hU!xY5IAeE{G>HlN~f#*z<~;k4^HOrv&wqv*5k=pP2t z4`U3oa47Dya6Rtw50Br(?pXZN)x-~`elYWcxgRY2U@3lSU+p!4L|JGwgYO@iI&C7h zJI6l@Rb8a9RZZZEt|mg3q;V`b3|VFTzsU(Pv!`W5`Nv zY#ftcjDw0>QQVQ1S?c_`jJ7qyjAFqu{ZmQ1evUwUlq#G3|<|3lV?fexa!`q_P>cha$Wnjf`3mn`z zy1IH++MN$jQNbXo(4%$Zc!C6(Fv`Se2dgLg@XYoc$e@>n8szCE}C&mRkOa~IJ<y5>9oMu~{mSwVx z%Ok+#W#wK3iHa;A-Iy_4Ne+A|^JKK5j+?8=!#QpGCh(5Qb;9lxhYrLvw-c>*_86k8 z8x-Wn>G4X|nIn`I(&ksET4s8SpTC`9aNlyWI|jI8whg5acGn`ObU)jr^Yl1wp}k0t zxq)TF^5fAY04}TJj5Sk@`)h;2HDUs4n&;^El|cH@`KlFrrQ5c1$)vQ6RQi{PvFRyj zmMq5!dv=NOeZ|bY`y~-1yXl$qri<`3(6a1s_IY%v^IIPLVUGWsaCq z2iV^kE;>e=Qxw|R{9VgA*Nc+g{zxm=WzNa|b&qk^im2a}Fmh|QTcMij7}@pNao}Ns z?=>MVcT^jRUJ5|8l{%%?H@`%Q7evngDm80Sh*>xH(?D8#R95_{Nohnr3<{;Tvs+2U z6GCSsCS?J_^8n8F0ET%0K|ccjJq>d@4x|1Tqn3p}j~ne4NYZ&=DGVDQPTKX?)Np4l zyr%k8iY}os9GgA5>K>y-&=QwFr<^1q%{9B>r@BU4S7NUZl%0$rkcK#e9wM?Xo#m5{ zPs^6}d9uE>zxIXsf}8@T>Ll!PHs*{T8Kx6s=oQ7NC*s1U{>j#w0lQi-(~?UAmkjg5 zu4jb?g~Zgjj>UoUtc`f|j-{kG00v*WHfni`n`3V1tS}_eRwW>d2cyNFn$A>Mwjw_x zoiDT6@jFSo+%PC`84S+s!qlRKON*FgX?>>YA5p1GzNDjJPkLpdsc^Thk1d;1EqONf z18VWJS{-9Eg0qcqHrk1{D`;!{ABG^xtHyp#n;YglD$MAHxo-K%}nvuc= z3)Y6EeU`Cl2-BxP<|1qK3Fm`H@FNH{&@D%tO3tEV`!&TDXt-}W7q>?H$8~b-EyPh8 zU9+P`q_*;tOQi8%rMvO$D;f2R-6u=ivr7%vo~+DrIu4?Qt;ol=eA8x~dDq89NXLfB znQPk5|7Q57HE8>@E9$CnK3duBk4n3Vxka6Lz*l&-SgmW1<1Md*ylA}6jBVRmc^jHp z2waeTyTM{oQaWH=GoM0bi&})+T~3PK5c($@gf6xxh9@6{D)_A@)kV0fK;^$R1vtvk zH!enAn8?D%R%u-|yGB;}Lo}e9HKh%ZN25$NeznQ=U~SvpYHpR}a+k!ux7QBpa{FYM zgB9|kYr-wlv2~iqhNvQ3+!QjO|?eQ29ub%Br$V|nO*17OgmrOcoH1&ZiC?l z_W}&oMbWC><@5LEsZyhb(L+zlN?<$hJWAPgvD-zbFf%A>%hjg9oUVES*A)Jk_)6UP z+o!oGi}Te=@UEBL{VAiDUEjlyD&TEMI6G=x4*$m7?k4Io@MtiL=aFot`x_*|4y1)k z$QbiFXzG%&66J|kX}uO>AgTKu(QuQWY<9lD+o(6C#Grn@32*S!=$JL;jfau0Vy$j@ zAzE&HlpcVHt&~5cG*$T4n8hI$+i(k2BYVJgl*W@ZM#=KWhJ}hm_Fh9V0bCu^c4*@Y zml^glY$mCW+32Lfsw>0dCjFVNp8tTW1NMT}q-ZLc^49=u8it;JtoI|n*|O{PA7ePE z5E3Wm!v``ii2K10_A9(l*z2jLu7@SY2jm2}ftYw&HMsD&iD%yG46ZwjuOityJ)y-tuG7>D3Jae{WfI|AGN|}wOq=r%&9dWYXt)0i`o8!e}Lvnd0FO={56I0j@ zjM8H@#jxpQ?LzI8_AH~Br`cgIrM|+M53Gj~n7{N*aWA7icAYD=l0IMt6Ol*)24#?b z!2_9pz}`3z2Aga~ehHwc3mFDWh5rr*Lw@|q&WlgAy=fdU~3ce687TT{QECnPa z@+%TRlWKBmOo5#|kf7osPRB`!pOTLIQvD`W=%K(yjbFv7PlJtUSu>_$>D6TgnzIud{BvRqwOwAApA$qnL!gpJ!Rw1B^Ja+HTy zR_qDqigXZ+V&}ySiiRkQC?LHw$vudz^xre2P1XZ(3Oh5P$L1Cohi9LS@ee;KlK&}L z+a{_cQNqh1aloLI&AJ96G-)TlP#?7@+elqh$8Zxl_i{qkT$Xz z*-15U?Jh7KV;f&~b!ud-Ckn?`F|Ba0bu{SwxHP?#hcyBj|}}LwqM8 zd2~FPi`=j8N8}L%NVqvVCx&f(Ll5~OwXao7-Ie{hVWuKTYDYK<1AaxE53|=M-W~;^ zs@=O0DD?|<@aCOIi3fnry9EU76gRAqH^%v=W;&7n+k;KIfd^t-e84>9OC1rw^-pTl z3w*XI`pWylJd29=1)};|i29UE$N|CEg(%2!+uKpa)r)k7nRh746@4cz;uqk;IO`$F zj(gNCvJUc!??yVyjPHg%!%46ed$%ppir0-y+Nm+=Y9aEWn0HFh4SaMix)FcJknjtA zq+YfEeYwBg4YK}6V#Pn!TAx6#?u%-C?f8-E?2`G#-nCPAX9u<{7Prui;FUV;?qLy3!JVy-4j{np9;!7W8SjoBZT|Q*|CQj2 zaHf!R#uL?VDpH*GxdcQVR}T0v2!ts}s(C@R&Pt_#s^K0O)f6AY-W3*=#DZ zI@@QJN}ZE}`Tqfkc<2(?#$aupmQW~QOW7E2b;=_)ds zT5K1!N^KO@JURbYO?Ht|t=m#$WjVDzJ#AR6M<0PIm3UB|7VFe=lz?D{;+Y=PV>7oXU!PhP2D24`LXfgv9n9-%{2Cf4l~=Pk_V{g%@9D5-uS5(DAn zhw>s3@#&2%|Hz@MpqGmH@*Wkk-VYQmQtlx_MhC+(w5a2)O)6m*(yR4esPZ=aiMX2b zg1~t6zEYPs^%4aWHhqIYtDE&NEQ4BeG_#lyxPn`Q4D=$Ut=Nz6hcH|Vy)i6zhd&^_ z^}?7P2O+je9bNw|OhXwLDVxiAV;lVj=Ib`_BP-bc@*xlu2aUh{5Dh2nLfqN)@R9i!|2_R+|{mqU)`X+mzdH+rdg7P3)HYdA5&KrnoW^hIrU?Y(L7GOq|g*+p^ zS#YX2on#i)DZ*(yjxc<;f{5_b@8KE=wBDviWOL!rFYr_Ga7|5veLXS?OK`jawVCxV z!zW_fTOO}}W6?MOWdt(K$YMlT5T%V@JcrF*;keZkZJ#w9)()a7XQM6%rUHILK`ax~ zBi9}gX)S&C7N~~n5BKVPPZ+@(-~NUv)d}^u`t|MCo7ncyu2uw(pIE9{vKr>*O@bf% zJq7U>%a3ERR@z29d2K~H!-?+(M_Oa(L>!*$CKwsk8qH(k!8z$1XD;c2jg9h!jO7$7 z%8A3&_z1eyBku{@`%dQcrFvacyAi7-o_R~=uH{b7(h<-KJ+LE0TYJfLoJJ|C)0I9L z>02Vcy$tOCHJ^!yz|#3b#0xUwXA>Kt7k;piFh2uHUN1QF>$vWR8!5{6+JO2^y z3w_r#x)b#n6<#9-K#`CWeP=GpQcAGF5$go@(3Lq%COy=WWwiklxaG6nQ&G>yNa=^2YS;ZPx3VcAaBdT)6~61;0c{q`3-fVWfkuJ$3Z)? zv$QJ}G(+c1yWw8p1uYzs#I>3J?9^Iswa%W3F2lgyXq3eD$f4YE*4BRX@-_lT; zCo=XdU*as)Qw9RC`S}W&A{$8_ScViAa|bTDI?6DF-InbmAcMn5vQV@Aai`Avx`KTw~a-aljY|rtYZY$VE zBS9~bWG;z?_GN;0c=^bwst4!q4A~FiZ}8bR1~>g87EOFTMpbHrm();*P{>g7P|1VB zFPCyh4P#%)haERXSmGY&U8weN&SR{|hOhbfvV2cDIA{THANKUz;rmD)ca>`HJW zSTuVq8es&-Y@}5%JDF4A_67>7n#CcU7YCN6sZ*V@^HTUej=b}J(L(z)B^}h3}(QWd0QmtVcgy%r#!^G8f*yfEH*wLn0GC@ zY;wQ3^zTyNm`a#Fo&d8jpZObK`52(%;>hL6_q)BAB@1(*Or5K zs3PRfw~jyWaX`M zorPXiCxiz=y;&2mwL5W7l$@#yUu34{3!dj}a4jV|0us(&)BQN!seYuVJN{T{mCOIg z4Vd);e!4&u-y23rh;m||o`Yy(V6Wf8d2=M>#W7tcc!%&i4FSx`y$gS%$$vJvIMbP9Bc*Ju&M+AGib?CC(`YsfUa#`Qj&H zfwfR9HyK{IQ>`DHwPBbET?ZU}*gI44eN0!F29fye!ChzC!xGsPf(|4`4V+}1YB)Zt zh^uy$f1!4_DB$DZsPjz@_X%R|%gic&8V1bCPjS_HPNHZu-oNH&IlaH48yJ1Js^5MMy)4v+>!Qk)Qc}*2yXE-GGO|c8DvLsg1CdknP&%CKcvFs1o;EG)&v>9I)IF@mEZq1 zwqWC`7kG6ljAoZevel}(jiOMGYhaEGVLnDryT9Q%b(pM27^h#0HHOu<&(T-dy@I@M zx>gjy3d(K?b@`QdYT!SO0j$2wkKv)Wsxo>p1oA!#{}HPhZjsX6MBFa_S8+$vh`U&l z+d*Fa6e~zd!oqXrMP&>*(6hqZW{f9-w^!s<^!FOOpjsv^4PQ1&T#zH;Q*`!N>H27Q zoP{QI;Vn@9dG~J0M9$>Vo$}p09A2~GJ2)S0%H%QZ57eoaHdZe!d5tY=Tn~P@mrA8n>9s1tR2FG1e?Sj- zEnsblFRbUy)&PBOFH2Nl%eu5f$J8nPu*ve1gWgfloeZ!7=l1rYY#+JD1AbFeiF;Zh zy&t;kUd+X*dClG3*(sDxFYb1f9CC+}5_7+bzMtCt0;(iUczKDFUZ%(B2mb0|poxW_ zik&*jyi_(=Hz!%_=jhS2Ns#988_{{R{(jZn#F~drF806?L0Hhvqmt>5c&v2v0&wzJ z!roZjy}SvQ?n# z_&{bilW1e_pmpyO$AuGR_%+$b2b3f+C^^~1>=O}WEhLlI*czqX8jO{VTuek*b))MI z?ud#%n~TqWzqhyd5V0Mj2w{)*U%+-iU%*`=<%=I7d#;m)ADOGYVdo|{XQ>vTX1dCUVeG?`q9J6($$M#tO^rkQ#-oIEmh_-hq*en9ec9I_Q*#1y* zFD+k^9(CQtb8cuhc(qkgbiCY4qMcx6FND4G8HBJpW`bC&MQw9W&vSx;gTYZOThv7D zrg~h20JU;T+YU5FYB+!WR%Ne=v8iEvN>sED0fcY+;3(egTmS`;{6my(30}~@^((r1k zNDVj;)OK^b8<2e!X`ykVuqGn5c&uyMAvfq8{}9k2W$QPW=U6>Zy=mn~&Ju};HLr4D9_iN#E$6he9W`uT z{8H|2)*3a)LFMK&Od;gvnl1JXmxyu^dg4+(C`QC<+x6Wrs!uBBR$ASI%?`gfb}M^J z^)hCDS*ux0T;8|2jr{ykqLdM}k{GMh`PkHKf++Lg;Z)c53BEgS?MsM@&ci@j?m(J8uu%NID%Cgj* z#sF#KN|MDXUtR=7hJcr~{1UEAUNxt-u*IK)&5>ouN9W1}M*6mr4RZOjz;!84E*lUR znbaSVvs&my)-Be6^^%4wORj^_;kWHoj&7C!Cv-_J%$(x^E*Om8JeDRF_9i>C687ig z_5Q&BT=5>}`y3+=P>1t|&Hx!oSvH6E1UD9VW&#j4TV$3JhmE$jI-1H^eoBv;gJ`!p zaWYwcCN@s}L-KoTsM>~@&PturJ8sn;6lN3c#|2sY)(=X+J8dZ=S<7w9qd%uGWc;-k zYYN&Z&axNUiLSB^)e$_U9O;`EMupv9onVlg^@|LyWZvM3gkNjw?!_XCOhHt*IYKoa zBt7Rbol7`x-<=8HJ2-Ewc850Gqki{dzFRmR9qjk;ghrX{XS#n&Tzc%>X}(I>@3po^ z?LO2VbGwp#M{qn!+3!2HM{j`B>*)QNk;l{en1oEO5I=Fg^6fy9_V4AgG2Ur>nDcnP zhGJ?IJt~8xrcr{9EG_g!s8Qt>hG#?(2bIK0%p17^y_AJt^EU61ZP$m2M;$U6TLiEP zIuTj~1uW7FjXj{m?qlRLTP#TL(;%yEXuZ0cKp)p2s}sNUca(s=j z$8C)@ZI8+UV`Y`XBSaslT-+tpb-yAeA2jB_TZG?M-syb^^B*95Rq{W23cQ>&vZ$8x z3(B9@z*io^TYJ1BCca9QT6BMC`6=;1QUZ89Cw73B|FYhNszSei{2=THBdXBtNP)WY zH;kYI?uSJzx_BJFysqy)`OEG?mLuB#sVsH0sRVYfwvYS#Q(^PL3ed~i)uK94|;C^8oy$KCK{80jQHhY0#IZ>-Bi^YD*rEzS})<7)A10ztL)+g z%YRIZb93%5+LtLTQvf*uc)fm$8c2hIR`ZPFf20A-X7E2& z_+TVKhUC; zvrRt^M9#yu24J?~D?jrqUkm6dv#jNvX6qP%cZ9&Rn*WhU;H%TQyJvm{bi5`%l%4)w zb{NBWWvYUnYZEL`FU0Oy%y$mwjf{{N@-p=+zs0y2BRb(0o&|PBxy4$W`)%DuDS^o) zzIn78#r|4K&2FQe3Wl$`8`QmL`07!N?osR+%NS5Ii{NpA`z%(?IvTrql5hdb^c@lx zBT!%CT;7c`CMo`l3uOB(UdZ-F;^I_y_YS2(Sm2({3Qq@nv(`oDU%l(VGF)bfU=svm zaF-k;pM(dH;mEuZ*WHQ^buvYYTy#t-7gyYGmu5G*#YwJQ@>>=Lhu|*!o6Jy7Z96D}v&O%@N!V@*noChxL6C zS~+pwitg|G5_EasI8?C+Mx2<8R5=O7M5sy%=WZVycw9ewDfw3vu&Qr67zZXO9C&K2 z9Yw!)4`(I(>+&(tG`2n*OK*bb6aWR}Netnxo z)Kgdqjo|mswD)sBcLAS3YYUVcIKezs#YuFGk`H=xTE9rSJT_MAyCXuW=Cm{Vwm9Kb z72_O)`;c1C=0?u-x-6BRzPQF;6*>9OM${5Q$sz7QM_-3kMbE;GschJ|NQxP22Cg^= zX}7$lX5CPQ{0b4@Gec%~K-TB>GE_dh4R1f9`Uof?z7-f>{ZNCx(e1zSU)&jw8W?h5 zSU%|R?Oi-SOZ^Y%zf$ZQ=vuhrf9qlUf?z@>#0w zl>NmTV^iwR4Paj@W)Hg2gXJs5{0te|bpkd!`YbsKQc4Q?ou7UpNoC(hYy-hRXzL|* z^bmbduD4`U@+sf@k81sZ={!dd%p0?}nTovdI<=^mR<`H5W$fuwc(v-9#WLuVVZXAA&V#y$D=GXMM zi|Xg5g}1r!R+*4lGvMrwi6@ptJGvqtDc{EX4b?oG2bqEPJZ^EWN+usI-y_L;PWAbnIFq#8ti~@)JX4D5PhNexWm;c9?39Ung8sT7@BrAVSd^S?b^{poScBP3HN_R zGx2Ti*ty_`Pkp|`qK~?p!5DW|fHToOCC@F~Zg%*Xlr`-#jrJz*H1DP|U>6j&na14X z>yacyP7sl#B~>KX6N}eRS-aZ_exmWc=7f6OK;}Fjt#+1^zv}xs3%hKnKy1Bs;i_O7 zXL?)|b4mDnVTTZ~mw&yVQQQ~elyC5*6IA`~VdK|411Ot59yl6S&3>mr zcVWm**qq}0TtN@&3p}sE+LffaLcuW+LAPmr>a9v`y$8%WRH-ujPVz1FfkrLHH!950 z zY7Nk{w%75suFbFPbKSDG+o7McA+=k+@CALIZP3UUo9K^N&C`Ojt5H(U@_8-RRk%lN zukyyve6F){OYE-l!Rvi1`Rx?*7TZCK^fc}@^Po_3>xKQ~(OJ4n4}|L%YfHeW`(~?G zxY=;+2kd^Gv#?ML@Had^c`Z|G@*}!^o!IU0Ft8Tya z)~D)z!zK`9cW%Ku&e!fkpoicu!2BHYKM-7PRssEb{nJ`Pv2F3>_lFTi_m_Lh7@y2n z0{ERc@XgLE%#VL;F08Xjj6Z!+^l!v7|788xRAP1)XLL7XeC;>96&>1*it6hCnprk0 z`JK3x$(&y^q-`dwrwsL#GI{!hK5+xdHKE=G(VT1B_sx^|T%k1E1BC5Y4fsjXQDJ+|SBA~u0@jJGma`)xT?p#d|!ZJ)ASe_{73 zB&}(Y-QZzCNo#mTP?F-RC2_RrL*RQ5#-B6I!!N=he$>{4@t#}pnL|F~xSdXl;3uDo za4VHlo&32?J(C(0JWY{7HY10{{LKJ1#qI%+*fAL0dFa67w*64~A}eO!YrSJ>Gno97 zw>3p{+NTf;7NBG)0zrdLRLh1WbSs460;yi~Xc0^Td`CE&FcorNdPRZ@?MF&|QVno$ z$hTd<7$o}Sa~iA-)@+##K7$@5a-hwkBC$k4Y{B!MX=sZMP6^7255}t^v|o==&nVke z&MHK+++y0KJxQ7S6&sAFzF&y%WVJVm?%;S^9fAL0i&eD?m7-F$%*$<$6rQ&Ii<`%| zu>gx_k{oe@ULlxDszmNUrFkE$Q5bgN60uVA6zZc ztir?V+m#ta4A$ynwOXEqfvqhkSXY#*&B5Z!lpSZ9Qp2w4I4>guB19!_d1qZPB@_mV{TXIc0Mq88>IuI;PsoAr}l$nKCSr;WMz4AZK zn-zjckUjzNoULC(!2}8R=P2B+)@Bet!6m;r*M|L5G8at7*|cm&_PmuaOO?_(JZzljbE$qx9dT+UR4 zK%Z6yWqOcum!PUE10O_I8Dr9+i}2LuddRbE&DChuJ%u~O=1O3%G)1|WW~-GN6XC8r zMYSx<*(o*A8et3uP}g;=+aM-Da1NbCJASbMn6`=|U1Rq;wCC7x){`UIY|PcD*3Uv+ zn+mGf8?8`n#%HTl8kOL#xJ0?J8mDg0o+6v)Z@2QyRfIbf=0f4FOhvh;XKfW4O+sBO z3ZAgnZ6aMO^SAQNM=;l0&|=~^W@p@}u?gNwx{_>e@_eIkcPvLw9Z z=Z>+~g(HW>+eTk%3#J$w#ZhgV^Lfk7KQPygBAZk5d8^I6{F{-va+Djl1Ypq3V?|M1 z8CSPZul~T2tha;}@YWDduF}4Uy1`0^%!1{5&O5)04F{-!Ru96w%p;`=UI3g_asLKN9d#C~XQQwzZwJC3E zU)SzKaS%kSd`ObGwdZY$8#%reUNyQo3AQz=nR>qO36Z??2Rg0@U&GbL1vuUeo=@M{ zIS0zFdwN>2vj`Q%`3LMAp3O_E1w>53c73X;P}0e|VJ?X&SFtC=j0>WN!yk8?{A;84a8~AnMewsm?xDE7DVX1 ze>8JyBo!;(cpPMX1v@<3cgeBgqh(ivjw6FQqf4qfqzPZM;1-{|uUbqb-h-lRKW+$` zX&0Av)5FWf3nS%0-_}MQz<1|qUXc|*4&HUvTmi@UU6?{n7$M5jm(bduvnzqfvlzOB z;2B%TwQuYjOCjXWBrCDXIC>`dLDGkWJb2Nvw^4yK>Qq00xFDR*9YUCbKTr|U?)Z7M z=}(B;6O~&<=4oJ6@=BAQFn8Pi>iy&RCsADHmhD74+(#uEqr#%GB(_VWVGqqbm~W4@jL9~s zbjs0WUG?ncq+=skHwqmiE(juMwS~<4V}ql?iqPOCp=1yPbwanL$T*O}5HQHk|HdcS z$8XdQw#r!dAX9WgbIUqCKS^dClyMO45w@H`O9aN(vh>}Jh+sOtvnXsN9>j}WP!LA& zrEv5~@q|8^SibT9WS@V3y90ZtT3Ms2p!(b8c5Vpe%jX;^Sf{E?R3sHQXJ>bHa9>SN zaxrVQ6FHD7J20x|iApS~ALLp}$TP+m5|R!|+K~FA`604~QUe&wrM*7~*aU+jNF~by z^WCS{+8R2xniHk3U9a6{K61P^`W;uLhgUxcaLd91vd2xVk)rqfca{rN3apw7G&Z3m znPyB%4N4qmMhZC@_O-z1|7H|9GXIjm_rl@pdKl}%&k{1O4ocG&vv{k7=Y!S8;e`eT zhQaNfGyNkLt_5ECi?7Cl&l#((n`ijgSU;o^0>JmVEIz<42z{=xKMC2I-+1qDG|po1xsHXLoU-5$zG2Me7Jzy0g)Nj+5B;(}w|}!UitoAZw-- z;}X1Bk-X13(@#8kHtR)R+|1B!1my}XBDOlzP?2HT8`nv=UJ_5^FV?(3rs4pm1!?Yv~1mmhj#QqchbDzkua5*Itf0ePvLB^F;RmIOaGRqv9W*m21n#jc@ zQXTmt7qg3E%N)b_*MX>l1T{rMrq^+B?`^D(ICUjtX@`=8?Aj zdLUlGng9_GE?WyPS+IY1;$VH6E#9=>4XfFC;11mUuwSSWzRO`Hx`w0$w-Li z1XZV4aXX^;4atbxQAsh@lGWX>RgEBwH7j;yfMZSDF-@`7QCt1uvw;(N0H8$C4wDiq zNl4__#UEgb=0!OLl?Wt@N4XZ@nyhehJ;f9;d{C6zE0R&d6`lv!cQDg?{jRS7Mogiw z%85KuRaw2F5kL%hcCT>D-{+Ins15aP#mq^1Ml~sVp}O`Mh$8dE86!t@xdk)lVI^R8 z-#4FIXgwCN*x@^sNI;g1fUQcJ6ynB)ECZW>p4`BR6*Xm7^CsKqkAJPkWMOzjtW!yGw^C|89sF+` z3lVW~kU;H7beT!sGHU52Q*iq7E`;zE`zgR%6`5~iN8sDHzu&k7LxvzX!pVTuQNSv0 z+`%$r$Kgedsu{9fjY)7jxgP)RrLH#tK#dq#1TEfXO{9HUgJg(BV-$VrUyO2>XYQ4-6|Q1DaZz2~3v` zxLwBZnqW#ERGCU!ATklZXR?7k=DiE~)NEesnvsE4vb;d9K- z?&GN*H)RIGbXXmIawH&Bid~pmOnMd4i`5}Otdd8~xZ0fMAl_mqV#$9aJS`N{Ta6bx U#adBWQON+u;9r*i0RRC1|ItLyG5`Po diff --git a/CPLD/MAXV/db/RAM2GS.map.qmsg b/CPLD/MAXV/db/RAM2GS.map.qmsg index 26e0d5b..dab2808 100644 --- a/CPLD/MAXV/db/RAM2GS.map.qmsg +++ b/CPLD/MAXV/db/RAM2GS.map.qmsg @@ -1,27 +1,27 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691916590238 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691916590238 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:49:50 2023 " "Processing started: Sun Aug 13 04:49:50 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691916590238 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691916590238 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691916590238 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1691916590566 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1691916590566 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(59) " "Verilog HDL warning at RAM2GS-MAX.v(59): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1691916598863 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/onedrive/documents/github/ram2gs/cpld/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691916598863 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691916598863 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(73) " "Verilog HDL Declaration warning at UFM.v(73): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 73 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691916598894 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(173) " "Verilog HDL Declaration warning at UFM.v(173): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 173 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691916598894 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_38r " "Found entity 1: UFM_altufm_none_38r" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691916598894 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 150 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691916598894 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691916598894 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1691916598926 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(162) " "Verilog HDL assignment warning at RAM2GS-MAX.v(162): truncated value with size 32 to match size of target (2)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 162 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691916598926 "|RAM2GS"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(167) " "Verilog HDL assignment warning at RAM2GS-MAX.v(167): truncated value with size 32 to match size of target (18)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 167 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691916598926 "|RAM2GS"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(294) " "Verilog HDL assignment warning at RAM2GS-MAX.v(294): truncated value with size 32 to match size of target (4)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 294 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691916598926 "|RAM2GS"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 90 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691916598941 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_38r UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component " "Elaborating entity \"UFM_altufm_none_38r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component\"" { } { { "UFM.v" "UFM_altufm_none_38r_component" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 201 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691916598941 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916599207 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916599207 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916599207 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916599207 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916599207 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916599207 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916599207 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916599207 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "248 " "Implemented 248 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1691916599238 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1691916599238 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1691916599238 ""} { "Info" "ICUT_CUT_TM_LCELLS" "184 " "Implemented 184 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1691916599238 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Design Software" 0 -1 1691916599238 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1691916599238 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691916599285 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4702 " "Peak virtual memory: 4702 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691916599301 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:49:59 2023 " "Processing ended: Sun Aug 13 04:49:59 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691916599301 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691916599301 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691916599301 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691916599301 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691922975519 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691922975519 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 06:36:15 2023 " "Processing started: Sun Aug 13 06:36:15 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691922975519 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691922975519 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691922975519 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1691922975832 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1691922975832 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(59) " "Verilog HDL warning at RAM2GS-MAX.v(59): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1691922985816 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/onedrive/documents/github/ram2gs/cpld/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691922985816 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691922985816 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(73) " "Verilog HDL Declaration warning at UFM.v(73): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 73 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691922985848 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(173) " "Verilog HDL Declaration warning at UFM.v(173): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 173 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691922985848 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_38r " "Found entity 1: UFM_altufm_none_38r" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691922985848 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 150 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691922985848 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691922985848 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1691922985863 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(162) " "Verilog HDL assignment warning at RAM2GS-MAX.v(162): truncated value with size 32 to match size of target (2)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 162 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691922985879 "|RAM2GS"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(167) " "Verilog HDL assignment warning at RAM2GS-MAX.v(167): truncated value with size 32 to match size of target (18)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 167 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691922985879 "|RAM2GS"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(294) " "Verilog HDL assignment warning at RAM2GS-MAX.v(294): truncated value with size 32 to match size of target (4)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 294 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691922985879 "|RAM2GS"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 90 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691922985879 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_38r UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component " "Elaborating entity \"UFM_altufm_none_38r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component\"" { } { { "UFM.v" "UFM_altufm_none_38r_component" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 201 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691922985879 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922986176 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922986176 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922986176 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922986176 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922986176 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922986176 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922986176 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922986176 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "248 " "Implemented 248 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1691922986238 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1691922986238 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1691922986238 ""} { "Info" "ICUT_CUT_TM_LCELLS" "184 " "Implemented 184 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1691922986238 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Design Software" 0 -1 1691922986238 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1691922986238 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691922986301 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4702 " "Peak virtual memory: 4702 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691922986316 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 06:36:26 2023 " "Processing ended: Sun Aug 13 06:36:26 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691922986316 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691922986316 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:27 " "Total CPU time (on all processors): 00:00:27" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691922986316 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691922986316 ""} diff --git a/CPLD/MAXV/db/RAM2GS.map.rdb b/CPLD/MAXV/db/RAM2GS.map.rdb index 45e0cf8df4b0524ae996c1a0ddfaa1ff1a290155..5123f7d3b5965f0e80dee527f1f0f6262f1f6ba2 100644 GIT binary patch delta 923 zcmV;M17!T{3GNAyPk-A300000006N80000000000008a;00000004La>{iWh6gL!~ zDN!qis;XMx#Nl0_iL}|TpoQeNL`g)IpoLAN_EdRiJQIV*9{D3-IC0}&;>uqJ@7a@G z2uY6|P%U}weg3@oVRiQh!a`w z;WAZBwpLhp0P|M4Q%?K2uWM#nJicBakTF$&#_BX+b?MHT;XtGgPFtp0Xqa&dF_Ar6^7jIm5Zb%OJ1B+Z z7D}V*z=t-WY$&zim8KHP)`iNYFKA!zGxQ8JMpuT_HGh#bnjva0!-b=;jg^j!S*vrw z950~Ixv#l$5s7?4p_V%SrCadV4LZrn7OY>q0piHrnbTGT&qGvM|74(ug{`M zaESIPbZs{G3!59!5EiDD;hc2$g1E@?+@p)Ug_#jGUox(s8TlbX_h$!FcsjcRME8%u zU`-=M&VLq?1FmF5##U;VKJ3A{aHr^dMAafXgREi>+Karvwu_z#`mIKJjmMOV`SQ8z zV`yVcEYwW-lI6}D^!1|6qUDqhD1#{7UC8kco$1jEBi>M8gmp$Nywk?^0cMgjG~VzM z)29o-XO~-EifqKZG$9oW?wFu-WiC5)uCY6VL4Vm)>>@?`f{LS`>w3U3S^8NTpPysx zu;SuPxC}8`wd?m(gY>9HR3p^t>>alJikvYN8Jg{ zZe0KNVR(F}@&SV9KF={hOD|y)A4be8U%_Y#hLfGG${d%}6gd#? z2DFFD^It(V{qFoKN6Y~H~tb=ei>BRof!zp z9`~@qlE#ownkE_UYu5Z@c%zLwJ~+9i>3=yS{fYBB&OdM>>n&WS zipkar3wL1NDtEwXKlgRbOpC{-j`R|egFwIy&Hw68FdOyJ_=bZF3AC%Y>~rgcs$iG- zira8<%1@epLh9Oyc?$41>3{42ss^k8s-@?=ViI0xCvtw)jni~`K1sH8(;877I9S_S zhw*SU0eGq$mw&LO4OSm>LaRPZrGx;pV7TSxkQe>zt@Z}I<)F)7dG1;$u<$AcPHSm< zAax~jD80%_q=k&B0yI{q0jo=Q#0&=_b#U4;)k4FJQ;3P|*^<8(z=Y7=HQqrfB)3o+ zT?an231vg64X-qnP_`yiE`34!f*+!1pfS2KtgeZq(SHn4dl@bqg{`l2WXxKf3+8wM zh0cA=m5WH^6AHD|@h{zie`wH2R<>aM;vLT&WKIWb95=NMhUZ!pB08e8G;jL6tZ?b3%mI1=sveUGSGL}!py%t3pc7ua^uGeN)AD6jFDQZZkCbbSnM zjERMsDPOYOd4s-Qv{|&A(g9@`uxfqXo zxPOc${ZW4iPrShJJbW~S;bbr#4?-`QKf_#e9JXV!M<#mMUSb837rW@^o*! zJC86@y|0^lk{@C_+Ez}u_Fv${zQbxEyEmRb2==CL;B}OCBSKvh*8>*;=nSW{ diff --git a/CPLD/MAXV/db/RAM2GS.pre_map.hdb b/CPLD/MAXV/db/RAM2GS.pre_map.hdb index 92d14d580e7b46020339ea97722fd32fe19f570b..ed5f656d4740789bead83341a9fb7d401bcc23af 100644 GIT binary patch delta 14897 zcmZvDWmMiwxNY&`?(#yRxVsgKyA+DMySoN=EydlTxbvdL-HW@syC1%D{@fooYwelI zUQd!IW0~1AX$1y>I0XQg_tXC#CP@Dm{}&Dl{$JW1;=~6rLr2BsUe0pri&E581O^jJ z&KIQXVT!;AC$l|Du(9r%N07uW?~p8WoGdBo_xi91^&dZeScnxe&}!EIvlJ8Si?31= z>WjchRQ=iEd!uIgN?%b@Qt{NC+Z$7yD84LX?pvdk7Zbl;}R_eKN{C0i@j}s#qMJC_)Is)CwnYWdKAi5 z&@rl!DDPbx)td0!4`CLYe4ArUIrd>7m!I*CzAl`i2{rMYaWtv)k=N9&ERe#ljg|+X z<*%d`SIl@nYc;U1fPG)kPF&1Z{_1iQET0<~Iinip_x5>Dp+-7XFQDQK_&;%1Ll}K& z`kEkf0kS|^4jNXF7>{Oe&rWK+YQC@_-Wls=a&XienF2G)jBu>`r@W(k_uBxAS$jQD ziSp}Hu9={c+XcPTY>A1tsF`xtX-)ua(r4ux20x>8;*j3e$gdt#d*J;h;y9#+m8I;i zl=c2a@6}&C!-OTAB^qe ztd>UOqWH*FapZ;aSOw*j$xMtT37j#o(1-b+1HYAt5BUWVGbmEjE4~IRK)(|jo0tVo zF68@-O{wQ|P=Nd^7$YC-3;;SqzF{XXPWu(r@G(ldaT#xPLI>VtR`$+<)CXhmTGM3> z|9O#%1z-AZ+WgmfSMY@;${$CQ;{T2=_jBaBzd>tG;oZBX; z@af`IOe3D$pGx5;8u!bM-OD; zf)n`LQ{DPmg0s$e#;(6F($}<5AMN65B50k;k(AKg1(rk!_p2j6=7gBZkoDWED1j#^ zUWG!aqL^wovZXNF&pvTev7ULcgX*MwB7~sgD{_I+1r+VVgB$nznRD4!*2bwBXDG4> zEx3rLMWXh3nu^nANL!?t?%^83CA!+6@B2E53$OKepkMcE$N82fyD$Djxk z{ZsK-@WH$4KtINcX{H)2b^1OeuawSp#9$;DW!4Bn@CbXX0M(B;Nq#F5og$|MMxCN- zv8)!Vy#^7(N5}^%>zNeV#Ue(2gD8&pg!KI>WyEBiPcV3S_kfLr0MqX&E?HL2eJJTy z(1^!b%gxBME}tG1jN?DsI0ip}oRjhBk5|sDZ!9xJ|q#Lu!6sY9aO-4k^HFO!)&HJPC z!}+z|4lnsS;z4UR)V*W`EI0v3TI?TP3t9MhtG0^spYO2K&6|wMJzXb>yc+!xta^=n z2!X@-B0w-bcA4xdr>_gaV|s9-zEJGKruX^vX?#m~2+%Wsz7O@DX>)*^Be|CLSP8Y7 z!$rvdV-3mkxW&4Vxh;PDdW+*U0oaj#U+Xw9bzPqhY6!jc7u#Vxo=YxTX zy86F9#=F14oeESPje+07f4Zq^&1XJ8mz{Om#%EicztwsGPgJptS&^g4pD;jHnl}m? z5&r=2yW5yxeUi=KHHU}16z@L$(g-`~#qQ<0%e+3xYbt?op2H<|oMWP``L1-txzgi_ z$lVWYtqWxYPMV?3@?hy7_!%s4>QqOy>BhhmImURWc-DqPG7`*4r=WLyWHKwpw*RO= z5hE03;=>@eZ#;GDe$7NMPbQTtbv@|hr~{mR(W+#t+Zg1lf}nMql9==815KpOid|b~ z352?e5CzZMap>-A>|AV}x54&1GK50KMh_UrMo!4u6pT$i$(@4s51lUXS*~BqBsFm( z_mFofzTxmwc3NJWD{K}9cjHGWiVIZTrPgFshzXoI#Tk{kEdkmk z$3@4pv^tEAC0<$YNK(r^c^)D>Qfb91F2$oBZ)_A5kz&^&j=y}>K3;vRcmr*Mahu?k zc>)M2c-@}X^+Dlml17os+!qv?=BzVcQ12xrbaMGru+34GQhR0)SJWgLf;+#B|n zV|q1-bSggx%h_DITG4$@AD$UM@atb=q@+&?Eb5T5{r?YP1dqe>o%Ju|=+a((1p3S} zQIC@}F$k%)202lFzr?seRVK{`KKV`t-I@1H+p!}3@mr_#c=Kn6l4`Lc0izr&OBf)J zya%g-EJ;17L&;SGtyT={i^vI`Xvm;i7?ML38h)NG8EbEwuyL4s@F3bbLOj_Le&g($ z_zi1{7aBYgZ0Z@is0kYL>s%t z&tr(Iw*2K!l*D{;99wje%;J@<29)=@cK_ZKmo5QU)^tj?SIW%Z!F54|UffF>i--S? zAW{EXTln;m8=|4gs+dxTm!YCZg=Zr)3ydv1*Ex@oKESfx*VAvqSjAi1YMl$onJxn= zK95v!FI5Zf*l?iFWj5){#960-SQb!YUQt`oJ}?!HCi^khmtytcZ*jzoD~r@mytpvT zQ%1l{YooQGLM65Fu^7Ht;}{I{?L_Zjs;B4tnVRjY(RP6u=lN|Y*KVi$X7e{F zxN|yQ<8GHv25}8WPg^$2mMte!ak)1$sX{R6Jbo>LT>aKA6H84NHn}tl4)t2M(aY5?4#Ph(&Y^l<_BAA_9ogp?> zZR9w8@K@&7gGo(pr&9Leg9VKhUg!4rhK~FeB+BtsJE5nfeQ!9qX; zckxQHrOU$T{bt4E>E$aG&^?JQX@Yz2P2RbYi|Ju(g{ep8qeH(WZ(is| z4mL;B8+phbK?KH@v`j0GiMP$<5bOY?4KyPjq&nTfYUYA2Yu1-_^;~gL02SVg-1DD8 z#Tzni{?7^}lFcI>st#P0S%*G0f<4gt^tmX1_;L5@2vEas$7X5H%1}ZSVMjQU(nda) zDH+q_EkMs^;&Pni62Ic)F2NxYXI8Q;$jA^@jHRu`%n1;J+sfTLA*7gWB2<7|PW`5U z%7y_ajoD?gYl)5GNat>Y*SE>EWGf7(v_1;lWHPH*zGF+bIa{|mMz=Y6w>cEIxjPCg z`k(`Pl)h$8Y;L938Q79_^{?Dx`8+nPox_;_9wQBe}SD@0(W zg1!2t=)HQbn2-1aT(KYV2e{()*qbINL<{DqU`3MV3NCkz4Jmg`PN+i01wc~5r6D!YR*2=S-E)Sr zMh0e<uCb`bZv3U{~dUQCn8eX1{z~Y5elm| z<-ixTz{veQ!eNIf)0%`Xw-v&yCJ2D7_&Z*b9&!wKvviaCr9b6t2G6KP!YJzSEsCYc zi|vCL`5*u)qbOLxFXDwDe5tNLVpoL^$Mim6_W|Go|2dldfvS*l*v{_QlU&~5^20#Q zfLZ1e|IolRV--}u62qyzF_sXmI!y~vSfrF_%D%KWm(4=HPPSCnX$k7P)6%k@(^C2e zv_3$n=R~ly#?FavM#8PhO9SBbUSud9b*Ds+6yTkX|BQ0gqZMzZ!_Hq#h?qK)>@&Y0 zx3sj6ZHJ=?-+L1Y_lz(hoCA$^%cmIMhdZS$hh$q#Wwdby>{E+aEKEU4%~<$8~~7?n%o!5XU|W~^e0T~I&FzJl>8ZlY2XLID1hiR>13$*Guy z&pq?~=AJZ29^56cHBjAaJjL&|ku-zi&E#pd&afWwHway-lb=-zZ8-D)JN>{|W(vFf zy|Z=xF-avwwhO&}do)VRYhqO03PXJINRh!6at!ZlsxkECR4s4Ao8U%dMc$+I7s6Iv zzHbR_nO11Lq5EbS!q|WiU2#vBS}p6epp&~MB^k4+33F`@C;pSVf^g9nNphB2V>B?O zTtSf&eaf2e)J>UdajoU4flTGB{$3H@7RM1!20rS^ihw}tw=QCcO1q6=duB4Ja&snlv5>zEqHZj3R(Df|}tvP)#RKcI4c* zMBV`EOPD21R2r+C$sm7Xwq5Yy*s>W%7MSJ_9w*+ugqvNBn_o!hub!Ccd?UY^f$swk zYh!$kr;BWS`O<--#xRRAf#WC0BIWJr<;Ah8JS@vm=8_F}OR!}P90cWaG5LEdM<*~Q z$;FBb&gN#tHIYCdoI5ctwb1ctijX!peqK^#lTtr+~`J1cn>(bx#A?0 zQZ*JYG?yY2GpL#m9Mk?Bm7&t_vf3NnZuaVM8UKw=)qzm(IupjBR94HeGB{%_?hxx&BygRE z&J(|@gR`W}PcUU&Vs|?1gHt{IBO+gBOMpLEPgC4EWWJsMcVqSwm-xTse#tR!^uNJO zYfKz_)+sJP2Cuq*203-+jpz{m;ET$p`xY)N_XykLL!jM_Q}=B6b6F@~>+(d#fw>(h zOcwJA9s5cVccM}*JUOnuVuFPwC{_UIR+M&r@W#3u!(eBYgFKxXV%)T^CTaMT-stxz zy&|C=lEEP511G(+7J?th@FrmG0KyiMS-wfull1@y`V$#XNySN=^roA$O(I7uUFmPx zw`WXt=HDjS_tJ1CzQ*n(IBwzjoOI`Vn2^ku#tw<3uCUAPQ>HPJ%b&OIXyWJ_91Ug~Ca%Yt+x!scPOV=dF9IvcY+-*k`p9Uo#wMajND~%N84Idx!8|UCw{AwB1h= zoqzyx?N9231oWT{zbLG9*5B(6ZiHvoyCrh(b*xnr7GaV;GrNd-Yd4->`uvfX_+C`0 z%%9wN^!g4V_#sBn{W%rgNt4(o4L)@LCsM^(Ix~MZfH1(>1`_De`_sAghDaBinOGuN zWy$hNO#K1Oq$ zUU>HJJ@#4O&TuD_-Ye7o_hNWmhY$(x#ed`PtTfZfj3PdZ8KZn%@uCkZlw$B;iZ=3q zK8Wys0{l>C^8H=P(_`5P0lTdzwjzm4-xyNS$%piA@&=KuNZE)pRtJJtiy*>=&M69~ zVNv!LdA)Ze2=+C}e`>Vk8Er2Bu~ZOh+R^v`4mnQT^|yt;M8wdlQjmB7d(3yuU(x*| zt~Ds#Gg#st*RdEeT01x4lRa0P}jpNf!@-1Rn{7k{L z)t<*U5(qjZ?p~FL<34O?$kcw<_>&MKQ{1F8C=3e?F17%DLY-I~%uX5?;W3#W=yk~372s>QgBW08NC59qWw!Cp z?PfrK$aBZ6a(bvn?iCs{*E{pVZz@<$>I=e(s9Ky*V%d8DbpaL+HS8*QG;xE@jFqaDH^Cj zUVTz5fM6r42Kq6d9}t^;uDsY7kr7ejzUi&v4GjoW-$R_fYX z#W$T(Vl7X;rg7IB*SkCCDw}hZV9U)>i_dVs^*N?OGryuwDfs^oQ!Ji$wqE34{#IAy z<7wr!f3ugxQD;^BG3BvdW1RteTB+fxci*gT?zhJpVPeV^93VDku7^%taCLne7vg6) z9G+oBIe7qzoc4KImtC!wm(;#D^nl`LAHKLQnJu^SdA0BswHA9dSsxyroSqyWW}Ka! zWaun6v^0@l5n$3%TTd&c2*Rg(mvnZlZGC^nRQXR;)&_#4oSc66OV=tas`H!&HsCz# z@>r$AnrLj{z`9%_vHu!;)LkGX8-@~3K_bvl%?1)M5SQYD)yH4aDF~$ae1(l#h}I44TVxTIDXBwy9n)A1bKeVxmlu~zv}i5PMiCr9szAMlBnQvo=3{alk`(K^+nma z)Y@R9_28p;el}7;*N+Sj=PkwoR8{FB+DNu%RrRpjwfJ0g^eA z<3RdElEx+38`cG)JPxc!CdXXhFv?d{i&1zNJ?BzwN8e-JR? zCc&>jNe+pC%I`5s%$*kf>H|45%{xT~W}2xJs&>W|KI_8wiiLP1;(A!6xyU1y7etq* zGuDKGv^boloMxvWfx{d5vaS%9N0ao|S0q@W;m_A6S3GOs&VLa_2BOLlvah7-OEeW7 z95BQLs}x^{U)c}nKJ8NLre)wIzBmGc$b883?dq}0;c?Fv2V-xyt9d!ZHm6DnD+)8b z+o+i^zYW=r`R6-}oZcn@=-=mMYT}Vbh2hBCeba;b4$Z7e_*q1Z@=?fhrPF4P-qP3W zO{1_<)Z78p+-sBIGtQnu?4b47H-i9x5A?$4r|kU{HZA)om^(SAlD2vN;{otjYB)5E zOe`i!?SO-XgNqG&7s$byZ<{_DphH4-Wy)FH&x88`lTZ(+&Q@pCV8|z!JSC5Y6a-(O zu0%1*(ceFc0G~_V^&gFZzIPPr?9=Vff>A2H-!04!kPbD#*?VyTrV z4?hJSio7poPVHNw`v+E4p?=rj7|=1OPPiyr9`irhmEA7h`G_PHd&pAaag&Ei7F z?lINl?zQg6pBMlsAz2w^6hIWjBJQD?PPTwZo z9z@m;QQMb5PmFv&V^xYq$j@O{1lTUN5WvPyTCH34zV}kVfuPpuY=e)agLFDzEH<-4 zj@0m4gE`HP{DvS2ygWt?X7upqD%6QIM$JF;6(&#co4fOr+n?~)~?HZ=Y=4CCa zpEQRf0CbZTTUMhuIi`=ICOgCnZxA*L{w2C=>dfzy950otJAAvv(qFV(R10Jp4#Cp( zWQohleZlyC*gcvYArFHF=+@j!m#c5;=?>qNANvX3Xnj;E(5E9@G^)*h%=j`kuJIv+ z#YFtYvuN*+OOe_3QD2RK|N0xyUFaKT&I6sZb7O@73Yeu3+46n|0>IVp{Qg1`=Z$6( zv>zFBuP4^tf!b_l{IX!lX4NYdTFkqWeCXS1C|ubqY8CLV$CrUD=B|C+2_YRTm%-9M zqCQOx2D0bI-)$>g39f{KPqZ0s2VdED0C#c#(m3f3J2vixD#!afUVKBYb{chznm8v8 zmkK2(mcuX)`%ik6Khv&YP-*DJyU5yYiYSpuX=t^nw9sD_zhuTCwo7lt?Mlec@Uplfqfez35TKuHKA>gV`0IDhn8Eiun9qF~f zr$wMXv#nx9oV$Bi^}2;Ny)Qy=JI(^_6&%y859Q8r8>5PzW!C2iIz6V-jc$#DY&x6Q zK#8>lLwlLZv=>wp^^m5gTUkNq#2Sl!{mm@HuQlSVgiGGsq_r8^!_Dc$32duFEBfiG z-s^f#M)SE$g4pkD-9tRhPUj>q+6LEt``dktTWX;~PGMMfk?v-f2Ef*7?WCvHU~9xV zO2z&&Tdup-C|@M1gtP!7D543bz3ibMh}9yZ>|4%TQ}I?af1N3G*IM|`I(uxt{bZ7- zvAGj-l+ho|Nre7j&L?5?k|%$ivdi)JMqlXm7>km3mDmfEzUz@{?)f7$4zA+M zYr>w+9s2-!E;*6)L((U@D3El6Tn&}qSl>mAJqkT!*R9a2ntFP=?X~B|r}DiX{0num z70$VporHY7q8EnmXwOFjxXS-Rn zIeZj@0j{7X%THD>FN@a%A7VTK>|f@~~8W?i8Q<;VJVuaxmLc;)N>mUb{hkbw2H81;MCS&n&x^D!kpS z{u*Hny*4!Uekpr=fog2yrsA6+Gpy^iL`(X}-o11hkJtzb z@px<;wCQ$ecY5SrYcOM84@;z9%c82=^5`D>5XTqa1{AyTYNTJYjx@d*p15{gAHxAlo4%7!s(aBcMI|n<^ z#EO;CG5>&mnVwx2cbz)zGPNMc@z5T6x8H+BtDf|C$5qX9loFH!1~#`hOP?UUjBIAi zU5rW*03?iyE^9{*Lta&e*yJ*06Nbkd|58gEeGv=e0-}|ympC2c6>K^(*JjAjt6)L) zxxoj~1}t{12JOI>siC9q9vOE6AbI_-#CGR?3AF%~1g#O_cu91!9;ZfssxXyS1tFNVg4yz_1t-@^PB@@~pn(bX&jnqNQkALc^c<9I) z!60L<-^DM^N20qo(uGQd;_gCE%xk~?+^B`nVwx$Q0YbK%`?YVvCzCs(rJbBHZdb4p zTpw%j6rl4Sy`+I7_lVBipTtCX#C#vC`q8$+fn@Z<#XY{x;kiosCu*B>QNOYghjJSl zuGIJ46}&v!LXt(qxn^}(c`8G)_-bYL4I9bY8J+Dh?iB~b%P<@CtJa{P_CwRoMk~YH zt8<4|lJrIxlW-eg$Ni$oO+qB^`;CLViIspc^zKDH0O{CWJAY4fCiFCQft%Seh_HuL zjiG8lWMh|hFnGCItnk(!5O|Z__F58iJ7gCP--$yNio(omJWWruGL2)H+Qk#|c=$|emrj7> zH@k)<`Xv+Q3#?OCR`&=_WK6X%KW~8dML?CHTrSGcwd;s6W1<+{N*g}dY$uR=qvUU~ zURo@Iwc2XZ*%jDzUpsJLIW00dFh->TaDE>rl=bt*Mxs zjMs6%mtWkOW=-K#H?q@3vcJ0f_ZRsRezONKr{&3r@xuP-5t44x8CwjJ5;g%a=VTCJ zpz8G!r4Cpp>#5SdKg%jk5y|B=vS_~Tld&tmY@h7e&xyF^j``Y zp;TP9Ux2nGJWKm7*Rxn?$Za&y|G4%5-NEkfgd^>V!ao-3(z4VdpGJ!!hl~^pTU<$x zh!-a_@1O^#F780ool?M!Uxg3!rFx>wUuMlYKpX#>)1he*6+c$}S18u^$R*Y(q>ZwE zo7(%RHpfn>4S}5{*F_T|#o71ut)niQ4_|AJ6UPM0j3C?bVVv`uY5h2-gejI;8uep7 zbC$m$VGf(78DTwJL>=-De&1nN`x@8L$b{1r9rxZU97u_%LtFVZD07NfvKsYXVu@qfX5|W8OXg* zYSjxRLTL4{L{J$Gn>yab1n9 z4KBCEzYh>T-meW-xs%)7i@ybOU6rj3^0mdgL0TM$^7f__2d~e!CHk%sJ|f%g=)7US z7Bx-Vd61vqiTf@SJ`$4>8$o2m|Lk7a`5YZTbXq!7`nL?%v!iS!C-zJrMZxbdlljAnnVXcG0ieVWI0s8abHc2XqeMP6`epzRTZ z3-KqA{RNxn(hf3fKfyiU;Z+f=j<4EOQoC?L6}O2mrUp42Jh@>1zT@uTUBX^C!HWr7 z;IYAg)+NP1BBuy2yj1X1+l~0Q)56`I@>HJ>`umunoXq}hEV%v{76q)W(h8khB<5I= z9w@rPbOiILFmADgN#9U>mteTAU%M!d>z*oQ4Oq@0?;41CBn@a8Vfy+phO_`+E%@81 zk!2s!Z`P82o-C=RTy-R+T)ibpK7Oa8b=HxQeZ2liM*<(gNRlL&M2Ww+02L}iFm`qb zd2KNE6TY@CUa9N`@?-eaCB)*lU0+SLS87rBxreHkT+n^!TZ7;Y<@eaFYIfan!G|A2 z<*G%^kXj%CFG`=H`x)p4`_`12feR7cmJd9?Lh|2D86-I4>|k z?D2GuKZ|sp*qoofNp~Khw)ZTr@wLb6U31+ZuSs`qMz($6H-90jXc}^58yxmIKa?mzF>cldYkNd$yIw4 zSw|_+``*^0cgP2^Yr^0|K!6J8lYxVy1~n0xNPOD2iEL(h=AISei#th=2zqdU=^*?r zsMiiBIT6;yQ@vhV;D=twuIYFspcTJslIUk$-viGgGb@vIZWX zoh;uzU1Z7mWU}%;C!P!5t3Bb07hZa0oY>qH%L4EeZ*7bfy4g_ALi(tIYc-{nF?Zuz z<_+p3X9woqtlyUgU+eK+(RMCYOYb}*dTtyDUV0ukxOM^o3eZdb;|7q3>T4wMFmTl+ zh{DZO2rEd;qK*&3%cNBc3`KQL07m#L9^VO+)Qhqo;#2emk=+xRF6_Mhvp;=Imxyl@ zc&f99{a;&&78LgXu4Ou_TJwxXB%9JrZ(Y4Qlp1uMH zZGtx=exA`hO%Rgzrh*192yqkJ3-Qez+ zitdKn)5%S?NGo*K5xD0IXT0uDoVx~Q-9DYqH)pO5GTQC<37fuO`We_|lCKTo2cHaj zlkk+qEi!pq!~Lq6rZJ?dErX)@49#y@g$QmVugGs2+fH@}_1^(>=6GAU>un~iYxwJI zCK@xHatIPQgQlo3K?VE-S_4bUyqEJ@^huQS3NZ>;e7p+uu8nT4Ql{W+$_s3LLsTyg z0Zhe=CnI?9EFVsKA3wJJU_}Im*}lSJ46g@7PwdW3HB>A&PMqOX588_M z+eDAQ$lKTOT}kcUisZk#6WF)$v-s~D_mjIjprL;~pvng})i&L|jZC8SG-zUfKZ3L4 zZ#jt6=4LsOP-a6U-~utlAR?3b{9w&f822oGehNY-Z_L>m)6Df6!n zf`M_uYsb?2z1bmKRnuc}oru@HJ>x8hAnA2EI1bi8r&sd!j2^L167=)%d#>x3X3LgJctVNZR(5^vOA zF9K$0YB&Y$+bX2!$|{$}rq)#ioHas!q?iq5q7Q-5YZZs6`|bR3`CadAa{ZIE0_=KN z9pigIjnvOH@-G%PPlXmI5}3VkS5U@!`6tY1we>)fVv9JSPzcRb zJA0rP8v%VmmSJcBx&2H#>b%|qL)eoqwuyIsqMqSSnPg9b$iu3oH$erxv#2Xg1#*|9 z#fR8{LKK&D)^2*h=ak!-g!p=^ePH*=2EN%8yORm@68g9yI1KmhAn@@1p&(*!yrJJq z3IMw@li5z}&q}Dx+~0gzHy&g+3Vl|FlnaoCqjP>T34+!Xi5KL+ zeL~AQbRNwYHZ^Way&}hM8=`H;e<|_4*nQlX7>3h>;HKN>;ujn!*VZLB-vj62GZI$f zzo_S*Rt~Gt?#c;-tjIn(K@8~Cmw}IT69G8y3|4-e%E}f6<{mlu&L_2@#}^;<_DiKR zNqjr1WC_@>@@F${xB>Sh?cHd>r_BDxd8Spp80+C2FqbRIr85->7WTf>jImEn{QvGb zPJpi){Y#ZGeUPPR55*n<3=B|?6EF%j{fO1E! z(cYC~GqR-IkMK5aqXE4rTy?Ey0I1_t{Eopv&-h%=|G5Tlw2SObK>nvAJ833H<%Zo9pmd{l1={>47N zk@NR^!g^(s(b+r^Ue&4lYsHf~rD~b!x$D`8um0Ledc~7gZF4I?7UC-|@O_)Fj*Gxyf8@ldxyEN@7 zzZH64*zMQ8@;&|r1VJwV+~damZs0pJ=tTm-7W|fq<0J@?0cC#;!HN93{%HLUa(hs? zWv2S_re=Gwi?>h0`4<4)x*k-FC~d$&oU#5a+|17Vr$xYs{01l8eoCNA@V1fhP)vJm zlw2it4egLv^cI(KlwI`C%kv!HZ+imc&Z1vXndZLydDCw{JR={tF4fCYey#Hx$PPRw zVYz8B`m~!s{-5kSyUs)R<(dB?3(k;h zax4S~bo#o+TuGZ@= zwf(^RPiHu6#rUwTT->>Ked=bydLIQZZgvyabp?V1PN&uE{7+S&-ro5vI(cAT*>Wz; zBJbHBCa$}Z^R{^E1y_j$OfFV*T)Fw{g63ZXam(V~L$*E1#fAxX^e3vU;pbw55%1*B zm+IW^8*NGtrr#A$1m#ZaGTc;$de$BG5I=in zSI$0%hWm676&`wjNq>GpHu8-~edZFLq-~g358+37zJK#v?{E>Ul2|^rUvVeUWih3g zJljLN`AaPk@Rx?{OCWY6ntJ+YGIz4*7ASg0;EBCE-p?KFU~o@3Hp+?OCB7u1{i(Pw zcuCGKQslwsFzgV%!8I3t1~blRTa$ZQ;vXfcE8jzwr4v3p!+<&&JfEh}Mm>5B`w#G# zLyT%k!$@^ghK@KLH-@WzIL2*?4x&V3SVEwiiSc^Vh&hZzHGQ1rX+9L(bJ$@;b&rTR zK$q4fa(YhRE1=y*y5<;OnN^}~*eeH(wErZ@y|7JA#?I1BadJUQvDG6ILi`J_0W+>_ z3uP;UdaI^}yUW&7Sp32-^kgu+K_ssxn^28V`!b#t!{w6H9VsTN7A)mmFzSmwL?=RF7T=)Va}pj5RgQQPD%SY6}=9c@CGSLtN+j+Y;w8O5}6C{sesUb0slCEB*RSA0zm>rFj^_xNvx6*|%0k^n7#5;HwI z^IZ$Hj&-RbVfm@?E+m7L%qE46r{UL3=2vX-Y!aq_0uzJr)jje#uS?8Mtt*t;gNTE{ z72Po#<(HmaKPV)W8|baa->Qo;i-8L9jQi>?^MaI=~Uw# z8P&zpZ1>H^$*nM%5qX0)6*uG{IDp)tJKcO(v{O#I^|P@ggV3ZDLv}9lNS_?oOiAvG zy&bF=-$5M&bQ3fC<^YBEGvO^Z!O8n|U1evvpMqu(QD|)E@h*Dz^0@Z}u&@C)Umu07 zW5-R|?a-rD#X}+du#3!eK)3QaHx@RA8f*M@>3LnbSEiujGDAnz^l(T*WO9HLWjDuu&4q0(bQl74nX8nMTilq{V3GIX5qmH zE+d_%;K}c&w+=IQ;xaJ6yj_%Cx3 zp~YGiCLdBrT~?UP>99{BgtT(aQ4t70H57Nn0j|*ItsBXq&^D>SmY4b@ib}o2$HR`5 z*75`T_hY5B5X{ICrx%elPtSaJ)*`cC|NTJ6p7^&2NgRI+y}YO( zs%)E8wI3dy;m!*3UfqNuC=K4)^z8x)Q}5HTx=)>=#_Is4#AJU~B6*YrToz0O_hVs! zC&H{y6RG^T@-hsEwUDLPC&a$AmRt0CQsMj91k?=RuUy9EIcNqTK}}iX&c#MfERp$A zfPtIKr1P0i^GC86eg(+jE>;2aM>Fv6W5*~)`?Rg+mNWo))w*?Sg|Y(ibv4+N<`JXC zr%N?PbA(GtA%b1Peu^WV*gH?a(9@oG{U_`M7I~cLWN;I6gMpwYMdO_OcZ{Ho?$Y`m z?`uiGk%ICvXtLMk1zI9tBbT$>7ma6F13mWgNGa&TJR`2!D6A*2+$MmW!n|rdhUuR; zY3DwpNID6E4q8Ct4VG?dQsVYGA{_MCwAYirvg&oOf1R7|TA`*e$p ze2S5T6^BeCopmZcdt(euTQzy+I3VaJU50h%Miw3srcwNWDqetKD;Cy z(QmXgQs}ZM>*&+XZc!Z!Rt%I{!lZ+y@Ljd7ATEOex~;N~puk~=n1rn$=w4e-$X}#n r6!dcT{8^uSRI@29y-bOInZH6)pc{o_w)OVt>J=ot!_>j@Ho*K3R}it5 delta 14889 zcmYkBWmFtZu&{yP?hcD2xCHk_g9Zs9!94^B?#|$@L4v!47k78pMS?Bv?zZ^Hz4y;I z=R8wA)ji#H&P?@8RSf~HK%6RoE)4g-hZ*Mo$^SXGivM5R9sbw{Bjd*>7q_#499nt% zZ`7q_<1IOKm^`($wIY87#b(-D$0tU!1~0?vYDH?Bszfjz;ba2;hT#zrCCO;~Hjr{N0CH(57 zk}3SH@w7JkI};%|>cnF7c3I1Z%Pia3HqCI4|Gt!vV?wT_;7h}*e6hFf@7NpsUT(|f zp;1wrgf{h}Iif$Tcg$D8T#GeXW|w`I+IRJsyDepAeU{KlhYnuhohlVOor!@O?*--x?K-PjdB1oNb_cQ&1}d zh5V{Zb}W23`7=j1P{3tPz#{%mNMPDoh}~_+VPi&kC_UJ4^N056RC9&WDBoIl$}5NW zz=_0S)^2ZLlFHhYYbL1dL{RNHTMptMHB;saO!GIJ^;`Ldq0Oi#HjNwUQnSfvyTHHF zHgB_{Ls&%%yQ!bV318DO%zg`|I!%c*`=+#(dH*zR1h<=>b=Zg;IkoQoJSv?(`N`K@ z*fw~3wgyUao3oSMUU}Mod1l{^Pd|{YDlwTfnP$FYm@L6r^rg11=#sTc7uNQ=s94zp zI+bQ~sD3Br>DH)a1)tdGE0P!L74J-O+-ezz7sdG#>Hz%w3@-cD$LpQj_cXV|a@5JG zPNop9FC6U?!oN%>WXO~&O2@A>?{%~?wB=E-|BOaKx7>$&~IA>)eso;OMp8MUy z81SlGQ&X#8k<4VI#5-q!H7sXhHAMFUP%K0&#M~}tVNf=HGpQYpxWYH=lg*eY#2n|e zWB_Ydj`D-&_EzdRY|Kmbu3EOC93%$g(km_2BigFXWu_c9AC%9m*gSacGKhTm9`+meMU$}8_BB&m#{A!8H0|DnhtgpTTmO+aAUfKIM&Vl98C?b#}hdEw|Ea`7sFK_k_+I%>c zMW$2-k)qcuXV*o&Q;HCwmMoJV0mjR!|g!au&sur^YY&E__>CcUeDCw!#vzS`X> z7h!>eX%}I`ZA*6(1CjU1oPIzLIJ)Gw&tVV2fEI>Ovj??Ex&3{xnjbUZ`HH=LB}L}b z``*+EoWuK4owZk?)LHj>bA_c&BS#cy4gW+@?eImj_ua|u)zj|}8`Zb;VOYO%v3;n% zobm8?Jk9LZV@{_|yK9q(hwy|j{h7B&;W@Y!McNSrx@g?zz~d9rpY>GIqKj^S)W^FX z-R@`b@4Hr0HinWOpcw1{rqiUnJpO2;h!Ezij@FgpWbnmM;B`{xmKHL z*zK=Z)h~7$pE>J#H@0&{PC8nj;d(I^DFiNJxwh;~7eni`^3b++tqyhEt3TJ`aMt#C zSeoZ3Vc)!90{(O zV103)`;R?M^XgjUnqrfw&A0SI7(y3H0_^d9OtuoraJLp^@Y3`Cc}Q;)GG}-ADyZ5S z2nkEw6PKQD(c-iF%Xo0H&UODSUCs-glap{lBMAM{xPuu5B9q|M1U>nD4S$_FAMal4bWE5?8ZN=ekATYIf ztsjDYam-yg<#P38E)NYoiHLR`&Mmn@_EMPUuN8#=Aq5`T1!5d67Kd%!2EXgZ*&uI| z)+dBsonjN!4oKR(i6uQ3Z6NOBV~d{k5LxkOf^A2ZE0XO^(hwqH#)BMwNrY3JDJ1>xS@=v@nI&3G@sPn=HAch4hKrw(tEM(1k>Iij#t!pO7wk0u3bQ3`JL0cIaxOn>*@*^D zrUPKyU7JP))nb5-P1a5mgzvJ=(&yq^#u0yEOckN;>xmAFVSAEkB?ey8lyU8j+oL zrm!lgont2Hod2%Sb@kvq?07;`(GhiqcnBE5otY)4-_s!1Tm=tCS)yfAH>)qoizri& zxj;>-#KI0woU}jB<3{e()RRxIv{W+;9UjMJ9mnx4(zY+sTIot}XUZb~@R;vtkDusZ zmNw7+xo?e375wwy1UDhKRr+(t3pN*-uxQ_p{fjrn=$itJ^QOqm6w_cn0?z|m{6jbI z>B2F8Z~RWdYm#jl#DDLZ92bDCibjkMA!mbUFs(vNiR#8T;zm~T8z%k#6l~pejPl4@ ze%kY%-?>a4bWGh|8|orGdOYnd5uNllt4v6fW*Fv|N?bA%16ppGHmM(B zZoxyiCzwl62_8?fvGy=T}EDezWWBd7DYN_|7$Xa-Gf?7x1(`Dppg-9Z7L z!Y@~O!mrC}M-$U-EQ-`o7BNA_y#OP*hHvNRLtou6zrGb<5A<3u70|R-;u7ys;A)3j z-5;0r)_c3oZRmhSj_ld9GhLdJAq|+C%|V53d&nqCTN9E~692eqNSBTw1mZ;YK4}iu z=45G-=U6|fEwy(s8t7&Y8@U2>C~aQ9Mel&5E;~)OzEOJ9ly&&ns=7Des2AYyo>fN( z+!ED2%;}48c9Bf&-b%SP*_#*dAL$Wx$;2w3t+s3d-pzS&?IdOyi(rzjf8qr6vHxaT z@7g?<3@8}IYR%TN`Z5X~)Ne3t{t=BS|F@Wux)Q@5fTszzrdv!SE1pxkKR!JWtL2Z6 zde!%8fG+$cv#xcT;aACm=~sEpH@6nMwN#z1dih7r$NH6J&it`nGuXSkX*gb}zj@+F zcVGPhG`l~ZE_zaGxn12}YP3c64;JK6Esw|l;P)AAW`9P~i;L-bb+6^505Qd?T=oZj z9B!KJBgu>Ni@}c4{PnfaKUc9tuj1Rlpj8qU`;Xynd`t`WjAjjTGiORR+jlKoFHmtc zeFlQPjYgWS5f>J#&x{-dv0H52)!E!Rk;fkIft8Iq2P4l@Z=VPJ4AT{4_{Q9TkV2ck z=+m~#*K=mfiKQWGOwuR5ls$DHv9v7VYNNFzgS4pcsR^~%rFY}E2+i<=-eYZ!u+v?8 z)~Tb1|Ji{FQWdiy*-9}T&Bun){V~1+M-DYb)cJTQA4&$s{%wJ3jH|Sb=8$jGxG;@2 z1N8bm!I~E0E~_RNwRHknhw#VqA1CFA$6q_RBSy`0(~e}ud=XJd?^<&jjy8+L>P)-nG#>qO^Ji|5y(}$j z8yBZVCYSbT{`?^VeWW=k9Iq}~#Xjbr1nO_yInq5*e)xi(oa0p%Y?eVfkBZ7BDzz!w zo7_K6T+H>iCZJmrEzr#RrOf)#%zB<-atvDG$gf-#%1AL9uXTparGeS{A+|2-KlEZm z&M)M(l}&#FO4>GuEmS8xj&}K75Y15a*bg|`Fxihpr^8p(PLJ3f!)Q&kzu-zFf%Q#!?gr zE_00yDRcevMs`R-GZsFOtsqqr(u`<@QO4b~YVz6C*!-|;0sg8{dScWSlC>1x{t*d9 z88vzLS9eH-GT!oyVy#i3Ea=Zd(|VUpToj9?^w1$OufIlP4w}|V0E3YWMw;I&y9L5` z>B$@tK~k4_`)9u|>AnSFTt$z(11YCdq^2$6rcnp0QEv+FffV3$m^8mTHtfrRoUHn} zQRqqnZRyINH`3q8ek1>l;x|fZOS>!2>E-^a&{{ndBpdO4{OJa)dOL2y8#%oQwG#wW}S#7{jY zMf=$i)+aRX(+jD$P%)tBc1q0UC9IQ}=G8T#x2?r)=C=L(@xPtmA}5zvF9+Rguv5ZM zl}}DbA*>WE^!(o+iXAsP4ycB|#Q_0_yJ{XKZOyxEQ=UL5K1%B`ezRUL``F>~ZM)fW zh%f3E$ zte>_Kv=xw(c-TxuDOSIP0% zDsP`~OM2N{uKXO2td(fU(y@(V{jF@mtg!t*u10<@; zOT-+PL?wi2!w9tGQ*i@NZ06d`FIYFcyBF7}R}Zdt*2)iG4E!tNk~Y0tjYAO#frc8p zxwS$pR_0P8c*vJ^=a9JsqVtPfkD`i@JHDa_^cPKh^;{RwE_af7TR4KuSkhfcoQ~*o z>57VJNB1wPAyLFcy#OHjgk^TXuzls_iPB6M3vq*O4NOMHuL6<0I}^3fDVl_f?>WuH%w+0bIbKesBG(-T3HszGr- z_S1Yi3(NGE%SeD(wYO=ykg9LUC;3D44x6st_fnsdVxsH{`p(Z_w=VbgdHV{Qk!wf4`GuDaR`gO#A0V`QL_wI4kPR zK*Az|N$hrLfr?=(h?Da193F-Vl)OYda$1X`vrhRM%o^oIxi)S|&Spo6KXisE7ZFWD zDzUf=`+ zvEDNESyeuoc5N8pd&@uBD3l6Jl|W>Q*(@T#?n2HNR#5>;czda zYXCnh=NB^DO3GnNtv2gdmc2n`?rhpzHi8MzzsO02f2@a90W$ZWz0@Q(C5H0Q->(|~ zZtm{$hzbu&mzAdPs1I#N!9>EHao(Xx7RKcyN zgD=I|^r(2eFT3`tMDpI@3R5c#D*58k_W8F0=|5Cb!(`_VjCn+6P$y-R&n-r$}pkfFP%H0tMZK2IjIM|9}{E^mlcWbQ%!Hv;2C~O z40lQhPk@BU;wwk+AR9bjB#iNFmIVPvR_eKW_-p0?wRFGL>nVh$PKK*C6fFAwLrf&E z#e?KB6ij~ap$|&tUJ;T;YKc>hmkk!$7;wqt+Lcb>z&&*p?g})J8)S~oE)@1?a+V$Z z)TZIb=qbV>OgPWHNS`=xVqgtH*)V_=25=vBL~&o48;g*bfoB}h`KLcGk>vna86Jp2 zHP6}ovf!9W0h34lV2ZCoox9z|8y19v3?6v#{?yQ*%@=(B4#{8B#g-rh9LVBOcJhRr znA!AT--W~|H%k32{2mv3Lh~-8{+7Hc6%Im6*#&v&0fiA}C7+dN)|2p%5Z0x;C*#g} z^Xn_zv(ONyB$%@FPg_kJi8o+`GgHFU{;m#02f}x`F7I0$nGXQ;$B+#k3p&YS%XHsm zQ4PhPyfRvs|8NX$!VqPowd*fF>OeM_aFH|i!r;F}+Hxmyd64n4Cr zQ*5QZw6(~q=&>O$(`Ti$Wu^A$d*#7VMB6|RGJ1L);ciCWj`VZ%4KX7W^dB_R z?PT|X{&QM-Bs%YJ(~*IZEwI*6^;uGFy`|dR2U}w`5{LwSc*a?1J6_(hanNv1yi2sH zx``x34elsC&?!{?-8X`Fq+dtJTBWS;pr|0e%#bC8V-UOoZt)d+p-2c)3=uFIBzTYo z_S2to?QTL1keJ%}N9xf*?V~&kV~v2Rdk`wB)5|U?-?JR>MhN#G`CpY2xIQ9 z)>G-X`{?`Vw_803i_G7++*!N@9ZQ#RZW<3vj&6YfZ^Zpzm51j>^G6zty6gw?gMPou z&29Xq5`(%J>P|G5JF+us*%a=FU=QjX1axoMmzbSnMNxF zgZ6GSs(l^~$f9`4B6Od^F3v_RCgLtf@UOf6Nnn|VABz&@5`V@hKSijt?w8wLtUZhG zgM!JQYiRpv=3^f7ry_V=ZNKuw&XB8L-cmLzu3;=kdaxc@_HdF2~!jU08>bRoR-7Gg)?| zf8$Wz#oe(vbGZ6jV+=FyyBAP298Q!qeky)Vv0I5R-Uj90kExU)&__twH86<1#vAC247M zMaYO_8ie{+XxytGE=v`4@*i@93r$xXzkGYtISsydZ6Q;pLM`~d7<3TCJ>bk+XWg1? zgOGkEh>DyPdn~N`TtNUzmp`euAFl}-pDo|K-;nN}R z49aOU=r;bYXP7B5l`>t{f$HuI;?-8O%cOSMb_!lze%k;!{QxnKFP z-F57A_6*V4Uc5O>JLW(SfH1Ic_A19HTWZ{hO5x!M)%3(wL|>6{AIHA z&FQW}J61ps*uehm%cR?b^x6)NPowxXIk4|_tR|+J$`RW}V*eQLPog>WVa9Ngs5rV+ z^+Eb|@mHnoNpHkg=#vj?8Ux7E;shrnuBdk%;@_7Ii5fFaVY~(oT>rWz9yqRjaTOHn zFActE5+ql9Fm6(>P`NCjH&w)lR>`^8b3rQ{9Jlz&SU!w;V#lvo38$i>A6{JVViVI) zF&aTM|5X(!xjos35BA$yexvXY!U5R`=etCXG4GOnUbu@rA|*~p1kuY*;b%w#_Jefi z2F^1_jxW3ex2-6E*UaFwmys7&%0n;G9?yw1U2D4gl-s$76{j(L zgY*JLbqXh|qU!*{0w-=K)_af)*~Wd|*0bhR#Tncw8JTz$bd2~Sr}ryWvYBUBMM_+$ zeGXsuYbDi044r7j{Tf{1Aj1UZmKmF6B3tpzRi|!xW(eRdPun^#FZSjHPdIklIR0bP zott>SUl9{=Q0Z&5Oj+tM4o5cZfxhoQ@zMvpzN%Oe#$ z#|mc#5(X;L9?~ZT%%#ztDxIY&`Zl~Mq#_{pSN|>N| zdq3J#{ubUfD0wzH?>P1AJm^GTm!6B3gNf_NRmSCV$Tqgw&Y+DX;+hM>>-X-}kuW~v zNlJ$PCAw8@Z^110R<^oT;>(InFR7#Zm(NVA#8(rWy{W%rM?*JlB+pnnL@*!d3*2@8 zwE_`_R64Ji%&Ww=Z=-w6uRJ(KoMYHe&k$;rj4CiPd*zmdD7HvkbOuG&Xr1v^2vp1< z>dB=be;f9!+W+2`-LSs0W?tnl$mkE98IMc?G=qHbCu#G?PZGv=*F`r?Q!6yN+}!`rEh zaLpX=l_n)Ke(nyZHM-sW_N@0(OeOb! zYS#1rW{I*=9Mo7h8p5s8&2SI!$VYs+exURMUEtBuo8c=77LT5II zaaHI5>Drq%m*~=s4ZwL7Z-g59Pv@3cE;cmpo*0-+hn*Zmmz!OEkR}Pe3kGi}%3^?i zu|H92Zfx}ReAAL{x)IzaXYtvXj(qvjV-vs0;;k=u+dQQ9W^?LYa1YsuqI)aDRmVpi zLA9hen|FOSex-?(1~po7pJA92b08%CpRy+azA|VDV7Q`p$elF9El1PLJJv?W@y)Ne zq1j~ah&*4Nbo6!4r={$)ny20n+c*c%f}9k$?KbL@%RAfQc8zAKIzN`0FWIvI%%tyH z@99_GZ1(z4o{?u3ioGW%k5GFdy;1(@YDJ1__aG=$;xLAiDbFpG{H}yx~yd5I*?+eN5~(mYs(Xof66v4{}`Rp@(UhjF~qbhw9nj z4s~pV|FnCdid>9}$|QW!!@j&v8?T;r>^vVUa3d?tw2mM+<|r3#4J{wcU3TxU2Mciv zVOv?5|3krBNIy)Mvr1RwgXMqj3auU92|v&(=Qb!&{#LimgIxUUraQVYK3>t@>r(ZE zZmU8It-AM{U?S&JZmsM9S>YFfI8`O-Us}P!tnwD;rA7#$w*(iy5A) zZgi}n8)rDT{$@n$&fU)3tS#n`w5))D9=A|MQI<%p(w<2Jb31LFXt>v3)BO5y zPqklBU0wINMXfbfn@rZfxbJo}Ya@3)m3Q+PZ^;MKPS-M%(HaJ7I0c>WSBi(YAOIC# zt|Vq+PqY^Vxg0|%df#i7T6amWCy@^YFI9gkya_}g3WiEBdz_0966y4FW0Fgy)|9N5 z;3p&w)GCTw>Y;yBu)JJP9p|ThN-f~^NP#d!%QG;Kukll_r54m#O-)VP1t!#!+bYlF zWhBL85l|e_Cyn<}2KbNY^1^N<&jFUAO;e(;XcT|2+nnZFmSPb#DG0G8F!y58*hgyq z`&yYc0G-F-`aJD&0oTwn!3HH9kF77(L^gI8ShoPU+kUl z^d@#gFNH)?f2i3J$bE8CdL$2^`|U0Wu_aL5Pc2YReIJ|&sdZyuwnQ}M{q!fonJq6Q zAXpkF?UpACd&f;L_qSBTb&?UK#Of9vNK_J<=ae(=rCRHMRO+!0%Z1MmBX-N%_GcpaN!?&@Ly9-4%@Qx>lG z+&YbUwCpSsovg^1n~t!Gwf7U9)kQ)Zihs|K(Wy;RerW0)o{22AB~+W+IDL_ID7t43 zJ+lrSjG9}Fi6`q%#ZG+sLJEGVSwl)NGu`Oh2^M}wXb>sHTt$;UA!YiH{`VLdSn z%}Y6}n{{%bFNCr{kU+1z^@j*7vTVWH3s>AJy@D%ze1GA7q%uFCbW!mB9>STIzwmDS z=C|xohHJHei@4=Oo4}>g>d;bq{OcgaedFp7rx*R%x$H}(z$NSI(A%Gy8@wf{jBsB{ zaqyaEdy?-s#l4H&_R0&^vzJ}r+PUoNR`gSmz@@H)@Bo4!eMwOBFdlh!KgV5Y2fSLu zDA=WA%J3i^Zs!|-v0TZPJP_IR^`nr+e?+DEc%fmLbr()Zh!;jVh|#mM4pt7NYw*iz zeeK_AY1BU_-2Rl`>TSBD>ZO8tO};GA9|LKyL`Mq$_>&3{t~a8&hUGqSxP33T(~LsZ+q7(|fB zZXoI*M`t3CoMlCxYm4L5c__x{eb}HelM!7B$PVlei z-w=4C#1*XtDIjYxEaeb2i;zX--+zpzz_?iavzr=t2K*)4M)S(n=1&f!zS1Gv?vJve zU(Ri&{R*-r?25F?5OK^YB=auRcX(-4*-+5?vI^UM$yF%e1lDF@E z_2VDx@8qtcS`P2^K_Zv|+_U!$m`05LP{*zifP4RfeiXl{{O{2c{2&dtDBZ_x`Qn}x0styc zERcsqx%^?i*(Vo~p$R=r)zl~TcJI3-aj$Z!L}BRcKud$0r-* zpPl6m5>VK9FWtG1^FNOVO|4RB&lT=q^_Vfr5cv`*Lj<4Xs}gaap&*;wSd4!SJg%ANw%qx2d#q=n{y^8d`KyDvm#7<;j?J)W&L*VjC!V`Oe6DDov z)Ibsyf6ecV3DLMaPATd1TuYYETu?ZgZ+ti5a&XfTk=IDu!k9VO*z29C}6Hgrq^c7+?(Iv}nlU_O*UM}Uuo9w~C1$sZjaox{wQjcGjo z)cbQ_+pGa1x@BY5Ypp)>lz#^bu#B&V`%su;yXWdp|Jgp>5JeUaV#7W=A7>2U;)!%284N)sd;g&xtvqCQm%H@dmXIXo|fs8^FW zt8UTR6Zce6qIn0ieJ;`3$i3=15o*oM#)E>$zc&Gh{g??sFtot=9~#hq+D-pJo@6aF=)S=(!Q^)01mEA#+fBkp!OUf-#fPOAWRO{}@j z23$Yr?PE1hQaI(7HcuAsN!g9WoZ8*)s<{GnDK4Qrxm(q@#3{z%mvy-}_(2?;odV)5 z{K6)$!Pi}IQ!sPwl)C-vW)Ix!TPtXZ8N)I(DT}D z<7?+z?f@|{3$p{yT>k~hDZzr*TxMGMT4{z!j-U_a^4$-h_7oMj<~mue06a5Ph#uwuGgn+OJDS_o4Oexc=2w=R5QLb9t?v_ldX26=mcVNRFbns5^X_sS3m59^FzHHT<*{vX;F@crdEIh&N;gs%twN#TduZDoZUjN@=lGbKxbrDULS!&BlS{(9T z=;q~L@p)+Af!63BH0a-kV$Z=aY;f)OA_LF6FaK@^{smEP_#DSq1YK3BTzHcY_r zwFJYg;2{J~mG4%8tcP~*fle^!=~Azula}Nmx_Q!WWd59$kP?(nlAu|z@GHcJXT6O( zxH2S>5#@s1q;Mep=fFS3iKP26cO@|FY%j2r50qi(v5k&)#{($B+JkGRJZKs&*Os6( zTPHSg7cu-pO)Xg5tBc5FX91Xc_v}F+a~_w^r79k76j4pc+yM&B-&3FPG&w*aG}%axpLt@8qwqKhhJ!JTf&OO^TwNimRy@f@$W|K>5`hf%%~*;;p2 z05N*Dqg1xv%q8v$B8lyA3~{k}_CySEi}<^`Q4@jjTgbzD@Sg3sZM((ep1-SLzaq~I z#$po2{7SOwJ;_yfXX@y!-OksSOz-ov-N3bMoR@ZQ;QWlWY3IRQXY3i*UZty?ae?<5 z*sFa8mN&$wXEMTI*{$7wOtZZD;9iyMmW=B-l>9*mO`{q~AwZhC-9ZyC%#Qh{!OGnd zChfEd=%#{Nz1dqB!%BH?LU%M?oeNiIyda2_KysBT&x^KVv-wgsmV4Ha5JUFEj?k<) ziaYQm1UvoG`&Wcm?JernW7cHUHAobsd}nu{n$U<9<5c&G8-5n5n51G~BOX9J2urBR zuQ%Cde0TD3PbLw=y;$T)EpYE)Wj%JICKRn>s^q|Of98t0lNs~`S=nGD6}>YRfW13k z4o7aVZ!Hg1N5aL)++QcohJwNUVKHkPDpnqhlQ65B=Hl;xMXaDU z5sOY21}M}Oe3ysG_Y7w`%& zo-`J`)xmgQtS_>VUlqVGbzafXTl1#gV$7`8CG1f1nCYLL`t_e z&IGTJ5cP|!T<%f7?2dj(n_#Tb-nApW`Z~t8hA3I8k=lvnAv$vRZ1VbYBW@|PL{YWo zO>V&T^Zn%M9Bxz>lUzWTw3G}o1u<U&RYOf1JjfA^3G7MNq^@GuU5mUljXSS>o9BTx@oZ8($};UJBo}F0iXt zwr^TytD#Q_nmfnQyXxdhcCs$N;QvAKpQ$T*#v+{x_G(hR=^95q6=ipg#DDb=?2Kdj zqQ+iq9I}&rWSsiW2HZzy;3Cf*@*%`C&mo*l0PmydoLo;gH3%&?oQ%OZ6onQKM9qC1 z*H@P5r$^<6t0{vQ8{LoQIzzx6fFimrp;AVLpZWaM1YM7aO^mmQMCmql{2Uax0-_H2 z@Knur8XKgRwI$;@(Ob2(`DQpmPw&UrQL`fWEcyCYL;PR&tt1{m{d><-?eDqaXdjHV z^78R1saK4|Cl-UDgT6h}NVJI9n{^Z^Wu9EqN#PBM5E6EGd3Jd#0vl~yb`;rtf)aL= z0n?Mo-=vMIJ+^|X%Qh;o-s5d62N;HEFd2ixdtPbBiH|4yB#(GZ4&Dls{i5W5v~p5o zov89CD0RJJ_d~jXDg)YH>w^^p6T>VKXnd_5S}bM$SdkKY#WVihpn9D)imi0y`p3pw zu8ry-<8Z&~#t)<>O2JSg8%7Ee3k4l?M#~uj)`OsfO74ei#N1mX*_a?ISA>)KkkrQ= z*9|EH2@Y!lS48t@0n`{eA)Wus%&cN$S(MbP73sCuW&wHZ9 zVLKug`3v9Q3xf$NnTvm@E3mwm9%bAIt@SXejkZePbDv<{;AD6xR{*=khs!0k z)a@n|jqwXS#|-T6HgfirIhwcu=ru>RnuHj^x|?q=>^(bQ`G=uKR1xqK>q51o`jk77#EA4dk@m={0wHZc)zzt7YyjbV@Q^h0T|k5S6g43) zxJ;%a6w#(R?^%8_Mx!ni$tE>VjLsr7@K#pKp8h$1TF3%fWc#ONIzn{knpIh#sTjgKkiRPy zv|4YHTHTu!@kH{IF0%y=6BI3AU~tcJEj++AJI@6b+8!~-ZgIz?Q<<|;Zc&U5)sJvZ z%UOYk5?*7YLQirW;wnk%mI!a1CAX~T>HrU!Nf;EA3v4=`- zNR!vb9x&imBEQ67F(2p(de{<`Y*o1!M}yYqtRQu)1PsiRat5?TB1WHitkPNZhLvpd z^1{)vrUX2>hUHj(o~QkM|G?I-_n(YNL^IZL##IW_PdJl`PpO*#*i4wPHVw3Hm-C2SS=?Gdm8-^2+n}NRdcvqqb*~@XHu$^@ZmEplS z^|z8w0n*FO`8)bcJamaXJ&xjuz+;pRx9Nr{-B2Sr;Yb{VGPoJ(-v`3S79=>hIs{DA z88I46V5#m0i8`YGUJ4hnW&C>4A|NsWUK**iuBgIn!5C?#`kG>?KpEM|G^z-HA*q`! zUnpQUG0{O;Z(u}_Hn-nbdEKBiDoBmTe`O5hYqW_WL6&Yu%#!{pvx)k!Q0oxHb<$TW zfydaHp`n^9yieRW?4i?|6Y{oY;F#oUeQkXEgv#vuJ6v`XG==lLyfb}J1vcSlNEqw# z^YLvIf;2YiuFWuvr!HY25!}rGsQ*9KZLOwzUw_iV`!vKPKJ0rqNAbM@54k zxvgW=;|ZUW%FyR;06rJ@yi-m6d$)P* zYcakTaq;^kIAoD=W%{Y4L#mgys2ruEy+;8-8X_6io$FaClmvs;u>&6}fcMGvXt`)2 z_}ut$u7XUoyppKj$rgo|dV|9o-v4+{`9pw>%a&lYvJcI!Cq}bh(+3UZ+a@LBAR1cO x$~EG9NqMcbb$2?v5VCTxa@}p2;QOgZG1(Dn`q_E(Hr0^xe3{|7WXy&eDn diff --git a/CPLD/MAXV/db/RAM2GS.routing.rdb b/CPLD/MAXV/db/RAM2GS.routing.rdb index 83c925ac845d0c22a41bfb286093344c9f32c149..afad9105b0d273353acad66cfe4f67af0fbe2e2b 100644 GIT binary patch delta 1290 zcmV+l1@-!g4D}0;Pk%fG00000000sJ0000000000008v`00000004La?3&wa6G0Tl z6A?iW(N|F^Lb3HB%w>0zeQqBV^d(q)E~VB$O-h?m@SoS&OUiz~mT41fEA0eAdNQ*! zXTI~D%bezMuh)AP-iuei-+LMU9?wqalj*_Qx5@GT+Lzs>m-N>SvPB7O- zr_>0vA1Y{VIVb~X$CHB}^Mvh8iBDDT7NWaa=NCr3TQUBfCT5NaK5U@ z>1>_-x3a3TN?5LnW$oy$siXpybupFDTouj6(VM$zKr=ad@YJhH{mbHJ^Ig?WG6Q2w zS9H0Exi7k-zVssILlK?ridf2K@+|g+=!bcCseC9a=Y=caJ|cOhiS) zXEKVFvwx!OK8wjX0-kjvIT5vj8hV6WM{)ez%gRv0jRYK9ah$;;#6mfnJ9^s;|^=pHDDvJqh8PJG=Jteoosco$pmMjfdh^NNs=GnKn=A5 z%x#B)71T(c(q%g=2yh^JBY}c(qtviDip47!#pvYt${;W&4`p9#Vw|KJ8lSD6$a&!v z)xao%>QZV%(eS7!kh}`XbXG-^iv@Xn^=?{U>zrH5DRCulZPXc!SEz!Va069=FU2Te z4u9iSJf~=IgI2B-wxgh8MWK^f_Gl#ooG}^u`doYv$A=my^K2$q#dC`D!e>;Q8H|D& z7&%4JaD_xO+DJVG;3Tn|Vt@t$GNZS~Nvpx!Xne-X6fs%rSged#N3EcSF2#Mp4V@g{ zH*?}R)C!?qv5KpKeZAgNvqJocb-QL9B!3_nG_D3tgqz5%wy+u)^`N6mL%; zgNk?-H+mQaSWyks8_P5npfk=3Ux)C{;wvdyA>6;v|uZcp4~)Ji)xajj6Qp(u*)i|ap5gdhVE8-L*l zfPE=7(6B<)N26#lhRIm!3N;?KAAx3UglaPrqj;9wxUDX6oT5u{5=26Qf#b)!#6;uY zb%~Y0xYWQGAku$zspL3vF-bWkl5q9|~vAHWxLH7e;1Y-I% zOP9c~Ab;zE|1N3%jYrY=Z+nm?U?co|1>%4EYnDF%00960cmZN(U}O+rV3Sz|uq?oF A(*OVf delta 1298 zcmV+t1?~Fv3yBPnPk&Ga00000000sJ0000000000000RF00000004La?3&wa6G0Tl z6A?iW(N|FkLb3HB%w>0zeQqBV^rcvQE>bm6lcEv9e_m%dn=;?8Wzy8PXgYzAOy+jx zJKwp?$=>btdJn>T`Rez3kHh!<*^l{T`g!nS^6hBw?(pRMvVWhS{r_cv)^i&Y28@9uRcv;%_A!^gI(hHh(T@P0Nw zJYHz-U_LpX{5qUZX47uonU7nI=NUA59iCe)o^Cik#dCLd{Nw91!@An;&Vt%o!uq0x zwH}tIuw%!Cvs#9~*t*_fu;O)_;4DG_ZUIlHR#k4It=DwNEkG_4J zO{c-_o=5rSx13}NGF_6@_~-48sr$vCC2K}Ad9M)|yMIQ9W=l@D$gKjJi(5d3^RjS0 zX~@~7Rl7x#S!FCQi)Cx*;da_&QUS|0naXHh7R`mBFYcxR&1~qwQdgz==lRXWZ%sML z42>~y)0d;TSs7`TBOCX6r%j#fN?F;C>Ub{pMU!IaTuN0J@ydlC$4zg2+;mpO(76z! zFjYLaRDY~WFTEJ-3zbTjf>gGYr65M>1?Ork2OKHRqp=Jw^?+$`(qiC5WhKC3BQ_N} z9G_HiWehveu!ZaksuWK2>#S(OjRj|`^fpRw?29J$B`0;M>$4O)Rx}hkkKU00>vgaz zTnxJ{g=R*H1T?I!>~yYIih3(v#Z}t$aw4m}W`CqoDX)lzZdB-b36Aayscfy_7@--_ z(2Z80p@Y4V13Eo|RUucPku9Yq^dizB0C_JO^dPW03g=b(b<&L}C&>*}imOE3a9`f2 z`+^u67OfHq`?5KfEo9I9gnY4{Ub3YE#!^$ zT7OM25UhPI+Am6R*T{mLW+TqX;B-vEU?d4x**mc#S8Gg3i;;{et`cMC@y9|lq-urs zVlGy;>6kJS7eu9$V$Ow=!Dtd3C?$!;jgfEzHiB0{0D_;yV566d_0UKrpRglJrA`(8 zIV}cG1b2)zvFEFc%a>Gc5-Aj1zGqB@#)f#!fe)c}`j?tc)gPPA`>vnN1 ze|=SAqvVHFREiE}Sy&GU=wQwS2Yxb}MpW#AQVg(C*ui!PRTUU~sMy3v;v-mevuFM9nQ%iDO`i#=r60SFRGrIs%{JH&DFA z;IyTn7b~NQjWBlun)ovU|6JUdr65e;NeSH9;oR`B2OhehLX#Ij5Gg;+A_pdU3!Y~A I1Cuxfy@gqG8UO$Q diff --git a/CPLD/MAXV/db/RAM2GS.rtlv.hdb b/CPLD/MAXV/db/RAM2GS.rtlv.hdb index 7cb9e29db7b3071a3a02876a074512e1e88ea5a7..4c0348186add85f984580e24fd9e4c49c59def32 100644 GIT binary patch delta 13680 zcmXxK1yCHm^F9ovc!5%^$RWku;c$0%iWYZwJ@_Dp9&)%-thl?oySo*4clh`Be&@~1 zlRUGT*=#1sPIhOn{O|l@l|TzTF#liU`|`i>|9Ur}|8Y;)Q$N%UN(rxvFQ#G)kC z)%l&tG1b3K=luTdd_fsXVIUzPVS4egSyVE)xDJ}vU!S+Y#Vz!oon1Hd`vCdf&1=oi zPu7BRl^$(J+tyCJd19`ksitxti7gr7vLc9v(ork!1 zi9x_(>gMM0I+7$Et9+lcKDFxkbf-Y?Z6pRzK*+TIfapN~-ER`y-Cxxt3=p_+r(b{p zaVELKq%ENtV3JI|Aes$R!qHiin@%Q&cgvS!^XX(@bGg^8&Ov{9{YFRAJNskQ=thme z1o)*Sqa*LkyS;M3#GxLP<$Q0RVO|ey01Z>p8=M3UD9Kg#o8gYeZMY`^*r57%Ob}>*G3^ zB_Ptl{?5|nvD@o&PjRV|e&qe9SfO$t0s4S2^pjZA$Fr;X3u?Jt;_w=3;|1`+4n&7| z7yCPY2TorC7|u1@WU`!lznE;Mg(UhRK$P z>U!p6%*0BMJuYt#$GUGWTztgZx_PIK*J{@?AX)G?x4aFm6wl-&KQ%I?rj5+@?#4%w z_VV(#x(4Yg*6%iTp*v#L9L-@L2%w}NNxgt%3%EhE5N%sMBmJF7?XX#!;oQ4|v3%;A zy9R}rCoeqxqy~1Ya<|#CdVMR`di2qS)k4mj;ZgpIg7SnTzvu$U0@`Sgb7r=?!ue%< zu)>U47BV4q5z~$QlaBf5B9R`uKA6lw#-(;j*`}i7zmTBGMPuBs_N=FtA`tW4!bhmz zwQnRoUG;&p*R4h8Cixz3w#~lJo(at~@98e@)6>^O-^{`K>=-mPe_?6|d{Xwr?bS=q z$;rb!p~4&W6^mmeAH3huhX|X9_-}tOZebztHM5OZ$Ri||Mg#6!3=&1uE!o7}ccV*^ zO0#IeZX3L@BLmf>y!a=tQXmdd%Jg=nTi=#$%|So?17^pCxnGoDWEKVZljBQtz-+VC zkZTEmx6!na0`upOMn0~jEiM}|91;60)I*9Q!aC`0Hfs_&x_5@g$Mf_qpqCN_901p~99!hQXZX!6T4@&kg=Inq<{b3l$ zc9s<5m9P~ucyTlt{`R5$LN;Gmr(q~%ic@!H`0jS16I!8@!F1C*=s57z%PTt6hHCr` z+ZKE$0H0fH4QfSaHOc}KD%=fQlb)EQYVaj7fE7g=T{3y>*hqh4q$8Dy> zu>j_YMJXuFch+gweN2D=h3I~}q&}o4WhA{X&D#k5`T2g*whmZzLcJdsWJ6U!xTYNb zVvv>c@xISW46e7+o8?+}Aixe*)$?DHTKfpSWWRu>xJqws2_NfUM^PtTCB7-+HR!353Au$N)S*8@0ch=zF+BK@)ZhhK&#+!Xqfv7KuRTyN*pJhZ6^kEqU-_YZ@3YuAKKfjU6wQ&&=c4 zoTL$jxFERtL*>SRisRs2}9!$@IY`&_P<2mzL!e-4Gldov_CR-vZTGA0-@gv2hlhDkMH z_Tses!@G$VFbkagsCgg0>1uuK)I*xY*haH5vj%WJaflK>?G*E7E4=GV%Q*Ob4+`k8Jr=C+`N1ie<-0WtH!^O${;5cwB}8IphUKpT4msgkPE`|3oUzy9NPW; z&}@#f5dLj{if~tZMEg&5lfiAT2`1vE)Tu(=LuOFOAf{Ri!n#z9P}I7gfacSu_2N$J z^_TrWJuNpt+LOwd?1bvhi4pmFg)cXs!vB*JHD&nqhpQnlh(ko~k1H#KQR%2FPusZP zPhKX7*A_dUAyvPiye_FKyPv!kniV9WRYgJY+FYx8^Nd%F9>eF9@mUEaC-tEI|uZ3FDPy zNnvrd!uNwKQ_m6Szh>w@cH*(QV0%y0;P@*O4S8#r*o}dlJ%kjmE^2l@JD_jRlv=Fp%wj63-hyzJ@#7n#p~3ctu{|%W$X36g$1o6v<&ThLLBOn zY0>~}1#w2W|EdK#&BdN4ws2HNjT5xQ?PyFGty67O^j)Q_2h^vmx7)4KH|Jrs zs;gZ5;nZgitrcdv>!rQfs&Rmlpy0#8LwQihKqG6jHBoqF5{1hSwTP5Nb{{dvqe3dg ze>I4FNy|FS{EI*hlMF{{{4oA(wAa!CwI&DjTo>2#RYo)U7F_2W`1rLPiYq`lLN|m(D$x~SD|taQ zNVzW&gOJjOJ-vjB!PkCpY=Vc7au@V6p}@tN^rgP}2|t}m>2+eY`t20JzB=>ge96s# zppxWsg&jMd-LmSz!yT9XddJZk6QO`Zjb4-4pq{{&vZ9;&xavm^ToTMk#clh0irOQ> zNyS?{M+4q3AHDM(rp8tLT>W@huN1qQ_^8=2(MYbgj=xpYnb6R+WcQrQ*;rLd%M_qa zsDMw5($H8`e9+d|YxDDMKi^;r{O3l}pwNECq3ap+wcCZ&_=H-7?1WtRi+4sgG;MpB zT1bk>qjnd{18UiDPM1?e#%Hp({O0TP2&a8q(stZ>jyS8-Q<9>cgn}-KST@jju#y*x z`$e^~we_lw0kmaviyT+q4rg4ltyh_&&)`@&$wjIq7=*>V>7V2U?Vp^nkHPv^tx8J9xnL(fDnQFE*+4lp zA96d|2Gy4x+iksK-X8tPtXgdosyjB*>Ej$Xj)%$_)-$&skKC5DA8Gi^l)4vboyk_N z;A^0Te9i37{k~YpFI56ssa$&tkFOq{Dx>AVPsXCX^~^6Dpk;e^otB-}a|!yroQ@#j zf_jz7`|~!fj!Tp^Gg?{Rf*gCCE0i8i!o`#T8#F#`ugvj48uYtaivU}Tuy-tH$w9-E ze`b4sC^122c7y95fd9bz5B&ci_z%K5vumP4SaBPt_2wkq^ZphT!(p`7(G!FLm^md#L&I=srE}}{rB0FrBniX*REGA!<%@3i-m{rq|$~6R^N=Cg01Ds z_nnI5)Y?Ndd{~g9PQM$b1ZVq{^TfFmvwhyifsR(lYKtl4^G&G~oeg~+_KB%#0f_G4 zB5Ro-6P`AO%51yfIyB9Emp5+O8w8FL(|4CtTy#XO2N?GeQ@^vWy4XEVXw%saoez8uJA&jLkYh&0PIoD^(_U$2=`x z7Q&m$F+pd_Se*JX2Q)t-$dXGYOwbfIr{0nBz8%t4-)~$lm{Hml>xgv}SObjJ9cqv3 zY0Akzty`TFWbwXY<(-O#ojC0(TL{h zn2ee>mH(F3%`31z10JX7rt@{i@6%#)0akeCm-@TmT4+3F(D|?YAeF*;^>Pz&x%rhyd?N$T0)O!lLe17$kH7XdQu|~%2~?Ip zD^=}waCA>6C*#;Pq)07zP%R?Rdv`xm>ldSIj4vY=I^)-|zDO6WbC}X(vbBE7x?c-S z%$C;=tO#l5Q@vxPd$wH)BNvZ8wZLFVjVP8a{9SIU*#6j6(r#%u3)10=z6IKa%xyA(a`L^t_KOW9$8`p3HZHthi2}yzWa-M|heirL zN(x~#@jChJNqaaP;6wE@GsOaXgZ;%rco`xs7Qw%Gd|`2wpO19ru6~_PBQiJ`THWZf zF3f0Mbbq^7!K`VLfPVcZ2MVintD0nCMSn=_sI@Fw_3Suol;~_8gS)?L+IG6K%q?pd_27Wa)&V_-{2cO2^8E%fdKR0Ek5-tU{Rw=! z|1sQyh;_^(OXJDAeu*OZKea{LwxovRvuu&?#Tu_IFacYIT zkS4HUd;Jps-S`dXo<#j^F7Wxr8wQJKML)(z-G}Y{@Z$$=Dn#t*RgpwZFKVL{$kBnM zzn-*a{`R+HBXmh=@Hdg)xoCEMYnD;ROTzf5iY8`c1MP`U<2s7tVgEqxT~i?wPlUFq z4m#-2@ONRf83U8a6bcs31L;akrFI)W)C5Z!#CFRL;g*joU`y)vZ#V?^1GP^PQCZRX z19ow}K;e5|7y`w&?*l&b!C<@JEUQuo#i&(NzGtm?enU32EP3%L0RIsNe_ksL8AGB# z`HRuxor;}BtlWzpqNF)_v-8dcg?c3l#U4`f`^=$e?+>(`kHK)s+?Y^J6s2#y(zXPE zG73)c>$632eF@e^a~!9%R0y#*%y;x`X83z3`s@;Z{V3|_+B#7FF0&lm$+DaZb-`rf z|GG-lgo+c*YeIw4uy4+AAZqzOXL=xteY@m>fM9cGs@^%TsPldLudaZ+KV@AZ^VWa? zj=yLcRQuVFYJ3lN6dLtGg4LErKzwPY@;g(A8z-Mx|9Q{Mh3(=q;&?Dr4WdBfd+){{}V>FN)Dn3{B|{6`_UG*^*7ww~Oh( zA_eF(HZka;=hNO6X_Y8S&K4)QdXN$ME8Vz7>Xwm2%ncqzayZpGGP7K2Q8Qgs5mmDA z?=4zbWOo|hxjrjb=O!Wy`wUnD&gfa&yu$a#Ob4bjeu^^L+-b$UOSM94#WbLh)eI4< z)%DSc@NXF-iAgyUPNytPO-emO=(QKEFBo|uN*ENuxc&zp$?jS?k~$Z*^oMf!up4Q= zbyk0TtgoFl!soH@kfOy~)G5Mclo=Y3LX(q$MU)pwAvcne2X9x9fz)95IEgE-QNF9r zAbgv8fQ1ns6A*imcKL_tt}}Pifv6+*t7BkH`n9ImT2^n>>og=Zx>>>z#a`_KQ z@`QvS&ymTFXU-lMU;RDoAnW*W{X$Vj%i7`-KhmLJ^rDwe2kyY7PHob`PeZsYX!qbO z-*7MW{s-!{g^?fT0(q`)F@2+l2*$BLFEU8iA@H=bni$vXw!Ck-p)&OSI2Nt#UIxTY zoZ9$}SGRh=da|*a!pS+b3BWsOl9^w0(}AE5aRVE9!QnQ*?|Q;7++r%JdsnkSyeOjt zWK4QbZepc2uLXa+bP1WH^R`VCx(T5z%Pd*oGj~6qXx}(#Wv$d!d_-{Cks=E1_JaiT ztD^+aKd)JkJZ7#GR=R?IonlU2pJ;P%*()$K3)h43e&iG1EOn*~4bOr1c=dj63p&N@ zc|V!xy>C=}pwFZK91ThT6mI9)POi03WA_|smr{WNPoR8ObrFK~a)H|9yTez@8)HG4 zyZcNVBDCaC?7;%9o%?}p;cfAv^#HmrJ5E2l*j!tjU9KY*_8OZ53bpI>+z+?H z{Ysm}UK>8ZbCzjw)$Gna{#c>wFm9kr07S0kx-K$^tHX88?|uSer^}VC3KFh=%hsHK z{K3V0!0Xfc;@x8IZSl-)cYJbwaei`=b#!)~rMq5R(@B5nj6p|ZJHw#o@|YOY!hN7h zB>pt<&4qcbBgh3+$jVOfyRytZUOHXOk#ae>V`qG2KqM8fS)jYd(;Z)W&X@ZX4QUUZ zTpl5M%!b(E2UNo_M4Nbi92DMs4VNjxxIbg;V$7t#O&M+au9|yGa5{TtVzaQ-$tv?l z-ILLsC^xx9%H7Ij^F!sz8luUx^>9QuX$>w-Mm&F7JnPfJi;x+1b5M7@kWJn}`> zdL0;Fn^CQ{4U@~nP>>TK0KLw6LKMMfjlZn^Z+AJ2&fMeP{eR0qhAqkO-|hbp&U8<9 z6~`jKPy1fRz}jD6F!0+x2;BddYZNt(c&2<-4XztR=qi{I(@YN+{Lb}aiPrzTxIF#4 z8U!VHt7_0ocw?D*q`#b7QmWyey@WGrLVo2V^&0%;TE?YHzyv~%j*ij-%R%QK;Zn>` zB*A|hJu6A}hJ#3dyd%cctJxmIUNe zF$M;OqGa1LCLON+szUaQz)|Q8ql%Od`l`J`ThZYL4M;n3qtcC3Ty%cZ6cdPJ&)Aw8I+z2u@9E+ z&Qy$d#x5BWq2ClZ?-xULZiy7H>nK9%C6tN{+FsW~pj!YE5C{~1^?;?+cP?0tNyaBQ zB^ItFi6j=rk+TKX>8xe3!ok~HiX z-(|Rlq&+`0pHHm^TzkW}{&Z4s`<6a{ZE*+RmG^|2+5eO&NgC|5gc?{M!^k@#U;7%V zek3z1yt7;QR4E@=bXVy0-ruz|xyQC&x|UlBat9miptln#Z^%|^$o9@7e;HWfDr_qB z5Asma?IVC^bUyVMjlxm#i_dHRrd$0u z*2A|k_y6rauT!t(Zq}}p+Pvh*-041 zu*~qmc{dG6OT|P4j+Tkir=;>EKd#5$w$j@LcyLGGN0?y~n8tjI4^3gN4zT5lO#4wj zu2l<7^uhn^as+faJwD!uad>D_bFs<-A9sz%YX!7_C<-I;M=1y7z_#_8n%DHMK`42DE z!K-ZR7R)KJ^o}{4-5-sBiO?VXde3qlxjPZ)8aCwAfOa%) z)oJL%S@NAb_UDQgzv#74!1cDF_(F@URSi%Dpl`UQoT;bPM|*JTSgl?zv%2S=L)`O$ z!MkXJ;*?N8+>>Sne>UcyU6fTl7pPgy9&im6^{vV^002rfB?1>4>cgw?PQ^)#r2 z>}lla(W~>eK!5VX(_|0)|Qu!AA|Is`WM`C})UgQS%6_QvJ6PIzN2e)59-Ds;>yldKA=vdWk2lG> zKrGBXzXR7;(2dS3Ymx%U%(i0G}YnD}&oL8XLiK^9+){{Vznp3ua{ho6C zKZOpE_}e$!=a<}!65Xec11#+f;VUhX_}0^6TB%?rP}R2Xr!p3Q!8!LZ0d#AtFBjJ_ zffA%ZA}`7l{?2^$Oz#aE+5RT%bmGU zYCj~Au#Zfr`&;_fF)0)J&$eG1x))IP6&$Ztgd2Y$oh6n3F%Z{ylE&XNg0YvkxDY6e z#70GT+h(>l%N9Z>0vNBuVVSF2uX1-iy@6B+Pl@%*5i*omAC{a;_! zo}j$6O)38KMOE|#_>Uj46>QwJedMxH60W1ix{PR4Djw2O-ivSyQG z(7+tAg#;=pdMv1sU^~ga00MqcLAY!tgeW~NACB&>diq)1D!&GVP-&xiJRT9d#Sa{F zmI}9CDVH*7eTuO0vv#%qw6LI9ia}PjxX2wfzmRNwDU}+4VY<5)e&kusrc$h+#c^XL zHe3HZ)iQHv+21PgB*JI5gfl9_ry3&m)I&mG<7!-^d7W0SS)A8YUA&@f_TRlAiQ+Fx zwT+EHs^%ie(%ln~Vx^M00k1}Pk_3O*&Id;+yU_e2Ks$=kkLRa z?VTT<9e#1SGvuy}WFaAvZv%42tji!(+uka`L;QsV9W2|8* zJ%5jOO$;vx?6QV@ zC4RdDSAZb>oYusa2vz)8sECpf$KCILtrP1#k=j&)njGnqNLOJfXnrdbGDu+fBa({Y zIkE7f<;pKdY!!cln(qEAAS5jMBp@4*40kZJ36Z33;48r@74h=UCXBX*%o z6b#tSNJB-v7rO<{e$HQ{@W#$xcb~pM?J1~_FrC4v*g+Sa7X4D zd&|9~L#rw9s4yjGU5llq$gF|V;f8_CBj z4%kTYs!eY5Z%p$-0_0~}=*5$VEZ1wObYmylX%Wy|d3?El{dTD=vyyKjk^pkSW3bBC z&@#C{WZJC_FV!?u(~xIc`HpP!t!{%@^V}LtOeJ||1LK7rcfQj!!1Df+i13kT+L2C5 z7a=~FZ(1q}O^Q@*rFby=O7r?Q7rOH@J7{`^(aYz_vHRq6M9A?a98w4&ex|&jUu(h4 z3iVr~``!b;>#lrsvRV*leN#(SSHiRS#ZQ;THX#GisY-1z3>><+cva7-M+mxODvx90 z(Er8QYkHYLVopIwm|X@@pX^F}t=3s@l~lwYKE(Ji{~jWvUN+SC_h`H^C~Ti1GdUJ% zj#j?vOU3>cmC(nN1P8Wm4yWOaWqYB%t-`vZ&W59;|1iE+Df=~uhx}t1|H;hauieBD z$Vt+_AK$B${TiJVEmIo&eG%le{h)Cm+PNR~+QNRV_z>}4>hkZuBe}5`^;*b&tt(s@ z1#gL8)ouGrfs^( zy-BqU@<&(wr|qMhBT#Z0C&2j!haek}Qzhd&lfp^uL>R0Su_qRd=hsPREOlrn58^!| zPnFhwR|hBJy&X@L!(?DP%2I=CheuuHVdmKnZ>`p_3WVvvQxsoRmloANldtnzG64{s zie2ws!@!U{H8<==5h+l64B$rOvsi=+k3;wE+4p^m<+_BaEyi7;eHK4F80W%D{!ki?v)57w~&K->sxD#z7T_iml+I3d3T_EGQ$e{4QGnDmc69)bWDo zp(cn<^G@`8j|A3cl=TYh?8mcdYuJ0SzIe7Z-n0U#wuXHEC+jPnvmKHZ3}IAW6r1c}3Ezo$Pw`+~h>Qr&rK-fS+R|-PkucT!q~;WAq~+ zKu2sR!Nb*pos3M>&+LzLv#>n7n$9(H|i7h!5b!pvr#x7~=|*LkiM|MqnvdUDN|j3sq)TMS>oZB!RmYDijiUcYgl zhrE|pPhAQq-g7;x6+Xa)3l+(gF79>t!z=|UpFg@PX<2wUm1&kmxw_R0;*;9_b=QmX z|H|*{0V=6Y?O|yrLHtk_e7t+wBAGz^kQRL0+zZ-_#rR(YJt0@Tp(K@1iX~<;o0#@+ z8EEg^46%9dL`1#0#S;3qYc~k%;0pg9M1Q#pvol$o=l=uo9?DbokpTBnOth5l{7VSU zHY;e~!g)t19Sh{5_<9iF!GG&VtlU^Uj|W;qZSMy>OL$oJ0-h;_GY2wsVe@@zvswJ{ zhYp-h!}R1Cqj8HQul~#{yD8MG4oEpH?u5p3U*o^`qlGp$^X(d{XVy$6z0bE#fn2~F z@H8Y?r8{W5Gl!OUWm^@Ge~UG z1AOiXKL0#tm$R{FaA@yw2!B3>x}J*%d%Rzu)q?j-C;Wt|`>`KlM079i6m(TOn>>Ca zk}8NAs2k$oF6lpk|Kvpq;5)@z%WceWz>5gHrQ-N9sqSH)S>9>3FWwUsi4T$QR;WGV;jX%-EB)Q;aHu?=#JfBL65H3ZbrgjD-<)t&jC75*@ zs{yhzfe!!b1Oknzl^guwK*&!HJv|4`>4(qzjJgNzDB8c+yPRxF**gI`rx0INud~Y~ z(kz6GKk|w@JgMO@2B)9@1iy-NyrP^cl~qD+=;;%uQG_1YTN)s5$7#-R14>8CF2uxXzZ=YJS z9z#q;!6s*DEWO|Mob*p5kn|1w9sFGFZ0FulkFsEYU;E{FaQynNjGonWYzQFM)x9`B zmG_|6_H@7|BI+&z@zlB9Jrt!oBE59(+J8*0=f=RuDtT{))hd3pRm-TSk^e9QJQrBm zB4Qm1_+#))jqoA;$52j*qF;bA?%!<78H;q?)0dW8oJ8AQ4h(u>Ct%Q4su9cGZa&Ha zr!l|ciu-l`$KNqM!pwTDksnuV^lHy37_EtE_L*yVA@COkh_KPD1;Cfk@57AjC&hI8 zZ-1RhsBdmLjIhb-S3Wo0pcIVvJl{)_gP@O1-^yD%HbZOhCJ=@nZ zFbE*~dkPvo#yxFKjvyK$0O=37_=N`bn%X2||2F@|XCh=m_OF}1uM1(;3ZeG>!c%;C z@CnlSOG{4oK7xPCBw;((Q9<|K$-HU!Nb8Nun;(Q>?$DONr_;SUoH$+6H*EKO{^@X| z9O}qK0S|oAUv>6p ze%?%KKQ}hu%LXvgH3;B6^XJ?IuR-(*F2+JO;9VnV74*8!Co~@6pHMnkNM3*YUTW)T?KX%*_~$oZ2W&&tdCLOOYZ%k8~T_GvTc7!g^e-2!bWU^mP++>< z{1n~!NX;3aaqq9;dLkuR%dzBEa=5`FeL;=$2CGr0o8ixb_bk>twRj*30&+eJ`WXx4 zy#1u{rNepF&PaMW#BFj^bFTvmytul9>S$irg^N;82bSM|;CCK_#L z1O`O!0U3`%D*Iq2!^r)s9lDCgqJ4&Us}fJC3jsLC*PlIt6OR@pJ%AH`q%E%>2VuVb zB&oHJ7O*j$*d0DgQzwv52}+PC^^y7FzQ}Kgzjqnm+-@7Xr)keNm39!7^JNDMYlH%D z2OoE9^W3_%vte8#SgDnp0z5#4V3J>#Yr?#bc}=HA|5eIq+yQTk|J@!klGnVW?Lh+m zhg#Rmm#yaAFOI#Fw_%!hTq?rb8{Z$8d}i$iE6Gxx3-0-;XeoPJa?!Pv?uhLSHZ9y zzhUvq<41DIZMyN45F7!h!80c4gO0?PmM$yrwx|fKM9A+^1VEo;*meV5^wX7*Y&UJl z2DT+FtvZkD{`X|E{R&!V=W{>XXf~6Beq+{oTr2by!Xk`u^B*$YC~K_>Hs~!i0~|Q; zC=t9QY*v{&H7kt&)yrnwI)is8aAfpjZ;K9KOxTJKe5jQM|FQFz-j=Q&SHn71elIe9 zv9eBoYO9q6yhGRxg{M|s%Qpn2ZEyBy7!RlX=2JHQ?2SeJ)S6ydifdfMBM+QW!5JdGXt0|?Z^cmHZ34jU5_PAol)vU&6kZ3Qjlx1}3?%oF1}BOIN?HN46D+>zt=* z&I|>7V`Z38#zX^~SCJf?=HGXaRJ)3N&I$sadQ+8Ze&I07XWF=tKqXd1Rb7?V$IVY@ z7kd^j83k=zY4gd3->y;{v1gE(j;hWy$Ssk`saOD- z##Mtun;T+KVkEvqevWEqGQiWNi@4i&uW>e@RRPIuQ`mW%QUO@s_9U~3=_CBIRLG6N z`ob^uM*Hr~8cnfyv8d@GfQ_HKZlZb8(S63Lsb!c}f5J$2s>234n1HIlr)9~Q;qc$3 zLP>!?8~vxXM-+bBorysX?n;A?HkMD||1%MgYu2>%jCBc?{2R0{|OklbLe<3hV6E!0Cfv*Bg6_G^ZZr@9+Y1AX>FUUjF6sv z@86mKcA^`LKi`C^T7E@loq?iZ2llAUQ34^geJMGq)w0D!;SPzchhFPiw_rQ8t1Mjw zZuUa&&LU+Tq?9NXv1u_iAK(>chm?H9?7|WMq6_Yvhc&?`~scEpiELV+liS2|#S` z{+s%u3+1=xxHagMtx`h}wHlw0s2Jp$sQ+KvXu>Hh*)Dlf-@Ez{dWbFJ>vc{npzN0T zTMb;|sS(+3Z_8gF^`XaCRx`P6+p@Mg_2GLgwtJjo0I4Yk{c@n_eQZ2{!4!jTIal;v zZKy(20D@hEn6SY{)@nEmN&oc#xx;MtVp)TvoE>N3#&@Ib| zx`X308B7~RxT2jALryh^mWCIRmKjleN@A}#F<1EMOnvP_YtmxaekHFX~fywk> z+s~{xfKUW7Qv_&Z2M#tz^btWYtzkChcz*;h1rbt`q2H=p>e03o|^egA0o># zje$sSkR+9QV2B73V);Sx1NNI2PbM$o+C%R}f?Z+beJ{inm!wS_p#U*|hI46}iI}2} zN|_%BC{Y#~58m01HWNq*<7HFFMT84QF}EtWCW-=>vj8MIs})yFX}Di3%K{XRqSSmZ5&-tg@k3DFH`C7R;n?~H)P%q+(NEXDGc!b3Z}I9 zmOe1iJ;i}oCVEJOUzDI3LNXnOL=o4)pOI1yr#~Krpl+nNQGU7sYy^ze-|6R}TK%{I zh-(c0gM^!YMbz2Qnd|iql$Zyf5{FocJW|1|6qNvs+`HWK-4%q{RK9O*}rBuAF?f0(68qnEQAmO1iiQu?8DvN-QC^Y9e&<>^`EMq zIn_JUwKX-n+k19z{4V^Wlz>S-nEwral>h7hr*#zmzuW`%*cUaGSTgC3(u+8Fkc{3y zme^QCQqzqmMF9`j&CMbPWr4*)xU+Ade!z}3%7zr|zn?|^?>#m{LPJAI==VHn=;7_Pe0xhTOwVsB0-73&ECK^c)^6SIRL9;7lmu_oTyOS{b!c&f z{C6;hE~}OO*vvDWn6(YcY@dg4n2V(wVxx6fVxbvf(oBm=*Ae;1l--Y zr)?kgKRUb4DG(#AS>KV4n$=liqoiAFO%_E(lHCKztHGLEJ~JbIIw)~vcm%8>a42JE z$8i#vt4?^T&++PEb7QKTsn3fuWKz!BIHcKMU#@@NB}UA69T?=8$%j_llh|)Iu}%Ig zP1wbrHA`bM62#sDs#7e2N+~6Xt}s4g(bRE8>K`@N*UT;v&Aq{7I4-Ex_B}Y*$4$9c z>y_QjdL0+sj;W5O|D7s!o8)c)Ona<-$L}rKYU_s$`G!*>*pF;p#bvAXRXn^lDimDL z-u&*@l4(`DJ5r&m12bLAX1mbjrkevMes|kN?TjUE9vy>LEB>kirU#P67H{{cv+1_a z=X!VTrz@X*rp+4>tgNPr*mkyC@SNgh2;*Q;L7e;H4?JCn~baz5z>4OxzZ$@ zli&W~8AQnDN*-OAtX;}mrntyUxSkuik2;my^KJBsV@yUYWJX)<{?}a_mAYH)hY}_% zn@_!jC0X~Rj0((~Z9%!fpB;?89m{q{EowX>4b6mma=guJZKof;bQ}i*J}tIWCVs1u z3Arco+SV(a*0vgidL>FzRZZeY<1&lZ!;mnb<%Xw1DgBI9oa$DW z8U5vvr72f;&w0eB%m;-^JJ?s3Mi>m2R(4f?dsSgHh`ztg1aF$h?nCstc*XI!f3`0W zcbg39Tz&XK(b#b(DkXdf@9S@petd1~^Xn4PC$R#=D>rcveVX5v{AgyAO|y^C39$!# zHQP$WPy6foszV55#f+>!OF!q-sMZ`7LqGd9DXAunIrh#-vBS$WNV!Qp8*W zN_^`penbPsFHu&ii-lzrl}L-XEN@w^OyU|$iU|)JCcGwpnwzD%xS+d!jI~{l=|9J{ z8p`y76Iqo~!}A_ZYogtb9{0Iy$8R>>=1Gimz#eIlGA7C+pL$g>Abos~cF=3&7m^H);_-8p*FQ_u!<?5D|Y_53q=Ci$YoN{)Ff3HK57PNIEhn-|GBefj`LxmPrL|@+_3vFxS`5Wx3{thneIaIsGMjn!5f1V*5Nu9QqwL(<5DljXYd^l=#)adN3 zH1jfMd&zOKqRM?H^R`VFwnvVNMS4+@_wmi6^bbh&Z4p}W5tnwX%d~Vu=HFX2+Eqhh z%62fl?w+0)C$ewZCXvr*S$?quWsYnrli9#*Z$6e4(|4PANS(LD(C z+a%(UPC;Jg?F`wdN=%A)B3I;5&w%TU-2-WLisTcSYBYC3Af572=_scnAABwq+X?+a za>^+nbDc3Oqlz~XP8&osA+T)e5wqXcqLmMxv6Lvz+1D zIRtZAvzeu2z=Q8cPgHRs$w*GntaOIKz~jZMQ6OBj$D8sIv+5-!FkI)Cdcs+fb&Ong z8<6?n3-`}^8f$j(m&4{taXdHIm$t`8o2wDLmcHdgeBVS|MW3(3bRxf!B%EzwtZ zQJ31DcvF_Zu630>NardE-x`-JM&1 z==4HPv-`lkr>i7IJ^`mWYjvl-&T2+0o~f}nbA3vK^9B~Cd5hG)Jp&{<0?F9%ST%|C z#zd1dCDj^X;>%~u8b7S=wlae7`vlG{(^z7S!FfzkNkVxH1QdO0gc_>?eYjKPLV`{q zmCJGyu{F#)!%EVGKydg7Nt{nb`O6va0Oqa;7pJvE%9f7^_~;f57IQh^sJi!)$t=H@V_ zHZM{@Pq*iCBR&i>=lWBFYr!hF+3ceP&W{y3#(>sgE2&+{-q)cTw) z0dWPYs|u$IYCNHwNMyk9@>Jzt{9?(x1^X&QDq`EW$ipFF4U+Be#6G0Ot)6zlKM-s_nm>YAULZ=2yfpe(ZFY zUj9qSc(Ye=88wDS!l3Kp;mexU2Q%2doran^`G6EryF4z7^bvjYR`UEckk|o z+h(EmqL`UT(7rOY&hyDe5T!W(>ei^@o)ZsD7^b*kcS~7yKs5UG8s9-5^5v~-rq#hG zQvfo6kNr%!rA~mH5fuK(#l^5$C50Xp<-6>TQwh6}eo?Uu)CL&@HzEfOLnZ*)ua~tR zuY36W8ZkfckO%(mVd}q}bX&fjU5bgVLdb~Ca+_;qVn@}qf~kr~6usAMN4on|JdoM$ z7@GQl?4`Nk@-)b+B7YZJHPsrCeQ7l`G)34zuBt#;Ego(42DtJby zy;U1DJULUDK(n+|f3P$6sqSBV)e2WNeLnaX_pf0WL9&VmHFOtmli#&+f5y`GmobDW zD{)kcHrW0HK1Tgv`BNwi|Du-_x6Yb2V1t|qU=wmPrH z@g1)3@O+2wI|8cn8iM?o$XgbyM}&SBy^Ma9ihwsCDPJo{8cms&-&3&4yQ1cr@`NTI zG|MPd@i^|Rfq8h#FXxFlP-J-?3f&?f3*8dlk?|;A=$8MUl)aY8uz<35 zPYtFdSIfB5=&2)%UEu1TwnorWqiMtk=c3;X*7OuON2V&d0R7%^@+wx^N4i96vyI%# z$7J&@Nc4mk5d1e#&rM2k&H=d!Qs-$wP)DX!t{8&gV$D>F&6Tjkxey=NMQ1eznUU3- zZS?+?dvP)wLtqmKf6y{oSNv>R2vpBSaBv(fdYkuZV+;ROzwa^bV(?tclaRsyGllI3 znNRpoMThI9q@{sj_)gG-d^cwP&De+N#na2Ntuatr|(j zzDeMSGk;I(BTR11^2L;*8vky5(y~!9B)h0m^V>&m2GafCs`-rdH*M(;jZ@29VsRG2 z#(LB4*Qu50MHkXU&U&EKEi4(=)Jnk-5(0lY&P) zTwiXRZp?pDw^fMo@;z!)suSw$`T9PFGy2tKfF)CklviqP=Yc)_;`P`47Q%N6d{awT zY1;ZJN{VHfg=^O((KTmL>nE4AGUQ;Q(wy{4Bd9CH;LG~A^no6*Pj&{PZd!edaeY(% z)pSVd=x9f~k(ls5F;IL@)lt47pD78R^5X&h^o7Xr1R|roz2#L3>+Gb)Str)*H_Xa< z=w~c>z`xA3e2kS1?JmBx$}oS)qjkORV_U;8{OxW1hU2X{vAxz^eFc`59|U%56FQw9 z)@Jv;&uvuZnysCtulHhokAYKu`twu5?J5FVI=hT_LWr;3(Z>|O!;g2cR+0Ctbw{r! zg^Gv)s&jPB@wJC12I3h@y3TZkJ70=xBJ{<#fqc8^z*Y<6q*6CwUEbOa&^f`Y@eA%P zSnXvx;PJ`}2AgkDFOvVeH~Z`U8#!K5gw(^cB3M=T?`keDXX_`umH1`zm+jWo-}6e+ zS;W4lVi`3}=|-(haU*iy)G@5jDPR@fc(dwR2O>hqZSLN!gbk$`=Je|h0%jLatE zNEEp4;Kj%?&1P7r9`;uN>zX5iNB(avdwh^z?Rsz!ujW4D6&u=e*cP5A5WJ(t7$C7x z>;Hit2FLAUL4{H{Qnfb>G|BIG>qdVdHTQ_1CPOsKhj4i) z)1h7C8xhW`&8Du&q`)*~w{5H;d46mA`kwL^nT20%TnkB1XIN$dj3wfFWZZCw2`y6X zt~ukL&yUwZ(>))Y>vLxW1nU!1wYC{W?JpDCI)d_kRMmMb>%Annek#dO&Bqn$kzCjz z=-)Rmc5^Zz$+;QuFRhIYH-|;DIRDH#@Mhb7fyjb?p^^Fo(WGh_E zHtqyfg9&Ja@^57ua`oA)b2{ z%{K{_qj66ilKbd^SG%{d!M&XY*M{S4Xnyx`Ky$R6JL7;C4cRPj z$F$#bRNyC5Rt02A7bEG^aL$%t8hq8-s1EFo7+91{Cq`D)l>VH zWdA%h{L%4%aT^L1qK-h+wyRRL20IW>rRrMy4su1X?_Q8*)^X{Z)cBzO-Ka5V8mnr> z5}@&q%y*9oRvLbTyUaKC6`JkJ@+n}ba~DHD^n;M-*#A0C&_oXrcvRoCS<(;zzV{>O zKji>z1d+o!uxU)1CN)pqnlZe5;>!qWCgqBgQ=SHa%zcf470n39OFtc(QLG>T(9jEN ze(7t*>P^q7*tp^AZ^CbEj_emY2hZoBl~q};D2clX+-mh+RlGuGeU{_$Z;Ow3%JWdS z*DadogE`|X`U3o)j^P3IrR%s;^uL0eT7Cd1thcu$gbM#Zw=1z<(^u_Z=+v;NdAXUL{SN0? zVc=#mK*JSYX*@_e+pO=Bz?ShH-K`RRT@PGcABKf69}G@0qb=S~I^GfRLu&0-U5sI8 zZUOD@TVeD2sVBz=r+TYgD;z6zn83~P(do%a`su-Gx?YWsq=Clz4vCube2!NA?l}Y4 z)qXUW_s?Y-)oyy7E&m>#-{fK{Yi7(b3-@=DsVr@D-=373@IZDJC-0wT7su>T|2-(q z6JZR3q!LjGlja0gC8 ktzfVQ?Q+P5Fvru!?``X-MYzkvV;TAJz@vA^FaQRv_@Gk zU=pKTa4vhyE5_m!+&Tz)gt+hL`cGPCr{)u>rY0~4)@CO#BXas?$&Ghao7s2uPF1+L zmmVLU>aN!K;6j|w1|v#WTT5F@S8;vQ(uy7%y{o-En2wxy+|?dgXAe*(X-kEF_Dmov z1;T1&zA%<0rNi&H&J)w30&!9Zfnbgai0;s%>;qfBL(y5qXn%xFzf{pgB>dz$Es3Yg zCUqaWx@_K774G6%rx5;Ec6F)yg`0SRdR$tK#NjX@0n*}h;?2*oY#+;Ms?|IOek1Cp zX5&-LvDIk9_^1wPpeBC2Lg3qtN*(Q1CBpdIcm1Mva&8K z&*cSXgsPHZKW9IzgW;D~!I~cPr~D@$#k;M^O)J^Z9H{3VBe34ko+9S{EwFxBA^bUS5VtR zH%u-e0>vz`3!=iw0q$hmXsO|MgzHL5h;4!h`qfEGbz9>^%STP$M4KQGGZ`oT(rE(seSk4DXGC{5>69zYIoJ%aJ@$&LYJfp)<={e;t zL?(P8JXRE`0>ELXlDP6V!fG?+sTEj?P_xHx=Hi=T_k9O{SwWhoPQkAqlf4zP%H!W9Sa^!yfi4qJgAr#%kj`#u6wmUX8Y zQToduvY(^l;V1!**IJ6#(lohTT(B#EfbEM=5}F^pEWq87f7vm&7noraJY~x%bX*I` zjO{_!ajft%ZxmB_d17?mXBP2n`MFYD-v|j%FbS=C)Lox=4jSEDMx(&!UhFv$T;-mQCp3t&xCHCN(c0(E(dT9z@*drL_*pij!2vN00A34+-Q>>~Z-~X@%*!5s40GqC2$B>e<=95ftv@NU3&gZ-_M-WX|E5-n2IBp zwR-#)6n+D+V|`&$<7MZ8zwMjvuWSD(DV*KWtTJC6*pg+$xAxVgpY^`eiSKk|tdH($ ze%(i3?MFM|ee|g7+W(Z~+Lr5HLt<9(ZY>YIpDnIDS(e-*m`?41AgAPZ-5vhm$XaL4 z-m_uKK7loKdGVDkbTcLO_@WFcg}lB0l7IUJ2`>srPA)a7S$P5Vd|&@3(|(L=y+M@o z(n*k2IMV_CSR+0jdVukphTj!GRC3kBEmVE|T!@Hh*G90M02ZCb;l$7L7(HT>NxCTo4 zvZ}Kt_mo=p!IE}ivDMo}&#hxJzu!;Ja8+jy%CU&+*@SQdnEq*_6gze z({pqX6h?Bjw4-?}Lz8tKx51WG_!BQdSNT{bIj6IPr5JuprHiSkyT|yeY(fR6 z=S3awe(&egH(e+h89rPFA{0W#31GgZ{9bzYg>cqvD0R3suzv>?Pdkb`{8K54j6;}< zn^o(75ctJV#wg!xc=P2>fzIdP$&fbalhNM#zUfuy!&TN8@>J(Jt99bV_@}LV&0Lkz zvVyq5^duS>(cog{a3!@~nob`t;bCt|b_Ch2I0%Rj!Y7KTc9>0Zb1~^)25{-m6;G$& zl65RNB<@6D%~b0|w!2;7&OL7TZ}S$Hr0Ies49kkjz$GONGwYG;u;BjQA?&FNZL{~1 zWZ{opC}O_VO-D^`babe@_hq2lU^zqlPq%uc;L9Lk&e{HZiIQzDoe~vk$82a##~|;C zFJ5Z9Y+iETbgj(M$kgftQYc{O>iC<)WbBWxmHGFuO>~*BDPSkFD;W+QmD+RSs zArR)`)dZEGf6q%Ey~q4S&?$pXkn&X{@?Y;@Hw;%jlJKY+DoW^_OcASv3SdtFp15#WWm zA<2V?^db?&HPsYtNX zEbt}SR`AFSLFvp6qyNe~CAGS^H<`tJP3rJ^3_t&-*8R{WSqnIhm}UKNfAP!CX}UoFi4F^#b~t-ZJ( zrCcZ#5tnO2Rh+e|=hBmQP?wsOFD{8xo5ij|htS(ktS=!-uNEcBMrz4ZF{VP!N41=) zz#mGuad=?}BS2g_v1Uw)Emnku2EsoQbB;P;ZCulm7I8+RA)oqbI?qgUoqUaPr16JOpSK=3p^lU^S~Hn>56zOX!)vf5)4Na4$LaFy z|M7%m8+*w;B}>3klZ;j^bz^%`TdGo1w_SMNj#4H`VMwXE6nqV)u;Tq1Qdi{3X%wTp z@M~mQtOEw5?1|+?YPyL1dE5_rLCFaO8S|Qq^**fLe`w_laK>X71f}nGL5BF_!TjHe zlL?7QZWQ&B_UH_m^!jW;h6D$^zu06T1Z4yV@`Axv9@0m=aO^Ti%(!~w*{*WQHlmQb zyf3WdJLh_BA)_sod2Ab4I2-dg0^O_wdG+lp?zN6ICPRz8|Ngq^gFX{u#5R{X97%b=-8vQ-V&MN>63s2MPxxIlGL}4ExU0)?ZQD`) z&55MDLs5@{gjidnZ*JDX7MO0TmTDY#38+DVcBuL#M%%d9{DbHU;%Zz>_xeve;G_?SI?(`;2a}osbsI!%y)xMeu-YvCTBvuM@!OLJl(41^R;4G}4e?k~uDq zM*EkR86Hvh#M*ZLHm?vo*jjA6`^ys`kE7&Z_2$KnpVQtVx$iT;Qt91hU6J338GNKI z(_Z&8tKih{PWw5KrBb2^Lgke>?!L(g6YZu*BPT2h-<;iKZH2GT`{P~mleC;9{pKi78Pm72))cOvKH7GUMmCkE3i z98`_|fpsMD5Ty0M7<0l_gSL?&-iGs)C+xJh(jnfC@Ri#S1hf#(*SfUU)rRfco{)Qa zH~lGvnRq=$@X!g(A9_FUq zbIi!iDV*c7OT;SyU#bw>L)_2U#YfpqsR1V1a zHxS(8R08P%2<8dj7B~(#T0nbEfFsWi_PZRJ_A73AEitz60`ot>8h@g#E^J@*guIbN zLdi->-t~hL5-yF^j0xLbdjBgwZH6Uy#$xGv3(=zFb;IrV)2oxp17uRGwa;_mhFuxr z!7t>75fnCEphqeTZ+kbEYlhQtoz#<-8G?uJ?#@8luI~Qa`{p1Ejo?I=8i_!->Q{>^!u{bkT|cN5&b6N z)&PXel(JQ{91{t>4c&cy|84^#E|vOFFX2(?w-2N`e>AB}!1{d~Yf0FEnc{PkzlCba zu+2l0bNn;OIw<9l-pu8eVeQP7<=VGbtm}?ub0a}c_hzU+A813xeN zoJZ~k0w@mpvNwK^f4U$raa!SYb1=FKbjVfr3Ls`2o>F@L`nL{**gT4R&r;g11oKBY zKjLwKcpexEc)251|^x%N$<5pVB1=MMXt%>_T2m2t2XP(PQT< zcC5_{D+F%^hq1o3*Qj@5Z3k#AAY~zH^&X<$+~^Qvx2Coe-K{fTinb&D4gTe=tp zBJzN#^R^pgM0_jZ7nJ{uCnk0lApc7>8Amuko@Zd=b;y=b;&f>|d#Saa*_Toet zQ**aTDrobV`z?|_A7VYn12gJ*a9x_VG`Zf@;|_Z^TfZ{ezcbn|8Uzf#ZozhqnnmzZ zSm0DLTzPI6ixjzIRm$?}J>(~X1ghl~nZ^*y&yJGxR59aVaD_&duP4&^3qz%M(S;S##TB zWg|hQyJ8u!$SutLjcqf@;tLbT)1c8`Xnl*;hQFx>w;E@iF&mqoS0DEm_y4@$PYS|I z?0Acw{b+Et5SEY+ezJ)v zf$#Xr4cHC2AiL3q-RWaJ&g$-$?TP_R_>V^-I&jPdo9;V-Z_bVG zrZ6-9mf952Hjw}9}9Zhf;<)ON!^ z0%juS&wjrqZmWY>z6a6xpzsx(TfjuL8EVMs+*S&#Q^aj#IVkAdPMFsZ93;Hac?kgc z=Jw68{3;zw198!n-2=9dr@H&ASr%W&tFWmZ^kc7O88226RWZhFlNzVKlc9~G_w3NU z0w}?oPdc}4UmRv>8-{ua+W7Dv*okN+PS9m8I_botI61JKyB*1 zJB-rPGIiP6a8RpCmX5G9&aGk0-fHgnkVzSYCTs289i{8W8|02Nr0p)BjRg6D$M3@c z6^a4NGY!c)KT}S*K)sUC)6ap|ekv1SWyz+V14QR6;aFr}1?KBu)$Frbn%S4djG)eZ zm8{54%Z5n10OUCf>9DCPB@1aFtWp@>C3(Ou^(4c!19@yEYQ^i@-57k@CJw{sJ&P%e zZvAPmPY}QceqL&@c~fld1m0J3%jdl5vIB@ge^vchr~CFdtib?o6qeW1KV1BcJL9BH z4*e~TWLKj5jSlq8`q%l6XdMXj%HJ}|h;6&O**4PMj0wYRM2y$99`Hf`t5H_xAT zx`h>!z>Pjk$$eo(^_$>~s(YIMHbE_Sl}-OKDK!zUIA@t$;2(xZYrpAGn4( z2D0@h^2?L1F02cILvrtFPari_kx(G^At=vL66)>CiX7Is|MsvxHjD^xuX|wBmbYs6 zvOG|wd-Tn`?fc*fAf9su`s!ZvZFhr_o4vQ(x5dB~62WH3y+6C^z|Y>~lLd^u?qfTg>lQZ7hspKt?(~a0A4MaMN^ttELt2>X znk5s3@kSQ_t`^_DQcwyH58cJTpfTIQJC2GAhrQtEosmZ5uzjv(?ODh7FEqIokuMb1 zcnM3>@}oBkaI5Ke>PT~wJY7ql=EXiU6L<)RUE|b@pwkgk*Lqrsfd=37ZG=T_IWpYU z3%b@EcacANrIgMrA^x##CC=UPA=k0LQXO7y#giBUrnv#4%da+T4|^+38gH!xwq@OZ zN0uJBiQhz;pk(_2qTzr1gMYywGT>p9bHfJQi4hLnmTOMs!-jwA78Q}EhLRA^{<)`6 z;q$&xLV_+ToP83%_dW1Gh&DdS!JMLqqUg+Z$U(;;3Yb4x_bwbDj#fdd6C-!47H{v8 zYM=ZH>~R0$TKra=*0t*77UA|o;4H@5{>v6 zKCi9|4Kc!vGf=z&sKI!0xHxtgl5F(Kaf-&|!D1DdMeOV#0b@?~f5NWl62%BXM?~YN zWVezgO$Y*Y6MSnoF)<2Qx&9P<=O29BAKf4h5?JLyW>tK8#7%gT0J+#j9sdxE`X`v_z%C2;7m|(?!R7SH^L&XG)-i zajHplWf2_r@$nb5oJljL;Ro!IqBW%t6ym}w5EO*n`AjqiPd86-{w&)LYqb~fy6YQk7z)8K5M5$#4q!&qnLT16JudG$q1I{>_qV$a%|2k z$5L@l@xjGa=Hw2JVhx8xrWOT}JzNnKI3UEM7t`SEThsB z@lF%WE^=6tvaq=xyfEXIhP2{T4cTcxg;yqpBuPeE9*CaEmku$`u$=xgZ-hVYXPeld zXNSeS{c*dK+9=q4)}v;eR)wNM)12B`f{>p4j|bzwiaKO8Y(>B12@|J(`-hQKhO;FG zobgUAKXjg=wme^)j2hiXb#`5d<&x~&lJAsD`ob#_6s%3tXuo>0oT;-OC zDVo8$Q^a!dZHMRnyVKvZ89jith`xeppi-5NFh+MI3 z`M5tum=SUx`T&9>cG9mc#${+JeuCPAO@7EDP$R?)Pou4sAiSV{IiIND%BCQjf|wNw zQyWsDiP&t( z^(jUr8dZ~Oe}sBv)33jgpDX|Ve>J(-V|}tMiumqV*?zR2HvG>{8Bw7Bu21nRU*e8o z$+o&0x4pmi-#@dNg>BdrH&<&8++wod;vSyRn4;4zyo$NC#eir{@8}jp#cmn;nWY8M zuq(aeRZp|hQ;?WjaEvSR!inrGgJ~Vz!iAVyQA`@C zDUUdJkQ3ss_y6|h2Q-iu!jZgVqAs{F7X`>oeQbYMCP(?I4CMVfhEVZ;?=SscITiGm z1tZ!%FzP~&evtd~!uP0^kXv5W{!%qBXEC>rrgdWWO;HyBSFdx2duh~#;Mh@+%@;OY z&~F4%Qv_&T>t`I!@B`UjbOsqzBOgN{R3qWadx?D#$*|+P0k)H>zq3s`%wm_(x$e*w z{h@ar=jjnAI#l+E9~xD5ClZ43N;XQ)5cJiXG%i--p?9qq_H~;rf;22AdZDtc6X=Na z`tj09dj^PrFe~{P4J?)?Um65^`L6ve*7jfBZAXL)9=KT(F4sGEGH!l?nS`{OT3LV> zl%w1>_-k_`+-xP`4}?(-4-x)1lDTDx74aXCIV(u9twM3pl$Ph|N3p-cK{&g1SBip6 z#84NpT-VR9bhp-U?wWk$Ip(k_o=~0(Mx1*%<=#UeMaJv~EJLVI#IGK~npfh1N4vg_ zP3KBEBg(^~II6nj$z`K&)r1cF|gx3*ho94IWFy?d|Mg5mR67=K8MOCDl< zF6fusN8am-aGN#@$bO+1PQS3EM7oo&@K&OW*0af4fg`rGR|?2^luJLo)h1IC@|xv0Pr6y_A8NGD9fC?`c9DHO(Xd*ZRbN-w%M!X;AR zPSRD6IqanW#O1Qn#H(XAvRj(68idx48R7PceCrD!$2m^4N;KrhJ;eXx|IuyP|C2r8 zU|@$xqHkVnKcVv>6ecmIJ|ST80YN%^jMMSVX5rsCW_K>FF0BZpH@o8iWL}JA_Euro z*h!7Y(8s{9T0Q70cc1C<&-`(QKB7}G{L|V*h>I1e2@|2JlA!Yu@L;g`;euT)h_cjY ze(^Y?s-)@W=GMOQ+;JI_+-PvUw4#3fEKp#`LULuJPvcj3vgZ=VY@x(|^wy z3JmdD`6n!}BIUaKgXLu*^4jg!jf}UB1Q$)I`FB^#FbW{0C_G!E8z6c^H_XSLf&MHk zpEGCC#34yDZ|8n{2NhM>)J!+L;i8EUCA)fQuS&`86@JH!e-n(hgl)@dsw(tSopcY< ziK){v2r2Bj^OW@Lj2x6zy5&yWR@$gDh_qne0_N*p`%oA)gHg&i;Tw1!HOAI3^@>|m zDWh_U+*CcsJv~jXquY1-URW+v$-)&(5M}QhlB~eejAK*nN!%*!fp+L|^aH9a zoc*Oq%oNgqg3LvmX98$saC#N9gN@VEyE{+^@{*)?+lRq?$dj+FcNO=F%qr83`ZIS~ zkuS8}-k2h*mM!UYuR4vcy?`X>x69)bBR>dGF@n|!=Xg!Fw64_puwp@nO6=lF_U9fTKYbus_m<# z1SMU25#7Ayc>=o2B2SVt`67|szJ4H^!ZBV7z>N02ZF?GdcNvSCq-56himiB-_xEA3 zL157DILHwCv!tii0QuD<{S3jb$FD`<4qAuy%4*l+V2}S&`_@wN)*=wH2CR969N%U8 zJM8<3!BeeHEN$tr55f0 zKQ^?J%4hy%oS?u96P* z6Ihuu5&~E17%LO%?5>hZ^%Gfnve}BNug~PK5E%G_nQKzqaiwqE^+T4)BY#F$#{7LN z&w8@$X~)()%4un9mA$$LToWk;$sICwe1O9`kKi4$;(r4Fn-Kk;sR%yI4%B-UK3b8GXXauiOs&7AlS!&0DAy>{f#{UnXjVdc+SAq6D@x|t5KaI z>f>;>miTEdX}>*RLoyGuH^y;XEa8N#_sjDCki6GWs^|rA zvlQlNXV>iIf=@u?|LCWs-tWp6A4H2i9_2j8q?8ZKbhq(*8ih{So?xaK9$=2)CYw!qAh-`v7H;xRGLhNYLmQtAc! z4;=u;Gn9wX?YtMC&AS`Ai#S68^1`0z;WBpQ!T*xJ8u0LX@#qmjP z3hCs$E)V0-f9Zx;RDbAeg8{~$XCJEV`xsNn2$0#+*sTXSnOJ14iHYb|NYM`x{?it! zzkj^B++;m7J$!-sLD|+FXN|}A@MGgnhc|N_y5!OrHQp8Alh8=&xp2@R`I5#M;(qRE6-QcnSAzWZYQp zm1;dIe1o3+Z=PtS_u^Nw6!)Cz=G5@{HZI&>B2{udZJnus-Nvz6y;RO^ftPzTCM+KR zoU`rh1jVijOc)Nh>d1W_djr;dPHQb?qsnnaNlVVK8e<P=wFhi*alhP3@u1vkZP8lgo6B0b$kye@n;SK%0;+|ZO$@B2JvGoY4pU2^221FJ zKfKEtx;QjYZamOXQuUL-qGA{gM5rYuF9oNx8g2deJe$Pd5AdiM--GyAaX$2Ve>ezv4Gs*P=$Ar9 zS@V4jpgkog8MK>1$bMN4)b@P8P0`g7;-L(D=~({#@qW#+3XV?hQ)z|tdIa8=W@k;- z8Of(l)++T3;a`H8nYGdkj3(ccbvXyp;pW3}p{3tVk~9cT;R%1hik%7fz? z{Ks#tWywd0F58-N+FhBfMJ(xeh2I}4#X5WBN~{{v@MWaIYtV;SHQ6(yl?1EWYpqKD zv`ll~1fX}WO3HO4)siB#ZcMC-!av&|I}`I~O6`6jw#1$Fs0d-L_1?J4=w zK)M5^5tRGprdnXtxzW-$ny=jzeXwZP$ALPPD{d^#t`f_~__WYtRpg(?9gf(f$CatM ziQkGJ0<5LV_w)($uWPxp+w)-hlFmtK_B%pbI+>iis72Y|*jsFd;+JS8W3@K$ZT3(9 zb8y?jaqDUzbtM6MEu=$xe&v1zzm>Q>eIU`j9ZmeYOWMP6DPwAf`WKV4z)z>F0*zf$ zO{#1ERsC(}&OQAfEJ<;L%Tg~sd-i(g3fh=*)nuCOx?yHS@=!)I%_{@NT`YCpe0&b~(=F{c_bw5^pU(_uls(rrc&Frrn*RY?snDvg)p-dpS1%V(pq6&6y=m(H>kE8*tOhh#SmV z1qhfSM}23BE3`gi;d3asDyl4Bsuf9*1&$!tYBQ=0I5Pt-bLSdfmcgT6t+R~^WP}nj z9Ca8{cZ=xDxCl8(^s}XpA|Fw3NkUUB z`acA_ul|EWf1IVF8fH$Qu17E4Uh0eSz!v{Pn;p}?{x`V42A<8Eq2obOl1_tO_>N)O zT^Z&{-&i*h9azG&O(kh-$+u{lg_l?-(QCxpd6Vck8ICiaRM3ZOrPG3j@(vo3uBH|` zPSaemUKKR0&k9*?SW(VD*4XxM+#zjFM~*c_ENhRoT0A4wTR2lF6_A72l^*x09~(+a zwwXw)E_45yjqEisd3T8qrvhgHK`rXVM)u+v9f1GlZlo!n`LS;`P-BU^=GMl+E9UbZ zfv{ABC)4~>Y0R8~#J4r$6G-ot;xMAbF7|W-(gc;2a*5qS`of+Z%PRhe512;HQkZc` zKg1;UQc-8rfW=?W3v-9}Umdf}_ls6XDhKyvW;oEf>Gi>CXNvMLwvbe`ffbnkIm6?4NVKt6;omPMC%dM1O0l{?%KH zbnu=Te{I)VN4+}x^v7v#KG9!wCLm#ZAN4v;0om({Q7V9@hw}j8y#3 z&d%4SBtn~rJn+vopuPTZJx8kju0Hr6Fd#~k~CdEH1()~u($!-P20uRUG&eq;6OR7}9!jPk)!`}MOJqZ^- zpYoJDP*RE-5&gLpNK4bGYUE=a8Ok4~OXyQf?oVYEbOx>bpeDndJ-5#dVVMnkffWy^ zx=6YA1dmVm+~AY|_*w?QYnCS@ePOb%gAw}JJB~n@WnOyulKG0oeql^BR19_HBME$t z>-}TcYX39nLw#FcRfY-ZXnrY1$aT8MvU5{XNepAYNm^d@GqY;q`xm9}(E3|hC8U4Z zbOno#uk3E%sa1AlN*kulRU8>|9~YK1SSr#p)~H(^tu!YeF~HQCUaGkn(cnebc#`-| zU)NymD%ev7 zgT0(qqD5zlj(fGSe9~~rk$Trhi5(|KVgxAei1o@PuYztdu{Nt$F8l@ zab2y+{A%^^*%@O;vE0e&*@xQV+|$+Y?KBTeZBS`eRmVRg2ERO>;+`zxa1JA)t3BtK zT!R!_-6`a{Xd=B^ahdh+sg+4M=^fHz`@b#ML?xo}6{0{;>j`y95ijd6xc?37z$-DF zX>OY|ee6(l>Mkw(NW7JV5sbLXh(Z6wUB<23Ng*zReQ4+TgJM}Q`CZF#0>@WYC=xW- zxCp?Pq~hmmH94O5xBFYRz%Lvy-tXeC+b=X`(R48nn)%8J3Kdi!XxPp%XVVSI zyS4;c7`@;FP6%+^&VIsp3#6p8|8QQkk0p3jKXF&|4?Kk<)M3EH=mnojPJW(3}f{w!uyZ15(!9{66j9#AB08U7iJOD*AVA2#Wms z%KCA>IadAUtJfe(#pMmWK&~XR(Ih9TK$yRO=bD?2GlcS|QgU3!C;ihklte-Vf1wQFW zv0!3>u$Ys*hGD%P(dbqcKdGHyZ0gKTmVn5!XzQ{AA9+yBFt9K*GI#`DFHW|amXQ$4 z(pGGm1|Kx6T5KQkk!*S#i47NFaUCtj);iD@n7rW>XYD;%YblU8JQp`bC#Ty; z>_yvt@V~50D(Q6d1?v_97-XRj`O%}0X;0dMRoig0-sf!?uQ^~Yh3@)wQc70BHE`oY zkmSxj_EGw{%RZ{>|B^N`&2d8InN!6drN}O38S(}(>84TExsljJTx0kI~lu{@ggP$?hl#e#YMW|A@F>iJ!DNV?|c zfv{u}aiU@uyJ>goFHx>WOv7;kQlOHUt>!Y%kMS?C&F0iUpxSOIELGYF7ygMePr`?h!Htgl!k$1<{gTH92jDgtML*>cBa0?T9 zZ5&y?9|~;rqYbN*&4maq?K4%pgAyI<>hYQ3-BoidiBfS2+ZGc@%~?L>8=cmdCA|2f69%c zb2ic7xWR}Sqggv1X>#cm@K|z%JQQBVJ*ejWT8b89N+WzoHnH~ft6v8n%HWErp>9=ck)n)hW2mZU(V}W;=ClgARs@W5$T1cmOv%7= zA9Dv#R~_tOl6vd@trvNGC9ZG;(r`uYtGl+Jwz{~Gu~Be{a0J{3*Q0>a2Wr(19onJ{ zk@Lv$gH0KNXe>li#t+x)CX4UJS7J1}=n8Ps*7VA9Vt@8Y>lYwlHK-wO5hw0Dctt2jP&w-vaSb$>gC;Bf70k4YxPH9 z6$-g}N_DHDAouz&wt+k0Fh5&Qog4Fm2d|g@5sh{7%i%6R7GZNB_zw^;hii83pG)hi z`zy=mPX(kJQap9lLQ${u`++77Rv7BXQvu3YYzpn|rVFO&WIY=FIE!{gtbUYpKa)5Z z6ZAMOd8?+o4pv{+*_LgvY!x>WZ0H6_#>6C3jb))REA!J z!MVThmN!6^b>$8peI|RMQGT_kM)e`A5C?HQM_Z=}a)76&h9y6JDHseHhU|+ptmo&| zu3_ips!}tg;jNCZw|KTA#fI;S6?qfAh7K+f4*hAPY0YaJ=Bqk$M}gXB7k8zjf2Ghv z83nk?aAhSQ9MfirAT(uBR_{IKd?$?*4-wnU>?ss78f6POKb8apb<_Ob&|64mdvYlU z;vXqVWYzAj_#eGf_ixe{Q*pq z`t9%%)o$xn`^XLjvT6tm4Qc4J>QIfoZ9}$0^$mriX@BKkq9o^&B`pRcUR$Q@@^uI8 zr&8de^*moHZ;YRhWxR>k;J(-C2!-T{g#&%1@p`KWqjs&24wj3lhFewinA#!If02QL6M8+4!xDrPPkgpYMm^*xl5Ifq&E}o9oB;Kt_eUcA zx}Q##hOcT$6-~UhCl`J_`p7c6aXv7L2;r>%xIOMq^MEQ!F`&ig%imFbjy`<1O(T=r z;(zYe1$5}d)EVtb=b^Z3Q|P*r9c%?g;Uh>LMy2BrhJVHbCH<3E!2 z7qh1-(DTxYB?mhT%VlM3HI*pWfa(W#EvqOSC3oUVb2Y%6icW>}lpoI@B8VAa&36f2 zNuFgdd9p;6oYbm=`zos+cJWxEwaL|uD{?kF(zxc{H~6YWh`uzcNaZ7_*BhYNk|Z~uEvq@3ucxj=`+X)*VLdYwnYATtA!Dyt(3~C zjY`77XPzN?Hs0;fcE9V76W!)w1Uoi$XuIC@m&Et^Cv`0j9`}04H8)5xXI}FfmZ2Z5 z#TS;whRxqR@B;zL2e{}RWB|pin9;uv-xypQ%y#LO+VUZxIKEb=l^TCW&;kMKA`zST zSnY19+Jj@ag=SwoPFD=V7>sxrH41oQ!lEyG&6&R_rh20sF~=)C_4R*vECC^gxqgkg zdPbIrOHL(MR5JgALqDx8dz9z}}Je4hwq~=o7@~w^;pYXez^tyH`VX@HG0W@3C1;Hi5j7c-8F7@|+q zm9Eb*p`4Mhhi*i|lS0?j_x#y96no!cS*QCcMM_GDtg5&Z- zaH3dMJC(y7Fg$mHtC51`!7RMRg1;A{%6H2=YpHMMS@%RncY1AEW+-ZC;xq{b4{k?* zajm$~F5uBB%SbBQn@kVy{lbf*6_&0W*{O*p>!BJaDQ#mKb;a=G0+<%3sb4Lqkm=R8 z&+Qgtu&dD{#juM@5d20p2?uTiO1L_x)Pl|jY1EDXnidN2UxQkM<5^m6+|IU_TwF}u z(JH&%Jdw!Vs_NX^l{PDJY*b6Q^4;8PJ%9RzNMA!Y(U5vAGuu0BWaASrJMn=A9c$c$ z%w4=fI*lDT#~Xd6ET@=gwNE4%LT5V*G2wFGD60eR#wmtWcd*+k8@;ozRruAVROS*o z!#nS5>C}yVRsk=i5`%{7%GW}WBGnlWA5h6Ze^hNTO?ApwFMB@9@V|c$46_!(y;R%k ztkhE&Tz?=X-R*w>EKo%BwVJEkj@;aSk73+C#=|UY^J3NdeSAe@l4xK7a!q)Sj7~ty zT=F9KN0_KD%8%`Sb~)N#^!rm(g8ekFOIV2JfPvIYqJT6zNp}2~>#=id z@fY`(-D~H<*BAV`!Q49*{%0u+`Bmht(rrR;!))iqON9xS-&@f^cnKoi_ zbs)0^g+dvm?->^mWFY2g3RFFLJ*N$q4@~X$R0Ca_v@zel`iL2kFI#JR$aW+>ymt=x zC7ADm9{?F6lD6(Q{wXxo&ECc2@O$k;u$_jnitF7BX;OUSaQ5L*#J)~fyWfVm(ZG9e z3zjzS!H|XhZq&slk&e@|F_B01Otsgo+iMv(m$9Dw{kt|S^}zFkjHlV!@)J=tv zFAm9ELz~vT3~|5;glvI|P{=H$XYB68qOMTB?k)<@fw6nZ4MWxK#faFb z(0YV-`u(oCf{?DbMK5F2S>l?G2eFbYYvkvW;BEO=zT}o`V>&~*`UV)EK;UpP(2z^B z9Gnl;#7aCeBDhgbDe+2wiuT4UDFO2vt^A6X%!k^Jk?s8;EM#$jvW|jmOd5ioZ_hQv zOAQW!H(P+a{i~0mrzJMcN#Sp6?%?c$lyS*o5lZdVRUv=Af|6QYF^(iawDJ%|_uY5m z!f#9Vn-1gxb31m$-L^!MDb+hHT$)l@$)Y43V^?q-KU3+e7BB4RTc`B!J=z+*hw4L; zl6uQtr>xtU8UAg^PSbeTCIgkt*xV7~(H@(U-lOGWJ2OiUPx+0}XGX00pnhiQmfw^x zB5;&{I}l~FUTioHmXRYD8Kw3FuyC9yE(jc?lu5d+xL9=P0ez;wKj=M7Y zGN*ohLsfoc2x{!jWE)&UsTSf>#Z62&OK1ADiA zfLy^f&DpF|x`G%zu(RO*ij@B9_kW2WvA zVj3~Bz_I0ANi|FNH-hMO_zg^M(3#r+V`?$uvm@0Jr&S*zVsS~k!(r8l?o;iy0U6~I zt{#)zmf@QY&d8zkuW(yo z@Y>|-rD0XEpBSX`<=oYd-o2G9t74%c`S+^roUtodv_gO}R8*y4y1IB@W`IE5Z6Z(+ zKV|J2R-5|={N|cwDv3+j@A%6{bn)BS2_pR}TS`O(MAJ2b4i?lZOZQ%N3N2JY?(sB< zPFE`ZO|{?c#*0+l6p|dKzAbN6{)65hyVjVzZZ%GQJCzffF1R!jobnU9IT`#A$WmLsr^G6oB&FDc;*z3?4Bzaj8jsUEh3W2bd7tqQsJxsT%z$czF}#2^b8 z6{EcYvrjkcti8=jI3GV%(G3yGlQ~Xu$~4kIP$a+fWDiJHlW-J{&2?lK)Xd34P9Pua&p2NH&>zS% z33tXHj6~FkrJLb7FjE~TCyOg;yDNq$6-pSmC$%PUwnm@Sl$Cu|vK{~(RMe#J|DrO- z60WQzE#e~Ifi%IZX(oo4HJ14~C%S13%rFYnW8gSmM6+952HIv(+U4h!yx+rRBXcez z+NhIXOu4MRWLlpx^S~ODM>7v}#Y0T4Ogd$OBx?jBf;YoIetLYTIB|=$f%aj^UV*)b zqTZ3$bI_Fu0g~EBe96N$Q`4E5*MFuQNA2aninf{nbuCWk8s9rdO{g!6xjl;bimdt- zApJqLe%;fQ%7Xv6>FWdTndKuW?OmnH^RsU(icwJ8%MFuZB`NpU=|K01qlMJX*u7|HRnaBQR z-#5WK!s99mGgLXpRTM?(*C-xYo|%OwrFVNDL@Zn>k3L*`Yq8N~M=Hp(it|RU2Q(`q z(l*6+zcce=bE%PYo$c}2o~tSC?7Hwwy)ruI=}zNJ$8E^j`#A3O{>KT^ZmfjY!_GAX z)yJ4K|Aq#JvwH{R5&3@b@$N>`!{OCL!~jpiwH00TBvovH>{VHr4S#*U*^Vxnwqh@v zUu0XzU(~Z`Zv1!GF-aWl{hC=uFDZl*gHVkvf_L_VB3BTW?b=Xbb-7`^IDmQRl`OD;NC9ZAxHs_Dy3zAa?Ni(>EX6K-U{7%_xg9Bo;#`IQ`iBY!t}yjq=;i$MmS zq$esJqdS+D+#{PWAKUU_92rHna@k@L{oCmi0q~1{ z5T%0*f7?>_3oZj_j%ZoWek$jz6{mqPFo^XT3aMzWfiC50F$fm(QzV4}ktz~_jJd=G zq=zno4^46@l}q91&Q986(n{@QhBV`ZUBkdRg@5^X2|OdWhybdMKM7Sd~HOXWA2O;IsDgntn+L+PgryE&jos}cSj_CzcHl2i8n$ktmd?0(5U)NSJjgvqs@ zoZIFsUTT4l2)I3hcDjqa6p*bG14)+7NPf}q%(catc-8OiTjrqs-T~D{N_F@+tI%ul zAg@1Q)>cl6-0x?R0~Hj*`*CzjGG1iUPDG{@#3x-hKcTwZAUm18#v_;!){ z!5*fK!#G&(rBAw!B!|u9#iLyqrIX@=$1>n*%dNn+0lUe_LBHwKz#d~krbAcamME?JK7)V)wfhE zt`9cxOj)O-L||kWf4IMxm>2|Gl*1?)H3I}=Sa|fr3m6;~-1tq?e(25N2=!rrmV)d^ zIG37x9ZtVo@%*foE|E8AQr*5>^|&?@iO`iU)*HFpyZ~Ls2fDL6QHRKXF7}nGf zI%adWD2ZpLjM<1PJIz3tdsb_yKCjOzz2 z%z4N~Ahojm&hgK5d`hZz8}n!>oJ zr6aK_$ava2vKtQSJ=P?%3vM`kII$j^=X)P0OmvNgA!+8==P$L@}H z@^mw=*3Tr5otOJF%_rCBi+DB?GvML%YczD=Tvsrn|8

    • BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 15 05:03:32 2023
+
+
+Command: bitgen -w -g ES:No -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
+
+Loading design for application Bitgen from file RAM2GS_LCMXO640C_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 3
+Loading device for application Bitgen from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from RAM2GS_LCMXO640C_impl1.prf.
+
+
+Preference Summary:
+
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                             ES  |                           No**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+Saving bit stream in "RAM2GS_LCMXO640C_impl1.bit".
+Total CPU Time: 0 secs 
+Total REAL Time: 0 secs 
+Peak Memory Usage: 46 MB
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+